From 9cbed28e7ea50cf614b9e4b2d23c574bcc442aa9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 18 Mar 2021 12:51:21 +0000 Subject: [PATCH] update ls180.il --- experiments9/non_generated/full_core_ls180.il | 335013 ++++++++------- .../coriolis2/ls180/litex_pinpads.json | 1330 +- .../symbolic/coriolis2/ls180/ls180_pins.py | 4 +- experiments9/symbolic/coriolis2/ls180/sdr.txt | 2 +- experiments9/symbolic/coriolis2/pinparse.py | 2 +- 5 files changed, 177405 insertions(+), 158946 deletions(-) diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index 3d746a3..2bb27e0 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -1,67 +1,67 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 14623 -attribute \src "libresoc.v:5.1-330.10" +autoidx 14913 +attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" attribute \generator "nMigen" module \ALU_dec19 - attribute \src "libresoc.v:279.3-288.6" + attribute \src "libresoc.v:284.3-293.6" wire width 3 $0\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:289.3-298.6" + attribute \src "libresoc.v:294.3-303.6" wire width 3 $0\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:319.3-328.6" + attribute \src "libresoc.v:324.3-333.6" wire width 2 $0\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:219.3-228.6" + attribute \src "libresoc.v:224.3-233.6" wire $0\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:189.3-198.6" - wire width 12 $0\ALU_dec19_function_unit[11:0] - attribute \src "libresoc.v:259.3-268.6" + attribute \src "libresoc.v:194.3-203.6" + wire width 14 $0\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:264.3-273.6" wire width 3 $0\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:269.3-278.6" + attribute \src "libresoc.v:274.3-283.6" wire width 4 $0\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:249.3-258.6" + attribute \src "libresoc.v:254.3-263.6" wire width 7 $0\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:199.3-208.6" + attribute \src "libresoc.v:204.3-213.6" wire $0\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:209.3-218.6" + attribute \src "libresoc.v:214.3-223.6" wire $0\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:229.3-238.6" + attribute \src "libresoc.v:234.3-243.6" wire $0\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:299.3-308.6" + attribute \src "libresoc.v:304.3-313.6" wire width 4 $0\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:309.3-318.6" + attribute \src "libresoc.v:314.3-323.6" wire width 2 $0\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:239.3-248.6" + attribute \src "libresoc.v:244.3-253.6" wire $0\ALU_dec19_sgn[0:0] attribute \src "libresoc.v:6.7-6.20" wire $0\initial[0:0] - attribute \src "libresoc.v:279.3-288.6" + attribute \src "libresoc.v:284.3-293.6" wire width 3 $1\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:289.3-298.6" + attribute \src "libresoc.v:294.3-303.6" wire width 3 $1\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:319.3-328.6" + attribute \src "libresoc.v:324.3-333.6" wire width 2 $1\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:219.3-228.6" + attribute \src "libresoc.v:224.3-233.6" wire $1\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:189.3-198.6" - wire width 12 $1\ALU_dec19_function_unit[11:0] - attribute \src "libresoc.v:259.3-268.6" + attribute \src "libresoc.v:194.3-203.6" + wire width 14 $1\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:264.3-273.6" wire width 3 $1\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:269.3-278.6" + attribute \src "libresoc.v:274.3-283.6" wire width 4 $1\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:249.3-258.6" + attribute \src "libresoc.v:254.3-263.6" wire width 7 $1\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:199.3-208.6" + attribute \src "libresoc.v:204.3-213.6" wire $1\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:209.3-218.6" + attribute \src "libresoc.v:214.3-223.6" wire $1\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:229.3-238.6" + attribute \src "libresoc.v:234.3-243.6" wire $1\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:299.3-308.6" + attribute \src "libresoc.v:304.3-313.6" wire width 4 $1\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:309.3-318.6" + attribute \src "libresoc.v:314.3-323.6" wire width 2 $1\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:239.3-248.6" + attribute \src "libresoc.v:244.3-253.6" wire $1\ALU_dec19_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -71,7 +71,8 @@ module \ALU_dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -79,38 +80,41 @@ module \ALU_dec19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec19_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -127,7 +131,7 @@ module \ALU_dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203,13 +207,14 @@ module \ALU_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -217,57 +222,57 @@ module \ALU_dec19 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec19_sgn attribute \src "libresoc.v:6.7-6.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:189.3-198.6" - process $proc$libresoc.v:189$1 + attribute \src "libresoc.v:194.3-203.6" + process $proc$libresoc.v:194$1 assign { } { } assign { } { } - assign $0\ALU_dec19_function_unit[11:0] $1\ALU_dec19_function_unit[11:0] - attribute \src "libresoc.v:190.5-190.29" + assign $0\ALU_dec19_function_unit[13:0] $1\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:195.5-195.29" switch \initial - attribute \src "libresoc.v:190.9-190.17" + attribute \src "libresoc.v:195.9-195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\ALU_dec19_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec19_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec19_function_unit[11:0] 12'000000000000 + assign $1\ALU_dec19_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[11:0] + update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[13:0] end - attribute \src "libresoc.v:199.3-208.6" - process $proc$libresoc.v:199$2 + attribute \src "libresoc.v:204.3-213.6" + process $proc$libresoc.v:204$2 assign { } { } assign { } { } assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:200.5-200.29" + attribute \src "libresoc.v:205.5-205.29" switch \initial - attribute \src "libresoc.v:200.9-200.17" + attribute \src "libresoc.v:205.9-205.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -279,18 +284,18 @@ module \ALU_dec19 sync always update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] end - attribute \src "libresoc.v:209.3-218.6" - process $proc$libresoc.v:209$3 + attribute \src "libresoc.v:214.3-223.6" + process $proc$libresoc.v:214$3 assign { } { } assign { } { } assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:210.5-210.29" + attribute \src "libresoc.v:215.5-215.29" switch \initial - attribute \src "libresoc.v:210.9-210.17" + attribute \src "libresoc.v:215.9-215.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -302,18 +307,18 @@ module \ALU_dec19 sync always update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] end - attribute \src "libresoc.v:219.3-228.6" - process $proc$libresoc.v:219$4 + attribute \src "libresoc.v:224.3-233.6" + process $proc$libresoc.v:224$4 assign { } { } assign { } { } assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:220.5-220.29" + attribute \src "libresoc.v:225.5-225.29" switch \initial - attribute \src "libresoc.v:220.9-220.17" + attribute \src "libresoc.v:225.9-225.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -325,18 +330,18 @@ module \ALU_dec19 sync always update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] end - attribute \src "libresoc.v:229.3-238.6" - process $proc$libresoc.v:229$5 + attribute \src "libresoc.v:234.3-243.6" + process $proc$libresoc.v:234$5 assign { } { } assign { } { } assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:230.5-230.29" + attribute \src "libresoc.v:235.5-235.29" switch \initial - attribute \src "libresoc.v:230.9-230.17" + attribute \src "libresoc.v:235.9-235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -348,18 +353,18 @@ module \ALU_dec19 sync always update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] end - attribute \src "libresoc.v:239.3-248.6" - process $proc$libresoc.v:239$6 + attribute \src "libresoc.v:244.3-253.6" + process $proc$libresoc.v:244$6 assign { } { } assign { } { } assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] - attribute \src "libresoc.v:240.5-240.29" + attribute \src "libresoc.v:245.5-245.29" switch \initial - attribute \src "libresoc.v:240.9-240.17" + attribute \src "libresoc.v:245.9-245.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -371,18 +376,18 @@ module \ALU_dec19 sync always update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] end - attribute \src "libresoc.v:249.3-258.6" - process $proc$libresoc.v:249$7 + attribute \src "libresoc.v:254.3-263.6" + process $proc$libresoc.v:254$7 assign { } { } assign { } { } assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:250.5-250.29" + attribute \src "libresoc.v:255.5-255.29" switch \initial - attribute \src "libresoc.v:250.9-250.17" + attribute \src "libresoc.v:255.9-255.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -394,18 +399,18 @@ module \ALU_dec19 sync always update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] end - attribute \src "libresoc.v:259.3-268.6" - process $proc$libresoc.v:259$8 + attribute \src "libresoc.v:264.3-273.6" + process $proc$libresoc.v:264$8 assign { } { } assign { } { } assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:260.5-260.29" + attribute \src "libresoc.v:265.5-265.29" switch \initial - attribute \src "libresoc.v:260.9-260.17" + attribute \src "libresoc.v:265.9-265.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -417,18 +422,18 @@ module \ALU_dec19 sync always update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] end - attribute \src "libresoc.v:269.3-278.6" - process $proc$libresoc.v:269$9 + attribute \src "libresoc.v:274.3-283.6" + process $proc$libresoc.v:274$9 assign { } { } assign { } { } assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:270.5-270.29" + attribute \src "libresoc.v:275.5-275.29" switch \initial - attribute \src "libresoc.v:270.9-270.17" + attribute \src "libresoc.v:275.9-275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -440,18 +445,18 @@ module \ALU_dec19 sync always update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] end - attribute \src "libresoc.v:279.3-288.6" - process $proc$libresoc.v:279$10 + attribute \src "libresoc.v:284.3-293.6" + process $proc$libresoc.v:284$10 assign { } { } assign { } { } assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:280.5-280.29" + attribute \src "libresoc.v:285.5-285.29" switch \initial - attribute \src "libresoc.v:280.9-280.17" + attribute \src "libresoc.v:285.9-285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -463,18 +468,18 @@ module \ALU_dec19 sync always update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] end - attribute \src "libresoc.v:289.3-298.6" - process $proc$libresoc.v:289$11 + attribute \src "libresoc.v:294.3-303.6" + process $proc$libresoc.v:294$11 assign { } { } assign { } { } assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:290.5-290.29" + attribute \src "libresoc.v:295.5-295.29" switch \initial - attribute \src "libresoc.v:290.9-290.17" + attribute \src "libresoc.v:295.9-295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -486,18 +491,18 @@ module \ALU_dec19 sync always update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] end - attribute \src "libresoc.v:299.3-308.6" - process $proc$libresoc.v:299$12 + attribute \src "libresoc.v:304.3-313.6" + process $proc$libresoc.v:304$12 assign { } { } assign { } { } assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:300.5-300.29" + attribute \src "libresoc.v:305.5-305.29" switch \initial - attribute \src "libresoc.v:300.9-300.17" + attribute \src "libresoc.v:305.9-305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -509,18 +514,18 @@ module \ALU_dec19 sync always update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] end - attribute \src "libresoc.v:309.3-318.6" - process $proc$libresoc.v:309$13 + attribute \src "libresoc.v:314.3-323.6" + process $proc$libresoc.v:314$13 assign { } { } assign { } { } assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:310.5-310.29" + attribute \src "libresoc.v:315.5-315.29" switch \initial - attribute \src "libresoc.v:310.9-310.17" + attribute \src "libresoc.v:315.9-315.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -532,18 +537,18 @@ module \ALU_dec19 sync always update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] end - attribute \src "libresoc.v:319.3-328.6" - process $proc$libresoc.v:319$14 + attribute \src "libresoc.v:324.3-333.6" + process $proc$libresoc.v:324$14 assign { } { } assign { } { } assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:320.5-320.29" + attribute \src "libresoc.v:325.5-325.29" switch \initial - attribute \src "libresoc.v:320.9-320.17" + attribute \src "libresoc.v:325.9-325.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -565,68 +570,68 @@ module \ALU_dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:334.1-1750.10" +attribute \src "libresoc.v:339.1-1785.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" attribute \generator "nMigen" module \ALU_dec31 - attribute \src "libresoc.v:1457.3-1478.6" + attribute \src "libresoc.v:1492.3-1513.6" wire width 3 $0\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1479.3-1500.6" + attribute \src "libresoc.v:1514.3-1535.6" wire width 3 $0\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1545.3-1566.6" + attribute \src "libresoc.v:1580.3-1601.6" wire width 2 $0\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1611.3-1632.6" + attribute \src "libresoc.v:1646.3-1667.6" wire $0\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1677.3-1698.6" - wire width 12 $0\ALU_dec31_function_unit[11:0] - attribute \src "libresoc.v:1721.3-1742.6" + attribute \src "libresoc.v:1712.3-1733.6" + wire width 14 $0\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1756.3-1777.6" wire width 3 $0\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1435.3-1456.6" + attribute \src "libresoc.v:1470.3-1491.6" wire width 4 $0\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1699.3-1720.6" + attribute \src "libresoc.v:1734.3-1755.6" wire width 7 $0\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1567.3-1588.6" + attribute \src "libresoc.v:1602.3-1623.6" wire $0\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1589.3-1610.6" + attribute \src "libresoc.v:1624.3-1645.6" wire $0\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1633.3-1654.6" + attribute \src "libresoc.v:1668.3-1689.6" wire $0\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1501.3-1522.6" + attribute \src "libresoc.v:1536.3-1557.6" wire width 4 $0\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1523.3-1544.6" + attribute \src "libresoc.v:1558.3-1579.6" wire width 2 $0\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1655.3-1676.6" + attribute \src "libresoc.v:1690.3-1711.6" wire $0\ALU_dec31_sgn[0:0] - attribute \src "libresoc.v:335.7-335.20" + attribute \src "libresoc.v:340.7-340.20" wire $0\initial[0:0] - attribute \src "libresoc.v:1457.3-1478.6" + attribute \src "libresoc.v:1492.3-1513.6" wire width 3 $1\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1479.3-1500.6" + attribute \src "libresoc.v:1514.3-1535.6" wire width 3 $1\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1545.3-1566.6" + attribute \src "libresoc.v:1580.3-1601.6" wire width 2 $1\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1611.3-1632.6" + attribute \src "libresoc.v:1646.3-1667.6" wire $1\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1677.3-1698.6" - wire width 12 $1\ALU_dec31_function_unit[11:0] - attribute \src "libresoc.v:1721.3-1742.6" + attribute \src "libresoc.v:1712.3-1733.6" + wire width 14 $1\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1756.3-1777.6" wire width 3 $1\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1435.3-1456.6" + attribute \src "libresoc.v:1470.3-1491.6" wire width 4 $1\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1699.3-1720.6" + attribute \src "libresoc.v:1734.3-1755.6" wire width 7 $1\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1567.3-1588.6" + attribute \src "libresoc.v:1602.3-1623.6" wire $1\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1589.3-1610.6" + attribute \src "libresoc.v:1624.3-1645.6" wire $1\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1633.3-1654.6" + attribute \src "libresoc.v:1668.3-1689.6" wire $1\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1501.3-1522.6" + attribute \src "libresoc.v:1536.3-1557.6" wire width 4 $1\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1523.3-1544.6" + attribute \src "libresoc.v:1558.3-1579.6" wire width 2 $1\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1655.3-1676.6" + attribute \src "libresoc.v:1690.3-1711.6" wire $1\ALU_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -636,7 +641,8 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -644,15 +650,16 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -662,7 +669,8 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -670,38 +678,41 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -718,7 +729,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -794,13 +805,14 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -808,17 +820,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -828,7 +840,8 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -836,38 +849,41 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -884,7 +900,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -960,13 +976,14 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -974,17 +991,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec31_dec_sub10_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -994,7 +1011,8 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1002,38 +1020,41 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1050,7 +1071,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1126,13 +1147,14 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1140,17 +1162,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec31_dec_sub22_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1160,7 +1182,8 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1168,38 +1191,41 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1216,7 +1242,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1292,13 +1318,14 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1306,17 +1333,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1326,7 +1353,8 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1334,38 +1362,41 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1382,7 +1413,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1458,13 +1489,14 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1472,40 +1504,42 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec31_dec_sub8_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1522,7 +1556,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1598,13 +1632,14 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1612,26 +1647,26 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_sgn - attribute \src "libresoc.v:335.7-335.15" + attribute \src "libresoc.v:340.7-340.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:1350.22-1366.4" + attribute \src "libresoc.v:1385.22-1401.4" cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out @@ -1650,7 +1685,7 @@ module \ALU_dec31 connect \opcode_in \ALU_dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:1367.23-1383.4" + attribute \src "libresoc.v:1402.23-1418.4" cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out @@ -1669,7 +1704,7 @@ module \ALU_dec31 connect \opcode_in \ALU_dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:1384.23-1400.4" + attribute \src "libresoc.v:1419.23-1435.4" cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out @@ -1688,7 +1723,7 @@ module \ALU_dec31 connect \opcode_in \ALU_dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:1401.23-1417.4" + attribute \src "libresoc.v:1436.23-1452.4" cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out @@ -1707,7 +1742,7 @@ module \ALU_dec31 connect \opcode_in \ALU_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:1418.22-1434.4" + attribute \src "libresoc.v:1453.22-1469.4" cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out @@ -1725,18 +1760,18 @@ module \ALU_dec31 connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn connect \opcode_in \ALU_dec31_dec_sub8_opcode_in end - attribute \src "libresoc.v:1435.3-1456.6" - process $proc$libresoc.v:1435$16 + attribute \src "libresoc.v:1470.3-1491.6" + process $proc$libresoc.v:1470$16 assign { } { } assign { } { } assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1436.5-1436.29" + attribute \src "libresoc.v:1471.5-1471.29" switch \initial - attribute \src "libresoc.v:1436.9-1436.17" + attribute \src "libresoc.v:1471.9-1471.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1764,18 +1799,18 @@ module \ALU_dec31 sync always update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:1457.3-1478.6" - process $proc$libresoc.v:1457$17 + attribute \src "libresoc.v:1492.3-1513.6" + process $proc$libresoc.v:1492$17 assign { } { } assign { } { } assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1458.5-1458.29" + attribute \src "libresoc.v:1493.5-1493.29" switch \initial - attribute \src "libresoc.v:1458.9-1458.17" + attribute \src "libresoc.v:1493.9-1493.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1803,18 +1838,18 @@ module \ALU_dec31 sync always update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] end - attribute \src "libresoc.v:1479.3-1500.6" - process $proc$libresoc.v:1479$18 + attribute \src "libresoc.v:1514.3-1535.6" + process $proc$libresoc.v:1514$18 assign { } { } assign { } { } assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1480.5-1480.29" + attribute \src "libresoc.v:1515.5-1515.29" switch \initial - attribute \src "libresoc.v:1480.9-1480.17" + attribute \src "libresoc.v:1515.9-1515.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1842,18 +1877,18 @@ module \ALU_dec31 sync always update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] end - attribute \src "libresoc.v:1501.3-1522.6" - process $proc$libresoc.v:1501$19 + attribute \src "libresoc.v:1536.3-1557.6" + process $proc$libresoc.v:1536$19 assign { } { } assign { } { } assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1502.5-1502.29" + attribute \src "libresoc.v:1537.5-1537.29" switch \initial - attribute \src "libresoc.v:1502.9-1502.17" + attribute \src "libresoc.v:1537.9-1537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1881,18 +1916,18 @@ module \ALU_dec31 sync always update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] end - attribute \src "libresoc.v:1523.3-1544.6" - process $proc$libresoc.v:1523$20 + attribute \src "libresoc.v:1558.3-1579.6" + process $proc$libresoc.v:1558$20 assign { } { } assign { } { } assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1524.5-1524.29" + attribute \src "libresoc.v:1559.5-1559.29" switch \initial - attribute \src "libresoc.v:1524.9-1524.17" + attribute \src "libresoc.v:1559.9-1559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1920,18 +1955,18 @@ module \ALU_dec31 sync always update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:1545.3-1566.6" - process $proc$libresoc.v:1545$21 + attribute \src "libresoc.v:1580.3-1601.6" + process $proc$libresoc.v:1580$21 assign { } { } assign { } { } assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1546.5-1546.29" + attribute \src "libresoc.v:1581.5-1581.29" switch \initial - attribute \src "libresoc.v:1546.9-1546.17" + attribute \src "libresoc.v:1581.9-1581.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1959,18 +1994,18 @@ module \ALU_dec31 sync always update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] end - attribute \src "libresoc.v:1567.3-1588.6" - process $proc$libresoc.v:1567$22 + attribute \src "libresoc.v:1602.3-1623.6" + process $proc$libresoc.v:1602$22 assign { } { } assign { } { } assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1568.5-1568.29" + attribute \src "libresoc.v:1603.5-1603.29" switch \initial - attribute \src "libresoc.v:1568.9-1568.17" + attribute \src "libresoc.v:1603.9-1603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1998,18 +2033,18 @@ module \ALU_dec31 sync always update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] end - attribute \src "libresoc.v:1589.3-1610.6" - process $proc$libresoc.v:1589$23 + attribute \src "libresoc.v:1624.3-1645.6" + process $proc$libresoc.v:1624$23 assign { } { } assign { } { } assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1590.5-1590.29" + attribute \src "libresoc.v:1625.5-1625.29" switch \initial - attribute \src "libresoc.v:1590.9-1590.17" + attribute \src "libresoc.v:1625.9-1625.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2037,18 +2072,18 @@ module \ALU_dec31 sync always update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] end - attribute \src "libresoc.v:1611.3-1632.6" - process $proc$libresoc.v:1611$24 + attribute \src "libresoc.v:1646.3-1667.6" + process $proc$libresoc.v:1646$24 assign { } { } assign { } { } assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1612.5-1612.29" + attribute \src "libresoc.v:1647.5-1647.29" switch \initial - attribute \src "libresoc.v:1612.9-1612.17" + attribute \src "libresoc.v:1647.9-1647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2076,18 +2111,18 @@ module \ALU_dec31 sync always update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] end - attribute \src "libresoc.v:1633.3-1654.6" - process $proc$libresoc.v:1633$25 + attribute \src "libresoc.v:1668.3-1689.6" + process $proc$libresoc.v:1668$25 assign { } { } assign { } { } assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1634.5-1634.29" + attribute \src "libresoc.v:1669.5-1669.29" switch \initial - attribute \src "libresoc.v:1634.9-1634.17" + attribute \src "libresoc.v:1669.9-1669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2115,18 +2150,18 @@ module \ALU_dec31 sync always update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] end - attribute \src "libresoc.v:1655.3-1676.6" - process $proc$libresoc.v:1655$26 + attribute \src "libresoc.v:1690.3-1711.6" + process $proc$libresoc.v:1690$26 assign { } { } assign { } { } assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] - attribute \src "libresoc.v:1656.5-1656.29" + attribute \src "libresoc.v:1691.5-1691.29" switch \initial - attribute \src "libresoc.v:1656.9-1656.17" + attribute \src "libresoc.v:1691.9-1691.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2154,57 +2189,57 @@ module \ALU_dec31 sync always update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] end - attribute \src "libresoc.v:1677.3-1698.6" - process $proc$libresoc.v:1677$27 + attribute \src "libresoc.v:1712.3-1733.6" + process $proc$libresoc.v:1712$27 assign { } { } assign { } { } - assign $0\ALU_dec31_function_unit[11:0] $1\ALU_dec31_function_unit[11:0] - attribute \src "libresoc.v:1678.5-1678.29" + assign $0\ALU_dec31_function_unit[13:0] $1\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1713.5-1713.29" switch \initial - attribute \src "libresoc.v:1678.9-1678.17" + attribute \src "libresoc.v:1713.9-1713.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit case - assign $1\ALU_dec31_function_unit[11:0] 12'000000000000 + assign $1\ALU_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[11:0] + update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[13:0] end - attribute \src "libresoc.v:1699.3-1720.6" - process $proc$libresoc.v:1699$28 + attribute \src "libresoc.v:1734.3-1755.6" + process $proc$libresoc.v:1734$28 assign { } { } assign { } { } assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1700.5-1700.29" + attribute \src "libresoc.v:1735.5-1735.29" switch \initial - attribute \src "libresoc.v:1700.9-1700.17" + attribute \src "libresoc.v:1735.9-1735.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2232,18 +2267,18 @@ module \ALU_dec31 sync always update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] end - attribute \src "libresoc.v:1721.3-1742.6" - process $proc$libresoc.v:1721$29 + attribute \src "libresoc.v:1756.3-1777.6" + process $proc$libresoc.v:1756$29 assign { } { } assign { } { } assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1722.5-1722.29" + attribute \src "libresoc.v:1757.5-1757.29" switch \initial - attribute \src "libresoc.v:1722.9-1722.17" + attribute \src "libresoc.v:1757.9-1757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2271,8 +2306,8 @@ module \ALU_dec31 sync always update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] end - attribute \src "libresoc.v:335.7-335.20" - process $proc$libresoc.v:335$30 + attribute \src "libresoc.v:340.7-340.20" + process $proc$libresoc.v:340$30 assign { } { } assign $0\initial[0:0] 1'0 sync always @@ -2287,68 +2322,68 @@ module \ALU_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:1754.1-2163.10" +attribute \src "libresoc.v:1789.1-2203.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" attribute \generator "nMigen" module \ALU_dec31_dec_sub0 - attribute \src "libresoc.v:2082.3-2097.6" + attribute \src "libresoc.v:2122.3-2137.6" wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:2098.3-2113.6" + attribute \src "libresoc.v:2138.3-2153.6" wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2146.3-2161.6" + attribute \src "libresoc.v:2186.3-2201.6" wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:1986.3-2001.6" + attribute \src "libresoc.v:2026.3-2041.6" wire $0\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:1938.3-1953.6" - wire width 12 $0\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:2050.3-2065.6" + attribute \src "libresoc.v:1978.3-1993.6" + wire width 14 $0\ALU_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:2090.3-2105.6" wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:2066.3-2081.6" + attribute \src "libresoc.v:2106.3-2121.6" wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2034.3-2049.6" + attribute \src "libresoc.v:2074.3-2089.6" wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:1954.3-1969.6" + attribute \src "libresoc.v:1994.3-2009.6" wire $0\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:1970.3-1985.6" + attribute \src "libresoc.v:2010.3-2025.6" wire $0\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:2002.3-2017.6" + attribute \src "libresoc.v:2042.3-2057.6" wire $0\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2114.3-2129.6" + attribute \src "libresoc.v:2154.3-2169.6" wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:2130.3-2145.6" + attribute \src "libresoc.v:2170.3-2185.6" wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2018.3-2033.6" + attribute \src "libresoc.v:2058.3-2073.6" wire $0\ALU_dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:1755.7-1755.20" + attribute \src "libresoc.v:1790.7-1790.20" wire $0\initial[0:0] - attribute \src "libresoc.v:2082.3-2097.6" + attribute \src "libresoc.v:2122.3-2137.6" wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:2098.3-2113.6" + attribute \src "libresoc.v:2138.3-2153.6" wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2146.3-2161.6" + attribute \src "libresoc.v:2186.3-2201.6" wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:1986.3-2001.6" + attribute \src "libresoc.v:2026.3-2041.6" wire $1\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:1938.3-1953.6" - wire width 12 $1\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:2050.3-2065.6" + attribute \src "libresoc.v:1978.3-1993.6" + wire width 14 $1\ALU_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:2090.3-2105.6" wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:2066.3-2081.6" + attribute \src "libresoc.v:2106.3-2121.6" wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2034.3-2049.6" + attribute \src "libresoc.v:2074.3-2089.6" wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:1954.3-1969.6" + attribute \src "libresoc.v:1994.3-2009.6" wire $1\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:1970.3-1985.6" + attribute \src "libresoc.v:2010.3-2025.6" wire $1\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:2002.3-2017.6" + attribute \src "libresoc.v:2042.3-2057.6" wire $1\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2114.3-2129.6" + attribute \src "libresoc.v:2154.3-2169.6" wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:2130.3-2145.6" + attribute \src "libresoc.v:2170.3-2185.6" wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2018.3-2033.6" + attribute \src "libresoc.v:2058.3-2073.6" wire $1\ALU_dec31_dec_sub0_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -2358,7 +2393,8 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -2366,38 +2402,41 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -2414,7 +2453,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -2490,13 +2529,14 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -2504,73 +2544,73 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub0_sgn - attribute \src "libresoc.v:1755.7-1755.15" + attribute \src "libresoc.v:1790.7-1790.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:1755.7-1755.20" - process $proc$libresoc.v:1755$45 + attribute \src "libresoc.v:1790.7-1790.20" + process $proc$libresoc.v:1790$45 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:1938.3-1953.6" - process $proc$libresoc.v:1938$31 + attribute \src "libresoc.v:1978.3-1993.6" + process $proc$libresoc.v:1978$31 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_function_unit[11:0] $1\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:1939.5-1939.29" + assign $0\ALU_dec31_dec_sub0_function_unit[13:0] $1\ALU_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:1979.5-1979.29" switch \initial - attribute \src "libresoc.v:1939.9-1939.17" + attribute \src "libresoc.v:1979.9-1979.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[11:0] + update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:1954.3-1969.6" - process $proc$libresoc.v:1954$32 + attribute \src "libresoc.v:1994.3-2009.6" + process $proc$libresoc.v:1994$32 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:1955.5-1955.29" + attribute \src "libresoc.v:1995.5-1995.29" switch \initial - attribute \src "libresoc.v:1955.9-1955.17" + attribute \src "libresoc.v:1995.9-1995.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2590,18 +2630,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:1970.3-1985.6" - process $proc$libresoc.v:1970$33 + attribute \src "libresoc.v:2010.3-2025.6" + process $proc$libresoc.v:2010$33 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:1971.5-1971.29" + attribute \src "libresoc.v:2011.5-2011.29" switch \initial - attribute \src "libresoc.v:1971.9-1971.17" + attribute \src "libresoc.v:2011.9-2011.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2621,18 +2661,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:1986.3-2001.6" - process $proc$libresoc.v:1986$34 + attribute \src "libresoc.v:2026.3-2041.6" + process $proc$libresoc.v:2026$34 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:1987.5-1987.29" + attribute \src "libresoc.v:2027.5-2027.29" switch \initial - attribute \src "libresoc.v:1987.9-1987.17" + attribute \src "libresoc.v:2027.9-2027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2652,18 +2692,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:2002.3-2017.6" - process $proc$libresoc.v:2002$35 + attribute \src "libresoc.v:2042.3-2057.6" + process $proc$libresoc.v:2042$35 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2003.5-2003.29" + attribute \src "libresoc.v:2043.5-2043.29" switch \initial - attribute \src "libresoc.v:2003.9-2003.17" + attribute \src "libresoc.v:2043.9-2043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2683,18 +2723,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:2018.3-2033.6" - process $proc$libresoc.v:2018$36 + attribute \src "libresoc.v:2058.3-2073.6" + process $proc$libresoc.v:2058$36 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:2019.5-2019.29" + attribute \src "libresoc.v:2059.5-2059.29" switch \initial - attribute \src "libresoc.v:2019.9-2019.17" + attribute \src "libresoc.v:2059.9-2059.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2714,18 +2754,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:2034.3-2049.6" - process $proc$libresoc.v:2034$37 + attribute \src "libresoc.v:2074.3-2089.6" + process $proc$libresoc.v:2074$37 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:2035.5-2035.29" + attribute \src "libresoc.v:2075.5-2075.29" switch \initial - attribute \src "libresoc.v:2035.9-2035.17" + attribute \src "libresoc.v:2075.9-2075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2745,18 +2785,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:2050.3-2065.6" - process $proc$libresoc.v:2050$38 + attribute \src "libresoc.v:2090.3-2105.6" + process $proc$libresoc.v:2090$38 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:2051.5-2051.29" + attribute \src "libresoc.v:2091.5-2091.29" switch \initial - attribute \src "libresoc.v:2051.9-2051.17" + attribute \src "libresoc.v:2091.9-2091.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2776,18 +2816,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:2066.3-2081.6" - process $proc$libresoc.v:2066$39 + attribute \src "libresoc.v:2106.3-2121.6" + process $proc$libresoc.v:2106$39 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2067.5-2067.29" + attribute \src "libresoc.v:2107.5-2107.29" switch \initial - attribute \src "libresoc.v:2067.9-2067.17" + attribute \src "libresoc.v:2107.9-2107.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2807,18 +2847,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:2082.3-2097.6" - process $proc$libresoc.v:2082$40 + attribute \src "libresoc.v:2122.3-2137.6" + process $proc$libresoc.v:2122$40 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:2083.5-2083.29" + attribute \src "libresoc.v:2123.5-2123.29" switch \initial - attribute \src "libresoc.v:2083.9-2083.17" + attribute \src "libresoc.v:2123.9-2123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2838,18 +2878,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:2098.3-2113.6" - process $proc$libresoc.v:2098$41 + attribute \src "libresoc.v:2138.3-2153.6" + process $proc$libresoc.v:2138$41 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2099.5-2099.29" + attribute \src "libresoc.v:2139.5-2139.29" switch \initial - attribute \src "libresoc.v:2099.9-2099.17" + attribute \src "libresoc.v:2139.9-2139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2869,18 +2909,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:2114.3-2129.6" - process $proc$libresoc.v:2114$42 + attribute \src "libresoc.v:2154.3-2169.6" + process $proc$libresoc.v:2154$42 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:2115.5-2115.29" + attribute \src "libresoc.v:2155.5-2155.29" switch \initial - attribute \src "libresoc.v:2115.9-2115.17" + attribute \src "libresoc.v:2155.9-2155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2900,18 +2940,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:2130.3-2145.6" - process $proc$libresoc.v:2130$43 + attribute \src "libresoc.v:2170.3-2185.6" + process $proc$libresoc.v:2170$43 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2131.5-2131.29" + attribute \src "libresoc.v:2171.5-2171.29" switch \initial - attribute \src "libresoc.v:2131.9-2131.17" + attribute \src "libresoc.v:2171.9-2171.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2931,18 +2971,18 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:2146.3-2161.6" - process $proc$libresoc.v:2146$44 + attribute \src "libresoc.v:2186.3-2201.6" + process $proc$libresoc.v:2186$44 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:2147.5-2147.29" + attribute \src "libresoc.v:2187.5-2187.29" switch \initial - attribute \src "libresoc.v:2147.9-2147.17" + attribute \src "libresoc.v:2187.9-2187.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2964,68 +3004,68 @@ module \ALU_dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:2167.1-2870.10" +attribute \src "libresoc.v:2207.1-2915.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" attribute \generator "nMigen" module \ALU_dec31_dec_sub10 - attribute \src "libresoc.v:2684.3-2720.6" + attribute \src "libresoc.v:2729.3-2765.6" wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2721.3-2757.6" + attribute \src "libresoc.v:2766.3-2802.6" wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2832.3-2868.6" + attribute \src "libresoc.v:2877.3-2913.6" wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2462.3-2498.6" + attribute \src "libresoc.v:2507.3-2543.6" wire $0\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2351.3-2387.6" - wire width 12 $0\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:2610.3-2646.6" + attribute \src "libresoc.v:2396.3-2432.6" + wire width 14 $0\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2655.3-2691.6" wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2647.3-2683.6" + attribute \src "libresoc.v:2692.3-2728.6" wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2573.3-2609.6" + attribute \src "libresoc.v:2618.3-2654.6" wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2388.3-2424.6" + attribute \src "libresoc.v:2433.3-2469.6" wire $0\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2425.3-2461.6" + attribute \src "libresoc.v:2470.3-2506.6" wire $0\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2499.3-2535.6" + attribute \src "libresoc.v:2544.3-2580.6" wire $0\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2758.3-2794.6" + attribute \src "libresoc.v:2803.3-2839.6" wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2795.3-2831.6" + attribute \src "libresoc.v:2840.3-2876.6" wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2536.3-2572.6" + attribute \src "libresoc.v:2581.3-2617.6" wire $0\ALU_dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:2168.7-2168.20" + attribute \src "libresoc.v:2208.7-2208.20" wire $0\initial[0:0] - attribute \src "libresoc.v:2684.3-2720.6" + attribute \src "libresoc.v:2729.3-2765.6" wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2721.3-2757.6" + attribute \src "libresoc.v:2766.3-2802.6" wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2832.3-2868.6" + attribute \src "libresoc.v:2877.3-2913.6" wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2462.3-2498.6" + attribute \src "libresoc.v:2507.3-2543.6" wire $1\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2351.3-2387.6" - wire width 12 $1\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:2610.3-2646.6" + attribute \src "libresoc.v:2396.3-2432.6" + wire width 14 $1\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2655.3-2691.6" wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2647.3-2683.6" + attribute \src "libresoc.v:2692.3-2728.6" wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2573.3-2609.6" + attribute \src "libresoc.v:2618.3-2654.6" wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2388.3-2424.6" + attribute \src "libresoc.v:2433.3-2469.6" wire $1\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2425.3-2461.6" + attribute \src "libresoc.v:2470.3-2506.6" wire $1\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2499.3-2535.6" + attribute \src "libresoc.v:2544.3-2580.6" wire $1\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2758.3-2794.6" + attribute \src "libresoc.v:2803.3-2839.6" wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2795.3-2831.6" + attribute \src "libresoc.v:2840.3-2876.6" wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2536.3-2572.6" + attribute \src "libresoc.v:2581.3-2617.6" wire $1\ALU_dec31_dec_sub10_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -3035,7 +3075,8 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -3043,38 +3084,41 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub10_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -3091,7 +3135,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -3167,13 +3211,14 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -3181,101 +3226,101 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub10_sgn - attribute \src "libresoc.v:2168.7-2168.15" + attribute \src "libresoc.v:2208.7-2208.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:2168.7-2168.20" - process $proc$libresoc.v:2168$60 + attribute \src "libresoc.v:2208.7-2208.20" + process $proc$libresoc.v:2208$60 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:2351.3-2387.6" - process $proc$libresoc.v:2351$46 + attribute \src "libresoc.v:2396.3-2432.6" + process $proc$libresoc.v:2396$46 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub10_function_unit[11:0] $1\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:2352.5-2352.29" + assign $0\ALU_dec31_dec_sub10_function_unit[13:0] $1\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2397.5-2397.29" switch \initial - attribute \src "libresoc.v:2352.9-2352.17" + attribute \src "libresoc.v:2397.9-2397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000000 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[11:0] + update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:2388.3-2424.6" - process $proc$libresoc.v:2388$47 + attribute \src "libresoc.v:2433.3-2469.6" + process $proc$libresoc.v:2433$47 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2389.5-2389.29" + attribute \src "libresoc.v:2434.5-2434.29" switch \initial - attribute \src "libresoc.v:2389.9-2389.17" + attribute \src "libresoc.v:2434.9-2434.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3323,18 +3368,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:2425.3-2461.6" - process $proc$libresoc.v:2425$48 + attribute \src "libresoc.v:2470.3-2506.6" + process $proc$libresoc.v:2470$48 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2426.5-2426.29" + attribute \src "libresoc.v:2471.5-2471.29" switch \initial - attribute \src "libresoc.v:2426.9-2426.17" + attribute \src "libresoc.v:2471.9-2471.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3382,18 +3427,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:2462.3-2498.6" - process $proc$libresoc.v:2462$49 + attribute \src "libresoc.v:2507.3-2543.6" + process $proc$libresoc.v:2507$49 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2463.5-2463.29" + attribute \src "libresoc.v:2508.5-2508.29" switch \initial - attribute \src "libresoc.v:2463.9-2463.17" + attribute \src "libresoc.v:2508.9-2508.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3441,18 +3486,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:2499.3-2535.6" - process $proc$libresoc.v:2499$50 + attribute \src "libresoc.v:2544.3-2580.6" + process $proc$libresoc.v:2544$50 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2500.5-2500.29" + attribute \src "libresoc.v:2545.5-2545.29" switch \initial - attribute \src "libresoc.v:2500.9-2500.17" + attribute \src "libresoc.v:2545.9-2545.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3500,18 +3545,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:2536.3-2572.6" - process $proc$libresoc.v:2536$51 + attribute \src "libresoc.v:2581.3-2617.6" + process $proc$libresoc.v:2581$51 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:2537.5-2537.29" + attribute \src "libresoc.v:2582.5-2582.29" switch \initial - attribute \src "libresoc.v:2537.9-2537.17" + attribute \src "libresoc.v:2582.9-2582.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3559,18 +3604,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:2573.3-2609.6" - process $proc$libresoc.v:2573$52 + attribute \src "libresoc.v:2618.3-2654.6" + process $proc$libresoc.v:2618$52 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2574.5-2574.29" + attribute \src "libresoc.v:2619.5-2619.29" switch \initial - attribute \src "libresoc.v:2574.9-2574.17" + attribute \src "libresoc.v:2619.9-2619.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3618,18 +3663,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:2610.3-2646.6" - process $proc$libresoc.v:2610$53 + attribute \src "libresoc.v:2655.3-2691.6" + process $proc$libresoc.v:2655$53 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2611.5-2611.29" + attribute \src "libresoc.v:2656.5-2656.29" switch \initial - attribute \src "libresoc.v:2611.9-2611.17" + attribute \src "libresoc.v:2656.9-2656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3677,18 +3722,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:2647.3-2683.6" - process $proc$libresoc.v:2647$54 + attribute \src "libresoc.v:2692.3-2728.6" + process $proc$libresoc.v:2692$54 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2648.5-2648.29" + attribute \src "libresoc.v:2693.5-2693.29" switch \initial - attribute \src "libresoc.v:2648.9-2648.17" + attribute \src "libresoc.v:2693.9-2693.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3736,18 +3781,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:2684.3-2720.6" - process $proc$libresoc.v:2684$55 + attribute \src "libresoc.v:2729.3-2765.6" + process $proc$libresoc.v:2729$55 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2685.5-2685.29" + attribute \src "libresoc.v:2730.5-2730.29" switch \initial - attribute \src "libresoc.v:2685.9-2685.17" + attribute \src "libresoc.v:2730.9-2730.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3795,18 +3840,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:2721.3-2757.6" - process $proc$libresoc.v:2721$56 + attribute \src "libresoc.v:2766.3-2802.6" + process $proc$libresoc.v:2766$56 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2722.5-2722.29" + attribute \src "libresoc.v:2767.5-2767.29" switch \initial - attribute \src "libresoc.v:2722.9-2722.17" + attribute \src "libresoc.v:2767.9-2767.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3854,18 +3899,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:2758.3-2794.6" - process $proc$libresoc.v:2758$57 + attribute \src "libresoc.v:2803.3-2839.6" + process $proc$libresoc.v:2803$57 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2759.5-2759.29" + attribute \src "libresoc.v:2804.5-2804.29" switch \initial - attribute \src "libresoc.v:2759.9-2759.17" + attribute \src "libresoc.v:2804.9-2804.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3913,18 +3958,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:2795.3-2831.6" - process $proc$libresoc.v:2795$58 + attribute \src "libresoc.v:2840.3-2876.6" + process $proc$libresoc.v:2840$58 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2796.5-2796.29" + attribute \src "libresoc.v:2841.5-2841.29" switch \initial - attribute \src "libresoc.v:2796.9-2796.17" + attribute \src "libresoc.v:2841.9-2841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3972,18 +4017,18 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:2832.3-2868.6" - process $proc$libresoc.v:2832$59 + attribute \src "libresoc.v:2877.3-2913.6" + process $proc$libresoc.v:2877$59 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2833.5-2833.29" + attribute \src "libresoc.v:2878.5-2878.29" switch \initial - attribute \src "libresoc.v:2833.9-2833.17" + attribute \src "libresoc.v:2878.9-2878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -4033,68 +4078,68 @@ module \ALU_dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:2874.1-3451.10" +attribute \src "libresoc.v:2919.1-3501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" attribute \generator "nMigen" module \ALU_dec31_dec_sub22 - attribute \src "libresoc.v:3310.3-3337.6" + attribute \src "libresoc.v:3360.3-3387.6" wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3338.3-3365.6" + attribute \src "libresoc.v:3388.3-3415.6" wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3422.3-3449.6" + attribute \src "libresoc.v:3472.3-3499.6" wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3142.3-3169.6" + attribute \src "libresoc.v:3192.3-3219.6" wire $0\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3058.3-3085.6" - wire width 12 $0\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:3254.3-3281.6" + attribute \src "libresoc.v:3108.3-3135.6" + wire width 14 $0\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3304.3-3331.6" wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3282.3-3309.6" + attribute \src "libresoc.v:3332.3-3359.6" wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3226.3-3253.6" + attribute \src "libresoc.v:3276.3-3303.6" wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3086.3-3113.6" + attribute \src "libresoc.v:3136.3-3163.6" wire $0\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3114.3-3141.6" + attribute \src "libresoc.v:3164.3-3191.6" wire $0\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3170.3-3197.6" + attribute \src "libresoc.v:3220.3-3247.6" wire $0\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3366.3-3393.6" + attribute \src "libresoc.v:3416.3-3443.6" wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3394.3-3421.6" + attribute \src "libresoc.v:3444.3-3471.6" wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3198.3-3225.6" + attribute \src "libresoc.v:3248.3-3275.6" wire $0\ALU_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:2875.7-2875.20" + attribute \src "libresoc.v:2920.7-2920.20" wire $0\initial[0:0] - attribute \src "libresoc.v:3310.3-3337.6" + attribute \src "libresoc.v:3360.3-3387.6" wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3338.3-3365.6" + attribute \src "libresoc.v:3388.3-3415.6" wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3422.3-3449.6" + attribute \src "libresoc.v:3472.3-3499.6" wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3142.3-3169.6" + attribute \src "libresoc.v:3192.3-3219.6" wire $1\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3058.3-3085.6" - wire width 12 $1\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:3254.3-3281.6" + attribute \src "libresoc.v:3108.3-3135.6" + wire width 14 $1\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3304.3-3331.6" wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3282.3-3309.6" + attribute \src "libresoc.v:3332.3-3359.6" wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3226.3-3253.6" + attribute \src "libresoc.v:3276.3-3303.6" wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3086.3-3113.6" + attribute \src "libresoc.v:3136.3-3163.6" wire $1\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3114.3-3141.6" + attribute \src "libresoc.v:3164.3-3191.6" wire $1\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3170.3-3197.6" + attribute \src "libresoc.v:3220.3-3247.6" wire $1\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3366.3-3393.6" + attribute \src "libresoc.v:3416.3-3443.6" wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3394.3-3421.6" + attribute \src "libresoc.v:3444.3-3471.6" wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3198.3-3225.6" + attribute \src "libresoc.v:3248.3-3275.6" wire $1\ALU_dec31_dec_sub22_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -4104,7 +4149,8 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -4112,38 +4158,41 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -4160,7 +4209,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -4236,13 +4285,14 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -4250,89 +4300,89 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub22_sgn - attribute \src "libresoc.v:2875.7-2875.15" + attribute \src "libresoc.v:2920.7-2920.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:2875.7-2875.20" - process $proc$libresoc.v:2875$75 + attribute \src "libresoc.v:2920.7-2920.20" + process $proc$libresoc.v:2920$75 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:3058.3-3085.6" - process $proc$libresoc.v:3058$61 + attribute \src "libresoc.v:3108.3-3135.6" + process $proc$libresoc.v:3108$61 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub22_function_unit[11:0] $1\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:3059.5-3059.29" + assign $0\ALU_dec31_dec_sub22_function_unit[13:0] $1\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3109.5-3109.29" switch \initial - attribute \src "libresoc.v:3059.9-3059.17" + attribute \src "libresoc.v:3109.9-3109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000000 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[11:0] + update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:3086.3-3113.6" - process $proc$libresoc.v:3086$62 + attribute \src "libresoc.v:3136.3-3163.6" + process $proc$libresoc.v:3136$62 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3087.5-3087.29" + attribute \src "libresoc.v:3137.5-3137.29" switch \initial - attribute \src "libresoc.v:3087.9-3087.17" + attribute \src "libresoc.v:3137.9-3137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4368,18 +4418,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:3114.3-3141.6" - process $proc$libresoc.v:3114$63 + attribute \src "libresoc.v:3164.3-3191.6" + process $proc$libresoc.v:3164$63 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3115.5-3115.29" + attribute \src "libresoc.v:3165.5-3165.29" switch \initial - attribute \src "libresoc.v:3115.9-3115.17" + attribute \src "libresoc.v:3165.9-3165.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4415,18 +4465,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:3142.3-3169.6" - process $proc$libresoc.v:3142$64 + attribute \src "libresoc.v:3192.3-3219.6" + process $proc$libresoc.v:3192$64 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3143.5-3143.29" + attribute \src "libresoc.v:3193.5-3193.29" switch \initial - attribute \src "libresoc.v:3143.9-3143.17" + attribute \src "libresoc.v:3193.9-3193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4462,18 +4512,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:3170.3-3197.6" - process $proc$libresoc.v:3170$65 + attribute \src "libresoc.v:3220.3-3247.6" + process $proc$libresoc.v:3220$65 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3171.5-3171.29" + attribute \src "libresoc.v:3221.5-3221.29" switch \initial - attribute \src "libresoc.v:3171.9-3171.17" + attribute \src "libresoc.v:3221.9-3221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4509,18 +4559,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:3198.3-3225.6" - process $proc$libresoc.v:3198$66 + attribute \src "libresoc.v:3248.3-3275.6" + process $proc$libresoc.v:3248$66 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:3199.5-3199.29" + attribute \src "libresoc.v:3249.5-3249.29" switch \initial - attribute \src "libresoc.v:3199.9-3199.17" + attribute \src "libresoc.v:3249.9-3249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4556,18 +4606,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:3226.3-3253.6" - process $proc$libresoc.v:3226$67 + attribute \src "libresoc.v:3276.3-3303.6" + process $proc$libresoc.v:3276$67 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3227.5-3227.29" + attribute \src "libresoc.v:3277.5-3277.29" switch \initial - attribute \src "libresoc.v:3227.9-3227.17" + attribute \src "libresoc.v:3277.9-3277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4603,18 +4653,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:3254.3-3281.6" - process $proc$libresoc.v:3254$68 + attribute \src "libresoc.v:3304.3-3331.6" + process $proc$libresoc.v:3304$68 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3255.5-3255.29" + attribute \src "libresoc.v:3305.5-3305.29" switch \initial - attribute \src "libresoc.v:3255.9-3255.17" + attribute \src "libresoc.v:3305.9-3305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4650,18 +4700,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:3282.3-3309.6" - process $proc$libresoc.v:3282$69 + attribute \src "libresoc.v:3332.3-3359.6" + process $proc$libresoc.v:3332$69 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3283.5-3283.29" + attribute \src "libresoc.v:3333.5-3333.29" switch \initial - attribute \src "libresoc.v:3283.9-3283.17" + attribute \src "libresoc.v:3333.9-3333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4697,18 +4747,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:3310.3-3337.6" - process $proc$libresoc.v:3310$70 + attribute \src "libresoc.v:3360.3-3387.6" + process $proc$libresoc.v:3360$70 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3311.5-3311.29" + attribute \src "libresoc.v:3361.5-3361.29" switch \initial - attribute \src "libresoc.v:3311.9-3311.17" + attribute \src "libresoc.v:3361.9-3361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4744,18 +4794,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:3338.3-3365.6" - process $proc$libresoc.v:3338$71 + attribute \src "libresoc.v:3388.3-3415.6" + process $proc$libresoc.v:3388$71 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3339.5-3339.29" + attribute \src "libresoc.v:3389.5-3389.29" switch \initial - attribute \src "libresoc.v:3339.9-3339.17" + attribute \src "libresoc.v:3389.9-3389.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4791,18 +4841,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:3366.3-3393.6" - process $proc$libresoc.v:3366$72 + attribute \src "libresoc.v:3416.3-3443.6" + process $proc$libresoc.v:3416$72 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3367.5-3367.29" + attribute \src "libresoc.v:3417.5-3417.29" switch \initial - attribute \src "libresoc.v:3367.9-3367.17" + attribute \src "libresoc.v:3417.9-3417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4838,18 +4888,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:3394.3-3421.6" - process $proc$libresoc.v:3394$73 + attribute \src "libresoc.v:3444.3-3471.6" + process $proc$libresoc.v:3444$73 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3395.5-3395.29" + attribute \src "libresoc.v:3445.5-3445.29" switch \initial - attribute \src "libresoc.v:3395.9-3395.17" + attribute \src "libresoc.v:3445.9-3445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4885,18 +4935,18 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:3422.3-3449.6" - process $proc$libresoc.v:3422$74 + attribute \src "libresoc.v:3472.3-3499.6" + process $proc$libresoc.v:3472$74 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3423.5-3423.29" + attribute \src "libresoc.v:3473.5-3473.29" switch \initial - attribute \src "libresoc.v:3423.9-3423.17" + attribute \src "libresoc.v:3473.9-3473.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4934,68 +4984,68 @@ module \ALU_dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:3455.1-3864.10" +attribute \src "libresoc.v:3505.1-3919.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" attribute \generator "nMigen" module \ALU_dec31_dec_sub26 - attribute \src "libresoc.v:3783.3-3798.6" + attribute \src "libresoc.v:3838.3-3853.6" wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3799.3-3814.6" + attribute \src "libresoc.v:3854.3-3869.6" wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3847.3-3862.6" + attribute \src "libresoc.v:3902.3-3917.6" wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3687.3-3702.6" + attribute \src "libresoc.v:3742.3-3757.6" wire $0\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3639.3-3654.6" - wire width 12 $0\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:3751.3-3766.6" + attribute \src "libresoc.v:3694.3-3709.6" + wire width 14 $0\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3806.3-3821.6" wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3767.3-3782.6" + attribute \src "libresoc.v:3822.3-3837.6" wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3735.3-3750.6" + attribute \src "libresoc.v:3790.3-3805.6" wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3655.3-3670.6" + attribute \src "libresoc.v:3710.3-3725.6" wire $0\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3671.3-3686.6" + attribute \src "libresoc.v:3726.3-3741.6" wire $0\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3703.3-3718.6" + attribute \src "libresoc.v:3758.3-3773.6" wire $0\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3815.3-3830.6" + attribute \src "libresoc.v:3870.3-3885.6" wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3831.3-3846.6" + attribute \src "libresoc.v:3886.3-3901.6" wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3719.3-3734.6" + attribute \src "libresoc.v:3774.3-3789.6" wire $0\ALU_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:3456.7-3456.20" + attribute \src "libresoc.v:3506.7-3506.20" wire $0\initial[0:0] - attribute \src "libresoc.v:3783.3-3798.6" + attribute \src "libresoc.v:3838.3-3853.6" wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3799.3-3814.6" + attribute \src "libresoc.v:3854.3-3869.6" wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3847.3-3862.6" + attribute \src "libresoc.v:3902.3-3917.6" wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3687.3-3702.6" + attribute \src "libresoc.v:3742.3-3757.6" wire $1\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3639.3-3654.6" - wire width 12 $1\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:3751.3-3766.6" + attribute \src "libresoc.v:3694.3-3709.6" + wire width 14 $1\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3806.3-3821.6" wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3767.3-3782.6" + attribute \src "libresoc.v:3822.3-3837.6" wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3735.3-3750.6" + attribute \src "libresoc.v:3790.3-3805.6" wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3655.3-3670.6" + attribute \src "libresoc.v:3710.3-3725.6" wire $1\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3671.3-3686.6" + attribute \src "libresoc.v:3726.3-3741.6" wire $1\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3703.3-3718.6" + attribute \src "libresoc.v:3758.3-3773.6" wire $1\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3815.3-3830.6" + attribute \src "libresoc.v:3870.3-3885.6" wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3831.3-3846.6" + attribute \src "libresoc.v:3886.3-3901.6" wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3719.3-3734.6" + attribute \src "libresoc.v:3774.3-3789.6" wire $1\ALU_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -5005,7 +5055,8 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -5013,38 +5064,41 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -5061,7 +5115,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -5137,13 +5191,14 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -5151,73 +5206,73 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub26_sgn - attribute \src "libresoc.v:3456.7-3456.15" + attribute \src "libresoc.v:3506.7-3506.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:3456.7-3456.20" - process $proc$libresoc.v:3456$90 + attribute \src "libresoc.v:3506.7-3506.20" + process $proc$libresoc.v:3506$90 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:3639.3-3654.6" - process $proc$libresoc.v:3639$76 + attribute \src "libresoc.v:3694.3-3709.6" + process $proc$libresoc.v:3694$76 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub26_function_unit[11:0] $1\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:3640.5-3640.29" + assign $0\ALU_dec31_dec_sub26_function_unit[13:0] $1\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3695.5-3695.29" switch \initial - attribute \src "libresoc.v:3640.9-3640.17" + attribute \src "libresoc.v:3695.9-3695.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[11:0] + update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:3655.3-3670.6" - process $proc$libresoc.v:3655$77 + attribute \src "libresoc.v:3710.3-3725.6" + process $proc$libresoc.v:3710$77 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3656.5-3656.29" + attribute \src "libresoc.v:3711.5-3711.29" switch \initial - attribute \src "libresoc.v:3656.9-3656.17" + attribute \src "libresoc.v:3711.9-3711.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5237,18 +5292,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:3671.3-3686.6" - process $proc$libresoc.v:3671$78 + attribute \src "libresoc.v:3726.3-3741.6" + process $proc$libresoc.v:3726$78 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3672.5-3672.29" + attribute \src "libresoc.v:3727.5-3727.29" switch \initial - attribute \src "libresoc.v:3672.9-3672.17" + attribute \src "libresoc.v:3727.9-3727.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5268,18 +5323,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:3687.3-3702.6" - process $proc$libresoc.v:3687$79 + attribute \src "libresoc.v:3742.3-3757.6" + process $proc$libresoc.v:3742$79 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3688.5-3688.29" + attribute \src "libresoc.v:3743.5-3743.29" switch \initial - attribute \src "libresoc.v:3688.9-3688.17" + attribute \src "libresoc.v:3743.9-3743.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5299,18 +5354,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:3703.3-3718.6" - process $proc$libresoc.v:3703$80 + attribute \src "libresoc.v:3758.3-3773.6" + process $proc$libresoc.v:3758$80 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3704.5-3704.29" + attribute \src "libresoc.v:3759.5-3759.29" switch \initial - attribute \src "libresoc.v:3704.9-3704.17" + attribute \src "libresoc.v:3759.9-3759.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5330,18 +5385,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:3719.3-3734.6" - process $proc$libresoc.v:3719$81 + attribute \src "libresoc.v:3774.3-3789.6" + process $proc$libresoc.v:3774$81 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:3720.5-3720.29" + attribute \src "libresoc.v:3775.5-3775.29" switch \initial - attribute \src "libresoc.v:3720.9-3720.17" + attribute \src "libresoc.v:3775.9-3775.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5361,18 +5416,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:3735.3-3750.6" - process $proc$libresoc.v:3735$82 + attribute \src "libresoc.v:3790.3-3805.6" + process $proc$libresoc.v:3790$82 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3736.5-3736.29" + attribute \src "libresoc.v:3791.5-3791.29" switch \initial - attribute \src "libresoc.v:3736.9-3736.17" + attribute \src "libresoc.v:3791.9-3791.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5392,18 +5447,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:3751.3-3766.6" - process $proc$libresoc.v:3751$83 + attribute \src "libresoc.v:3806.3-3821.6" + process $proc$libresoc.v:3806$83 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3752.5-3752.29" + attribute \src "libresoc.v:3807.5-3807.29" switch \initial - attribute \src "libresoc.v:3752.9-3752.17" + attribute \src "libresoc.v:3807.9-3807.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5423,18 +5478,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:3767.3-3782.6" - process $proc$libresoc.v:3767$84 + attribute \src "libresoc.v:3822.3-3837.6" + process $proc$libresoc.v:3822$84 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3768.5-3768.29" + attribute \src "libresoc.v:3823.5-3823.29" switch \initial - attribute \src "libresoc.v:3768.9-3768.17" + attribute \src "libresoc.v:3823.9-3823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5454,18 +5509,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:3783.3-3798.6" - process $proc$libresoc.v:3783$85 + attribute \src "libresoc.v:3838.3-3853.6" + process $proc$libresoc.v:3838$85 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3784.5-3784.29" + attribute \src "libresoc.v:3839.5-3839.29" switch \initial - attribute \src "libresoc.v:3784.9-3784.17" + attribute \src "libresoc.v:3839.9-3839.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5485,18 +5540,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:3799.3-3814.6" - process $proc$libresoc.v:3799$86 + attribute \src "libresoc.v:3854.3-3869.6" + process $proc$libresoc.v:3854$86 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3800.5-3800.29" + attribute \src "libresoc.v:3855.5-3855.29" switch \initial - attribute \src "libresoc.v:3800.9-3800.17" + attribute \src "libresoc.v:3855.9-3855.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5516,18 +5571,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:3815.3-3830.6" - process $proc$libresoc.v:3815$87 + attribute \src "libresoc.v:3870.3-3885.6" + process $proc$libresoc.v:3870$87 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3816.5-3816.29" + attribute \src "libresoc.v:3871.5-3871.29" switch \initial - attribute \src "libresoc.v:3816.9-3816.17" + attribute \src "libresoc.v:3871.9-3871.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5547,18 +5602,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:3831.3-3846.6" - process $proc$libresoc.v:3831$88 + attribute \src "libresoc.v:3886.3-3901.6" + process $proc$libresoc.v:3886$88 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3832.5-3832.29" + attribute \src "libresoc.v:3887.5-3887.29" switch \initial - attribute \src "libresoc.v:3832.9-3832.17" + attribute \src "libresoc.v:3887.9-3887.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5578,18 +5633,18 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:3847.3-3862.6" - process $proc$libresoc.v:3847$89 + attribute \src "libresoc.v:3902.3-3917.6" + process $proc$libresoc.v:3902$89 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3848.5-3848.29" + attribute \src "libresoc.v:3903.5-3903.29" switch \initial - attribute \src "libresoc.v:3848.9-3848.17" + attribute \src "libresoc.v:3903.9-3903.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5611,68 +5666,68 @@ module \ALU_dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:3868.1-4655.10" +attribute \src "libresoc.v:3923.1-4715.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" attribute \generator "nMigen" module \ALU_dec31_dec_sub8 - attribute \src "libresoc.v:4439.3-4481.6" + attribute \src "libresoc.v:4499.3-4541.6" wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4482.3-4524.6" + attribute \src "libresoc.v:4542.3-4584.6" wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4611.3-4653.6" + attribute \src "libresoc.v:4671.3-4713.6" wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4181.3-4223.6" + attribute \src "libresoc.v:4241.3-4283.6" wire $0\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4052.3-4094.6" - wire width 12 $0\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:4353.3-4395.6" + attribute \src "libresoc.v:4112.3-4154.6" + wire width 14 $0\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4413.3-4455.6" wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4396.3-4438.6" + attribute \src "libresoc.v:4456.3-4498.6" wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4310.3-4352.6" + attribute \src "libresoc.v:4370.3-4412.6" wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4095.3-4137.6" + attribute \src "libresoc.v:4155.3-4197.6" wire $0\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4138.3-4180.6" + attribute \src "libresoc.v:4198.3-4240.6" wire $0\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4224.3-4266.6" + attribute \src "libresoc.v:4284.3-4326.6" wire $0\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4525.3-4567.6" + attribute \src "libresoc.v:4585.3-4627.6" wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4568.3-4610.6" + attribute \src "libresoc.v:4628.3-4670.6" wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4267.3-4309.6" + attribute \src "libresoc.v:4327.3-4369.6" wire $0\ALU_dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:3869.7-3869.20" + attribute \src "libresoc.v:3924.7-3924.20" wire $0\initial[0:0] - attribute \src "libresoc.v:4439.3-4481.6" + attribute \src "libresoc.v:4499.3-4541.6" wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4482.3-4524.6" + attribute \src "libresoc.v:4542.3-4584.6" wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4611.3-4653.6" + attribute \src "libresoc.v:4671.3-4713.6" wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4181.3-4223.6" + attribute \src "libresoc.v:4241.3-4283.6" wire $1\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4052.3-4094.6" - wire width 12 $1\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:4353.3-4395.6" + attribute \src "libresoc.v:4112.3-4154.6" + wire width 14 $1\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4413.3-4455.6" wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4396.3-4438.6" + attribute \src "libresoc.v:4456.3-4498.6" wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4310.3-4352.6" + attribute \src "libresoc.v:4370.3-4412.6" wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4095.3-4137.6" + attribute \src "libresoc.v:4155.3-4197.6" wire $1\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4138.3-4180.6" + attribute \src "libresoc.v:4198.3-4240.6" wire $1\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4224.3-4266.6" + attribute \src "libresoc.v:4284.3-4326.6" wire $1\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4525.3-4567.6" + attribute \src "libresoc.v:4585.3-4627.6" wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4568.3-4610.6" + attribute \src "libresoc.v:4628.3-4670.6" wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4267.3-4309.6" + attribute \src "libresoc.v:4327.3-4369.6" wire $1\ALU_dec31_dec_sub8_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -5682,7 +5737,8 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -5690,38 +5746,41 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub8_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -5738,7 +5797,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -5814,13 +5873,14 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -5828,109 +5888,109 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub8_sgn - attribute \src "libresoc.v:3869.7-3869.15" + attribute \src "libresoc.v:3924.7-3924.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:3869.7-3869.20" - process $proc$libresoc.v:3869$105 + attribute \src "libresoc.v:3924.7-3924.20" + process $proc$libresoc.v:3924$105 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:4052.3-4094.6" - process $proc$libresoc.v:4052$91 + attribute \src "libresoc.v:4112.3-4154.6" + process $proc$libresoc.v:4112$91 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub8_function_unit[11:0] $1\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:4053.5-4053.29" + assign $0\ALU_dec31_dec_sub8_function_unit[13:0] $1\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4113.5-4113.29" switch \initial - attribute \src "libresoc.v:4053.9-4053.17" + attribute \src "libresoc.v:4113.9-4113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000000 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[11:0] + update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:4095.3-4137.6" - process $proc$libresoc.v:4095$92 + attribute \src "libresoc.v:4155.3-4197.6" + process $proc$libresoc.v:4155$92 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4096.5-4096.29" + attribute \src "libresoc.v:4156.5-4156.29" switch \initial - attribute \src "libresoc.v:4096.9-4096.17" + attribute \src "libresoc.v:4156.9-4156.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -5986,18 +6046,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:4138.3-4180.6" - process $proc$libresoc.v:4138$93 + attribute \src "libresoc.v:4198.3-4240.6" + process $proc$libresoc.v:4198$93 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4139.5-4139.29" + attribute \src "libresoc.v:4199.5-4199.29" switch \initial - attribute \src "libresoc.v:4139.9-4139.17" + attribute \src "libresoc.v:4199.9-4199.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6053,18 +6113,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:4181.3-4223.6" - process $proc$libresoc.v:4181$94 + attribute \src "libresoc.v:4241.3-4283.6" + process $proc$libresoc.v:4241$94 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4182.5-4182.29" + attribute \src "libresoc.v:4242.5-4242.29" switch \initial - attribute \src "libresoc.v:4182.9-4182.17" + attribute \src "libresoc.v:4242.9-4242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6120,18 +6180,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:4224.3-4266.6" - process $proc$libresoc.v:4224$95 + attribute \src "libresoc.v:4284.3-4326.6" + process $proc$libresoc.v:4284$95 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4225.5-4225.29" + attribute \src "libresoc.v:4285.5-4285.29" switch \initial - attribute \src "libresoc.v:4225.9-4225.17" + attribute \src "libresoc.v:4285.9-4285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6187,18 +6247,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:4267.3-4309.6" - process $proc$libresoc.v:4267$96 + attribute \src "libresoc.v:4327.3-4369.6" + process $proc$libresoc.v:4327$96 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:4268.5-4268.29" + attribute \src "libresoc.v:4328.5-4328.29" switch \initial - attribute \src "libresoc.v:4268.9-4268.17" + attribute \src "libresoc.v:4328.9-4328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6254,18 +6314,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:4310.3-4352.6" - process $proc$libresoc.v:4310$97 + attribute \src "libresoc.v:4370.3-4412.6" + process $proc$libresoc.v:4370$97 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4311.5-4311.29" + attribute \src "libresoc.v:4371.5-4371.29" switch \initial - attribute \src "libresoc.v:4311.9-4311.17" + attribute \src "libresoc.v:4371.9-4371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6321,18 +6381,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:4353.3-4395.6" - process $proc$libresoc.v:4353$98 + attribute \src "libresoc.v:4413.3-4455.6" + process $proc$libresoc.v:4413$98 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4354.5-4354.29" + attribute \src "libresoc.v:4414.5-4414.29" switch \initial - attribute \src "libresoc.v:4354.9-4354.17" + attribute \src "libresoc.v:4414.9-4414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6388,18 +6448,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:4396.3-4438.6" - process $proc$libresoc.v:4396$99 + attribute \src "libresoc.v:4456.3-4498.6" + process $proc$libresoc.v:4456$99 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4397.5-4397.29" + attribute \src "libresoc.v:4457.5-4457.29" switch \initial - attribute \src "libresoc.v:4397.9-4397.17" + attribute \src "libresoc.v:4457.9-4457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6455,18 +6515,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:4439.3-4481.6" - process $proc$libresoc.v:4439$100 + attribute \src "libresoc.v:4499.3-4541.6" + process $proc$libresoc.v:4499$100 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4440.5-4440.29" + attribute \src "libresoc.v:4500.5-4500.29" switch \initial - attribute \src "libresoc.v:4440.9-4440.17" + attribute \src "libresoc.v:4500.9-4500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6522,18 +6582,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:4482.3-4524.6" - process $proc$libresoc.v:4482$101 + attribute \src "libresoc.v:4542.3-4584.6" + process $proc$libresoc.v:4542$101 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4483.5-4483.29" + attribute \src "libresoc.v:4543.5-4543.29" switch \initial - attribute \src "libresoc.v:4483.9-4483.17" + attribute \src "libresoc.v:4543.9-4543.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6589,18 +6649,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:4525.3-4567.6" - process $proc$libresoc.v:4525$102 + attribute \src "libresoc.v:4585.3-4627.6" + process $proc$libresoc.v:4585$102 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4526.5-4526.29" + attribute \src "libresoc.v:4586.5-4586.29" switch \initial - attribute \src "libresoc.v:4526.9-4526.17" + attribute \src "libresoc.v:4586.9-4586.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6656,18 +6716,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:4568.3-4610.6" - process $proc$libresoc.v:4568$103 + attribute \src "libresoc.v:4628.3-4670.6" + process $proc$libresoc.v:4628$103 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4569.5-4569.29" + attribute \src "libresoc.v:4629.5-4629.29" switch \initial - attribute \src "libresoc.v:4569.9-4569.17" + attribute \src "libresoc.v:4629.9-4629.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6723,18 +6783,18 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:4611.3-4653.6" - process $proc$libresoc.v:4611$104 + attribute \src "libresoc.v:4671.3-4713.6" + process $proc$libresoc.v:4671$104 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4612.5-4612.29" + attribute \src "libresoc.v:4672.5-4672.29" switch \initial - attribute \src "libresoc.v:4612.9-4612.17" + attribute \src "libresoc.v:4672.9-4672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6792,44 +6852,44 @@ module \ALU_dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:4659.1-4938.10" +attribute \src "libresoc.v:4719.1-5003.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" attribute \generator "nMigen" module \BRANCH_dec19 - attribute \src "libresoc.v:4857.3-4872.6" + attribute \src "libresoc.v:4922.3-4937.6" wire width 3 $0\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4873.3-4888.6" + attribute \src "libresoc.v:4938.3-4953.6" wire width 3 $0\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4809.3-4824.6" - wire width 12 $0\BRANCH_dec19_function_unit[11:0] - attribute \src "libresoc.v:4841.3-4856.6" + attribute \src "libresoc.v:4874.3-4889.6" + wire width 14 $0\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4906.3-4921.6" wire width 4 $0\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4825.3-4840.6" + attribute \src "libresoc.v:4890.3-4905.6" wire width 7 $0\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4905.3-4920.6" + attribute \src "libresoc.v:4970.3-4985.6" wire $0\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4921.3-4936.6" + attribute \src "libresoc.v:4986.3-5001.6" wire $0\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4889.3-4904.6" + attribute \src "libresoc.v:4954.3-4969.6" wire width 2 $0\BRANCH_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4660.7-4660.20" + attribute \src "libresoc.v:4720.7-4720.20" wire $0\initial[0:0] - attribute \src "libresoc.v:4857.3-4872.6" + attribute \src "libresoc.v:4922.3-4937.6" wire width 3 $1\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4873.3-4888.6" + attribute \src "libresoc.v:4938.3-4953.6" wire width 3 $1\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4809.3-4824.6" - wire width 12 $1\BRANCH_dec19_function_unit[11:0] - attribute \src "libresoc.v:4841.3-4856.6" + attribute \src "libresoc.v:4874.3-4889.6" + wire width 14 $1\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4906.3-4921.6" wire width 4 $1\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4825.3-4840.6" + attribute \src "libresoc.v:4890.3-4905.6" wire width 7 $1\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4905.3-4920.6" + attribute \src "libresoc.v:4970.3-4985.6" wire $1\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4921.3-4936.6" + attribute \src "libresoc.v:4986.3-5001.6" wire $1\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4889.3-4904.6" + attribute \src "libresoc.v:4954.3-4969.6" wire width 2 $1\BRANCH_dec19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -6839,7 +6899,8 @@ module \BRANCH_dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -6847,23 +6908,26 @@ module \BRANCH_dec19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \BRANCH_dec19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \BRANCH_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -6879,7 +6943,7 @@ module \BRANCH_dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -6955,75 +7019,76 @@ module \BRANCH_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 7 \BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \BRANCH_dec19_rc_sel - attribute \src "libresoc.v:4660.7-4660.15" + attribute \src "libresoc.v:4720.7-4720.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:4660.7-4660.20" - process $proc$libresoc.v:4660$114 + attribute \src "libresoc.v:4720.7-4720.20" + process $proc$libresoc.v:4720$114 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:4809.3-4824.6" - process $proc$libresoc.v:4809$106 + attribute \src "libresoc.v:4874.3-4889.6" + process $proc$libresoc.v:4874$106 assign { } { } assign { } { } - assign $0\BRANCH_dec19_function_unit[11:0] $1\BRANCH_dec19_function_unit[11:0] - attribute \src "libresoc.v:4810.5-4810.29" + assign $0\BRANCH_dec19_function_unit[13:0] $1\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4875.5-4875.29" switch \initial - attribute \src "libresoc.v:4810.9-4810.17" + attribute \src "libresoc.v:4875.9-4875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 case - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000000000 + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000000000 end sync always - update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[11:0] + update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[13:0] end - attribute \src "libresoc.v:4825.3-4840.6" - process $proc$libresoc.v:4825$107 + attribute \src "libresoc.v:4890.3-4905.6" + process $proc$libresoc.v:4890$107 assign { } { } assign { } { } assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4826.5-4826.29" + attribute \src "libresoc.v:4891.5-4891.29" switch \initial - attribute \src "libresoc.v:4826.9-4826.17" + attribute \src "libresoc.v:4891.9-4891.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7043,18 +7108,18 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] end - attribute \src "libresoc.v:4841.3-4856.6" - process $proc$libresoc.v:4841$108 + attribute \src "libresoc.v:4906.3-4921.6" + process $proc$libresoc.v:4906$108 assign { } { } assign { } { } assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4842.5-4842.29" + attribute \src "libresoc.v:4907.5-4907.29" switch \initial - attribute \src "libresoc.v:4842.9-4842.17" + attribute \src "libresoc.v:4907.9-4907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7074,18 +7139,18 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] end - attribute \src "libresoc.v:4857.3-4872.6" - process $proc$libresoc.v:4857$109 + attribute \src "libresoc.v:4922.3-4937.6" + process $proc$libresoc.v:4922$109 assign { } { } assign { } { } assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4858.5-4858.29" + attribute \src "libresoc.v:4923.5-4923.29" switch \initial - attribute \src "libresoc.v:4858.9-4858.17" + attribute \src "libresoc.v:4923.9-4923.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7105,18 +7170,18 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] end - attribute \src "libresoc.v:4873.3-4888.6" - process $proc$libresoc.v:4873$110 + attribute \src "libresoc.v:4938.3-4953.6" + process $proc$libresoc.v:4938$110 assign { } { } assign { } { } assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4874.5-4874.29" + attribute \src "libresoc.v:4939.5-4939.29" switch \initial - attribute \src "libresoc.v:4874.9-4874.17" + attribute \src "libresoc.v:4939.9-4939.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7136,18 +7201,18 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] end - attribute \src "libresoc.v:4889.3-4904.6" - process $proc$libresoc.v:4889$111 + attribute \src "libresoc.v:4954.3-4969.6" + process $proc$libresoc.v:4954$111 assign { } { } assign { } { } assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4890.5-4890.29" + attribute \src "libresoc.v:4955.5-4955.29" switch \initial - attribute \src "libresoc.v:4890.9-4890.17" + attribute \src "libresoc.v:4955.9-4955.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7167,18 +7232,18 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] end - attribute \src "libresoc.v:4905.3-4920.6" - process $proc$libresoc.v:4905$112 + attribute \src "libresoc.v:4970.3-4985.6" + process $proc$libresoc.v:4970$112 assign { } { } assign { } { } assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4906.5-4906.29" + attribute \src "libresoc.v:4971.5-4971.29" switch \initial - attribute \src "libresoc.v:4906.9-4906.17" + attribute \src "libresoc.v:4971.9-4971.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7198,18 +7263,18 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] end - attribute \src "libresoc.v:4921.3-4936.6" - process $proc$libresoc.v:4921$113 + attribute \src "libresoc.v:4986.3-5001.6" + process $proc$libresoc.v:4986$113 assign { } { } assign { } { } assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4922.5-4922.29" + attribute \src "libresoc.v:4987.5-4987.29" switch \initial - attribute \src "libresoc.v:4922.9-4922.17" + attribute \src "libresoc.v:4987.9-4987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7231,32 +7296,32 @@ module \BRANCH_dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:4942.1-5239.10" +attribute \src "libresoc.v:5007.1-5309.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec19" attribute \generator "nMigen" module \CR_dec19 - attribute \src "libresoc.v:5136.3-5169.6" + attribute \src "libresoc.v:5206.3-5239.6" wire width 3 $0\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5170.3-5203.6" + attribute \src "libresoc.v:5240.3-5273.6" wire width 3 $0\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5068.3-5101.6" - wire width 12 $0\CR_dec19_function_unit[11:0] - attribute \src "libresoc.v:5102.3-5135.6" + attribute \src "libresoc.v:5138.3-5171.6" + wire width 14 $0\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5172.3-5205.6" wire width 7 $0\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5204.3-5237.6" + attribute \src "libresoc.v:5274.3-5307.6" wire width 2 $0\CR_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4943.7-4943.20" + attribute \src "libresoc.v:5008.7-5008.20" wire $0\initial[0:0] - attribute \src "libresoc.v:5136.3-5169.6" + attribute \src "libresoc.v:5206.3-5239.6" wire width 3 $1\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5170.3-5203.6" + attribute \src "libresoc.v:5240.3-5273.6" wire width 3 $1\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5068.3-5101.6" - wire width 12 $1\CR_dec19_function_unit[11:0] - attribute \src "libresoc.v:5102.3-5135.6" + attribute \src "libresoc.v:5138.3-5171.6" + wire width 14 $1\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5172.3-5205.6" wire width 7 $1\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5204.3-5237.6" + attribute \src "libresoc.v:5274.3-5307.6" wire width 2 $1\CR_dec19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7266,7 +7331,8 @@ module \CR_dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7274,23 +7340,26 @@ module \CR_dec19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -7365,95 +7434,96 @@ module \CR_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec19_rc_sel - attribute \src "libresoc.v:4943.7-4943.15" + attribute \src "libresoc.v:5008.7-5008.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:4943.7-4943.20" - process $proc$libresoc.v:4943$120 + attribute \src "libresoc.v:5008.7-5008.20" + process $proc$libresoc.v:5008$120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:5068.3-5101.6" - process $proc$libresoc.v:5068$115 + attribute \src "libresoc.v:5138.3-5171.6" + process $proc$libresoc.v:5138$115 assign { } { } assign { } { } - assign $0\CR_dec19_function_unit[11:0] $1\CR_dec19_function_unit[11:0] - attribute \src "libresoc.v:5069.5-5069.29" + assign $0\CR_dec19_function_unit[13:0] $1\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5139.5-5139.29" switch \initial - attribute \src "libresoc.v:5069.9-5069.17" + attribute \src "libresoc.v:5139.9-5139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec19_function_unit[11:0] 12'000000000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec19_function_unit $0\CR_dec19_function_unit[11:0] + update \CR_dec19_function_unit $0\CR_dec19_function_unit[13:0] end - attribute \src "libresoc.v:5102.3-5135.6" - process $proc$libresoc.v:5102$116 + attribute \src "libresoc.v:5172.3-5205.6" + process $proc$libresoc.v:5172$116 assign { } { } assign { } { } assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5103.5-5103.29" + attribute \src "libresoc.v:5173.5-5173.29" switch \initial - attribute \src "libresoc.v:5103.9-5103.17" + attribute \src "libresoc.v:5173.9-5173.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7497,18 +7567,18 @@ module \CR_dec19 sync always update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] end - attribute \src "libresoc.v:5136.3-5169.6" - process $proc$libresoc.v:5136$117 + attribute \src "libresoc.v:5206.3-5239.6" + process $proc$libresoc.v:5206$117 assign { } { } assign { } { } assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5137.5-5137.29" + attribute \src "libresoc.v:5207.5-5207.29" switch \initial - attribute \src "libresoc.v:5137.9-5137.17" + attribute \src "libresoc.v:5207.9-5207.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7552,18 +7622,18 @@ module \CR_dec19 sync always update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] end - attribute \src "libresoc.v:5170.3-5203.6" - process $proc$libresoc.v:5170$118 + attribute \src "libresoc.v:5240.3-5273.6" + process $proc$libresoc.v:5240$118 assign { } { } assign { } { } assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5171.5-5171.29" + attribute \src "libresoc.v:5241.5-5241.29" switch \initial - attribute \src "libresoc.v:5171.9-5171.17" + attribute \src "libresoc.v:5241.9-5241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7607,18 +7677,18 @@ module \CR_dec19 sync always update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] end - attribute \src "libresoc.v:5204.3-5237.6" - process $proc$libresoc.v:5204$119 + attribute \src "libresoc.v:5274.3-5307.6" + process $proc$libresoc.v:5274$119 assign { } { } assign { } { } assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] - attribute \src "libresoc.v:5205.5-5205.29" + attribute \src "libresoc.v:5275.5-5275.29" switch \initial - attribute \src "libresoc.v:5205.9-5205.17" + attribute \src "libresoc.v:5275.9-5275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7664,32 +7734,32 @@ module \CR_dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:5243.1-5972.10" +attribute \src "libresoc.v:5313.1-6067.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31" attribute \generator "nMigen" module \CR_dec31 - attribute \src "libresoc.v:5928.3-5946.6" + attribute \src "libresoc.v:6023.3-6041.6" wire width 3 $0\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:5947.3-5965.6" + attribute \src "libresoc.v:6042.3-6060.6" wire width 3 $0\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:5890.3-5908.6" - wire width 12 $0\CR_dec31_function_unit[11:0] - attribute \src "libresoc.v:5909.3-5927.6" + attribute \src "libresoc.v:5985.3-6003.6" + wire width 14 $0\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:6004.3-6022.6" wire width 7 $0\CR_dec31_internal_op[6:0] - attribute \src "libresoc.v:5871.3-5889.6" + attribute \src "libresoc.v:5966.3-5984.6" wire width 2 $0\CR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:5244.7-5244.20" + attribute \src "libresoc.v:5314.7-5314.20" wire $0\initial[0:0] - attribute \src "libresoc.v:5928.3-5946.6" + attribute \src "libresoc.v:6023.3-6041.6" wire width 3 $1\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:5947.3-5965.6" + attribute \src "libresoc.v:6042.3-6060.6" wire width 3 $1\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:5890.3-5908.6" - wire width 12 $1\CR_dec31_function_unit[11:0] - attribute \src "libresoc.v:5909.3-5927.6" + attribute \src "libresoc.v:5985.3-6003.6" + wire width 14 $1\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:6004.3-6022.6" wire width 7 $1\CR_dec31_internal_op[6:0] - attribute \src "libresoc.v:5871.3-5889.6" + attribute \src "libresoc.v:5966.3-5984.6" wire width 2 $1\CR_dec31_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7699,7 +7769,8 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7707,7 +7778,8 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7717,7 +7789,8 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7725,23 +7798,26 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -7816,15 +7892,16 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \CR_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7834,7 +7911,8 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7842,23 +7920,26 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -7933,15 +8014,16 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \CR_dec31_dec_sub15_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7951,7 +8033,8 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7959,23 +8042,26 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8050,15 +8136,16 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \CR_dec31_dec_sub16_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8068,7 +8155,8 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8076,23 +8164,26 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8167,31 +8258,34 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \CR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8266,24 +8360,25 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_rc_sel - attribute \src "libresoc.v:5244.7-5244.15" + attribute \src "libresoc.v:5314.7-5314.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:5839.21-5846.4" + attribute \src "libresoc.v:5934.21-5941.4" cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out @@ -8293,7 +8388,7 @@ module \CR_dec31 connect \opcode_in \CR_dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:5847.22-5854.4" + attribute \src "libresoc.v:5942.22-5949.4" cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out @@ -8303,7 +8398,7 @@ module \CR_dec31 connect \opcode_in \CR_dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:5855.22-5862.4" + attribute \src "libresoc.v:5950.22-5957.4" cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out @@ -8313,7 +8408,7 @@ module \CR_dec31 connect \opcode_in \CR_dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:5863.22-5870.4" + attribute \src "libresoc.v:5958.22-5965.4" cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out @@ -8322,26 +8417,26 @@ module \CR_dec31 connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel connect \opcode_in \CR_dec31_dec_sub19_opcode_in end - attribute \src "libresoc.v:5244.7-5244.20" - process $proc$libresoc.v:5244$126 + attribute \src "libresoc.v:5314.7-5314.20" + process $proc$libresoc.v:5314$126 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:5871.3-5889.6" - process $proc$libresoc.v:5871$121 + attribute \src "libresoc.v:5966.3-5984.6" + process $proc$libresoc.v:5966$121 assign { } { } assign { } { } assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:5872.5-5872.29" + attribute \src "libresoc.v:5967.5-5967.29" switch \initial - attribute \src "libresoc.v:5872.9-5872.17" + attribute \src "libresoc.v:5967.9-5967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8365,53 +8460,53 @@ module \CR_dec31 sync always update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:5890.3-5908.6" - process $proc$libresoc.v:5890$122 + attribute \src "libresoc.v:5985.3-6003.6" + process $proc$libresoc.v:5985$122 assign { } { } assign { } { } - assign $0\CR_dec31_function_unit[11:0] $1\CR_dec31_function_unit[11:0] - attribute \src "libresoc.v:5891.5-5891.29" + assign $0\CR_dec31_function_unit[13:0] $1\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:5986.5-5986.29" switch \initial - attribute \src "libresoc.v:5891.9-5891.17" + attribute \src "libresoc.v:5986.9-5986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit case - assign $1\CR_dec31_function_unit[11:0] 12'000000000000 + assign $1\CR_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_function_unit $0\CR_dec31_function_unit[11:0] + update \CR_dec31_function_unit $0\CR_dec31_function_unit[13:0] end - attribute \src "libresoc.v:5909.3-5927.6" - process $proc$libresoc.v:5909$123 + attribute \src "libresoc.v:6004.3-6022.6" + process $proc$libresoc.v:6004$123 assign { } { } assign { } { } assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] - attribute \src "libresoc.v:5910.5-5910.29" + attribute \src "libresoc.v:6005.5-6005.29" switch \initial - attribute \src "libresoc.v:5910.9-5910.17" + attribute \src "libresoc.v:6005.9-6005.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8435,18 +8530,18 @@ module \CR_dec31 sync always update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] end - attribute \src "libresoc.v:5928.3-5946.6" - process $proc$libresoc.v:5928$124 + attribute \src "libresoc.v:6023.3-6041.6" + process $proc$libresoc.v:6023$124 assign { } { } assign { } { } assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:5929.5-5929.29" + attribute \src "libresoc.v:6024.5-6024.29" switch \initial - attribute \src "libresoc.v:5929.9-5929.17" + attribute \src "libresoc.v:6024.9-6024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8470,18 +8565,18 @@ module \CR_dec31 sync always update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] end - attribute \src "libresoc.v:5947.3-5965.6" - process $proc$libresoc.v:5947$125 + attribute \src "libresoc.v:6042.3-6060.6" + process $proc$libresoc.v:6042$125 assign { } { } assign { } { } assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:5948.5-5948.29" + attribute \src "libresoc.v:6043.5-6043.29" switch \initial - attribute \src "libresoc.v:5948.9-5948.17" + attribute \src "libresoc.v:6043.9-6043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8512,32 +8607,32 @@ module \CR_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:5976.1-6153.10" +attribute \src "libresoc.v:6071.1-6253.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" attribute \generator "nMigen" module \CR_dec31_dec_sub0 - attribute \src "libresoc.v:6122.3-6131.6" + attribute \src "libresoc.v:6222.3-6231.6" wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6132.3-6141.6" + attribute \src "libresoc.v:6232.3-6241.6" wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6102.3-6111.6" - wire width 12 $0\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:6112.3-6121.6" + attribute \src "libresoc.v:6202.3-6211.6" + wire width 14 $0\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6212.3-6221.6" wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:6142.3-6151.6" + attribute \src "libresoc.v:6242.3-6251.6" wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:5977.7-5977.20" + attribute \src "libresoc.v:6072.7-6072.20" wire $0\initial[0:0] - attribute \src "libresoc.v:6122.3-6131.6" + attribute \src "libresoc.v:6222.3-6231.6" wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6132.3-6141.6" + attribute \src "libresoc.v:6232.3-6241.6" wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6102.3-6111.6" - wire width 12 $1\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:6112.3-6121.6" + attribute \src "libresoc.v:6202.3-6211.6" + wire width 14 $1\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6212.3-6221.6" wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:6142.3-6151.6" + attribute \src "libresoc.v:6242.3-6251.6" wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8547,7 +8642,8 @@ module \CR_dec31_dec_sub0 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8555,23 +8651,26 @@ module \CR_dec31_dec_sub0 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8646,63 +8745,64 @@ module \CR_dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel - attribute \src "libresoc.v:5977.7-5977.15" + attribute \src "libresoc.v:6072.7-6072.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:5977.7-5977.20" - process $proc$libresoc.v:5977$132 + attribute \src "libresoc.v:6072.7-6072.20" + process $proc$libresoc.v:6072$132 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:6102.3-6111.6" - process $proc$libresoc.v:6102$127 + attribute \src "libresoc.v:6202.3-6211.6" + process $proc$libresoc.v:6202$127 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub0_function_unit[11:0] $1\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:6103.5-6103.29" + assign $0\CR_dec31_dec_sub0_function_unit[13:0] $1\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6203.5-6203.29" switch \initial - attribute \src "libresoc.v:6103.9-6103.17" + attribute \src "libresoc.v:6203.9-6203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub0_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + assign $1\CR_dec31_dec_sub0_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[11:0] + update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:6112.3-6121.6" - process $proc$libresoc.v:6112$128 + attribute \src "libresoc.v:6212.3-6221.6" + process $proc$libresoc.v:6212$128 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:6113.5-6113.29" + attribute \src "libresoc.v:6213.5-6213.29" switch \initial - attribute \src "libresoc.v:6113.9-6113.17" + attribute \src "libresoc.v:6213.9-6213.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8714,18 +8814,18 @@ module \CR_dec31_dec_sub0 sync always update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:6122.3-6131.6" - process $proc$libresoc.v:6122$129 + attribute \src "libresoc.v:6222.3-6231.6" + process $proc$libresoc.v:6222$129 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6123.5-6123.29" + attribute \src "libresoc.v:6223.5-6223.29" switch \initial - attribute \src "libresoc.v:6123.9-6123.17" + attribute \src "libresoc.v:6223.9-6223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8737,18 +8837,18 @@ module \CR_dec31_dec_sub0 sync always update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:6132.3-6141.6" - process $proc$libresoc.v:6132$130 + attribute \src "libresoc.v:6232.3-6241.6" + process $proc$libresoc.v:6232$130 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6133.5-6133.29" + attribute \src "libresoc.v:6233.5-6233.29" switch \initial - attribute \src "libresoc.v:6133.9-6133.17" + attribute \src "libresoc.v:6233.9-6233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8760,18 +8860,18 @@ module \CR_dec31_dec_sub0 sync always update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:6142.3-6151.6" - process $proc$libresoc.v:6142$131 + attribute \src "libresoc.v:6242.3-6251.6" + process $proc$libresoc.v:6242$131 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:6143.5-6143.29" + attribute \src "libresoc.v:6243.5-6243.29" switch \initial - attribute \src "libresoc.v:6143.9-6143.17" + attribute \src "libresoc.v:6243.9-6243.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8785,32 +8885,32 @@ module \CR_dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:6157.1-6799.10" +attribute \src "libresoc.v:6257.1-6904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" attribute \generator "nMigen" module \CR_dec31_dec_sub15 - attribute \src "libresoc.v:6489.3-6591.6" + attribute \src "libresoc.v:6594.3-6696.6" wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6592.3-6694.6" + attribute \src "libresoc.v:6697.3-6799.6" wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6283.3-6385.6" - wire width 12 $0\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:6386.3-6488.6" + attribute \src "libresoc.v:6388.3-6490.6" + wire width 14 $0\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6491.3-6593.6" wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6695.3-6797.6" + attribute \src "libresoc.v:6800.3-6902.6" wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:6158.7-6158.20" + attribute \src "libresoc.v:6258.7-6258.20" wire $0\initial[0:0] - attribute \src "libresoc.v:6489.3-6591.6" + attribute \src "libresoc.v:6594.3-6696.6" wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6592.3-6694.6" + attribute \src "libresoc.v:6697.3-6799.6" wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6283.3-6385.6" - wire width 12 $1\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:6386.3-6488.6" + attribute \src "libresoc.v:6388.3-6490.6" + wire width 14 $1\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6491.3-6593.6" wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6695.3-6797.6" + attribute \src "libresoc.v:6800.3-6902.6" wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8820,7 +8920,8 @@ module \CR_dec31_dec_sub15 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8828,23 +8929,26 @@ module \CR_dec31_dec_sub15 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_dec_sub15_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8919,187 +9023,188 @@ module \CR_dec31_dec_sub15 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel - attribute \src "libresoc.v:6158.7-6158.15" + attribute \src "libresoc.v:6258.7-6258.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:6158.7-6158.20" - process $proc$libresoc.v:6158$138 + attribute \src "libresoc.v:6258.7-6258.20" + process $proc$libresoc.v:6258$138 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:6283.3-6385.6" - process $proc$libresoc.v:6283$133 + attribute \src "libresoc.v:6388.3-6490.6" + process $proc$libresoc.v:6388$133 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub15_function_unit[11:0] $1\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:6284.5-6284.29" + assign $0\CR_dec31_dec_sub15_function_unit[13:0] $1\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6389.5-6389.29" switch \initial - attribute \src "libresoc.v:6284.9-6284.17" + attribute \src "libresoc.v:6389.9-6389.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000000000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[11:0] + update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:6386.3-6488.6" - process $proc$libresoc.v:6386$134 + attribute \src "libresoc.v:6491.3-6593.6" + process $proc$libresoc.v:6491$134 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6387.5-6387.29" + attribute \src "libresoc.v:6492.5-6492.29" switch \initial - attribute \src "libresoc.v:6387.9-6387.17" + attribute \src "libresoc.v:6492.9-6492.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9235,18 +9340,18 @@ module \CR_dec31_dec_sub15 sync always update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:6489.3-6591.6" - process $proc$libresoc.v:6489$135 + attribute \src "libresoc.v:6594.3-6696.6" + process $proc$libresoc.v:6594$135 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6490.5-6490.29" + attribute \src "libresoc.v:6595.5-6595.29" switch \initial - attribute \src "libresoc.v:6490.9-6490.17" + attribute \src "libresoc.v:6595.9-6595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9382,18 +9487,18 @@ module \CR_dec31_dec_sub15 sync always update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:6592.3-6694.6" - process $proc$libresoc.v:6592$136 + attribute \src "libresoc.v:6697.3-6799.6" + process $proc$libresoc.v:6697$136 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6593.5-6593.29" + attribute \src "libresoc.v:6698.5-6698.29" switch \initial - attribute \src "libresoc.v:6593.9-6593.17" + attribute \src "libresoc.v:6698.9-6698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9529,18 +9634,18 @@ module \CR_dec31_dec_sub15 sync always update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:6695.3-6797.6" - process $proc$libresoc.v:6695$137 + attribute \src "libresoc.v:6800.3-6902.6" + process $proc$libresoc.v:6800$137 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:6696.5-6696.29" + attribute \src "libresoc.v:6801.5-6801.29" switch \initial - attribute \src "libresoc.v:6696.9-6696.17" + attribute \src "libresoc.v:6801.9-6801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9678,32 +9783,32 @@ module \CR_dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:6803.1-6980.10" +attribute \src "libresoc.v:6908.1-7090.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" attribute \generator "nMigen" module \CR_dec31_dec_sub16 - attribute \src "libresoc.v:6949.3-6958.6" + attribute \src "libresoc.v:7059.3-7068.6" wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:6959.3-6968.6" + attribute \src "libresoc.v:7069.3-7078.6" wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:6929.3-6938.6" - wire width 12 $0\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:6939.3-6948.6" + attribute \src "libresoc.v:7039.3-7048.6" + wire width 14 $0\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7049.3-7058.6" wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:6969.3-6978.6" + attribute \src "libresoc.v:7079.3-7088.6" wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:6804.7-6804.20" + attribute \src "libresoc.v:6909.7-6909.20" wire $0\initial[0:0] - attribute \src "libresoc.v:6949.3-6958.6" + attribute \src "libresoc.v:7059.3-7068.6" wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:6959.3-6968.6" + attribute \src "libresoc.v:7069.3-7078.6" wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:6929.3-6938.6" - wire width 12 $1\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:6939.3-6948.6" + attribute \src "libresoc.v:7039.3-7048.6" + wire width 14 $1\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7049.3-7058.6" wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:6969.3-6978.6" + attribute \src "libresoc.v:7079.3-7088.6" wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -9713,7 +9818,8 @@ module \CR_dec31_dec_sub16 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -9721,23 +9827,26 @@ module \CR_dec31_dec_sub16 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_dec_sub16_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -9812,63 +9921,64 @@ module \CR_dec31_dec_sub16 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel - attribute \src "libresoc.v:6804.7-6804.15" + attribute \src "libresoc.v:6909.7-6909.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:6804.7-6804.20" - process $proc$libresoc.v:6804$144 + attribute \src "libresoc.v:6909.7-6909.20" + process $proc$libresoc.v:6909$144 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:6929.3-6938.6" - process $proc$libresoc.v:6929$139 + attribute \src "libresoc.v:7039.3-7048.6" + process $proc$libresoc.v:7039$139 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub16_function_unit[11:0] $1\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:6930.5-6930.29" + assign $0\CR_dec31_dec_sub16_function_unit[13:0] $1\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7040.5-7040.29" switch \initial - attribute \src "libresoc.v:6930.9-6930.17" + attribute \src "libresoc.v:7040.9-7040.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub16_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000000000000 + assign $1\CR_dec31_dec_sub16_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[11:0] + update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:6939.3-6948.6" - process $proc$libresoc.v:6939$140 + attribute \src "libresoc.v:7049.3-7058.6" + process $proc$libresoc.v:7049$140 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:6940.5-6940.29" + attribute \src "libresoc.v:7050.5-7050.29" switch \initial - attribute \src "libresoc.v:6940.9-6940.17" + attribute \src "libresoc.v:7050.9-7050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9880,18 +9990,18 @@ module \CR_dec31_dec_sub16 sync always update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:6949.3-6958.6" - process $proc$libresoc.v:6949$141 + attribute \src "libresoc.v:7059.3-7068.6" + process $proc$libresoc.v:7059$141 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:6950.5-6950.29" + attribute \src "libresoc.v:7060.5-7060.29" switch \initial - attribute \src "libresoc.v:6950.9-6950.17" + attribute \src "libresoc.v:7060.9-7060.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9903,18 +10013,18 @@ module \CR_dec31_dec_sub16 sync always update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:6959.3-6968.6" - process $proc$libresoc.v:6959$142 + attribute \src "libresoc.v:7069.3-7078.6" + process $proc$libresoc.v:7069$142 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:6960.5-6960.29" + attribute \src "libresoc.v:7070.5-7070.29" switch \initial - attribute \src "libresoc.v:6960.9-6960.17" + attribute \src "libresoc.v:7070.9-7070.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9926,18 +10036,18 @@ module \CR_dec31_dec_sub16 sync always update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:6969.3-6978.6" - process $proc$libresoc.v:6969$143 + attribute \src "libresoc.v:7079.3-7088.6" + process $proc$libresoc.v:7079$143 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:6970.5-6970.29" + attribute \src "libresoc.v:7080.5-7080.29" switch \initial - attribute \src "libresoc.v:6970.9-6970.17" + attribute \src "libresoc.v:7080.9-7080.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9951,32 +10061,32 @@ module \CR_dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:6984.1-7161.10" +attribute \src "libresoc.v:7094.1-7276.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" attribute \generator "nMigen" module \CR_dec31_dec_sub19 - attribute \src "libresoc.v:7130.3-7139.6" + attribute \src "libresoc.v:7245.3-7254.6" wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7140.3-7149.6" + attribute \src "libresoc.v:7255.3-7264.6" wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7110.3-7119.6" - wire width 12 $0\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:7120.3-7129.6" + attribute \src "libresoc.v:7225.3-7234.6" + wire width 14 $0\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7235.3-7244.6" wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7150.3-7159.6" + attribute \src "libresoc.v:7265.3-7274.6" wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:6985.7-6985.20" + attribute \src "libresoc.v:7095.7-7095.20" wire $0\initial[0:0] - attribute \src "libresoc.v:7130.3-7139.6" + attribute \src "libresoc.v:7245.3-7254.6" wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7140.3-7149.6" + attribute \src "libresoc.v:7255.3-7264.6" wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7110.3-7119.6" - wire width 12 $1\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:7120.3-7129.6" + attribute \src "libresoc.v:7225.3-7234.6" + wire width 14 $1\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7235.3-7244.6" wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7150.3-7159.6" + attribute \src "libresoc.v:7265.3-7274.6" wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -9986,7 +10096,8 @@ module \CR_dec31_dec_sub19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -9994,23 +10105,26 @@ module \CR_dec31_dec_sub19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -10085,63 +10199,64 @@ module \CR_dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:6985.7-6985.15" + attribute \src "libresoc.v:7095.7-7095.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:6985.7-6985.20" - process $proc$libresoc.v:6985$150 + attribute \src "libresoc.v:7095.7-7095.20" + process $proc$libresoc.v:7095$150 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:7110.3-7119.6" - process $proc$libresoc.v:7110$145 + attribute \src "libresoc.v:7225.3-7234.6" + process $proc$libresoc.v:7225$145 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub19_function_unit[11:0] $1\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:7111.5-7111.29" + assign $0\CR_dec31_dec_sub19_function_unit[13:0] $1\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7226.5-7226.29" switch \initial - attribute \src "libresoc.v:7111.9-7111.17" + attribute \src "libresoc.v:7226.9-7226.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000001000000 + assign $1\CR_dec31_dec_sub19_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + assign $1\CR_dec31_dec_sub19_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[11:0] + update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:7120.3-7129.6" - process $proc$libresoc.v:7120$146 + attribute \src "libresoc.v:7235.3-7244.6" + process $proc$libresoc.v:7235$146 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7121.5-7121.29" + attribute \src "libresoc.v:7236.5-7236.29" switch \initial - attribute \src "libresoc.v:7121.9-7121.17" + attribute \src "libresoc.v:7236.9-7236.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10153,18 +10268,18 @@ module \CR_dec31_dec_sub19 sync always update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:7130.3-7139.6" - process $proc$libresoc.v:7130$147 + attribute \src "libresoc.v:7245.3-7254.6" + process $proc$libresoc.v:7245$147 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7131.5-7131.29" + attribute \src "libresoc.v:7246.5-7246.29" switch \initial - attribute \src "libresoc.v:7131.9-7131.17" + attribute \src "libresoc.v:7246.9-7246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10176,18 +10291,18 @@ module \CR_dec31_dec_sub19 sync always update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:7140.3-7149.6" - process $proc$libresoc.v:7140$148 + attribute \src "libresoc.v:7255.3-7264.6" + process $proc$libresoc.v:7255$148 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7141.5-7141.29" + attribute \src "libresoc.v:7256.5-7256.29" switch \initial - attribute \src "libresoc.v:7141.9-7141.17" + attribute \src "libresoc.v:7256.9-7256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10199,18 +10314,18 @@ module \CR_dec31_dec_sub19 sync always update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:7150.3-7159.6" - process $proc$libresoc.v:7150$149 + attribute \src "libresoc.v:7265.3-7274.6" + process $proc$libresoc.v:7265$149 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:7151.5-7151.29" + attribute \src "libresoc.v:7266.5-7266.29" switch \initial - attribute \src "libresoc.v:7151.9-7151.17" + attribute \src "libresoc.v:7266.9-7266.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10224,68 +10339,68 @@ module \CR_dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:7165.1-7903.10" +attribute \src "libresoc.v:7280.1-8033.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" attribute \generator "nMigen" module \DIV_dec31 - attribute \src "libresoc.v:7873.3-7885.6" + attribute \src "libresoc.v:8003.3-8015.6" wire width 3 $0\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7886.3-7898.6" + attribute \src "libresoc.v:8016.3-8028.6" wire width 3 $0\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7743.3-7755.6" + attribute \src "libresoc.v:7873.3-7885.6" wire width 2 $0\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7782.3-7794.6" + attribute \src "libresoc.v:7912.3-7924.6" wire $0\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7821.3-7833.6" - wire width 12 $0\DIV_dec31_function_unit[11:0] - attribute \src "libresoc.v:7847.3-7859.6" + attribute \src "libresoc.v:7951.3-7963.6" + wire width 14 $0\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7977.3-7989.6" wire width 3 $0\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7860.3-7872.6" + attribute \src "libresoc.v:7990.3-8002.6" wire width 4 $0\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7834.3-7846.6" + attribute \src "libresoc.v:7964.3-7976.6" wire width 7 $0\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7756.3-7768.6" + attribute \src "libresoc.v:7886.3-7898.6" wire $0\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7769.3-7781.6" + attribute \src "libresoc.v:7899.3-7911.6" wire $0\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7795.3-7807.6" + attribute \src "libresoc.v:7925.3-7937.6" wire $0\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7717.3-7729.6" + attribute \src "libresoc.v:7847.3-7859.6" wire width 4 $0\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7730.3-7742.6" + attribute \src "libresoc.v:7860.3-7872.6" wire width 2 $0\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7808.3-7820.6" + attribute \src "libresoc.v:7938.3-7950.6" wire $0\DIV_dec31_sgn[0:0] - attribute \src "libresoc.v:7166.7-7166.20" + attribute \src "libresoc.v:7281.7-7281.20" wire $0\initial[0:0] - attribute \src "libresoc.v:7873.3-7885.6" + attribute \src "libresoc.v:8003.3-8015.6" wire width 3 $1\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7886.3-7898.6" + attribute \src "libresoc.v:8016.3-8028.6" wire width 3 $1\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7743.3-7755.6" + attribute \src "libresoc.v:7873.3-7885.6" wire width 2 $1\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7782.3-7794.6" + attribute \src "libresoc.v:7912.3-7924.6" wire $1\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7821.3-7833.6" - wire width 12 $1\DIV_dec31_function_unit[11:0] - attribute \src "libresoc.v:7847.3-7859.6" + attribute \src "libresoc.v:7951.3-7963.6" + wire width 14 $1\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7977.3-7989.6" wire width 3 $1\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7860.3-7872.6" + attribute \src "libresoc.v:7990.3-8002.6" wire width 4 $1\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7834.3-7846.6" + attribute \src "libresoc.v:7964.3-7976.6" wire width 7 $1\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7756.3-7768.6" + attribute \src "libresoc.v:7886.3-7898.6" wire $1\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7769.3-7781.6" + attribute \src "libresoc.v:7899.3-7911.6" wire $1\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7795.3-7807.6" + attribute \src "libresoc.v:7925.3-7937.6" wire $1\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7717.3-7729.6" + attribute \src "libresoc.v:7847.3-7859.6" wire width 4 $1\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7730.3-7742.6" + attribute \src "libresoc.v:7860.3-7872.6" wire width 2 $1\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7808.3-7820.6" + attribute \src "libresoc.v:7938.3-7950.6" wire $1\DIV_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10295,7 +10410,8 @@ module \DIV_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10303,15 +10419,16 @@ module \DIV_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \DIV_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10321,7 +10438,8 @@ module \DIV_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10329,38 +10447,41 @@ module \DIV_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10377,7 +10498,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10453,13 +10574,14 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10467,17 +10589,17 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \DIV_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10487,7 +10609,8 @@ module \DIV_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10495,38 +10618,41 @@ module \DIV_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10543,7 +10669,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10619,13 +10745,14 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10633,40 +10760,42 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \DIV_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \DIV_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10683,7 +10812,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10759,13 +10888,14 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10773,26 +10903,26 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \DIV_dec31_sgn - attribute \src "libresoc.v:7166.7-7166.15" + attribute \src "libresoc.v:7281.7-7281.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:7683.23-7699.4" + attribute \src "libresoc.v:7813.23-7829.4" cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out @@ -10811,7 +10941,7 @@ module \DIV_dec31 connect \opcode_in \DIV_dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:7700.22-7716.4" + attribute \src "libresoc.v:7830.22-7846.4" cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out @@ -10829,26 +10959,26 @@ module \DIV_dec31 connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn connect \opcode_in \DIV_dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:7166.7-7166.20" - process $proc$libresoc.v:7166$165 + attribute \src "libresoc.v:7281.7-7281.20" + process $proc$libresoc.v:7281$165 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:7717.3-7729.6" - process $proc$libresoc.v:7717$151 + attribute \src "libresoc.v:7847.3-7859.6" + process $proc$libresoc.v:7847$151 assign { } { } assign { } { } assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7718.5-7718.29" + attribute \src "libresoc.v:7848.5-7848.29" switch \initial - attribute \src "libresoc.v:7718.9-7718.17" + attribute \src "libresoc.v:7848.9-7848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10864,18 +10994,18 @@ module \DIV_dec31 sync always update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] end - attribute \src "libresoc.v:7730.3-7742.6" - process $proc$libresoc.v:7730$152 + attribute \src "libresoc.v:7860.3-7872.6" + process $proc$libresoc.v:7860$152 assign { } { } assign { } { } assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7731.5-7731.29" + attribute \src "libresoc.v:7861.5-7861.29" switch \initial - attribute \src "libresoc.v:7731.9-7731.17" + attribute \src "libresoc.v:7861.9-7861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10891,18 +11021,18 @@ module \DIV_dec31 sync always update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:7743.3-7755.6" - process $proc$libresoc.v:7743$153 + attribute \src "libresoc.v:7873.3-7885.6" + process $proc$libresoc.v:7873$153 assign { } { } assign { } { } assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7744.5-7744.29" + attribute \src "libresoc.v:7874.5-7874.29" switch \initial - attribute \src "libresoc.v:7744.9-7744.17" + attribute \src "libresoc.v:7874.9-7874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10918,18 +11048,18 @@ module \DIV_dec31 sync always update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] end - attribute \src "libresoc.v:7756.3-7768.6" - process $proc$libresoc.v:7756$154 + attribute \src "libresoc.v:7886.3-7898.6" + process $proc$libresoc.v:7886$154 assign { } { } assign { } { } assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7757.5-7757.29" + attribute \src "libresoc.v:7887.5-7887.29" switch \initial - attribute \src "libresoc.v:7757.9-7757.17" + attribute \src "libresoc.v:7887.9-7887.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10945,18 +11075,18 @@ module \DIV_dec31 sync always update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] end - attribute \src "libresoc.v:7769.3-7781.6" - process $proc$libresoc.v:7769$155 + attribute \src "libresoc.v:7899.3-7911.6" + process $proc$libresoc.v:7899$155 assign { } { } assign { } { } assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7770.5-7770.29" + attribute \src "libresoc.v:7900.5-7900.29" switch \initial - attribute \src "libresoc.v:7770.9-7770.17" + attribute \src "libresoc.v:7900.9-7900.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10972,18 +11102,18 @@ module \DIV_dec31 sync always update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] end - attribute \src "libresoc.v:7782.3-7794.6" - process $proc$libresoc.v:7782$156 + attribute \src "libresoc.v:7912.3-7924.6" + process $proc$libresoc.v:7912$156 assign { } { } assign { } { } assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7783.5-7783.29" + attribute \src "libresoc.v:7913.5-7913.29" switch \initial - attribute \src "libresoc.v:7783.9-7783.17" + attribute \src "libresoc.v:7913.9-7913.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10999,18 +11129,18 @@ module \DIV_dec31 sync always update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] end - attribute \src "libresoc.v:7795.3-7807.6" - process $proc$libresoc.v:7795$157 + attribute \src "libresoc.v:7925.3-7937.6" + process $proc$libresoc.v:7925$157 assign { } { } assign { } { } assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7796.5-7796.29" + attribute \src "libresoc.v:7926.5-7926.29" switch \initial - attribute \src "libresoc.v:7796.9-7796.17" + attribute \src "libresoc.v:7926.9-7926.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11026,18 +11156,18 @@ module \DIV_dec31 sync always update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] end - attribute \src "libresoc.v:7808.3-7820.6" - process $proc$libresoc.v:7808$158 + attribute \src "libresoc.v:7938.3-7950.6" + process $proc$libresoc.v:7938$158 assign { } { } assign { } { } assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] - attribute \src "libresoc.v:7809.5-7809.29" + attribute \src "libresoc.v:7939.5-7939.29" switch \initial - attribute \src "libresoc.v:7809.9-7809.17" + attribute \src "libresoc.v:7939.9-7939.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11053,45 +11183,45 @@ module \DIV_dec31 sync always update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] end - attribute \src "libresoc.v:7821.3-7833.6" - process $proc$libresoc.v:7821$159 + attribute \src "libresoc.v:7951.3-7963.6" + process $proc$libresoc.v:7951$159 assign { } { } assign { } { } - assign $0\DIV_dec31_function_unit[11:0] $1\DIV_dec31_function_unit[11:0] - attribute \src "libresoc.v:7822.5-7822.29" + assign $0\DIV_dec31_function_unit[13:0] $1\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7952.5-7952.29" switch \initial - attribute \src "libresoc.v:7822.9-7822.17" + attribute \src "libresoc.v:7952.9-7952.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + assign $1\DIV_dec31_function_unit[13:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + assign $1\DIV_dec31_function_unit[13:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit case - assign $1\DIV_dec31_function_unit[11:0] 12'000000000000 + assign $1\DIV_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[11:0] + update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[13:0] end - attribute \src "libresoc.v:7834.3-7846.6" - process $proc$libresoc.v:7834$160 + attribute \src "libresoc.v:7964.3-7976.6" + process $proc$libresoc.v:7964$160 assign { } { } assign { } { } assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7835.5-7835.29" + attribute \src "libresoc.v:7965.5-7965.29" switch \initial - attribute \src "libresoc.v:7835.9-7835.17" + attribute \src "libresoc.v:7965.9-7965.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11107,18 +11237,18 @@ module \DIV_dec31 sync always update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] end - attribute \src "libresoc.v:7847.3-7859.6" - process $proc$libresoc.v:7847$161 + attribute \src "libresoc.v:7977.3-7989.6" + process $proc$libresoc.v:7977$161 assign { } { } assign { } { } assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7848.5-7848.29" + attribute \src "libresoc.v:7978.5-7978.29" switch \initial - attribute \src "libresoc.v:7848.9-7848.17" + attribute \src "libresoc.v:7978.9-7978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11134,18 +11264,18 @@ module \DIV_dec31 sync always update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] end - attribute \src "libresoc.v:7860.3-7872.6" - process $proc$libresoc.v:7860$162 + attribute \src "libresoc.v:7990.3-8002.6" + process $proc$libresoc.v:7990$162 assign { } { } assign { } { } assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7861.5-7861.29" + attribute \src "libresoc.v:7991.5-7991.29" switch \initial - attribute \src "libresoc.v:7861.9-7861.17" + attribute \src "libresoc.v:7991.9-7991.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11161,18 +11291,18 @@ module \DIV_dec31 sync always update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:7873.3-7885.6" - process $proc$libresoc.v:7873$163 + attribute \src "libresoc.v:8003.3-8015.6" + process $proc$libresoc.v:8003$163 assign { } { } assign { } { } assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7874.5-7874.29" + attribute \src "libresoc.v:8004.5-8004.29" switch \initial - attribute \src "libresoc.v:7874.9-7874.17" + attribute \src "libresoc.v:8004.9-8004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11188,18 +11318,18 @@ module \DIV_dec31 sync always update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] end - attribute \src "libresoc.v:7886.3-7898.6" - process $proc$libresoc.v:7886$164 + attribute \src "libresoc.v:8016.3-8028.6" + process $proc$libresoc.v:8016$164 assign { } { } assign { } { } assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7887.5-7887.29" + attribute \src "libresoc.v:8017.5-8017.29" switch \initial - attribute \src "libresoc.v:7887.9-7887.17" + attribute \src "libresoc.v:8017.9-8017.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11220,68 +11350,68 @@ module \DIV_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:7907.1-8610.10" +attribute \src "libresoc.v:8037.1-8745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" attribute \generator "nMigen" module \DIV_dec31_dec_sub11 - attribute \src "libresoc.v:8424.3-8460.6" + attribute \src "libresoc.v:8559.3-8595.6" wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8461.3-8497.6" + attribute \src "libresoc.v:8596.3-8632.6" wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8572.3-8608.6" + attribute \src "libresoc.v:8707.3-8743.6" wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8202.3-8238.6" + attribute \src "libresoc.v:8337.3-8373.6" wire $0\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8091.3-8127.6" - wire width 12 $0\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:8350.3-8386.6" + attribute \src "libresoc.v:8226.3-8262.6" + wire width 14 $0\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8485.3-8521.6" wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8387.3-8423.6" + attribute \src "libresoc.v:8522.3-8558.6" wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8313.3-8349.6" + attribute \src "libresoc.v:8448.3-8484.6" wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8128.3-8164.6" + attribute \src "libresoc.v:8263.3-8299.6" wire $0\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8165.3-8201.6" + attribute \src "libresoc.v:8300.3-8336.6" wire $0\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8239.3-8275.6" + attribute \src "libresoc.v:8374.3-8410.6" wire $0\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8498.3-8534.6" + attribute \src "libresoc.v:8633.3-8669.6" wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8535.3-8571.6" + attribute \src "libresoc.v:8670.3-8706.6" wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8276.3-8312.6" + attribute \src "libresoc.v:8411.3-8447.6" wire $0\DIV_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:7908.7-7908.20" + attribute \src "libresoc.v:8038.7-8038.20" wire $0\initial[0:0] - attribute \src "libresoc.v:8424.3-8460.6" + attribute \src "libresoc.v:8559.3-8595.6" wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8461.3-8497.6" + attribute \src "libresoc.v:8596.3-8632.6" wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8572.3-8608.6" + attribute \src "libresoc.v:8707.3-8743.6" wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8202.3-8238.6" + attribute \src "libresoc.v:8337.3-8373.6" wire $1\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8091.3-8127.6" - wire width 12 $1\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:8350.3-8386.6" + attribute \src "libresoc.v:8226.3-8262.6" + wire width 14 $1\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8485.3-8521.6" wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8387.3-8423.6" + attribute \src "libresoc.v:8522.3-8558.6" wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8313.3-8349.6" + attribute \src "libresoc.v:8448.3-8484.6" wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8128.3-8164.6" + attribute \src "libresoc.v:8263.3-8299.6" wire $1\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8165.3-8201.6" + attribute \src "libresoc.v:8300.3-8336.6" wire $1\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8239.3-8275.6" + attribute \src "libresoc.v:8374.3-8410.6" wire $1\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8498.3-8534.6" + attribute \src "libresoc.v:8633.3-8669.6" wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8535.3-8571.6" + attribute \src "libresoc.v:8670.3-8706.6" wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8276.3-8312.6" + attribute \src "libresoc.v:8411.3-8447.6" wire $1\DIV_dec31_dec_sub11_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -11291,7 +11421,8 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -11299,38 +11430,41 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \DIV_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -11347,7 +11481,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -11423,13 +11557,14 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -11437,101 +11572,101 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \DIV_dec31_dec_sub11_sgn - attribute \src "libresoc.v:7908.7-7908.15" + attribute \src "libresoc.v:8038.7-8038.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:7908.7-7908.20" - process $proc$libresoc.v:7908$180 + attribute \src "libresoc.v:8038.7-8038.20" + process $proc$libresoc.v:8038$180 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:8091.3-8127.6" - process $proc$libresoc.v:8091$166 + attribute \src "libresoc.v:8226.3-8262.6" + process $proc$libresoc.v:8226$166 assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub11_function_unit[11:0] $1\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:8092.5-8092.29" + assign $0\DIV_dec31_dec_sub11_function_unit[13:0] $1\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8227.5-8227.29" switch \initial - attribute \src "libresoc.v:8092.9-8092.17" + attribute \src "libresoc.v:8227.9-8227.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 case - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'000000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always - update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[11:0] + update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:8128.3-8164.6" - process $proc$libresoc.v:8128$167 + attribute \src "libresoc.v:8263.3-8299.6" + process $proc$libresoc.v:8263$167 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8129.5-8129.29" + attribute \src "libresoc.v:8264.5-8264.29" switch \initial - attribute \src "libresoc.v:8129.9-8129.17" + attribute \src "libresoc.v:8264.9-8264.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11579,18 +11714,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:8165.3-8201.6" - process $proc$libresoc.v:8165$168 + attribute \src "libresoc.v:8300.3-8336.6" + process $proc$libresoc.v:8300$168 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8166.5-8166.29" + attribute \src "libresoc.v:8301.5-8301.29" switch \initial - attribute \src "libresoc.v:8166.9-8166.17" + attribute \src "libresoc.v:8301.9-8301.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11638,18 +11773,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:8202.3-8238.6" - process $proc$libresoc.v:8202$169 + attribute \src "libresoc.v:8337.3-8373.6" + process $proc$libresoc.v:8337$169 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8203.5-8203.29" + attribute \src "libresoc.v:8338.5-8338.29" switch \initial - attribute \src "libresoc.v:8203.9-8203.17" + attribute \src "libresoc.v:8338.9-8338.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11697,18 +11832,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:8239.3-8275.6" - process $proc$libresoc.v:8239$170 + attribute \src "libresoc.v:8374.3-8410.6" + process $proc$libresoc.v:8374$170 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8240.5-8240.29" + attribute \src "libresoc.v:8375.5-8375.29" switch \initial - attribute \src "libresoc.v:8240.9-8240.17" + attribute \src "libresoc.v:8375.9-8375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11756,18 +11891,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:8276.3-8312.6" - process $proc$libresoc.v:8276$171 + attribute \src "libresoc.v:8411.3-8447.6" + process $proc$libresoc.v:8411$171 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:8277.5-8277.29" + attribute \src "libresoc.v:8412.5-8412.29" switch \initial - attribute \src "libresoc.v:8277.9-8277.17" + attribute \src "libresoc.v:8412.9-8412.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11815,18 +11950,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:8313.3-8349.6" - process $proc$libresoc.v:8313$172 + attribute \src "libresoc.v:8448.3-8484.6" + process $proc$libresoc.v:8448$172 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8314.5-8314.29" + attribute \src "libresoc.v:8449.5-8449.29" switch \initial - attribute \src "libresoc.v:8314.9-8314.17" + attribute \src "libresoc.v:8449.9-8449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11874,18 +12009,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:8350.3-8386.6" - process $proc$libresoc.v:8350$173 + attribute \src "libresoc.v:8485.3-8521.6" + process $proc$libresoc.v:8485$173 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8351.5-8351.29" + attribute \src "libresoc.v:8486.5-8486.29" switch \initial - attribute \src "libresoc.v:8351.9-8351.17" + attribute \src "libresoc.v:8486.9-8486.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11933,18 +12068,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:8387.3-8423.6" - process $proc$libresoc.v:8387$174 + attribute \src "libresoc.v:8522.3-8558.6" + process $proc$libresoc.v:8522$174 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8388.5-8388.29" + attribute \src "libresoc.v:8523.5-8523.29" switch \initial - attribute \src "libresoc.v:8388.9-8388.17" + attribute \src "libresoc.v:8523.9-8523.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11992,18 +12127,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:8424.3-8460.6" - process $proc$libresoc.v:8424$175 + attribute \src "libresoc.v:8559.3-8595.6" + process $proc$libresoc.v:8559$175 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8425.5-8425.29" + attribute \src "libresoc.v:8560.5-8560.29" switch \initial - attribute \src "libresoc.v:8425.9-8425.17" + attribute \src "libresoc.v:8560.9-8560.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12051,18 +12186,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:8461.3-8497.6" - process $proc$libresoc.v:8461$176 + attribute \src "libresoc.v:8596.3-8632.6" + process $proc$libresoc.v:8596$176 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8462.5-8462.29" + attribute \src "libresoc.v:8597.5-8597.29" switch \initial - attribute \src "libresoc.v:8462.9-8462.17" + attribute \src "libresoc.v:8597.9-8597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12110,18 +12245,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:8498.3-8534.6" - process $proc$libresoc.v:8498$177 + attribute \src "libresoc.v:8633.3-8669.6" + process $proc$libresoc.v:8633$177 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8499.5-8499.29" + attribute \src "libresoc.v:8634.5-8634.29" switch \initial - attribute \src "libresoc.v:8499.9-8499.17" + attribute \src "libresoc.v:8634.9-8634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12169,18 +12304,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:8535.3-8571.6" - process $proc$libresoc.v:8535$178 + attribute \src "libresoc.v:8670.3-8706.6" + process $proc$libresoc.v:8670$178 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8536.5-8536.29" + attribute \src "libresoc.v:8671.5-8671.29" switch \initial - attribute \src "libresoc.v:8536.9-8536.17" + attribute \src "libresoc.v:8671.9-8671.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12228,18 +12363,18 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:8572.3-8608.6" - process $proc$libresoc.v:8572$179 + attribute \src "libresoc.v:8707.3-8743.6" + process $proc$libresoc.v:8707$179 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8573.5-8573.29" + attribute \src "libresoc.v:8708.5-8708.29" switch \initial - attribute \src "libresoc.v:8573.9-8573.17" + attribute \src "libresoc.v:8708.9-8708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12289,68 +12424,68 @@ module \DIV_dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:8614.1-9317.10" +attribute \src "libresoc.v:8749.1-9457.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" attribute \generator "nMigen" module \DIV_dec31_dec_sub9 - attribute \src "libresoc.v:9131.3-9167.6" + attribute \src "libresoc.v:9271.3-9307.6" wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9168.3-9204.6" + attribute \src "libresoc.v:9308.3-9344.6" wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9279.3-9315.6" + attribute \src "libresoc.v:9419.3-9455.6" wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:8909.3-8945.6" + attribute \src "libresoc.v:9049.3-9085.6" wire $0\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8798.3-8834.6" - wire width 12 $0\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:9057.3-9093.6" + attribute \src "libresoc.v:8938.3-8974.6" + wire width 14 $0\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:9197.3-9233.6" wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9094.3-9130.6" + attribute \src "libresoc.v:9234.3-9270.6" wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9020.3-9056.6" + attribute \src "libresoc.v:9160.3-9196.6" wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:8835.3-8871.6" + attribute \src "libresoc.v:8975.3-9011.6" wire $0\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8872.3-8908.6" + attribute \src "libresoc.v:9012.3-9048.6" wire $0\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:8946.3-8982.6" + attribute \src "libresoc.v:9086.3-9122.6" wire $0\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:9205.3-9241.6" + attribute \src "libresoc.v:9345.3-9381.6" wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9242.3-9278.6" + attribute \src "libresoc.v:9382.3-9418.6" wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:8983.3-9019.6" + attribute \src "libresoc.v:9123.3-9159.6" wire $0\DIV_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:8615.7-8615.20" + attribute \src "libresoc.v:8750.7-8750.20" wire $0\initial[0:0] - attribute \src "libresoc.v:9131.3-9167.6" + attribute \src "libresoc.v:9271.3-9307.6" wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9168.3-9204.6" + attribute \src "libresoc.v:9308.3-9344.6" wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9279.3-9315.6" + attribute \src "libresoc.v:9419.3-9455.6" wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:8909.3-8945.6" + attribute \src "libresoc.v:9049.3-9085.6" wire $1\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8798.3-8834.6" - wire width 12 $1\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:9057.3-9093.6" + attribute \src "libresoc.v:8938.3-8974.6" + wire width 14 $1\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:9197.3-9233.6" wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9094.3-9130.6" + attribute \src "libresoc.v:9234.3-9270.6" wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9020.3-9056.6" + attribute \src "libresoc.v:9160.3-9196.6" wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:8835.3-8871.6" + attribute \src "libresoc.v:8975.3-9011.6" wire $1\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8872.3-8908.6" + attribute \src "libresoc.v:9012.3-9048.6" wire $1\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:8946.3-8982.6" + attribute \src "libresoc.v:9086.3-9122.6" wire $1\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:9205.3-9241.6" + attribute \src "libresoc.v:9345.3-9381.6" wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9242.3-9278.6" + attribute \src "libresoc.v:9382.3-9418.6" wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:8983.3-9019.6" + attribute \src "libresoc.v:9123.3-9159.6" wire $1\DIV_dec31_dec_sub9_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -12360,7 +12495,8 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -12368,38 +12504,41 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \DIV_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -12416,7 +12555,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -12492,13 +12631,14 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -12506,101 +12646,101 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \DIV_dec31_dec_sub9_sgn - attribute \src "libresoc.v:8615.7-8615.15" + attribute \src "libresoc.v:8750.7-8750.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:8615.7-8615.20" - process $proc$libresoc.v:8615$195 + attribute \src "libresoc.v:8750.7-8750.20" + process $proc$libresoc.v:8750$195 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:8798.3-8834.6" - process $proc$libresoc.v:8798$181 + attribute \src "libresoc.v:8938.3-8974.6" + process $proc$libresoc.v:8938$181 assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub9_function_unit[11:0] $1\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:8799.5-8799.29" + assign $0\DIV_dec31_dec_sub9_function_unit[13:0] $1\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:8939.5-8939.29" switch \initial - attribute \src "libresoc.v:8799.9-8799.17" + attribute \src "libresoc.v:8939.9-8939.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 case - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'000000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always - update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[11:0] + update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:8835.3-8871.6" - process $proc$libresoc.v:8835$182 + attribute \src "libresoc.v:8975.3-9011.6" + process $proc$libresoc.v:8975$182 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8836.5-8836.29" + attribute \src "libresoc.v:8976.5-8976.29" switch \initial - attribute \src "libresoc.v:8836.9-8836.17" + attribute \src "libresoc.v:8976.9-8976.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12648,18 +12788,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:8872.3-8908.6" - process $proc$libresoc.v:8872$183 + attribute \src "libresoc.v:9012.3-9048.6" + process $proc$libresoc.v:9012$183 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:8873.5-8873.29" + attribute \src "libresoc.v:9013.5-9013.29" switch \initial - attribute \src "libresoc.v:8873.9-8873.17" + attribute \src "libresoc.v:9013.9-9013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12707,18 +12847,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:8909.3-8945.6" - process $proc$libresoc.v:8909$184 + attribute \src "libresoc.v:9049.3-9085.6" + process $proc$libresoc.v:9049$184 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8910.5-8910.29" + attribute \src "libresoc.v:9050.5-9050.29" switch \initial - attribute \src "libresoc.v:8910.9-8910.17" + attribute \src "libresoc.v:9050.9-9050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12766,18 +12906,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:8946.3-8982.6" - process $proc$libresoc.v:8946$185 + attribute \src "libresoc.v:9086.3-9122.6" + process $proc$libresoc.v:9086$185 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:8947.5-8947.29" + attribute \src "libresoc.v:9087.5-9087.29" switch \initial - attribute \src "libresoc.v:8947.9-8947.17" + attribute \src "libresoc.v:9087.9-9087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12825,18 +12965,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:8983.3-9019.6" - process $proc$libresoc.v:8983$186 + attribute \src "libresoc.v:9123.3-9159.6" + process $proc$libresoc.v:9123$186 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:8984.5-8984.29" + attribute \src "libresoc.v:9124.5-9124.29" switch \initial - attribute \src "libresoc.v:8984.9-8984.17" + attribute \src "libresoc.v:9124.9-9124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12884,18 +13024,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:9020.3-9056.6" - process $proc$libresoc.v:9020$187 + attribute \src "libresoc.v:9160.3-9196.6" + process $proc$libresoc.v:9160$187 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:9021.5-9021.29" + attribute \src "libresoc.v:9161.5-9161.29" switch \initial - attribute \src "libresoc.v:9021.9-9021.17" + attribute \src "libresoc.v:9161.9-9161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12943,18 +13083,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:9057.3-9093.6" - process $proc$libresoc.v:9057$188 + attribute \src "libresoc.v:9197.3-9233.6" + process $proc$libresoc.v:9197$188 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9058.5-9058.29" + attribute \src "libresoc.v:9198.5-9198.29" switch \initial - attribute \src "libresoc.v:9058.9-9058.17" + attribute \src "libresoc.v:9198.9-9198.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13002,18 +13142,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:9094.3-9130.6" - process $proc$libresoc.v:9094$189 + attribute \src "libresoc.v:9234.3-9270.6" + process $proc$libresoc.v:9234$189 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9095.5-9095.29" + attribute \src "libresoc.v:9235.5-9235.29" switch \initial - attribute \src "libresoc.v:9095.9-9095.17" + attribute \src "libresoc.v:9235.9-9235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13061,18 +13201,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:9131.3-9167.6" - process $proc$libresoc.v:9131$190 + attribute \src "libresoc.v:9271.3-9307.6" + process $proc$libresoc.v:9271$190 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9132.5-9132.29" + attribute \src "libresoc.v:9272.5-9272.29" switch \initial - attribute \src "libresoc.v:9132.9-9132.17" + attribute \src "libresoc.v:9272.9-9272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13120,18 +13260,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:9168.3-9204.6" - process $proc$libresoc.v:9168$191 + attribute \src "libresoc.v:9308.3-9344.6" + process $proc$libresoc.v:9308$191 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9169.5-9169.29" + attribute \src "libresoc.v:9309.5-9309.29" switch \initial - attribute \src "libresoc.v:9169.9-9169.17" + attribute \src "libresoc.v:9309.9-9309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13179,18 +13319,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:9205.3-9241.6" - process $proc$libresoc.v:9205$192 + attribute \src "libresoc.v:9345.3-9381.6" + process $proc$libresoc.v:9345$192 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9206.5-9206.29" + attribute \src "libresoc.v:9346.5-9346.29" switch \initial - attribute \src "libresoc.v:9206.9-9206.17" + attribute \src "libresoc.v:9346.9-9346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13238,18 +13378,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:9242.3-9278.6" - process $proc$libresoc.v:9242$193 + attribute \src "libresoc.v:9382.3-9418.6" + process $proc$libresoc.v:9382$193 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:9243.5-9243.29" + attribute \src "libresoc.v:9383.5-9383.29" switch \initial - attribute \src "libresoc.v:9243.9-9243.17" + attribute \src "libresoc.v:9383.9-9383.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13297,18 +13437,18 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:9279.3-9315.6" - process $proc$libresoc.v:9279$194 + attribute \src "libresoc.v:9419.3-9455.6" + process $proc$libresoc.v:9419$194 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:9280.5-9280.29" + attribute \src "libresoc.v:9420.5-9420.29" switch \initial - attribute \src "libresoc.v:9280.9-9280.17" + attribute \src "libresoc.v:9420.9-9420.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13358,66 +13498,66 @@ module \DIV_dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:9321.1-10482.10" +attribute \src "libresoc.v:9461.1-10647.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" attribute \generator "nMigen" module \LDST_dec31 - attribute \src "libresoc.v:10324.3-10342.6" + attribute \src "libresoc.v:10489.3-10507.6" wire $0\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10229.3-10247.6" + attribute \src "libresoc.v:10394.3-10412.6" wire width 3 $0\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10248.3-10266.6" + attribute \src "libresoc.v:10413.3-10431.6" wire width 3 $0\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10400.3-10418.6" - wire width 12 $0\LDST_dec31_function_unit[11:0] - attribute \src "libresoc.v:10438.3-10456.6" + attribute \src "libresoc.v:10565.3-10583.6" + wire width 14 $0\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10603.3-10621.6" wire width 3 $0\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10457.3-10475.6" + attribute \src "libresoc.v:10622.3-10640.6" wire width 4 $0\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10419.3-10437.6" + attribute \src "libresoc.v:10584.3-10602.6" wire width 7 $0\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10362.3-10380.6" + attribute \src "libresoc.v:10527.3-10545.6" wire $0\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10267.3-10285.6" + attribute \src "libresoc.v:10432.3-10450.6" wire width 4 $0\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10305.3-10323.6" + attribute \src "libresoc.v:10470.3-10488.6" wire width 2 $0\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10381.3-10399.6" + attribute \src "libresoc.v:10546.3-10564.6" wire $0\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10343.3-10361.6" + attribute \src "libresoc.v:10508.3-10526.6" wire $0\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10286.3-10304.6" + attribute \src "libresoc.v:10451.3-10469.6" wire width 2 $0\LDST_dec31_upd[1:0] - attribute \src "libresoc.v:9322.7-9322.20" + attribute \src "libresoc.v:9462.7-9462.20" wire $0\initial[0:0] - attribute \src "libresoc.v:10324.3-10342.6" + attribute \src "libresoc.v:10489.3-10507.6" wire $1\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10229.3-10247.6" + attribute \src "libresoc.v:10394.3-10412.6" wire width 3 $1\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10248.3-10266.6" + attribute \src "libresoc.v:10413.3-10431.6" wire width 3 $1\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10400.3-10418.6" - wire width 12 $1\LDST_dec31_function_unit[11:0] - attribute \src "libresoc.v:10438.3-10456.6" + attribute \src "libresoc.v:10565.3-10583.6" + wire width 14 $1\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10603.3-10621.6" wire width 3 $1\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10457.3-10475.6" + attribute \src "libresoc.v:10622.3-10640.6" wire width 4 $1\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10419.3-10437.6" + attribute \src "libresoc.v:10584.3-10602.6" wire width 7 $1\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10362.3-10380.6" + attribute \src "libresoc.v:10527.3-10545.6" wire $1\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10267.3-10285.6" + attribute \src "libresoc.v:10432.3-10450.6" wire width 4 $1\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10305.3-10323.6" + attribute \src "libresoc.v:10470.3-10488.6" wire width 2 $1\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10381.3-10399.6" + attribute \src "libresoc.v:10546.3-10564.6" wire $1\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10343.3-10361.6" + attribute \src "libresoc.v:10508.3-10526.6" wire $1\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10286.3-10304.6" + attribute \src "libresoc.v:10451.3-10469.6" wire width 2 $1\LDST_dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13427,7 +13567,8 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13435,9 +13576,10 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13447,7 +13589,8 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13455,30 +13598,33 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13495,7 +13641,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13571,9 +13717,10 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13581,28 +13728,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec31_dec_sub20_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13612,7 +13759,8 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13620,30 +13768,33 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13660,7 +13811,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13736,9 +13887,10 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13746,28 +13898,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13777,7 +13929,8 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13785,30 +13938,33 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13825,7 +13981,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13901,9 +14057,10 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13911,28 +14068,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13942,7 +14099,8 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13950,30 +14108,33 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13990,7 +14151,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14066,9 +14227,10 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14076,49 +14238,51 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec31_dec_sub23_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -14135,7 +14299,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14211,9 +14375,10 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14221,35 +14386,35 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LDST_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LDST_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_upd - attribute \src "libresoc.v:9322.7-9322.15" + attribute \src "libresoc.v:9462.7-9462.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:10165.24-10180.4" + attribute \src "libresoc.v:10330.24-10345.4" cell \LDST_dec31_dec_sub20 \LDST_dec31_dec_sub20 connect \LDST_dec31_dec_sub20_br \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br connect \LDST_dec31_dec_sub20_cr_in \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in @@ -14267,7 +14432,7 @@ module \LDST_dec31 connect \opcode_in \LDST_dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:10181.24-10196.4" + attribute \src "libresoc.v:10346.24-10361.4" cell \LDST_dec31_dec_sub21 \LDST_dec31_dec_sub21 connect \LDST_dec31_dec_sub21_br \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br connect \LDST_dec31_dec_sub21_cr_in \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in @@ -14285,7 +14450,7 @@ module \LDST_dec31 connect \opcode_in \LDST_dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:10197.24-10212.4" + attribute \src "libresoc.v:10362.24-10377.4" cell \LDST_dec31_dec_sub22 \LDST_dec31_dec_sub22 connect \LDST_dec31_dec_sub22_br \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br connect \LDST_dec31_dec_sub22_cr_in \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in @@ -14303,7 +14468,7 @@ module \LDST_dec31 connect \opcode_in \LDST_dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:10213.24-10228.4" + attribute \src "libresoc.v:10378.24-10393.4" cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in @@ -14320,18 +14485,18 @@ module \LDST_dec31 connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd connect \opcode_in \LDST_dec31_dec_sub23_opcode_in end - attribute \src "libresoc.v:10229.3-10247.6" - process $proc$libresoc.v:10229$196 + attribute \src "libresoc.v:10394.3-10412.6" + process $proc$libresoc.v:10394$196 assign { } { } assign { } { } assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10230.5-10230.29" + attribute \src "libresoc.v:10395.5-10395.29" switch \initial - attribute \src "libresoc.v:10230.9-10230.17" + attribute \src "libresoc.v:10395.9-10395.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14355,18 +14520,18 @@ module \LDST_dec31 sync always update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] end - attribute \src "libresoc.v:10248.3-10266.6" - process $proc$libresoc.v:10248$197 + attribute \src "libresoc.v:10413.3-10431.6" + process $proc$libresoc.v:10413$197 assign { } { } assign { } { } assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10249.5-10249.29" + attribute \src "libresoc.v:10414.5-10414.29" switch \initial - attribute \src "libresoc.v:10249.9-10249.17" + attribute \src "libresoc.v:10414.9-10414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14390,18 +14555,18 @@ module \LDST_dec31 sync always update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] end - attribute \src "libresoc.v:10267.3-10285.6" - process $proc$libresoc.v:10267$198 + attribute \src "libresoc.v:10432.3-10450.6" + process $proc$libresoc.v:10432$198 assign { } { } assign { } { } assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10268.5-10268.29" + attribute \src "libresoc.v:10433.5-10433.29" switch \initial - attribute \src "libresoc.v:10268.9-10268.17" + attribute \src "libresoc.v:10433.9-10433.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14425,18 +14590,18 @@ module \LDST_dec31 sync always update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] end - attribute \src "libresoc.v:10286.3-10304.6" - process $proc$libresoc.v:10286$199 + attribute \src "libresoc.v:10451.3-10469.6" + process $proc$libresoc.v:10451$199 assign { } { } assign { } { } assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] - attribute \src "libresoc.v:10287.5-10287.29" + attribute \src "libresoc.v:10452.5-10452.29" switch \initial - attribute \src "libresoc.v:10287.9-10287.17" + attribute \src "libresoc.v:10452.9-10452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14460,18 +14625,18 @@ module \LDST_dec31 sync always update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] end - attribute \src "libresoc.v:10305.3-10323.6" - process $proc$libresoc.v:10305$200 + attribute \src "libresoc.v:10470.3-10488.6" + process $proc$libresoc.v:10470$200 assign { } { } assign { } { } assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10306.5-10306.29" + attribute \src "libresoc.v:10471.5-10471.29" switch \initial - attribute \src "libresoc.v:10306.9-10306.17" + attribute \src "libresoc.v:10471.9-10471.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14495,18 +14660,18 @@ module \LDST_dec31 sync always update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:10324.3-10342.6" - process $proc$libresoc.v:10324$201 + attribute \src "libresoc.v:10489.3-10507.6" + process $proc$libresoc.v:10489$201 assign { } { } assign { } { } assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10325.5-10325.29" + attribute \src "libresoc.v:10490.5-10490.29" switch \initial - attribute \src "libresoc.v:10325.9-10325.17" + attribute \src "libresoc.v:10490.9-10490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14530,18 +14695,18 @@ module \LDST_dec31 sync always update \LDST_dec31_br $0\LDST_dec31_br[0:0] end - attribute \src "libresoc.v:10343.3-10361.6" - process $proc$libresoc.v:10343$202 + attribute \src "libresoc.v:10508.3-10526.6" + process $proc$libresoc.v:10508$202 assign { } { } assign { } { } assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10344.5-10344.29" + attribute \src "libresoc.v:10509.5-10509.29" switch \initial - attribute \src "libresoc.v:10344.9-10344.17" + attribute \src "libresoc.v:10509.9-10509.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14565,18 +14730,18 @@ module \LDST_dec31 sync always update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:10362.3-10380.6" - process $proc$libresoc.v:10362$203 + attribute \src "libresoc.v:10527.3-10545.6" + process $proc$libresoc.v:10527$203 assign { } { } assign { } { } assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10363.5-10363.29" + attribute \src "libresoc.v:10528.5-10528.29" switch \initial - attribute \src "libresoc.v:10363.9-10363.17" + attribute \src "libresoc.v:10528.9-10528.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14600,18 +14765,18 @@ module \LDST_dec31 sync always update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] end - attribute \src "libresoc.v:10381.3-10399.6" - process $proc$libresoc.v:10381$204 + attribute \src "libresoc.v:10546.3-10564.6" + process $proc$libresoc.v:10546$204 assign { } { } assign { } { } assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10382.5-10382.29" + attribute \src "libresoc.v:10547.5-10547.29" switch \initial - attribute \src "libresoc.v:10382.9-10382.17" + attribute \src "libresoc.v:10547.9-10547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14635,53 +14800,53 @@ module \LDST_dec31 sync always update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] end - attribute \src "libresoc.v:10400.3-10418.6" - process $proc$libresoc.v:10400$205 + attribute \src "libresoc.v:10565.3-10583.6" + process $proc$libresoc.v:10565$205 assign { } { } assign { } { } - assign $0\LDST_dec31_function_unit[11:0] $1\LDST_dec31_function_unit[11:0] - attribute \src "libresoc.v:10401.5-10401.29" + assign $0\LDST_dec31_function_unit[13:0] $1\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10566.5-10566.29" switch \initial - attribute \src "libresoc.v:10401.9-10401.17" + attribute \src "libresoc.v:10566.9-10566.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit case - assign $1\LDST_dec31_function_unit[11:0] 12'000000000000 + assign $1\LDST_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[11:0] + update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[13:0] end - attribute \src "libresoc.v:10419.3-10437.6" - process $proc$libresoc.v:10419$206 + attribute \src "libresoc.v:10584.3-10602.6" + process $proc$libresoc.v:10584$206 assign { } { } assign { } { } assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10420.5-10420.29" + attribute \src "libresoc.v:10585.5-10585.29" switch \initial - attribute \src "libresoc.v:10420.9-10420.17" + attribute \src "libresoc.v:10585.9-10585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14705,18 +14870,18 @@ module \LDST_dec31 sync always update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] end - attribute \src "libresoc.v:10438.3-10456.6" - process $proc$libresoc.v:10438$207 + attribute \src "libresoc.v:10603.3-10621.6" + process $proc$libresoc.v:10603$207 assign { } { } assign { } { } assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10439.5-10439.29" + attribute \src "libresoc.v:10604.5-10604.29" switch \initial - attribute \src "libresoc.v:10439.9-10439.17" + attribute \src "libresoc.v:10604.9-10604.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14740,18 +14905,18 @@ module \LDST_dec31 sync always update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] end - attribute \src "libresoc.v:10457.3-10475.6" - process $proc$libresoc.v:10457$208 + attribute \src "libresoc.v:10622.3-10640.6" + process $proc$libresoc.v:10622$208 assign { } { } assign { } { } assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10458.5-10458.29" + attribute \src "libresoc.v:10623.5-10623.29" switch \initial - attribute \src "libresoc.v:10458.9-10458.17" + attribute \src "libresoc.v:10623.9-10623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14775,8 +14940,8 @@ module \LDST_dec31 sync always update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:9322.7-9322.20" - process $proc$libresoc.v:9322$209 + attribute \src "libresoc.v:9462.7-9462.20" + process $proc$libresoc.v:9462$209 assign { } { } assign $0\initial[0:0] 1'0 sync always @@ -14790,66 +14955,66 @@ module \LDST_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:10486.1-10994.10" +attribute \src "libresoc.v:10651.1-11164.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" attribute \generator "nMigen" module \LDST_dec31_dec_sub20 - attribute \src "libresoc.v:10693.3-10717.6" + attribute \src "libresoc.v:10863.3-10887.6" wire $0\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10868.3-10892.6" + attribute \src "libresoc.v:11038.3-11062.6" wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10893.3-10917.6" + attribute \src "libresoc.v:11063.3-11087.6" wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10668.3-10692.6" - wire width 12 $0\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:10818.3-10842.6" + attribute \src "libresoc.v:10838.3-10862.6" + wire width 14 $0\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10988.3-11012.6" wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10843.3-10867.6" + attribute \src "libresoc.v:11013.3-11037.6" wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10793.3-10817.6" + attribute \src "libresoc.v:10963.3-10987.6" wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10743.3-10767.6" + attribute \src "libresoc.v:10913.3-10937.6" wire $0\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:10918.3-10942.6" + attribute \src "libresoc.v:11088.3-11112.6" wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:10968.3-10992.6" + attribute \src "libresoc.v:11138.3-11162.6" wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:10768.3-10792.6" + attribute \src "libresoc.v:10938.3-10962.6" wire $0\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10718.3-10742.6" + attribute \src "libresoc.v:10888.3-10912.6" wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:10943.3-10967.6" + attribute \src "libresoc.v:11113.3-11137.6" wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:10487.7-10487.20" + attribute \src "libresoc.v:10652.7-10652.20" wire $0\initial[0:0] - attribute \src "libresoc.v:10693.3-10717.6" + attribute \src "libresoc.v:10863.3-10887.6" wire $1\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10868.3-10892.6" + attribute \src "libresoc.v:11038.3-11062.6" wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10893.3-10917.6" + attribute \src "libresoc.v:11063.3-11087.6" wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10668.3-10692.6" - wire width 12 $1\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:10818.3-10842.6" + attribute \src "libresoc.v:10838.3-10862.6" + wire width 14 $1\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10988.3-11012.6" wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10843.3-10867.6" + attribute \src "libresoc.v:11013.3-11037.6" wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10793.3-10817.6" + attribute \src "libresoc.v:10963.3-10987.6" wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10743.3-10767.6" + attribute \src "libresoc.v:10913.3-10937.6" wire $1\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:10918.3-10942.6" + attribute \src "libresoc.v:11088.3-11112.6" wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:10968.3-10992.6" + attribute \src "libresoc.v:11138.3-11162.6" wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:10768.3-10792.6" + attribute \src "libresoc.v:10938.3-10962.6" wire $1\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10718.3-10742.6" + attribute \src "libresoc.v:10888.3-10912.6" wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:10943.3-10967.6" + attribute \src "libresoc.v:11113.3-11137.6" wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -14859,7 +15024,8 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -14867,30 +15033,33 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_dec_sub20_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -14907,7 +15076,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14983,9 +15152,10 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14993,94 +15163,94 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_dec_sub20_upd - attribute \src "libresoc.v:10487.7-10487.15" + attribute \src "libresoc.v:10652.7-10652.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:10487.7-10487.20" - process $proc$libresoc.v:10487$223 + attribute \src "libresoc.v:10652.7-10652.20" + process $proc$libresoc.v:10652$223 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:10668.3-10692.6" - process $proc$libresoc.v:10668$210 + attribute \src "libresoc.v:10838.3-10862.6" + process $proc$libresoc.v:10838$210 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_function_unit[11:0] $1\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:10669.5-10669.29" + assign $0\LDST_dec31_dec_sub20_function_unit[13:0] $1\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10839.5-10839.29" switch \initial - attribute \src "libresoc.v:10669.9-10669.17" + attribute \src "libresoc.v:10839.9-10839.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000000 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[11:0] + update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:10693.3-10717.6" - process $proc$libresoc.v:10693$211 + attribute \src "libresoc.v:10863.3-10887.6" + process $proc$libresoc.v:10863$211 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10694.5-10694.29" + attribute \src "libresoc.v:10864.5-10864.29" switch \initial - attribute \src "libresoc.v:10694.9-10694.17" + attribute \src "libresoc.v:10864.9-10864.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15112,18 +15282,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:10718.3-10742.6" - process $proc$libresoc.v:10718$212 + attribute \src "libresoc.v:10888.3-10912.6" + process $proc$libresoc.v:10888$212 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:10719.5-10719.29" + attribute \src "libresoc.v:10889.5-10889.29" switch \initial - attribute \src "libresoc.v:10719.9-10719.17" + attribute \src "libresoc.v:10889.9-10889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15155,18 +15325,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:10743.3-10767.6" - process $proc$libresoc.v:10743$213 + attribute \src "libresoc.v:10913.3-10937.6" + process $proc$libresoc.v:10913$213 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:10744.5-10744.29" + attribute \src "libresoc.v:10914.5-10914.29" switch \initial - attribute \src "libresoc.v:10744.9-10744.17" + attribute \src "libresoc.v:10914.9-10914.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15198,18 +15368,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:10768.3-10792.6" - process $proc$libresoc.v:10768$214 + attribute \src "libresoc.v:10938.3-10962.6" + process $proc$libresoc.v:10938$214 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10769.5-10769.29" + attribute \src "libresoc.v:10939.5-10939.29" switch \initial - attribute \src "libresoc.v:10769.9-10769.17" + attribute \src "libresoc.v:10939.9-10939.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15241,18 +15411,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:10793.3-10817.6" - process $proc$libresoc.v:10793$215 + attribute \src "libresoc.v:10963.3-10987.6" + process $proc$libresoc.v:10963$215 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10794.5-10794.29" + attribute \src "libresoc.v:10964.5-10964.29" switch \initial - attribute \src "libresoc.v:10794.9-10794.17" + attribute \src "libresoc.v:10964.9-10964.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15284,18 +15454,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:10818.3-10842.6" - process $proc$libresoc.v:10818$216 + attribute \src "libresoc.v:10988.3-11012.6" + process $proc$libresoc.v:10988$216 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10819.5-10819.29" + attribute \src "libresoc.v:10989.5-10989.29" switch \initial - attribute \src "libresoc.v:10819.9-10819.17" + attribute \src "libresoc.v:10989.9-10989.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15327,18 +15497,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:10843.3-10867.6" - process $proc$libresoc.v:10843$217 + attribute \src "libresoc.v:11013.3-11037.6" + process $proc$libresoc.v:11013$217 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10844.5-10844.29" + attribute \src "libresoc.v:11014.5-11014.29" switch \initial - attribute \src "libresoc.v:10844.9-10844.17" + attribute \src "libresoc.v:11014.9-11014.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15370,18 +15540,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:10868.3-10892.6" - process $proc$libresoc.v:10868$218 + attribute \src "libresoc.v:11038.3-11062.6" + process $proc$libresoc.v:11038$218 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10869.5-10869.29" + attribute \src "libresoc.v:11039.5-11039.29" switch \initial - attribute \src "libresoc.v:10869.9-10869.17" + attribute \src "libresoc.v:11039.9-11039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15413,18 +15583,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:10893.3-10917.6" - process $proc$libresoc.v:10893$219 + attribute \src "libresoc.v:11063.3-11087.6" + process $proc$libresoc.v:11063$219 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10894.5-10894.29" + attribute \src "libresoc.v:11064.5-11064.29" switch \initial - attribute \src "libresoc.v:10894.9-10894.17" + attribute \src "libresoc.v:11064.9-11064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15456,18 +15626,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:10918.3-10942.6" - process $proc$libresoc.v:10918$220 + attribute \src "libresoc.v:11088.3-11112.6" + process $proc$libresoc.v:11088$220 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:10919.5-10919.29" + attribute \src "libresoc.v:11089.5-11089.29" switch \initial - attribute \src "libresoc.v:10919.9-10919.17" + attribute \src "libresoc.v:11089.9-11089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15499,18 +15669,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:10943.3-10967.6" - process $proc$libresoc.v:10943$221 + attribute \src "libresoc.v:11113.3-11137.6" + process $proc$libresoc.v:11113$221 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:10944.5-10944.29" + attribute \src "libresoc.v:11114.5-11114.29" switch \initial - attribute \src "libresoc.v:10944.9-10944.17" + attribute \src "libresoc.v:11114.9-11114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15542,18 +15712,18 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:10968.3-10992.6" - process $proc$libresoc.v:10968$222 + attribute \src "libresoc.v:11138.3-11162.6" + process $proc$libresoc.v:11138$222 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:10969.5-10969.29" + attribute \src "libresoc.v:11139.5-11139.29" switch \initial - attribute \src "libresoc.v:10969.9-10969.17" + attribute \src "libresoc.v:11139.9-11139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15587,66 +15757,66 @@ module \LDST_dec31_dec_sub20 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:10998.1-11818.10" +attribute \src "libresoc.v:11168.1-11993.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" attribute \generator "nMigen" module \LDST_dec31_dec_sub21 - attribute \src "libresoc.v:11229.3-11277.6" + attribute \src "libresoc.v:11404.3-11452.6" wire $0\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11572.3-11620.6" + attribute \src "libresoc.v:11747.3-11795.6" wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11621.3-11669.6" + attribute \src "libresoc.v:11796.3-11844.6" wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11180.3-11228.6" - wire width 12 $0\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:11474.3-11522.6" + attribute \src "libresoc.v:11355.3-11403.6" + wire width 14 $0\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11649.3-11697.6" wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11523.3-11571.6" + attribute \src "libresoc.v:11698.3-11746.6" wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11425.3-11473.6" + attribute \src "libresoc.v:11600.3-11648.6" wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11327.3-11375.6" + attribute \src "libresoc.v:11502.3-11550.6" wire $0\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11670.3-11718.6" + attribute \src "libresoc.v:11845.3-11893.6" wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11768.3-11816.6" + attribute \src "libresoc.v:11943.3-11991.6" wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11376.3-11424.6" + attribute \src "libresoc.v:11551.3-11599.6" wire $0\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11278.3-11326.6" + attribute \src "libresoc.v:11453.3-11501.6" wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11719.3-11767.6" + attribute \src "libresoc.v:11894.3-11942.6" wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:10999.7-10999.20" + attribute \src "libresoc.v:11169.7-11169.20" wire $0\initial[0:0] - attribute \src "libresoc.v:11229.3-11277.6" + attribute \src "libresoc.v:11404.3-11452.6" wire $1\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11572.3-11620.6" + attribute \src "libresoc.v:11747.3-11795.6" wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11621.3-11669.6" + attribute \src "libresoc.v:11796.3-11844.6" wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11180.3-11228.6" - wire width 12 $1\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:11474.3-11522.6" + attribute \src "libresoc.v:11355.3-11403.6" + wire width 14 $1\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11649.3-11697.6" wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11523.3-11571.6" + attribute \src "libresoc.v:11698.3-11746.6" wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11425.3-11473.6" + attribute \src "libresoc.v:11600.3-11648.6" wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11327.3-11375.6" + attribute \src "libresoc.v:11502.3-11550.6" wire $1\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11670.3-11718.6" + attribute \src "libresoc.v:11845.3-11893.6" wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11768.3-11816.6" + attribute \src "libresoc.v:11943.3-11991.6" wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11376.3-11424.6" + attribute \src "libresoc.v:11551.3-11599.6" wire $1\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11278.3-11326.6" + attribute \src "libresoc.v:11453.3-11501.6" wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11719.3-11767.6" + attribute \src "libresoc.v:11894.3-11942.6" wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -15656,7 +15826,8 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -15664,30 +15835,33 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_dec_sub21_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -15704,7 +15878,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -15780,9 +15954,10 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -15790,126 +15965,126 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_dec_sub21_upd - attribute \src "libresoc.v:10999.7-10999.15" + attribute \src "libresoc.v:11169.7-11169.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:10999.7-10999.20" - process $proc$libresoc.v:10999$237 + attribute \src "libresoc.v:11169.7-11169.20" + process $proc$libresoc.v:11169$237 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:11180.3-11228.6" - process $proc$libresoc.v:11180$224 + attribute \src "libresoc.v:11355.3-11403.6" + process $proc$libresoc.v:11355$224 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_function_unit[11:0] $1\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:11181.5-11181.29" + assign $0\LDST_dec31_dec_sub21_function_unit[13:0] $1\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11356.5-11356.29" switch \initial - attribute \src "libresoc.v:11181.9-11181.17" + attribute \src "libresoc.v:11356.9-11356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000000 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[11:0] + update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:11229.3-11277.6" - process $proc$libresoc.v:11229$225 + attribute \src "libresoc.v:11404.3-11452.6" + process $proc$libresoc.v:11404$225 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11230.5-11230.29" + attribute \src "libresoc.v:11405.5-11405.29" switch \initial - attribute \src "libresoc.v:11230.9-11230.17" + attribute \src "libresoc.v:11405.9-11405.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -15973,18 +16148,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:11278.3-11326.6" - process $proc$libresoc.v:11278$226 + attribute \src "libresoc.v:11453.3-11501.6" + process $proc$libresoc.v:11453$226 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11279.5-11279.29" + attribute \src "libresoc.v:11454.5-11454.29" switch \initial - attribute \src "libresoc.v:11279.9-11279.17" + attribute \src "libresoc.v:11454.9-11454.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16048,18 +16223,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:11327.3-11375.6" - process $proc$libresoc.v:11327$227 + attribute \src "libresoc.v:11502.3-11550.6" + process $proc$libresoc.v:11502$227 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11328.5-11328.29" + attribute \src "libresoc.v:11503.5-11503.29" switch \initial - attribute \src "libresoc.v:11328.9-11328.17" + attribute \src "libresoc.v:11503.9-11503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16123,18 +16298,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:11376.3-11424.6" - process $proc$libresoc.v:11376$228 + attribute \src "libresoc.v:11551.3-11599.6" + process $proc$libresoc.v:11551$228 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11377.5-11377.29" + attribute \src "libresoc.v:11552.5-11552.29" switch \initial - attribute \src "libresoc.v:11377.9-11377.17" + attribute \src "libresoc.v:11552.9-11552.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16198,18 +16373,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:11425.3-11473.6" - process $proc$libresoc.v:11425$229 + attribute \src "libresoc.v:11600.3-11648.6" + process $proc$libresoc.v:11600$229 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11426.5-11426.29" + attribute \src "libresoc.v:11601.5-11601.29" switch \initial - attribute \src "libresoc.v:11426.9-11426.17" + attribute \src "libresoc.v:11601.9-11601.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16273,18 +16448,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:11474.3-11522.6" - process $proc$libresoc.v:11474$230 + attribute \src "libresoc.v:11649.3-11697.6" + process $proc$libresoc.v:11649$230 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11475.5-11475.29" + attribute \src "libresoc.v:11650.5-11650.29" switch \initial - attribute \src "libresoc.v:11475.9-11475.17" + attribute \src "libresoc.v:11650.9-11650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16348,18 +16523,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:11523.3-11571.6" - process $proc$libresoc.v:11523$231 + attribute \src "libresoc.v:11698.3-11746.6" + process $proc$libresoc.v:11698$231 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11524.5-11524.29" + attribute \src "libresoc.v:11699.5-11699.29" switch \initial - attribute \src "libresoc.v:11524.9-11524.17" + attribute \src "libresoc.v:11699.9-11699.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16423,18 +16598,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:11572.3-11620.6" - process $proc$libresoc.v:11572$232 + attribute \src "libresoc.v:11747.3-11795.6" + process $proc$libresoc.v:11747$232 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11573.5-11573.29" + attribute \src "libresoc.v:11748.5-11748.29" switch \initial - attribute \src "libresoc.v:11573.9-11573.17" + attribute \src "libresoc.v:11748.9-11748.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16498,18 +16673,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:11621.3-11669.6" - process $proc$libresoc.v:11621$233 + attribute \src "libresoc.v:11796.3-11844.6" + process $proc$libresoc.v:11796$233 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11622.5-11622.29" + attribute \src "libresoc.v:11797.5-11797.29" switch \initial - attribute \src "libresoc.v:11622.9-11622.17" + attribute \src "libresoc.v:11797.9-11797.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16573,18 +16748,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:11670.3-11718.6" - process $proc$libresoc.v:11670$234 + attribute \src "libresoc.v:11845.3-11893.6" + process $proc$libresoc.v:11845$234 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11671.5-11671.29" + attribute \src "libresoc.v:11846.5-11846.29" switch \initial - attribute \src "libresoc.v:11671.9-11671.17" + attribute \src "libresoc.v:11846.9-11846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16648,18 +16823,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:11719.3-11767.6" - process $proc$libresoc.v:11719$235 + attribute \src "libresoc.v:11894.3-11942.6" + process $proc$libresoc.v:11894$235 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:11720.5-11720.29" + attribute \src "libresoc.v:11895.5-11895.29" switch \initial - attribute \src "libresoc.v:11720.9-11720.17" + attribute \src "libresoc.v:11895.9-11895.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16723,18 +16898,18 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:11768.3-11816.6" - process $proc$libresoc.v:11768$236 + attribute \src "libresoc.v:11943.3-11991.6" + process $proc$libresoc.v:11943$236 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11769.5-11769.29" + attribute \src "libresoc.v:11944.5-11944.29" switch \initial - attribute \src "libresoc.v:11769.9-11769.17" + attribute \src "libresoc.v:11944.9-11944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16800,66 +16975,66 @@ module \LDST_dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:11822.1-12408.10" +attribute \src "libresoc.v:11997.1-12588.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" attribute \generator "nMigen" module \LDST_dec31_dec_sub22 - attribute \src "libresoc.v:12035.3-12065.6" + attribute \src "libresoc.v:12215.3-12245.6" wire $0\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12252.3-12282.6" + attribute \src "libresoc.v:12432.3-12462.6" wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12283.3-12313.6" + attribute \src "libresoc.v:12463.3-12493.6" wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12004.3-12034.6" - wire width 12 $0\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:12190.3-12220.6" + attribute \src "libresoc.v:12184.3-12214.6" + wire width 14 $0\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12370.3-12400.6" wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12221.3-12251.6" + attribute \src "libresoc.v:12401.3-12431.6" wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12159.3-12189.6" + attribute \src "libresoc.v:12339.3-12369.6" wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12097.3-12127.6" + attribute \src "libresoc.v:12277.3-12307.6" wire $0\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12314.3-12344.6" + attribute \src "libresoc.v:12494.3-12524.6" wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12376.3-12406.6" + attribute \src "libresoc.v:12556.3-12586.6" wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12128.3-12158.6" + attribute \src "libresoc.v:12308.3-12338.6" wire $0\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12066.3-12096.6" + attribute \src "libresoc.v:12246.3-12276.6" wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12345.3-12375.6" + attribute \src "libresoc.v:12525.3-12555.6" wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:11823.7-11823.20" + attribute \src "libresoc.v:11998.7-11998.20" wire $0\initial[0:0] - attribute \src "libresoc.v:12035.3-12065.6" + attribute \src "libresoc.v:12215.3-12245.6" wire $1\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12252.3-12282.6" + attribute \src "libresoc.v:12432.3-12462.6" wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12283.3-12313.6" + attribute \src "libresoc.v:12463.3-12493.6" wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12004.3-12034.6" - wire width 12 $1\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:12190.3-12220.6" + attribute \src "libresoc.v:12184.3-12214.6" + wire width 14 $1\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12370.3-12400.6" wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12221.3-12251.6" + attribute \src "libresoc.v:12401.3-12431.6" wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12159.3-12189.6" + attribute \src "libresoc.v:12339.3-12369.6" wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12097.3-12127.6" + attribute \src "libresoc.v:12277.3-12307.6" wire $1\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12314.3-12344.6" + attribute \src "libresoc.v:12494.3-12524.6" wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12376.3-12406.6" + attribute \src "libresoc.v:12556.3-12586.6" wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12128.3-12158.6" + attribute \src "libresoc.v:12308.3-12338.6" wire $1\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12066.3-12096.6" + attribute \src "libresoc.v:12246.3-12276.6" wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12345.3-12375.6" + attribute \src "libresoc.v:12525.3-12555.6" wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -16869,7 +17044,8 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -16877,30 +17053,33 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -16917,7 +17096,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -16993,9 +17172,10 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -17003,102 +17183,102 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_dec_sub22_upd - attribute \src "libresoc.v:11823.7-11823.15" + attribute \src "libresoc.v:11998.7-11998.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:11823.7-11823.20" - process $proc$libresoc.v:11823$251 + attribute \src "libresoc.v:11998.7-11998.20" + process $proc$libresoc.v:11998$251 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:12004.3-12034.6" - process $proc$libresoc.v:12004$238 + attribute \src "libresoc.v:12184.3-12214.6" + process $proc$libresoc.v:12184$238 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub22_function_unit[11:0] $1\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:12005.5-12005.29" + assign $0\LDST_dec31_dec_sub22_function_unit[13:0] $1\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12185.5-12185.29" switch \initial - attribute \src "libresoc.v:12005.9-12005.17" + attribute \src "libresoc.v:12185.9-12185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000000 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[11:0] + update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:12035.3-12065.6" - process $proc$libresoc.v:12035$239 + attribute \src "libresoc.v:12215.3-12245.6" + process $proc$libresoc.v:12215$239 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12036.5-12036.29" + attribute \src "libresoc.v:12216.5-12216.29" switch \initial - attribute \src "libresoc.v:12036.9-12036.17" + attribute \src "libresoc.v:12216.9-12216.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17138,18 +17318,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:12066.3-12096.6" - process $proc$libresoc.v:12066$240 + attribute \src "libresoc.v:12246.3-12276.6" + process $proc$libresoc.v:12246$240 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12067.5-12067.29" + attribute \src "libresoc.v:12247.5-12247.29" switch \initial - attribute \src "libresoc.v:12067.9-12067.17" + attribute \src "libresoc.v:12247.9-12247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17189,18 +17369,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:12097.3-12127.6" - process $proc$libresoc.v:12097$241 + attribute \src "libresoc.v:12277.3-12307.6" + process $proc$libresoc.v:12277$241 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12098.5-12098.29" + attribute \src "libresoc.v:12278.5-12278.29" switch \initial - attribute \src "libresoc.v:12098.9-12098.17" + attribute \src "libresoc.v:12278.9-12278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17240,18 +17420,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:12128.3-12158.6" - process $proc$libresoc.v:12128$242 + attribute \src "libresoc.v:12308.3-12338.6" + process $proc$libresoc.v:12308$242 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12129.5-12129.29" + attribute \src "libresoc.v:12309.5-12309.29" switch \initial - attribute \src "libresoc.v:12129.9-12129.17" + attribute \src "libresoc.v:12309.9-12309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17291,18 +17471,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:12159.3-12189.6" - process $proc$libresoc.v:12159$243 + attribute \src "libresoc.v:12339.3-12369.6" + process $proc$libresoc.v:12339$243 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12160.5-12160.29" + attribute \src "libresoc.v:12340.5-12340.29" switch \initial - attribute \src "libresoc.v:12160.9-12160.17" + attribute \src "libresoc.v:12340.9-12340.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17342,18 +17522,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:12190.3-12220.6" - process $proc$libresoc.v:12190$244 + attribute \src "libresoc.v:12370.3-12400.6" + process $proc$libresoc.v:12370$244 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12191.5-12191.29" + attribute \src "libresoc.v:12371.5-12371.29" switch \initial - attribute \src "libresoc.v:12191.9-12191.17" + attribute \src "libresoc.v:12371.9-12371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17393,18 +17573,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:12221.3-12251.6" - process $proc$libresoc.v:12221$245 + attribute \src "libresoc.v:12401.3-12431.6" + process $proc$libresoc.v:12401$245 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12222.5-12222.29" + attribute \src "libresoc.v:12402.5-12402.29" switch \initial - attribute \src "libresoc.v:12222.9-12222.17" + attribute \src "libresoc.v:12402.9-12402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17444,18 +17624,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:12252.3-12282.6" - process $proc$libresoc.v:12252$246 + attribute \src "libresoc.v:12432.3-12462.6" + process $proc$libresoc.v:12432$246 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12253.5-12253.29" + attribute \src "libresoc.v:12433.5-12433.29" switch \initial - attribute \src "libresoc.v:12253.9-12253.17" + attribute \src "libresoc.v:12433.9-12433.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17495,18 +17675,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:12283.3-12313.6" - process $proc$libresoc.v:12283$247 + attribute \src "libresoc.v:12463.3-12493.6" + process $proc$libresoc.v:12463$247 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12284.5-12284.29" + attribute \src "libresoc.v:12464.5-12464.29" switch \initial - attribute \src "libresoc.v:12284.9-12284.17" + attribute \src "libresoc.v:12464.9-12464.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17523,7 +17703,7 @@ module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } @@ -17531,7 +17711,7 @@ module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } @@ -17539,25 +17719,25 @@ module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 case assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 end sync always update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:12314.3-12344.6" - process $proc$libresoc.v:12314$248 + attribute \src "libresoc.v:12494.3-12524.6" + process $proc$libresoc.v:12494$248 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12315.5-12315.29" + attribute \src "libresoc.v:12495.5-12495.29" switch \initial - attribute \src "libresoc.v:12315.9-12315.17" + attribute \src "libresoc.v:12495.9-12495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17597,18 +17777,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:12345.3-12375.6" - process $proc$libresoc.v:12345$249 + attribute \src "libresoc.v:12525.3-12555.6" + process $proc$libresoc.v:12525$249 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:12346.5-12346.29" + attribute \src "libresoc.v:12526.5-12526.29" switch \initial - attribute \src "libresoc.v:12346.9-12346.17" + attribute \src "libresoc.v:12526.9-12526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17648,18 +17828,18 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:12376.3-12406.6" - process $proc$libresoc.v:12376$250 + attribute \src "libresoc.v:12556.3-12586.6" + process $proc$libresoc.v:12556$250 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12377.5-12377.29" + attribute \src "libresoc.v:12557.5-12557.29" switch \initial - attribute \src "libresoc.v:12377.9-12377.17" + attribute \src "libresoc.v:12557.9-12557.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17672,11 +17852,11 @@ module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'10 + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } @@ -17684,7 +17864,7 @@ module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } @@ -17692,7 +17872,7 @@ module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 case assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 end @@ -17701,66 +17881,66 @@ module \LDST_dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:12412.1-13232.10" +attribute \src "libresoc.v:12592.1-13417.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" attribute \generator "nMigen" module \LDST_dec31_dec_sub23 - attribute \src "libresoc.v:12643.3-12691.6" + attribute \src "libresoc.v:12828.3-12876.6" wire $0\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:12986.3-13034.6" + attribute \src "libresoc.v:13171.3-13219.6" wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:13035.3-13083.6" + attribute \src "libresoc.v:13220.3-13268.6" wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:12594.3-12642.6" - wire width 12 $0\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:12888.3-12936.6" + attribute \src "libresoc.v:12779.3-12827.6" + wire width 14 $0\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:13073.3-13121.6" wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:12937.3-12985.6" + attribute \src "libresoc.v:13122.3-13170.6" wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:12839.3-12887.6" + attribute \src "libresoc.v:13024.3-13072.6" wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12741.3-12789.6" + attribute \src "libresoc.v:12926.3-12974.6" wire $0\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:13084.3-13132.6" + attribute \src "libresoc.v:13269.3-13317.6" wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13182.3-13230.6" + attribute \src "libresoc.v:13367.3-13415.6" wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:12790.3-12838.6" + attribute \src "libresoc.v:12975.3-13023.6" wire $0\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12692.3-12740.6" + attribute \src "libresoc.v:12877.3-12925.6" wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:13133.3-13181.6" + attribute \src "libresoc.v:13318.3-13366.6" wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:12413.7-12413.20" + attribute \src "libresoc.v:12593.7-12593.20" wire $0\initial[0:0] - attribute \src "libresoc.v:12643.3-12691.6" + attribute \src "libresoc.v:12828.3-12876.6" wire $1\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:12986.3-13034.6" + attribute \src "libresoc.v:13171.3-13219.6" wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:13035.3-13083.6" + attribute \src "libresoc.v:13220.3-13268.6" wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:12594.3-12642.6" - wire width 12 $1\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:12888.3-12936.6" + attribute \src "libresoc.v:12779.3-12827.6" + wire width 14 $1\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:13073.3-13121.6" wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:12937.3-12985.6" + attribute \src "libresoc.v:13122.3-13170.6" wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:12839.3-12887.6" + attribute \src "libresoc.v:13024.3-13072.6" wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12741.3-12789.6" + attribute \src "libresoc.v:12926.3-12974.6" wire $1\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:13084.3-13132.6" + attribute \src "libresoc.v:13269.3-13317.6" wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13182.3-13230.6" + attribute \src "libresoc.v:13367.3-13415.6" wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:12790.3-12838.6" + attribute \src "libresoc.v:12975.3-13023.6" wire $1\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12692.3-12740.6" + attribute \src "libresoc.v:12877.3-12925.6" wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:13133.3-13181.6" + attribute \src "libresoc.v:13318.3-13366.6" wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -17770,7 +17950,8 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -17778,30 +17959,33 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_dec_sub23_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -17818,7 +18002,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -17894,9 +18078,10 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -17904,126 +18089,126 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_dec_sub23_upd - attribute \src "libresoc.v:12413.7-12413.15" + attribute \src "libresoc.v:12593.7-12593.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:12413.7-12413.20" - process $proc$libresoc.v:12413$265 + attribute \src "libresoc.v:12593.7-12593.20" + process $proc$libresoc.v:12593$265 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:12594.3-12642.6" - process $proc$libresoc.v:12594$252 + attribute \src "libresoc.v:12779.3-12827.6" + process $proc$libresoc.v:12779$252 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub23_function_unit[11:0] $1\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:12595.5-12595.29" + assign $0\LDST_dec31_dec_sub23_function_unit[13:0] $1\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:12780.5-12780.29" switch \initial - attribute \src "libresoc.v:12595.9-12595.17" + attribute \src "libresoc.v:12780.9-12780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000000 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[11:0] + update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:12643.3-12691.6" - process $proc$libresoc.v:12643$253 + attribute \src "libresoc.v:12828.3-12876.6" + process $proc$libresoc.v:12828$253 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:12644.5-12644.29" + attribute \src "libresoc.v:12829.5-12829.29" switch \initial - attribute \src "libresoc.v:12644.9-12644.17" + attribute \src "libresoc.v:12829.9-12829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18087,18 +18272,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:12692.3-12740.6" - process $proc$libresoc.v:12692$254 + attribute \src "libresoc.v:12877.3-12925.6" + process $proc$libresoc.v:12877$254 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:12693.5-12693.29" + attribute \src "libresoc.v:12878.5-12878.29" switch \initial - attribute \src "libresoc.v:12693.9-12693.17" + attribute \src "libresoc.v:12878.9-12878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18162,18 +18347,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:12741.3-12789.6" - process $proc$libresoc.v:12741$255 + attribute \src "libresoc.v:12926.3-12974.6" + process $proc$libresoc.v:12926$255 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:12742.5-12742.29" + attribute \src "libresoc.v:12927.5-12927.29" switch \initial - attribute \src "libresoc.v:12742.9-12742.17" + attribute \src "libresoc.v:12927.9-12927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18237,18 +18422,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:12790.3-12838.6" - process $proc$libresoc.v:12790$256 + attribute \src "libresoc.v:12975.3-13023.6" + process $proc$libresoc.v:12975$256 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12791.5-12791.29" + attribute \src "libresoc.v:12976.5-12976.29" switch \initial - attribute \src "libresoc.v:12791.9-12791.17" + attribute \src "libresoc.v:12976.9-12976.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18312,18 +18497,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:12839.3-12887.6" - process $proc$libresoc.v:12839$257 + attribute \src "libresoc.v:13024.3-13072.6" + process $proc$libresoc.v:13024$257 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12840.5-12840.29" + attribute \src "libresoc.v:13025.5-13025.29" switch \initial - attribute \src "libresoc.v:12840.9-12840.17" + attribute \src "libresoc.v:13025.9-13025.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18387,18 +18572,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:12888.3-12936.6" - process $proc$libresoc.v:12888$258 + attribute \src "libresoc.v:13073.3-13121.6" + process $proc$libresoc.v:13073$258 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:12889.5-12889.29" + attribute \src "libresoc.v:13074.5-13074.29" switch \initial - attribute \src "libresoc.v:12889.9-12889.17" + attribute \src "libresoc.v:13074.9-13074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18462,18 +18647,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:12937.3-12985.6" - process $proc$libresoc.v:12937$259 + attribute \src "libresoc.v:13122.3-13170.6" + process $proc$libresoc.v:13122$259 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:12938.5-12938.29" + attribute \src "libresoc.v:13123.5-13123.29" switch \initial - attribute \src "libresoc.v:12938.9-12938.17" + attribute \src "libresoc.v:13123.9-13123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18537,18 +18722,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:12986.3-13034.6" - process $proc$libresoc.v:12986$260 + attribute \src "libresoc.v:13171.3-13219.6" + process $proc$libresoc.v:13171$260 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:12987.5-12987.29" + attribute \src "libresoc.v:13172.5-13172.29" switch \initial - attribute \src "libresoc.v:12987.9-12987.17" + attribute \src "libresoc.v:13172.9-13172.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18612,18 +18797,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:13035.3-13083.6" - process $proc$libresoc.v:13035$261 + attribute \src "libresoc.v:13220.3-13268.6" + process $proc$libresoc.v:13220$261 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:13036.5-13036.29" + attribute \src "libresoc.v:13221.5-13221.29" switch \initial - attribute \src "libresoc.v:13036.9-13036.17" + attribute \src "libresoc.v:13221.9-13221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18664,7 +18849,7 @@ module \LDST_dec31_dec_sub23 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } @@ -18687,18 +18872,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:13084.3-13132.6" - process $proc$libresoc.v:13084$262 + attribute \src "libresoc.v:13269.3-13317.6" + process $proc$libresoc.v:13269$262 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13085.5-13085.29" + attribute \src "libresoc.v:13270.5-13270.29" switch \initial - attribute \src "libresoc.v:13085.9-13085.17" + attribute \src "libresoc.v:13270.9-13270.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18762,18 +18947,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:13133.3-13181.6" - process $proc$libresoc.v:13133$263 + attribute \src "libresoc.v:13318.3-13366.6" + process $proc$libresoc.v:13318$263 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:13134.5-13134.29" + attribute \src "libresoc.v:13319.5-13319.29" switch \initial - attribute \src "libresoc.v:13134.9-13134.17" + attribute \src "libresoc.v:13319.9-13319.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18837,18 +19022,18 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:13182.3-13230.6" - process $proc$libresoc.v:13182$264 + attribute \src "libresoc.v:13367.3-13415.6" + process $proc$libresoc.v:13367$264 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:13183.5-13183.29" + attribute \src "libresoc.v:13368.5-13368.29" switch \initial - attribute \src "libresoc.v:13183.9-13183.17" + attribute \src "libresoc.v:13368.9-13368.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18889,7 +19074,7 @@ module \LDST_dec31_dec_sub23 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } @@ -18914,66 +19099,66 @@ module \LDST_dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:13236.1-13627.10" +attribute \src "libresoc.v:13421.1-13817.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" attribute \generator "nMigen" module \LDST_dec58 - attribute \src "libresoc.v:13434.3-13449.6" + attribute \src "libresoc.v:13624.3-13639.6" wire $0\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13546.3-13561.6" + attribute \src "libresoc.v:13736.3-13751.6" wire width 3 $0\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13562.3-13577.6" + attribute \src "libresoc.v:13752.3-13767.6" wire width 3 $0\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13418.3-13433.6" - wire width 12 $0\LDST_dec58_function_unit[11:0] - attribute \src "libresoc.v:13514.3-13529.6" + attribute \src "libresoc.v:13608.3-13623.6" + wire width 14 $0\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13704.3-13719.6" wire width 3 $0\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13530.3-13545.6" + attribute \src "libresoc.v:13720.3-13735.6" wire width 4 $0\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13498.3-13513.6" + attribute \src "libresoc.v:13688.3-13703.6" wire width 7 $0\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13466.3-13481.6" + attribute \src "libresoc.v:13656.3-13671.6" wire $0\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13578.3-13593.6" + attribute \src "libresoc.v:13768.3-13783.6" wire width 4 $0\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13610.3-13625.6" + attribute \src "libresoc.v:13800.3-13815.6" wire width 2 $0\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13482.3-13497.6" + attribute \src "libresoc.v:13672.3-13687.6" wire $0\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13450.3-13465.6" + attribute \src "libresoc.v:13640.3-13655.6" wire $0\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13594.3-13609.6" + attribute \src "libresoc.v:13784.3-13799.6" wire width 2 $0\LDST_dec58_upd[1:0] - attribute \src "libresoc.v:13237.7-13237.20" + attribute \src "libresoc.v:13422.7-13422.20" wire $0\initial[0:0] - attribute \src "libresoc.v:13434.3-13449.6" + attribute \src "libresoc.v:13624.3-13639.6" wire $1\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13546.3-13561.6" + attribute \src "libresoc.v:13736.3-13751.6" wire width 3 $1\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13562.3-13577.6" + attribute \src "libresoc.v:13752.3-13767.6" wire width 3 $1\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13418.3-13433.6" - wire width 12 $1\LDST_dec58_function_unit[11:0] - attribute \src "libresoc.v:13514.3-13529.6" + attribute \src "libresoc.v:13608.3-13623.6" + wire width 14 $1\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13704.3-13719.6" wire width 3 $1\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13530.3-13545.6" + attribute \src "libresoc.v:13720.3-13735.6" wire width 4 $1\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13498.3-13513.6" + attribute \src "libresoc.v:13688.3-13703.6" wire width 7 $1\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13466.3-13481.6" + attribute \src "libresoc.v:13656.3-13671.6" wire $1\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13578.3-13593.6" + attribute \src "libresoc.v:13768.3-13783.6" wire width 4 $1\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13610.3-13625.6" + attribute \src "libresoc.v:13800.3-13815.6" wire width 2 $1\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13482.3-13497.6" + attribute \src "libresoc.v:13672.3-13687.6" wire $1\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13450.3-13465.6" + attribute \src "libresoc.v:13640.3-13655.6" wire $1\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13594.3-13609.6" + attribute \src "libresoc.v:13784.3-13799.6" wire width 2 $1\LDST_dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -18983,7 +19168,8 @@ module \LDST_dec58 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -18991,30 +19177,33 @@ module \LDST_dec58 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec58_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec58_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -19031,7 +19220,7 @@ module \LDST_dec58 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -19107,9 +19296,10 @@ module \LDST_dec58 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -19117,82 +19307,82 @@ module \LDST_dec58 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec58_upd - attribute \src "libresoc.v:13237.7-13237.15" + attribute \src "libresoc.v:13422.7-13422.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 2 \opcode_switch - attribute \src "libresoc.v:13237.7-13237.20" - process $proc$libresoc.v:13237$279 + attribute \src "libresoc.v:13422.7-13422.20" + process $proc$libresoc.v:13422$279 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:13418.3-13433.6" - process $proc$libresoc.v:13418$266 + attribute \src "libresoc.v:13608.3-13623.6" + process $proc$libresoc.v:13608$266 assign { } { } assign { } { } - assign $0\LDST_dec58_function_unit[11:0] $1\LDST_dec58_function_unit[11:0] - attribute \src "libresoc.v:13419.5-13419.29" + assign $0\LDST_dec58_function_unit[13:0] $1\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13609.5-13609.29" switch \initial - attribute \src "libresoc.v:13419.9-13419.17" + attribute \src "libresoc.v:13609.9-13609.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec58_function_unit[11:0] 12'000000000000 + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[11:0] + update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[13:0] end - attribute \src "libresoc.v:13434.3-13449.6" - process $proc$libresoc.v:13434$267 + attribute \src "libresoc.v:13624.3-13639.6" + process $proc$libresoc.v:13624$267 assign { } { } assign { } { } assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13435.5-13435.29" + attribute \src "libresoc.v:13625.5-13625.29" switch \initial - attribute \src "libresoc.v:13435.9-13435.17" + attribute \src "libresoc.v:13625.9-13625.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19212,18 +19402,18 @@ module \LDST_dec58 sync always update \LDST_dec58_br $0\LDST_dec58_br[0:0] end - attribute \src "libresoc.v:13450.3-13465.6" - process $proc$libresoc.v:13450$268 + attribute \src "libresoc.v:13640.3-13655.6" + process $proc$libresoc.v:13640$268 assign { } { } assign { } { } assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13451.5-13451.29" + attribute \src "libresoc.v:13641.5-13641.29" switch \initial - attribute \src "libresoc.v:13451.9-13451.17" + attribute \src "libresoc.v:13641.9-13641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19243,18 +19433,18 @@ module \LDST_dec58 sync always update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:13466.3-13481.6" - process $proc$libresoc.v:13466$269 + attribute \src "libresoc.v:13656.3-13671.6" + process $proc$libresoc.v:13656$269 assign { } { } assign { } { } assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13467.5-13467.29" + attribute \src "libresoc.v:13657.5-13657.29" switch \initial - attribute \src "libresoc.v:13467.9-13467.17" + attribute \src "libresoc.v:13657.9-13657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19274,18 +19464,18 @@ module \LDST_dec58 sync always update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] end - attribute \src "libresoc.v:13482.3-13497.6" - process $proc$libresoc.v:13482$270 + attribute \src "libresoc.v:13672.3-13687.6" + process $proc$libresoc.v:13672$270 assign { } { } assign { } { } assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13483.5-13483.29" + attribute \src "libresoc.v:13673.5-13673.29" switch \initial - attribute \src "libresoc.v:13483.9-13483.17" + attribute \src "libresoc.v:13673.9-13673.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19305,18 +19495,18 @@ module \LDST_dec58 sync always update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] end - attribute \src "libresoc.v:13498.3-13513.6" - process $proc$libresoc.v:13498$271 + attribute \src "libresoc.v:13688.3-13703.6" + process $proc$libresoc.v:13688$271 assign { } { } assign { } { } assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13499.5-13499.29" + attribute \src "libresoc.v:13689.5-13689.29" switch \initial - attribute \src "libresoc.v:13499.9-13499.17" + attribute \src "libresoc.v:13689.9-13689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19336,18 +19526,18 @@ module \LDST_dec58 sync always update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] end - attribute \src "libresoc.v:13514.3-13529.6" - process $proc$libresoc.v:13514$272 + attribute \src "libresoc.v:13704.3-13719.6" + process $proc$libresoc.v:13704$272 assign { } { } assign { } { } assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13515.5-13515.29" + attribute \src "libresoc.v:13705.5-13705.29" switch \initial - attribute \src "libresoc.v:13515.9-13515.17" + attribute \src "libresoc.v:13705.9-13705.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19367,18 +19557,18 @@ module \LDST_dec58 sync always update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] end - attribute \src "libresoc.v:13530.3-13545.6" - process $proc$libresoc.v:13530$273 + attribute \src "libresoc.v:13720.3-13735.6" + process $proc$libresoc.v:13720$273 assign { } { } assign { } { } assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13531.5-13531.29" + attribute \src "libresoc.v:13721.5-13721.29" switch \initial - attribute \src "libresoc.v:13531.9-13531.17" + attribute \src "libresoc.v:13721.9-13721.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19398,18 +19588,18 @@ module \LDST_dec58 sync always update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] end - attribute \src "libresoc.v:13546.3-13561.6" - process $proc$libresoc.v:13546$274 + attribute \src "libresoc.v:13736.3-13751.6" + process $proc$libresoc.v:13736$274 assign { } { } assign { } { } assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13547.5-13547.29" + attribute \src "libresoc.v:13737.5-13737.29" switch \initial - attribute \src "libresoc.v:13547.9-13547.17" + attribute \src "libresoc.v:13737.9-13737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19429,18 +19619,18 @@ module \LDST_dec58 sync always update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] end - attribute \src "libresoc.v:13562.3-13577.6" - process $proc$libresoc.v:13562$275 + attribute \src "libresoc.v:13752.3-13767.6" + process $proc$libresoc.v:13752$275 assign { } { } assign { } { } assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13563.5-13563.29" + attribute \src "libresoc.v:13753.5-13753.29" switch \initial - attribute \src "libresoc.v:13563.9-13563.17" + attribute \src "libresoc.v:13753.9-13753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19460,18 +19650,18 @@ module \LDST_dec58 sync always update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] end - attribute \src "libresoc.v:13578.3-13593.6" - process $proc$libresoc.v:13578$276 + attribute \src "libresoc.v:13768.3-13783.6" + process $proc$libresoc.v:13768$276 assign { } { } assign { } { } assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13579.5-13579.29" + attribute \src "libresoc.v:13769.5-13769.29" switch \initial - attribute \src "libresoc.v:13579.9-13579.17" + attribute \src "libresoc.v:13769.9-13769.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19491,18 +19681,18 @@ module \LDST_dec58 sync always update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] end - attribute \src "libresoc.v:13594.3-13609.6" - process $proc$libresoc.v:13594$277 + attribute \src "libresoc.v:13784.3-13799.6" + process $proc$libresoc.v:13784$277 assign { } { } assign { } { } assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] - attribute \src "libresoc.v:13595.5-13595.29" + attribute \src "libresoc.v:13785.5-13785.29" switch \initial - attribute \src "libresoc.v:13595.9-13595.17" + attribute \src "libresoc.v:13785.9-13785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19522,18 +19712,18 @@ module \LDST_dec58 sync always update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] end - attribute \src "libresoc.v:13610.3-13625.6" - process $proc$libresoc.v:13610$278 + attribute \src "libresoc.v:13800.3-13815.6" + process $proc$libresoc.v:13800$278 assign { } { } assign { } { } assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13611.5-13611.29" + attribute \src "libresoc.v:13801.5-13801.29" switch \initial - attribute \src "libresoc.v:13611.9-13611.17" + attribute \src "libresoc.v:13801.9-13801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19555,66 +19745,66 @@ module \LDST_dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:13631.1-13983.10" +attribute \src "libresoc.v:13821.1-14178.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" attribute \generator "nMigen" module \LDST_dec62 - attribute \src "libresoc.v:13826.3-13838.6" + attribute \src "libresoc.v:14021.3-14033.6" wire $0\LDST_dec62_br[0:0] - attribute \src "libresoc.v:13917.3-13929.6" + attribute \src "libresoc.v:14112.3-14124.6" wire width 3 $0\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:13930.3-13942.6" + attribute \src "libresoc.v:14125.3-14137.6" wire width 3 $0\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:13813.3-13825.6" - wire width 12 $0\LDST_dec62_function_unit[11:0] - attribute \src "libresoc.v:13891.3-13903.6" + attribute \src "libresoc.v:14008.3-14020.6" + wire width 14 $0\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14086.3-14098.6" wire width 3 $0\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:13904.3-13916.6" + attribute \src "libresoc.v:14099.3-14111.6" wire width 4 $0\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:13878.3-13890.6" + attribute \src "libresoc.v:14073.3-14085.6" wire width 7 $0\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13852.3-13864.6" + attribute \src "libresoc.v:14047.3-14059.6" wire $0\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:13943.3-13955.6" + attribute \src "libresoc.v:14138.3-14150.6" wire width 4 $0\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:13969.3-13981.6" + attribute \src "libresoc.v:14164.3-14176.6" wire width 2 $0\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:13865.3-13877.6" + attribute \src "libresoc.v:14060.3-14072.6" wire $0\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13839.3-13851.6" + attribute \src "libresoc.v:14034.3-14046.6" wire $0\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:13956.3-13968.6" + attribute \src "libresoc.v:14151.3-14163.6" wire width 2 $0\LDST_dec62_upd[1:0] - attribute \src "libresoc.v:13632.7-13632.20" + attribute \src "libresoc.v:13822.7-13822.20" wire $0\initial[0:0] - attribute \src "libresoc.v:13826.3-13838.6" + attribute \src "libresoc.v:14021.3-14033.6" wire $1\LDST_dec62_br[0:0] - attribute \src "libresoc.v:13917.3-13929.6" + attribute \src "libresoc.v:14112.3-14124.6" wire width 3 $1\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:13930.3-13942.6" + attribute \src "libresoc.v:14125.3-14137.6" wire width 3 $1\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:13813.3-13825.6" - wire width 12 $1\LDST_dec62_function_unit[11:0] - attribute \src "libresoc.v:13891.3-13903.6" + attribute \src "libresoc.v:14008.3-14020.6" + wire width 14 $1\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14086.3-14098.6" wire width 3 $1\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:13904.3-13916.6" + attribute \src "libresoc.v:14099.3-14111.6" wire width 4 $1\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:13878.3-13890.6" + attribute \src "libresoc.v:14073.3-14085.6" wire width 7 $1\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13852.3-13864.6" + attribute \src "libresoc.v:14047.3-14059.6" wire $1\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:13943.3-13955.6" + attribute \src "libresoc.v:14138.3-14150.6" wire width 4 $1\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:13969.3-13981.6" + attribute \src "libresoc.v:14164.3-14176.6" wire width 2 $1\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:13865.3-13877.6" + attribute \src "libresoc.v:14060.3-14072.6" wire $1\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13839.3-13851.6" + attribute \src "libresoc.v:14034.3-14046.6" wire $1\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:13956.3-13968.6" + attribute \src "libresoc.v:14151.3-14163.6" wire width 2 $1\LDST_dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -19624,7 +19814,8 @@ module \LDST_dec62 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -19632,30 +19823,33 @@ module \LDST_dec62 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec62_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec62_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -19672,7 +19866,7 @@ module \LDST_dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -19748,9 +19942,10 @@ module \LDST_dec62 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -19758,78 +19953,78 @@ module \LDST_dec62 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec62_upd - attribute \src "libresoc.v:13632.7-13632.15" + attribute \src "libresoc.v:13822.7-13822.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 2 \opcode_switch - attribute \src "libresoc.v:13632.7-13632.20" - process $proc$libresoc.v:13632$293 + attribute \src "libresoc.v:13822.7-13822.20" + process $proc$libresoc.v:13822$293 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:13813.3-13825.6" - process $proc$libresoc.v:13813$280 + attribute \src "libresoc.v:14008.3-14020.6" + process $proc$libresoc.v:14008$280 assign { } { } assign { } { } - assign $0\LDST_dec62_function_unit[11:0] $1\LDST_dec62_function_unit[11:0] - attribute \src "libresoc.v:13814.5-13814.29" + assign $0\LDST_dec62_function_unit[13:0] $1\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14009.5-14009.29" switch \initial - attribute \src "libresoc.v:13814.9-13814.17" + attribute \src "libresoc.v:14009.9-14009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec62_function_unit[11:0] 12'000000000000 + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[11:0] + update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[13:0] end - attribute \src "libresoc.v:13826.3-13838.6" - process $proc$libresoc.v:13826$281 + attribute \src "libresoc.v:14021.3-14033.6" + process $proc$libresoc.v:14021$281 assign { } { } assign { } { } assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] - attribute \src "libresoc.v:13827.5-13827.29" + attribute \src "libresoc.v:14022.5-14022.29" switch \initial - attribute \src "libresoc.v:13827.9-13827.17" + attribute \src "libresoc.v:14022.9-14022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19845,18 +20040,18 @@ module \LDST_dec62 sync always update \LDST_dec62_br $0\LDST_dec62_br[0:0] end - attribute \src "libresoc.v:13839.3-13851.6" - process $proc$libresoc.v:13839$282 + attribute \src "libresoc.v:14034.3-14046.6" + process $proc$libresoc.v:14034$282 assign { } { } assign { } { } assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:13840.5-13840.29" + attribute \src "libresoc.v:14035.5-14035.29" switch \initial - attribute \src "libresoc.v:13840.9-13840.17" + attribute \src "libresoc.v:14035.9-14035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19872,18 +20067,18 @@ module \LDST_dec62 sync always update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:13852.3-13864.6" - process $proc$libresoc.v:13852$283 + attribute \src "libresoc.v:14047.3-14059.6" + process $proc$libresoc.v:14047$283 assign { } { } assign { } { } assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:13853.5-13853.29" + attribute \src "libresoc.v:14048.5-14048.29" switch \initial - attribute \src "libresoc.v:13853.9-13853.17" + attribute \src "libresoc.v:14048.9-14048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19899,18 +20094,18 @@ module \LDST_dec62 sync always update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] end - attribute \src "libresoc.v:13865.3-13877.6" - process $proc$libresoc.v:13865$284 + attribute \src "libresoc.v:14060.3-14072.6" + process $proc$libresoc.v:14060$284 assign { } { } assign { } { } assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13866.5-13866.29" + attribute \src "libresoc.v:14061.5-14061.29" switch \initial - attribute \src "libresoc.v:13866.9-13866.17" + attribute \src "libresoc.v:14061.9-14061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19926,18 +20121,18 @@ module \LDST_dec62 sync always update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] end - attribute \src "libresoc.v:13878.3-13890.6" - process $proc$libresoc.v:13878$285 + attribute \src "libresoc.v:14073.3-14085.6" + process $proc$libresoc.v:14073$285 assign { } { } assign { } { } assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13879.5-13879.29" + attribute \src "libresoc.v:14074.5-14074.29" switch \initial - attribute \src "libresoc.v:13879.9-13879.17" + attribute \src "libresoc.v:14074.9-14074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19953,18 +20148,18 @@ module \LDST_dec62 sync always update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] end - attribute \src "libresoc.v:13891.3-13903.6" - process $proc$libresoc.v:13891$286 + attribute \src "libresoc.v:14086.3-14098.6" + process $proc$libresoc.v:14086$286 assign { } { } assign { } { } assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:13892.5-13892.29" + attribute \src "libresoc.v:14087.5-14087.29" switch \initial - attribute \src "libresoc.v:13892.9-13892.17" + attribute \src "libresoc.v:14087.9-14087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19980,18 +20175,18 @@ module \LDST_dec62 sync always update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] end - attribute \src "libresoc.v:13904.3-13916.6" - process $proc$libresoc.v:13904$287 + attribute \src "libresoc.v:14099.3-14111.6" + process $proc$libresoc.v:14099$287 assign { } { } assign { } { } assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:13905.5-13905.29" + attribute \src "libresoc.v:14100.5-14100.29" switch \initial - attribute \src "libresoc.v:13905.9-13905.17" + attribute \src "libresoc.v:14100.9-14100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20007,18 +20202,18 @@ module \LDST_dec62 sync always update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] end - attribute \src "libresoc.v:13917.3-13929.6" - process $proc$libresoc.v:13917$288 + attribute \src "libresoc.v:14112.3-14124.6" + process $proc$libresoc.v:14112$288 assign { } { } assign { } { } assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:13918.5-13918.29" + attribute \src "libresoc.v:14113.5-14113.29" switch \initial - attribute \src "libresoc.v:13918.9-13918.17" + attribute \src "libresoc.v:14113.9-14113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20034,18 +20229,18 @@ module \LDST_dec62 sync always update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] end - attribute \src "libresoc.v:13930.3-13942.6" - process $proc$libresoc.v:13930$289 + attribute \src "libresoc.v:14125.3-14137.6" + process $proc$libresoc.v:14125$289 assign { } { } assign { } { } assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:13931.5-13931.29" + attribute \src "libresoc.v:14126.5-14126.29" switch \initial - attribute \src "libresoc.v:13931.9-13931.17" + attribute \src "libresoc.v:14126.9-14126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20061,18 +20256,18 @@ module \LDST_dec62 sync always update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] end - attribute \src "libresoc.v:13943.3-13955.6" - process $proc$libresoc.v:13943$290 + attribute \src "libresoc.v:14138.3-14150.6" + process $proc$libresoc.v:14138$290 assign { } { } assign { } { } assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:13944.5-13944.29" + attribute \src "libresoc.v:14139.5-14139.29" switch \initial - attribute \src "libresoc.v:13944.9-13944.17" + attribute \src "libresoc.v:14139.9-14139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20088,18 +20283,18 @@ module \LDST_dec62 sync always update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] end - attribute \src "libresoc.v:13956.3-13968.6" - process $proc$libresoc.v:13956$291 + attribute \src "libresoc.v:14151.3-14163.6" + process $proc$libresoc.v:14151$291 assign { } { } assign { } { } assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] - attribute \src "libresoc.v:13957.5-13957.29" + attribute \src "libresoc.v:14152.5-14152.29" switch \initial - attribute \src "libresoc.v:13957.9-13957.17" + attribute \src "libresoc.v:14152.9-14152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20115,18 +20310,18 @@ module \LDST_dec62 sync always update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] end - attribute \src "libresoc.v:13969.3-13981.6" - process $proc$libresoc.v:13969$292 + attribute \src "libresoc.v:14164.3-14176.6" + process $proc$libresoc.v:14164$292 assign { } { } assign { } { } assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:13970.5-13970.29" + attribute \src "libresoc.v:14165.5-14165.29" switch \initial - attribute \src "libresoc.v:13970.9-13970.17" + attribute \src "libresoc.v:14165.9-14165.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20144,68 +20339,68 @@ module \LDST_dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:13987.1-14725.10" +attribute \src "libresoc.v:14182.1-14935.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" attribute \generator "nMigen" module \LOGICAL_dec31 - attribute \src "libresoc.v:14695.3-14707.6" + attribute \src "libresoc.v:14905.3-14917.6" wire width 3 $0\LOGICAL_dec31_cr_in[2:0] - attribute \src "libresoc.v:14708.3-14720.6" + attribute \src "libresoc.v:14918.3-14930.6" wire width 3 $0\LOGICAL_dec31_cr_out[2:0] - attribute \src "libresoc.v:14565.3-14577.6" + attribute \src "libresoc.v:14775.3-14787.6" wire width 2 $0\LOGICAL_dec31_cry_in[1:0] - attribute \src "libresoc.v:14604.3-14616.6" + attribute \src "libresoc.v:14814.3-14826.6" wire $0\LOGICAL_dec31_cry_out[0:0] - attribute \src "libresoc.v:14643.3-14655.6" - wire width 12 $0\LOGICAL_dec31_function_unit[11:0] - attribute \src "libresoc.v:14669.3-14681.6" + attribute \src "libresoc.v:14853.3-14865.6" + wire width 14 $0\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14879.3-14891.6" wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] - attribute \src "libresoc.v:14682.3-14694.6" + attribute \src "libresoc.v:14892.3-14904.6" wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:14656.3-14668.6" + attribute \src "libresoc.v:14866.3-14878.6" wire width 7 $0\LOGICAL_dec31_internal_op[6:0] - attribute \src "libresoc.v:14578.3-14590.6" + attribute \src "libresoc.v:14788.3-14800.6" wire $0\LOGICAL_dec31_inv_a[0:0] - attribute \src "libresoc.v:14591.3-14603.6" + attribute \src "libresoc.v:14801.3-14813.6" wire $0\LOGICAL_dec31_inv_out[0:0] - attribute \src "libresoc.v:14617.3-14629.6" + attribute \src "libresoc.v:14827.3-14839.6" wire $0\LOGICAL_dec31_is_32b[0:0] - attribute \src "libresoc.v:14539.3-14551.6" + attribute \src "libresoc.v:14749.3-14761.6" wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] - attribute \src "libresoc.v:14552.3-14564.6" + attribute \src "libresoc.v:14762.3-14774.6" wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:14630.3-14642.6" + attribute \src "libresoc.v:14840.3-14852.6" wire $0\LOGICAL_dec31_sgn[0:0] - attribute \src "libresoc.v:13988.7-13988.20" + attribute \src "libresoc.v:14183.7-14183.20" wire $0\initial[0:0] - attribute \src "libresoc.v:14695.3-14707.6" + attribute \src "libresoc.v:14905.3-14917.6" wire width 3 $1\LOGICAL_dec31_cr_in[2:0] - attribute \src "libresoc.v:14708.3-14720.6" + attribute \src "libresoc.v:14918.3-14930.6" wire width 3 $1\LOGICAL_dec31_cr_out[2:0] - attribute \src "libresoc.v:14565.3-14577.6" + attribute \src "libresoc.v:14775.3-14787.6" wire width 2 $1\LOGICAL_dec31_cry_in[1:0] - attribute \src "libresoc.v:14604.3-14616.6" + attribute \src "libresoc.v:14814.3-14826.6" wire $1\LOGICAL_dec31_cry_out[0:0] - attribute \src "libresoc.v:14643.3-14655.6" - wire width 12 $1\LOGICAL_dec31_function_unit[11:0] - attribute \src "libresoc.v:14669.3-14681.6" + attribute \src "libresoc.v:14853.3-14865.6" + wire width 14 $1\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14879.3-14891.6" wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] - attribute \src "libresoc.v:14682.3-14694.6" + attribute \src "libresoc.v:14892.3-14904.6" wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:14656.3-14668.6" + attribute \src "libresoc.v:14866.3-14878.6" wire width 7 $1\LOGICAL_dec31_internal_op[6:0] - attribute \src "libresoc.v:14578.3-14590.6" + attribute \src "libresoc.v:14788.3-14800.6" wire $1\LOGICAL_dec31_inv_a[0:0] - attribute \src "libresoc.v:14591.3-14603.6" + attribute \src "libresoc.v:14801.3-14813.6" wire $1\LOGICAL_dec31_inv_out[0:0] - attribute \src "libresoc.v:14617.3-14629.6" + attribute \src "libresoc.v:14827.3-14839.6" wire $1\LOGICAL_dec31_is_32b[0:0] - attribute \src "libresoc.v:14539.3-14551.6" + attribute \src "libresoc.v:14749.3-14761.6" wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] - attribute \src "libresoc.v:14552.3-14564.6" + attribute \src "libresoc.v:14762.3-14774.6" wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:14630.3-14642.6" + attribute \src "libresoc.v:14840.3-14852.6" wire $1\LOGICAL_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20215,7 +20410,8 @@ module \LOGICAL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20223,15 +20419,16 @@ module \LOGICAL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LOGICAL_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LOGICAL_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20241,7 +20438,8 @@ module \LOGICAL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20249,38 +20447,41 @@ module \LOGICAL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20297,7 +20498,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20373,13 +20574,14 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20387,17 +20589,17 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20407,7 +20609,8 @@ module \LOGICAL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20415,38 +20618,41 @@ module \LOGICAL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20463,7 +20669,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20539,13 +20745,14 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20553,40 +20760,42 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LOGICAL_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20603,7 +20812,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20679,13 +20888,14 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LOGICAL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LOGICAL_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LOGICAL_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20693,26 +20903,26 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LOGICAL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \LOGICAL_dec31_sgn - attribute \src "libresoc.v:13988.7-13988.15" + attribute \src "libresoc.v:14183.7-14183.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:14505.27-14521.4" + attribute \src "libresoc.v:14715.27-14731.4" cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out @@ -20731,7 +20941,7 @@ module \LOGICAL_dec31 connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:14522.27-14538.4" + attribute \src "libresoc.v:14732.27-14748.4" cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out @@ -20749,26 +20959,26 @@ module \LOGICAL_dec31 connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in end - attribute \src "libresoc.v:13988.7-13988.20" - process $proc$libresoc.v:13988$308 + attribute \src "libresoc.v:14183.7-14183.20" + process $proc$libresoc.v:14183$308 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:14539.3-14551.6" - process $proc$libresoc.v:14539$294 + attribute \src "libresoc.v:14749.3-14761.6" + process $proc$libresoc.v:14749$294 assign { } { } assign { } { } assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] - attribute \src "libresoc.v:14540.5-14540.29" + attribute \src "libresoc.v:14750.5-14750.29" switch \initial - attribute \src "libresoc.v:14540.9-14540.17" + attribute \src "libresoc.v:14750.9-14750.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20784,18 +20994,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] end - attribute \src "libresoc.v:14552.3-14564.6" - process $proc$libresoc.v:14552$295 + attribute \src "libresoc.v:14762.3-14774.6" + process $proc$libresoc.v:14762$295 assign { } { } assign { } { } assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:14553.5-14553.29" + attribute \src "libresoc.v:14763.5-14763.29" switch \initial - attribute \src "libresoc.v:14553.9-14553.17" + attribute \src "libresoc.v:14763.9-14763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20811,18 +21021,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:14565.3-14577.6" - process $proc$libresoc.v:14565$296 + attribute \src "libresoc.v:14775.3-14787.6" + process $proc$libresoc.v:14775$296 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] - attribute \src "libresoc.v:14566.5-14566.29" + attribute \src "libresoc.v:14776.5-14776.29" switch \initial - attribute \src "libresoc.v:14566.9-14566.17" + attribute \src "libresoc.v:14776.9-14776.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20838,18 +21048,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] end - attribute \src "libresoc.v:14578.3-14590.6" - process $proc$libresoc.v:14578$297 + attribute \src "libresoc.v:14788.3-14800.6" + process $proc$libresoc.v:14788$297 assign { } { } assign { } { } assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] - attribute \src "libresoc.v:14579.5-14579.29" + attribute \src "libresoc.v:14789.5-14789.29" switch \initial - attribute \src "libresoc.v:14579.9-14579.17" + attribute \src "libresoc.v:14789.9-14789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20865,18 +21075,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] end - attribute \src "libresoc.v:14591.3-14603.6" - process $proc$libresoc.v:14591$298 + attribute \src "libresoc.v:14801.3-14813.6" + process $proc$libresoc.v:14801$298 assign { } { } assign { } { } assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] - attribute \src "libresoc.v:14592.5-14592.29" + attribute \src "libresoc.v:14802.5-14802.29" switch \initial - attribute \src "libresoc.v:14592.9-14592.17" + attribute \src "libresoc.v:14802.9-14802.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20892,18 +21102,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] end - attribute \src "libresoc.v:14604.3-14616.6" - process $proc$libresoc.v:14604$299 + attribute \src "libresoc.v:14814.3-14826.6" + process $proc$libresoc.v:14814$299 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] - attribute \src "libresoc.v:14605.5-14605.29" + attribute \src "libresoc.v:14815.5-14815.29" switch \initial - attribute \src "libresoc.v:14605.9-14605.17" + attribute \src "libresoc.v:14815.9-14815.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20919,18 +21129,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] end - attribute \src "libresoc.v:14617.3-14629.6" - process $proc$libresoc.v:14617$300 + attribute \src "libresoc.v:14827.3-14839.6" + process $proc$libresoc.v:14827$300 assign { } { } assign { } { } assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] - attribute \src "libresoc.v:14618.5-14618.29" + attribute \src "libresoc.v:14828.5-14828.29" switch \initial - attribute \src "libresoc.v:14618.9-14618.17" + attribute \src "libresoc.v:14828.9-14828.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20946,18 +21156,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] end - attribute \src "libresoc.v:14630.3-14642.6" - process $proc$libresoc.v:14630$301 + attribute \src "libresoc.v:14840.3-14852.6" + process $proc$libresoc.v:14840$301 assign { } { } assign { } { } assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] - attribute \src "libresoc.v:14631.5-14631.29" + attribute \src "libresoc.v:14841.5-14841.29" switch \initial - attribute \src "libresoc.v:14631.9-14631.17" + attribute \src "libresoc.v:14841.9-14841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20973,45 +21183,45 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] end - attribute \src "libresoc.v:14643.3-14655.6" - process $proc$libresoc.v:14643$302 + attribute \src "libresoc.v:14853.3-14865.6" + process $proc$libresoc.v:14853$302 assign { } { } assign { } { } - assign $0\LOGICAL_dec31_function_unit[11:0] $1\LOGICAL_dec31_function_unit[11:0] - attribute \src "libresoc.v:14644.5-14644.29" + assign $0\LOGICAL_dec31_function_unit[13:0] $1\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14854.5-14854.29" switch \initial - attribute \src "libresoc.v:14644.9-14644.17" + attribute \src "libresoc.v:14854.9-14854.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + assign $1\LOGICAL_dec31_function_unit[13:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + assign $1\LOGICAL_dec31_function_unit[13:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit case - assign $1\LOGICAL_dec31_function_unit[11:0] 12'000000000000 + assign $1\LOGICAL_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[11:0] + update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[13:0] end - attribute \src "libresoc.v:14656.3-14668.6" - process $proc$libresoc.v:14656$303 + attribute \src "libresoc.v:14866.3-14878.6" + process $proc$libresoc.v:14866$303 assign { } { } assign { } { } assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] - attribute \src "libresoc.v:14657.5-14657.29" + attribute \src "libresoc.v:14867.5-14867.29" switch \initial - attribute \src "libresoc.v:14657.9-14657.17" + attribute \src "libresoc.v:14867.9-14867.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21027,18 +21237,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] end - attribute \src "libresoc.v:14669.3-14681.6" - process $proc$libresoc.v:14669$304 + attribute \src "libresoc.v:14879.3-14891.6" + process $proc$libresoc.v:14879$304 assign { } { } assign { } { } assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] - attribute \src "libresoc.v:14670.5-14670.29" + attribute \src "libresoc.v:14880.5-14880.29" switch \initial - attribute \src "libresoc.v:14670.9-14670.17" + attribute \src "libresoc.v:14880.9-14880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21054,18 +21264,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] end - attribute \src "libresoc.v:14682.3-14694.6" - process $proc$libresoc.v:14682$305 + attribute \src "libresoc.v:14892.3-14904.6" + process $proc$libresoc.v:14892$305 assign { } { } assign { } { } assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:14683.5-14683.29" + attribute \src "libresoc.v:14893.5-14893.29" switch \initial - attribute \src "libresoc.v:14683.9-14683.17" + attribute \src "libresoc.v:14893.9-14893.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21081,18 +21291,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:14695.3-14707.6" - process $proc$libresoc.v:14695$306 + attribute \src "libresoc.v:14905.3-14917.6" + process $proc$libresoc.v:14905$306 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] - attribute \src "libresoc.v:14696.5-14696.29" + attribute \src "libresoc.v:14906.5-14906.29" switch \initial - attribute \src "libresoc.v:14696.9-14696.17" + attribute \src "libresoc.v:14906.9-14906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21108,18 +21318,18 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] end - attribute \src "libresoc.v:14708.3-14720.6" - process $proc$libresoc.v:14708$307 + attribute \src "libresoc.v:14918.3-14930.6" + process $proc$libresoc.v:14918$307 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] - attribute \src "libresoc.v:14709.5-14709.29" + attribute \src "libresoc.v:14919.5-14919.29" switch \initial - attribute \src "libresoc.v:14709.9-14709.17" + attribute \src "libresoc.v:14919.9-14919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21140,68 +21350,68 @@ module \LOGICAL_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:14729.1-15390.10" +attribute \src "libresoc.v:14939.1-15605.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" attribute \generator "nMigen" module \LOGICAL_dec31_dec_sub26 - attribute \src "libresoc.v:15219.3-15252.6" + attribute \src "libresoc.v:15434.3-15467.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15253.3-15286.6" + attribute \src "libresoc.v:15468.3-15501.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15355.3-15388.6" + attribute \src "libresoc.v:15570.3-15603.6" wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15015.3-15048.6" + attribute \src "libresoc.v:15230.3-15263.6" wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:14913.3-14946.6" - wire width 12 $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:15151.3-15184.6" + attribute \src "libresoc.v:15128.3-15161.6" + wire width 14 $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15366.3-15399.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15185.3-15218.6" + attribute \src "libresoc.v:15400.3-15433.6" wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15117.3-15150.6" + attribute \src "libresoc.v:15332.3-15365.6" wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:14947.3-14980.6" + attribute \src "libresoc.v:15162.3-15195.6" wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:14981.3-15014.6" + attribute \src "libresoc.v:15196.3-15229.6" wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:15049.3-15082.6" + attribute \src "libresoc.v:15264.3-15297.6" wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15287.3-15320.6" + attribute \src "libresoc.v:15502.3-15535.6" wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15321.3-15354.6" + attribute \src "libresoc.v:15536.3-15569.6" wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15083.3-15116.6" + attribute \src "libresoc.v:15298.3-15331.6" wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:14730.7-14730.20" + attribute \src "libresoc.v:14940.7-14940.20" wire $0\initial[0:0] - attribute \src "libresoc.v:15219.3-15252.6" + attribute \src "libresoc.v:15434.3-15467.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15253.3-15286.6" + attribute \src "libresoc.v:15468.3-15501.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15355.3-15388.6" + attribute \src "libresoc.v:15570.3-15603.6" wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15015.3-15048.6" + attribute \src "libresoc.v:15230.3-15263.6" wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:14913.3-14946.6" - wire width 12 $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:15151.3-15184.6" + attribute \src "libresoc.v:15128.3-15161.6" + wire width 14 $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15366.3-15399.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15185.3-15218.6" + attribute \src "libresoc.v:15400.3-15433.6" wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15117.3-15150.6" + attribute \src "libresoc.v:15332.3-15365.6" wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:14947.3-14980.6" + attribute \src "libresoc.v:15162.3-15195.6" wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:14981.3-15014.6" + attribute \src "libresoc.v:15196.3-15229.6" wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:15049.3-15082.6" + attribute \src "libresoc.v:15264.3-15297.6" wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15287.3-15320.6" + attribute \src "libresoc.v:15502.3-15535.6" wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15321.3-15354.6" + attribute \src "libresoc.v:15536.3-15569.6" wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15083.3-15116.6" + attribute \src "libresoc.v:15298.3-15331.6" wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -21211,7 +21421,8 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -21219,38 +21430,41 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -21267,7 +21481,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -21343,13 +21557,14 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -21357,97 +21572,97 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \LOGICAL_dec31_dec_sub26_sgn - attribute \src "libresoc.v:14730.7-14730.15" + attribute \src "libresoc.v:14940.7-14940.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:14730.7-14730.20" - process $proc$libresoc.v:14730$323 + attribute \src "libresoc.v:14940.7-14940.20" + process $proc$libresoc.v:14940$323 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:14913.3-14946.6" - process $proc$libresoc.v:14913$309 + attribute \src "libresoc.v:15128.3-15161.6" + process $proc$libresoc.v:15128$309 assign { } { } assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:14914.5-14914.29" + assign $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15129.5-15129.29" switch \initial - attribute \src "libresoc.v:14914.9-14914.17" + attribute \src "libresoc.v:15129.9-15129.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 case - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always - update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] + update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:14947.3-14980.6" - process $proc$libresoc.v:14947$310 + attribute \src "libresoc.v:15162.3-15195.6" + process $proc$libresoc.v:15162$310 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:14948.5-14948.29" + attribute \src "libresoc.v:15163.5-15163.29" switch \initial - attribute \src "libresoc.v:14948.9-14948.17" + attribute \src "libresoc.v:15163.9-15163.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21491,18 +21706,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:14981.3-15014.6" - process $proc$libresoc.v:14981$311 + attribute \src "libresoc.v:15196.3-15229.6" + process $proc$libresoc.v:15196$311 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:14982.5-14982.29" + attribute \src "libresoc.v:15197.5-15197.29" switch \initial - attribute \src "libresoc.v:14982.9-14982.17" + attribute \src "libresoc.v:15197.9-15197.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21546,18 +21761,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:15015.3-15048.6" - process $proc$libresoc.v:15015$312 + attribute \src "libresoc.v:15230.3-15263.6" + process $proc$libresoc.v:15230$312 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:15016.5-15016.29" + attribute \src "libresoc.v:15231.5-15231.29" switch \initial - attribute \src "libresoc.v:15016.9-15016.17" + attribute \src "libresoc.v:15231.9-15231.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21601,18 +21816,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:15049.3-15082.6" - process $proc$libresoc.v:15049$313 + attribute \src "libresoc.v:15264.3-15297.6" + process $proc$libresoc.v:15264$313 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15050.5-15050.29" + attribute \src "libresoc.v:15265.5-15265.29" switch \initial - attribute \src "libresoc.v:15050.9-15050.17" + attribute \src "libresoc.v:15265.9-15265.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21656,18 +21871,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:15083.3-15116.6" - process $proc$libresoc.v:15083$314 + attribute \src "libresoc.v:15298.3-15331.6" + process $proc$libresoc.v:15298$314 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:15084.5-15084.29" + attribute \src "libresoc.v:15299.5-15299.29" switch \initial - attribute \src "libresoc.v:15084.9-15084.17" + attribute \src "libresoc.v:15299.9-15299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21711,18 +21926,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:15117.3-15150.6" - process $proc$libresoc.v:15117$315 + attribute \src "libresoc.v:15332.3-15365.6" + process $proc$libresoc.v:15332$315 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:15118.5-15118.29" + attribute \src "libresoc.v:15333.5-15333.29" switch \initial - attribute \src "libresoc.v:15118.9-15118.17" + attribute \src "libresoc.v:15333.9-15333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21766,18 +21981,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:15151.3-15184.6" - process $proc$libresoc.v:15151$316 + attribute \src "libresoc.v:15366.3-15399.6" + process $proc$libresoc.v:15366$316 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15152.5-15152.29" + attribute \src "libresoc.v:15367.5-15367.29" switch \initial - attribute \src "libresoc.v:15152.9-15152.17" + attribute \src "libresoc.v:15367.9-15367.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21821,18 +22036,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:15185.3-15218.6" - process $proc$libresoc.v:15185$317 + attribute \src "libresoc.v:15400.3-15433.6" + process $proc$libresoc.v:15400$317 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15186.5-15186.29" + attribute \src "libresoc.v:15401.5-15401.29" switch \initial - attribute \src "libresoc.v:15186.9-15186.17" + attribute \src "libresoc.v:15401.9-15401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21876,18 +22091,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:15219.3-15252.6" - process $proc$libresoc.v:15219$318 + attribute \src "libresoc.v:15434.3-15467.6" + process $proc$libresoc.v:15434$318 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15220.5-15220.29" + attribute \src "libresoc.v:15435.5-15435.29" switch \initial - attribute \src "libresoc.v:15220.9-15220.17" + attribute \src "libresoc.v:15435.9-15435.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21931,18 +22146,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:15253.3-15286.6" - process $proc$libresoc.v:15253$319 + attribute \src "libresoc.v:15468.3-15501.6" + process $proc$libresoc.v:15468$319 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15254.5-15254.29" + attribute \src "libresoc.v:15469.5-15469.29" switch \initial - attribute \src "libresoc.v:15254.9-15254.17" + attribute \src "libresoc.v:15469.9-15469.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21986,18 +22201,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:15287.3-15320.6" - process $proc$libresoc.v:15287$320 + attribute \src "libresoc.v:15502.3-15535.6" + process $proc$libresoc.v:15502$320 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15288.5-15288.29" + attribute \src "libresoc.v:15503.5-15503.29" switch \initial - attribute \src "libresoc.v:15288.9-15288.17" + attribute \src "libresoc.v:15503.9-15503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22041,18 +22256,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:15321.3-15354.6" - process $proc$libresoc.v:15321$321 + attribute \src "libresoc.v:15536.3-15569.6" + process $proc$libresoc.v:15536$321 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15322.5-15322.29" + attribute \src "libresoc.v:15537.5-15537.29" switch \initial - attribute \src "libresoc.v:15322.9-15322.17" + attribute \src "libresoc.v:15537.9-15537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22096,18 +22311,18 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:15355.3-15388.6" - process $proc$libresoc.v:15355$322 + attribute \src "libresoc.v:15570.3-15603.6" + process $proc$libresoc.v:15570$322 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15356.5-15356.29" + attribute \src "libresoc.v:15571.5-15571.29" switch \initial - attribute \src "libresoc.v:15356.9-15356.17" + attribute \src "libresoc.v:15571.9-15571.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22153,68 +22368,68 @@ module \LOGICAL_dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:15394.1-16097.10" +attribute \src "libresoc.v:15609.1-16317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" attribute \generator "nMigen" module \LOGICAL_dec31_dec_sub28 - attribute \src "libresoc.v:15911.3-15947.6" + attribute \src "libresoc.v:16131.3-16167.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:15948.3-15984.6" + attribute \src "libresoc.v:16168.3-16204.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:16059.3-16095.6" + attribute \src "libresoc.v:16279.3-16315.6" wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:15689.3-15725.6" + attribute \src "libresoc.v:15909.3-15945.6" wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15578.3-15614.6" - wire width 12 $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:15837.3-15873.6" + attribute \src "libresoc.v:15798.3-15834.6" + wire width 14 $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:16057.3-16093.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:15874.3-15910.6" + attribute \src "libresoc.v:16094.3-16130.6" wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:15800.3-15836.6" + attribute \src "libresoc.v:16020.3-16056.6" wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15615.3-15651.6" + attribute \src "libresoc.v:15835.3-15871.6" wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15652.3-15688.6" + attribute \src "libresoc.v:15872.3-15908.6" wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15726.3-15762.6" + attribute \src "libresoc.v:15946.3-15982.6" wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:15985.3-16021.6" + attribute \src "libresoc.v:16205.3-16241.6" wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:16022.3-16058.6" + attribute \src "libresoc.v:16242.3-16278.6" wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:15763.3-15799.6" + attribute \src "libresoc.v:15983.3-16019.6" wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:15395.7-15395.20" + attribute \src "libresoc.v:15610.7-15610.20" wire $0\initial[0:0] - attribute \src "libresoc.v:15911.3-15947.6" + attribute \src "libresoc.v:16131.3-16167.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:15948.3-15984.6" + attribute \src "libresoc.v:16168.3-16204.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:16059.3-16095.6" + attribute \src "libresoc.v:16279.3-16315.6" wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:15689.3-15725.6" + attribute \src "libresoc.v:15909.3-15945.6" wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15578.3-15614.6" - wire width 12 $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:15837.3-15873.6" + attribute \src "libresoc.v:15798.3-15834.6" + wire width 14 $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:16057.3-16093.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:15874.3-15910.6" + attribute \src "libresoc.v:16094.3-16130.6" wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:15800.3-15836.6" + attribute \src "libresoc.v:16020.3-16056.6" wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15615.3-15651.6" + attribute \src "libresoc.v:15835.3-15871.6" wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15652.3-15688.6" + attribute \src "libresoc.v:15872.3-15908.6" wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15726.3-15762.6" + attribute \src "libresoc.v:15946.3-15982.6" wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:15985.3-16021.6" + attribute \src "libresoc.v:16205.3-16241.6" wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:16022.3-16058.6" + attribute \src "libresoc.v:16242.3-16278.6" wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:15763.3-15799.6" + attribute \src "libresoc.v:15983.3-16019.6" wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -22224,7 +22439,8 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -22232,38 +22448,41 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -22280,7 +22499,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -22356,13 +22575,14 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -22370,101 +22590,101 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \LOGICAL_dec31_dec_sub28_sgn - attribute \src "libresoc.v:15395.7-15395.15" + attribute \src "libresoc.v:15610.7-15610.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:15395.7-15395.20" - process $proc$libresoc.v:15395$338 + attribute \src "libresoc.v:15610.7-15610.20" + process $proc$libresoc.v:15610$338 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:15578.3-15614.6" - process $proc$libresoc.v:15578$324 + attribute \src "libresoc.v:15798.3-15834.6" + process $proc$libresoc.v:15798$324 assign { } { } assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:15579.5-15579.29" + assign $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:15799.5-15799.29" switch \initial - attribute \src "libresoc.v:15579.9-15579.17" + attribute \src "libresoc.v:15799.9-15799.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 case - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000000000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000000000 end sync always - update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] + update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:15615.3-15651.6" - process $proc$libresoc.v:15615$325 + attribute \src "libresoc.v:15835.3-15871.6" + process $proc$libresoc.v:15835$325 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15616.5-15616.29" + attribute \src "libresoc.v:15836.5-15836.29" switch \initial - attribute \src "libresoc.v:15616.9-15616.17" + attribute \src "libresoc.v:15836.9-15836.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22512,18 +22732,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:15652.3-15688.6" - process $proc$libresoc.v:15652$326 + attribute \src "libresoc.v:15872.3-15908.6" + process $proc$libresoc.v:15872$326 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15653.5-15653.29" + attribute \src "libresoc.v:15873.5-15873.29" switch \initial - attribute \src "libresoc.v:15653.9-15653.17" + attribute \src "libresoc.v:15873.9-15873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22571,18 +22791,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:15689.3-15725.6" - process $proc$libresoc.v:15689$327 + attribute \src "libresoc.v:15909.3-15945.6" + process $proc$libresoc.v:15909$327 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15690.5-15690.29" + attribute \src "libresoc.v:15910.5-15910.29" switch \initial - attribute \src "libresoc.v:15690.9-15690.17" + attribute \src "libresoc.v:15910.9-15910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22630,18 +22850,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:15726.3-15762.6" - process $proc$libresoc.v:15726$328 + attribute \src "libresoc.v:15946.3-15982.6" + process $proc$libresoc.v:15946$328 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:15727.5-15727.29" + attribute \src "libresoc.v:15947.5-15947.29" switch \initial - attribute \src "libresoc.v:15727.9-15727.17" + attribute \src "libresoc.v:15947.9-15947.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22689,18 +22909,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:15763.3-15799.6" - process $proc$libresoc.v:15763$329 + attribute \src "libresoc.v:15983.3-16019.6" + process $proc$libresoc.v:15983$329 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:15764.5-15764.29" + attribute \src "libresoc.v:15984.5-15984.29" switch \initial - attribute \src "libresoc.v:15764.9-15764.17" + attribute \src "libresoc.v:15984.9-15984.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22748,18 +22968,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:15800.3-15836.6" - process $proc$libresoc.v:15800$330 + attribute \src "libresoc.v:16020.3-16056.6" + process $proc$libresoc.v:16020$330 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15801.5-15801.29" + attribute \src "libresoc.v:16021.5-16021.29" switch \initial - attribute \src "libresoc.v:15801.9-15801.17" + attribute \src "libresoc.v:16021.9-16021.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22807,18 +23027,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:15837.3-15873.6" - process $proc$libresoc.v:15837$331 + attribute \src "libresoc.v:16057.3-16093.6" + process $proc$libresoc.v:16057$331 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:15838.5-15838.29" + attribute \src "libresoc.v:16058.5-16058.29" switch \initial - attribute \src "libresoc.v:15838.9-15838.17" + attribute \src "libresoc.v:16058.9-16058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22866,18 +23086,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:15874.3-15910.6" - process $proc$libresoc.v:15874$332 + attribute \src "libresoc.v:16094.3-16130.6" + process $proc$libresoc.v:16094$332 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:15875.5-15875.29" + attribute \src "libresoc.v:16095.5-16095.29" switch \initial - attribute \src "libresoc.v:15875.9-15875.17" + attribute \src "libresoc.v:16095.9-16095.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22925,18 +23145,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:15911.3-15947.6" - process $proc$libresoc.v:15911$333 + attribute \src "libresoc.v:16131.3-16167.6" + process $proc$libresoc.v:16131$333 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:15912.5-15912.29" + attribute \src "libresoc.v:16132.5-16132.29" switch \initial - attribute \src "libresoc.v:15912.9-15912.17" + attribute \src "libresoc.v:16132.9-16132.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22984,18 +23204,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:15948.3-15984.6" - process $proc$libresoc.v:15948$334 + attribute \src "libresoc.v:16168.3-16204.6" + process $proc$libresoc.v:16168$334 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:15949.5-15949.29" + attribute \src "libresoc.v:16169.5-16169.29" switch \initial - attribute \src "libresoc.v:15949.9-15949.17" + attribute \src "libresoc.v:16169.9-16169.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23043,18 +23263,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:15985.3-16021.6" - process $proc$libresoc.v:15985$335 + attribute \src "libresoc.v:16205.3-16241.6" + process $proc$libresoc.v:16205$335 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:15986.5-15986.29" + attribute \src "libresoc.v:16206.5-16206.29" switch \initial - attribute \src "libresoc.v:15986.9-15986.17" + attribute \src "libresoc.v:16206.9-16206.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23102,18 +23322,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:16022.3-16058.6" - process $proc$libresoc.v:16022$336 + attribute \src "libresoc.v:16242.3-16278.6" + process $proc$libresoc.v:16242$336 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:16023.5-16023.29" + attribute \src "libresoc.v:16243.5-16243.29" switch \initial - attribute \src "libresoc.v:16023.9-16023.17" + attribute \src "libresoc.v:16243.9-16243.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23161,18 +23381,18 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:16059.3-16095.6" - process $proc$libresoc.v:16059$337 + attribute \src "libresoc.v:16279.3-16315.6" + process $proc$libresoc.v:16279$337 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:16060.5-16060.29" + attribute \src "libresoc.v:16280.5-16280.29" switch \initial - attribute \src "libresoc.v:16060.9-16060.17" + attribute \src "libresoc.v:16280.9-16280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23222,44 +23442,44 @@ module \LOGICAL_dec31_dec_sub28 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:16101.1-16659.10" +attribute \src "libresoc.v:16321.1-16894.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" attribute \generator "nMigen" module \MUL_dec31 - attribute \src "libresoc.v:16616.3-16628.6" + attribute \src "libresoc.v:16851.3-16863.6" wire width 3 $0\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16629.3-16641.6" + attribute \src "libresoc.v:16864.3-16876.6" wire width 3 $0\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16577.3-16589.6" - wire width 12 $0\MUL_dec31_function_unit[11:0] - attribute \src "libresoc.v:16603.3-16615.6" + attribute \src "libresoc.v:16812.3-16824.6" + wire width 14 $0\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16838.3-16850.6" wire width 4 $0\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16590.3-16602.6" + attribute \src "libresoc.v:16825.3-16837.6" wire width 7 $0\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16551.3-16563.6" + attribute \src "libresoc.v:16786.3-16798.6" wire $0\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16642.3-16654.6" + attribute \src "libresoc.v:16877.3-16889.6" wire width 2 $0\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16564.3-16576.6" + attribute \src "libresoc.v:16799.3-16811.6" wire $0\MUL_dec31_sgn[0:0] - attribute \src "libresoc.v:16102.7-16102.20" + attribute \src "libresoc.v:16322.7-16322.20" wire $0\initial[0:0] - attribute \src "libresoc.v:16616.3-16628.6" + attribute \src "libresoc.v:16851.3-16863.6" wire width 3 $1\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16629.3-16641.6" + attribute \src "libresoc.v:16864.3-16876.6" wire width 3 $1\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16577.3-16589.6" - wire width 12 $1\MUL_dec31_function_unit[11:0] - attribute \src "libresoc.v:16603.3-16615.6" + attribute \src "libresoc.v:16812.3-16824.6" + wire width 14 $1\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16838.3-16850.6" wire width 4 $1\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16590.3-16602.6" + attribute \src "libresoc.v:16825.3-16837.6" wire width 7 $1\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16551.3-16563.6" + attribute \src "libresoc.v:16786.3-16798.6" wire $1\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16642.3-16654.6" + attribute \src "libresoc.v:16877.3-16889.6" wire width 2 $1\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16564.3-16576.6" + attribute \src "libresoc.v:16799.3-16811.6" wire $1\MUL_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23269,7 +23489,8 @@ module \MUL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23277,7 +23498,8 @@ module \MUL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \MUL_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23287,7 +23509,8 @@ module \MUL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23295,23 +23518,26 @@ module \MUL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23327,7 +23553,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23403,19 +23629,20 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \MUL_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23425,7 +23652,8 @@ module \MUL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23433,23 +23661,26 @@ module \MUL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23465,7 +23696,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23541,35 +23772,38 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \MUL_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \MUL_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23585,7 +23819,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23661,28 +23895,29 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 7 \MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \MUL_dec31_sgn - attribute \src "libresoc.v:16102.7-16102.15" + attribute \src "libresoc.v:16322.7-16322.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:16529.23-16539.4" + attribute \src "libresoc.v:16764.23-16774.4" cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out @@ -23695,7 +23930,7 @@ module \MUL_dec31 connect \opcode_in \MUL_dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:16540.22-16550.4" + attribute \src "libresoc.v:16775.22-16785.4" cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out @@ -23707,26 +23942,26 @@ module \MUL_dec31 connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn connect \opcode_in \MUL_dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:16102.7-16102.20" - process $proc$libresoc.v:16102$347 + attribute \src "libresoc.v:16322.7-16322.20" + process $proc$libresoc.v:16322$347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:16551.3-16563.6" - process $proc$libresoc.v:16551$339 + attribute \src "libresoc.v:16786.3-16798.6" + process $proc$libresoc.v:16786$339 assign { } { } assign { } { } assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16552.5-16552.29" + attribute \src "libresoc.v:16787.5-16787.29" switch \initial - attribute \src "libresoc.v:16552.9-16552.17" + attribute \src "libresoc.v:16787.9-16787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23742,18 +23977,18 @@ module \MUL_dec31 sync always update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] end - attribute \src "libresoc.v:16564.3-16576.6" - process $proc$libresoc.v:16564$340 + attribute \src "libresoc.v:16799.3-16811.6" + process $proc$libresoc.v:16799$340 assign { } { } assign { } { } assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] - attribute \src "libresoc.v:16565.5-16565.29" + attribute \src "libresoc.v:16800.5-16800.29" switch \initial - attribute \src "libresoc.v:16565.9-16565.17" + attribute \src "libresoc.v:16800.9-16800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23769,45 +24004,45 @@ module \MUL_dec31 sync always update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] end - attribute \src "libresoc.v:16577.3-16589.6" - process $proc$libresoc.v:16577$341 + attribute \src "libresoc.v:16812.3-16824.6" + process $proc$libresoc.v:16812$341 assign { } { } assign { } { } - assign $0\MUL_dec31_function_unit[11:0] $1\MUL_dec31_function_unit[11:0] - attribute \src "libresoc.v:16578.5-16578.29" + assign $0\MUL_dec31_function_unit[13:0] $1\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16813.5-16813.29" switch \initial - attribute \src "libresoc.v:16578.9-16578.17" + attribute \src "libresoc.v:16813.9-16813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + assign $1\MUL_dec31_function_unit[13:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + assign $1\MUL_dec31_function_unit[13:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit case - assign $1\MUL_dec31_function_unit[11:0] 12'000000000000 + assign $1\MUL_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[11:0] + update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[13:0] end - attribute \src "libresoc.v:16590.3-16602.6" - process $proc$libresoc.v:16590$342 + attribute \src "libresoc.v:16825.3-16837.6" + process $proc$libresoc.v:16825$342 assign { } { } assign { } { } assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16591.5-16591.29" + attribute \src "libresoc.v:16826.5-16826.29" switch \initial - attribute \src "libresoc.v:16591.9-16591.17" + attribute \src "libresoc.v:16826.9-16826.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23823,18 +24058,18 @@ module \MUL_dec31 sync always update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] end - attribute \src "libresoc.v:16603.3-16615.6" - process $proc$libresoc.v:16603$343 + attribute \src "libresoc.v:16838.3-16850.6" + process $proc$libresoc.v:16838$343 assign { } { } assign { } { } assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16604.5-16604.29" + attribute \src "libresoc.v:16839.5-16839.29" switch \initial - attribute \src "libresoc.v:16604.9-16604.17" + attribute \src "libresoc.v:16839.9-16839.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23850,18 +24085,18 @@ module \MUL_dec31 sync always update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:16616.3-16628.6" - process $proc$libresoc.v:16616$344 + attribute \src "libresoc.v:16851.3-16863.6" + process $proc$libresoc.v:16851$344 assign { } { } assign { } { } assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16617.5-16617.29" + attribute \src "libresoc.v:16852.5-16852.29" switch \initial - attribute \src "libresoc.v:16617.9-16617.17" + attribute \src "libresoc.v:16852.9-16852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23877,18 +24112,18 @@ module \MUL_dec31 sync always update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] end - attribute \src "libresoc.v:16629.3-16641.6" - process $proc$libresoc.v:16629$345 + attribute \src "libresoc.v:16864.3-16876.6" + process $proc$libresoc.v:16864$345 assign { } { } assign { } { } assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16630.5-16630.29" + attribute \src "libresoc.v:16865.5-16865.29" switch \initial - attribute \src "libresoc.v:16630.9-16630.17" + attribute \src "libresoc.v:16865.9-16865.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23904,18 +24139,18 @@ module \MUL_dec31 sync always update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] end - attribute \src "libresoc.v:16642.3-16654.6" - process $proc$libresoc.v:16642$346 + attribute \src "libresoc.v:16877.3-16889.6" + process $proc$libresoc.v:16877$346 assign { } { } assign { } { } assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16643.5-16643.29" + attribute \src "libresoc.v:16878.5-16878.29" switch \initial - attribute \src "libresoc.v:16643.9-16643.17" + attribute \src "libresoc.v:16878.9-16878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23936,44 +24171,44 @@ module \MUL_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:16663.1-17014.10" +attribute \src "libresoc.v:16898.1-17254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" attribute \generator "nMigen" module \MUL_dec31_dec_sub11 - attribute \src "libresoc.v:16888.3-16912.6" + attribute \src "libresoc.v:17128.3-17152.6" wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:16913.3-16937.6" + attribute \src "libresoc.v:17153.3-17177.6" wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:16813.3-16837.6" - wire width 12 $0\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:16863.3-16887.6" + attribute \src "libresoc.v:17053.3-17077.6" + wire width 14 $0\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17103.3-17127.6" wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:16838.3-16862.6" + attribute \src "libresoc.v:17078.3-17102.6" wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:16963.3-16987.6" + attribute \src "libresoc.v:17203.3-17227.6" wire $0\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:16938.3-16962.6" + attribute \src "libresoc.v:17178.3-17202.6" wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:16988.3-17012.6" + attribute \src "libresoc.v:17228.3-17252.6" wire $0\MUL_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:16664.7-16664.20" + attribute \src "libresoc.v:16899.7-16899.20" wire $0\initial[0:0] - attribute \src "libresoc.v:16888.3-16912.6" + attribute \src "libresoc.v:17128.3-17152.6" wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:16913.3-16937.6" + attribute \src "libresoc.v:17153.3-17177.6" wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:16813.3-16837.6" - wire width 12 $1\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:16863.3-16887.6" + attribute \src "libresoc.v:17053.3-17077.6" + wire width 14 $1\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17103.3-17127.6" wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:16838.3-16862.6" + attribute \src "libresoc.v:17078.3-17102.6" wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:16963.3-16987.6" + attribute \src "libresoc.v:17203.3-17227.6" wire $1\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:16938.3-16962.6" + attribute \src "libresoc.v:17178.3-17202.6" wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:16988.3-17012.6" + attribute \src "libresoc.v:17228.3-17252.6" wire $1\MUL_dec31_dec_sub11_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23983,7 +24218,8 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23991,23 +24227,26 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \MUL_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -24023,7 +24262,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -24099,87 +24338,88 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 7 \MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \MUL_dec31_dec_sub11_sgn - attribute \src "libresoc.v:16664.7-16664.15" + attribute \src "libresoc.v:16899.7-16899.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:16664.7-16664.20" - process $proc$libresoc.v:16664$356 + attribute \src "libresoc.v:16899.7-16899.20" + process $proc$libresoc.v:16899$356 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:16813.3-16837.6" - process $proc$libresoc.v:16813$348 + attribute \src "libresoc.v:17053.3-17077.6" + process $proc$libresoc.v:17053$348 assign { } { } assign { } { } - assign $0\MUL_dec31_dec_sub11_function_unit[11:0] $1\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:16814.5-16814.29" + assign $0\MUL_dec31_dec_sub11_function_unit[13:0] $1\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17054.5-17054.29" switch \initial - attribute \src "libresoc.v:16814.9-16814.17" + attribute \src "libresoc.v:17054.9-17054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 case - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000000000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always - update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[11:0] + update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:16838.3-16862.6" - process $proc$libresoc.v:16838$349 + attribute \src "libresoc.v:17078.3-17102.6" + process $proc$libresoc.v:17078$349 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:16839.5-16839.29" + attribute \src "libresoc.v:17079.5-17079.29" switch \initial - attribute \src "libresoc.v:16839.9-16839.17" + attribute \src "libresoc.v:17079.9-17079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24211,18 +24451,18 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:16863.3-16887.6" - process $proc$libresoc.v:16863$350 + attribute \src "libresoc.v:17103.3-17127.6" + process $proc$libresoc.v:17103$350 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:16864.5-16864.29" + attribute \src "libresoc.v:17104.5-17104.29" switch \initial - attribute \src "libresoc.v:16864.9-16864.17" + attribute \src "libresoc.v:17104.9-17104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24254,18 +24494,18 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:16888.3-16912.6" - process $proc$libresoc.v:16888$351 + attribute \src "libresoc.v:17128.3-17152.6" + process $proc$libresoc.v:17128$351 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:16889.5-16889.29" + attribute \src "libresoc.v:17129.5-17129.29" switch \initial - attribute \src "libresoc.v:16889.9-16889.17" + attribute \src "libresoc.v:17129.9-17129.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24297,18 +24537,18 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:16913.3-16937.6" - process $proc$libresoc.v:16913$352 + attribute \src "libresoc.v:17153.3-17177.6" + process $proc$libresoc.v:17153$352 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:16914.5-16914.29" + attribute \src "libresoc.v:17154.5-17154.29" switch \initial - attribute \src "libresoc.v:16914.9-16914.17" + attribute \src "libresoc.v:17154.9-17154.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24340,18 +24580,18 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:16938.3-16962.6" - process $proc$libresoc.v:16938$353 + attribute \src "libresoc.v:17178.3-17202.6" + process $proc$libresoc.v:17178$353 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:16939.5-16939.29" + attribute \src "libresoc.v:17179.5-17179.29" switch \initial - attribute \src "libresoc.v:16939.9-16939.17" + attribute \src "libresoc.v:17179.9-17179.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24383,18 +24623,18 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:16963.3-16987.6" - process $proc$libresoc.v:16963$354 + attribute \src "libresoc.v:17203.3-17227.6" + process $proc$libresoc.v:17203$354 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:16964.5-16964.29" + attribute \src "libresoc.v:17204.5-17204.29" switch \initial - attribute \src "libresoc.v:16964.9-16964.17" + attribute \src "libresoc.v:17204.9-17204.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24426,18 +24666,18 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:16988.3-17012.6" - process $proc$libresoc.v:16988$355 + attribute \src "libresoc.v:17228.3-17252.6" + process $proc$libresoc.v:17228$355 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:16989.5-16989.29" + attribute \src "libresoc.v:17229.5-17229.29" switch \initial - attribute \src "libresoc.v:16989.9-16989.17" + attribute \src "libresoc.v:17229.9-17229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24471,44 +24711,44 @@ module \MUL_dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:17018.1-17369.10" +attribute \src "libresoc.v:17258.1-17614.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" attribute \generator "nMigen" module \MUL_dec31_dec_sub9 - attribute \src "libresoc.v:17243.3-17267.6" + attribute \src "libresoc.v:17488.3-17512.6" wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17268.3-17292.6" + attribute \src "libresoc.v:17513.3-17537.6" wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17168.3-17192.6" - wire width 12 $0\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:17218.3-17242.6" + attribute \src "libresoc.v:17413.3-17437.6" + wire width 14 $0\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17463.3-17487.6" wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17193.3-17217.6" + attribute \src "libresoc.v:17438.3-17462.6" wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17318.3-17342.6" + attribute \src "libresoc.v:17563.3-17587.6" wire $0\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17293.3-17317.6" + attribute \src "libresoc.v:17538.3-17562.6" wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17343.3-17367.6" + attribute \src "libresoc.v:17588.3-17612.6" wire $0\MUL_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:17019.7-17019.20" + attribute \src "libresoc.v:17259.7-17259.20" wire $0\initial[0:0] - attribute \src "libresoc.v:17243.3-17267.6" + attribute \src "libresoc.v:17488.3-17512.6" wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17268.3-17292.6" + attribute \src "libresoc.v:17513.3-17537.6" wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17168.3-17192.6" - wire width 12 $1\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:17218.3-17242.6" + attribute \src "libresoc.v:17413.3-17437.6" + wire width 14 $1\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17463.3-17487.6" wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17193.3-17217.6" + attribute \src "libresoc.v:17438.3-17462.6" wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17318.3-17342.6" + attribute \src "libresoc.v:17563.3-17587.6" wire $1\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17293.3-17317.6" + attribute \src "libresoc.v:17538.3-17562.6" wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17343.3-17367.6" + attribute \src "libresoc.v:17588.3-17612.6" wire $1\MUL_dec31_dec_sub9_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -24518,7 +24758,8 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -24526,23 +24767,26 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \MUL_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -24558,7 +24802,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -24634,87 +24878,88 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 7 \MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \MUL_dec31_dec_sub9_sgn - attribute \src "libresoc.v:17019.7-17019.15" + attribute \src "libresoc.v:17259.7-17259.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:17019.7-17019.20" - process $proc$libresoc.v:17019$365 + attribute \src "libresoc.v:17259.7-17259.20" + process $proc$libresoc.v:17259$365 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:17168.3-17192.6" - process $proc$libresoc.v:17168$357 + attribute \src "libresoc.v:17413.3-17437.6" + process $proc$libresoc.v:17413$357 assign { } { } assign { } { } - assign $0\MUL_dec31_dec_sub9_function_unit[11:0] $1\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:17169.5-17169.29" + assign $0\MUL_dec31_dec_sub9_function_unit[13:0] $1\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17414.5-17414.29" switch \initial - attribute \src "libresoc.v:17169.9-17169.17" + attribute \src "libresoc.v:17414.9-17414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 case - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000000000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always - update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[11:0] + update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:17193.3-17217.6" - process $proc$libresoc.v:17193$358 + attribute \src "libresoc.v:17438.3-17462.6" + process $proc$libresoc.v:17438$358 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17194.5-17194.29" + attribute \src "libresoc.v:17439.5-17439.29" switch \initial - attribute \src "libresoc.v:17194.9-17194.17" + attribute \src "libresoc.v:17439.9-17439.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24746,18 +24991,18 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:17218.3-17242.6" - process $proc$libresoc.v:17218$359 + attribute \src "libresoc.v:17463.3-17487.6" + process $proc$libresoc.v:17463$359 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17219.5-17219.29" + attribute \src "libresoc.v:17464.5-17464.29" switch \initial - attribute \src "libresoc.v:17219.9-17219.17" + attribute \src "libresoc.v:17464.9-17464.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24789,18 +25034,18 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:17243.3-17267.6" - process $proc$libresoc.v:17243$360 + attribute \src "libresoc.v:17488.3-17512.6" + process $proc$libresoc.v:17488$360 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17244.5-17244.29" + attribute \src "libresoc.v:17489.5-17489.29" switch \initial - attribute \src "libresoc.v:17244.9-17244.17" + attribute \src "libresoc.v:17489.9-17489.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24832,18 +25077,18 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:17268.3-17292.6" - process $proc$libresoc.v:17268$361 + attribute \src "libresoc.v:17513.3-17537.6" + process $proc$libresoc.v:17513$361 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17269.5-17269.29" + attribute \src "libresoc.v:17514.5-17514.29" switch \initial - attribute \src "libresoc.v:17269.9-17269.17" + attribute \src "libresoc.v:17514.9-17514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24875,18 +25120,18 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:17293.3-17317.6" - process $proc$libresoc.v:17293$362 + attribute \src "libresoc.v:17538.3-17562.6" + process $proc$libresoc.v:17538$362 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17294.5-17294.29" + attribute \src "libresoc.v:17539.5-17539.29" switch \initial - attribute \src "libresoc.v:17294.9-17294.17" + attribute \src "libresoc.v:17539.9-17539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24918,18 +25163,18 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:17318.3-17342.6" - process $proc$libresoc.v:17318$363 + attribute \src "libresoc.v:17563.3-17587.6" + process $proc$libresoc.v:17563$363 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17319.5-17319.29" + attribute \src "libresoc.v:17564.5-17564.29" switch \initial - attribute \src "libresoc.v:17319.9-17319.17" + attribute \src "libresoc.v:17564.9-17564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24961,18 +25206,18 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:17343.3-17367.6" - process $proc$libresoc.v:17343$364 + attribute \src "libresoc.v:17588.3-17612.6" + process $proc$libresoc.v:17588$364 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:17344.5-17344.29" + attribute \src "libresoc.v:17589.5-17589.29" switch \initial - attribute \src "libresoc.v:17344.9-17344.17" + attribute \src "libresoc.v:17589.9-17589.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25006,56 +25251,56 @@ module \MUL_dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:17373.1-17944.10" +attribute \src "libresoc.v:17618.1-18194.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" attribute \generator "nMigen" module \SHIFT_ROT_dec30 - attribute \src "libresoc.v:17721.3-17757.6" + attribute \src "libresoc.v:17971.3-18007.6" wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17758.3-17794.6" + attribute \src "libresoc.v:18008.3-18044.6" wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17832.3-17868.6" + attribute \src "libresoc.v:18082.3-18118.6" wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17906.3-17942.6" + attribute \src "libresoc.v:18156.3-18192.6" wire $0\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17536.3-17572.6" - wire width 12 $0\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17684.3-17720.6" + attribute \src "libresoc.v:17786.3-17822.6" + wire width 14 $0\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17934.3-17970.6" wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17647.3-17683.6" + attribute \src "libresoc.v:17897.3-17933.6" wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17869.3-17905.6" + attribute \src "libresoc.v:18119.3-18155.6" wire $0\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:17573.3-17609.6" + attribute \src "libresoc.v:17823.3-17859.6" wire $0\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17795.3-17831.6" + attribute \src "libresoc.v:18045.3-18081.6" wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17610.3-17646.6" + attribute \src "libresoc.v:17860.3-17896.6" wire $0\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "libresoc.v:17374.7-17374.20" + attribute \src "libresoc.v:17619.7-17619.20" wire $0\initial[0:0] - attribute \src "libresoc.v:17721.3-17757.6" + attribute \src "libresoc.v:17971.3-18007.6" wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17758.3-17794.6" + attribute \src "libresoc.v:18008.3-18044.6" wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17832.3-17868.6" + attribute \src "libresoc.v:18082.3-18118.6" wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17906.3-17942.6" + attribute \src "libresoc.v:18156.3-18192.6" wire $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17536.3-17572.6" - wire width 12 $1\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17684.3-17720.6" + attribute \src "libresoc.v:17786.3-17822.6" + wire width 14 $1\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17934.3-17970.6" wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17647.3-17683.6" + attribute \src "libresoc.v:17897.3-17933.6" wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17869.3-17905.6" + attribute \src "libresoc.v:18119.3-18155.6" wire $1\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:17573.3-17609.6" + attribute \src "libresoc.v:17823.3-17859.6" wire $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17795.3-17831.6" + attribute \src "libresoc.v:18045.3-18081.6" wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17610.3-17646.6" + attribute \src "libresoc.v:17860.3-17896.6" wire $1\SHIFT_ROT_dec30_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -25065,7 +25310,8 @@ module \SHIFT_ROT_dec30 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -25073,31 +25319,34 @@ module \SHIFT_ROT_dec30 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 7 \SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec30_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -25113,7 +25362,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -25189,105 +25438,106 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \SHIFT_ROT_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec30_sgn - attribute \src "libresoc.v:17374.7-17374.15" + attribute \src "libresoc.v:17619.7-17619.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 4 \opcode_switch - attribute \src "libresoc.v:17374.7-17374.20" - process $proc$libresoc.v:17374$377 + attribute \src "libresoc.v:17619.7-17619.20" + process $proc$libresoc.v:17619$377 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:17536.3-17572.6" - process $proc$libresoc.v:17536$366 + attribute \src "libresoc.v:17786.3-17822.6" + process $proc$libresoc.v:17786$366 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec30_function_unit[11:0] $1\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17537.5-17537.29" + assign $0\SHIFT_ROT_dec30_function_unit[13:0] $1\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17787.5-17787.29" switch \initial - attribute \src "libresoc.v:17537.9-17537.17" + attribute \src "libresoc.v:17787.9-17787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000000000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[11:0] + update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[13:0] end - attribute \src "libresoc.v:17573.3-17609.6" - process $proc$libresoc.v:17573$367 + attribute \src "libresoc.v:17823.3-17859.6" + process $proc$libresoc.v:17823$367 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17574.5-17574.29" + attribute \src "libresoc.v:17824.5-17824.29" switch \initial - attribute \src "libresoc.v:17574.9-17574.17" + attribute \src "libresoc.v:17824.9-17824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25335,18 +25585,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] end - attribute \src "libresoc.v:17610.3-17646.6" - process $proc$libresoc.v:17610$368 + attribute \src "libresoc.v:17860.3-17896.6" + process $proc$libresoc.v:17860$368 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "libresoc.v:17611.5-17611.29" + attribute \src "libresoc.v:17861.5-17861.29" switch \initial - attribute \src "libresoc.v:17611.9-17611.17" + attribute \src "libresoc.v:17861.9-17861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25394,18 +25644,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] end - attribute \src "libresoc.v:17647.3-17683.6" - process $proc$libresoc.v:17647$369 + attribute \src "libresoc.v:17897.3-17933.6" + process $proc$libresoc.v:17897$369 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17648.5-17648.29" + attribute \src "libresoc.v:17898.5-17898.29" switch \initial - attribute \src "libresoc.v:17648.9-17648.17" + attribute \src "libresoc.v:17898.9-17898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25453,18 +25703,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] end - attribute \src "libresoc.v:17684.3-17720.6" - process $proc$libresoc.v:17684$370 + attribute \src "libresoc.v:17934.3-17970.6" + process $proc$libresoc.v:17934$370 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17685.5-17685.29" + attribute \src "libresoc.v:17935.5-17935.29" switch \initial - attribute \src "libresoc.v:17685.9-17685.17" + attribute \src "libresoc.v:17935.9-17935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25512,18 +25762,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] end - attribute \src "libresoc.v:17721.3-17757.6" - process $proc$libresoc.v:17721$371 + attribute \src "libresoc.v:17971.3-18007.6" + process $proc$libresoc.v:17971$371 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17722.5-17722.29" + attribute \src "libresoc.v:17972.5-17972.29" switch \initial - attribute \src "libresoc.v:17722.9-17722.17" + attribute \src "libresoc.v:17972.9-17972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25571,18 +25821,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] end - attribute \src "libresoc.v:17758.3-17794.6" - process $proc$libresoc.v:17758$372 + attribute \src "libresoc.v:18008.3-18044.6" + process $proc$libresoc.v:18008$372 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17759.5-17759.29" + attribute \src "libresoc.v:18009.5-18009.29" switch \initial - attribute \src "libresoc.v:17759.9-17759.17" + attribute \src "libresoc.v:18009.9-18009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25630,18 +25880,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] end - attribute \src "libresoc.v:17795.3-17831.6" - process $proc$libresoc.v:17795$373 + attribute \src "libresoc.v:18045.3-18081.6" + process $proc$libresoc.v:18045$373 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17796.5-17796.29" + attribute \src "libresoc.v:18046.5-18046.29" switch \initial - attribute \src "libresoc.v:17796.9-17796.17" + attribute \src "libresoc.v:18046.9-18046.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25689,18 +25939,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] end - attribute \src "libresoc.v:17832.3-17868.6" - process $proc$libresoc.v:17832$374 + attribute \src "libresoc.v:18082.3-18118.6" + process $proc$libresoc.v:18082$374 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17833.5-17833.29" + attribute \src "libresoc.v:18083.5-18083.29" switch \initial - attribute \src "libresoc.v:17833.9-17833.17" + attribute \src "libresoc.v:18083.9-18083.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25748,18 +25998,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] end - attribute \src "libresoc.v:17869.3-17905.6" - process $proc$libresoc.v:17869$375 + attribute \src "libresoc.v:18119.3-18155.6" + process $proc$libresoc.v:18119$375 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_inv_a[0:0] $1\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:17870.5-17870.29" + attribute \src "libresoc.v:18120.5-18120.29" switch \initial - attribute \src "libresoc.v:17870.9-17870.17" + attribute \src "libresoc.v:18120.9-18120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25807,18 +26057,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_inv_a $0\SHIFT_ROT_dec30_inv_a[0:0] end - attribute \src "libresoc.v:17906.3-17942.6" - process $proc$libresoc.v:17906$376 + attribute \src "libresoc.v:18156.3-18192.6" + process $proc$libresoc.v:18156$376 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17907.5-17907.29" + attribute \src "libresoc.v:18157.5-18157.29" switch \initial - attribute \src "libresoc.v:17907.9-17907.17" + attribute \src "libresoc.v:18157.9-18157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25868,56 +26118,56 @@ module \SHIFT_ROT_dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:17948.1-18780.10" +attribute \src "libresoc.v:18198.1-19050.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" attribute \generator "nMigen" module \SHIFT_ROT_dec31 - attribute \src "libresoc.v:18743.3-18758.6" + attribute \src "libresoc.v:19013.3-19028.6" wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18759.3-18774.6" + attribute \src "libresoc.v:19029.3-19044.6" wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18615.3-18630.6" + attribute \src "libresoc.v:18885.3-18900.6" wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18647.3-18662.6" + attribute \src "libresoc.v:18917.3-18932.6" wire $0\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18695.3-18710.6" - wire width 12 $0\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18727.3-18742.6" + attribute \src "libresoc.v:18965.3-18980.6" + wire width 14 $0\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18997.3-19012.6" wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18711.3-18726.6" + attribute \src "libresoc.v:18981.3-18996.6" wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18631.3-18646.6" + attribute \src "libresoc.v:18901.3-18916.6" wire $0\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18663.3-18678.6" + attribute \src "libresoc.v:18933.3-18948.6" wire $0\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18599.3-18614.6" + attribute \src "libresoc.v:18869.3-18884.6" wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18679.3-18694.6" + attribute \src "libresoc.v:18949.3-18964.6" wire $0\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "libresoc.v:17949.7-17949.20" + attribute \src "libresoc.v:18199.7-18199.20" wire $0\initial[0:0] - attribute \src "libresoc.v:18743.3-18758.6" + attribute \src "libresoc.v:19013.3-19028.6" wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18759.3-18774.6" + attribute \src "libresoc.v:19029.3-19044.6" wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18615.3-18630.6" + attribute \src "libresoc.v:18885.3-18900.6" wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18647.3-18662.6" + attribute \src "libresoc.v:18917.3-18932.6" wire $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18695.3-18710.6" - wire width 12 $1\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18727.3-18742.6" + attribute \src "libresoc.v:18965.3-18980.6" + wire width 14 $1\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18997.3-19012.6" wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18711.3-18726.6" + attribute \src "libresoc.v:18981.3-18996.6" wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18631.3-18646.6" + attribute \src "libresoc.v:18901.3-18916.6" wire $1\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18663.3-18678.6" + attribute \src "libresoc.v:18933.3-18948.6" wire $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18599.3-18614.6" + attribute \src "libresoc.v:18869.3-18884.6" wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18679.3-18694.6" + attribute \src "libresoc.v:18949.3-18964.6" wire $1\SHIFT_ROT_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -25927,7 +26177,8 @@ module \SHIFT_ROT_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -25935,15 +26186,16 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 7 \SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -25953,7 +26205,8 @@ module \SHIFT_ROT_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -25961,31 +26214,34 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26001,7 +26257,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26077,21 +26333,22 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26101,7 +26358,8 @@ module \SHIFT_ROT_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26109,31 +26367,34 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26149,7 +26410,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26225,21 +26486,22 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26249,7 +26511,8 @@ module \SHIFT_ROT_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26257,31 +26520,34 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26297,7 +26563,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26373,37 +26639,40 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26419,7 +26688,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26495,30 +26764,31 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \SHIFT_ROT_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec31_sgn - attribute \src "libresoc.v:17949.7-17949.15" + attribute \src "libresoc.v:18199.7-18199.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:18557.29-18570.4" + attribute \src "libresoc.v:18827.29-18840.4" cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out @@ -26534,7 +26804,7 @@ module \SHIFT_ROT_dec31 connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:18571.29-18584.4" + attribute \src "libresoc.v:18841.29-18854.4" cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out @@ -26550,7 +26820,7 @@ module \SHIFT_ROT_dec31 connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:18585.29-18598.4" + attribute \src "libresoc.v:18855.29-18868.4" cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out @@ -26565,26 +26835,26 @@ module \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in end - attribute \src "libresoc.v:17949.7-17949.20" - process $proc$libresoc.v:17949$389 + attribute \src "libresoc.v:18199.7-18199.20" + process $proc$libresoc.v:18199$389 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:18599.3-18614.6" - process $proc$libresoc.v:18599$378 + attribute \src "libresoc.v:18869.3-18884.6" + process $proc$libresoc.v:18869$378 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18600.5-18600.29" + attribute \src "libresoc.v:18870.5-18870.29" switch \initial - attribute \src "libresoc.v:18600.9-18600.17" + attribute \src "libresoc.v:18870.9-18870.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26604,18 +26874,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:18615.3-18630.6" - process $proc$libresoc.v:18615$379 + attribute \src "libresoc.v:18885.3-18900.6" + process $proc$libresoc.v:18885$379 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18616.5-18616.29" + attribute \src "libresoc.v:18886.5-18886.29" switch \initial - attribute \src "libresoc.v:18616.9-18616.17" + attribute \src "libresoc.v:18886.9-18886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26635,18 +26905,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] end - attribute \src "libresoc.v:18631.3-18646.6" - process $proc$libresoc.v:18631$380 + attribute \src "libresoc.v:18901.3-18916.6" + process $proc$libresoc.v:18901$380 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_inv_a[0:0] $1\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18632.5-18632.29" + attribute \src "libresoc.v:18902.5-18902.29" switch \initial - attribute \src "libresoc.v:18632.9-18632.17" + attribute \src "libresoc.v:18902.9-18902.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26666,18 +26936,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_inv_a $0\SHIFT_ROT_dec31_inv_a[0:0] end - attribute \src "libresoc.v:18647.3-18662.6" - process $proc$libresoc.v:18647$381 + attribute \src "libresoc.v:18917.3-18932.6" + process $proc$libresoc.v:18917$381 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18648.5-18648.29" + attribute \src "libresoc.v:18918.5-18918.29" switch \initial - attribute \src "libresoc.v:18648.9-18648.17" + attribute \src "libresoc.v:18918.9-18918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26697,18 +26967,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] end - attribute \src "libresoc.v:18663.3-18678.6" - process $proc$libresoc.v:18663$382 + attribute \src "libresoc.v:18933.3-18948.6" + process $proc$libresoc.v:18933$382 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18664.5-18664.29" + attribute \src "libresoc.v:18934.5-18934.29" switch \initial - attribute \src "libresoc.v:18664.9-18664.17" + attribute \src "libresoc.v:18934.9-18934.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26728,18 +26998,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] end - attribute \src "libresoc.v:18679.3-18694.6" - process $proc$libresoc.v:18679$383 + attribute \src "libresoc.v:18949.3-18964.6" + process $proc$libresoc.v:18949$383 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "libresoc.v:18680.5-18680.29" + attribute \src "libresoc.v:18950.5-18950.29" switch \initial - attribute \src "libresoc.v:18680.9-18680.17" + attribute \src "libresoc.v:18950.9-18950.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26759,49 +27029,49 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] end - attribute \src "libresoc.v:18695.3-18710.6" - process $proc$libresoc.v:18695$384 + attribute \src "libresoc.v:18965.3-18980.6" + process $proc$libresoc.v:18965$384 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_function_unit[11:0] $1\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18696.5-18696.29" + assign $0\SHIFT_ROT_dec31_function_unit[13:0] $1\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18966.5-18966.29" switch \initial - attribute \src "libresoc.v:18696.9-18696.17" + attribute \src "libresoc.v:18966.9-18966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit case - assign $1\SHIFT_ROT_dec31_function_unit[11:0] 12'000000000000 + assign $1\SHIFT_ROT_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[11:0] + update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[13:0] end - attribute \src "libresoc.v:18711.3-18726.6" - process $proc$libresoc.v:18711$385 + attribute \src "libresoc.v:18981.3-18996.6" + process $proc$libresoc.v:18981$385 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18712.5-18712.29" + attribute \src "libresoc.v:18982.5-18982.29" switch \initial - attribute \src "libresoc.v:18712.9-18712.17" + attribute \src "libresoc.v:18982.9-18982.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26821,18 +27091,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] end - attribute \src "libresoc.v:18727.3-18742.6" - process $proc$libresoc.v:18727$386 + attribute \src "libresoc.v:18997.3-19012.6" + process $proc$libresoc.v:18997$386 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18728.5-18728.29" + attribute \src "libresoc.v:18998.5-18998.29" switch \initial - attribute \src "libresoc.v:18728.9-18728.17" + attribute \src "libresoc.v:18998.9-18998.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26852,18 +27122,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:18743.3-18758.6" - process $proc$libresoc.v:18743$387 + attribute \src "libresoc.v:19013.3-19028.6" + process $proc$libresoc.v:19013$387 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18744.5-18744.29" + attribute \src "libresoc.v:19014.5-19014.29" switch \initial - attribute \src "libresoc.v:18744.9-18744.17" + attribute \src "libresoc.v:19014.9-19014.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26883,18 +27153,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] end - attribute \src "libresoc.v:18759.3-18774.6" - process $proc$libresoc.v:18759$388 + attribute \src "libresoc.v:19029.3-19044.6" + process $proc$libresoc.v:19029$388 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18760.5-18760.29" + attribute \src "libresoc.v:19030.5-19030.29" switch \initial - attribute \src "libresoc.v:18760.9-18760.17" + attribute \src "libresoc.v:19030.9-19030.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26920,56 +27190,56 @@ module \SHIFT_ROT_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:18784.1-19157.10" +attribute \src "libresoc.v:19054.1-19432.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub24 - attribute \src "libresoc.v:19042.3-19060.6" + attribute \src "libresoc.v:19317.3-19335.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19061.3-19079.6" + attribute \src "libresoc.v:19336.3-19354.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19099.3-19117.6" + attribute \src "libresoc.v:19374.3-19392.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19137.3-19155.6" + attribute \src "libresoc.v:19412.3-19430.6" wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:18947.3-18965.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:19023.3-19041.6" + attribute \src "libresoc.v:19222.3-19240.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19298.3-19316.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19004.3-19022.6" + attribute \src "libresoc.v:19279.3-19297.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19118.3-19136.6" + attribute \src "libresoc.v:19393.3-19411.6" wire $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:18966.3-18984.6" + attribute \src "libresoc.v:19241.3-19259.6" wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:19080.3-19098.6" + attribute \src "libresoc.v:19355.3-19373.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:18985.3-19003.6" + attribute \src "libresoc.v:19260.3-19278.6" wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:18785.7-18785.20" + attribute \src "libresoc.v:19055.7-19055.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19042.3-19060.6" + attribute \src "libresoc.v:19317.3-19335.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19061.3-19079.6" + attribute \src "libresoc.v:19336.3-19354.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19099.3-19117.6" + attribute \src "libresoc.v:19374.3-19392.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19137.3-19155.6" + attribute \src "libresoc.v:19412.3-19430.6" wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:18947.3-18965.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:19023.3-19041.6" + attribute \src "libresoc.v:19222.3-19240.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19298.3-19316.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19004.3-19022.6" + attribute \src "libresoc.v:19279.3-19297.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19118.3-19136.6" + attribute \src "libresoc.v:19393.3-19411.6" wire $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:18966.3-18984.6" + attribute \src "libresoc.v:19241.3-19259.6" wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:19080.3-19098.6" + attribute \src "libresoc.v:19355.3-19373.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:18985.3-19003.6" + attribute \src "libresoc.v:19260.3-19278.6" wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26979,7 +27249,8 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26987,31 +27258,34 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -27027,7 +27301,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -27103,81 +27377,82 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "libresoc.v:18785.7-18785.15" + attribute \src "libresoc.v:19055.7-19055.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:18785.7-18785.20" - process $proc$libresoc.v:18785$401 + attribute \src "libresoc.v:19055.7-19055.20" + process $proc$libresoc.v:19055$401 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:18947.3-18965.6" - process $proc$libresoc.v:18947$390 + attribute \src "libresoc.v:19222.3-19240.6" + process $proc$libresoc.v:19222$390 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:18948.5-18948.29" + assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19223.5-19223.29" switch \initial - attribute \src "libresoc.v:18948.9-18948.17" + attribute \src "libresoc.v:19223.9-19223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000000000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:18966.3-18984.6" - process $proc$libresoc.v:18966$391 + attribute \src "libresoc.v:19241.3-19259.6" + process $proc$libresoc.v:19241$391 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:18967.5-18967.29" + attribute \src "libresoc.v:19242.5-19242.29" switch \initial - attribute \src "libresoc.v:18967.9-18967.17" + attribute \src "libresoc.v:19242.9-19242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27201,18 +27476,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:18985.3-19003.6" - process $proc$libresoc.v:18985$392 + attribute \src "libresoc.v:19260.3-19278.6" + process $proc$libresoc.v:19260$392 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:18986.5-18986.29" + attribute \src "libresoc.v:19261.5-19261.29" switch \initial - attribute \src "libresoc.v:18986.9-18986.17" + attribute \src "libresoc.v:19261.9-19261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27236,18 +27511,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:19004.3-19022.6" - process $proc$libresoc.v:19004$393 + attribute \src "libresoc.v:19279.3-19297.6" + process $proc$libresoc.v:19279$393 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19005.5-19005.29" + attribute \src "libresoc.v:19280.5-19280.29" switch \initial - attribute \src "libresoc.v:19005.9-19005.17" + attribute \src "libresoc.v:19280.9-19280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27271,18 +27546,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:19023.3-19041.6" - process $proc$libresoc.v:19023$394 + attribute \src "libresoc.v:19298.3-19316.6" + process $proc$libresoc.v:19298$394 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19024.5-19024.29" + attribute \src "libresoc.v:19299.5-19299.29" switch \initial - attribute \src "libresoc.v:19024.9-19024.17" + attribute \src "libresoc.v:19299.9-19299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27306,18 +27581,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:19042.3-19060.6" - process $proc$libresoc.v:19042$395 + attribute \src "libresoc.v:19317.3-19335.6" + process $proc$libresoc.v:19317$395 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19043.5-19043.29" + attribute \src "libresoc.v:19318.5-19318.29" switch \initial - attribute \src "libresoc.v:19043.9-19043.17" + attribute \src "libresoc.v:19318.9-19318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27341,18 +27616,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:19061.3-19079.6" - process $proc$libresoc.v:19061$396 + attribute \src "libresoc.v:19336.3-19354.6" + process $proc$libresoc.v:19336$396 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19062.5-19062.29" + attribute \src "libresoc.v:19337.5-19337.29" switch \initial - attribute \src "libresoc.v:19062.9-19062.17" + attribute \src "libresoc.v:19337.9-19337.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27376,18 +27651,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:19080.3-19098.6" - process $proc$libresoc.v:19080$397 + attribute \src "libresoc.v:19355.3-19373.6" + process $proc$libresoc.v:19355$397 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:19081.5-19081.29" + attribute \src "libresoc.v:19356.5-19356.29" switch \initial - attribute \src "libresoc.v:19081.9-19081.17" + attribute \src "libresoc.v:19356.9-19356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27411,18 +27686,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:19099.3-19117.6" - process $proc$libresoc.v:19099$398 + attribute \src "libresoc.v:19374.3-19392.6" + process $proc$libresoc.v:19374$398 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19100.5-19100.29" + attribute \src "libresoc.v:19375.5-19375.29" switch \initial - attribute \src "libresoc.v:19100.9-19100.17" + attribute \src "libresoc.v:19375.9-19375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27446,18 +27721,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:19118.3-19136.6" - process $proc$libresoc.v:19118$399 + attribute \src "libresoc.v:19393.3-19411.6" + process $proc$libresoc.v:19393$399 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:19119.5-19119.29" + attribute \src "libresoc.v:19394.5-19394.29" switch \initial - attribute \src "libresoc.v:19119.9-19119.17" + attribute \src "libresoc.v:19394.9-19394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27481,18 +27756,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_inv_a $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:19137.3-19155.6" - process $proc$libresoc.v:19137$400 + attribute \src "libresoc.v:19412.3-19430.6" + process $proc$libresoc.v:19412$400 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:19138.5-19138.29" + attribute \src "libresoc.v:19413.5-19413.29" switch \initial - attribute \src "libresoc.v:19138.9-19138.17" + attribute \src "libresoc.v:19413.9-19413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27518,56 +27793,56 @@ module \SHIFT_ROT_dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:19161.1-19501.10" +attribute \src "libresoc.v:19436.1-19781.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub26 - attribute \src "libresoc.v:19404.3-19419.6" + attribute \src "libresoc.v:19684.3-19699.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19420.3-19435.6" + attribute \src "libresoc.v:19700.3-19715.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19452.3-19467.6" + attribute \src "libresoc.v:19732.3-19747.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19484.3-19499.6" + attribute \src "libresoc.v:19764.3-19779.6" wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19324.3-19339.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19388.3-19403.6" + attribute \src "libresoc.v:19604.3-19619.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19668.3-19683.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19372.3-19387.6" + attribute \src "libresoc.v:19652.3-19667.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19468.3-19483.6" + attribute \src "libresoc.v:19748.3-19763.6" wire $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19340.3-19355.6" + attribute \src "libresoc.v:19620.3-19635.6" wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19436.3-19451.6" + attribute \src "libresoc.v:19716.3-19731.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19356.3-19371.6" + attribute \src "libresoc.v:19636.3-19651.6" wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:19162.7-19162.20" + attribute \src "libresoc.v:19437.7-19437.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19404.3-19419.6" + attribute \src "libresoc.v:19684.3-19699.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19420.3-19435.6" + attribute \src "libresoc.v:19700.3-19715.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19452.3-19467.6" + attribute \src "libresoc.v:19732.3-19747.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19484.3-19499.6" + attribute \src "libresoc.v:19764.3-19779.6" wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19324.3-19339.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19388.3-19403.6" + attribute \src "libresoc.v:19604.3-19619.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19668.3-19683.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19372.3-19387.6" + attribute \src "libresoc.v:19652.3-19667.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19468.3-19483.6" + attribute \src "libresoc.v:19748.3-19763.6" wire $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19340.3-19355.6" + attribute \src "libresoc.v:19620.3-19635.6" wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19436.3-19451.6" + attribute \src "libresoc.v:19716.3-19731.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19356.3-19371.6" + attribute \src "libresoc.v:19636.3-19651.6" wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -27577,7 +27852,8 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -27585,31 +27861,34 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -27625,7 +27904,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -27701,77 +27980,78 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "libresoc.v:19162.7-19162.15" + attribute \src "libresoc.v:19437.7-19437.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:19162.7-19162.20" - process $proc$libresoc.v:19162$413 + attribute \src "libresoc.v:19437.7-19437.20" + process $proc$libresoc.v:19437$413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:19324.3-19339.6" - process $proc$libresoc.v:19324$402 + attribute \src "libresoc.v:19604.3-19619.6" + process $proc$libresoc.v:19604$402 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19325.5-19325.29" + assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19605.5-19605.29" switch \initial - attribute \src "libresoc.v:19325.9-19325.17" + attribute \src "libresoc.v:19605.9-19605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:19340.3-19355.6" - process $proc$libresoc.v:19340$403 + attribute \src "libresoc.v:19620.3-19635.6" + process $proc$libresoc.v:19620$403 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19341.5-19341.29" + attribute \src "libresoc.v:19621.5-19621.29" switch \initial - attribute \src "libresoc.v:19341.9-19341.17" + attribute \src "libresoc.v:19621.9-19621.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27791,18 +28071,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:19356.3-19371.6" - process $proc$libresoc.v:19356$404 + attribute \src "libresoc.v:19636.3-19651.6" + process $proc$libresoc.v:19636$404 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:19357.5-19357.29" + attribute \src "libresoc.v:19637.5-19637.29" switch \initial - attribute \src "libresoc.v:19357.9-19357.17" + attribute \src "libresoc.v:19637.9-19637.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27822,18 +28102,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:19372.3-19387.6" - process $proc$libresoc.v:19372$405 + attribute \src "libresoc.v:19652.3-19667.6" + process $proc$libresoc.v:19652$405 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19373.5-19373.29" + attribute \src "libresoc.v:19653.5-19653.29" switch \initial - attribute \src "libresoc.v:19373.9-19373.17" + attribute \src "libresoc.v:19653.9-19653.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27853,18 +28133,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:19388.3-19403.6" - process $proc$libresoc.v:19388$406 + attribute \src "libresoc.v:19668.3-19683.6" + process $proc$libresoc.v:19668$406 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19389.5-19389.29" + attribute \src "libresoc.v:19669.5-19669.29" switch \initial - attribute \src "libresoc.v:19389.9-19389.17" + attribute \src "libresoc.v:19669.9-19669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27884,18 +28164,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:19404.3-19419.6" - process $proc$libresoc.v:19404$407 + attribute \src "libresoc.v:19684.3-19699.6" + process $proc$libresoc.v:19684$407 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19405.5-19405.29" + attribute \src "libresoc.v:19685.5-19685.29" switch \initial - attribute \src "libresoc.v:19405.9-19405.17" + attribute \src "libresoc.v:19685.9-19685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27915,18 +28195,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:19420.3-19435.6" - process $proc$libresoc.v:19420$408 + attribute \src "libresoc.v:19700.3-19715.6" + process $proc$libresoc.v:19700$408 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19421.5-19421.29" + attribute \src "libresoc.v:19701.5-19701.29" switch \initial - attribute \src "libresoc.v:19421.9-19421.17" + attribute \src "libresoc.v:19701.9-19701.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27946,18 +28226,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:19436.3-19451.6" - process $proc$libresoc.v:19436$409 + attribute \src "libresoc.v:19716.3-19731.6" + process $proc$libresoc.v:19716$409 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19437.5-19437.29" + attribute \src "libresoc.v:19717.5-19717.29" switch \initial - attribute \src "libresoc.v:19437.9-19437.17" + attribute \src "libresoc.v:19717.9-19717.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27977,18 +28257,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:19452.3-19467.6" - process $proc$libresoc.v:19452$410 + attribute \src "libresoc.v:19732.3-19747.6" + process $proc$libresoc.v:19732$410 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19453.5-19453.29" + attribute \src "libresoc.v:19733.5-19733.29" switch \initial - attribute \src "libresoc.v:19453.9-19453.17" + attribute \src "libresoc.v:19733.9-19733.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28008,18 +28288,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:19468.3-19483.6" - process $proc$libresoc.v:19468$411 + attribute \src "libresoc.v:19748.3-19763.6" + process $proc$libresoc.v:19748$411 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19469.5-19469.29" + attribute \src "libresoc.v:19749.5-19749.29" switch \initial - attribute \src "libresoc.v:19469.9-19469.17" + attribute \src "libresoc.v:19749.9-19749.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28039,18 +28319,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_inv_a $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:19484.3-19499.6" - process $proc$libresoc.v:19484$412 + attribute \src "libresoc.v:19764.3-19779.6" + process $proc$libresoc.v:19764$412 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19485.5-19485.29" + attribute \src "libresoc.v:19765.5-19765.29" switch \initial - attribute \src "libresoc.v:19485.9-19485.17" + attribute \src "libresoc.v:19765.9-19765.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28072,56 +28352,56 @@ module \SHIFT_ROT_dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:19505.1-19878.10" +attribute \src "libresoc.v:19785.1-20163.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub27 - attribute \src "libresoc.v:19763.3-19781.6" + attribute \src "libresoc.v:20048.3-20066.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19782.3-19800.6" + attribute \src "libresoc.v:20067.3-20085.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19820.3-19838.6" + attribute \src "libresoc.v:20105.3-20123.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19858.3-19876.6" + attribute \src "libresoc.v:20143.3-20161.6" wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19668.3-19686.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19744.3-19762.6" + attribute \src "libresoc.v:19953.3-19971.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:20029.3-20047.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19725.3-19743.6" + attribute \src "libresoc.v:20010.3-20028.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19839.3-19857.6" + attribute \src "libresoc.v:20124.3-20142.6" wire $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:19687.3-19705.6" + attribute \src "libresoc.v:19972.3-19990.6" wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19801.3-19819.6" + attribute \src "libresoc.v:20086.3-20104.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19706.3-19724.6" + attribute \src "libresoc.v:19991.3-20009.6" wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:19506.7-19506.20" + attribute \src "libresoc.v:19786.7-19786.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19763.3-19781.6" + attribute \src "libresoc.v:20048.3-20066.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19782.3-19800.6" + attribute \src "libresoc.v:20067.3-20085.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19820.3-19838.6" + attribute \src "libresoc.v:20105.3-20123.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19858.3-19876.6" + attribute \src "libresoc.v:20143.3-20161.6" wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19668.3-19686.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19744.3-19762.6" + attribute \src "libresoc.v:19953.3-19971.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:20029.3-20047.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19725.3-19743.6" + attribute \src "libresoc.v:20010.3-20028.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19839.3-19857.6" + attribute \src "libresoc.v:20124.3-20142.6" wire $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:19687.3-19705.6" + attribute \src "libresoc.v:19972.3-19990.6" wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19801.3-19819.6" + attribute \src "libresoc.v:20086.3-20104.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19706.3-19724.6" + attribute \src "libresoc.v:19991.3-20009.6" wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -28131,7 +28411,8 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -28139,31 +28420,34 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -28179,7 +28463,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -28255,81 +28539,82 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "libresoc.v:19506.7-19506.15" + attribute \src "libresoc.v:19786.7-19786.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:19506.7-19506.20" - process $proc$libresoc.v:19506$425 + attribute \src "libresoc.v:19786.7-19786.20" + process $proc$libresoc.v:19786$425 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:19668.3-19686.6" - process $proc$libresoc.v:19668$414 + attribute \src "libresoc.v:19953.3-19971.6" + process $proc$libresoc.v:19953$414 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19669.5-19669.29" + assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:19954.5-19954.29" switch \initial - attribute \src "libresoc.v:19669.9-19669.17" + attribute \src "libresoc.v:19954.9-19954.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000000000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:19687.3-19705.6" - process $proc$libresoc.v:19687$415 + attribute \src "libresoc.v:19972.3-19990.6" + process $proc$libresoc.v:19972$415 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19688.5-19688.29" + attribute \src "libresoc.v:19973.5-19973.29" switch \initial - attribute \src "libresoc.v:19688.9-19688.17" + attribute \src "libresoc.v:19973.9-19973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28353,18 +28638,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:19706.3-19724.6" - process $proc$libresoc.v:19706$416 + attribute \src "libresoc.v:19991.3-20009.6" + process $proc$libresoc.v:19991$416 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:19707.5-19707.29" + attribute \src "libresoc.v:19992.5-19992.29" switch \initial - attribute \src "libresoc.v:19707.9-19707.17" + attribute \src "libresoc.v:19992.9-19992.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28388,18 +28673,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:19725.3-19743.6" - process $proc$libresoc.v:19725$417 + attribute \src "libresoc.v:20010.3-20028.6" + process $proc$libresoc.v:20010$417 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19726.5-19726.29" + attribute \src "libresoc.v:20011.5-20011.29" switch \initial - attribute \src "libresoc.v:19726.9-19726.17" + attribute \src "libresoc.v:20011.9-20011.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28423,18 +28708,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:19744.3-19762.6" - process $proc$libresoc.v:19744$418 + attribute \src "libresoc.v:20029.3-20047.6" + process $proc$libresoc.v:20029$418 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19745.5-19745.29" + attribute \src "libresoc.v:20030.5-20030.29" switch \initial - attribute \src "libresoc.v:19745.9-19745.17" + attribute \src "libresoc.v:20030.9-20030.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28458,18 +28743,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:19763.3-19781.6" - process $proc$libresoc.v:19763$419 + attribute \src "libresoc.v:20048.3-20066.6" + process $proc$libresoc.v:20048$419 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19764.5-19764.29" + attribute \src "libresoc.v:20049.5-20049.29" switch \initial - attribute \src "libresoc.v:19764.9-19764.17" + attribute \src "libresoc.v:20049.9-20049.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28493,18 +28778,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:19782.3-19800.6" - process $proc$libresoc.v:19782$420 + attribute \src "libresoc.v:20067.3-20085.6" + process $proc$libresoc.v:20067$420 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19783.5-19783.29" + attribute \src "libresoc.v:20068.5-20068.29" switch \initial - attribute \src "libresoc.v:19783.9-19783.17" + attribute \src "libresoc.v:20068.9-20068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28528,18 +28813,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:19801.3-19819.6" - process $proc$libresoc.v:19801$421 + attribute \src "libresoc.v:20086.3-20104.6" + process $proc$libresoc.v:20086$421 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19802.5-19802.29" + attribute \src "libresoc.v:20087.5-20087.29" switch \initial - attribute \src "libresoc.v:19802.9-19802.17" + attribute \src "libresoc.v:20087.9-20087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28563,18 +28848,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:19820.3-19838.6" - process $proc$libresoc.v:19820$422 + attribute \src "libresoc.v:20105.3-20123.6" + process $proc$libresoc.v:20105$422 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19821.5-19821.29" + attribute \src "libresoc.v:20106.5-20106.29" switch \initial - attribute \src "libresoc.v:19821.9-19821.17" + attribute \src "libresoc.v:20106.9-20106.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28598,18 +28883,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:19839.3-19857.6" - process $proc$libresoc.v:19839$423 + attribute \src "libresoc.v:20124.3-20142.6" + process $proc$libresoc.v:20124$423 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:19840.5-19840.29" + attribute \src "libresoc.v:20125.5-20125.29" switch \initial - attribute \src "libresoc.v:19840.9-19840.17" + attribute \src "libresoc.v:20125.9-20125.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28633,18 +28918,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_inv_a $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:19858.3-19876.6" - process $proc$libresoc.v:19858$424 + attribute \src "libresoc.v:20143.3-20161.6" + process $proc$libresoc.v:20143$424 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19859.5-19859.29" + attribute \src "libresoc.v:20144.5-20144.29" switch \initial - attribute \src "libresoc.v:19859.9-19859.17" + attribute \src "libresoc.v:20144.9-20144.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28670,36 +28955,51 @@ module \SHIFT_ROT_dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:19882.1-20204.10" +attribute \src "SPBlock_512W64B8W.v:2.1-7.10" +attribute \cells_not_processed 1 +attribute \blackbox 1 +module \SPBlock_512W64B8W + attribute \src "SPBlock_512W64B8W.v:2.38-2.39" + wire width 9 input 1 \a + attribute \src "SPBlock_512W64B8W.v:6.11-6.14" + wire input 5 \clk + attribute \src "SPBlock_512W64B8W.v:3.18-3.19" + wire width 64 input 2 \d + attribute \src "SPBlock_512W64B8W.v:4.19-4.20" + wire width 64 output 3 \q + attribute \src "SPBlock_512W64B8W.v:5.17-5.19" + wire width 8 input 4 \we +end +attribute \src "libresoc.v:20167.1-20499.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" attribute \generator "nMigen" module \SPR_dec31 - attribute \src "libresoc.v:20161.3-20170.6" + attribute \src "libresoc.v:20456.3-20465.6" wire width 3 $0\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20171.3-20180.6" + attribute \src "libresoc.v:20466.3-20475.6" wire width 3 $0\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20141.3-20150.6" - wire width 12 $0\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20151.3-20160.6" + attribute \src "libresoc.v:20436.3-20445.6" + wire width 14 $0\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20446.3-20455.6" wire width 7 $0\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20191.3-20200.6" + attribute \src "libresoc.v:20486.3-20495.6" wire $0\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20181.3-20190.6" + attribute \src "libresoc.v:20476.3-20485.6" wire width 2 $0\SPR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:19883.7-19883.20" + attribute \src "libresoc.v:20168.7-20168.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20161.3-20170.6" + attribute \src "libresoc.v:20456.3-20465.6" wire width 3 $1\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20171.3-20180.6" + attribute \src "libresoc.v:20466.3-20475.6" wire width 3 $1\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20141.3-20150.6" - wire width 12 $1\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20151.3-20160.6" + attribute \src "libresoc.v:20436.3-20445.6" + wire width 14 $1\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20446.3-20455.6" wire width 7 $1\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20191.3-20200.6" + attribute \src "libresoc.v:20486.3-20495.6" wire $1\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20181.3-20190.6" + attribute \src "libresoc.v:20476.3-20485.6" wire width 2 $1\SPR_dec31_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -28709,7 +29009,8 @@ module \SPR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -28717,7 +29018,8 @@ module \SPR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \SPR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -28727,7 +29029,8 @@ module \SPR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -28735,23 +29038,26 @@ module \SPR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -28826,33 +29132,36 @@ module \SPR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SPR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SPR_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -28927,26 +29236,27 @@ module \SPR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 6 \SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \SPR_dec31_rc_sel - attribute \src "libresoc.v:19883.7-19883.15" + attribute \src "libresoc.v:20168.7-20168.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:20132.23-20140.4" + attribute \src "libresoc.v:20427.23-20435.4" cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out @@ -28956,49 +29266,49 @@ module \SPR_dec31 connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel connect \opcode_in \SPR_dec31_dec_sub19_opcode_in end - attribute \src "libresoc.v:19883.7-19883.20" - process $proc$libresoc.v:19883$432 + attribute \src "libresoc.v:20168.7-20168.20" + process $proc$libresoc.v:20168$432 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20141.3-20150.6" - process $proc$libresoc.v:20141$426 + attribute \src "libresoc.v:20436.3-20445.6" + process $proc$libresoc.v:20436$426 assign { } { } assign { } { } - assign $0\SPR_dec31_function_unit[11:0] $1\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20142.5-20142.29" + assign $0\SPR_dec31_function_unit[13:0] $1\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20437.5-20437.29" switch \initial - attribute \src "libresoc.v:20142.9-20142.17" + attribute \src "libresoc.v:20437.9-20437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\SPR_dec31_function_unit[11:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + assign $1\SPR_dec31_function_unit[13:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit case - assign $1\SPR_dec31_function_unit[11:0] 12'000000000000 + assign $1\SPR_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[11:0] + update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[13:0] end - attribute \src "libresoc.v:20151.3-20160.6" - process $proc$libresoc.v:20151$427 + attribute \src "libresoc.v:20446.3-20455.6" + process $proc$libresoc.v:20446$427 assign { } { } assign { } { } assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20152.5-20152.29" + attribute \src "libresoc.v:20447.5-20447.29" switch \initial - attribute \src "libresoc.v:20152.9-20152.17" + attribute \src "libresoc.v:20447.9-20447.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29010,18 +29320,18 @@ module \SPR_dec31 sync always update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] end - attribute \src "libresoc.v:20161.3-20170.6" - process $proc$libresoc.v:20161$428 + attribute \src "libresoc.v:20456.3-20465.6" + process $proc$libresoc.v:20456$428 assign { } { } assign { } { } assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20162.5-20162.29" + attribute \src "libresoc.v:20457.5-20457.29" switch \initial - attribute \src "libresoc.v:20162.9-20162.17" + attribute \src "libresoc.v:20457.9-20457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29033,18 +29343,18 @@ module \SPR_dec31 sync always update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] end - attribute \src "libresoc.v:20171.3-20180.6" - process $proc$libresoc.v:20171$429 + attribute \src "libresoc.v:20466.3-20475.6" + process $proc$libresoc.v:20466$429 assign { } { } assign { } { } assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20172.5-20172.29" + attribute \src "libresoc.v:20467.5-20467.29" switch \initial - attribute \src "libresoc.v:20172.9-20172.17" + attribute \src "libresoc.v:20467.9-20467.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29056,18 +29366,18 @@ module \SPR_dec31 sync always update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] end - attribute \src "libresoc.v:20181.3-20190.6" - process $proc$libresoc.v:20181$430 + attribute \src "libresoc.v:20476.3-20485.6" + process $proc$libresoc.v:20476$430 assign { } { } assign { } { } assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:20182.5-20182.29" + attribute \src "libresoc.v:20477.5-20477.29" switch \initial - attribute \src "libresoc.v:20182.9-20182.17" + attribute \src "libresoc.v:20477.9-20477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29079,18 +29389,18 @@ module \SPR_dec31 sync always update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:20191.3-20200.6" - process $proc$libresoc.v:20191$431 + attribute \src "libresoc.v:20486.3-20495.6" + process $proc$libresoc.v:20486$431 assign { } { } assign { } { } assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20192.5-20192.29" + attribute \src "libresoc.v:20487.5-20487.29" switch \initial - attribute \src "libresoc.v:20192.9-20192.17" + attribute \src "libresoc.v:20487.9-20487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29106,36 +29416,36 @@ module \SPR_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:20208.1-20416.10" +attribute \src "libresoc.v:20503.1-20716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" attribute \generator "nMigen" module \SPR_dec31_dec_sub19 - attribute \src "libresoc.v:20363.3-20375.6" + attribute \src "libresoc.v:20663.3-20675.6" wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20376.3-20388.6" + attribute \src "libresoc.v:20676.3-20688.6" wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20337.3-20349.6" - wire width 12 $0\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20350.3-20362.6" + attribute \src "libresoc.v:20637.3-20649.6" + wire width 14 $0\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20650.3-20662.6" wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20402.3-20414.6" + attribute \src "libresoc.v:20702.3-20714.6" wire $0\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20389.3-20401.6" + attribute \src "libresoc.v:20689.3-20701.6" wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:20209.7-20209.20" + attribute \src "libresoc.v:20504.7-20504.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20363.3-20375.6" + attribute \src "libresoc.v:20663.3-20675.6" wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20376.3-20388.6" + attribute \src "libresoc.v:20676.3-20688.6" wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20337.3-20349.6" - wire width 12 $1\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20350.3-20362.6" + attribute \src "libresoc.v:20637.3-20649.6" + wire width 14 $1\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20650.3-20662.6" wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20402.3-20414.6" + attribute \src "libresoc.v:20702.3-20714.6" wire $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20389.3-20401.6" + attribute \src "libresoc.v:20689.3-20701.6" wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -29145,7 +29455,8 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -29153,23 +29464,26 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SPR_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -29244,69 +29558,70 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 6 \SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:20209.7-20209.15" + attribute \src "libresoc.v:20504.7-20504.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:20209.7-20209.20" - process $proc$libresoc.v:20209$439 + attribute \src "libresoc.v:20504.7-20504.20" + process $proc$libresoc.v:20504$439 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20337.3-20349.6" - process $proc$libresoc.v:20337$433 + attribute \src "libresoc.v:20637.3-20649.6" + process $proc$libresoc.v:20637$433 assign { } { } assign { } { } - assign $0\SPR_dec31_dec_sub19_function_unit[11:0] $1\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20338.5-20338.29" + assign $0\SPR_dec31_dec_sub19_function_unit[13:0] $1\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20638.5-20638.29" switch \initial - attribute \src "libresoc.v:20338.9-20338.17" + attribute \src "libresoc.v:20638.9-20638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00010000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00010000000000 case - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00000000000000 end sync always - update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[11:0] + update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:20350.3-20362.6" - process $proc$libresoc.v:20350$434 + attribute \src "libresoc.v:20650.3-20662.6" + process $proc$libresoc.v:20650$434 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20351.5-20351.29" + attribute \src "libresoc.v:20651.5-20651.29" switch \initial - attribute \src "libresoc.v:20351.9-20351.17" + attribute \src "libresoc.v:20651.9-20651.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29322,18 +29637,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:20363.3-20375.6" - process $proc$libresoc.v:20363$435 + attribute \src "libresoc.v:20663.3-20675.6" + process $proc$libresoc.v:20663$435 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20364.5-20364.29" + attribute \src "libresoc.v:20664.5-20664.29" switch \initial - attribute \src "libresoc.v:20364.9-20364.17" + attribute \src "libresoc.v:20664.9-20664.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29349,18 +29664,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:20376.3-20388.6" - process $proc$libresoc.v:20376$436 + attribute \src "libresoc.v:20676.3-20688.6" + process $proc$libresoc.v:20676$436 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20377.5-20377.29" + attribute \src "libresoc.v:20677.5-20677.29" switch \initial - attribute \src "libresoc.v:20377.9-20377.17" + attribute \src "libresoc.v:20677.9-20677.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29376,18 +29691,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:20389.3-20401.6" - process $proc$libresoc.v:20389$437 + attribute \src "libresoc.v:20689.3-20701.6" + process $proc$libresoc.v:20689$437 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:20390.5-20390.29" + attribute \src "libresoc.v:20690.5-20690.29" switch \initial - attribute \src "libresoc.v:20390.9-20390.17" + attribute \src "libresoc.v:20690.9-20690.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29403,18 +29718,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:20402.3-20414.6" - process $proc$libresoc.v:20402$438 + attribute \src "libresoc.v:20702.3-20714.6" + process $proc$libresoc.v:20702$438 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20403.5-20403.29" + attribute \src "libresoc.v:20703.5-20703.29" switch \initial - attribute \src "libresoc.v:20403.9-20403.17" + attribute \src "libresoc.v:20703.9-20703.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29432,93 +29747,93 @@ module \SPR_dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:20420.1-20692.10" +attribute \src "libresoc.v:20720.1-20992.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" attribute \generator "nMigen" module \_fsm - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $0\fsm_state$next[3:0]$464 - attribute \src "libresoc.v:20506.3-20507.35" + attribute \src "libresoc.v:20806.3-20807.35" wire width 4 $0\fsm_state[3:0] - attribute \src "libresoc.v:20421.7-20421.20" + attribute \src "libresoc.v:20721.7-20721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20512.3-20539.6" + attribute \src "libresoc.v:20812.3-20839.6" wire $0\isdr$next[0:0]$460 - attribute \src "libresoc.v:20508.3-20509.25" + attribute \src "libresoc.v:20808.3-20809.25" wire $0\isdr[0:0] - attribute \src "libresoc.v:20655.3-20682.6" + attribute \src "libresoc.v:20955.3-20982.6" wire $0\isir$next[0:0]$477 - attribute \src "libresoc.v:20510.3-20511.25" + attribute \src "libresoc.v:20810.3-20811.25" wire $0\isir[0:0] - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $10\fsm_state$next[3:0]$474 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $11\fsm_state$next[3:0]$475 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $1\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20461.13-20461.29" + attribute \src "libresoc.v:20761.13-20761.29" wire width 4 $1\fsm_state[3:0] - attribute \src "libresoc.v:20512.3-20539.6" + attribute \src "libresoc.v:20812.3-20839.6" wire $1\isdr$next[0:0]$461 - attribute \src "libresoc.v:20466.7-20466.18" + attribute \src "libresoc.v:20766.7-20766.18" wire $1\isdr[0:0] - attribute \src "libresoc.v:20655.3-20682.6" + attribute \src "libresoc.v:20955.3-20982.6" wire $1\isir$next[0:0]$478 - attribute \src "libresoc.v:20471.7-20471.18" + attribute \src "libresoc.v:20771.7-20771.18" wire $1\isir[0:0] - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $2\fsm_state$next[3:0]$466 - attribute \src "libresoc.v:20512.3-20539.6" + attribute \src "libresoc.v:20812.3-20839.6" wire $2\isdr$next[0:0]$462 - attribute \src "libresoc.v:20655.3-20682.6" + attribute \src "libresoc.v:20955.3-20982.6" wire $2\isir$next[0:0]$479 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $3\fsm_state$next[3:0]$467 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $4\fsm_state$next[3:0]$468 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $5\fsm_state$next[3:0]$469 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $6\fsm_state$next[3:0]$470 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $7\fsm_state$next[3:0]$471 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $8\fsm_state$next[3:0]$472 - attribute \src "libresoc.v:20540.3-20654.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $9\fsm_state$next[3:0]$473 - attribute \src "libresoc.v:20490.17-20490.110" - wire $eq$libresoc.v:20490$440_Y - attribute \src "libresoc.v:20491.18-20491.111" - wire $eq$libresoc.v:20491$441_Y - attribute \src "libresoc.v:20492.18-20492.111" - wire $eq$libresoc.v:20492$442_Y - attribute \src "libresoc.v:20493.18-20493.111" - wire $eq$libresoc.v:20493$443_Y - attribute \src "libresoc.v:20494.18-20494.111" - wire $eq$libresoc.v:20494$444_Y - attribute \src "libresoc.v:20495.17-20495.108" - wire $eq$libresoc.v:20495$445_Y - attribute \src "libresoc.v:20496.18-20496.111" - wire $eq$libresoc.v:20496$446_Y - attribute \src "libresoc.v:20497.18-20497.111" - wire $eq$libresoc.v:20497$447_Y - attribute \src "libresoc.v:20498.18-20498.111" - wire $eq$libresoc.v:20498$448_Y - attribute \src "libresoc.v:20499.18-20499.111" - wire $eq$libresoc.v:20499$449_Y - attribute \src "libresoc.v:20500.18-20500.111" - wire $eq$libresoc.v:20500$450_Y - attribute \src "libresoc.v:20501.18-20501.111" - wire $eq$libresoc.v:20501$451_Y - attribute \src "libresoc.v:20502.18-20502.112" - wire $eq$libresoc.v:20502$452_Y - attribute \src "libresoc.v:20503.17-20503.108" - wire $eq$libresoc.v:20503$453_Y - attribute \src "libresoc.v:20504.17-20504.108" - wire $eq$libresoc.v:20504$454_Y - attribute \src "libresoc.v:20505.17-20505.108" - wire $eq$libresoc.v:20505$455_Y + attribute \src "libresoc.v:20790.17-20790.110" + wire $eq$libresoc.v:20790$440_Y + attribute \src "libresoc.v:20791.18-20791.111" + wire $eq$libresoc.v:20791$441_Y + attribute \src "libresoc.v:20792.18-20792.111" + wire $eq$libresoc.v:20792$442_Y + attribute \src "libresoc.v:20793.18-20793.111" + wire $eq$libresoc.v:20793$443_Y + attribute \src "libresoc.v:20794.18-20794.111" + wire $eq$libresoc.v:20794$444_Y + attribute \src "libresoc.v:20795.17-20795.108" + wire $eq$libresoc.v:20795$445_Y + attribute \src "libresoc.v:20796.18-20796.111" + wire $eq$libresoc.v:20796$446_Y + attribute \src "libresoc.v:20797.18-20797.111" + wire $eq$libresoc.v:20797$447_Y + attribute \src "libresoc.v:20798.18-20798.111" + wire $eq$libresoc.v:20798$448_Y + attribute \src "libresoc.v:20799.18-20799.111" + wire $eq$libresoc.v:20799$449_Y + attribute \src "libresoc.v:20800.18-20800.111" + wire $eq$libresoc.v:20800$450_Y + attribute \src "libresoc.v:20801.18-20801.111" + wire $eq$libresoc.v:20801$451_Y + attribute \src "libresoc.v:20802.18-20802.112" + wire $eq$libresoc.v:20802$452_Y + attribute \src "libresoc.v:20803.17-20803.108" + wire $eq$libresoc.v:20803$453_Y + attribute \src "libresoc.v:20804.17-20804.108" + wire $eq$libresoc.v:20804$454_Y + attribute \src "libresoc.v:20805.17-20805.108" + wire $eq$libresoc.v:20805$455_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" @@ -29561,7 +29876,7 @@ module \_fsm wire width 4 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" wire width 4 \fsm_state$next - attribute \src "libresoc.v:20421.7-20421.15" + attribute \src "libresoc.v:20721.7-20721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" wire output 11 \isdr @@ -29588,7 +29903,7 @@ module \_fsm attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire output 3 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - cell $eq $eq$libresoc.v:20490$440 + cell $eq $eq$libresoc.v:20790$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29596,10 +29911,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20490$440_Y + connect \Y $eq$libresoc.v:20790$440_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - cell $eq $eq$libresoc.v:20491$441 + cell $eq $eq$libresoc.v:20791$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29607,10 +29922,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20491$441_Y + connect \Y $eq$libresoc.v:20791$441_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" - cell $eq $eq$libresoc.v:20492$442 + cell $eq $eq$libresoc.v:20792$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29618,10 +29933,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20492$442_Y + connect \Y $eq$libresoc.v:20792$442_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" - cell $eq $eq$libresoc.v:20493$443 + cell $eq $eq$libresoc.v:20793$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29629,10 +29944,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20493$443_Y + connect \Y $eq$libresoc.v:20793$443_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - cell $eq $eq$libresoc.v:20494$444 + cell $eq $eq$libresoc.v:20794$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29640,10 +29955,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20494$444_Y + connect \Y $eq$libresoc.v:20794$444_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" - cell $eq $eq$libresoc.v:20495$445 + cell $eq $eq$libresoc.v:20795$445 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29651,10 +29966,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:20495$445_Y + connect \Y $eq$libresoc.v:20795$445_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - cell $eq $eq$libresoc.v:20496$446 + cell $eq $eq$libresoc.v:20796$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29662,10 +29977,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20496$446_Y + connect \Y $eq$libresoc.v:20796$446_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" - cell $eq $eq$libresoc.v:20497$447 + cell $eq $eq$libresoc.v:20797$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29673,10 +29988,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20497$447_Y + connect \Y $eq$libresoc.v:20797$447_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" - cell $eq $eq$libresoc.v:20498$448 + cell $eq $eq$libresoc.v:20798$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29684,10 +29999,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20498$448_Y + connect \Y $eq$libresoc.v:20798$448_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" - cell $eq $eq$libresoc.v:20499$449 + cell $eq $eq$libresoc.v:20799$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29695,10 +30010,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20499$449_Y + connect \Y $eq$libresoc.v:20799$449_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" - cell $eq $eq$libresoc.v:20500$450 + cell $eq $eq$libresoc.v:20800$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29706,10 +30021,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20500$450_Y + connect \Y $eq$libresoc.v:20800$450_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" - cell $eq $eq$libresoc.v:20501$451 + cell $eq $eq$libresoc.v:20801$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29717,10 +30032,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20501$451_Y + connect \Y $eq$libresoc.v:20801$451_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" - cell $eq $eq$libresoc.v:20502$452 + cell $eq $eq$libresoc.v:20802$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29728,10 +30043,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20502$452_Y + connect \Y $eq$libresoc.v:20802$452_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - cell $eq $eq$libresoc.v:20503$453 + cell $eq $eq$libresoc.v:20803$453 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29739,10 +30054,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'11 - connect \Y $eq$libresoc.v:20503$453_Y + connect \Y $eq$libresoc.v:20803$453_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - cell $eq $eq$libresoc.v:20504$454 + cell $eq $eq$libresoc.v:20804$454 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29750,10 +30065,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 3'101 - connect \Y $eq$libresoc.v:20504$454_Y + connect \Y $eq$libresoc.v:20804$454_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - cell $eq $eq$libresoc.v:20505$455 + cell $eq $eq$libresoc.v:20805$455 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29761,69 +30076,69 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 4'1000 - connect \Y $eq$libresoc.v:20505$455_Y + connect \Y $eq$libresoc.v:20805$455_Y end - attribute \src "libresoc.v:20421.7-20421.20" - process $proc$libresoc.v:20421$480 + attribute \src "libresoc.v:20721.7-20721.20" + process $proc$libresoc.v:20721$480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20461.13-20461.29" - process $proc$libresoc.v:20461$481 + attribute \src "libresoc.v:20761.13-20761.29" + process $proc$libresoc.v:20761$481 assign { } { } assign $1\fsm_state[3:0] 4'0000 sync always sync init update \fsm_state $1\fsm_state[3:0] end - attribute \src "libresoc.v:20466.7-20466.18" - process $proc$libresoc.v:20466$482 + attribute \src "libresoc.v:20766.7-20766.18" + process $proc$libresoc.v:20766$482 assign { } { } assign $1\isdr[0:0] 1'0 sync always sync init update \isdr $1\isdr[0:0] end - attribute \src "libresoc.v:20471.7-20471.18" - process $proc$libresoc.v:20471$483 + attribute \src "libresoc.v:20771.7-20771.18" + process $proc$libresoc.v:20771$483 assign { } { } assign $1\isir[0:0] 1'0 sync always sync init update \isir $1\isir[0:0] end - attribute \src "libresoc.v:20506.3-20507.35" - process $proc$libresoc.v:20506$456 + attribute \src "libresoc.v:20806.3-20807.35" + process $proc$libresoc.v:20806$456 assign { } { } assign $0\fsm_state[3:0] \fsm_state$next sync posedge \local_clk update \fsm_state $0\fsm_state[3:0] end - attribute \src "libresoc.v:20508.3-20509.25" - process $proc$libresoc.v:20508$457 + attribute \src "libresoc.v:20808.3-20809.25" + process $proc$libresoc.v:20808$457 assign { } { } assign $0\isdr[0:0] \isdr$next sync posedge \local_clk update \isdr $0\isdr[0:0] end - attribute \src "libresoc.v:20510.3-20511.25" - process $proc$libresoc.v:20510$458 + attribute \src "libresoc.v:20810.3-20811.25" + process $proc$libresoc.v:20810$458 assign { } { } assign $0\isir[0:0] \isir$next sync posedge \local_clk update \isir $0\isir[0:0] end - attribute \src "libresoc.v:20512.3-20539.6" - process $proc$libresoc.v:20512$459 + attribute \src "libresoc.v:20812.3-20839.6" + process $proc$libresoc.v:20812$459 assign { } { } assign { } { } assign $0\isdr$next[0:0]$460 $1\isdr$next[0:0]$461 - attribute \src "libresoc.v:20513.5-20513.29" + attribute \src "libresoc.v:20813.5-20813.29" switch \initial - attribute \src "libresoc.v:20513.9-20513.17" + attribute \src "libresoc.v:20813.9-20813.17" case 1'1 case end @@ -29860,14 +30175,14 @@ module \_fsm sync always update \isdr$next $0\isdr$next[0:0]$460 end - attribute \src "libresoc.v:20540.3-20654.6" - process $proc$libresoc.v:20540$463 + attribute \src "libresoc.v:20840.3-20954.6" + process $proc$libresoc.v:20840$463 assign { } { } assign { } { } assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20541.5-20541.29" + attribute \src "libresoc.v:20841.5-20841.29" switch \initial - attribute \src "libresoc.v:20541.9-20541.17" + attribute \src "libresoc.v:20841.9-20841.17" case 1'1 case end @@ -30021,14 +30336,14 @@ module \_fsm sync always update \fsm_state$next $0\fsm_state$next[3:0]$464 end - attribute \src "libresoc.v:20655.3-20682.6" - process $proc$libresoc.v:20655$476 + attribute \src "libresoc.v:20955.3-20982.6" + process $proc$libresoc.v:20955$476 assign { } { } assign { } { } assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 - attribute \src "libresoc.v:20656.5-20656.29" + attribute \src "libresoc.v:20956.5-20956.29" switch \initial - attribute \src "libresoc.v:20656.9-20656.17" + attribute \src "libresoc.v:20956.9-20956.17" case 1'1 case end @@ -30065,22 +30380,22 @@ module \_fsm sync always update \isir$next $0\isir$next[0:0]$477 end - connect \$9 $eq$libresoc.v:20490$440_Y - connect \$11 $eq$libresoc.v:20491$441_Y - connect \$13 $eq$libresoc.v:20492$442_Y - connect \$15 $eq$libresoc.v:20493$443_Y - connect \$17 $eq$libresoc.v:20494$444_Y - connect \$1 $eq$libresoc.v:20495$445_Y - connect \$19 $eq$libresoc.v:20496$446_Y - connect \$21 $eq$libresoc.v:20497$447_Y - connect \$23 $eq$libresoc.v:20498$448_Y - connect \$25 $eq$libresoc.v:20499$449_Y - connect \$27 $eq$libresoc.v:20500$450_Y - connect \$29 $eq$libresoc.v:20501$451_Y - connect \$31 $eq$libresoc.v:20502$452_Y - connect \$3 $eq$libresoc.v:20503$453_Y - connect \$5 $eq$libresoc.v:20504$454_Y - connect \$7 $eq$libresoc.v:20505$455_Y + connect \$9 $eq$libresoc.v:20790$440_Y + connect \$11 $eq$libresoc.v:20791$441_Y + connect \$13 $eq$libresoc.v:20792$442_Y + connect \$15 $eq$libresoc.v:20793$443_Y + connect \$17 $eq$libresoc.v:20794$444_Y + connect \$1 $eq$libresoc.v:20795$445_Y + connect \$19 $eq$libresoc.v:20796$446_Y + connect \$21 $eq$libresoc.v:20797$447_Y + connect \$23 $eq$libresoc.v:20798$448_Y + connect \$25 $eq$libresoc.v:20799$449_Y + connect \$27 $eq$libresoc.v:20800$450_Y + connect \$29 $eq$libresoc.v:20801$451_Y + connect \$31 $eq$libresoc.v:20802$452_Y + connect \$3 $eq$libresoc.v:20803$453_Y + connect \$5 $eq$libresoc.v:20804$454_Y + connect \$7 $eq$libresoc.v:20805$455_Y connect \update \$7 connect \shift \$5 connect \capture \$3 @@ -30091,29 +30406,29 @@ module \_fsm connect \posjtag_rst \rst connect \posjtag_clk \TAP_bus__tck end -attribute \src "libresoc.v:20696.1-20768.10" +attribute \src "libresoc.v:20996.1-21068.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" attribute \generator "nMigen" module \_idblock - attribute \src "libresoc.v:20741.3-20761.6" + attribute \src "libresoc.v:21041.3-21061.6" wire width 32 $0\TAP_id_sr$next[31:0]$489 - attribute \src "libresoc.v:20739.3-20740.35" + attribute \src "libresoc.v:21039.3-21040.35" wire width 32 $0\TAP_id_sr[31:0] - attribute \src "libresoc.v:20697.7-20697.20" + attribute \src "libresoc.v:20997.7-20997.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20741.3-20761.6" + attribute \src "libresoc.v:21041.3-21061.6" wire width 32 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:20707.14-20707.31" + attribute \src "libresoc.v:21007.14-21007.31" wire width 32 $1\TAP_id_sr[31:0] - attribute \src "libresoc.v:20741.3-20761.6" + attribute \src "libresoc.v:21041.3-21061.6" wire width 32 $2\TAP_id_sr$next[31:0]$491 - attribute \src "libresoc.v:20736.17-20736.110" - wire $and$libresoc.v:20736$484_Y - attribute \src "libresoc.v:20737.17-20737.108" - wire $and$libresoc.v:20737$485_Y - attribute \src "libresoc.v:20738.17-20738.109" - wire $and$libresoc.v:20738$486_Y + attribute \src "libresoc.v:21036.17-21036.110" + wire $and$libresoc.v:21036$484_Y + attribute \src "libresoc.v:21037.17-21037.108" + wire $and$libresoc.v:21037$485_Y + attribute \src "libresoc.v:21038.17-21038.109" + wire $and$libresoc.v:21038$486_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" @@ -30142,7 +30457,7 @@ module \_idblock wire input 2 \capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" wire input 1 \id_bypass - attribute \src "libresoc.v:20697.7-20697.15" + attribute \src "libresoc.v:20997.7-20997.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 8 \posjtag_clk @@ -30155,7 +30470,7 @@ module \_idblock attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 4 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - cell $and $and$libresoc.v:20736$484 + cell $and $and$libresoc.v:21036$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30163,10 +30478,10 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \capture - connect \Y $and$libresoc.v:20736$484_Y + connect \Y $and$libresoc.v:21036$484_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - cell $and $and$libresoc.v:20737$485 + cell $and $and$libresoc.v:21037$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30174,10 +30489,10 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \shift - connect \Y $and$libresoc.v:20737$485_Y + connect \Y $and$libresoc.v:21037$485_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - cell $and $and$libresoc.v:20738$486 + cell $and $and$libresoc.v:21038$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30185,39 +30500,39 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \update - connect \Y $and$libresoc.v:20738$486_Y + connect \Y $and$libresoc.v:21038$486_Y end - attribute \src "libresoc.v:20697.7-20697.20" - process $proc$libresoc.v:20697$492 + attribute \src "libresoc.v:20997.7-20997.20" + process $proc$libresoc.v:20997$492 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20707.14-20707.31" - process $proc$libresoc.v:20707$493 + attribute \src "libresoc.v:21007.14-21007.31" + process $proc$libresoc.v:21007$493 assign { } { } assign $1\TAP_id_sr[31:0] 0 sync always sync init update \TAP_id_sr $1\TAP_id_sr[31:0] end - attribute \src "libresoc.v:20739.3-20740.35" - process $proc$libresoc.v:20739$487 + attribute \src "libresoc.v:21039.3-21040.35" + process $proc$libresoc.v:21039$487 assign { } { } assign $0\TAP_id_sr[31:0] \TAP_id_sr$next sync posedge \posjtag_clk update \TAP_id_sr $0\TAP_id_sr[31:0] end - attribute \src "libresoc.v:20741.3-20761.6" - process $proc$libresoc.v:20741$488 + attribute \src "libresoc.v:21041.3-21061.6" + process $proc$libresoc.v:21041$488 assign { } { } assign { } { } assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:20742.5-20742.29" + attribute \src "libresoc.v:21042.5-21042.29" switch \initial - attribute \src "libresoc.v:20742.9-20742.17" + attribute \src "libresoc.v:21042.9-21042.17" case 1'1 case end @@ -30248,9 +30563,9 @@ module \_idblock sync always update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 end - connect \$1 $and$libresoc.v:20736$484_Y - connect \$3 $and$libresoc.v:20737$485_Y - connect \$5 $and$libresoc.v:20738$486_Y + connect \$1 $and$libresoc.v:21036$484_Y + connect \$3 $and$libresoc.v:21037$485_Y + connect \$5 $and$libresoc.v:21038$486_Y connect \TAP_id_tdo \TAP_id_sr [0] connect \_bypass \id_bypass connect \_update \$5 @@ -30258,43 +30573,43 @@ module \_idblock connect \_capture \$1 connect \_tdi \TAP_bus__tdi end -attribute \src "libresoc.v:20772.1-20856.10" +attribute \src "libresoc.v:21072.1-21156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" attribute \generator "nMigen" module \_irblock - attribute \src "libresoc.v:20773.7-20773.20" + attribute \src "libresoc.v:21073.7-21073.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20834.3-20854.6" + attribute \src "libresoc.v:21134.3-21154.6" wire width 4 $0\ir$next[3:0]$506 - attribute \src "libresoc.v:20817.3-20818.21" + attribute \src "libresoc.v:21117.3-21118.21" wire width 4 $0\ir[3:0] - attribute \src "libresoc.v:20821.3-20833.6" + attribute \src "libresoc.v:21121.3-21133.6" wire width 4 $0\shift_ir$next[3:0]$503 - attribute \src "libresoc.v:20819.3-20820.33" + attribute \src "libresoc.v:21119.3-21120.33" wire width 4 $0\shift_ir[3:0] - attribute \src "libresoc.v:20834.3-20854.6" + attribute \src "libresoc.v:21134.3-21154.6" wire width 4 $1\ir$next[3:0]$507 - attribute \src "libresoc.v:20792.13-20792.22" + attribute \src "libresoc.v:21092.13-21092.22" wire width 4 $1\ir[3:0] - attribute \src "libresoc.v:20821.3-20833.6" + attribute \src "libresoc.v:21121.3-21133.6" wire width 4 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:20804.13-20804.28" + attribute \src "libresoc.v:21104.13-21104.28" wire width 4 $1\shift_ir[3:0] - attribute \src "libresoc.v:20834.3-20854.6" + attribute \src "libresoc.v:21134.3-21154.6" wire width 4 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:20811.17-20811.103" - wire $and$libresoc.v:20811$494_Y - attribute \src "libresoc.v:20812.18-20812.105" - wire $and$libresoc.v:20812$495_Y - attribute \src "libresoc.v:20813.17-20813.105" - wire $and$libresoc.v:20813$496_Y - attribute \src "libresoc.v:20814.17-20814.103" - wire $and$libresoc.v:20814$497_Y - attribute \src "libresoc.v:20815.17-20815.104" - wire $and$libresoc.v:20815$498_Y - attribute \src "libresoc.v:20816.17-20816.105" - wire $and$libresoc.v:20816$499_Y + attribute \src "libresoc.v:21111.17-21111.103" + wire $and$libresoc.v:21111$494_Y + attribute \src "libresoc.v:21112.18-21112.105" + wire $and$libresoc.v:21112$495_Y + attribute \src "libresoc.v:21113.17-21113.105" + wire $and$libresoc.v:21113$496_Y + attribute \src "libresoc.v:21114.17-21114.103" + wire $and$libresoc.v:21114$497_Y + attribute \src "libresoc.v:21115.17-21115.104" + wire $and$libresoc.v:21115$498_Y + attribute \src "libresoc.v:21116.17-21116.105" + wire $and$libresoc.v:21116$499_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" @@ -30311,7 +30626,7 @@ module \_irblock wire input 4 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire input 1 \capture - attribute \src "libresoc.v:20773.7-20773.15" + attribute \src "libresoc.v:21073.7-21073.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 output 9 \ir @@ -30334,7 +30649,7 @@ module \_irblock attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 3 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:20811$494 + cell $and $and$libresoc.v:21111$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30342,10 +30657,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:20811$494_Y + connect \Y $and$libresoc.v:21111$494_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:20812$495 + cell $and $and$libresoc.v:21112$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30353,10 +30668,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:20812$495_Y + connect \Y $and$libresoc.v:21112$495_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:20813$496 + cell $and $and$libresoc.v:21113$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30364,10 +30679,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:20813$496_Y + connect \Y $and$libresoc.v:21113$496_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:20814$497 + cell $and $and$libresoc.v:21114$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30375,10 +30690,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:20814$497_Y + connect \Y $and$libresoc.v:21114$497_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:20815$498 + cell $and $and$libresoc.v:21115$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30386,10 +30701,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:20815$498_Y + connect \Y $and$libresoc.v:21115$498_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:20816$499 + cell $and $and$libresoc.v:21116$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30397,54 +30712,54 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:20816$499_Y + connect \Y $and$libresoc.v:21116$499_Y end - attribute \src "libresoc.v:20773.7-20773.20" - process $proc$libresoc.v:20773$509 + attribute \src "libresoc.v:21073.7-21073.20" + process $proc$libresoc.v:21073$509 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20792.13-20792.22" - process $proc$libresoc.v:20792$510 + attribute \src "libresoc.v:21092.13-21092.22" + process $proc$libresoc.v:21092$510 assign { } { } assign $1\ir[3:0] 4'0001 sync always sync init update \ir $1\ir[3:0] end - attribute \src "libresoc.v:20804.13-20804.28" - process $proc$libresoc.v:20804$511 + attribute \src "libresoc.v:21104.13-21104.28" + process $proc$libresoc.v:21104$511 assign { } { } assign $1\shift_ir[3:0] 4'0000 sync always sync init update \shift_ir $1\shift_ir[3:0] end - attribute \src "libresoc.v:20817.3-20818.21" - process $proc$libresoc.v:20817$500 + attribute \src "libresoc.v:21117.3-21118.21" + process $proc$libresoc.v:21117$500 assign { } { } assign $0\ir[3:0] \ir$next sync posedge \posjtag_clk update \ir $0\ir[3:0] end - attribute \src "libresoc.v:20819.3-20820.33" - process $proc$libresoc.v:20819$501 + attribute \src "libresoc.v:21119.3-21120.33" + process $proc$libresoc.v:21119$501 assign { } { } assign $0\shift_ir[3:0] \shift_ir$next sync posedge \posjtag_clk update \shift_ir $0\shift_ir[3:0] end - attribute \src "libresoc.v:20821.3-20833.6" - process $proc$libresoc.v:20821$502 + attribute \src "libresoc.v:21121.3-21133.6" + process $proc$libresoc.v:21121$502 assign { } { } assign { } { } assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:20822.5-20822.29" + attribute \src "libresoc.v:21122.5-21122.29" switch \initial - attribute \src "libresoc.v:20822.9-20822.17" + attribute \src "libresoc.v:21122.9-21122.17" case 1'1 case end @@ -30464,15 +30779,15 @@ module \_irblock sync always update \shift_ir$next $0\shift_ir$next[3:0]$503 end - attribute \src "libresoc.v:20834.3-20854.6" - process $proc$libresoc.v:20834$505 + attribute \src "libresoc.v:21134.3-21154.6" + process $proc$libresoc.v:21134$505 assign { } { } assign { } { } assign { } { } assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:20835.5-20835.29" + attribute \src "libresoc.v:21135.5-21135.29" switch \initial - attribute \src "libresoc.v:20835.9-20835.17" + attribute \src "libresoc.v:21135.9-21135.17" case 1'1 case end @@ -30503,83 +30818,83 @@ module \_irblock sync always update \ir$next $0\ir$next[3:0]$506 end - connect \$9 $and$libresoc.v:20811$494_Y - connect \$11 $and$libresoc.v:20812$495_Y - connect \$1 $and$libresoc.v:20813$496_Y - connect \$3 $and$libresoc.v:20814$497_Y - connect \$5 $and$libresoc.v:20815$498_Y - connect \$7 $and$libresoc.v:20816$499_Y + connect \$9 $and$libresoc.v:21111$494_Y + connect \$11 $and$libresoc.v:21112$495_Y + connect \$1 $and$libresoc.v:21113$496_Y + connect \$3 $and$libresoc.v:21114$497_Y + connect \$5 $and$libresoc.v:21115$498_Y + connect \$7 $and$libresoc.v:21116$499_Y connect \tdo \ir [0] end -attribute \src "libresoc.v:20860.1-20918.10" +attribute \src "libresoc.v:21160.1-21218.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" attribute \generator "nMigen" module \adr_l - attribute \src "libresoc.v:20861.7-20861.20" + attribute \src "libresoc.v:21161.7-21161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20906.3-20914.6" + attribute \src "libresoc.v:21206.3-21214.6" wire $0\q_int$next[0:0]$522 - attribute \src "libresoc.v:20904.3-20905.27" + attribute \src "libresoc.v:21204.3-21205.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:20906.3-20914.6" + attribute \src "libresoc.v:21206.3-21214.6" wire $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:20885.7-20885.19" + attribute \src "libresoc.v:21185.7-21185.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:20896.17-20896.96" - wire $and$libresoc.v:20896$512_Y - attribute \src "libresoc.v:20901.17-20901.96" - wire $and$libresoc.v:20901$517_Y - attribute \src "libresoc.v:20898.18-20898.93" - wire $not$libresoc.v:20898$514_Y - attribute \src "libresoc.v:20900.17-20900.92" - wire $not$libresoc.v:20900$516_Y - attribute \src "libresoc.v:20903.17-20903.92" - wire $not$libresoc.v:20903$519_Y - attribute \src "libresoc.v:20897.18-20897.98" - wire $or$libresoc.v:20897$513_Y - attribute \src "libresoc.v:20899.18-20899.99" - wire $or$libresoc.v:20899$515_Y - attribute \src "libresoc.v:20902.17-20902.97" - wire $or$libresoc.v:20902$518_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:21196.17-21196.96" + wire $and$libresoc.v:21196$512_Y + attribute \src "libresoc.v:21201.17-21201.96" + wire $and$libresoc.v:21201$517_Y + attribute \src "libresoc.v:21198.18-21198.93" + wire $not$libresoc.v:21198$514_Y + attribute \src "libresoc.v:21200.17-21200.92" + wire $not$libresoc.v:21200$516_Y + attribute \src "libresoc.v:21203.17-21203.92" + wire $not$libresoc.v:21203$519_Y + attribute \src "libresoc.v:21197.18-21197.98" + wire $or$libresoc.v:21197$513_Y + attribute \src "libresoc.v:21199.18-21199.99" + wire $or$libresoc.v:21199$515_Y + attribute \src "libresoc.v:21202.17-21202.97" + wire $or$libresoc.v:21202$518_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:20861.7-20861.15" + attribute \src "libresoc.v:21161.7-21161.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:20896$512 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:21196$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30587,10 +30902,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:20896$512_Y + connect \Y $and$libresoc.v:21196$512_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:20901$517 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:21201$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30598,34 +30913,34 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:20901$517_Y + connect \Y $and$libresoc.v:21201$517_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:20898$514 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:21198$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_adr - connect \Y $not$libresoc.v:20898$514_Y + connect \Y $not$libresoc.v:21198$514_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:20900$516 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:21200$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:20900$516_Y + connect \Y $not$libresoc.v:21200$516_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:20903$519 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:21203$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:20903$519_Y + connect \Y $not$libresoc.v:21203$519_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:20897$513 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:21197$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30633,10 +30948,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_adr - connect \Y $or$libresoc.v:20897$513_Y + connect \Y $or$libresoc.v:21197$513_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:20899$515 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:21199$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30644,10 +30959,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_adr connect \B \q_int - connect \Y $or$libresoc.v:20899$515_Y + connect \Y $or$libresoc.v:21199$515_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:20902$518 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:21202$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30655,39 +30970,39 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_adr - connect \Y $or$libresoc.v:20902$518_Y + connect \Y $or$libresoc.v:21202$518_Y end - attribute \src "libresoc.v:20861.7-20861.20" - process $proc$libresoc.v:20861$524 + attribute \src "libresoc.v:21161.7-21161.20" + process $proc$libresoc.v:21161$524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20885.7-20885.19" - process $proc$libresoc.v:20885$525 + attribute \src "libresoc.v:21185.7-21185.19" + process $proc$libresoc.v:21185$525 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:20904.3-20905.27" - process $proc$libresoc.v:20904$520 + attribute \src "libresoc.v:21204.3-21205.27" + process $proc$libresoc.v:21204$520 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:20906.3-20914.6" - process $proc$libresoc.v:20906$521 + attribute \src "libresoc.v:21206.3-21214.6" + process $proc$libresoc.v:21206$521 assign { } { } assign { } { } assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:20907.5-20907.29" + attribute \src "libresoc.v:21207.5-21207.29" switch \initial - attribute \src "libresoc.v:20907.9-20907.17" + attribute \src "libresoc.v:21207.9-21207.17" case 1'1 case end @@ -30703,87 +31018,87 @@ module \adr_l sync always update \q_int$next $0\q_int$next[0:0]$522 end - connect \$9 $and$libresoc.v:20896$512_Y - connect \$11 $or$libresoc.v:20897$513_Y - connect \$13 $not$libresoc.v:20898$514_Y - connect \$15 $or$libresoc.v:20899$515_Y - connect \$1 $not$libresoc.v:20900$516_Y - connect \$3 $and$libresoc.v:20901$517_Y - connect \$5 $or$libresoc.v:20902$518_Y - connect \$7 $not$libresoc.v:20903$519_Y + connect \$9 $and$libresoc.v:21196$512_Y + connect \$11 $or$libresoc.v:21197$513_Y + connect \$13 $not$libresoc.v:21198$514_Y + connect \$15 $or$libresoc.v:21199$515_Y + connect \$1 $not$libresoc.v:21200$516_Y + connect \$3 $and$libresoc.v:21201$517_Y + connect \$5 $or$libresoc.v:21202$518_Y + connect \$7 $not$libresoc.v:21203$519_Y connect \qlq_adr \$15 connect \qn_adr \$13 connect \q_adr \$11 end -attribute \src "libresoc.v:20922.1-20980.10" +attribute \src "libresoc.v:21222.1-21280.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" attribute \generator "nMigen" module \adrok_l - attribute \src "libresoc.v:20923.7-20923.20" + attribute \src "libresoc.v:21223.7-21223.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20968.3-20976.6" + attribute \src "libresoc.v:21268.3-21276.6" wire $0\q_int$next[0:0]$536 - attribute \src "libresoc.v:20966.3-20967.27" + attribute \src "libresoc.v:21266.3-21267.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:20968.3-20976.6" + attribute \src "libresoc.v:21268.3-21276.6" wire $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:20947.7-20947.19" + attribute \src "libresoc.v:21247.7-21247.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:20958.17-20958.96" - wire $and$libresoc.v:20958$526_Y - attribute \src "libresoc.v:20963.17-20963.96" - wire $and$libresoc.v:20963$531_Y - attribute \src "libresoc.v:20960.18-20960.100" - wire $not$libresoc.v:20960$528_Y - attribute \src "libresoc.v:20962.17-20962.99" - wire $not$libresoc.v:20962$530_Y - attribute \src "libresoc.v:20965.17-20965.99" - wire $not$libresoc.v:20965$533_Y - attribute \src "libresoc.v:20959.18-20959.105" - wire $or$libresoc.v:20959$527_Y - attribute \src "libresoc.v:20961.18-20961.106" - wire $or$libresoc.v:20961$529_Y - attribute \src "libresoc.v:20964.17-20964.104" - wire $or$libresoc.v:20964$532_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:21258.17-21258.96" + wire $and$libresoc.v:21258$526_Y + attribute \src "libresoc.v:21263.17-21263.96" + wire $and$libresoc.v:21263$531_Y + attribute \src "libresoc.v:21260.18-21260.100" + wire $not$libresoc.v:21260$528_Y + attribute \src "libresoc.v:21262.17-21262.99" + wire $not$libresoc.v:21262$530_Y + attribute \src "libresoc.v:21265.17-21265.99" + wire $not$libresoc.v:21265$533_Y + attribute \src "libresoc.v:21259.18-21259.105" + wire $or$libresoc.v:21259$527_Y + attribute \src "libresoc.v:21261.18-21261.106" + wire $or$libresoc.v:21261$529_Y + attribute \src "libresoc.v:21264.17-21264.104" + wire $or$libresoc.v:21264$532_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:20923.7-20923.15" + attribute \src "libresoc.v:21223.7-21223.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 5 \q_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire output 4 \qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:20958$526 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:21258$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30791,10 +31106,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:20958$526_Y + connect \Y $and$libresoc.v:21258$526_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:20963$531 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:21263$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30802,34 +31117,34 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:20963$531_Y + connect \Y $and$libresoc.v:21263$531_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:20960$528 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:21260$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_addr_acked - connect \Y $not$libresoc.v:20960$528_Y + connect \Y $not$libresoc.v:21260$528_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:20962$530 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:21262$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:20962$530_Y + connect \Y $not$libresoc.v:21262$530_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:20965$533 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:21265$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:20965$533_Y + connect \Y $not$libresoc.v:21265$533_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:20959$527 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:21259$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30837,10 +31152,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_addr_acked - connect \Y $or$libresoc.v:20959$527_Y + connect \Y $or$libresoc.v:21259$527_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:20961$529 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:21261$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30848,10 +31163,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_addr_acked connect \B \q_int - connect \Y $or$libresoc.v:20961$529_Y + connect \Y $or$libresoc.v:21261$529_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:20964$532 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:21264$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30859,39 +31174,39 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_addr_acked - connect \Y $or$libresoc.v:20964$532_Y + connect \Y $or$libresoc.v:21264$532_Y end - attribute \src "libresoc.v:20923.7-20923.20" - process $proc$libresoc.v:20923$538 + attribute \src "libresoc.v:21223.7-21223.20" + process $proc$libresoc.v:21223$538 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20947.7-20947.19" - process $proc$libresoc.v:20947$539 + attribute \src "libresoc.v:21247.7-21247.19" + process $proc$libresoc.v:21247$539 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:20966.3-20967.27" - process $proc$libresoc.v:20966$534 + attribute \src "libresoc.v:21266.3-21267.27" + process $proc$libresoc.v:21266$534 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:20968.3-20976.6" - process $proc$libresoc.v:20968$535 + attribute \src "libresoc.v:21268.3-21276.6" + process $proc$libresoc.v:21268$535 assign { } { } assign { } { } assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:20969.5-20969.29" + attribute \src "libresoc.v:21269.5-21269.29" switch \initial - attribute \src "libresoc.v:20969.9-20969.17" + attribute \src "libresoc.v:21269.9-21269.17" case 1'1 case end @@ -30907,593 +31222,593 @@ module \adrok_l sync always update \q_int$next $0\q_int$next[0:0]$536 end - connect \$9 $and$libresoc.v:20958$526_Y - connect \$11 $or$libresoc.v:20959$527_Y - connect \$13 $not$libresoc.v:20960$528_Y - connect \$15 $or$libresoc.v:20961$529_Y - connect \$1 $not$libresoc.v:20962$530_Y - connect \$3 $and$libresoc.v:20963$531_Y - connect \$5 $or$libresoc.v:20964$532_Y - connect \$7 $not$libresoc.v:20965$533_Y + connect \$9 $and$libresoc.v:21258$526_Y + connect \$11 $or$libresoc.v:21259$527_Y + connect \$13 $not$libresoc.v:21260$528_Y + connect \$15 $or$libresoc.v:21261$529_Y + connect \$1 $not$libresoc.v:21262$530_Y + connect \$3 $and$libresoc.v:21263$531_Y + connect \$5 $or$libresoc.v:21264$532_Y + connect \$7 $not$libresoc.v:21265$533_Y connect \qlq_addr_acked \$15 connect \qn_addr_acked \$13 connect \q_addr_acked \$11 end -attribute \src "libresoc.v:20984.1-22309.10" +attribute \src "libresoc.v:21284.1-22615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" attribute \generator "nMigen" module \alu0 - attribute \src "libresoc.v:21820.3-21821.25" + attribute \src "libresoc.v:22126.3-22127.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 - attribute \src "libresoc.v:21792.3-21793.67" + attribute \src "libresoc.v:22098.3-22099.67" wire width 4 $0\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 12 $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 - attribute \src "libresoc.v:21762.3-21763.65" - wire width 12 $0\alu_alu0_alu_op__fn_unit[11:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" + wire width 14 $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 + attribute \src "libresoc.v:22068.3-22069.65" + wire width 14 $0\alu_alu0_alu_op__fn_unit[13:0] + attribute \src "libresoc.v:22316.3-22354.6" wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 - attribute \src "libresoc.v:21764.3-21765.79" + attribute \src "libresoc.v:22070.3-22071.79" wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 - attribute \src "libresoc.v:21766.3-21767.75" + attribute \src "libresoc.v:22072.3-22073.75" wire $0\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 - attribute \src "libresoc.v:21784.3-21785.73" + attribute \src "libresoc.v:22090.3-22091.73" wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 - attribute \src "libresoc.v:21794.3-21795.59" + attribute \src "libresoc.v:22100.3-22101.59" wire width 32 $0\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 - attribute \src "libresoc.v:21760.3-21761.69" + attribute \src "libresoc.v:22066.3-22067.69" wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 - attribute \src "libresoc.v:21776.3-21777.69" + attribute \src "libresoc.v:22082.3-22083.69" wire $0\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 - attribute \src "libresoc.v:21780.3-21781.71" + attribute \src "libresoc.v:22086.3-22087.71" wire $0\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 - attribute \src "libresoc.v:21788.3-21789.67" + attribute \src "libresoc.v:22094.3-22095.67" wire $0\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 - attribute \src "libresoc.v:21790.3-21791.69" + attribute \src "libresoc.v:22096.3-22097.69" wire $0\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 - attribute \src "libresoc.v:21772.3-21773.63" + attribute \src "libresoc.v:22078.3-22079.63" wire $0\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 - attribute \src "libresoc.v:21774.3-21775.63" + attribute \src "libresoc.v:22080.3-22081.63" wire $0\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 - attribute \src "libresoc.v:21786.3-21787.75" + attribute \src "libresoc.v:22092.3-22093.75" wire $0\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 - attribute \src "libresoc.v:21770.3-21771.63" + attribute \src "libresoc.v:22076.3-22077.63" wire $0\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 - attribute \src "libresoc.v:21768.3-21769.63" + attribute \src "libresoc.v:22074.3-22075.63" wire $0\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 - attribute \src "libresoc.v:21782.3-21783.69" + attribute \src "libresoc.v:22088.3-22089.69" wire $0\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 - attribute \src "libresoc.v:21778.3-21779.63" + attribute \src "libresoc.v:22084.3-22085.63" wire $0\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21818.3-21819.40" + attribute \src "libresoc.v:22124.3-22125.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:22208.3-22216.6" + attribute \src "libresoc.v:22514.3-22522.6" wire $0\alu_l_r_alu$next[0:0]$784 - attribute \src "libresoc.v:21728.3-21729.39" + attribute \src "libresoc.v:22034.3-22035.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22199.3-22207.6" + attribute \src "libresoc.v:22505.3-22513.6" wire $0\alui_l_r_alui$next[0:0]$781 - attribute \src "libresoc.v:21730.3-21731.43" + attribute \src "libresoc.v:22036.3-22037.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22049.3-22070.6" + attribute \src "libresoc.v:22355.3-22376.6" wire width 64 $0\data_r0__o$next[63:0]$729 - attribute \src "libresoc.v:21756.3-21757.37" + attribute \src "libresoc.v:22062.3-22063.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:22049.3-22070.6" + attribute \src "libresoc.v:22355.3-22376.6" wire $0\data_r0__o_ok$next[0:0]$730 - attribute \src "libresoc.v:21758.3-21759.43" + attribute \src "libresoc.v:22064.3-22065.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22071.3-22092.6" + attribute \src "libresoc.v:22377.3-22398.6" wire width 4 $0\data_r1__cr_a$next[3:0]$737 - attribute \src "libresoc.v:21752.3-21753.43" + attribute \src "libresoc.v:22058.3-22059.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22071.3-22092.6" + attribute \src "libresoc.v:22377.3-22398.6" wire $0\data_r1__cr_a_ok$next[0:0]$738 - attribute \src "libresoc.v:21754.3-21755.49" + attribute \src "libresoc.v:22060.3-22061.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22093.3-22114.6" + attribute \src "libresoc.v:22399.3-22420.6" wire width 2 $0\data_r2__xer_ca$next[1:0]$745 - attribute \src "libresoc.v:21748.3-21749.47" + attribute \src "libresoc.v:22054.3-22055.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22093.3-22114.6" + attribute \src "libresoc.v:22399.3-22420.6" wire $0\data_r2__xer_ca_ok$next[0:0]$746 - attribute \src "libresoc.v:21750.3-21751.53" + attribute \src "libresoc.v:22056.3-22057.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22115.3-22136.6" + attribute \src "libresoc.v:22421.3-22442.6" wire width 2 $0\data_r3__xer_ov$next[1:0]$753 - attribute \src "libresoc.v:21744.3-21745.47" + attribute \src "libresoc.v:22050.3-22051.47" wire width 2 $0\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22115.3-22136.6" + attribute \src "libresoc.v:22421.3-22442.6" wire $0\data_r3__xer_ov_ok$next[0:0]$754 - attribute \src "libresoc.v:21746.3-21747.53" + attribute \src "libresoc.v:22052.3-22053.53" wire $0\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22137.3-22158.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $0\data_r4__xer_so$next[0:0]$761 - attribute \src "libresoc.v:21740.3-21741.47" + attribute \src "libresoc.v:22046.3-22047.47" wire $0\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22137.3-22158.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $0\data_r4__xer_so_ok$next[0:0]$762 - attribute \src "libresoc.v:21742.3-21743.53" + attribute \src "libresoc.v:22048.3-22049.53" wire $0\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22217.3-22226.6" + attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:22227.3-22236.6" + attribute \src "libresoc.v:22533.3-22542.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:22237.3-22246.6" + attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:22247.3-22256.6" + attribute \src "libresoc.v:22553.3-22562.6" wire width 2 $0\dest4_o[1:0] - attribute \src "libresoc.v:22257.3-22266.6" + attribute \src "libresoc.v:22563.3-22572.6" wire $0\dest5_o[0:0] - attribute \src "libresoc.v:20985.7-20985.20" + attribute \src "libresoc.v:21285.7-21285.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21965.3-21973.6" + attribute \src "libresoc.v:22271.3-22279.6" wire $0\opc_l_r_opc$next[0:0]$671 - attribute \src "libresoc.v:21804.3-21805.39" + attribute \src "libresoc.v:22110.3-22111.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:21956.3-21964.6" + attribute \src "libresoc.v:22262.3-22270.6" wire $0\opc_l_s_opc$next[0:0]$668 - attribute \src "libresoc.v:21806.3-21807.39" + attribute \src "libresoc.v:22112.3-22113.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22267.3-22275.6" + attribute \src "libresoc.v:22573.3-22581.6" wire width 5 $0\prev_wr_go$next[4:0]$792 - attribute \src "libresoc.v:21816.3-21817.37" + attribute \src "libresoc.v:22122.3-22123.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:21910.3-21919.6" + attribute \src "libresoc.v:22216.3-22225.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:22001.3-22009.6" + attribute \src "libresoc.v:22307.3-22315.6" wire width 5 $0\req_l_r_req$next[4:0]$683 - attribute \src "libresoc.v:21796.3-21797.39" + attribute \src "libresoc.v:22102.3-22103.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:21992.3-22000.6" + attribute \src "libresoc.v:22298.3-22306.6" wire width 5 $0\req_l_s_req$next[4:0]$680 - attribute \src "libresoc.v:21798.3-21799.39" + attribute \src "libresoc.v:22104.3-22105.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:21929.3-21937.6" + attribute \src "libresoc.v:22235.3-22243.6" wire $0\rok_l_r_rdok$next[0:0]$659 - attribute \src "libresoc.v:21812.3-21813.41" + attribute \src "libresoc.v:22118.3-22119.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:21920.3-21928.6" + attribute \src "libresoc.v:22226.3-22234.6" wire $0\rok_l_s_rdok$next[0:0]$656 - attribute \src "libresoc.v:21814.3-21815.41" + attribute \src "libresoc.v:22120.3-22121.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:21947.3-21955.6" + attribute \src "libresoc.v:22253.3-22261.6" wire $0\rst_l_r_rst$next[0:0]$665 - attribute \src "libresoc.v:21808.3-21809.39" + attribute \src "libresoc.v:22114.3-22115.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:21938.3-21946.6" + attribute \src "libresoc.v:22244.3-22252.6" wire $0\rst_l_s_rst$next[0:0]$662 - attribute \src "libresoc.v:21810.3-21811.39" + attribute \src "libresoc.v:22116.3-22117.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:21983.3-21991.6" + attribute \src "libresoc.v:22289.3-22297.6" wire width 4 $0\src_l_r_src$next[3:0]$677 - attribute \src "libresoc.v:21800.3-21801.39" + attribute \src "libresoc.v:22106.3-22107.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:21974.3-21982.6" + attribute \src "libresoc.v:22280.3-22288.6" wire width 4 $0\src_l_s_src$next[3:0]$674 - attribute \src "libresoc.v:21802.3-21803.39" + attribute \src "libresoc.v:22108.3-22109.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:22159.3-22168.6" + attribute \src "libresoc.v:22465.3-22474.6" wire width 64 $0\src_r0$next[63:0]$769 - attribute \src "libresoc.v:21738.3-21739.29" + attribute \src "libresoc.v:22044.3-22045.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:22169.3-22178.6" + attribute \src "libresoc.v:22475.3-22484.6" wire width 64 $0\src_r1$next[63:0]$772 - attribute \src "libresoc.v:21736.3-21737.29" + attribute \src "libresoc.v:22042.3-22043.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:22179.3-22188.6" + attribute \src "libresoc.v:22485.3-22494.6" wire $0\src_r2$next[0:0]$775 - attribute \src "libresoc.v:21734.3-21735.29" + attribute \src "libresoc.v:22040.3-22041.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:22189.3-22198.6" + attribute \src "libresoc.v:22495.3-22504.6" wire width 2 $0\src_r3$next[1:0]$778 - attribute \src "libresoc.v:21732.3-21733.29" + attribute \src "libresoc.v:22038.3-22039.29" wire width 2 $0\src_r3[1:0] - attribute \src "libresoc.v:21123.7-21123.24" + attribute \src "libresoc.v:21423.7-21423.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 - attribute \src "libresoc.v:21131.13-21131.45" + attribute \src "libresoc.v:21431.13-21431.45" wire width 4 $1\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 12 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 - attribute \src "libresoc.v:21148.14-21148.48" - wire width 12 $1\alu_alu0_alu_op__fn_unit[11:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" + wire width 14 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 + attribute \src "libresoc.v:21450.14-21450.49" + wire width 14 $1\alu_alu0_alu_op__fn_unit[13:0] + attribute \src "libresoc.v:22316.3-22354.6" wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 - attribute \src "libresoc.v:21152.14-21152.68" + attribute \src "libresoc.v:21454.14-21454.68" wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 - attribute \src "libresoc.v:21156.7-21156.43" + attribute \src "libresoc.v:21458.7-21458.43" wire $1\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 - attribute \src "libresoc.v:21164.13-21164.48" + attribute \src "libresoc.v:21466.13-21466.48" wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 - attribute \src "libresoc.v:21168.14-21168.43" + attribute \src "libresoc.v:21470.14-21470.43" wire width 32 $1\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 - attribute \src "libresoc.v:21246.13-21246.47" + attribute \src "libresoc.v:21549.13-21549.47" wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 - attribute \src "libresoc.v:21250.7-21250.40" + attribute \src "libresoc.v:21553.7-21553.40" wire $1\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 - attribute \src "libresoc.v:21254.7-21254.41" + attribute \src "libresoc.v:21557.7-21557.41" wire $1\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 - attribute \src "libresoc.v:21258.7-21258.39" + attribute \src "libresoc.v:21561.7-21561.39" wire $1\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 - attribute \src "libresoc.v:21262.7-21262.40" + attribute \src "libresoc.v:21565.7-21565.40" wire $1\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 - attribute \src "libresoc.v:21266.7-21266.37" + attribute \src "libresoc.v:21569.7-21569.37" wire $1\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 - attribute \src "libresoc.v:21270.7-21270.37" + attribute \src "libresoc.v:21573.7-21573.37" wire $1\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 - attribute \src "libresoc.v:21274.7-21274.43" + attribute \src "libresoc.v:21577.7-21577.43" wire $1\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 - attribute \src "libresoc.v:21278.7-21278.37" + attribute \src "libresoc.v:21581.7-21581.37" wire $1\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 - attribute \src "libresoc.v:21282.7-21282.37" + attribute \src "libresoc.v:21585.7-21585.37" wire $1\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 - attribute \src "libresoc.v:21286.7-21286.40" + attribute \src "libresoc.v:21589.7-21589.40" wire $1\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 - attribute \src "libresoc.v:21290.7-21290.37" + attribute \src "libresoc.v:21593.7-21593.37" wire $1\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21322.7-21322.26" + attribute \src "libresoc.v:21625.7-21625.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:22208.3-22216.6" + attribute \src "libresoc.v:22514.3-22522.6" wire $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:21330.7-21330.25" + attribute \src "libresoc.v:21633.7-21633.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22199.3-22207.6" + attribute \src "libresoc.v:22505.3-22513.6" wire $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:21342.7-21342.27" + attribute \src "libresoc.v:21645.7-21645.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22049.3-22070.6" + attribute \src "libresoc.v:22355.3-22376.6" wire width 64 $1\data_r0__o$next[63:0]$731 - attribute \src "libresoc.v:21376.14-21376.47" + attribute \src "libresoc.v:21679.14-21679.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:22049.3-22070.6" + attribute \src "libresoc.v:22355.3-22376.6" wire $1\data_r0__o_ok$next[0:0]$732 - attribute \src "libresoc.v:21380.7-21380.27" + attribute \src "libresoc.v:21683.7-21683.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22071.3-22092.6" + attribute \src "libresoc.v:22377.3-22398.6" wire width 4 $1\data_r1__cr_a$next[3:0]$739 - attribute \src "libresoc.v:21384.13-21384.33" + attribute \src "libresoc.v:21687.13-21687.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22071.3-22092.6" + attribute \src "libresoc.v:22377.3-22398.6" wire $1\data_r1__cr_a_ok$next[0:0]$740 - attribute \src "libresoc.v:21388.7-21388.30" + attribute \src "libresoc.v:21691.7-21691.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22093.3-22114.6" + attribute \src "libresoc.v:22399.3-22420.6" wire width 2 $1\data_r2__xer_ca$next[1:0]$747 - attribute \src "libresoc.v:21392.13-21392.35" + attribute \src "libresoc.v:21695.13-21695.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22093.3-22114.6" + attribute \src "libresoc.v:22399.3-22420.6" wire $1\data_r2__xer_ca_ok$next[0:0]$748 - attribute \src "libresoc.v:21396.7-21396.32" + attribute \src "libresoc.v:21699.7-21699.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22115.3-22136.6" + attribute \src "libresoc.v:22421.3-22442.6" wire width 2 $1\data_r3__xer_ov$next[1:0]$755 - attribute \src "libresoc.v:21400.13-21400.35" + attribute \src "libresoc.v:21703.13-21703.35" wire width 2 $1\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22115.3-22136.6" + attribute \src "libresoc.v:22421.3-22442.6" wire $1\data_r3__xer_ov_ok$next[0:0]$756 - attribute \src "libresoc.v:21404.7-21404.32" + attribute \src "libresoc.v:21707.7-21707.32" wire $1\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22137.3-22158.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $1\data_r4__xer_so$next[0:0]$763 - attribute \src "libresoc.v:21408.7-21408.29" + attribute \src "libresoc.v:21711.7-21711.29" wire $1\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22137.3-22158.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $1\data_r4__xer_so_ok$next[0:0]$764 - attribute \src "libresoc.v:21412.7-21412.32" + attribute \src "libresoc.v:21715.7-21715.32" wire $1\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22217.3-22226.6" + attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:22227.3-22236.6" + attribute \src "libresoc.v:22533.3-22542.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:22237.3-22246.6" + attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:22247.3-22256.6" + attribute \src "libresoc.v:22553.3-22562.6" wire width 2 $1\dest4_o[1:0] - attribute \src "libresoc.v:22257.3-22266.6" + attribute \src "libresoc.v:22563.3-22572.6" wire $1\dest5_o[0:0] - attribute \src "libresoc.v:21965.3-21973.6" + attribute \src "libresoc.v:22271.3-22279.6" wire $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:21435.7-21435.25" + attribute \src "libresoc.v:21738.7-21738.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:21956.3-21964.6" + attribute \src "libresoc.v:22262.3-22270.6" wire $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:21439.7-21439.25" + attribute \src "libresoc.v:21742.7-21742.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22267.3-22275.6" + attribute \src "libresoc.v:22573.3-22581.6" wire width 5 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:21570.13-21570.31" + attribute \src "libresoc.v:21876.13-21876.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:21910.3-21919.6" + attribute \src "libresoc.v:22216.3-22225.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:22001.3-22009.6" + attribute \src "libresoc.v:22307.3-22315.6" wire width 5 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:21578.13-21578.32" + attribute \src "libresoc.v:21884.13-21884.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:21992.3-22000.6" + attribute \src "libresoc.v:22298.3-22306.6" wire width 5 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:21582.13-21582.32" + attribute \src "libresoc.v:21888.13-21888.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:21929.3-21937.6" + attribute \src "libresoc.v:22235.3-22243.6" wire $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:21594.7-21594.26" + attribute \src "libresoc.v:21900.7-21900.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:21920.3-21928.6" + attribute \src "libresoc.v:22226.3-22234.6" wire $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:21598.7-21598.26" + attribute \src "libresoc.v:21904.7-21904.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:21947.3-21955.6" + attribute \src "libresoc.v:22253.3-22261.6" wire $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:21602.7-21602.25" + attribute \src "libresoc.v:21908.7-21908.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:21938.3-21946.6" + attribute \src "libresoc.v:22244.3-22252.6" wire $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:21606.7-21606.25" + attribute \src "libresoc.v:21912.7-21912.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:21983.3-21991.6" + attribute \src "libresoc.v:22289.3-22297.6" wire width 4 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:21622.13-21622.31" + attribute \src "libresoc.v:21928.13-21928.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:21974.3-21982.6" + attribute \src "libresoc.v:22280.3-22288.6" wire width 4 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:21626.13-21626.31" + attribute \src "libresoc.v:21932.13-21932.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:22159.3-22168.6" + attribute \src "libresoc.v:22465.3-22474.6" wire width 64 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:21634.14-21634.43" + attribute \src "libresoc.v:21940.14-21940.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:22169.3-22178.6" + attribute \src "libresoc.v:22475.3-22484.6" wire width 64 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:21638.14-21638.43" + attribute \src "libresoc.v:21944.14-21944.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:22179.3-22188.6" + attribute \src "libresoc.v:22485.3-22494.6" wire $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:21642.7-21642.20" + attribute \src "libresoc.v:21948.7-21948.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:22189.3-22198.6" + attribute \src "libresoc.v:22495.3-22504.6" wire width 2 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:21646.13-21646.26" + attribute \src "libresoc.v:21952.13-21952.26" wire width 2 $1\src_r3[1:0] - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 - attribute \src "libresoc.v:22010.3-22048.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22049.3-22070.6" + attribute \src "libresoc.v:22355.3-22376.6" wire width 64 $2\data_r0__o$next[63:0]$733 - attribute \src "libresoc.v:22049.3-22070.6" + attribute \src "libresoc.v:22355.3-22376.6" wire $2\data_r0__o_ok$next[0:0]$734 - attribute \src "libresoc.v:22071.3-22092.6" + attribute \src "libresoc.v:22377.3-22398.6" wire width 4 $2\data_r1__cr_a$next[3:0]$741 - attribute \src "libresoc.v:22071.3-22092.6" + attribute \src "libresoc.v:22377.3-22398.6" wire $2\data_r1__cr_a_ok$next[0:0]$742 - attribute \src "libresoc.v:22093.3-22114.6" + attribute \src "libresoc.v:22399.3-22420.6" wire width 2 $2\data_r2__xer_ca$next[1:0]$749 - attribute \src "libresoc.v:22093.3-22114.6" + attribute \src "libresoc.v:22399.3-22420.6" wire $2\data_r2__xer_ca_ok$next[0:0]$750 - attribute \src "libresoc.v:22115.3-22136.6" + attribute \src "libresoc.v:22421.3-22442.6" wire width 2 $2\data_r3__xer_ov$next[1:0]$757 - attribute \src "libresoc.v:22115.3-22136.6" + attribute \src "libresoc.v:22421.3-22442.6" wire $2\data_r3__xer_ov_ok$next[0:0]$758 - attribute \src "libresoc.v:22137.3-22158.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $2\data_r4__xer_so$next[0:0]$765 - attribute \src "libresoc.v:22137.3-22158.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $2\data_r4__xer_so_ok$next[0:0]$766 - attribute \src "libresoc.v:22049.3-22070.6" + attribute \src "libresoc.v:22355.3-22376.6" wire $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22071.3-22092.6" + attribute \src "libresoc.v:22377.3-22398.6" wire $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22093.3-22114.6" + attribute \src "libresoc.v:22399.3-22420.6" wire $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22115.3-22136.6" + attribute \src "libresoc.v:22421.3-22442.6" wire $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22137.3-22158.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:21662.18-21662.134" - wire $and$libresoc.v:21662$541_Y - attribute \src "libresoc.v:21663.19-21663.133" - wire $and$libresoc.v:21663$542_Y - attribute \src "libresoc.v:21664.19-21664.161" - wire width 4 $and$libresoc.v:21664$543_Y - attribute \src "libresoc.v:21667.19-21667.134" - wire width 4 $and$libresoc.v:21667$546_Y - attribute \src "libresoc.v:21669.19-21669.115" - wire width 4 $and$libresoc.v:21669$548_Y - attribute \src "libresoc.v:21670.19-21670.125" - wire $and$libresoc.v:21670$549_Y - attribute \src "libresoc.v:21671.19-21671.125" - wire $and$libresoc.v:21671$550_Y - attribute \src "libresoc.v:21672.18-21672.110" - wire $and$libresoc.v:21672$551_Y - attribute \src "libresoc.v:21673.19-21673.125" - wire $and$libresoc.v:21673$552_Y - attribute \src "libresoc.v:21674.19-21674.125" - wire $and$libresoc.v:21674$553_Y - attribute \src "libresoc.v:21675.19-21675.125" - wire $and$libresoc.v:21675$554_Y - attribute \src "libresoc.v:21676.19-21676.157" - wire width 5 $and$libresoc.v:21676$555_Y - attribute \src "libresoc.v:21677.19-21677.121" - wire width 5 $and$libresoc.v:21677$556_Y - attribute \src "libresoc.v:21678.19-21678.127" - wire $and$libresoc.v:21678$557_Y - attribute \src "libresoc.v:21679.19-21679.127" - wire $and$libresoc.v:21679$558_Y - attribute \src "libresoc.v:21680.19-21680.127" - wire $and$libresoc.v:21680$559_Y - attribute \src "libresoc.v:21681.19-21681.127" - wire $and$libresoc.v:21681$560_Y - attribute \src "libresoc.v:21682.19-21682.127" - wire $and$libresoc.v:21682$561_Y - attribute \src "libresoc.v:21684.18-21684.98" - wire $and$libresoc.v:21684$563_Y - attribute \src "libresoc.v:21686.18-21686.100" - wire $and$libresoc.v:21686$565_Y - attribute \src "libresoc.v:21687.18-21687.171" - wire width 5 $and$libresoc.v:21687$566_Y - attribute \src "libresoc.v:21689.18-21689.119" - wire width 5 $and$libresoc.v:21689$568_Y - attribute \src "libresoc.v:21692.18-21692.116" - wire $and$libresoc.v:21692$571_Y - attribute \src "libresoc.v:21696.17-21696.123" - wire $and$libresoc.v:21696$575_Y - attribute \src "libresoc.v:21698.18-21698.113" - wire $and$libresoc.v:21698$577_Y - attribute \src "libresoc.v:21699.18-21699.125" - wire width 5 $and$libresoc.v:21699$578_Y - attribute \src "libresoc.v:21701.18-21701.112" - wire $and$libresoc.v:21701$580_Y - attribute \src "libresoc.v:21703.18-21703.126" - wire $and$libresoc.v:21703$582_Y - attribute \src "libresoc.v:21704.18-21704.126" - wire $and$libresoc.v:21704$583_Y - attribute \src "libresoc.v:21705.18-21705.117" - wire $and$libresoc.v:21705$584_Y - attribute \src "libresoc.v:21710.18-21710.130" - wire $and$libresoc.v:21710$589_Y - attribute \src "libresoc.v:21711.18-21711.124" - wire width 5 $and$libresoc.v:21711$590_Y - attribute \src "libresoc.v:21714.18-21714.116" - wire $and$libresoc.v:21714$593_Y - attribute \src "libresoc.v:21715.18-21715.119" - wire $and$libresoc.v:21715$594_Y - attribute \src "libresoc.v:21716.18-21716.121" - wire $and$libresoc.v:21716$595_Y - attribute \src "libresoc.v:21717.18-21717.121" - wire $and$libresoc.v:21717$596_Y - attribute \src "libresoc.v:21718.18-21718.121" - wire $and$libresoc.v:21718$597_Y - attribute \src "libresoc.v:21700.18-21700.113" - wire $eq$libresoc.v:21700$579_Y - attribute \src "libresoc.v:21702.18-21702.119" - wire $eq$libresoc.v:21702$581_Y - attribute \src "libresoc.v:21665.19-21665.126" - wire $not$libresoc.v:21665$544_Y - attribute \src "libresoc.v:21666.19-21666.132" - wire $not$libresoc.v:21666$545_Y - attribute \src "libresoc.v:21668.19-21668.115" - wire width 4 $not$libresoc.v:21668$547_Y - attribute \src "libresoc.v:21683.18-21683.97" - wire $not$libresoc.v:21683$562_Y - attribute \src "libresoc.v:21685.18-21685.99" - wire $not$libresoc.v:21685$564_Y - attribute \src "libresoc.v:21688.18-21688.113" - wire width 5 $not$libresoc.v:21688$567_Y - attribute \src "libresoc.v:21691.18-21691.106" - wire $not$libresoc.v:21691$570_Y - attribute \src "libresoc.v:21697.18-21697.120" - wire $not$libresoc.v:21697$576_Y - attribute \src "libresoc.v:21712.17-21712.113" - wire width 4 $not$libresoc.v:21712$591_Y - attribute \src "libresoc.v:21695.18-21695.112" - wire $or$libresoc.v:21695$574_Y - attribute \src "libresoc.v:21706.18-21706.122" - wire $or$libresoc.v:21706$585_Y - attribute \src "libresoc.v:21707.18-21707.124" - wire $or$libresoc.v:21707$586_Y - attribute \src "libresoc.v:21708.18-21708.181" - wire width 5 $or$libresoc.v:21708$587_Y - attribute \src "libresoc.v:21709.18-21709.168" - wire width 4 $or$libresoc.v:21709$588_Y - attribute \src "libresoc.v:21713.18-21713.120" - wire width 5 $or$libresoc.v:21713$592_Y - attribute \src "libresoc.v:21722.17-21722.117" - wire width 4 $or$libresoc.v:21722$601_Y - attribute \src "libresoc.v:21661.17-21661.104" - wire $reduce_and$libresoc.v:21661$540_Y - attribute \src "libresoc.v:21690.18-21690.106" - wire $reduce_or$libresoc.v:21690$569_Y - attribute \src "libresoc.v:21693.18-21693.113" - wire $reduce_or$libresoc.v:21693$572_Y - attribute \src "libresoc.v:21694.18-21694.112" - wire $reduce_or$libresoc.v:21694$573_Y - attribute \src "libresoc.v:21719.18-21719.154" - wire $ternary$libresoc.v:21719$598_Y - attribute \src "libresoc.v:21720.18-21720.155" - wire width 64 $ternary$libresoc.v:21720$599_Y - attribute \src "libresoc.v:21721.18-21721.160" - wire $ternary$libresoc.v:21721$600_Y - attribute \src "libresoc.v:21723.18-21723.172" - wire width 64 $ternary$libresoc.v:21723$602_Y - attribute \src "libresoc.v:21724.18-21724.115" - wire width 64 $ternary$libresoc.v:21724$603_Y - attribute \src "libresoc.v:21725.18-21725.125" - wire width 64 $ternary$libresoc.v:21725$604_Y - attribute \src "libresoc.v:21726.18-21726.118" - wire $ternary$libresoc.v:21726$605_Y - attribute \src "libresoc.v:21727.18-21727.118" - wire width 2 $ternary$libresoc.v:21727$606_Y + attribute \src "libresoc.v:21968.18-21968.134" + wire $and$libresoc.v:21968$541_Y + attribute \src "libresoc.v:21969.19-21969.133" + wire $and$libresoc.v:21969$542_Y + attribute \src "libresoc.v:21970.19-21970.161" + wire width 4 $and$libresoc.v:21970$543_Y + attribute \src "libresoc.v:21973.19-21973.134" + wire width 4 $and$libresoc.v:21973$546_Y + attribute \src "libresoc.v:21975.19-21975.115" + wire width 4 $and$libresoc.v:21975$548_Y + attribute \src "libresoc.v:21976.19-21976.125" + wire $and$libresoc.v:21976$549_Y + attribute \src "libresoc.v:21977.19-21977.125" + wire $and$libresoc.v:21977$550_Y + attribute \src "libresoc.v:21978.18-21978.110" + wire $and$libresoc.v:21978$551_Y + attribute \src "libresoc.v:21979.19-21979.125" + wire $and$libresoc.v:21979$552_Y + attribute \src "libresoc.v:21980.19-21980.125" + wire $and$libresoc.v:21980$553_Y + attribute \src "libresoc.v:21981.19-21981.125" + wire $and$libresoc.v:21981$554_Y + attribute \src "libresoc.v:21982.19-21982.157" + wire width 5 $and$libresoc.v:21982$555_Y + attribute \src "libresoc.v:21983.19-21983.121" + wire width 5 $and$libresoc.v:21983$556_Y + attribute \src "libresoc.v:21984.19-21984.127" + wire $and$libresoc.v:21984$557_Y + attribute \src "libresoc.v:21985.19-21985.127" + wire $and$libresoc.v:21985$558_Y + attribute \src "libresoc.v:21986.19-21986.127" + wire $and$libresoc.v:21986$559_Y + attribute \src "libresoc.v:21987.19-21987.127" + wire $and$libresoc.v:21987$560_Y + attribute \src "libresoc.v:21988.19-21988.127" + wire $and$libresoc.v:21988$561_Y + attribute \src "libresoc.v:21990.18-21990.98" + wire $and$libresoc.v:21990$563_Y + attribute \src "libresoc.v:21992.18-21992.100" + wire $and$libresoc.v:21992$565_Y + attribute \src "libresoc.v:21993.18-21993.171" + wire width 5 $and$libresoc.v:21993$566_Y + attribute \src "libresoc.v:21995.18-21995.119" + wire width 5 $and$libresoc.v:21995$568_Y + attribute \src "libresoc.v:21998.18-21998.116" + wire $and$libresoc.v:21998$571_Y + attribute \src "libresoc.v:22002.17-22002.123" + wire $and$libresoc.v:22002$575_Y + attribute \src "libresoc.v:22004.18-22004.113" + wire $and$libresoc.v:22004$577_Y + attribute \src "libresoc.v:22005.18-22005.125" + wire width 5 $and$libresoc.v:22005$578_Y + attribute \src "libresoc.v:22007.18-22007.112" + wire $and$libresoc.v:22007$580_Y + attribute \src "libresoc.v:22009.18-22009.126" + wire $and$libresoc.v:22009$582_Y + attribute \src "libresoc.v:22010.18-22010.126" + wire $and$libresoc.v:22010$583_Y + attribute \src "libresoc.v:22011.18-22011.117" + wire $and$libresoc.v:22011$584_Y + attribute \src "libresoc.v:22016.18-22016.130" + wire $and$libresoc.v:22016$589_Y + attribute \src "libresoc.v:22017.18-22017.124" + wire width 5 $and$libresoc.v:22017$590_Y + attribute \src "libresoc.v:22020.18-22020.116" + wire $and$libresoc.v:22020$593_Y + attribute \src "libresoc.v:22021.18-22021.119" + wire $and$libresoc.v:22021$594_Y + attribute \src "libresoc.v:22022.18-22022.121" + wire $and$libresoc.v:22022$595_Y + attribute \src "libresoc.v:22023.18-22023.121" + wire $and$libresoc.v:22023$596_Y + attribute \src "libresoc.v:22024.18-22024.121" + wire $and$libresoc.v:22024$597_Y + attribute \src "libresoc.v:22006.18-22006.113" + wire $eq$libresoc.v:22006$579_Y + attribute \src "libresoc.v:22008.18-22008.119" + wire $eq$libresoc.v:22008$581_Y + attribute \src "libresoc.v:21971.19-21971.126" + wire $not$libresoc.v:21971$544_Y + attribute \src "libresoc.v:21972.19-21972.132" + wire $not$libresoc.v:21972$545_Y + attribute \src "libresoc.v:21974.19-21974.115" + wire width 4 $not$libresoc.v:21974$547_Y + attribute \src "libresoc.v:21989.18-21989.97" + wire $not$libresoc.v:21989$562_Y + attribute \src "libresoc.v:21991.18-21991.99" + wire $not$libresoc.v:21991$564_Y + attribute \src "libresoc.v:21994.18-21994.113" + wire width 5 $not$libresoc.v:21994$567_Y + attribute \src "libresoc.v:21997.18-21997.106" + wire $not$libresoc.v:21997$570_Y + attribute \src "libresoc.v:22003.18-22003.120" + wire $not$libresoc.v:22003$576_Y + attribute \src "libresoc.v:22018.17-22018.113" + wire width 4 $not$libresoc.v:22018$591_Y + attribute \src "libresoc.v:22001.18-22001.112" + wire $or$libresoc.v:22001$574_Y + attribute \src "libresoc.v:22012.18-22012.122" + wire $or$libresoc.v:22012$585_Y + attribute \src "libresoc.v:22013.18-22013.124" + wire $or$libresoc.v:22013$586_Y + attribute \src "libresoc.v:22014.18-22014.181" + wire width 5 $or$libresoc.v:22014$587_Y + attribute \src "libresoc.v:22015.18-22015.168" + wire width 4 $or$libresoc.v:22015$588_Y + attribute \src "libresoc.v:22019.18-22019.120" + wire width 5 $or$libresoc.v:22019$592_Y + attribute \src "libresoc.v:22028.17-22028.117" + wire width 4 $or$libresoc.v:22028$601_Y + attribute \src "libresoc.v:21967.17-21967.104" + wire $reduce_and$libresoc.v:21967$540_Y + attribute \src "libresoc.v:21996.18-21996.106" + wire $reduce_or$libresoc.v:21996$569_Y + attribute \src "libresoc.v:21999.18-21999.113" + wire $reduce_or$libresoc.v:21999$572_Y + attribute \src "libresoc.v:22000.18-22000.112" + wire $reduce_or$libresoc.v:22000$573_Y + attribute \src "libresoc.v:22025.18-22025.154" + wire $ternary$libresoc.v:22025$598_Y + attribute \src "libresoc.v:22026.18-22026.155" + wire width 64 $ternary$libresoc.v:22026$599_Y + attribute \src "libresoc.v:22027.18-22027.160" + wire $ternary$libresoc.v:22027$600_Y + attribute \src "libresoc.v:22029.18-22029.172" + wire width 64 $ternary$libresoc.v:22029$602_Y + attribute \src "libresoc.v:22030.18-22030.115" + wire width 64 $ternary$libresoc.v:22030$603_Y + attribute \src "libresoc.v:22031.18-22031.125" + wire width 64 $ternary$libresoc.v:22031$604_Y + attribute \src "libresoc.v:22032.18-22032.118" + wire $ternary$libresoc.v:22032$605_Y + attribute \src "libresoc.v:22033.18-22033.118" + wire width 2 $ternary$libresoc.v:22033$606_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -31526,7 +31841,7 @@ module \alu0 wire width 5 \$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$129 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$131 @@ -31536,11 +31851,11 @@ module \alu0 wire \$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$137 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 5 \$21 @@ -31618,47 +31933,49 @@ module \alu0 wire \$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 2 \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_alu0_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_alu0_alu_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_alu0_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_alu0_alu_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_alu0_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_alu0_alu_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_alu0_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -31753,6 +32070,7 @@ module \alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_alu0_alu_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -31803,15 +32121,15 @@ module \alu0 wire \alu_alu0_alu_op__zero_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_alu0_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_alu0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_alu0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_alu0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_alu0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_alu0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_alu0_ra @@ -31829,35 +32147,35 @@ module \alu0 wire \alu_alu0_xer_so$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 5 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -31933,37 +32251,39 @@ module \alu0 wire width 2 output 38 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 40 \dest5_o - attribute \src "libresoc.v:20985.7-20985.15" + attribute \src "libresoc.v:21285.7-21285.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_alu0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_alu0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -32050,6 +32370,7 @@ module \alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -32080,15 +32401,15 @@ module \alu0 wire width 5 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -32096,23 +32417,23 @@ module \alu0 wire width 4 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -32124,35 +32445,35 @@ module \alu0 wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 28 \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm$88 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel @@ -32167,7 +32488,7 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 39 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:21662$541 + cell $and $and$libresoc.v:21968$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32175,10 +32496,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:21662$541_Y + connect \Y $and$libresoc.v:21968$541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:21663$542 + cell $and $and$libresoc.v:21969$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32186,10 +32507,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:21663$542_Y + connect \Y $and$libresoc.v:21969$542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21664$543 + cell $and $and$libresoc.v:21970$543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32197,10 +32518,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21664$543_Y + connect \Y $and$libresoc.v:21970$543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21667$546 + cell $and $and$libresoc.v:21973$546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32208,10 +32529,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$103 connect \B { 2'11 \$107 \$105 } - connect \Y $and$libresoc.v:21667$546_Y + connect \Y $and$libresoc.v:21973$546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21669$548 + cell $and $and$libresoc.v:21975$548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32219,10 +32540,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$109 connect \B \$111 - connect \Y $and$libresoc.v:21669$548_Y + connect \Y $and$libresoc.v:21975$548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21670$549 + cell $and $and$libresoc.v:21976$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32230,10 +32551,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21670$549_Y + connect \Y $and$libresoc.v:21976$549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21671$550 + cell $and $and$libresoc.v:21977$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32241,10 +32562,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21671$550_Y + connect \Y $and$libresoc.v:21977$550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:21672$551 + cell $and $and$libresoc.v:21978$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32252,10 +32573,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:21672$551_Y + connect \Y $and$libresoc.v:21978$551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21673$552 + cell $and $and$libresoc.v:21979$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32263,10 +32584,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21673$552_Y + connect \Y $and$libresoc.v:21979$552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21674$553 + cell $and $and$libresoc.v:21980$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32274,10 +32595,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21674$553_Y + connect \Y $and$libresoc.v:21980$553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21675$554 + cell $and $and$libresoc.v:21981$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32285,10 +32606,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21675$554_Y + connect \Y $and$libresoc.v:21981$554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21676$555 + cell $and $and$libresoc.v:21982$555 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32296,10 +32617,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$115 \$117 \$119 \$121 \$123 } - connect \Y $and$libresoc.v:21676$555_Y + connect \Y $and$libresoc.v:21982$555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21677$556 + cell $and $and$libresoc.v:21983$556 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32307,10 +32628,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \$125 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21677$556_Y + connect \Y $and$libresoc.v:21983$556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21678$557 + cell $and $and$libresoc.v:21984$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32318,10 +32639,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21678$557_Y + connect \Y $and$libresoc.v:21984$557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21679$558 + cell $and $and$libresoc.v:21985$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32329,10 +32650,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21679$558_Y + connect \Y $and$libresoc.v:21985$558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21680$559 + cell $and $and$libresoc.v:21986$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32340,10 +32661,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21680$559_Y + connect \Y $and$libresoc.v:21986$559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21681$560 + cell $and $and$libresoc.v:21987$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32351,10 +32672,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21681$560_Y + connect \Y $and$libresoc.v:21987$560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21682$561 + cell $and $and$libresoc.v:21988$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32362,10 +32683,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21682$561_Y + connect \Y $and$libresoc.v:21988$561_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:21684$563 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:21990$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32373,10 +32694,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:21684$563_Y + connect \Y $and$libresoc.v:21990$563_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:21686$565 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:21992$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32384,10 +32705,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:21686$565_Y + connect \Y $and$libresoc.v:21992$565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:21687$566 + cell $and $and$libresoc.v:21993$566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32395,10 +32716,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21687$566_Y + connect \Y $and$libresoc.v:21993$566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21689$568 + cell $and $and$libresoc.v:21995$568 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32406,10 +32727,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:21689$568_Y + connect \Y $and$libresoc.v:21995$568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21692$571 + cell $and $and$libresoc.v:21998$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32417,10 +32738,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:21692$571_Y + connect \Y $and$libresoc.v:21998$571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:21696$575 + cell $and $and$libresoc.v:22002$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32428,10 +32749,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:21696$575_Y + connect \Y $and$libresoc.v:22002$575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:21698$577 + cell $and $and$libresoc.v:22004$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32439,10 +32760,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:21698$577_Y + connect \Y $and$libresoc.v:22004$577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:21699$578 + cell $and $and$libresoc.v:22005$578 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32450,10 +32771,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21699$578_Y + connect \Y $and$libresoc.v:22005$578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:21701$580 + cell $and $and$libresoc.v:22007$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32461,10 +32782,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:21701$580_Y + connect \Y $and$libresoc.v:22007$580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21703$582 + cell $and $and$libresoc.v:22009$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32472,10 +32793,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_alu0_n_ready_i - connect \Y $and$libresoc.v:21703$582_Y + connect \Y $and$libresoc.v:22009$582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21704$583 + cell $and $and$libresoc.v:22010$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32483,10 +32804,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_alu0_n_valid_o - connect \Y $and$libresoc.v:21704$583_Y + connect \Y $and$libresoc.v:22010$583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21705$584 + cell $and $and$libresoc.v:22011$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32494,10 +32815,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:21705$584_Y + connect \Y $and$libresoc.v:22011$584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:21710$589 + cell $and $and$libresoc.v:22016$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32505,10 +32826,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:21710$589_Y + connect \Y $and$libresoc.v:22016$589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:21711$590 + cell $and $and$libresoc.v:22017$590 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32516,10 +32837,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21711$590_Y + connect \Y $and$libresoc.v:22017$590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21714$593 + cell $and $and$libresoc.v:22020$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32527,10 +32848,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21714$593_Y + connect \Y $and$libresoc.v:22020$593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21715$594 + cell $and $and$libresoc.v:22021$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32538,10 +32859,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21715$594_Y + connect \Y $and$libresoc.v:22021$594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21716$595 + cell $and $and$libresoc.v:22022$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32549,10 +32870,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21716$595_Y + connect \Y $and$libresoc.v:22022$595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21717$596 + cell $and $and$libresoc.v:22023$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32560,10 +32881,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21717$596_Y + connect \Y $and$libresoc.v:22023$596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21718$597 + cell $and $and$libresoc.v:22024$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32571,10 +32892,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21718$597_Y + connect \Y $and$libresoc.v:22024$597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:21700$579 + cell $eq $eq$libresoc.v:22006$579 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32582,10 +32903,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:21700$579_Y + connect \Y $eq$libresoc.v:22006$579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:21702$581 + cell $eq $eq$libresoc.v:22008$581 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32593,82 +32914,82 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:21702$581_Y + connect \Y $eq$libresoc.v:22008$581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21665$544 + cell $not $not$libresoc.v:21971$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__zero_a - connect \Y $not$libresoc.v:21665$544_Y + connect \Y $not$libresoc.v:21971$544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21666$545 + cell $not $not$libresoc.v:21972$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__imm_data__ok - connect \Y $not$libresoc.v:21666$545_Y + connect \Y $not$libresoc.v:21972$545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:21668$547 + cell $not $not$libresoc.v:21974$547 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:21668$547_Y + connect \Y $not$libresoc.v:21974$547_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:21683$562 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:21989$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:21683$562_Y + connect \Y $not$libresoc.v:21989$562_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:21685$564 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:21991$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:21685$564_Y + connect \Y $not$libresoc.v:21991$564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21688$567 + cell $not $not$libresoc.v:21994$567 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:21688$567_Y + connect \Y $not$libresoc.v:21994$567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21691$570 + cell $not $not$libresoc.v:21997$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:21691$570_Y + connect \Y $not$libresoc.v:21997$570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:21697$576 + cell $not $not$libresoc.v:22003$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_ready_i - connect \Y $not$libresoc.v:21697$576_Y + connect \Y $not$libresoc.v:22003$576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:21712$591 + cell $not $not$libresoc.v:22018$591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:21712$591_Y + connect \Y $not$libresoc.v:22018$591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:21695$574 + cell $or $or$libresoc.v:22001$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32676,10 +32997,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:21695$574_Y + connect \Y $or$libresoc.v:22001$574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:21706$585 + cell $or $or$libresoc.v:22012$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32687,10 +33008,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:21706$585_Y + connect \Y $or$libresoc.v:22012$585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:21707$586 + cell $or $or$libresoc.v:22013$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32698,10 +33019,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:21707$586_Y + connect \Y $or$libresoc.v:22013$586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:21708$587 + cell $or $or$libresoc.v:22014$587 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32709,10 +33030,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:21708$587_Y + connect \Y $or$libresoc.v:22014$587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:21709$588 + cell $or $or$libresoc.v:22015$588 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32720,10 +33041,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:21709$588_Y + connect \Y $or$libresoc.v:22015$588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:21713$592 + cell $or $or$libresoc.v:22019$592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32731,10 +33052,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:21713$592_Y + connect \Y $or$libresoc.v:22019$592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:21722$601 + cell $or $or$libresoc.v:22028$601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32742,106 +33063,106 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:21722$601_Y + connect \Y $or$libresoc.v:22028$601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:21661$540 + cell $reduce_and $reduce_and$libresoc.v:21967$540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:21661$540_Y + connect \Y $reduce_and$libresoc.v:21967$540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:21690$569 + cell $reduce_or $reduce_or$libresoc.v:21996$569 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:21690$569_Y + connect \Y $reduce_or$libresoc.v:21996$569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21693$572 + cell $reduce_or $reduce_or$libresoc.v:21999$572 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:21693$572_Y + connect \Y $reduce_or$libresoc.v:21999$572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21694$573 + cell $reduce_or $reduce_or$libresoc.v:22000$573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:21694$573_Y + connect \Y $reduce_or$libresoc.v:22000$573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:21719$598 + cell $mux $ternary$libresoc.v:22025$598 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:21719$598_Y + connect \Y $ternary$libresoc.v:22025$598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:21720$599 + cell $mux $ternary$libresoc.v:22026$599 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:21720$599_Y + connect \Y $ternary$libresoc.v:22026$599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:21721$600 + cell $mux $ternary$libresoc.v:22027$600 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:21721$600_Y + connect \Y $ternary$libresoc.v:22027$600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:21723$602 + cell $mux $ternary$libresoc.v:22029$602 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_alu0_alu_op__imm_data__data connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:21723$602_Y + connect \Y $ternary$libresoc.v:22029$602_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21724$603 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:22030$603 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:21724$603_Y + connect \Y $ternary$libresoc.v:22030$603_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21725$604 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:22031$604 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$88 connect \S \src_sel$85 - connect \Y $ternary$libresoc.v:21725$604_Y + connect \Y $ternary$libresoc.v:22031$604_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21726$605 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:22032$605 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:21726$605_Y + connect \Y $ternary$libresoc.v:22032$605_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21727$606 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:22033$606 parameter \WIDTH 2 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:21727$606_Y + connect \Y $ternary$libresoc.v:22033$606_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:21822.12-21861.4" + attribute \src "libresoc.v:22128.12-22167.4" cell \alu_alu0 \alu_alu0 connect \alu_op__data_len \alu_alu0_alu_op__data_len connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit @@ -32883,7 +33204,7 @@ module \alu0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:21862.9-21868.4" + attribute \src "libresoc.v:22168.9-22174.4" cell \alu_l \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32892,7 +33213,7 @@ module \alu0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:21869.10-21875.4" + attribute \src "libresoc.v:22175.10-22181.4" cell \alui_l \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32901,7 +33222,7 @@ module \alu0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:21876.9-21882.4" + attribute \src "libresoc.v:22182.9-22188.4" cell \opc_l \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32910,7 +33231,7 @@ module \alu0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:21883.9-21889.4" + attribute \src "libresoc.v:22189.9-22195.4" cell \req_l \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32919,7 +33240,7 @@ module \alu0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:21890.9-21896.4" + attribute \src "libresoc.v:22196.9-22202.4" cell \rok_l \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32928,7 +33249,7 @@ module \alu0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:21897.9-21902.4" + attribute \src "libresoc.v:22203.9-22208.4" cell \rst_l \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32936,7 +33257,7 @@ module \alu0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:21903.9-21909.4" + attribute \src "libresoc.v:22209.9-22215.4" cell \src_l \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32944,727 +33265,727 @@ module \alu0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:20985.7-20985.20" - process $proc$libresoc.v:20985$794 + attribute \src "libresoc.v:21285.7-21285.20" + process $proc$libresoc.v:21285$794 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21123.7-21123.24" - process $proc$libresoc.v:21123$795 + attribute \src "libresoc.v:21423.7-21423.24" + process $proc$libresoc.v:21423$795 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:21131.13-21131.45" - process $proc$libresoc.v:21131$796 + attribute \src "libresoc.v:21431.13-21431.45" + process $proc$libresoc.v:21431$796 assign { } { } assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:21148.14-21148.48" - process $proc$libresoc.v:21148$797 + attribute \src "libresoc.v:21450.14-21450.49" + process $proc$libresoc.v:21450$797 assign { } { } - assign $1\alu_alu0_alu_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_alu0_alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[11:0] + update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:21152.14-21152.68" - process $proc$libresoc.v:21152$798 + attribute \src "libresoc.v:21454.14-21454.68" + process $proc$libresoc.v:21454$798 assign { } { } assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:21156.7-21156.43" - process $proc$libresoc.v:21156$799 + attribute \src "libresoc.v:21458.7-21458.43" + process $proc$libresoc.v:21458$799 assign { } { } assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:21164.13-21164.48" - process $proc$libresoc.v:21164$800 + attribute \src "libresoc.v:21466.13-21466.48" + process $proc$libresoc.v:21466$800 assign { } { } assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:21168.14-21168.43" - process $proc$libresoc.v:21168$801 + attribute \src "libresoc.v:21470.14-21470.43" + process $proc$libresoc.v:21470$801 assign { } { } assign $1\alu_alu0_alu_op__insn[31:0] 0 sync always sync init update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:21246.13-21246.47" - process $proc$libresoc.v:21246$802 + attribute \src "libresoc.v:21549.13-21549.47" + process $proc$libresoc.v:21549$802 assign { } { } assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:21250.7-21250.40" - process $proc$libresoc.v:21250$803 + attribute \src "libresoc.v:21553.7-21553.40" + process $proc$libresoc.v:21553$803 assign { } { } assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:21254.7-21254.41" - process $proc$libresoc.v:21254$804 + attribute \src "libresoc.v:21557.7-21557.41" + process $proc$libresoc.v:21557$804 assign { } { } assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:21258.7-21258.39" - process $proc$libresoc.v:21258$805 + attribute \src "libresoc.v:21561.7-21561.39" + process $proc$libresoc.v:21561$805 assign { } { } assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:21262.7-21262.40" - process $proc$libresoc.v:21262$806 + attribute \src "libresoc.v:21565.7-21565.40" + process $proc$libresoc.v:21565$806 assign { } { } assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:21266.7-21266.37" - process $proc$libresoc.v:21266$807 + attribute \src "libresoc.v:21569.7-21569.37" + process $proc$libresoc.v:21569$807 assign { } { } assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:21270.7-21270.37" - process $proc$libresoc.v:21270$808 + attribute \src "libresoc.v:21573.7-21573.37" + process $proc$libresoc.v:21573$808 assign { } { } assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:21274.7-21274.43" - process $proc$libresoc.v:21274$809 + attribute \src "libresoc.v:21577.7-21577.43" + process $proc$libresoc.v:21577$809 assign { } { } assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:21278.7-21278.37" - process $proc$libresoc.v:21278$810 + attribute \src "libresoc.v:21581.7-21581.37" + process $proc$libresoc.v:21581$810 assign { } { } assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:21282.7-21282.37" - process $proc$libresoc.v:21282$811 + attribute \src "libresoc.v:21585.7-21585.37" + process $proc$libresoc.v:21585$811 assign { } { } assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:21286.7-21286.40" - process $proc$libresoc.v:21286$812 + attribute \src "libresoc.v:21589.7-21589.40" + process $proc$libresoc.v:21589$812 assign { } { } assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:21290.7-21290.37" - process $proc$libresoc.v:21290$813 + attribute \src "libresoc.v:21593.7-21593.37" + process $proc$libresoc.v:21593$813 assign { } { } assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:21322.7-21322.26" - process $proc$libresoc.v:21322$814 + attribute \src "libresoc.v:21625.7-21625.26" + process $proc$libresoc.v:21625$814 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:21330.7-21330.25" - process $proc$libresoc.v:21330$815 + attribute \src "libresoc.v:21633.7-21633.25" + process $proc$libresoc.v:21633$815 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:21342.7-21342.27" - process $proc$libresoc.v:21342$816 + attribute \src "libresoc.v:21645.7-21645.27" + process $proc$libresoc.v:21645$816 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:21376.14-21376.47" - process $proc$libresoc.v:21376$817 + attribute \src "libresoc.v:21679.14-21679.47" + process $proc$libresoc.v:21679$817 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:21380.7-21380.27" - process $proc$libresoc.v:21380$818 + attribute \src "libresoc.v:21683.7-21683.27" + process $proc$libresoc.v:21683$818 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:21384.13-21384.33" - process $proc$libresoc.v:21384$819 + attribute \src "libresoc.v:21687.13-21687.33" + process $proc$libresoc.v:21687$819 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:21388.7-21388.30" - process $proc$libresoc.v:21388$820 + attribute \src "libresoc.v:21691.7-21691.30" + process $proc$libresoc.v:21691$820 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:21392.13-21392.35" - process $proc$libresoc.v:21392$821 + attribute \src "libresoc.v:21695.13-21695.35" + process $proc$libresoc.v:21695$821 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:21396.7-21396.32" - process $proc$libresoc.v:21396$822 + attribute \src "libresoc.v:21699.7-21699.32" + process $proc$libresoc.v:21699$822 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:21400.13-21400.35" - process $proc$libresoc.v:21400$823 + attribute \src "libresoc.v:21703.13-21703.35" + process $proc$libresoc.v:21703$823 assign { } { } assign $1\data_r3__xer_ov[1:0] 2'00 sync always sync init update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:21404.7-21404.32" - process $proc$libresoc.v:21404$824 + attribute \src "libresoc.v:21707.7-21707.32" + process $proc$libresoc.v:21707$824 assign { } { } assign $1\data_r3__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:21408.7-21408.29" - process $proc$libresoc.v:21408$825 + attribute \src "libresoc.v:21711.7-21711.29" + process $proc$libresoc.v:21711$825 assign { } { } assign $1\data_r4__xer_so[0:0] 1'0 sync always sync init update \data_r4__xer_so $1\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:21412.7-21412.32" - process $proc$libresoc.v:21412$826 + attribute \src "libresoc.v:21715.7-21715.32" + process $proc$libresoc.v:21715$826 assign { } { } assign $1\data_r4__xer_so_ok[0:0] 1'0 sync always sync init update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:21435.7-21435.25" - process $proc$libresoc.v:21435$827 + attribute \src "libresoc.v:21738.7-21738.25" + process $proc$libresoc.v:21738$827 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:21439.7-21439.25" - process $proc$libresoc.v:21439$828 + attribute \src "libresoc.v:21742.7-21742.25" + process $proc$libresoc.v:21742$828 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:21570.13-21570.31" - process $proc$libresoc.v:21570$829 + attribute \src "libresoc.v:21876.13-21876.31" + process $proc$libresoc.v:21876$829 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:21578.13-21578.32" - process $proc$libresoc.v:21578$830 + attribute \src "libresoc.v:21884.13-21884.32" + process $proc$libresoc.v:21884$830 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:21582.13-21582.32" - process $proc$libresoc.v:21582$831 + attribute \src "libresoc.v:21888.13-21888.32" + process $proc$libresoc.v:21888$831 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:21594.7-21594.26" - process $proc$libresoc.v:21594$832 + attribute \src "libresoc.v:21900.7-21900.26" + process $proc$libresoc.v:21900$832 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:21598.7-21598.26" - process $proc$libresoc.v:21598$833 + attribute \src "libresoc.v:21904.7-21904.26" + process $proc$libresoc.v:21904$833 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:21602.7-21602.25" - process $proc$libresoc.v:21602$834 + attribute \src "libresoc.v:21908.7-21908.25" + process $proc$libresoc.v:21908$834 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:21606.7-21606.25" - process $proc$libresoc.v:21606$835 + attribute \src "libresoc.v:21912.7-21912.25" + process $proc$libresoc.v:21912$835 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:21622.13-21622.31" - process $proc$libresoc.v:21622$836 + attribute \src "libresoc.v:21928.13-21928.31" + process $proc$libresoc.v:21928$836 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:21626.13-21626.31" - process $proc$libresoc.v:21626$837 + attribute \src "libresoc.v:21932.13-21932.31" + process $proc$libresoc.v:21932$837 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:21634.14-21634.43" - process $proc$libresoc.v:21634$838 + attribute \src "libresoc.v:21940.14-21940.43" + process $proc$libresoc.v:21940$838 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:21638.14-21638.43" - process $proc$libresoc.v:21638$839 + attribute \src "libresoc.v:21944.14-21944.43" + process $proc$libresoc.v:21944$839 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:21642.7-21642.20" - process $proc$libresoc.v:21642$840 + attribute \src "libresoc.v:21948.7-21948.20" + process $proc$libresoc.v:21948$840 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:21646.13-21646.26" - process $proc$libresoc.v:21646$841 + attribute \src "libresoc.v:21952.13-21952.26" + process $proc$libresoc.v:21952$841 assign { } { } assign $1\src_r3[1:0] 2'00 sync always sync init update \src_r3 $1\src_r3[1:0] end - attribute \src "libresoc.v:21728.3-21729.39" - process $proc$libresoc.v:21728$607 + attribute \src "libresoc.v:22034.3-22035.39" + process $proc$libresoc.v:22034$607 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:21730.3-21731.43" - process $proc$libresoc.v:21730$608 + attribute \src "libresoc.v:22036.3-22037.43" + process $proc$libresoc.v:22036$608 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:21732.3-21733.29" - process $proc$libresoc.v:21732$609 + attribute \src "libresoc.v:22038.3-22039.29" + process $proc$libresoc.v:22038$609 assign { } { } assign $0\src_r3[1:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[1:0] end - attribute \src "libresoc.v:21734.3-21735.29" - process $proc$libresoc.v:21734$610 + attribute \src "libresoc.v:22040.3-22041.29" + process $proc$libresoc.v:22040$610 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:21736.3-21737.29" - process $proc$libresoc.v:21736$611 + attribute \src "libresoc.v:22042.3-22043.29" + process $proc$libresoc.v:22042$611 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:21738.3-21739.29" - process $proc$libresoc.v:21738$612 + attribute \src "libresoc.v:22044.3-22045.29" + process $proc$libresoc.v:22044$612 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:21740.3-21741.47" - process $proc$libresoc.v:21740$613 + attribute \src "libresoc.v:22046.3-22047.47" + process $proc$libresoc.v:22046$613 assign { } { } assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next sync posedge \coresync_clk update \data_r4__xer_so $0\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:21742.3-21743.53" - process $proc$libresoc.v:21742$614 + attribute \src "libresoc.v:22048.3-22049.53" + process $proc$libresoc.v:22048$614 assign { } { } assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next sync posedge \coresync_clk update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:21744.3-21745.47" - process $proc$libresoc.v:21744$615 + attribute \src "libresoc.v:22050.3-22051.47" + process $proc$libresoc.v:22050$615 assign { } { } assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next sync posedge \coresync_clk update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:21746.3-21747.53" - process $proc$libresoc.v:21746$616 + attribute \src "libresoc.v:22052.3-22053.53" + process $proc$libresoc.v:22052$616 assign { } { } assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next sync posedge \coresync_clk update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:21748.3-21749.47" - process $proc$libresoc.v:21748$617 + attribute \src "libresoc.v:22054.3-22055.47" + process $proc$libresoc.v:22054$617 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:21750.3-21751.53" - process $proc$libresoc.v:21750$618 + attribute \src "libresoc.v:22056.3-22057.53" + process $proc$libresoc.v:22056$618 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:21752.3-21753.43" - process $proc$libresoc.v:21752$619 + attribute \src "libresoc.v:22058.3-22059.43" + process $proc$libresoc.v:22058$619 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:21754.3-21755.49" - process $proc$libresoc.v:21754$620 + attribute \src "libresoc.v:22060.3-22061.49" + process $proc$libresoc.v:22060$620 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:21756.3-21757.37" - process $proc$libresoc.v:21756$621 + attribute \src "libresoc.v:22062.3-22063.37" + process $proc$libresoc.v:22062$621 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:21758.3-21759.43" - process $proc$libresoc.v:21758$622 + attribute \src "libresoc.v:22064.3-22065.43" + process $proc$libresoc.v:22064$622 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:21760.3-21761.69" - process $proc$libresoc.v:21760$623 + attribute \src "libresoc.v:22066.3-22067.69" + process $proc$libresoc.v:22066$623 assign { } { } assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:21762.3-21763.65" - process $proc$libresoc.v:21762$624 + attribute \src "libresoc.v:22068.3-22069.65" + process $proc$libresoc.v:22068$624 assign { } { } - assign $0\alu_alu0_alu_op__fn_unit[11:0] \alu_alu0_alu_op__fn_unit$next + assign $0\alu_alu0_alu_op__fn_unit[13:0] \alu_alu0_alu_op__fn_unit$next sync posedge \coresync_clk - update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[11:0] + update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:21764.3-21765.79" - process $proc$libresoc.v:21764$625 + attribute \src "libresoc.v:22070.3-22071.79" + process $proc$libresoc.v:22070$625 assign { } { } assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:21766.3-21767.75" - process $proc$libresoc.v:21766$626 + attribute \src "libresoc.v:22072.3-22073.75" + process $proc$libresoc.v:22072$626 assign { } { } assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:21768.3-21769.63" - process $proc$libresoc.v:21768$627 + attribute \src "libresoc.v:22074.3-22075.63" + process $proc$libresoc.v:22074$627 assign { } { } assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:21770.3-21771.63" - process $proc$libresoc.v:21770$628 + attribute \src "libresoc.v:22076.3-22077.63" + process $proc$libresoc.v:22076$628 assign { } { } assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:21772.3-21773.63" - process $proc$libresoc.v:21772$629 + attribute \src "libresoc.v:22078.3-22079.63" + process $proc$libresoc.v:22078$629 assign { } { } assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:21774.3-21775.63" - process $proc$libresoc.v:21774$630 + attribute \src "libresoc.v:22080.3-22081.63" + process $proc$libresoc.v:22080$630 assign { } { } assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:21776.3-21777.69" - process $proc$libresoc.v:21776$631 + attribute \src "libresoc.v:22082.3-22083.69" + process $proc$libresoc.v:22082$631 assign { } { } assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:21778.3-21779.63" - process $proc$libresoc.v:21778$632 + attribute \src "libresoc.v:22084.3-22085.63" + process $proc$libresoc.v:22084$632 assign { } { } assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next sync posedge \coresync_clk update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:21780.3-21781.71" - process $proc$libresoc.v:21780$633 + attribute \src "libresoc.v:22086.3-22087.71" + process $proc$libresoc.v:22086$633 assign { } { } assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:21782.3-21783.69" - process $proc$libresoc.v:21782$634 + attribute \src "libresoc.v:22088.3-22089.69" + process $proc$libresoc.v:22088$634 assign { } { } assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next sync posedge \coresync_clk update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:21784.3-21785.73" - process $proc$libresoc.v:21784$635 + attribute \src "libresoc.v:22090.3-22091.73" + process $proc$libresoc.v:22090$635 assign { } { } assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:21786.3-21787.75" - process $proc$libresoc.v:21786$636 + attribute \src "libresoc.v:22092.3-22093.75" + process $proc$libresoc.v:22092$636 assign { } { } assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:21788.3-21789.67" - process $proc$libresoc.v:21788$637 + attribute \src "libresoc.v:22094.3-22095.67" + process $proc$libresoc.v:22094$637 assign { } { } assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:21790.3-21791.69" - process $proc$libresoc.v:21790$638 + attribute \src "libresoc.v:22096.3-22097.69" + process $proc$libresoc.v:22096$638 assign { } { } assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:21792.3-21793.67" - process $proc$libresoc.v:21792$639 + attribute \src "libresoc.v:22098.3-22099.67" + process $proc$libresoc.v:22098$639 assign { } { } assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next sync posedge \coresync_clk update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:21794.3-21795.59" - process $proc$libresoc.v:21794$640 + attribute \src "libresoc.v:22100.3-22101.59" + process $proc$libresoc.v:22100$640 assign { } { } assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:21796.3-21797.39" - process $proc$libresoc.v:21796$641 + attribute \src "libresoc.v:22102.3-22103.39" + process $proc$libresoc.v:22102$641 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:21798.3-21799.39" - process $proc$libresoc.v:21798$642 + attribute \src "libresoc.v:22104.3-22105.39" + process $proc$libresoc.v:22104$642 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:21800.3-21801.39" - process $proc$libresoc.v:21800$643 + attribute \src "libresoc.v:22106.3-22107.39" + process $proc$libresoc.v:22106$643 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:21802.3-21803.39" - process $proc$libresoc.v:21802$644 + attribute \src "libresoc.v:22108.3-22109.39" + process $proc$libresoc.v:22108$644 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:21804.3-21805.39" - process $proc$libresoc.v:21804$645 + attribute \src "libresoc.v:22110.3-22111.39" + process $proc$libresoc.v:22110$645 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:21806.3-21807.39" - process $proc$libresoc.v:21806$646 + attribute \src "libresoc.v:22112.3-22113.39" + process $proc$libresoc.v:22112$646 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:21808.3-21809.39" - process $proc$libresoc.v:21808$647 + attribute \src "libresoc.v:22114.3-22115.39" + process $proc$libresoc.v:22114$647 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:21810.3-21811.39" - process $proc$libresoc.v:21810$648 + attribute \src "libresoc.v:22116.3-22117.39" + process $proc$libresoc.v:22116$648 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:21812.3-21813.41" - process $proc$libresoc.v:21812$649 + attribute \src "libresoc.v:22118.3-22119.41" + process $proc$libresoc.v:22118$649 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:21814.3-21815.41" - process $proc$libresoc.v:21814$650 + attribute \src "libresoc.v:22120.3-22121.41" + process $proc$libresoc.v:22120$650 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:21816.3-21817.37" - process $proc$libresoc.v:21816$651 + attribute \src "libresoc.v:22122.3-22123.37" + process $proc$libresoc.v:22122$651 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:21818.3-21819.40" - process $proc$libresoc.v:21818$652 + attribute \src "libresoc.v:22124.3-22125.40" + process $proc$libresoc.v:22124$652 assign { } { } assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:21820.3-21821.25" - process $proc$libresoc.v:21820$653 + attribute \src "libresoc.v:22126.3-22127.25" + process $proc$libresoc.v:22126$653 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:21910.3-21919.6" - process $proc$libresoc.v:21910$654 + attribute \src "libresoc.v:22216.3-22225.6" + process $proc$libresoc.v:22216$654 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:21911.5-21911.29" + attribute \src "libresoc.v:22217.5-22217.29" switch \initial - attribute \src "libresoc.v:21911.9-21911.17" + attribute \src "libresoc.v:22217.9-22217.17" case 1'1 case end @@ -33680,14 +34001,14 @@ module \alu0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:21920.3-21928.6" - process $proc$libresoc.v:21920$655 + attribute \src "libresoc.v:22226.3-22234.6" + process $proc$libresoc.v:22226$655 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:21921.5-21921.29" + attribute \src "libresoc.v:22227.5-22227.29" switch \initial - attribute \src "libresoc.v:21921.9-21921.17" + attribute \src "libresoc.v:22227.9-22227.17" case 1'1 case end @@ -33703,14 +34024,14 @@ module \alu0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 end - attribute \src "libresoc.v:21929.3-21937.6" - process $proc$libresoc.v:21929$658 + attribute \src "libresoc.v:22235.3-22243.6" + process $proc$libresoc.v:22235$658 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:21930.5-21930.29" + attribute \src "libresoc.v:22236.5-22236.29" switch \initial - attribute \src "libresoc.v:21930.9-21930.17" + attribute \src "libresoc.v:22236.9-22236.17" case 1'1 case end @@ -33726,14 +34047,14 @@ module \alu0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 end - attribute \src "libresoc.v:21938.3-21946.6" - process $proc$libresoc.v:21938$661 + attribute \src "libresoc.v:22244.3-22252.6" + process $proc$libresoc.v:22244$661 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:21939.5-21939.29" + attribute \src "libresoc.v:22245.5-22245.29" switch \initial - attribute \src "libresoc.v:21939.9-21939.17" + attribute \src "libresoc.v:22245.9-22245.17" case 1'1 case end @@ -33749,14 +34070,14 @@ module \alu0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 end - attribute \src "libresoc.v:21947.3-21955.6" - process $proc$libresoc.v:21947$664 + attribute \src "libresoc.v:22253.3-22261.6" + process $proc$libresoc.v:22253$664 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:21948.5-21948.29" + attribute \src "libresoc.v:22254.5-22254.29" switch \initial - attribute \src "libresoc.v:21948.9-21948.17" + attribute \src "libresoc.v:22254.9-22254.17" case 1'1 case end @@ -33772,14 +34093,14 @@ module \alu0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 end - attribute \src "libresoc.v:21956.3-21964.6" - process $proc$libresoc.v:21956$667 + attribute \src "libresoc.v:22262.3-22270.6" + process $proc$libresoc.v:22262$667 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:21957.5-21957.29" + attribute \src "libresoc.v:22263.5-22263.29" switch \initial - attribute \src "libresoc.v:21957.9-21957.17" + attribute \src "libresoc.v:22263.9-22263.17" case 1'1 case end @@ -33795,14 +34116,14 @@ module \alu0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 end - attribute \src "libresoc.v:21965.3-21973.6" - process $proc$libresoc.v:21965$670 + attribute \src "libresoc.v:22271.3-22279.6" + process $proc$libresoc.v:22271$670 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:21966.5-21966.29" + attribute \src "libresoc.v:22272.5-22272.29" switch \initial - attribute \src "libresoc.v:21966.9-21966.17" + attribute \src "libresoc.v:22272.9-22272.17" case 1'1 case end @@ -33818,14 +34139,14 @@ module \alu0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 end - attribute \src "libresoc.v:21974.3-21982.6" - process $proc$libresoc.v:21974$673 + attribute \src "libresoc.v:22280.3-22288.6" + process $proc$libresoc.v:22280$673 assign { } { } assign { } { } assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:21975.5-21975.29" + attribute \src "libresoc.v:22281.5-22281.29" switch \initial - attribute \src "libresoc.v:21975.9-21975.17" + attribute \src "libresoc.v:22281.9-22281.17" case 1'1 case end @@ -33841,14 +34162,14 @@ module \alu0 sync always update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 end - attribute \src "libresoc.v:21983.3-21991.6" - process $proc$libresoc.v:21983$676 + attribute \src "libresoc.v:22289.3-22297.6" + process $proc$libresoc.v:22289$676 assign { } { } assign { } { } assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:21984.5-21984.29" + attribute \src "libresoc.v:22290.5-22290.29" switch \initial - attribute \src "libresoc.v:21984.9-21984.17" + attribute \src "libresoc.v:22290.9-22290.17" case 1'1 case end @@ -33864,14 +34185,14 @@ module \alu0 sync always update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 end - attribute \src "libresoc.v:21992.3-22000.6" - process $proc$libresoc.v:21992$679 + attribute \src "libresoc.v:22298.3-22306.6" + process $proc$libresoc.v:22298$679 assign { } { } assign { } { } assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:21993.5-21993.29" + attribute \src "libresoc.v:22299.5-22299.29" switch \initial - attribute \src "libresoc.v:21993.9-21993.17" + attribute \src "libresoc.v:22299.9-22299.17" case 1'1 case end @@ -33887,14 +34208,14 @@ module \alu0 sync always update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 end - attribute \src "libresoc.v:22001.3-22009.6" - process $proc$libresoc.v:22001$682 + attribute \src "libresoc.v:22307.3-22315.6" + process $proc$libresoc.v:22307$682 assign { } { } assign { } { } assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:22002.5-22002.29" + attribute \src "libresoc.v:22308.5-22308.29" switch \initial - attribute \src "libresoc.v:22002.9-22002.17" + attribute \src "libresoc.v:22308.9-22308.17" case 1'1 case end @@ -33910,8 +34231,8 @@ module \alu0 sync always update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 end - attribute \src "libresoc.v:22010.3-22048.6" - process $proc$libresoc.v:22010$685 + attribute \src "libresoc.v:22316.3-22354.6" + process $proc$libresoc.v:22316$685 assign { } { } assign { } { } assign { } { } @@ -33949,7 +34270,7 @@ module \alu0 assign { } { } assign { } { } assign $0\alu_alu0_alu_op__data_len$next[3:0]$686 $1\alu_alu0_alu_op__data_len$next[3:0]$704 - assign $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 + assign $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 assign { } { } assign { } { } assign $0\alu_alu0_alu_op__input_carry$next[1:0]$690 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 @@ -33972,9 +34293,9 @@ module \alu0 assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22011.5-22011.29" + attribute \src "libresoc.v:22317.5-22317.29" switch \initial - attribute \src "libresoc.v:22011.9-22011.17" + attribute \src "libresoc.v:22317.9-22317.17" case 1'1 case end @@ -34000,10 +34321,10 @@ module \alu0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } case assign $1\alu_alu0_alu_op__data_len$next[3:0]$704 \alu_alu0_alu_op__data_len - assign $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 \alu_alu0_alu_op__fn_unit + assign $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 \alu_alu0_alu_op__fn_unit assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 \alu_alu0_alu_op__imm_data__data assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 \alu_alu0_alu_op__imm_data__ok assign $1\alu_alu0_alu_op__input_carry$next[1:0]$708 \alu_alu0_alu_op__input_carry @@ -34047,7 +34368,7 @@ module \alu0 end sync always update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$686 - update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 + update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$690 @@ -34065,8 +34386,8 @@ module \alu0 update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 end - attribute \src "libresoc.v:22049.3-22070.6" - process $proc$libresoc.v:22049$728 + attribute \src "libresoc.v:22355.3-22376.6" + process $proc$libresoc.v:22355$728 assign { } { } assign { } { } assign { } { } @@ -34076,9 +34397,9 @@ module \alu0 assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 assign { } { } assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22050.5-22050.29" + attribute \src "libresoc.v:22356.5-22356.29" switch \initial - attribute \src "libresoc.v:22050.9-22050.17" + attribute \src "libresoc.v:22356.9-22356.17" case 1'1 case end @@ -34117,8 +34438,8 @@ module \alu0 update \data_r0__o$next $0\data_r0__o$next[63:0]$729 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 end - attribute \src "libresoc.v:22071.3-22092.6" - process $proc$libresoc.v:22071$736 + attribute \src "libresoc.v:22377.3-22398.6" + process $proc$libresoc.v:22377$736 assign { } { } assign { } { } assign { } { } @@ -34128,9 +34449,9 @@ module \alu0 assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22072.5-22072.29" + attribute \src "libresoc.v:22378.5-22378.29" switch \initial - attribute \src "libresoc.v:22072.9-22072.17" + attribute \src "libresoc.v:22378.9-22378.17" case 1'1 case end @@ -34169,8 +34490,8 @@ module \alu0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 end - attribute \src "libresoc.v:22093.3-22114.6" - process $proc$libresoc.v:22093$744 + attribute \src "libresoc.v:22399.3-22420.6" + process $proc$libresoc.v:22399$744 assign { } { } assign { } { } assign { } { } @@ -34180,9 +34501,9 @@ module \alu0 assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 assign { } { } assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22094.5-22094.29" + attribute \src "libresoc.v:22400.5-22400.29" switch \initial - attribute \src "libresoc.v:22094.9-22094.17" + attribute \src "libresoc.v:22400.9-22400.17" case 1'1 case end @@ -34221,8 +34542,8 @@ module \alu0 update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 end - attribute \src "libresoc.v:22115.3-22136.6" - process $proc$libresoc.v:22115$752 + attribute \src "libresoc.v:22421.3-22442.6" + process $proc$libresoc.v:22421$752 assign { } { } assign { } { } assign { } { } @@ -34232,9 +34553,9 @@ module \alu0 assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 assign { } { } assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22116.5-22116.29" + attribute \src "libresoc.v:22422.5-22422.29" switch \initial - attribute \src "libresoc.v:22116.9-22116.17" + attribute \src "libresoc.v:22422.9-22422.17" case 1'1 case end @@ -34273,8 +34594,8 @@ module \alu0 update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 end - attribute \src "libresoc.v:22137.3-22158.6" - process $proc$libresoc.v:22137$760 + attribute \src "libresoc.v:22443.3-22464.6" + process $proc$libresoc.v:22443$760 assign { } { } assign { } { } assign { } { } @@ -34284,9 +34605,9 @@ module \alu0 assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 assign { } { } assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:22138.5-22138.29" + attribute \src "libresoc.v:22444.5-22444.29" switch \initial - attribute \src "libresoc.v:22138.9-22138.17" + attribute \src "libresoc.v:22444.9-22444.17" case 1'1 case end @@ -34325,18 +34646,18 @@ module \alu0 update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 end - attribute \src "libresoc.v:22159.3-22168.6" - process $proc$libresoc.v:22159$768 + attribute \src "libresoc.v:22465.3-22474.6" + process $proc$libresoc.v:22465$768 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:22160.5-22160.29" + attribute \src "libresoc.v:22466.5-22466.29" switch \initial - attribute \src "libresoc.v:22160.9-22160.17" + attribute \src "libresoc.v:22466.9-22466.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -34348,18 +34669,18 @@ module \alu0 sync always update \src_r0$next $0\src_r0$next[63:0]$769 end - attribute \src "libresoc.v:22169.3-22178.6" - process $proc$libresoc.v:22169$771 + attribute \src "libresoc.v:22475.3-22484.6" + process $proc$libresoc.v:22475$771 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:22170.5-22170.29" + attribute \src "libresoc.v:22476.5-22476.29" switch \initial - attribute \src "libresoc.v:22170.9-22170.17" + attribute \src "libresoc.v:22476.9-22476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -34371,18 +34692,18 @@ module \alu0 sync always update \src_r1$next $0\src_r1$next[63:0]$772 end - attribute \src "libresoc.v:22179.3-22188.6" - process $proc$libresoc.v:22179$774 + attribute \src "libresoc.v:22485.3-22494.6" + process $proc$libresoc.v:22485$774 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:22180.5-22180.29" + attribute \src "libresoc.v:22486.5-22486.29" switch \initial - attribute \src "libresoc.v:22180.9-22180.17" + attribute \src "libresoc.v:22486.9-22486.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -34394,18 +34715,18 @@ module \alu0 sync always update \src_r2$next $0\src_r2$next[0:0]$775 end - attribute \src "libresoc.v:22189.3-22198.6" - process $proc$libresoc.v:22189$777 + attribute \src "libresoc.v:22495.3-22504.6" + process $proc$libresoc.v:22495$777 assign { } { } assign { } { } assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:22190.5-22190.29" + attribute \src "libresoc.v:22496.5-22496.29" switch \initial - attribute \src "libresoc.v:22190.9-22190.17" + attribute \src "libresoc.v:22496.9-22496.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -34417,14 +34738,14 @@ module \alu0 sync always update \src_r3$next $0\src_r3$next[1:0]$778 end - attribute \src "libresoc.v:22199.3-22207.6" - process $proc$libresoc.v:22199$780 + attribute \src "libresoc.v:22505.3-22513.6" + process $proc$libresoc.v:22505$780 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:22200.5-22200.29" + attribute \src "libresoc.v:22506.5-22506.29" switch \initial - attribute \src "libresoc.v:22200.9-22200.17" + attribute \src "libresoc.v:22506.9-22506.17" case 1'1 case end @@ -34440,14 +34761,14 @@ module \alu0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$781 end - attribute \src "libresoc.v:22208.3-22216.6" - process $proc$libresoc.v:22208$783 + attribute \src "libresoc.v:22514.3-22522.6" + process $proc$libresoc.v:22514$783 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$784 $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:22209.5-22209.29" + attribute \src "libresoc.v:22515.5-22515.29" switch \initial - attribute \src "libresoc.v:22209.9-22209.17" + attribute \src "libresoc.v:22515.9-22515.17" case 1'1 case end @@ -34463,14 +34784,14 @@ module \alu0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$784 end - attribute \src "libresoc.v:22217.3-22226.6" - process $proc$libresoc.v:22217$786 + attribute \src "libresoc.v:22523.3-22532.6" + process $proc$libresoc.v:22523$786 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:22218.5-22218.29" + attribute \src "libresoc.v:22524.5-22524.29" switch \initial - attribute \src "libresoc.v:22218.9-22218.17" + attribute \src "libresoc.v:22524.9-22524.17" case 1'1 case end @@ -34486,14 +34807,14 @@ module \alu0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:22227.3-22236.6" - process $proc$libresoc.v:22227$787 + attribute \src "libresoc.v:22533.3-22542.6" + process $proc$libresoc.v:22533$787 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:22228.5-22228.29" + attribute \src "libresoc.v:22534.5-22534.29" switch \initial - attribute \src "libresoc.v:22228.9-22228.17" + attribute \src "libresoc.v:22534.9-22534.17" case 1'1 case end @@ -34509,14 +34830,14 @@ module \alu0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:22237.3-22246.6" - process $proc$libresoc.v:22237$788 + attribute \src "libresoc.v:22543.3-22552.6" + process $proc$libresoc.v:22543$788 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:22238.5-22238.29" + attribute \src "libresoc.v:22544.5-22544.29" switch \initial - attribute \src "libresoc.v:22238.9-22238.17" + attribute \src "libresoc.v:22544.9-22544.17" case 1'1 case end @@ -34532,14 +34853,14 @@ module \alu0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:22247.3-22256.6" - process $proc$libresoc.v:22247$789 + attribute \src "libresoc.v:22553.3-22562.6" + process $proc$libresoc.v:22553$789 assign { } { } assign { } { } assign $0\dest4_o[1:0] $1\dest4_o[1:0] - attribute \src "libresoc.v:22248.5-22248.29" + attribute \src "libresoc.v:22554.5-22554.29" switch \initial - attribute \src "libresoc.v:22248.9-22248.17" + attribute \src "libresoc.v:22554.9-22554.17" case 1'1 case end @@ -34555,14 +34876,14 @@ module \alu0 sync always update \dest4_o $0\dest4_o[1:0] end - attribute \src "libresoc.v:22257.3-22266.6" - process $proc$libresoc.v:22257$790 + attribute \src "libresoc.v:22563.3-22572.6" + process $proc$libresoc.v:22563$790 assign { } { } assign { } { } assign $0\dest5_o[0:0] $1\dest5_o[0:0] - attribute \src "libresoc.v:22258.5-22258.29" + attribute \src "libresoc.v:22564.5-22564.29" switch \initial - attribute \src "libresoc.v:22258.9-22258.17" + attribute \src "libresoc.v:22564.9-22564.17" case 1'1 case end @@ -34578,14 +34899,14 @@ module \alu0 sync always update \dest5_o $0\dest5_o[0:0] end - attribute \src "libresoc.v:22267.3-22275.6" - process $proc$libresoc.v:22267$791 + attribute \src "libresoc.v:22573.3-22581.6" + process $proc$libresoc.v:22573$791 assign { } { } assign { } { } assign $0\prev_wr_go$next[4:0]$792 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:22268.5-22268.29" + attribute \src "libresoc.v:22574.5-22574.29" switch \initial - attribute \src "libresoc.v:22268.9-22268.17" + attribute \src "libresoc.v:22574.9-22574.17" case 1'1 case end @@ -34601,73 +34922,73 @@ module \alu0 sync always update \prev_wr_go$next $0\prev_wr_go$next[4:0]$792 end - connect \$5 $reduce_and$libresoc.v:21661$540_Y - connect \$99 $and$libresoc.v:21662$541_Y - connect \$101 $and$libresoc.v:21663$542_Y - connect \$103 $and$libresoc.v:21664$543_Y - connect \$105 $not$libresoc.v:21665$544_Y - connect \$107 $not$libresoc.v:21666$545_Y - connect \$109 $and$libresoc.v:21667$546_Y - connect \$111 $not$libresoc.v:21668$547_Y - connect \$113 $and$libresoc.v:21669$548_Y - connect \$115 $and$libresoc.v:21670$549_Y - connect \$117 $and$libresoc.v:21671$550_Y - connect \$11 $and$libresoc.v:21672$551_Y - connect \$119 $and$libresoc.v:21673$552_Y - connect \$121 $and$libresoc.v:21674$553_Y - connect \$123 $and$libresoc.v:21675$554_Y - connect \$125 $and$libresoc.v:21676$555_Y - connect \$127 $and$libresoc.v:21677$556_Y - connect \$129 $and$libresoc.v:21678$557_Y - connect \$131 $and$libresoc.v:21679$558_Y - connect \$133 $and$libresoc.v:21680$559_Y - connect \$135 $and$libresoc.v:21681$560_Y - connect \$137 $and$libresoc.v:21682$561_Y - connect \$13 $not$libresoc.v:21683$562_Y - connect \$15 $and$libresoc.v:21684$563_Y - connect \$17 $not$libresoc.v:21685$564_Y - connect \$19 $and$libresoc.v:21686$565_Y - connect \$21 $and$libresoc.v:21687$566_Y - connect \$25 $not$libresoc.v:21688$567_Y - connect \$27 $and$libresoc.v:21689$568_Y - connect \$24 $reduce_or$libresoc.v:21690$569_Y - connect \$23 $not$libresoc.v:21691$570_Y - connect \$31 $and$libresoc.v:21692$571_Y - connect \$33 $reduce_or$libresoc.v:21693$572_Y - connect \$35 $reduce_or$libresoc.v:21694$573_Y - connect \$37 $or$libresoc.v:21695$574_Y - connect \$3 $and$libresoc.v:21696$575_Y - connect \$39 $not$libresoc.v:21697$576_Y - connect \$41 $and$libresoc.v:21698$577_Y - connect \$43 $and$libresoc.v:21699$578_Y - connect \$45 $eq$libresoc.v:21700$579_Y - connect \$47 $and$libresoc.v:21701$580_Y - connect \$49 $eq$libresoc.v:21702$581_Y - connect \$51 $and$libresoc.v:21703$582_Y - connect \$53 $and$libresoc.v:21704$583_Y - connect \$55 $and$libresoc.v:21705$584_Y - connect \$57 $or$libresoc.v:21706$585_Y - connect \$59 $or$libresoc.v:21707$586_Y - connect \$61 $or$libresoc.v:21708$587_Y - connect \$63 $or$libresoc.v:21709$588_Y - connect \$65 $and$libresoc.v:21710$589_Y - connect \$67 $and$libresoc.v:21711$590_Y - connect \$6 $not$libresoc.v:21712$591_Y - connect \$69 $or$libresoc.v:21713$592_Y - connect \$71 $and$libresoc.v:21714$593_Y - connect \$73 $and$libresoc.v:21715$594_Y - connect \$75 $and$libresoc.v:21716$595_Y - connect \$77 $and$libresoc.v:21717$596_Y - connect \$79 $and$libresoc.v:21718$597_Y - connect \$81 $ternary$libresoc.v:21719$598_Y - connect \$83 $ternary$libresoc.v:21720$599_Y - connect \$86 $ternary$libresoc.v:21721$600_Y - connect \$8 $or$libresoc.v:21722$601_Y - connect \$89 $ternary$libresoc.v:21723$602_Y - connect \$91 $ternary$libresoc.v:21724$603_Y - connect \$93 $ternary$libresoc.v:21725$604_Y - connect \$95 $ternary$libresoc.v:21726$605_Y - connect \$97 $ternary$libresoc.v:21727$606_Y + connect \$5 $reduce_and$libresoc.v:21967$540_Y + connect \$99 $and$libresoc.v:21968$541_Y + connect \$101 $and$libresoc.v:21969$542_Y + connect \$103 $and$libresoc.v:21970$543_Y + connect \$105 $not$libresoc.v:21971$544_Y + connect \$107 $not$libresoc.v:21972$545_Y + connect \$109 $and$libresoc.v:21973$546_Y + connect \$111 $not$libresoc.v:21974$547_Y + connect \$113 $and$libresoc.v:21975$548_Y + connect \$115 $and$libresoc.v:21976$549_Y + connect \$117 $and$libresoc.v:21977$550_Y + connect \$11 $and$libresoc.v:21978$551_Y + connect \$119 $and$libresoc.v:21979$552_Y + connect \$121 $and$libresoc.v:21980$553_Y + connect \$123 $and$libresoc.v:21981$554_Y + connect \$125 $and$libresoc.v:21982$555_Y + connect \$127 $and$libresoc.v:21983$556_Y + connect \$129 $and$libresoc.v:21984$557_Y + connect \$131 $and$libresoc.v:21985$558_Y + connect \$133 $and$libresoc.v:21986$559_Y + connect \$135 $and$libresoc.v:21987$560_Y + connect \$137 $and$libresoc.v:21988$561_Y + connect \$13 $not$libresoc.v:21989$562_Y + connect \$15 $and$libresoc.v:21990$563_Y + connect \$17 $not$libresoc.v:21991$564_Y + connect \$19 $and$libresoc.v:21992$565_Y + connect \$21 $and$libresoc.v:21993$566_Y + connect \$25 $not$libresoc.v:21994$567_Y + connect \$27 $and$libresoc.v:21995$568_Y + connect \$24 $reduce_or$libresoc.v:21996$569_Y + connect \$23 $not$libresoc.v:21997$570_Y + connect \$31 $and$libresoc.v:21998$571_Y + connect \$33 $reduce_or$libresoc.v:21999$572_Y + connect \$35 $reduce_or$libresoc.v:22000$573_Y + connect \$37 $or$libresoc.v:22001$574_Y + connect \$3 $and$libresoc.v:22002$575_Y + connect \$39 $not$libresoc.v:22003$576_Y + connect \$41 $and$libresoc.v:22004$577_Y + connect \$43 $and$libresoc.v:22005$578_Y + connect \$45 $eq$libresoc.v:22006$579_Y + connect \$47 $and$libresoc.v:22007$580_Y + connect \$49 $eq$libresoc.v:22008$581_Y + connect \$51 $and$libresoc.v:22009$582_Y + connect \$53 $and$libresoc.v:22010$583_Y + connect \$55 $and$libresoc.v:22011$584_Y + connect \$57 $or$libresoc.v:22012$585_Y + connect \$59 $or$libresoc.v:22013$586_Y + connect \$61 $or$libresoc.v:22014$587_Y + connect \$63 $or$libresoc.v:22015$588_Y + connect \$65 $and$libresoc.v:22016$589_Y + connect \$67 $and$libresoc.v:22017$590_Y + connect \$6 $not$libresoc.v:22018$591_Y + connect \$69 $or$libresoc.v:22019$592_Y + connect \$71 $and$libresoc.v:22020$593_Y + connect \$73 $and$libresoc.v:22021$594_Y + connect \$75 $and$libresoc.v:22022$595_Y + connect \$77 $and$libresoc.v:22023$596_Y + connect \$79 $and$libresoc.v:22024$597_Y + connect \$81 $ternary$libresoc.v:22025$598_Y + connect \$83 $ternary$libresoc.v:22026$599_Y + connect \$86 $ternary$libresoc.v:22027$600_Y + connect \$8 $or$libresoc.v:22028$601_Y + connect \$89 $ternary$libresoc.v:22029$602_Y + connect \$91 $ternary$libresoc.v:22030$603_Y + connect \$93 $ternary$libresoc.v:22031$604_Y + connect \$95 $ternary$libresoc.v:22032$605_Y + connect \$97 $ternary$libresoc.v:22033$606_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$127 @@ -34702,7 +35023,7 @@ module \alu0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:22313.1-23373.10" +attribute \src "libresoc.v:22619.1-23697.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0" attribute \generator "nMigen" @@ -34712,35 +35033,39 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$70 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 10 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 10 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$55 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 11 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -34839,6 +35164,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 9 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -34915,6 +35241,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -34961,64 +35288,68 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 28 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 8 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 7 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 27 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 37 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 36 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe1_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe1_alu_op__data_len$20 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_alu_op__fn_unit$5 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_alu_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35117,6 +35448,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -35193,6 +35525,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_alu_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35243,21 +35576,21 @@ module \alu_alu0 wire width 4 \pipe1_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_ra @@ -35284,35 +35617,39 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe2_alu_op__data_len$41 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_alu_op__fn_unit$26 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_alu_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35411,6 +35748,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -35487,6 +35825,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_alu_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35541,13 +35880,13 @@ module \alu_alu0 wire \pipe2_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe2_o @@ -35557,9 +35896,9 @@ module \alu_alu0 wire \pipe2_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe2_xer_ca @@ -35606,19 +35945,19 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 6 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:23212.5-23215.4" + attribute \src "libresoc.v:23536.5-23539.4" cell \n \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:23216.5-23219.4" + attribute \src "libresoc.v:23540.5-23543.4" cell \p \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:23220.9-23279.4" + attribute \src "libresoc.v:23544.9-23603.4" cell \pipe1 \pipe1 connect \alu_op__data_len \pipe1_alu_op__data_len connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 @@ -35680,7 +36019,7 @@ module \alu_alu0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:23280.9-23345.4" + attribute \src "libresoc.v:23604.9-23669.4" cell \pipe2 \pipe2 connect \alu_op__data_len \pipe2_alu_op__data_len connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 @@ -35775,7 +36114,7 @@ module \alu_alu0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:23377.1-23912.10" +attribute \src "libresoc.v:23701.1-24248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" attribute \generator "nMigen" @@ -35785,35 +36124,39 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__cia$15 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \br_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \br_op__fn_unit$17 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 11 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35900,6 +36243,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \br_op__insn_type attribute \enum_base_type "MicrOp" @@ -35976,6 +36320,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \br_op__insn_type$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35986,9 +36331,9 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a @@ -36004,56 +36349,60 @@ module \alu_branch0 wire width 64 input 19 \fast2$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 17 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 22 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 21 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__cia$4 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_br_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_br_op__fn_unit$6 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_br_op__fn_unit$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36140,6 +36489,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_br_op__insn_type attribute \enum_base_type "MicrOp" @@ -36216,6 +36566,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_br_op__insn_type$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36240,36 +36591,36 @@ module \alu_branch0 wire width 64 \pipe_fast2$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \module_not_derived 1 - attribute \src "libresoc.v:23854.10-23857.4" + attribute \src "libresoc.v:24190.10-24193.4" cell \n$18 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:23858.10-23861.4" + attribute \src "libresoc.v:24194.10-24197.4" cell \p$17 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:23862.13-23896.4" + attribute \src "libresoc.v:24198.13-24232.4" cell \pipe$19 \pipe connect \br_op__cia \pipe_br_op__cia connect \br_op__cia$2 \pipe_br_op__cia$4 @@ -36321,14 +36672,14 @@ module \alu_branch0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:23916.1-24419.10" +attribute \src "libresoc.v:24252.1-24767.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 12 \cr_a @@ -36341,35 +36692,39 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 18 \cr_c attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 8 \cr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 8 \cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \cr_op__fn_unit$11 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \cr_op__fn_unit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 9 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36448,6 +36803,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 7 \cr_op__insn_type attribute \enum_base_type "MicrOp" @@ -36524,6 +36880,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -36532,21 +36889,21 @@ module \alu_cr0 wire width 32 input 15 \full_cr$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 10 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 20 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 19 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_a @@ -36559,35 +36916,39 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_c attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_cr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_cr_op__fn_unit$5 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_cr_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36666,6 +37027,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_cr_op__insn_type attribute \enum_base_type "MicrOp" @@ -36742,6 +37104,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_cr_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -36750,21 +37113,21 @@ module \alu_cr0 wire width 32 \pipe_full_cr$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_ra @@ -36775,19 +37138,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \module_not_derived 1 - attribute \src "libresoc.v:24365.9-24368.4" + attribute \src "libresoc.v:24713.9-24716.4" cell \n$6 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:24369.9-24372.4" + attribute \src "libresoc.v:24717.9-24720.4" cell \p$5 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:24373.8-24400.4" + attribute \src "libresoc.v:24721.8-24748.4" cell \pipe \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -36835,14 +37198,14 @@ module \alu_cr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:24423.1-25864.10" +attribute \src "libresoc.v:24771.1-26236.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 27 \cr_a @@ -36853,35 +37216,39 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$88 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$73 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 10 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36980,6 +37347,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -37056,6 +37424,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37102,21 +37471,21 @@ module \alu_div0 wire input 17 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 7 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 6 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 26 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 34 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 33 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe_end_cr_a @@ -37137,35 +37506,39 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_end_logical_op__data_len$68 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_end_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_end_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_end_logical_op__fn_unit$53 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_end_logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_end_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37264,6 +37637,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_end_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -37340,6 +37714,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_end_logical_op__insn_type$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37386,21 +37761,21 @@ module \alu_div0 wire \pipe_end_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__zero_a$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_end_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_end_muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_end_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_end_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_end_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_end_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_end_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_end_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 \pipe_end_quotient_root @@ -37449,35 +37824,39 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_middle_0_logical_op__data_len$41 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_middle_0_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_middle_0_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_middle_0_logical_op__fn_unit$26 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_middle_0_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_middle_0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37576,6 +37955,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_middle_0_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -37652,6 +38032,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_middle_0_logical_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37698,19 +38079,19 @@ module \alu_div0 wire \pipe_middle_0_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_middle_0_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_middle_0_muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_middle_0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_middle_0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \pipe_middle_0_operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_middle_0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_middle_0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 \pipe_middle_0_quotient_root @@ -37747,35 +38128,39 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_start_logical_op__data_len$19 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_start_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_start_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_start_logical_op__fn_unit$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_start_logical_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_start_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37874,6 +38259,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_start_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -37950,6 +38336,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_start_logical_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37996,19 +38383,19 @@ module \alu_div0 wire \pipe_start_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__zero_a$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_start_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_start_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_start_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_start_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \pipe_start_operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_start_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_start_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_start_ra @@ -38037,19 +38424,19 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:25620.10-25623.4" + attribute \src "libresoc.v:25992.10-25995.4" cell \n$75 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:25624.10-25627.4" + attribute \src "libresoc.v:25996.10-25999.4" cell \p$74 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:25628.12-25691.4" + attribute \src "libresoc.v:26000.12-26063.4" cell \pipe_end \pipe_end connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38115,7 +38502,7 @@ module \alu_div0 connect \xer_so_ok \pipe_end_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:25692.17-25758.4" + attribute \src "libresoc.v:26064.17-26130.4" cell \pipe_middle_0 \pipe_middle_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38184,7 +38571,7 @@ module \alu_div0 connect \xer_so$22 \pipe_middle_0_xer_so$45 end attribute \module_not_derived 1 - attribute \src "libresoc.v:25759.14-25818.4" + attribute \src "libresoc.v:26131.14-26190.4" cell \pipe_start \pipe_start connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38291,75 +38678,75 @@ module \alu_div0 connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o end -attribute \src "libresoc.v:25868.1-25926.10" +attribute \src "libresoc.v:26240.1-26298.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" attribute \generator "nMigen" module \alu_l - attribute \src "libresoc.v:25869.7-25869.20" + attribute \src "libresoc.v:26241.7-26241.20" wire $0\initial[0:0] - attribute \src "libresoc.v:25914.3-25922.6" + attribute \src "libresoc.v:26286.3-26294.6" wire $0\q_int$next[0:0]$852 - attribute \src "libresoc.v:25912.3-25913.27" + attribute \src "libresoc.v:26284.3-26285.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:25914.3-25922.6" + attribute \src "libresoc.v:26286.3-26294.6" wire $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:25893.7-25893.19" + attribute \src "libresoc.v:26265.7-26265.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:25904.17-25904.96" - wire $and$libresoc.v:25904$842_Y - attribute \src "libresoc.v:25909.17-25909.96" - wire $and$libresoc.v:25909$847_Y - attribute \src "libresoc.v:25906.18-25906.93" - wire $not$libresoc.v:25906$844_Y - attribute \src "libresoc.v:25908.17-25908.92" - wire $not$libresoc.v:25908$846_Y - attribute \src "libresoc.v:25911.17-25911.92" - wire $not$libresoc.v:25911$849_Y - attribute \src "libresoc.v:25905.18-25905.98" - wire $or$libresoc.v:25905$843_Y - attribute \src "libresoc.v:25907.18-25907.99" - wire $or$libresoc.v:25907$845_Y - attribute \src "libresoc.v:25910.17-25910.97" - wire $or$libresoc.v:25910$848_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26276.17-26276.96" + wire $and$libresoc.v:26276$842_Y + attribute \src "libresoc.v:26281.17-26281.96" + wire $and$libresoc.v:26281$847_Y + attribute \src "libresoc.v:26278.18-26278.93" + wire $not$libresoc.v:26278$844_Y + attribute \src "libresoc.v:26280.17-26280.92" + wire $not$libresoc.v:26280$846_Y + attribute \src "libresoc.v:26283.17-26283.92" + wire $not$libresoc.v:26283$849_Y + attribute \src "libresoc.v:26277.18-26277.98" + wire $or$libresoc.v:26277$843_Y + attribute \src "libresoc.v:26279.18-26279.99" + wire $or$libresoc.v:26279$845_Y + attribute \src "libresoc.v:26282.17-26282.97" + wire $or$libresoc.v:26282$848_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:25869.7-25869.15" + attribute \src "libresoc.v:26241.7-26241.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:25904$842 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26276$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38367,10 +38754,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:25904$842_Y + connect \Y $and$libresoc.v:26276$842_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:25909$847 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26281$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38378,34 +38765,34 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:25909$847_Y + connect \Y $and$libresoc.v:26281$847_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:25906$844 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26278$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:25906$844_Y + connect \Y $not$libresoc.v:26278$844_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:25908$846 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26280$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25908$846_Y + connect \Y $not$libresoc.v:26280$846_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:25911$849 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26283$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25911$849_Y + connect \Y $not$libresoc.v:26283$849_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:25905$843 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26277$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38413,10 +38800,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:25905$843_Y + connect \Y $or$libresoc.v:26277$843_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:25907$845 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26279$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38424,10 +38811,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:25907$845_Y + connect \Y $or$libresoc.v:26279$845_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:25910$848 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26282$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38435,39 +38822,39 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:25910$848_Y + connect \Y $or$libresoc.v:26282$848_Y end - attribute \src "libresoc.v:25869.7-25869.20" - process $proc$libresoc.v:25869$854 + attribute \src "libresoc.v:26241.7-26241.20" + process $proc$libresoc.v:26241$854 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:25893.7-25893.19" - process $proc$libresoc.v:25893$855 + attribute \src "libresoc.v:26265.7-26265.19" + process $proc$libresoc.v:26265$855 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:25912.3-25913.27" - process $proc$libresoc.v:25912$850 + attribute \src "libresoc.v:26284.3-26285.27" + process $proc$libresoc.v:26284$850 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:25914.3-25922.6" - process $proc$libresoc.v:25914$851 + attribute \src "libresoc.v:26286.3-26294.6" + process $proc$libresoc.v:26286$851 assign { } { } assign { } { } assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:25915.5-25915.29" + attribute \src "libresoc.v:26287.5-26287.29" switch \initial - attribute \src "libresoc.v:25915.9-25915.17" + attribute \src "libresoc.v:26287.9-26287.17" case 1'1 case end @@ -38483,87 +38870,87 @@ module \alu_l sync always update \q_int$next $0\q_int$next[0:0]$852 end - connect \$9 $and$libresoc.v:25904$842_Y - connect \$11 $or$libresoc.v:25905$843_Y - connect \$13 $not$libresoc.v:25906$844_Y - connect \$15 $or$libresoc.v:25907$845_Y - connect \$1 $not$libresoc.v:25908$846_Y - connect \$3 $and$libresoc.v:25909$847_Y - connect \$5 $or$libresoc.v:25910$848_Y - connect \$7 $not$libresoc.v:25911$849_Y + connect \$9 $and$libresoc.v:26276$842_Y + connect \$11 $or$libresoc.v:26277$843_Y + connect \$13 $not$libresoc.v:26278$844_Y + connect \$15 $or$libresoc.v:26279$845_Y + connect \$1 $not$libresoc.v:26280$846_Y + connect \$3 $and$libresoc.v:26281$847_Y + connect \$5 $or$libresoc.v:26282$848_Y + connect \$7 $not$libresoc.v:26283$849_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:25930.1-25988.10" +attribute \src "libresoc.v:26302.1-26360.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" attribute \generator "nMigen" module \alu_l$107 - attribute \src "libresoc.v:25931.7-25931.20" + attribute \src "libresoc.v:26303.7-26303.20" wire $0\initial[0:0] - attribute \src "libresoc.v:25976.3-25984.6" + attribute \src "libresoc.v:26348.3-26356.6" wire $0\q_int$next[0:0]$866 - attribute \src "libresoc.v:25974.3-25975.27" + attribute \src "libresoc.v:26346.3-26347.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:25976.3-25984.6" + attribute \src "libresoc.v:26348.3-26356.6" wire $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:25955.7-25955.19" + attribute \src "libresoc.v:26327.7-26327.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:25966.17-25966.96" - wire $and$libresoc.v:25966$856_Y - attribute \src "libresoc.v:25971.17-25971.96" - wire $and$libresoc.v:25971$861_Y - attribute \src "libresoc.v:25968.18-25968.93" - wire $not$libresoc.v:25968$858_Y - attribute \src "libresoc.v:25970.17-25970.92" - wire $not$libresoc.v:25970$860_Y - attribute \src "libresoc.v:25973.17-25973.92" - wire $not$libresoc.v:25973$863_Y - attribute \src "libresoc.v:25967.18-25967.98" - wire $or$libresoc.v:25967$857_Y - attribute \src "libresoc.v:25969.18-25969.99" - wire $or$libresoc.v:25969$859_Y - attribute \src "libresoc.v:25972.17-25972.97" - wire $or$libresoc.v:25972$862_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26338.17-26338.96" + wire $and$libresoc.v:26338$856_Y + attribute \src "libresoc.v:26343.17-26343.96" + wire $and$libresoc.v:26343$861_Y + attribute \src "libresoc.v:26340.18-26340.93" + wire $not$libresoc.v:26340$858_Y + attribute \src "libresoc.v:26342.17-26342.92" + wire $not$libresoc.v:26342$860_Y + attribute \src "libresoc.v:26345.17-26345.92" + wire $not$libresoc.v:26345$863_Y + attribute \src "libresoc.v:26339.18-26339.98" + wire $or$libresoc.v:26339$857_Y + attribute \src "libresoc.v:26341.18-26341.99" + wire $or$libresoc.v:26341$859_Y + attribute \src "libresoc.v:26344.17-26344.97" + wire $or$libresoc.v:26344$862_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:25931.7-25931.15" + attribute \src "libresoc.v:26303.7-26303.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:25966$856 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26338$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38571,10 +38958,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:25966$856_Y + connect \Y $and$libresoc.v:26338$856_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:25971$861 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26343$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38582,34 +38969,34 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:25971$861_Y + connect \Y $and$libresoc.v:26343$861_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:25968$858 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26340$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:25968$858_Y + connect \Y $not$libresoc.v:26340$858_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:25970$860 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26342$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25970$860_Y + connect \Y $not$libresoc.v:26342$860_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:25973$863 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26345$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25973$863_Y + connect \Y $not$libresoc.v:26345$863_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:25967$857 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26339$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38617,10 +39004,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:25967$857_Y + connect \Y $or$libresoc.v:26339$857_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:25969$859 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26341$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38628,10 +39015,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:25969$859_Y + connect \Y $or$libresoc.v:26341$859_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:25972$862 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26344$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38639,39 +39026,39 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:25972$862_Y + connect \Y $or$libresoc.v:26344$862_Y end - attribute \src "libresoc.v:25931.7-25931.20" - process $proc$libresoc.v:25931$868 + attribute \src "libresoc.v:26303.7-26303.20" + process $proc$libresoc.v:26303$868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:25955.7-25955.19" - process $proc$libresoc.v:25955$869 + attribute \src "libresoc.v:26327.7-26327.19" + process $proc$libresoc.v:26327$869 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:25974.3-25975.27" - process $proc$libresoc.v:25974$864 + attribute \src "libresoc.v:26346.3-26347.27" + process $proc$libresoc.v:26346$864 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:25976.3-25984.6" - process $proc$libresoc.v:25976$865 + attribute \src "libresoc.v:26348.3-26356.6" + process $proc$libresoc.v:26348$865 assign { } { } assign { } { } assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:25977.5-25977.29" + attribute \src "libresoc.v:26349.5-26349.29" switch \initial - attribute \src "libresoc.v:25977.9-25977.17" + attribute \src "libresoc.v:26349.9-26349.17" case 1'1 case end @@ -38687,87 +39074,87 @@ module \alu_l$107 sync always update \q_int$next $0\q_int$next[0:0]$866 end - connect \$9 $and$libresoc.v:25966$856_Y - connect \$11 $or$libresoc.v:25967$857_Y - connect \$13 $not$libresoc.v:25968$858_Y - connect \$15 $or$libresoc.v:25969$859_Y - connect \$1 $not$libresoc.v:25970$860_Y - connect \$3 $and$libresoc.v:25971$861_Y - connect \$5 $or$libresoc.v:25972$862_Y - connect \$7 $not$libresoc.v:25973$863_Y + connect \$9 $and$libresoc.v:26338$856_Y + connect \$11 $or$libresoc.v:26339$857_Y + connect \$13 $not$libresoc.v:26340$858_Y + connect \$15 $or$libresoc.v:26341$859_Y + connect \$1 $not$libresoc.v:26342$860_Y + connect \$3 $and$libresoc.v:26343$861_Y + connect \$5 $or$libresoc.v:26344$862_Y + connect \$7 $not$libresoc.v:26345$863_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:25992.1-26050.10" +attribute \src "libresoc.v:26364.1-26422.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" attribute \generator "nMigen" module \alu_l$125 - attribute \src "libresoc.v:25993.7-25993.20" + attribute \src "libresoc.v:26365.7-26365.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26038.3-26046.6" + attribute \src "libresoc.v:26410.3-26418.6" wire $0\q_int$next[0:0]$880 - attribute \src "libresoc.v:26036.3-26037.27" + attribute \src "libresoc.v:26408.3-26409.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26038.3-26046.6" + attribute \src "libresoc.v:26410.3-26418.6" wire $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26017.7-26017.19" + attribute \src "libresoc.v:26389.7-26389.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26028.17-26028.96" - wire $and$libresoc.v:26028$870_Y - attribute \src "libresoc.v:26033.17-26033.96" - wire $and$libresoc.v:26033$875_Y - attribute \src "libresoc.v:26030.18-26030.93" - wire $not$libresoc.v:26030$872_Y - attribute \src "libresoc.v:26032.17-26032.92" - wire $not$libresoc.v:26032$874_Y - attribute \src "libresoc.v:26035.17-26035.92" - wire $not$libresoc.v:26035$877_Y - attribute \src "libresoc.v:26029.18-26029.98" - wire $or$libresoc.v:26029$871_Y - attribute \src "libresoc.v:26031.18-26031.99" - wire $or$libresoc.v:26031$873_Y - attribute \src "libresoc.v:26034.17-26034.97" - wire $or$libresoc.v:26034$876_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26400.17-26400.96" + wire $and$libresoc.v:26400$870_Y + attribute \src "libresoc.v:26405.17-26405.96" + wire $and$libresoc.v:26405$875_Y + attribute \src "libresoc.v:26402.18-26402.93" + wire $not$libresoc.v:26402$872_Y + attribute \src "libresoc.v:26404.17-26404.92" + wire $not$libresoc.v:26404$874_Y + attribute \src "libresoc.v:26407.17-26407.92" + wire $not$libresoc.v:26407$877_Y + attribute \src "libresoc.v:26401.18-26401.98" + wire $or$libresoc.v:26401$871_Y + attribute \src "libresoc.v:26403.18-26403.99" + wire $or$libresoc.v:26403$873_Y + attribute \src "libresoc.v:26406.17-26406.97" + wire $or$libresoc.v:26406$876_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:25993.7-25993.15" + attribute \src "libresoc.v:26365.7-26365.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26028$870 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26400$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38775,10 +39162,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26028$870_Y + connect \Y $and$libresoc.v:26400$870_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26033$875 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26405$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38786,34 +39173,34 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26033$875_Y + connect \Y $and$libresoc.v:26405$875_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26030$872 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26402$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26030$872_Y + connect \Y $not$libresoc.v:26402$872_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26032$874 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26404$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26032$874_Y + connect \Y $not$libresoc.v:26404$874_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26035$877 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26407$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26035$877_Y + connect \Y $not$libresoc.v:26407$877_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26029$871 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26401$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38821,10 +39208,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26029$871_Y + connect \Y $or$libresoc.v:26401$871_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26031$873 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26403$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38832,10 +39219,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26031$873_Y + connect \Y $or$libresoc.v:26403$873_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26034$876 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26406$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38843,39 +39230,39 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26034$876_Y + connect \Y $or$libresoc.v:26406$876_Y end - attribute \src "libresoc.v:25993.7-25993.20" - process $proc$libresoc.v:25993$882 + attribute \src "libresoc.v:26365.7-26365.20" + process $proc$libresoc.v:26365$882 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26017.7-26017.19" - process $proc$libresoc.v:26017$883 + attribute \src "libresoc.v:26389.7-26389.19" + process $proc$libresoc.v:26389$883 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26036.3-26037.27" - process $proc$libresoc.v:26036$878 + attribute \src "libresoc.v:26408.3-26409.27" + process $proc$libresoc.v:26408$878 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26038.3-26046.6" - process $proc$libresoc.v:26038$879 + attribute \src "libresoc.v:26410.3-26418.6" + process $proc$libresoc.v:26410$879 assign { } { } assign { } { } assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26039.5-26039.29" + attribute \src "libresoc.v:26411.5-26411.29" switch \initial - attribute \src "libresoc.v:26039.9-26039.17" + attribute \src "libresoc.v:26411.9-26411.17" case 1'1 case end @@ -38891,87 +39278,87 @@ module \alu_l$125 sync always update \q_int$next $0\q_int$next[0:0]$880 end - connect \$9 $and$libresoc.v:26028$870_Y - connect \$11 $or$libresoc.v:26029$871_Y - connect \$13 $not$libresoc.v:26030$872_Y - connect \$15 $or$libresoc.v:26031$873_Y - connect \$1 $not$libresoc.v:26032$874_Y - connect \$3 $and$libresoc.v:26033$875_Y - connect \$5 $or$libresoc.v:26034$876_Y - connect \$7 $not$libresoc.v:26035$877_Y + connect \$9 $and$libresoc.v:26400$870_Y + connect \$11 $or$libresoc.v:26401$871_Y + connect \$13 $not$libresoc.v:26402$872_Y + connect \$15 $or$libresoc.v:26403$873_Y + connect \$1 $not$libresoc.v:26404$874_Y + connect \$3 $and$libresoc.v:26405$875_Y + connect \$5 $or$libresoc.v:26406$876_Y + connect \$7 $not$libresoc.v:26407$877_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26054.1-26112.10" +attribute \src "libresoc.v:26426.1-26484.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" attribute \generator "nMigen" module \alu_l$128 - attribute \src "libresoc.v:26055.7-26055.20" + attribute \src "libresoc.v:26427.7-26427.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26100.3-26108.6" + attribute \src "libresoc.v:26472.3-26480.6" wire $0\q_int$next[0:0]$894 - attribute \src "libresoc.v:26098.3-26099.27" + attribute \src "libresoc.v:26470.3-26471.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26100.3-26108.6" + attribute \src "libresoc.v:26472.3-26480.6" wire $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26079.7-26079.19" + attribute \src "libresoc.v:26451.7-26451.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26090.17-26090.96" - wire $and$libresoc.v:26090$884_Y - attribute \src "libresoc.v:26095.17-26095.96" - wire $and$libresoc.v:26095$889_Y - attribute \src "libresoc.v:26092.18-26092.93" - wire $not$libresoc.v:26092$886_Y - attribute \src "libresoc.v:26094.17-26094.92" - wire $not$libresoc.v:26094$888_Y - attribute \src "libresoc.v:26097.17-26097.92" - wire $not$libresoc.v:26097$891_Y - attribute \src "libresoc.v:26091.18-26091.98" - wire $or$libresoc.v:26091$885_Y - attribute \src "libresoc.v:26093.18-26093.99" - wire $or$libresoc.v:26093$887_Y - attribute \src "libresoc.v:26096.17-26096.97" - wire $or$libresoc.v:26096$890_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26462.17-26462.96" + wire $and$libresoc.v:26462$884_Y + attribute \src "libresoc.v:26467.17-26467.96" + wire $and$libresoc.v:26467$889_Y + attribute \src "libresoc.v:26464.18-26464.93" + wire $not$libresoc.v:26464$886_Y + attribute \src "libresoc.v:26466.17-26466.92" + wire $not$libresoc.v:26466$888_Y + attribute \src "libresoc.v:26469.17-26469.92" + wire $not$libresoc.v:26469$891_Y + attribute \src "libresoc.v:26463.18-26463.98" + wire $or$libresoc.v:26463$885_Y + attribute \src "libresoc.v:26465.18-26465.99" + wire $or$libresoc.v:26465$887_Y + attribute \src "libresoc.v:26468.17-26468.97" + wire $or$libresoc.v:26468$890_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26055.7-26055.15" + attribute \src "libresoc.v:26427.7-26427.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26090$884 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26462$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38979,10 +39366,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26090$884_Y + connect \Y $and$libresoc.v:26462$884_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26095$889 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26467$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38990,34 +39377,34 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26095$889_Y + connect \Y $and$libresoc.v:26467$889_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26092$886 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26464$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26092$886_Y + connect \Y $not$libresoc.v:26464$886_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26094$888 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26466$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26094$888_Y + connect \Y $not$libresoc.v:26466$888_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26097$891 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26469$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26097$891_Y + connect \Y $not$libresoc.v:26469$891_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26091$885 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26463$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39025,10 +39412,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26091$885_Y + connect \Y $or$libresoc.v:26463$885_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26093$887 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26465$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39036,10 +39423,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26093$887_Y + connect \Y $or$libresoc.v:26465$887_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26096$890 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26468$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39047,39 +39434,39 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26096$890_Y + connect \Y $or$libresoc.v:26468$890_Y end - attribute \src "libresoc.v:26055.7-26055.20" - process $proc$libresoc.v:26055$896 + attribute \src "libresoc.v:26427.7-26427.20" + process $proc$libresoc.v:26427$896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26079.7-26079.19" - process $proc$libresoc.v:26079$897 + attribute \src "libresoc.v:26451.7-26451.19" + process $proc$libresoc.v:26451$897 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26098.3-26099.27" - process $proc$libresoc.v:26098$892 + attribute \src "libresoc.v:26470.3-26471.27" + process $proc$libresoc.v:26470$892 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26100.3-26108.6" - process $proc$libresoc.v:26100$893 + attribute \src "libresoc.v:26472.3-26480.6" + process $proc$libresoc.v:26472$893 assign { } { } assign { } { } assign $0\q_int$next[0:0]$894 $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26101.5-26101.29" + attribute \src "libresoc.v:26473.5-26473.29" switch \initial - attribute \src "libresoc.v:26101.9-26101.17" + attribute \src "libresoc.v:26473.9-26473.17" case 1'1 case end @@ -39095,87 +39482,87 @@ module \alu_l$128 sync always update \q_int$next $0\q_int$next[0:0]$894 end - connect \$9 $and$libresoc.v:26090$884_Y - connect \$11 $or$libresoc.v:26091$885_Y - connect \$13 $not$libresoc.v:26092$886_Y - connect \$15 $or$libresoc.v:26093$887_Y - connect \$1 $not$libresoc.v:26094$888_Y - connect \$3 $and$libresoc.v:26095$889_Y - connect \$5 $or$libresoc.v:26096$890_Y - connect \$7 $not$libresoc.v:26097$891_Y + connect \$9 $and$libresoc.v:26462$884_Y + connect \$11 $or$libresoc.v:26463$885_Y + connect \$13 $not$libresoc.v:26464$886_Y + connect \$15 $or$libresoc.v:26465$887_Y + connect \$1 $not$libresoc.v:26466$888_Y + connect \$3 $and$libresoc.v:26467$889_Y + connect \$5 $or$libresoc.v:26468$890_Y + connect \$7 $not$libresoc.v:26469$891_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26116.1-26174.10" +attribute \src "libresoc.v:26488.1-26546.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" attribute \generator "nMigen" module \alu_l$16 - attribute \src "libresoc.v:26117.7-26117.20" + attribute \src "libresoc.v:26489.7-26489.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26162.3-26170.6" + attribute \src "libresoc.v:26534.3-26542.6" wire $0\q_int$next[0:0]$908 - attribute \src "libresoc.v:26160.3-26161.27" + attribute \src "libresoc.v:26532.3-26533.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26162.3-26170.6" + attribute \src "libresoc.v:26534.3-26542.6" wire $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26141.7-26141.19" + attribute \src "libresoc.v:26513.7-26513.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26152.17-26152.96" - wire $and$libresoc.v:26152$898_Y - attribute \src "libresoc.v:26157.17-26157.96" - wire $and$libresoc.v:26157$903_Y - attribute \src "libresoc.v:26154.18-26154.93" - wire $not$libresoc.v:26154$900_Y - attribute \src "libresoc.v:26156.17-26156.92" - wire $not$libresoc.v:26156$902_Y - attribute \src "libresoc.v:26159.17-26159.92" - wire $not$libresoc.v:26159$905_Y - attribute \src "libresoc.v:26153.18-26153.98" - wire $or$libresoc.v:26153$899_Y - attribute \src "libresoc.v:26155.18-26155.99" - wire $or$libresoc.v:26155$901_Y - attribute \src "libresoc.v:26158.17-26158.97" - wire $or$libresoc.v:26158$904_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26524.17-26524.96" + wire $and$libresoc.v:26524$898_Y + attribute \src "libresoc.v:26529.17-26529.96" + wire $and$libresoc.v:26529$903_Y + attribute \src "libresoc.v:26526.18-26526.93" + wire $not$libresoc.v:26526$900_Y + attribute \src "libresoc.v:26528.17-26528.92" + wire $not$libresoc.v:26528$902_Y + attribute \src "libresoc.v:26531.17-26531.92" + wire $not$libresoc.v:26531$905_Y + attribute \src "libresoc.v:26525.18-26525.98" + wire $or$libresoc.v:26525$899_Y + attribute \src "libresoc.v:26527.18-26527.99" + wire $or$libresoc.v:26527$901_Y + attribute \src "libresoc.v:26530.17-26530.97" + wire $or$libresoc.v:26530$904_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26117.7-26117.15" + attribute \src "libresoc.v:26489.7-26489.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26152$898 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26524$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39183,10 +39570,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26152$898_Y + connect \Y $and$libresoc.v:26524$898_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26157$903 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26529$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39194,34 +39581,34 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26157$903_Y + connect \Y $and$libresoc.v:26529$903_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26154$900 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26526$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26154$900_Y + connect \Y $not$libresoc.v:26526$900_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26156$902 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26528$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26156$902_Y + connect \Y $not$libresoc.v:26528$902_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26159$905 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26531$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26159$905_Y + connect \Y $not$libresoc.v:26531$905_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26153$899 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26525$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39229,10 +39616,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26153$899_Y + connect \Y $or$libresoc.v:26525$899_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26155$901 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26527$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39240,10 +39627,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26155$901_Y + connect \Y $or$libresoc.v:26527$901_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26158$904 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26530$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39251,39 +39638,39 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26158$904_Y + connect \Y $or$libresoc.v:26530$904_Y end - attribute \src "libresoc.v:26117.7-26117.20" - process $proc$libresoc.v:26117$910 + attribute \src "libresoc.v:26489.7-26489.20" + process $proc$libresoc.v:26489$910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26141.7-26141.19" - process $proc$libresoc.v:26141$911 + attribute \src "libresoc.v:26513.7-26513.19" + process $proc$libresoc.v:26513$911 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26160.3-26161.27" - process $proc$libresoc.v:26160$906 + attribute \src "libresoc.v:26532.3-26533.27" + process $proc$libresoc.v:26532$906 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26162.3-26170.6" - process $proc$libresoc.v:26162$907 + attribute \src "libresoc.v:26534.3-26542.6" + process $proc$libresoc.v:26534$907 assign { } { } assign { } { } assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26163.5-26163.29" + attribute \src "libresoc.v:26535.5-26535.29" switch \initial - attribute \src "libresoc.v:26163.9-26163.17" + attribute \src "libresoc.v:26535.9-26535.17" case 1'1 case end @@ -39299,87 +39686,87 @@ module \alu_l$16 sync always update \q_int$next $0\q_int$next[0:0]$908 end - connect \$9 $and$libresoc.v:26152$898_Y - connect \$11 $or$libresoc.v:26153$899_Y - connect \$13 $not$libresoc.v:26154$900_Y - connect \$15 $or$libresoc.v:26155$901_Y - connect \$1 $not$libresoc.v:26156$902_Y - connect \$3 $and$libresoc.v:26157$903_Y - connect \$5 $or$libresoc.v:26158$904_Y - connect \$7 $not$libresoc.v:26159$905_Y + connect \$9 $and$libresoc.v:26524$898_Y + connect \$11 $or$libresoc.v:26525$899_Y + connect \$13 $not$libresoc.v:26526$900_Y + connect \$15 $or$libresoc.v:26527$901_Y + connect \$1 $not$libresoc.v:26528$902_Y + connect \$3 $and$libresoc.v:26529$903_Y + connect \$5 $or$libresoc.v:26530$904_Y + connect \$7 $not$libresoc.v:26531$905_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26178.1-26236.10" +attribute \src "libresoc.v:26550.1-26608.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" attribute \generator "nMigen" module \alu_l$29 - attribute \src "libresoc.v:26179.7-26179.20" + attribute \src "libresoc.v:26551.7-26551.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26224.3-26232.6" + attribute \src "libresoc.v:26596.3-26604.6" wire $0\q_int$next[0:0]$922 - attribute \src "libresoc.v:26222.3-26223.27" + attribute \src "libresoc.v:26594.3-26595.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26224.3-26232.6" + attribute \src "libresoc.v:26596.3-26604.6" wire $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26203.7-26203.19" + attribute \src "libresoc.v:26575.7-26575.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26214.17-26214.96" - wire $and$libresoc.v:26214$912_Y - attribute \src "libresoc.v:26219.17-26219.96" - wire $and$libresoc.v:26219$917_Y - attribute \src "libresoc.v:26216.18-26216.93" - wire $not$libresoc.v:26216$914_Y - attribute \src "libresoc.v:26218.17-26218.92" - wire $not$libresoc.v:26218$916_Y - attribute \src "libresoc.v:26221.17-26221.92" - wire $not$libresoc.v:26221$919_Y - attribute \src "libresoc.v:26215.18-26215.98" - wire $or$libresoc.v:26215$913_Y - attribute \src "libresoc.v:26217.18-26217.99" - wire $or$libresoc.v:26217$915_Y - attribute \src "libresoc.v:26220.17-26220.97" - wire $or$libresoc.v:26220$918_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26586.17-26586.96" + wire $and$libresoc.v:26586$912_Y + attribute \src "libresoc.v:26591.17-26591.96" + wire $and$libresoc.v:26591$917_Y + attribute \src "libresoc.v:26588.18-26588.93" + wire $not$libresoc.v:26588$914_Y + attribute \src "libresoc.v:26590.17-26590.92" + wire $not$libresoc.v:26590$916_Y + attribute \src "libresoc.v:26593.17-26593.92" + wire $not$libresoc.v:26593$919_Y + attribute \src "libresoc.v:26587.18-26587.98" + wire $or$libresoc.v:26587$913_Y + attribute \src "libresoc.v:26589.18-26589.99" + wire $or$libresoc.v:26589$915_Y + attribute \src "libresoc.v:26592.17-26592.97" + wire $or$libresoc.v:26592$918_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26179.7-26179.15" + attribute \src "libresoc.v:26551.7-26551.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26214$912 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26586$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39387,10 +39774,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26214$912_Y + connect \Y $and$libresoc.v:26586$912_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26219$917 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26591$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39398,34 +39785,34 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26219$917_Y + connect \Y $and$libresoc.v:26591$917_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26216$914 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26588$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26216$914_Y + connect \Y $not$libresoc.v:26588$914_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26218$916 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26590$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26218$916_Y + connect \Y $not$libresoc.v:26590$916_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26221$919 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26593$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26221$919_Y + connect \Y $not$libresoc.v:26593$919_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26215$913 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26587$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39433,10 +39820,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26215$913_Y + connect \Y $or$libresoc.v:26587$913_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26217$915 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26589$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39444,10 +39831,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26217$915_Y + connect \Y $or$libresoc.v:26589$915_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26220$918 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26592$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39455,39 +39842,39 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26220$918_Y + connect \Y $or$libresoc.v:26592$918_Y end - attribute \src "libresoc.v:26179.7-26179.20" - process $proc$libresoc.v:26179$924 + attribute \src "libresoc.v:26551.7-26551.20" + process $proc$libresoc.v:26551$924 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26203.7-26203.19" - process $proc$libresoc.v:26203$925 + attribute \src "libresoc.v:26575.7-26575.19" + process $proc$libresoc.v:26575$925 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26222.3-26223.27" - process $proc$libresoc.v:26222$920 + attribute \src "libresoc.v:26594.3-26595.27" + process $proc$libresoc.v:26594$920 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26224.3-26232.6" - process $proc$libresoc.v:26224$921 + attribute \src "libresoc.v:26596.3-26604.6" + process $proc$libresoc.v:26596$921 assign { } { } assign { } { } assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26225.5-26225.29" + attribute \src "libresoc.v:26597.5-26597.29" switch \initial - attribute \src "libresoc.v:26225.9-26225.17" + attribute \src "libresoc.v:26597.9-26597.17" case 1'1 case end @@ -39503,87 +39890,87 @@ module \alu_l$29 sync always update \q_int$next $0\q_int$next[0:0]$922 end - connect \$9 $and$libresoc.v:26214$912_Y - connect \$11 $or$libresoc.v:26215$913_Y - connect \$13 $not$libresoc.v:26216$914_Y - connect \$15 $or$libresoc.v:26217$915_Y - connect \$1 $not$libresoc.v:26218$916_Y - connect \$3 $and$libresoc.v:26219$917_Y - connect \$5 $or$libresoc.v:26220$918_Y - connect \$7 $not$libresoc.v:26221$919_Y + connect \$9 $and$libresoc.v:26586$912_Y + connect \$11 $or$libresoc.v:26587$913_Y + connect \$13 $not$libresoc.v:26588$914_Y + connect \$15 $or$libresoc.v:26589$915_Y + connect \$1 $not$libresoc.v:26590$916_Y + connect \$3 $and$libresoc.v:26591$917_Y + connect \$5 $or$libresoc.v:26592$918_Y + connect \$7 $not$libresoc.v:26593$919_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26240.1-26298.10" +attribute \src "libresoc.v:26612.1-26670.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" attribute \generator "nMigen" module \alu_l$45 - attribute \src "libresoc.v:26241.7-26241.20" + attribute \src "libresoc.v:26613.7-26613.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26286.3-26294.6" + attribute \src "libresoc.v:26658.3-26666.6" wire $0\q_int$next[0:0]$936 - attribute \src "libresoc.v:26284.3-26285.27" + attribute \src "libresoc.v:26656.3-26657.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26286.3-26294.6" + attribute \src "libresoc.v:26658.3-26666.6" wire $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26265.7-26265.19" + attribute \src "libresoc.v:26637.7-26637.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26276.17-26276.96" - wire $and$libresoc.v:26276$926_Y - attribute \src "libresoc.v:26281.17-26281.96" - wire $and$libresoc.v:26281$931_Y - attribute \src "libresoc.v:26278.18-26278.93" - wire $not$libresoc.v:26278$928_Y - attribute \src "libresoc.v:26280.17-26280.92" - wire $not$libresoc.v:26280$930_Y - attribute \src "libresoc.v:26283.17-26283.92" - wire $not$libresoc.v:26283$933_Y - attribute \src "libresoc.v:26277.18-26277.98" - wire $or$libresoc.v:26277$927_Y - attribute \src "libresoc.v:26279.18-26279.99" - wire $or$libresoc.v:26279$929_Y - attribute \src "libresoc.v:26282.17-26282.97" - wire $or$libresoc.v:26282$932_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26648.17-26648.96" + wire $and$libresoc.v:26648$926_Y + attribute \src "libresoc.v:26653.17-26653.96" + wire $and$libresoc.v:26653$931_Y + attribute \src "libresoc.v:26650.18-26650.93" + wire $not$libresoc.v:26650$928_Y + attribute \src "libresoc.v:26652.17-26652.92" + wire $not$libresoc.v:26652$930_Y + attribute \src "libresoc.v:26655.17-26655.92" + wire $not$libresoc.v:26655$933_Y + attribute \src "libresoc.v:26649.18-26649.98" + wire $or$libresoc.v:26649$927_Y + attribute \src "libresoc.v:26651.18-26651.99" + wire $or$libresoc.v:26651$929_Y + attribute \src "libresoc.v:26654.17-26654.97" + wire $or$libresoc.v:26654$932_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26241.7-26241.15" + attribute \src "libresoc.v:26613.7-26613.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26276$926 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26648$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39591,10 +39978,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26276$926_Y + connect \Y $and$libresoc.v:26648$926_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26281$931 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26653$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39602,34 +39989,34 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26281$931_Y + connect \Y $and$libresoc.v:26653$931_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26278$928 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26650$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26278$928_Y + connect \Y $not$libresoc.v:26650$928_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26280$930 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26652$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26280$930_Y + connect \Y $not$libresoc.v:26652$930_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26283$933 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26655$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26283$933_Y + connect \Y $not$libresoc.v:26655$933_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26277$927 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26649$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39637,10 +40024,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26277$927_Y + connect \Y $or$libresoc.v:26649$927_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26279$929 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26651$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39648,10 +40035,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26279$929_Y + connect \Y $or$libresoc.v:26651$929_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26282$932 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26654$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39659,39 +40046,39 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26282$932_Y + connect \Y $or$libresoc.v:26654$932_Y end - attribute \src "libresoc.v:26241.7-26241.20" - process $proc$libresoc.v:26241$938 + attribute \src "libresoc.v:26613.7-26613.20" + process $proc$libresoc.v:26613$938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26265.7-26265.19" - process $proc$libresoc.v:26265$939 + attribute \src "libresoc.v:26637.7-26637.19" + process $proc$libresoc.v:26637$939 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26284.3-26285.27" - process $proc$libresoc.v:26284$934 + attribute \src "libresoc.v:26656.3-26657.27" + process $proc$libresoc.v:26656$934 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26286.3-26294.6" - process $proc$libresoc.v:26286$935 + attribute \src "libresoc.v:26658.3-26666.6" + process $proc$libresoc.v:26658$935 assign { } { } assign { } { } assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26287.5-26287.29" + attribute \src "libresoc.v:26659.5-26659.29" switch \initial - attribute \src "libresoc.v:26287.9-26287.17" + attribute \src "libresoc.v:26659.9-26659.17" case 1'1 case end @@ -39707,87 +40094,87 @@ module \alu_l$45 sync always update \q_int$next $0\q_int$next[0:0]$936 end - connect \$9 $and$libresoc.v:26276$926_Y - connect \$11 $or$libresoc.v:26277$927_Y - connect \$13 $not$libresoc.v:26278$928_Y - connect \$15 $or$libresoc.v:26279$929_Y - connect \$1 $not$libresoc.v:26280$930_Y - connect \$3 $and$libresoc.v:26281$931_Y - connect \$5 $or$libresoc.v:26282$932_Y - connect \$7 $not$libresoc.v:26283$933_Y + connect \$9 $and$libresoc.v:26648$926_Y + connect \$11 $or$libresoc.v:26649$927_Y + connect \$13 $not$libresoc.v:26650$928_Y + connect \$15 $or$libresoc.v:26651$929_Y + connect \$1 $not$libresoc.v:26652$930_Y + connect \$3 $and$libresoc.v:26653$931_Y + connect \$5 $or$libresoc.v:26654$932_Y + connect \$7 $not$libresoc.v:26655$933_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26302.1-26360.10" +attribute \src "libresoc.v:26674.1-26732.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" attribute \generator "nMigen" module \alu_l$61 - attribute \src "libresoc.v:26303.7-26303.20" + attribute \src "libresoc.v:26675.7-26675.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26348.3-26356.6" + attribute \src "libresoc.v:26720.3-26728.6" wire $0\q_int$next[0:0]$950 - attribute \src "libresoc.v:26346.3-26347.27" + attribute \src "libresoc.v:26718.3-26719.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26348.3-26356.6" + attribute \src "libresoc.v:26720.3-26728.6" wire $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26327.7-26327.19" + attribute \src "libresoc.v:26699.7-26699.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26338.17-26338.96" - wire $and$libresoc.v:26338$940_Y - attribute \src "libresoc.v:26343.17-26343.96" - wire $and$libresoc.v:26343$945_Y - attribute \src "libresoc.v:26340.18-26340.93" - wire $not$libresoc.v:26340$942_Y - attribute \src "libresoc.v:26342.17-26342.92" - wire $not$libresoc.v:26342$944_Y - attribute \src "libresoc.v:26345.17-26345.92" - wire $not$libresoc.v:26345$947_Y - attribute \src "libresoc.v:26339.18-26339.98" - wire $or$libresoc.v:26339$941_Y - attribute \src "libresoc.v:26341.18-26341.99" - wire $or$libresoc.v:26341$943_Y - attribute \src "libresoc.v:26344.17-26344.97" - wire $or$libresoc.v:26344$946_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26710.17-26710.96" + wire $and$libresoc.v:26710$940_Y + attribute \src "libresoc.v:26715.17-26715.96" + wire $and$libresoc.v:26715$945_Y + attribute \src "libresoc.v:26712.18-26712.93" + wire $not$libresoc.v:26712$942_Y + attribute \src "libresoc.v:26714.17-26714.92" + wire $not$libresoc.v:26714$944_Y + attribute \src "libresoc.v:26717.17-26717.92" + wire $not$libresoc.v:26717$947_Y + attribute \src "libresoc.v:26711.18-26711.98" + wire $or$libresoc.v:26711$941_Y + attribute \src "libresoc.v:26713.18-26713.99" + wire $or$libresoc.v:26713$943_Y + attribute \src "libresoc.v:26716.17-26716.97" + wire $or$libresoc.v:26716$946_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26303.7-26303.15" + attribute \src "libresoc.v:26675.7-26675.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26338$940 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26710$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39795,10 +40182,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26338$940_Y + connect \Y $and$libresoc.v:26710$940_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26343$945 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26715$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39806,34 +40193,34 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26343$945_Y + connect \Y $and$libresoc.v:26715$945_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26340$942 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26712$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26340$942_Y + connect \Y $not$libresoc.v:26712$942_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26342$944 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26714$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26342$944_Y + connect \Y $not$libresoc.v:26714$944_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26345$947 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26717$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26345$947_Y + connect \Y $not$libresoc.v:26717$947_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26339$941 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26711$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39841,10 +40228,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26339$941_Y + connect \Y $or$libresoc.v:26711$941_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26341$943 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26713$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39852,10 +40239,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26341$943_Y + connect \Y $or$libresoc.v:26713$943_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26344$946 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26716$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39863,39 +40250,39 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26344$946_Y + connect \Y $or$libresoc.v:26716$946_Y end - attribute \src "libresoc.v:26303.7-26303.20" - process $proc$libresoc.v:26303$952 + attribute \src "libresoc.v:26675.7-26675.20" + process $proc$libresoc.v:26675$952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26327.7-26327.19" - process $proc$libresoc.v:26327$953 + attribute \src "libresoc.v:26699.7-26699.19" + process $proc$libresoc.v:26699$953 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26346.3-26347.27" - process $proc$libresoc.v:26346$948 + attribute \src "libresoc.v:26718.3-26719.27" + process $proc$libresoc.v:26718$948 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26348.3-26356.6" - process $proc$libresoc.v:26348$949 + attribute \src "libresoc.v:26720.3-26728.6" + process $proc$libresoc.v:26720$949 assign { } { } assign { } { } assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26349.5-26349.29" + attribute \src "libresoc.v:26721.5-26721.29" switch \initial - attribute \src "libresoc.v:26349.9-26349.17" + attribute \src "libresoc.v:26721.9-26721.17" case 1'1 case end @@ -39911,87 +40298,87 @@ module \alu_l$61 sync always update \q_int$next $0\q_int$next[0:0]$950 end - connect \$9 $and$libresoc.v:26338$940_Y - connect \$11 $or$libresoc.v:26339$941_Y - connect \$13 $not$libresoc.v:26340$942_Y - connect \$15 $or$libresoc.v:26341$943_Y - connect \$1 $not$libresoc.v:26342$944_Y - connect \$3 $and$libresoc.v:26343$945_Y - connect \$5 $or$libresoc.v:26344$946_Y - connect \$7 $not$libresoc.v:26345$947_Y + connect \$9 $and$libresoc.v:26710$940_Y + connect \$11 $or$libresoc.v:26711$941_Y + connect \$13 $not$libresoc.v:26712$942_Y + connect \$15 $or$libresoc.v:26713$943_Y + connect \$1 $not$libresoc.v:26714$944_Y + connect \$3 $and$libresoc.v:26715$945_Y + connect \$5 $or$libresoc.v:26716$946_Y + connect \$7 $not$libresoc.v:26717$947_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26364.1-26422.10" +attribute \src "libresoc.v:26736.1-26794.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_l" attribute \generator "nMigen" module \alu_l$73 - attribute \src "libresoc.v:26365.7-26365.20" + attribute \src "libresoc.v:26737.7-26737.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26410.3-26418.6" + attribute \src "libresoc.v:26782.3-26790.6" wire $0\q_int$next[0:0]$964 - attribute \src "libresoc.v:26408.3-26409.27" + attribute \src "libresoc.v:26780.3-26781.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26410.3-26418.6" + attribute \src "libresoc.v:26782.3-26790.6" wire $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26389.7-26389.19" + attribute \src "libresoc.v:26761.7-26761.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26400.17-26400.96" - wire $and$libresoc.v:26400$954_Y - attribute \src "libresoc.v:26405.17-26405.96" - wire $and$libresoc.v:26405$959_Y - attribute \src "libresoc.v:26402.18-26402.93" - wire $not$libresoc.v:26402$956_Y - attribute \src "libresoc.v:26404.17-26404.92" - wire $not$libresoc.v:26404$958_Y - attribute \src "libresoc.v:26407.17-26407.92" - wire $not$libresoc.v:26407$961_Y - attribute \src "libresoc.v:26401.18-26401.98" - wire $or$libresoc.v:26401$955_Y - attribute \src "libresoc.v:26403.18-26403.99" - wire $or$libresoc.v:26403$957_Y - attribute \src "libresoc.v:26406.17-26406.97" - wire $or$libresoc.v:26406$960_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26772.17-26772.96" + wire $and$libresoc.v:26772$954_Y + attribute \src "libresoc.v:26777.17-26777.96" + wire $and$libresoc.v:26777$959_Y + attribute \src "libresoc.v:26774.18-26774.93" + wire $not$libresoc.v:26774$956_Y + attribute \src "libresoc.v:26776.17-26776.92" + wire $not$libresoc.v:26776$958_Y + attribute \src "libresoc.v:26779.17-26779.92" + wire $not$libresoc.v:26779$961_Y + attribute \src "libresoc.v:26773.18-26773.98" + wire $or$libresoc.v:26773$955_Y + attribute \src "libresoc.v:26775.18-26775.99" + wire $or$libresoc.v:26775$957_Y + attribute \src "libresoc.v:26778.17-26778.97" + wire $or$libresoc.v:26778$960_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26365.7-26365.15" + attribute \src "libresoc.v:26737.7-26737.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26400$954 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26772$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39999,10 +40386,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26400$954_Y + connect \Y $and$libresoc.v:26772$954_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26405$959 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26777$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40010,34 +40397,34 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26405$959_Y + connect \Y $and$libresoc.v:26777$959_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26402$956 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26774$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26402$956_Y + connect \Y $not$libresoc.v:26774$956_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26404$958 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26776$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26404$958_Y + connect \Y $not$libresoc.v:26776$958_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26407$961 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26779$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26407$961_Y + connect \Y $not$libresoc.v:26779$961_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26401$955 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26773$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40045,10 +40432,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26401$955_Y + connect \Y $or$libresoc.v:26773$955_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26403$957 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26775$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40056,10 +40443,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26403$957_Y + connect \Y $or$libresoc.v:26775$957_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26406$960 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26778$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40067,39 +40454,39 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26406$960_Y + connect \Y $or$libresoc.v:26778$960_Y end - attribute \src "libresoc.v:26365.7-26365.20" - process $proc$libresoc.v:26365$966 + attribute \src "libresoc.v:26737.7-26737.20" + process $proc$libresoc.v:26737$966 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26389.7-26389.19" - process $proc$libresoc.v:26389$967 + attribute \src "libresoc.v:26761.7-26761.19" + process $proc$libresoc.v:26761$967 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26408.3-26409.27" - process $proc$libresoc.v:26408$962 + attribute \src "libresoc.v:26780.3-26781.27" + process $proc$libresoc.v:26780$962 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26410.3-26418.6" - process $proc$libresoc.v:26410$963 + attribute \src "libresoc.v:26782.3-26790.6" + process $proc$libresoc.v:26782$963 assign { } { } assign { } { } assign $0\q_int$next[0:0]$964 $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26411.5-26411.29" + attribute \src "libresoc.v:26783.5-26783.29" switch \initial - attribute \src "libresoc.v:26411.9-26411.17" + attribute \src "libresoc.v:26783.9-26783.17" case 1'1 case end @@ -40115,87 +40502,87 @@ module \alu_l$73 sync always update \q_int$next $0\q_int$next[0:0]$964 end - connect \$9 $and$libresoc.v:26400$954_Y - connect \$11 $or$libresoc.v:26401$955_Y - connect \$13 $not$libresoc.v:26402$956_Y - connect \$15 $or$libresoc.v:26403$957_Y - connect \$1 $not$libresoc.v:26404$958_Y - connect \$3 $and$libresoc.v:26405$959_Y - connect \$5 $or$libresoc.v:26406$960_Y - connect \$7 $not$libresoc.v:26407$961_Y + connect \$9 $and$libresoc.v:26772$954_Y + connect \$11 $or$libresoc.v:26773$955_Y + connect \$13 $not$libresoc.v:26774$956_Y + connect \$15 $or$libresoc.v:26775$957_Y + connect \$1 $not$libresoc.v:26776$958_Y + connect \$3 $and$libresoc.v:26777$959_Y + connect \$5 $or$libresoc.v:26778$960_Y + connect \$7 $not$libresoc.v:26779$961_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26426.1-26484.10" +attribute \src "libresoc.v:26798.1-26856.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_l" attribute \generator "nMigen" module \alu_l$90 - attribute \src "libresoc.v:26427.7-26427.20" + attribute \src "libresoc.v:26799.7-26799.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26472.3-26480.6" + attribute \src "libresoc.v:26844.3-26852.6" wire $0\q_int$next[0:0]$978 - attribute \src "libresoc.v:26470.3-26471.27" + attribute \src "libresoc.v:26842.3-26843.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26472.3-26480.6" + attribute \src "libresoc.v:26844.3-26852.6" wire $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26451.7-26451.19" + attribute \src "libresoc.v:26823.7-26823.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26462.17-26462.96" - wire $and$libresoc.v:26462$968_Y - attribute \src "libresoc.v:26467.17-26467.96" - wire $and$libresoc.v:26467$973_Y - attribute \src "libresoc.v:26464.18-26464.93" - wire $not$libresoc.v:26464$970_Y - attribute \src "libresoc.v:26466.17-26466.92" - wire $not$libresoc.v:26466$972_Y - attribute \src "libresoc.v:26469.17-26469.92" - wire $not$libresoc.v:26469$975_Y - attribute \src "libresoc.v:26463.18-26463.98" - wire $or$libresoc.v:26463$969_Y - attribute \src "libresoc.v:26465.18-26465.99" - wire $or$libresoc.v:26465$971_Y - attribute \src "libresoc.v:26468.17-26468.97" - wire $or$libresoc.v:26468$974_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:26834.17-26834.96" + wire $and$libresoc.v:26834$968_Y + attribute \src "libresoc.v:26839.17-26839.96" + wire $and$libresoc.v:26839$973_Y + attribute \src "libresoc.v:26836.18-26836.93" + wire $not$libresoc.v:26836$970_Y + attribute \src "libresoc.v:26838.17-26838.92" + wire $not$libresoc.v:26838$972_Y + attribute \src "libresoc.v:26841.17-26841.92" + wire $not$libresoc.v:26841$975_Y + attribute \src "libresoc.v:26835.18-26835.98" + wire $or$libresoc.v:26835$969_Y + attribute \src "libresoc.v:26837.18-26837.99" + wire $or$libresoc.v:26837$971_Y + attribute \src "libresoc.v:26840.17-26840.97" + wire $or$libresoc.v:26840$974_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26427.7-26427.15" + attribute \src "libresoc.v:26799.7-26799.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26462$968 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26834$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40203,10 +40590,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26462$968_Y + connect \Y $and$libresoc.v:26834$968_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26467$973 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26839$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40214,34 +40601,34 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26467$973_Y + connect \Y $and$libresoc.v:26839$973_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26464$970 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26836$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26464$970_Y + connect \Y $not$libresoc.v:26836$970_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26466$972 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26838$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26466$972_Y + connect \Y $not$libresoc.v:26838$972_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26469$975 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26841$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26469$975_Y + connect \Y $not$libresoc.v:26841$975_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26463$969 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26835$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40249,10 +40636,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26463$969_Y + connect \Y $or$libresoc.v:26835$969_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26465$971 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26837$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40260,10 +40647,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26465$971_Y + connect \Y $or$libresoc.v:26837$971_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26468$974 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26840$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40271,39 +40658,39 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26468$974_Y + connect \Y $or$libresoc.v:26840$974_Y end - attribute \src "libresoc.v:26427.7-26427.20" - process $proc$libresoc.v:26427$980 + attribute \src "libresoc.v:26799.7-26799.20" + process $proc$libresoc.v:26799$980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26451.7-26451.19" - process $proc$libresoc.v:26451$981 + attribute \src "libresoc.v:26823.7-26823.19" + process $proc$libresoc.v:26823$981 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26470.3-26471.27" - process $proc$libresoc.v:26470$976 + attribute \src "libresoc.v:26842.3-26843.27" + process $proc$libresoc.v:26842$976 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26472.3-26480.6" - process $proc$libresoc.v:26472$977 + attribute \src "libresoc.v:26844.3-26852.6" + process $proc$libresoc.v:26844$977 assign { } { } assign { } { } assign $0\q_int$next[0:0]$978 $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26473.5-26473.29" + attribute \src "libresoc.v:26845.5-26845.29" switch \initial - attribute \src "libresoc.v:26473.9-26473.17" + attribute \src "libresoc.v:26845.9-26845.17" case 1'1 case end @@ -40319,26 +40706,26 @@ module \alu_l$90 sync always update \q_int$next $0\q_int$next[0:0]$978 end - connect \$9 $and$libresoc.v:26462$968_Y - connect \$11 $or$libresoc.v:26463$969_Y - connect \$13 $not$libresoc.v:26464$970_Y - connect \$15 $or$libresoc.v:26465$971_Y - connect \$1 $not$libresoc.v:26466$972_Y - connect \$3 $and$libresoc.v:26467$973_Y - connect \$5 $or$libresoc.v:26468$974_Y - connect \$7 $not$libresoc.v:26469$975_Y + connect \$9 $and$libresoc.v:26834$968_Y + connect \$11 $or$libresoc.v:26835$969_Y + connect \$13 $not$libresoc.v:26836$970_Y + connect \$15 $or$libresoc.v:26837$971_Y + connect \$1 $not$libresoc.v:26838$972_Y + connect \$3 $and$libresoc.v:26839$973_Y + connect \$5 $or$libresoc.v:26840$974_Y + connect \$7 $not$libresoc.v:26841$975_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26488.1-27483.10" +attribute \src "libresoc.v:26860.1-27873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -40349,35 +40736,39 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$61 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 7 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$46 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -40476,6 +40867,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -40552,6 +40944,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -40607,35 +41000,39 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe1_logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_pipe1_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe1_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_pipe1_logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe1_logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_pipe1_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -40734,6 +41131,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe1_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -40810,6 +41208,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe1_logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -40856,21 +41255,21 @@ module \alu_logical0 wire \logical_pipe1_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \logical_pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \logical_pipe1_muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \logical_pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \logical_pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \logical_pipe1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \logical_pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \logical_pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \logical_pipe1_ra @@ -40895,35 +41294,39 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe2_logical_op__data_len$38 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_pipe2_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe2_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_pipe2_logical_op__fn_unit$23 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe2_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_pipe2_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41022,6 +41425,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe2_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -41098,6 +41502,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe2_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41144,13 +41549,13 @@ module \alu_logical0 wire \logical_pipe2_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__zero_a$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \logical_pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \logical_pipe2_muxid$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \logical_pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \logical_pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \logical_pipe2_o @@ -41160,29 +41565,29 @@ module \alu_logical0 wire \logical_pipe2_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_o_ok$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \logical_pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \logical_pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 5 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 4 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 24 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 30 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 29 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 26 \ra @@ -41191,7 +41596,7 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 28 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:27343.17-27397.4" + attribute \src "libresoc.v:27733.17-27787.4" cell \logical_pipe1 \logical_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41248,7 +41653,7 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27398.17-27453.4" + attribute \src "libresoc.v:27788.17-27843.4" cell \logical_pipe2 \logical_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41306,13 +41711,13 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe2_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27454.10-27457.4" + attribute \src "libresoc.v:27844.10-27847.4" cell \n$47 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:27458.10-27461.4" + attribute \src "libresoc.v:27848.10-27851.4" cell \p$46 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i @@ -41339,49 +41744,53 @@ module \alu_logical0 connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o end -attribute \src "libresoc.v:27487.1-28680.10" +attribute \src "libresoc.v:27877.1-29094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \cr_a_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$51 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 10 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41468,6 +41877,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -41544,6 +41954,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41575,35 +41986,39 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$58 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe1_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe1_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe1_mul_op__fn_unit$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe1_mul_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe1_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41690,6 +42105,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe1_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -41766,6 +42182,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe1_mul_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41796,21 +42213,21 @@ module \alu_mul0 wire \mul_pipe1_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__write_cr0$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe1_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \mul_pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \mul_pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \mul_pipe1_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire \mul_pipe1_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \mul_pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \mul_pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul_pipe1_ra @@ -41825,35 +42242,39 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe1_xer_so$17 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe2_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe2_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe2_mul_op__fn_unit$20 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe2_mul_op__fn_unit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe2_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41940,6 +42361,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe2_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -42016,6 +42438,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe2_mul_op__insn_type$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42046,13 +42469,13 @@ module \alu_mul0 wire \mul_pipe2_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__write_cr0$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe2_muxid$18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \mul_pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \mul_pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \mul_pipe2_neg_res @@ -42064,9 +42487,9 @@ module \alu_mul0 wire \mul_pipe2_neg_res32$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul_pipe2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \mul_pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \mul_pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul_pipe2_ra @@ -42081,35 +42504,39 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_cr_a_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe3_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe3_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe3_mul_op__fn_unit$36 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe3_mul_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42196,6 +42623,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe3_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -42272,6 +42700,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe3_mul_op__insn_type$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42302,13 +42731,13 @@ module \alu_mul0 wire \mul_pipe3_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__write_cr0$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe3_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe3_muxid$34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \mul_pipe3_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \mul_pipe3_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire \mul_pipe3_neg_res @@ -42320,9 +42749,9 @@ module \alu_mul0 wire width 64 \mul_pipe3_o$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \mul_pipe3_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \mul_pipe3_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \mul_pipe3_xer_ov @@ -42334,21 +42763,21 @@ module \alu_mul0 wire \mul_pipe3_xer_so$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 7 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 6 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 20 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 28 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 27 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 24 \ra @@ -42365,7 +42794,7 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:28508.13-28549.4" + attribute \src "libresoc.v:28922.13-28963.4" cell \mul_pipe1 \mul_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42409,7 +42838,7 @@ module \alu_mul0 connect \xer_so$16 \mul_pipe1_xer_so$17 end attribute \module_not_derived 1 - attribute \src "libresoc.v:28550.13-28592.4" + attribute \src "libresoc.v:28964.13-29006.4" cell \mul_pipe2 \mul_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42454,7 +42883,7 @@ module \alu_mul0 connect \xer_so$14 \mul_pipe2_xer_so$31 end attribute \module_not_derived 1 - attribute \src "libresoc.v:28593.13-28638.4" + attribute \src "libresoc.v:29007.13-29052.4" cell \mul_pipe3 \mul_pipe3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42502,13 +42931,13 @@ module \alu_mul0 connect \xer_so_ok \mul_pipe3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:28639.10-28642.4" + attribute \src "libresoc.v:29053.10-29056.4" cell \n$92 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:28643.10-28646.4" + attribute \src "libresoc.v:29057.10-29060.4" cell \p$91 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i @@ -42547,54 +42976,54 @@ module \alu_mul0 connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o end -attribute \src "libresoc.v:28684.1-29699.10" +attribute \src "libresoc.v:29098.1-30131.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 24 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 33 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 32 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe1_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_ra @@ -42603,35 +43032,39 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rc attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_sr_op__fn_unit$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_sr_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42734,6 +43167,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -42810,6 +43244,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_sr_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42872,13 +43307,13 @@ module \alu_shift_rot0 wire \pipe2_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_cr_a_ok$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe2_o @@ -42888,40 +43323,44 @@ module \alu_shift_rot0 wire \pipe2_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_o_ok$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe2_p_valid_i attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_sr_op__fn_unit$24 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_sr_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43024,6 +43463,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -43100,6 +43540,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_sr_op__insn_type$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43161,35 +43602,39 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 29 \rc attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 8 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 8 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$48 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 9 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43292,6 +43737,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 7 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -43368,6 +43814,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43419,19 +43866,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 30 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:29551.11-29554.4" + attribute \src "libresoc.v:29983.11-29986.4" cell \n$109 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:29555.11-29558.4" + attribute \src "libresoc.v:29987.11-29990.4" cell \p$108 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:29559.15-29615.4" + attribute \src "libresoc.v:29991.15-30047.4" cell \pipe1$110 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -43490,7 +43937,7 @@ module \alu_shift_rot0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:29616.15-29673.4" + attribute \src "libresoc.v:30048.15-30105.4" cell \pipe2$115 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -43575,14 +44022,14 @@ module \alu_shift_rot0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:29703.1-30249.10" +attribute \src "libresoc.v:30135.1-30693.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \fast1 @@ -43590,21 +44037,21 @@ module \alu_spr0 wire width 64 input 22 \fast1$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 6 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 9 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 8 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 14 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 27 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 26 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast1 @@ -43612,21 +44059,21 @@ module \alu_spr0 wire width 64 \pipe_fast1$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid$6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_ra @@ -43637,35 +44084,39 @@ module \alu_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_spr1_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_spr_op__fn_unit$8 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_spr_op__fn_unit$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43744,6 +44195,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_spr_op__insn_type attribute \enum_base_type "MicrOp" @@ -43820,6 +44272,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_spr_op__insn_type$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43853,35 +44306,39 @@ module \alu_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 7 \spr1_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 11 \spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 11 \spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_op__fn_unit$18 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 12 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43960,6 +44417,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 10 \spr_op__insn_type attribute \enum_base_type "MicrOp" @@ -44036,6 +44494,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_op__insn_type$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44061,19 +44520,19 @@ module \alu_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:30184.10-30187.4" + attribute \src "libresoc.v:30628.10-30631.4" cell \n$63 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:30188.10-30191.4" + attribute \src "libresoc.v:30632.10-30635.4" cell \p$62 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:30192.13-30227.4" + attribute \src "libresoc.v:30636.13-30671.4" cell \pipe$64 \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -44132,14 +44591,14 @@ module \alu_spr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:30253.1-31108.10" +attribute \src "libresoc.v:30697.1-31570.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 19 \fast1 @@ -44157,13 +44616,13 @@ module \alu_trap0 wire width 64 output 22 \msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 6 \msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 8 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 7 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 21 \nia @@ -44173,9 +44632,9 @@ module \alu_trap0 wire width 64 output 18 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 28 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 27 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_fast1 @@ -44185,17 +44644,17 @@ module \alu_trap0 wire width 64 \pipe1_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_fast2$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_ra @@ -44210,35 +44669,39 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_trap_op__cia$8 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_trap_op__fn_unit$5 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_trap_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44317,6 +44780,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -44393,6 +44857,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_trap_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44431,13 +44896,13 @@ module \alu_trap0 wire width 64 \pipe2_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe2_nia @@ -44447,9 +44912,9 @@ module \alu_trap0 wire width 64 \pipe2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe2_ra @@ -44460,35 +44925,39 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_trap_op__cia$22 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_trap_op__fn_unit$19 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_trap_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe2_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44567,6 +45036,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -44643,6 +45113,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_trap_op__insn_type$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44674,35 +45145,39 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__cia$34 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 10 \trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 10 \trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$31 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 11 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44781,6 +45256,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 9 \trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -44857,6 +45333,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44880,19 +45357,19 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$36 attribute \module_not_derived 1 - attribute \src "libresoc.v:30996.10-30999.4" + attribute \src "libresoc.v:31458.10-31461.4" cell \n$31 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:31000.10-31003.4" + attribute \src "libresoc.v:31462.10-31465.4" cell \p$30 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:31004.14-31039.4" + attribute \src "libresoc.v:31466.14-31501.4" cell \pipe1$32 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -44930,7 +45407,7 @@ module \alu_trap0 connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 end attribute \module_not_derived 1 - attribute \src "libresoc.v:31040.14-31081.4" + attribute \src "libresoc.v:31502.14-31543.4" cell \pipe2$35 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -45000,75 +45477,75 @@ module \alu_trap0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:31112.1-31170.10" +attribute \src "libresoc.v:31574.1-31632.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" attribute \generator "nMigen" module \alui_l - attribute \src "libresoc.v:31113.7-31113.20" + attribute \src "libresoc.v:31575.7-31575.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31158.3-31166.6" + attribute \src "libresoc.v:31620.3-31628.6" wire $0\q_int$next[0:0]$992 - attribute \src "libresoc.v:31156.3-31157.27" + attribute \src "libresoc.v:31618.3-31619.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31158.3-31166.6" + attribute \src "libresoc.v:31620.3-31628.6" wire $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31137.7-31137.19" + attribute \src "libresoc.v:31599.7-31599.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31148.17-31148.96" - wire $and$libresoc.v:31148$982_Y - attribute \src "libresoc.v:31153.17-31153.96" - wire $and$libresoc.v:31153$987_Y - attribute \src "libresoc.v:31150.18-31150.94" - wire $not$libresoc.v:31150$984_Y - attribute \src "libresoc.v:31152.17-31152.93" - wire $not$libresoc.v:31152$986_Y - attribute \src "libresoc.v:31155.17-31155.93" - wire $not$libresoc.v:31155$989_Y - attribute \src "libresoc.v:31149.18-31149.99" - wire $or$libresoc.v:31149$983_Y - attribute \src "libresoc.v:31151.18-31151.100" - wire $or$libresoc.v:31151$985_Y - attribute \src "libresoc.v:31154.17-31154.98" - wire $or$libresoc.v:31154$988_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:31610.17-31610.96" + wire $and$libresoc.v:31610$982_Y + attribute \src "libresoc.v:31615.17-31615.96" + wire $and$libresoc.v:31615$987_Y + attribute \src "libresoc.v:31612.18-31612.94" + wire $not$libresoc.v:31612$984_Y + attribute \src "libresoc.v:31614.17-31614.93" + wire $not$libresoc.v:31614$986_Y + attribute \src "libresoc.v:31617.17-31617.93" + wire $not$libresoc.v:31617$989_Y + attribute \src "libresoc.v:31611.18-31611.99" + wire $or$libresoc.v:31611$983_Y + attribute \src "libresoc.v:31613.18-31613.100" + wire $or$libresoc.v:31613$985_Y + attribute \src "libresoc.v:31616.17-31616.98" + wire $or$libresoc.v:31616$988_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31113.7-31113.15" + attribute \src "libresoc.v:31575.7-31575.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31148$982 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31610$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45076,10 +45553,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31148$982_Y + connect \Y $and$libresoc.v:31610$982_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31153$987 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31615$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45087,34 +45564,34 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31153$987_Y + connect \Y $and$libresoc.v:31615$987_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31150$984 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31612$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31150$984_Y + connect \Y $not$libresoc.v:31612$984_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31152$986 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31614$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31152$986_Y + connect \Y $not$libresoc.v:31614$986_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31155$989 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31617$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31155$989_Y + connect \Y $not$libresoc.v:31617$989_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31149$983 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31611$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45122,10 +45599,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31149$983_Y + connect \Y $or$libresoc.v:31611$983_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31151$985 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31613$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45133,10 +45610,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31151$985_Y + connect \Y $or$libresoc.v:31613$985_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31154$988 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31616$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45144,39 +45621,39 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31154$988_Y + connect \Y $or$libresoc.v:31616$988_Y end - attribute \src "libresoc.v:31113.7-31113.20" - process $proc$libresoc.v:31113$994 + attribute \src "libresoc.v:31575.7-31575.20" + process $proc$libresoc.v:31575$994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31137.7-31137.19" - process $proc$libresoc.v:31137$995 + attribute \src "libresoc.v:31599.7-31599.19" + process $proc$libresoc.v:31599$995 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31156.3-31157.27" - process $proc$libresoc.v:31156$990 + attribute \src "libresoc.v:31618.3-31619.27" + process $proc$libresoc.v:31618$990 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31158.3-31166.6" - process $proc$libresoc.v:31158$991 + attribute \src "libresoc.v:31620.3-31628.6" + process $proc$libresoc.v:31620$991 assign { } { } assign { } { } assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31159.5-31159.29" + attribute \src "libresoc.v:31621.5-31621.29" switch \initial - attribute \src "libresoc.v:31159.9-31159.17" + attribute \src "libresoc.v:31621.9-31621.17" case 1'1 case end @@ -45192,87 +45669,87 @@ module \alui_l sync always update \q_int$next $0\q_int$next[0:0]$992 end - connect \$9 $and$libresoc.v:31148$982_Y - connect \$11 $or$libresoc.v:31149$983_Y - connect \$13 $not$libresoc.v:31150$984_Y - connect \$15 $or$libresoc.v:31151$985_Y - connect \$1 $not$libresoc.v:31152$986_Y - connect \$3 $and$libresoc.v:31153$987_Y - connect \$5 $or$libresoc.v:31154$988_Y - connect \$7 $not$libresoc.v:31155$989_Y + connect \$9 $and$libresoc.v:31610$982_Y + connect \$11 $or$libresoc.v:31611$983_Y + connect \$13 $not$libresoc.v:31612$984_Y + connect \$15 $or$libresoc.v:31613$985_Y + connect \$1 $not$libresoc.v:31614$986_Y + connect \$3 $and$libresoc.v:31615$987_Y + connect \$5 $or$libresoc.v:31616$988_Y + connect \$7 $not$libresoc.v:31617$989_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31174.1-31232.10" +attribute \src "libresoc.v:31636.1-31694.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" attribute \generator "nMigen" module \alui_l$106 - attribute \src "libresoc.v:31175.7-31175.20" + attribute \src "libresoc.v:31637.7-31637.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31220.3-31228.6" + attribute \src "libresoc.v:31682.3-31690.6" wire $0\q_int$next[0:0]$1006 - attribute \src "libresoc.v:31218.3-31219.27" + attribute \src "libresoc.v:31680.3-31681.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31220.3-31228.6" + attribute \src "libresoc.v:31682.3-31690.6" wire $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31199.7-31199.19" + attribute \src "libresoc.v:31661.7-31661.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31210.17-31210.96" - wire $and$libresoc.v:31210$996_Y - attribute \src "libresoc.v:31215.17-31215.96" - wire $and$libresoc.v:31215$1001_Y - attribute \src "libresoc.v:31212.18-31212.94" - wire $not$libresoc.v:31212$998_Y - attribute \src "libresoc.v:31214.17-31214.93" - wire $not$libresoc.v:31214$1000_Y - attribute \src "libresoc.v:31217.17-31217.93" - wire $not$libresoc.v:31217$1003_Y - attribute \src "libresoc.v:31211.18-31211.99" - wire $or$libresoc.v:31211$997_Y - attribute \src "libresoc.v:31213.18-31213.100" - wire $or$libresoc.v:31213$999_Y - attribute \src "libresoc.v:31216.17-31216.98" - wire $or$libresoc.v:31216$1002_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:31672.17-31672.96" + wire $and$libresoc.v:31672$996_Y + attribute \src "libresoc.v:31677.17-31677.96" + wire $and$libresoc.v:31677$1001_Y + attribute \src "libresoc.v:31674.18-31674.94" + wire $not$libresoc.v:31674$998_Y + attribute \src "libresoc.v:31676.17-31676.93" + wire $not$libresoc.v:31676$1000_Y + attribute \src "libresoc.v:31679.17-31679.93" + wire $not$libresoc.v:31679$1003_Y + attribute \src "libresoc.v:31673.18-31673.99" + wire $or$libresoc.v:31673$997_Y + attribute \src "libresoc.v:31675.18-31675.100" + wire $or$libresoc.v:31675$999_Y + attribute \src "libresoc.v:31678.17-31678.98" + wire $or$libresoc.v:31678$1002_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31175.7-31175.15" + attribute \src "libresoc.v:31637.7-31637.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31210$996 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31672$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45280,10 +45757,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31210$996_Y + connect \Y $and$libresoc.v:31672$996_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31215$1001 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31677$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45291,34 +45768,34 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31215$1001_Y + connect \Y $and$libresoc.v:31677$1001_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31212$998 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31674$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31212$998_Y + connect \Y $not$libresoc.v:31674$998_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31214$1000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31676$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31214$1000_Y + connect \Y $not$libresoc.v:31676$1000_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31217$1003 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31679$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31217$1003_Y + connect \Y $not$libresoc.v:31679$1003_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31211$997 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31673$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45326,10 +45803,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31211$997_Y + connect \Y $or$libresoc.v:31673$997_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31213$999 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31675$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45337,10 +45814,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31213$999_Y + connect \Y $or$libresoc.v:31675$999_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31216$1002 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31678$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45348,39 +45825,39 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31216$1002_Y + connect \Y $or$libresoc.v:31678$1002_Y end - attribute \src "libresoc.v:31175.7-31175.20" - process $proc$libresoc.v:31175$1008 + attribute \src "libresoc.v:31637.7-31637.20" + process $proc$libresoc.v:31637$1008 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31199.7-31199.19" - process $proc$libresoc.v:31199$1009 + attribute \src "libresoc.v:31661.7-31661.19" + process $proc$libresoc.v:31661$1009 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31218.3-31219.27" - process $proc$libresoc.v:31218$1004 + attribute \src "libresoc.v:31680.3-31681.27" + process $proc$libresoc.v:31680$1004 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31220.3-31228.6" - process $proc$libresoc.v:31220$1005 + attribute \src "libresoc.v:31682.3-31690.6" + process $proc$libresoc.v:31682$1005 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31221.5-31221.29" + attribute \src "libresoc.v:31683.5-31683.29" switch \initial - attribute \src "libresoc.v:31221.9-31221.17" + attribute \src "libresoc.v:31683.9-31683.17" case 1'1 case end @@ -45396,87 +45873,87 @@ module \alui_l$106 sync always update \q_int$next $0\q_int$next[0:0]$1006 end - connect \$9 $and$libresoc.v:31210$996_Y - connect \$11 $or$libresoc.v:31211$997_Y - connect \$13 $not$libresoc.v:31212$998_Y - connect \$15 $or$libresoc.v:31213$999_Y - connect \$1 $not$libresoc.v:31214$1000_Y - connect \$3 $and$libresoc.v:31215$1001_Y - connect \$5 $or$libresoc.v:31216$1002_Y - connect \$7 $not$libresoc.v:31217$1003_Y + connect \$9 $and$libresoc.v:31672$996_Y + connect \$11 $or$libresoc.v:31673$997_Y + connect \$13 $not$libresoc.v:31674$998_Y + connect \$15 $or$libresoc.v:31675$999_Y + connect \$1 $not$libresoc.v:31676$1000_Y + connect \$3 $and$libresoc.v:31677$1001_Y + connect \$5 $or$libresoc.v:31678$1002_Y + connect \$7 $not$libresoc.v:31679$1003_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31236.1-31294.10" +attribute \src "libresoc.v:31698.1-31756.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" attribute \generator "nMigen" module \alui_l$124 - attribute \src "libresoc.v:31237.7-31237.20" + attribute \src "libresoc.v:31699.7-31699.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31282.3-31290.6" + attribute \src "libresoc.v:31744.3-31752.6" wire $0\q_int$next[0:0]$1020 - attribute \src "libresoc.v:31280.3-31281.27" + attribute \src "libresoc.v:31742.3-31743.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31282.3-31290.6" + attribute \src "libresoc.v:31744.3-31752.6" wire $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31261.7-31261.19" + attribute \src "libresoc.v:31723.7-31723.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31272.17-31272.96" - wire $and$libresoc.v:31272$1010_Y - attribute \src "libresoc.v:31277.17-31277.96" - wire $and$libresoc.v:31277$1015_Y - attribute \src "libresoc.v:31274.18-31274.94" - wire $not$libresoc.v:31274$1012_Y - attribute \src "libresoc.v:31276.17-31276.93" - wire $not$libresoc.v:31276$1014_Y - attribute \src "libresoc.v:31279.17-31279.93" - wire $not$libresoc.v:31279$1017_Y - attribute \src "libresoc.v:31273.18-31273.99" - wire $or$libresoc.v:31273$1011_Y - attribute \src "libresoc.v:31275.18-31275.100" - wire $or$libresoc.v:31275$1013_Y - attribute \src "libresoc.v:31278.17-31278.98" - wire $or$libresoc.v:31278$1016_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:31734.17-31734.96" + wire $and$libresoc.v:31734$1010_Y + attribute \src "libresoc.v:31739.17-31739.96" + wire $and$libresoc.v:31739$1015_Y + attribute \src "libresoc.v:31736.18-31736.94" + wire $not$libresoc.v:31736$1012_Y + attribute \src "libresoc.v:31738.17-31738.93" + wire $not$libresoc.v:31738$1014_Y + attribute \src "libresoc.v:31741.17-31741.93" + wire $not$libresoc.v:31741$1017_Y + attribute \src "libresoc.v:31735.18-31735.99" + wire $or$libresoc.v:31735$1011_Y + attribute \src "libresoc.v:31737.18-31737.100" + wire $or$libresoc.v:31737$1013_Y + attribute \src "libresoc.v:31740.17-31740.98" + wire $or$libresoc.v:31740$1016_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31237.7-31237.15" + attribute \src "libresoc.v:31699.7-31699.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31272$1010 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31734$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45484,10 +45961,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31272$1010_Y + connect \Y $and$libresoc.v:31734$1010_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31277$1015 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31739$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45495,34 +45972,34 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31277$1015_Y + connect \Y $and$libresoc.v:31739$1015_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31274$1012 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31736$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31274$1012_Y + connect \Y $not$libresoc.v:31736$1012_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31276$1014 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31738$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31276$1014_Y + connect \Y $not$libresoc.v:31738$1014_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31279$1017 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31741$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31279$1017_Y + connect \Y $not$libresoc.v:31741$1017_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31273$1011 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31735$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45530,10 +46007,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31273$1011_Y + connect \Y $or$libresoc.v:31735$1011_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31275$1013 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31737$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45541,10 +46018,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31275$1013_Y + connect \Y $or$libresoc.v:31737$1013_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31278$1016 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31740$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45552,39 +46029,39 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31278$1016_Y + connect \Y $or$libresoc.v:31740$1016_Y end - attribute \src "libresoc.v:31237.7-31237.20" - process $proc$libresoc.v:31237$1022 + attribute \src "libresoc.v:31699.7-31699.20" + process $proc$libresoc.v:31699$1022 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31261.7-31261.19" - process $proc$libresoc.v:31261$1023 + attribute \src "libresoc.v:31723.7-31723.19" + process $proc$libresoc.v:31723$1023 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31280.3-31281.27" - process $proc$libresoc.v:31280$1018 + attribute \src "libresoc.v:31742.3-31743.27" + process $proc$libresoc.v:31742$1018 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31282.3-31290.6" - process $proc$libresoc.v:31282$1019 + attribute \src "libresoc.v:31744.3-31752.6" + process $proc$libresoc.v:31744$1019 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31283.5-31283.29" + attribute \src "libresoc.v:31745.5-31745.29" switch \initial - attribute \src "libresoc.v:31283.9-31283.17" + attribute \src "libresoc.v:31745.9-31745.17" case 1'1 case end @@ -45600,87 +46077,87 @@ module \alui_l$124 sync always update \q_int$next $0\q_int$next[0:0]$1020 end - connect \$9 $and$libresoc.v:31272$1010_Y - connect \$11 $or$libresoc.v:31273$1011_Y - connect \$13 $not$libresoc.v:31274$1012_Y - connect \$15 $or$libresoc.v:31275$1013_Y - connect \$1 $not$libresoc.v:31276$1014_Y - connect \$3 $and$libresoc.v:31277$1015_Y - connect \$5 $or$libresoc.v:31278$1016_Y - connect \$7 $not$libresoc.v:31279$1017_Y + connect \$9 $and$libresoc.v:31734$1010_Y + connect \$11 $or$libresoc.v:31735$1011_Y + connect \$13 $not$libresoc.v:31736$1012_Y + connect \$15 $or$libresoc.v:31737$1013_Y + connect \$1 $not$libresoc.v:31738$1014_Y + connect \$3 $and$libresoc.v:31739$1015_Y + connect \$5 $or$libresoc.v:31740$1016_Y + connect \$7 $not$libresoc.v:31741$1017_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31298.1-31356.10" +attribute \src "libresoc.v:31760.1-31818.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" attribute \generator "nMigen" module \alui_l$15 - attribute \src "libresoc.v:31299.7-31299.20" + attribute \src "libresoc.v:31761.7-31761.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31344.3-31352.6" + attribute \src "libresoc.v:31806.3-31814.6" wire $0\q_int$next[0:0]$1034 - attribute \src "libresoc.v:31342.3-31343.27" + attribute \src "libresoc.v:31804.3-31805.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31344.3-31352.6" + attribute \src "libresoc.v:31806.3-31814.6" wire $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31323.7-31323.19" + attribute \src "libresoc.v:31785.7-31785.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31334.17-31334.96" - wire $and$libresoc.v:31334$1024_Y - attribute \src "libresoc.v:31339.17-31339.96" - wire $and$libresoc.v:31339$1029_Y - attribute \src "libresoc.v:31336.18-31336.94" - wire $not$libresoc.v:31336$1026_Y - attribute \src "libresoc.v:31338.17-31338.93" - wire $not$libresoc.v:31338$1028_Y - attribute \src "libresoc.v:31341.17-31341.93" - wire $not$libresoc.v:31341$1031_Y - attribute \src "libresoc.v:31335.18-31335.99" - wire $or$libresoc.v:31335$1025_Y - attribute \src "libresoc.v:31337.18-31337.100" - wire $or$libresoc.v:31337$1027_Y - attribute \src "libresoc.v:31340.17-31340.98" - wire $or$libresoc.v:31340$1030_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:31796.17-31796.96" + wire $and$libresoc.v:31796$1024_Y + attribute \src "libresoc.v:31801.17-31801.96" + wire $and$libresoc.v:31801$1029_Y + attribute \src "libresoc.v:31798.18-31798.94" + wire $not$libresoc.v:31798$1026_Y + attribute \src "libresoc.v:31800.17-31800.93" + wire $not$libresoc.v:31800$1028_Y + attribute \src "libresoc.v:31803.17-31803.93" + wire $not$libresoc.v:31803$1031_Y + attribute \src "libresoc.v:31797.18-31797.99" + wire $or$libresoc.v:31797$1025_Y + attribute \src "libresoc.v:31799.18-31799.100" + wire $or$libresoc.v:31799$1027_Y + attribute \src "libresoc.v:31802.17-31802.98" + wire $or$libresoc.v:31802$1030_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31299.7-31299.15" + attribute \src "libresoc.v:31761.7-31761.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31334$1024 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31796$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45688,10 +46165,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31334$1024_Y + connect \Y $and$libresoc.v:31796$1024_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31339$1029 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31801$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45699,34 +46176,34 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31339$1029_Y + connect \Y $and$libresoc.v:31801$1029_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31336$1026 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31798$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31336$1026_Y + connect \Y $not$libresoc.v:31798$1026_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31338$1028 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31800$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31338$1028_Y + connect \Y $not$libresoc.v:31800$1028_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31341$1031 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31803$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31341$1031_Y + connect \Y $not$libresoc.v:31803$1031_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31335$1025 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31797$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45734,10 +46211,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31335$1025_Y + connect \Y $or$libresoc.v:31797$1025_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31337$1027 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31799$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45745,10 +46222,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31337$1027_Y + connect \Y $or$libresoc.v:31799$1027_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31340$1030 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31802$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45756,39 +46233,39 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31340$1030_Y + connect \Y $or$libresoc.v:31802$1030_Y end - attribute \src "libresoc.v:31299.7-31299.20" - process $proc$libresoc.v:31299$1036 + attribute \src "libresoc.v:31761.7-31761.20" + process $proc$libresoc.v:31761$1036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31323.7-31323.19" - process $proc$libresoc.v:31323$1037 + attribute \src "libresoc.v:31785.7-31785.19" + process $proc$libresoc.v:31785$1037 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31342.3-31343.27" - process $proc$libresoc.v:31342$1032 + attribute \src "libresoc.v:31804.3-31805.27" + process $proc$libresoc.v:31804$1032 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31344.3-31352.6" - process $proc$libresoc.v:31344$1033 + attribute \src "libresoc.v:31806.3-31814.6" + process $proc$libresoc.v:31806$1033 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31345.5-31345.29" + attribute \src "libresoc.v:31807.5-31807.29" switch \initial - attribute \src "libresoc.v:31345.9-31345.17" + attribute \src "libresoc.v:31807.9-31807.17" case 1'1 case end @@ -45804,87 +46281,87 @@ module \alui_l$15 sync always update \q_int$next $0\q_int$next[0:0]$1034 end - connect \$9 $and$libresoc.v:31334$1024_Y - connect \$11 $or$libresoc.v:31335$1025_Y - connect \$13 $not$libresoc.v:31336$1026_Y - connect \$15 $or$libresoc.v:31337$1027_Y - connect \$1 $not$libresoc.v:31338$1028_Y - connect \$3 $and$libresoc.v:31339$1029_Y - connect \$5 $or$libresoc.v:31340$1030_Y - connect \$7 $not$libresoc.v:31341$1031_Y + connect \$9 $and$libresoc.v:31796$1024_Y + connect \$11 $or$libresoc.v:31797$1025_Y + connect \$13 $not$libresoc.v:31798$1026_Y + connect \$15 $or$libresoc.v:31799$1027_Y + connect \$1 $not$libresoc.v:31800$1028_Y + connect \$3 $and$libresoc.v:31801$1029_Y + connect \$5 $or$libresoc.v:31802$1030_Y + connect \$7 $not$libresoc.v:31803$1031_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31360.1-31418.10" +attribute \src "libresoc.v:31822.1-31880.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" attribute \generator "nMigen" module \alui_l$28 - attribute \src "libresoc.v:31361.7-31361.20" + attribute \src "libresoc.v:31823.7-31823.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31406.3-31414.6" + attribute \src "libresoc.v:31868.3-31876.6" wire $0\q_int$next[0:0]$1048 - attribute \src "libresoc.v:31404.3-31405.27" + attribute \src "libresoc.v:31866.3-31867.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31406.3-31414.6" + attribute \src "libresoc.v:31868.3-31876.6" wire $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31385.7-31385.19" + attribute \src "libresoc.v:31847.7-31847.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31396.17-31396.96" - wire $and$libresoc.v:31396$1038_Y - attribute \src "libresoc.v:31401.17-31401.96" - wire $and$libresoc.v:31401$1043_Y - attribute \src "libresoc.v:31398.18-31398.94" - wire $not$libresoc.v:31398$1040_Y - attribute \src "libresoc.v:31400.17-31400.93" - wire $not$libresoc.v:31400$1042_Y - attribute \src "libresoc.v:31403.17-31403.93" - wire $not$libresoc.v:31403$1045_Y - attribute \src "libresoc.v:31397.18-31397.99" - wire $or$libresoc.v:31397$1039_Y - attribute \src "libresoc.v:31399.18-31399.100" - wire $or$libresoc.v:31399$1041_Y - attribute \src "libresoc.v:31402.17-31402.98" - wire $or$libresoc.v:31402$1044_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:31858.17-31858.96" + wire $and$libresoc.v:31858$1038_Y + attribute \src "libresoc.v:31863.17-31863.96" + wire $and$libresoc.v:31863$1043_Y + attribute \src "libresoc.v:31860.18-31860.94" + wire $not$libresoc.v:31860$1040_Y + attribute \src "libresoc.v:31862.17-31862.93" + wire $not$libresoc.v:31862$1042_Y + attribute \src "libresoc.v:31865.17-31865.93" + wire $not$libresoc.v:31865$1045_Y + attribute \src "libresoc.v:31859.18-31859.99" + wire $or$libresoc.v:31859$1039_Y + attribute \src "libresoc.v:31861.18-31861.100" + wire $or$libresoc.v:31861$1041_Y + attribute \src "libresoc.v:31864.17-31864.98" + wire $or$libresoc.v:31864$1044_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31361.7-31361.15" + attribute \src "libresoc.v:31823.7-31823.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31396$1038 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31858$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45892,10 +46369,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31396$1038_Y + connect \Y $and$libresoc.v:31858$1038_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31401$1043 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31863$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45903,34 +46380,34 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31401$1043_Y + connect \Y $and$libresoc.v:31863$1043_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31398$1040 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31860$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31398$1040_Y + connect \Y $not$libresoc.v:31860$1040_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31400$1042 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31862$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31400$1042_Y + connect \Y $not$libresoc.v:31862$1042_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31403$1045 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31865$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31403$1045_Y + connect \Y $not$libresoc.v:31865$1045_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31397$1039 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31859$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45938,10 +46415,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31397$1039_Y + connect \Y $or$libresoc.v:31859$1039_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31399$1041 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31861$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45949,10 +46426,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31399$1041_Y + connect \Y $or$libresoc.v:31861$1041_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31402$1044 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31864$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45960,39 +46437,39 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31402$1044_Y + connect \Y $or$libresoc.v:31864$1044_Y end - attribute \src "libresoc.v:31361.7-31361.20" - process $proc$libresoc.v:31361$1050 + attribute \src "libresoc.v:31823.7-31823.20" + process $proc$libresoc.v:31823$1050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31385.7-31385.19" - process $proc$libresoc.v:31385$1051 + attribute \src "libresoc.v:31847.7-31847.19" + process $proc$libresoc.v:31847$1051 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31404.3-31405.27" - process $proc$libresoc.v:31404$1046 + attribute \src "libresoc.v:31866.3-31867.27" + process $proc$libresoc.v:31866$1046 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31406.3-31414.6" - process $proc$libresoc.v:31406$1047 + attribute \src "libresoc.v:31868.3-31876.6" + process $proc$libresoc.v:31868$1047 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31407.5-31407.29" + attribute \src "libresoc.v:31869.5-31869.29" switch \initial - attribute \src "libresoc.v:31407.9-31407.17" + attribute \src "libresoc.v:31869.9-31869.17" case 1'1 case end @@ -46008,87 +46485,87 @@ module \alui_l$28 sync always update \q_int$next $0\q_int$next[0:0]$1048 end - connect \$9 $and$libresoc.v:31396$1038_Y - connect \$11 $or$libresoc.v:31397$1039_Y - connect \$13 $not$libresoc.v:31398$1040_Y - connect \$15 $or$libresoc.v:31399$1041_Y - connect \$1 $not$libresoc.v:31400$1042_Y - connect \$3 $and$libresoc.v:31401$1043_Y - connect \$5 $or$libresoc.v:31402$1044_Y - connect \$7 $not$libresoc.v:31403$1045_Y + connect \$9 $and$libresoc.v:31858$1038_Y + connect \$11 $or$libresoc.v:31859$1039_Y + connect \$13 $not$libresoc.v:31860$1040_Y + connect \$15 $or$libresoc.v:31861$1041_Y + connect \$1 $not$libresoc.v:31862$1042_Y + connect \$3 $and$libresoc.v:31863$1043_Y + connect \$5 $or$libresoc.v:31864$1044_Y + connect \$7 $not$libresoc.v:31865$1045_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31422.1-31480.10" +attribute \src "libresoc.v:31884.1-31942.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" attribute \generator "nMigen" module \alui_l$44 - attribute \src "libresoc.v:31423.7-31423.20" + attribute \src "libresoc.v:31885.7-31885.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31468.3-31476.6" + attribute \src "libresoc.v:31930.3-31938.6" wire $0\q_int$next[0:0]$1062 - attribute \src "libresoc.v:31466.3-31467.27" + attribute \src "libresoc.v:31928.3-31929.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31468.3-31476.6" + attribute \src "libresoc.v:31930.3-31938.6" wire $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31447.7-31447.19" + attribute \src "libresoc.v:31909.7-31909.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31458.17-31458.96" - wire $and$libresoc.v:31458$1052_Y - attribute \src "libresoc.v:31463.17-31463.96" - wire $and$libresoc.v:31463$1057_Y - attribute \src "libresoc.v:31460.18-31460.94" - wire $not$libresoc.v:31460$1054_Y - attribute \src "libresoc.v:31462.17-31462.93" - wire $not$libresoc.v:31462$1056_Y - attribute \src "libresoc.v:31465.17-31465.93" - wire $not$libresoc.v:31465$1059_Y - attribute \src "libresoc.v:31459.18-31459.99" - wire $or$libresoc.v:31459$1053_Y - attribute \src "libresoc.v:31461.18-31461.100" - wire $or$libresoc.v:31461$1055_Y - attribute \src "libresoc.v:31464.17-31464.98" - wire $or$libresoc.v:31464$1058_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:31920.17-31920.96" + wire $and$libresoc.v:31920$1052_Y + attribute \src "libresoc.v:31925.17-31925.96" + wire $and$libresoc.v:31925$1057_Y + attribute \src "libresoc.v:31922.18-31922.94" + wire $not$libresoc.v:31922$1054_Y + attribute \src "libresoc.v:31924.17-31924.93" + wire $not$libresoc.v:31924$1056_Y + attribute \src "libresoc.v:31927.17-31927.93" + wire $not$libresoc.v:31927$1059_Y + attribute \src "libresoc.v:31921.18-31921.99" + wire $or$libresoc.v:31921$1053_Y + attribute \src "libresoc.v:31923.18-31923.100" + wire $or$libresoc.v:31923$1055_Y + attribute \src "libresoc.v:31926.17-31926.98" + wire $or$libresoc.v:31926$1058_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31423.7-31423.15" + attribute \src "libresoc.v:31885.7-31885.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31458$1052 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31920$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46096,10 +46573,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31458$1052_Y + connect \Y $and$libresoc.v:31920$1052_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31463$1057 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31925$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46107,34 +46584,34 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31463$1057_Y + connect \Y $and$libresoc.v:31925$1057_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31460$1054 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31922$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31460$1054_Y + connect \Y $not$libresoc.v:31922$1054_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31462$1056 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31924$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31462$1056_Y + connect \Y $not$libresoc.v:31924$1056_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31465$1059 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31927$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31465$1059_Y + connect \Y $not$libresoc.v:31927$1059_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31459$1053 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31921$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46142,10 +46619,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31459$1053_Y + connect \Y $or$libresoc.v:31921$1053_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31461$1055 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31923$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46153,10 +46630,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31461$1055_Y + connect \Y $or$libresoc.v:31923$1055_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31464$1058 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31926$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46164,39 +46641,39 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31464$1058_Y + connect \Y $or$libresoc.v:31926$1058_Y end - attribute \src "libresoc.v:31423.7-31423.20" - process $proc$libresoc.v:31423$1064 + attribute \src "libresoc.v:31885.7-31885.20" + process $proc$libresoc.v:31885$1064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31447.7-31447.19" - process $proc$libresoc.v:31447$1065 + attribute \src "libresoc.v:31909.7-31909.19" + process $proc$libresoc.v:31909$1065 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31466.3-31467.27" - process $proc$libresoc.v:31466$1060 + attribute \src "libresoc.v:31928.3-31929.27" + process $proc$libresoc.v:31928$1060 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31468.3-31476.6" - process $proc$libresoc.v:31468$1061 + attribute \src "libresoc.v:31930.3-31938.6" + process $proc$libresoc.v:31930$1061 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31469.5-31469.29" + attribute \src "libresoc.v:31931.5-31931.29" switch \initial - attribute \src "libresoc.v:31469.9-31469.17" + attribute \src "libresoc.v:31931.9-31931.17" case 1'1 case end @@ -46212,87 +46689,87 @@ module \alui_l$44 sync always update \q_int$next $0\q_int$next[0:0]$1062 end - connect \$9 $and$libresoc.v:31458$1052_Y - connect \$11 $or$libresoc.v:31459$1053_Y - connect \$13 $not$libresoc.v:31460$1054_Y - connect \$15 $or$libresoc.v:31461$1055_Y - connect \$1 $not$libresoc.v:31462$1056_Y - connect \$3 $and$libresoc.v:31463$1057_Y - connect \$5 $or$libresoc.v:31464$1058_Y - connect \$7 $not$libresoc.v:31465$1059_Y + connect \$9 $and$libresoc.v:31920$1052_Y + connect \$11 $or$libresoc.v:31921$1053_Y + connect \$13 $not$libresoc.v:31922$1054_Y + connect \$15 $or$libresoc.v:31923$1055_Y + connect \$1 $not$libresoc.v:31924$1056_Y + connect \$3 $and$libresoc.v:31925$1057_Y + connect \$5 $or$libresoc.v:31926$1058_Y + connect \$7 $not$libresoc.v:31927$1059_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31484.1-31542.10" +attribute \src "libresoc.v:31946.1-32004.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" attribute \generator "nMigen" module \alui_l$60 - attribute \src "libresoc.v:31485.7-31485.20" + attribute \src "libresoc.v:31947.7-31947.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31530.3-31538.6" + attribute \src "libresoc.v:31992.3-32000.6" wire $0\q_int$next[0:0]$1076 - attribute \src "libresoc.v:31528.3-31529.27" + attribute \src "libresoc.v:31990.3-31991.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31530.3-31538.6" + attribute \src "libresoc.v:31992.3-32000.6" wire $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31509.7-31509.19" + attribute \src "libresoc.v:31971.7-31971.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31520.17-31520.96" - wire $and$libresoc.v:31520$1066_Y - attribute \src "libresoc.v:31525.17-31525.96" - wire $and$libresoc.v:31525$1071_Y - attribute \src "libresoc.v:31522.18-31522.94" - wire $not$libresoc.v:31522$1068_Y - attribute \src "libresoc.v:31524.17-31524.93" - wire $not$libresoc.v:31524$1070_Y - attribute \src "libresoc.v:31527.17-31527.93" - wire $not$libresoc.v:31527$1073_Y - attribute \src "libresoc.v:31521.18-31521.99" - wire $or$libresoc.v:31521$1067_Y - attribute \src "libresoc.v:31523.18-31523.100" - wire $or$libresoc.v:31523$1069_Y - attribute \src "libresoc.v:31526.17-31526.98" - wire $or$libresoc.v:31526$1072_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:31982.17-31982.96" + wire $and$libresoc.v:31982$1066_Y + attribute \src "libresoc.v:31987.17-31987.96" + wire $and$libresoc.v:31987$1071_Y + attribute \src "libresoc.v:31984.18-31984.94" + wire $not$libresoc.v:31984$1068_Y + attribute \src "libresoc.v:31986.17-31986.93" + wire $not$libresoc.v:31986$1070_Y + attribute \src "libresoc.v:31989.17-31989.93" + wire $not$libresoc.v:31989$1073_Y + attribute \src "libresoc.v:31983.18-31983.99" + wire $or$libresoc.v:31983$1067_Y + attribute \src "libresoc.v:31985.18-31985.100" + wire $or$libresoc.v:31985$1069_Y + attribute \src "libresoc.v:31988.17-31988.98" + wire $or$libresoc.v:31988$1072_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31485.7-31485.15" + attribute \src "libresoc.v:31947.7-31947.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31520$1066 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31982$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46300,10 +46777,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31520$1066_Y + connect \Y $and$libresoc.v:31982$1066_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31525$1071 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31987$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46311,34 +46788,34 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31525$1071_Y + connect \Y $and$libresoc.v:31987$1071_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31522$1068 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31984$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31522$1068_Y + connect \Y $not$libresoc.v:31984$1068_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31524$1070 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31986$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31524$1070_Y + connect \Y $not$libresoc.v:31986$1070_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31527$1073 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31989$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31527$1073_Y + connect \Y $not$libresoc.v:31989$1073_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31521$1067 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31983$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46346,10 +46823,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31521$1067_Y + connect \Y $or$libresoc.v:31983$1067_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31523$1069 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31985$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46357,10 +46834,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31523$1069_Y + connect \Y $or$libresoc.v:31985$1069_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31526$1072 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31988$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46368,39 +46845,39 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31526$1072_Y + connect \Y $or$libresoc.v:31988$1072_Y end - attribute \src "libresoc.v:31485.7-31485.20" - process $proc$libresoc.v:31485$1078 + attribute \src "libresoc.v:31947.7-31947.20" + process $proc$libresoc.v:31947$1078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31509.7-31509.19" - process $proc$libresoc.v:31509$1079 + attribute \src "libresoc.v:31971.7-31971.19" + process $proc$libresoc.v:31971$1079 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31528.3-31529.27" - process $proc$libresoc.v:31528$1074 + attribute \src "libresoc.v:31990.3-31991.27" + process $proc$libresoc.v:31990$1074 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31530.3-31538.6" - process $proc$libresoc.v:31530$1075 + attribute \src "libresoc.v:31992.3-32000.6" + process $proc$libresoc.v:31992$1075 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31531.5-31531.29" + attribute \src "libresoc.v:31993.5-31993.29" switch \initial - attribute \src "libresoc.v:31531.9-31531.17" + attribute \src "libresoc.v:31993.9-31993.17" case 1'1 case end @@ -46416,87 +46893,87 @@ module \alui_l$60 sync always update \q_int$next $0\q_int$next[0:0]$1076 end - connect \$9 $and$libresoc.v:31520$1066_Y - connect \$11 $or$libresoc.v:31521$1067_Y - connect \$13 $not$libresoc.v:31522$1068_Y - connect \$15 $or$libresoc.v:31523$1069_Y - connect \$1 $not$libresoc.v:31524$1070_Y - connect \$3 $and$libresoc.v:31525$1071_Y - connect \$5 $or$libresoc.v:31526$1072_Y - connect \$7 $not$libresoc.v:31527$1073_Y + connect \$9 $and$libresoc.v:31982$1066_Y + connect \$11 $or$libresoc.v:31983$1067_Y + connect \$13 $not$libresoc.v:31984$1068_Y + connect \$15 $or$libresoc.v:31985$1069_Y + connect \$1 $not$libresoc.v:31986$1070_Y + connect \$3 $and$libresoc.v:31987$1071_Y + connect \$5 $or$libresoc.v:31988$1072_Y + connect \$7 $not$libresoc.v:31989$1073_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31546.1-31604.10" +attribute \src "libresoc.v:32008.1-32066.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" attribute \generator "nMigen" module \alui_l$72 - attribute \src "libresoc.v:31547.7-31547.20" + attribute \src "libresoc.v:32009.7-32009.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31592.3-31600.6" + attribute \src "libresoc.v:32054.3-32062.6" wire $0\q_int$next[0:0]$1090 - attribute \src "libresoc.v:31590.3-31591.27" + attribute \src "libresoc.v:32052.3-32053.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31592.3-31600.6" + attribute \src "libresoc.v:32054.3-32062.6" wire $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:31571.7-31571.19" + attribute \src "libresoc.v:32033.7-32033.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31582.17-31582.96" - wire $and$libresoc.v:31582$1080_Y - attribute \src "libresoc.v:31587.17-31587.96" - wire $and$libresoc.v:31587$1085_Y - attribute \src "libresoc.v:31584.18-31584.94" - wire $not$libresoc.v:31584$1082_Y - attribute \src "libresoc.v:31586.17-31586.93" - wire $not$libresoc.v:31586$1084_Y - attribute \src "libresoc.v:31589.17-31589.93" - wire $not$libresoc.v:31589$1087_Y - attribute \src "libresoc.v:31583.18-31583.99" - wire $or$libresoc.v:31583$1081_Y - attribute \src "libresoc.v:31585.18-31585.100" - wire $or$libresoc.v:31585$1083_Y - attribute \src "libresoc.v:31588.17-31588.98" - wire $or$libresoc.v:31588$1086_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:32044.17-32044.96" + wire $and$libresoc.v:32044$1080_Y + attribute \src "libresoc.v:32049.17-32049.96" + wire $and$libresoc.v:32049$1085_Y + attribute \src "libresoc.v:32046.18-32046.94" + wire $not$libresoc.v:32046$1082_Y + attribute \src "libresoc.v:32048.17-32048.93" + wire $not$libresoc.v:32048$1084_Y + attribute \src "libresoc.v:32051.17-32051.93" + wire $not$libresoc.v:32051$1087_Y + attribute \src "libresoc.v:32045.18-32045.99" + wire $or$libresoc.v:32045$1081_Y + attribute \src "libresoc.v:32047.18-32047.100" + wire $or$libresoc.v:32047$1083_Y + attribute \src "libresoc.v:32050.17-32050.98" + wire $or$libresoc.v:32050$1086_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31547.7-31547.15" + attribute \src "libresoc.v:32009.7-32009.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31582$1080 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:32044$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46504,10 +46981,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31582$1080_Y + connect \Y $and$libresoc.v:32044$1080_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31587$1085 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:32049$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46515,34 +46992,34 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31587$1085_Y + connect \Y $and$libresoc.v:32049$1085_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31584$1082 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:32046$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31584$1082_Y + connect \Y $not$libresoc.v:32046$1082_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31586$1084 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:32048$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31586$1084_Y + connect \Y $not$libresoc.v:32048$1084_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31589$1087 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:32051$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31589$1087_Y + connect \Y $not$libresoc.v:32051$1087_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31583$1081 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:32045$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46550,10 +47027,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31583$1081_Y + connect \Y $or$libresoc.v:32045$1081_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31585$1083 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:32047$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46561,10 +47038,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31585$1083_Y + connect \Y $or$libresoc.v:32047$1083_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31588$1086 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:32050$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46572,39 +47049,39 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31588$1086_Y + connect \Y $or$libresoc.v:32050$1086_Y end - attribute \src "libresoc.v:31547.7-31547.20" - process $proc$libresoc.v:31547$1092 + attribute \src "libresoc.v:32009.7-32009.20" + process $proc$libresoc.v:32009$1092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31571.7-31571.19" - process $proc$libresoc.v:31571$1093 + attribute \src "libresoc.v:32033.7-32033.19" + process $proc$libresoc.v:32033$1093 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31590.3-31591.27" - process $proc$libresoc.v:31590$1088 + attribute \src "libresoc.v:32052.3-32053.27" + process $proc$libresoc.v:32052$1088 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31592.3-31600.6" - process $proc$libresoc.v:31592$1089 + attribute \src "libresoc.v:32054.3-32062.6" + process $proc$libresoc.v:32054$1089 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:31593.5-31593.29" + attribute \src "libresoc.v:32055.5-32055.29" switch \initial - attribute \src "libresoc.v:31593.9-31593.17" + attribute \src "libresoc.v:32055.9-32055.17" case 1'1 case end @@ -46620,87 +47097,87 @@ module \alui_l$72 sync always update \q_int$next $0\q_int$next[0:0]$1090 end - connect \$9 $and$libresoc.v:31582$1080_Y - connect \$11 $or$libresoc.v:31583$1081_Y - connect \$13 $not$libresoc.v:31584$1082_Y - connect \$15 $or$libresoc.v:31585$1083_Y - connect \$1 $not$libresoc.v:31586$1084_Y - connect \$3 $and$libresoc.v:31587$1085_Y - connect \$5 $or$libresoc.v:31588$1086_Y - connect \$7 $not$libresoc.v:31589$1087_Y + connect \$9 $and$libresoc.v:32044$1080_Y + connect \$11 $or$libresoc.v:32045$1081_Y + connect \$13 $not$libresoc.v:32046$1082_Y + connect \$15 $or$libresoc.v:32047$1083_Y + connect \$1 $not$libresoc.v:32048$1084_Y + connect \$3 $and$libresoc.v:32049$1085_Y + connect \$5 $or$libresoc.v:32050$1086_Y + connect \$7 $not$libresoc.v:32051$1087_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31608.1-31666.10" +attribute \src "libresoc.v:32070.1-32128.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alui_l" attribute \generator "nMigen" module \alui_l$89 - attribute \src "libresoc.v:31609.7-31609.20" + attribute \src "libresoc.v:32071.7-32071.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31654.3-31662.6" + attribute \src "libresoc.v:32116.3-32124.6" wire $0\q_int$next[0:0]$1104 - attribute \src "libresoc.v:31652.3-31653.27" + attribute \src "libresoc.v:32114.3-32115.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31654.3-31662.6" + attribute \src "libresoc.v:32116.3-32124.6" wire $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:31633.7-31633.19" + attribute \src "libresoc.v:32095.7-32095.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31644.17-31644.96" - wire $and$libresoc.v:31644$1094_Y - attribute \src "libresoc.v:31649.17-31649.96" - wire $and$libresoc.v:31649$1099_Y - attribute \src "libresoc.v:31646.18-31646.94" - wire $not$libresoc.v:31646$1096_Y - attribute \src "libresoc.v:31648.17-31648.93" - wire $not$libresoc.v:31648$1098_Y - attribute \src "libresoc.v:31651.17-31651.93" - wire $not$libresoc.v:31651$1101_Y - attribute \src "libresoc.v:31645.18-31645.99" - wire $or$libresoc.v:31645$1095_Y - attribute \src "libresoc.v:31647.18-31647.100" - wire $or$libresoc.v:31647$1097_Y - attribute \src "libresoc.v:31650.17-31650.98" - wire $or$libresoc.v:31650$1100_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:32106.17-32106.96" + wire $and$libresoc.v:32106$1094_Y + attribute \src "libresoc.v:32111.17-32111.96" + wire $and$libresoc.v:32111$1099_Y + attribute \src "libresoc.v:32108.18-32108.94" + wire $not$libresoc.v:32108$1096_Y + attribute \src "libresoc.v:32110.17-32110.93" + wire $not$libresoc.v:32110$1098_Y + attribute \src "libresoc.v:32113.17-32113.93" + wire $not$libresoc.v:32113$1101_Y + attribute \src "libresoc.v:32107.18-32107.99" + wire $or$libresoc.v:32107$1095_Y + attribute \src "libresoc.v:32109.18-32109.100" + wire $or$libresoc.v:32109$1097_Y + attribute \src "libresoc.v:32112.17-32112.98" + wire $or$libresoc.v:32112$1100_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31609.7-31609.15" + attribute \src "libresoc.v:32071.7-32071.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31644$1094 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:32106$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46708,10 +47185,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31644$1094_Y + connect \Y $and$libresoc.v:32106$1094_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31649$1099 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:32111$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46719,34 +47196,34 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31649$1099_Y + connect \Y $and$libresoc.v:32111$1099_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31646$1096 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:32108$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31646$1096_Y + connect \Y $not$libresoc.v:32108$1096_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31648$1098 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:32110$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31648$1098_Y + connect \Y $not$libresoc.v:32110$1098_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31651$1101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:32113$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31651$1101_Y + connect \Y $not$libresoc.v:32113$1101_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31645$1095 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:32107$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46754,10 +47231,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31645$1095_Y + connect \Y $or$libresoc.v:32107$1095_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31647$1097 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:32109$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46765,10 +47242,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31647$1097_Y + connect \Y $or$libresoc.v:32109$1097_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31650$1100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:32112$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46776,39 +47253,39 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31650$1100_Y + connect \Y $or$libresoc.v:32112$1100_Y end - attribute \src "libresoc.v:31609.7-31609.20" - process $proc$libresoc.v:31609$1106 + attribute \src "libresoc.v:32071.7-32071.20" + process $proc$libresoc.v:32071$1106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31633.7-31633.19" - process $proc$libresoc.v:31633$1107 + attribute \src "libresoc.v:32095.7-32095.19" + process $proc$libresoc.v:32095$1107 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31652.3-31653.27" - process $proc$libresoc.v:31652$1102 + attribute \src "libresoc.v:32114.3-32115.27" + process $proc$libresoc.v:32114$1102 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31654.3-31662.6" - process $proc$libresoc.v:31654$1103 + attribute \src "libresoc.v:32116.3-32124.6" + process $proc$libresoc.v:32116$1103 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1104 $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:31655.5-31655.29" + attribute \src "libresoc.v:32117.5-32117.29" switch \initial - attribute \src "libresoc.v:31655.9-31655.17" + attribute \src "libresoc.v:32117.9-32117.17" case 1'1 case end @@ -46824,75 +47301,75 @@ module \alui_l$89 sync always update \q_int$next $0\q_int$next[0:0]$1104 end - connect \$9 $and$libresoc.v:31644$1094_Y - connect \$11 $or$libresoc.v:31645$1095_Y - connect \$13 $not$libresoc.v:31646$1096_Y - connect \$15 $or$libresoc.v:31647$1097_Y - connect \$1 $not$libresoc.v:31648$1098_Y - connect \$3 $and$libresoc.v:31649$1099_Y - connect \$5 $or$libresoc.v:31650$1100_Y - connect \$7 $not$libresoc.v:31651$1101_Y + connect \$9 $and$libresoc.v:32106$1094_Y + connect \$11 $or$libresoc.v:32107$1095_Y + connect \$13 $not$libresoc.v:32108$1096_Y + connect \$15 $or$libresoc.v:32109$1097_Y + connect \$1 $not$libresoc.v:32110$1098_Y + connect \$3 $and$libresoc.v:32111$1099_Y + connect \$5 $or$libresoc.v:32112$1100_Y + connect \$7 $not$libresoc.v:32113$1101_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31670.1-33014.10" +attribute \src "libresoc.v:32132.1-33476.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" attribute \generator "nMigen" module \bpermd - attribute \src "libresoc.v:31671.7-31671.20" + attribute \src "libresoc.v:32133.7-32133.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire width 64 $0\perm[63:0] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $10\perm[4:4] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $11\perm[5:5] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $12\perm[5:5] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $13\perm[6:6] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $14\perm[6:6] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $15\perm[7:7] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $16\perm[7:7] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $1\perm[0:0] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $2\perm[0:0] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $3\perm[1:1] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $4\perm[1:1] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $5\perm[2:2] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $6\perm[2:2] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $7\perm[3:3] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $8\perm[3:3] - attribute \src "libresoc.v:31848.3-32939.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $9\perm[4:4] - attribute \src "libresoc.v:31840.17-31840.104" - wire $lt$libresoc.v:31840$1108_Y - attribute \src "libresoc.v:31841.18-31841.105" - wire $lt$libresoc.v:31841$1109_Y - attribute \src "libresoc.v:31842.18-31842.105" - wire $lt$libresoc.v:31842$1110_Y - attribute \src "libresoc.v:31843.18-31843.105" - wire $lt$libresoc.v:31843$1111_Y - attribute \src "libresoc.v:31844.17-31844.104" - wire $lt$libresoc.v:31844$1112_Y - attribute \src "libresoc.v:31845.17-31845.104" - wire $lt$libresoc.v:31845$1113_Y - attribute \src "libresoc.v:31846.17-31846.104" - wire $lt$libresoc.v:31846$1114_Y - attribute \src "libresoc.v:31847.17-31847.104" - wire $lt$libresoc.v:31847$1115_Y + attribute \src "libresoc.v:32302.17-32302.104" + wire $lt$libresoc.v:32302$1108_Y + attribute \src "libresoc.v:32303.18-32303.105" + wire $lt$libresoc.v:32303$1109_Y + attribute \src "libresoc.v:32304.18-32304.105" + wire $lt$libresoc.v:32304$1110_Y + attribute \src "libresoc.v:32305.18-32305.105" + wire $lt$libresoc.v:32305$1111_Y + attribute \src "libresoc.v:32306.17-32306.104" + wire $lt$libresoc.v:32306$1112_Y + attribute \src "libresoc.v:32307.17-32307.104" + wire $lt$libresoc.v:32307$1113_Y + attribute \src "libresoc.v:32308.17-32308.104" + wire $lt$libresoc.v:32308$1114_Y + attribute \src "libresoc.v:32309.17-32309.104" + wire $lt$libresoc.v:32309$1115_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" @@ -46925,7 +47402,7 @@ module \bpermd wire width 8 \idx_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_7 - attribute \src "libresoc.v:31671.7-31671.15" + attribute \src "libresoc.v:32133.7-32133.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" wire width 64 \perm @@ -47064,7 +47541,7 @@ module \bpermd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 input 3 \rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31840$1108 + cell $lt $lt$libresoc.v:32302$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47072,10 +47549,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_4 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31840$1108_Y + connect \Y $lt$libresoc.v:32302$1108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31841$1109 + cell $lt $lt$libresoc.v:32303$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47083,10 +47560,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_5 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31841$1109_Y + connect \Y $lt$libresoc.v:32303$1109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31842$1110 + cell $lt $lt$libresoc.v:32304$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47094,10 +47571,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_6 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31842$1110_Y + connect \Y $lt$libresoc.v:32304$1110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31843$1111 + cell $lt $lt$libresoc.v:32305$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47105,10 +47582,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_7 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31843$1111_Y + connect \Y $lt$libresoc.v:32305$1111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31844$1112 + cell $lt $lt$libresoc.v:32306$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47116,10 +47593,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_0 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31844$1112_Y + connect \Y $lt$libresoc.v:32306$1112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31845$1113 + cell $lt $lt$libresoc.v:32307$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47127,10 +47604,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_1 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31845$1113_Y + connect \Y $lt$libresoc.v:32307$1113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31846$1114 + cell $lt $lt$libresoc.v:32308$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47138,10 +47615,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_2 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31846$1114_Y + connect \Y $lt$libresoc.v:32308$1114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31847$1115 + cell $lt $lt$libresoc.v:32309$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47149,18 +47626,18 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_3 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31847$1115_Y + connect \Y $lt$libresoc.v:32309$1115_Y end - attribute \src "libresoc.v:31671.7-31671.20" - process $proc$libresoc.v:31671$1117 + attribute \src "libresoc.v:32133.7-32133.20" + process $proc$libresoc.v:32133$1117 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31848.3-32939.6" - process $proc$libresoc.v:31848$1116 + attribute \src "libresoc.v:32310.3-33401.6" + process $proc$libresoc.v:32310$1116 assign { } { } assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 assign $0\perm[63:0] [0] $1\perm[0:0] @@ -47171,9 +47648,9 @@ module \bpermd assign $0\perm[63:0] [5] $11\perm[5:5] assign $0\perm[63:0] [6] $13\perm[6:6] assign $0\perm[63:0] [7] $15\perm[7:7] - attribute \src "libresoc.v:31849.5-31849.29" + attribute \src "libresoc.v:32311.5-32311.29" switch \initial - attribute \src "libresoc.v:31849.9-31849.17" + attribute \src "libresoc.v:32311.9-32311.17" case 1'1 case end @@ -49340,14 +49817,14 @@ module \bpermd sync always update \perm $0\perm[63:0] end - connect \$9 $lt$libresoc.v:31840$1108_Y - connect \$11 $lt$libresoc.v:31841$1109_Y - connect \$13 $lt$libresoc.v:31842$1110_Y - connect \$15 $lt$libresoc.v:31843$1111_Y - connect \$1 $lt$libresoc.v:31844$1112_Y - connect \$3 $lt$libresoc.v:31845$1113_Y - connect \$5 $lt$libresoc.v:31846$1114_Y - connect \$7 $lt$libresoc.v:31847$1115_Y + connect \$9 $lt$libresoc.v:32302$1108_Y + connect \$11 $lt$libresoc.v:32303$1109_Y + connect \$13 $lt$libresoc.v:32304$1110_Y + connect \$15 $lt$libresoc.v:32305$1111_Y + connect \$1 $lt$libresoc.v:32306$1112_Y + connect \$3 $lt$libresoc.v:32307$1113_Y + connect \$5 $lt$libresoc.v:32308$1114_Y + connect \$7 $lt$libresoc.v:32309$1115_Y connect \ra [7:0] \perm [7:0] connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 connect \idx_7 \rs [63:56] @@ -49423,413 +49900,413 @@ module \bpermd connect \rb64_1 \rb [62] connect \rb64_0 \rb [63] end -attribute \src "libresoc.v:33018.1-34067.10" +attribute \src "libresoc.v:33480.1-34535.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" attribute \generator "nMigen" module \branch0 - attribute \src "libresoc.v:33684.3-33685.25" + attribute \src "libresoc.v:34152.3-34153.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 - attribute \src "libresoc.v:33644.3-33645.61" + attribute \src "libresoc.v:34112.3-34113.61" wire width 64 $0\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 12 $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 - attribute \src "libresoc.v:33648.3-33649.69" - wire width 12 $0\alu_branch0_br_op__fn_unit[11:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" + wire width 14 $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 + attribute \src "libresoc.v:34116.3-34117.69" + wire width 14 $0\alu_branch0_br_op__fn_unit[13:0] + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 - attribute \src "libresoc.v:33652.3-33653.83" + attribute \src "libresoc.v:34120.3-34121.83" wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 - attribute \src "libresoc.v:33654.3-33655.79" + attribute \src "libresoc.v:34122.3-34123.79" wire $0\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 - attribute \src "libresoc.v:33650.3-33651.63" + attribute \src "libresoc.v:34118.3-34119.63" wire width 32 $0\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 - attribute \src "libresoc.v:33646.3-33647.73" + attribute \src "libresoc.v:34114.3-34115.73" wire width 7 $0\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 - attribute \src "libresoc.v:33658.3-33659.71" + attribute \src "libresoc.v:34126.3-34127.71" wire $0\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $0\alu_branch0_br_op__lk$next[0:0]$1246 - attribute \src "libresoc.v:33656.3-33657.59" + attribute \src "libresoc.v:34124.3-34125.59" wire $0\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33682.3-33683.43" + attribute \src "libresoc.v:34150.3-34151.43" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:33989.3-33997.6" + attribute \src "libresoc.v:34457.3-34465.6" wire $0\alu_l_r_alu$next[0:0]$1294 - attribute \src "libresoc.v:33622.3-33623.39" + attribute \src "libresoc.v:34090.3-34091.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:33980.3-33988.6" + attribute \src "libresoc.v:34448.3-34456.6" wire $0\alui_l_r_alui$next[0:0]$1291 - attribute \src "libresoc.v:33624.3-33625.43" + attribute \src "libresoc.v:34092.3-34093.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:33884.3-33905.6" + attribute \src "libresoc.v:34352.3-34373.6" wire width 64 $0\data_r0__fast1$next[63:0]$1258 - attribute \src "libresoc.v:33640.3-33641.45" + attribute \src "libresoc.v:34108.3-34109.45" wire width 64 $0\data_r0__fast1[63:0] - attribute \src "libresoc.v:33884.3-33905.6" + attribute \src "libresoc.v:34352.3-34373.6" wire $0\data_r0__fast1_ok$next[0:0]$1259 - attribute \src "libresoc.v:33642.3-33643.51" + attribute \src "libresoc.v:34110.3-34111.51" wire $0\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:33906.3-33927.6" + attribute \src "libresoc.v:34374.3-34395.6" wire width 64 $0\data_r1__fast2$next[63:0]$1266 - attribute \src "libresoc.v:33636.3-33637.45" + attribute \src "libresoc.v:34104.3-34105.45" wire width 64 $0\data_r1__fast2[63:0] - attribute \src "libresoc.v:33906.3-33927.6" + attribute \src "libresoc.v:34374.3-34395.6" wire $0\data_r1__fast2_ok$next[0:0]$1267 - attribute \src "libresoc.v:33638.3-33639.51" + attribute \src "libresoc.v:34106.3-34107.51" wire $0\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:33928.3-33949.6" + attribute \src "libresoc.v:34396.3-34417.6" wire width 64 $0\data_r2__nia$next[63:0]$1274 - attribute \src "libresoc.v:33632.3-33633.41" + attribute \src "libresoc.v:34100.3-34101.41" wire width 64 $0\data_r2__nia[63:0] - attribute \src "libresoc.v:33928.3-33949.6" + attribute \src "libresoc.v:34396.3-34417.6" wire $0\data_r2__nia_ok$next[0:0]$1275 - attribute \src "libresoc.v:33634.3-33635.47" + attribute \src "libresoc.v:34102.3-34103.47" wire $0\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:33998.3-34007.6" + attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:34008.3-34017.6" + attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:34018.3-34027.6" + attribute \src "libresoc.v:34486.3-34495.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:33019.7-33019.20" + attribute \src "libresoc.v:33481.7-33481.20" wire $0\initial[0:0] - attribute \src "libresoc.v:33814.3-33822.6" + attribute \src "libresoc.v:34282.3-34290.6" wire $0\opc_l_r_opc$next[0:0]$1224 - attribute \src "libresoc.v:33668.3-33669.39" + attribute \src "libresoc.v:34136.3-34137.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:33805.3-33813.6" + attribute \src "libresoc.v:34273.3-34281.6" wire $0\opc_l_s_opc$next[0:0]$1221 - attribute \src "libresoc.v:33670.3-33671.39" + attribute \src "libresoc.v:34138.3-34139.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34028.3-34036.6" + attribute \src "libresoc.v:34496.3-34504.6" wire width 3 $0\prev_wr_go$next[2:0]$1300 - attribute \src "libresoc.v:33680.3-33681.37" + attribute \src "libresoc.v:34148.3-34149.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:33759.3-33768.6" + attribute \src "libresoc.v:34227.3-34236.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:33850.3-33858.6" + attribute \src "libresoc.v:34318.3-34326.6" wire width 3 $0\req_l_r_req$next[2:0]$1236 - attribute \src "libresoc.v:33660.3-33661.39" + attribute \src "libresoc.v:34128.3-34129.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:33841.3-33849.6" + attribute \src "libresoc.v:34309.3-34317.6" wire width 3 $0\req_l_s_req$next[2:0]$1233 - attribute \src "libresoc.v:33662.3-33663.39" + attribute \src "libresoc.v:34130.3-34131.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:33778.3-33786.6" + attribute \src "libresoc.v:34246.3-34254.6" wire $0\rok_l_r_rdok$next[0:0]$1212 - attribute \src "libresoc.v:33676.3-33677.41" + attribute \src "libresoc.v:34144.3-34145.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:33769.3-33777.6" + attribute \src "libresoc.v:34237.3-34245.6" wire $0\rok_l_s_rdok$next[0:0]$1209 - attribute \src "libresoc.v:33678.3-33679.41" + attribute \src "libresoc.v:34146.3-34147.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:33796.3-33804.6" + attribute \src "libresoc.v:34264.3-34272.6" wire $0\rst_l_r_rst$next[0:0]$1218 - attribute \src "libresoc.v:33672.3-33673.39" + attribute \src "libresoc.v:34140.3-34141.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:33787.3-33795.6" + attribute \src "libresoc.v:34255.3-34263.6" wire $0\rst_l_s_rst$next[0:0]$1215 - attribute \src "libresoc.v:33674.3-33675.39" + attribute \src "libresoc.v:34142.3-34143.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:33832.3-33840.6" + attribute \src "libresoc.v:34300.3-34308.6" wire width 3 $0\src_l_r_src$next[2:0]$1230 - attribute \src "libresoc.v:33664.3-33665.39" + attribute \src "libresoc.v:34132.3-34133.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:33823.3-33831.6" + attribute \src "libresoc.v:34291.3-34299.6" wire width 3 $0\src_l_s_src$next[2:0]$1227 - attribute \src "libresoc.v:33666.3-33667.39" + attribute \src "libresoc.v:34134.3-34135.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:33950.3-33959.6" + attribute \src "libresoc.v:34418.3-34427.6" wire width 64 $0\src_r0$next[63:0]$1282 - attribute \src "libresoc.v:33630.3-33631.29" + attribute \src "libresoc.v:34098.3-34099.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:33960.3-33969.6" + attribute \src "libresoc.v:34428.3-34437.6" wire width 64 $0\src_r1$next[63:0]$1285 - attribute \src "libresoc.v:33628.3-33629.29" + attribute \src "libresoc.v:34096.3-34097.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:33970.3-33979.6" + attribute \src "libresoc.v:34438.3-34447.6" wire width 4 $0\src_r2$next[3:0]$1288 - attribute \src "libresoc.v:33626.3-33627.29" + attribute \src "libresoc.v:34094.3-34095.29" wire width 4 $0\src_r2[3:0] - attribute \src "libresoc.v:33137.7-33137.24" + attribute \src "libresoc.v:33599.7-33599.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 - attribute \src "libresoc.v:33145.14-33145.59" + attribute \src "libresoc.v:33607.14-33607.59" wire width 64 $1\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 12 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 - attribute \src "libresoc.v:33162.14-33162.50" - wire width 12 $1\alu_branch0_br_op__fn_unit[11:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" + wire width 14 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 + attribute \src "libresoc.v:33626.14-33626.51" + wire width 14 $1\alu_branch0_br_op__fn_unit[13:0] + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 - attribute \src "libresoc.v:33166.14-33166.70" + attribute \src "libresoc.v:33630.14-33630.70" wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 - attribute \src "libresoc.v:33170.7-33170.45" + attribute \src "libresoc.v:33634.7-33634.45" wire $1\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1251 - attribute \src "libresoc.v:33174.14-33174.45" + attribute \src "libresoc.v:33638.14-33638.45" wire width 32 $1\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 - attribute \src "libresoc.v:33252.13-33252.49" + attribute \src "libresoc.v:33717.13-33717.49" wire width 7 $1\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 - attribute \src "libresoc.v:33256.7-33256.41" + attribute \src "libresoc.v:33721.7-33721.41" wire $1\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $1\alu_branch0_br_op__lk$next[0:0]$1254 - attribute \src "libresoc.v:33260.7-33260.35" + attribute \src "libresoc.v:33725.7-33725.35" wire $1\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33286.7-33286.26" + attribute \src "libresoc.v:33751.7-33751.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:33989.3-33997.6" + attribute \src "libresoc.v:34457.3-34465.6" wire $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:33294.7-33294.25" + attribute \src "libresoc.v:33759.7-33759.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:33980.3-33988.6" + attribute \src "libresoc.v:34448.3-34456.6" wire $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:33306.7-33306.27" + attribute \src "libresoc.v:33771.7-33771.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:33884.3-33905.6" + attribute \src "libresoc.v:34352.3-34373.6" wire width 64 $1\data_r0__fast1$next[63:0]$1260 - attribute \src "libresoc.v:33338.14-33338.51" + attribute \src "libresoc.v:33803.14-33803.51" wire width 64 $1\data_r0__fast1[63:0] - attribute \src "libresoc.v:33884.3-33905.6" + attribute \src "libresoc.v:34352.3-34373.6" wire $1\data_r0__fast1_ok$next[0:0]$1261 - attribute \src "libresoc.v:33342.7-33342.31" + attribute \src "libresoc.v:33807.7-33807.31" wire $1\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:33906.3-33927.6" + attribute \src "libresoc.v:34374.3-34395.6" wire width 64 $1\data_r1__fast2$next[63:0]$1268 - attribute \src "libresoc.v:33346.14-33346.51" + attribute \src "libresoc.v:33811.14-33811.51" wire width 64 $1\data_r1__fast2[63:0] - attribute \src "libresoc.v:33906.3-33927.6" + attribute \src "libresoc.v:34374.3-34395.6" wire $1\data_r1__fast2_ok$next[0:0]$1269 - attribute \src "libresoc.v:33350.7-33350.31" + attribute \src "libresoc.v:33815.7-33815.31" wire $1\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:33928.3-33949.6" + attribute \src "libresoc.v:34396.3-34417.6" wire width 64 $1\data_r2__nia$next[63:0]$1276 - attribute \src "libresoc.v:33354.14-33354.49" + attribute \src "libresoc.v:33819.14-33819.49" wire width 64 $1\data_r2__nia[63:0] - attribute \src "libresoc.v:33928.3-33949.6" + attribute \src "libresoc.v:34396.3-34417.6" wire $1\data_r2__nia_ok$next[0:0]$1277 - attribute \src "libresoc.v:33358.7-33358.29" + attribute \src "libresoc.v:33823.7-33823.29" wire $1\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:33998.3-34007.6" + attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:34008.3-34017.6" + attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:34018.3-34027.6" + attribute \src "libresoc.v:34486.3-34495.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:33814.3-33822.6" + attribute \src "libresoc.v:34282.3-34290.6" wire $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:33379.7-33379.25" + attribute \src "libresoc.v:33844.7-33844.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:33805.3-33813.6" + attribute \src "libresoc.v:34273.3-34281.6" wire $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:33383.7-33383.25" + attribute \src "libresoc.v:33848.7-33848.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34028.3-34036.6" + attribute \src "libresoc.v:34496.3-34504.6" wire width 3 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:33490.13-33490.30" + attribute \src "libresoc.v:33958.13-33958.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:33759.3-33768.6" + attribute \src "libresoc.v:34227.3-34236.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:33850.3-33858.6" + attribute \src "libresoc.v:34318.3-34326.6" wire width 3 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:33498.13-33498.31" + attribute \src "libresoc.v:33966.13-33966.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:33841.3-33849.6" + attribute \src "libresoc.v:34309.3-34317.6" wire width 3 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:33502.13-33502.31" + attribute \src "libresoc.v:33970.13-33970.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:33778.3-33786.6" + attribute \src "libresoc.v:34246.3-34254.6" wire $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:33514.7-33514.26" + attribute \src "libresoc.v:33982.7-33982.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:33769.3-33777.6" + attribute \src "libresoc.v:34237.3-34245.6" wire $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:33518.7-33518.26" + attribute \src "libresoc.v:33986.7-33986.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:33796.3-33804.6" + attribute \src "libresoc.v:34264.3-34272.6" wire $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:33522.7-33522.25" + attribute \src "libresoc.v:33990.7-33990.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:33787.3-33795.6" + attribute \src "libresoc.v:34255.3-34263.6" wire $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:33526.7-33526.25" + attribute \src "libresoc.v:33994.7-33994.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:33832.3-33840.6" + attribute \src "libresoc.v:34300.3-34308.6" wire width 3 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:33540.13-33540.31" + attribute \src "libresoc.v:34008.13-34008.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:33823.3-33831.6" + attribute \src "libresoc.v:34291.3-34299.6" wire width 3 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:33544.13-33544.31" + attribute \src "libresoc.v:34012.13-34012.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:33950.3-33959.6" + attribute \src "libresoc.v:34418.3-34427.6" wire width 64 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:33550.14-33550.43" + attribute \src "libresoc.v:34018.14-34018.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:33960.3-33969.6" + attribute \src "libresoc.v:34428.3-34437.6" wire width 64 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:33554.14-33554.43" + attribute \src "libresoc.v:34022.14-34022.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:33970.3-33979.6" + attribute \src "libresoc.v:34438.3-34447.6" wire width 4 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:33558.13-33558.26" + attribute \src "libresoc.v:34026.13-34026.26" wire width 4 $1\src_r2[3:0] - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 - attribute \src "libresoc.v:33859.3-33883.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:33884.3-33905.6" + attribute \src "libresoc.v:34352.3-34373.6" wire width 64 $2\data_r0__fast1$next[63:0]$1262 - attribute \src "libresoc.v:33884.3-33905.6" + attribute \src "libresoc.v:34352.3-34373.6" wire $2\data_r0__fast1_ok$next[0:0]$1263 - attribute \src "libresoc.v:33906.3-33927.6" + attribute \src "libresoc.v:34374.3-34395.6" wire width 64 $2\data_r1__fast2$next[63:0]$1270 - attribute \src "libresoc.v:33906.3-33927.6" + attribute \src "libresoc.v:34374.3-34395.6" wire $2\data_r1__fast2_ok$next[0:0]$1271 - attribute \src "libresoc.v:33928.3-33949.6" + attribute \src "libresoc.v:34396.3-34417.6" wire width 64 $2\data_r2__nia$next[63:0]$1278 - attribute \src "libresoc.v:33928.3-33949.6" + attribute \src "libresoc.v:34396.3-34417.6" wire $2\data_r2__nia_ok$next[0:0]$1279 - attribute \src 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$reduce_or$libresoc.v:34055$1140_Y + attribute \src "libresoc.v:34078.18-34078.162" + wire $ternary$libresoc.v:34078$1163_Y + attribute \src "libresoc.v:34079.18-34079.176" + wire width 64 $ternary$libresoc.v:34079$1164_Y + attribute \src "libresoc.v:34080.18-34080.118" + wire width 64 $ternary$libresoc.v:34080$1165_Y + attribute \src "libresoc.v:34081.18-34081.115" + wire width 64 $ternary$libresoc.v:34081$1166_Y + attribute \src "libresoc.v:34082.18-34082.118" + wire width 4 $ternary$libresoc.v:34082$1167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -49848,13 +50325,13 @@ module \branch0 wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 3 \$21 @@ -49924,11 +50401,11 @@ module \branch0 wire width 64 \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 4 \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$87 @@ -49946,35 +50423,37 @@ module \branch0 wire width 3 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__cia$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_branch0_br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_branch0_br_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_branch0_br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_branch0_br_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50061,6 +50540,7 @@ module \branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_branch0_br_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50083,47 +50563,47 @@ module \branch0 wire width 64 \alu_branch0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_branch0_fast2$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_branch0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_branch0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_branch0_nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_branch0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_branch0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 3 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o @@ -50181,37 +50661,39 @@ module \branch0 wire output 18 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast2_ok - attribute \src "libresoc.v:33019.7-33019.15" + attribute \src "libresoc.v:33481.7-33481.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 2 \oper_i_alu_branch0__cia attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 4 \oper_i_alu_branch0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 4 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 6 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50292,6 +50774,7 @@ module \branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 3 \oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50304,15 +50787,15 @@ module \branch0 wire width 3 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -50320,23 +50803,23 @@ module \branch0 wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -50346,36 +50829,36 @@ module \branch0 wire width 64 input 17 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 15 \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33566$1119 + cell $and $and$libresoc.v:34034$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50383,10 +50866,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:33566$1119_Y + connect \Y $and$libresoc.v:34034$1119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33567$1120 + cell $and $and$libresoc.v:34035$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50394,10 +50877,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33567$1120_Y + connect \Y $and$libresoc.v:34035$1120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33568$1121 + cell $and $and$libresoc.v:34036$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50405,10 +50888,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33568$1121_Y + connect \Y $and$libresoc.v:34036$1121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33569$1122 + cell $and $and$libresoc.v:34037$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50416,10 +50899,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33569$1122_Y + connect \Y $and$libresoc.v:34037$1122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:33570$1123 + cell $and $and$libresoc.v:34038$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50427,10 +50910,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:33570$1123_Y + connect \Y $and$libresoc.v:34038$1123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:33571$1124 + cell $and $and$libresoc.v:34039$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50438,10 +50921,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33571$1124_Y + connect \Y $and$libresoc.v:34039$1124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33572$1125 + cell $and $and$libresoc.v:34040$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50449,10 +50932,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33572$1125_Y + connect \Y $and$libresoc.v:34040$1125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33573$1126 + cell $and $and$libresoc.v:34041$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50460,10 +50943,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33573$1126_Y + connect \Y $and$libresoc.v:34041$1126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33574$1127 + cell $and $and$libresoc.v:34042$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50471,10 +50954,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33574$1127_Y + connect \Y $and$libresoc.v:34042$1127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:33575$1128 + cell $and $and$libresoc.v:34043$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50482,10 +50965,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:33575$1128_Y + connect \Y $and$libresoc.v:34043$1128_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:33577$1130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:34045$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50493,10 +50976,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:33577$1130_Y + connect \Y $and$libresoc.v:34045$1130_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:33579$1132 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:34047$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50504,10 +50987,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:33579$1132_Y + connect \Y $and$libresoc.v:34047$1132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:33580$1133 + cell $and $and$libresoc.v:34048$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50515,10 +50998,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:33580$1133_Y + connect \Y $and$libresoc.v:34048$1133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:33582$1135 + cell $and $and$libresoc.v:34050$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50526,10 +51009,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:33582$1135_Y + connect \Y $and$libresoc.v:34050$1135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:33585$1138 + cell $and $and$libresoc.v:34053$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50537,10 +51020,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:33585$1138_Y + connect \Y $and$libresoc.v:34053$1138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:33589$1142 + cell $and $and$libresoc.v:34057$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50548,10 +51031,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:33589$1142_Y + connect \Y $and$libresoc.v:34057$1142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:33591$1144 + cell $and $and$libresoc.v:34059$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50559,10 +51042,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:33591$1144_Y + connect \Y $and$libresoc.v:34059$1144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:33592$1145 + cell $and $and$libresoc.v:34060$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50570,10 +51053,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33592$1145_Y + connect \Y $and$libresoc.v:34060$1145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:33594$1147 + cell $and $and$libresoc.v:34062$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50581,10 +51064,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:33594$1147_Y + connect \Y $and$libresoc.v:34062$1147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33596$1149 + cell $and $and$libresoc.v:34064$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50592,10 +51075,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_branch0_n_ready_i - connect \Y $and$libresoc.v:33596$1149_Y + connect \Y $and$libresoc.v:34064$1149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33597$1150 + cell $and $and$libresoc.v:34065$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50603,10 +51086,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_branch0_n_valid_o - connect \Y $and$libresoc.v:33597$1150_Y + connect \Y $and$libresoc.v:34065$1150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33598$1151 + cell $and $and$libresoc.v:34066$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50614,10 +51097,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:33598$1151_Y + connect \Y $and$libresoc.v:34066$1151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:33603$1156 + cell $and $and$libresoc.v:34071$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50625,10 +51108,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:33603$1156_Y + connect \Y $and$libresoc.v:34071$1156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:33604$1157 + cell $and $and$libresoc.v:34072$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50636,10 +51119,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33604$1157_Y + connect \Y $and$libresoc.v:34072$1157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33607$1160 + cell $and $and$libresoc.v:34075$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50647,10 +51130,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33607$1160_Y + connect \Y $and$libresoc.v:34075$1160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33608$1161 + cell $and $and$libresoc.v:34076$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50658,10 +51141,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33608$1161_Y + connect \Y $and$libresoc.v:34076$1161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33609$1162 + cell $and $and$libresoc.v:34077$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50669,10 +51152,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33609$1162_Y + connect \Y $and$libresoc.v:34077$1162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:33615$1168 + cell $and $and$libresoc.v:34083$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50680,10 +51163,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:33615$1168_Y + connect \Y $and$libresoc.v:34083$1168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:33617$1170 + cell $and $and$libresoc.v:34085$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50691,10 +51174,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:33617$1170_Y + connect \Y $and$libresoc.v:34085$1170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33618$1171 + cell $and $and$libresoc.v:34086$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50702,10 +51185,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:33618$1171_Y + connect \Y $and$libresoc.v:34086$1171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33620$1173 + cell $and $and$libresoc.v:34088$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50713,10 +51196,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$91 connect \B { 1'1 \$93 1'1 } - connect \Y $and$libresoc.v:33620$1173_Y + connect \Y $and$libresoc.v:34088$1173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:33593$1146 + cell $eq $eq$libresoc.v:34061$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50724,10 +51207,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:33593$1146_Y + connect \Y $eq$libresoc.v:34061$1146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:33595$1148 + cell $eq $eq$libresoc.v:34063$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50735,74 +51218,74 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:33595$1148_Y + connect \Y $eq$libresoc.v:34063$1148_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:33576$1129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:34044$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:33576$1129_Y + connect \Y $not$libresoc.v:34044$1129_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:33578$1131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:34046$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:33578$1131_Y + connect \Y $not$libresoc.v:34046$1131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:33581$1134 + cell $not $not$libresoc.v:34049$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:33581$1134_Y + connect \Y $not$libresoc.v:34049$1134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:33584$1137 + cell $not $not$libresoc.v:34052$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:33584$1137_Y + connect \Y $not$libresoc.v:34052$1137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:33590$1143 + cell $not $not$libresoc.v:34058$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_ready_i - connect \Y $not$libresoc.v:33590$1143_Y + connect \Y $not$libresoc.v:34058$1143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:33605$1158 + cell $not $not$libresoc.v:34073$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:33605$1158_Y + connect \Y $not$libresoc.v:34073$1158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:33619$1172 + cell $not $not$libresoc.v:34087$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_br_op__imm_data__ok - connect \Y $not$libresoc.v:33619$1172_Y + connect \Y $not$libresoc.v:34087$1172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:33621$1174 + cell $not $not$libresoc.v:34089$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:33621$1174_Y + connect \Y $not$libresoc.v:34089$1174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:33588$1141 + cell $or $or$libresoc.v:34056$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50810,10 +51293,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:33588$1141_Y + connect \Y $or$libresoc.v:34056$1141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:33599$1152 + cell $or $or$libresoc.v:34067$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50821,10 +51304,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:33599$1152_Y + connect \Y $or$libresoc.v:34067$1152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:33600$1153 + cell $or $or$libresoc.v:34068$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50832,10 +51315,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:33600$1153_Y + connect \Y $or$libresoc.v:34068$1153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:33601$1154 + cell $or $or$libresoc.v:34069$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50843,10 +51326,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:33601$1154_Y + connect \Y $or$libresoc.v:34069$1154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:33602$1155 + cell $or $or$libresoc.v:34070$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50854,10 +51337,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:33602$1155_Y + connect \Y $or$libresoc.v:34070$1155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:33606$1159 + cell $or $or$libresoc.v:34074$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50865,10 +51348,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:33606$1159_Y + connect \Y $or$libresoc.v:34074$1159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:33616$1169 + cell $or $or$libresoc.v:34084$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50876,82 +51359,82 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:33616$1169_Y + connect \Y $or$libresoc.v:34084$1169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:33565$1118 + cell $reduce_and $reduce_and$libresoc.v:34033$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:33565$1118_Y + connect \Y $reduce_and$libresoc.v:34033$1118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:33583$1136 + cell $reduce_or $reduce_or$libresoc.v:34051$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:33583$1136_Y + connect \Y $reduce_or$libresoc.v:34051$1136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:33586$1139 + cell $reduce_or $reduce_or$libresoc.v:34054$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:33586$1139_Y + connect \Y $reduce_or$libresoc.v:34054$1139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:33587$1140 + cell $reduce_or $reduce_or$libresoc.v:34055$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:33587$1140_Y + connect \Y $reduce_or$libresoc.v:34055$1140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:33610$1163 + cell $mux $ternary$libresoc.v:34078$1163 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:33610$1163_Y + connect \Y $ternary$libresoc.v:34078$1163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:33611$1164 + cell $mux $ternary$libresoc.v:34079$1164 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_branch0_br_op__imm_data__data connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:33611$1164_Y + connect \Y $ternary$libresoc.v:34079$1164_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33612$1165 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:34080$1165 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:33612$1165_Y + connect \Y $ternary$libresoc.v:34080$1165_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33613$1166 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:34081$1166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:33613$1166_Y + connect \Y $ternary$libresoc.v:34081$1166_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33614$1167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:34082$1167 parameter \WIDTH 4 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:33614$1167_Y + connect \Y $ternary$libresoc.v:34082$1167_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:33686.15-33710.4" + attribute \src "libresoc.v:34154.15-34178.4" cell \alu_branch0 \alu_branch0 connect \br_op__cia \alu_branch0_br_op__cia connect \br_op__fn_unit \alu_branch0_br_op__fn_unit @@ -50978,7 +51461,7 @@ module \branch0 connect \p_valid_i \alu_branch0_p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:33711.14-33717.4" + attribute \src "libresoc.v:34179.14-34185.4" cell \alu_l$29 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50987,7 +51470,7 @@ module \branch0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:33718.15-33724.4" + attribute \src "libresoc.v:34186.15-34192.4" cell \alui_l$28 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50996,7 +51479,7 @@ module \branch0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:33725.14-33731.4" + attribute \src "libresoc.v:34193.14-34199.4" cell \opc_l$24 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51005,7 +51488,7 @@ module \branch0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:33732.14-33738.4" + attribute \src "libresoc.v:34200.14-34206.4" cell \req_l$25 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51014,7 +51497,7 @@ module \branch0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:33739.14-33745.4" + attribute \src "libresoc.v:34207.14-34213.4" cell \rok_l$27 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51023,7 +51506,7 @@ module \branch0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:33746.14-33751.4" + attribute \src "libresoc.v:34214.14-34219.4" cell \rst_l$26 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51031,7 +51514,7 @@ module \branch0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:33752.14-33758.4" + attribute \src "libresoc.v:34220.14-34226.4" cell \src_l$23 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51039,502 +51522,502 @@ module \branch0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:33019.7-33019.20" - process $proc$libresoc.v:33019$1302 + attribute \src "libresoc.v:33481.7-33481.20" + process $proc$libresoc.v:33481$1302 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:33137.7-33137.24" - process $proc$libresoc.v:33137$1303 + attribute \src "libresoc.v:33599.7-33599.24" + process $proc$libresoc.v:33599$1303 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:33145.14-33145.59" - process $proc$libresoc.v:33145$1304 + attribute \src "libresoc.v:33607.14-33607.59" + process $proc$libresoc.v:33607$1304 assign { } { } assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:33162.14-33162.50" - process $proc$libresoc.v:33162$1305 + attribute \src "libresoc.v:33626.14-33626.51" + process $proc$libresoc.v:33626$1305 assign { } { } - assign $1\alu_branch0_br_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_branch0_br_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[11:0] + update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[13:0] end - attribute \src "libresoc.v:33166.14-33166.70" - process $proc$libresoc.v:33166$1306 + attribute \src "libresoc.v:33630.14-33630.70" + process $proc$libresoc.v:33630$1306 assign { } { } assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:33170.7-33170.45" - process $proc$libresoc.v:33170$1307 + attribute \src "libresoc.v:33634.7-33634.45" + process $proc$libresoc.v:33634$1307 assign { } { } assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:33174.14-33174.45" - process $proc$libresoc.v:33174$1308 + attribute \src "libresoc.v:33638.14-33638.45" + process $proc$libresoc.v:33638$1308 assign { } { } assign $1\alu_branch0_br_op__insn[31:0] 0 sync always sync init update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:33252.13-33252.49" - process $proc$libresoc.v:33252$1309 + attribute \src "libresoc.v:33717.13-33717.49" + process $proc$libresoc.v:33717$1309 assign { } { } assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:33256.7-33256.41" - process $proc$libresoc.v:33256$1310 + attribute \src "libresoc.v:33721.7-33721.41" + process $proc$libresoc.v:33721$1310 assign { } { } assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 sync always sync init update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:33260.7-33260.35" - process $proc$libresoc.v:33260$1311 + attribute \src "libresoc.v:33725.7-33725.35" + process $proc$libresoc.v:33725$1311 assign { } { } assign $1\alu_branch0_br_op__lk[0:0] 1'0 sync always sync init update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:33286.7-33286.26" - process $proc$libresoc.v:33286$1312 + attribute \src "libresoc.v:33751.7-33751.26" + process $proc$libresoc.v:33751$1312 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:33294.7-33294.25" - process $proc$libresoc.v:33294$1313 + attribute \src "libresoc.v:33759.7-33759.25" + process $proc$libresoc.v:33759$1313 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:33306.7-33306.27" - process $proc$libresoc.v:33306$1314 + attribute \src "libresoc.v:33771.7-33771.27" + process $proc$libresoc.v:33771$1314 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:33338.14-33338.51" - process $proc$libresoc.v:33338$1315 + attribute \src "libresoc.v:33803.14-33803.51" + process $proc$libresoc.v:33803$1315 assign { } { } assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__fast1 $1\data_r0__fast1[63:0] end - attribute \src "libresoc.v:33342.7-33342.31" - process $proc$libresoc.v:33342$1316 + attribute \src "libresoc.v:33807.7-33807.31" + process $proc$libresoc.v:33807$1316 assign { } { } assign $1\data_r0__fast1_ok[0:0] 1'0 sync always sync init update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:33346.14-33346.51" - process $proc$libresoc.v:33346$1317 + attribute \src "libresoc.v:33811.14-33811.51" + process $proc$libresoc.v:33811$1317 assign { } { } assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast2 $1\data_r1__fast2[63:0] end - attribute \src "libresoc.v:33350.7-33350.31" - process $proc$libresoc.v:33350$1318 + attribute \src "libresoc.v:33815.7-33815.31" + process $proc$libresoc.v:33815$1318 assign { } { } assign $1\data_r1__fast2_ok[0:0] 1'0 sync always sync init update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:33354.14-33354.49" - process $proc$libresoc.v:33354$1319 + attribute \src "libresoc.v:33819.14-33819.49" + process $proc$libresoc.v:33819$1319 assign { } { } assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__nia $1\data_r2__nia[63:0] end - attribute \src "libresoc.v:33358.7-33358.29" - process $proc$libresoc.v:33358$1320 + attribute \src "libresoc.v:33823.7-33823.29" + process $proc$libresoc.v:33823$1320 assign { } { } assign $1\data_r2__nia_ok[0:0] 1'0 sync always sync init update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:33379.7-33379.25" - process $proc$libresoc.v:33379$1321 + attribute \src "libresoc.v:33844.7-33844.25" + process $proc$libresoc.v:33844$1321 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:33383.7-33383.25" - process $proc$libresoc.v:33383$1322 + attribute \src "libresoc.v:33848.7-33848.25" + process $proc$libresoc.v:33848$1322 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:33490.13-33490.30" - process $proc$libresoc.v:33490$1323 + attribute \src "libresoc.v:33958.13-33958.30" + process $proc$libresoc.v:33958$1323 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:33498.13-33498.31" - process $proc$libresoc.v:33498$1324 + attribute \src "libresoc.v:33966.13-33966.31" + process $proc$libresoc.v:33966$1324 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:33502.13-33502.31" - process $proc$libresoc.v:33502$1325 + attribute \src "libresoc.v:33970.13-33970.31" + process $proc$libresoc.v:33970$1325 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:33514.7-33514.26" - process $proc$libresoc.v:33514$1326 + attribute \src "libresoc.v:33982.7-33982.26" + process $proc$libresoc.v:33982$1326 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:33518.7-33518.26" - process $proc$libresoc.v:33518$1327 + attribute \src "libresoc.v:33986.7-33986.26" + process $proc$libresoc.v:33986$1327 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:33522.7-33522.25" - process $proc$libresoc.v:33522$1328 + attribute \src "libresoc.v:33990.7-33990.25" + process $proc$libresoc.v:33990$1328 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:33526.7-33526.25" - process $proc$libresoc.v:33526$1329 + attribute \src "libresoc.v:33994.7-33994.25" + process $proc$libresoc.v:33994$1329 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:33540.13-33540.31" - process $proc$libresoc.v:33540$1330 + attribute \src "libresoc.v:34008.13-34008.31" + process $proc$libresoc.v:34008$1330 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:33544.13-33544.31" - process $proc$libresoc.v:33544$1331 + attribute \src "libresoc.v:34012.13-34012.31" + process $proc$libresoc.v:34012$1331 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:33550.14-33550.43" - process $proc$libresoc.v:33550$1332 + attribute \src "libresoc.v:34018.14-34018.43" + process $proc$libresoc.v:34018$1332 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:33554.14-33554.43" - process $proc$libresoc.v:33554$1333 + attribute \src "libresoc.v:34022.14-34022.43" + process $proc$libresoc.v:34022$1333 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:33558.13-33558.26" - process $proc$libresoc.v:33558$1334 + attribute \src "libresoc.v:34026.13-34026.26" + process $proc$libresoc.v:34026$1334 assign { } { } assign $1\src_r2[3:0] 4'0000 sync always sync init update \src_r2 $1\src_r2[3:0] end - attribute \src "libresoc.v:33622.3-33623.39" - process $proc$libresoc.v:33622$1175 + attribute \src "libresoc.v:34090.3-34091.39" + process $proc$libresoc.v:34090$1175 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:33624.3-33625.43" - process $proc$libresoc.v:33624$1176 + attribute \src "libresoc.v:34092.3-34093.43" + process $proc$libresoc.v:34092$1176 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:33626.3-33627.29" - process $proc$libresoc.v:33626$1177 + attribute \src "libresoc.v:34094.3-34095.29" + process $proc$libresoc.v:34094$1177 assign { } { } assign $0\src_r2[3:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[3:0] end - attribute \src "libresoc.v:33628.3-33629.29" - process $proc$libresoc.v:33628$1178 + attribute \src "libresoc.v:34096.3-34097.29" + process $proc$libresoc.v:34096$1178 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:33630.3-33631.29" - process $proc$libresoc.v:33630$1179 + attribute \src "libresoc.v:34098.3-34099.29" + process $proc$libresoc.v:34098$1179 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:33632.3-33633.41" - process $proc$libresoc.v:33632$1180 + attribute \src "libresoc.v:34100.3-34101.41" + process $proc$libresoc.v:34100$1180 assign { } { } assign $0\data_r2__nia[63:0] \data_r2__nia$next sync posedge \coresync_clk update \data_r2__nia $0\data_r2__nia[63:0] end - attribute \src "libresoc.v:33634.3-33635.47" - process $proc$libresoc.v:33634$1181 + attribute \src "libresoc.v:34102.3-34103.47" + process $proc$libresoc.v:34102$1181 assign { } { } assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next sync posedge \coresync_clk update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:33636.3-33637.45" - process $proc$libresoc.v:33636$1182 + attribute \src "libresoc.v:34104.3-34105.45" + process $proc$libresoc.v:34104$1182 assign { } { } assign $0\data_r1__fast2[63:0] \data_r1__fast2$next sync posedge \coresync_clk update \data_r1__fast2 $0\data_r1__fast2[63:0] end - attribute \src "libresoc.v:33638.3-33639.51" - process $proc$libresoc.v:33638$1183 + attribute \src "libresoc.v:34106.3-34107.51" + process $proc$libresoc.v:34106$1183 assign { } { } assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next sync posedge \coresync_clk update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:33640.3-33641.45" - process $proc$libresoc.v:33640$1184 + attribute \src "libresoc.v:34108.3-34109.45" + process $proc$libresoc.v:34108$1184 assign { } { } assign $0\data_r0__fast1[63:0] \data_r0__fast1$next sync posedge \coresync_clk update \data_r0__fast1 $0\data_r0__fast1[63:0] end - attribute \src "libresoc.v:33642.3-33643.51" - process $proc$libresoc.v:33642$1185 + attribute \src "libresoc.v:34110.3-34111.51" + process $proc$libresoc.v:34110$1185 assign { } { } assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next sync posedge \coresync_clk update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:33644.3-33645.61" - process $proc$libresoc.v:33644$1186 + attribute \src "libresoc.v:34112.3-34113.61" + process $proc$libresoc.v:34112$1186 assign { } { } assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next sync posedge \coresync_clk update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:33646.3-33647.73" - process $proc$libresoc.v:33646$1187 + attribute \src "libresoc.v:34114.3-34115.73" + process $proc$libresoc.v:34114$1187 assign { } { } assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next sync posedge \coresync_clk update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:33648.3-33649.69" - process $proc$libresoc.v:33648$1188 + attribute \src "libresoc.v:34116.3-34117.69" + process $proc$libresoc.v:34116$1188 assign { } { } - assign $0\alu_branch0_br_op__fn_unit[11:0] \alu_branch0_br_op__fn_unit$next + assign $0\alu_branch0_br_op__fn_unit[13:0] \alu_branch0_br_op__fn_unit$next sync posedge \coresync_clk - update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[11:0] + update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[13:0] end - attribute \src "libresoc.v:33650.3-33651.63" - process $proc$libresoc.v:33650$1189 + attribute \src "libresoc.v:34118.3-34119.63" + process $proc$libresoc.v:34118$1189 assign { } { } assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next sync posedge \coresync_clk update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:33652.3-33653.83" - process $proc$libresoc.v:33652$1190 + attribute \src "libresoc.v:34120.3-34121.83" + process $proc$libresoc.v:34120$1190 assign { } { } assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:33654.3-33655.79" - process $proc$libresoc.v:33654$1191 + attribute \src "libresoc.v:34122.3-34123.79" + process $proc$libresoc.v:34122$1191 assign { } { } assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:33656.3-33657.59" - process $proc$libresoc.v:33656$1192 + attribute \src "libresoc.v:34124.3-34125.59" + process $proc$libresoc.v:34124$1192 assign { } { } assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next sync posedge \coresync_clk update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:33658.3-33659.71" - process $proc$libresoc.v:33658$1193 + attribute \src "libresoc.v:34126.3-34127.71" + process $proc$libresoc.v:34126$1193 assign { } { } assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next sync posedge \coresync_clk update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:33660.3-33661.39" - process $proc$libresoc.v:33660$1194 + attribute \src "libresoc.v:34128.3-34129.39" + process $proc$libresoc.v:34128$1194 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:33662.3-33663.39" - process $proc$libresoc.v:33662$1195 + attribute \src "libresoc.v:34130.3-34131.39" + process $proc$libresoc.v:34130$1195 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:33664.3-33665.39" - process $proc$libresoc.v:33664$1196 + attribute \src "libresoc.v:34132.3-34133.39" + process $proc$libresoc.v:34132$1196 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:33666.3-33667.39" - process $proc$libresoc.v:33666$1197 + attribute \src "libresoc.v:34134.3-34135.39" + process $proc$libresoc.v:34134$1197 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:33668.3-33669.39" - process $proc$libresoc.v:33668$1198 + attribute \src "libresoc.v:34136.3-34137.39" + process $proc$libresoc.v:34136$1198 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:33670.3-33671.39" - process $proc$libresoc.v:33670$1199 + attribute \src "libresoc.v:34138.3-34139.39" + process $proc$libresoc.v:34138$1199 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:33672.3-33673.39" - process $proc$libresoc.v:33672$1200 + attribute \src "libresoc.v:34140.3-34141.39" + process $proc$libresoc.v:34140$1200 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:33674.3-33675.39" - process $proc$libresoc.v:33674$1201 + attribute \src "libresoc.v:34142.3-34143.39" + process $proc$libresoc.v:34142$1201 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:33676.3-33677.41" - process $proc$libresoc.v:33676$1202 + attribute \src "libresoc.v:34144.3-34145.41" + process $proc$libresoc.v:34144$1202 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:33678.3-33679.41" - process $proc$libresoc.v:33678$1203 + attribute \src "libresoc.v:34146.3-34147.41" + process $proc$libresoc.v:34146$1203 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:33680.3-33681.37" - process $proc$libresoc.v:33680$1204 + attribute \src "libresoc.v:34148.3-34149.37" + process $proc$libresoc.v:34148$1204 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:33682.3-33683.43" - process $proc$libresoc.v:33682$1205 + attribute \src "libresoc.v:34150.3-34151.43" + process $proc$libresoc.v:34150$1205 assign { } { } assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:33684.3-33685.25" - process $proc$libresoc.v:33684$1206 + attribute \src "libresoc.v:34152.3-34153.25" + process $proc$libresoc.v:34152$1206 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:33759.3-33768.6" - process $proc$libresoc.v:33759$1207 + attribute \src "libresoc.v:34227.3-34236.6" + process $proc$libresoc.v:34227$1207 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:33760.5-33760.29" + attribute \src "libresoc.v:34228.5-34228.29" switch \initial - attribute \src "libresoc.v:33760.9-33760.17" + attribute \src "libresoc.v:34228.9-34228.17" case 1'1 case end @@ -51550,14 +52033,14 @@ module \branch0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:33769.3-33777.6" - process $proc$libresoc.v:33769$1208 + attribute \src "libresoc.v:34237.3-34245.6" + process $proc$libresoc.v:34237$1208 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:33770.5-33770.29" + attribute \src "libresoc.v:34238.5-34238.29" switch \initial - attribute \src "libresoc.v:33770.9-33770.17" + attribute \src "libresoc.v:34238.9-34238.17" case 1'1 case end @@ -51573,14 +52056,14 @@ module \branch0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 end - attribute \src "libresoc.v:33778.3-33786.6" - process $proc$libresoc.v:33778$1211 + attribute \src "libresoc.v:34246.3-34254.6" + process $proc$libresoc.v:34246$1211 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:33779.5-33779.29" + attribute \src "libresoc.v:34247.5-34247.29" switch \initial - attribute \src "libresoc.v:33779.9-33779.17" + attribute \src "libresoc.v:34247.9-34247.17" case 1'1 case end @@ -51596,14 +52079,14 @@ module \branch0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 end - attribute \src "libresoc.v:33787.3-33795.6" - process $proc$libresoc.v:33787$1214 + attribute \src "libresoc.v:34255.3-34263.6" + process $proc$libresoc.v:34255$1214 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:33788.5-33788.29" + attribute \src "libresoc.v:34256.5-34256.29" switch \initial - attribute \src "libresoc.v:33788.9-33788.17" + attribute \src "libresoc.v:34256.9-34256.17" case 1'1 case end @@ -51619,14 +52102,14 @@ module \branch0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 end - attribute \src "libresoc.v:33796.3-33804.6" - process $proc$libresoc.v:33796$1217 + attribute \src "libresoc.v:34264.3-34272.6" + process $proc$libresoc.v:34264$1217 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:33797.5-33797.29" + attribute \src "libresoc.v:34265.5-34265.29" switch \initial - attribute \src "libresoc.v:33797.9-33797.17" + attribute \src "libresoc.v:34265.9-34265.17" case 1'1 case end @@ -51642,14 +52125,14 @@ module \branch0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 end - attribute \src "libresoc.v:33805.3-33813.6" - process $proc$libresoc.v:33805$1220 + attribute \src "libresoc.v:34273.3-34281.6" + process $proc$libresoc.v:34273$1220 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:33806.5-33806.29" + attribute \src "libresoc.v:34274.5-34274.29" switch \initial - attribute \src "libresoc.v:33806.9-33806.17" + attribute \src "libresoc.v:34274.9-34274.17" case 1'1 case end @@ -51665,14 +52148,14 @@ module \branch0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 end - attribute \src "libresoc.v:33814.3-33822.6" - process $proc$libresoc.v:33814$1223 + attribute \src "libresoc.v:34282.3-34290.6" + process $proc$libresoc.v:34282$1223 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:33815.5-33815.29" + attribute \src "libresoc.v:34283.5-34283.29" switch \initial - attribute \src "libresoc.v:33815.9-33815.17" + attribute \src "libresoc.v:34283.9-34283.17" case 1'1 case end @@ -51688,14 +52171,14 @@ module \branch0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 end - attribute \src "libresoc.v:33823.3-33831.6" - process $proc$libresoc.v:33823$1226 + attribute \src "libresoc.v:34291.3-34299.6" + process $proc$libresoc.v:34291$1226 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:33824.5-33824.29" + attribute \src "libresoc.v:34292.5-34292.29" switch \initial - attribute \src "libresoc.v:33824.9-33824.17" + attribute \src "libresoc.v:34292.9-34292.17" case 1'1 case end @@ -51711,14 +52194,14 @@ module \branch0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 end - attribute \src "libresoc.v:33832.3-33840.6" - process $proc$libresoc.v:33832$1229 + attribute \src "libresoc.v:34300.3-34308.6" + process $proc$libresoc.v:34300$1229 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:33833.5-33833.29" + attribute \src "libresoc.v:34301.5-34301.29" switch \initial - attribute \src "libresoc.v:33833.9-33833.17" + attribute \src "libresoc.v:34301.9-34301.17" case 1'1 case end @@ -51734,14 +52217,14 @@ module \branch0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 end - attribute \src "libresoc.v:33841.3-33849.6" - process $proc$libresoc.v:33841$1232 + attribute \src "libresoc.v:34309.3-34317.6" + process $proc$libresoc.v:34309$1232 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:33842.5-33842.29" + attribute \src "libresoc.v:34310.5-34310.29" switch \initial - attribute \src "libresoc.v:33842.9-33842.17" + attribute \src "libresoc.v:34310.9-34310.17" case 1'1 case end @@ -51757,14 +52240,14 @@ module \branch0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 end - attribute \src "libresoc.v:33850.3-33858.6" - process $proc$libresoc.v:33850$1235 + attribute \src "libresoc.v:34318.3-34326.6" + process $proc$libresoc.v:34318$1235 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:33851.5-33851.29" + attribute \src "libresoc.v:34319.5-34319.29" switch \initial - attribute \src "libresoc.v:33851.9-33851.17" + attribute \src "libresoc.v:34319.9-34319.17" case 1'1 case end @@ -51780,8 +52263,8 @@ module \branch0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 end - attribute \src "libresoc.v:33859.3-33883.6" - process $proc$libresoc.v:33859$1238 + attribute \src "libresoc.v:34327.3-34351.6" + process $proc$libresoc.v:34327$1238 assign { } { } assign { } { } assign { } { } @@ -51799,7 +52282,7 @@ module \branch0 assign { } { } assign { } { } assign $0\alu_branch0_br_op__cia$next[63:0]$1239 $1\alu_branch0_br_op__cia$next[63:0]$1247 - assign $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 + assign $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 assign { } { } assign { } { } assign $0\alu_branch0_br_op__insn$next[31:0]$1243 $1\alu_branch0_br_op__insn$next[31:0]$1251 @@ -51808,9 +52291,9 @@ module \branch0 assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:33860.5-33860.29" + attribute \src "libresoc.v:34328.5-34328.29" switch \initial - attribute \src "libresoc.v:33860.9-33860.17" + attribute \src "libresoc.v:34328.9-34328.17" case 1'1 case end @@ -51826,10 +52309,10 @@ module \branch0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } case assign $1\alu_branch0_br_op__cia$next[63:0]$1247 \alu_branch0_br_op__cia - assign $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 \alu_branch0_br_op__fn_unit + assign $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 \alu_branch0_br_op__fn_unit assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 \alu_branch0_br_op__imm_data__data assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 \alu_branch0_br_op__imm_data__ok assign $1\alu_branch0_br_op__insn$next[31:0]$1251 \alu_branch0_br_op__insn @@ -51851,7 +52334,7 @@ module \branch0 end sync always update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1239 - update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 + update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1243 @@ -51859,8 +52342,8 @@ module \branch0 update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 end - attribute \src "libresoc.v:33884.3-33905.6" - process $proc$libresoc.v:33884$1257 + attribute \src "libresoc.v:34352.3-34373.6" + process $proc$libresoc.v:34352$1257 assign { } { } assign { } { } assign { } { } @@ -51870,9 +52353,9 @@ module \branch0 assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 assign { } { } assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:33885.5-33885.29" + attribute \src "libresoc.v:34353.5-34353.29" switch \initial - attribute \src "libresoc.v:33885.9-33885.17" + attribute \src "libresoc.v:34353.9-34353.17" case 1'1 case end @@ -51911,8 +52394,8 @@ module \branch0 update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 end - attribute \src "libresoc.v:33906.3-33927.6" - process $proc$libresoc.v:33906$1265 + attribute \src "libresoc.v:34374.3-34395.6" + process $proc$libresoc.v:34374$1265 assign { } { } assign { } { } assign { } { } @@ -51922,9 +52405,9 @@ module \branch0 assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 assign { } { } assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:33907.5-33907.29" + attribute \src "libresoc.v:34375.5-34375.29" switch \initial - attribute \src "libresoc.v:33907.9-33907.17" + attribute \src "libresoc.v:34375.9-34375.17" case 1'1 case end @@ -51963,8 +52446,8 @@ module \branch0 update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 end - attribute \src "libresoc.v:33928.3-33949.6" - process $proc$libresoc.v:33928$1273 + attribute \src "libresoc.v:34396.3-34417.6" + process $proc$libresoc.v:34396$1273 assign { } { } assign { } { } assign { } { } @@ -51974,9 +52457,9 @@ module \branch0 assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 assign { } { } assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:33929.5-33929.29" + attribute \src "libresoc.v:34397.5-34397.29" switch \initial - attribute \src "libresoc.v:33929.9-33929.17" + attribute \src "libresoc.v:34397.9-34397.17" case 1'1 case end @@ -52015,18 +52498,18 @@ module \branch0 update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 end - attribute \src "libresoc.v:33950.3-33959.6" - process $proc$libresoc.v:33950$1281 + attribute \src "libresoc.v:34418.3-34427.6" + process $proc$libresoc.v:34418$1281 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:33951.5-33951.29" + attribute \src "libresoc.v:34419.5-34419.29" switch \initial - attribute \src "libresoc.v:33951.9-33951.17" + attribute \src "libresoc.v:34419.9-34419.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -52038,18 +52521,18 @@ module \branch0 sync always update \src_r0$next $0\src_r0$next[63:0]$1282 end - attribute \src "libresoc.v:33960.3-33969.6" - process $proc$libresoc.v:33960$1284 + attribute \src "libresoc.v:34428.3-34437.6" + process $proc$libresoc.v:34428$1284 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:33961.5-33961.29" + attribute \src "libresoc.v:34429.5-34429.29" switch \initial - attribute \src "libresoc.v:33961.9-33961.17" + attribute \src "libresoc.v:34429.9-34429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -52061,18 +52544,18 @@ module \branch0 sync always update \src_r1$next $0\src_r1$next[63:0]$1285 end - attribute \src "libresoc.v:33970.3-33979.6" - process $proc$libresoc.v:33970$1287 + attribute \src "libresoc.v:34438.3-34447.6" + process $proc$libresoc.v:34438$1287 assign { } { } assign { } { } assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:33971.5-33971.29" + attribute \src "libresoc.v:34439.5-34439.29" switch \initial - attribute \src "libresoc.v:33971.9-33971.17" + attribute \src "libresoc.v:34439.9-34439.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -52084,14 +52567,14 @@ module \branch0 sync always update \src_r2$next $0\src_r2$next[3:0]$1288 end - attribute \src "libresoc.v:33980.3-33988.6" - process $proc$libresoc.v:33980$1290 + attribute \src "libresoc.v:34448.3-34456.6" + process $proc$libresoc.v:34448$1290 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:33981.5-33981.29" + attribute \src "libresoc.v:34449.5-34449.29" switch \initial - attribute \src "libresoc.v:33981.9-33981.17" + attribute \src "libresoc.v:34449.9-34449.17" case 1'1 case end @@ -52107,14 +52590,14 @@ module \branch0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 end - attribute \src "libresoc.v:33989.3-33997.6" - process $proc$libresoc.v:33989$1293 + attribute \src "libresoc.v:34457.3-34465.6" + process $proc$libresoc.v:34457$1293 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:33990.5-33990.29" + attribute \src "libresoc.v:34458.5-34458.29" switch \initial - attribute \src "libresoc.v:33990.9-33990.17" + attribute \src "libresoc.v:34458.9-34458.17" case 1'1 case end @@ -52130,14 +52613,14 @@ module \branch0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 end - attribute \src "libresoc.v:33998.3-34007.6" - process $proc$libresoc.v:33998$1296 + attribute \src "libresoc.v:34466.3-34475.6" + process $proc$libresoc.v:34466$1296 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:33999.5-33999.29" + attribute \src "libresoc.v:34467.5-34467.29" switch \initial - attribute \src "libresoc.v:33999.9-33999.17" + attribute \src "libresoc.v:34467.9-34467.17" case 1'1 case end @@ -52153,14 +52636,14 @@ module \branch0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:34008.3-34017.6" - process $proc$libresoc.v:34008$1297 + attribute \src "libresoc.v:34476.3-34485.6" + process $proc$libresoc.v:34476$1297 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:34009.5-34009.29" + attribute \src "libresoc.v:34477.5-34477.29" switch \initial - attribute \src "libresoc.v:34009.9-34009.17" + attribute \src "libresoc.v:34477.9-34477.17" case 1'1 case end @@ -52176,14 +52659,14 @@ module \branch0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:34018.3-34027.6" - process $proc$libresoc.v:34018$1298 + attribute \src "libresoc.v:34486.3-34495.6" + process $proc$libresoc.v:34486$1298 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:34019.5-34019.29" + attribute \src "libresoc.v:34487.5-34487.29" switch \initial - attribute \src "libresoc.v:34019.9-34019.17" + attribute \src "libresoc.v:34487.9-34487.17" case 1'1 case end @@ -52199,14 +52682,14 @@ module \branch0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:34028.3-34036.6" - process $proc$libresoc.v:34028$1299 + attribute \src "libresoc.v:34496.3-34504.6" + process $proc$libresoc.v:34496$1299 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:34029.5-34029.29" + attribute \src "libresoc.v:34497.5-34497.29" switch \initial - attribute \src "libresoc.v:34029.9-34029.17" + attribute \src "libresoc.v:34497.9-34497.17" case 1'1 case end @@ -52222,63 +52705,63 @@ module \branch0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1300 end - connect \$5 $reduce_and$libresoc.v:33565$1118_Y - connect \$99 $and$libresoc.v:33566$1119_Y - connect \$101 $and$libresoc.v:33567$1120_Y - connect \$103 $and$libresoc.v:33568$1121_Y - connect \$105 $and$libresoc.v:33569$1122_Y - connect \$107 $and$libresoc.v:33570$1123_Y - connect \$109 $and$libresoc.v:33571$1124_Y - connect \$111 $and$libresoc.v:33572$1125_Y - connect \$113 $and$libresoc.v:33573$1126_Y - connect \$115 $and$libresoc.v:33574$1127_Y - connect \$11 $and$libresoc.v:33575$1128_Y - connect \$13 $not$libresoc.v:33576$1129_Y - connect \$15 $and$libresoc.v:33577$1130_Y - connect \$17 $not$libresoc.v:33578$1131_Y - connect \$19 $and$libresoc.v:33579$1132_Y - connect \$21 $and$libresoc.v:33580$1133_Y - connect \$25 $not$libresoc.v:33581$1134_Y - connect \$27 $and$libresoc.v:33582$1135_Y - connect \$24 $reduce_or$libresoc.v:33583$1136_Y - connect \$23 $not$libresoc.v:33584$1137_Y - connect \$31 $and$libresoc.v:33585$1138_Y - connect \$33 $reduce_or$libresoc.v:33586$1139_Y - connect \$35 $reduce_or$libresoc.v:33587$1140_Y - connect \$37 $or$libresoc.v:33588$1141_Y - connect \$3 $and$libresoc.v:33589$1142_Y - connect \$39 $not$libresoc.v:33590$1143_Y - connect \$41 $and$libresoc.v:33591$1144_Y - connect \$43 $and$libresoc.v:33592$1145_Y - connect \$45 $eq$libresoc.v:33593$1146_Y - connect \$47 $and$libresoc.v:33594$1147_Y - connect \$49 $eq$libresoc.v:33595$1148_Y - connect \$51 $and$libresoc.v:33596$1149_Y - connect \$53 $and$libresoc.v:33597$1150_Y - connect \$55 $and$libresoc.v:33598$1151_Y - connect \$57 $or$libresoc.v:33599$1152_Y - connect \$59 $or$libresoc.v:33600$1153_Y - connect \$61 $or$libresoc.v:33601$1154_Y - connect \$63 $or$libresoc.v:33602$1155_Y - connect \$65 $and$libresoc.v:33603$1156_Y - connect \$67 $and$libresoc.v:33604$1157_Y - connect \$6 $not$libresoc.v:33605$1158_Y - connect \$69 $or$libresoc.v:33606$1159_Y - connect \$71 $and$libresoc.v:33607$1160_Y - connect \$73 $and$libresoc.v:33608$1161_Y - connect \$75 $and$libresoc.v:33609$1162_Y - connect \$77 $ternary$libresoc.v:33610$1163_Y - connect \$79 $ternary$libresoc.v:33611$1164_Y - connect \$81 $ternary$libresoc.v:33612$1165_Y - connect \$83 $ternary$libresoc.v:33613$1166_Y - connect \$85 $ternary$libresoc.v:33614$1167_Y - connect \$87 $and$libresoc.v:33615$1168_Y - connect \$8 $or$libresoc.v:33616$1169_Y - connect \$89 $and$libresoc.v:33617$1170_Y - connect \$91 $and$libresoc.v:33618$1171_Y - connect \$93 $not$libresoc.v:33619$1172_Y - connect \$95 $and$libresoc.v:33620$1173_Y - connect \$97 $not$libresoc.v:33621$1174_Y + connect \$5 $reduce_and$libresoc.v:34033$1118_Y + connect \$99 $and$libresoc.v:34034$1119_Y + connect \$101 $and$libresoc.v:34035$1120_Y + connect \$103 $and$libresoc.v:34036$1121_Y + connect \$105 $and$libresoc.v:34037$1122_Y + connect \$107 $and$libresoc.v:34038$1123_Y + connect \$109 $and$libresoc.v:34039$1124_Y + connect \$111 $and$libresoc.v:34040$1125_Y + connect \$113 $and$libresoc.v:34041$1126_Y + connect \$115 $and$libresoc.v:34042$1127_Y + connect \$11 $and$libresoc.v:34043$1128_Y + connect \$13 $not$libresoc.v:34044$1129_Y + connect \$15 $and$libresoc.v:34045$1130_Y + connect \$17 $not$libresoc.v:34046$1131_Y + connect \$19 $and$libresoc.v:34047$1132_Y + connect \$21 $and$libresoc.v:34048$1133_Y + connect \$25 $not$libresoc.v:34049$1134_Y + connect \$27 $and$libresoc.v:34050$1135_Y + connect \$24 $reduce_or$libresoc.v:34051$1136_Y + connect \$23 $not$libresoc.v:34052$1137_Y + connect \$31 $and$libresoc.v:34053$1138_Y + connect \$33 $reduce_or$libresoc.v:34054$1139_Y + connect \$35 $reduce_or$libresoc.v:34055$1140_Y + connect \$37 $or$libresoc.v:34056$1141_Y + connect \$3 $and$libresoc.v:34057$1142_Y + connect \$39 $not$libresoc.v:34058$1143_Y + connect \$41 $and$libresoc.v:34059$1144_Y + connect \$43 $and$libresoc.v:34060$1145_Y + connect \$45 $eq$libresoc.v:34061$1146_Y + connect \$47 $and$libresoc.v:34062$1147_Y + connect \$49 $eq$libresoc.v:34063$1148_Y + connect \$51 $and$libresoc.v:34064$1149_Y + connect \$53 $and$libresoc.v:34065$1150_Y + connect \$55 $and$libresoc.v:34066$1151_Y + connect \$57 $or$libresoc.v:34067$1152_Y + connect \$59 $or$libresoc.v:34068$1153_Y + connect \$61 $or$libresoc.v:34069$1154_Y + connect \$63 $or$libresoc.v:34070$1155_Y + connect \$65 $and$libresoc.v:34071$1156_Y + connect \$67 $and$libresoc.v:34072$1157_Y + connect \$6 $not$libresoc.v:34073$1158_Y + connect \$69 $or$libresoc.v:34074$1159_Y + connect \$71 $and$libresoc.v:34075$1160_Y + connect \$73 $and$libresoc.v:34076$1161_Y + connect \$75 $and$libresoc.v:34077$1162_Y + connect \$77 $ternary$libresoc.v:34078$1163_Y + connect \$79 $ternary$libresoc.v:34079$1164_Y + connect \$81 $ternary$libresoc.v:34080$1165_Y + connect \$83 $ternary$libresoc.v:34081$1166_Y + connect \$85 $ternary$libresoc.v:34082$1167_Y + connect \$87 $and$libresoc.v:34083$1168_Y + connect \$8 $or$libresoc.v:34084$1169_Y + connect \$89 $and$libresoc.v:34085$1170_Y + connect \$91 $and$libresoc.v:34086$1171_Y + connect \$93 $not$libresoc.v:34087$1172_Y + connect \$95 $and$libresoc.v:34088$1173_Y + connect \$97 $not$libresoc.v:34089$1174_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -52310,75 +52793,75 @@ module \branch0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:34071.1-34129.10" +attribute \src "libresoc.v:34539.1-34597.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" attribute \generator "nMigen" module \busy_l - attribute \src "libresoc.v:34072.7-34072.20" + attribute \src "libresoc.v:34540.7-34540.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34117.3-34125.6" + attribute \src "libresoc.v:34585.3-34593.6" wire $0\q_int$next[0:0]$1345 - attribute \src "libresoc.v:34115.3-34116.27" + attribute \src "libresoc.v:34583.3-34584.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:34117.3-34125.6" + attribute \src "libresoc.v:34585.3-34593.6" wire $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34096.7-34096.19" + attribute \src "libresoc.v:34564.7-34564.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:34107.17-34107.96" - wire $and$libresoc.v:34107$1335_Y - attribute \src "libresoc.v:34112.17-34112.96" - wire $and$libresoc.v:34112$1340_Y - attribute \src "libresoc.v:34109.18-34109.94" - wire $not$libresoc.v:34109$1337_Y - attribute \src "libresoc.v:34111.17-34111.93" - wire $not$libresoc.v:34111$1339_Y - attribute \src "libresoc.v:34114.17-34114.93" - wire $not$libresoc.v:34114$1342_Y - attribute \src "libresoc.v:34108.18-34108.99" - wire $or$libresoc.v:34108$1336_Y - attribute \src "libresoc.v:34110.18-34110.100" - wire $or$libresoc.v:34110$1338_Y - attribute \src "libresoc.v:34113.17-34113.98" - wire $or$libresoc.v:34113$1341_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:34575.17-34575.96" + wire $and$libresoc.v:34575$1335_Y + attribute \src "libresoc.v:34580.17-34580.96" + wire $and$libresoc.v:34580$1340_Y + attribute \src "libresoc.v:34577.18-34577.94" + wire $not$libresoc.v:34577$1337_Y + attribute \src "libresoc.v:34579.17-34579.93" + wire $not$libresoc.v:34579$1339_Y + attribute \src "libresoc.v:34582.17-34582.93" + wire $not$libresoc.v:34582$1342_Y + attribute \src "libresoc.v:34576.18-34576.99" + wire $or$libresoc.v:34576$1336_Y + attribute \src "libresoc.v:34578.18-34578.100" + wire $or$libresoc.v:34578$1338_Y + attribute \src "libresoc.v:34581.17-34581.98" + wire $or$libresoc.v:34581$1341_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:34072.7-34072.15" + attribute \src "libresoc.v:34540.7-34540.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:34107$1335 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:34575$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52386,10 +52869,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:34107$1335_Y + connect \Y $and$libresoc.v:34575$1335_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:34112$1340 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:34580$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52397,34 +52880,34 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:34112$1340_Y + connect \Y $and$libresoc.v:34580$1340_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:34109$1337 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:34577$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_busy - connect \Y $not$libresoc.v:34109$1337_Y + connect \Y $not$libresoc.v:34577$1337_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:34111$1339 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:34579$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:34111$1339_Y + connect \Y $not$libresoc.v:34579$1339_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:34114$1342 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:34582$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:34114$1342_Y + connect \Y $not$libresoc.v:34582$1342_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:34108$1336 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:34576$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52432,10 +52915,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_busy - connect \Y $or$libresoc.v:34108$1336_Y + connect \Y $or$libresoc.v:34576$1336_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:34110$1338 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:34578$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52443,10 +52926,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_busy connect \B \q_int - connect \Y $or$libresoc.v:34110$1338_Y + connect \Y $or$libresoc.v:34578$1338_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:34113$1341 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:34581$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52454,39 +52937,39 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_busy - connect \Y $or$libresoc.v:34113$1341_Y + connect \Y $or$libresoc.v:34581$1341_Y end - attribute \src "libresoc.v:34072.7-34072.20" - process $proc$libresoc.v:34072$1347 + attribute \src "libresoc.v:34540.7-34540.20" + process $proc$libresoc.v:34540$1347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:34096.7-34096.19" - process $proc$libresoc.v:34096$1348 + attribute \src "libresoc.v:34564.7-34564.19" + process $proc$libresoc.v:34564$1348 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:34115.3-34116.27" - process $proc$libresoc.v:34115$1343 + attribute \src "libresoc.v:34583.3-34584.27" + process $proc$libresoc.v:34583$1343 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:34117.3-34125.6" - process $proc$libresoc.v:34117$1344 + attribute \src "libresoc.v:34585.3-34593.6" + process $proc$libresoc.v:34585$1344 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34118.5-34118.29" + attribute \src "libresoc.v:34586.5-34586.29" switch \initial - attribute \src "libresoc.v:34118.9-34118.17" + attribute \src "libresoc.v:34586.9-34586.17" case 1'1 case end @@ -52502,909 +52985,909 @@ module \busy_l sync always update \q_int$next $0\q_int$next[0:0]$1345 end - connect \$9 $and$libresoc.v:34107$1335_Y - connect \$11 $or$libresoc.v:34108$1336_Y - connect \$13 $not$libresoc.v:34109$1337_Y - connect \$15 $or$libresoc.v:34110$1338_Y - connect \$1 $not$libresoc.v:34111$1339_Y - connect \$3 $and$libresoc.v:34112$1340_Y - connect \$5 $or$libresoc.v:34113$1341_Y - connect \$7 $not$libresoc.v:34114$1342_Y + connect \$9 $and$libresoc.v:34575$1335_Y + connect \$11 $or$libresoc.v:34576$1336_Y + connect \$13 $not$libresoc.v:34577$1337_Y + connect \$15 $or$libresoc.v:34578$1338_Y + connect \$1 $not$libresoc.v:34579$1339_Y + connect \$3 $and$libresoc.v:34580$1340_Y + connect \$5 $or$libresoc.v:34581$1341_Y + connect \$7 $not$libresoc.v:34582$1342_Y connect \qlq_busy \$15 connect \qn_busy \$13 connect \q_busy \$11 end -attribute \src "libresoc.v:34133.1-35741.10" +attribute \src "libresoc.v:34601.1-36209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" attribute \generator "nMigen" module \clz - attribute \src "libresoc.v:34608.3-34622.6" + attribute \src "libresoc.v:35076.3-35090.6" wire width 2 $0\cnt_1_0[1:0] - attribute \src "libresoc.v:34698.3-34712.6" + attribute \src "libresoc.v:35166.3-35180.6" wire width 2 $0\cnt_1_10[1:0] - attribute \src "libresoc.v:34713.3-34727.6" + attribute \src "libresoc.v:35181.3-35195.6" wire width 2 $0\cnt_1_11[1:0] - attribute \src "libresoc.v:34728.3-34742.6" + attribute \src "libresoc.v:35196.3-35210.6" wire width 2 $0\cnt_1_12[1:0] - attribute \src "libresoc.v:34743.3-34757.6" + attribute \src "libresoc.v:35211.3-35225.6" wire width 2 $0\cnt_1_13[1:0] - attribute \src "libresoc.v:34758.3-34772.6" + attribute \src "libresoc.v:35226.3-35240.6" wire width 2 $0\cnt_1_14[1:0] - attribute \src "libresoc.v:34788.3-34802.6" + attribute \src "libresoc.v:35256.3-35270.6" wire width 2 $0\cnt_1_15[1:0] - attribute \src "libresoc.v:34803.3-34817.6" + attribute \src "libresoc.v:35271.3-35285.6" wire width 2 $0\cnt_1_16[1:0] - attribute \src "libresoc.v:34818.3-34832.6" + attribute \src "libresoc.v:35286.3-35300.6" wire width 2 $0\cnt_1_17[1:0] - attribute \src "libresoc.v:34833.3-34847.6" + attribute \src "libresoc.v:35301.3-35315.6" wire width 2 $0\cnt_1_18[1:0] - attribute \src "libresoc.v:34848.3-34862.6" + attribute \src "libresoc.v:35316.3-35330.6" wire width 2 $0\cnt_1_19[1:0] - attribute \src "libresoc.v:34773.3-34787.6" + attribute \src "libresoc.v:35241.3-35255.6" wire width 2 $0\cnt_1_1[1:0] - attribute \src "libresoc.v:34863.3-34877.6" + attribute \src "libresoc.v:35331.3-35345.6" wire width 2 $0\cnt_1_20[1:0] - attribute \src "libresoc.v:34878.3-34892.6" + attribute \src "libresoc.v:35346.3-35360.6" wire width 2 $0\cnt_1_21[1:0] - attribute \src "libresoc.v:34893.3-34907.6" + attribute \src "libresoc.v:35361.3-35375.6" wire width 2 $0\cnt_1_22[1:0] - attribute \src "libresoc.v:34908.3-34922.6" + attribute \src "libresoc.v:35376.3-35390.6" wire width 2 $0\cnt_1_23[1:0] - attribute \src "libresoc.v:34923.3-34937.6" + attribute \src "libresoc.v:35391.3-35405.6" wire width 2 $0\cnt_1_24[1:0] - attribute \src "libresoc.v:34953.3-34967.6" + attribute \src "libresoc.v:35421.3-35435.6" wire width 2 $0\cnt_1_25[1:0] - attribute \src "libresoc.v:34968.3-34982.6" + attribute \src "libresoc.v:35436.3-35450.6" wire width 2 $0\cnt_1_26[1:0] - attribute \src "libresoc.v:34983.3-34997.6" + attribute \src "libresoc.v:35451.3-35465.6" wire width 2 $0\cnt_1_27[1:0] - attribute \src "libresoc.v:34998.3-35012.6" + attribute \src "libresoc.v:35466.3-35480.6" wire width 2 $0\cnt_1_28[1:0] - attribute \src "libresoc.v:35013.3-35027.6" + attribute \src "libresoc.v:35481.3-35495.6" wire width 2 $0\cnt_1_29[1:0] - attribute \src "libresoc.v:34938.3-34952.6" + attribute \src "libresoc.v:35406.3-35420.6" wire width 2 $0\cnt_1_2[1:0] - attribute \src "libresoc.v:35028.3-35042.6" + attribute \src "libresoc.v:35496.3-35510.6" wire width 2 $0\cnt_1_30[1:0] - attribute \src "libresoc.v:35043.3-35057.6" + attribute \src "libresoc.v:35511.3-35525.6" wire width 2 $0\cnt_1_31[1:0] - attribute \src "libresoc.v:35178.3-35192.6" + attribute \src "libresoc.v:35646.3-35660.6" wire width 2 $0\cnt_1_3[1:0] - attribute \src "libresoc.v:35593.3-35607.6" + attribute \src "libresoc.v:36061.3-36075.6" wire width 2 $0\cnt_1_4[1:0] - attribute \src "libresoc.v:34623.3-34637.6" + attribute \src "libresoc.v:35091.3-35105.6" wire width 2 $0\cnt_1_5[1:0] - attribute \src "libresoc.v:34638.3-34652.6" + attribute \src "libresoc.v:35106.3-35120.6" wire width 2 $0\cnt_1_6[1:0] - attribute \src "libresoc.v:34653.3-34667.6" + attribute \src "libresoc.v:35121.3-35135.6" wire width 2 $0\cnt_1_7[1:0] - attribute \src "libresoc.v:34668.3-34682.6" + attribute \src "libresoc.v:35136.3-35150.6" wire width 2 $0\cnt_1_8[1:0] - attribute \src "libresoc.v:34683.3-34697.6" + attribute \src "libresoc.v:35151.3-35165.6" wire width 2 $0\cnt_1_9[1:0] - attribute \src "libresoc.v:35058.3-35077.6" + attribute \src "libresoc.v:35526.3-35545.6" wire width 3 $0\cnt_2_0[2:0] - attribute \src "libresoc.v:35158.3-35177.6" + attribute \src "libresoc.v:35626.3-35645.6" wire width 3 $0\cnt_2_10[2:0] - attribute \src "libresoc.v:35193.3-35212.6" + attribute \src "libresoc.v:35661.3-35680.6" wire width 3 $0\cnt_2_12[2:0] - attribute \src "libresoc.v:35213.3-35232.6" + attribute \src "libresoc.v:35681.3-35700.6" wire width 3 $0\cnt_2_14[2:0] - attribute \src "libresoc.v:35233.3-35252.6" + attribute \src "libresoc.v:35701.3-35720.6" wire width 3 $0\cnt_2_16[2:0] - attribute \src "libresoc.v:35253.3-35272.6" + attribute \src "libresoc.v:35721.3-35740.6" wire width 3 $0\cnt_2_18[2:0] - attribute \src "libresoc.v:35273.3-35292.6" + attribute \src "libresoc.v:35741.3-35760.6" wire width 3 $0\cnt_2_20[2:0] - attribute \src "libresoc.v:35293.3-35312.6" + attribute \src "libresoc.v:35761.3-35780.6" wire width 3 $0\cnt_2_22[2:0] - attribute \src "libresoc.v:35313.3-35332.6" + attribute \src "libresoc.v:35781.3-35800.6" wire width 3 $0\cnt_2_24[2:0] - attribute \src "libresoc.v:35333.3-35352.6" + attribute \src "libresoc.v:35801.3-35820.6" wire width 3 $0\cnt_2_26[2:0] - attribute \src "libresoc.v:35353.3-35372.6" + attribute \src "libresoc.v:35821.3-35840.6" wire width 3 $0\cnt_2_28[2:0] - attribute \src "libresoc.v:35078.3-35097.6" + attribute \src "libresoc.v:35546.3-35565.6" wire width 3 $0\cnt_2_2[2:0] - attribute \src "libresoc.v:35373.3-35392.6" + attribute \src "libresoc.v:35841.3-35860.6" wire width 3 $0\cnt_2_30[2:0] - attribute \src "libresoc.v:35098.3-35117.6" + attribute \src "libresoc.v:35566.3-35585.6" wire width 3 $0\cnt_2_4[2:0] - attribute \src "libresoc.v:35118.3-35137.6" + attribute \src "libresoc.v:35586.3-35605.6" wire width 3 $0\cnt_2_6[2:0] - attribute \src "libresoc.v:35138.3-35157.6" + attribute \src "libresoc.v:35606.3-35625.6" wire width 3 $0\cnt_2_8[2:0] - attribute \src "libresoc.v:35393.3-35412.6" + attribute \src "libresoc.v:35861.3-35880.6" wire width 4 $0\cnt_3_0[3:0] - attribute \src "libresoc.v:35493.3-35512.6" + attribute \src "libresoc.v:35961.3-35980.6" wire width 4 $0\cnt_3_10[3:0] - attribute \src "libresoc.v:35513.3-35532.6" + attribute \src "libresoc.v:35981.3-36000.6" wire width 4 $0\cnt_3_12[3:0] - attribute \src "libresoc.v:35533.3-35552.6" + attribute \src "libresoc.v:36001.3-36020.6" wire width 4 $0\cnt_3_14[3:0] - attribute \src "libresoc.v:35413.3-35432.6" + attribute \src "libresoc.v:35881.3-35900.6" wire width 4 $0\cnt_3_2[3:0] - attribute \src "libresoc.v:35433.3-35452.6" + attribute \src "libresoc.v:35901.3-35920.6" wire width 4 $0\cnt_3_4[3:0] - attribute \src "libresoc.v:35453.3-35472.6" + attribute \src "libresoc.v:35921.3-35940.6" wire width 4 $0\cnt_3_6[3:0] - attribute \src "libresoc.v:35473.3-35492.6" + attribute \src "libresoc.v:35941.3-35960.6" wire width 4 $0\cnt_3_8[3:0] - attribute \src "libresoc.v:35553.3-35572.6" + attribute \src "libresoc.v:36021.3-36040.6" wire width 5 $0\cnt_4_0[4:0] - attribute \src "libresoc.v:35573.3-35592.6" + attribute \src "libresoc.v:36041.3-36060.6" wire width 5 $0\cnt_4_2[4:0] - attribute \src "libresoc.v:35608.3-35627.6" + attribute \src "libresoc.v:36076.3-36095.6" wire width 5 $0\cnt_4_4[4:0] - attribute \src "libresoc.v:35628.3-35647.6" + attribute \src "libresoc.v:36096.3-36115.6" wire width 5 $0\cnt_4_6[4:0] - attribute \src "libresoc.v:35648.3-35667.6" + attribute \src "libresoc.v:36116.3-36135.6" wire width 6 $0\cnt_5_0[5:0] - attribute \src "libresoc.v:35668.3-35687.6" + attribute \src "libresoc.v:36136.3-36155.6" wire width 6 $0\cnt_5_2[5:0] - attribute \src "libresoc.v:35688.3-35707.6" + attribute \src "libresoc.v:36156.3-36175.6" wire width 7 $0\cnt_6_0[6:0] - attribute \src "libresoc.v:34134.7-34134.20" + attribute \src "libresoc.v:34602.7-34602.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34608.3-34622.6" + attribute \src "libresoc.v:35076.3-35090.6" wire width 2 $1\cnt_1_0[1:0] - attribute \src "libresoc.v:34698.3-34712.6" + attribute \src "libresoc.v:35166.3-35180.6" wire width 2 $1\cnt_1_10[1:0] - attribute \src "libresoc.v:34713.3-34727.6" + attribute \src "libresoc.v:35181.3-35195.6" wire width 2 $1\cnt_1_11[1:0] - attribute \src "libresoc.v:34728.3-34742.6" + attribute \src "libresoc.v:35196.3-35210.6" wire width 2 $1\cnt_1_12[1:0] - attribute \src "libresoc.v:34743.3-34757.6" + attribute \src "libresoc.v:35211.3-35225.6" wire width 2 $1\cnt_1_13[1:0] - attribute \src "libresoc.v:34758.3-34772.6" + attribute \src "libresoc.v:35226.3-35240.6" wire width 2 $1\cnt_1_14[1:0] - attribute \src "libresoc.v:34788.3-34802.6" + attribute \src "libresoc.v:35256.3-35270.6" wire width 2 $1\cnt_1_15[1:0] - attribute \src "libresoc.v:34803.3-34817.6" + attribute \src "libresoc.v:35271.3-35285.6" wire width 2 $1\cnt_1_16[1:0] - attribute \src "libresoc.v:34818.3-34832.6" + attribute \src "libresoc.v:35286.3-35300.6" wire width 2 $1\cnt_1_17[1:0] - attribute \src "libresoc.v:34833.3-34847.6" + attribute \src "libresoc.v:35301.3-35315.6" wire width 2 $1\cnt_1_18[1:0] - attribute \src "libresoc.v:34848.3-34862.6" + attribute \src "libresoc.v:35316.3-35330.6" wire width 2 $1\cnt_1_19[1:0] - attribute \src "libresoc.v:34773.3-34787.6" + attribute \src "libresoc.v:35241.3-35255.6" wire width 2 $1\cnt_1_1[1:0] - attribute \src "libresoc.v:34863.3-34877.6" + attribute \src "libresoc.v:35331.3-35345.6" wire width 2 $1\cnt_1_20[1:0] - attribute \src "libresoc.v:34878.3-34892.6" + attribute \src "libresoc.v:35346.3-35360.6" wire width 2 $1\cnt_1_21[1:0] - attribute \src "libresoc.v:34893.3-34907.6" + attribute \src "libresoc.v:35361.3-35375.6" wire width 2 $1\cnt_1_22[1:0] - attribute \src "libresoc.v:34908.3-34922.6" + attribute \src "libresoc.v:35376.3-35390.6" wire width 2 $1\cnt_1_23[1:0] - attribute \src "libresoc.v:34923.3-34937.6" + attribute \src "libresoc.v:35391.3-35405.6" wire width 2 $1\cnt_1_24[1:0] - attribute \src "libresoc.v:34953.3-34967.6" + attribute \src "libresoc.v:35421.3-35435.6" wire width 2 $1\cnt_1_25[1:0] - attribute \src "libresoc.v:34968.3-34982.6" + attribute \src "libresoc.v:35436.3-35450.6" wire width 2 $1\cnt_1_26[1:0] - attribute \src "libresoc.v:34983.3-34997.6" + attribute \src "libresoc.v:35451.3-35465.6" wire width 2 $1\cnt_1_27[1:0] - attribute \src "libresoc.v:34998.3-35012.6" + attribute \src "libresoc.v:35466.3-35480.6" wire width 2 $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35013.3-35027.6" + attribute \src "libresoc.v:35481.3-35495.6" wire width 2 $1\cnt_1_29[1:0] - attribute \src "libresoc.v:34938.3-34952.6" + attribute \src "libresoc.v:35406.3-35420.6" wire width 2 $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35028.3-35042.6" + attribute \src "libresoc.v:35496.3-35510.6" wire width 2 $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35043.3-35057.6" + attribute \src "libresoc.v:35511.3-35525.6" wire width 2 $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35178.3-35192.6" + attribute \src "libresoc.v:35646.3-35660.6" wire width 2 $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35593.3-35607.6" + attribute \src "libresoc.v:36061.3-36075.6" wire width 2 $1\cnt_1_4[1:0] - attribute \src "libresoc.v:34623.3-34637.6" + attribute \src "libresoc.v:35091.3-35105.6" wire width 2 $1\cnt_1_5[1:0] - attribute \src "libresoc.v:34638.3-34652.6" + attribute \src "libresoc.v:35106.3-35120.6" wire width 2 $1\cnt_1_6[1:0] - attribute \src "libresoc.v:34653.3-34667.6" + attribute \src "libresoc.v:35121.3-35135.6" wire width 2 $1\cnt_1_7[1:0] - attribute \src "libresoc.v:34668.3-34682.6" + attribute \src "libresoc.v:35136.3-35150.6" wire width 2 $1\cnt_1_8[1:0] - attribute \src "libresoc.v:34683.3-34697.6" + attribute \src "libresoc.v:35151.3-35165.6" wire width 2 $1\cnt_1_9[1:0] - attribute \src "libresoc.v:35058.3-35077.6" + attribute \src "libresoc.v:35526.3-35545.6" wire width 3 $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35158.3-35177.6" + attribute \src "libresoc.v:35626.3-35645.6" wire width 3 $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35193.3-35212.6" + attribute \src "libresoc.v:35661.3-35680.6" wire width 3 $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35213.3-35232.6" + attribute \src "libresoc.v:35681.3-35700.6" wire width 3 $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35233.3-35252.6" + attribute \src "libresoc.v:35701.3-35720.6" wire width 3 $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35253.3-35272.6" + attribute \src "libresoc.v:35721.3-35740.6" wire width 3 $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35273.3-35292.6" + attribute \src "libresoc.v:35741.3-35760.6" wire width 3 $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35293.3-35312.6" + attribute \src "libresoc.v:35761.3-35780.6" wire width 3 $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35313.3-35332.6" + attribute \src "libresoc.v:35781.3-35800.6" wire width 3 $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35333.3-35352.6" + attribute \src "libresoc.v:35801.3-35820.6" wire width 3 $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35353.3-35372.6" + attribute \src "libresoc.v:35821.3-35840.6" wire width 3 $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35078.3-35097.6" + attribute \src "libresoc.v:35546.3-35565.6" wire width 3 $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35373.3-35392.6" + attribute \src "libresoc.v:35841.3-35860.6" wire width 3 $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35098.3-35117.6" + attribute \src "libresoc.v:35566.3-35585.6" wire width 3 $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35118.3-35137.6" + attribute \src "libresoc.v:35586.3-35605.6" wire width 3 $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35138.3-35157.6" + attribute \src "libresoc.v:35606.3-35625.6" wire width 3 $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35393.3-35412.6" + attribute \src "libresoc.v:35861.3-35880.6" wire width 4 $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35493.3-35512.6" + attribute \src "libresoc.v:35961.3-35980.6" wire width 4 $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35513.3-35532.6" + attribute \src "libresoc.v:35981.3-36000.6" wire width 4 $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35533.3-35552.6" + attribute \src "libresoc.v:36001.3-36020.6" wire width 4 $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35413.3-35432.6" + attribute \src "libresoc.v:35881.3-35900.6" wire width 4 $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35433.3-35452.6" + attribute \src "libresoc.v:35901.3-35920.6" wire width 4 $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35453.3-35472.6" + attribute \src "libresoc.v:35921.3-35940.6" wire width 4 $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35473.3-35492.6" + attribute \src "libresoc.v:35941.3-35960.6" wire width 4 $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35553.3-35572.6" + attribute \src "libresoc.v:36021.3-36040.6" wire width 5 $1\cnt_4_0[4:0] - attribute \src "libresoc.v:35573.3-35592.6" + attribute \src "libresoc.v:36041.3-36060.6" wire width 5 $1\cnt_4_2[4:0] - attribute \src "libresoc.v:35608.3-35627.6" + attribute \src "libresoc.v:36076.3-36095.6" wire width 5 $1\cnt_4_4[4:0] - attribute \src "libresoc.v:35628.3-35647.6" + attribute \src "libresoc.v:36096.3-36115.6" wire width 5 $1\cnt_4_6[4:0] - attribute \src "libresoc.v:35648.3-35667.6" + attribute \src "libresoc.v:36116.3-36135.6" wire width 6 $1\cnt_5_0[5:0] - attribute \src "libresoc.v:35668.3-35687.6" + attribute \src "libresoc.v:36136.3-36155.6" wire width 6 $1\cnt_5_2[5:0] - attribute \src "libresoc.v:35688.3-35707.6" + attribute \src "libresoc.v:36156.3-36175.6" wire width 7 $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35058.3-35077.6" + attribute \src "libresoc.v:35526.3-35545.6" wire width 3 $2\cnt_2_0[2:0] - attribute \src "libresoc.v:35158.3-35177.6" + attribute \src "libresoc.v:35626.3-35645.6" wire width 3 $2\cnt_2_10[2:0] - attribute \src "libresoc.v:35193.3-35212.6" + attribute \src "libresoc.v:35661.3-35680.6" wire width 3 $2\cnt_2_12[2:0] - attribute \src "libresoc.v:35213.3-35232.6" + attribute \src "libresoc.v:35681.3-35700.6" wire width 3 $2\cnt_2_14[2:0] - attribute \src "libresoc.v:35233.3-35252.6" + attribute \src "libresoc.v:35701.3-35720.6" wire width 3 $2\cnt_2_16[2:0] - attribute \src "libresoc.v:35253.3-35272.6" + attribute \src "libresoc.v:35721.3-35740.6" wire width 3 $2\cnt_2_18[2:0] - attribute \src "libresoc.v:35273.3-35292.6" + attribute \src "libresoc.v:35741.3-35760.6" wire width 3 $2\cnt_2_20[2:0] - attribute \src "libresoc.v:35293.3-35312.6" + attribute \src "libresoc.v:35761.3-35780.6" wire width 3 $2\cnt_2_22[2:0] - attribute \src "libresoc.v:35313.3-35332.6" + attribute \src "libresoc.v:35781.3-35800.6" wire width 3 $2\cnt_2_24[2:0] - attribute \src "libresoc.v:35333.3-35352.6" + attribute \src "libresoc.v:35801.3-35820.6" wire width 3 $2\cnt_2_26[2:0] - attribute \src "libresoc.v:35353.3-35372.6" + attribute \src "libresoc.v:35821.3-35840.6" wire width 3 $2\cnt_2_28[2:0] - attribute \src "libresoc.v:35078.3-35097.6" + attribute \src "libresoc.v:35546.3-35565.6" wire width 3 $2\cnt_2_2[2:0] - attribute \src "libresoc.v:35373.3-35392.6" + attribute \src "libresoc.v:35841.3-35860.6" wire width 3 $2\cnt_2_30[2:0] - attribute \src "libresoc.v:35098.3-35117.6" + attribute \src "libresoc.v:35566.3-35585.6" wire width 3 $2\cnt_2_4[2:0] - attribute \src "libresoc.v:35118.3-35137.6" + attribute \src "libresoc.v:35586.3-35605.6" wire width 3 $2\cnt_2_6[2:0] - attribute \src "libresoc.v:35138.3-35157.6" + attribute \src "libresoc.v:35606.3-35625.6" wire width 3 $2\cnt_2_8[2:0] - attribute \src "libresoc.v:35393.3-35412.6" + attribute \src "libresoc.v:35861.3-35880.6" wire width 4 $2\cnt_3_0[3:0] - attribute \src "libresoc.v:35493.3-35512.6" + attribute \src "libresoc.v:35961.3-35980.6" wire width 4 $2\cnt_3_10[3:0] - attribute \src "libresoc.v:35513.3-35532.6" + attribute \src "libresoc.v:35981.3-36000.6" wire width 4 $2\cnt_3_12[3:0] - attribute \src "libresoc.v:35533.3-35552.6" + attribute \src "libresoc.v:36001.3-36020.6" wire width 4 $2\cnt_3_14[3:0] - attribute \src "libresoc.v:35413.3-35432.6" + attribute \src "libresoc.v:35881.3-35900.6" wire width 4 $2\cnt_3_2[3:0] - attribute \src "libresoc.v:35433.3-35452.6" + attribute \src "libresoc.v:35901.3-35920.6" wire width 4 $2\cnt_3_4[3:0] - attribute \src "libresoc.v:35453.3-35472.6" + attribute \src "libresoc.v:35921.3-35940.6" wire width 4 $2\cnt_3_6[3:0] - attribute \src "libresoc.v:35473.3-35492.6" + attribute \src "libresoc.v:35941.3-35960.6" wire width 4 $2\cnt_3_8[3:0] - attribute \src "libresoc.v:35553.3-35572.6" + attribute \src "libresoc.v:36021.3-36040.6" wire width 5 $2\cnt_4_0[4:0] - attribute \src "libresoc.v:35573.3-35592.6" + attribute \src "libresoc.v:36041.3-36060.6" wire width 5 $2\cnt_4_2[4:0] - attribute \src "libresoc.v:35608.3-35627.6" + attribute \src "libresoc.v:36076.3-36095.6" wire width 5 $2\cnt_4_4[4:0] - attribute \src "libresoc.v:35628.3-35647.6" + attribute \src "libresoc.v:36096.3-36115.6" wire width 5 $2\cnt_4_6[4:0] - attribute \src "libresoc.v:35648.3-35667.6" + attribute \src "libresoc.v:36116.3-36135.6" wire width 6 $2\cnt_5_0[5:0] - attribute \src "libresoc.v:35668.3-35687.6" + attribute \src "libresoc.v:36136.3-36155.6" wire width 6 $2\cnt_5_2[5:0] - attribute \src "libresoc.v:35688.3-35707.6" + attribute \src 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"libresoc.v:35058.18-35058.107" + wire width 3 $pos$libresoc.v:35058$1424_Y + attribute \src "libresoc.v:35061.18-35061.107" + wire width 3 $pos$libresoc.v:35061$1427_Y + attribute \src "libresoc.v:35064.18-35064.107" + wire width 3 $pos$libresoc.v:35064$1430_Y + attribute \src "libresoc.v:35068.18-35068.107" + wire width 3 $pos$libresoc.v:35068$1434_Y + attribute \src "libresoc.v:35071.18-35071.107" + wire width 3 $pos$libresoc.v:35071$1437_Y + attribute \src "libresoc.v:35074.18-35074.107" + wire width 3 $pos$libresoc.v:35074$1440_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$129 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$131 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$133 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$135 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$137 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$139 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$141 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$143 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$145 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$147 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 5 \$149 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$151 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$153 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 5 \$155 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$157 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$159 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 5 \$161 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$163 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$165 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 5 \$167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$171 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 6 \$173 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$175 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$177 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 6 \$179 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$181 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$183 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 7 \$185 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$99 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 5 \cnt_4_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 5 \cnt_4_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 5 \cnt_4_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 5 \cnt_4_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 6 \cnt_5_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 6 \cnt_5_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 7 \cnt_6_0 - attribute \src "libresoc.v:34134.7-34134.15" + attribute \src "libresoc.v:34602.7-34602.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 7 output 1 \lz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair38 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair42 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair54 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair56 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" wire width 64 input 2 \sig_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34515$1349 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34983$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53412,10 +53895,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_2 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34515$1349_Y + connect \Y $eq$libresoc.v:34983$1349_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34516$1350 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34984$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53423,10 +53906,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_0 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34516$1350_Y + connect \Y $eq$libresoc.v:34984$1350_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34518$1352 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34986$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53434,10 +53917,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_6 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34518$1352_Y + connect \Y $eq$libresoc.v:34986$1352_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34519$1353 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34987$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53445,10 +53928,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_4 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34519$1353_Y + connect \Y $eq$libresoc.v:34987$1353_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34521$1355 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34989$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53456,10 +53939,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_10 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34521$1355_Y + connect \Y $eq$libresoc.v:34989$1355_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34522$1356 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34990$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53467,10 +53950,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_8 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34522$1356_Y + connect \Y $eq$libresoc.v:34990$1356_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34524$1358 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34992$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53478,10 +53961,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_14 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34524$1358_Y + connect \Y $eq$libresoc.v:34992$1358_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34525$1359 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34993$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53489,10 +53972,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_12 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34525$1359_Y + connect \Y $eq$libresoc.v:34993$1359_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34528$1362 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34996$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53500,10 +53983,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_18 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34528$1362_Y + connect \Y $eq$libresoc.v:34996$1362_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34529$1363 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34997$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53511,10 +53994,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_16 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34529$1363_Y + connect \Y $eq$libresoc.v:34997$1363_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34531$1365 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34999$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53522,10 +54005,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_22 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34531$1365_Y + connect \Y $eq$libresoc.v:34999$1365_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34532$1366 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35000$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53533,10 +54016,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_20 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34532$1366_Y + connect \Y $eq$libresoc.v:35000$1366_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34534$1368 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35002$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53544,10 +54027,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_26 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34534$1368_Y + connect \Y $eq$libresoc.v:35002$1368_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34535$1369 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35003$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53555,10 +54038,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_24 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34535$1369_Y + connect \Y $eq$libresoc.v:35003$1369_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34537$1371 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35005$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53566,10 +54049,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_5 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34537$1371_Y + connect \Y $eq$libresoc.v:35005$1371_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34538$1372 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35006$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53577,10 +54060,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_30 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34538$1372_Y + connect \Y $eq$libresoc.v:35006$1372_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34539$1373 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35007$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53588,10 +54071,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_28 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34539$1373_Y + connect \Y $eq$libresoc.v:35007$1373_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34541$1375 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35009$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53599,10 +54082,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_2 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34541$1375_Y + connect \Y $eq$libresoc.v:35009$1375_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34542$1376 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35010$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53610,10 +54093,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_0 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34542$1376_Y + connect \Y $eq$libresoc.v:35010$1376_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34544$1378 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35012$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53621,10 +54104,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_6 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34544$1378_Y + connect \Y $eq$libresoc.v:35012$1378_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34545$1379 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35013$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53632,10 +54115,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_4 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34545$1379_Y + connect \Y $eq$libresoc.v:35013$1379_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34547$1381 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35015$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53643,10 +54126,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_10 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34547$1381_Y + connect \Y $eq$libresoc.v:35015$1381_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34548$1382 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35016$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53654,10 +54137,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_4 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34548$1382_Y + connect \Y $eq$libresoc.v:35016$1382_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34549$1383 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35017$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53665,10 +54148,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_8 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34549$1383_Y + connect \Y $eq$libresoc.v:35017$1383_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34551$1385 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35019$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53676,10 +54159,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_14 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34551$1385_Y + connect \Y $eq$libresoc.v:35019$1385_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34552$1386 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35020$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53687,10 +54170,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_12 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34552$1386_Y + connect \Y $eq$libresoc.v:35020$1386_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34554$1388 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35022$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53698,10 +54181,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_2 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34554$1388_Y + connect \Y $eq$libresoc.v:35022$1388_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34555$1389 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35023$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53709,10 +54192,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_0 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34555$1389_Y + connect \Y $eq$libresoc.v:35023$1389_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34557$1391 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35025$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53720,10 +54203,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_6 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34557$1391_Y + connect \Y $eq$libresoc.v:35025$1391_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34558$1392 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35026$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53731,10 +54214,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_4 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34558$1392_Y + connect \Y $eq$libresoc.v:35026$1392_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34561$1395 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35029$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53742,10 +54225,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_2 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:34561$1395_Y + connect \Y $eq$libresoc.v:35029$1395_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34562$1396 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35030$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53753,10 +54236,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_0 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:34562$1396_Y + connect \Y $eq$libresoc.v:35030$1396_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34564$1398 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35032$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53764,10 +54247,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_1 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34564$1398_Y + connect \Y $eq$libresoc.v:35032$1398_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34565$1399 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35033$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53775,10 +54258,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_7 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34565$1399_Y + connect \Y $eq$libresoc.v:35033$1399_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34566$1400 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35034$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53786,10 +54269,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_6 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34566$1400_Y + connect \Y $eq$libresoc.v:35034$1400_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34568$1402 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35036$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53797,10 +54280,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_9 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34568$1402_Y + connect \Y $eq$libresoc.v:35036$1402_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34569$1403 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35037$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53808,10 +54291,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_8 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34569$1403_Y + connect \Y $eq$libresoc.v:35037$1403_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34571$1405 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35039$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53819,10 +54302,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_11 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34571$1405_Y + connect \Y $eq$libresoc.v:35039$1405_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34572$1406 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35040$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53830,10 +54313,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_10 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34572$1406_Y + connect \Y $eq$libresoc.v:35040$1406_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34574$1408 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35042$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53841,10 +54324,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_13 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34574$1408_Y + connect \Y $eq$libresoc.v:35042$1408_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34575$1409 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35043$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53852,10 +54335,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_0 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34575$1409_Y + connect \Y $eq$libresoc.v:35043$1409_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34576$1410 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35044$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53863,10 +54346,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_12 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34576$1410_Y + connect \Y $eq$libresoc.v:35044$1410_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34578$1412 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35046$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53874,10 +54357,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_15 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34578$1412_Y + connect \Y $eq$libresoc.v:35046$1412_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34579$1413 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35047$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53885,10 +54368,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_14 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34579$1413_Y + connect \Y $eq$libresoc.v:35047$1413_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34581$1415 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35049$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53896,10 +54379,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_17 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34581$1415_Y + connect \Y $eq$libresoc.v:35049$1415_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34582$1416 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35050$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53907,10 +54390,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_16 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34582$1416_Y + connect \Y $eq$libresoc.v:35050$1416_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34584$1418 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35052$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53918,10 +54401,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_19 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34584$1418_Y + connect \Y $eq$libresoc.v:35052$1418_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34585$1419 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35053$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53929,10 +54412,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_18 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34585$1419_Y + connect \Y $eq$libresoc.v:35053$1419_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34588$1422 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35056$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53940,10 +54423,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_21 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34588$1422_Y + connect \Y $eq$libresoc.v:35056$1422_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34589$1423 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35057$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53951,10 +54434,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_20 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34589$1423_Y + connect \Y $eq$libresoc.v:35057$1423_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34591$1425 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35059$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53962,10 +54445,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_23 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34591$1425_Y + connect \Y $eq$libresoc.v:35059$1425_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34592$1426 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35060$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53973,10 +54456,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_22 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34592$1426_Y + connect \Y $eq$libresoc.v:35060$1426_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34594$1428 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35062$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53984,10 +54467,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_25 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34594$1428_Y + connect \Y $eq$libresoc.v:35062$1428_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34595$1429 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35063$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53995,10 +54478,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_24 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34595$1429_Y + connect \Y $eq$libresoc.v:35063$1429_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34597$1431 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35065$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54006,10 +54489,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_3 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34597$1431_Y + connect \Y $eq$libresoc.v:35065$1431_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34598$1432 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35066$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54017,10 +54500,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_27 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34598$1432_Y + connect \Y $eq$libresoc.v:35066$1432_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34599$1433 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35067$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54028,10 +54511,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_26 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34599$1433_Y + connect \Y $eq$libresoc.v:35067$1433_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34601$1435 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35069$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54039,10 +54522,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_29 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34601$1435_Y + connect \Y $eq$libresoc.v:35069$1435_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34602$1436 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35070$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54050,10 +54533,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_28 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34602$1436_Y + connect \Y $eq$libresoc.v:35070$1436_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34604$1438 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35072$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54061,10 +54544,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_31 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34604$1438_Y + connect \Y $eq$libresoc.v:35072$1438_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34605$1439 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35073$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54072,10 +54555,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_30 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34605$1439_Y + connect \Y $eq$libresoc.v:35073$1439_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34607$1441 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35075$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54083,275 +54566,275 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_2 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34607$1441_Y + connect \Y $eq$libresoc.v:35075$1441_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34517$1351 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34985$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_0 [1:0] } - connect \Y $pos$libresoc.v:34517$1351_Y + connect \Y $pos$libresoc.v:34985$1351_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34520$1354 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34988$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_4 [1:0] } - connect \Y $pos$libresoc.v:34520$1354_Y + connect \Y $pos$libresoc.v:34988$1354_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34523$1357 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34991$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_8 [1:0] } - connect \Y $pos$libresoc.v:34523$1357_Y + connect \Y $pos$libresoc.v:34991$1357_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34526$1360 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34994$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_2 [0] } - connect \Y $pos$libresoc.v:34526$1360_Y + connect \Y $pos$libresoc.v:34994$1360_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34527$1361 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34995$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_12 [1:0] } - connect \Y $pos$libresoc.v:34527$1361_Y + connect \Y $pos$libresoc.v:34995$1361_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34530$1364 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34998$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_16 [1:0] } - connect \Y $pos$libresoc.v:34530$1364_Y + connect \Y $pos$libresoc.v:34998$1364_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34533$1367 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35001$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_20 [1:0] } - connect \Y $pos$libresoc.v:34533$1367_Y + connect \Y $pos$libresoc.v:35001$1367_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34536$1370 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35004$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_24 [1:0] } - connect \Y $pos$libresoc.v:34536$1370_Y + connect \Y $pos$libresoc.v:35004$1370_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34540$1374 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35008$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_28 [1:0] } - connect \Y $pos$libresoc.v:34540$1374_Y + connect \Y $pos$libresoc.v:35008$1374_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34543$1377 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35011$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_0 [2:0] } - connect \Y $pos$libresoc.v:34543$1377_Y + connect \Y $pos$libresoc.v:35011$1377_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34546$1380 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35014$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_4 [2:0] } - connect \Y $pos$libresoc.v:34546$1380_Y + connect \Y $pos$libresoc.v:35014$1380_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34550$1384 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35018$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_8 [2:0] } - connect \Y $pos$libresoc.v:34550$1384_Y + connect \Y $pos$libresoc.v:35018$1384_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34553$1387 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35021$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_12 [2:0] } - connect \Y $pos$libresoc.v:34553$1387_Y + connect \Y $pos$libresoc.v:35021$1387_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34556$1390 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35024$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_0 [3:0] } - connect \Y $pos$libresoc.v:34556$1390_Y + connect \Y $pos$libresoc.v:35024$1390_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34559$1393 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35027$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_4 [0] } - connect \Y $pos$libresoc.v:34559$1393_Y + connect \Y $pos$libresoc.v:35027$1393_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34560$1394 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35028$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_4 [3:0] } - connect \Y $pos$libresoc.v:34560$1394_Y + connect \Y $pos$libresoc.v:35028$1394_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34563$1397 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35031$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { 2'01 \cnt_5_0 [4:0] } - connect \Y $pos$libresoc.v:34563$1397_Y + connect \Y $pos$libresoc.v:35031$1397_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34567$1401 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35035$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_6 [0] } - connect \Y $pos$libresoc.v:34567$1401_Y + connect \Y $pos$libresoc.v:35035$1401_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34570$1404 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35038$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_8 [0] } - connect \Y $pos$libresoc.v:34570$1404_Y + connect \Y $pos$libresoc.v:35038$1404_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34573$1407 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35041$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_10 [0] } - connect \Y $pos$libresoc.v:34573$1407_Y + connect \Y $pos$libresoc.v:35041$1407_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34577$1411 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35045$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_12 [0] } - connect \Y $pos$libresoc.v:34577$1411_Y + connect \Y $pos$libresoc.v:35045$1411_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34580$1414 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35048$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_14 [0] } - connect \Y $pos$libresoc.v:34580$1414_Y + connect \Y $pos$libresoc.v:35048$1414_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34583$1417 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35051$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_16 [0] } - connect \Y $pos$libresoc.v:34583$1417_Y + connect \Y $pos$libresoc.v:35051$1417_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34586$1420 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35054$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_0 [0] } - connect \Y $pos$libresoc.v:34586$1420_Y + connect \Y $pos$libresoc.v:35054$1420_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34587$1421 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35055$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_18 [0] } - connect \Y $pos$libresoc.v:34587$1421_Y + connect \Y $pos$libresoc.v:35055$1421_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34590$1424 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35058$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_20 [0] } - connect \Y $pos$libresoc.v:34590$1424_Y + connect \Y $pos$libresoc.v:35058$1424_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34593$1427 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35061$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_22 [0] } - connect \Y $pos$libresoc.v:34593$1427_Y + connect \Y $pos$libresoc.v:35061$1427_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34596$1430 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35064$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_24 [0] } - connect \Y $pos$libresoc.v:34596$1430_Y + connect \Y $pos$libresoc.v:35064$1430_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34600$1434 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35068$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_26 [0] } - connect \Y $pos$libresoc.v:34600$1434_Y + connect \Y $pos$libresoc.v:35068$1434_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34603$1437 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35071$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_28 [0] } - connect \Y $pos$libresoc.v:34603$1437_Y + connect \Y $pos$libresoc.v:35071$1437_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34606$1440 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35074$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_30 [0] } - connect \Y $pos$libresoc.v:34606$1440_Y + connect \Y $pos$libresoc.v:35074$1440_Y end - attribute \src "libresoc.v:34134.7-34134.20" - process $proc$libresoc.v:34134$1505 + attribute \src "libresoc.v:34602.7-34602.20" + process $proc$libresoc.v:34602$1505 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:34608.3-34622.6" - process $proc$libresoc.v:34608$1442 + attribute \src "libresoc.v:35076.3-35090.6" + process $proc$libresoc.v:35076$1442 assign { } { } assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] - attribute \src "libresoc.v:34609.5-34609.29" + attribute \src "libresoc.v:35077.5-35077.29" switch \initial - attribute \src "libresoc.v:34609.9-34609.17" + attribute \src "libresoc.v:35077.9-35077.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair0 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54369,17 +54852,17 @@ module \clz sync always update \cnt_1_0 $0\cnt_1_0[1:0] end - attribute \src "libresoc.v:34623.3-34637.6" - process $proc$libresoc.v:34623$1443 + attribute \src "libresoc.v:35091.3-35105.6" + process $proc$libresoc.v:35091$1443 assign { } { } assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] - attribute \src "libresoc.v:34624.5-34624.29" + attribute \src "libresoc.v:35092.5-35092.29" switch \initial - attribute \src "libresoc.v:34624.9-34624.17" + attribute \src "libresoc.v:35092.9-35092.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair10 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54397,17 +54880,17 @@ module \clz sync always update \cnt_1_5 $0\cnt_1_5[1:0] end - attribute \src "libresoc.v:34638.3-34652.6" - process $proc$libresoc.v:34638$1444 + attribute \src "libresoc.v:35106.3-35120.6" + process $proc$libresoc.v:35106$1444 assign { } { } assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] - attribute \src "libresoc.v:34639.5-34639.29" + attribute \src "libresoc.v:35107.5-35107.29" switch \initial - attribute \src "libresoc.v:34639.9-34639.17" + attribute \src "libresoc.v:35107.9-35107.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair12 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54425,17 +54908,17 @@ module \clz sync always update \cnt_1_6 $0\cnt_1_6[1:0] end - attribute \src "libresoc.v:34653.3-34667.6" - process $proc$libresoc.v:34653$1445 + attribute \src "libresoc.v:35121.3-35135.6" + process $proc$libresoc.v:35121$1445 assign { } { } assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] - attribute \src "libresoc.v:34654.5-34654.29" + attribute \src "libresoc.v:35122.5-35122.29" switch \initial - attribute \src "libresoc.v:34654.9-34654.17" + attribute \src "libresoc.v:35122.9-35122.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair14 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54453,17 +54936,17 @@ module \clz sync always update \cnt_1_7 $0\cnt_1_7[1:0] end - attribute \src "libresoc.v:34668.3-34682.6" - process $proc$libresoc.v:34668$1446 + attribute \src "libresoc.v:35136.3-35150.6" + process $proc$libresoc.v:35136$1446 assign { } { } assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] - attribute \src "libresoc.v:34669.5-34669.29" + attribute \src "libresoc.v:35137.5-35137.29" switch \initial - attribute \src "libresoc.v:34669.9-34669.17" + attribute \src "libresoc.v:35137.9-35137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair16 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54481,17 +54964,17 @@ module \clz sync always update \cnt_1_8 $0\cnt_1_8[1:0] end - attribute \src "libresoc.v:34683.3-34697.6" - process $proc$libresoc.v:34683$1447 + attribute \src "libresoc.v:35151.3-35165.6" + process $proc$libresoc.v:35151$1447 assign { } { } assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] - attribute \src "libresoc.v:34684.5-34684.29" + attribute \src "libresoc.v:35152.5-35152.29" switch \initial - attribute \src "libresoc.v:34684.9-34684.17" + attribute \src "libresoc.v:35152.9-35152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair18 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54509,17 +54992,17 @@ module \clz sync always update \cnt_1_9 $0\cnt_1_9[1:0] end - attribute \src "libresoc.v:34698.3-34712.6" - process $proc$libresoc.v:34698$1448 + attribute \src "libresoc.v:35166.3-35180.6" + process $proc$libresoc.v:35166$1448 assign { } { } assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] - attribute \src "libresoc.v:34699.5-34699.29" + attribute \src "libresoc.v:35167.5-35167.29" switch \initial - attribute \src "libresoc.v:34699.9-34699.17" + attribute \src "libresoc.v:35167.9-35167.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair20 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54537,17 +55020,17 @@ module \clz sync always update \cnt_1_10 $0\cnt_1_10[1:0] end - attribute \src "libresoc.v:34713.3-34727.6" - process $proc$libresoc.v:34713$1449 + attribute \src "libresoc.v:35181.3-35195.6" + process $proc$libresoc.v:35181$1449 assign { } { } assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] - attribute \src "libresoc.v:34714.5-34714.29" + attribute \src "libresoc.v:35182.5-35182.29" switch \initial - attribute \src "libresoc.v:34714.9-34714.17" + attribute \src "libresoc.v:35182.9-35182.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair22 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54565,17 +55048,17 @@ module \clz sync always update \cnt_1_11 $0\cnt_1_11[1:0] end - attribute \src "libresoc.v:34728.3-34742.6" - process $proc$libresoc.v:34728$1450 + attribute \src "libresoc.v:35196.3-35210.6" + process $proc$libresoc.v:35196$1450 assign { } { } assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] - attribute \src "libresoc.v:34729.5-34729.29" + attribute \src "libresoc.v:35197.5-35197.29" switch \initial - attribute \src "libresoc.v:34729.9-34729.17" + attribute \src "libresoc.v:35197.9-35197.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair24 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54593,17 +55076,17 @@ module \clz sync always update \cnt_1_12 $0\cnt_1_12[1:0] end - attribute \src "libresoc.v:34743.3-34757.6" - process $proc$libresoc.v:34743$1451 + attribute \src "libresoc.v:35211.3-35225.6" + process $proc$libresoc.v:35211$1451 assign { } { } assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] - attribute \src "libresoc.v:34744.5-34744.29" + attribute \src "libresoc.v:35212.5-35212.29" switch \initial - attribute \src "libresoc.v:34744.9-34744.17" + attribute \src "libresoc.v:35212.9-35212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair26 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54621,17 +55104,17 @@ module \clz sync always update \cnt_1_13 $0\cnt_1_13[1:0] end - attribute \src "libresoc.v:34758.3-34772.6" - process $proc$libresoc.v:34758$1452 + attribute \src "libresoc.v:35226.3-35240.6" + process $proc$libresoc.v:35226$1452 assign { } { } assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] - attribute \src "libresoc.v:34759.5-34759.29" + attribute \src "libresoc.v:35227.5-35227.29" switch \initial - attribute \src "libresoc.v:34759.9-34759.17" + attribute \src "libresoc.v:35227.9-35227.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair28 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54649,17 +55132,17 @@ module \clz sync always update \cnt_1_14 $0\cnt_1_14[1:0] end - attribute \src "libresoc.v:34773.3-34787.6" - process $proc$libresoc.v:34773$1453 + attribute \src "libresoc.v:35241.3-35255.6" + process $proc$libresoc.v:35241$1453 assign { } { } assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] - attribute \src "libresoc.v:34774.5-34774.29" + attribute \src "libresoc.v:35242.5-35242.29" switch \initial - attribute \src "libresoc.v:34774.9-34774.17" + attribute \src "libresoc.v:35242.9-35242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair2 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54677,17 +55160,17 @@ module \clz sync always update \cnt_1_1 $0\cnt_1_1[1:0] end - attribute \src "libresoc.v:34788.3-34802.6" - process $proc$libresoc.v:34788$1454 + attribute \src "libresoc.v:35256.3-35270.6" + process $proc$libresoc.v:35256$1454 assign { } { } assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] - attribute \src "libresoc.v:34789.5-34789.29" + attribute \src "libresoc.v:35257.5-35257.29" switch \initial - attribute \src "libresoc.v:34789.9-34789.17" + attribute \src "libresoc.v:35257.9-35257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair30 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54705,17 +55188,17 @@ module \clz sync always update \cnt_1_15 $0\cnt_1_15[1:0] end - attribute \src "libresoc.v:34803.3-34817.6" - process $proc$libresoc.v:34803$1455 + attribute \src "libresoc.v:35271.3-35285.6" + process $proc$libresoc.v:35271$1455 assign { } { } assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] - attribute \src "libresoc.v:34804.5-34804.29" + attribute \src "libresoc.v:35272.5-35272.29" switch \initial - attribute \src "libresoc.v:34804.9-34804.17" + attribute \src "libresoc.v:35272.9-35272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair32 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54733,17 +55216,17 @@ module \clz sync always update \cnt_1_16 $0\cnt_1_16[1:0] end - attribute \src "libresoc.v:34818.3-34832.6" - process $proc$libresoc.v:34818$1456 + attribute \src "libresoc.v:35286.3-35300.6" + process $proc$libresoc.v:35286$1456 assign { } { } assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] - attribute \src "libresoc.v:34819.5-34819.29" + attribute \src "libresoc.v:35287.5-35287.29" switch \initial - attribute \src "libresoc.v:34819.9-34819.17" + attribute \src "libresoc.v:35287.9-35287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair34 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54761,17 +55244,17 @@ module \clz sync always update \cnt_1_17 $0\cnt_1_17[1:0] end - attribute \src "libresoc.v:34833.3-34847.6" - process $proc$libresoc.v:34833$1457 + attribute \src "libresoc.v:35301.3-35315.6" + process $proc$libresoc.v:35301$1457 assign { } { } assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] - attribute \src "libresoc.v:34834.5-34834.29" + attribute \src "libresoc.v:35302.5-35302.29" switch \initial - attribute \src "libresoc.v:34834.9-34834.17" + attribute \src "libresoc.v:35302.9-35302.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair36 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54789,17 +55272,17 @@ module \clz sync always update \cnt_1_18 $0\cnt_1_18[1:0] end - attribute \src "libresoc.v:34848.3-34862.6" - process $proc$libresoc.v:34848$1458 + attribute \src "libresoc.v:35316.3-35330.6" + process $proc$libresoc.v:35316$1458 assign { } { } assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] - attribute \src "libresoc.v:34849.5-34849.29" + attribute \src "libresoc.v:35317.5-35317.29" switch \initial - attribute \src "libresoc.v:34849.9-34849.17" + attribute \src "libresoc.v:35317.9-35317.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair38 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54817,17 +55300,17 @@ module \clz sync always update \cnt_1_19 $0\cnt_1_19[1:0] end - attribute \src "libresoc.v:34863.3-34877.6" - process $proc$libresoc.v:34863$1459 + attribute \src "libresoc.v:35331.3-35345.6" + process $proc$libresoc.v:35331$1459 assign { } { } assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] - attribute \src "libresoc.v:34864.5-34864.29" + attribute \src "libresoc.v:35332.5-35332.29" switch \initial - attribute \src "libresoc.v:34864.9-34864.17" + attribute \src "libresoc.v:35332.9-35332.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair40 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54845,17 +55328,17 @@ module \clz sync always update \cnt_1_20 $0\cnt_1_20[1:0] end - attribute \src "libresoc.v:34878.3-34892.6" - process $proc$libresoc.v:34878$1460 + attribute \src "libresoc.v:35346.3-35360.6" + process $proc$libresoc.v:35346$1460 assign { } { } assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] - attribute \src "libresoc.v:34879.5-34879.29" + attribute \src "libresoc.v:35347.5-35347.29" switch \initial - attribute \src "libresoc.v:34879.9-34879.17" + attribute \src "libresoc.v:35347.9-35347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair42 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54873,17 +55356,17 @@ module \clz sync always update \cnt_1_21 $0\cnt_1_21[1:0] end - attribute \src "libresoc.v:34893.3-34907.6" - process $proc$libresoc.v:34893$1461 + attribute \src "libresoc.v:35361.3-35375.6" + process $proc$libresoc.v:35361$1461 assign { } { } assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] - attribute \src "libresoc.v:34894.5-34894.29" + attribute \src "libresoc.v:35362.5-35362.29" switch \initial - attribute \src "libresoc.v:34894.9-34894.17" + attribute \src "libresoc.v:35362.9-35362.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair44 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54901,17 +55384,17 @@ module \clz sync always update \cnt_1_22 $0\cnt_1_22[1:0] end - attribute \src "libresoc.v:34908.3-34922.6" - process $proc$libresoc.v:34908$1462 + attribute \src "libresoc.v:35376.3-35390.6" + process $proc$libresoc.v:35376$1462 assign { } { } assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] - attribute \src "libresoc.v:34909.5-34909.29" + attribute \src "libresoc.v:35377.5-35377.29" switch \initial - attribute \src "libresoc.v:34909.9-34909.17" + attribute \src "libresoc.v:35377.9-35377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair46 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54929,17 +55412,17 @@ module \clz sync always update \cnt_1_23 $0\cnt_1_23[1:0] end - attribute \src "libresoc.v:34923.3-34937.6" - process $proc$libresoc.v:34923$1463 + attribute \src "libresoc.v:35391.3-35405.6" + process $proc$libresoc.v:35391$1463 assign { } { } assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] - attribute \src "libresoc.v:34924.5-34924.29" + attribute \src "libresoc.v:35392.5-35392.29" switch \initial - attribute \src "libresoc.v:34924.9-34924.17" + attribute \src "libresoc.v:35392.9-35392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair48 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54957,17 +55440,17 @@ module \clz sync always update \cnt_1_24 $0\cnt_1_24[1:0] end - attribute \src "libresoc.v:34938.3-34952.6" - process $proc$libresoc.v:34938$1464 + attribute \src "libresoc.v:35406.3-35420.6" + process $proc$libresoc.v:35406$1464 assign { } { } assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] - attribute \src "libresoc.v:34939.5-34939.29" + attribute \src "libresoc.v:35407.5-35407.29" switch \initial - attribute \src "libresoc.v:34939.9-34939.17" + attribute \src "libresoc.v:35407.9-35407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair4 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -54985,17 +55468,17 @@ module \clz sync always update \cnt_1_2 $0\cnt_1_2[1:0] end - attribute \src "libresoc.v:34953.3-34967.6" - process $proc$libresoc.v:34953$1465 + attribute \src "libresoc.v:35421.3-35435.6" + process $proc$libresoc.v:35421$1465 assign { } { } assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] - attribute \src "libresoc.v:34954.5-34954.29" + attribute \src "libresoc.v:35422.5-35422.29" switch \initial - attribute \src "libresoc.v:34954.9-34954.17" + attribute \src "libresoc.v:35422.9-35422.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair50 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -55013,17 +55496,17 @@ module \clz sync always update \cnt_1_25 $0\cnt_1_25[1:0] end - attribute \src "libresoc.v:34968.3-34982.6" - process $proc$libresoc.v:34968$1466 + attribute \src "libresoc.v:35436.3-35450.6" + process $proc$libresoc.v:35436$1466 assign { } { } assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] - attribute \src "libresoc.v:34969.5-34969.29" + attribute \src "libresoc.v:35437.5-35437.29" switch \initial - attribute \src "libresoc.v:34969.9-34969.17" + attribute \src "libresoc.v:35437.9-35437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair52 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -55041,17 +55524,17 @@ module \clz sync always update \cnt_1_26 $0\cnt_1_26[1:0] end - attribute \src "libresoc.v:34983.3-34997.6" - process $proc$libresoc.v:34983$1467 + attribute \src "libresoc.v:35451.3-35465.6" + process $proc$libresoc.v:35451$1467 assign { } { } assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] - attribute \src "libresoc.v:34984.5-34984.29" + attribute \src "libresoc.v:35452.5-35452.29" switch \initial - attribute \src "libresoc.v:34984.9-34984.17" + attribute \src "libresoc.v:35452.9-35452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair54 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -55069,17 +55552,17 @@ module \clz sync always update \cnt_1_27 $0\cnt_1_27[1:0] end - attribute \src "libresoc.v:34998.3-35012.6" - process $proc$libresoc.v:34998$1468 + attribute \src "libresoc.v:35466.3-35480.6" + process $proc$libresoc.v:35466$1468 assign { } { } assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] - attribute \src "libresoc.v:34999.5-34999.29" + attribute \src "libresoc.v:35467.5-35467.29" switch \initial - attribute \src "libresoc.v:34999.9-34999.17" + attribute \src "libresoc.v:35467.9-35467.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair56 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -55097,17 +55580,17 @@ module \clz sync always update \cnt_1_28 $0\cnt_1_28[1:0] end - attribute \src "libresoc.v:35013.3-35027.6" - process $proc$libresoc.v:35013$1469 + attribute \src "libresoc.v:35481.3-35495.6" + process $proc$libresoc.v:35481$1469 assign { } { } assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35014.5-35014.29" + attribute \src "libresoc.v:35482.5-35482.29" switch \initial - attribute \src "libresoc.v:35014.9-35014.17" + attribute \src "libresoc.v:35482.9-35482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair58 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -55125,17 +55608,17 @@ module \clz sync always update \cnt_1_29 $0\cnt_1_29[1:0] end - attribute \src "libresoc.v:35028.3-35042.6" - process $proc$libresoc.v:35028$1470 + attribute \src "libresoc.v:35496.3-35510.6" + process $proc$libresoc.v:35496$1470 assign { } { } assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35029.5-35029.29" + attribute \src "libresoc.v:35497.5-35497.29" switch \initial - attribute \src "libresoc.v:35029.9-35029.17" + attribute \src "libresoc.v:35497.9-35497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair60 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -55153,17 +55636,17 @@ module \clz sync always update \cnt_1_30 $0\cnt_1_30[1:0] end - attribute \src "libresoc.v:35043.3-35057.6" - process $proc$libresoc.v:35043$1471 + attribute \src "libresoc.v:35511.3-35525.6" + process $proc$libresoc.v:35511$1471 assign { } { } assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35044.5-35044.29" + attribute \src "libresoc.v:35512.5-35512.29" switch \initial - attribute \src "libresoc.v:35044.9-35044.17" + attribute \src "libresoc.v:35512.9-35512.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair62 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -55181,23 +55664,23 @@ module \clz sync always update \cnt_1_31 $0\cnt_1_31[1:0] end - attribute \src "libresoc.v:35058.3-35077.6" - process $proc$libresoc.v:35058$1472 + attribute \src "libresoc.v:35526.3-35545.6" + process $proc$libresoc.v:35526$1472 assign { } { } assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35059.5-35059.29" + attribute \src "libresoc.v:35527.5-35527.29" switch \initial - attribute \src "libresoc.v:35059.9-35059.17" + attribute \src "libresoc.v:35527.9-35527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55216,23 +55699,23 @@ module \clz sync always update \cnt_2_0 $0\cnt_2_0[2:0] end - attribute \src "libresoc.v:35078.3-35097.6" - process $proc$libresoc.v:35078$1473 + attribute \src "libresoc.v:35546.3-35565.6" + process $proc$libresoc.v:35546$1473 assign { } { } assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35079.5-35079.29" + attribute \src "libresoc.v:35547.5-35547.29" switch \initial - attribute \src "libresoc.v:35079.9-35079.17" + attribute \src "libresoc.v:35547.9-35547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55251,23 +55734,23 @@ module \clz sync always update \cnt_2_2 $0\cnt_2_2[2:0] end - attribute \src "libresoc.v:35098.3-35117.6" - process $proc$libresoc.v:35098$1474 + attribute \src "libresoc.v:35566.3-35585.6" + process $proc$libresoc.v:35566$1474 assign { } { } assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35099.5-35099.29" + attribute \src "libresoc.v:35567.5-35567.29" switch \initial - attribute \src "libresoc.v:35099.9-35099.17" + attribute \src "libresoc.v:35567.9-35567.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55286,23 +55769,23 @@ module \clz sync always update \cnt_2_4 $0\cnt_2_4[2:0] end - attribute \src "libresoc.v:35118.3-35137.6" - process $proc$libresoc.v:35118$1475 + attribute \src "libresoc.v:35586.3-35605.6" + process $proc$libresoc.v:35586$1475 assign { } { } assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35119.5-35119.29" + attribute \src "libresoc.v:35587.5-35587.29" switch \initial - attribute \src "libresoc.v:35119.9-35119.17" + attribute \src "libresoc.v:35587.9-35587.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55321,23 +55804,23 @@ module \clz sync always update \cnt_2_6 $0\cnt_2_6[2:0] end - attribute \src "libresoc.v:35138.3-35157.6" - process $proc$libresoc.v:35138$1476 + attribute \src "libresoc.v:35606.3-35625.6" + process $proc$libresoc.v:35606$1476 assign { } { } assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35139.5-35139.29" + attribute \src "libresoc.v:35607.5-35607.29" switch \initial - attribute \src "libresoc.v:35139.9-35139.17" + attribute \src "libresoc.v:35607.9-35607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55356,23 +55839,23 @@ module \clz sync always update \cnt_2_8 $0\cnt_2_8[2:0] end - attribute \src "libresoc.v:35158.3-35177.6" - process $proc$libresoc.v:35158$1477 + attribute \src "libresoc.v:35626.3-35645.6" + process $proc$libresoc.v:35626$1477 assign { } { } assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35159.5-35159.29" + attribute \src "libresoc.v:35627.5-35627.29" switch \initial - attribute \src "libresoc.v:35159.9-35159.17" + attribute \src "libresoc.v:35627.9-35627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55391,17 +55874,17 @@ module \clz sync always update \cnt_2_10 $0\cnt_2_10[2:0] end - attribute \src "libresoc.v:35178.3-35192.6" - process $proc$libresoc.v:35178$1478 + attribute \src "libresoc.v:35646.3-35660.6" + process $proc$libresoc.v:35646$1478 assign { } { } assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35179.5-35179.29" + attribute \src "libresoc.v:35647.5-35647.29" switch \initial - attribute \src "libresoc.v:35179.9-35179.17" + attribute \src "libresoc.v:35647.9-35647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair6 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -55419,23 +55902,23 @@ module \clz sync always update \cnt_1_3 $0\cnt_1_3[1:0] end - attribute \src "libresoc.v:35193.3-35212.6" - process $proc$libresoc.v:35193$1479 + attribute \src "libresoc.v:35661.3-35680.6" + process $proc$libresoc.v:35661$1479 assign { } { } assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35194.5-35194.29" + attribute \src "libresoc.v:35662.5-35662.29" switch \initial - attribute \src "libresoc.v:35194.9-35194.17" + attribute \src "libresoc.v:35662.9-35662.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55454,23 +55937,23 @@ module \clz sync always update \cnt_2_12 $0\cnt_2_12[2:0] end - attribute \src "libresoc.v:35213.3-35232.6" - process $proc$libresoc.v:35213$1480 + attribute \src "libresoc.v:35681.3-35700.6" + process $proc$libresoc.v:35681$1480 assign { } { } assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35214.5-35214.29" + attribute \src "libresoc.v:35682.5-35682.29" switch \initial - attribute \src "libresoc.v:35214.9-35214.17" + attribute \src "libresoc.v:35682.9-35682.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55489,23 +55972,23 @@ module \clz sync always update \cnt_2_14 $0\cnt_2_14[2:0] end - attribute \src "libresoc.v:35233.3-35252.6" - process $proc$libresoc.v:35233$1481 + attribute \src "libresoc.v:35701.3-35720.6" + process $proc$libresoc.v:35701$1481 assign { } { } assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35234.5-35234.29" + attribute \src "libresoc.v:35702.5-35702.29" switch \initial - attribute \src "libresoc.v:35234.9-35234.17" + attribute \src "libresoc.v:35702.9-35702.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$51 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55524,23 +56007,23 @@ module \clz sync always update \cnt_2_16 $0\cnt_2_16[2:0] end - attribute \src "libresoc.v:35253.3-35272.6" - process $proc$libresoc.v:35253$1482 + attribute \src "libresoc.v:35721.3-35740.6" + process $proc$libresoc.v:35721$1482 assign { } { } assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35254.5-35254.29" + attribute \src "libresoc.v:35722.5-35722.29" switch \initial - attribute \src "libresoc.v:35254.9-35254.17" + attribute \src "libresoc.v:35722.9-35722.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55559,23 +56042,23 @@ module \clz sync always update \cnt_2_18 $0\cnt_2_18[2:0] end - attribute \src "libresoc.v:35273.3-35292.6" - process $proc$libresoc.v:35273$1483 + attribute \src "libresoc.v:35741.3-35760.6" + process $proc$libresoc.v:35741$1483 assign { } { } assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35274.5-35274.29" + attribute \src "libresoc.v:35742.5-35742.29" switch \initial - attribute \src "libresoc.v:35274.9-35274.17" + attribute \src "libresoc.v:35742.9-35742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55594,23 +56077,23 @@ module \clz sync always update \cnt_2_20 $0\cnt_2_20[2:0] end - attribute \src "libresoc.v:35293.3-35312.6" - process $proc$libresoc.v:35293$1484 + attribute \src "libresoc.v:35761.3-35780.6" + process $proc$libresoc.v:35761$1484 assign { } { } assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35294.5-35294.29" + attribute \src "libresoc.v:35762.5-35762.29" switch \initial - attribute \src "libresoc.v:35294.9-35294.17" + attribute \src "libresoc.v:35762.9-35762.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55629,23 +56112,23 @@ module \clz sync always update \cnt_2_22 $0\cnt_2_22[2:0] end - attribute \src "libresoc.v:35313.3-35332.6" - process $proc$libresoc.v:35313$1485 + attribute \src "libresoc.v:35781.3-35800.6" + process $proc$libresoc.v:35781$1485 assign { } { } assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35314.5-35314.29" + attribute \src "libresoc.v:35782.5-35782.29" switch \initial - attribute \src "libresoc.v:35314.9-35314.17" + attribute \src "libresoc.v:35782.9-35782.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$75 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55664,23 +56147,23 @@ module \clz sync always update \cnt_2_24 $0\cnt_2_24[2:0] end - attribute \src "libresoc.v:35333.3-35352.6" - process $proc$libresoc.v:35333$1486 + attribute \src "libresoc.v:35801.3-35820.6" + process $proc$libresoc.v:35801$1486 assign { } { } assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35334.5-35334.29" + attribute \src "libresoc.v:35802.5-35802.29" switch \initial - attribute \src "libresoc.v:35334.9-35334.17" + attribute \src "libresoc.v:35802.9-35802.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$79 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55699,23 +56182,23 @@ module \clz sync always update \cnt_2_26 $0\cnt_2_26[2:0] end - attribute \src "libresoc.v:35353.3-35372.6" - process $proc$libresoc.v:35353$1487 + attribute \src "libresoc.v:35821.3-35840.6" + process $proc$libresoc.v:35821$1487 assign { } { } assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35354.5-35354.29" + attribute \src "libresoc.v:35822.5-35822.29" switch \initial - attribute \src "libresoc.v:35354.9-35354.17" + attribute \src "libresoc.v:35822.9-35822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55734,23 +56217,23 @@ module \clz sync always update \cnt_2_28 $0\cnt_2_28[2:0] end - attribute \src "libresoc.v:35373.3-35392.6" - process $proc$libresoc.v:35373$1488 + attribute \src "libresoc.v:35841.3-35860.6" + process $proc$libresoc.v:35841$1488 assign { } { } assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35374.5-35374.29" + attribute \src "libresoc.v:35842.5-35842.29" switch \initial - attribute \src "libresoc.v:35374.9-35374.17" + attribute \src "libresoc.v:35842.9-35842.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$91 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55769,23 +56252,23 @@ module \clz sync always update \cnt_2_30 $0\cnt_2_30[2:0] end - attribute \src "libresoc.v:35393.3-35412.6" - process $proc$libresoc.v:35393$1489 + attribute \src "libresoc.v:35861.3-35880.6" + process $proc$libresoc.v:35861$1489 assign { } { } assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35394.5-35394.29" + attribute \src "libresoc.v:35862.5-35862.29" switch \initial - attribute \src "libresoc.v:35394.9-35394.17" + attribute \src "libresoc.v:35862.9-35862.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$97 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$99 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55804,23 +56287,23 @@ module \clz sync always update \cnt_3_0 $0\cnt_3_0[3:0] end - attribute \src "libresoc.v:35413.3-35432.6" - process $proc$libresoc.v:35413$1490 + attribute \src "libresoc.v:35881.3-35900.6" + process $proc$libresoc.v:35881$1490 assign { } { } assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35414.5-35414.29" + attribute \src "libresoc.v:35882.5-35882.29" switch \initial - attribute \src "libresoc.v:35414.9-35414.17" + attribute \src "libresoc.v:35882.9-35882.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55839,23 +56322,23 @@ module \clz sync always update \cnt_3_2 $0\cnt_3_2[3:0] end - attribute \src "libresoc.v:35433.3-35452.6" - process $proc$libresoc.v:35433$1491 + attribute \src "libresoc.v:35901.3-35920.6" + process $proc$libresoc.v:35901$1491 assign { } { } assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35434.5-35434.29" + attribute \src "libresoc.v:35902.5-35902.29" switch \initial - attribute \src "libresoc.v:35434.9-35434.17" + attribute \src "libresoc.v:35902.9-35902.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$109 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$111 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55874,23 +56357,23 @@ module \clz sync always update \cnt_3_4 $0\cnt_3_4[3:0] end - attribute \src "libresoc.v:35453.3-35472.6" - process $proc$libresoc.v:35453$1492 + attribute \src "libresoc.v:35921.3-35940.6" + process $proc$libresoc.v:35921$1492 assign { } { } assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35454.5-35454.29" + attribute \src "libresoc.v:35922.5-35922.29" switch \initial - attribute \src "libresoc.v:35454.9-35454.17" + attribute \src "libresoc.v:35922.9-35922.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55909,23 +56392,23 @@ module \clz sync always update \cnt_3_6 $0\cnt_3_6[3:0] end - attribute \src "libresoc.v:35473.3-35492.6" - process $proc$libresoc.v:35473$1493 + attribute \src "libresoc.v:35941.3-35960.6" + process $proc$libresoc.v:35941$1493 assign { } { } assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35474.5-35474.29" + attribute \src "libresoc.v:35942.5-35942.29" switch \initial - attribute \src "libresoc.v:35474.9-35474.17" + attribute \src "libresoc.v:35942.9-35942.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55944,23 +56427,23 @@ module \clz sync always update \cnt_3_8 $0\cnt_3_8[3:0] end - attribute \src "libresoc.v:35493.3-35512.6" - process $proc$libresoc.v:35493$1494 + attribute \src "libresoc.v:35961.3-35980.6" + process $proc$libresoc.v:35961$1494 assign { } { } assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35494.5-35494.29" + attribute \src "libresoc.v:35962.5-35962.29" switch \initial - attribute \src "libresoc.v:35494.9-35494.17" + attribute \src "libresoc.v:35962.9-35962.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -55979,23 +56462,23 @@ module \clz sync always update \cnt_3_10 $0\cnt_3_10[3:0] end - attribute \src "libresoc.v:35513.3-35532.6" - process $proc$libresoc.v:35513$1495 + attribute \src "libresoc.v:35981.3-36000.6" + process $proc$libresoc.v:35981$1495 assign { } { } assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35514.5-35514.29" + attribute \src "libresoc.v:35982.5-35982.29" switch \initial - attribute \src "libresoc.v:35514.9-35514.17" + attribute \src "libresoc.v:35982.9-35982.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56014,23 +56497,23 @@ module \clz sync always update \cnt_3_12 $0\cnt_3_12[3:0] end - attribute \src "libresoc.v:35533.3-35552.6" - process $proc$libresoc.v:35533$1496 + attribute \src "libresoc.v:36001.3-36020.6" + process $proc$libresoc.v:36001$1496 assign { } { } assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35534.5-35534.29" + attribute \src "libresoc.v:36002.5-36002.29" switch \initial - attribute \src "libresoc.v:35534.9-35534.17" + attribute \src "libresoc.v:36002.9-36002.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$139 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$141 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56049,23 +56532,23 @@ module \clz sync always update \cnt_3_14 $0\cnt_3_14[3:0] end - attribute \src "libresoc.v:35553.3-35572.6" - process $proc$libresoc.v:35553$1497 + attribute \src "libresoc.v:36021.3-36040.6" + process $proc$libresoc.v:36021$1497 assign { } { } assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] - attribute \src "libresoc.v:35554.5-35554.29" + attribute \src "libresoc.v:36022.5-36022.29" switch \initial - attribute \src "libresoc.v:35554.9-35554.17" + attribute \src "libresoc.v:36022.9-36022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$145 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$147 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56084,23 +56567,23 @@ module \clz sync always update \cnt_4_0 $0\cnt_4_0[4:0] end - attribute \src "libresoc.v:35573.3-35592.6" - process $proc$libresoc.v:35573$1498 + attribute \src "libresoc.v:36041.3-36060.6" + process $proc$libresoc.v:36041$1498 assign { } { } assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] - attribute \src "libresoc.v:35574.5-35574.29" + attribute \src "libresoc.v:36042.5-36042.29" switch \initial - attribute \src "libresoc.v:35574.9-35574.17" + attribute \src "libresoc.v:36042.9-36042.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$151 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$153 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56119,17 +56602,17 @@ module \clz sync always update \cnt_4_2 $0\cnt_4_2[4:0] end - attribute \src "libresoc.v:35593.3-35607.6" - process $proc$libresoc.v:35593$1499 + attribute \src "libresoc.v:36061.3-36075.6" + process $proc$libresoc.v:36061$1499 assign { } { } assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] - attribute \src "libresoc.v:35594.5-35594.29" + attribute \src "libresoc.v:36062.5-36062.29" switch \initial - attribute \src "libresoc.v:35594.9-35594.17" + attribute \src "libresoc.v:36062.9-36062.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair8 attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -56147,23 +56630,23 @@ module \clz sync always update \cnt_1_4 $0\cnt_1_4[1:0] end - attribute \src "libresoc.v:35608.3-35627.6" - process $proc$libresoc.v:35608$1500 + attribute \src "libresoc.v:36076.3-36095.6" + process $proc$libresoc.v:36076$1500 assign { } { } assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] - attribute \src "libresoc.v:35609.5-35609.29" + attribute \src "libresoc.v:36077.5-36077.29" switch \initial - attribute \src "libresoc.v:35609.9-35609.17" + attribute \src "libresoc.v:36077.9-36077.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$157 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$159 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56182,23 +56665,23 @@ module \clz sync always update \cnt_4_4 $0\cnt_4_4[4:0] end - attribute \src "libresoc.v:35628.3-35647.6" - process $proc$libresoc.v:35628$1501 + attribute \src "libresoc.v:36096.3-36115.6" + process $proc$libresoc.v:36096$1501 assign { } { } assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] - attribute \src "libresoc.v:35629.5-35629.29" + attribute \src "libresoc.v:36097.5-36097.29" switch \initial - attribute \src "libresoc.v:35629.9-35629.17" + attribute \src "libresoc.v:36097.9-36097.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$163 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$165 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56217,23 +56700,23 @@ module \clz sync always update \cnt_4_6 $0\cnt_4_6[4:0] end - attribute \src "libresoc.v:35648.3-35667.6" - process $proc$libresoc.v:35648$1502 + attribute \src "libresoc.v:36116.3-36135.6" + process $proc$libresoc.v:36116$1502 assign { } { } assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] - attribute \src "libresoc.v:35649.5-35649.29" + attribute \src "libresoc.v:36117.5-36117.29" switch \initial - attribute \src "libresoc.v:35649.9-35649.17" + attribute \src "libresoc.v:36117.9-36117.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$169 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$171 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56252,23 +56735,23 @@ module \clz sync always update \cnt_5_0 $0\cnt_5_0[5:0] end - attribute \src "libresoc.v:35668.3-35687.6" - process $proc$libresoc.v:35668$1503 + attribute \src "libresoc.v:36136.3-36155.6" + process $proc$libresoc.v:36136$1503 assign { } { } assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] - attribute \src "libresoc.v:35669.5-35669.29" + attribute \src "libresoc.v:36137.5-36137.29" switch \initial - attribute \src "libresoc.v:35669.9-35669.17" + attribute \src "libresoc.v:36137.9-36137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$175 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$177 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56287,23 +56770,23 @@ module \clz sync always update \cnt_5_2 $0\cnt_5_2[5:0] end - attribute \src "libresoc.v:35688.3-35707.6" - process $proc$libresoc.v:35688$1504 + attribute \src "libresoc.v:36156.3-36175.6" + process $proc$libresoc.v:36156$1504 assign { } { } assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35689.5-35689.29" + attribute \src "libresoc.v:36157.5-36157.29" switch \initial - attribute \src "libresoc.v:35689.9-35689.17" + attribute \src "libresoc.v:36157.9-36157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$181 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$183 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -56322,99 +56805,99 @@ module \clz sync always update \cnt_6_0 $0\cnt_6_0[6:0] end - connect \$9 $eq$libresoc.v:34515$1349_Y - connect \$99 $eq$libresoc.v:34516$1350_Y - connect \$101 $pos$libresoc.v:34517$1351_Y - connect \$103 $eq$libresoc.v:34518$1352_Y - connect \$105 $eq$libresoc.v:34519$1353_Y - connect \$107 $pos$libresoc.v:34520$1354_Y - connect \$109 $eq$libresoc.v:34521$1355_Y - connect \$111 $eq$libresoc.v:34522$1356_Y - connect \$113 $pos$libresoc.v:34523$1357_Y - connect \$115 $eq$libresoc.v:34524$1358_Y - connect \$117 $eq$libresoc.v:34525$1359_Y - connect \$11 $pos$libresoc.v:34526$1360_Y - connect \$119 $pos$libresoc.v:34527$1361_Y - connect \$121 $eq$libresoc.v:34528$1362_Y - connect \$123 $eq$libresoc.v:34529$1363_Y - connect \$125 $pos$libresoc.v:34530$1364_Y - connect \$127 $eq$libresoc.v:34531$1365_Y - connect \$129 $eq$libresoc.v:34532$1366_Y - connect \$131 $pos$libresoc.v:34533$1367_Y - connect \$133 $eq$libresoc.v:34534$1368_Y - connect \$135 $eq$libresoc.v:34535$1369_Y - connect \$137 $pos$libresoc.v:34536$1370_Y - connect \$13 $eq$libresoc.v:34537$1371_Y - connect \$139 $eq$libresoc.v:34538$1372_Y - connect \$141 $eq$libresoc.v:34539$1373_Y - connect \$143 $pos$libresoc.v:34540$1374_Y - connect \$145 $eq$libresoc.v:34541$1375_Y - connect \$147 $eq$libresoc.v:34542$1376_Y - connect \$149 $pos$libresoc.v:34543$1377_Y - connect \$151 $eq$libresoc.v:34544$1378_Y - connect \$153 $eq$libresoc.v:34545$1379_Y - connect \$155 $pos$libresoc.v:34546$1380_Y - connect \$157 $eq$libresoc.v:34547$1381_Y - connect \$15 $eq$libresoc.v:34548$1382_Y - connect \$159 $eq$libresoc.v:34549$1383_Y - connect \$161 $pos$libresoc.v:34550$1384_Y - connect \$163 $eq$libresoc.v:34551$1385_Y - connect \$165 $eq$libresoc.v:34552$1386_Y - connect \$167 $pos$libresoc.v:34553$1387_Y - connect \$169 $eq$libresoc.v:34554$1388_Y - connect \$171 $eq$libresoc.v:34555$1389_Y - connect \$173 $pos$libresoc.v:34556$1390_Y - connect \$175 $eq$libresoc.v:34557$1391_Y - connect \$177 $eq$libresoc.v:34558$1392_Y - connect \$17 $pos$libresoc.v:34559$1393_Y - connect \$179 $pos$libresoc.v:34560$1394_Y - connect \$181 $eq$libresoc.v:34561$1395_Y - connect \$183 $eq$libresoc.v:34562$1396_Y - connect \$185 $pos$libresoc.v:34563$1397_Y - connect \$1 $eq$libresoc.v:34564$1398_Y - connect \$19 $eq$libresoc.v:34565$1399_Y - connect \$21 $eq$libresoc.v:34566$1400_Y - connect \$23 $pos$libresoc.v:34567$1401_Y - connect \$25 $eq$libresoc.v:34568$1402_Y - connect \$27 $eq$libresoc.v:34569$1403_Y - connect \$29 $pos$libresoc.v:34570$1404_Y - connect \$31 $eq$libresoc.v:34571$1405_Y - connect \$33 $eq$libresoc.v:34572$1406_Y - connect \$35 $pos$libresoc.v:34573$1407_Y - connect \$37 $eq$libresoc.v:34574$1408_Y - connect \$3 $eq$libresoc.v:34575$1409_Y - connect \$39 $eq$libresoc.v:34576$1410_Y - connect \$41 $pos$libresoc.v:34577$1411_Y - connect \$43 $eq$libresoc.v:34578$1412_Y - connect \$45 $eq$libresoc.v:34579$1413_Y - connect \$47 $pos$libresoc.v:34580$1414_Y - connect \$49 $eq$libresoc.v:34581$1415_Y - connect \$51 $eq$libresoc.v:34582$1416_Y - connect \$53 $pos$libresoc.v:34583$1417_Y - connect \$55 $eq$libresoc.v:34584$1418_Y - connect \$57 $eq$libresoc.v:34585$1419_Y - connect \$5 $pos$libresoc.v:34586$1420_Y - connect \$59 $pos$libresoc.v:34587$1421_Y - connect \$61 $eq$libresoc.v:34588$1422_Y - connect \$63 $eq$libresoc.v:34589$1423_Y - connect \$65 $pos$libresoc.v:34590$1424_Y - connect \$67 $eq$libresoc.v:34591$1425_Y - connect \$69 $eq$libresoc.v:34592$1426_Y - connect \$71 $pos$libresoc.v:34593$1427_Y - connect \$73 $eq$libresoc.v:34594$1428_Y - connect \$75 $eq$libresoc.v:34595$1429_Y - connect \$77 $pos$libresoc.v:34596$1430_Y - connect \$7 $eq$libresoc.v:34597$1431_Y - connect \$79 $eq$libresoc.v:34598$1432_Y - connect \$81 $eq$libresoc.v:34599$1433_Y - connect \$83 $pos$libresoc.v:34600$1434_Y - connect \$85 $eq$libresoc.v:34601$1435_Y - connect \$87 $eq$libresoc.v:34602$1436_Y - connect \$89 $pos$libresoc.v:34603$1437_Y - connect \$91 $eq$libresoc.v:34604$1438_Y - connect \$93 $eq$libresoc.v:34605$1439_Y - connect \$95 $pos$libresoc.v:34606$1440_Y - connect \$97 $eq$libresoc.v:34607$1441_Y + connect \$9 $eq$libresoc.v:34983$1349_Y + connect \$99 $eq$libresoc.v:34984$1350_Y + connect \$101 $pos$libresoc.v:34985$1351_Y + connect \$103 $eq$libresoc.v:34986$1352_Y + connect \$105 $eq$libresoc.v:34987$1353_Y + connect \$107 $pos$libresoc.v:34988$1354_Y + connect \$109 $eq$libresoc.v:34989$1355_Y + connect \$111 $eq$libresoc.v:34990$1356_Y + connect \$113 $pos$libresoc.v:34991$1357_Y + connect \$115 $eq$libresoc.v:34992$1358_Y + connect \$117 $eq$libresoc.v:34993$1359_Y + connect \$11 $pos$libresoc.v:34994$1360_Y + connect \$119 $pos$libresoc.v:34995$1361_Y + connect \$121 $eq$libresoc.v:34996$1362_Y + connect \$123 $eq$libresoc.v:34997$1363_Y + connect \$125 $pos$libresoc.v:34998$1364_Y + connect \$127 $eq$libresoc.v:34999$1365_Y + connect \$129 $eq$libresoc.v:35000$1366_Y + connect \$131 $pos$libresoc.v:35001$1367_Y + connect \$133 $eq$libresoc.v:35002$1368_Y + connect \$135 $eq$libresoc.v:35003$1369_Y + connect \$137 $pos$libresoc.v:35004$1370_Y + connect \$13 $eq$libresoc.v:35005$1371_Y + connect \$139 $eq$libresoc.v:35006$1372_Y + connect \$141 $eq$libresoc.v:35007$1373_Y + connect \$143 $pos$libresoc.v:35008$1374_Y + connect \$145 $eq$libresoc.v:35009$1375_Y + connect \$147 $eq$libresoc.v:35010$1376_Y + connect \$149 $pos$libresoc.v:35011$1377_Y + connect \$151 $eq$libresoc.v:35012$1378_Y + connect \$153 $eq$libresoc.v:35013$1379_Y + connect \$155 $pos$libresoc.v:35014$1380_Y + connect \$157 $eq$libresoc.v:35015$1381_Y + connect \$15 $eq$libresoc.v:35016$1382_Y + connect \$159 $eq$libresoc.v:35017$1383_Y + connect \$161 $pos$libresoc.v:35018$1384_Y + connect \$163 $eq$libresoc.v:35019$1385_Y + connect \$165 $eq$libresoc.v:35020$1386_Y + connect \$167 $pos$libresoc.v:35021$1387_Y + connect \$169 $eq$libresoc.v:35022$1388_Y + connect \$171 $eq$libresoc.v:35023$1389_Y + connect \$173 $pos$libresoc.v:35024$1390_Y + connect \$175 $eq$libresoc.v:35025$1391_Y + connect \$177 $eq$libresoc.v:35026$1392_Y + connect \$17 $pos$libresoc.v:35027$1393_Y + connect \$179 $pos$libresoc.v:35028$1394_Y + connect \$181 $eq$libresoc.v:35029$1395_Y + connect \$183 $eq$libresoc.v:35030$1396_Y + connect \$185 $pos$libresoc.v:35031$1397_Y + connect \$1 $eq$libresoc.v:35032$1398_Y + connect \$19 $eq$libresoc.v:35033$1399_Y + connect \$21 $eq$libresoc.v:35034$1400_Y + connect \$23 $pos$libresoc.v:35035$1401_Y + connect \$25 $eq$libresoc.v:35036$1402_Y + connect \$27 $eq$libresoc.v:35037$1403_Y + connect \$29 $pos$libresoc.v:35038$1404_Y + connect \$31 $eq$libresoc.v:35039$1405_Y + connect \$33 $eq$libresoc.v:35040$1406_Y + connect \$35 $pos$libresoc.v:35041$1407_Y + connect \$37 $eq$libresoc.v:35042$1408_Y + connect \$3 $eq$libresoc.v:35043$1409_Y + connect \$39 $eq$libresoc.v:35044$1410_Y + connect \$41 $pos$libresoc.v:35045$1411_Y + connect \$43 $eq$libresoc.v:35046$1412_Y + connect \$45 $eq$libresoc.v:35047$1413_Y + connect \$47 $pos$libresoc.v:35048$1414_Y + connect \$49 $eq$libresoc.v:35049$1415_Y + connect \$51 $eq$libresoc.v:35050$1416_Y + connect \$53 $pos$libresoc.v:35051$1417_Y + connect \$55 $eq$libresoc.v:35052$1418_Y + connect \$57 $eq$libresoc.v:35053$1419_Y + connect \$5 $pos$libresoc.v:35054$1420_Y + connect \$59 $pos$libresoc.v:35055$1421_Y + connect \$61 $eq$libresoc.v:35056$1422_Y + connect \$63 $eq$libresoc.v:35057$1423_Y + connect \$65 $pos$libresoc.v:35058$1424_Y + connect \$67 $eq$libresoc.v:35059$1425_Y + connect \$69 $eq$libresoc.v:35060$1426_Y + connect \$71 $pos$libresoc.v:35061$1427_Y + connect \$73 $eq$libresoc.v:35062$1428_Y + connect \$75 $eq$libresoc.v:35063$1429_Y + connect \$77 $pos$libresoc.v:35064$1430_Y + connect \$7 $eq$libresoc.v:35065$1431_Y + connect \$79 $eq$libresoc.v:35066$1432_Y + connect \$81 $eq$libresoc.v:35067$1433_Y + connect \$83 $pos$libresoc.v:35068$1434_Y + connect \$85 $eq$libresoc.v:35069$1435_Y + connect \$87 $eq$libresoc.v:35070$1436_Y + connect \$89 $pos$libresoc.v:35071$1437_Y + connect \$91 $eq$libresoc.v:35072$1438_Y + connect \$93 $eq$libresoc.v:35073$1439_Y + connect \$95 $pos$libresoc.v:35074$1440_Y + connect \$97 $eq$libresoc.v:35075$1441_Y connect \lz \cnt_6_0 connect \pair62 \sig_in [63:62] connect \pair60 \sig_in [61:60] @@ -56449,5116 +56932,5126 @@ module \clz connect \pair2 \sig_in [3:2] connect \pair0 \sig_in [1:0] end -attribute \src "libresoc.v:35745.1-48550.10" +attribute \src "libresoc.v:36213.1-49141.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core" attribute \generator "nMigen" module \core - attribute \src "libresoc.v:45520.3-45540.6" - wire $0\core_terminate_o$next[0:0]$2588 - attribute \src "libresoc.v:42412.3-42413.49" + attribute \src "libresoc.v:46587.3-46607.6" + wire $0\core_terminate_o$next[0:0]$2673 + attribute \src "libresoc.v:42982.3-42983.49" wire $0\core_terminate_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $0\corebusy_o[0:0] - attribute \src "libresoc.v:45345.3-45371.6" - wire width 2 $0\counter$next[1:0]$2565 - attribute \src "libresoc.v:42414.3-42415.31" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $0\counter$next[1:0]$2654 + attribute \src "libresoc.v:42984.3-42985.31" wire width 2 $0\counter[1:0] - attribute \src "libresoc.v:45830.3-45838.6" - wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 - attribute \src "libresoc.v:42348.3-42349.57" + attribute \src "libresoc.v:46412.3-46420.6" + wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 + attribute \src "libresoc.v:42918.3-42919.57" wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:45811.3-45819.6" - wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 - attribute \src "libresoc.v:42350.3-42351.49" + attribute \src "libresoc.v:46393.3-46401.6" + wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 + attribute \src "libresoc.v:42920.3-42921.49" wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:45849.3-45857.6" - wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 - attribute \src "libresoc.v:42346.3-42347.49" + attribute \src "libresoc.v:46458.3-46466.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 + attribute \src "libresoc.v:42916.3-42917.49" wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:45898.3-45906.6" - wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 - attribute \src "libresoc.v:42344.3-42345.49" + attribute \src "libresoc.v:46568.3-46576.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 + attribute \src "libresoc.v:42914.3-42915.49" wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:45762.3-45770.6" - wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 - attribute \src "libresoc.v:42352.3-42353.55" + attribute \src "libresoc.v:46374.3-46382.6" + wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 + attribute \src "libresoc.v:42922.3-42923.55" wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:45917.3-45925.6" - wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 - attribute \src "libresoc.v:42342.3-42343.63" + attribute \src "libresoc.v:46608.3-46616.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 + attribute \src "libresoc.v:42912.3-42913.63" wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:45984.3-45992.6" - wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 - attribute \src "libresoc.v:42338.3-42339.57" + attribute \src "libresoc.v:46675.3-46683.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 + attribute \src "libresoc.v:42908.3-42909.57" wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:45936.3-45944.6" - wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 - attribute \src "libresoc.v:42340.3-42341.59" + attribute \src "libresoc.v:46627.3-46635.6" + wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 + attribute \src "libresoc.v:42910.3-42911.59" wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46032.3-46040.6" - wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 - attribute \src "libresoc.v:42336.3-42337.63" + attribute \src "libresoc.v:46723.3-46731.6" + wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 + attribute \src "libresoc.v:42906.3-42907.63" wire $0\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46051.3-46059.6" - wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 - attribute \src "libresoc.v:42334.3-42335.59" + attribute \src "libresoc.v:46742.3-46750.6" + wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 + attribute \src "libresoc.v:42904.3-42905.59" wire $0\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:44984.3-44992.6" - wire $0\dp_INT_ra_alu0_0$next[0:0]$2457 - attribute \src "libresoc.v:42410.3-42411.49" + attribute \src "libresoc.v:45823.3-45831.6" + wire $0\dp_INT_ra_alu0_0$next[0:0]$2474 + attribute \src "libresoc.v:42980.3-42981.49" wire $0\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45003.3-45011.6" - wire $0\dp_INT_ra_cr0_1$next[0:0]$2461 - attribute \src "libresoc.v:42408.3-42409.47" + attribute \src "libresoc.v:45842.3-45850.6" + wire $0\dp_INT_ra_cr0_1$next[0:0]$2478 + attribute \src "libresoc.v:42978.3-42979.47" wire $0\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45079.3-45087.6" - wire $0\dp_INT_ra_div0_5$next[0:0]$2485 - attribute \src "libresoc.v:42400.3-42401.49" + attribute \src "libresoc.v:45918.3-45926.6" + wire $0\dp_INT_ra_div0_5$next[0:0]$2502 + attribute \src "libresoc.v:42970.3-42971.49" wire $0\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45136.3-45144.6" - wire $0\dp_INT_ra_ldst0_8$next[0:0]$2503 - attribute \src "libresoc.v:42394.3-42395.51" + attribute \src "libresoc.v:45975.3-45983.6" + wire $0\dp_INT_ra_ldst0_8$next[0:0]$2520 + attribute \src "libresoc.v:42964.3-42965.51" wire $0\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45041.3-45049.6" - wire $0\dp_INT_ra_logical0_3$next[0:0]$2473 - attribute \src "libresoc.v:42404.3-42405.57" + attribute \src "libresoc.v:45880.3-45888.6" + wire $0\dp_INT_ra_logical0_3$next[0:0]$2490 + attribute \src "libresoc.v:42974.3-42975.57" wire $0\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45098.3-45106.6" - wire $0\dp_INT_ra_mul0_6$next[0:0]$2491 - attribute \src "libresoc.v:42398.3-42399.49" + attribute \src "libresoc.v:45937.3-45945.6" + wire $0\dp_INT_ra_mul0_6$next[0:0]$2508 + attribute \src "libresoc.v:42968.3-42969.49" wire $0\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45117.3-45125.6" - wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 - attribute \src "libresoc.v:42396.3-42397.59" + attribute \src "libresoc.v:45956.3-45964.6" + wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 + attribute \src "libresoc.v:42966.3-42967.59" wire $0\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45060.3-45068.6" - wire $0\dp_INT_ra_spr0_4$next[0:0]$2479 - attribute \src "libresoc.v:42402.3-42403.49" + attribute \src "libresoc.v:45899.3-45907.6" + wire $0\dp_INT_ra_spr0_4$next[0:0]$2496 + attribute \src "libresoc.v:42972.3-42973.49" wire $0\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45022.3-45030.6" - wire $0\dp_INT_ra_trap0_2$next[0:0]$2467 - attribute \src "libresoc.v:42406.3-42407.51" + attribute \src "libresoc.v:45861.3-45869.6" + wire $0\dp_INT_ra_trap0_2$next[0:0]$2484 + attribute \src "libresoc.v:42976.3-42977.51" wire $0\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45155.3-45163.6" - wire $0\dp_INT_rb_alu0_0$next[0:0]$2509 - attribute \src "libresoc.v:42392.3-42393.49" + attribute \src "libresoc.v:45994.3-46002.6" + wire $0\dp_INT_rb_alu0_0$next[0:0]$2526 + attribute \src "libresoc.v:42962.3-42963.49" wire $0\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:45174.3-45182.6" - wire $0\dp_INT_rb_cr0_1$next[0:0]$2513 - attribute \src "libresoc.v:42390.3-42391.47" + attribute \src "libresoc.v:46013.3-46021.6" + wire $0\dp_INT_rb_cr0_1$next[0:0]$2530 + attribute \src "libresoc.v:42960.3-42961.47" wire $0\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:45231.3-45239.6" - wire $0\dp_INT_rb_div0_4$next[0:0]$2531 - attribute \src "libresoc.v:42384.3-42385.49" + attribute \src "libresoc.v:46070.3-46078.6" + wire $0\dp_INT_rb_div0_4$next[0:0]$2548 + attribute \src "libresoc.v:42954.3-42955.49" wire $0\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:45288.3-45296.6" - wire $0\dp_INT_rb_ldst0_7$next[0:0]$2549 - attribute \src "libresoc.v:42378.3-42379.51" + attribute \src "libresoc.v:46127.3-46135.6" + wire $0\dp_INT_rb_ldst0_7$next[0:0]$2566 + attribute \src "libresoc.v:42948.3-42949.51" wire $0\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:45212.3-45220.6" - wire $0\dp_INT_rb_logical0_3$next[0:0]$2525 - attribute \src "libresoc.v:42386.3-42387.57" + attribute \src "libresoc.v:46051.3-46059.6" + wire $0\dp_INT_rb_logical0_3$next[0:0]$2542 + attribute \src "libresoc.v:42956.3-42957.57" wire $0\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:45250.3-45258.6" - wire $0\dp_INT_rb_mul0_5$next[0:0]$2537 - attribute \src "libresoc.v:42382.3-42383.49" + attribute \src "libresoc.v:46089.3-46097.6" + wire $0\dp_INT_rb_mul0_5$next[0:0]$2554 + attribute \src "libresoc.v:42952.3-42953.49" wire $0\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:45269.3-45277.6" - wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 - attribute \src "libresoc.v:42380.3-42381.59" + attribute \src "libresoc.v:46108.3-46116.6" + wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 + attribute \src "libresoc.v:42950.3-42951.59" wire $0\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:45193.3-45201.6" - wire $0\dp_INT_rb_trap0_2$next[0:0]$2519 - attribute \src "libresoc.v:42388.3-42389.51" + attribute \src "libresoc.v:46032.3-46040.6" + wire $0\dp_INT_rb_trap0_2$next[0:0]$2536 + attribute \src "libresoc.v:42958.3-42959.51" wire $0\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:45326.3-45334.6" - wire $0\dp_INT_rc_ldst0_1$next[0:0]$2559 - attribute \src "libresoc.v:42374.3-42375.51" + attribute \src "libresoc.v:46165.3-46173.6" + wire $0\dp_INT_rc_ldst0_1$next[0:0]$2576 + attribute \src "libresoc.v:42944.3-42945.51" wire $0\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:45307.3-45315.6" - wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 - attribute \src "libresoc.v:42376.3-42377.59" + attribute \src "libresoc.v:46146.3-46154.6" + wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 + attribute \src "libresoc.v:42946.3-42947.59" wire $0\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46099.3-46107.6" - wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 - attribute \src "libresoc.v:42332.3-42333.53" + attribute \src "libresoc.v:46791.3-46799.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 + attribute \src "libresoc.v:42902.3-42903.53" wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45627.3-45635.6" - wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 - attribute \src "libresoc.v:42360.3-42361.57" + attribute \src "libresoc.v:46298.3-46306.6" + wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 + attribute \src "libresoc.v:42930.3-42931.57" wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45694.3-45702.6" - wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 - attribute \src "libresoc.v:42356.3-42357.67" + attribute \src "libresoc.v:46336.3-46344.6" + wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 + attribute \src "libresoc.v:42926.3-42927.67" wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45675.3-45683.6" - wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 - attribute \src "libresoc.v:42358.3-42359.57" + attribute \src "libresoc.v:46317.3-46325.6" + wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 + attribute \src "libresoc.v:42928.3-42929.57" wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:45743.3-45751.6" - wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 - attribute \src "libresoc.v:42354.3-42355.57" + attribute \src "libresoc.v:46355.3-46363.6" + wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 + attribute \src "libresoc.v:42924.3-42925.57" wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:45372.3-45380.6" - wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 - attribute \src "libresoc.v:42372.3-42373.57" + attribute \src "libresoc.v:46184.3-46192.6" + wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 + attribute \src "libresoc.v:42942.3-42943.57" wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45541.3-45549.6" - wire $0\dp_XER_xer_so_div0_3$next[0:0]$2593 - attribute \src "libresoc.v:42366.3-42367.57" + attribute \src "libresoc.v:46241.3-46249.6" + wire $0\dp_XER_xer_so_div0_3$next[0:0]$2598 + attribute \src "libresoc.v:42936.3-42937.57" wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:45482.3-45490.6" - wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 - attribute \src "libresoc.v:42370.3-42371.65" + attribute \src "libresoc.v:46203.3-46211.6" + wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 + attribute \src "libresoc.v:42940.3-42941.65" wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45560.3-45568.6" - wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 - attribute \src "libresoc.v:42364.3-42365.57" + attribute \src "libresoc.v:46260.3-46268.6" + wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 + attribute \src "libresoc.v:42934.3-42935.57" wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45608.3-45616.6" - wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 - attribute \src "libresoc.v:42362.3-42363.67" + attribute \src "libresoc.v:46279.3-46287.6" + wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 + attribute \src "libresoc.v:42932.3-42933.67" wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:45501.3-45509.6" - wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 - attribute \src "libresoc.v:42368.3-42369.57" + attribute \src "libresoc.v:46222.3-46230.6" + wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 + attribute \src "libresoc.v:42938.3-42939.57" wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46619.3-46647.6" - wire $0\fus_cu_issue_i$11[0:0]$2768 - attribute \src "libresoc.v:47016.3-47044.6" - wire $0\fus_cu_issue_i$14[0:0]$2830 - attribute \src "libresoc.v:47380.3-47408.6" - wire $0\fus_cu_issue_i$17[0:0]$2864 - attribute \src "libresoc.v:47876.3-47904.6" - wire $0\fus_cu_issue_i$20[0:0]$2889 - attribute \src "libresoc.v:43203.3-43231.6" - wire $0\fus_cu_issue_i$23[0:0]$2356 - attribute \src "libresoc.v:43699.3-43727.6" - wire $0\fus_cu_issue_i$26[0:0]$2381 - attribute \src "libresoc.v:44021.3-44049.6" - wire $0\fus_cu_issue_i$29[0:0]$2400 - attribute \src "libresoc.v:44488.3-44516.6" - wire $0\fus_cu_issue_i$32[0:0]$2424 - attribute \src "libresoc.v:44926.3-44954.6" - wire $0\fus_cu_issue_i$35[0:0]$2447 - attribute \src "libresoc.v:46411.3-46439.6" + attribute \src "libresoc.v:47566.3-47594.6" + wire $0\fus_cu_issue_i$13[0:0]$2821 + attribute \src "libresoc.v:47900.3-47928.6" + wire $0\fus_cu_issue_i$16[0:0]$2862 + attribute \src "libresoc.v:48219.3-48247.6" + wire $0\fus_cu_issue_i$19[0:0]$2881 + attribute \src "libresoc.v:43868.3-43896.6" + wire $0\fus_cu_issue_i$22[0:0]$2359 + attribute \src "libresoc.v:44042.3-44070.6" + wire $0\fus_cu_issue_i$25[0:0]$2373 + attribute \src "libresoc.v:44538.3-44566.6" + wire $0\fus_cu_issue_i$28[0:0]$2398 + attribute \src "libresoc.v:44860.3-44888.6" + wire $0\fus_cu_issue_i$31[0:0]$2417 + attribute \src "libresoc.v:45327.3-45355.6" + wire $0\fus_cu_issue_i$34[0:0]$2441 + attribute \src "libresoc.v:45765.3-45793.6" + wire $0\fus_cu_issue_i$37[0:0]$2464 + attribute \src "libresoc.v:47349.3-47377.6" wire $0\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46657.3-46685.6" - wire width 6 $0\fus_cu_rdmaskn_i$13[5:0]$2776 - attribute \src "libresoc.v:47054.3-47082.6" - wire width 3 $0\fus_cu_rdmaskn_i$16[2:0]$2838 - attribute \src "libresoc.v:47409.3-47437.6" - wire width 4 $0\fus_cu_rdmaskn_i$19[3:0]$2869 - attribute \src "libresoc.v:47905.3-47933.6" - wire width 3 $0\fus_cu_rdmaskn_i$22[2:0]$2894 - attribute \src "libresoc.v:43232.3-43260.6" - wire width 6 $0\fus_cu_rdmaskn_i$25[5:0]$2361 - attribute \src "libresoc.v:43728.3-43756.6" - wire width 3 $0\fus_cu_rdmaskn_i$28[2:0]$2386 - attribute \src "libresoc.v:44050.3-44078.6" - wire width 3 $0\fus_cu_rdmaskn_i$31[2:0]$2405 - attribute \src "libresoc.v:44517.3-44545.6" - wire width 5 $0\fus_cu_rdmaskn_i$34[4:0]$2429 - attribute \src "libresoc.v:44955.3-44983.6" - wire width 3 $0\fus_cu_rdmaskn_i$37[2:0]$2452 - attribute \src "libresoc.v:46449.3-46477.6" + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2829 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2867 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2886 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2364 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2378 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2403 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2422 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2446 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2469 + attribute \src "libresoc.v:47396.3-47424.6" wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46326.3-46354.6" + attribute \src "libresoc.v:47273.3-47301.6" wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45636.3-45664.6" - wire width 12 $0\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45703.3-45732.6" + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $0\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45703.3-45732.6" + attribute \src "libresoc.v:46761.3-46790.6" wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46156.3-46184.6" + attribute \src "libresoc.v:47094.3-47122.6" wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46373.3-46401.6" + attribute \src "libresoc.v:47311.3-47339.6" wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45579.3-45607.6" + attribute \src "libresoc.v:46646.3-46674.6" wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45955.3-45983.6" + attribute \src "libresoc.v:46933.3-46961.6" wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46070.3-46098.6" + attribute \src "libresoc.v:47018.3-47046.6" wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46241.3-46269.6" + attribute \src "libresoc.v:47188.3-47216.6" wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46288.3-46316.6" + attribute \src "libresoc.v:47226.3-47254.6" wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45868.3-45897.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:45868.3-45897.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46203.3-46231.6" + attribute \src "libresoc.v:47141.3-47169.6" wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45781.3-45810.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45781.3-45810.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46118.3-46146.6" + attribute \src "libresoc.v:47056.3-47084.6" wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46003.3-46031.6" + attribute \src "libresoc.v:46980.3-47008.6" wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46704.3-46732.6" + attribute \src "libresoc.v:47651.3-47679.6" wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46789.3-46817.6" - wire width 12 $0\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46874.3-46903.6" + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $0\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:46874.3-46903.6" + attribute \src "libresoc.v:47812.3-47841.6" wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46827.3-46855.6" + attribute \src "libresoc.v:47774.3-47802.6" wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46742.3-46770.6" + attribute \src "libresoc.v:47689.3-47717.6" wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46969.3-46997.6" + attribute \src "libresoc.v:47871.3-47899.6" wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46931.3-46959.6" + attribute \src "libresoc.v:47842.3-47870.6" wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46534.3-46562.6" - wire width 12 $0\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46581.3-46609.6" + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $0\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46487.3-46515.6" + attribute \src "libresoc.v:47434.3-47462.6" wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43641.3-43669.6" + attribute \src "libresoc.v:44480.3-44508.6" wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43290.3-43318.6" - wire width 12 $0\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43319.3-43348.6" + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $0\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43319.3-43348.6" + attribute \src "libresoc.v:44158.3-44187.6" wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43467.3-43495.6" + attribute \src "libresoc.v:44306.3-44334.6" wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43670.3-43698.6" + attribute \src "libresoc.v:44509.3-44537.6" wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43261.3-43289.6" + attribute \src "libresoc.v:44100.3-44128.6" wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43409.3-43437.6" + attribute \src "libresoc.v:44248.3-44276.6" wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43496.3-43524.6" + attribute \src "libresoc.v:44335.3-44363.6" wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43583.3-43611.6" + attribute \src "libresoc.v:44422.3-44450.6" wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43612.3-43640.6" + attribute \src "libresoc.v:44451.3-44479.6" wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43379.3-43408.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43379.3-43408.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43554.3-43582.6" + attribute \src "libresoc.v:44393.3-44421.6" wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43349.3-43378.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43349.3-43378.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43525.3-43553.6" + attribute \src "libresoc.v:44364.3-44392.6" wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43438.3-43466.6" + attribute \src "libresoc.v:44277.3-44305.6" wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:47818.3-47846.6" + attribute \src "libresoc.v:43810.3-43838.6" wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47467.3-47495.6" - wire width 12 $0\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47496.3-47525.6" + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $0\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47496.3-47525.6" + attribute \src "libresoc.v:48335.3-48364.6" wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47644.3-47672.6" + attribute \src "libresoc.v:48483.3-48511.6" wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47847.3-47875.6" + attribute \src "libresoc.v:43839.3-43867.6" wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47438.3-47466.6" + attribute \src "libresoc.v:48277.3-48305.6" wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47586.3-47614.6" + attribute \src "libresoc.v:48425.3-48453.6" wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47673.3-47701.6" + attribute \src "libresoc.v:48512.3-48540.6" wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47760.3-47788.6" + attribute \src "libresoc.v:43752.3-43780.6" wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47789.3-47817.6" + attribute \src "libresoc.v:43781.3-43809.6" wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47556.3-47585.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47556.3-47585.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47731.3-47759.6" + attribute \src "libresoc.v:43723.3-43751.6" wire $0\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47526.3-47555.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47526.3-47555.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47702.3-47730.6" + attribute \src "libresoc.v:48541.3-48569.6" wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47615.3-47643.6" + attribute \src "libresoc.v:48454.3-48482.6" wire $0\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43786.3-43814.6" - wire width 12 $0\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43815.3-43844.6" + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $0\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:43815.3-43844.6" + attribute \src "libresoc.v:44654.3-44683.6" wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43992.3-44020.6" + attribute \src "libresoc.v:44831.3-44859.6" wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43757.3-43785.6" + attribute \src "libresoc.v:44596.3-44624.6" wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43934.3-43962.6" + attribute \src "libresoc.v:44773.3-44801.6" wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43963.3-43991.6" + attribute \src "libresoc.v:44802.3-44830.6" wire $0\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43875.3-43904.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:43875.3-43904.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43845.3-43874.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:43845.3-43874.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43905.3-43933.6" + attribute \src "libresoc.v:44744.3-44772.6" wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44108.3-44136.6" - wire width 12 $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44137.3-44166.6" + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44137.3-44166.6" + attribute \src "libresoc.v:44976.3-45005.6" wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44285.3-44313.6" + attribute \src "libresoc.v:45124.3-45152.6" wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44343.3-44371.6" + attribute \src "libresoc.v:45182.3-45210.6" wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44459.3-44487.6" + attribute \src "libresoc.v:45298.3-45326.6" wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44079.3-44107.6" + attribute \src "libresoc.v:44918.3-44946.6" wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44256.3-44284.6" + attribute \src "libresoc.v:45095.3-45123.6" wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44401.3-44429.6" + attribute \src "libresoc.v:45240.3-45268.6" wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44430.3-44458.6" + attribute \src "libresoc.v:45269.3-45297.6" wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44197.3-44226.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44197.3-44226.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44314.3-44342.6" + attribute \src "libresoc.v:45153.3-45181.6" wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44372.3-44400.6" + attribute \src "libresoc.v:45211.3-45239.6" wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44167.3-44196.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44167.3-44196.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44227.3-44255.6" + attribute \src "libresoc.v:45066.3-45094.6" wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:47963.3-47991.6" - wire width 12 $0\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:43145.3-43173.6" + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $0\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47934.3-47962.6" + attribute \src "libresoc.v:43926.3-43954.6" wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43174.3-43202.6" + attribute \src "libresoc.v:44013.3-44041.6" wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47235.3-47263.6" + attribute \src "libresoc.v:48074.3-48102.6" wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47139.3-47167.6" - wire width 12 $0\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:47177.3-47205.6" + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $0\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47092.3-47120.6" + attribute \src "libresoc.v:47958.3-47986.6" wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47264.3-47292.6" + attribute \src "libresoc.v:48103.3-48131.6" wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47351.3-47379.6" + attribute \src "libresoc.v:48190.3-48218.6" wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47206.3-47234.6" + attribute \src "libresoc.v:48045.3-48073.6" wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47322.3-47350.6" + attribute \src "libresoc.v:48161.3-48189.6" wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47293.3-47321.6" + attribute \src "libresoc.v:48132.3-48160.6" wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:44810.3-44838.6" + attribute \src "libresoc.v:45649.3-45677.6" wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44781.3-44809.6" + attribute \src "libresoc.v:45620.3-45648.6" wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44575.3-44603.6" - wire width 12 $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44604.3-44633.6" + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44604.3-44633.6" + attribute \src "libresoc.v:45443.3-45472.6" wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44897.3-44925.6" + attribute \src "libresoc.v:45736.3-45764.6" wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44546.3-44574.6" + attribute \src "libresoc.v:45385.3-45413.6" wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44723.3-44751.6" + attribute \src "libresoc.v:45562.3-45590.6" wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44752.3-44780.6" + attribute \src "libresoc.v:45591.3-45619.6" wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44868.3-44896.6" + attribute \src "libresoc.v:45707.3-45735.6" wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44693.3-44722.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44693.3-44722.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44663.3-44692.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44663.3-44692.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44839.3-44867.6" + attribute \src "libresoc.v:45678.3-45706.6" wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44634.3-44662.6" + attribute \src "libresoc.v:45473.3-45501.6" wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45012.3-45021.6" - wire width 64 $0\fus_src1_i$40[63:0]$2464 - attribute \src "libresoc.v:45031.3-45040.6" - wire width 64 $0\fus_src1_i$43[63:0]$2470 - attribute \src "libresoc.v:45050.3-45059.6" - wire width 64 $0\fus_src1_i$46[63:0]$2476 - attribute \src "libresoc.v:45069.3-45078.6" - wire width 64 $0\fus_src1_i$49[63:0]$2482 - attribute \src "libresoc.v:45088.3-45097.6" - wire width 64 $0\fus_src1_i$52[63:0]$2488 - attribute \src "libresoc.v:45107.3-45116.6" - wire width 64 $0\fus_src1_i$55[63:0]$2494 - attribute \src "libresoc.v:45126.3-45135.6" - wire width 64 $0\fus_src1_i$58[63:0]$2500 - attribute \src "libresoc.v:45145.3-45154.6" - wire width 64 $0\fus_src1_i$61[63:0]$2506 - attribute \src "libresoc.v:45926.3-45935.6" - wire width 64 $0\fus_src1_i$84[63:0]$2669 - attribute \src "libresoc.v:44993.3-45002.6" + attribute \src "libresoc.v:45851.3-45860.6" + wire width 64 $0\fus_src1_i$42[63:0]$2481 + attribute \src "libresoc.v:45870.3-45879.6" + wire width 64 $0\fus_src1_i$45[63:0]$2487 + attribute \src "libresoc.v:45889.3-45898.6" + wire width 64 $0\fus_src1_i$48[63:0]$2493 + attribute \src "libresoc.v:45908.3-45917.6" + wire width 64 $0\fus_src1_i$51[63:0]$2499 + attribute \src "libresoc.v:45927.3-45936.6" + wire width 64 $0\fus_src1_i$54[63:0]$2505 + attribute \src "libresoc.v:45946.3-45955.6" + wire width 64 $0\fus_src1_i$57[63:0]$2511 + attribute \src "libresoc.v:45965.3-45974.6" + wire width 64 $0\fus_src1_i$60[63:0]$2517 + attribute \src "libresoc.v:45984.3-45993.6" + wire width 64 $0\fus_src1_i$63[63:0]$2523 + attribute \src "libresoc.v:46617.3-46626.6" + wire width 64 $0\fus_src1_i$86[63:0]$2681 + attribute \src "libresoc.v:45832.3-45841.6" wire width 64 $0\fus_src1_i[63:0] - attribute \src "libresoc.v:45183.3-45192.6" - wire width 64 $0\fus_src2_i$62[63:0]$2516 - attribute \src "libresoc.v:45202.3-45211.6" - wire width 64 $0\fus_src2_i$63[63:0]$2522 - attribute \src "libresoc.v:45221.3-45230.6" - wire width 64 $0\fus_src2_i$64[63:0]$2528 - attribute \src "libresoc.v:45240.3-45249.6" - wire width 64 $0\fus_src2_i$65[63:0]$2534 - attribute \src "libresoc.v:45259.3-45268.6" - wire width 64 $0\fus_src2_i$66[63:0]$2540 - attribute \src "libresoc.v:45278.3-45287.6" - wire width 64 $0\fus_src2_i$67[63:0]$2546 - attribute \src "libresoc.v:45297.3-45306.6" - wire width 64 $0\fus_src2_i$68[63:0]$2552 + attribute \src "libresoc.v:46022.3-46031.6" + wire width 64 $0\fus_src2_i$64[63:0]$2533 attribute \src "libresoc.v:46041.3-46050.6" - wire width 64 $0\fus_src2_i$87[63:0]$2689 - attribute \src "libresoc.v:46108.3-46117.6" - wire width 64 $0\fus_src2_i$89[63:0]$2702 - attribute \src "libresoc.v:45164.3-45173.6" + wire width 64 $0\fus_src2_i$65[63:0]$2539 + attribute \src "libresoc.v:46060.3-46069.6" + wire width 64 $0\fus_src2_i$66[63:0]$2545 + attribute \src "libresoc.v:46079.3-46088.6" + wire width 64 $0\fus_src2_i$67[63:0]$2551 + attribute \src "libresoc.v:46098.3-46107.6" + wire width 64 $0\fus_src2_i$68[63:0]$2557 + attribute \src "libresoc.v:46117.3-46126.6" + wire width 64 $0\fus_src2_i$69[63:0]$2563 + attribute \src "libresoc.v:46136.3-46145.6" + wire width 64 $0\fus_src2_i$70[63:0]$2569 + attribute \src "libresoc.v:46732.3-46741.6" + wire width 64 $0\fus_src2_i$89[63:0]$2701 + attribute \src "libresoc.v:46800.3-46809.6" + wire width 64 $0\fus_src2_i$91[63:0]$2714 + attribute \src "libresoc.v:46003.3-46012.6" wire width 64 $0\fus_src2_i[63:0] - attribute \src "libresoc.v:45335.3-45344.6" - wire width 64 $0\fus_src3_i$69[63:0]$2562 - attribute \src "libresoc.v:45381.3-45390.6" - wire $0\fus_src3_i$70[0:0]$2574 - attribute \src "libresoc.v:45491.3-45500.6" - wire $0\fus_src3_i$71[0:0]$2581 - attribute \src "libresoc.v:45550.3-45559.6" - wire $0\fus_src3_i$72[0:0]$2596 - attribute \src "libresoc.v:45569.3-45578.6" - wire $0\fus_src3_i$73[0:0]$2602 - attribute \src "libresoc.v:45771.3-45780.6" - wire width 32 $0\fus_src3_i$77[31:0]$2637 - attribute \src "libresoc.v:45839.3-45848.6" - wire width 4 $0\fus_src3_i$81[3:0]$2650 - attribute \src "libresoc.v:45945.3-45954.6" - wire width 64 $0\fus_src3_i$85[63:0]$2675 - attribute \src "libresoc.v:45993.3-46002.6" - wire width 64 $0\fus_src3_i$86[63:0]$2682 - attribute \src "libresoc.v:45316.3-45325.6" + attribute \src "libresoc.v:46174.3-46183.6" + wire width 64 $0\fus_src3_i$71[63:0]$2579 + attribute \src "libresoc.v:46193.3-46202.6" + wire $0\fus_src3_i$72[0:0]$2585 + attribute \src "libresoc.v:46212.3-46221.6" + wire $0\fus_src3_i$73[0:0]$2591 + attribute \src "libresoc.v:46250.3-46259.6" + wire $0\fus_src3_i$74[0:0]$2601 + attribute \src "libresoc.v:46269.3-46278.6" + wire $0\fus_src3_i$75[0:0]$2607 + attribute \src "libresoc.v:46383.3-46392.6" + wire width 32 $0\fus_src3_i$79[31:0]$2639 + attribute \src "libresoc.v:46421.3-46430.6" + wire width 4 $0\fus_src3_i$83[3:0]$2651 + attribute \src "libresoc.v:46636.3-46645.6" + wire width 64 $0\fus_src3_i$87[63:0]$2687 + attribute \src "libresoc.v:46684.3-46693.6" + wire width 64 $0\fus_src3_i$88[63:0]$2694 + attribute \src "libresoc.v:46155.3-46164.6" wire width 64 $0\fus_src3_i[63:0] - attribute \src "libresoc.v:45617.3-45626.6" - wire $0\fus_src4_i$74[0:0]$2609 - attribute \src "libresoc.v:45665.3-45674.6" - wire width 2 $0\fus_src4_i$75[1:0]$2616 - attribute \src "libresoc.v:45820.3-45829.6" - wire width 4 $0\fus_src4_i$78[3:0]$2644 - attribute \src "libresoc.v:46060.3-46069.6" - wire width 64 $0\fus_src4_i$88[63:0]$2695 - attribute \src "libresoc.v:45510.3-45519.6" + attribute \src "libresoc.v:46288.3-46297.6" + wire $0\fus_src4_i$76[0:0]$2613 + attribute \src "libresoc.v:46307.3-46316.6" + wire width 2 $0\fus_src4_i$77[1:0]$2619 + attribute \src "libresoc.v:46402.3-46411.6" + wire width 4 $0\fus_src4_i$80[3:0]$2645 + attribute \src "libresoc.v:46751.3-46760.6" + wire width 64 $0\fus_src4_i$90[63:0]$2707 + attribute \src "libresoc.v:46231.3-46240.6" wire $0\fus_src4_i[0:0] - attribute \src "libresoc.v:45752.3-45761.6" - wire width 2 $0\fus_src5_i$76[1:0]$2631 - attribute \src "libresoc.v:45858.3-45867.6" - wire width 4 $0\fus_src5_i$82[3:0]$2656 - attribute \src "libresoc.v:45733.3-45742.6" + attribute \src "libresoc.v:46364.3-46373.6" + wire width 2 $0\fus_src5_i$78[1:0]$2633 + attribute \src "libresoc.v:46467.3-46476.6" + wire width 4 $0\fus_src5_i$84[3:0]$2663 + attribute \src "libresoc.v:46345.3-46354.6" wire width 2 $0\fus_src5_i[1:0] - attribute \src "libresoc.v:45907.3-45916.6" - wire width 4 $0\fus_src6_i$83[3:0]$2663 - attribute \src "libresoc.v:45684.3-45693.6" + attribute \src "libresoc.v:46577.3-46586.6" + wire width 4 $0\fus_src6_i$85[3:0]$2670 + attribute \src "libresoc.v:46326.3-46335.6" wire width 2 $0\fus_src6_i[1:0] - attribute \src "libresoc.v:35746.7-35746.20" + attribute \src "libresoc.v:36214.7-36214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:46194.3-46202.6" - wire $0\wr_pick_dly$1000$next[0:0]$2713 - attribute \src "libresoc.v:42326.3-42327.51" - wire $0\wr_pick_dly$1000[0:0]$2307 - attribute \src "libresoc.v:41156.7-41156.32" - wire $0\wr_pick_dly$1000[0:0]$2945 - attribute \src "libresoc.v:46232.3-46240.6" - wire $0\wr_pick_dly$1021$next[0:0]$2717 - attribute \src "libresoc.v:42324.3-42325.51" - wire $0\wr_pick_dly$1021[0:0]$2305 - attribute \src "libresoc.v:41160.7-41160.32" - wire $0\wr_pick_dly$1021[0:0]$2947 - attribute \src "libresoc.v:46270.3-46278.6" - wire $0\wr_pick_dly$1039$next[0:0]$2721 - attribute \src "libresoc.v:42322.3-42323.51" - wire $0\wr_pick_dly$1039[0:0]$2303 - attribute \src "libresoc.v:41164.7-41164.32" - wire $0\wr_pick_dly$1039[0:0]$2949 - attribute \src "libresoc.v:46279.3-46287.6" - wire $0\wr_pick_dly$1061$next[0:0]$2724 - attribute \src "libresoc.v:42320.3-42321.51" - wire $0\wr_pick_dly$1061[0:0]$2301 - attribute \src "libresoc.v:41168.7-41168.32" - wire $0\wr_pick_dly$1061[0:0]$2951 - attribute \src "libresoc.v:46317.3-46325.6" - wire $0\wr_pick_dly$1081$next[0:0]$2728 - attribute \src "libresoc.v:42318.3-42319.51" - wire $0\wr_pick_dly$1081[0:0]$2299 - attribute \src "libresoc.v:41172.7-41172.32" - wire $0\wr_pick_dly$1081[0:0]$2953 - attribute \src "libresoc.v:46355.3-46363.6" - wire $0\wr_pick_dly$1101$next[0:0]$2732 - attribute \src "libresoc.v:42316.3-42317.51" - wire $0\wr_pick_dly$1101[0:0]$2297 - attribute \src "libresoc.v:41176.7-41176.32" - wire $0\wr_pick_dly$1101[0:0]$2955 - attribute \src "libresoc.v:46364.3-46372.6" - wire $0\wr_pick_dly$1120$next[0:0]$2735 - attribute \src "libresoc.v:42314.3-42315.51" - wire $0\wr_pick_dly$1120[0:0]$2295 - attribute \src "libresoc.v:41180.7-41180.32" - wire $0\wr_pick_dly$1120[0:0]$2957 - attribute \src "libresoc.v:46402.3-46410.6" - wire $0\wr_pick_dly$1138$next[0:0]$2739 - attribute \src "libresoc.v:42312.3-42313.51" - wire $0\wr_pick_dly$1138[0:0]$2293 - attribute \src "libresoc.v:41184.7-41184.32" - wire $0\wr_pick_dly$1138[0:0]$2959 - attribute \src "libresoc.v:46440.3-46448.6" - wire $0\wr_pick_dly$1211$next[0:0]$2743 - attribute \src "libresoc.v:42310.3-42311.51" - wire $0\wr_pick_dly$1211[0:0]$2291 - attribute \src "libresoc.v:41188.7-41188.32" - wire $0\wr_pick_dly$1211[0:0]$2961 - attribute \src "libresoc.v:46478.3-46486.6" - wire $0\wr_pick_dly$1239$next[0:0]$2747 - attribute \src "libresoc.v:42308.3-42309.51" - wire $0\wr_pick_dly$1239[0:0]$2289 - attribute \src "libresoc.v:41192.7-41192.32" - wire $0\wr_pick_dly$1239[0:0]$2963 - attribute \src "libresoc.v:46516.3-46524.6" - wire $0\wr_pick_dly$1259$next[0:0]$2751 - attribute \src "libresoc.v:42306.3-42307.51" - wire $0\wr_pick_dly$1259[0:0]$2287 - attribute \src "libresoc.v:41196.7-41196.32" - wire $0\wr_pick_dly$1259[0:0]$2965 - attribute \src "libresoc.v:46525.3-46533.6" - wire $0\wr_pick_dly$1279$next[0:0]$2754 - attribute \src "libresoc.v:42304.3-42305.51" - wire $0\wr_pick_dly$1279[0:0]$2285 - attribute \src "libresoc.v:41200.7-41200.32" - wire $0\wr_pick_dly$1279[0:0]$2967 - attribute \src "libresoc.v:46563.3-46571.6" - wire $0\wr_pick_dly$1299$next[0:0]$2758 - attribute \src "libresoc.v:42302.3-42303.51" - wire $0\wr_pick_dly$1299[0:0]$2283 - attribute \src "libresoc.v:41204.7-41204.32" - wire $0\wr_pick_dly$1299[0:0]$2969 - attribute \src "libresoc.v:46572.3-46580.6" - wire $0\wr_pick_dly$1319$next[0:0]$2761 - attribute \src "libresoc.v:42300.3-42301.51" - wire $0\wr_pick_dly$1319[0:0]$2281 - attribute \src "libresoc.v:41208.7-41208.32" - wire $0\wr_pick_dly$1319[0:0]$2971 - attribute \src "libresoc.v:46610.3-46618.6" - wire $0\wr_pick_dly$1339$next[0:0]$2765 - attribute \src "libresoc.v:42298.3-42299.51" - wire $0\wr_pick_dly$1339[0:0]$2279 - attribute \src "libresoc.v:41212.7-41212.32" - wire $0\wr_pick_dly$1339[0:0]$2973 - attribute \src "libresoc.v:46648.3-46656.6" - wire $0\wr_pick_dly$1386$next[0:0]$2773 - attribute \src "libresoc.v:42296.3-42297.51" - wire $0\wr_pick_dly$1386[0:0]$2277 - attribute \src "libresoc.v:41216.7-41216.32" - wire $0\wr_pick_dly$1386[0:0]$2975 - attribute \src "libresoc.v:46686.3-46694.6" - wire $0\wr_pick_dly$1402$next[0:0]$2781 - attribute \src "libresoc.v:42294.3-42295.51" - wire $0\wr_pick_dly$1402[0:0]$2275 - attribute \src "libresoc.v:41220.7-41220.32" - wire $0\wr_pick_dly$1402[0:0]$2977 - attribute \src "libresoc.v:46695.3-46703.6" - wire $0\wr_pick_dly$1418$next[0:0]$2784 - attribute \src "libresoc.v:42292.3-42293.51" - wire $0\wr_pick_dly$1418[0:0]$2273 - attribute \src "libresoc.v:41224.7-41224.32" - wire $0\wr_pick_dly$1418[0:0]$2979 - attribute \src "libresoc.v:46733.3-46741.6" - wire $0\wr_pick_dly$1452$next[0:0]$2788 - attribute \src "libresoc.v:42290.3-42291.51" - wire $0\wr_pick_dly$1452[0:0]$2271 - attribute \src "libresoc.v:41228.7-41228.32" - wire $0\wr_pick_dly$1452[0:0]$2981 - attribute \src "libresoc.v:46771.3-46779.6" - wire $0\wr_pick_dly$1468$next[0:0]$2792 - attribute \src "libresoc.v:42288.3-42289.51" - wire $0\wr_pick_dly$1468[0:0]$2269 - attribute \src "libresoc.v:41232.7-41232.32" - wire $0\wr_pick_dly$1468[0:0]$2983 - attribute \src "libresoc.v:46780.3-46788.6" - wire $0\wr_pick_dly$1484$next[0:0]$2795 - attribute \src "libresoc.v:42286.3-42287.51" - wire $0\wr_pick_dly$1484[0:0]$2267 - attribute \src "libresoc.v:41236.7-41236.32" - wire $0\wr_pick_dly$1484[0:0]$2985 - attribute \src "libresoc.v:46818.3-46826.6" - wire $0\wr_pick_dly$1500$next[0:0]$2799 - attribute \src "libresoc.v:42284.3-42285.51" - wire $0\wr_pick_dly$1500[0:0]$2265 - attribute \src "libresoc.v:41240.7-41240.32" - wire $0\wr_pick_dly$1500[0:0]$2987 - attribute \src "libresoc.v:46856.3-46864.6" - wire $0\wr_pick_dly$1536$next[0:0]$2803 - attribute \src "libresoc.v:42282.3-42283.51" - wire $0\wr_pick_dly$1536[0:0]$2263 - attribute \src "libresoc.v:41244.7-41244.32" - wire $0\wr_pick_dly$1536[0:0]$2989 - attribute \src "libresoc.v:46865.3-46873.6" - wire $0\wr_pick_dly$1552$next[0:0]$2806 - attribute \src "libresoc.v:42280.3-42281.51" - wire $0\wr_pick_dly$1552[0:0]$2261 - attribute \src "libresoc.v:41248.7-41248.32" - wire $0\wr_pick_dly$1552[0:0]$2991 - attribute \src "libresoc.v:46904.3-46912.6" - wire $0\wr_pick_dly$1568$next[0:0]$2810 - attribute \src "libresoc.v:42278.3-42279.51" - wire $0\wr_pick_dly$1568[0:0]$2259 - attribute \src "libresoc.v:41252.7-41252.32" - wire $0\wr_pick_dly$1568[0:0]$2993 - attribute \src "libresoc.v:46913.3-46921.6" - wire $0\wr_pick_dly$1584$next[0:0]$2813 - attribute \src "libresoc.v:42276.3-42277.51" - wire $0\wr_pick_dly$1584[0:0]$2257 - attribute \src "libresoc.v:41256.7-41256.32" - wire $0\wr_pick_dly$1584[0:0]$2995 - attribute \src "libresoc.v:46922.3-46930.6" - wire $0\wr_pick_dly$1626$next[0:0]$2816 - attribute \src "libresoc.v:42274.3-42275.51" - wire $0\wr_pick_dly$1626[0:0]$2255 - attribute \src "libresoc.v:41260.7-41260.32" - wire $0\wr_pick_dly$1626[0:0]$2997 - attribute \src "libresoc.v:46960.3-46968.6" - wire $0\wr_pick_dly$1645$next[0:0]$2820 - attribute \src "libresoc.v:42272.3-42273.51" - wire $0\wr_pick_dly$1645[0:0]$2253 - attribute \src "libresoc.v:41264.7-41264.32" - wire $0\wr_pick_dly$1645[0:0]$2999 - attribute \src "libresoc.v:46998.3-47006.6" - wire $0\wr_pick_dly$1661$next[0:0]$2824 - attribute \src "libresoc.v:42270.3-42271.51" - wire $0\wr_pick_dly$1661[0:0]$2251 - attribute \src "libresoc.v:41268.7-41268.32" - wire $0\wr_pick_dly$1661[0:0]$3001 - attribute \src "libresoc.v:47007.3-47015.6" - wire $0\wr_pick_dly$1677$next[0:0]$2827 - attribute \src "libresoc.v:42268.3-42269.51" - wire $0\wr_pick_dly$1677[0:0]$2249 - attribute \src "libresoc.v:41272.7-41272.32" - wire $0\wr_pick_dly$1677[0:0]$3003 - attribute \src "libresoc.v:47045.3-47053.6" - wire $0\wr_pick_dly$1693$next[0:0]$2835 - attribute \src "libresoc.v:42266.3-42267.51" - wire $0\wr_pick_dly$1693[0:0]$2247 - attribute \src "libresoc.v:41276.7-41276.32" - wire $0\wr_pick_dly$1693[0:0]$3005 - attribute \src "libresoc.v:47083.3-47091.6" - wire $0\wr_pick_dly$1737$next[0:0]$2843 - attribute \src "libresoc.v:42264.3-42265.51" - wire $0\wr_pick_dly$1737[0:0]$2245 - attribute \src "libresoc.v:41280.7-41280.32" - wire $0\wr_pick_dly$1737[0:0]$3007 - attribute \src "libresoc.v:47121.3-47129.6" - wire $0\wr_pick_dly$1753$next[0:0]$2847 - attribute \src "libresoc.v:42262.3-42263.51" - wire $0\wr_pick_dly$1753[0:0]$2243 - attribute \src "libresoc.v:41284.7-41284.32" - wire $0\wr_pick_dly$1753[0:0]$3009 - attribute \src "libresoc.v:47130.3-47138.6" - wire $0\wr_pick_dly$1777$next[0:0]$2850 - attribute \src "libresoc.v:42260.3-42261.51" - wire $0\wr_pick_dly$1777[0:0]$2241 - attribute \src "libresoc.v:41288.7-41288.32" - wire $0\wr_pick_dly$1777[0:0]$3011 - attribute \src "libresoc.v:47168.3-47176.6" - wire $0\wr_pick_dly$1797$next[0:0]$2854 - attribute \src "libresoc.v:42258.3-42259.51" - wire $0\wr_pick_dly$1797[0:0]$2239 - attribute \src "libresoc.v:41292.7-41292.32" - wire $0\wr_pick_dly$1797[0:0]$3013 - attribute \src "libresoc.v:46185.3-46193.6" - wire $0\wr_pick_dly$981$next[0:0]$2710 - attribute \src "libresoc.v:42328.3-42329.49" - wire $0\wr_pick_dly$981[0:0]$2309 - attribute \src "libresoc.v:41296.7-41296.31" - wire $0\wr_pick_dly$981[0:0]$3015 - attribute \src "libresoc.v:46147.3-46155.6" - wire $0\wr_pick_dly$next[0:0]$2706 - attribute \src "libresoc.v:42330.3-42331.39" + attribute \src "libresoc.v:46858.3-46866.6" + wire $0\wr_pick_dly$1010$next[0:0]$2724 + attribute \src "libresoc.v:42896.3-42897.51" + wire $0\wr_pick_dly$1010[0:0]$2307 + attribute \src "libresoc.v:41726.7-41726.32" + wire $0\wr_pick_dly$1010[0:0]$2945 + attribute \src "libresoc.v:46867.3-46875.6" + wire $0\wr_pick_dly$1031$next[0:0]$2727 + attribute \src "libresoc.v:42894.3-42895.51" + wire $0\wr_pick_dly$1031[0:0]$2305 + attribute \src "libresoc.v:41730.7-41730.32" + wire $0\wr_pick_dly$1031[0:0]$2947 + attribute \src "libresoc.v:46906.3-46914.6" + wire $0\wr_pick_dly$1049$next[0:0]$2731 + attribute \src "libresoc.v:42892.3-42893.51" + wire $0\wr_pick_dly$1049[0:0]$2303 + attribute \src "libresoc.v:41734.7-41734.32" + wire $0\wr_pick_dly$1049[0:0]$2949 + attribute \src "libresoc.v:46915.3-46923.6" + wire $0\wr_pick_dly$1071$next[0:0]$2734 + attribute \src "libresoc.v:42890.3-42891.51" + wire $0\wr_pick_dly$1071[0:0]$2301 + attribute \src "libresoc.v:41738.7-41738.32" + wire $0\wr_pick_dly$1071[0:0]$2951 + attribute \src "libresoc.v:46924.3-46932.6" + wire $0\wr_pick_dly$1091$next[0:0]$2737 + attribute \src "libresoc.v:42888.3-42889.51" + wire $0\wr_pick_dly$1091[0:0]$2299 + attribute \src "libresoc.v:41742.7-41742.32" + wire $0\wr_pick_dly$1091[0:0]$2953 + attribute \src "libresoc.v:46962.3-46970.6" + wire $0\wr_pick_dly$1111$next[0:0]$2741 + attribute \src "libresoc.v:42886.3-42887.51" + wire $0\wr_pick_dly$1111[0:0]$2297 + attribute \src "libresoc.v:41746.7-41746.32" + wire $0\wr_pick_dly$1111[0:0]$2955 + attribute \src "libresoc.v:46971.3-46979.6" + wire $0\wr_pick_dly$1130$next[0:0]$2744 + attribute \src "libresoc.v:42884.3-42885.51" + wire $0\wr_pick_dly$1130[0:0]$2295 + attribute \src "libresoc.v:41750.7-41750.32" + wire $0\wr_pick_dly$1130[0:0]$2957 + attribute \src "libresoc.v:47009.3-47017.6" + wire $0\wr_pick_dly$1148$next[0:0]$2748 + attribute \src "libresoc.v:42882.3-42883.51" + wire $0\wr_pick_dly$1148[0:0]$2293 + attribute \src "libresoc.v:41754.7-41754.32" + wire $0\wr_pick_dly$1148[0:0]$2959 + attribute \src "libresoc.v:47047.3-47055.6" + wire $0\wr_pick_dly$1222$next[0:0]$2752 + attribute \src "libresoc.v:42880.3-42881.51" + wire $0\wr_pick_dly$1222[0:0]$2291 + attribute \src "libresoc.v:41758.7-41758.32" + wire $0\wr_pick_dly$1222[0:0]$2961 + attribute \src "libresoc.v:47085.3-47093.6" + wire $0\wr_pick_dly$1250$next[0:0]$2756 + attribute \src "libresoc.v:42878.3-42879.51" + wire $0\wr_pick_dly$1250[0:0]$2289 + attribute \src "libresoc.v:41762.7-41762.32" + wire $0\wr_pick_dly$1250[0:0]$2963 + attribute \src "libresoc.v:47123.3-47131.6" + wire $0\wr_pick_dly$1270$next[0:0]$2760 + attribute \src "libresoc.v:42876.3-42877.51" + wire $0\wr_pick_dly$1270[0:0]$2287 + attribute \src "libresoc.v:41766.7-41766.32" + wire $0\wr_pick_dly$1270[0:0]$2965 + attribute \src "libresoc.v:47132.3-47140.6" + wire $0\wr_pick_dly$1290$next[0:0]$2763 + attribute \src "libresoc.v:42874.3-42875.51" + wire $0\wr_pick_dly$1290[0:0]$2285 + attribute \src "libresoc.v:41770.7-41770.32" + wire $0\wr_pick_dly$1290[0:0]$2967 + attribute \src "libresoc.v:47170.3-47178.6" + wire $0\wr_pick_dly$1310$next[0:0]$2767 + attribute \src "libresoc.v:42872.3-42873.51" + wire $0\wr_pick_dly$1310[0:0]$2283 + attribute \src "libresoc.v:41774.7-41774.32" + wire $0\wr_pick_dly$1310[0:0]$2969 + attribute \src "libresoc.v:47179.3-47187.6" + wire $0\wr_pick_dly$1330$next[0:0]$2770 + attribute \src "libresoc.v:42870.3-42871.51" + wire $0\wr_pick_dly$1330[0:0]$2281 + attribute \src "libresoc.v:41778.7-41778.32" + wire $0\wr_pick_dly$1330[0:0]$2971 + attribute \src "libresoc.v:47217.3-47225.6" + wire $0\wr_pick_dly$1350$next[0:0]$2774 + attribute \src "libresoc.v:42868.3-42869.51" + wire $0\wr_pick_dly$1350[0:0]$2279 + attribute \src "libresoc.v:41782.7-41782.32" + wire $0\wr_pick_dly$1350[0:0]$2973 + attribute \src "libresoc.v:47255.3-47263.6" + wire $0\wr_pick_dly$1397$next[0:0]$2778 + attribute \src "libresoc.v:42866.3-42867.51" + wire $0\wr_pick_dly$1397[0:0]$2277 + attribute \src "libresoc.v:41786.7-41786.32" + wire $0\wr_pick_dly$1397[0:0]$2975 + attribute \src "libresoc.v:47264.3-47272.6" + wire $0\wr_pick_dly$1413$next[0:0]$2781 + attribute \src "libresoc.v:42864.3-42865.51" + wire $0\wr_pick_dly$1413[0:0]$2275 + attribute \src "libresoc.v:41790.7-41790.32" + wire $0\wr_pick_dly$1413[0:0]$2977 + attribute \src "libresoc.v:47302.3-47310.6" + wire $0\wr_pick_dly$1429$next[0:0]$2785 + attribute \src "libresoc.v:42862.3-42863.51" + wire $0\wr_pick_dly$1429[0:0]$2273 + attribute \src "libresoc.v:41794.7-41794.32" + wire $0\wr_pick_dly$1429[0:0]$2979 + attribute \src "libresoc.v:47340.3-47348.6" + wire $0\wr_pick_dly$1463$next[0:0]$2789 + attribute \src "libresoc.v:42860.3-42861.51" + wire $0\wr_pick_dly$1463[0:0]$2271 + attribute \src "libresoc.v:41798.7-41798.32" + wire $0\wr_pick_dly$1463[0:0]$2981 + attribute \src "libresoc.v:47378.3-47386.6" + wire $0\wr_pick_dly$1479$next[0:0]$2793 + attribute \src "libresoc.v:42858.3-42859.51" + wire $0\wr_pick_dly$1479[0:0]$2269 + attribute \src "libresoc.v:41802.7-41802.32" + wire $0\wr_pick_dly$1479[0:0]$2983 + attribute \src "libresoc.v:47387.3-47395.6" + wire $0\wr_pick_dly$1495$next[0:0]$2796 + attribute \src "libresoc.v:42856.3-42857.51" + wire $0\wr_pick_dly$1495[0:0]$2267 + attribute \src "libresoc.v:41806.7-41806.32" + wire $0\wr_pick_dly$1495[0:0]$2985 + attribute \src "libresoc.v:47425.3-47433.6" + wire $0\wr_pick_dly$1511$next[0:0]$2800 + attribute \src "libresoc.v:42854.3-42855.51" + wire $0\wr_pick_dly$1511[0:0]$2265 + attribute \src "libresoc.v:41810.7-41810.32" + wire $0\wr_pick_dly$1511[0:0]$2987 + attribute \src "libresoc.v:47463.3-47471.6" + wire $0\wr_pick_dly$1547$next[0:0]$2804 + attribute \src "libresoc.v:42852.3-42853.51" + wire $0\wr_pick_dly$1547[0:0]$2263 + attribute \src "libresoc.v:41814.7-41814.32" + wire $0\wr_pick_dly$1547[0:0]$2989 + attribute \src "libresoc.v:47472.3-47480.6" + wire $0\wr_pick_dly$1563$next[0:0]$2807 + attribute \src "libresoc.v:42850.3-42851.51" + wire $0\wr_pick_dly$1563[0:0]$2261 + attribute \src "libresoc.v:41818.7-41818.32" + wire $0\wr_pick_dly$1563[0:0]$2991 + attribute \src "libresoc.v:47510.3-47518.6" + wire $0\wr_pick_dly$1579$next[0:0]$2811 + attribute \src "libresoc.v:42848.3-42849.51" + wire $0\wr_pick_dly$1579[0:0]$2259 + attribute \src "libresoc.v:41822.7-41822.32" + wire $0\wr_pick_dly$1579[0:0]$2993 + attribute \src "libresoc.v:47519.3-47527.6" + wire $0\wr_pick_dly$1595$next[0:0]$2814 + attribute \src "libresoc.v:42846.3-42847.51" + wire $0\wr_pick_dly$1595[0:0]$2257 + attribute \src "libresoc.v:41826.7-41826.32" + wire $0\wr_pick_dly$1595[0:0]$2995 + attribute \src "libresoc.v:47557.3-47565.6" + wire $0\wr_pick_dly$1637$next[0:0]$2818 + attribute \src "libresoc.v:42844.3-42845.51" + wire $0\wr_pick_dly$1637[0:0]$2255 + attribute \src "libresoc.v:41830.7-41830.32" + wire $0\wr_pick_dly$1637[0:0]$2997 + attribute \src "libresoc.v:47595.3-47603.6" + wire $0\wr_pick_dly$1656$next[0:0]$2826 + attribute \src "libresoc.v:42842.3-42843.51" + wire $0\wr_pick_dly$1656[0:0]$2253 + attribute \src "libresoc.v:41834.7-41834.32" + wire $0\wr_pick_dly$1656[0:0]$2999 + attribute \src "libresoc.v:47633.3-47641.6" + wire $0\wr_pick_dly$1672$next[0:0]$2834 + attribute \src "libresoc.v:42840.3-42841.51" + wire $0\wr_pick_dly$1672[0:0]$2251 + attribute \src "libresoc.v:41838.7-41838.32" + wire $0\wr_pick_dly$1672[0:0]$3001 + attribute \src "libresoc.v:47642.3-47650.6" + wire $0\wr_pick_dly$1688$next[0:0]$2837 + attribute \src "libresoc.v:42838.3-42839.51" + wire $0\wr_pick_dly$1688[0:0]$2249 + attribute \src "libresoc.v:41842.7-41842.32" + wire $0\wr_pick_dly$1688[0:0]$3003 + attribute \src "libresoc.v:47680.3-47688.6" + wire $0\wr_pick_dly$1704$next[0:0]$2841 + attribute \src "libresoc.v:42836.3-42837.51" + wire $0\wr_pick_dly$1704[0:0]$2247 + attribute \src "libresoc.v:41846.7-41846.32" + wire $0\wr_pick_dly$1704[0:0]$3005 + attribute \src "libresoc.v:47718.3-47726.6" + wire $0\wr_pick_dly$1748$next[0:0]$2845 + attribute \src "libresoc.v:42834.3-42835.51" + wire $0\wr_pick_dly$1748[0:0]$2245 + attribute \src "libresoc.v:41850.7-41850.32" + wire $0\wr_pick_dly$1748[0:0]$3007 + attribute \src "libresoc.v:47727.3-47735.6" + wire $0\wr_pick_dly$1764$next[0:0]$2848 + attribute \src "libresoc.v:42832.3-42833.51" + wire $0\wr_pick_dly$1764[0:0]$2243 + attribute \src "libresoc.v:41854.7-41854.32" + wire $0\wr_pick_dly$1764[0:0]$3009 + attribute \src "libresoc.v:47765.3-47773.6" + wire $0\wr_pick_dly$1788$next[0:0]$2852 + attribute \src "libresoc.v:42830.3-42831.51" + wire $0\wr_pick_dly$1788[0:0]$2241 + attribute \src "libresoc.v:41858.7-41858.32" + wire $0\wr_pick_dly$1788[0:0]$3011 + attribute \src "libresoc.v:47803.3-47811.6" + wire $0\wr_pick_dly$1808$next[0:0]$2856 + attribute \src "libresoc.v:42828.3-42829.51" + wire $0\wr_pick_dly$1808[0:0]$2239 + attribute \src "libresoc.v:41862.7-41862.32" + wire $0\wr_pick_dly$1808[0:0]$3013 + attribute \src "libresoc.v:46819.3-46827.6" + wire $0\wr_pick_dly$991$next[0:0]$2720 + attribute \src "libresoc.v:42898.3-42899.49" + wire $0\wr_pick_dly$991[0:0]$2309 + attribute \src "libresoc.v:41866.7-41866.31" + wire $0\wr_pick_dly$991[0:0]$3015 + attribute \src "libresoc.v:46810.3-46818.6" + wire $0\wr_pick_dly$next[0:0]$2717 + attribute \src "libresoc.v:42900.3-42901.39" wire $0\wr_pick_dly[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $10\corebusy_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $11\corebusy_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $12\corebusy_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $13\corebusy_o[0:0] - attribute \src "libresoc.v:45520.3-45540.6" - wire $1\core_terminate_o$next[0:0]$2589 - attribute \src "libresoc.v:37778.7-37778.30" + attribute \src "libresoc.v:46587.3-46607.6" + wire $1\core_terminate_o$next[0:0]$2674 + attribute \src "libresoc.v:38263.7-38263.30" wire $1\core_terminate_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $1\corebusy_o[0:0] - attribute \src "libresoc.v:45345.3-45371.6" - wire width 2 $1\counter$next[1:0]$2566 - attribute \src "libresoc.v:37791.13-37791.27" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $1\counter$next[1:0]$2655 + attribute \src "libresoc.v:38276.13-38276.27" wire width 2 $1\counter[1:0] - attribute \src "libresoc.v:45830.3-45838.6" - wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:38921.7-38921.34" + attribute \src "libresoc.v:46412.3-46420.6" + wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 + attribute \src "libresoc.v:39443.7-39443.34" wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:45811.3-45819.6" - wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:38925.7-38925.30" + attribute \src "libresoc.v:46393.3-46401.6" + wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 + attribute \src "libresoc.v:39447.7-39447.30" wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:45849.3-45857.6" - wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 - attribute \src "libresoc.v:38929.7-38929.30" + attribute \src "libresoc.v:46458.3-46466.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:39451.7-39451.30" wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:45898.3-45906.6" - wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:38933.7-38933.30" + attribute \src "libresoc.v:46568.3-46576.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 + attribute \src "libresoc.v:39455.7-39455.30" wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:45762.3-45770.6" - wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 - attribute \src "libresoc.v:38937.7-38937.33" + attribute \src "libresoc.v:46374.3-46382.6" + wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 + attribute \src "libresoc.v:39459.7-39459.33" wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:45917.3-45925.6" - wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 - attribute \src "libresoc.v:38941.7-38941.37" + attribute \src "libresoc.v:46608.3-46616.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 + attribute \src "libresoc.v:39463.7-39463.37" wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:45984.3-45992.6" - wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 - attribute \src "libresoc.v:38945.7-38945.34" + attribute \src "libresoc.v:46675.3-46683.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 + attribute \src "libresoc.v:39467.7-39467.34" wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:45936.3-45944.6" - wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 - attribute \src "libresoc.v:38949.7-38949.35" + attribute \src "libresoc.v:46627.3-46635.6" + wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 + attribute \src "libresoc.v:39471.7-39471.35" wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46032.3-46040.6" - wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 - attribute \src "libresoc.v:38953.7-38953.37" + attribute \src "libresoc.v:46723.3-46731.6" + wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 + attribute \src "libresoc.v:39475.7-39475.37" wire $1\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46051.3-46059.6" - wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 - attribute \src "libresoc.v:38957.7-38957.35" + attribute \src "libresoc.v:46742.3-46750.6" + wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 + attribute \src "libresoc.v:39479.7-39479.35" wire $1\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:44984.3-44992.6" - wire $1\dp_INT_ra_alu0_0$next[0:0]$2458 - attribute \src "libresoc.v:38961.7-38961.30" + attribute \src "libresoc.v:45823.3-45831.6" + wire $1\dp_INT_ra_alu0_0$next[0:0]$2475 + attribute \src "libresoc.v:39483.7-39483.30" wire $1\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45003.3-45011.6" - wire $1\dp_INT_ra_cr0_1$next[0:0]$2462 - attribute \src "libresoc.v:38965.7-38965.29" + attribute \src "libresoc.v:45842.3-45850.6" + wire $1\dp_INT_ra_cr0_1$next[0:0]$2479 + attribute \src "libresoc.v:39487.7-39487.29" wire $1\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45079.3-45087.6" - wire $1\dp_INT_ra_div0_5$next[0:0]$2486 - attribute \src "libresoc.v:38969.7-38969.30" + attribute \src "libresoc.v:45918.3-45926.6" + wire $1\dp_INT_ra_div0_5$next[0:0]$2503 + attribute \src "libresoc.v:39491.7-39491.30" wire $1\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45136.3-45144.6" - wire $1\dp_INT_ra_ldst0_8$next[0:0]$2504 - attribute \src "libresoc.v:38973.7-38973.31" + attribute \src "libresoc.v:45975.3-45983.6" + wire $1\dp_INT_ra_ldst0_8$next[0:0]$2521 + attribute \src "libresoc.v:39495.7-39495.31" wire $1\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45041.3-45049.6" - wire $1\dp_INT_ra_logical0_3$next[0:0]$2474 - attribute \src "libresoc.v:38977.7-38977.34" + attribute \src "libresoc.v:45880.3-45888.6" + wire $1\dp_INT_ra_logical0_3$next[0:0]$2491 + attribute \src "libresoc.v:39499.7-39499.34" wire $1\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45098.3-45106.6" - wire $1\dp_INT_ra_mul0_6$next[0:0]$2492 - attribute \src "libresoc.v:38981.7-38981.30" + attribute \src "libresoc.v:45937.3-45945.6" + wire $1\dp_INT_ra_mul0_6$next[0:0]$2509 + attribute \src "libresoc.v:39503.7-39503.30" wire $1\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45117.3-45125.6" - wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 - attribute \src "libresoc.v:38985.7-38985.35" + attribute \src "libresoc.v:45956.3-45964.6" + wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 + attribute \src "libresoc.v:39507.7-39507.35" wire $1\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45060.3-45068.6" - wire $1\dp_INT_ra_spr0_4$next[0:0]$2480 - attribute \src "libresoc.v:38989.7-38989.30" + attribute \src "libresoc.v:45899.3-45907.6" + wire $1\dp_INT_ra_spr0_4$next[0:0]$2497 + attribute \src "libresoc.v:39511.7-39511.30" wire $1\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45022.3-45030.6" - wire $1\dp_INT_ra_trap0_2$next[0:0]$2468 - attribute \src "libresoc.v:38993.7-38993.31" + attribute \src "libresoc.v:45861.3-45869.6" + wire $1\dp_INT_ra_trap0_2$next[0:0]$2485 + attribute \src "libresoc.v:39515.7-39515.31" wire $1\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45155.3-45163.6" - wire $1\dp_INT_rb_alu0_0$next[0:0]$2510 - attribute \src "libresoc.v:38997.7-38997.30" + attribute \src "libresoc.v:45994.3-46002.6" + wire $1\dp_INT_rb_alu0_0$next[0:0]$2527 + attribute \src "libresoc.v:39519.7-39519.30" wire $1\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:45174.3-45182.6" - wire $1\dp_INT_rb_cr0_1$next[0:0]$2514 - attribute \src "libresoc.v:39001.7-39001.29" + attribute \src "libresoc.v:46013.3-46021.6" + wire $1\dp_INT_rb_cr0_1$next[0:0]$2531 + attribute \src "libresoc.v:39523.7-39523.29" wire $1\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:45231.3-45239.6" - wire $1\dp_INT_rb_div0_4$next[0:0]$2532 - attribute \src "libresoc.v:39005.7-39005.30" + attribute \src "libresoc.v:46070.3-46078.6" + wire $1\dp_INT_rb_div0_4$next[0:0]$2549 + attribute \src "libresoc.v:39527.7-39527.30" wire $1\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:45288.3-45296.6" - wire $1\dp_INT_rb_ldst0_7$next[0:0]$2550 - attribute \src "libresoc.v:39009.7-39009.31" + attribute \src "libresoc.v:46127.3-46135.6" + wire $1\dp_INT_rb_ldst0_7$next[0:0]$2567 + attribute \src "libresoc.v:39531.7-39531.31" wire $1\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:45212.3-45220.6" - wire $1\dp_INT_rb_logical0_3$next[0:0]$2526 - attribute \src "libresoc.v:39013.7-39013.34" + attribute \src "libresoc.v:46051.3-46059.6" + wire $1\dp_INT_rb_logical0_3$next[0:0]$2543 + attribute \src "libresoc.v:39535.7-39535.34" wire $1\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:45250.3-45258.6" - wire $1\dp_INT_rb_mul0_5$next[0:0]$2538 - attribute \src "libresoc.v:39017.7-39017.30" + attribute \src "libresoc.v:46089.3-46097.6" + wire $1\dp_INT_rb_mul0_5$next[0:0]$2555 + attribute \src "libresoc.v:39539.7-39539.30" wire $1\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:45269.3-45277.6" - wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 - attribute \src "libresoc.v:39021.7-39021.35" + attribute \src "libresoc.v:46108.3-46116.6" + wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 + attribute \src "libresoc.v:39543.7-39543.35" wire $1\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:45193.3-45201.6" - wire $1\dp_INT_rb_trap0_2$next[0:0]$2520 - attribute \src "libresoc.v:39025.7-39025.31" + attribute \src "libresoc.v:46032.3-46040.6" + wire $1\dp_INT_rb_trap0_2$next[0:0]$2537 + attribute \src "libresoc.v:39547.7-39547.31" wire $1\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:45326.3-45334.6" - wire $1\dp_INT_rc_ldst0_1$next[0:0]$2560 - attribute \src "libresoc.v:39029.7-39029.31" + attribute \src "libresoc.v:46165.3-46173.6" + wire $1\dp_INT_rc_ldst0_1$next[0:0]$2577 + attribute \src "libresoc.v:39551.7-39551.31" wire $1\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:45307.3-45315.6" - wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 - attribute \src "libresoc.v:39033.7-39033.35" + attribute \src "libresoc.v:46146.3-46154.6" + wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 + attribute \src "libresoc.v:39555.7-39555.35" wire $1\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46099.3-46107.6" - wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 - attribute \src "libresoc.v:39037.7-39037.32" + attribute \src "libresoc.v:46791.3-46799.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 + attribute \src "libresoc.v:39559.7-39559.32" wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45627.3-45635.6" - wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 - attribute \src "libresoc.v:39041.7-39041.34" + attribute \src "libresoc.v:46298.3-46306.6" + wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 + attribute \src "libresoc.v:39563.7-39563.34" wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45694.3-45702.6" - wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 - attribute \src "libresoc.v:39045.7-39045.39" + attribute \src "libresoc.v:46336.3-46344.6" + wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 + attribute \src "libresoc.v:39567.7-39567.39" wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45675.3-45683.6" - wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 - attribute \src "libresoc.v:39049.7-39049.34" + attribute \src "libresoc.v:46317.3-46325.6" + wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 + attribute \src "libresoc.v:39571.7-39571.34" wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:45743.3-45751.6" - wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 - attribute \src "libresoc.v:39053.7-39053.34" + attribute \src "libresoc.v:46355.3-46363.6" + wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 + attribute \src "libresoc.v:39575.7-39575.34" wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:45372.3-45380.6" - wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 - attribute \src "libresoc.v:39057.7-39057.34" + attribute \src "libresoc.v:46184.3-46192.6" + wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 + attribute \src "libresoc.v:39579.7-39579.34" wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45541.3-45549.6" - wire $1\dp_XER_xer_so_div0_3$next[0:0]$2594 - attribute \src "libresoc.v:39061.7-39061.34" + attribute \src "libresoc.v:46241.3-46249.6" + wire $1\dp_XER_xer_so_div0_3$next[0:0]$2599 + attribute \src "libresoc.v:39583.7-39583.34" wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:45482.3-45490.6" - wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 - attribute \src "libresoc.v:39065.7-39065.38" + attribute \src "libresoc.v:46203.3-46211.6" + wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 + attribute \src "libresoc.v:39587.7-39587.38" wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45560.3-45568.6" - wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 - attribute \src "libresoc.v:39069.7-39069.34" + attribute \src "libresoc.v:46260.3-46268.6" + wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 + attribute \src "libresoc.v:39591.7-39591.34" wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45608.3-45616.6" - wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 - attribute \src "libresoc.v:39073.7-39073.39" + attribute \src "libresoc.v:46279.3-46287.6" + wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + attribute \src "libresoc.v:39595.7-39595.39" wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:45501.3-45509.6" - wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 - attribute \src "libresoc.v:39077.7-39077.34" + attribute \src "libresoc.v:46222.3-46230.6" + wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 + attribute \src "libresoc.v:39599.7-39599.34" wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46619.3-46647.6" - wire $1\fus_cu_issue_i$11[0:0]$2769 - attribute \src "libresoc.v:47016.3-47044.6" - wire $1\fus_cu_issue_i$14[0:0]$2831 - attribute \src "libresoc.v:47380.3-47408.6" - wire $1\fus_cu_issue_i$17[0:0]$2865 - attribute \src "libresoc.v:47876.3-47904.6" - wire $1\fus_cu_issue_i$20[0:0]$2890 - attribute \src "libresoc.v:43203.3-43231.6" - wire $1\fus_cu_issue_i$23[0:0]$2357 - attribute \src "libresoc.v:43699.3-43727.6" - wire $1\fus_cu_issue_i$26[0:0]$2382 - attribute \src "libresoc.v:44021.3-44049.6" - wire $1\fus_cu_issue_i$29[0:0]$2401 - attribute \src "libresoc.v:44488.3-44516.6" - wire $1\fus_cu_issue_i$32[0:0]$2425 - attribute \src "libresoc.v:44926.3-44954.6" - wire $1\fus_cu_issue_i$35[0:0]$2448 - attribute \src "libresoc.v:46411.3-46439.6" + attribute \src "libresoc.v:47566.3-47594.6" + wire $1\fus_cu_issue_i$13[0:0]$2822 + attribute \src "libresoc.v:47900.3-47928.6" + wire $1\fus_cu_issue_i$16[0:0]$2863 + attribute \src "libresoc.v:48219.3-48247.6" + wire $1\fus_cu_issue_i$19[0:0]$2882 + attribute \src "libresoc.v:43868.3-43896.6" + wire $1\fus_cu_issue_i$22[0:0]$2360 + attribute \src "libresoc.v:44042.3-44070.6" + wire $1\fus_cu_issue_i$25[0:0]$2374 + attribute \src "libresoc.v:44538.3-44566.6" + wire $1\fus_cu_issue_i$28[0:0]$2399 + attribute \src "libresoc.v:44860.3-44888.6" + wire $1\fus_cu_issue_i$31[0:0]$2418 + attribute \src "libresoc.v:45327.3-45355.6" + wire $1\fus_cu_issue_i$34[0:0]$2442 + attribute \src "libresoc.v:45765.3-45793.6" + wire $1\fus_cu_issue_i$37[0:0]$2465 + attribute \src "libresoc.v:47349.3-47377.6" wire $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46657.3-46685.6" - wire width 6 $1\fus_cu_rdmaskn_i$13[5:0]$2777 - attribute \src "libresoc.v:47054.3-47082.6" - wire width 3 $1\fus_cu_rdmaskn_i$16[2:0]$2839 - attribute \src "libresoc.v:47409.3-47437.6" - wire width 4 $1\fus_cu_rdmaskn_i$19[3:0]$2870 - attribute \src "libresoc.v:47905.3-47933.6" - wire width 3 $1\fus_cu_rdmaskn_i$22[2:0]$2895 - attribute \src "libresoc.v:43232.3-43260.6" - wire width 6 $1\fus_cu_rdmaskn_i$25[5:0]$2362 - attribute \src "libresoc.v:43728.3-43756.6" - wire width 3 $1\fus_cu_rdmaskn_i$28[2:0]$2387 - attribute \src "libresoc.v:44050.3-44078.6" - wire width 3 $1\fus_cu_rdmaskn_i$31[2:0]$2406 - attribute \src "libresoc.v:44517.3-44545.6" - wire width 5 $1\fus_cu_rdmaskn_i$34[4:0]$2430 - attribute \src "libresoc.v:44955.3-44983.6" - wire width 3 $1\fus_cu_rdmaskn_i$37[2:0]$2453 - attribute \src "libresoc.v:46449.3-46477.6" + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2830 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2868 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2887 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2365 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2379 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2404 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2423 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2447 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2470 + attribute \src "libresoc.v:47396.3-47424.6" wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46326.3-46354.6" + attribute \src "libresoc.v:47273.3-47301.6" wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45636.3-45664.6" - wire width 12 $1\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45703.3-45732.6" + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $1\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45703.3-45732.6" + attribute \src "libresoc.v:46761.3-46790.6" wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46156.3-46184.6" + attribute \src "libresoc.v:47094.3-47122.6" wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46373.3-46401.6" + attribute \src "libresoc.v:47311.3-47339.6" wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45579.3-45607.6" + attribute \src "libresoc.v:46646.3-46674.6" wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45955.3-45983.6" + attribute \src "libresoc.v:46933.3-46961.6" wire $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46070.3-46098.6" + attribute \src "libresoc.v:47018.3-47046.6" wire $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46241.3-46269.6" + attribute \src "libresoc.v:47188.3-47216.6" wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46288.3-46316.6" + attribute \src "libresoc.v:47226.3-47254.6" wire $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45868.3-45897.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:45868.3-45897.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46203.3-46231.6" + attribute \src "libresoc.v:47141.3-47169.6" wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45781.3-45810.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45781.3-45810.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46118.3-46146.6" + attribute \src "libresoc.v:47056.3-47084.6" wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46003.3-46031.6" + attribute \src "libresoc.v:46980.3-47008.6" wire $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46704.3-46732.6" + attribute \src "libresoc.v:47651.3-47679.6" wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46789.3-46817.6" - wire width 12 $1\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46874.3-46903.6" + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $1\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:46874.3-46903.6" + attribute \src "libresoc.v:47812.3-47841.6" wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46827.3-46855.6" + attribute \src "libresoc.v:47774.3-47802.6" wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46742.3-46770.6" + attribute \src "libresoc.v:47689.3-47717.6" wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46969.3-46997.6" + attribute \src "libresoc.v:47871.3-47899.6" wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46931.3-46959.6" + attribute \src "libresoc.v:47842.3-47870.6" wire $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46534.3-46562.6" - wire width 12 $1\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46581.3-46609.6" + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $1\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46487.3-46515.6" + attribute \src "libresoc.v:47434.3-47462.6" wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43641.3-43669.6" + attribute \src "libresoc.v:44480.3-44508.6" wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43290.3-43318.6" - wire width 12 $1\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43319.3-43348.6" + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $1\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43319.3-43348.6" + attribute \src "libresoc.v:44158.3-44187.6" wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43467.3-43495.6" + attribute \src "libresoc.v:44306.3-44334.6" wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43670.3-43698.6" + attribute \src "libresoc.v:44509.3-44537.6" wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43261.3-43289.6" + attribute \src "libresoc.v:44100.3-44128.6" wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43409.3-43437.6" + attribute \src "libresoc.v:44248.3-44276.6" wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43496.3-43524.6" + attribute \src "libresoc.v:44335.3-44363.6" wire $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43583.3-43611.6" + attribute \src "libresoc.v:44422.3-44450.6" wire $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43612.3-43640.6" + attribute \src "libresoc.v:44451.3-44479.6" wire $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43379.3-43408.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $1\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43379.3-43408.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43554.3-43582.6" + attribute \src "libresoc.v:44393.3-44421.6" wire $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43349.3-43378.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $1\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43349.3-43378.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43525.3-43553.6" + attribute \src "libresoc.v:44364.3-44392.6" wire $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43438.3-43466.6" + attribute \src "libresoc.v:44277.3-44305.6" wire $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:47818.3-47846.6" + attribute \src "libresoc.v:43810.3-43838.6" wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47467.3-47495.6" - wire width 12 $1\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47496.3-47525.6" + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $1\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47496.3-47525.6" + attribute \src "libresoc.v:48335.3-48364.6" wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47644.3-47672.6" + attribute \src "libresoc.v:48483.3-48511.6" wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47847.3-47875.6" + attribute \src "libresoc.v:43839.3-43867.6" wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47438.3-47466.6" + attribute \src "libresoc.v:48277.3-48305.6" wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47586.3-47614.6" + attribute \src "libresoc.v:48425.3-48453.6" wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47673.3-47701.6" + attribute \src "libresoc.v:48512.3-48540.6" wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47760.3-47788.6" + attribute \src "libresoc.v:43752.3-43780.6" wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47789.3-47817.6" + attribute \src "libresoc.v:43781.3-43809.6" wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47556.3-47585.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47556.3-47585.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47731.3-47759.6" + attribute \src "libresoc.v:43723.3-43751.6" wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47526.3-47555.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47526.3-47555.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47702.3-47730.6" + attribute \src "libresoc.v:48541.3-48569.6" wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47615.3-47643.6" + attribute \src "libresoc.v:48454.3-48482.6" wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43786.3-43814.6" - wire width 12 $1\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43815.3-43844.6" + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $1\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:43815.3-43844.6" + attribute \src "libresoc.v:44654.3-44683.6" wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43992.3-44020.6" + attribute \src "libresoc.v:44831.3-44859.6" wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43757.3-43785.6" + attribute \src "libresoc.v:44596.3-44624.6" wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43934.3-43962.6" + attribute \src "libresoc.v:44773.3-44801.6" wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43963.3-43991.6" + attribute \src "libresoc.v:44802.3-44830.6" wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43875.3-43904.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:43875.3-43904.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43845.3-43874.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:43845.3-43874.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43905.3-43933.6" + attribute \src "libresoc.v:44744.3-44772.6" wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44108.3-44136.6" - wire width 12 $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44137.3-44166.6" + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44137.3-44166.6" + attribute \src "libresoc.v:44976.3-45005.6" wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44285.3-44313.6" + attribute \src "libresoc.v:45124.3-45152.6" wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44343.3-44371.6" + attribute \src "libresoc.v:45182.3-45210.6" wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44459.3-44487.6" + attribute \src "libresoc.v:45298.3-45326.6" wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44079.3-44107.6" + attribute \src "libresoc.v:44918.3-44946.6" wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44256.3-44284.6" + attribute \src "libresoc.v:45095.3-45123.6" wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44401.3-44429.6" + attribute \src "libresoc.v:45240.3-45268.6" wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44430.3-44458.6" + attribute \src "libresoc.v:45269.3-45297.6" wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44197.3-44226.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44197.3-44226.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44314.3-44342.6" + attribute \src "libresoc.v:45153.3-45181.6" wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44372.3-44400.6" + attribute \src "libresoc.v:45211.3-45239.6" wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44167.3-44196.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44167.3-44196.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44227.3-44255.6" + attribute \src "libresoc.v:45066.3-45094.6" wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:47963.3-47991.6" - wire width 12 $1\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:43145.3-43173.6" + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $1\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47934.3-47962.6" + attribute \src "libresoc.v:43926.3-43954.6" wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43174.3-43202.6" + attribute \src "libresoc.v:44013.3-44041.6" wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47235.3-47263.6" + attribute \src "libresoc.v:48074.3-48102.6" wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47139.3-47167.6" - wire width 12 $1\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:47177.3-47205.6" + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $1\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47092.3-47120.6" + attribute \src "libresoc.v:47958.3-47986.6" wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47264.3-47292.6" + attribute \src "libresoc.v:48103.3-48131.6" wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47351.3-47379.6" + attribute \src "libresoc.v:48190.3-48218.6" wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47206.3-47234.6" + attribute \src "libresoc.v:48045.3-48073.6" wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47322.3-47350.6" + attribute \src "libresoc.v:48161.3-48189.6" wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47293.3-47321.6" + attribute \src "libresoc.v:48132.3-48160.6" wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:44810.3-44838.6" + attribute \src "libresoc.v:45649.3-45677.6" wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44781.3-44809.6" + attribute \src "libresoc.v:45620.3-45648.6" wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44575.3-44603.6" - wire width 12 $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44604.3-44633.6" + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44604.3-44633.6" + attribute \src "libresoc.v:45443.3-45472.6" wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44897.3-44925.6" + attribute \src "libresoc.v:45736.3-45764.6" wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44546.3-44574.6" + attribute \src "libresoc.v:45385.3-45413.6" wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44723.3-44751.6" + attribute \src "libresoc.v:45562.3-45590.6" wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44752.3-44780.6" + attribute \src "libresoc.v:45591.3-45619.6" wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44868.3-44896.6" + attribute \src "libresoc.v:45707.3-45735.6" wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44693.3-44722.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44693.3-44722.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44663.3-44692.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44663.3-44692.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44839.3-44867.6" + attribute \src "libresoc.v:45678.3-45706.6" wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44634.3-44662.6" + attribute \src "libresoc.v:45473.3-45501.6" wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45012.3-45021.6" - wire width 64 $1\fus_src1_i$40[63:0]$2465 - attribute \src "libresoc.v:45031.3-45040.6" - wire width 64 $1\fus_src1_i$43[63:0]$2471 - attribute \src "libresoc.v:45050.3-45059.6" - wire width 64 $1\fus_src1_i$46[63:0]$2477 - attribute \src "libresoc.v:45069.3-45078.6" - wire width 64 $1\fus_src1_i$49[63:0]$2483 - attribute \src "libresoc.v:45088.3-45097.6" - wire width 64 $1\fus_src1_i$52[63:0]$2489 - attribute \src "libresoc.v:45107.3-45116.6" - wire width 64 $1\fus_src1_i$55[63:0]$2495 - attribute \src "libresoc.v:45126.3-45135.6" - wire width 64 $1\fus_src1_i$58[63:0]$2501 - attribute \src "libresoc.v:45145.3-45154.6" - wire width 64 $1\fus_src1_i$61[63:0]$2507 - attribute \src "libresoc.v:45926.3-45935.6" - wire width 64 $1\fus_src1_i$84[63:0]$2670 - attribute \src "libresoc.v:44993.3-45002.6" + attribute \src "libresoc.v:45851.3-45860.6" + wire width 64 $1\fus_src1_i$42[63:0]$2482 + attribute \src "libresoc.v:45870.3-45879.6" + wire width 64 $1\fus_src1_i$45[63:0]$2488 + attribute \src "libresoc.v:45889.3-45898.6" + wire width 64 $1\fus_src1_i$48[63:0]$2494 + attribute \src "libresoc.v:45908.3-45917.6" + wire width 64 $1\fus_src1_i$51[63:0]$2500 + attribute \src "libresoc.v:45927.3-45936.6" + wire width 64 $1\fus_src1_i$54[63:0]$2506 + attribute \src "libresoc.v:45946.3-45955.6" + wire width 64 $1\fus_src1_i$57[63:0]$2512 + attribute \src "libresoc.v:45965.3-45974.6" + wire width 64 $1\fus_src1_i$60[63:0]$2518 + attribute \src "libresoc.v:45984.3-45993.6" + wire width 64 $1\fus_src1_i$63[63:0]$2524 + attribute \src "libresoc.v:46617.3-46626.6" + wire width 64 $1\fus_src1_i$86[63:0]$2682 + attribute \src "libresoc.v:45832.3-45841.6" wire width 64 $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45183.3-45192.6" - wire width 64 $1\fus_src2_i$62[63:0]$2517 - attribute \src "libresoc.v:45202.3-45211.6" - wire width 64 $1\fus_src2_i$63[63:0]$2523 - attribute \src "libresoc.v:45221.3-45230.6" - wire width 64 $1\fus_src2_i$64[63:0]$2529 - attribute \src "libresoc.v:45240.3-45249.6" - wire width 64 $1\fus_src2_i$65[63:0]$2535 - attribute \src "libresoc.v:45259.3-45268.6" - wire width 64 $1\fus_src2_i$66[63:0]$2541 - attribute \src "libresoc.v:45278.3-45287.6" - wire width 64 $1\fus_src2_i$67[63:0]$2547 - attribute \src "libresoc.v:45297.3-45306.6" - wire width 64 $1\fus_src2_i$68[63:0]$2553 + attribute \src "libresoc.v:46022.3-46031.6" + wire width 64 $1\fus_src2_i$64[63:0]$2534 attribute \src "libresoc.v:46041.3-46050.6" - wire width 64 $1\fus_src2_i$87[63:0]$2690 - attribute \src "libresoc.v:46108.3-46117.6" - wire width 64 $1\fus_src2_i$89[63:0]$2703 - attribute \src "libresoc.v:45164.3-45173.6" + wire width 64 $1\fus_src2_i$65[63:0]$2540 + attribute \src "libresoc.v:46060.3-46069.6" + wire width 64 $1\fus_src2_i$66[63:0]$2546 + attribute \src "libresoc.v:46079.3-46088.6" + wire width 64 $1\fus_src2_i$67[63:0]$2552 + attribute \src "libresoc.v:46098.3-46107.6" + wire width 64 $1\fus_src2_i$68[63:0]$2558 + attribute \src "libresoc.v:46117.3-46126.6" + wire width 64 $1\fus_src2_i$69[63:0]$2564 + attribute \src "libresoc.v:46136.3-46145.6" + wire width 64 $1\fus_src2_i$70[63:0]$2570 + attribute \src "libresoc.v:46732.3-46741.6" + wire width 64 $1\fus_src2_i$89[63:0]$2702 + attribute \src "libresoc.v:46800.3-46809.6" + wire width 64 $1\fus_src2_i$91[63:0]$2715 + attribute \src "libresoc.v:46003.3-46012.6" wire width 64 $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45335.3-45344.6" - wire width 64 $1\fus_src3_i$69[63:0]$2563 - attribute \src "libresoc.v:45381.3-45390.6" - wire $1\fus_src3_i$70[0:0]$2575 - attribute \src "libresoc.v:45491.3-45500.6" - wire $1\fus_src3_i$71[0:0]$2582 - attribute \src "libresoc.v:45550.3-45559.6" - wire $1\fus_src3_i$72[0:0]$2597 - attribute \src "libresoc.v:45569.3-45578.6" - wire $1\fus_src3_i$73[0:0]$2603 - attribute \src "libresoc.v:45771.3-45780.6" - wire width 32 $1\fus_src3_i$77[31:0]$2638 - attribute \src "libresoc.v:45839.3-45848.6" - wire width 4 $1\fus_src3_i$81[3:0]$2651 - attribute \src "libresoc.v:45945.3-45954.6" - wire width 64 $1\fus_src3_i$85[63:0]$2676 - attribute \src "libresoc.v:45993.3-46002.6" - wire width 64 $1\fus_src3_i$86[63:0]$2683 - attribute \src "libresoc.v:45316.3-45325.6" + attribute \src "libresoc.v:46174.3-46183.6" + wire width 64 $1\fus_src3_i$71[63:0]$2580 + attribute \src "libresoc.v:46193.3-46202.6" + wire $1\fus_src3_i$72[0:0]$2586 + attribute \src "libresoc.v:46212.3-46221.6" + wire $1\fus_src3_i$73[0:0]$2592 + attribute \src "libresoc.v:46250.3-46259.6" + wire $1\fus_src3_i$74[0:0]$2602 + attribute \src "libresoc.v:46269.3-46278.6" + wire $1\fus_src3_i$75[0:0]$2608 + attribute \src "libresoc.v:46383.3-46392.6" + wire width 32 $1\fus_src3_i$79[31:0]$2640 + attribute \src "libresoc.v:46421.3-46430.6" + wire width 4 $1\fus_src3_i$83[3:0]$2652 + attribute \src "libresoc.v:46636.3-46645.6" + wire width 64 $1\fus_src3_i$87[63:0]$2688 + attribute \src "libresoc.v:46684.3-46693.6" + wire width 64 $1\fus_src3_i$88[63:0]$2695 + attribute \src "libresoc.v:46155.3-46164.6" wire width 64 $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45617.3-45626.6" - wire $1\fus_src4_i$74[0:0]$2610 - attribute \src "libresoc.v:45665.3-45674.6" - wire width 2 $1\fus_src4_i$75[1:0]$2617 - attribute \src "libresoc.v:45820.3-45829.6" - wire width 4 $1\fus_src4_i$78[3:0]$2645 - attribute \src "libresoc.v:46060.3-46069.6" - wire width 64 $1\fus_src4_i$88[63:0]$2696 - attribute \src "libresoc.v:45510.3-45519.6" + attribute \src "libresoc.v:46288.3-46297.6" + wire $1\fus_src4_i$76[0:0]$2614 + attribute \src "libresoc.v:46307.3-46316.6" + wire width 2 $1\fus_src4_i$77[1:0]$2620 + attribute \src "libresoc.v:46402.3-46411.6" + wire width 4 $1\fus_src4_i$80[3:0]$2646 + attribute \src "libresoc.v:46751.3-46760.6" + wire width 64 $1\fus_src4_i$90[63:0]$2708 + attribute \src "libresoc.v:46231.3-46240.6" wire $1\fus_src4_i[0:0] - attribute \src "libresoc.v:45752.3-45761.6" - wire width 2 $1\fus_src5_i$76[1:0]$2632 - attribute \src "libresoc.v:45858.3-45867.6" - wire width 4 $1\fus_src5_i$82[3:0]$2657 - attribute \src "libresoc.v:45733.3-45742.6" + attribute \src "libresoc.v:46364.3-46373.6" + wire width 2 $1\fus_src5_i$78[1:0]$2634 + attribute \src "libresoc.v:46467.3-46476.6" + wire width 4 $1\fus_src5_i$84[3:0]$2664 + attribute \src "libresoc.v:46345.3-46354.6" wire width 2 $1\fus_src5_i[1:0] - attribute \src "libresoc.v:45907.3-45916.6" - wire width 4 $1\fus_src6_i$83[3:0]$2664 - attribute \src "libresoc.v:45684.3-45693.6" + attribute \src "libresoc.v:46577.3-46586.6" + wire width 4 $1\fus_src6_i$85[3:0]$2671 + attribute \src "libresoc.v:46326.3-46335.6" wire width 2 $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46194.3-46202.6" - wire $1\wr_pick_dly$1000$next[0:0]$2714 - attribute \src "libresoc.v:46232.3-46240.6" - wire $1\wr_pick_dly$1021$next[0:0]$2718 - attribute \src "libresoc.v:46270.3-46278.6" - wire $1\wr_pick_dly$1039$next[0:0]$2722 - attribute \src "libresoc.v:46279.3-46287.6" - wire $1\wr_pick_dly$1061$next[0:0]$2725 - attribute \src "libresoc.v:46317.3-46325.6" - wire $1\wr_pick_dly$1081$next[0:0]$2729 - attribute \src "libresoc.v:46355.3-46363.6" - wire $1\wr_pick_dly$1101$next[0:0]$2733 - attribute \src "libresoc.v:46364.3-46372.6" - wire $1\wr_pick_dly$1120$next[0:0]$2736 - attribute \src "libresoc.v:46402.3-46410.6" - wire $1\wr_pick_dly$1138$next[0:0]$2740 - attribute \src "libresoc.v:46440.3-46448.6" - wire $1\wr_pick_dly$1211$next[0:0]$2744 - attribute \src "libresoc.v:46478.3-46486.6" - wire $1\wr_pick_dly$1239$next[0:0]$2748 - attribute \src "libresoc.v:46516.3-46524.6" - wire $1\wr_pick_dly$1259$next[0:0]$2752 - attribute \src "libresoc.v:46525.3-46533.6" - wire $1\wr_pick_dly$1279$next[0:0]$2755 - attribute \src "libresoc.v:46563.3-46571.6" - wire $1\wr_pick_dly$1299$next[0:0]$2759 - attribute \src "libresoc.v:46572.3-46580.6" - wire $1\wr_pick_dly$1319$next[0:0]$2762 - attribute \src "libresoc.v:46610.3-46618.6" - wire $1\wr_pick_dly$1339$next[0:0]$2766 - attribute \src "libresoc.v:46648.3-46656.6" - wire $1\wr_pick_dly$1386$next[0:0]$2774 - attribute \src "libresoc.v:46686.3-46694.6" - wire $1\wr_pick_dly$1402$next[0:0]$2782 - attribute \src "libresoc.v:46695.3-46703.6" - wire $1\wr_pick_dly$1418$next[0:0]$2785 - attribute \src "libresoc.v:46733.3-46741.6" - wire $1\wr_pick_dly$1452$next[0:0]$2789 - attribute \src "libresoc.v:46771.3-46779.6" - wire $1\wr_pick_dly$1468$next[0:0]$2793 - attribute \src "libresoc.v:46780.3-46788.6" - wire $1\wr_pick_dly$1484$next[0:0]$2796 - attribute \src "libresoc.v:46818.3-46826.6" - wire $1\wr_pick_dly$1500$next[0:0]$2800 - attribute \src "libresoc.v:46856.3-46864.6" - wire $1\wr_pick_dly$1536$next[0:0]$2804 - attribute \src "libresoc.v:46865.3-46873.6" - wire $1\wr_pick_dly$1552$next[0:0]$2807 - attribute \src "libresoc.v:46904.3-46912.6" - wire $1\wr_pick_dly$1568$next[0:0]$2811 - attribute \src "libresoc.v:46913.3-46921.6" - wire $1\wr_pick_dly$1584$next[0:0]$2814 - attribute \src "libresoc.v:46922.3-46930.6" - wire $1\wr_pick_dly$1626$next[0:0]$2817 - attribute \src "libresoc.v:46960.3-46968.6" - wire $1\wr_pick_dly$1645$next[0:0]$2821 - attribute \src "libresoc.v:46998.3-47006.6" - wire $1\wr_pick_dly$1661$next[0:0]$2825 - attribute \src "libresoc.v:47007.3-47015.6" - wire $1\wr_pick_dly$1677$next[0:0]$2828 - attribute \src "libresoc.v:47045.3-47053.6" - wire $1\wr_pick_dly$1693$next[0:0]$2836 - attribute \src "libresoc.v:47083.3-47091.6" - wire $1\wr_pick_dly$1737$next[0:0]$2844 - attribute \src "libresoc.v:47121.3-47129.6" - wire $1\wr_pick_dly$1753$next[0:0]$2848 - attribute \src "libresoc.v:47130.3-47138.6" - wire $1\wr_pick_dly$1777$next[0:0]$2851 - attribute \src "libresoc.v:47168.3-47176.6" - wire $1\wr_pick_dly$1797$next[0:0]$2855 - attribute \src "libresoc.v:46185.3-46193.6" - wire $1\wr_pick_dly$981$next[0:0]$2711 - attribute \src "libresoc.v:46147.3-46155.6" - wire $1\wr_pick_dly$next[0:0]$2707 - attribute \src "libresoc.v:41154.7-41154.25" + attribute \src "libresoc.v:46858.3-46866.6" + wire $1\wr_pick_dly$1010$next[0:0]$2725 + attribute \src "libresoc.v:46867.3-46875.6" + wire $1\wr_pick_dly$1031$next[0:0]$2728 + attribute \src "libresoc.v:46906.3-46914.6" + wire $1\wr_pick_dly$1049$next[0:0]$2732 + attribute \src "libresoc.v:46915.3-46923.6" + wire $1\wr_pick_dly$1071$next[0:0]$2735 + attribute \src "libresoc.v:46924.3-46932.6" + wire $1\wr_pick_dly$1091$next[0:0]$2738 + attribute \src "libresoc.v:46962.3-46970.6" + wire $1\wr_pick_dly$1111$next[0:0]$2742 + attribute \src "libresoc.v:46971.3-46979.6" + wire $1\wr_pick_dly$1130$next[0:0]$2745 + attribute \src "libresoc.v:47009.3-47017.6" + wire $1\wr_pick_dly$1148$next[0:0]$2749 + attribute \src "libresoc.v:47047.3-47055.6" + wire $1\wr_pick_dly$1222$next[0:0]$2753 + attribute \src "libresoc.v:47085.3-47093.6" + wire $1\wr_pick_dly$1250$next[0:0]$2757 + attribute \src "libresoc.v:47123.3-47131.6" + wire $1\wr_pick_dly$1270$next[0:0]$2761 + attribute \src "libresoc.v:47132.3-47140.6" + wire $1\wr_pick_dly$1290$next[0:0]$2764 + attribute \src "libresoc.v:47170.3-47178.6" + wire $1\wr_pick_dly$1310$next[0:0]$2768 + attribute \src "libresoc.v:47179.3-47187.6" + wire $1\wr_pick_dly$1330$next[0:0]$2771 + attribute \src "libresoc.v:47217.3-47225.6" + wire $1\wr_pick_dly$1350$next[0:0]$2775 + attribute \src "libresoc.v:47255.3-47263.6" + wire $1\wr_pick_dly$1397$next[0:0]$2779 + attribute \src "libresoc.v:47264.3-47272.6" + wire $1\wr_pick_dly$1413$next[0:0]$2782 + attribute \src "libresoc.v:47302.3-47310.6" + wire $1\wr_pick_dly$1429$next[0:0]$2786 + attribute \src "libresoc.v:47340.3-47348.6" + wire $1\wr_pick_dly$1463$next[0:0]$2790 + attribute \src "libresoc.v:47378.3-47386.6" + wire $1\wr_pick_dly$1479$next[0:0]$2794 + attribute \src "libresoc.v:47387.3-47395.6" + wire $1\wr_pick_dly$1495$next[0:0]$2797 + attribute \src "libresoc.v:47425.3-47433.6" + wire $1\wr_pick_dly$1511$next[0:0]$2801 + attribute \src "libresoc.v:47463.3-47471.6" + wire $1\wr_pick_dly$1547$next[0:0]$2805 + attribute \src "libresoc.v:47472.3-47480.6" + wire $1\wr_pick_dly$1563$next[0:0]$2808 + attribute \src "libresoc.v:47510.3-47518.6" + wire $1\wr_pick_dly$1579$next[0:0]$2812 + attribute \src "libresoc.v:47519.3-47527.6" + wire $1\wr_pick_dly$1595$next[0:0]$2815 + attribute \src "libresoc.v:47557.3-47565.6" + wire $1\wr_pick_dly$1637$next[0:0]$2819 + attribute \src "libresoc.v:47595.3-47603.6" + wire $1\wr_pick_dly$1656$next[0:0]$2827 + attribute \src "libresoc.v:47633.3-47641.6" + wire $1\wr_pick_dly$1672$next[0:0]$2835 + attribute \src "libresoc.v:47642.3-47650.6" + wire $1\wr_pick_dly$1688$next[0:0]$2838 + attribute \src "libresoc.v:47680.3-47688.6" + wire $1\wr_pick_dly$1704$next[0:0]$2842 + attribute \src "libresoc.v:47718.3-47726.6" + wire $1\wr_pick_dly$1748$next[0:0]$2846 + attribute \src "libresoc.v:47727.3-47735.6" + wire $1\wr_pick_dly$1764$next[0:0]$2849 + attribute \src "libresoc.v:47765.3-47773.6" + wire $1\wr_pick_dly$1788$next[0:0]$2853 + attribute \src "libresoc.v:47803.3-47811.6" + wire $1\wr_pick_dly$1808$next[0:0]$2857 + attribute \src "libresoc.v:46819.3-46827.6" + wire $1\wr_pick_dly$991$next[0:0]$2721 + attribute \src "libresoc.v:46810.3-46818.6" + wire $1\wr_pick_dly$next[0:0]$2718 + attribute \src "libresoc.v:41724.7-41724.25" wire $1\wr_pick_dly[0:0] - attribute \src "libresoc.v:45520.3-45540.6" - wire $2\core_terminate_o$next[0:0]$2590 - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46587.3-46607.6" + wire $2\core_terminate_o$next[0:0]$2675 + attribute \src "libresoc.v:46477.3-46567.6" wire $2\corebusy_o[0:0] - attribute \src "libresoc.v:45345.3-45371.6" - wire width 2 $2\counter$next[1:0]$2567 - attribute \src "libresoc.v:46619.3-46647.6" - wire $2\fus_cu_issue_i$11[0:0]$2770 - attribute \src "libresoc.v:47016.3-47044.6" - wire $2\fus_cu_issue_i$14[0:0]$2832 - attribute \src "libresoc.v:47380.3-47408.6" - wire $2\fus_cu_issue_i$17[0:0]$2866 - attribute \src "libresoc.v:47876.3-47904.6" - wire $2\fus_cu_issue_i$20[0:0]$2891 - attribute \src "libresoc.v:43203.3-43231.6" - wire $2\fus_cu_issue_i$23[0:0]$2358 - attribute \src "libresoc.v:43699.3-43727.6" - wire $2\fus_cu_issue_i$26[0:0]$2383 - attribute \src "libresoc.v:44021.3-44049.6" - wire $2\fus_cu_issue_i$29[0:0]$2402 - attribute \src "libresoc.v:44488.3-44516.6" - wire $2\fus_cu_issue_i$32[0:0]$2426 - attribute \src "libresoc.v:44926.3-44954.6" - wire $2\fus_cu_issue_i$35[0:0]$2449 - attribute \src "libresoc.v:46411.3-46439.6" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $2\counter$next[1:0]$2656 + attribute \src "libresoc.v:47566.3-47594.6" + wire $2\fus_cu_issue_i$13[0:0]$2823 + attribute \src "libresoc.v:47900.3-47928.6" + wire $2\fus_cu_issue_i$16[0:0]$2864 + attribute \src "libresoc.v:48219.3-48247.6" + wire $2\fus_cu_issue_i$19[0:0]$2883 + attribute \src "libresoc.v:43868.3-43896.6" + wire $2\fus_cu_issue_i$22[0:0]$2361 + attribute \src "libresoc.v:44042.3-44070.6" + wire $2\fus_cu_issue_i$25[0:0]$2375 + attribute \src "libresoc.v:44538.3-44566.6" + wire $2\fus_cu_issue_i$28[0:0]$2400 + attribute \src "libresoc.v:44860.3-44888.6" + wire $2\fus_cu_issue_i$31[0:0]$2419 + attribute \src "libresoc.v:45327.3-45355.6" + wire $2\fus_cu_issue_i$34[0:0]$2443 + attribute \src "libresoc.v:45765.3-45793.6" + wire $2\fus_cu_issue_i$37[0:0]$2466 + attribute \src "libresoc.v:47349.3-47377.6" wire $2\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46657.3-46685.6" - wire width 6 $2\fus_cu_rdmaskn_i$13[5:0]$2778 - attribute \src "libresoc.v:47054.3-47082.6" - wire width 3 $2\fus_cu_rdmaskn_i$16[2:0]$2840 - attribute \src "libresoc.v:47409.3-47437.6" - wire width 4 $2\fus_cu_rdmaskn_i$19[3:0]$2871 - attribute \src "libresoc.v:47905.3-47933.6" - wire width 3 $2\fus_cu_rdmaskn_i$22[2:0]$2896 - attribute \src "libresoc.v:43232.3-43260.6" - wire width 6 $2\fus_cu_rdmaskn_i$25[5:0]$2363 - attribute \src "libresoc.v:43728.3-43756.6" - wire width 3 $2\fus_cu_rdmaskn_i$28[2:0]$2388 - attribute \src "libresoc.v:44050.3-44078.6" - wire width 3 $2\fus_cu_rdmaskn_i$31[2:0]$2407 - attribute \src "libresoc.v:44517.3-44545.6" - wire width 5 $2\fus_cu_rdmaskn_i$34[4:0]$2431 - attribute \src "libresoc.v:44955.3-44983.6" - wire width 3 $2\fus_cu_rdmaskn_i$37[2:0]$2454 - attribute \src "libresoc.v:46449.3-46477.6" + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2831 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2869 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2888 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2366 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2380 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2405 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2424 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2448 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2471 + attribute \src "libresoc.v:47396.3-47424.6" wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46326.3-46354.6" + attribute \src "libresoc.v:47273.3-47301.6" wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45636.3-45664.6" - wire width 12 $2\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45703.3-45732.6" + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $2\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45703.3-45732.6" + attribute \src "libresoc.v:46761.3-46790.6" wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46156.3-46184.6" + attribute \src "libresoc.v:47094.3-47122.6" wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46373.3-46401.6" + attribute \src "libresoc.v:47311.3-47339.6" wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45579.3-45607.6" + attribute \src "libresoc.v:46646.3-46674.6" wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45955.3-45983.6" + attribute \src "libresoc.v:46933.3-46961.6" wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46070.3-46098.6" + attribute \src "libresoc.v:47018.3-47046.6" wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46241.3-46269.6" + attribute \src "libresoc.v:47188.3-47216.6" wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46288.3-46316.6" + attribute \src "libresoc.v:47226.3-47254.6" wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45868.3-45897.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:45868.3-45897.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46203.3-46231.6" + attribute \src "libresoc.v:47141.3-47169.6" wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45781.3-45810.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45781.3-45810.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46118.3-46146.6" + attribute \src "libresoc.v:47056.3-47084.6" wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46003.3-46031.6" + attribute \src "libresoc.v:46980.3-47008.6" wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46704.3-46732.6" + attribute \src "libresoc.v:47651.3-47679.6" wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46789.3-46817.6" - wire width 12 $2\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46874.3-46903.6" + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $2\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:46874.3-46903.6" + attribute \src "libresoc.v:47812.3-47841.6" wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46827.3-46855.6" + attribute \src "libresoc.v:47774.3-47802.6" wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46742.3-46770.6" + attribute \src "libresoc.v:47689.3-47717.6" wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46969.3-46997.6" + attribute \src "libresoc.v:47871.3-47899.6" wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46931.3-46959.6" + attribute \src "libresoc.v:47842.3-47870.6" wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46534.3-46562.6" - wire width 12 $2\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46581.3-46609.6" + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $2\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46487.3-46515.6" + attribute \src "libresoc.v:47434.3-47462.6" wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43641.3-43669.6" + attribute \src "libresoc.v:44480.3-44508.6" wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43290.3-43318.6" - wire width 12 $2\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43319.3-43348.6" + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $2\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43319.3-43348.6" + attribute \src "libresoc.v:44158.3-44187.6" wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43467.3-43495.6" + attribute \src "libresoc.v:44306.3-44334.6" wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43670.3-43698.6" + attribute \src "libresoc.v:44509.3-44537.6" wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43261.3-43289.6" + attribute \src "libresoc.v:44100.3-44128.6" wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43409.3-43437.6" + attribute \src "libresoc.v:44248.3-44276.6" wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43496.3-43524.6" + attribute \src "libresoc.v:44335.3-44363.6" wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43583.3-43611.6" + attribute \src "libresoc.v:44422.3-44450.6" wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43612.3-43640.6" + attribute \src "libresoc.v:44451.3-44479.6" wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43379.3-43408.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43379.3-43408.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43554.3-43582.6" + attribute \src "libresoc.v:44393.3-44421.6" wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43349.3-43378.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $2\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43349.3-43378.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43525.3-43553.6" + attribute \src "libresoc.v:44364.3-44392.6" wire $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43438.3-43466.6" + attribute \src "libresoc.v:44277.3-44305.6" wire $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:47818.3-47846.6" + attribute \src "libresoc.v:43810.3-43838.6" wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47467.3-47495.6" - wire width 12 $2\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47496.3-47525.6" + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $2\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47496.3-47525.6" + attribute \src "libresoc.v:48335.3-48364.6" wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47644.3-47672.6" + attribute \src "libresoc.v:48483.3-48511.6" wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47847.3-47875.6" + attribute \src "libresoc.v:43839.3-43867.6" wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47438.3-47466.6" + attribute \src "libresoc.v:48277.3-48305.6" wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47586.3-47614.6" + attribute \src "libresoc.v:48425.3-48453.6" wire $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47673.3-47701.6" + attribute \src "libresoc.v:48512.3-48540.6" wire $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47760.3-47788.6" + attribute \src "libresoc.v:43752.3-43780.6" wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47789.3-47817.6" + attribute \src "libresoc.v:43781.3-43809.6" wire $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47556.3-47585.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47556.3-47585.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47731.3-47759.6" + attribute \src "libresoc.v:43723.3-43751.6" wire $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47526.3-47555.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47526.3-47555.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47702.3-47730.6" + attribute \src "libresoc.v:48541.3-48569.6" wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47615.3-47643.6" + attribute \src "libresoc.v:48454.3-48482.6" wire $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43786.3-43814.6" - wire width 12 $2\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43815.3-43844.6" + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $2\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:43815.3-43844.6" + attribute \src "libresoc.v:44654.3-44683.6" wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43992.3-44020.6" + attribute \src "libresoc.v:44831.3-44859.6" wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43757.3-43785.6" + attribute \src "libresoc.v:44596.3-44624.6" wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43934.3-43962.6" + attribute \src "libresoc.v:44773.3-44801.6" wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43963.3-43991.6" + attribute \src "libresoc.v:44802.3-44830.6" wire $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43875.3-43904.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:43875.3-43904.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43845.3-43874.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:43845.3-43874.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43905.3-43933.6" + attribute \src "libresoc.v:44744.3-44772.6" wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44108.3-44136.6" - wire width 12 $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44137.3-44166.6" + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44137.3-44166.6" + attribute \src "libresoc.v:44976.3-45005.6" wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44285.3-44313.6" + attribute \src "libresoc.v:45124.3-45152.6" wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44343.3-44371.6" + attribute \src "libresoc.v:45182.3-45210.6" wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44459.3-44487.6" + attribute \src "libresoc.v:45298.3-45326.6" wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44079.3-44107.6" + attribute \src "libresoc.v:44918.3-44946.6" wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44256.3-44284.6" + attribute \src "libresoc.v:45095.3-45123.6" wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44401.3-44429.6" + attribute \src "libresoc.v:45240.3-45268.6" wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44430.3-44458.6" + attribute \src "libresoc.v:45269.3-45297.6" wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44197.3-44226.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44197.3-44226.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44314.3-44342.6" + attribute \src "libresoc.v:45153.3-45181.6" wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44372.3-44400.6" + attribute \src "libresoc.v:45211.3-45239.6" wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44167.3-44196.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44167.3-44196.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44227.3-44255.6" + attribute \src "libresoc.v:45066.3-45094.6" wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:47963.3-47991.6" - wire width 12 $2\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:43145.3-43173.6" + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $2\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47934.3-47962.6" + attribute \src "libresoc.v:43926.3-43954.6" wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43174.3-43202.6" + attribute \src "libresoc.v:44013.3-44041.6" wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47235.3-47263.6" + attribute \src "libresoc.v:48074.3-48102.6" wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47139.3-47167.6" - wire width 12 $2\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:47177.3-47205.6" + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $2\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47092.3-47120.6" + attribute \src "libresoc.v:47958.3-47986.6" wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47264.3-47292.6" + attribute \src "libresoc.v:48103.3-48131.6" wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47351.3-47379.6" + attribute \src "libresoc.v:48190.3-48218.6" wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47206.3-47234.6" + attribute \src "libresoc.v:48045.3-48073.6" wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47322.3-47350.6" + attribute \src "libresoc.v:48161.3-48189.6" wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47293.3-47321.6" + attribute \src "libresoc.v:48132.3-48160.6" wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:44810.3-44838.6" + attribute \src "libresoc.v:45649.3-45677.6" wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44781.3-44809.6" + attribute \src "libresoc.v:45620.3-45648.6" wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44575.3-44603.6" - wire width 12 $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44604.3-44633.6" + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44604.3-44633.6" + attribute \src "libresoc.v:45443.3-45472.6" wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44897.3-44925.6" + attribute \src "libresoc.v:45736.3-45764.6" wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44546.3-44574.6" + attribute \src "libresoc.v:45385.3-45413.6" wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44723.3-44751.6" + attribute \src "libresoc.v:45562.3-45590.6" wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44752.3-44780.6" + attribute \src "libresoc.v:45591.3-45619.6" wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44868.3-44896.6" + attribute \src "libresoc.v:45707.3-45735.6" wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44693.3-44722.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44693.3-44722.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44663.3-44692.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44663.3-44692.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44839.3-44867.6" + attribute \src "libresoc.v:45678.3-45706.6" wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44634.3-44662.6" + attribute \src "libresoc.v:45473.3-45501.6" wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45520.3-45540.6" - wire $3\core_terminate_o$next[0:0]$2591 - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46587.3-46607.6" + wire $3\core_terminate_o$next[0:0]$2676 + attribute \src "libresoc.v:46477.3-46567.6" wire $3\corebusy_o[0:0] - attribute \src "libresoc.v:45345.3-45371.6" - wire width 2 $3\counter$next[1:0]$2568 - attribute \src "libresoc.v:46619.3-46647.6" - wire $3\fus_cu_issue_i$11[0:0]$2771 - attribute \src "libresoc.v:47016.3-47044.6" - wire $3\fus_cu_issue_i$14[0:0]$2833 - attribute \src "libresoc.v:47380.3-47408.6" - wire $3\fus_cu_issue_i$17[0:0]$2867 - attribute \src "libresoc.v:47876.3-47904.6" - wire $3\fus_cu_issue_i$20[0:0]$2892 - attribute \src "libresoc.v:43203.3-43231.6" - wire $3\fus_cu_issue_i$23[0:0]$2359 - attribute \src "libresoc.v:43699.3-43727.6" - wire $3\fus_cu_issue_i$26[0:0]$2384 - attribute \src "libresoc.v:44021.3-44049.6" - wire $3\fus_cu_issue_i$29[0:0]$2403 - attribute \src "libresoc.v:44488.3-44516.6" - wire $3\fus_cu_issue_i$32[0:0]$2427 - attribute \src "libresoc.v:44926.3-44954.6" - wire $3\fus_cu_issue_i$35[0:0]$2450 - attribute \src "libresoc.v:46411.3-46439.6" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $3\counter$next[1:0]$2657 + attribute \src "libresoc.v:47566.3-47594.6" + wire $3\fus_cu_issue_i$13[0:0]$2824 + attribute \src "libresoc.v:47900.3-47928.6" + wire $3\fus_cu_issue_i$16[0:0]$2865 + attribute \src "libresoc.v:48219.3-48247.6" + wire $3\fus_cu_issue_i$19[0:0]$2884 + attribute \src "libresoc.v:43868.3-43896.6" + wire $3\fus_cu_issue_i$22[0:0]$2362 + attribute \src "libresoc.v:44042.3-44070.6" + wire $3\fus_cu_issue_i$25[0:0]$2376 + attribute \src "libresoc.v:44538.3-44566.6" + wire $3\fus_cu_issue_i$28[0:0]$2401 + attribute \src "libresoc.v:44860.3-44888.6" + wire $3\fus_cu_issue_i$31[0:0]$2420 + attribute \src "libresoc.v:45327.3-45355.6" + wire $3\fus_cu_issue_i$34[0:0]$2444 + attribute \src "libresoc.v:45765.3-45793.6" + wire $3\fus_cu_issue_i$37[0:0]$2467 + attribute \src "libresoc.v:47349.3-47377.6" wire $3\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46657.3-46685.6" - wire width 6 $3\fus_cu_rdmaskn_i$13[5:0]$2779 - attribute \src "libresoc.v:47054.3-47082.6" - wire width 3 $3\fus_cu_rdmaskn_i$16[2:0]$2841 - attribute \src "libresoc.v:47409.3-47437.6" - wire width 4 $3\fus_cu_rdmaskn_i$19[3:0]$2872 - attribute \src "libresoc.v:47905.3-47933.6" - wire width 3 $3\fus_cu_rdmaskn_i$22[2:0]$2897 - attribute \src "libresoc.v:43232.3-43260.6" - wire width 6 $3\fus_cu_rdmaskn_i$25[5:0]$2364 - attribute \src "libresoc.v:43728.3-43756.6" - wire width 3 $3\fus_cu_rdmaskn_i$28[2:0]$2389 - attribute \src "libresoc.v:44050.3-44078.6" - wire width 3 $3\fus_cu_rdmaskn_i$31[2:0]$2408 - attribute \src "libresoc.v:44517.3-44545.6" - wire width 5 $3\fus_cu_rdmaskn_i$34[4:0]$2432 - attribute \src "libresoc.v:44955.3-44983.6" - wire width 3 $3\fus_cu_rdmaskn_i$37[2:0]$2455 - attribute \src "libresoc.v:46449.3-46477.6" + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2832 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2870 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2889 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2367 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2381 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2406 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2425 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2449 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2472 + attribute \src "libresoc.v:47396.3-47424.6" wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46326.3-46354.6" + attribute \src "libresoc.v:47273.3-47301.6" wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45636.3-45664.6" - wire width 12 $3\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45703.3-45732.6" + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $3\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45703.3-45732.6" + attribute \src "libresoc.v:46761.3-46790.6" wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46156.3-46184.6" + attribute \src "libresoc.v:47094.3-47122.6" wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46373.3-46401.6" + attribute \src "libresoc.v:47311.3-47339.6" wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45579.3-45607.6" + attribute \src "libresoc.v:46646.3-46674.6" wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45955.3-45983.6" + attribute \src "libresoc.v:46933.3-46961.6" wire $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46070.3-46098.6" + attribute \src "libresoc.v:47018.3-47046.6" wire $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46241.3-46269.6" + attribute \src "libresoc.v:47188.3-47216.6" wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46288.3-46316.6" + attribute \src "libresoc.v:47226.3-47254.6" wire $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45868.3-45897.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:45868.3-45897.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46203.3-46231.6" + attribute \src "libresoc.v:47141.3-47169.6" wire $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45781.3-45810.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45781.3-45810.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46118.3-46146.6" + attribute \src "libresoc.v:47056.3-47084.6" wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46003.3-46031.6" + attribute \src "libresoc.v:46980.3-47008.6" wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46704.3-46732.6" + attribute \src "libresoc.v:47651.3-47679.6" wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46789.3-46817.6" - wire width 12 $3\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46874.3-46903.6" + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $3\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:46874.3-46903.6" + attribute \src "libresoc.v:47812.3-47841.6" wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46827.3-46855.6" + attribute \src "libresoc.v:47774.3-47802.6" wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46742.3-46770.6" + attribute \src "libresoc.v:47689.3-47717.6" wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46969.3-46997.6" + attribute \src "libresoc.v:47871.3-47899.6" wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46931.3-46959.6" + attribute \src "libresoc.v:47842.3-47870.6" wire $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46534.3-46562.6" - wire width 12 $3\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46581.3-46609.6" + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $3\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46487.3-46515.6" + attribute \src "libresoc.v:47434.3-47462.6" wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43641.3-43669.6" + attribute \src "libresoc.v:44480.3-44508.6" wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43290.3-43318.6" - wire width 12 $3\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43319.3-43348.6" + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $3\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43319.3-43348.6" + attribute \src "libresoc.v:44158.3-44187.6" wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43467.3-43495.6" + attribute \src "libresoc.v:44306.3-44334.6" wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43670.3-43698.6" + attribute \src "libresoc.v:44509.3-44537.6" wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43261.3-43289.6" + attribute \src "libresoc.v:44100.3-44128.6" wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43409.3-43437.6" + attribute \src "libresoc.v:44248.3-44276.6" wire $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43496.3-43524.6" + attribute \src "libresoc.v:44335.3-44363.6" wire $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43583.3-43611.6" + attribute \src "libresoc.v:44422.3-44450.6" wire $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43612.3-43640.6" + attribute \src "libresoc.v:44451.3-44479.6" wire $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43379.3-43408.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $3\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43379.3-43408.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43554.3-43582.6" + attribute \src "libresoc.v:44393.3-44421.6" wire $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43349.3-43378.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $3\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43349.3-43378.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43525.3-43553.6" + attribute \src "libresoc.v:44364.3-44392.6" wire $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43438.3-43466.6" + attribute \src "libresoc.v:44277.3-44305.6" wire $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:47818.3-47846.6" + attribute \src "libresoc.v:43810.3-43838.6" wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47467.3-47495.6" - wire width 12 $3\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47496.3-47525.6" + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $3\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47496.3-47525.6" + attribute \src "libresoc.v:48335.3-48364.6" wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47644.3-47672.6" + attribute \src "libresoc.v:48483.3-48511.6" wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47847.3-47875.6" + attribute \src "libresoc.v:43839.3-43867.6" wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47438.3-47466.6" + attribute \src "libresoc.v:48277.3-48305.6" wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47586.3-47614.6" + attribute \src "libresoc.v:48425.3-48453.6" wire $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47673.3-47701.6" + attribute \src "libresoc.v:48512.3-48540.6" wire $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47760.3-47788.6" + attribute \src "libresoc.v:43752.3-43780.6" wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47789.3-47817.6" + attribute \src "libresoc.v:43781.3-43809.6" wire $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47556.3-47585.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47556.3-47585.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47731.3-47759.6" + attribute \src "libresoc.v:43723.3-43751.6" wire $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47526.3-47555.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47526.3-47555.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47702.3-47730.6" + attribute \src "libresoc.v:48541.3-48569.6" wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47615.3-47643.6" + attribute \src "libresoc.v:48454.3-48482.6" wire $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43786.3-43814.6" - wire width 12 $3\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43815.3-43844.6" + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $3\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:43815.3-43844.6" + attribute \src "libresoc.v:44654.3-44683.6" wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43992.3-44020.6" + attribute \src "libresoc.v:44831.3-44859.6" wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43757.3-43785.6" + attribute \src "libresoc.v:44596.3-44624.6" wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43934.3-43962.6" + attribute \src "libresoc.v:44773.3-44801.6" wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43963.3-43991.6" + attribute \src "libresoc.v:44802.3-44830.6" wire $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43875.3-43904.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:43875.3-43904.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43845.3-43874.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:43845.3-43874.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43905.3-43933.6" + attribute \src "libresoc.v:44744.3-44772.6" wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44108.3-44136.6" - wire width 12 $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44137.3-44166.6" + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44137.3-44166.6" + attribute \src "libresoc.v:44976.3-45005.6" wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44285.3-44313.6" + attribute \src "libresoc.v:45124.3-45152.6" wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44343.3-44371.6" + attribute \src "libresoc.v:45182.3-45210.6" wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44459.3-44487.6" + attribute \src "libresoc.v:45298.3-45326.6" wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44079.3-44107.6" + attribute \src "libresoc.v:44918.3-44946.6" wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44256.3-44284.6" + attribute \src "libresoc.v:45095.3-45123.6" wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44401.3-44429.6" + attribute \src "libresoc.v:45240.3-45268.6" wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44430.3-44458.6" + attribute \src "libresoc.v:45269.3-45297.6" wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44197.3-44226.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44197.3-44226.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44314.3-44342.6" + attribute \src "libresoc.v:45153.3-45181.6" wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44372.3-44400.6" + attribute \src "libresoc.v:45211.3-45239.6" wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44167.3-44196.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44167.3-44196.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44227.3-44255.6" + attribute \src "libresoc.v:45066.3-45094.6" wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:47963.3-47991.6" - wire width 12 $3\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:43145.3-43173.6" + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $3\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47934.3-47962.6" + attribute \src "libresoc.v:43926.3-43954.6" wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43174.3-43202.6" + attribute \src "libresoc.v:44013.3-44041.6" wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47235.3-47263.6" + attribute \src "libresoc.v:48074.3-48102.6" wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47139.3-47167.6" - wire width 12 $3\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:47177.3-47205.6" + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $3\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47092.3-47120.6" + attribute \src "libresoc.v:47958.3-47986.6" wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47264.3-47292.6" + attribute \src "libresoc.v:48103.3-48131.6" wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47351.3-47379.6" + attribute \src "libresoc.v:48190.3-48218.6" wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47206.3-47234.6" + attribute \src "libresoc.v:48045.3-48073.6" wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47322.3-47350.6" + attribute \src "libresoc.v:48161.3-48189.6" wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47293.3-47321.6" + attribute \src "libresoc.v:48132.3-48160.6" wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:44810.3-44838.6" + attribute \src "libresoc.v:45649.3-45677.6" wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44781.3-44809.6" + attribute \src "libresoc.v:45620.3-45648.6" wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44575.3-44603.6" - wire width 12 $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44604.3-44633.6" + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44604.3-44633.6" + attribute \src "libresoc.v:45443.3-45472.6" wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44897.3-44925.6" + attribute \src "libresoc.v:45736.3-45764.6" wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44546.3-44574.6" + attribute \src "libresoc.v:45385.3-45413.6" wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44723.3-44751.6" + attribute \src "libresoc.v:45562.3-45590.6" wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44752.3-44780.6" + attribute \src "libresoc.v:45591.3-45619.6" wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44868.3-44896.6" + attribute \src "libresoc.v:45707.3-45735.6" wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44693.3-44722.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44693.3-44722.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44663.3-44692.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44663.3-44692.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44839.3-44867.6" + attribute \src "libresoc.v:45678.3-45706.6" wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44634.3-44662.6" + attribute \src "libresoc.v:45473.3-45501.6" wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $4\corebusy_o[0:0] - attribute \src "libresoc.v:45345.3-45371.6" - wire width 2 $4\counter$next[1:0]$2569 - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $4\counter$next[1:0]$2658 + attribute \src "libresoc.v:46477.3-46567.6" wire $5\corebusy_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $6\corebusy_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $7\corebusy_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $8\corebusy_o[0:0] - attribute \src "libresoc.v:45391.3-45481.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $9\corebusy_o[0:0] - attribute \src "libresoc.v:41534.20-41534.109" - wire $and$libresoc.v:41534$1507_Y - attribute \src "libresoc.v:41535.20-41535.122" - wire $and$libresoc.v:41535$1508_Y - attribute \src "libresoc.v:41537.20-41537.122" - wire $and$libresoc.v:41537$1510_Y - attribute \src "libresoc.v:41538.20-41538.126" - wire $and$libresoc.v:41538$1511_Y - attribute \src "libresoc.v:41540.20-41540.110" - wire $and$libresoc.v:41540$1513_Y - attribute \src "libresoc.v:41541.20-41541.123" - wire $and$libresoc.v:41541$1514_Y - attribute \src "libresoc.v:41543.20-41543.122" - wire $and$libresoc.v:41543$1516_Y - attribute \src "libresoc.v:41544.20-41544.126" - wire $and$libresoc.v:41544$1517_Y - attribute \src "libresoc.v:41546.20-41546.110" - wire $and$libresoc.v:41546$1519_Y - attribute \src "libresoc.v:41547.20-41547.123" - wire $and$libresoc.v:41547$1520_Y - attribute \src "libresoc.v:41549.20-41549.123" - wire $and$libresoc.v:41549$1522_Y - attribute \src "libresoc.v:41550.20-41550.126" - wire $and$libresoc.v:41550$1523_Y - attribute \src "libresoc.v:41552.20-41552.110" - wire $and$libresoc.v:41552$1525_Y - attribute \src "libresoc.v:41553.20-41553.123" - wire $and$libresoc.v:41553$1526_Y - attribute \src "libresoc.v:41555.20-41555.123" - wire $and$libresoc.v:41555$1528_Y - attribute \src "libresoc.v:41556.20-41556.126" - wire $and$libresoc.v:41556$1529_Y - attribute \src "libresoc.v:41558.20-41558.110" - wire $and$libresoc.v:41558$1531_Y - attribute \src "libresoc.v:41559.20-41559.123" - wire $and$libresoc.v:41559$1532_Y - attribute \src "libresoc.v:41561.20-41561.123" - wire $and$libresoc.v:41561$1534_Y - attribute \src "libresoc.v:41562.20-41562.126" - wire $and$libresoc.v:41562$1535_Y - attribute \src "libresoc.v:41564.20-41564.110" - wire $and$libresoc.v:41564$1537_Y - attribute \src "libresoc.v:41565.20-41565.123" - wire $and$libresoc.v:41565$1538_Y - attribute \src "libresoc.v:41567.20-41567.113" - wire $and$libresoc.v:41567$1540_Y - attribute \src "libresoc.v:41568.20-41568.126" - wire $and$libresoc.v:41568$1541_Y - attribute \src "libresoc.v:41570.20-41570.110" - wire $and$libresoc.v:41570$1543_Y - attribute \src "libresoc.v:41571.20-41571.123" - wire $and$libresoc.v:41571$1544_Y - attribute \src "libresoc.v:41573.20-41573.114" - wire $and$libresoc.v:41573$1546_Y - attribute \src "libresoc.v:41574.20-41574.126" - wire $and$libresoc.v:41574$1547_Y - attribute \src "libresoc.v:41576.20-41576.110" - wire $and$libresoc.v:41576$1549_Y - attribute \src "libresoc.v:41577.20-41577.123" - wire $and$libresoc.v:41577$1550_Y - attribute \src "libresoc.v:41606.20-41606.123" - wire $and$libresoc.v:41606$1579_Y - attribute \src "libresoc.v:41607.20-41607.128" - wire $and$libresoc.v:41607$1580_Y - attribute \src "libresoc.v:41608.20-41608.133" - wire $and$libresoc.v:41608$1581_Y - attribute \src "libresoc.v:41610.20-41610.110" - wire $and$libresoc.v:41610$1583_Y - attribute \src "libresoc.v:41611.20-41611.128" - wire $and$libresoc.v:41611$1584_Y - attribute \src "libresoc.v:41613.20-41613.116" - wire $and$libresoc.v:41613$1586_Y - attribute \src "libresoc.v:41614.20-41614.123" - wire $and$libresoc.v:41614$1587_Y - attribute \src "libresoc.v:41615.20-41615.128" - wire $and$libresoc.v:41615$1588_Y - attribute \src "libresoc.v:41616.20-41616.128" - wire $and$libresoc.v:41616$1589_Y - attribute \src "libresoc.v:41617.20-41617.129" - wire $and$libresoc.v:41617$1590_Y - attribute \src "libresoc.v:41618.20-41618.129" - wire $and$libresoc.v:41618$1591_Y - attribute \src "libresoc.v:41619.20-41619.129" - wire $and$libresoc.v:41619$1592_Y - attribute \src "libresoc.v:41620.20-41620.130" - wire $and$libresoc.v:41620$1593_Y - attribute \src "libresoc.v:41622.20-41622.110" - wire $and$libresoc.v:41622$1595_Y - attribute \src "libresoc.v:41623.20-41623.125" - wire $and$libresoc.v:41623$1596_Y - attribute \src "libresoc.v:41627.20-41627.126" - wire $and$libresoc.v:41627$1600_Y - attribute \src "libresoc.v:41628.20-41628.130" - wire $and$libresoc.v:41628$1601_Y - attribute \src "libresoc.v:41630.20-41630.110" - wire $and$libresoc.v:41630$1603_Y - attribute \src "libresoc.v:41631.20-41631.125" - wire $and$libresoc.v:41631$1604_Y - attribute \src "libresoc.v:41635.20-41635.126" - wire $and$libresoc.v:41635$1608_Y - attribute \src "libresoc.v:41636.20-41636.130" - wire $and$libresoc.v:41636$1609_Y - attribute \src "libresoc.v:41638.20-41638.110" - wire $and$libresoc.v:41638$1611_Y - attribute \src "libresoc.v:41639.20-41639.125" - wire $and$libresoc.v:41639$1612_Y - attribute \src "libresoc.v:41643.20-41643.126" - wire $and$libresoc.v:41643$1616_Y - attribute \src "libresoc.v:41644.20-41644.130" - wire $and$libresoc.v:41644$1617_Y - attribute \src "libresoc.v:41646.20-41646.110" - wire $and$libresoc.v:41646$1619_Y - attribute \src "libresoc.v:41647.20-41647.125" - wire $and$libresoc.v:41647$1620_Y - attribute \src "libresoc.v:41651.20-41651.126" - wire $and$libresoc.v:41651$1624_Y - attribute \src "libresoc.v:41652.20-41652.130" - wire $and$libresoc.v:41652$1625_Y - attribute \src "libresoc.v:41654.20-41654.110" - wire $and$libresoc.v:41654$1627_Y - attribute \src "libresoc.v:41655.20-41655.125" - wire $and$libresoc.v:41655$1628_Y - attribute \src "libresoc.v:41659.20-41659.126" - wire $and$libresoc.v:41659$1632_Y - attribute \src "libresoc.v:41660.20-41660.130" - wire $and$libresoc.v:41660$1633_Y - attribute \src "libresoc.v:41662.20-41662.110" - wire $and$libresoc.v:41662$1635_Y - attribute \src "libresoc.v:41663.20-41663.125" - wire $and$libresoc.v:41663$1636_Y - attribute \src "libresoc.v:41677.20-41677.118" - wire $and$libresoc.v:41677$1650_Y - attribute \src "libresoc.v:41678.20-41678.123" - wire $and$libresoc.v:41678$1651_Y - attribute \src "libresoc.v:41679.20-41679.129" - wire $and$libresoc.v:41679$1652_Y - attribute \src "libresoc.v:41680.20-41680.129" - wire $and$libresoc.v:41680$1653_Y - attribute \src "libresoc.v:41681.20-41681.136" - wire $and$libresoc.v:41681$1654_Y - attribute \src "libresoc.v:41683.20-41683.110" - wire $and$libresoc.v:41683$1656_Y - attribute \src "libresoc.v:41684.20-41684.128" - wire $and$libresoc.v:41684$1657_Y - attribute \src "libresoc.v:41686.20-41686.128" - wire $and$libresoc.v:41686$1659_Y - attribute \src "libresoc.v:41687.20-41687.136" - wire $and$libresoc.v:41687$1660_Y - attribute \src "libresoc.v:41689.20-41689.110" - wire $and$libresoc.v:41689$1662_Y - attribute \src "libresoc.v:41690.20-41690.128" - wire $and$libresoc.v:41690$1663_Y - attribute \src "libresoc.v:41692.20-41692.128" - wire $and$libresoc.v:41692$1665_Y - attribute \src "libresoc.v:41693.20-41693.136" - wire $and$libresoc.v:41693$1666_Y - attribute \src "libresoc.v:41695.20-41695.110" - wire $and$libresoc.v:41695$1668_Y - attribute \src "libresoc.v:41696.20-41696.128" - wire $and$libresoc.v:41696$1669_Y - attribute \src "libresoc.v:41703.20-41703.118" - wire $and$libresoc.v:41703$1677_Y - attribute \src "libresoc.v:41704.20-41704.123" - wire $and$libresoc.v:41704$1678_Y - attribute \src "libresoc.v:41705.20-41705.129" - wire $and$libresoc.v:41705$1679_Y - attribute \src "libresoc.v:41706.20-41706.129" - wire $and$libresoc.v:41706$1680_Y - attribute \src "libresoc.v:41707.20-41707.129" - wire $and$libresoc.v:41707$1681_Y - attribute \src "libresoc.v:41708.20-41708.136" - wire $and$libresoc.v:41708$1682_Y - attribute \src "libresoc.v:41710.20-41710.110" - wire $and$libresoc.v:41710$1684_Y - attribute \src "libresoc.v:41711.20-41711.128" - wire $and$libresoc.v:41711$1685_Y - attribute \src "libresoc.v:41713.20-41713.128" - wire $and$libresoc.v:41713$1687_Y - attribute \src "libresoc.v:41714.20-41714.136" - wire $and$libresoc.v:41714$1688_Y - attribute \src "libresoc.v:41716.20-41716.110" - wire $and$libresoc.v:41716$1690_Y - attribute \src "libresoc.v:41717.20-41717.128" - wire $and$libresoc.v:41717$1691_Y - attribute \src "libresoc.v:41719.20-41719.128" - wire $and$libresoc.v:41719$1693_Y - attribute \src "libresoc.v:41720.20-41720.136" - wire $and$libresoc.v:41720$1694_Y - attribute \src "libresoc.v:41722.20-41722.110" - wire $and$libresoc.v:41722$1696_Y - attribute \src "libresoc.v:41723.20-41723.128" - wire $and$libresoc.v:41723$1697_Y - attribute \src "libresoc.v:41725.20-41725.128" - wire $and$libresoc.v:41725$1699_Y - attribute \src "libresoc.v:41726.20-41726.136" - wire $and$libresoc.v:41726$1700_Y - attribute \src "libresoc.v:41728.20-41728.110" - wire $and$libresoc.v:41728$1702_Y - attribute \src "libresoc.v:41729.20-41729.128" - wire $and$libresoc.v:41729$1703_Y - attribute \src "libresoc.v:41737.20-41737.118" - wire $and$libresoc.v:41737$1711_Y - attribute \src "libresoc.v:41738.20-41738.123" - wire $and$libresoc.v:41738$1712_Y - attribute \src "libresoc.v:41739.20-41739.129" - wire $and$libresoc.v:41739$1713_Y - attribute \src "libresoc.v:41740.20-41740.129" - wire $and$libresoc.v:41740$1714_Y - attribute \src "libresoc.v:41741.20-41741.129" - wire $and$libresoc.v:41741$1715_Y - attribute \src "libresoc.v:41742.20-41742.136" - wire $and$libresoc.v:41742$1716_Y - attribute \src "libresoc.v:41744.20-41744.110" - wire $and$libresoc.v:41744$1718_Y - attribute \src "libresoc.v:41745.20-41745.128" - wire $and$libresoc.v:41745$1719_Y - attribute \src "libresoc.v:41747.20-41747.128" - wire $and$libresoc.v:41747$1721_Y - attribute \src "libresoc.v:41748.20-41748.136" - wire $and$libresoc.v:41748$1722_Y - attribute \src "libresoc.v:41750.20-41750.110" - wire $and$libresoc.v:41750$1724_Y - attribute \src "libresoc.v:41751.20-41751.128" - wire $and$libresoc.v:41751$1725_Y - attribute \src "libresoc.v:41753.20-41753.128" - wire $and$libresoc.v:41753$1727_Y - attribute \src "libresoc.v:41754.20-41754.136" - wire $and$libresoc.v:41754$1728_Y - attribute \src "libresoc.v:41756.20-41756.110" - wire $and$libresoc.v:41756$1730_Y - attribute \src "libresoc.v:41757.20-41757.128" - wire $and$libresoc.v:41757$1731_Y - attribute \src "libresoc.v:41759.20-41759.128" - wire $and$libresoc.v:41759$1733_Y - attribute \src "libresoc.v:41760.20-41760.136" - wire $and$libresoc.v:41760$1734_Y - attribute \src "libresoc.v:41762.20-41762.110" - wire $and$libresoc.v:41762$1736_Y - attribute \src "libresoc.v:41763.20-41763.128" - wire $and$libresoc.v:41763$1737_Y - attribute \src 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wire \addr_en_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire input 63 \bigendian_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 67 \bigendian_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 8 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 7 \cia__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 7 \cia__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" - wire width 64 input 39 \core_core_cia + wire width 64 input 42 \core_core_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 input 58 \core_core_cr_rd + wire width 8 input 61 \core_core_cr_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 59 \core_core_cr_rd_ok + wire input 62 \core_core_cr_rd_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 input 60 \core_core_cr_wr + wire width 8 input 63 \core_core_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 49 \core_core_exc_$signal + wire input 52 \core_core_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 50 \core_core_exc_$signal$3 + wire input 53 \core_core_exc_$signal$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 51 \core_core_exc_$signal$4 + wire input 54 \core_core_exc_$signal$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 52 \core_core_exc_$signal$5 + wire input 55 \core_core_exc_$signal$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 53 \core_core_exc_$signal$6 + wire input 56 \core_core_exc_$signal$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 54 \core_core_exc_$signal$7 + wire input 57 \core_core_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 55 \core_core_exc_$signal$8 + wire input 58 \core_core_exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 56 \core_core_exc_$signal$9 + wire input 59 \core_core_exc_$signal$9 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 input 42 \core_core_fn_unit + wire width 14 input 45 \core_core_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 2 input 47 \core_core_input_carry + wire width 2 input 50 \core_core_input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 32 input 40 \core_core_insn + wire width 32 input 43 \core_core_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -61633,68 +62126,69 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 7 input 41 \core_core_insn_type + wire width 7 input 44 \core_core_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire input 61 \core_core_is_32bit + wire input 64 \core_core_is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 input 38 \core_core_msr + wire width 64 input 41 \core_core_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 45 \core_core_oe + wire input 48 \core_core_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 46 \core_core_oe_ok + wire input 49 \core_core_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 43 \core_core_rc + wire input 46 \core_core_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 44 \core_core_rc_ok + wire input 47 \core_core_rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 13 input 57 \core_core_trapaddr + wire width 13 input 60 \core_core_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 8 input 48 \core_core_traptype + wire width 8 input 51 \core_core_traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 input 31 \core_cr_in1 + wire width 7 input 34 \core_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 32 \core_cr_in1_ok + wire input 35 \core_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 input 33 \core_cr_in2 + wire width 7 input 36 \core_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 input 35 \core_cr_in2$1 + wire width 7 input 38 \core_cr_in2$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 34 \core_cr_in2_ok + wire input 37 \core_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 36 \core_cr_in2_ok$2 + wire input 39 \core_cr_in2_ok$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 input 37 \core_cr_out + wire width 7 input 40 \core_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 input 14 \core_ea + wire width 7 input 17 \core_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 input 25 \core_fast1 + wire width 3 input 28 \core_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \core_fast1_ok + wire input 29 \core_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 input 27 \core_fast2 + wire width 3 input 30 \core_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 28 \core_fast2_ok + wire input 31 \core_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 input 29 \core_fasto1 + wire width 3 input 32 \core_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 input 30 \core_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 3 input 33 \core_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 65 \core_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 input 15 \core_reg1 + wire width 7 input 18 \core_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 16 \core_reg1_ok + wire input 19 \core_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 input 17 \core_reg2 + wire width 7 input 20 \core_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 18 \core_reg2_ok + wire input 21 \core_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 input 19 \core_reg3 + wire width 7 input 22 \core_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \core_reg3_ok + wire input 23 \core_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 input 13 \core_rego + wire width 7 input 16 \core_rego attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -61760,6 +62254,9 @@ module \core attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -61807,9 +62304,9 @@ module \core attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 input 22 \core_spr1 + wire width 10 input 25 \core_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 23 \core_spr1_ok + wire input 26 \core_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -61875,6 +62372,9 @@ module \core attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -61922,46 +62422,46 @@ module \core attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 input 21 \core_spro + wire width 10 input 24 \core_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" - wire output 12 \core_terminate_o + wire output 14 \core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire \core_terminate_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" - wire width 3 input 24 \core_xer_in + wire width 3 input 27 \core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 92 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 97 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" wire width 2 \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" wire width 2 \counter$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 \cr_full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 \cr_full_wr__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_full_wr__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 4 \cu_ad__go_i @@ -61971,43 +62471,47 @@ module \core wire input 6 \cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire output 3 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 10 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 12 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 70 \data_i$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 84 \dbus__ack + wire input 89 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 89 \dbus__adr + wire width 45 output 94 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 83 \dbus__cyc + wire output 88 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 88 \dbus__dat_r + wire width 64 input 93 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 91 \dbus__dat_w + wire width 64 output 96 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 85 \dbus__err + wire input 90 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 87 \dbus__sel + wire width 8 output 92 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 86 \dbus__stb + wire output 91 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 90 \dbus__we + wire output 95 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_ALU_ALU__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_ALU_ALU__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_ALU_ALU__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_ALU_ALU__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62094,6 +62598,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_ALU_ALU__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62118,27 +62623,31 @@ module \core wire \dec_ALU_ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_ALU_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_ALU_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec_ALU_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__cia attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_BRANCH_BRANCH__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_BRANCH_BRANCH__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62219,31 +62728,34 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_BRANCH_BRANCH__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_BRANCH_BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_BRANCH_BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_BRANCH_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_BRANCH_raw_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_CR_CR__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_CR_CR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_CR_CR__insn attribute \enum_base_type "MicrOp" @@ -62320,29 +62832,32 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_CR_CR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_CR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_CR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_DIV_DIV__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_DIV_DIV__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_DIV_DIV__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_DIV_DIV__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62429,6 +62944,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_DIV_DIV__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62453,29 +62969,33 @@ module \core wire \dec_DIV_DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_DIV_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_DIV_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec_DIV_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LDST_LDST__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_LDST_LDST__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_LDST_LDST__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_LDST_LDST__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62556,6 +63076,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_LDST_LDST__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62581,27 +63102,31 @@ module \core wire \dec_LDST_LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_LDST_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_LDST_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec_LDST_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LOGICAL_LOGICAL__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_LOGICAL_LOGICAL__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_LOGICAL_LOGICAL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_LOGICAL_LOGICAL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62688,6 +63213,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_LOGICAL_LOGICAL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62712,25 +63238,29 @@ module \core wire \dec_LOGICAL_LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_LOGICAL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_LOGICAL_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec_LOGICAL_sv_a_nz attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_MUL_MUL__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_MUL_MUL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_MUL_MUL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62811,6 +63341,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_MUL_MUL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62827,25 +63358,27 @@ module \core wire \dec_MUL_MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_MUL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_MUL_raw_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62934,6 +63467,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_SHIFT_ROT_SHIFT_ROT__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62956,25 +63490,27 @@ module \core wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_SHIFT_ROT_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_SHIFT_ROT_raw_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_SPR_SPR__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_SPR_SPR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_SPR_SPR__insn attribute \enum_base_type "MicrOp" @@ -63051,389 +63587,386 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_SPR_SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SPR_SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec_SPR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_SPR_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 69 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 71 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 70 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 74 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 76 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 75 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_c_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast2_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast2_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_div0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_ldst0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_mul0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_shiftrot0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_spr0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rc_ldst0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rc_shiftrot0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_SPR_spr1_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_shiftrot0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_div0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_logical0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_mul0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_shiftrot0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_spr0_2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_ldst0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_trap0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \fast_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \fast_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \fast_dest1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \fast_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \fast_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \fast_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \fast_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \fast_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \fast_src2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" wire width 10 \fu_enable - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 73 \full_rd2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 72 \full_rd2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 output 75 \full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 74 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 32 output 78 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 input 77 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 6 output 80 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 79 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_cr_a_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_cr_a_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_cr_a_ok$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_cr_a_ok$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_cr_a_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_cr_a_ok$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_cr_a_ok$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o attribute \src 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\fus_cu_issue_i$23 + wire \fus_cu_issue_i$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$26 + wire \fus_cu_issue_i$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$29 + wire \fus_cu_issue_i$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$32 + wire \fus_cu_issue_i$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$35 + wire \fus_cu_issue_i$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__go_i$39 + wire width 6 \fus_cu_rd__go_i$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__go_i$42 + wire width 4 \fus_cu_rd__go_i$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$45 + wire width 3 \fus_cu_rd__go_i$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__go_i$48 + wire width 6 \fus_cu_rd__go_i$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$51 + wire width 3 \fus_cu_rd__go_i$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$54 + wire width 3 \fus_cu_rd__go_i$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_rd__go_i$57 + wire width 5 \fus_cu_rd__go_i$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$60 + wire width 3 \fus_cu_rd__go_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$80 + wire width 3 \fus_cu_rd__go_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__rel_o$38 + wire width 6 \fus_cu_rd__rel_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__rel_o$41 + wire width 4 \fus_cu_rd__rel_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$44 + wire width 3 \fus_cu_rd__rel_o$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__rel_o$47 + wire width 6 \fus_cu_rd__rel_o$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$50 + wire width 3 \fus_cu_rd__rel_o$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$53 + wire width 3 \fus_cu_rd__rel_o$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_rd__rel_o$56 + wire width 5 \fus_cu_rd__rel_o$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$59 + wire width 3 \fus_cu_rd__rel_o$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$79 + wire width 3 \fus_cu_rd__rel_o$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 4 \fus_cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 \fus_cu_rdmaskn_i$13 + wire width 6 \fus_cu_rdmaskn_i$15 attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 \fus_cu_rdmaskn_i$34 + wire width 5 \fus_cu_rdmaskn_i$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$37 + wire width 3 \fus_cu_rdmaskn_i$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_wr__go_i$101 + wire width 2 \fus_cu_wr__go_i$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__go_i$104 + wire width 6 \fus_cu_wr__go_i$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__go_i$107 + wire width 4 \fus_cu_wr__go_i$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$110 + wire width 4 \fus_cu_wr__go_i$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__go_i$112 + wire width 3 \fus_cu_wr__go_i$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$147 + wire width 2 \fus_cu_wr__go_i$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$92 + wire width 3 \fus_cu_wr__go_i$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__go_i$95 + wire width 3 \fus_cu_wr__go_i$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__go_i$98 + wire width 5 \fus_cu_wr__go_i$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_wr__rel_o attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$91 + wire width 3 \fus_cu_wr__rel_o$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__rel_o$94 + wire width 5 \fus_cu_wr__rel_o$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__rel_o$97 + wire width 2 \fus_cu_wr__rel_o$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$116 @@ -63444,13 +63977,13 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$151 + wire width 64 \fus_dest1_o$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 \fus_dest2_o + wire width 64 \fus_dest1_o$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$125 + wire width 64 \fus_dest1_o$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$126 + wire width 32 \fus_dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest2_o$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" @@ -63458,43 +63991,47 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest2_o$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$152 + wire width 4 \fus_dest2_o$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest2_o$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$160 + wire width 64 \fus_dest2_o$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest3_o + wire width 64 \fus_dest2_o$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$132 + wire width 4 \fus_dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$133 + wire width 2 \fus_dest3_o$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$137 + wire width 2 \fus_dest3_o$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$138 + wire width 2 \fus_dest3_o$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$153 + wire width 2 \fus_dest3_o$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest3_o$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest3_o$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire \fus_dest4_o$143 + wire \fus_dest4_o$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire \fus_dest4_o$144 + wire \fus_dest4_o$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire \fus_dest4_o$145 + wire \fus_dest4_o$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest4_o$158 + wire width 64 \fus_dest4_o$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire \fus_dest5_o$142 + wire \fus_dest5_o$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest5_o$159 + wire width 64 \fus_dest5_o$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -63502,13 +64039,13 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_fast1_ok$148 + wire \fus_fast1_ok$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_fast1_ok$149 + wire \fus_fast1_ok$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_fast2_ok$150 + wire \fus_fast2_ok$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -63524,10 +64061,6 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \fus_ldst_port0_exc_$signal$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \fus_ldst_port0_exc_$signal$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$164 @@ -63537,6 +64070,10 @@ module \core wire \fus_ldst_port0_exc_$signal$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire \fus_ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" @@ -63554,42 +64091,44 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_nia_ok$156 + wire \fus_nia_ok$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fus_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_o_ok$102 + wire \fus_o_ok$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_o_ok$105 + wire \fus_o_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_o_ok$108 + wire \fus_o_ok$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_o_ok$90 + wire \fus_o_ok$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_o_ok$93 + wire \fus_o_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_o_ok$96 + wire \fus_o_ok$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_o_ok$99 + wire \fus_o_ok$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_alu0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_alu0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63676,6 +64215,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63703,20 +64243,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_branch0__cia attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_branch0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63797,6 +64339,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63804,20 +64347,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_branch0__lk attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_cr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" @@ -63894,25 +64439,28 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_div0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_div0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63999,6 +64547,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64026,20 +64575,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_logical0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_logical0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64126,6 +64677,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64151,20 +64703,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__zero_a attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_mul0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64245,6 +64799,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64262,20 +64817,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__write_cr0 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_shift_rot0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64364,6 +64921,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64387,20 +64945,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_spr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" @@ -64477,6 +65037,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64484,20 +65045,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_trap0__cia attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_trap0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" @@ -64574,6 +65137,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64591,20 +65155,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_ldst_ldst0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64685,6 +65251,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64715,30 +65282,26 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$40 + wire width 64 \fus_src1_i$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$43 + wire width 64 \fus_src1_i$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$46 + wire width 64 \fus_src1_i$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$49 + wire width 64 \fus_src1_i$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$52 + wire width 64 \fus_src1_i$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$55 + wire width 64 \fus_src1_i$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$58 + wire width 64 \fus_src1_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$61 + wire width 64 \fus_src1_i$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$84 + wire width 64 \fus_src1_i$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$65 @@ -64749,972 +65312,1027 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$87 + wire width 64 \fus_src2_i$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$89 + wire width 64 \fus_src2_i$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i + wire width 64 \fus_src2_i$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$69 + wire width 64 \fus_src2_i$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$70 + wire width 64 \fus_src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$71 + wire width 64 \fus_src3_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src3_i$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src3_i$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 \fus_src3_i$77 + wire \fus_src3_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire \fus_src3_i$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src3_i$81 + wire width 32 \fus_src3_i$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$85 + wire width 4 \fus_src3_i$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$86 + wire width 64 \fus_src3_i$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src4_i$74 + wire \fus_src4_i$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src4_i$75 + wire width 2 \fus_src4_i$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src4_i$78 + wire width 4 \fus_src4_i$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src4_i$88 + wire width 64 \fus_src4_i$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 \fus_src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src5_i$76 + wire width 2 \fus_src5_i$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src5_i$82 + wire width 4 \fus_src5_i$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 \fus_src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src6_i$83 + wire width 4 \fus_src6_i$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ca_ok$130 + wire \fus_xer_ca_ok$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ca_ok$131 + wire \fus_xer_ca_ok$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ov_ok$134 + wire \fus_xer_ov_ok$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ov_ok$135 + wire \fus_xer_ov_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ov_ok$136 + wire \fus_xer_ov_ok$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_so_ok$139 + wire \fus_xer_so_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_so_ok$140 + wire \fus_xer_so_ok$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_so_ok$141 - attribute \src "libresoc.v:35746.7-35746.15" + wire \fus_xer_so_ok$143 + attribute \src "libresoc.v:36214.7-36214.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \int_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_dest1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \int_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \int_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \int_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 76 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 79 \issue__addr$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 81 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 78 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 77 \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 80 \issue__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 81 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 84 \issue__addr$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 86 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 83 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 82 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 85 \issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" - wire input 67 \issue_i + wire input 72 \issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" - wire input 66 \ivalid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 64 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \msr__ren + wire input 71 \ivalid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 15 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 13 \msr__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire width 32 input 62 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + wire width 32 input 66 \raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_CR_cr_a_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_CR_cr_b_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_CR_cr_c_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_CR_full_cr_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_FAST_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_FAST_fast2_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_INT_ra_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_INT_rb_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_INT_rc_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_SPR_spr1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_XER_xer_so_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_a_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 \rdpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 \rdpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_b_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_CR_cr_b_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_CR_cr_b_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_c_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_CR_cr_c_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_CR_cr_c_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_full_cr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_FAST_fast1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 \rdpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 \rdpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_FAST_fast2_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 \rdpick_FAST_fast2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 \rdpick_FAST_fast2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_INT_ra_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 9 \rdpick_INT_ra_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 9 \rdpick_INT_ra_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_INT_rb_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \rdpick_INT_rb_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \rdpick_INT_rb_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_INT_rc_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 \rdpick_INT_rc_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 \rdpick_INT_rc_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_SPR_spr1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_XER_xer_ca_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 \rdpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 \rdpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_XER_xer_ov_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_XER_xer_so_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 6 \rdpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 7 \spr_spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr$173 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 7 \spr_spr1__addr$175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \spr_spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \spr_spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \spr_spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \spr_spr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \state_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i$172 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 68 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \state_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire input 82 \wb_dcache_en - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \state_data_i$174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 output 73 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \state_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 10 \sv__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 9 \sv__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire input 68 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire input 87 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 11 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 69 \wen$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1028 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1050 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1070 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1090 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1324 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1344 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1391 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1423 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1457 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1473 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1489 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1505 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1541 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1557 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1573 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1589 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1634 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1650 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1666 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1682 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1698 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1742 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1758 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1782 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1802 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$989 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" wire \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1018 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1036 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1058 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1078 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1098 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1316 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1336 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1465 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1481 - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1319$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1339 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1339$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1386 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1386$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1402 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1402$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1418 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1418$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1452 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1452$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1468 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1468$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1484 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1484$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1500 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1500$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1536 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1536$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1552 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1552$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1568 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1568$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1584 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1584$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1626 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1626$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1645 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1645$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1661 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1661$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1677 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1677$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1693 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1693$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1737 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1737$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1753 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1753$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1777 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1777$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1797 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1797$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$981 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$981$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1010 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1010$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1031 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1031$next + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1547 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1547$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1563 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1563$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1579 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1579$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1595 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1595$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1637 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1637$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1656 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1656$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1672 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1672$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1688 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1688$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1704 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1704$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1748 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1748$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1764 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1764$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1788 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1788$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1808 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$1808$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$991 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \wr_pick_dly$991$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1001 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1006 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1007 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1008 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1009 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1022 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1027 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1040 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1045 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1046 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1047 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1048 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1049 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1062 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1067 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1068 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1069 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1082 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1087 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1088 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1089 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1102 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1108 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1126 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1627 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1632 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1633 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$968 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$969 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$970 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$971 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$982 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$987 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$988 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1011 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1016 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1017 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1018 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1019 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1032 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1037 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1050 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1055 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1056 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1057 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1058 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1059 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1072 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1077 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1078 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1079 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1092 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1097 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1098 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1099 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1112 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1118 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1136 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1638 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1643 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1644 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$978 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$979 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$980 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$981 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$992 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$997 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_o_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_CR_cr_a_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 6 \wrpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 \wrpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_CR_full_cr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \wrpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \wrpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_FAST_fast1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 5 \wrpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 5 \wrpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_INT_o_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 10 \wrpick_INT_o_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 10 \wrpick_INT_o_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_SPR_spr1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \wrpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \wrpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_STATE_msr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \wrpick_STATE_msr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \wrpick_STATE_msr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_STATE_nia_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 \wrpick_STATE_nia_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 \wrpick_STATE_nia_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_XER_xer_ca_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 \wrpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 \wrpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_XER_xer_ov_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 4 \wrpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 4 \wrpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_XER_xer_so_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 4 \wrpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 4 \wrpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$168 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_data_i$170 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \xer_data_i$172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen$171 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41534$1507 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \xer_wen$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42103$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$988 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:42103$1506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42105$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$95 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:42105$1508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42106$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [2] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:42106$1509_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42108$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$997 - connect \B \$1002 - connect \Y $and$libresoc.v:41534$1507_Y + connect \A \wr_pick$1007 + connect \B \$1012 + connect \Y $and$libresoc.v:42108$1511_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41535$1508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42109$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$997 + connect \A \wr_pick$1007 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41535$1508_Y + connect \Y $and$libresoc.v:42109$1512_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41537$1510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42111$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$96 - connect \B \fus_cu_busy_o$21 - connect \Y $and$libresoc.v:41537$1510_Y + connect \A \fus_o_ok$98 + connect \B \fus_cu_busy_o$23 + connect \Y $and$libresoc.v:42111$1514_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41538$1511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42112$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65722,43 +66340,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41538$1511_Y + connect \Y $and$libresoc.v:42112$1515_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41540$1513 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42114$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1018 - connect \B \$1023 - connect \Y $and$libresoc.v:41540$1513_Y + connect \A \wr_pick$1028 + connect \B \$1033 + connect \Y $and$libresoc.v:42114$1517_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41541$1514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42115$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1018 + connect \A \wr_pick$1028 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41541$1514_Y + connect \Y $and$libresoc.v:42115$1518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41543$1516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42117$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$99 - connect \B \fus_cu_busy_o$24 - connect \Y $and$libresoc.v:41543$1516_Y + connect \A \fus_o_ok$101 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:42117$1520_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41544$1517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42118$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65766,43 +66384,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41544$1517_Y + connect \Y $and$libresoc.v:42118$1521_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41546$1519 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42120$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1036 - connect \B \$1041 - connect \Y $and$libresoc.v:41546$1519_Y + connect \A \wr_pick$1046 + connect \B \$1051 + connect \Y $and$libresoc.v:42120$1523_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41547$1520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42121$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1036 + connect \A \wr_pick$1046 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41547$1520_Y + connect \Y $and$libresoc.v:42121$1524_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41549$1522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42123$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$102 - connect \B \fus_cu_busy_o$27 - connect \Y $and$libresoc.v:41549$1522_Y + connect \A \fus_o_ok$104 + connect \B \fus_cu_busy_o$29 + connect \Y $and$libresoc.v:42123$1526_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41550$1523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42124$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65810,43 +66428,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41550$1523_Y + connect \Y $and$libresoc.v:42124$1527_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41552$1525 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42126$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1058 - connect \B \$1063 - connect \Y $and$libresoc.v:41552$1525_Y + connect \A \wr_pick$1068 + connect \B \$1073 + connect \Y $and$libresoc.v:42126$1529_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41553$1526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42127$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1058 + connect \A \wr_pick$1068 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41553$1526_Y + connect \Y $and$libresoc.v:42127$1530_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41555$1528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42129$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$105 - connect \B \fus_cu_busy_o$30 - connect \Y $and$libresoc.v:41555$1528_Y + connect \A \fus_o_ok$107 + connect \B \fus_cu_busy_o$32 + connect \Y $and$libresoc.v:42129$1532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41556$1529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42130$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65854,43 +66472,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41556$1529_Y + connect \Y $and$libresoc.v:42130$1533_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41558$1531 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42132$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1078 - connect \B \$1083 - connect \Y $and$libresoc.v:41558$1531_Y + connect \A \wr_pick$1088 + connect \B \$1093 + connect \Y $and$libresoc.v:42132$1535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41559$1532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42133$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1078 + connect \A \wr_pick$1088 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41559$1532_Y + connect \Y $and$libresoc.v:42133$1536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41561$1534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42135$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$108 - connect \B \fus_cu_busy_o$33 - connect \Y $and$libresoc.v:41561$1534_Y + connect \A \fus_o_ok$110 + connect \B \fus_cu_busy_o$35 + connect \Y $and$libresoc.v:42135$1538_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41562$1535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42136$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65898,43 +66516,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41562$1535_Y + connect \Y $and$libresoc.v:42136$1539_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41564$1537 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42138$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1098 - connect \B \$1103 - connect \Y $and$libresoc.v:41564$1537_Y + connect \A \wr_pick$1108 + connect \B \$1113 + connect \Y $and$libresoc.v:42138$1541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41565$1538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42139$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1098 + connect \A \wr_pick$1108 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41565$1538_Y + connect \Y $and$libresoc.v:42139$1542_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41567$1540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42141$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok - connect \B \fus_cu_busy_o$36 - connect \Y $and$libresoc.v:41567$1540_Y + connect \B \fus_cu_busy_o$38 + connect \Y $and$libresoc.v:42141$1544_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41568$1541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42142$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65942,43 +66560,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41568$1541_Y + connect \Y $and$libresoc.v:42142$1545_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41570$1543 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42144$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1117 - connect \B \$1122 - connect \Y $and$libresoc.v:41570$1543_Y + connect \A \wr_pick$1127 + connect \B \$1132 + connect \Y $and$libresoc.v:42144$1547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41571$1544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42145$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1117 + connect \A \wr_pick$1127 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41571$1544_Y + connect \Y $and$libresoc.v:42145$1548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41573$1546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42147$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ea_ok - connect \B \fus_cu_busy_o$36 - connect \Y $and$libresoc.v:41573$1546_Y + connect \B \fus_cu_busy_o$38 + connect \Y $and$libresoc.v:42147$1550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41574$1547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42148$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65986,54 +66604,54 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41574$1547_Y + connect \Y $and$libresoc.v:42148$1551_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41576$1549 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42150$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1135 - connect \B \$1139 - connect \Y $and$libresoc.v:41576$1549_Y + connect \A \wr_pick$1145 + connect \B \$1149 + connect \Y $and$libresoc.v:42150$1553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41577$1550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42151$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1135 + connect \A \wr_pick$1145 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41577$1550_Y + connect \Y $and$libresoc.v:42151$1554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41606$1579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42180$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok - connect \B \fus_cu_busy_o$12 - connect \Y $and$libresoc.v:41606$1579_Y + connect \B \fus_cu_busy_o$14 + connect \Y $and$libresoc.v:42180$1583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41607$1580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42181$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$91 [1] + connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41607$1580_Y + connect \Y $and$libresoc.v:42181$1584_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41608$1581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42182$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66041,32 +66659,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41608$1581_Y + connect \Y $and$libresoc.v:42182$1585_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41610$1583 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42184$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1208 - connect \B \$1212 - connect \Y $and$libresoc.v:41610$1583_Y + connect \A \wr_pick$1219 + connect \B \$1223 + connect \Y $and$libresoc.v:42184$1587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41611$1584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42185$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1208 + connect \A \wr_pick$1219 connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41611$1584_Y + connect \Y $and$libresoc.v:42185$1588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41613$1586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42187$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66074,10 +66692,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41613$1586_Y + connect \Y $and$libresoc.v:42187$1590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41614$1587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42188$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66085,65 +66703,65 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41614$1587_Y + connect \Y $and$libresoc.v:42188$1591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41615$1588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42189$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$91 [2] + connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41615$1588_Y + connect \Y $and$libresoc.v:42189$1592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41616$1589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42190$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$97 [1] + connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41616$1589_Y + connect \Y $and$libresoc.v:42190$1593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41617$1590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42191$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$103 [1] + connect \A \fus_cu_wr__rel_o$105 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41617$1590_Y + connect \Y $and$libresoc.v:42191$1594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41618$1591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42192$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$106 [1] + connect \A \fus_cu_wr__rel_o$108 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41618$1591_Y + connect \Y $and$libresoc.v:42192$1595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41619$1592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42193$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$109 [1] + connect \A \fus_cu_wr__rel_o$111 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41619$1592_Y + connect \Y $and$libresoc.v:42193$1596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41620$1593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42194$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66151,43 +66769,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41620$1593_Y + connect \Y $and$libresoc.v:42194$1597_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41622$1595 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42196$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1236 - connect \B \$1240 - connect \Y $and$libresoc.v:41622$1595_Y + connect \A \wr_pick$1247 + connect \B \$1251 + connect \Y $and$libresoc.v:42196$1599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41623$1596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42197$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1236 + connect \A \wr_pick$1247 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41623$1596_Y + connect \Y $and$libresoc.v:42197$1600_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41627$1600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42201$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$120 - connect \B \fus_cu_busy_o$12 - connect \Y $and$libresoc.v:41627$1600_Y + connect \A \fus_cr_a_ok$122 + connect \B \fus_cu_busy_o$14 + connect \Y $and$libresoc.v:42201$1604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41628$1601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42202$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66195,43 +66813,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41628$1601_Y + connect \Y $and$libresoc.v:42202$1605_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41630$1603 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42204$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1256 - connect \B \$1260 - connect \Y $and$libresoc.v:41630$1603_Y + connect \A \wr_pick$1267 + connect \B \$1271 + connect \Y $and$libresoc.v:42204$1607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41631$1604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42205$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1256 + connect \A \wr_pick$1267 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41631$1604_Y + connect \Y $and$libresoc.v:42205$1608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41635$1608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42209$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$121 - connect \B \fus_cu_busy_o$21 - connect \Y $and$libresoc.v:41635$1608_Y + connect \A \fus_cr_a_ok$123 + connect \B \fus_cu_busy_o$23 + connect \Y $and$libresoc.v:42209$1612_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41636$1609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42210$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66239,43 +66857,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41636$1609_Y + connect \Y $and$libresoc.v:42210$1613_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41638$1611 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42212$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1276 - connect \B \$1280 - connect \Y $and$libresoc.v:41638$1611_Y + connect \A \wr_pick$1287 + connect \B \$1291 + connect \Y $and$libresoc.v:42212$1615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41639$1612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42213$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1276 + connect \A \wr_pick$1287 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41639$1612_Y + connect \Y $and$libresoc.v:42213$1616_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41643$1616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42217$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$122 - connect \B \fus_cu_busy_o$27 - connect \Y $and$libresoc.v:41643$1616_Y + connect \A \fus_cr_a_ok$124 + connect \B \fus_cu_busy_o$29 + connect \Y $and$libresoc.v:42217$1620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41644$1617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42218$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66283,43 +66901,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41644$1617_Y + connect \Y $and$libresoc.v:42218$1621_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41646$1619 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42220$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1296 - connect \B \$1300 - connect \Y $and$libresoc.v:41646$1619_Y + connect \A \wr_pick$1307 + connect \B \$1311 + connect \Y $and$libresoc.v:42220$1623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41647$1620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42221$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1296 + connect \A \wr_pick$1307 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41647$1620_Y + connect \Y $and$libresoc.v:42221$1624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41651$1624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42225$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$123 - connect \B \fus_cu_busy_o$30 - connect \Y $and$libresoc.v:41651$1624_Y + connect \A \fus_cr_a_ok$125 + connect \B \fus_cu_busy_o$32 + connect \Y $and$libresoc.v:42225$1628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41652$1625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42226$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66327,43 +66945,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41652$1625_Y + connect \Y $and$libresoc.v:42226$1629_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41654$1627 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42228$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1316 - connect \B \$1320 - connect \Y $and$libresoc.v:41654$1627_Y + connect \A \wr_pick$1327 + connect \B \$1331 + connect \Y $and$libresoc.v:42228$1631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41655$1628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42229$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1316 + connect \A \wr_pick$1327 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41655$1628_Y + connect \Y $and$libresoc.v:42229$1632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41659$1632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42233$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$124 - connect \B \fus_cu_busy_o$33 - connect \Y $and$libresoc.v:41659$1632_Y + connect \A \fus_cr_a_ok$126 + connect \B \fus_cu_busy_o$35 + connect \Y $and$libresoc.v:42233$1636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41660$1633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42234$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66371,32 +66989,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41660$1633_Y + connect \Y $and$libresoc.v:42234$1637_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41662$1635 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42236$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1336 - connect \B \$1340 - connect \Y $and$libresoc.v:41662$1635_Y + connect \A \wr_pick$1347 + connect \B \$1351 + connect \Y $and$libresoc.v:42236$1639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41663$1636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42237$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1336 + connect \A \wr_pick$1347 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41663$1636_Y + connect \Y $and$libresoc.v:42237$1640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41677$1650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42251$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66404,10 +67022,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41677$1650_Y + connect \Y $and$libresoc.v:42251$1654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41678$1651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42252$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66415,32 +67033,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41678$1651_Y + connect \Y $and$libresoc.v:42252$1655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41679$1652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42253$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$100 [5] + connect \A \fus_cu_wr__rel_o$102 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41679$1652_Y + connect \Y $and$libresoc.v:42253$1656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41680$1653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42254$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$109 [2] + connect \A \fus_cu_wr__rel_o$111 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41680$1653_Y + connect \Y $and$libresoc.v:42254$1657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41681$1654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42255$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66448,43 +67066,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41681$1654_Y + connect \Y $and$libresoc.v:42255$1658_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41683$1656 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42257$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1383 - connect \B \$1387 - connect \Y $and$libresoc.v:41683$1656_Y + connect \A \wr_pick$1394 + connect \B \$1398 + connect \Y $and$libresoc.v:42257$1660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41684$1657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42258$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1383 + connect \A \wr_pick$1394 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41684$1657_Y + connect \Y $and$libresoc.v:42258$1661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41686$1659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42260$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$130 - connect \B \fus_cu_busy_o$24 - connect \Y $and$libresoc.v:41686$1659_Y + connect \A \fus_xer_ca_ok$132 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:42260$1663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41687$1660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42261$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66492,43 +67110,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41687$1660_Y + connect \Y $and$libresoc.v:42261$1664_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41689$1662 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42263$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1399 - connect \B \$1403 - connect \Y $and$libresoc.v:41689$1662_Y + connect \A \wr_pick$1410 + connect \B \$1414 + connect \Y $and$libresoc.v:42263$1666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41690$1663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42264$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1399 + connect \A \wr_pick$1410 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41690$1663_Y + connect \Y $and$libresoc.v:42264$1667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41692$1665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42266$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$131 - connect \B \fus_cu_busy_o$33 - connect \Y $and$libresoc.v:41692$1665_Y + connect \A \fus_xer_ca_ok$133 + connect \B \fus_cu_busy_o$35 + connect \Y $and$libresoc.v:42266$1669_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41693$1666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42267$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66536,32 +67154,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41693$1666_Y + connect \Y $and$libresoc.v:42267$1670_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41695$1668 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42269$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1415 - connect \B \$1419 - connect \Y $and$libresoc.v:41695$1668_Y + connect \A \wr_pick$1426 + connect \B \$1430 + connect \Y $and$libresoc.v:42269$1672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41696$1669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42270$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1415 + connect \A \wr_pick$1426 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41696$1669_Y + connect \Y $and$libresoc.v:42270$1673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41703$1677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42277$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66569,10 +67187,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41703$1677_Y + connect \Y $and$libresoc.v:42277$1681_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41704$1678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42278$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66580,43 +67198,43 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41704$1678_Y + connect \Y $and$libresoc.v:42278$1682_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41705$1679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42279$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$100 [4] + connect \A \fus_cu_wr__rel_o$102 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41705$1679_Y + connect \Y $and$libresoc.v:42279$1683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41706$1680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42280$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$103 [2] + connect \A \fus_cu_wr__rel_o$105 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41706$1680_Y + connect \Y $and$libresoc.v:42280$1684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41707$1681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42281$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$106 [2] + connect \A \fus_cu_wr__rel_o$108 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41707$1681_Y + connect \Y $and$libresoc.v:42281$1685_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41708$1682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42282$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66624,43 +67242,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41708$1682_Y + connect \Y $and$libresoc.v:42282$1686_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41710$1684 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42284$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1449 - connect \B \$1453 - connect \Y $and$libresoc.v:41710$1684_Y + connect \A \wr_pick$1460 + connect \B \$1464 + connect \Y $and$libresoc.v:42284$1688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41711$1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42285$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1449 + connect \A \wr_pick$1460 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41711$1685_Y + connect \Y $and$libresoc.v:42285$1689_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41713$1687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42287$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$134 - connect \B \fus_cu_busy_o$24 - connect \Y $and$libresoc.v:41713$1687_Y + connect \A \fus_xer_ov_ok$136 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:42287$1691_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41714$1688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42288$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66668,43 +67286,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41714$1688_Y + connect \Y $and$libresoc.v:42288$1692_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41716$1690 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42290$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1465 - connect \B \$1469 - connect \Y $and$libresoc.v:41716$1690_Y + connect \A \wr_pick$1476 + connect \B \$1480 + connect \Y $and$libresoc.v:42290$1694_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41717$1691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42291$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1465 + connect \A \wr_pick$1476 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41717$1691_Y + connect \Y $and$libresoc.v:42291$1695_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41719$1693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42293$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$135 - connect \B \fus_cu_busy_o$27 - connect \Y $and$libresoc.v:41719$1693_Y + connect \A \fus_xer_ov_ok$137 + connect \B \fus_cu_busy_o$29 + connect \Y $and$libresoc.v:42293$1697_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41720$1694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42294$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66712,43 +67330,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41720$1694_Y + connect \Y $and$libresoc.v:42294$1698_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41722$1696 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42296$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1481 - connect \B \$1485 - connect \Y $and$libresoc.v:41722$1696_Y + connect \A \wr_pick$1492 + connect \B \$1496 + connect \Y $and$libresoc.v:42296$1700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41723$1697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42297$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1481 + connect \A \wr_pick$1492 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41723$1697_Y + connect \Y $and$libresoc.v:42297$1701_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41725$1699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42299$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$136 - connect \B \fus_cu_busy_o$30 - connect \Y $and$libresoc.v:41725$1699_Y + connect \A \fus_xer_ov_ok$138 + connect \B \fus_cu_busy_o$32 + connect \Y $and$libresoc.v:42299$1703_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41726$1700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42300$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66756,32 +67374,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41726$1700_Y + connect \Y $and$libresoc.v:42300$1704_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41728$1702 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42302$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1497 - connect \B \$1501 - connect \Y $and$libresoc.v:41728$1702_Y + connect \A \wr_pick$1508 + connect \B \$1512 + connect \Y $and$libresoc.v:42302$1706_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41729$1703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42303$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1497 + connect \A \wr_pick$1508 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41729$1703_Y + connect \Y $and$libresoc.v:42303$1707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41737$1711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42311$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66789,10 +67407,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41737$1711_Y + connect \Y $and$libresoc.v:42311$1715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41738$1712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42312$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66800,43 +67418,43 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41738$1712_Y + connect \Y $and$libresoc.v:42312$1716_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41739$1713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42313$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$100 [3] + connect \A \fus_cu_wr__rel_o$102 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41739$1713_Y + connect \Y $and$libresoc.v:42313$1717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41740$1714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42314$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$103 [3] + connect \A \fus_cu_wr__rel_o$105 [3] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41740$1714_Y + connect \Y $and$libresoc.v:42314$1718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41741$1715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42315$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$106 [3] + connect \A \fus_cu_wr__rel_o$108 [3] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41741$1715_Y + connect \Y $and$libresoc.v:42315$1719_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41742$1716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42316$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66844,43 +67462,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41742$1716_Y + connect \Y $and$libresoc.v:42316$1720_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41744$1718 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42318$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1533 - connect \B \$1537 - connect \Y $and$libresoc.v:41744$1718_Y + connect \A \wr_pick$1544 + connect \B \$1548 + connect \Y $and$libresoc.v:42318$1722_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41745$1719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42319$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1533 + connect \A \wr_pick$1544 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41745$1719_Y + connect \Y $and$libresoc.v:42319$1723_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41747$1721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42321$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$139 - connect \B \fus_cu_busy_o$24 - connect \Y $and$libresoc.v:41747$1721_Y + connect \A \fus_xer_so_ok$141 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:42321$1725_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41748$1722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42322$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66888,43 +67506,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41748$1722_Y + connect \Y $and$libresoc.v:42322$1726_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41750$1724 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42324$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1549 - connect \B \$1553 - connect \Y $and$libresoc.v:41750$1724_Y + connect \A \wr_pick$1560 + connect \B \$1564 + connect \Y $and$libresoc.v:42324$1728_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41751$1725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42325$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1549 + connect \A \wr_pick$1560 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41751$1725_Y + connect \Y $and$libresoc.v:42325$1729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41753$1727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42327$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$140 - connect \B \fus_cu_busy_o$27 - connect \Y $and$libresoc.v:41753$1727_Y + connect \A \fus_xer_so_ok$142 + connect \B \fus_cu_busy_o$29 + connect \Y $and$libresoc.v:42327$1731_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41754$1728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42328$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66932,43 +67550,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41754$1728_Y + connect \Y $and$libresoc.v:42328$1732_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41756$1730 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42330$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1565 - connect \B \$1569 - connect \Y $and$libresoc.v:41756$1730_Y + connect \A \wr_pick$1576 + connect \B \$1580 + connect \Y $and$libresoc.v:42330$1734_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41757$1731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42331$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1565 + connect \A \wr_pick$1576 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41757$1731_Y + connect \Y $and$libresoc.v:42331$1735_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41759$1733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42333$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$141 - connect \B \fus_cu_busy_o$30 - connect \Y $and$libresoc.v:41759$1733_Y + connect \A \fus_xer_so_ok$143 + connect \B \fus_cu_busy_o$32 + connect \Y $and$libresoc.v:42333$1737_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41760$1734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42334$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66976,98 +67594,98 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41760$1734_Y + connect \Y $and$libresoc.v:42334$1738_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41762$1736 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42336$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1581 - connect \B \$1585 - connect \Y $and$libresoc.v:41762$1736_Y + connect \A \wr_pick$1592 + connect \B \$1596 + connect \Y $and$libresoc.v:42336$1740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41763$1737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42337$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1581 + connect \A \wr_pick$1592 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41763$1737_Y + connect \Y $and$libresoc.v:42337$1741_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41773$1749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42347$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast1_ok - connect \B \fus_cu_busy_o$15 - connect \Y $and$libresoc.v:41773$1749_Y + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:42347$1753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41774$1750 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42348$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$146 [0] + connect \A \fus_cu_wr__rel_o$148 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41774$1750_Y + connect \Y $and$libresoc.v:42348$1754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41775$1751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42349$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$94 [1] + connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41775$1751_Y + connect \Y $and$libresoc.v:42349$1755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41776$1752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42350$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$100 [2] + connect \A \fus_cu_wr__rel_o$102 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41776$1752_Y + connect \Y $and$libresoc.v:42350$1756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41777$1753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42351$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$146 [1] + connect \A \fus_cu_wr__rel_o$148 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41777$1753_Y + connect \Y $and$libresoc.v:42351$1757_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41778$1754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42352$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$94 [2] + connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41778$1754_Y + connect \Y $and$libresoc.v:42352$1758_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41779$1755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42353$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67075,43 +67693,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41779$1755_Y + connect \Y $and$libresoc.v:42353$1759_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41781$1757 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42355$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1623 - connect \B \$1628 - connect \Y $and$libresoc.v:41781$1757_Y + connect \A \wr_pick$1634 + connect \B \$1639 + connect \Y $and$libresoc.v:42355$1761_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41782$1758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42356$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1623 + connect \A \wr_pick$1634 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41782$1758_Y + connect \Y $and$libresoc.v:42356$1762_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41784$1760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42358$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$148 - connect \B \fus_cu_busy_o$18 - connect \Y $and$libresoc.v:41784$1760_Y + connect \A \fus_fast1_ok$150 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:42358$1764_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41785$1761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42359$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67119,43 +67737,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41785$1761_Y + connect \Y $and$libresoc.v:42359$1765_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41787$1763 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42361$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1642 - connect \B \$1646 - connect \Y $and$libresoc.v:41787$1763_Y + connect \A \wr_pick$1653 + connect \B \$1657 + connect \Y $and$libresoc.v:42361$1767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41788$1764 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42362$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1642 + connect \A \wr_pick$1653 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41788$1764_Y + connect \Y $and$libresoc.v:42362$1768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41790$1766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42364$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$149 - connect \B \fus_cu_busy_o$24 - connect \Y $and$libresoc.v:41790$1766_Y + connect \A \fus_fast1_ok$151 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:42364$1770_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41791$1767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42365$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67163,43 +67781,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41791$1767_Y + connect \Y $and$libresoc.v:42365$1771_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41793$1769 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42367$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1658 - connect \B \$1662 - connect \Y $and$libresoc.v:41793$1769_Y + connect \A \wr_pick$1669 + connect \B \$1673 + connect \Y $and$libresoc.v:42367$1773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41794$1770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42368$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1658 + connect \A \wr_pick$1669 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41794$1770_Y + connect \Y $and$libresoc.v:42368$1774_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41796$1772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42370$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast2_ok - connect \B \fus_cu_busy_o$15 - connect \Y $and$libresoc.v:41796$1772_Y + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:42370$1776_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41797$1773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42371$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67207,43 +67825,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41797$1773_Y + connect \Y $and$libresoc.v:42371$1777_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41799$1775 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42373$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1674 - connect \B \$1678 - connect \Y $and$libresoc.v:41799$1775_Y + connect \A \wr_pick$1685 + connect \B \$1689 + connect \Y $and$libresoc.v:42373$1779_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41800$1776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42374$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1674 + connect \A \wr_pick$1685 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41800$1776_Y + connect \Y $and$libresoc.v:42374$1780_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41802$1778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42376$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok$150 - connect \B \fus_cu_busy_o$18 - connect \Y $and$libresoc.v:41802$1778_Y + connect \A \fus_fast2_ok$152 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:42376$1782_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41803$1779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42377$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67251,65 +67869,65 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41803$1779_Y + connect \Y $and$libresoc.v:42377$1783_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41805$1781 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42379$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1690 - connect \B \$1694 - connect \Y $and$libresoc.v:41805$1781_Y + connect \A \wr_pick$1701 + connect \B \$1705 + connect \Y $and$libresoc.v:42379$1785_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41806$1782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42380$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1690 + connect \A \wr_pick$1701 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41806$1782_Y + connect \Y $and$libresoc.v:42380$1786_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41820$1796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42394$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_nia_ok - connect \B \fus_cu_busy_o$15 - connect \Y $and$libresoc.v:41820$1796_Y + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:42394$1800_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41821$1797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42395$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$146 [2] + connect \A \fus_cu_wr__rel_o$148 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41821$1797_Y + connect \Y $and$libresoc.v:42395$1801_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41822$1798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42396$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$94 [3] + connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41822$1798_Y + connect \Y $and$libresoc.v:42396$1802_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41823$1799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42397$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67317,43 +67935,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:41823$1799_Y + connect \Y $and$libresoc.v:42397$1803_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41825$1801 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42399$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1734 - connect \B \$1738 - connect \Y $and$libresoc.v:41825$1801_Y + connect \A \wr_pick$1745 + connect \B \$1749 + connect \Y $and$libresoc.v:42399$1805_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41826$1802 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42400$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1734 + connect \A \wr_pick$1745 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:41826$1802_Y + connect \Y $and$libresoc.v:42400$1806_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41828$1804 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42402$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_nia_ok$156 - connect \B \fus_cu_busy_o$18 - connect \Y $and$libresoc.v:41828$1804_Y + connect \A \fus_nia_ok$158 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:42402$1808_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41829$1805 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42403$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67361,65 +67979,54 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:41829$1805_Y + connect \Y $and$libresoc.v:42403$1809_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41831$1807 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42405$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1750 - connect \B \$1754 - connect \Y $and$libresoc.v:41831$1807_Y + connect \A \wr_pick$1761 + connect \B \$1765 + connect \Y $and$libresoc.v:42405$1811_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41832$1808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 2'10 - connect \Y $and$libresoc.v:41832$1808_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41833$1809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42406$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1750 + connect \A \wr_pick$1761 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:41833$1809_Y + connect \Y $and$libresoc.v:42406$1812_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41839$1816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42411$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_msr_ok - connect \B \fus_cu_busy_o$18 - connect \Y $and$libresoc.v:41839$1816_Y + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:42411$1818_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41840$1817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42412$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$94 [4] + connect \A \fus_cu_wr__rel_o$96 [4] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41840$1817_Y + connect \Y $and$libresoc.v:42412$1819_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41841$1818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42413$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67427,54 +68034,54 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:41841$1818_Y + connect \Y $and$libresoc.v:42413$1820_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41843$1820 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42415$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1774 - connect \B \$1778 - connect \Y $and$libresoc.v:41843$1820_Y + connect \A \wr_pick$1785 + connect \B \$1789 + connect \Y $and$libresoc.v:42415$1822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41844$1821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42416$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1774 + connect \A \wr_pick$1785 connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:41844$1821_Y + connect \Y $and$libresoc.v:42416$1823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41847$1825 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42419$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_spr1_ok - connect \B \fus_cu_busy_o$24 - connect \Y $and$libresoc.v:41847$1825_Y + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:42419$1827_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:41848$1826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42420$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$100 [1] + connect \A \fus_cu_wr__rel_o$102 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41848$1826_Y + connect \Y $and$libresoc.v:42420$1828_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41849$1827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42421$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67482,131 +68089,142 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:41849$1827_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41851$1829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 7'1000000 - connect \Y $and$libresoc.v:41851$1829_Y + connect \Y $and$libresoc.v:42421$1829_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41852$1830 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42423$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1794 - connect \B \$1798 - connect \Y $and$libresoc.v:41852$1830_Y + connect \A \wr_pick$1805 + connect \B \$1809 + connect \Y $and$libresoc.v:42423$1831_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41853$1831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42424$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1794 + connect \A \wr_pick$1805 connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:41853$1831_Y + connect \Y $and$libresoc.v:42424$1832_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42426$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 14 + connect \A \core_core_fn_unit + connect \B 2'10 + connect \Y $and$libresoc.v:42426$1834_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42428$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 14 + connect \A \core_core_fn_unit + connect \B 7'1000000 + connect \Y $and$libresoc.v:42428$1836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41856$1834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42430$1838 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 6 - parameter \Y_WIDTH 12 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 6'100000 - connect \Y $and$libresoc.v:41856$1834_Y + connect \Y $and$libresoc.v:42430$1838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41858$1836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42432$1840 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 8 - parameter \Y_WIDTH 12 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 8'10000000 - connect \Y $and$libresoc.v:41858$1836_Y + connect \Y $and$libresoc.v:42432$1840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41860$1838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42434$1842 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 5 - parameter \Y_WIDTH 12 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 5'10000 - connect \Y $and$libresoc.v:41860$1838_Y + connect \Y $and$libresoc.v:42434$1842_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41862$1840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42436$1844 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 11 - parameter \Y_WIDTH 12 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 11'10000000000 - connect \Y $and$libresoc.v:41862$1840_Y + connect \Y $and$libresoc.v:42436$1844_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41864$1842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42438$1846 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 10 - parameter \Y_WIDTH 12 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 10'1000000000 - connect \Y $and$libresoc.v:41864$1842_Y + connect \Y $and$libresoc.v:42438$1846_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41866$1844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42440$1848 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 9 - parameter \Y_WIDTH 12 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 9'100000000 - connect \Y $and$libresoc.v:41866$1844_Y + connect \Y $and$libresoc.v:42440$1848_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41868$1846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42442$1850 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 4 - parameter \Y_WIDTH 12 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 4'1000 - connect \Y $and$libresoc.v:41868$1846_Y + connect \Y $and$libresoc.v:42442$1850_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:41870$1848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42444$1852 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 3 - parameter \Y_WIDTH 12 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 3'100 - connect \Y $and$libresoc.v:41870$1848_Y + connect \Y $and$libresoc.v:42444$1852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41875$1853 + cell $and $and$libresoc.v:42449$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67614,10 +68232,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41875$1853_Y + connect \Y $and$libresoc.v:42449$1857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41876$1854 + cell $and $and$libresoc.v:42450$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67625,10 +68243,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41876$1854_Y + connect \Y $and$libresoc.v:42450$1858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41879$1857 + cell $and $and$libresoc.v:42453$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67636,10 +68254,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41879$1857_Y + connect \Y $and$libresoc.v:42453$1861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:41882$1860 + cell $and $and$libresoc.v:42456$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67647,10 +68265,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:41882$1860_Y + connect \Y $and$libresoc.v:42456$1864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41889$1867 + cell $and $and$libresoc.v:42463$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67658,10 +68276,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41889$1867_Y + connect \Y $and$libresoc.v:42463$1871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41890$1868 + cell $and $and$libresoc.v:42464$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67669,10 +68287,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41890$1868_Y + connect \Y $and$libresoc.v:42464$1872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41893$1871 + cell $and $and$libresoc.v:42467$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67680,10 +68298,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41893$1871_Y + connect \Y $and$libresoc.v:42467$1875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41896$1874 + cell $and $and$libresoc.v:42470$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67691,10 +68309,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41896$1874_Y + connect \Y $and$libresoc.v:42470$1878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41897$1875 + cell $and $and$libresoc.v:42471$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67702,10 +68320,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41897$1875_Y + connect \Y $and$libresoc.v:42471$1879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41900$1878 + cell $and $and$libresoc.v:42474$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67713,10 +68331,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41900$1878_Y + connect \Y $and$libresoc.v:42474$1882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:41902$1880 + cell $and $and$libresoc.v:42476$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67724,10 +68342,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41902$1880_Y + connect \Y $and$libresoc.v:42476$1884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:41903$1881 + cell $and $and$libresoc.v:42477$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67735,10 +68353,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:41903$1881_Y + connect \Y $and$libresoc.v:42477$1885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:41907$1885 + cell $and $and$libresoc.v:42481$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67746,10 +68364,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:41907$1885_Y + connect \Y $and$libresoc.v:42481$1889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41911$1889 + cell $and $and$libresoc.v:42485$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67757,10 +68375,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41911$1889_Y + connect \Y $and$libresoc.v:42485$1893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41912$1890 + cell $and $and$libresoc.v:42486$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67768,10 +68386,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41912$1890_Y + connect \Y $and$libresoc.v:42486$1894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41915$1893 + cell $and $and$libresoc.v:42489$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67779,10 +68397,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41915$1893_Y + connect \Y $and$libresoc.v:42489$1897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41918$1896 + cell $and $and$libresoc.v:42492$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67790,10 +68408,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41918$1896_Y + connect \Y $and$libresoc.v:42492$1900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41919$1897 + cell $and $and$libresoc.v:42493$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67801,10 +68419,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41919$1897_Y + connect \Y $and$libresoc.v:42493$1901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41922$1900 + cell $and $and$libresoc.v:42496$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67812,10 +68430,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41922$1900_Y + connect \Y $and$libresoc.v:42496$1904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41925$1903 + cell $and $and$libresoc.v:42499$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67823,10 +68441,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41925$1903_Y + connect \Y $and$libresoc.v:42499$1907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41926$1904 + cell $and $and$libresoc.v:42500$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67834,10 +68452,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41926$1904_Y + connect \Y $and$libresoc.v:42500$1908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41929$1907 + cell $and $and$libresoc.v:42503$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67845,10 +68463,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41929$1907_Y + connect \Y $and$libresoc.v:42503$1911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:41932$1910 + cell $and $and$libresoc.v:42506$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67856,10 +68474,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:41932$1910_Y + connect \Y $and$libresoc.v:42506$1914_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41937$1915 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42511$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67867,32 +68485,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41937$1915_Y + connect \Y $and$libresoc.v:42511$1919_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41938$1916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42512$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$345 + connect \A \$352 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41938$1916_Y + connect \Y $and$libresoc.v:42512$1920_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41940$1918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42514$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$347 - connect \B \$349 - connect \Y $and$libresoc.v:41940$1918_Y + connect \A \$354 + connect \B \$356 + connect \Y $and$libresoc.v:42514$1922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41941$1919 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42515$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67900,43 +68518,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [0] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41941$1919_Y + connect \Y $and$libresoc.v:42515$1923_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41943$1921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42517$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$38 [0] + connect \A \fus_cu_rd__rel_o$40 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41943$1921_Y + connect \Y $and$libresoc.v:42517$1925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41944$1922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42518$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$357 + connect \A \$364 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41944$1922_Y + connect \Y $and$libresoc.v:42518$1926_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41946$1924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42520$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $and$libresoc.v:41946$1924_Y + connect \A \$366 + connect \B \$368 + connect \Y $and$libresoc.v:42520$1928_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41947$1925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42521$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67944,43 +68562,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [1] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41947$1925_Y + connect \Y $and$libresoc.v:42521$1929_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41949$1927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42523$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$41 [0] + connect \A \fus_cu_rd__rel_o$43 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41949$1927_Y + connect \Y $and$libresoc.v:42523$1931_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41950$1928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42524$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$369 + connect \A \$376 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41950$1928_Y + connect \Y $and$libresoc.v:42524$1932_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41952$1930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42526$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$371 - connect \B \$373 - connect \Y $and$libresoc.v:41952$1930_Y + connect \A \$378 + connect \B \$380 + connect \Y $and$libresoc.v:42526$1934_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41953$1931 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42527$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67988,43 +68606,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [2] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41953$1931_Y + connect \Y $and$libresoc.v:42527$1935_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41955$1933 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42529$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$44 [0] + connect \A \fus_cu_rd__rel_o$46 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41955$1933_Y + connect \Y $and$libresoc.v:42529$1937_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41956$1934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42530$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$381 + connect \A \$388 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41956$1934_Y + connect \Y $and$libresoc.v:42530$1938_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41958$1936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42532$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$383 - connect \B \$385 - connect \Y $and$libresoc.v:41958$1936_Y + connect \A \$390 + connect \B \$392 + connect \Y $and$libresoc.v:42532$1940_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41959$1937 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42533$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68032,43 +68650,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [3] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41959$1937_Y + connect \Y $and$libresoc.v:42533$1941_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41961$1939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42535$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$47 [0] + connect \A \fus_cu_rd__rel_o$49 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41961$1939_Y + connect \Y $and$libresoc.v:42535$1943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41962$1940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42536$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$393 + connect \A \$400 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41962$1940_Y + connect \Y $and$libresoc.v:42536$1944_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41964$1942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42538$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$395 - connect \B \$397 - connect \Y $and$libresoc.v:41964$1942_Y + connect \A \$402 + connect \B \$404 + connect \Y $and$libresoc.v:42538$1946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41965$1943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42539$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68076,43 +68694,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [4] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41965$1943_Y + connect \Y $and$libresoc.v:42539$1947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41967$1945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42541$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$50 [0] + connect \A \fus_cu_rd__rel_o$52 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41967$1945_Y + connect \Y $and$libresoc.v:42541$1949_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41968$1946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42542$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$405 + connect \A \$412 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41968$1946_Y + connect \Y $and$libresoc.v:42542$1950_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41970$1948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42544$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$407 - connect \B \$409 - connect \Y $and$libresoc.v:41970$1948_Y + connect \A \$414 + connect \B \$416 + connect \Y $and$libresoc.v:42544$1952_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41971$1949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42545$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68120,43 +68738,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [5] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41971$1949_Y + connect \Y $and$libresoc.v:42545$1953_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41973$1951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42547$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$53 [0] + connect \A \fus_cu_rd__rel_o$55 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41973$1951_Y + connect \Y $and$libresoc.v:42547$1955_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41974$1952 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42548$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$417 + connect \A \$424 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41974$1952_Y + connect \Y $and$libresoc.v:42548$1956_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41976$1954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42550$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$419 - connect \B \$421 - connect \Y $and$libresoc.v:41976$1954_Y + connect \A \$426 + connect \B \$428 + connect \Y $and$libresoc.v:42550$1958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41977$1955 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42551$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68164,43 +68782,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [6] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41977$1955_Y + connect \Y $and$libresoc.v:42551$1959_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41979$1957 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42553$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$56 [0] + connect \A \fus_cu_rd__rel_o$58 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41979$1957_Y + connect \Y $and$libresoc.v:42553$1961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41980$1958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42554$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$429 + connect \A \$436 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41980$1958_Y + connect \Y $and$libresoc.v:42554$1962_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41982$1960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42556$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$431 - connect \B \$433 - connect \Y $and$libresoc.v:41982$1960_Y + connect \A \$438 + connect \B \$440 + connect \Y $and$libresoc.v:42556$1964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41983$1961 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42557$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68208,43 +68826,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [7] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41983$1961_Y + connect \Y $and$libresoc.v:42557$1965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41985$1963 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42559$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$59 [0] + connect \A \fus_cu_rd__rel_o$61 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:41985$1963_Y + connect \Y $and$libresoc.v:42559$1967_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:41986$1964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42560$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$441 + connect \A \$448 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41986$1964_Y + connect \Y $and$libresoc.v:42560$1968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:41988$1966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42562$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$443 - connect \B \$445 - connect \Y $and$libresoc.v:41988$1966_Y + connect \A \$450 + connect \B \$452 + connect \Y $and$libresoc.v:42562$1970_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:41989$1967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42563$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68252,10 +68870,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [8] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41989$1967_Y + connect \Y $and$libresoc.v:42563$1971_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42000$1978 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42574$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68263,32 +68881,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42000$1978_Y + connect \Y $and$libresoc.v:42574$1982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42001$1979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42575$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$471 + connect \A \$479 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42001$1979_Y + connect \Y $and$libresoc.v:42575$1983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42003$1981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42577$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$473 - connect \B \$475 - connect \Y $and$libresoc.v:42003$1981_Y + connect \A \$481 + connect \B \$483 + connect \Y $and$libresoc.v:42577$1985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42004$1982 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42578$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68296,43 +68914,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [0] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42004$1982_Y + connect \Y $and$libresoc.v:42578$1986_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42006$1984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42580$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$38 [1] + connect \A \fus_cu_rd__rel_o$40 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42006$1984_Y + connect \Y $and$libresoc.v:42580$1988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42007$1985 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42581$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$483 + connect \A \$491 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42007$1985_Y + connect \Y $and$libresoc.v:42581$1989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42009$1987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42583$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$485 - connect \B \$487 - connect \Y $and$libresoc.v:42009$1987_Y + connect \A \$493 + connect \B \$495 + connect \Y $and$libresoc.v:42583$1991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42010$1988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42584$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68340,43 +68958,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [1] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42010$1988_Y + connect \Y $and$libresoc.v:42584$1992_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42012$1990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42586$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$41 [1] + connect \A \fus_cu_rd__rel_o$43 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42012$1990_Y + connect \Y $and$libresoc.v:42586$1994_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42013$1991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42587$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$495 + connect \A \$503 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42013$1991_Y + connect \Y $and$libresoc.v:42587$1995_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42015$1993 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42589$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$497 - connect \B \$499 - connect \Y $and$libresoc.v:42015$1993_Y + connect \A \$505 + connect \B \$507 + connect \Y $and$libresoc.v:42589$1997_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42016$1994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42590$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68384,43 +69002,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [2] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42016$1994_Y + connect \Y $and$libresoc.v:42590$1998_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42018$1996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42592$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$44 [1] + connect \A \fus_cu_rd__rel_o$46 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42018$1996_Y + connect \Y $and$libresoc.v:42592$2000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42019$1997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42593$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$507 + connect \A \$515 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42019$1997_Y + connect \Y $and$libresoc.v:42593$2001_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42021$1999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42595$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$509 - connect \B \$511 - connect \Y $and$libresoc.v:42021$1999_Y + connect \A \$517 + connect \B \$519 + connect \Y $and$libresoc.v:42595$2003_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42022$2000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42596$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68428,43 +69046,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [3] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42022$2000_Y + connect \Y $and$libresoc.v:42596$2004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42024$2002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42598$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$50 [1] + connect \A \fus_cu_rd__rel_o$52 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42024$2002_Y + connect \Y $and$libresoc.v:42598$2006_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42025$2003 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42599$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$519 + connect \A \$527 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42025$2003_Y + connect \Y $and$libresoc.v:42599$2007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42027$2005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42601$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$521 - connect \B \$523 - connect \Y $and$libresoc.v:42027$2005_Y + connect \A \$529 + connect \B \$531 + connect \Y $and$libresoc.v:42601$2009_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42028$2006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42602$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68472,43 +69090,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [4] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42028$2006_Y + connect \Y $and$libresoc.v:42602$2010_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42030$2008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42604$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$53 [1] + connect \A \fus_cu_rd__rel_o$55 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42030$2008_Y + connect \Y $and$libresoc.v:42604$2012_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42031$2009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42605$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$531 + connect \A \$539 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42031$2009_Y + connect \Y $and$libresoc.v:42605$2013_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42033$2011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42607$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$533 - connect \B \$535 - connect \Y $and$libresoc.v:42033$2011_Y + connect \A \$541 + connect \B \$543 + connect \Y $and$libresoc.v:42607$2015_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42034$2012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42608$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68516,43 +69134,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [5] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42034$2012_Y + connect \Y $and$libresoc.v:42608$2016_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42036$2014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42610$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$56 [1] + connect \A \fus_cu_rd__rel_o$58 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42036$2014_Y + connect \Y $and$libresoc.v:42610$2018_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42037$2015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42611$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$543 + connect \A \$551 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42037$2015_Y + connect \Y $and$libresoc.v:42611$2019_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42039$2017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42613$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$545 - connect \B \$547 - connect \Y $and$libresoc.v:42039$2017_Y + connect \A \$553 + connect \B \$555 + connect \Y $and$libresoc.v:42613$2021_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42040$2018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42614$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68560,43 +69178,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [6] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42040$2018_Y + connect \Y $and$libresoc.v:42614$2022_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42042$2020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42616$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$59 [1] + connect \A \fus_cu_rd__rel_o$61 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42042$2020_Y + connect \Y $and$libresoc.v:42616$2024_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42043$2021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42617$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$555 + connect \A \$563 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42043$2021_Y + connect \Y $and$libresoc.v:42617$2025_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42045$2023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42619$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$557 - connect \B \$559 - connect \Y $and$libresoc.v:42045$2023_Y + connect \A \$565 + connect \B \$567 + connect \Y $and$libresoc.v:42619$2027_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42046$2024 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42620$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68604,43 +69222,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [7] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42046$2024_Y + connect \Y $and$libresoc.v:42620$2028_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42056$2034 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42630$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$56 [2] + connect \A \fus_cu_rd__rel_o$58 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42056$2034_Y + connect \Y $and$libresoc.v:42630$2038_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42057$2035 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42631$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$583 + connect \A \$592 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42057$2035_Y + connect \Y $and$libresoc.v:42631$2039_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42059$2037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42633$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$585 - connect \B \$587 - connect \Y $and$libresoc.v:42059$2037_Y + connect \A \$594 + connect \B \$596 + connect \Y $and$libresoc.v:42633$2041_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42060$2038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42634$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68648,43 +69266,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [0] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42060$2038_Y + connect \Y $and$libresoc.v:42634$2042_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42062$2040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42636$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$59 [2] + connect \A \fus_cu_rd__rel_o$61 [2] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42062$2040_Y + connect \Y $and$libresoc.v:42636$2044_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42063$2041 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42637$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$595 + connect \A \$604 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42063$2041_Y + connect \Y $and$libresoc.v:42637$2045_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42065$2043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42639$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$597 - connect \B \$599 - connect \Y $and$libresoc.v:42065$2043_Y + connect \A \$606 + connect \B \$608 + connect \Y $and$libresoc.v:42639$2047_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42066$2044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42640$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68692,10 +69310,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [1] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42066$2044_Y + connect \Y $and$libresoc.v:42640$2048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42070$2048 + cell $and $and$libresoc.v:42644$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68703,10 +69321,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42070$2048_Y + connect \Y $and$libresoc.v:42644$2052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42071$2049 + cell $and $and$libresoc.v:42645$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68714,10 +69332,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42071$2049_Y + connect \Y $and$libresoc.v:42645$2053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42074$2052 + cell $and $and$libresoc.v:42648$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68725,10 +69343,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42074$2052_Y + connect \Y $and$libresoc.v:42648$2056_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42076$2054 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42650$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68736,32 +69354,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42076$2054_Y + connect \Y $and$libresoc.v:42650$2058_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42077$2055 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42651$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$623 + connect \A \$633 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42077$2055_Y + connect \Y $and$libresoc.v:42651$2059_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42079$2057 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42653$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$625 - connect \B \$627 - connect \Y $and$libresoc.v:42079$2057_Y + connect \A \$635 + connect \B \$637 + connect \Y $and$libresoc.v:42653$2061_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42080$2058 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42654$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68769,43 +69387,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42080$2058_Y + connect \Y $and$libresoc.v:42654$2062_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42082$2060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42656$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$44 [2] + connect \A \fus_cu_rd__rel_o$46 [2] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42082$2060_Y + connect \Y $and$libresoc.v:42656$2064_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42083$2061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42657$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$635 + connect \A \$645 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42083$2061_Y + connect \Y $and$libresoc.v:42657$2065_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42085$2063 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42659$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$637 - connect \B \$639 - connect \Y $and$libresoc.v:42085$2063_Y + connect \A \$647 + connect \B \$649 + connect \Y $and$libresoc.v:42659$2067_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42086$2064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42660$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68813,43 +69431,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42086$2064_Y + connect \Y $and$libresoc.v:42660$2068_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42088$2066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42662$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$47 [3] + connect \A \fus_cu_rd__rel_o$49 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42088$2066_Y + connect \Y $and$libresoc.v:42662$2070_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42089$2067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42663$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$647 + connect \A \$657 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42089$2067_Y + connect \Y $and$libresoc.v:42663$2071_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42091$2069 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42665$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$649 - connect \B \$651 - connect \Y $and$libresoc.v:42091$2069_Y + connect \A \$659 + connect \B \$661 + connect \Y $and$libresoc.v:42665$2073_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42092$2070 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42666$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68857,43 +69475,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42092$2070_Y + connect \Y $and$libresoc.v:42666$2074_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42094$2072 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42668$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$50 [2] + connect \A \fus_cu_rd__rel_o$52 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42094$2072_Y + connect \Y $and$libresoc.v:42668$2076_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42095$2073 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42669$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$659 + connect \A \$669 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42095$2073_Y + connect \Y $and$libresoc.v:42669$2077_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42097$2075 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42671$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$661 - connect \B \$663 - connect \Y $and$libresoc.v:42097$2075_Y + connect \A \$671 + connect \B \$673 + connect \Y $and$libresoc.v:42671$2079_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42098$2076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42672$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68901,43 +69519,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42098$2076_Y + connect \Y $and$libresoc.v:42672$2080_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42100$2078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42674$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$53 [2] + connect \A \fus_cu_rd__rel_o$55 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42100$2078_Y + connect \Y $and$libresoc.v:42674$2082_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42101$2079 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42675$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$671 + connect \A \$681 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42101$2079_Y + connect \Y $and$libresoc.v:42675$2083_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42103$2081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42677$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$673 - connect \B \$675 - connect \Y $and$libresoc.v:42103$2081_Y + connect \A \$683 + connect \B \$685 + connect \Y $and$libresoc.v:42677$2085_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42104$2082 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42678$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68945,43 +69563,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42104$2082_Y + connect \Y $and$libresoc.v:42678$2086_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42106$2084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42680$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$56 [3] + connect \A \fus_cu_rd__rel_o$58 [3] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42106$2084_Y + connect \Y $and$libresoc.v:42680$2088_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42107$2085 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42681$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$683 + connect \A \$693 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42107$2085_Y + connect \Y $and$libresoc.v:42681$2089_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42109$2087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42683$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$685 - connect \B \$687 - connect \Y $and$libresoc.v:42109$2087_Y + connect \A \$695 + connect \B \$697 + connect \Y $and$libresoc.v:42683$2091_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42110$2088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42684$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68989,10 +69607,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [5] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42110$2088_Y + connect \Y $and$libresoc.v:42684$2092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42119$2098 + cell $and $and$libresoc.v:42693$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69000,10 +69618,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42119$2098_Y + connect \Y $and$libresoc.v:42693$2102_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42122$2101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42696$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69011,32 +69629,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42122$2101_Y + connect \Y $and$libresoc.v:42696$2105_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42123$2102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42697$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$715 + connect \A \$725 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42123$2102_Y + connect \Y $and$libresoc.v:42697$2106_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42125$2104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42699$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$717 - connect \B \$719 - connect \Y $and$libresoc.v:42125$2104_Y + connect \A \$727 + connect \B \$729 + connect \Y $and$libresoc.v:42699$2108_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42126$2105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42700$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69044,43 +69662,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42126$2105_Y + connect \Y $and$libresoc.v:42700$2109_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42128$2107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42702$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$47 [5] + connect \A \fus_cu_rd__rel_o$49 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42128$2107_Y + connect \Y $and$libresoc.v:42702$2111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42129$2108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42703$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$727 + connect \A \$737 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42129$2108_Y + connect \Y $and$libresoc.v:42703$2112_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42131$2110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42705$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$729 - connect \B \$731 - connect \Y $and$libresoc.v:42131$2110_Y + connect \A \$739 + connect \B \$741 + connect \Y $and$libresoc.v:42705$2114_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42132$2111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42706$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69088,43 +69706,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42132$2111_Y + connect \Y $and$libresoc.v:42706$2115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42134$2113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42708$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$56 [4] + connect \A \fus_cu_rd__rel_o$58 [4] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42134$2113_Y + connect \Y $and$libresoc.v:42708$2117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42135$2114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42709$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$739 + connect \A \$749 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42135$2114_Y + connect \Y $and$libresoc.v:42709$2118_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42137$2116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42711$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$741 - connect \B \$743 - connect \Y $and$libresoc.v:42137$2116_Y + connect \A \$751 + connect \B \$753 + connect \Y $and$libresoc.v:42711$2120_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42138$2117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42712$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69132,10 +69750,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42138$2117_Y + connect \Y $and$libresoc.v:42712$2121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42143$2123 + cell $and $and$libresoc.v:42717$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69143,10 +69761,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42143$2123_Y + connect \Y $and$libresoc.v:42717$2127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42144$2124 + cell $and $and$libresoc.v:42718$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69154,43 +69772,43 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42144$2124_Y + connect \Y $and$libresoc.v:42718$2128_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42147$2127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42721$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$47 [4] + connect \A \fus_cu_rd__rel_o$49 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42147$2127_Y + connect \Y $and$libresoc.v:42721$2131_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42148$2128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42722$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$765 + connect \A \$775 connect \B \rdflag_XER_xer_ov_0 - connect \Y $and$libresoc.v:42148$2128_Y + connect \Y $and$libresoc.v:42722$2132_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42150$2130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42724$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$767 - connect \B \$769 - connect \Y $and$libresoc.v:42150$2130_Y + connect \A \$777 + connect \B \$779 + connect \Y $and$libresoc.v:42724$2134_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42151$2131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42725$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69198,43 +69816,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42151$2131_Y + connect \Y $and$libresoc.v:42725$2135_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42153$2133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42727$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$38 [2] + connect \A \fus_cu_rd__rel_o$40 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42153$2133_Y + connect \Y $and$libresoc.v:42727$2137_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42154$2134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42728$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$777 + connect \A \$787 connect \B \rdflag_CR_full_cr_0 - connect \Y $and$libresoc.v:42154$2134_Y + connect \Y $and$libresoc.v:42728$2138_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42156$2136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42730$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$779 - connect \B \$781 - connect \Y $and$libresoc.v:42156$2136_Y + connect \A \$789 + connect \B \$791 + connect \Y $and$libresoc.v:42730$2140_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42157$2137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42731$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69242,43 +69860,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42157$2137_Y + connect \Y $and$libresoc.v:42731$2141_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42159$2139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42733$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$38 [3] + connect \A \fus_cu_rd__rel_o$40 [3] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42159$2139_Y + connect \Y $and$libresoc.v:42733$2143_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42160$2140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42734$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$789 + connect \A \$799 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42160$2140_Y + connect \Y $and$libresoc.v:42734$2144_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42162$2142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42736$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$791 - connect \B \$793 - connect \Y $and$libresoc.v:42162$2142_Y + connect \A \$801 + connect \B \$803 + connect \Y $and$libresoc.v:42736$2146_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42163$2143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42737$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69286,43 +69904,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42163$2143_Y + connect \Y $and$libresoc.v:42737$2147_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42167$2147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42741$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$79 [2] + connect \A \fus_cu_rd__rel_o$81 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42167$2147_Y + connect \Y $and$libresoc.v:42741$2151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42168$2148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42742$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$805 + connect \A \$815 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42168$2148_Y + connect \Y $and$libresoc.v:42742$2152_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42170$2150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42744$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$807 - connect \B \$809 - connect \Y $and$libresoc.v:42170$2150_Y + connect \A \$817 + connect \B \$819 + connect \Y $and$libresoc.v:42744$2154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42171$2151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42745$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69330,43 +69948,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42171$2151_Y + connect \Y $and$libresoc.v:42745$2155_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42176$2156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42750$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$38 [4] + connect \A \fus_cu_rd__rel_o$40 [4] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42176$2156_Y + connect \Y $and$libresoc.v:42750$2160_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42177$2157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42751$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$824 + connect \A \$834 connect \B \rdflag_CR_cr_b_0 - connect \Y $and$libresoc.v:42177$2157_Y + connect \Y $and$libresoc.v:42751$2161_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42179$2159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42753$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$826 - connect \B \$828 - connect \Y $and$libresoc.v:42179$2159_Y + connect \A \$836 + connect \B \$838 + connect \Y $and$libresoc.v:42753$2163_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42180$2160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42754$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69374,43 +69992,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $and$libresoc.v:42180$2160_Y + connect \Y $and$libresoc.v:42754$2164_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42184$2164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42758$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$38 [5] + connect \A \fus_cu_rd__rel_o$40 [5] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42184$2164_Y + connect \Y $and$libresoc.v:42758$2168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42185$2165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42759$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$840 + connect \A \$850 connect \B \rdflag_CR_cr_c_0 - connect \Y $and$libresoc.v:42185$2165_Y + connect \Y $and$libresoc.v:42759$2169_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42187$2167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42761$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$842 - connect \B \$844 - connect \Y $and$libresoc.v:42187$2167_Y + connect \A \$852 + connect \B \$854 + connect \Y $and$libresoc.v:42761$2171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42188$2168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42762$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69418,43 +70036,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $and$libresoc.v:42188$2168_Y + connect \Y $and$libresoc.v:42762$2172_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42192$2172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42766$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$79 [0] + connect \A \fus_cu_rd__rel_o$81 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42192$2172_Y + connect \Y $and$libresoc.v:42766$2176_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42193$2173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42767$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$856 + connect \A \$866 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42193$2173_Y + connect \Y $and$libresoc.v:42767$2177_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42195$2175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42769$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$858 - connect \B \$860 - connect \Y $and$libresoc.v:42195$2175_Y + connect \A \$868 + connect \B \$870 + connect \Y $and$libresoc.v:42769$2179_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42196$2176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42770$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69462,43 +70080,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42196$2176_Y + connect \Y $and$libresoc.v:42770$2180_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42198$2178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42772$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$41 [2] + connect \A \fus_cu_rd__rel_o$43 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42198$2178_Y + connect \Y $and$libresoc.v:42772$2182_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42199$2179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42773$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$868 + connect \A \$878 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42199$2179_Y + connect \Y $and$libresoc.v:42773$2183_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42201$2181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42775$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$870 - connect \B \$872 - connect \Y $and$libresoc.v:42201$2181_Y + connect \A \$880 + connect \B \$882 + connect \Y $and$libresoc.v:42775$2185_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42202$2182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42776$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69506,43 +70124,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42202$2182_Y + connect \Y $and$libresoc.v:42776$2186_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42204$2184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42778$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$47 [2] + connect \A \fus_cu_rd__rel_o$49 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42204$2184_Y + connect \Y $and$libresoc.v:42778$2188_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42205$2185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42779$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$880 + connect \A \$890 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42205$2185_Y + connect \Y $and$libresoc.v:42779$2189_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42207$2187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42781$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$882 - connect \B \$884 - connect \Y $and$libresoc.v:42207$2187_Y + connect \A \$892 + connect \B \$894 + connect \Y $and$libresoc.v:42781$2191_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42208$2188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42782$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69550,43 +70168,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42208$2188_Y + connect \Y $and$libresoc.v:42782$2192_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42213$2193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42787$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$79 [1] + connect \A \fus_cu_rd__rel_o$81 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42213$2193_Y + connect \Y $and$libresoc.v:42787$2197_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42214$2194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42788$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$898 + connect \A \$908 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42214$2194_Y + connect \Y $and$libresoc.v:42788$2198_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42216$2196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42790$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$900 - connect \B \$902 - connect \Y $and$libresoc.v:42216$2196_Y + connect \A \$910 + connect \B \$912 + connect \Y $and$libresoc.v:42790$2200_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42217$2197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42791$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69594,43 +70212,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [0] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42217$2197_Y + connect \Y $and$libresoc.v:42791$2201_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42219$2199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42793$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$41 [3] + connect \A \fus_cu_rd__rel_o$43 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42219$2199_Y + connect \Y $and$libresoc.v:42793$2203_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42220$2200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42794$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$910 + connect \A \$920 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42220$2200_Y + connect \Y $and$libresoc.v:42794$2204_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42222$2202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42796$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$912 - connect \B \$914 - connect \Y $and$libresoc.v:42222$2202_Y + connect \A \$922 + connect \B \$924 + connect \Y $and$libresoc.v:42796$2206_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42223$2203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42797$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69638,43 +70256,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [1] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42223$2203_Y + connect \Y $and$libresoc.v:42797$2207_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42227$2207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42801$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$47 [1] + connect \A \fus_cu_rd__rel_o$49 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42227$2207_Y + connect \Y $and$libresoc.v:42801$2211_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42228$2208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42802$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$926 + connect \A \$936 connect \B \rdflag_SPR_spr1_0 - connect \Y $and$libresoc.v:42228$2208_Y + connect \Y $and$libresoc.v:42802$2212_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42230$2210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42804$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$928 - connect \B \$930 - connect \Y $and$libresoc.v:42230$2210_Y + connect \A \$938 + connect \B \$940 + connect \Y $and$libresoc.v:42804$2214_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42231$2211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42805$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69682,10 +70300,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42231$2211_Y + connect \Y $and$libresoc.v:42805$2215_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:42234$2214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42808$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69693,10 +70311,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42234$2214_Y + connect \Y $and$libresoc.v:42808$2218_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42235$2215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42809$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69704,109 +70322,109 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42235$2215_Y + connect \Y $and$libresoc.v:42809$2219_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42236$2216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42810$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$91 [0] + connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42236$2216_Y + connect \Y $and$libresoc.v:42810$2220_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42237$2217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42811$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$94 [0] + connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42237$2217_Y + connect \Y $and$libresoc.v:42811$2221_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42238$2218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42812$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$97 [0] + connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42238$2218_Y + connect \Y $and$libresoc.v:42812$2222_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42239$2219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42813$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$100 [0] + connect \A \fus_cu_wr__rel_o$102 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42239$2219_Y + connect \Y $and$libresoc.v:42813$2223_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42240$2220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42814$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$103 [0] + connect \A \fus_cu_wr__rel_o$105 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42240$2220_Y + connect \Y $and$libresoc.v:42814$2224_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42241$2221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42815$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$106 [0] + connect \A \fus_cu_wr__rel_o$108 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42241$2221_Y + connect \Y $and$libresoc.v:42815$2225_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42242$2222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42816$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$109 [0] + connect \A \fus_cu_wr__rel_o$111 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42242$2222_Y + connect \Y $and$libresoc.v:42816$2226_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42243$2223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42817$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$111 [0] + connect \A \fus_cu_wr__rel_o$113 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42243$2223_Y + connect \Y $and$libresoc.v:42817$2227_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" - cell $and $and$libresoc.v:42244$2224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42818$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$111 [1] + connect \A \fus_cu_wr__rel_o$113 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42244$2224_Y + connect \Y $and$libresoc.v:42818$2228_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:42245$2225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42819$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69814,21 +70432,21 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42245$2225_Y + connect \Y $and$libresoc.v:42819$2229_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:42247$2227 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42821$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick - connect \B \$964 - connect \Y $and$libresoc.v:42247$2227_Y + connect \B \$974 + connect \Y $and$libresoc.v:42821$2231_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:42248$2228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42822$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69836,21 +70454,21 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42248$2228_Y + connect \Y $and$libresoc.v:42822$2232_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:42250$2230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42824$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$90 - connect \B \fus_cu_busy_o$12 - connect \Y $and$libresoc.v:42250$2230_Y + connect \A \fus_o_ok$92 + connect \B \fus_cu_busy_o$14 + connect \Y $and$libresoc.v:42824$2234_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:42251$2231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42825$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69858,65 +70476,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42251$2231_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:42253$2233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$978 - connect \B \$983 - connect \Y $and$libresoc.v:42253$2233_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:42254$2234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$978 - connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42254$2234_Y + connect \Y $and$libresoc.v:42825$2235_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:42256$2236 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42827$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$93 - connect \B \fus_cu_busy_o$18 - connect \Y $and$libresoc.v:42256$2236_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:42257$2237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [2] - connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42257$2237_Y + connect \A \wr_pick$988 + connect \B \$993 + connect \Y $and$libresoc.v:42827$2237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41877$1855 + cell $eq $eq$libresoc.v:42451$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$224 + connect \A \$231 connect \B 1'1 - connect \Y $eq$libresoc.v:41877$1855_Y + connect \Y $eq$libresoc.v:42451$1859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:41881$1859 + cell $eq $eq$libresoc.v:42455$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -69924,54 +70509,54 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:41881$1859_Y + connect \Y $eq$libresoc.v:42455$1863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:41883$1861 + cell $eq $eq$libresoc.v:42457$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$236 + connect \A \$243 connect \B 3'100 - connect \Y $eq$libresoc.v:41883$1861_Y + connect \Y $eq$libresoc.v:42457$1865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41891$1869 + cell $eq $eq$libresoc.v:42465$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$252 + connect \A \$259 connect \B 1'1 - connect \Y $eq$libresoc.v:41891$1869_Y + connect \Y $eq$libresoc.v:42465$1873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41898$1876 + cell $eq $eq$libresoc.v:42472$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$266 + connect \A \$273 connect \B 1'1 - connect \Y $eq$libresoc.v:41898$1876_Y + connect \Y $eq$libresoc.v:42472$1880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:41904$1882 + cell $eq $eq$libresoc.v:42478$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$278 + connect \A \$285 connect \B 2'10 - connect \Y $eq$libresoc.v:41904$1882_Y + connect \Y $eq$libresoc.v:42478$1886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:41906$1884 + cell $eq $eq$libresoc.v:42480$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -69979,54 +70564,54 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:41906$1884_Y + connect \Y $eq$libresoc.v:42480$1888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:41908$1886 + cell $eq $eq$libresoc.v:42482$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$286 + connect \A \$293 connect \B 3'100 - connect \Y $eq$libresoc.v:41908$1886_Y + connect \Y $eq$libresoc.v:42482$1890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41913$1891 + cell $eq $eq$libresoc.v:42487$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$296 + connect \A \$303 connect \B 1'1 - connect \Y $eq$libresoc.v:41913$1891_Y + connect \Y $eq$libresoc.v:42487$1895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41920$1898 + cell $eq $eq$libresoc.v:42494$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$310 + connect \A \$317 connect \B 1'1 - connect \Y $eq$libresoc.v:41920$1898_Y + connect \Y $eq$libresoc.v:42494$1902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41927$1905 + cell $eq $eq$libresoc.v:42501$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$324 + connect \A \$331 connect \B 1'1 - connect \Y $eq$libresoc.v:41927$1905_Y + connect \Y $eq$libresoc.v:42501$1909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:41931$1909 + cell $eq $eq$libresoc.v:42505$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70034,32 +70619,32 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:41931$1909_Y + connect \Y $eq$libresoc.v:42505$1913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:41933$1911 + cell $eq $eq$libresoc.v:42507$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$336 + connect \A \$343 connect \B 3'100 - connect \Y $eq$libresoc.v:41933$1911_Y + connect \Y $eq$libresoc.v:42507$1915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42072$2050 + cell $eq $eq$libresoc.v:42646$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$613 + connect \A \$623 connect \B 1'1 - connect \Y $eq$libresoc.v:42072$2050_Y + connect \Y $eq$libresoc.v:42646$2054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42118$2097 + cell $eq $eq$libresoc.v:42692$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70067,88 +70652,88 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42118$2097_Y + connect \Y $eq$libresoc.v:42692$2101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42120$2099 + cell $eq $eq$libresoc.v:42694$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$709 + connect \A \$719 connect \B 3'100 - connect \Y $eq$libresoc.v:42120$2099_Y + connect \Y $eq$libresoc.v:42694$2103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42145$2125 + cell $eq $eq$libresoc.v:42719$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$759 + connect \A \$769 connect \B 2'10 - connect \Y $eq$libresoc.v:42145$2125_Y + connect \Y $eq$libresoc.v:42719$2129_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:41702$1675 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $extend$libresoc.v:42276$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$1436 - connect \Y $extend$libresoc.v:41702$1675_Y + connect \A \$1447 + connect \Y $extend$libresoc.v:42276$1679_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:41768$1742 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $extend$libresoc.v:42342$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 - connect \A \$1600 - connect \Y $extend$libresoc.v:41768$1742_Y + connect \A \$1611 + connect \Y $extend$libresoc.v:42342$1746_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:41772$1747 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $extend$libresoc.v:42346$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$1608 - connect \Y $extend$libresoc.v:41772$1747_Y + connect \A \$1619 + connect \Y $extend$libresoc.v:42346$1751_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $pos $extend$libresoc.v:41837$1813 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $pos $extend$libresoc.v:42410$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \$1767 - connect \Y $extend$libresoc.v:41837$1813_Y + parameter \Y_WIDTH 3 + connect \A \$1778 + connect \Y $extend$libresoc.v:42410$1816_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $pos $extend$libresoc.v:41846$1823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $pos $extend$libresoc.v:42418$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 2 - parameter \Y_WIDTH 4 - connect \A \addr_en$1785 - connect \Y $extend$libresoc.v:41846$1823_Y + parameter \Y_WIDTH 3 + connect \A \addr_en$1796 + connect \Y $extend$libresoc.v:42418$1825_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:42117$2095 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $extend$libresoc.v:42691$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$704 - connect \Y $extend$libresoc.v:42117$2095_Y + connect \A \$714 + connect \Y $extend$libresoc.v:42691$2099_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:42142$2121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $extend$libresoc.v:42716$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$754 - connect \Y $extend$libresoc.v:42142$2121_Y + connect \A \$764 + connect \Y $extend$libresoc.v:42716$2125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $ne $ne$libresoc.v:41872$1850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + cell $ne $ne$libresoc.v:42446$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70156,10 +70741,10 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:41872$1850_Y + connect \Y $ne$libresoc.v:42446$1854_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $ne $ne$libresoc.v:41874$1852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + cell $ne $ne$libresoc.v:42448$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70167,761 +70752,761 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:41874$1852_Y + connect \Y $ne$libresoc.v:42448$1856_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41533$1506 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42107$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1000 - connect \Y $not$libresoc.v:41533$1506_Y + connect \A \wr_pick_dly$1010 + connect \Y $not$libresoc.v:42107$1510_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41539$1512 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42113$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1021 - connect \Y $not$libresoc.v:41539$1512_Y + connect \A \wr_pick_dly$1031 + connect \Y $not$libresoc.v:42113$1516_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41545$1518 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42119$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1039 - connect \Y $not$libresoc.v:41545$1518_Y + connect \A \wr_pick_dly$1049 + connect \Y $not$libresoc.v:42119$1522_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41551$1524 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42125$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1061 - connect \Y $not$libresoc.v:41551$1524_Y + connect \A \wr_pick_dly$1071 + connect \Y $not$libresoc.v:42125$1528_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41557$1530 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42131$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1081 - connect \Y $not$libresoc.v:41557$1530_Y + connect \A \wr_pick_dly$1091 + connect \Y $not$libresoc.v:42131$1534_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41563$1536 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42137$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1101 - connect \Y $not$libresoc.v:41563$1536_Y + connect \A \wr_pick_dly$1111 + connect \Y $not$libresoc.v:42137$1540_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41569$1542 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42143$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1120 - connect \Y $not$libresoc.v:41569$1542_Y + connect \A \wr_pick_dly$1130 + connect \Y $not$libresoc.v:42143$1546_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41575$1548 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42149$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1138 - connect \Y $not$libresoc.v:41575$1548_Y + connect \A \wr_pick_dly$1148 + connect \Y $not$libresoc.v:42149$1552_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41609$1582 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42183$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1211 - connect \Y $not$libresoc.v:41609$1582_Y + connect \A \wr_pick_dly$1222 + connect \Y $not$libresoc.v:42183$1586_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41621$1594 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42195$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1239 - connect \Y $not$libresoc.v:41621$1594_Y + connect \A \wr_pick_dly$1250 + connect \Y $not$libresoc.v:42195$1598_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41629$1602 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42203$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1259 - connect \Y $not$libresoc.v:41629$1602_Y + connect \A \wr_pick_dly$1270 + connect \Y $not$libresoc.v:42203$1606_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41637$1610 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42211$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1279 - connect \Y $not$libresoc.v:41637$1610_Y + connect \A \wr_pick_dly$1290 + connect \Y $not$libresoc.v:42211$1614_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41645$1618 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42219$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1299 - connect \Y $not$libresoc.v:41645$1618_Y + connect \A \wr_pick_dly$1310 + connect \Y $not$libresoc.v:42219$1622_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41653$1626 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42227$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1319 - connect \Y $not$libresoc.v:41653$1626_Y + connect \A \wr_pick_dly$1330 + connect \Y $not$libresoc.v:42227$1630_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41661$1634 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42235$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1339 - connect \Y $not$libresoc.v:41661$1634_Y + connect \A \wr_pick_dly$1350 + connect \Y $not$libresoc.v:42235$1638_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41682$1655 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42256$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1386 - connect \Y $not$libresoc.v:41682$1655_Y + connect \A \wr_pick_dly$1397 + connect \Y $not$libresoc.v:42256$1659_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41688$1661 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42262$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1402 - connect \Y $not$libresoc.v:41688$1661_Y + connect \A \wr_pick_dly$1413 + connect \Y $not$libresoc.v:42262$1665_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41694$1667 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42268$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1418 - connect \Y $not$libresoc.v:41694$1667_Y + connect \A \wr_pick_dly$1429 + connect \Y $not$libresoc.v:42268$1671_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41709$1683 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42283$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1452 - connect \Y $not$libresoc.v:41709$1683_Y + connect \A \wr_pick_dly$1463 + connect \Y $not$libresoc.v:42283$1687_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41715$1689 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42289$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1468 - connect \Y $not$libresoc.v:41715$1689_Y + connect \A \wr_pick_dly$1479 + connect \Y $not$libresoc.v:42289$1693_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41721$1695 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42295$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1484 - connect \Y $not$libresoc.v:41721$1695_Y + connect \A \wr_pick_dly$1495 + connect \Y $not$libresoc.v:42295$1699_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41727$1701 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42301$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1500 - connect \Y $not$libresoc.v:41727$1701_Y + connect \A \wr_pick_dly$1511 + connect \Y $not$libresoc.v:42301$1705_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41743$1717 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42317$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1536 - connect \Y $not$libresoc.v:41743$1717_Y + connect \A \wr_pick_dly$1547 + connect \Y $not$libresoc.v:42317$1721_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41749$1723 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42323$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1552 - connect \Y $not$libresoc.v:41749$1723_Y + connect \A \wr_pick_dly$1563 + connect \Y $not$libresoc.v:42323$1727_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41755$1729 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42329$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1568 - connect \Y $not$libresoc.v:41755$1729_Y + connect \A \wr_pick_dly$1579 + connect \Y $not$libresoc.v:42329$1733_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41761$1735 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42335$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1584 - connect \Y $not$libresoc.v:41761$1735_Y + connect \A \wr_pick_dly$1595 + connect \Y $not$libresoc.v:42335$1739_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41780$1756 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:42354$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1626 - connect \Y $not$libresoc.v:41780$1756_Y + connect \A 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parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 - connect \Y $not$libresoc.v:42178$2158_Y + connect \Y $not$libresoc.v:42752$2162_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $not $not$libresoc.v:42186$2166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42760$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 - connect \Y $not$libresoc.v:42186$2166_Y + connect \Y $not$libresoc.v:42760$2170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $not $not$libresoc.v:42194$2174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42768$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 - connect \Y $not$libresoc.v:42194$2174_Y + connect \Y $not$libresoc.v:42768$2178_Y end - attribute \src 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$or$libresoc.v:41595$1568_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$1187 + connect \B \$1191 + connect \Y $or$libresoc.v:42169$1572_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41596$1569 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42170$1573 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$1174 - connect \B \$1182 - connect \Y $or$libresoc.v:41596$1569_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$1185 + connect \B \$1193 + connect \Y $or$libresoc.v:42170$1573_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41597$1570 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42171$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp - connect \B \wp$989 - connect \Y $or$libresoc.v:41597$1570_Y + connect \B \wp$999 + connect \Y $or$libresoc.v:42171$1574_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41598$1571 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42172$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1028 - connect \B \wp$1050 - connect \Y $or$libresoc.v:41598$1571_Y + connect \A \wp$1038 + connect \B \wp$1060 + connect \Y $or$libresoc.v:42172$1575_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41599$1572 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42173$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1010 - connect \B \$1188 - connect \Y $or$libresoc.v:41599$1572_Y + connect \A \wp$1020 + connect \B \$1199 + connect \Y $or$libresoc.v:42173$1576_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41600$1573 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42174$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1186 - connect \B \$1190 - connect \Y $or$libresoc.v:41600$1573_Y + connect \A \$1197 + connect \B \$1201 + connect \Y $or$libresoc.v:42174$1577_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41601$1574 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42175$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1070 - connect \B \wp$1090 - connect \Y $or$libresoc.v:41601$1574_Y + connect \A \wp$1080 + connect \B \wp$1100 + connect \Y $or$libresoc.v:42175$1578_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41602$1575 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42176$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1127 - connect \B \wp$1143 - connect \Y $or$libresoc.v:41602$1575_Y + connect \A \wp$1137 + connect \B \wp$1153 + connect \Y $or$libresoc.v:42176$1579_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41603$1576 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42177$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1109 - connect \B \$1196 - connect \Y $or$libresoc.v:41603$1576_Y + connect \A \wp$1119 + connect \B \$1207 + connect \Y $or$libresoc.v:42177$1580_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41604$1577 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42178$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1194 - connect \B \$1198 - connect \Y $or$libresoc.v:41604$1577_Y + connect \A \$1205 + connect \B \$1209 + connect \Y $or$libresoc.v:42178$1581_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41605$1578 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42179$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1192 - connect \B \$1200 - connect \Y $or$libresoc.v:41605$1578_Y + connect \A \$1203 + connect \B \$1211 + connect \Y $or$libresoc.v:42179$1582_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41667$1640 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42241$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest3_o - connect \B \fus_dest2_o$126 - connect \Y $or$libresoc.v:41667$1640_Y + connect \B \fus_dest2_o$128 + connect \Y $or$libresoc.v:42241$1644_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41668$1641 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42242$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$125 - connect \B \$1354 - connect \Y $or$libresoc.v:41668$1641_Y + connect \A \fus_dest2_o$127 + connect \B \$1365 + connect \Y $or$libresoc.v:42242$1645_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41669$1642 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42243$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$128 - connect \B \fus_dest2_o$129 - connect \Y $or$libresoc.v:41669$1642_Y + connect \A \fus_dest2_o$130 + connect \B \fus_dest2_o$131 + connect \Y $or$libresoc.v:42243$1646_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41670$1643 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42244$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$127 - connect \B \$1358 - connect \Y $or$libresoc.v:41670$1643_Y + connect \A \fus_dest2_o$129 + connect \B \$1369 + connect \Y $or$libresoc.v:42244$1647_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41671$1644 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42245$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \$1356 - connect \B \$1360 - connect \Y $or$libresoc.v:41671$1644_Y + connect \A \$1367 + connect \B \$1371 + connect \Y $or$libresoc.v:42245$1648_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41672$1645 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42246$1649 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 256 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1267 - connect \B \addr_en$1287 - connect \Y $or$libresoc.v:41672$1645_Y + parameter \B_WIDTH 256 + parameter \Y_WIDTH 256 + connect \A \addr_en$1278 + connect \B \addr_en$1298 + connect \Y $or$libresoc.v:42246$1649_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41673$1646 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42247$1650 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 256 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1247 - connect \B \$1365 - connect \Y $or$libresoc.v:41673$1646_Y + parameter \B_WIDTH 256 + parameter \Y_WIDTH 256 + connect \A \addr_en$1258 + connect \B \$1376 + connect \Y $or$libresoc.v:42247$1650_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41674$1647 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42248$1651 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 256 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1327 - connect \B \addr_en$1347 - connect \Y $or$libresoc.v:41674$1647_Y + parameter \B_WIDTH 256 + parameter \Y_WIDTH 256 + connect \A \addr_en$1338 + connect \B \addr_en$1358 + connect \Y $or$libresoc.v:42248$1651_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41675$1648 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42249$1652 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 256 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1307 - connect \B \$1369 - connect \Y $or$libresoc.v:41675$1648_Y + parameter \B_WIDTH 256 + parameter \Y_WIDTH 256 + connect \A \addr_en$1318 + connect \B \$1380 + connect \Y $or$libresoc.v:42249$1652_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41676$1649 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42250$1653 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 256 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \$1367 - connect \B \$1371 - connect \Y $or$libresoc.v:41676$1649_Y + parameter \B_WIDTH 256 + parameter \Y_WIDTH 256 + connect \A \$1378 + connect \B \$1382 + connect \Y $or$libresoc.v:42250$1653_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41698$1671 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42272$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest6_o - connect \B \fus_dest3_o$133 - connect \Y $or$libresoc.v:41698$1671_Y + connect \B \fus_dest3_o$135 + connect \Y $or$libresoc.v:42272$1675_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41699$1672 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42273$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$132 - connect \B \$1429 - connect \Y $or$libresoc.v:41699$1672_Y + connect \A \fus_dest3_o$134 + connect \B \$1440 + connect \Y $or$libresoc.v:42273$1676_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41700$1673 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42274$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1410 - connect \B \addr_en$1426 - connect \Y $or$libresoc.v:41700$1673_Y + connect \A \addr_en$1421 + connect \B \addr_en$1437 + connect \Y $or$libresoc.v:42274$1677_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41701$1674 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42275$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1394 - connect \B \$1434 - connect \Y $or$libresoc.v:41701$1674_Y + connect \A \addr_en$1405 + connect \B \$1445 + connect \Y $or$libresoc.v:42275$1678_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41731$1705 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42305$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71325,659 +71910,659 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $or$libresoc.v:41731$1705_Y + connect \Y $or$libresoc.v:42305$1709_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41732$1706 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42306$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$137 - connect \B \fus_dest3_o$138 - connect \Y $or$libresoc.v:41732$1706_Y + connect \A \fus_dest3_o$139 + connect \B \fus_dest3_o$140 + connect \Y $or$libresoc.v:42306$1710_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41733$1707 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42307$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \$1511 - connect \B \$1513 - connect \Y $or$libresoc.v:41733$1707_Y + connect \A \$1522 + connect \B \$1524 + connect \Y $or$libresoc.v:42307$1711_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41734$1708 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42308$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1460 - connect \B \addr_en$1476 - connect \Y $or$libresoc.v:41734$1708_Y + connect \A \addr_en$1471 + connect \B \addr_en$1487 + connect \Y $or$libresoc.v:42308$1712_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41735$1709 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42309$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1492 - connect \B \addr_en$1508 - connect \Y $or$libresoc.v:41735$1709_Y + connect \A \addr_en$1503 + connect \B \addr_en$1519 + connect \Y $or$libresoc.v:42309$1713_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41736$1710 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42310$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \$1517 - connect \B \$1519 - connect \Y $or$libresoc.v:41736$1710_Y + connect \A \$1528 + connect \B \$1530 + connect \Y $or$libresoc.v:42310$1714_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41765$1739 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42339$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_dest5_o$142 - connect \B \fus_dest4_o$143 - connect \Y $or$libresoc.v:41765$1739_Y + connect \A \fus_dest5_o$144 + connect \B \fus_dest4_o$145 + connect \Y $or$libresoc.v:42339$1743_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41766$1740 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42340$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_dest4_o$144 - connect \B \fus_dest4_o$145 - connect \Y $or$libresoc.v:41766$1740_Y + connect \A \fus_dest4_o$146 + connect \B \fus_dest4_o$147 + connect \Y $or$libresoc.v:42340$1744_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41767$1741 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42341$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1596 - connect \B \$1598 - connect \Y $or$libresoc.v:41767$1741_Y + connect \A \$1607 + connect \B \$1609 + connect \Y $or$libresoc.v:42341$1745_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41769$1744 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42343$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1544 - connect \B \addr_en$1560 - connect \Y $or$libresoc.v:41769$1744_Y + connect \A \addr_en$1555 + connect \B \addr_en$1571 + connect \Y $or$libresoc.v:42343$1748_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41770$1745 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42344$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1576 - connect \B \addr_en$1592 - connect \Y $or$libresoc.v:41770$1745_Y + connect \A \addr_en$1587 + connect \B \addr_en$1603 + connect \Y $or$libresoc.v:42344$1749_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41771$1746 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42345$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1604 - connect \B \$1606 - connect \Y $or$libresoc.v:41771$1746_Y + connect \A \$1615 + connect \B \$1617 + connect \Y $or$libresoc.v:42345$1750_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41808$1784 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42382$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$151 - connect \B \fus_dest2_o$152 - connect \Y $or$libresoc.v:41808$1784_Y + connect \A \fus_dest1_o$153 + connect \B \fus_dest2_o$154 + connect \Y $or$libresoc.v:42382$1788_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41809$1785 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42383$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest2_o$154 - connect \B \fus_dest3_o$155 - connect \Y $or$libresoc.v:41809$1785_Y + connect \A \fus_dest2_o$156 + connect \B \fus_dest3_o$157 + connect \Y $or$libresoc.v:42383$1789_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41810$1786 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42384$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$153 - connect \B \$1706 - connect \Y $or$libresoc.v:41810$1786_Y + connect \A \fus_dest3_o$155 + connect \B \$1717 + connect \Y $or$libresoc.v:42384$1790_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41811$1787 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42385$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$1704 - connect \B \$1708 - connect \Y $or$libresoc.v:41811$1787_Y + connect \A \$1715 + connect \B \$1719 + connect \Y $or$libresoc.v:42385$1791_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41812$1788 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42386$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1637 - connect \B \addr_en$1653 - connect \Y $or$libresoc.v:41812$1788_Y + connect \A \addr_en$1648 + connect \B \addr_en$1664 + connect \Y $or$libresoc.v:42386$1792_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41813$1789 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42387$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1685 - connect \B \addr_en$1701 - connect \Y $or$libresoc.v:41813$1789_Y + connect \A \addr_en$1696 + connect \B \addr_en$1712 + connect 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$or$libresoc.v:42389$1795_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41816$1792 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42390$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1634 - connect \B \wp$1650 - connect \Y $or$libresoc.v:41816$1792_Y + connect \A \wp$1645 + connect \B \wp$1661 + connect \Y $or$libresoc.v:42390$1796_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41817$1793 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42391$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1682 - connect \B \wp$1698 - connect \Y $or$libresoc.v:41817$1793_Y + connect \A \wp$1693 + connect \B \wp$1709 + connect \Y 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- connect \Y $or$libresoc.v:41901$1879_Y + connect \A \$277 + connect \B \$279 + connect \Y $or$libresoc.v:42475$1883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:41905$1883 + cell $or $or$libresoc.v:42479$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$276 - connect \B \$280 - connect \Y $or$libresoc.v:41905$1883_Y + connect \A \$283 + connect \B \$287 + connect \Y $or$libresoc.v:42479$1887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:41909$1887 + cell $or $or$libresoc.v:42483$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$284 - connect \B \$288 - connect \Y $or$libresoc.v:41909$1887_Y + connect \A \$291 + connect \B \$295 + connect \Y $or$libresoc.v:42483$1891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41914$1892 + cell $or $or$libresoc.v:42488$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$294 - connect \B \$298 - connect \Y $or$libresoc.v:41914$1892_Y + connect \A \$301 + connect \B \$305 + connect \Y $or$libresoc.v:42488$1896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41916$1894 + cell $or $or$libresoc.v:42490$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$300 - connect \B \$302 - connect \Y $or$libresoc.v:41916$1894_Y + connect \A \$307 + connect \B \$309 + connect \Y $or$libresoc.v:42490$1898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41921$1899 + cell $or $or$libresoc.v:42495$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$308 - connect \B \$312 - connect \Y $or$libresoc.v:41921$1899_Y + connect \A \$315 + connect \B \$319 + connect \Y $or$libresoc.v:42495$1903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41923$1901 + cell $or $or$libresoc.v:42497$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$314 - connect \B \$316 - connect \Y $or$libresoc.v:41923$1901_Y + connect \A \$321 + connect \B \$323 + connect \Y $or$libresoc.v:42497$1905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41928$1906 + cell $or $or$libresoc.v:42502$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$322 - connect \B \$326 - connect \Y $or$libresoc.v:41928$1906_Y + connect \A \$329 + connect \B \$333 + connect \Y $or$libresoc.v:42502$1910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41930$1908 + cell $or $or$libresoc.v:42504$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$328 - connect \B \$330 - connect \Y $or$libresoc.v:41930$1908_Y + connect \A \$335 + connect \B \$337 + connect \Y $or$libresoc.v:42504$1912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:41934$1912 + cell $or $or$libresoc.v:42508$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$334 - connect \B \$338 - connect \Y $or$libresoc.v:41934$1912_Y + connect \A \$341 + connect \B \$345 + connect \Y $or$libresoc.v:42508$1916_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41991$1969 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42565$1973 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_alu0_0 connect \B \addr_en_INT_ra_cr0_1 - connect \Y $or$libresoc.v:41991$1969_Y + connect \Y $or$libresoc.v:42565$1973_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41992$1970 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42566$1974 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_trap0_2 connect \B \addr_en_INT_ra_logical0_3 - connect \Y $or$libresoc.v:41992$1970_Y + connect \Y $or$libresoc.v:42566$1974_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41993$1971 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42567$1975 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$453 - connect \B \$455 - connect \Y $or$libresoc.v:41993$1971_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$461 + connect \B \$463 + connect \Y $or$libresoc.v:42567$1975_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41994$1972 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42568$1976 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_spr0_4 connect \B \addr_en_INT_ra_div0_5 - connect \Y $or$libresoc.v:41994$1972_Y + connect \Y $or$libresoc.v:42568$1976_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41995$1973 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42569$1977 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_shiftrot0_7 connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $or$libresoc.v:41995$1973_Y + connect \Y $or$libresoc.v:42569$1977_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41996$1974 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42570$1978 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_mul0_6 - connect \B \$461 - connect \Y $or$libresoc.v:41996$1974_Y + connect \B \$469 + connect \Y $or$libresoc.v:42570$1978_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41997$1975 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42571$1979 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$459 - connect \B \$463 - connect \Y $or$libresoc.v:41997$1975_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$467 + connect \B \$471 + connect \Y $or$libresoc.v:42571$1979_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41998$1976 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42572$1980 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$457 - connect \B \$465 - connect \Y $or$libresoc.v:41998$1976_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$465 + connect \B \$473 + connect \Y $or$libresoc.v:42572$1980_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42048$2026 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42622$2030 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_alu0_0 connect \B \addr_en_INT_rb_cr0_1 - connect \Y $or$libresoc.v:42048$2026_Y + connect \Y $or$libresoc.v:42622$2030_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42049$2027 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42623$2031 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_trap0_2 connect \B \addr_en_INT_rb_logical0_3 - connect \Y $or$libresoc.v:42049$2027_Y + connect \Y $or$libresoc.v:42623$2031_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:42050$2028 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42624$2032 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$567 - connect \B \$569 - connect \Y $or$libresoc.v:42050$2028_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$576 + connect \B \$578 + connect \Y $or$libresoc.v:42624$2032_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42051$2029 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42625$2033 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_div0_4 connect \B \addr_en_INT_rb_mul0_5 - connect \Y $or$libresoc.v:42051$2029_Y + connect \Y $or$libresoc.v:42625$2033_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42052$2030 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42626$2034 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_shiftrot0_6 connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $or$libresoc.v:42052$2030_Y + connect \Y $or$libresoc.v:42626$2034_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:42053$2031 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42627$2035 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$573 - connect \B \$575 - connect \Y $or$libresoc.v:42053$2031_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$582 + connect \B \$584 + connect \Y $or$libresoc.v:42627$2035_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:42054$2032 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42628$2036 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$571 - connect \B \$577 - connect \Y $or$libresoc.v:42054$2032_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$580 + connect \B \$586 + connect \Y $or$libresoc.v:42628$2036_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42068$2046 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42642$2050 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \addr_en_INT_rc_shiftrot0_0 connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $or$libresoc.v:42068$2046_Y + connect \Y $or$libresoc.v:42642$2050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42073$2051 + cell $or $or$libresoc.v:42647$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$611 - connect \B \$615 - connect \Y $or$libresoc.v:42073$2051_Y + connect \A \$621 + connect \B \$625 + connect \Y $or$libresoc.v:42647$2055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42075$2053 + cell $or $or$libresoc.v:42649$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$617 - connect \B \$619 - connect \Y $or$libresoc.v:42075$2053_Y + connect \A \$627 + connect \B \$629 + connect \Y $or$libresoc.v:42649$2057_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42112$2090 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42686$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71985,21 +72570,21 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_logical0_1 connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $or$libresoc.v:42112$2090_Y + connect \Y $or$libresoc.v:42686$2094_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:42113$2091 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42687$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 - connect \B \$696 - connect \Y $or$libresoc.v:42113$2091_Y + connect \B \$706 + connect \Y $or$libresoc.v:42687$2095_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42114$2092 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42688$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72007,43 +72592,43 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_mul0_4 connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $or$libresoc.v:42114$2092_Y + connect \Y $or$libresoc.v:42688$2096_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:42115$2093 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42689$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_div0_3 - connect \B \$700 - connect \Y $or$libresoc.v:42115$2093_Y + connect \B \$710 + connect \Y $or$libresoc.v:42689$2097_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:42116$2094 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42690$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$698 - connect \B \$702 - connect \Y $or$libresoc.v:42116$2094_Y + connect \A \$708 + connect \B \$712 + connect \Y $or$libresoc.v:42690$2098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42121$2100 + cell $or $or$libresoc.v:42695$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$707 - connect \B \$711 - connect \Y $or$libresoc.v:42121$2100_Y + connect \A \$717 + connect \B \$721 + connect \Y $or$libresoc.v:42695$2104_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42140$2119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42714$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72051,43 +72636,43 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $or$libresoc.v:42140$2119_Y + connect \Y $or$libresoc.v:42714$2123_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:42141$2120 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42715$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 - connect \B \$752 - connect \Y $or$libresoc.v:42141$2120_Y + connect \B \$762 + connect \Y $or$libresoc.v:42715$2124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42146$2126 + cell $or $or$libresoc.v:42720$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$757 - connect \B \$761 - connect \Y $or$libresoc.v:42146$2126_Y + connect \A \$767 + connect \B \$771 + connect \Y $or$libresoc.v:42720$2130_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42175$2155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42749$2159 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 256 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 256 + parameter \Y_WIDTH 256 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $or$libresoc.v:42175$2155_Y + connect \Y $or$libresoc.v:42749$2159_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42210$2190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42784$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72095,21 +72680,21 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_trap0_1 connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $or$libresoc.v:42210$2190_Y + connect \Y $or$libresoc.v:42784$2194_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:42211$2191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42785$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_0 - connect \B \$892 - connect \Y $or$libresoc.v:42211$2191_Y + connect \B \$902 + connect \Y $or$libresoc.v:42785$2195_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:42225$2205 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42799$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72117,370 +72702,370 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast2_branch0_0 connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $or$libresoc.v:42225$2205_Y + connect \Y $or$libresoc.v:42799$2209_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:41702$1676 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $pos$libresoc.v:42276$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:41702$1675_Y - connect \Y $pos$libresoc.v:41702$1676_Y + connect \A $extend$libresoc.v:42276$1679_Y + connect \Y $pos$libresoc.v:42276$1680_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:41768$1743 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $pos$libresoc.v:42342$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:41768$1742_Y - connect \Y $pos$libresoc.v:41768$1743_Y + connect \A $extend$libresoc.v:42342$1746_Y + connect \Y $pos$libresoc.v:42342$1747_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:41772$1748 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $pos$libresoc.v:42346$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:41772$1747_Y - connect \Y $pos$libresoc.v:41772$1748_Y + connect \A $extend$libresoc.v:42346$1751_Y + connect \Y $pos$libresoc.v:42346$1752_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $pos $pos$libresoc.v:41837$1814 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $pos $pos$libresoc.v:42410$1817 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:41837$1813_Y - connect \Y $pos$libresoc.v:41837$1814_Y + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $extend$libresoc.v:42410$1816_Y + connect \Y $pos$libresoc.v:42410$1817_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $pos $pos$libresoc.v:41846$1824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $pos $pos$libresoc.v:42418$1826 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:41846$1823_Y - connect \Y $pos$libresoc.v:41846$1824_Y + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $extend$libresoc.v:42418$1825_Y + connect \Y $pos$libresoc.v:42418$1826_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:42117$2096 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $pos$libresoc.v:42691$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42117$2095_Y - connect \Y $pos$libresoc.v:42117$2096_Y + connect \A $extend$libresoc.v:42691$2099_Y + connect \Y $pos$libresoc.v:42691$2100_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:42142$2122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $pos $pos$libresoc.v:42716$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42142$2121_Y - connect \Y $pos$libresoc.v:42142$2122_Y + connect \A $extend$libresoc.v:42716$2125_Y + connect \Y $pos$libresoc.v:42716$2126_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41838$1815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42427$1835 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$175 - connect \Y $reduce_or$libresoc.v:41838$1815_Y + connect \A \$182 + connect \Y $reduce_or$libresoc.v:42427$1835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41855$1833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42429$1837 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$179 - connect \Y $reduce_or$libresoc.v:41855$1833_Y + connect \A \$186 + connect \Y $reduce_or$libresoc.v:42429$1837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41857$1835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42431$1839 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$183 - connect \Y $reduce_or$libresoc.v:41857$1835_Y + connect \A \$190 + connect \Y $reduce_or$libresoc.v:42431$1839_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41859$1837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42433$1841 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$187 - connect \Y $reduce_or$libresoc.v:41859$1837_Y + connect \A \$194 + connect \Y $reduce_or$libresoc.v:42433$1841_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41861$1839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42435$1843 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$191 - connect \Y $reduce_or$libresoc.v:41861$1839_Y + connect \A \$198 + connect \Y $reduce_or$libresoc.v:42435$1843_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41863$1841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42437$1845 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$195 - connect \Y $reduce_or$libresoc.v:41863$1841_Y + connect \A \$202 + connect \Y $reduce_or$libresoc.v:42437$1845_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41865$1843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42439$1847 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$199 - connect \Y $reduce_or$libresoc.v:41865$1843_Y + connect \A \$206 + connect \Y $reduce_or$libresoc.v:42439$1847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41867$1845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42441$1849 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$203 - connect \Y $reduce_or$libresoc.v:41867$1845_Y + connect \A \$210 + connect \Y $reduce_or$libresoc.v:42441$1849_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41869$1847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42443$1851 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$207 - connect \Y $reduce_or$libresoc.v:41869$1847_Y + connect \A \$214 + connect \Y $reduce_or$libresoc.v:42443$1851_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $reduce_or $reduce_or$libresoc.v:41871$1849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42445$1853 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$211 - connect \Y $reduce_or$libresoc.v:41871$1849_Y + connect \A \$218 + connect \Y $reduce_or$libresoc.v:42445$1853_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" - cell $reduce_or $reduce_or$libresoc.v:41999$1977 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42573$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $reduce_or$libresoc.v:41999$1977_Y + connect \Y $reduce_or$libresoc.v:42573$1981_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" - cell $reduce_or $reduce_or$libresoc.v:42055$2033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42629$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $reduce_or$libresoc.v:42055$2033_Y + connect \Y $reduce_or$libresoc.v:42629$2037_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" - cell $reduce_or $reduce_or$libresoc.v:42069$2047 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42643$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $reduce_or$libresoc.v:42069$2047_Y + connect \Y $reduce_or$libresoc.v:42643$2051_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" - cell $reduce_or $reduce_or$libresoc.v:42212$2192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42786$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $reduce_or$libresoc.v:42212$2192_Y + connect \Y $reduce_or$libresoc.v:42786$2196_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" - cell $reduce_or $reduce_or$libresoc.v:42226$2206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42800$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $reduce_or$libresoc.v:42226$2206_Y + connect \Y $reduce_or$libresoc.v:42800$2210_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" - cell $reduce_or $reduce_or$libresoc.v:42233$2213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42807$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rp_SPR_spr1_spr0_0 - connect \Y $reduce_or$libresoc.v:42233$2213_Y + connect \Y $reduce_or$libresoc.v:42807$2217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41625$1598 + cell $sshl $sshl$libresoc.v:42199$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1248 - connect \Y $sshl$libresoc.v:41625$1598_Y + connect \B \$1259 + connect \Y $sshl$libresoc.v:42199$1602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41633$1606 + cell $sshl $sshl$libresoc.v:42207$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1268 - connect \Y $sshl$libresoc.v:41633$1606_Y + connect \B \$1279 + connect \Y $sshl$libresoc.v:42207$1610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41641$1614 + cell $sshl $sshl$libresoc.v:42215$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1288 - connect \Y $sshl$libresoc.v:41641$1614_Y + connect \B \$1299 + connect \Y $sshl$libresoc.v:42215$1618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41649$1622 + cell $sshl $sshl$libresoc.v:42223$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1308 - connect \Y $sshl$libresoc.v:41649$1622_Y + connect \B \$1319 + connect \Y $sshl$libresoc.v:42223$1626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41657$1630 + cell $sshl $sshl$libresoc.v:42231$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1328 - connect \Y $sshl$libresoc.v:41657$1630_Y + connect \B \$1339 + connect \Y $sshl$libresoc.v:42231$1634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41665$1638 + cell $sshl $sshl$libresoc.v:42239$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1348 - connect \Y $sshl$libresoc.v:41665$1638_Y + connect \B \$1359 + connect \Y $sshl$libresoc.v:42239$1642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42165$2145 + cell $sshl $sshl$libresoc.v:42739$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$799 - connect \Y $sshl$libresoc.v:42165$2145_Y + connect \B \$809 + connect \Y $sshl$libresoc.v:42739$2149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42173$2153 + cell $sshl $sshl$libresoc.v:42747$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$815 - connect \Y $sshl$libresoc.v:42173$2153_Y + connect \B \$825 + connect \Y $sshl$libresoc.v:42747$2157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $sshl$libresoc.v:42182$2162 + cell $sshl $sshl$libresoc.v:42756$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$834 - connect \Y $sshl$libresoc.v:42182$2162_Y + connect \B \$844 + connect \Y $sshl$libresoc.v:42756$2166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $sshl$libresoc.v:42190$2170 + cell $sshl $sshl$libresoc.v:42764$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$850 - connect \Y $sshl$libresoc.v:42190$2170_Y + connect \B \$860 + connect \Y $sshl$libresoc.v:42764$2174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41624$1597 + cell $sub $sub$libresoc.v:42198$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41624$1597_Y + connect \Y $sub$libresoc.v:42198$1601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41632$1605 + cell $sub $sub$libresoc.v:42206$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41632$1605_Y + connect \Y $sub$libresoc.v:42206$1609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41640$1613 + cell $sub $sub$libresoc.v:42214$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41640$1613_Y + connect \Y $sub$libresoc.v:42214$1617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41648$1621 + cell $sub $sub$libresoc.v:42222$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41648$1621_Y + connect \Y $sub$libresoc.v:42222$1625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41656$1629 + cell $sub $sub$libresoc.v:42230$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41656$1629_Y + connect \Y $sub$libresoc.v:42230$1633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41664$1637 + cell $sub $sub$libresoc.v:42238$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41664$1637_Y + connect \Y $sub$libresoc.v:42238$1641_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:185" - cell $sub $sub$libresoc.v:41873$1851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + cell $sub $sub$libresoc.v:42447$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72488,670 +73073,670 @@ module \core parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 - connect \Y $sub$libresoc.v:41873$1851_Y + connect \Y $sub$libresoc.v:42447$1855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42164$2144 + cell $sub $sub$libresoc.v:42738$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42164$2144_Y + connect \Y $sub$libresoc.v:42738$2148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42172$2152 + cell $sub $sub$libresoc.v:42746$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42172$2152_Y + connect \Y $sub$libresoc.v:42746$2156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $sub$libresoc.v:42181$2161 + cell $sub $sub$libresoc.v:42755$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2 - connect \Y $sub$libresoc.v:42181$2161_Y + connect \Y $sub$libresoc.v:42755$2165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $sub$libresoc.v:42189$2169 + cell $sub $sub$libresoc.v:42763$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2$1 - connect \Y $sub$libresoc.v:42189$2169_Y + connect \Y $sub$libresoc.v:42763$2173_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41536$1509 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42104$1507 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1010 - connect \Y $ternary$libresoc.v:41536$1509_Y + connect \S \wp$999 + connect \Y $ternary$libresoc.v:42104$1507_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41542$1515 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42110$1513 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1028 - connect \Y $ternary$libresoc.v:41542$1515_Y + connect \S \wp$1020 + connect \Y $ternary$libresoc.v:42110$1513_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41548$1521 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42116$1519 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1050 - connect \Y $ternary$libresoc.v:41548$1521_Y + connect \S \wp$1038 + connect \Y $ternary$libresoc.v:42116$1519_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41554$1527 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42122$1525 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1070 - connect \Y $ternary$libresoc.v:41554$1527_Y + connect \S \wp$1060 + connect \Y $ternary$libresoc.v:42122$1525_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41560$1533 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42128$1531 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1090 - connect \Y $ternary$libresoc.v:41560$1533_Y + connect \S \wp$1080 + connect \Y $ternary$libresoc.v:42128$1531_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41566$1539 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42134$1537 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1109 - connect \Y $ternary$libresoc.v:41566$1539_Y + connect \S \wp$1100 + connect \Y $ternary$libresoc.v:42134$1537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41572$1545 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42140$1543 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1127 - connect \Y $ternary$libresoc.v:41572$1545_Y + connect \S \wp$1119 + connect \Y $ternary$libresoc.v:42140$1543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41578$1551 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42146$1549 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_rego + connect \S \wp$1137 + connect \Y $ternary$libresoc.v:42146$1549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42152$1555 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_ea - connect \S \wp$1143 - connect \Y $ternary$libresoc.v:41578$1551_Y + connect \S \wp$1153 + connect \Y $ternary$libresoc.v:42152$1555_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41612$1585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42186$1589 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_wr - connect \S \wp$1216 - connect \Y $ternary$libresoc.v:41612$1585_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41626$1599 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1250 - connect \S \wp$1244 - connect \Y $ternary$libresoc.v:41626$1599_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41634$1607 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1270 - connect \S \wp$1264 - connect \Y $ternary$libresoc.v:41634$1607_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41642$1615 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1290 - connect \S \wp$1284 - connect \Y $ternary$libresoc.v:41642$1615_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41650$1623 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1310 - connect \S \wp$1304 - connect \Y $ternary$libresoc.v:41650$1623_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41658$1631 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1330 - connect \S \wp$1324 - connect \Y $ternary$libresoc.v:41658$1631_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41666$1639 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1350 - connect \S \wp$1344 - connect \Y $ternary$libresoc.v:41666$1639_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41685$1658 + connect \S \wp$1227 + connect \Y $ternary$libresoc.v:42186$1589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42200$1603 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$1261 + connect \S \wp$1255 + connect \Y $ternary$libresoc.v:42200$1603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42208$1611 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$1281 + connect \S \wp$1275 + connect \Y $ternary$libresoc.v:42208$1611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42216$1619 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$1301 + connect \S \wp$1295 + connect \Y $ternary$libresoc.v:42216$1619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42224$1627 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$1321 + connect \S \wp$1315 + connect \Y $ternary$libresoc.v:42224$1627_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42232$1635 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$1341 + connect \S \wp$1335 + connect \Y $ternary$libresoc.v:42232$1635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42240$1643 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$1361 + connect \S \wp$1355 + connect \Y $ternary$libresoc.v:42240$1643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42259$1662 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1391 - connect \Y $ternary$libresoc.v:41685$1658_Y + connect \S \wp$1402 + connect \Y $ternary$libresoc.v:42259$1662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41691$1664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42265$1668 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1407 - connect \Y $ternary$libresoc.v:41691$1664_Y + connect \S \wp$1418 + connect \Y $ternary$libresoc.v:42265$1668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41697$1670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42271$1674 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1423 - connect \Y $ternary$libresoc.v:41697$1670_Y + connect \S \wp$1434 + connect \Y $ternary$libresoc.v:42271$1674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41712$1686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42286$1690 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1457 - connect \Y $ternary$libresoc.v:41712$1686_Y + connect \S \wp$1468 + connect \Y $ternary$libresoc.v:42286$1690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41718$1692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42292$1696 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1473 - connect \Y $ternary$libresoc.v:41718$1692_Y + connect \S \wp$1484 + connect \Y $ternary$libresoc.v:42292$1696_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41724$1698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42298$1702 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1489 - connect \Y $ternary$libresoc.v:41724$1698_Y + connect \S \wp$1500 + connect \Y $ternary$libresoc.v:42298$1702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41730$1704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42304$1708 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1505 - connect \Y $ternary$libresoc.v:41730$1704_Y + connect \S \wp$1516 + connect \Y $ternary$libresoc.v:42304$1708_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41746$1720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42320$1724 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1541 - connect \Y $ternary$libresoc.v:41746$1720_Y + connect \S \wp$1552 + connect \Y $ternary$libresoc.v:42320$1724_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41752$1726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42326$1730 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1557 - connect \Y $ternary$libresoc.v:41752$1726_Y + connect \S \wp$1568 + connect \Y $ternary$libresoc.v:42326$1730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41758$1732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42332$1736 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1573 - connect \Y $ternary$libresoc.v:41758$1732_Y + connect \S \wp$1584 + connect \Y $ternary$libresoc.v:42332$1736_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41764$1738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42338$1742 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1589 - connect \Y $ternary$libresoc.v:41764$1738_Y + connect \S \wp$1600 + connect \Y $ternary$libresoc.v:42338$1742_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41783$1759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42357$1763 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1634 - connect \Y $ternary$libresoc.v:41783$1759_Y + connect \S \wp$1645 + connect \Y $ternary$libresoc.v:42357$1763_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41789$1765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42363$1769 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1650 - connect \Y $ternary$libresoc.v:41789$1765_Y + connect \S \wp$1661 + connect \Y $ternary$libresoc.v:42363$1769_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41795$1771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42369$1775 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1666 - connect \Y $ternary$libresoc.v:41795$1771_Y + connect \S \wp$1677 + connect \Y $ternary$libresoc.v:42369$1775_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41801$1777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42375$1781 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 - connect \S \wp$1682 - connect \Y $ternary$libresoc.v:41801$1777_Y + connect \S \wp$1693 + connect \Y $ternary$libresoc.v:42375$1781_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41807$1783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42381$1787 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 - connect \S \wp$1698 - connect \Y $ternary$libresoc.v:41807$1783_Y + connect \S \wp$1709 + connect \Y $ternary$libresoc.v:42381$1787_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41827$1803 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42401$1807 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1742 - connect \Y $ternary$libresoc.v:41827$1803_Y + connect \S \wp$1753 + connect \Y $ternary$libresoc.v:42401$1807_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41834$1810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42407$1813 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1758 - connect \Y $ternary$libresoc.v:41834$1810_Y + connect \S \wp$1769 + connect \Y $ternary$libresoc.v:42407$1813_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41845$1822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42417$1824 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1782 - connect \Y $ternary$libresoc.v:41845$1822_Y + connect \S \wp$1793 + connect \Y $ternary$libresoc.v:42417$1824_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41854$1832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42425$1833 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spro - connect \S \wp$1802 - connect \Y $ternary$libresoc.v:41854$1832_Y + connect \S \wp$1813 + connect \Y $ternary$libresoc.v:42425$1833_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41942$1920 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42516$1924 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_alu0_0 - connect \Y $ternary$libresoc.v:41942$1920_Y + connect \Y $ternary$libresoc.v:42516$1924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41948$1926 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42522$1930 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_cr0_1 - connect \Y $ternary$libresoc.v:41948$1926_Y + connect \Y $ternary$libresoc.v:42522$1930_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41954$1932 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42528$1936 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_trap0_2 - connect \Y $ternary$libresoc.v:41954$1932_Y + connect \Y $ternary$libresoc.v:42528$1936_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41960$1938 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42534$1942 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_logical0_3 - connect \Y $ternary$libresoc.v:41960$1938_Y + connect \Y $ternary$libresoc.v:42534$1942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41966$1944 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42540$1948 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_spr0_4 - connect \Y $ternary$libresoc.v:41966$1944_Y + connect \Y $ternary$libresoc.v:42540$1948_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41972$1950 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42546$1954 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_div0_5 - connect \Y $ternary$libresoc.v:41972$1950_Y + connect \Y $ternary$libresoc.v:42546$1954_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41978$1956 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42552$1960 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_mul0_6 - connect \Y $ternary$libresoc.v:41978$1956_Y + connect \Y $ternary$libresoc.v:42552$1960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41984$1962 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42558$1966 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $ternary$libresoc.v:41984$1962_Y + connect \Y $ternary$libresoc.v:42558$1966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:41990$1968 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42564$1972 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_ldst0_8 - connect \Y $ternary$libresoc.v:41990$1968_Y + connect \Y $ternary$libresoc.v:42564$1972_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42005$1983 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42579$1987 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_alu0_0 - connect \Y $ternary$libresoc.v:42005$1983_Y + connect \Y $ternary$libresoc.v:42579$1987_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42011$1989 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42585$1993 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_cr0_1 - connect \Y $ternary$libresoc.v:42011$1989_Y + connect \Y $ternary$libresoc.v:42585$1993_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42017$1995 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42591$1999 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_trap0_2 - connect \Y $ternary$libresoc.v:42017$1995_Y + connect \Y $ternary$libresoc.v:42591$1999_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42023$2001 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42597$2005 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_logical0_3 - connect \Y $ternary$libresoc.v:42023$2001_Y + connect \Y $ternary$libresoc.v:42597$2005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42029$2007 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42603$2011 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_div0_4 - connect \Y $ternary$libresoc.v:42029$2007_Y + connect \Y $ternary$libresoc.v:42603$2011_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42035$2013 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42609$2017 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_mul0_5 - connect \Y $ternary$libresoc.v:42035$2013_Y + connect \Y $ternary$libresoc.v:42609$2017_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42041$2019 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42615$2023 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $ternary$libresoc.v:42041$2019_Y + connect \Y $ternary$libresoc.v:42615$2023_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42047$2025 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42621$2029 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_ldst0_7 - connect \Y $ternary$libresoc.v:42047$2025_Y + connect \Y $ternary$libresoc.v:42621$2029_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42061$2039 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42635$2043 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $ternary$libresoc.v:42061$2039_Y + connect \Y $ternary$libresoc.v:42635$2043_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42067$2045 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42641$2049 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rc_ldst0_1 - connect \Y $ternary$libresoc.v:42067$2045_Y + connect \Y $ternary$libresoc.v:42641$2049_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42081$2059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42655$2063 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$libresoc.v:42081$2059_Y + connect \Y $ternary$libresoc.v:42655$2063_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42087$2065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42661$2069 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$libresoc.v:42087$2065_Y + connect \Y $ternary$libresoc.v:42661$2069_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42093$2071 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42667$2075 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$libresoc.v:42093$2071_Y + connect \Y $ternary$libresoc.v:42667$2075_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42099$2077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42673$2081 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$libresoc.v:42099$2077_Y + connect \Y $ternary$libresoc.v:42673$2081_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42105$2083 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42679$2087 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$libresoc.v:42105$2083_Y + connect \Y $ternary$libresoc.v:42679$2087_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42111$2089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42685$2093 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$libresoc.v:42111$2089_Y + connect \Y $ternary$libresoc.v:42685$2093_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42127$2106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42701$2110 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$libresoc.v:42127$2106_Y + connect \Y $ternary$libresoc.v:42701$2110_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42133$2112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42707$2116 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$libresoc.v:42133$2112_Y + connect \Y $ternary$libresoc.v:42707$2116_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42139$2118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42713$2122 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$libresoc.v:42139$2118_Y + connect \Y $ternary$libresoc.v:42713$2122_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42152$2132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42726$2136 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$libresoc.v:42152$2132_Y + connect \Y $ternary$libresoc.v:42726$2136_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42158$2138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42732$2142 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$libresoc.v:42158$2138_Y + connect \Y $ternary$libresoc.v:42732$2142_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42166$2146 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42740$2150 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$811 connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$libresoc.v:42166$2146_Y + connect \Y $ternary$libresoc.v:42740$2150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42174$2154 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42748$2158 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$827 connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$libresoc.v:42174$2154_Y + connect \Y $ternary$libresoc.v:42748$2158_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42183$2163 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42757$2167 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$846 connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$libresoc.v:42183$2163_Y + connect \Y $ternary$libresoc.v:42757$2167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42191$2171 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42765$2175 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$862 connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$libresoc.v:42191$2171_Y + connect \Y $ternary$libresoc.v:42765$2175_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42197$2177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42771$2181 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$libresoc.v:42197$2177_Y + connect \Y $ternary$libresoc.v:42771$2181_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42203$2183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42777$2187 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$libresoc.v:42203$2183_Y + connect \Y $ternary$libresoc.v:42777$2187_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42209$2189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42783$2193 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$libresoc.v:42209$2189_Y + connect \Y $ternary$libresoc.v:42783$2193_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42218$2198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42792$2202 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_branch0_0 - connect \Y $ternary$libresoc.v:42218$2198_Y + connect \Y $ternary$libresoc.v:42792$2202_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42224$2204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42798$2208 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_trap0_1 - connect \Y $ternary$libresoc.v:42224$2204_Y + connect \Y $ternary$libresoc.v:42798$2208_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42232$2212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42806$2216 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$libresoc.v:42232$2212_Y + connect \Y $ternary$libresoc.v:42806$2216_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:42249$2229 - parameter \WIDTH 5 - connect \A 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42823$2233 + parameter \WIDTH 7 + connect \A 7'0000000 connect \B \core_rego connect \S \wp - connect \Y $ternary$libresoc.v:42249$2229_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:42255$2235 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$989 - connect \Y $ternary$libresoc.v:42255$2235_Y + connect \Y $ternary$libresoc.v:42823$2233_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:42416.6-42433.4" + attribute \src "libresoc.v:42986.6-43003.4" cell \cr \cr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73171,7 +73756,7 @@ module \core connect \wen \cr_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:42434.11-42455.4" + attribute \src "libresoc.v:43004.11-43026.4" cell \dec_ALU \dec_ALU connect \ALU__data_len \dec_ALU_ALU__data_len connect \ALU__fn_unit \dec_ALU_ALU__fn_unit @@ -73193,9 +73778,10 @@ module \core connect \ALU__zero_a \dec_ALU_ALU__zero_a connect \bigendian \dec_ALU_bigendian connect \raw_opcode_in \dec_ALU_raw_opcode_in + connect \sv_a_nz \dec_ALU_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:42456.14-42468.4" + attribute \src "libresoc.v:43027.14-43039.4" cell \dec_BRANCH \dec_BRANCH connect \BRANCH__cia \dec_BRANCH_BRANCH__cia connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit @@ -73210,7 +73796,7 @@ module \core connect \raw_opcode_in \dec_BRANCH_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42469.10-42475.4" + attribute \src "libresoc.v:43040.10-43046.4" cell \dec_CR \dec_CR connect \CR__fn_unit \dec_CR_CR__fn_unit connect \CR__insn \dec_CR_CR__insn @@ -73219,7 +73805,7 @@ module \core connect \raw_opcode_in \dec_CR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42476.11-42497.4" + attribute \src "libresoc.v:43047.11-43069.4" cell \dec_DIV \dec_DIV connect \DIV__data_len \dec_DIV_DIV__data_len connect \DIV__fn_unit \dec_DIV_DIV__fn_unit @@ -73241,9 +73827,10 @@ module \core connect \DIV__zero_a \dec_DIV_DIV__zero_a connect \bigendian \dec_DIV_bigendian connect \raw_opcode_in \dec_DIV_raw_opcode_in + connect \sv_a_nz \dec_DIV_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:42498.12-42517.4" + attribute \src "libresoc.v:43070.12-43090.4" cell \dec_LDST \dec_LDST connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse connect \LDST__data_len \dec_LDST_LDST__data_len @@ -73263,9 +73850,10 @@ module \core connect \LDST__zero_a \dec_LDST_LDST__zero_a connect \bigendian \dec_LDST_bigendian connect \raw_opcode_in \dec_LDST_raw_opcode_in + connect \sv_a_nz \dec_LDST_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:42518.15-42539.4" + attribute \src "libresoc.v:43091.15-43113.4" cell \dec_LOGICAL \dec_LOGICAL connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit @@ -73287,9 +73875,10 @@ module \core connect \LOGICAL__zero_a \dec_LOGICAL_LOGICAL__zero_a connect \bigendian \dec_LOGICAL_bigendian connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + connect \sv_a_nz \dec_LOGICAL_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:42540.11-42555.4" + attribute \src "libresoc.v:43114.11-43129.4" cell \dec_MUL \dec_MUL connect \MUL__fn_unit \dec_MUL_MUL__fn_unit connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data @@ -73307,7 +73896,7 @@ module \core connect \raw_opcode_in \dec_MUL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42556.17-42576.4" + attribute \src "libresoc.v:43130.17-43150.4" cell \dec_SHIFT_ROT \dec_SHIFT_ROT connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data @@ -73330,7 +73919,7 @@ module \core connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42577.11-42584.4" + attribute \src "libresoc.v:43151.11-43158.4" cell \dec_SPR \dec_SPR connect \SPR__fn_unit \dec_SPR_SPR__fn_unit connect \SPR__insn \dec_SPR_SPR__insn @@ -73340,7 +73929,7 @@ module \core connect \raw_opcode_in \dec_SPR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42585.8-42603.4" + attribute \src "libresoc.v:43159.8-43177.4" cell \fast \fast connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73348,7 +73937,7 @@ module \core connect \dest1__data_i \fast_dest1__data_i connect \dest1__wen \fast_dest1__wen connect \issue__addr \issue__addr - connect \issue__addr$1 \issue__addr$10 + connect \issue__addr$1 \issue__addr$12 connect \issue__data_i \issue__data_i connect \issue__data_o \issue__data_o connect \issue__ren \issue__ren @@ -73361,131 +73950,131 @@ module \core connect \src2__ren \fast_src2__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:42604.7-42935.4" + attribute \src "libresoc.v:43178.7-43509.4" cell \fus \fus connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \fus_cr_a_ok - connect \cr_a_ok$110 \fus_cr_a_ok$120 - connect \cr_a_ok$111 \fus_cr_a_ok$121 - connect \cr_a_ok$112 \fus_cr_a_ok$122 - connect \cr_a_ok$113 \fus_cr_a_ok$123 - connect \cr_a_ok$114 \fus_cr_a_ok$124 + connect \cr_a_ok$110 \fus_cr_a_ok$122 + connect \cr_a_ok$111 \fus_cr_a_ok$123 + connect \cr_a_ok$112 \fus_cr_a_ok$124 + connect \cr_a_ok$113 \fus_cr_a_ok$125 + connect \cr_a_ok$114 \fus_cr_a_ok$126 connect \cu_ad__go_i \cu_ad__go_i connect \cu_ad__rel_o \cu_ad__rel_o connect \cu_busy_o \fus_cu_busy_o - connect \cu_busy_o$11 \fus_cu_busy_o$21 - connect \cu_busy_o$14 \fus_cu_busy_o$24 - connect \cu_busy_o$17 \fus_cu_busy_o$27 - connect \cu_busy_o$2 \fus_cu_busy_o$12 - connect \cu_busy_o$20 \fus_cu_busy_o$30 - connect \cu_busy_o$23 \fus_cu_busy_o$33 - connect \cu_busy_o$26 \fus_cu_busy_o$36 - connect \cu_busy_o$5 \fus_cu_busy_o$15 - connect \cu_busy_o$8 \fus_cu_busy_o$18 + connect \cu_busy_o$11 \fus_cu_busy_o$23 + connect \cu_busy_o$14 \fus_cu_busy_o$26 + connect \cu_busy_o$17 \fus_cu_busy_o$29 + connect \cu_busy_o$2 \fus_cu_busy_o$14 + connect \cu_busy_o$20 \fus_cu_busy_o$32 + connect \cu_busy_o$23 \fus_cu_busy_o$35 + connect \cu_busy_o$26 \fus_cu_busy_o$38 + connect \cu_busy_o$5 \fus_cu_busy_o$17 + connect \cu_busy_o$8 \fus_cu_busy_o$20 connect \cu_issue_i \fus_cu_issue_i - connect \cu_issue_i$1 \fus_cu_issue_i$11 - connect \cu_issue_i$10 \fus_cu_issue_i$20 - connect \cu_issue_i$13 \fus_cu_issue_i$23 - connect \cu_issue_i$16 \fus_cu_issue_i$26 - connect \cu_issue_i$19 \fus_cu_issue_i$29 - connect \cu_issue_i$22 \fus_cu_issue_i$32 - connect \cu_issue_i$25 \fus_cu_issue_i$35 - connect \cu_issue_i$4 \fus_cu_issue_i$14 - connect \cu_issue_i$7 \fus_cu_issue_i$17 + connect \cu_issue_i$1 \fus_cu_issue_i$13 + connect \cu_issue_i$10 \fus_cu_issue_i$22 + connect \cu_issue_i$13 \fus_cu_issue_i$25 + connect \cu_issue_i$16 \fus_cu_issue_i$28 + connect \cu_issue_i$19 \fus_cu_issue_i$31 + connect \cu_issue_i$22 \fus_cu_issue_i$34 + connect \cu_issue_i$25 \fus_cu_issue_i$37 + connect \cu_issue_i$4 \fus_cu_issue_i$16 + connect \cu_issue_i$7 \fus_cu_issue_i$19 connect \cu_rd__go_i \fus_cu_rd__go_i - connect \cu_rd__go_i$29 \fus_cu_rd__go_i$39 - connect \cu_rd__go_i$32 \fus_cu_rd__go_i$42 - connect \cu_rd__go_i$35 \fus_cu_rd__go_i$45 - connect \cu_rd__go_i$38 \fus_cu_rd__go_i$48 - connect \cu_rd__go_i$41 \fus_cu_rd__go_i$51 - connect \cu_rd__go_i$44 \fus_cu_rd__go_i$54 - connect \cu_rd__go_i$47 \fus_cu_rd__go_i$57 - connect \cu_rd__go_i$50 \fus_cu_rd__go_i$60 - connect \cu_rd__go_i$70 \fus_cu_rd__go_i$80 + connect \cu_rd__go_i$29 \fus_cu_rd__go_i$41 + connect \cu_rd__go_i$32 \fus_cu_rd__go_i$44 + connect \cu_rd__go_i$35 \fus_cu_rd__go_i$47 + connect \cu_rd__go_i$38 \fus_cu_rd__go_i$50 + connect \cu_rd__go_i$41 \fus_cu_rd__go_i$53 + connect \cu_rd__go_i$44 \fus_cu_rd__go_i$56 + connect \cu_rd__go_i$47 \fus_cu_rd__go_i$59 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$62 + connect \cu_rd__go_i$70 \fus_cu_rd__go_i$82 connect \cu_rd__rel_o \fus_cu_rd__rel_o - connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$38 - connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$41 - connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$44 - connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$47 - connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$50 - connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$53 - connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$56 - connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$59 - connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$79 + connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$40 + connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$43 + connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$46 + connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$49 + connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$52 + connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$55 + connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$58 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$61 + connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$81 connect \cu_rdmaskn_i \fus_cu_rdmaskn_i - connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$22 - connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$25 - connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$28 - connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$31 - connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$34 - connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$37 - connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$13 - connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$16 - connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$19 + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$24 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$27 + connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$30 + connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$33 + connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$36 + connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$39 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$15 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$18 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$21 connect \cu_st__go_i \cu_st__go_i connect \cu_st__rel_o \cu_st__rel_o connect \cu_wr__go_i \fus_cu_wr__go_i - connect \cu_wr__go_i$100 \fus_cu_wr__go_i$110 - connect \cu_wr__go_i$102 \fus_cu_wr__go_i$112 - connect \cu_wr__go_i$137 \fus_cu_wr__go_i$147 - connect \cu_wr__go_i$82 \fus_cu_wr__go_i$92 - connect \cu_wr__go_i$85 \fus_cu_wr__go_i$95 - connect \cu_wr__go_i$88 \fus_cu_wr__go_i$98 - connect \cu_wr__go_i$91 \fus_cu_wr__go_i$101 - connect \cu_wr__go_i$94 \fus_cu_wr__go_i$104 - connect \cu_wr__go_i$97 \fus_cu_wr__go_i$107 + connect \cu_wr__go_i$100 \fus_cu_wr__go_i$112 + connect \cu_wr__go_i$102 \fus_cu_wr__go_i$114 + connect \cu_wr__go_i$137 \fus_cu_wr__go_i$149 + connect \cu_wr__go_i$82 \fus_cu_wr__go_i$94 + connect \cu_wr__go_i$85 \fus_cu_wr__go_i$97 + connect \cu_wr__go_i$88 \fus_cu_wr__go_i$100 + connect \cu_wr__go_i$91 \fus_cu_wr__go_i$103 + connect \cu_wr__go_i$94 \fus_cu_wr__go_i$106 + connect \cu_wr__go_i$97 \fus_cu_wr__go_i$109 connect \cu_wr__rel_o \fus_cu_wr__rel_o - connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$111 - connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$146 - connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$91 - connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$94 - connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$97 - connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$100 - connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$103 - connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$106 - connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$109 + connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$113 + connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$148 + connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$93 + connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$96 + connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$99 + connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$102 + connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$105 + connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$108 + connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$111 connect \dest1_o \fus_dest1_o - connect \dest1_o$103 \fus_dest1_o$113 - connect \dest1_o$104 \fus_dest1_o$114 - connect \dest1_o$105 \fus_dest1_o$115 - connect \dest1_o$106 \fus_dest1_o$116 - connect \dest1_o$107 \fus_dest1_o$117 - connect \dest1_o$108 \fus_dest1_o$118 - connect \dest1_o$109 \fus_dest1_o$119 - connect \dest1_o$141 \fus_dest1_o$151 + connect \dest1_o$103 \fus_dest1_o$115 + connect \dest1_o$104 \fus_dest1_o$116 + connect \dest1_o$105 \fus_dest1_o$117 + connect \dest1_o$106 \fus_dest1_o$118 + connect \dest1_o$107 \fus_dest1_o$119 + connect \dest1_o$108 \fus_dest1_o$120 + connect \dest1_o$109 \fus_dest1_o$121 + connect \dest1_o$141 \fus_dest1_o$153 connect \dest2_o \fus_dest2_o - connect \dest2_o$115 \fus_dest2_o$125 - connect \dest2_o$116 \fus_dest2_o$126 - connect \dest2_o$117 \fus_dest2_o$127 - connect \dest2_o$118 \fus_dest2_o$128 - connect \dest2_o$119 \fus_dest2_o$129 - connect \dest2_o$142 \fus_dest2_o$152 - connect \dest2_o$144 \fus_dest2_o$154 - connect \dest2_o$150 \fus_dest2_o$160 + connect \dest2_o$115 \fus_dest2_o$127 + connect \dest2_o$116 \fus_dest2_o$128 + connect \dest2_o$117 \fus_dest2_o$129 + connect \dest2_o$118 \fus_dest2_o$130 + connect \dest2_o$119 \fus_dest2_o$131 + connect \dest2_o$142 \fus_dest2_o$154 + connect \dest2_o$144 \fus_dest2_o$156 + connect \dest2_o$150 \fus_dest2_o$162 connect \dest3_o \fus_dest3_o - connect \dest3_o$122 \fus_dest3_o$132 - connect \dest3_o$123 \fus_dest3_o$133 - connect \dest3_o$127 \fus_dest3_o$137 - connect \dest3_o$128 \fus_dest3_o$138 - connect \dest3_o$143 \fus_dest3_o$153 - connect \dest3_o$145 \fus_dest3_o$155 - connect \dest3_o$147 \fus_dest3_o$157 + connect \dest3_o$122 \fus_dest3_o$134 + connect \dest3_o$123 \fus_dest3_o$135 + connect \dest3_o$127 \fus_dest3_o$139 + connect \dest3_o$128 \fus_dest3_o$140 + connect \dest3_o$143 \fus_dest3_o$155 + connect \dest3_o$145 \fus_dest3_o$157 + connect \dest3_o$147 \fus_dest3_o$159 connect \dest4_o \fus_dest4_o - connect \dest4_o$133 \fus_dest4_o$143 - connect \dest4_o$134 \fus_dest4_o$144 - connect \dest4_o$135 \fus_dest4_o$145 - connect \dest4_o$148 \fus_dest4_o$158 + connect \dest4_o$133 \fus_dest4_o$145 + connect \dest4_o$134 \fus_dest4_o$146 + connect \dest4_o$135 \fus_dest4_o$147 + connect \dest4_o$148 \fus_dest4_o$160 connect \dest5_o \fus_dest5_o - connect \dest5_o$132 \fus_dest5_o$142 - connect \dest5_o$149 \fus_dest5_o$159 + connect \dest5_o$132 \fus_dest5_o$144 + connect \dest5_o$149 \fus_dest5_o$161 connect \dest6_o \fus_dest6_o connect \ea \fus_ea connect \fast1_ok \fus_fast1_ok - connect \fast1_ok$138 \fus_fast1_ok$148 - connect \fast1_ok$139 \fus_fast1_ok$149 + connect \fast1_ok$138 \fus_fast1_ok$150 + connect \fast1_ok$139 \fus_fast1_ok$151 connect \fast2_ok \fus_fast2_ok - connect \fast2_ok$140 \fus_fast2_ok$150 + connect \fast2_ok$140 \fus_fast2_ok$152 connect \full_cr_ok \fus_full_cr_ok connect \ldst_port0_addr_i \fus_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok @@ -73493,13 +74082,13 @@ module \core connect \ldst_port0_busy_o \fus_ldst_port0_busy_o connect \ldst_port0_data_len \fus_ldst_port0_data_len connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$151 \fus_ldst_port0_exc_$signal$161 - connect \ldst_port0_exc_$signal$152 \fus_ldst_port0_exc_$signal$162 - connect \ldst_port0_exc_$signal$153 \fus_ldst_port0_exc_$signal$163 - connect \ldst_port0_exc_$signal$154 \fus_ldst_port0_exc_$signal$164 - connect \ldst_port0_exc_$signal$155 \fus_ldst_port0_exc_$signal$165 - connect \ldst_port0_exc_$signal$156 \fus_ldst_port0_exc_$signal$166 - connect \ldst_port0_exc_$signal$157 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_exc_$signal$151 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$152 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$153 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$154 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$155 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_exc_$signal$156 \fus_ldst_port0_exc_$signal$168 + connect \ldst_port0_exc_$signal$157 \fus_ldst_port0_exc_$signal$169 connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o @@ -73508,16 +74097,16 @@ module \core connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok connect \msr_ok \fus_msr_ok connect \nia_ok \fus_nia_ok - connect \nia_ok$146 \fus_nia_ok$156 + connect \nia_ok$146 \fus_nia_ok$158 connect \o \fus_o connect \o_ok \fus_o_ok - connect \o_ok$80 \fus_o_ok$90 - connect \o_ok$83 \fus_o_ok$93 - connect \o_ok$86 \fus_o_ok$96 - connect \o_ok$89 \fus_o_ok$99 - connect \o_ok$92 \fus_o_ok$102 - connect \o_ok$95 \fus_o_ok$105 - connect \o_ok$98 \fus_o_ok$108 + connect \o_ok$80 \fus_o_ok$92 + connect \o_ok$83 \fus_o_ok$95 + connect \o_ok$86 \fus_o_ok$98 + connect \o_ok$89 \fus_o_ok$101 + connect \o_ok$92 \fus_o_ok$104 + connect \o_ok$95 \fus_o_ok$107 + connect \o_ok$98 \fus_o_ok$110 connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data @@ -73643,59 +74232,59 @@ module \core connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a connect \spr1_ok \fus_spr1_ok connect \src1_i \fus_src1_i - connect \src1_i$30 \fus_src1_i$40 - connect \src1_i$33 \fus_src1_i$43 - connect \src1_i$36 \fus_src1_i$46 - connect \src1_i$39 \fus_src1_i$49 - connect \src1_i$42 \fus_src1_i$52 - connect \src1_i$45 \fus_src1_i$55 - connect \src1_i$48 \fus_src1_i$58 - connect \src1_i$51 \fus_src1_i$61 - connect \src1_i$74 \fus_src1_i$84 + connect \src1_i$30 \fus_src1_i$42 + connect \src1_i$33 \fus_src1_i$45 + connect \src1_i$36 \fus_src1_i$48 + connect \src1_i$39 \fus_src1_i$51 + connect \src1_i$42 \fus_src1_i$54 + connect \src1_i$45 \fus_src1_i$57 + connect \src1_i$48 \fus_src1_i$60 + connect \src1_i$51 \fus_src1_i$63 + connect \src1_i$74 \fus_src1_i$86 connect \src2_i \fus_src2_i - connect \src2_i$52 \fus_src2_i$62 - connect \src2_i$53 \fus_src2_i$63 - connect \src2_i$54 \fus_src2_i$64 - connect \src2_i$55 \fus_src2_i$65 - connect \src2_i$56 \fus_src2_i$66 - connect \src2_i$57 \fus_src2_i$67 - connect \src2_i$58 \fus_src2_i$68 - connect \src2_i$77 \fus_src2_i$87 - connect \src2_i$79 \fus_src2_i$89 + connect \src2_i$52 \fus_src2_i$64 + connect \src2_i$53 \fus_src2_i$65 + connect \src2_i$54 \fus_src2_i$66 + connect \src2_i$55 \fus_src2_i$67 + connect \src2_i$56 \fus_src2_i$68 + connect \src2_i$57 \fus_src2_i$69 + connect \src2_i$58 \fus_src2_i$70 + connect \src2_i$77 \fus_src2_i$89 + connect \src2_i$79 \fus_src2_i$91 connect \src3_i \fus_src3_i - connect \src3_i$59 \fus_src3_i$69 - connect \src3_i$60 \fus_src3_i$70 - connect \src3_i$61 \fus_src3_i$71 - connect \src3_i$62 \fus_src3_i$72 - connect \src3_i$63 \fus_src3_i$73 - connect \src3_i$67 \fus_src3_i$77 - connect \src3_i$71 \fus_src3_i$81 - connect \src3_i$75 \fus_src3_i$85 - connect \src3_i$76 \fus_src3_i$86 + connect \src3_i$59 \fus_src3_i$71 + connect \src3_i$60 \fus_src3_i$72 + connect \src3_i$61 \fus_src3_i$73 + connect \src3_i$62 \fus_src3_i$74 + connect \src3_i$63 \fus_src3_i$75 + connect \src3_i$67 \fus_src3_i$79 + connect \src3_i$71 \fus_src3_i$83 + connect \src3_i$75 \fus_src3_i$87 + connect \src3_i$76 \fus_src3_i$88 connect \src4_i \fus_src4_i - connect \src4_i$64 \fus_src4_i$74 - connect \src4_i$65 \fus_src4_i$75 - connect \src4_i$68 \fus_src4_i$78 - connect \src4_i$78 \fus_src4_i$88 + connect \src4_i$64 \fus_src4_i$76 + connect \src4_i$65 \fus_src4_i$77 + connect \src4_i$68 \fus_src4_i$80 + connect \src4_i$78 \fus_src4_i$90 connect \src5_i \fus_src5_i - connect \src5_i$66 \fus_src5_i$76 - connect \src5_i$72 \fus_src5_i$82 + connect \src5_i$66 \fus_src5_i$78 + connect \src5_i$72 \fus_src5_i$84 connect \src6_i \fus_src6_i - connect \src6_i$73 \fus_src6_i$83 + connect \src6_i$73 \fus_src6_i$85 connect \xer_ca_ok \fus_xer_ca_ok - connect \xer_ca_ok$120 \fus_xer_ca_ok$130 - connect \xer_ca_ok$121 \fus_xer_ca_ok$131 + connect \xer_ca_ok$120 \fus_xer_ca_ok$132 + connect \xer_ca_ok$121 \fus_xer_ca_ok$133 connect \xer_ov_ok \fus_xer_ov_ok - connect \xer_ov_ok$124 \fus_xer_ov_ok$134 - connect \xer_ov_ok$125 \fus_xer_ov_ok$135 - connect \xer_ov_ok$126 \fus_xer_ov_ok$136 + connect \xer_ov_ok$124 \fus_xer_ov_ok$136 + connect \xer_ov_ok$125 \fus_xer_ov_ok$137 + connect \xer_ov_ok$126 \fus_xer_ov_ok$138 connect \xer_so_ok \fus_xer_so_ok - connect \xer_so_ok$129 \fus_xer_so_ok$139 - connect \xer_so_ok$130 \fus_xer_so_ok$140 - connect \xer_so_ok$131 \fus_xer_so_ok$141 + connect \xer_so_ok$129 \fus_xer_so_ok$141 + connect \xer_so_ok$130 \fus_xer_so_ok$142 + connect \xer_so_ok$131 \fus_xer_so_ok$143 end attribute \module_not_derived 1 - attribute \src "libresoc.v:42936.9-42954.4" + attribute \src "libresoc.v:43510.9-43528.4" cell \int \int connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73716,7 +74305,7 @@ module \core connect \src3__ren \int_src3__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:42955.6-42987.4" + attribute \src "libresoc.v:43529.6-43561.4" cell \l0 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73735,13 +74324,13 @@ module \core connect \ldst_port0_busy_o \fus_ldst_port0_busy_o connect \ldst_port0_data_len \fus_ldst_port0_data_len connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$1 \fus_ldst_port0_exc_$signal$161 - connect \ldst_port0_exc_$signal$2 \fus_ldst_port0_exc_$signal$162 - connect \ldst_port0_exc_$signal$3 \fus_ldst_port0_exc_$signal$163 - connect \ldst_port0_exc_$signal$4 \fus_ldst_port0_exc_$signal$164 - connect \ldst_port0_exc_$signal$5 \fus_ldst_port0_exc_$signal$165 - connect \ldst_port0_exc_$signal$6 \fus_ldst_port0_exc_$signal$166 - connect \ldst_port0_exc_$signal$7 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_exc_$signal$1 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$2 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$3 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$4 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$5 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_exc_$signal$6 \fus_ldst_port0_exc_$signal$168 + connect \ldst_port0_exc_$signal$7 \fus_ldst_port0_exc_$signal$169 connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o @@ -73751,202 +74340,206 @@ module \core connect \wb_dcache_en \wb_dcache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:42988.18-42992.4" + attribute \src "libresoc.v:43562.18-43566.4" cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \en_o \rdpick_CR_cr_a_en_o connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42993.18-42997.4" + attribute \src "libresoc.v:43567.18-43571.4" cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \en_o \rdpick_CR_cr_b_en_o connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42998.18-43002.4" + attribute \src "libresoc.v:43572.18-43576.4" cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \en_o \rdpick_CR_cr_c_en_o connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43003.21-43007.4" + attribute \src "libresoc.v:43577.21-43581.4" cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \en_o \rdpick_CR_full_cr_en_o connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43008.21-43012.4" + attribute \src "libresoc.v:43582.21-43586.4" cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \en_o \rdpick_FAST_fast1_en_o connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43013.21-43017.4" + attribute \src "libresoc.v:43587.21-43591.4" cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 connect \en_o \rdpick_FAST_fast2_en_o connect \i \rdpick_FAST_fast2_i connect \o \rdpick_FAST_fast2_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43018.17-43022.4" + attribute \src "libresoc.v:43592.17-43596.4" cell \rdpick_INT_ra \rdpick_INT_ra connect \en_o \rdpick_INT_ra_en_o connect \i \rdpick_INT_ra_i connect \o \rdpick_INT_ra_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43023.17-43027.4" + attribute \src "libresoc.v:43597.17-43601.4" cell \rdpick_INT_rb \rdpick_INT_rb connect \en_o \rdpick_INT_rb_en_o connect \i \rdpick_INT_rb_i connect \o \rdpick_INT_rb_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43028.17-43032.4" + attribute \src "libresoc.v:43602.17-43606.4" cell \rdpick_INT_rc \rdpick_INT_rc connect \en_o \rdpick_INT_rc_en_o connect \i \rdpick_INT_rc_i connect \o \rdpick_INT_rc_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43033.19-43037.4" + attribute \src "libresoc.v:43607.19-43611.4" cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \en_o \rdpick_SPR_spr1_en_o connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43038.21-43042.4" + attribute \src "libresoc.v:43612.21-43616.4" cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43043.21-43047.4" + attribute \src "libresoc.v:43617.21-43621.4" cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \en_o \rdpick_XER_xer_ov_en_o connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43048.21-43052.4" + attribute \src "libresoc.v:43622.21-43626.4" cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43053.7-43062.4" + attribute \src "libresoc.v:43627.7-43636.4" cell \spr \spr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \spr1__addr \spr_spr1__addr - connect \spr1__addr$1 \spr_spr1__addr$173 + connect \spr1__addr$1 \spr_spr1__addr$175 connect \spr1__data_i \spr_spr1__data_i connect \spr1__data_o \spr_spr1__data_o connect \spr1__ren \spr_spr1__ren connect \spr1__wen \spr_spr1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43063.9-43076.4" + attribute \src "libresoc.v:43637.9-43654.4" cell \state \state connect \cia__data_o \cia__data_o connect \cia__ren \cia__ren connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \data_i \data_i - connect \data_i$1 \state_data_i - connect \data_i$2 \state_data_i$172 + connect \data_i$2 \data_i$11 + connect \data_i$3 \state_data_i + connect \data_i$4 \state_data_i$174 connect \msr__data_o \msr__data_o connect \msr__ren \msr__ren connect \state_nia_wen \state_nia_wen + connect \sv__data_o \sv__data_o + connect \sv__ren \sv__ren connect \wen \wen - connect \wen$3 \state_wen + connect \wen$1 \wen$10 + connect \wen$5 \state_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43077.18-43081.4" + attribute \src "libresoc.v:43655.18-43659.4" cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43082.21-43086.4" + attribute \src "libresoc.v:43660.21-43664.4" cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \en_o \wrpick_CR_full_cr_en_o connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43087.21-43091.4" + attribute \src "libresoc.v:43665.21-43669.4" cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \en_o \wrpick_FAST_fast1_en_o connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43092.16-43096.4" + attribute \src "libresoc.v:43670.16-43674.4" cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43097.19-43101.4" + attribute \src "libresoc.v:43675.19-43679.4" cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \en_o \wrpick_SPR_spr1_en_o connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43102.20-43106.4" + attribute \src "libresoc.v:43680.20-43684.4" cell \wrpick_STATE_msr \wrpick_STATE_msr connect \en_o \wrpick_STATE_msr_en_o connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43107.20-43111.4" + attribute \src "libresoc.v:43685.20-43689.4" cell \wrpick_STATE_nia \wrpick_STATE_nia connect \en_o \wrpick_STATE_nia_en_o connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43112.21-43116.4" + attribute \src "libresoc.v:43690.21-43694.4" cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43117.21-43121.4" + attribute \src "libresoc.v:43695.21-43699.4" cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43122.21-43126.4" + attribute \src "libresoc.v:43700.21-43704.4" cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43127.7-43144.4" + attribute \src "libresoc.v:43705.7-43722.4" cell \xer \xer connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \data_i \xer_data_i - connect \data_i$1 \xer_data_i$168 - connect \data_i$3 \xer_data_i$170 + connect \data_i$1 \xer_data_i$170 + connect \data_i$3 \xer_data_i$172 connect \full_rd__data_o \full_rd__data_o connect \full_rd__ren \full_rd__ren connect \src1__data_o \xer_src1__data_o @@ -73956,1400 +74549,1805 @@ module \core connect \src3__data_o \xer_src3__data_o connect \src3__ren \xer_src3__ren connect \wen \xer_wen - connect \wen$2 \xer_wen$169 - connect \wen$4 \xer_wen$171 + connect \wen$2 \xer_wen$171 + connect \wen$4 \xer_wen$173 end - attribute \src "libresoc.v:35746.7-35746.20" - process $proc$libresoc.v:35746$2900 + attribute \src "libresoc.v:36214.7-36214.20" + process $proc$libresoc.v:36214$2900 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:37778.7-37778.30" - process $proc$libresoc.v:37778$2901 + attribute \src "libresoc.v:38263.7-38263.30" + process $proc$libresoc.v:38263$2901 assign { } { } assign $1\core_terminate_o[0:0] 1'0 sync always sync init update \core_terminate_o $1\core_terminate_o[0:0] end - attribute \src "libresoc.v:37791.13-37791.27" - process $proc$libresoc.v:37791$2902 + attribute \src "libresoc.v:38276.13-38276.27" + process $proc$libresoc.v:38276$2902 assign { } { } assign $1\counter[1:0] 2'00 sync always sync init update \counter $1\counter[1:0] end - attribute \src "libresoc.v:38921.7-38921.34" - process $proc$libresoc.v:38921$2903 + attribute \src "libresoc.v:39443.7-39443.34" + process $proc$libresoc.v:39443$2903 assign { } { } assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 sync always sync init update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:38925.7-38925.30" - process $proc$libresoc.v:38925$2904 + attribute \src "libresoc.v:39447.7-39447.30" + process $proc$libresoc.v:39447$2904 assign { } { } assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:38929.7-38929.30" - process $proc$libresoc.v:38929$2905 + attribute \src "libresoc.v:39451.7-39451.30" + process $proc$libresoc.v:39451$2905 assign { } { } assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:38933.7-38933.30" - process $proc$libresoc.v:38933$2906 + attribute \src "libresoc.v:39455.7-39455.30" + process $proc$libresoc.v:39455$2906 assign { } { } assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:38937.7-38937.33" - process $proc$libresoc.v:38937$2907 + attribute \src "libresoc.v:39459.7-39459.33" + process $proc$libresoc.v:39459$2907 assign { } { } assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:38941.7-38941.37" - process $proc$libresoc.v:38941$2908 + attribute \src "libresoc.v:39463.7-39463.37" + process $proc$libresoc.v:39463$2908 assign { } { } assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:38945.7-38945.34" - process $proc$libresoc.v:38945$2909 + attribute \src "libresoc.v:39467.7-39467.34" + process $proc$libresoc.v:39467$2909 assign { } { } assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 sync always sync init update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:38949.7-38949.35" - process $proc$libresoc.v:38949$2910 + attribute \src "libresoc.v:39471.7-39471.35" + process $proc$libresoc.v:39471$2910 assign { } { } assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:38953.7-38953.37" - process $proc$libresoc.v:38953$2911 + attribute \src "libresoc.v:39475.7-39475.37" + process $proc$libresoc.v:39475$2911 assign { } { } assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:38957.7-38957.35" - process $proc$libresoc.v:38957$2912 + attribute \src "libresoc.v:39479.7-39479.35" + process $proc$libresoc.v:39479$2912 assign { } { } assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:38961.7-38961.30" - process $proc$libresoc.v:38961$2913 + attribute \src "libresoc.v:39483.7-39483.30" + process $proc$libresoc.v:39483$2913 assign { } { } assign $1\dp_INT_ra_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:38965.7-38965.29" - process $proc$libresoc.v:38965$2914 + attribute \src "libresoc.v:39487.7-39487.29" + process $proc$libresoc.v:39487$2914 assign { } { } assign $1\dp_INT_ra_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:38969.7-38969.30" - process $proc$libresoc.v:38969$2915 + attribute \src "libresoc.v:39491.7-39491.30" + process $proc$libresoc.v:39491$2915 assign { } { } assign $1\dp_INT_ra_div0_5[0:0] 1'0 sync always sync init update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:38973.7-38973.31" - process $proc$libresoc.v:38973$2916 + attribute \src "libresoc.v:39495.7-39495.31" + process $proc$libresoc.v:39495$2916 assign { } { } assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 sync always sync init update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:38977.7-38977.34" - process $proc$libresoc.v:38977$2917 + attribute \src "libresoc.v:39499.7-39499.34" + process $proc$libresoc.v:39499$2917 assign { } { } assign $1\dp_INT_ra_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:38981.7-38981.30" - process $proc$libresoc.v:38981$2918 + attribute \src "libresoc.v:39503.7-39503.30" + process $proc$libresoc.v:39503$2918 assign { } { } assign $1\dp_INT_ra_mul0_6[0:0] 1'0 sync always sync init update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:38985.7-38985.35" - process $proc$libresoc.v:38985$2919 + attribute \src "libresoc.v:39507.7-39507.35" + process $proc$libresoc.v:39507$2919 assign { } { } assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 sync always sync init update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:38989.7-38989.30" - process $proc$libresoc.v:38989$2920 + attribute \src "libresoc.v:39511.7-39511.30" + process $proc$libresoc.v:39511$2920 assign { } { } assign $1\dp_INT_ra_spr0_4[0:0] 1'0 sync always sync init update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:38993.7-38993.31" - process $proc$libresoc.v:38993$2921 + attribute \src "libresoc.v:39515.7-39515.31" + process $proc$libresoc.v:39515$2921 assign { } { } assign $1\dp_INT_ra_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:38997.7-38997.30" - process $proc$libresoc.v:38997$2922 + attribute \src "libresoc.v:39519.7-39519.30" + process $proc$libresoc.v:39519$2922 assign { } { } assign $1\dp_INT_rb_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:39001.7-39001.29" - process $proc$libresoc.v:39001$2923 + attribute \src "libresoc.v:39523.7-39523.29" + process $proc$libresoc.v:39523$2923 assign { } { } assign $1\dp_INT_rb_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:39005.7-39005.30" - process $proc$libresoc.v:39005$2924 + attribute \src "libresoc.v:39527.7-39527.30" + process $proc$libresoc.v:39527$2924 assign { } { } assign $1\dp_INT_rb_div0_4[0:0] 1'0 sync always sync init update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:39009.7-39009.31" - process $proc$libresoc.v:39009$2925 + attribute \src "libresoc.v:39531.7-39531.31" + process $proc$libresoc.v:39531$2925 assign { } { } assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 sync always sync init update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:39013.7-39013.34" - process $proc$libresoc.v:39013$2926 + attribute \src "libresoc.v:39535.7-39535.34" + process $proc$libresoc.v:39535$2926 assign { } { } assign $1\dp_INT_rb_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:39017.7-39017.30" - process $proc$libresoc.v:39017$2927 + attribute \src "libresoc.v:39539.7-39539.30" + process $proc$libresoc.v:39539$2927 assign { } { } assign $1\dp_INT_rb_mul0_5[0:0] 1'0 sync always sync init update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:39021.7-39021.35" - process $proc$libresoc.v:39021$2928 + attribute \src "libresoc.v:39543.7-39543.35" + process $proc$libresoc.v:39543$2928 assign { } { } assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 sync always sync init update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:39025.7-39025.31" - process $proc$libresoc.v:39025$2929 + attribute \src "libresoc.v:39547.7-39547.31" + process $proc$libresoc.v:39547$2929 assign { } { } assign $1\dp_INT_rb_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:39029.7-39029.31" - process $proc$libresoc.v:39029$2930 + attribute \src "libresoc.v:39551.7-39551.31" + process $proc$libresoc.v:39551$2930 assign { } { } assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 sync always sync init update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:39033.7-39033.35" - process $proc$libresoc.v:39033$2931 + attribute \src "libresoc.v:39555.7-39555.35" + process $proc$libresoc.v:39555$2931 assign { } { } assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 sync always sync init update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:39037.7-39037.32" - process $proc$libresoc.v:39037$2932 + attribute \src "libresoc.v:39559.7-39559.32" + process $proc$libresoc.v:39559$2932 assign { } { } assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 sync always sync init update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:39041.7-39041.34" - process $proc$libresoc.v:39041$2933 + attribute \src "libresoc.v:39563.7-39563.34" + process $proc$libresoc.v:39563$2933 assign { } { } assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:39045.7-39045.39" - process $proc$libresoc.v:39045$2934 + attribute \src "libresoc.v:39567.7-39567.39" + process $proc$libresoc.v:39567$2934 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:39049.7-39049.34" - process $proc$libresoc.v:39049$2935 + attribute \src "libresoc.v:39571.7-39571.34" + process $proc$libresoc.v:39571$2935 assign { } { } assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:39053.7-39053.34" - process $proc$libresoc.v:39053$2936 + attribute \src "libresoc.v:39575.7-39575.34" + process $proc$libresoc.v:39575$2936 assign { } { } assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:39057.7-39057.34" - process $proc$libresoc.v:39057$2937 + attribute \src "libresoc.v:39579.7-39579.34" + process $proc$libresoc.v:39579$2937 assign { } { } assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:39061.7-39061.34" - process $proc$libresoc.v:39061$2938 + attribute \src "libresoc.v:39583.7-39583.34" + process $proc$libresoc.v:39583$2938 assign { } { } assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 sync always sync init update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:39065.7-39065.38" - process $proc$libresoc.v:39065$2939 + attribute \src "libresoc.v:39587.7-39587.38" + process $proc$libresoc.v:39587$2939 assign { } { } assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:39069.7-39069.34" - process $proc$libresoc.v:39069$2940 + attribute \src "libresoc.v:39591.7-39591.34" + process $proc$libresoc.v:39591$2940 assign { } { } assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 sync always sync init update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:39073.7-39073.39" - process $proc$libresoc.v:39073$2941 + attribute \src "libresoc.v:39595.7-39595.39" + process $proc$libresoc.v:39595$2941 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 sync always sync init update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:39077.7-39077.34" - process $proc$libresoc.v:39077$2942 + attribute \src "libresoc.v:39599.7-39599.34" + process $proc$libresoc.v:39599$2942 assign { } { } assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:41154.7-41154.25" - process $proc$libresoc.v:41154$2943 + attribute \src "libresoc.v:41724.7-41724.25" + process $proc$libresoc.v:41724$2943 assign { } { } assign $1\wr_pick_dly[0:0] 1'0 sync always sync init update \wr_pick_dly $1\wr_pick_dly[0:0] end - attribute \src "libresoc.v:41156.7-41156.32" - process $proc$libresoc.v:41156$2944 + attribute \src "libresoc.v:41726.7-41726.32" + process $proc$libresoc.v:41726$2944 assign { } { } - assign $0\wr_pick_dly$1000[0:0]$2945 1'0 + assign $0\wr_pick_dly$1010[0:0]$2945 1'0 sync always sync init - update \wr_pick_dly$1000 $0\wr_pick_dly$1000[0:0]$2945 + update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2945 end - attribute \src "libresoc.v:41160.7-41160.32" - process $proc$libresoc.v:41160$2946 + attribute \src "libresoc.v:41730.7-41730.32" + process $proc$libresoc.v:41730$2946 assign { } { } - assign $0\wr_pick_dly$1021[0:0]$2947 1'0 + assign $0\wr_pick_dly$1031[0:0]$2947 1'0 sync always sync init - update \wr_pick_dly$1021 $0\wr_pick_dly$1021[0:0]$2947 + update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2947 end - attribute \src "libresoc.v:41164.7-41164.32" - process $proc$libresoc.v:41164$2948 + attribute \src "libresoc.v:41734.7-41734.32" + process $proc$libresoc.v:41734$2948 assign { } { } - assign $0\wr_pick_dly$1039[0:0]$2949 1'0 + assign $0\wr_pick_dly$1049[0:0]$2949 1'0 sync always sync init - update \wr_pick_dly$1039 $0\wr_pick_dly$1039[0:0]$2949 + update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2949 end - attribute \src "libresoc.v:41168.7-41168.32" - process $proc$libresoc.v:41168$2950 + attribute \src "libresoc.v:41738.7-41738.32" + process $proc$libresoc.v:41738$2950 assign { } { } - assign $0\wr_pick_dly$1061[0:0]$2951 1'0 + assign $0\wr_pick_dly$1071[0:0]$2951 1'0 sync always sync init - update \wr_pick_dly$1061 $0\wr_pick_dly$1061[0:0]$2951 + update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2951 end - attribute \src "libresoc.v:41172.7-41172.32" - process $proc$libresoc.v:41172$2952 + attribute \src "libresoc.v:41742.7-41742.32" + process $proc$libresoc.v:41742$2952 assign { } { } - assign $0\wr_pick_dly$1081[0:0]$2953 1'0 + assign $0\wr_pick_dly$1091[0:0]$2953 1'0 sync always sync init - update \wr_pick_dly$1081 $0\wr_pick_dly$1081[0:0]$2953 + update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2953 end - attribute \src "libresoc.v:41176.7-41176.32" - process $proc$libresoc.v:41176$2954 + attribute \src "libresoc.v:41746.7-41746.32" + process $proc$libresoc.v:41746$2954 assign { } { } - assign $0\wr_pick_dly$1101[0:0]$2955 1'0 + assign $0\wr_pick_dly$1111[0:0]$2955 1'0 sync always sync init - update \wr_pick_dly$1101 $0\wr_pick_dly$1101[0:0]$2955 + update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2955 end - attribute \src "libresoc.v:41180.7-41180.32" - process $proc$libresoc.v:41180$2956 + attribute \src "libresoc.v:41750.7-41750.32" + process $proc$libresoc.v:41750$2956 assign { } { } - assign $0\wr_pick_dly$1120[0:0]$2957 1'0 + assign $0\wr_pick_dly$1130[0:0]$2957 1'0 sync always sync init - update \wr_pick_dly$1120 $0\wr_pick_dly$1120[0:0]$2957 + update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2957 end - attribute \src "libresoc.v:41184.7-41184.32" - process $proc$libresoc.v:41184$2958 + attribute \src "libresoc.v:41754.7-41754.32" + process $proc$libresoc.v:41754$2958 assign { } { } - assign $0\wr_pick_dly$1138[0:0]$2959 1'0 + assign $0\wr_pick_dly$1148[0:0]$2959 1'0 sync always sync init - update \wr_pick_dly$1138 $0\wr_pick_dly$1138[0:0]$2959 + update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2959 end - attribute \src "libresoc.v:41188.7-41188.32" - process $proc$libresoc.v:41188$2960 + attribute \src "libresoc.v:41758.7-41758.32" + process $proc$libresoc.v:41758$2960 assign { } { } - assign $0\wr_pick_dly$1211[0:0]$2961 1'0 + assign $0\wr_pick_dly$1222[0:0]$2961 1'0 sync always sync init - update \wr_pick_dly$1211 $0\wr_pick_dly$1211[0:0]$2961 + update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2961 end - attribute \src "libresoc.v:41192.7-41192.32" - process $proc$libresoc.v:41192$2962 + attribute \src "libresoc.v:41762.7-41762.32" + process $proc$libresoc.v:41762$2962 assign { } { } - assign $0\wr_pick_dly$1239[0:0]$2963 1'0 + assign $0\wr_pick_dly$1250[0:0]$2963 1'0 sync always sync init - update \wr_pick_dly$1239 $0\wr_pick_dly$1239[0:0]$2963 + update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2963 end - attribute \src "libresoc.v:41196.7-41196.32" - process $proc$libresoc.v:41196$2964 + attribute \src "libresoc.v:41766.7-41766.32" + process $proc$libresoc.v:41766$2964 assign { } { } - assign $0\wr_pick_dly$1259[0:0]$2965 1'0 + assign $0\wr_pick_dly$1270[0:0]$2965 1'0 sync always sync init - update \wr_pick_dly$1259 $0\wr_pick_dly$1259[0:0]$2965 + update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2965 end - attribute \src "libresoc.v:41200.7-41200.32" - process $proc$libresoc.v:41200$2966 + attribute \src "libresoc.v:41770.7-41770.32" + process $proc$libresoc.v:41770$2966 assign { } { } - assign $0\wr_pick_dly$1279[0:0]$2967 1'0 + assign $0\wr_pick_dly$1290[0:0]$2967 1'0 sync always sync init - update \wr_pick_dly$1279 $0\wr_pick_dly$1279[0:0]$2967 + update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2967 end - attribute \src "libresoc.v:41204.7-41204.32" - process $proc$libresoc.v:41204$2968 + attribute \src "libresoc.v:41774.7-41774.32" + process $proc$libresoc.v:41774$2968 assign { } { } - assign $0\wr_pick_dly$1299[0:0]$2969 1'0 + assign $0\wr_pick_dly$1310[0:0]$2969 1'0 sync always sync init - update \wr_pick_dly$1299 $0\wr_pick_dly$1299[0:0]$2969 + update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2969 end - attribute \src "libresoc.v:41208.7-41208.32" - process $proc$libresoc.v:41208$2970 + attribute \src "libresoc.v:41778.7-41778.32" + process $proc$libresoc.v:41778$2970 assign { } { } - assign $0\wr_pick_dly$1319[0:0]$2971 1'0 + assign $0\wr_pick_dly$1330[0:0]$2971 1'0 sync always sync init - update \wr_pick_dly$1319 $0\wr_pick_dly$1319[0:0]$2971 + update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2971 end - attribute \src "libresoc.v:41212.7-41212.32" - process $proc$libresoc.v:41212$2972 + attribute \src "libresoc.v:41782.7-41782.32" + process $proc$libresoc.v:41782$2972 assign { } { } - assign $0\wr_pick_dly$1339[0:0]$2973 1'0 + assign $0\wr_pick_dly$1350[0:0]$2973 1'0 sync always sync init - update \wr_pick_dly$1339 $0\wr_pick_dly$1339[0:0]$2973 + update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2973 end - attribute \src "libresoc.v:41216.7-41216.32" - process $proc$libresoc.v:41216$2974 + attribute \src "libresoc.v:41786.7-41786.32" + process $proc$libresoc.v:41786$2974 assign { } { } - assign $0\wr_pick_dly$1386[0:0]$2975 1'0 + assign $0\wr_pick_dly$1397[0:0]$2975 1'0 sync always sync init - update \wr_pick_dly$1386 $0\wr_pick_dly$1386[0:0]$2975 + update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2975 end - attribute \src "libresoc.v:41220.7-41220.32" - process $proc$libresoc.v:41220$2976 + attribute \src "libresoc.v:41790.7-41790.32" + process $proc$libresoc.v:41790$2976 assign { } { } - assign $0\wr_pick_dly$1402[0:0]$2977 1'0 + assign $0\wr_pick_dly$1413[0:0]$2977 1'0 sync always sync init - update \wr_pick_dly$1402 $0\wr_pick_dly$1402[0:0]$2977 + update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2977 end - attribute \src "libresoc.v:41224.7-41224.32" - process $proc$libresoc.v:41224$2978 + attribute \src "libresoc.v:41794.7-41794.32" + process $proc$libresoc.v:41794$2978 assign { } { } - assign $0\wr_pick_dly$1418[0:0]$2979 1'0 + assign $0\wr_pick_dly$1429[0:0]$2979 1'0 sync always sync init - update \wr_pick_dly$1418 $0\wr_pick_dly$1418[0:0]$2979 + update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2979 end - attribute \src "libresoc.v:41228.7-41228.32" - process $proc$libresoc.v:41228$2980 + attribute \src "libresoc.v:41798.7-41798.32" + process $proc$libresoc.v:41798$2980 assign { } { } - assign $0\wr_pick_dly$1452[0:0]$2981 1'0 + assign $0\wr_pick_dly$1463[0:0]$2981 1'0 sync always sync init - update \wr_pick_dly$1452 $0\wr_pick_dly$1452[0:0]$2981 + update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2981 end - attribute \src "libresoc.v:41232.7-41232.32" - process $proc$libresoc.v:41232$2982 + attribute \src "libresoc.v:41802.7-41802.32" + process $proc$libresoc.v:41802$2982 assign { } { } - assign $0\wr_pick_dly$1468[0:0]$2983 1'0 + assign $0\wr_pick_dly$1479[0:0]$2983 1'0 sync always sync init - update \wr_pick_dly$1468 $0\wr_pick_dly$1468[0:0]$2983 + update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2983 end - attribute \src "libresoc.v:41236.7-41236.32" - process $proc$libresoc.v:41236$2984 + attribute \src "libresoc.v:41806.7-41806.32" + process $proc$libresoc.v:41806$2984 assign { } { } - assign $0\wr_pick_dly$1484[0:0]$2985 1'0 + assign $0\wr_pick_dly$1495[0:0]$2985 1'0 sync always sync init - update \wr_pick_dly$1484 $0\wr_pick_dly$1484[0:0]$2985 + update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2985 end - attribute \src "libresoc.v:41240.7-41240.32" - process $proc$libresoc.v:41240$2986 + attribute \src "libresoc.v:41810.7-41810.32" + process $proc$libresoc.v:41810$2986 assign { } { } - assign $0\wr_pick_dly$1500[0:0]$2987 1'0 + assign $0\wr_pick_dly$1511[0:0]$2987 1'0 sync always sync init - update \wr_pick_dly$1500 $0\wr_pick_dly$1500[0:0]$2987 + update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2987 end - attribute \src "libresoc.v:41244.7-41244.32" - process $proc$libresoc.v:41244$2988 + attribute \src "libresoc.v:41814.7-41814.32" + process $proc$libresoc.v:41814$2988 assign { } { } - assign $0\wr_pick_dly$1536[0:0]$2989 1'0 + assign $0\wr_pick_dly$1547[0:0]$2989 1'0 sync always sync init - update \wr_pick_dly$1536 $0\wr_pick_dly$1536[0:0]$2989 + update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2989 end - attribute \src "libresoc.v:41248.7-41248.32" - process $proc$libresoc.v:41248$2990 + attribute \src "libresoc.v:41818.7-41818.32" + process $proc$libresoc.v:41818$2990 assign { } { } - assign $0\wr_pick_dly$1552[0:0]$2991 1'0 + assign $0\wr_pick_dly$1563[0:0]$2991 1'0 sync always sync init - update \wr_pick_dly$1552 $0\wr_pick_dly$1552[0:0]$2991 + update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2991 end - attribute \src "libresoc.v:41252.7-41252.32" - process $proc$libresoc.v:41252$2992 + attribute \src "libresoc.v:41822.7-41822.32" + process $proc$libresoc.v:41822$2992 assign { } { } - assign $0\wr_pick_dly$1568[0:0]$2993 1'0 + assign $0\wr_pick_dly$1579[0:0]$2993 1'0 sync always sync init - update \wr_pick_dly$1568 $0\wr_pick_dly$1568[0:0]$2993 + update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2993 end - attribute \src "libresoc.v:41256.7-41256.32" - process $proc$libresoc.v:41256$2994 + attribute \src "libresoc.v:41826.7-41826.32" + process $proc$libresoc.v:41826$2994 assign { } { } - assign $0\wr_pick_dly$1584[0:0]$2995 1'0 + assign $0\wr_pick_dly$1595[0:0]$2995 1'0 sync always sync init - update \wr_pick_dly$1584 $0\wr_pick_dly$1584[0:0]$2995 + update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2995 end - attribute \src "libresoc.v:41260.7-41260.32" - process $proc$libresoc.v:41260$2996 + attribute \src "libresoc.v:41830.7-41830.32" + process $proc$libresoc.v:41830$2996 assign { } { } - assign $0\wr_pick_dly$1626[0:0]$2997 1'0 + assign $0\wr_pick_dly$1637[0:0]$2997 1'0 sync always sync init - update \wr_pick_dly$1626 $0\wr_pick_dly$1626[0:0]$2997 + update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2997 end - attribute \src "libresoc.v:41264.7-41264.32" - process $proc$libresoc.v:41264$2998 + attribute \src "libresoc.v:41834.7-41834.32" + process $proc$libresoc.v:41834$2998 assign { } { } - assign $0\wr_pick_dly$1645[0:0]$2999 1'0 + assign $0\wr_pick_dly$1656[0:0]$2999 1'0 sync always sync init - update \wr_pick_dly$1645 $0\wr_pick_dly$1645[0:0]$2999 + update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2999 end - attribute \src "libresoc.v:41268.7-41268.32" - process $proc$libresoc.v:41268$3000 + attribute \src "libresoc.v:41838.7-41838.32" + process $proc$libresoc.v:41838$3000 assign { } { } - assign $0\wr_pick_dly$1661[0:0]$3001 1'0 + assign $0\wr_pick_dly$1672[0:0]$3001 1'0 sync always sync init - update \wr_pick_dly$1661 $0\wr_pick_dly$1661[0:0]$3001 + update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$3001 end - attribute \src "libresoc.v:41272.7-41272.32" - process $proc$libresoc.v:41272$3002 + attribute \src "libresoc.v:41842.7-41842.32" + process $proc$libresoc.v:41842$3002 assign { } { } - assign $0\wr_pick_dly$1677[0:0]$3003 1'0 + assign $0\wr_pick_dly$1688[0:0]$3003 1'0 sync always sync init - update \wr_pick_dly$1677 $0\wr_pick_dly$1677[0:0]$3003 + update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$3003 end - attribute \src "libresoc.v:41276.7-41276.32" - process $proc$libresoc.v:41276$3004 + attribute \src "libresoc.v:41846.7-41846.32" + process $proc$libresoc.v:41846$3004 assign { } { } - assign $0\wr_pick_dly$1693[0:0]$3005 1'0 + assign $0\wr_pick_dly$1704[0:0]$3005 1'0 sync always sync init - update \wr_pick_dly$1693 $0\wr_pick_dly$1693[0:0]$3005 + update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$3005 end - attribute \src "libresoc.v:41280.7-41280.32" - process $proc$libresoc.v:41280$3006 + attribute \src "libresoc.v:41850.7-41850.32" + process $proc$libresoc.v:41850$3006 assign { } { } - assign $0\wr_pick_dly$1737[0:0]$3007 1'0 + assign $0\wr_pick_dly$1748[0:0]$3007 1'0 sync always sync init - update \wr_pick_dly$1737 $0\wr_pick_dly$1737[0:0]$3007 + update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$3007 end - attribute \src "libresoc.v:41284.7-41284.32" - process $proc$libresoc.v:41284$3008 + attribute \src "libresoc.v:41854.7-41854.32" + process $proc$libresoc.v:41854$3008 assign { } { } - assign $0\wr_pick_dly$1753[0:0]$3009 1'0 + assign $0\wr_pick_dly$1764[0:0]$3009 1'0 sync always sync init - update \wr_pick_dly$1753 $0\wr_pick_dly$1753[0:0]$3009 + update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$3009 end - attribute \src "libresoc.v:41288.7-41288.32" - process $proc$libresoc.v:41288$3010 + attribute \src "libresoc.v:41858.7-41858.32" + process $proc$libresoc.v:41858$3010 assign { } { } - assign $0\wr_pick_dly$1777[0:0]$3011 1'0 + assign $0\wr_pick_dly$1788[0:0]$3011 1'0 sync always sync init - update \wr_pick_dly$1777 $0\wr_pick_dly$1777[0:0]$3011 + update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$3011 end - attribute \src "libresoc.v:41292.7-41292.32" - process $proc$libresoc.v:41292$3012 + attribute \src "libresoc.v:41862.7-41862.32" + process $proc$libresoc.v:41862$3012 assign { } { } - assign $0\wr_pick_dly$1797[0:0]$3013 1'0 + assign $0\wr_pick_dly$1808[0:0]$3013 1'0 sync always sync init - update \wr_pick_dly$1797 $0\wr_pick_dly$1797[0:0]$3013 + update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$3013 end - attribute \src "libresoc.v:41296.7-41296.31" - process $proc$libresoc.v:41296$3014 + attribute \src "libresoc.v:41866.7-41866.31" + process $proc$libresoc.v:41866$3014 assign { } { } - assign $0\wr_pick_dly$981[0:0]$3015 1'0 + assign $0\wr_pick_dly$991[0:0]$3015 1'0 sync always sync init - update \wr_pick_dly$981 $0\wr_pick_dly$981[0:0]$3015 + update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$3015 end - attribute \src "libresoc.v:42258.3-42259.51" - process $proc$libresoc.v:42258$2238 + attribute \src "libresoc.v:42828.3-42829.51" + process $proc$libresoc.v:42828$2238 assign { } { } - assign $0\wr_pick_dly$1797[0:0]$2239 \wr_pick_dly$1797$next + assign $0\wr_pick_dly$1808[0:0]$2239 \wr_pick_dly$1808$next sync posedge \coresync_clk - update \wr_pick_dly$1797 $0\wr_pick_dly$1797[0:0]$2239 + update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$2239 end - attribute \src "libresoc.v:42260.3-42261.51" - process $proc$libresoc.v:42260$2240 + attribute \src "libresoc.v:42830.3-42831.51" + process $proc$libresoc.v:42830$2240 assign { } { } - assign $0\wr_pick_dly$1777[0:0]$2241 \wr_pick_dly$1777$next + assign $0\wr_pick_dly$1788[0:0]$2241 \wr_pick_dly$1788$next sync posedge \coresync_clk - update \wr_pick_dly$1777 $0\wr_pick_dly$1777[0:0]$2241 + update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$2241 end - attribute \src "libresoc.v:42262.3-42263.51" - process $proc$libresoc.v:42262$2242 + attribute \src "libresoc.v:42832.3-42833.51" + process $proc$libresoc.v:42832$2242 assign { } { } - assign $0\wr_pick_dly$1753[0:0]$2243 \wr_pick_dly$1753$next + assign $0\wr_pick_dly$1764[0:0]$2243 \wr_pick_dly$1764$next sync posedge \coresync_clk - update \wr_pick_dly$1753 $0\wr_pick_dly$1753[0:0]$2243 + update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$2243 end - attribute \src "libresoc.v:42264.3-42265.51" - process $proc$libresoc.v:42264$2244 + attribute \src "libresoc.v:42834.3-42835.51" + process $proc$libresoc.v:42834$2244 assign { } { } - assign $0\wr_pick_dly$1737[0:0]$2245 \wr_pick_dly$1737$next + assign $0\wr_pick_dly$1748[0:0]$2245 \wr_pick_dly$1748$next sync posedge \coresync_clk - update \wr_pick_dly$1737 $0\wr_pick_dly$1737[0:0]$2245 + update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$2245 end - attribute \src "libresoc.v:42266.3-42267.51" - process $proc$libresoc.v:42266$2246 + attribute \src "libresoc.v:42836.3-42837.51" + process $proc$libresoc.v:42836$2246 assign { } { } - assign $0\wr_pick_dly$1693[0:0]$2247 \wr_pick_dly$1693$next + assign $0\wr_pick_dly$1704[0:0]$2247 \wr_pick_dly$1704$next sync posedge \coresync_clk - update \wr_pick_dly$1693 $0\wr_pick_dly$1693[0:0]$2247 + update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$2247 end - attribute \src "libresoc.v:42268.3-42269.51" - process $proc$libresoc.v:42268$2248 + attribute \src "libresoc.v:42838.3-42839.51" + process $proc$libresoc.v:42838$2248 assign { } { } - assign $0\wr_pick_dly$1677[0:0]$2249 \wr_pick_dly$1677$next + assign $0\wr_pick_dly$1688[0:0]$2249 \wr_pick_dly$1688$next sync posedge \coresync_clk - update \wr_pick_dly$1677 $0\wr_pick_dly$1677[0:0]$2249 + update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$2249 end - attribute \src "libresoc.v:42270.3-42271.51" - process $proc$libresoc.v:42270$2250 + attribute \src "libresoc.v:42840.3-42841.51" + process $proc$libresoc.v:42840$2250 assign { } { } - assign $0\wr_pick_dly$1661[0:0]$2251 \wr_pick_dly$1661$next + assign $0\wr_pick_dly$1672[0:0]$2251 \wr_pick_dly$1672$next sync posedge \coresync_clk - update \wr_pick_dly$1661 $0\wr_pick_dly$1661[0:0]$2251 + update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$2251 end - attribute \src "libresoc.v:42272.3-42273.51" - process $proc$libresoc.v:42272$2252 + attribute \src "libresoc.v:42842.3-42843.51" + process $proc$libresoc.v:42842$2252 assign { } { } - assign $0\wr_pick_dly$1645[0:0]$2253 \wr_pick_dly$1645$next + assign $0\wr_pick_dly$1656[0:0]$2253 \wr_pick_dly$1656$next sync posedge \coresync_clk - update \wr_pick_dly$1645 $0\wr_pick_dly$1645[0:0]$2253 + update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2253 end - attribute \src "libresoc.v:42274.3-42275.51" - process $proc$libresoc.v:42274$2254 + attribute \src "libresoc.v:42844.3-42845.51" + process $proc$libresoc.v:42844$2254 assign { } { } - assign $0\wr_pick_dly$1626[0:0]$2255 \wr_pick_dly$1626$next + assign $0\wr_pick_dly$1637[0:0]$2255 \wr_pick_dly$1637$next sync posedge \coresync_clk - update \wr_pick_dly$1626 $0\wr_pick_dly$1626[0:0]$2255 + update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2255 end - attribute \src "libresoc.v:42276.3-42277.51" - process $proc$libresoc.v:42276$2256 + attribute \src "libresoc.v:42846.3-42847.51" + process $proc$libresoc.v:42846$2256 assign { } { } - assign $0\wr_pick_dly$1584[0:0]$2257 \wr_pick_dly$1584$next + assign $0\wr_pick_dly$1595[0:0]$2257 \wr_pick_dly$1595$next sync posedge \coresync_clk - update \wr_pick_dly$1584 $0\wr_pick_dly$1584[0:0]$2257 + update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2257 end - attribute \src "libresoc.v:42278.3-42279.51" - process $proc$libresoc.v:42278$2258 + attribute \src "libresoc.v:42848.3-42849.51" + process $proc$libresoc.v:42848$2258 assign { } { } - assign $0\wr_pick_dly$1568[0:0]$2259 \wr_pick_dly$1568$next + assign $0\wr_pick_dly$1579[0:0]$2259 \wr_pick_dly$1579$next sync posedge \coresync_clk - update \wr_pick_dly$1568 $0\wr_pick_dly$1568[0:0]$2259 + update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2259 end - attribute \src "libresoc.v:42280.3-42281.51" - process $proc$libresoc.v:42280$2260 + attribute \src "libresoc.v:42850.3-42851.51" + process $proc$libresoc.v:42850$2260 assign { } { } - assign $0\wr_pick_dly$1552[0:0]$2261 \wr_pick_dly$1552$next + assign $0\wr_pick_dly$1563[0:0]$2261 \wr_pick_dly$1563$next sync posedge \coresync_clk - update \wr_pick_dly$1552 $0\wr_pick_dly$1552[0:0]$2261 + update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2261 end - attribute \src "libresoc.v:42282.3-42283.51" - process $proc$libresoc.v:42282$2262 + attribute \src "libresoc.v:42852.3-42853.51" + process $proc$libresoc.v:42852$2262 assign { } { } - assign $0\wr_pick_dly$1536[0:0]$2263 \wr_pick_dly$1536$next + assign $0\wr_pick_dly$1547[0:0]$2263 \wr_pick_dly$1547$next sync posedge \coresync_clk - update \wr_pick_dly$1536 $0\wr_pick_dly$1536[0:0]$2263 + update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2263 end - attribute \src "libresoc.v:42284.3-42285.51" - process $proc$libresoc.v:42284$2264 + attribute \src "libresoc.v:42854.3-42855.51" + process $proc$libresoc.v:42854$2264 assign { } { } - assign $0\wr_pick_dly$1500[0:0]$2265 \wr_pick_dly$1500$next + assign $0\wr_pick_dly$1511[0:0]$2265 \wr_pick_dly$1511$next sync posedge \coresync_clk - update \wr_pick_dly$1500 $0\wr_pick_dly$1500[0:0]$2265 + update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2265 end - attribute \src "libresoc.v:42286.3-42287.51" - process $proc$libresoc.v:42286$2266 + attribute \src "libresoc.v:42856.3-42857.51" + process $proc$libresoc.v:42856$2266 assign { } { } - assign $0\wr_pick_dly$1484[0:0]$2267 \wr_pick_dly$1484$next + assign $0\wr_pick_dly$1495[0:0]$2267 \wr_pick_dly$1495$next sync posedge \coresync_clk - update \wr_pick_dly$1484 $0\wr_pick_dly$1484[0:0]$2267 + update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2267 end - attribute \src "libresoc.v:42288.3-42289.51" - process $proc$libresoc.v:42288$2268 + attribute \src "libresoc.v:42858.3-42859.51" + process $proc$libresoc.v:42858$2268 assign { } { } - assign $0\wr_pick_dly$1468[0:0]$2269 \wr_pick_dly$1468$next + assign $0\wr_pick_dly$1479[0:0]$2269 \wr_pick_dly$1479$next sync posedge \coresync_clk - update \wr_pick_dly$1468 $0\wr_pick_dly$1468[0:0]$2269 + update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2269 end - attribute \src "libresoc.v:42290.3-42291.51" - process $proc$libresoc.v:42290$2270 + attribute \src "libresoc.v:42860.3-42861.51" + process $proc$libresoc.v:42860$2270 assign { } { } - assign $0\wr_pick_dly$1452[0:0]$2271 \wr_pick_dly$1452$next + assign $0\wr_pick_dly$1463[0:0]$2271 \wr_pick_dly$1463$next sync posedge \coresync_clk - update \wr_pick_dly$1452 $0\wr_pick_dly$1452[0:0]$2271 + update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2271 end - attribute \src "libresoc.v:42292.3-42293.51" - process $proc$libresoc.v:42292$2272 + attribute \src "libresoc.v:42862.3-42863.51" + process $proc$libresoc.v:42862$2272 assign { } { } - assign $0\wr_pick_dly$1418[0:0]$2273 \wr_pick_dly$1418$next + assign $0\wr_pick_dly$1429[0:0]$2273 \wr_pick_dly$1429$next sync posedge \coresync_clk - update \wr_pick_dly$1418 $0\wr_pick_dly$1418[0:0]$2273 + update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2273 end - attribute \src "libresoc.v:42294.3-42295.51" - process $proc$libresoc.v:42294$2274 + attribute \src "libresoc.v:42864.3-42865.51" + process $proc$libresoc.v:42864$2274 assign { } { } - assign $0\wr_pick_dly$1402[0:0]$2275 \wr_pick_dly$1402$next + assign $0\wr_pick_dly$1413[0:0]$2275 \wr_pick_dly$1413$next sync posedge \coresync_clk - update \wr_pick_dly$1402 $0\wr_pick_dly$1402[0:0]$2275 + update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2275 end - attribute \src "libresoc.v:42296.3-42297.51" - process $proc$libresoc.v:42296$2276 + attribute \src "libresoc.v:42866.3-42867.51" + process $proc$libresoc.v:42866$2276 assign { } { } - assign $0\wr_pick_dly$1386[0:0]$2277 \wr_pick_dly$1386$next + assign $0\wr_pick_dly$1397[0:0]$2277 \wr_pick_dly$1397$next sync posedge \coresync_clk - update \wr_pick_dly$1386 $0\wr_pick_dly$1386[0:0]$2277 + update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2277 end - attribute \src "libresoc.v:42298.3-42299.51" - process $proc$libresoc.v:42298$2278 + attribute \src "libresoc.v:42868.3-42869.51" + process $proc$libresoc.v:42868$2278 assign { } { } - assign $0\wr_pick_dly$1339[0:0]$2279 \wr_pick_dly$1339$next + assign $0\wr_pick_dly$1350[0:0]$2279 \wr_pick_dly$1350$next sync posedge \coresync_clk - update \wr_pick_dly$1339 $0\wr_pick_dly$1339[0:0]$2279 + update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2279 end - attribute \src "libresoc.v:42300.3-42301.51" - process $proc$libresoc.v:42300$2280 + attribute \src "libresoc.v:42870.3-42871.51" + process $proc$libresoc.v:42870$2280 assign { } { } - assign $0\wr_pick_dly$1319[0:0]$2281 \wr_pick_dly$1319$next + assign $0\wr_pick_dly$1330[0:0]$2281 \wr_pick_dly$1330$next sync posedge \coresync_clk - update \wr_pick_dly$1319 $0\wr_pick_dly$1319[0:0]$2281 + update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2281 end - attribute \src "libresoc.v:42302.3-42303.51" - process $proc$libresoc.v:42302$2282 + attribute \src "libresoc.v:42872.3-42873.51" + process $proc$libresoc.v:42872$2282 assign { } { } - assign $0\wr_pick_dly$1299[0:0]$2283 \wr_pick_dly$1299$next + assign $0\wr_pick_dly$1310[0:0]$2283 \wr_pick_dly$1310$next sync posedge \coresync_clk - update \wr_pick_dly$1299 $0\wr_pick_dly$1299[0:0]$2283 + update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2283 end - attribute \src "libresoc.v:42304.3-42305.51" - process $proc$libresoc.v:42304$2284 + attribute \src "libresoc.v:42874.3-42875.51" + process $proc$libresoc.v:42874$2284 assign { } { } - assign $0\wr_pick_dly$1279[0:0]$2285 \wr_pick_dly$1279$next + assign $0\wr_pick_dly$1290[0:0]$2285 \wr_pick_dly$1290$next sync posedge \coresync_clk - update \wr_pick_dly$1279 $0\wr_pick_dly$1279[0:0]$2285 + update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2285 end - attribute \src "libresoc.v:42306.3-42307.51" - process $proc$libresoc.v:42306$2286 + attribute \src "libresoc.v:42876.3-42877.51" + process $proc$libresoc.v:42876$2286 assign { } { } - assign $0\wr_pick_dly$1259[0:0]$2287 \wr_pick_dly$1259$next + assign $0\wr_pick_dly$1270[0:0]$2287 \wr_pick_dly$1270$next sync posedge \coresync_clk - update \wr_pick_dly$1259 $0\wr_pick_dly$1259[0:0]$2287 + update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2287 end - attribute \src "libresoc.v:42308.3-42309.51" - process $proc$libresoc.v:42308$2288 + attribute \src "libresoc.v:42878.3-42879.51" + process $proc$libresoc.v:42878$2288 assign { } { } - assign $0\wr_pick_dly$1239[0:0]$2289 \wr_pick_dly$1239$next + assign $0\wr_pick_dly$1250[0:0]$2289 \wr_pick_dly$1250$next sync posedge \coresync_clk - update \wr_pick_dly$1239 $0\wr_pick_dly$1239[0:0]$2289 + update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2289 end - attribute \src "libresoc.v:42310.3-42311.51" - process $proc$libresoc.v:42310$2290 + attribute \src "libresoc.v:42880.3-42881.51" + process $proc$libresoc.v:42880$2290 assign { } { } - assign $0\wr_pick_dly$1211[0:0]$2291 \wr_pick_dly$1211$next + assign $0\wr_pick_dly$1222[0:0]$2291 \wr_pick_dly$1222$next sync posedge \coresync_clk - update \wr_pick_dly$1211 $0\wr_pick_dly$1211[0:0]$2291 + update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2291 end - attribute \src "libresoc.v:42312.3-42313.51" - process $proc$libresoc.v:42312$2292 + attribute \src "libresoc.v:42882.3-42883.51" + process $proc$libresoc.v:42882$2292 assign { } { } - assign $0\wr_pick_dly$1138[0:0]$2293 \wr_pick_dly$1138$next + assign $0\wr_pick_dly$1148[0:0]$2293 \wr_pick_dly$1148$next sync posedge \coresync_clk - update \wr_pick_dly$1138 $0\wr_pick_dly$1138[0:0]$2293 + update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2293 end - attribute \src "libresoc.v:42314.3-42315.51" - process $proc$libresoc.v:42314$2294 + attribute \src "libresoc.v:42884.3-42885.51" + process $proc$libresoc.v:42884$2294 assign { } { } - assign $0\wr_pick_dly$1120[0:0]$2295 \wr_pick_dly$1120$next + assign $0\wr_pick_dly$1130[0:0]$2295 \wr_pick_dly$1130$next sync posedge \coresync_clk - update \wr_pick_dly$1120 $0\wr_pick_dly$1120[0:0]$2295 + update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2295 end - attribute \src "libresoc.v:42316.3-42317.51" - process $proc$libresoc.v:42316$2296 + attribute \src "libresoc.v:42886.3-42887.51" + process $proc$libresoc.v:42886$2296 assign { } { } - assign $0\wr_pick_dly$1101[0:0]$2297 \wr_pick_dly$1101$next + assign $0\wr_pick_dly$1111[0:0]$2297 \wr_pick_dly$1111$next sync posedge \coresync_clk - update \wr_pick_dly$1101 $0\wr_pick_dly$1101[0:0]$2297 + update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2297 end - attribute \src "libresoc.v:42318.3-42319.51" - process $proc$libresoc.v:42318$2298 + attribute \src "libresoc.v:42888.3-42889.51" + process $proc$libresoc.v:42888$2298 assign { } { } - assign $0\wr_pick_dly$1081[0:0]$2299 \wr_pick_dly$1081$next + assign $0\wr_pick_dly$1091[0:0]$2299 \wr_pick_dly$1091$next sync posedge \coresync_clk - update \wr_pick_dly$1081 $0\wr_pick_dly$1081[0:0]$2299 + update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2299 end - attribute \src "libresoc.v:42320.3-42321.51" - process $proc$libresoc.v:42320$2300 + attribute \src "libresoc.v:42890.3-42891.51" + process $proc$libresoc.v:42890$2300 assign { } { } - assign $0\wr_pick_dly$1061[0:0]$2301 \wr_pick_dly$1061$next + assign $0\wr_pick_dly$1071[0:0]$2301 \wr_pick_dly$1071$next sync posedge \coresync_clk - update \wr_pick_dly$1061 $0\wr_pick_dly$1061[0:0]$2301 + update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2301 end - attribute \src "libresoc.v:42322.3-42323.51" - process $proc$libresoc.v:42322$2302 + attribute \src "libresoc.v:42892.3-42893.51" + process $proc$libresoc.v:42892$2302 assign { } { } - assign $0\wr_pick_dly$1039[0:0]$2303 \wr_pick_dly$1039$next + assign $0\wr_pick_dly$1049[0:0]$2303 \wr_pick_dly$1049$next sync posedge \coresync_clk - update \wr_pick_dly$1039 $0\wr_pick_dly$1039[0:0]$2303 + update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2303 end - attribute \src "libresoc.v:42324.3-42325.51" - process $proc$libresoc.v:42324$2304 + attribute \src "libresoc.v:42894.3-42895.51" + process $proc$libresoc.v:42894$2304 assign { } { } - assign $0\wr_pick_dly$1021[0:0]$2305 \wr_pick_dly$1021$next + assign $0\wr_pick_dly$1031[0:0]$2305 \wr_pick_dly$1031$next sync posedge \coresync_clk - update \wr_pick_dly$1021 $0\wr_pick_dly$1021[0:0]$2305 + update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2305 end - attribute \src "libresoc.v:42326.3-42327.51" - process $proc$libresoc.v:42326$2306 + attribute \src "libresoc.v:42896.3-42897.51" + process $proc$libresoc.v:42896$2306 assign { } { } - assign $0\wr_pick_dly$1000[0:0]$2307 \wr_pick_dly$1000$next + assign $0\wr_pick_dly$1010[0:0]$2307 \wr_pick_dly$1010$next sync posedge \coresync_clk - update \wr_pick_dly$1000 $0\wr_pick_dly$1000[0:0]$2307 + update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2307 end - attribute \src "libresoc.v:42328.3-42329.49" - process $proc$libresoc.v:42328$2308 + attribute \src "libresoc.v:42898.3-42899.49" + process $proc$libresoc.v:42898$2308 assign { } { } - assign $0\wr_pick_dly$981[0:0]$2309 \wr_pick_dly$981$next + assign $0\wr_pick_dly$991[0:0]$2309 \wr_pick_dly$991$next sync posedge \coresync_clk - update \wr_pick_dly$981 $0\wr_pick_dly$981[0:0]$2309 + update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$2309 end - attribute \src "libresoc.v:42330.3-42331.39" - process $proc$libresoc.v:42330$2310 + attribute \src "libresoc.v:42900.3-42901.39" + process $proc$libresoc.v:42900$2310 assign { } { } assign $0\wr_pick_dly[0:0] \wr_pick_dly$next sync posedge \coresync_clk update \wr_pick_dly $0\wr_pick_dly[0:0] end - attribute \src "libresoc.v:42332.3-42333.53" - process $proc$libresoc.v:42332$2311 + attribute \src "libresoc.v:42902.3-42903.53" + process $proc$libresoc.v:42902$2311 assign { } { } assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:42334.3-42335.59" - process $proc$libresoc.v:42334$2312 + attribute \src "libresoc.v:42904.3-42905.59" + process $proc$libresoc.v:42904$2312 assign { } { } assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:42336.3-42337.63" - process $proc$libresoc.v:42336$2313 + attribute \src "libresoc.v:42906.3-42907.63" + process $proc$libresoc.v:42906$2313 assign { } { } assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:42338.3-42339.57" - process $proc$libresoc.v:42338$2314 + attribute \src "libresoc.v:42908.3-42909.57" + process $proc$libresoc.v:42908$2314 assign { } { } assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:42340.3-42341.59" - process $proc$libresoc.v:42340$2315 + attribute \src "libresoc.v:42910.3-42911.59" + process $proc$libresoc.v:42910$2315 assign { } { } assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:42342.3-42343.63" - process $proc$libresoc.v:42342$2316 + attribute \src "libresoc.v:42912.3-42913.63" + process $proc$libresoc.v:42912$2316 assign { } { } assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:42344.3-42345.49" - process $proc$libresoc.v:42344$2317 + attribute \src "libresoc.v:42914.3-42915.49" + process $proc$libresoc.v:42914$2317 assign { } { } assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:42346.3-42347.49" - process $proc$libresoc.v:42346$2318 + attribute \src "libresoc.v:42916.3-42917.49" + process $proc$libresoc.v:42916$2318 assign { } { } assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:42348.3-42349.57" - process $proc$libresoc.v:42348$2319 + attribute \src "libresoc.v:42918.3-42919.57" + process $proc$libresoc.v:42918$2319 assign { } { } assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:42350.3-42351.49" - process $proc$libresoc.v:42350$2320 + attribute \src "libresoc.v:42920.3-42921.49" + process $proc$libresoc.v:42920$2320 assign { } { } assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:42352.3-42353.55" - process $proc$libresoc.v:42352$2321 + attribute \src "libresoc.v:42922.3-42923.55" + process $proc$libresoc.v:42922$2321 assign { } { } assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:42354.3-42355.57" - process $proc$libresoc.v:42354$2322 + attribute \src "libresoc.v:42924.3-42925.57" + process $proc$libresoc.v:42924$2322 assign { } { } assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:42356.3-42357.67" - process $proc$libresoc.v:42356$2323 + attribute \src "libresoc.v:42926.3-42927.67" + process $proc$libresoc.v:42926$2323 assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:42358.3-42359.57" - process $proc$libresoc.v:42358$2324 + attribute \src "libresoc.v:42928.3-42929.57" + process $proc$libresoc.v:42928$2324 assign { } { } assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:42360.3-42361.57" - process $proc$libresoc.v:42360$2325 + attribute \src "libresoc.v:42930.3-42931.57" + process $proc$libresoc.v:42930$2325 assign { } { } assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:42362.3-42363.67" - process $proc$libresoc.v:42362$2326 + attribute \src "libresoc.v:42932.3-42933.67" + process $proc$libresoc.v:42932$2326 assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next sync posedge \coresync_clk update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:42364.3-42365.57" - process $proc$libresoc.v:42364$2327 + attribute \src "libresoc.v:42934.3-42935.57" + process $proc$libresoc.v:42934$2327 assign { } { } assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next sync posedge \coresync_clk update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:42366.3-42367.57" - process $proc$libresoc.v:42366$2328 + attribute \src "libresoc.v:42936.3-42937.57" + process $proc$libresoc.v:42936$2328 assign { } { } assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next sync posedge \coresync_clk update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:42368.3-42369.57" - process $proc$libresoc.v:42368$2329 + attribute \src "libresoc.v:42938.3-42939.57" + process $proc$libresoc.v:42938$2329 assign { } { } assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next sync posedge \coresync_clk update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:42370.3-42371.65" - process $proc$libresoc.v:42370$2330 + attribute \src "libresoc.v:42940.3-42941.65" + process $proc$libresoc.v:42940$2330 assign { } { } assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next sync posedge \coresync_clk update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:42372.3-42373.57" - process $proc$libresoc.v:42372$2331 + attribute \src "libresoc.v:42942.3-42943.57" + process $proc$libresoc.v:42942$2331 assign { } { } assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:42374.3-42375.51" - process $proc$libresoc.v:42374$2332 + attribute \src "libresoc.v:42944.3-42945.51" + process $proc$libresoc.v:42944$2332 assign { } { } assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next sync posedge \coresync_clk update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:42376.3-42377.59" - process $proc$libresoc.v:42376$2333 + attribute \src "libresoc.v:42946.3-42947.59" + process $proc$libresoc.v:42946$2333 assign { } { } assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next sync posedge \coresync_clk update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:42378.3-42379.51" - process $proc$libresoc.v:42378$2334 + attribute \src "libresoc.v:42948.3-42949.51" + process $proc$libresoc.v:42948$2334 assign { } { } assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next sync posedge \coresync_clk update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:42380.3-42381.59" - process $proc$libresoc.v:42380$2335 + attribute \src "libresoc.v:42950.3-42951.59" + process $proc$libresoc.v:42950$2335 assign { } { } assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next sync posedge \coresync_clk update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:42382.3-42383.49" - process $proc$libresoc.v:42382$2336 + attribute \src "libresoc.v:42952.3-42953.49" + process $proc$libresoc.v:42952$2336 assign { } { } assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next sync posedge \coresync_clk update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:42384.3-42385.49" - process $proc$libresoc.v:42384$2337 + attribute \src "libresoc.v:42954.3-42955.49" + process $proc$libresoc.v:42954$2337 assign { } { } assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next sync posedge \coresync_clk update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:42386.3-42387.57" - process $proc$libresoc.v:42386$2338 + attribute \src "libresoc.v:42956.3-42957.57" + process $proc$libresoc.v:42956$2338 assign { } { } assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next sync posedge \coresync_clk update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:42388.3-42389.51" - process $proc$libresoc.v:42388$2339 + attribute \src "libresoc.v:42958.3-42959.51" + process $proc$libresoc.v:42958$2339 assign { } { } assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next sync posedge \coresync_clk update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:42390.3-42391.47" - process $proc$libresoc.v:42390$2340 + attribute \src "libresoc.v:42960.3-42961.47" + process $proc$libresoc.v:42960$2340 assign { } { } assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next sync posedge \coresync_clk update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:42392.3-42393.49" - process $proc$libresoc.v:42392$2341 + attribute \src "libresoc.v:42962.3-42963.49" + process $proc$libresoc.v:42962$2341 assign { } { } assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next sync posedge \coresync_clk update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:42394.3-42395.51" - process $proc$libresoc.v:42394$2342 + attribute \src "libresoc.v:42964.3-42965.51" + process $proc$libresoc.v:42964$2342 assign { } { } assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next sync posedge \coresync_clk update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:42396.3-42397.59" - process $proc$libresoc.v:42396$2343 + attribute \src "libresoc.v:42966.3-42967.59" + process $proc$libresoc.v:42966$2343 assign { } { } assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next sync posedge \coresync_clk update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:42398.3-42399.49" - process $proc$libresoc.v:42398$2344 + attribute \src "libresoc.v:42968.3-42969.49" + process $proc$libresoc.v:42968$2344 assign { } { } assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next sync posedge \coresync_clk update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:42400.3-42401.49" - process $proc$libresoc.v:42400$2345 + attribute \src "libresoc.v:42970.3-42971.49" + process $proc$libresoc.v:42970$2345 assign { } { } assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next sync posedge \coresync_clk update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:42402.3-42403.49" - process $proc$libresoc.v:42402$2346 + attribute \src "libresoc.v:42972.3-42973.49" + process $proc$libresoc.v:42972$2346 assign { } { } assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next sync posedge \coresync_clk update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:42404.3-42405.57" - process $proc$libresoc.v:42404$2347 + attribute \src "libresoc.v:42974.3-42975.57" + process $proc$libresoc.v:42974$2347 assign { } { } assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next sync posedge \coresync_clk update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:42406.3-42407.51" - process $proc$libresoc.v:42406$2348 + attribute \src "libresoc.v:42976.3-42977.51" + process $proc$libresoc.v:42976$2348 assign { } { } assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next sync posedge \coresync_clk update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:42408.3-42409.47" - process $proc$libresoc.v:42408$2349 + attribute \src "libresoc.v:42978.3-42979.47" + process $proc$libresoc.v:42978$2349 assign { } { } assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next sync posedge \coresync_clk update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:42410.3-42411.49" - process $proc$libresoc.v:42410$2350 + attribute \src "libresoc.v:42980.3-42981.49" + process $proc$libresoc.v:42980$2350 assign { } { } assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next sync posedge \coresync_clk update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:42412.3-42413.49" - process $proc$libresoc.v:42412$2351 + attribute \src "libresoc.v:42982.3-42983.49" + process $proc$libresoc.v:42982$2351 assign { } { } assign $0\core_terminate_o[0:0] \core_terminate_o$next sync posedge \coresync_clk update \core_terminate_o $0\core_terminate_o[0:0] end - attribute \src "libresoc.v:42414.3-42415.31" - process $proc$libresoc.v:42414$2352 + attribute \src "libresoc.v:42984.3-42985.31" + process $proc$libresoc.v:42984$2352 assign { } { } assign $0\counter[1:0] \counter$next sync posedge \coresync_clk update \counter $0\counter[1:0] end - attribute \src "libresoc.v:43145.3-43173.6" - process $proc$libresoc.v:43145$2353 + attribute \src "libresoc.v:43723.3-43751.6" + process $proc$libresoc.v:43723$2353 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43146.5-43146.29" + assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:43724.5-43724.29" switch \initial - attribute \src "libresoc.v:43146.9-43146.17" + attribute \src "libresoc.v:43724.9-43724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry case - assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 end sync always - update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] end - attribute \src "libresoc.v:43174.3-43202.6" - process $proc$libresoc.v:43174$2354 + attribute \src "libresoc.v:43752.3-43780.6" + process $proc$libresoc.v:43752$2354 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:43175.5-43175.29" + assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:43753.5-43753.29" switch \initial - attribute \src "libresoc.v:43175.9-43175.17" + attribute \src "libresoc.v:43753.9-43753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit case - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 end sync always - update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] + end + attribute \src "libresoc.v:43781.3-43809.6" + process $proc$libresoc.v:43781$2355 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:43782.5-43782.29" + switch \initial + attribute \src "libresoc.v:43782.9-43782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed + case + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] + end + attribute \src "libresoc.v:43810.3-43838.6" + process $proc$libresoc.v:43810$2356 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:43811.5-43811.29" + switch \initial + attribute \src "libresoc.v:43811.9-43811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len + case + assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] + end + attribute \src "libresoc.v:43839.3-43867.6" + process $proc$libresoc.v:43839$2357 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:43840.5-43840.29" + switch \initial + attribute \src "libresoc.v:43840.9-43840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn + case + assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] end - attribute \src "libresoc.v:43203.3-43231.6" - process $proc$libresoc.v:43203$2355 + attribute \src "libresoc.v:43868.3-43896.6" + process $proc$libresoc.v:43868$2358 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$23[0:0]$2356 $1\fus_cu_issue_i$23[0:0]$2357 - attribute \src "libresoc.v:43204.5-43204.29" + assign $0\fus_cu_issue_i$22[0:0]$2359 $1\fus_cu_issue_i$22[0:0]$2360 + attribute \src "libresoc.v:43869.5-43869.29" switch \initial - attribute \src "libresoc.v:43204.9-43204.17" + attribute \src "libresoc.v:43869.9-43869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$23[0:0]$2357 $2\fus_cu_issue_i$23[0:0]$2358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_issue_i$22[0:0]$2360 $2\fus_cu_issue_i$22[0:0]$2361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$23[0:0]$2358 1'0 + assign $2\fus_cu_issue_i$22[0:0]$2361 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$23[0:0]$2358 1'0 + assign $2\fus_cu_issue_i$22[0:0]$2361 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$23[0:0]$2358 $3\fus_cu_issue_i$23[0:0]$2359 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_issue_i$22[0:0]$2361 $3\fus_cu_issue_i$22[0:0]$2362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$22[0:0]$2362 \issue_i + case + assign $3\fus_cu_issue_i$22[0:0]$2362 1'0 + end + end + case + assign $1\fus_cu_issue_i$22[0:0]$2360 1'0 + end + sync always + update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2359 + end + attribute \src "libresoc.v:43897.3-43925.6" + process $proc$libresoc.v:43897$2363 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$24[2:0]$2364 $1\fus_cu_rdmaskn_i$24[2:0]$2365 + attribute \src "libresoc.v:43898.5-43898.29" + switch \initial + attribute \src "libresoc.v:43898.9-43898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 $2\fus_cu_rdmaskn_i$24[2:0]$2366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 $3\fus_cu_rdmaskn_i$24[2:0]$2367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$24[2:0]$2367 \$256 + case + assign $3\fus_cu_rdmaskn_i$24[2:0]$2367 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 3'000 + end + sync always + update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2364 + end + attribute \src "libresoc.v:43926.3-43954.6" + process $proc$libresoc.v:43926$2368 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43927.5-43927.29" + switch \initial + attribute \src "libresoc.v:43927.9-43927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$23[0:0]$2359 \issue_i + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type case - assign $3\fus_cu_issue_i$23[0:0]$2359 1'0 + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 end end case - assign $1\fus_cu_issue_i$23[0:0]$2357 1'0 + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 end sync always - update \fus_cu_issue_i$23 $0\fus_cu_issue_i$23[0:0]$2356 + update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] end - attribute \src "libresoc.v:43232.3-43260.6" - process $proc$libresoc.v:43232$2360 + attribute \src "libresoc.v:43955.3-43983.6" + process $proc$libresoc.v:43955$2369 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$25[5:0]$2361 $1\fus_cu_rdmaskn_i$25[5:0]$2362 - attribute \src "libresoc.v:43233.5-43233.29" + assign $0\fus_oper_i_alu_spr0__fn_unit[13:0] $1\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43956.5-43956.29" switch \initial - attribute \src "libresoc.v:43233.9-43233.17" + attribute \src "libresoc.v:43956.9-43956.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$25[5:0]$2362 $2\fus_cu_rdmaskn_i$25[5:0]$2363 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] $2\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$25[5:0]$2363 6'000000 + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$25[5:0]$2363 6'000000 + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$25[5:0]$2363 $3\fus_cu_rdmaskn_i$25[5:0]$2364 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] $3\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$25[5:0]$2364 \$263 + assign $3\fus_oper_i_alu_spr0__fn_unit[13:0] \dec_SPR_SPR__fn_unit case - assign $3\fus_cu_rdmaskn_i$25[5:0]$2364 6'000000 + assign $3\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_cu_rdmaskn_i$25[5:0]$2362 6'000000 + assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_cu_rdmaskn_i$25 $0\fus_cu_rdmaskn_i$25[5:0]$2361 + update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[13:0] end - attribute \src "libresoc.v:43261.3-43289.6" - process $proc$libresoc.v:43261$2365 + attribute \src "libresoc.v:43984.3-44012.6" + process $proc$libresoc.v:43984$2370 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43985.5-43985.29" + switch \initial + attribute \src "libresoc.v:43985.9-43985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn + case + assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + end + attribute \src "libresoc.v:44013.3-44041.6" + process $proc$libresoc.v:44013$2371 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:44014.5-44014.29" + switch \initial + attribute \src "libresoc.v:44014.9-44014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit + case + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + end + attribute \src "libresoc.v:44042.3-44070.6" + process $proc$libresoc.v:44042$2372 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$25[0:0]$2373 $1\fus_cu_issue_i$25[0:0]$2374 + attribute \src "libresoc.v:44043.5-44043.29" + switch \initial + attribute \src "libresoc.v:44043.9-44043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$25[0:0]$2374 $2\fus_cu_issue_i$25[0:0]$2375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$25[0:0]$2375 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$25[0:0]$2375 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$25[0:0]$2375 $3\fus_cu_issue_i$25[0:0]$2376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$25[0:0]$2376 \issue_i + case + assign $3\fus_cu_issue_i$25[0:0]$2376 1'0 + end + end + case + assign $1\fus_cu_issue_i$25[0:0]$2374 1'0 + end + sync always + update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2373 + end + attribute \src "libresoc.v:44071.3-44099.6" + process $proc$libresoc.v:44071$2377 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$27[5:0]$2378 $1\fus_cu_rdmaskn_i$27[5:0]$2379 + attribute \src "libresoc.v:44072.5-44072.29" + switch \initial + attribute \src "libresoc.v:44072.9-44072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 $2\fus_cu_rdmaskn_i$27[5:0]$2380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 $3\fus_cu_rdmaskn_i$27[5:0]$2381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$27[5:0]$2381 \$270 + case + assign $3\fus_cu_rdmaskn_i$27[5:0]$2381 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2378 + end + attribute \src "libresoc.v:44100.3-44128.6" + process $proc$libresoc.v:44100$2382 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43262.5-43262.29" + attribute \src "libresoc.v:44101.5-44101.29" switch \initial - attribute \src "libresoc.v:43262.9-43262.17" + attribute \src "libresoc.v:44101.9-44101.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75361,7 +76359,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75377,66 +76375,66 @@ module \core sync always update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] end - attribute \src "libresoc.v:43290.3-43318.6" - process $proc$libresoc.v:43290$2366 + attribute \src "libresoc.v:44129.3-44157.6" + process $proc$libresoc.v:44129$2383 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__fn_unit[11:0] $1\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43291.5-43291.29" + assign $0\fus_oper_i_alu_div0__fn_unit[13:0] $1\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44130.5-44130.29" switch \initial - attribute \src "libresoc.v:43291.9-43291.17" + attribute \src "libresoc.v:44130.9-44130.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_div0__fn_unit[11:0] $2\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_div0__fn_unit[13:0] $2\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] $3\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] $3\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__fn_unit[11:0] \dec_DIV_DIV__fn_unit + assign $3\fus_oper_i_alu_div0__fn_unit[13:0] \dec_DIV_DIV__fn_unit case - assign $3\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + assign $3\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + assign $1\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[11:0] + update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[13:0] end - attribute \src "libresoc.v:43319.3-43348.6" - process $proc$libresoc.v:43319$2367 + attribute \src "libresoc.v:44158.3-44187.6" + process $proc$libresoc.v:44158$2384 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43320.5-43320.29" + attribute \src "libresoc.v:44159.5-44159.29" switch \initial - attribute \src "libresoc.v:43320.9-43320.17" + attribute \src "libresoc.v:44159.9-44159.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75444,7 +76442,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75460,7 +76458,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75480,21 +76478,21 @@ module \core update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] end - attribute \src "libresoc.v:43349.3-43378.6" - process $proc$libresoc.v:43349$2368 + attribute \src "libresoc.v:44188.3-44217.6" + process $proc$libresoc.v:44188$2385 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43350.5-43350.29" + attribute \src "libresoc.v:44189.5-44189.29" switch \initial - attribute \src "libresoc.v:43350.9-43350.17" + attribute \src "libresoc.v:44189.9-44189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75502,7 +76500,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75518,7 +76516,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75538,21 +76536,21 @@ module \core update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] end - attribute \src "libresoc.v:43379.3-43408.6" - process $proc$libresoc.v:43379$2369 + attribute \src "libresoc.v:44218.3-44247.6" + process $proc$libresoc.v:44218$2386 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43380.5-43380.29" + attribute \src "libresoc.v:44219.5-44219.29" switch \initial - attribute \src "libresoc.v:43380.9-43380.17" + attribute \src "libresoc.v:44219.9-44219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75560,7 +76558,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75576,7 +76574,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75596,24 +76594,24 @@ module \core update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] end - attribute \src "libresoc.v:43409.3-43437.6" - process $proc$libresoc.v:43409$2370 + attribute \src "libresoc.v:44248.3-44276.6" + process $proc$libresoc.v:44248$2387 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43410.5-43410.29" + attribute \src "libresoc.v:44249.5-44249.29" switch \initial - attribute \src "libresoc.v:43410.9-43410.17" + attribute \src "libresoc.v:44249.9-44249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75625,7 +76623,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75641,24 +76639,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] end - attribute \src "libresoc.v:43438.3-43466.6" - process $proc$libresoc.v:43438$2371 + attribute \src "libresoc.v:44277.3-44305.6" + process $proc$libresoc.v:44277$2388 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43439.5-43439.29" + attribute \src "libresoc.v:44278.5-44278.29" switch \initial - attribute \src "libresoc.v:43439.9-43439.17" + attribute \src "libresoc.v:44278.9-44278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75670,7 +76668,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75686,24 +76684,24 @@ module \core sync always update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] end - attribute \src "libresoc.v:43467.3-43495.6" - process $proc$libresoc.v:43467$2372 + attribute \src "libresoc.v:44306.3-44334.6" + process $proc$libresoc.v:44306$2389 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43468.5-43468.29" + attribute \src "libresoc.v:44307.5-44307.29" switch \initial - attribute \src "libresoc.v:43468.9-43468.17" + attribute \src "libresoc.v:44307.9-44307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75715,7 +76713,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75731,24 +76729,24 @@ module \core sync always update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] end - attribute \src "libresoc.v:43496.3-43524.6" - process $proc$libresoc.v:43496$2373 + attribute \src "libresoc.v:44335.3-44363.6" + process $proc$libresoc.v:44335$2390 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43497.5-43497.29" + attribute \src "libresoc.v:44336.5-44336.29" switch \initial - attribute \src "libresoc.v:43497.9-43497.17" + attribute \src "libresoc.v:44336.9-44336.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75760,7 +76758,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75776,24 +76774,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] end - attribute \src "libresoc.v:43525.3-43553.6" - process $proc$libresoc.v:43525$2374 + attribute \src "libresoc.v:44364.3-44392.6" + process $proc$libresoc.v:44364$2391 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43526.5-43526.29" + attribute \src "libresoc.v:44365.5-44365.29" switch \initial - attribute \src "libresoc.v:43526.9-43526.17" + attribute \src "libresoc.v:44365.9-44365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75805,7 +76803,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75821,24 +76819,24 @@ module \core sync always update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] end - attribute \src "libresoc.v:43554.3-43582.6" - process $proc$libresoc.v:43554$2375 + attribute \src "libresoc.v:44393.3-44421.6" + process $proc$libresoc.v:44393$2392 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43555.5-43555.29" + attribute \src "libresoc.v:44394.5-44394.29" switch \initial - attribute \src "libresoc.v:43555.9-43555.17" + attribute \src "libresoc.v:44394.9-44394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75850,7 +76848,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75866,24 +76864,24 @@ module \core sync always update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] end - attribute \src "libresoc.v:43583.3-43611.6" - process $proc$libresoc.v:43583$2376 + attribute \src "libresoc.v:44422.3-44450.6" + process $proc$libresoc.v:44422$2393 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43584.5-43584.29" + attribute \src "libresoc.v:44423.5-44423.29" switch \initial - attribute \src "libresoc.v:43584.9-43584.17" + attribute \src "libresoc.v:44423.9-44423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75895,7 +76893,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75911,24 +76909,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] end - attribute \src "libresoc.v:43612.3-43640.6" - process $proc$libresoc.v:43612$2377 + attribute \src "libresoc.v:44451.3-44479.6" + process $proc$libresoc.v:44451$2394 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43613.5-43613.29" + attribute \src "libresoc.v:44452.5-44452.29" switch \initial - attribute \src "libresoc.v:43613.9-43613.17" + attribute \src "libresoc.v:44452.9-44452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75940,7 +76938,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75956,24 +76954,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] end - attribute \src "libresoc.v:43641.3-43669.6" - process $proc$libresoc.v:43641$2378 + attribute \src "libresoc.v:44480.3-44508.6" + process $proc$libresoc.v:44480$2395 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43642.5-43642.29" + attribute \src "libresoc.v:44481.5-44481.29" switch \initial - attribute \src "libresoc.v:43642.9-43642.17" + attribute \src "libresoc.v:44481.9-44481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75985,7 +76983,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76001,24 +76999,24 @@ module \core sync always update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] end - attribute \src "libresoc.v:43670.3-43698.6" - process $proc$libresoc.v:43670$2379 + attribute \src "libresoc.v:44509.3-44537.6" + process $proc$libresoc.v:44509$2396 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43671.5-43671.29" + attribute \src "libresoc.v:44510.5-44510.29" switch \initial - attribute \src "libresoc.v:43671.9-43671.17" + attribute \src "libresoc.v:44510.9-44510.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76030,7 +77028,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76046,114 +77044,114 @@ module \core sync always update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] end - attribute \src "libresoc.v:43699.3-43727.6" - process $proc$libresoc.v:43699$2380 + attribute \src "libresoc.v:44538.3-44566.6" + process $proc$libresoc.v:44538$2397 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$26[0:0]$2381 $1\fus_cu_issue_i$26[0:0]$2382 - attribute \src "libresoc.v:43700.5-43700.29" + assign $0\fus_cu_issue_i$28[0:0]$2398 $1\fus_cu_issue_i$28[0:0]$2399 + attribute \src "libresoc.v:44539.5-44539.29" switch \initial - attribute \src "libresoc.v:43700.9-43700.17" + attribute \src "libresoc.v:44539.9-44539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$26[0:0]$2382 $2\fus_cu_issue_i$26[0:0]$2383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_issue_i$28[0:0]$2399 $2\fus_cu_issue_i$28[0:0]$2400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$26[0:0]$2383 1'0 + assign $2\fus_cu_issue_i$28[0:0]$2400 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$26[0:0]$2383 1'0 + assign $2\fus_cu_issue_i$28[0:0]$2400 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$26[0:0]$2383 $3\fus_cu_issue_i$26[0:0]$2384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_issue_i$28[0:0]$2400 $3\fus_cu_issue_i$28[0:0]$2401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$26[0:0]$2384 \issue_i + assign $3\fus_cu_issue_i$28[0:0]$2401 \issue_i case - assign $3\fus_cu_issue_i$26[0:0]$2384 1'0 + assign $3\fus_cu_issue_i$28[0:0]$2401 1'0 end end case - assign $1\fus_cu_issue_i$26[0:0]$2382 1'0 + assign $1\fus_cu_issue_i$28[0:0]$2399 1'0 end sync always - update \fus_cu_issue_i$26 $0\fus_cu_issue_i$26[0:0]$2381 + update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2398 end - attribute \src "libresoc.v:43728.3-43756.6" - process $proc$libresoc.v:43728$2385 + attribute \src "libresoc.v:44567.3-44595.6" + process $proc$libresoc.v:44567$2402 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$28[2:0]$2386 $1\fus_cu_rdmaskn_i$28[2:0]$2387 - attribute \src "libresoc.v:43729.5-43729.29" + assign $0\fus_cu_rdmaskn_i$30[2:0]$2403 $1\fus_cu_rdmaskn_i$30[2:0]$2404 + attribute \src "libresoc.v:44568.5-44568.29" switch \initial - attribute \src "libresoc.v:43729.9-43729.17" + attribute \src "libresoc.v:44568.9-44568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$28[2:0]$2387 $2\fus_cu_rdmaskn_i$28[2:0]$2388 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 $2\fus_cu_rdmaskn_i$30[2:0]$2405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$28[2:0]$2388 3'000 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$28[2:0]$2388 3'000 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$28[2:0]$2388 $3\fus_cu_rdmaskn_i$28[2:0]$2389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 $3\fus_cu_rdmaskn_i$30[2:0]$2406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$28[2:0]$2389 \$293 + assign $3\fus_cu_rdmaskn_i$30[2:0]$2406 \$300 case - assign $3\fus_cu_rdmaskn_i$28[2:0]$2389 3'000 + assign $3\fus_cu_rdmaskn_i$30[2:0]$2406 3'000 end end case - assign $1\fus_cu_rdmaskn_i$28[2:0]$2387 3'000 + assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 3'000 end sync always - update \fus_cu_rdmaskn_i$28 $0\fus_cu_rdmaskn_i$28[2:0]$2386 + update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2403 end - attribute \src "libresoc.v:43757.3-43785.6" - process $proc$libresoc.v:43757$2390 + attribute \src "libresoc.v:44596.3-44624.6" + process $proc$libresoc.v:44596$2407 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43758.5-43758.29" + attribute \src "libresoc.v:44597.5-44597.29" switch \initial - attribute \src "libresoc.v:43758.9-43758.17" + attribute \src "libresoc.v:44597.9-44597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76165,7 +77163,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76181,66 +77179,66 @@ module \core sync always update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] end - attribute \src "libresoc.v:43786.3-43814.6" - process $proc$libresoc.v:43786$2391 + attribute \src "libresoc.v:44625.3-44653.6" + process $proc$libresoc.v:44625$2408 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_mul0__fn_unit[11:0] $1\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43787.5-43787.29" + assign $0\fus_oper_i_alu_mul0__fn_unit[13:0] $1\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44626.5-44626.29" switch \initial - attribute \src "libresoc.v:43787.9-43787.17" + attribute \src "libresoc.v:44626.9-44626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] $2\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] $2\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] $3\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] $3\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] \dec_MUL_MUL__fn_unit + assign $3\fus_oper_i_alu_mul0__fn_unit[13:0] \dec_MUL_MUL__fn_unit case - assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + assign $3\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[11:0] + update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[13:0] end - attribute \src "libresoc.v:43815.3-43844.6" - process $proc$libresoc.v:43815$2392 + attribute \src "libresoc.v:44654.3-44683.6" + process $proc$libresoc.v:44654$2409 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43816.5-43816.29" + attribute \src "libresoc.v:44655.5-44655.29" switch \initial - attribute \src "libresoc.v:43816.9-43816.17" + attribute \src "libresoc.v:44655.9-44655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76248,7 +77246,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76264,7 +77262,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76284,21 +77282,21 @@ module \core update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] end - attribute \src "libresoc.v:43845.3-43874.6" - process $proc$libresoc.v:43845$2393 + attribute \src "libresoc.v:44684.3-44713.6" + process $proc$libresoc.v:44684$2410 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43846.5-43846.29" + attribute \src "libresoc.v:44685.5-44685.29" switch \initial - attribute \src "libresoc.v:43846.9-43846.17" + attribute \src "libresoc.v:44685.9-44685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76306,7 +77304,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76322,7 +77320,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76342,21 +77340,21 @@ module \core update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] end - attribute \src "libresoc.v:43875.3-43904.6" - process $proc$libresoc.v:43875$2394 + attribute \src "libresoc.v:44714.3-44743.6" + process $proc$libresoc.v:44714$2411 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43876.5-43876.29" + attribute \src "libresoc.v:44715.5-44715.29" switch \initial - attribute \src "libresoc.v:43876.9-43876.17" + attribute \src "libresoc.v:44715.9-44715.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76364,7 +77362,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76380,7 +77378,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76400,24 +77398,24 @@ module \core update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] end - attribute \src "libresoc.v:43905.3-43933.6" - process $proc$libresoc.v:43905$2395 + attribute \src "libresoc.v:44744.3-44772.6" + process $proc$libresoc.v:44744$2412 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:43906.5-43906.29" + attribute \src "libresoc.v:44745.5-44745.29" switch \initial - attribute \src "libresoc.v:43906.9-43906.17" + attribute \src "libresoc.v:44745.9-44745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76429,7 +77427,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76445,24 +77443,24 @@ module \core sync always update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] end - attribute \src "libresoc.v:43934.3-43962.6" - process $proc$libresoc.v:43934$2396 + attribute \src "libresoc.v:44773.3-44801.6" + process $proc$libresoc.v:44773$2413 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43935.5-43935.29" + attribute \src "libresoc.v:44774.5-44774.29" switch \initial - attribute \src "libresoc.v:43935.9-43935.17" + attribute \src "libresoc.v:44774.9-44774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76474,7 +77472,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76490,24 +77488,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] end - attribute \src "libresoc.v:43963.3-43991.6" - process $proc$libresoc.v:43963$2397 + attribute \src "libresoc.v:44802.3-44830.6" + process $proc$libresoc.v:44802$2414 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43964.5-43964.29" + attribute \src "libresoc.v:44803.5-44803.29" switch \initial - attribute \src "libresoc.v:43964.9-43964.17" + attribute \src "libresoc.v:44803.9-44803.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76519,7 +77517,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76535,24 +77533,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] end - attribute \src "libresoc.v:43992.3-44020.6" - process $proc$libresoc.v:43992$2398 + attribute \src "libresoc.v:44831.3-44859.6" + process $proc$libresoc.v:44831$2415 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43993.5-43993.29" + attribute \src "libresoc.v:44832.5-44832.29" switch \initial - attribute \src "libresoc.v:43993.9-43993.17" + attribute \src "libresoc.v:44832.9-44832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76564,7 +77562,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76580,114 +77578,114 @@ module \core sync always update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] end - attribute \src "libresoc.v:44021.3-44049.6" - process $proc$libresoc.v:44021$2399 + attribute \src "libresoc.v:44860.3-44888.6" + process $proc$libresoc.v:44860$2416 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$29[0:0]$2400 $1\fus_cu_issue_i$29[0:0]$2401 - attribute \src "libresoc.v:44022.5-44022.29" + assign $0\fus_cu_issue_i$31[0:0]$2417 $1\fus_cu_issue_i$31[0:0]$2418 + attribute \src "libresoc.v:44861.5-44861.29" switch \initial - attribute \src "libresoc.v:44022.9-44022.17" + attribute \src "libresoc.v:44861.9-44861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$29[0:0]$2401 $2\fus_cu_issue_i$29[0:0]$2402 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_issue_i$31[0:0]$2418 $2\fus_cu_issue_i$31[0:0]$2419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$29[0:0]$2402 1'0 + assign $2\fus_cu_issue_i$31[0:0]$2419 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$29[0:0]$2402 1'0 + assign $2\fus_cu_issue_i$31[0:0]$2419 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$29[0:0]$2402 $3\fus_cu_issue_i$29[0:0]$2403 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_issue_i$31[0:0]$2419 $3\fus_cu_issue_i$31[0:0]$2420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$29[0:0]$2403 \issue_i + assign $3\fus_cu_issue_i$31[0:0]$2420 \issue_i case - assign $3\fus_cu_issue_i$29[0:0]$2403 1'0 + assign $3\fus_cu_issue_i$31[0:0]$2420 1'0 end end case - assign $1\fus_cu_issue_i$29[0:0]$2401 1'0 + assign $1\fus_cu_issue_i$31[0:0]$2418 1'0 end sync always - update \fus_cu_issue_i$29 $0\fus_cu_issue_i$29[0:0]$2400 + update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2417 end - attribute \src "libresoc.v:44050.3-44078.6" - process $proc$libresoc.v:44050$2404 + attribute \src "libresoc.v:44889.3-44917.6" + process $proc$libresoc.v:44889$2421 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$31[2:0]$2405 $1\fus_cu_rdmaskn_i$31[2:0]$2406 - attribute \src "libresoc.v:44051.5-44051.29" + assign $0\fus_cu_rdmaskn_i$33[2:0]$2422 $1\fus_cu_rdmaskn_i$33[2:0]$2423 + attribute \src "libresoc.v:44890.5-44890.29" switch \initial - attribute \src "libresoc.v:44051.9-44051.17" + attribute \src "libresoc.v:44890.9-44890.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$31[2:0]$2406 $2\fus_cu_rdmaskn_i$31[2:0]$2407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 $2\fus_cu_rdmaskn_i$33[2:0]$2424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$31[2:0]$2407 3'000 + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$31[2:0]$2407 3'000 + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$31[2:0]$2407 $3\fus_cu_rdmaskn_i$31[2:0]$2408 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 $3\fus_cu_rdmaskn_i$33[2:0]$2425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$31[2:0]$2408 \$307 + assign $3\fus_cu_rdmaskn_i$33[2:0]$2425 \$314 case - assign $3\fus_cu_rdmaskn_i$31[2:0]$2408 3'000 + assign $3\fus_cu_rdmaskn_i$33[2:0]$2425 3'000 end end case - assign $1\fus_cu_rdmaskn_i$31[2:0]$2406 3'000 + assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 3'000 end sync always - update \fus_cu_rdmaskn_i$31 $0\fus_cu_rdmaskn_i$31[2:0]$2405 + update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2422 end - attribute \src "libresoc.v:44079.3-44107.6" - process $proc$libresoc.v:44079$2409 + attribute \src "libresoc.v:44918.3-44946.6" + process $proc$libresoc.v:44918$2426 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44080.5-44080.29" + attribute \src "libresoc.v:44919.5-44919.29" switch \initial - attribute \src "libresoc.v:44080.9-44080.17" + attribute \src "libresoc.v:44919.9-44919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76699,7 +77697,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76715,66 +77713,66 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] end - attribute \src "libresoc.v:44108.3-44136.6" - process $proc$libresoc.v:44108$2410 + attribute \src "libresoc.v:44947.3-44975.6" + process $proc$libresoc.v:44947$2427 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44109.5-44109.29" + assign $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44948.5-44948.29" switch \initial - attribute \src "libresoc.v:44109.9-44109.17" + attribute \src "libresoc.v:44948.9-44948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit case - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] end - attribute \src "libresoc.v:44137.3-44166.6" - process $proc$libresoc.v:44137$2411 + attribute \src "libresoc.v:44976.3-45005.6" + process $proc$libresoc.v:44976$2428 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44138.5-44138.29" + attribute \src "libresoc.v:44977.5-44977.29" switch \initial - attribute \src "libresoc.v:44138.9-44138.17" + attribute \src "libresoc.v:44977.9-44977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76782,7 +77780,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76798,7 +77796,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76818,21 +77816,21 @@ module \core update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44167.3-44196.6" - process $proc$libresoc.v:44167$2412 + attribute \src "libresoc.v:45006.3-45035.6" + process $proc$libresoc.v:45006$2429 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44168.5-44168.29" + attribute \src "libresoc.v:45007.5-45007.29" switch \initial - attribute \src "libresoc.v:44168.9-44168.17" + attribute \src "libresoc.v:45007.9-45007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76840,7 +77838,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76856,7 +77854,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76876,21 +77874,21 @@ module \core update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] end - attribute \src "libresoc.v:44197.3-44226.6" - process $proc$libresoc.v:44197$2413 + attribute \src "libresoc.v:45036.3-45065.6" + process $proc$libresoc.v:45036$2430 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44198.5-44198.29" + attribute \src "libresoc.v:45037.5-45037.29" switch \initial - attribute \src "libresoc.v:44198.9-44198.17" + attribute \src "libresoc.v:45037.9-45037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76898,7 +77896,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76914,7 +77912,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76934,24 +77932,24 @@ module \core update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] end - attribute \src "libresoc.v:44227.3-44255.6" - process $proc$libresoc.v:44227$2414 + attribute \src "libresoc.v:45066.3-45094.6" + process $proc$libresoc.v:45066$2431 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:44228.5-44228.29" + attribute \src "libresoc.v:45067.5-45067.29" switch \initial - attribute \src "libresoc.v:44228.9-44228.17" + attribute \src "libresoc.v:45067.9-45067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76963,7 +77961,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76979,24 +77977,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] end - attribute \src "libresoc.v:44256.3-44284.6" - process $proc$libresoc.v:44256$2415 + attribute \src "libresoc.v:45095.3-45123.6" + process $proc$libresoc.v:45095$2432 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44257.5-44257.29" + attribute \src "libresoc.v:45096.5-45096.29" switch \initial - attribute \src "libresoc.v:44257.9-44257.17" + attribute \src "libresoc.v:45096.9-45096.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77008,7 +78006,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77024,24 +78022,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] end - attribute \src "libresoc.v:44285.3-44313.6" - process $proc$libresoc.v:44285$2416 + attribute \src "libresoc.v:45124.3-45152.6" + process $proc$libresoc.v:45124$2433 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44286.5-44286.29" + attribute \src "libresoc.v:45125.5-45125.29" switch \initial - attribute \src "libresoc.v:44286.9-44286.17" + attribute \src "libresoc.v:45125.9-45125.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77053,7 +78051,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77069,24 +78067,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] end - attribute \src "libresoc.v:44314.3-44342.6" - process $proc$libresoc.v:44314$2417 + attribute \src "libresoc.v:45153.3-45181.6" + process $proc$libresoc.v:45153$2434 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44315.5-44315.29" + attribute \src "libresoc.v:45154.5-45154.29" switch \initial - attribute \src "libresoc.v:44315.9-44315.17" + attribute \src "libresoc.v:45154.9-45154.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77098,7 +78096,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77114,24 +78112,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] end - attribute \src "libresoc.v:44343.3-44371.6" - process $proc$libresoc.v:44343$2418 + attribute \src "libresoc.v:45182.3-45210.6" + process $proc$libresoc.v:45182$2435 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44344.5-44344.29" + attribute \src "libresoc.v:45183.5-45183.29" switch \initial - attribute \src "libresoc.v:44344.9-44344.17" + attribute \src "libresoc.v:45183.9-45183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77143,7 +78141,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77159,24 +78157,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] end - attribute \src "libresoc.v:44372.3-44400.6" - process $proc$libresoc.v:44372$2419 + attribute \src "libresoc.v:45211.3-45239.6" + process $proc$libresoc.v:45211$2436 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44373.5-44373.29" + attribute \src "libresoc.v:45212.5-45212.29" switch \initial - attribute \src "libresoc.v:44373.9-44373.17" + attribute \src "libresoc.v:45212.9-45212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77188,7 +78186,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77204,24 +78202,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] end - attribute \src "libresoc.v:44401.3-44429.6" - process $proc$libresoc.v:44401$2420 + attribute \src "libresoc.v:45240.3-45268.6" + process $proc$libresoc.v:45240$2437 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44402.5-44402.29" + attribute \src "libresoc.v:45241.5-45241.29" switch \initial - attribute \src "libresoc.v:44402.9-44402.17" + attribute \src "libresoc.v:45241.9-45241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77233,7 +78231,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77249,24 +78247,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] end - attribute \src "libresoc.v:44430.3-44458.6" - process $proc$libresoc.v:44430$2421 + attribute \src "libresoc.v:45269.3-45297.6" + process $proc$libresoc.v:45269$2438 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44431.5-44431.29" + attribute \src "libresoc.v:45270.5-45270.29" switch \initial - attribute \src "libresoc.v:44431.9-44431.17" + attribute \src "libresoc.v:45270.9-45270.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77278,7 +78276,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77294,24 +78292,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] end - attribute \src "libresoc.v:44459.3-44487.6" - process $proc$libresoc.v:44459$2422 + attribute \src "libresoc.v:45298.3-45326.6" + process $proc$libresoc.v:45298$2439 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44460.5-44460.29" + attribute \src "libresoc.v:45299.5-45299.29" switch \initial - attribute \src "libresoc.v:44460.9-44460.17" + attribute \src "libresoc.v:45299.9-45299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77323,7 +78321,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77339,114 +78337,114 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] end - attribute \src "libresoc.v:44488.3-44516.6" - process $proc$libresoc.v:44488$2423 + attribute \src "libresoc.v:45327.3-45355.6" + process $proc$libresoc.v:45327$2440 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$32[0:0]$2424 $1\fus_cu_issue_i$32[0:0]$2425 - attribute \src "libresoc.v:44489.5-44489.29" + assign $0\fus_cu_issue_i$34[0:0]$2441 $1\fus_cu_issue_i$34[0:0]$2442 + attribute \src "libresoc.v:45328.5-45328.29" switch \initial - attribute \src "libresoc.v:44489.9-44489.17" + attribute \src "libresoc.v:45328.9-45328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$32[0:0]$2425 $2\fus_cu_issue_i$32[0:0]$2426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_issue_i$34[0:0]$2442 $2\fus_cu_issue_i$34[0:0]$2443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$32[0:0]$2426 1'0 + assign $2\fus_cu_issue_i$34[0:0]$2443 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$32[0:0]$2426 1'0 + assign $2\fus_cu_issue_i$34[0:0]$2443 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$32[0:0]$2426 $3\fus_cu_issue_i$32[0:0]$2427 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_issue_i$34[0:0]$2443 $3\fus_cu_issue_i$34[0:0]$2444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$32[0:0]$2427 \issue_i + assign $3\fus_cu_issue_i$34[0:0]$2444 \issue_i case - assign $3\fus_cu_issue_i$32[0:0]$2427 1'0 + assign $3\fus_cu_issue_i$34[0:0]$2444 1'0 end end case - assign $1\fus_cu_issue_i$32[0:0]$2425 1'0 + assign $1\fus_cu_issue_i$34[0:0]$2442 1'0 end sync always - update \fus_cu_issue_i$32 $0\fus_cu_issue_i$32[0:0]$2424 + update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2441 end - attribute \src "libresoc.v:44517.3-44545.6" - process $proc$libresoc.v:44517$2428 + attribute \src "libresoc.v:45356.3-45384.6" + process $proc$libresoc.v:45356$2445 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$34[4:0]$2429 $1\fus_cu_rdmaskn_i$34[4:0]$2430 - attribute \src "libresoc.v:44518.5-44518.29" + assign $0\fus_cu_rdmaskn_i$36[4:0]$2446 $1\fus_cu_rdmaskn_i$36[4:0]$2447 + attribute \src "libresoc.v:45357.5-45357.29" switch \initial - attribute \src "libresoc.v:44518.9-44518.17" + attribute \src "libresoc.v:45357.9-45357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$34[4:0]$2430 $2\fus_cu_rdmaskn_i$34[4:0]$2431 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 $2\fus_cu_rdmaskn_i$36[4:0]$2448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$34[4:0]$2431 5'00000 + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 5'00000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$34[4:0]$2431 5'00000 + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 5'00000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$34[4:0]$2431 $3\fus_cu_rdmaskn_i$34[4:0]$2432 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 $3\fus_cu_rdmaskn_i$36[4:0]$2449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$34[4:0]$2432 \$321 + assign $3\fus_cu_rdmaskn_i$36[4:0]$2449 \$328 case - assign $3\fus_cu_rdmaskn_i$34[4:0]$2432 5'00000 + assign $3\fus_cu_rdmaskn_i$36[4:0]$2449 5'00000 end end case - assign $1\fus_cu_rdmaskn_i$34[4:0]$2430 5'00000 + assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 5'00000 end sync always - update \fus_cu_rdmaskn_i$34 $0\fus_cu_rdmaskn_i$34[4:0]$2429 + update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2446 end - attribute \src "libresoc.v:44546.3-44574.6" - process $proc$libresoc.v:44546$2433 + attribute \src "libresoc.v:45385.3-45413.6" + process $proc$libresoc.v:45385$2450 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44547.5-44547.29" + attribute \src "libresoc.v:45386.5-45386.29" switch \initial - attribute \src "libresoc.v:44547.9-44547.17" + attribute \src "libresoc.v:45386.9-45386.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77458,7 +78456,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77474,66 +78472,66 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] end - attribute \src "libresoc.v:44575.3-44603.6" - process $proc$libresoc.v:44575$2434 + attribute \src "libresoc.v:45414.3-45442.6" + process $proc$libresoc.v:45414$2451 assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44576.5-44576.29" + assign $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45415.5-45415.29" switch \initial - attribute \src "libresoc.v:44576.9-44576.17" + attribute \src "libresoc.v:45415.9-45415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] \dec_LDST_LDST__fn_unit + assign $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] \dec_LDST_LDST__fn_unit case - assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + assign $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] + update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] end - attribute \src "libresoc.v:44604.3-44633.6" - process $proc$libresoc.v:44604$2435 + attribute \src "libresoc.v:45443.3-45472.6" + process $proc$libresoc.v:45443$2452 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44605.5-44605.29" + attribute \src "libresoc.v:45444.5-45444.29" switch \initial - attribute \src "libresoc.v:44605.9-44605.17" + attribute \src "libresoc.v:45444.9-45444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77541,7 +78539,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77557,7 +78555,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77577,24 +78575,24 @@ module \core update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44634.3-44662.6" - process $proc$libresoc.v:44634$2436 + attribute \src "libresoc.v:45473.3-45501.6" + process $proc$libresoc.v:45473$2453 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:44635.5-44635.29" + attribute \src "libresoc.v:45474.5-45474.29" switch \initial - attribute \src "libresoc.v:44635.9-44635.17" + attribute \src "libresoc.v:45474.9-45474.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77606,7 +78604,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77622,21 +78620,21 @@ module \core sync always update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] end - attribute \src "libresoc.v:44663.3-44692.6" - process $proc$libresoc.v:44663$2437 + attribute \src "libresoc.v:45502.3-45531.6" + process $proc$libresoc.v:45502$2454 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44664.5-44664.29" + attribute \src "libresoc.v:45503.5-45503.29" switch \initial - attribute \src "libresoc.v:44664.9-44664.17" + attribute \src "libresoc.v:45503.9-45503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77644,7 +78642,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77660,7 +78658,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77680,21 +78678,21 @@ module \core update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] end - attribute \src "libresoc.v:44693.3-44722.6" - process $proc$libresoc.v:44693$2438 + attribute \src "libresoc.v:45532.3-45561.6" + process $proc$libresoc.v:45532$2455 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44694.5-44694.29" + attribute \src "libresoc.v:45533.5-45533.29" switch \initial - attribute \src "libresoc.v:44694.9-44694.17" + attribute \src "libresoc.v:45533.9-45533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77702,7 +78700,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77718,7 +78716,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77738,24 +78736,24 @@ module \core update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] end - attribute \src "libresoc.v:44723.3-44751.6" - process $proc$libresoc.v:44723$2439 + attribute \src "libresoc.v:45562.3-45590.6" + process $proc$libresoc.v:45562$2456 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44724.5-44724.29" + attribute \src "libresoc.v:45563.5-45563.29" switch \initial - attribute \src "libresoc.v:44724.9-44724.17" + attribute \src "libresoc.v:45563.9-45563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77767,7 +78765,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77783,24 +78781,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] end - attribute \src "libresoc.v:44752.3-44780.6" - process $proc$libresoc.v:44752$2440 + attribute \src "libresoc.v:45591.3-45619.6" + process $proc$libresoc.v:45591$2457 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44753.5-44753.29" + attribute \src "libresoc.v:45592.5-45592.29" switch \initial - attribute \src "libresoc.v:44753.9-44753.17" + attribute \src "libresoc.v:45592.9-45592.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77812,7 +78810,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77828,24 +78826,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] end - attribute \src "libresoc.v:44781.3-44809.6" - process $proc$libresoc.v:44781$2441 + attribute \src "libresoc.v:45620.3-45648.6" + process $proc$libresoc.v:45620$2458 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44782.5-44782.29" + attribute \src "libresoc.v:45621.5-45621.29" switch \initial - attribute \src "libresoc.v:44782.9-44782.17" + attribute \src "libresoc.v:45621.9-45621.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77857,7 +78855,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77873,24 +78871,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] end - attribute \src "libresoc.v:44810.3-44838.6" - process $proc$libresoc.v:44810$2442 + attribute \src "libresoc.v:45649.3-45677.6" + process $proc$libresoc.v:45649$2459 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44811.5-44811.29" + attribute \src "libresoc.v:45650.5-45650.29" switch \initial - attribute \src "libresoc.v:44811.9-44811.17" + attribute \src "libresoc.v:45650.9-45650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77902,7 +78900,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77918,24 +78916,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] end - attribute \src "libresoc.v:44839.3-44867.6" - process $proc$libresoc.v:44839$2443 + attribute \src "libresoc.v:45678.3-45706.6" + process $proc$libresoc.v:45678$2460 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44840.5-44840.29" + attribute \src "libresoc.v:45679.5-45679.29" switch \initial - attribute \src "libresoc.v:44840.9-44840.17" + attribute \src "libresoc.v:45679.9-45679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77947,7 +78945,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77963,24 +78961,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] end - attribute \src "libresoc.v:44868.3-44896.6" - process $proc$libresoc.v:44868$2444 + attribute \src "libresoc.v:45707.3-45735.6" + process $proc$libresoc.v:45707$2461 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44869.5-44869.29" + attribute \src "libresoc.v:45708.5-45708.29" switch \initial - attribute \src "libresoc.v:44869.9-44869.17" + attribute \src "libresoc.v:45708.9-45708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77992,7 +78990,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78008,24 +79006,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] end - attribute \src "libresoc.v:44897.3-44925.6" - process $proc$libresoc.v:44897$2445 + attribute \src "libresoc.v:45736.3-45764.6" + process $proc$libresoc.v:45736$2462 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44898.5-44898.29" + attribute \src "libresoc.v:45737.5-45737.29" switch \initial - attribute \src "libresoc.v:44898.9-44898.17" + attribute \src "libresoc.v:45737.9-45737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78037,7 +79035,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78053,104 +79051,104 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] end - attribute \src "libresoc.v:44926.3-44954.6" - process $proc$libresoc.v:44926$2446 + attribute \src "libresoc.v:45765.3-45793.6" + process $proc$libresoc.v:45765$2463 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$35[0:0]$2447 $1\fus_cu_issue_i$35[0:0]$2448 - attribute \src "libresoc.v:44927.5-44927.29" + assign $0\fus_cu_issue_i$37[0:0]$2464 $1\fus_cu_issue_i$37[0:0]$2465 + attribute \src "libresoc.v:45766.5-45766.29" switch \initial - attribute \src "libresoc.v:44927.9-44927.17" + attribute \src "libresoc.v:45766.9-45766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$35[0:0]$2448 $2\fus_cu_issue_i$35[0:0]$2449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_issue_i$37[0:0]$2465 $2\fus_cu_issue_i$37[0:0]$2466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$35[0:0]$2449 1'0 + assign $2\fus_cu_issue_i$37[0:0]$2466 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$35[0:0]$2449 1'0 + assign $2\fus_cu_issue_i$37[0:0]$2466 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$35[0:0]$2449 $3\fus_cu_issue_i$35[0:0]$2450 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_issue_i$37[0:0]$2466 $3\fus_cu_issue_i$37[0:0]$2467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$35[0:0]$2450 \issue_i + assign $3\fus_cu_issue_i$37[0:0]$2467 \issue_i case - assign $3\fus_cu_issue_i$35[0:0]$2450 1'0 + assign $3\fus_cu_issue_i$37[0:0]$2467 1'0 end end case - assign $1\fus_cu_issue_i$35[0:0]$2448 1'0 + assign $1\fus_cu_issue_i$37[0:0]$2465 1'0 end sync always - update \fus_cu_issue_i$35 $0\fus_cu_issue_i$35[0:0]$2447 + update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2464 end - attribute \src "libresoc.v:44955.3-44983.6" - process $proc$libresoc.v:44955$2451 + attribute \src "libresoc.v:45794.3-45822.6" + process $proc$libresoc.v:45794$2468 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$37[2:0]$2452 $1\fus_cu_rdmaskn_i$37[2:0]$2453 - attribute \src "libresoc.v:44956.5-44956.29" + assign $0\fus_cu_rdmaskn_i$39[2:0]$2469 $1\fus_cu_rdmaskn_i$39[2:0]$2470 + attribute \src "libresoc.v:45795.5-45795.29" switch \initial - attribute \src "libresoc.v:44956.9-44956.17" + attribute \src "libresoc.v:45795.9-45795.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$37[2:0]$2453 $2\fus_cu_rdmaskn_i$37[2:0]$2454 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 $2\fus_cu_rdmaskn_i$39[2:0]$2471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$37[2:0]$2454 3'000 + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$37[2:0]$2454 3'000 + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$37[2:0]$2454 $3\fus_cu_rdmaskn_i$37[2:0]$2455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 $3\fus_cu_rdmaskn_i$39[2:0]$2472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$37[2:0]$2455 \$343 + assign $3\fus_cu_rdmaskn_i$39[2:0]$2472 \$350 case - assign $3\fus_cu_rdmaskn_i$37[2:0]$2455 3'000 + assign $3\fus_cu_rdmaskn_i$39[2:0]$2472 3'000 end end case - assign $1\fus_cu_rdmaskn_i$37[2:0]$2453 3'000 + assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 3'000 end sync always - update \fus_cu_rdmaskn_i$37 $0\fus_cu_rdmaskn_i$37[2:0]$2452 + update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2469 end - attribute \src "libresoc.v:44984.3-44992.6" - process $proc$libresoc.v:44984$2456 + attribute \src "libresoc.v:45823.3-45831.6" + process $proc$libresoc.v:45823$2473 assign { } { } assign { } { } - assign $0\dp_INT_ra_alu0_0$next[0:0]$2457 $1\dp_INT_ra_alu0_0$next[0:0]$2458 - attribute \src "libresoc.v:44985.5-44985.29" + assign $0\dp_INT_ra_alu0_0$next[0:0]$2474 $1\dp_INT_ra_alu0_0$next[0:0]$2475 + attribute \src "libresoc.v:45824.5-45824.29" switch \initial - attribute \src "libresoc.v:44985.9-44985.17" + attribute \src "libresoc.v:45824.9-45824.17" case 1'1 case end @@ -78159,25 +79157,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_alu0_0$next[0:0]$2458 1'0 + assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 1'0 case - assign $1\dp_INT_ra_alu0_0$next[0:0]$2458 \rp_INT_ra_alu0_0 + assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 \rp_INT_ra_alu0_0 end sync always - update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2457 + update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2474 end - attribute \src "libresoc.v:44993.3-45002.6" - process $proc$libresoc.v:44993$2459 + attribute \src "libresoc.v:45832.3-45841.6" + process $proc$libresoc.v:45832$2476 assign { } { } assign { } { } assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "libresoc.v:44994.5-44994.29" + attribute \src "libresoc.v:45833.5-45833.29" switch \initial - attribute \src "libresoc.v:44994.9-44994.17" + attribute \src "libresoc.v:45833.9-45833.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78189,14 +79187,14 @@ module \core sync always update \fus_src1_i $0\fus_src1_i[63:0] end - attribute \src "libresoc.v:45003.3-45011.6" - process $proc$libresoc.v:45003$2460 + attribute \src "libresoc.v:45842.3-45850.6" + process $proc$libresoc.v:45842$2477 assign { } { } assign { } { } - assign $0\dp_INT_ra_cr0_1$next[0:0]$2461 $1\dp_INT_ra_cr0_1$next[0:0]$2462 - attribute \src "libresoc.v:45004.5-45004.29" + assign $0\dp_INT_ra_cr0_1$next[0:0]$2478 $1\dp_INT_ra_cr0_1$next[0:0]$2479 + attribute \src "libresoc.v:45843.5-45843.29" switch \initial - attribute \src "libresoc.v:45004.9-45004.17" + attribute \src "libresoc.v:45843.9-45843.17" case 1'1 case end @@ -78205,44 +79203,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_cr0_1$next[0:0]$2462 1'0 + assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 1'0 case - assign $1\dp_INT_ra_cr0_1$next[0:0]$2462 \rp_INT_ra_cr0_1 + assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 \rp_INT_ra_cr0_1 end sync always - update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2461 + update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2478 end - attribute \src "libresoc.v:45012.3-45021.6" - process $proc$libresoc.v:45012$2463 + attribute \src "libresoc.v:45851.3-45860.6" + process $proc$libresoc.v:45851$2480 assign { } { } assign { } { } - assign $0\fus_src1_i$40[63:0]$2464 $1\fus_src1_i$40[63:0]$2465 - attribute \src "libresoc.v:45013.5-45013.29" + assign $0\fus_src1_i$42[63:0]$2481 $1\fus_src1_i$42[63:0]$2482 + attribute \src "libresoc.v:45852.5-45852.29" switch \initial - attribute \src "libresoc.v:45013.9-45013.17" + attribute \src "libresoc.v:45852.9-45852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$40[63:0]$2465 \int_src1__data_o + assign $1\fus_src1_i$42[63:0]$2482 \int_src1__data_o case - assign $1\fus_src1_i$40[63:0]$2465 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$40 $0\fus_src1_i$40[63:0]$2464 + update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2481 end - attribute \src "libresoc.v:45022.3-45030.6" - process $proc$libresoc.v:45022$2466 + attribute \src "libresoc.v:45861.3-45869.6" + process $proc$libresoc.v:45861$2483 assign { } { } assign { } { } - assign $0\dp_INT_ra_trap0_2$next[0:0]$2467 $1\dp_INT_ra_trap0_2$next[0:0]$2468 - attribute \src "libresoc.v:45023.5-45023.29" + assign $0\dp_INT_ra_trap0_2$next[0:0]$2484 $1\dp_INT_ra_trap0_2$next[0:0]$2485 + attribute \src "libresoc.v:45862.5-45862.29" switch \initial - attribute \src "libresoc.v:45023.9-45023.17" + attribute \src "libresoc.v:45862.9-45862.17" case 1'1 case end @@ -78251,44 +79249,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_trap0_2$next[0:0]$2468 1'0 + assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 1'0 case - assign $1\dp_INT_ra_trap0_2$next[0:0]$2468 \rp_INT_ra_trap0_2 + assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 \rp_INT_ra_trap0_2 end sync always - update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2467 + update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2484 end - attribute \src "libresoc.v:45031.3-45040.6" - process $proc$libresoc.v:45031$2469 + attribute \src "libresoc.v:45870.3-45879.6" + process $proc$libresoc.v:45870$2486 assign { } { } assign { } { } - assign $0\fus_src1_i$43[63:0]$2470 $1\fus_src1_i$43[63:0]$2471 - attribute \src "libresoc.v:45032.5-45032.29" + assign $0\fus_src1_i$45[63:0]$2487 $1\fus_src1_i$45[63:0]$2488 + attribute \src "libresoc.v:45871.5-45871.29" switch \initial - attribute \src "libresoc.v:45032.9-45032.17" + attribute \src "libresoc.v:45871.9-45871.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$43[63:0]$2471 \int_src1__data_o + assign $1\fus_src1_i$45[63:0]$2488 \int_src1__data_o case - assign $1\fus_src1_i$43[63:0]$2471 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$43 $0\fus_src1_i$43[63:0]$2470 + update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2487 end - attribute \src "libresoc.v:45041.3-45049.6" - process $proc$libresoc.v:45041$2472 + attribute \src "libresoc.v:45880.3-45888.6" + process $proc$libresoc.v:45880$2489 assign { } { } assign { } { } - assign $0\dp_INT_ra_logical0_3$next[0:0]$2473 $1\dp_INT_ra_logical0_3$next[0:0]$2474 - attribute \src "libresoc.v:45042.5-45042.29" + assign $0\dp_INT_ra_logical0_3$next[0:0]$2490 $1\dp_INT_ra_logical0_3$next[0:0]$2491 + attribute \src "libresoc.v:45881.5-45881.29" switch \initial - attribute \src "libresoc.v:45042.9-45042.17" + attribute \src "libresoc.v:45881.9-45881.17" case 1'1 case end @@ -78297,44 +79295,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_logical0_3$next[0:0]$2474 1'0 + assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 1'0 case - assign $1\dp_INT_ra_logical0_3$next[0:0]$2474 \rp_INT_ra_logical0_3 + assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 \rp_INT_ra_logical0_3 end sync always - update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2473 + update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2490 end - attribute \src "libresoc.v:45050.3-45059.6" - process $proc$libresoc.v:45050$2475 + attribute \src "libresoc.v:45889.3-45898.6" + process $proc$libresoc.v:45889$2492 assign { } { } assign { } { } - assign $0\fus_src1_i$46[63:0]$2476 $1\fus_src1_i$46[63:0]$2477 - attribute \src "libresoc.v:45051.5-45051.29" + assign $0\fus_src1_i$48[63:0]$2493 $1\fus_src1_i$48[63:0]$2494 + attribute \src "libresoc.v:45890.5-45890.29" switch \initial - attribute \src "libresoc.v:45051.9-45051.17" + attribute \src "libresoc.v:45890.9-45890.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$46[63:0]$2477 \int_src1__data_o + assign $1\fus_src1_i$48[63:0]$2494 \int_src1__data_o case - assign $1\fus_src1_i$46[63:0]$2477 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$46 $0\fus_src1_i$46[63:0]$2476 + update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2493 end - attribute \src "libresoc.v:45060.3-45068.6" - process $proc$libresoc.v:45060$2478 + attribute \src "libresoc.v:45899.3-45907.6" + process $proc$libresoc.v:45899$2495 assign { } { } assign { } { } - assign $0\dp_INT_ra_spr0_4$next[0:0]$2479 $1\dp_INT_ra_spr0_4$next[0:0]$2480 - attribute \src "libresoc.v:45061.5-45061.29" + assign $0\dp_INT_ra_spr0_4$next[0:0]$2496 $1\dp_INT_ra_spr0_4$next[0:0]$2497 + attribute \src "libresoc.v:45900.5-45900.29" switch \initial - attribute \src "libresoc.v:45061.9-45061.17" + attribute \src "libresoc.v:45900.9-45900.17" case 1'1 case end @@ -78343,44 +79341,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_spr0_4$next[0:0]$2480 1'0 + assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 1'0 case - assign $1\dp_INT_ra_spr0_4$next[0:0]$2480 \rp_INT_ra_spr0_4 + assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 \rp_INT_ra_spr0_4 end sync always - update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2479 + update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2496 end - attribute \src "libresoc.v:45069.3-45078.6" - process $proc$libresoc.v:45069$2481 + attribute \src "libresoc.v:45908.3-45917.6" + process $proc$libresoc.v:45908$2498 assign { } { } assign { } { } - assign $0\fus_src1_i$49[63:0]$2482 $1\fus_src1_i$49[63:0]$2483 - attribute \src "libresoc.v:45070.5-45070.29" + assign $0\fus_src1_i$51[63:0]$2499 $1\fus_src1_i$51[63:0]$2500 + attribute \src "libresoc.v:45909.5-45909.29" switch \initial - attribute \src "libresoc.v:45070.9-45070.17" + attribute \src "libresoc.v:45909.9-45909.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_spr0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$49[63:0]$2483 \int_src1__data_o + assign $1\fus_src1_i$51[63:0]$2500 \int_src1__data_o case - assign $1\fus_src1_i$49[63:0]$2483 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$49 $0\fus_src1_i$49[63:0]$2482 + update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2499 end - attribute \src "libresoc.v:45079.3-45087.6" - process $proc$libresoc.v:45079$2484 + attribute \src "libresoc.v:45918.3-45926.6" + process $proc$libresoc.v:45918$2501 assign { } { } assign { } { } - assign $0\dp_INT_ra_div0_5$next[0:0]$2485 $1\dp_INT_ra_div0_5$next[0:0]$2486 - attribute \src "libresoc.v:45080.5-45080.29" + assign $0\dp_INT_ra_div0_5$next[0:0]$2502 $1\dp_INT_ra_div0_5$next[0:0]$2503 + attribute \src "libresoc.v:45919.5-45919.29" switch \initial - attribute \src "libresoc.v:45080.9-45080.17" + attribute \src "libresoc.v:45919.9-45919.17" case 1'1 case end @@ -78389,44 +79387,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_div0_5$next[0:0]$2486 1'0 + assign $1\dp_INT_ra_div0_5$next[0:0]$2503 1'0 case - assign $1\dp_INT_ra_div0_5$next[0:0]$2486 \rp_INT_ra_div0_5 + assign $1\dp_INT_ra_div0_5$next[0:0]$2503 \rp_INT_ra_div0_5 end sync always - update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2485 + update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2502 end - attribute \src "libresoc.v:45088.3-45097.6" - process $proc$libresoc.v:45088$2487 + attribute \src "libresoc.v:45927.3-45936.6" + process $proc$libresoc.v:45927$2504 assign { } { } assign { } { } - assign $0\fus_src1_i$52[63:0]$2488 $1\fus_src1_i$52[63:0]$2489 - attribute \src "libresoc.v:45089.5-45089.29" + assign $0\fus_src1_i$54[63:0]$2505 $1\fus_src1_i$54[63:0]$2506 + attribute \src "libresoc.v:45928.5-45928.29" switch \initial - attribute \src "libresoc.v:45089.9-45089.17" + attribute \src "libresoc.v:45928.9-45928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_div0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$52[63:0]$2489 \int_src1__data_o + assign $1\fus_src1_i$54[63:0]$2506 \int_src1__data_o case - assign $1\fus_src1_i$52[63:0]$2489 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$52 $0\fus_src1_i$52[63:0]$2488 + update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2505 end - attribute \src "libresoc.v:45098.3-45106.6" - process $proc$libresoc.v:45098$2490 + attribute \src "libresoc.v:45937.3-45945.6" + process $proc$libresoc.v:45937$2507 assign { } { } assign { } { } - assign $0\dp_INT_ra_mul0_6$next[0:0]$2491 $1\dp_INT_ra_mul0_6$next[0:0]$2492 - attribute \src "libresoc.v:45099.5-45099.29" + assign $0\dp_INT_ra_mul0_6$next[0:0]$2508 $1\dp_INT_ra_mul0_6$next[0:0]$2509 + attribute \src "libresoc.v:45938.5-45938.29" switch \initial - attribute \src "libresoc.v:45099.9-45099.17" + attribute \src "libresoc.v:45938.9-45938.17" case 1'1 case end @@ -78435,44 +79433,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_mul0_6$next[0:0]$2492 1'0 + assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 1'0 case - assign $1\dp_INT_ra_mul0_6$next[0:0]$2492 \rp_INT_ra_mul0_6 + assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 \rp_INT_ra_mul0_6 end sync always - update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2491 + update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2508 end - attribute \src "libresoc.v:45107.3-45116.6" - process $proc$libresoc.v:45107$2493 + attribute \src "libresoc.v:45946.3-45955.6" + process $proc$libresoc.v:45946$2510 assign { } { } assign { } { } - assign $0\fus_src1_i$55[63:0]$2494 $1\fus_src1_i$55[63:0]$2495 - attribute \src "libresoc.v:45108.5-45108.29" + assign $0\fus_src1_i$57[63:0]$2511 $1\fus_src1_i$57[63:0]$2512 + attribute \src "libresoc.v:45947.5-45947.29" switch \initial - attribute \src "libresoc.v:45108.9-45108.17" + attribute \src "libresoc.v:45947.9-45947.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_mul0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$55[63:0]$2495 \int_src1__data_o + assign $1\fus_src1_i$57[63:0]$2512 \int_src1__data_o case - assign $1\fus_src1_i$55[63:0]$2495 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$55 $0\fus_src1_i$55[63:0]$2494 + update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2511 end - attribute \src "libresoc.v:45117.3-45125.6" - process $proc$libresoc.v:45117$2496 + attribute \src "libresoc.v:45956.3-45964.6" + process $proc$libresoc.v:45956$2513 assign { } { } assign { } { } - assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 - attribute \src "libresoc.v:45118.5-45118.29" + assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 + attribute \src "libresoc.v:45957.5-45957.29" switch \initial - attribute \src "libresoc.v:45118.9-45118.17" + attribute \src "libresoc.v:45957.9-45957.17" case 1'1 case end @@ -78481,44 +79479,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 1'0 + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 1'0 case - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 \rp_INT_ra_shiftrot0_7 + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 \rp_INT_ra_shiftrot0_7 end sync always - update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 + update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 end - attribute \src "libresoc.v:45126.3-45135.6" - process $proc$libresoc.v:45126$2499 + attribute \src "libresoc.v:45965.3-45974.6" + process $proc$libresoc.v:45965$2516 assign { } { } assign { } { } - assign $0\fus_src1_i$58[63:0]$2500 $1\fus_src1_i$58[63:0]$2501 - attribute \src "libresoc.v:45127.5-45127.29" + assign $0\fus_src1_i$60[63:0]$2517 $1\fus_src1_i$60[63:0]$2518 + attribute \src "libresoc.v:45966.5-45966.29" switch \initial - attribute \src "libresoc.v:45127.9-45127.17" + attribute \src "libresoc.v:45966.9-45966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_shiftrot0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$58[63:0]$2501 \int_src1__data_o + assign $1\fus_src1_i$60[63:0]$2518 \int_src1__data_o case - assign $1\fus_src1_i$58[63:0]$2501 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$58 $0\fus_src1_i$58[63:0]$2500 + update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2517 end - attribute \src "libresoc.v:45136.3-45144.6" - process $proc$libresoc.v:45136$2502 + attribute \src "libresoc.v:45975.3-45983.6" + process $proc$libresoc.v:45975$2519 assign { } { } assign { } { } - assign $0\dp_INT_ra_ldst0_8$next[0:0]$2503 $1\dp_INT_ra_ldst0_8$next[0:0]$2504 - attribute \src "libresoc.v:45137.5-45137.29" + assign $0\dp_INT_ra_ldst0_8$next[0:0]$2520 $1\dp_INT_ra_ldst0_8$next[0:0]$2521 + attribute \src "libresoc.v:45976.5-45976.29" switch \initial - attribute \src "libresoc.v:45137.9-45137.17" + attribute \src "libresoc.v:45976.9-45976.17" case 1'1 case end @@ -78527,44 +79525,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2504 1'0 + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 1'0 case - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2504 \rp_INT_ra_ldst0_8 + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 \rp_INT_ra_ldst0_8 end sync always - update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2503 + update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2520 end - attribute \src "libresoc.v:45145.3-45154.6" - process $proc$libresoc.v:45145$2505 + attribute \src "libresoc.v:45984.3-45993.6" + process $proc$libresoc.v:45984$2522 assign { } { } assign { } { } - assign $0\fus_src1_i$61[63:0]$2506 $1\fus_src1_i$61[63:0]$2507 - attribute \src "libresoc.v:45146.5-45146.29" + assign $0\fus_src1_i$63[63:0]$2523 $1\fus_src1_i$63[63:0]$2524 + attribute \src "libresoc.v:45985.5-45985.29" switch \initial - attribute \src "libresoc.v:45146.9-45146.17" + attribute \src "libresoc.v:45985.9-45985.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_ldst0_8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$61[63:0]$2507 \int_src1__data_o + assign $1\fus_src1_i$63[63:0]$2524 \int_src1__data_o case - assign $1\fus_src1_i$61[63:0]$2507 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$63[63:0]$2524 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$61 $0\fus_src1_i$61[63:0]$2506 + update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2523 end - attribute \src "libresoc.v:45155.3-45163.6" - process $proc$libresoc.v:45155$2508 + attribute \src "libresoc.v:45994.3-46002.6" + process $proc$libresoc.v:45994$2525 assign { } { } assign { } { } - assign $0\dp_INT_rb_alu0_0$next[0:0]$2509 $1\dp_INT_rb_alu0_0$next[0:0]$2510 - attribute \src "libresoc.v:45156.5-45156.29" + assign $0\dp_INT_rb_alu0_0$next[0:0]$2526 $1\dp_INT_rb_alu0_0$next[0:0]$2527 + attribute \src "libresoc.v:45995.5-45995.29" switch \initial - attribute \src "libresoc.v:45156.9-45156.17" + attribute \src "libresoc.v:45995.9-45995.17" case 1'1 case end @@ -78573,25 +79571,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_alu0_0$next[0:0]$2510 1'0 + assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 1'0 case - assign $1\dp_INT_rb_alu0_0$next[0:0]$2510 \rp_INT_rb_alu0_0 + assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 \rp_INT_rb_alu0_0 end sync always - update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2509 + update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2526 end - attribute \src "libresoc.v:45164.3-45173.6" - process $proc$libresoc.v:45164$2511 + attribute \src "libresoc.v:46003.3-46012.6" + process $proc$libresoc.v:46003$2528 assign { } { } assign { } { } assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45165.5-45165.29" + attribute \src "libresoc.v:46004.5-46004.29" switch \initial - attribute \src "libresoc.v:45165.9-45165.17" + attribute \src "libresoc.v:46004.9-46004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78603,14 +79601,14 @@ module \core sync always update \fus_src2_i $0\fus_src2_i[63:0] end - attribute \src "libresoc.v:45174.3-45182.6" - process $proc$libresoc.v:45174$2512 + attribute \src "libresoc.v:46013.3-46021.6" + process $proc$libresoc.v:46013$2529 assign { } { } assign { } { } - assign $0\dp_INT_rb_cr0_1$next[0:0]$2513 $1\dp_INT_rb_cr0_1$next[0:0]$2514 - attribute \src "libresoc.v:45175.5-45175.29" + assign $0\dp_INT_rb_cr0_1$next[0:0]$2530 $1\dp_INT_rb_cr0_1$next[0:0]$2531 + attribute \src "libresoc.v:46014.5-46014.29" switch \initial - attribute \src "libresoc.v:45175.9-45175.17" + attribute \src "libresoc.v:46014.9-46014.17" case 1'1 case end @@ -78619,44 +79617,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_cr0_1$next[0:0]$2514 1'0 + assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 1'0 case - assign $1\dp_INT_rb_cr0_1$next[0:0]$2514 \rp_INT_rb_cr0_1 + assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 \rp_INT_rb_cr0_1 end sync always - update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2513 + update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2530 end - attribute \src "libresoc.v:45183.3-45192.6" - process $proc$libresoc.v:45183$2515 + attribute \src "libresoc.v:46022.3-46031.6" + process $proc$libresoc.v:46022$2532 assign { } { } assign { } { } - assign $0\fus_src2_i$62[63:0]$2516 $1\fus_src2_i$62[63:0]$2517 - attribute \src "libresoc.v:45184.5-45184.29" + assign $0\fus_src2_i$64[63:0]$2533 $1\fus_src2_i$64[63:0]$2534 + attribute \src "libresoc.v:46023.5-46023.29" switch \initial - attribute \src "libresoc.v:45184.9-45184.17" + attribute \src "libresoc.v:46023.9-46023.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$62[63:0]$2517 \int_src2__data_o + assign $1\fus_src2_i$64[63:0]$2534 \int_src2__data_o case - assign $1\fus_src2_i$62[63:0]$2517 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$64[63:0]$2534 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$62 $0\fus_src2_i$62[63:0]$2516 + update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2533 end - attribute \src "libresoc.v:45193.3-45201.6" - process $proc$libresoc.v:45193$2518 + attribute \src "libresoc.v:46032.3-46040.6" + process $proc$libresoc.v:46032$2535 assign { } { } assign { } { } - assign $0\dp_INT_rb_trap0_2$next[0:0]$2519 $1\dp_INT_rb_trap0_2$next[0:0]$2520 - attribute \src "libresoc.v:45194.5-45194.29" + assign $0\dp_INT_rb_trap0_2$next[0:0]$2536 $1\dp_INT_rb_trap0_2$next[0:0]$2537 + attribute \src "libresoc.v:46033.5-46033.29" switch \initial - attribute \src "libresoc.v:45194.9-45194.17" + attribute \src "libresoc.v:46033.9-46033.17" case 1'1 case end @@ -78665,44 +79663,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_trap0_2$next[0:0]$2520 1'0 + assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 1'0 case - assign $1\dp_INT_rb_trap0_2$next[0:0]$2520 \rp_INT_rb_trap0_2 + assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 \rp_INT_rb_trap0_2 end sync always - update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2519 + update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2536 end - attribute \src "libresoc.v:45202.3-45211.6" - process $proc$libresoc.v:45202$2521 + attribute \src "libresoc.v:46041.3-46050.6" + process $proc$libresoc.v:46041$2538 assign { } { } assign { } { } - assign $0\fus_src2_i$63[63:0]$2522 $1\fus_src2_i$63[63:0]$2523 - attribute \src "libresoc.v:45203.5-45203.29" + assign $0\fus_src2_i$65[63:0]$2539 $1\fus_src2_i$65[63:0]$2540 + attribute \src "libresoc.v:46042.5-46042.29" switch \initial - attribute \src "libresoc.v:45203.9-45203.17" + attribute \src "libresoc.v:46042.9-46042.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$63[63:0]$2523 \int_src2__data_o + assign $1\fus_src2_i$65[63:0]$2540 \int_src2__data_o case - assign $1\fus_src2_i$63[63:0]$2523 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$65[63:0]$2540 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$63 $0\fus_src2_i$63[63:0]$2522 + update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2539 end - attribute \src "libresoc.v:45212.3-45220.6" - process $proc$libresoc.v:45212$2524 + attribute \src "libresoc.v:46051.3-46059.6" + process $proc$libresoc.v:46051$2541 assign { } { } assign { } { } - assign $0\dp_INT_rb_logical0_3$next[0:0]$2525 $1\dp_INT_rb_logical0_3$next[0:0]$2526 - attribute \src "libresoc.v:45213.5-45213.29" + assign $0\dp_INT_rb_logical0_3$next[0:0]$2542 $1\dp_INT_rb_logical0_3$next[0:0]$2543 + attribute \src "libresoc.v:46052.5-46052.29" switch \initial - attribute \src "libresoc.v:45213.9-45213.17" + attribute \src "libresoc.v:46052.9-46052.17" case 1'1 case end @@ -78711,44 +79709,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_logical0_3$next[0:0]$2526 1'0 + assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 1'0 case - assign $1\dp_INT_rb_logical0_3$next[0:0]$2526 \rp_INT_rb_logical0_3 + assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 \rp_INT_rb_logical0_3 end sync always - update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2525 + update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2542 end - attribute \src "libresoc.v:45221.3-45230.6" - process $proc$libresoc.v:45221$2527 + attribute \src "libresoc.v:46060.3-46069.6" + process $proc$libresoc.v:46060$2544 assign { } { } assign { } { } - assign $0\fus_src2_i$64[63:0]$2528 $1\fus_src2_i$64[63:0]$2529 - attribute \src "libresoc.v:45222.5-45222.29" + assign $0\fus_src2_i$66[63:0]$2545 $1\fus_src2_i$66[63:0]$2546 + attribute \src "libresoc.v:46061.5-46061.29" switch \initial - attribute \src "libresoc.v:45222.9-45222.17" + attribute \src "libresoc.v:46061.9-46061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$64[63:0]$2529 \int_src2__data_o + assign $1\fus_src2_i$66[63:0]$2546 \int_src2__data_o case - assign $1\fus_src2_i$64[63:0]$2529 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$66[63:0]$2546 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2528 + update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2545 end - attribute \src "libresoc.v:45231.3-45239.6" - process $proc$libresoc.v:45231$2530 + attribute \src "libresoc.v:46070.3-46078.6" + process $proc$libresoc.v:46070$2547 assign { } { } assign { } { } - assign $0\dp_INT_rb_div0_4$next[0:0]$2531 $1\dp_INT_rb_div0_4$next[0:0]$2532 - attribute \src "libresoc.v:45232.5-45232.29" + assign $0\dp_INT_rb_div0_4$next[0:0]$2548 $1\dp_INT_rb_div0_4$next[0:0]$2549 + attribute \src "libresoc.v:46071.5-46071.29" switch \initial - attribute \src "libresoc.v:45232.9-45232.17" + attribute \src "libresoc.v:46071.9-46071.17" case 1'1 case end @@ -78757,44 +79755,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_div0_4$next[0:0]$2532 1'0 + assign $1\dp_INT_rb_div0_4$next[0:0]$2549 1'0 case - assign $1\dp_INT_rb_div0_4$next[0:0]$2532 \rp_INT_rb_div0_4 + assign $1\dp_INT_rb_div0_4$next[0:0]$2549 \rp_INT_rb_div0_4 end sync always - update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2531 + update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2548 end - attribute \src "libresoc.v:45240.3-45249.6" - process $proc$libresoc.v:45240$2533 + attribute \src "libresoc.v:46079.3-46088.6" + process $proc$libresoc.v:46079$2550 assign { } { } assign { } { } - assign $0\fus_src2_i$65[63:0]$2534 $1\fus_src2_i$65[63:0]$2535 - attribute \src "libresoc.v:45241.5-45241.29" + assign $0\fus_src2_i$67[63:0]$2551 $1\fus_src2_i$67[63:0]$2552 + attribute \src "libresoc.v:46080.5-46080.29" switch \initial - attribute \src "libresoc.v:45241.9-45241.17" + attribute \src "libresoc.v:46080.9-46080.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_div0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$65[63:0]$2535 \int_src2__data_o + assign $1\fus_src2_i$67[63:0]$2552 \int_src2__data_o case - assign $1\fus_src2_i$65[63:0]$2535 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$67[63:0]$2552 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2534 + update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2551 end - attribute \src "libresoc.v:45250.3-45258.6" - process $proc$libresoc.v:45250$2536 + attribute \src "libresoc.v:46089.3-46097.6" + process $proc$libresoc.v:46089$2553 assign { } { } assign { } { } - assign $0\dp_INT_rb_mul0_5$next[0:0]$2537 $1\dp_INT_rb_mul0_5$next[0:0]$2538 - attribute \src "libresoc.v:45251.5-45251.29" + assign $0\dp_INT_rb_mul0_5$next[0:0]$2554 $1\dp_INT_rb_mul0_5$next[0:0]$2555 + attribute \src "libresoc.v:46090.5-46090.29" switch \initial - attribute \src "libresoc.v:45251.9-45251.17" + attribute \src "libresoc.v:46090.9-46090.17" case 1'1 case end @@ -78803,44 +79801,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_mul0_5$next[0:0]$2538 1'0 + assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 1'0 case - assign $1\dp_INT_rb_mul0_5$next[0:0]$2538 \rp_INT_rb_mul0_5 + assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 \rp_INT_rb_mul0_5 end sync always - update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2537 + update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2554 end - attribute \src "libresoc.v:45259.3-45268.6" - process $proc$libresoc.v:45259$2539 + attribute \src "libresoc.v:46098.3-46107.6" + process $proc$libresoc.v:46098$2556 assign { } { } assign { } { } - assign $0\fus_src2_i$66[63:0]$2540 $1\fus_src2_i$66[63:0]$2541 - attribute \src "libresoc.v:45260.5-45260.29" + assign $0\fus_src2_i$68[63:0]$2557 $1\fus_src2_i$68[63:0]$2558 + attribute \src "libresoc.v:46099.5-46099.29" switch \initial - attribute \src "libresoc.v:45260.9-45260.17" + attribute \src "libresoc.v:46099.9-46099.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_mul0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$66[63:0]$2541 \int_src2__data_o + assign $1\fus_src2_i$68[63:0]$2558 \int_src2__data_o case - assign $1\fus_src2_i$66[63:0]$2541 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$68[63:0]$2558 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2540 + update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2557 end - attribute \src "libresoc.v:45269.3-45277.6" - process $proc$libresoc.v:45269$2542 + attribute \src "libresoc.v:46108.3-46116.6" + process $proc$libresoc.v:46108$2559 assign { } { } assign { } { } - assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 - attribute \src "libresoc.v:45270.5-45270.29" + assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 + attribute \src "libresoc.v:46109.5-46109.29" switch \initial - attribute \src "libresoc.v:45270.9-45270.17" + attribute \src "libresoc.v:46109.9-46109.17" case 1'1 case end @@ -78849,44 +79847,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 1'0 + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 1'0 case - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 \rp_INT_rb_shiftrot0_6 + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 \rp_INT_rb_shiftrot0_6 end sync always - update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 + update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 end - attribute \src "libresoc.v:45278.3-45287.6" - process $proc$libresoc.v:45278$2545 + attribute \src "libresoc.v:46117.3-46126.6" + process $proc$libresoc.v:46117$2562 assign { } { } assign { } { } - assign $0\fus_src2_i$67[63:0]$2546 $1\fus_src2_i$67[63:0]$2547 - attribute \src "libresoc.v:45279.5-45279.29" + assign $0\fus_src2_i$69[63:0]$2563 $1\fus_src2_i$69[63:0]$2564 + attribute \src "libresoc.v:46118.5-46118.29" switch \initial - attribute \src "libresoc.v:45279.9-45279.17" + attribute \src "libresoc.v:46118.9-46118.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_shiftrot0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$67[63:0]$2547 \int_src2__data_o + assign $1\fus_src2_i$69[63:0]$2564 \int_src2__data_o case - assign $1\fus_src2_i$67[63:0]$2547 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$69[63:0]$2564 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2546 + update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2563 end - attribute \src "libresoc.v:45288.3-45296.6" - process $proc$libresoc.v:45288$2548 + attribute \src "libresoc.v:46127.3-46135.6" + process $proc$libresoc.v:46127$2565 assign { } { } assign { } { } - assign $0\dp_INT_rb_ldst0_7$next[0:0]$2549 $1\dp_INT_rb_ldst0_7$next[0:0]$2550 - attribute \src "libresoc.v:45289.5-45289.29" + assign $0\dp_INT_rb_ldst0_7$next[0:0]$2566 $1\dp_INT_rb_ldst0_7$next[0:0]$2567 + attribute \src "libresoc.v:46128.5-46128.29" switch \initial - attribute \src "libresoc.v:45289.9-45289.17" + attribute \src "libresoc.v:46128.9-46128.17" case 1'1 case end @@ -78895,44 +79893,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2550 1'0 + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 1'0 case - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2550 \rp_INT_rb_ldst0_7 + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 \rp_INT_rb_ldst0_7 end sync always - update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2549 + update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2566 end - attribute \src "libresoc.v:45297.3-45306.6" - process $proc$libresoc.v:45297$2551 + attribute \src "libresoc.v:46136.3-46145.6" + process $proc$libresoc.v:46136$2568 assign { } { } assign { } { } - assign $0\fus_src2_i$68[63:0]$2552 $1\fus_src2_i$68[63:0]$2553 - attribute \src "libresoc.v:45298.5-45298.29" + assign $0\fus_src2_i$70[63:0]$2569 $1\fus_src2_i$70[63:0]$2570 + attribute \src "libresoc.v:46137.5-46137.29" switch \initial - attribute \src "libresoc.v:45298.9-45298.17" + attribute \src "libresoc.v:46137.9-46137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_ldst0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$68[63:0]$2553 \int_src2__data_o + assign $1\fus_src2_i$70[63:0]$2570 \int_src2__data_o case - assign $1\fus_src2_i$68[63:0]$2553 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$70[63:0]$2570 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2552 + update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2569 end - attribute \src "libresoc.v:45307.3-45315.6" - process $proc$libresoc.v:45307$2554 + attribute \src "libresoc.v:46146.3-46154.6" + process $proc$libresoc.v:46146$2571 assign { } { } assign { } { } - assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 - attribute \src "libresoc.v:45308.5-45308.29" + assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 + attribute \src "libresoc.v:46147.5-46147.29" switch \initial - attribute \src "libresoc.v:45308.9-45308.17" + attribute \src "libresoc.v:46147.9-46147.17" case 1'1 case end @@ -78941,25 +79939,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 1'0 + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 1'0 case - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 \rp_INT_rc_shiftrot0_0 + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 \rp_INT_rc_shiftrot0_0 end sync always - update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 + update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 end - attribute \src "libresoc.v:45316.3-45325.6" - process $proc$libresoc.v:45316$2557 + attribute \src "libresoc.v:46155.3-46164.6" + process $proc$libresoc.v:46155$2574 assign { } { } assign { } { } assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45317.5-45317.29" + attribute \src "libresoc.v:46156.5-46156.29" switch \initial - attribute \src "libresoc.v:45317.9-45317.17" + attribute \src "libresoc.v:46156.9-46156.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rc_shiftrot0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78971,14 +79969,14 @@ module \core sync always update \fus_src3_i $0\fus_src3_i[63:0] end - attribute \src "libresoc.v:45326.3-45334.6" - process $proc$libresoc.v:45326$2558 + attribute \src "libresoc.v:46165.3-46173.6" + process $proc$libresoc.v:46165$2575 assign { } { } assign { } { } - assign $0\dp_INT_rc_ldst0_1$next[0:0]$2559 $1\dp_INT_rc_ldst0_1$next[0:0]$2560 - attribute \src "libresoc.v:45327.5-45327.29" + assign $0\dp_INT_rc_ldst0_1$next[0:0]$2576 $1\dp_INT_rc_ldst0_1$next[0:0]$2577 + attribute \src "libresoc.v:46166.5-46166.29" switch \initial - attribute \src "libresoc.v:45327.9-45327.17" + attribute \src "libresoc.v:46166.9-46166.17" case 1'1 case end @@ -78987,96 +79985,90 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2560 1'0 + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 1'0 case - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2560 \rp_INT_rc_ldst0_1 + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 \rp_INT_rc_ldst0_1 end sync always - update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2559 + update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2576 end - attribute \src "libresoc.v:45335.3-45344.6" - process $proc$libresoc.v:45335$2561 + attribute \src "libresoc.v:46174.3-46183.6" + process $proc$libresoc.v:46174$2578 assign { } { } assign { } { } - assign $0\fus_src3_i$69[63:0]$2562 $1\fus_src3_i$69[63:0]$2563 - attribute \src "libresoc.v:45336.5-45336.29" + assign $0\fus_src3_i$71[63:0]$2579 $1\fus_src3_i$71[63:0]$2580 + attribute \src "libresoc.v:46175.5-46175.29" switch \initial - attribute \src "libresoc.v:45336.9-45336.17" + attribute \src "libresoc.v:46175.9-46175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rc_ldst0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$69[63:0]$2563 \int_src3__data_o + assign $1\fus_src3_i$71[63:0]$2580 \int_src3__data_o case - assign $1\fus_src3_i$69[63:0]$2563 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src3_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$69 $0\fus_src3_i$69[63:0]$2562 + update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2579 end - attribute \src "libresoc.v:45345.3-45371.6" - process $proc$libresoc.v:45345$2564 - assign { } { } - assign { } { } + attribute \src "libresoc.v:46184.3-46192.6" + process $proc$libresoc.v:46184$2581 assign { } { } assign { } { } - assign $0\counter$next[1:0]$2565 $4\counter$next[1:0]$2569 - attribute \src "libresoc.v:45346.5-45346.29" + assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 + attribute \src "libresoc.v:46185.5-46185.29" switch \initial - attribute \src "libresoc.v:45346.9-45346.17" + attribute \src "libresoc.v:46185.9-46185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - switch \$214 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\counter$next[1:0]$2566 \$216 [1:0] + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 1'0 case - assign $1\counter$next[1:0]$2566 \counter + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 \rp_XER_xer_so_alu0_0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 + end + attribute \src "libresoc.v:46193.3-46202.6" + process $proc$libresoc.v:46193$2584 + assign { } { } + assign { } { } + assign $0\fus_src3_i$72[0:0]$2585 $1\fus_src3_i$72[0:0]$2586 + attribute \src "libresoc.v:46194.5-46194.29" + switch \initial + attribute \src "libresoc.v:46194.9-46194.17" case 1'1 - assign { } { } - assign $2\counter$next[1:0]$2567 $3\counter$next[1:0]$2568 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign { } { } - assign $3\counter$next[1:0]$2568 2'10 - case - assign $3\counter$next[1:0]$2568 $1\counter$next[1:0]$2566 - end case - assign $2\counter$next[1:0]$2567 $1\counter$next[1:0]$2566 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\counter$next[1:0]$2569 2'00 + assign $1\fus_src3_i$72[0:0]$2586 \xer_src1__data_o [0] case - assign $4\counter$next[1:0]$2569 $2\counter$next[1:0]$2567 + assign $1\fus_src3_i$72[0:0]$2586 1'0 end sync always - update \counter$next $0\counter$next[1:0]$2565 + update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2585 end - attribute \src "libresoc.v:45372.3-45380.6" - process $proc$libresoc.v:45372$2570 + attribute \src "libresoc.v:46203.3-46211.6" + process $proc$libresoc.v:46203$2587 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 - attribute \src "libresoc.v:45373.5-45373.29" + assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 + attribute \src "libresoc.v:46204.5-46204.29" switch \initial - attribute \src "libresoc.v:45373.9-45373.17" + attribute \src "libresoc.v:46204.9-46204.17" case 1'1 case end @@ -79085,190 +80077,90 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 1'0 + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 1'0 case - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 \rp_XER_xer_so_alu0_0 + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 \rp_XER_xer_so_logical0_1 end sync always - update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 + update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 end - attribute \src "libresoc.v:45381.3-45390.6" - process $proc$libresoc.v:45381$2573 + attribute \src "libresoc.v:46212.3-46221.6" + process $proc$libresoc.v:46212$2590 assign { } { } assign { } { } - assign $0\fus_src3_i$70[0:0]$2574 $1\fus_src3_i$70[0:0]$2575 - attribute \src "libresoc.v:45382.5-45382.29" + assign $0\fus_src3_i$73[0:0]$2591 $1\fus_src3_i$73[0:0]$2592 + attribute \src "libresoc.v:46213.5-46213.29" switch \initial - attribute \src "libresoc.v:45382.9-45382.17" + attribute \src "libresoc.v:46213.9-46213.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_logical0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$70[0:0]$2575 \xer_src1__data_o [0] + assign $1\fus_src3_i$73[0:0]$2592 \xer_src1__data_o [0] case - assign $1\fus_src3_i$70[0:0]$2575 1'0 + assign $1\fus_src3_i$73[0:0]$2592 1'0 end sync always - update \fus_src3_i$70 $0\fus_src3_i$70[0:0]$2574 + update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2591 end - attribute \src "libresoc.v:45391.3-45481.6" - process $proc$libresoc.v:45391$2576 + attribute \src "libresoc.v:46222.3-46230.6" + process $proc$libresoc.v:46222$2593 assign { } { } assign { } { } - assign { } { } - assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "libresoc.v:45392.5-45392.29" + assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 + attribute \src "libresoc.v:46223.5-46223.29" switch \initial - attribute \src "libresoc.v:45392.9-45392.17" + attribute \src "libresoc.v:46223.9-46223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - switch \$219 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\corebusy_o[0:0] 1'1 + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 1'0 case - assign $1\corebusy_o[0:0] 1'0 + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 \rp_XER_xer_so_spr0_2 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i + sync always + update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 + end + attribute \src "libresoc.v:46231.3-46240.6" + process $proc$libresoc.v:46231$2596 + assign { } { } + assign { } { } + assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] + attribute \src "libresoc.v:46232.5-46232.29" + switch \initial + attribute \src "libresoc.v:46232.9-46232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign { } { } - assign $3\corebusy_o[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\corebusy_o[0:0] \fus_cu_busy_o - case - assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\corebusy_o[0:0] \fus_cu_busy_o$12 - case - assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\corebusy_o[0:0] \fus_cu_busy_o$15 - case - assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\corebusy_o[0:0] \fus_cu_busy_o$18 - case - assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\corebusy_o[0:0] \fus_cu_busy_o$21 - case - assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\corebusy_o[0:0] \fus_cu_busy_o$24 - case - assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\corebusy_o[0:0] \fus_cu_busy_o$27 - case - assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\corebusy_o[0:0] \fus_cu_busy_o$30 - case - assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $12\corebusy_o[0:0] \fus_cu_busy_o$33 - case - assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\corebusy_o[0:0] \fus_cu_busy_o$36 - case - assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] - end - end + assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] case - assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] + assign $1\fus_src4_i[0:0] 1'0 end sync always - update \corebusy_o $0\corebusy_o[0:0] + update \fus_src4_i $0\fus_src4_i[0:0] end - attribute \src "libresoc.v:45482.3-45490.6" - process $proc$libresoc.v:45482$2577 + attribute \src "libresoc.v:46241.3-46249.6" + process $proc$libresoc.v:46241$2597 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 - attribute \src "libresoc.v:45483.5-45483.29" + assign $0\dp_XER_xer_so_div0_3$next[0:0]$2598 $1\dp_XER_xer_so_div0_3$next[0:0]$2599 + attribute \src "libresoc.v:46242.5-46242.29" switch \initial - attribute \src "libresoc.v:45483.9-45483.17" + attribute \src "libresoc.v:46242.9-46242.17" case 1'1 case end @@ -79277,44 +80169,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 1'0 + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2599 1'0 case - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 \rp_XER_xer_so_logical0_1 + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2599 \rp_XER_xer_so_div0_3 end sync always - update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 + update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2598 end - attribute \src "libresoc.v:45491.3-45500.6" - process $proc$libresoc.v:45491$2580 + attribute \src "libresoc.v:46250.3-46259.6" + process $proc$libresoc.v:46250$2600 assign { } { } assign { } { } - assign $0\fus_src3_i$71[0:0]$2581 $1\fus_src3_i$71[0:0]$2582 - attribute \src "libresoc.v:45492.5-45492.29" + assign $0\fus_src3_i$74[0:0]$2601 $1\fus_src3_i$74[0:0]$2602 + attribute \src "libresoc.v:46251.5-46251.29" switch \initial - attribute \src "libresoc.v:45492.9-45492.17" + attribute \src "libresoc.v:46251.9-46251.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_div0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$71[0:0]$2582 \xer_src1__data_o [0] + assign $1\fus_src3_i$74[0:0]$2602 \xer_src1__data_o [0] case - assign $1\fus_src3_i$71[0:0]$2582 1'0 + assign $1\fus_src3_i$74[0:0]$2602 1'0 end sync always - update \fus_src3_i$71 $0\fus_src3_i$71[0:0]$2581 + update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2601 end - attribute \src "libresoc.v:45501.3-45509.6" - process $proc$libresoc.v:45501$2583 + attribute \src "libresoc.v:46260.3-46268.6" + process $proc$libresoc.v:46260$2603 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 - attribute \src "libresoc.v:45502.5-45502.29" + assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 + attribute \src "libresoc.v:46261.5-46261.29" switch \initial - attribute \src "libresoc.v:45502.9-45502.17" + attribute \src "libresoc.v:46261.9-46261.17" case 1'1 case end @@ -79323,86 +80215,136 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 1'0 + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 1'0 case - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 \rp_XER_xer_so_spr0_2 + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 \rp_XER_xer_so_mul0_4 end sync always - update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 + update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 end - attribute \src "libresoc.v:45510.3-45519.6" - process $proc$libresoc.v:45510$2586 + attribute \src "libresoc.v:46269.3-46278.6" + process $proc$libresoc.v:46269$2606 assign { } { } assign { } { } - assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "libresoc.v:45511.5-45511.29" + assign $0\fus_src3_i$75[0:0]$2607 $1\fus_src3_i$75[0:0]$2608 + attribute \src "libresoc.v:46270.5-46270.29" switch \initial - attribute \src "libresoc.v:45511.9-45511.17" + attribute \src "libresoc.v:46270.9-46270.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_mul0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] + assign $1\fus_src3_i$75[0:0]$2608 \xer_src1__data_o [0] case - assign $1\fus_src4_i[0:0] 1'0 + assign $1\fus_src3_i$75[0:0]$2608 1'0 end sync always - update \fus_src4_i $0\fus_src4_i[0:0] + update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2607 end - attribute \src "libresoc.v:45520.3-45540.6" - process $proc$libresoc.v:45520$2587 + attribute \src "libresoc.v:46279.3-46287.6" + process $proc$libresoc.v:46279$2609 + assign { } { } assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + attribute \src "libresoc.v:46280.5-46280.29" + switch \initial + attribute \src "libresoc.v:46280.9-46280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 1'0 + case + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 \rp_XER_xer_so_shiftrot0_5 + end + sync always + update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 + end + attribute \src "libresoc.v:46288.3-46297.6" + process $proc$libresoc.v:46288$2612 assign { } { } assign { } { } - assign $0\core_terminate_o$next[0:0]$2588 $3\core_terminate_o$next[0:0]$2591 - attribute \src "libresoc.v:45521.5-45521.29" + assign $0\fus_src4_i$76[0:0]$2613 $1\fus_src4_i$76[0:0]$2614 + attribute \src "libresoc.v:46289.5-46289.29" switch \initial - attribute \src "libresoc.v:45521.9-45521.17" + attribute \src "libresoc.v:46289.9-46289.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_shiftrot0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_terminate_o$next[0:0]$2589 $2\core_terminate_o$next[0:0]$2590 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign { } { } - assign $2\core_terminate_o$next[0:0]$2590 1'1 - case - assign $2\core_terminate_o$next[0:0]$2590 \core_terminate_o - end + assign $1\fus_src4_i$76[0:0]$2614 \xer_src1__data_o [0] + case + assign $1\fus_src4_i$76[0:0]$2614 1'0 + end + sync always + update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2613 + end + attribute \src "libresoc.v:46298.3-46306.6" + process $proc$libresoc.v:46298$2615 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 + attribute \src "libresoc.v:46299.5-46299.29" + switch \initial + attribute \src "libresoc.v:46299.9-46299.17" + case 1'1 case - assign $1\core_terminate_o$next[0:0]$2589 \core_terminate_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_terminate_o$next[0:0]$2591 1'0 + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 1'0 + case + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 \rp_XER_xer_ca_alu0_0 + end + sync always + update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 + end + attribute \src "libresoc.v:46307.3-46316.6" + process $proc$libresoc.v:46307$2618 + assign { } { } + assign { } { } + assign $0\fus_src4_i$77[1:0]$2619 $1\fus_src4_i$77[1:0]$2620 + attribute \src "libresoc.v:46308.5-46308.29" + switch \initial + attribute \src "libresoc.v:46308.9-46308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$77[1:0]$2620 \xer_src2__data_o case - assign $3\core_terminate_o$next[0:0]$2591 $1\core_terminate_o$next[0:0]$2589 + assign $1\fus_src4_i$77[1:0]$2620 2'00 end sync always - update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2588 + update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2619 end - attribute \src "libresoc.v:45541.3-45549.6" - process $proc$libresoc.v:45541$2592 + attribute \src "libresoc.v:46317.3-46325.6" + process $proc$libresoc.v:46317$2621 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_div0_3$next[0:0]$2593 $1\dp_XER_xer_so_div0_3$next[0:0]$2594 - attribute \src "libresoc.v:45542.5-45542.29" + assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 + attribute \src "libresoc.v:46318.5-46318.29" switch \initial - attribute \src "libresoc.v:45542.9-45542.17" + attribute \src "libresoc.v:46318.9-46318.17" case 1'1 case end @@ -79411,44 +80353,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2594 1'0 + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 1'0 case - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2594 \rp_XER_xer_so_div0_3 + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 \rp_XER_xer_ca_spr0_1 end sync always - update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2593 + update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 end - attribute \src "libresoc.v:45550.3-45559.6" - process $proc$libresoc.v:45550$2595 + attribute \src "libresoc.v:46326.3-46335.6" + process $proc$libresoc.v:46326$2624 assign { } { } assign { } { } - assign $0\fus_src3_i$72[0:0]$2596 $1\fus_src3_i$72[0:0]$2597 - attribute \src "libresoc.v:45551.5-45551.29" + assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] + attribute \src "libresoc.v:46327.5-46327.29" switch \initial - attribute \src "libresoc.v:45551.9-45551.17" + attribute \src "libresoc.v:46327.9-46327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_spr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$72[0:0]$2597 \xer_src1__data_o [0] + assign $1\fus_src6_i[1:0] \xer_src2__data_o case - assign $1\fus_src3_i$72[0:0]$2597 1'0 + assign $1\fus_src6_i[1:0] 2'00 end sync always - update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2596 + update \fus_src6_i $0\fus_src6_i[1:0] end - attribute \src "libresoc.v:45560.3-45568.6" - process $proc$libresoc.v:45560$2598 + attribute \src "libresoc.v:46336.3-46344.6" + process $proc$libresoc.v:46336$2625 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 - attribute \src "libresoc.v:45561.5-45561.29" + assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 + attribute \src "libresoc.v:46337.5-46337.29" switch \initial - attribute \src "libresoc.v:45561.9-45561.17" + attribute \src "libresoc.v:46337.9-46337.17" case 1'1 case end @@ -79457,89 +80399,90 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 1'0 + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 1'0 case - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 \rp_XER_xer_so_mul0_4 + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 \rp_XER_xer_ca_shiftrot0_2 end sync always - update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 + update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 end - attribute \src "libresoc.v:45569.3-45578.6" - process $proc$libresoc.v:45569$2601 + attribute \src "libresoc.v:46345.3-46354.6" + process $proc$libresoc.v:46345$2628 assign { } { } assign { } { } - assign $0\fus_src3_i$73[0:0]$2602 $1\fus_src3_i$73[0:0]$2603 - attribute \src "libresoc.v:45570.5-45570.29" + assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] + attribute \src "libresoc.v:46346.5-46346.29" switch \initial - attribute \src "libresoc.v:45570.9-45570.17" + attribute \src "libresoc.v:46346.9-46346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_shiftrot0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$73[0:0]$2603 \xer_src1__data_o [0] + assign $1\fus_src5_i[1:0] \xer_src2__data_o case - assign $1\fus_src3_i$73[0:0]$2603 1'0 + assign $1\fus_src5_i[1:0] 2'00 end sync always - update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2602 + update \fus_src5_i $0\fus_src5_i[1:0] end - attribute \src "libresoc.v:45579.3-45607.6" - process $proc$libresoc.v:45579$2604 + attribute \src "libresoc.v:46355.3-46363.6" + process $proc$libresoc.v:46355$2629 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45580.5-45580.29" + assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 + attribute \src "libresoc.v:46356.5-46356.29" switch \initial - attribute \src "libresoc.v:45580.9-45580.17" + attribute \src "libresoc.v:46356.9-46356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type - case - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - end - end + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 1'0 case - assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 \rp_XER_xer_ov_spr0_0 end sync always - update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] + update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 + end + attribute \src "libresoc.v:46364.3-46373.6" + process $proc$libresoc.v:46364$2632 + assign { } { } + assign { } { } + assign $0\fus_src5_i$78[1:0]$2633 $1\fus_src5_i$78[1:0]$2634 + attribute \src "libresoc.v:46365.5-46365.29" + switch \initial + attribute \src "libresoc.v:46365.9-46365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ov_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$78[1:0]$2634 \xer_src3__data_o + case + assign $1\fus_src5_i$78[1:0]$2634 2'00 + end + sync always + update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2633 end - attribute \src "libresoc.v:45608.3-45616.6" - process $proc$libresoc.v:45608$2605 + attribute \src "libresoc.v:46374.3-46382.6" + process $proc$libresoc.v:46374$2635 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 - attribute \src "libresoc.v:45609.5-45609.29" + assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 + attribute \src "libresoc.v:46375.5-46375.29" switch \initial - attribute \src "libresoc.v:45609.9-45609.17" + attribute \src "libresoc.v:46375.9-46375.17" case 1'1 case end @@ -79548,44 +80491,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 1'0 + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 1'0 case - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 \rp_XER_xer_so_shiftrot0_5 + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 \rp_CR_full_cr_cr0_0 end sync always - update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 + update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 end - attribute \src "libresoc.v:45617.3-45626.6" - process $proc$libresoc.v:45617$2608 + attribute \src "libresoc.v:46383.3-46392.6" + process $proc$libresoc.v:46383$2638 assign { } { } assign { } { } - assign $0\fus_src4_i$74[0:0]$2609 $1\fus_src4_i$74[0:0]$2610 - attribute \src "libresoc.v:45618.5-45618.29" + assign $0\fus_src3_i$79[31:0]$2639 $1\fus_src3_i$79[31:0]$2640 + attribute \src "libresoc.v:46384.5-46384.29" switch \initial - attribute \src "libresoc.v:45618.9-45618.17" + attribute \src "libresoc.v:46384.9-46384.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_full_cr_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$74[0:0]$2610 \xer_src1__data_o [0] + assign $1\fus_src3_i$79[31:0]$2640 \cr_full_rd__data_o case - assign $1\fus_src4_i$74[0:0]$2610 1'0 + assign $1\fus_src3_i$79[31:0]$2640 0 end sync always - update \fus_src4_i$74 $0\fus_src4_i$74[0:0]$2609 + update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2639 end - attribute \src "libresoc.v:45627.3-45635.6" - process $proc$libresoc.v:45627$2611 + attribute \src "libresoc.v:46393.3-46401.6" + process $proc$libresoc.v:46393$2641 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 - attribute \src "libresoc.v:45628.5-45628.29" + assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 + attribute \src "libresoc.v:46394.5-46394.29" switch \initial - attribute \src "libresoc.v:45628.9-45628.17" + attribute \src "libresoc.v:46394.9-46394.17" case 1'1 case end @@ -79594,135 +80537,142 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 1'0 + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 1'0 case - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 \rp_XER_xer_ca_alu0_0 + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 \rp_CR_cr_a_cr0_0 end sync always - update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 + update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 end - attribute \src "libresoc.v:45636.3-45664.6" - process $proc$libresoc.v:45636$2614 + attribute \src "libresoc.v:46402.3-46411.6" + process $proc$libresoc.v:46402$2644 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__fn_unit[11:0] $1\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45637.5-45637.29" + assign $0\fus_src4_i$80[3:0]$2645 $1\fus_src4_i$80[3:0]$2646 + attribute \src "libresoc.v:46403.5-46403.29" switch \initial - attribute \src "libresoc.v:45637.9-45637.17" + attribute \src "libresoc.v:46403.9-46403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_a_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] $2\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] $3\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] \dec_ALU_ALU__fn_unit - case - assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - end - end + assign $1\fus_src4_i$80[3:0]$2646 \cr_src1__data_o case - assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + assign $1\fus_src4_i$80[3:0]$2646 4'0000 end sync always - update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[11:0] + update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2645 end - attribute \src "libresoc.v:45665.3-45674.6" - process $proc$libresoc.v:45665$2615 + attribute \src "libresoc.v:46412.3-46420.6" + process $proc$libresoc.v:46412$2647 assign { } { } assign { } { } - assign $0\fus_src4_i$75[1:0]$2616 $1\fus_src4_i$75[1:0]$2617 - attribute \src "libresoc.v:45666.5-45666.29" + assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 + attribute \src "libresoc.v:46413.5-46413.29" switch \initial - attribute \src "libresoc.v:45666.9-45666.17" + attribute \src "libresoc.v:46413.9-46413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$75[1:0]$2617 \xer_src2__data_o + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 1'0 case - assign $1\fus_src4_i$75[1:0]$2617 2'00 + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 \rp_CR_cr_a_branch0_1 end sync always - update \fus_src4_i$75 $0\fus_src4_i$75[1:0]$2616 + update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 end - attribute \src "libresoc.v:45675.3-45683.6" - process $proc$libresoc.v:45675$2618 + attribute \src "libresoc.v:46421.3-46430.6" + process $proc$libresoc.v:46421$2650 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 - attribute \src "libresoc.v:45676.5-45676.29" + assign $0\fus_src3_i$83[3:0]$2651 $1\fus_src3_i$83[3:0]$2652 + attribute \src "libresoc.v:46422.5-46422.29" switch \initial - attribute \src "libresoc.v:45676.9-45676.17" + attribute \src "libresoc.v:46422.9-46422.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_a_branch0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 1'0 + assign $1\fus_src3_i$83[3:0]$2652 \cr_src1__data_o case - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 \rp_XER_xer_ca_spr0_1 + assign $1\fus_src3_i$83[3:0]$2652 4'0000 end sync always - update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 + update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2651 end - attribute \src "libresoc.v:45684.3-45693.6" - process $proc$libresoc.v:45684$2621 + attribute \src "libresoc.v:46431.3-46457.6" + process $proc$libresoc.v:46431$2653 assign { } { } assign { } { } - assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "libresoc.v:45685.5-45685.29" + assign { } { } + assign { } { } + assign $0\counter$next[1:0]$2654 $4\counter$next[1:0]$2658 + attribute \src "libresoc.v:46432.5-46432.29" switch \initial - attribute \src "libresoc.v:45685.9-45685.17" + attribute \src "libresoc.v:46432.9-46432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \$221 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src6_i[1:0] \xer_src2__data_o + assign $1\counter$next[1:0]$2655 \$223 [1:0] case - assign $1\fus_src6_i[1:0] 2'00 + assign $1\counter$next[1:0]$2655 \counter + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter$next[1:0]$2656 $3\counter$next[1:0]$2657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\counter$next[1:0]$2657 2'10 + case + assign $3\counter$next[1:0]$2657 $1\counter$next[1:0]$2655 + end + case + assign $2\counter$next[1:0]$2656 $1\counter$next[1:0]$2655 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\counter$next[1:0]$2658 2'00 + case + assign $4\counter$next[1:0]$2658 $2\counter$next[1:0]$2656 end sync always - update \fus_src6_i $0\fus_src6_i[1:0] + update \counter$next $0\counter$next[1:0]$2654 end - attribute \src "libresoc.v:45694.3-45702.6" - process $proc$libresoc.v:45694$2622 + attribute \src "libresoc.v:46458.3-46466.6" + process $proc$libresoc.v:46458$2659 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 - attribute \src "libresoc.v:45695.5-45695.29" + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:46459.5-46459.29" switch \initial - attribute \src "libresoc.v:45695.9-45695.17" + attribute \src "libresoc.v:46459.9-46459.17" case 1'1 case end @@ -79731,148 +80681,278 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 1'0 + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 1'0 case - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 \rp_XER_xer_ca_shiftrot0_2 + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 \rp_CR_cr_b_cr0_0 end sync always - update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 end - attribute \src "libresoc.v:45703.3-45732.6" - process $proc$libresoc.v:45703$2625 + attribute \src "libresoc.v:46467.3-46476.6" + process $proc$libresoc.v:46467$2662 assign { } { } assign { } { } + assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664 + attribute \src "libresoc.v:46468.5-46468.29" + switch \initial + attribute \src "libresoc.v:46468.9-46468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_b_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$84[3:0]$2664 \cr_src2__data_o + case + assign $1\fus_src5_i$84[3:0]$2664 4'0000 + end + sync always + update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663 + end + attribute \src "libresoc.v:46477.3-46567.6" + process $proc$libresoc.v:46477$2665 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45704.5-45704.29" + assign { } { } + assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] + attribute \src "libresoc.v:46478.5-46478.29" switch \initial - attribute \src "libresoc.v:45704.9-45704.17" + attribute \src "libresoc.v:46478.9-46478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $1\corebusy_o[0:0] 1'1 + case + assign $1\corebusy_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + assign { } { } + assign $3\corebusy_o[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $4\corebusy_o[0:0] \fus_cu_busy_o + case + assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } + assign $5\corebusy_o[0:0] \fus_cu_busy_o$14 case - assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\corebusy_o[0:0] \fus_cu_busy_o$17 + case + assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\corebusy_o[0:0] \fus_cu_busy_o$20 + case + assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\corebusy_o[0:0] \fus_cu_busy_o$23 + case + assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\corebusy_o[0:0] \fus_cu_busy_o$26 + case + assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\corebusy_o[0:0] \fus_cu_busy_o$29 + case + assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\corebusy_o[0:0] \fus_cu_busy_o$32 + case + assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\corebusy_o[0:0] \fus_cu_busy_o$35 + case + assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\corebusy_o[0:0] \fus_cu_busy_o$38 + case + assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] end end case - assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] end sync always - update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + update \corebusy_o $0\corebusy_o[0:0] end - attribute \src "libresoc.v:45733.3-45742.6" - process $proc$libresoc.v:45733$2626 + attribute \src "libresoc.v:46568.3-46576.6" + process $proc$libresoc.v:46568$2666 assign { } { } assign { } { } - assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "libresoc.v:45734.5-45734.29" + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 + attribute \src "libresoc.v:46569.5-46569.29" switch \initial - attribute \src "libresoc.v:45734.9-45734.17" + attribute \src "libresoc.v:46569.9-46569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i[1:0] \xer_src2__data_o + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 1'0 case - assign $1\fus_src5_i[1:0] 2'00 + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 \rp_CR_cr_c_cr0_0 end sync always - update \fus_src5_i $0\fus_src5_i[1:0] + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 end - attribute \src "libresoc.v:45743.3-45751.6" - process $proc$libresoc.v:45743$2627 + attribute \src "libresoc.v:46577.3-46586.6" + process $proc$libresoc.v:46577$2669 assign { } { } assign { } { } - assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 - attribute \src "libresoc.v:45744.5-45744.29" + assign $0\fus_src6_i$85[3:0]$2670 $1\fus_src6_i$85[3:0]$2671 + attribute \src "libresoc.v:46578.5-46578.29" switch \initial - attribute \src "libresoc.v:45744.9-45744.17" + attribute \src "libresoc.v:46578.9-46578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_c_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 1'0 + assign $1\fus_src6_i$85[3:0]$2671 \cr_src3__data_o case - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 \rp_XER_xer_ov_spr0_0 + assign $1\fus_src6_i$85[3:0]$2671 4'0000 end sync always - update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 + update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2670 end - attribute \src "libresoc.v:45752.3-45761.6" - process $proc$libresoc.v:45752$2630 + attribute \src "libresoc.v:46587.3-46607.6" + process $proc$libresoc.v:46587$2672 assign { } { } assign { } { } - assign $0\fus_src5_i$76[1:0]$2631 $1\fus_src5_i$76[1:0]$2632 - attribute \src "libresoc.v:45753.5-45753.29" + assign { } { } + assign $0\core_terminate_o$next[0:0]$2673 $3\core_terminate_o$next[0:0]$2676 + attribute \src "libresoc.v:46588.5-46588.29" switch \initial - attribute \src "libresoc.v:45753.9-45753.17" + attribute \src "libresoc.v:46588.9-46588.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i$76[1:0]$2632 \xer_src3__data_o + assign $1\core_terminate_o$next[0:0]$2674 $2\core_terminate_o$next[0:0]$2675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign { } { } + assign $2\core_terminate_o$next[0:0]$2675 1'1 + case + assign $2\core_terminate_o$next[0:0]$2675 \core_terminate_o + end case - assign $1\fus_src5_i$76[1:0]$2632 2'00 + assign $1\core_terminate_o$next[0:0]$2674 \core_terminate_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_terminate_o$next[0:0]$2676 1'0 + case + assign $3\core_terminate_o$next[0:0]$2676 $1\core_terminate_o$next[0:0]$2674 end sync always - update \fus_src5_i$76 $0\fus_src5_i$76[1:0]$2631 + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2673 end - attribute \src "libresoc.v:45762.3-45770.6" - process $proc$libresoc.v:45762$2633 + attribute \src "libresoc.v:46608.3-46616.6" + process $proc$libresoc.v:46608$2677 assign { } { } assign { } { } - assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 - attribute \src "libresoc.v:45763.5-45763.29" + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 + attribute \src "libresoc.v:46609.5-46609.29" switch \initial - attribute \src "libresoc.v:45763.9-45763.17" + attribute \src "libresoc.v:46609.9-46609.17" case 1'1 case end @@ -79881,102 +80961,135 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 1'0 + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 1'0 case - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 \rp_CR_full_cr_cr0_0 + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 \rp_FAST_fast1_branch0_0 end sync always - update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 end - attribute \src "libresoc.v:45771.3-45780.6" - process $proc$libresoc.v:45771$2636 + attribute \src "libresoc.v:46617.3-46626.6" + process $proc$libresoc.v:46617$2680 assign { } { } assign { } { } - assign $0\fus_src3_i$77[31:0]$2637 $1\fus_src3_i$77[31:0]$2638 - attribute \src "libresoc.v:45772.5-45772.29" + assign $0\fus_src1_i$86[63:0]$2681 $1\fus_src1_i$86[63:0]$2682 + attribute \src "libresoc.v:46618.5-46618.29" switch \initial - attribute \src "libresoc.v:45772.9-45772.17" + attribute \src "libresoc.v:46618.9-46618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$86[63:0]$2682 \fast_src1__data_o + case + assign $1\fus_src1_i$86[63:0]$2682 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2681 + end + attribute \src "libresoc.v:46627.3-46635.6" + process $proc$libresoc.v:46627$2683 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 + attribute \src "libresoc.v:46628.5-46628.29" + switch \initial + attribute \src "libresoc.v:46628.9-46628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$77[31:0]$2638 \cr_full_rd__data_o + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 1'0 case - assign $1\fus_src3_i$77[31:0]$2638 0 + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 \rp_FAST_fast1_trap0_1 end sync always - update \fus_src3_i$77 $0\fus_src3_i$77[31:0]$2637 + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 end - attribute \src "libresoc.v:45781.3-45810.6" - process $proc$libresoc.v:45781$2639 + attribute \src "libresoc.v:46636.3-46645.6" + process $proc$libresoc.v:46636$2686 assign { } { } assign { } { } + assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688 + attribute \src "libresoc.v:46637.5-46637.29" + switch \initial + attribute \src "libresoc.v:46637.9-46637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$87[63:0]$2688 \fast_src1__data_o + case + assign $1\fus_src3_i$87[63:0]$2688 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687 + end + attribute \src "libresoc.v:46646.3-46674.6" + process $proc$libresoc.v:46646$2689 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:45782.5-45782.29" + assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46647.5-46647.29" switch \initial - attribute \src "libresoc.v:45782.9-45782.17" + attribute \src "libresoc.v:46647.9-46647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type case - assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 end end case - assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 end sync always - update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] - update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] + update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] end - attribute \src "libresoc.v:45811.3-45819.6" - process $proc$libresoc.v:45811$2640 + attribute \src "libresoc.v:46675.3-46683.6" + process $proc$libresoc.v:46675$2690 assign { } { } assign { } { } - assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:45812.5-45812.29" + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 + attribute \src "libresoc.v:46676.5-46676.29" switch \initial - attribute \src "libresoc.v:45812.9-45812.17" + attribute \src "libresoc.v:46676.9-46676.17" case 1'1 case end @@ -79985,44 +81098,89 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 1'0 + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 1'0 case - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 \rp_CR_cr_a_cr0_0 + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 \rp_FAST_fast1_spr0_2 end sync always - update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 end - attribute \src "libresoc.v:45820.3-45829.6" - process $proc$libresoc.v:45820$2643 + attribute \src "libresoc.v:46684.3-46693.6" + process $proc$libresoc.v:46684$2693 assign { } { } assign { } { } - assign $0\fus_src4_i$78[3:0]$2644 $1\fus_src4_i$78[3:0]$2645 - attribute \src "libresoc.v:45821.5-45821.29" + assign $0\fus_src3_i$88[63:0]$2694 $1\fus_src3_i$88[63:0]$2695 + attribute \src "libresoc.v:46685.5-46685.29" switch \initial - attribute \src "libresoc.v:45821.9-45821.17" + attribute \src "libresoc.v:46685.9-46685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$78[3:0]$2645 \cr_src1__data_o + assign $1\fus_src3_i$88[63:0]$2695 \fast_src1__data_o + case + assign $1\fus_src3_i$88[63:0]$2695 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2694 + end + attribute \src "libresoc.v:46694.3-46722.6" + process $proc$libresoc.v:46694$2696 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46695.5-46695.29" + switch \initial + attribute \src "libresoc.v:46695.9-46695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] \dec_ALU_ALU__fn_unit + case + assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + end + end case - assign $1\fus_src4_i$78[3:0]$2645 4'0000 + assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_src4_i$78 $0\fus_src4_i$78[3:0]$2644 + update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0] end - attribute \src "libresoc.v:45830.3-45838.6" - process $proc$libresoc.v:45830$2646 + attribute \src "libresoc.v:46723.3-46731.6" + process $proc$libresoc.v:46723$2697 assign { } { } assign { } { } - assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:45831.5-45831.29" + assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 + attribute \src "libresoc.v:46724.5-46724.29" switch \initial - attribute \src "libresoc.v:45831.9-45831.17" + attribute \src "libresoc.v:46724.9-46724.17" case 1'1 case end @@ -80031,44 +81189,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 1'0 + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 1'0 case - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 \rp_CR_cr_a_branch0_1 + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 \rp_FAST_fast2_branch0_0 end sync always - update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 + update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 end - attribute \src "libresoc.v:45839.3-45848.6" - process $proc$libresoc.v:45839$2649 + attribute \src "libresoc.v:46732.3-46741.6" + process $proc$libresoc.v:46732$2700 assign { } { } assign { } { } - assign $0\fus_src3_i$81[3:0]$2650 $1\fus_src3_i$81[3:0]$2651 - attribute \src "libresoc.v:45840.5-45840.29" + assign $0\fus_src2_i$89[63:0]$2701 $1\fus_src2_i$89[63:0]$2702 + attribute \src "libresoc.v:46733.5-46733.29" switch \initial - attribute \src "libresoc.v:45840.9-45840.17" + attribute \src "libresoc.v:46733.9-46733.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast2_branch0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$81[3:0]$2651 \cr_src1__data_o + assign $1\fus_src2_i$89[63:0]$2702 \fast_src2__data_o case - assign $1\fus_src3_i$81[3:0]$2651 4'0000 + assign $1\fus_src2_i$89[63:0]$2702 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$81 $0\fus_src3_i$81[3:0]$2650 + update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2701 end - attribute \src "libresoc.v:45849.3-45857.6" - process $proc$libresoc.v:45849$2652 + attribute \src "libresoc.v:46742.3-46750.6" + process $proc$libresoc.v:46742$2703 assign { } { } assign { } { } - assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 - attribute \src "libresoc.v:45850.5-45850.29" + assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 + attribute \src "libresoc.v:46743.5-46743.29" switch \initial - attribute \src "libresoc.v:45850.9-45850.17" + attribute \src "libresoc.v:46743.9-46743.17" case 1'1 case end @@ -80077,102 +81235,102 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 1'0 + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 1'0 case - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 \rp_CR_cr_b_cr0_0 + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 \rp_FAST_fast2_trap0_1 end sync always - update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 + update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 end - attribute \src "libresoc.v:45858.3-45867.6" - process $proc$libresoc.v:45858$2655 + attribute \src "libresoc.v:46751.3-46760.6" + process $proc$libresoc.v:46751$2706 assign { } { } assign { } { } - assign $0\fus_src5_i$82[3:0]$2656 $1\fus_src5_i$82[3:0]$2657 - attribute \src "libresoc.v:45859.5-45859.29" + assign $0\fus_src4_i$90[63:0]$2707 $1\fus_src4_i$90[63:0]$2708 + attribute \src "libresoc.v:46752.5-46752.29" switch \initial - attribute \src "libresoc.v:45859.9-45859.17" + attribute \src "libresoc.v:46752.9-46752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast2_trap0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i$82[3:0]$2657 \cr_src2__data_o + assign $1\fus_src4_i$90[63:0]$2708 \fast_src2__data_o case - assign $1\fus_src5_i$82[3:0]$2657 4'0000 + assign $1\fus_src4_i$90[63:0]$2708 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src5_i$82 $0\fus_src5_i$82[3:0]$2656 + update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2707 end - attribute \src "libresoc.v:45868.3-45897.6" - process $proc$libresoc.v:45868$2658 + attribute \src "libresoc.v:46761.3-46790.6" + process $proc$libresoc.v:46761$2709 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:45869.5-45869.29" + assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46762.5-46762.29" switch \initial - attribute \src "libresoc.v:45869.9-45869.17" + attribute \src "libresoc.v:46762.9-46762.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } + assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } case - assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 end sync always - update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] - update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] + update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] end - attribute \src "libresoc.v:45898.3-45906.6" - process $proc$libresoc.v:45898$2659 + attribute \src "libresoc.v:46791.3-46799.6" + process $proc$libresoc.v:46791$2710 assign { } { } assign { } { } - assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:45899.5-45899.29" + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 + attribute \src "libresoc.v:46792.5-46792.29" switch \initial - attribute \src "libresoc.v:45899.9-45899.17" + attribute \src "libresoc.v:46792.9-46792.17" case 1'1 case end @@ -80181,44 +81339,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 1'0 + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 1'0 case - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 \rp_CR_cr_c_cr0_0 + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 \rp_SPR_spr1_spr0_0 end sync always - update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 end - attribute \src "libresoc.v:45907.3-45916.6" - process $proc$libresoc.v:45907$2662 + attribute \src "libresoc.v:46800.3-46809.6" + process $proc$libresoc.v:46800$2713 assign { } { } assign { } { } - assign $0\fus_src6_i$83[3:0]$2663 $1\fus_src6_i$83[3:0]$2664 - attribute \src "libresoc.v:45908.5-45908.29" + assign $0\fus_src2_i$91[63:0]$2714 $1\fus_src2_i$91[63:0]$2715 + attribute \src "libresoc.v:46801.5-46801.29" switch \initial - attribute \src "libresoc.v:45908.9-45908.17" + attribute \src "libresoc.v:46801.9-46801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_SPR_spr1_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src6_i$83[3:0]$2664 \cr_src3__data_o + assign $1\fus_src2_i$91[63:0]$2715 \spr_spr1__data_o case - assign $1\fus_src6_i$83[3:0]$2664 4'0000 + assign $1\fus_src2_i$91[63:0]$2715 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src6_i$83 $0\fus_src6_i$83[3:0]$2663 + update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2714 end - attribute \src "libresoc.v:45917.3-45925.6" - process $proc$libresoc.v:45917$2665 + attribute \src "libresoc.v:46810.3-46818.6" + process $proc$libresoc.v:46810$2716 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 - attribute \src "libresoc.v:45918.5-45918.29" + assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718 + attribute \src "libresoc.v:46811.5-46811.29" switch \initial - attribute \src "libresoc.v:45918.9-45918.17" + attribute \src "libresoc.v:46811.9-46811.17" case 1'1 case end @@ -80227,44 +81385,102 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 1'0 + assign $1\wr_pick_dly$next[0:0]$2718 1'0 case - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 \rp_FAST_fast1_branch0_0 + assign $1\wr_pick_dly$next[0:0]$2718 \wr_pick end sync always - update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717 end - attribute \src "libresoc.v:45926.3-45935.6" - process $proc$libresoc.v:45926$2668 + attribute \src "libresoc.v:46819.3-46827.6" + process $proc$libresoc.v:46819$2719 assign { } { } assign { } { } - assign $0\fus_src1_i$84[63:0]$2669 $1\fus_src1_i$84[63:0]$2670 - attribute \src "libresoc.v:45927.5-45927.29" + assign $0\wr_pick_dly$991$next[0:0]$2720 $1\wr_pick_dly$991$next[0:0]$2721 + attribute \src "libresoc.v:46820.5-46820.29" switch \initial - attribute \src "libresoc.v:45927.9-45927.17" + attribute \src "libresoc.v:46820.9-46820.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$991$next[0:0]$2721 1'0 + case + assign $1\wr_pick_dly$991$next[0:0]$2721 \wr_pick$988 + end + sync always + update \wr_pick_dly$991$next $0\wr_pick_dly$991$next[0:0]$2720 + end + attribute \src "libresoc.v:46828.3-46857.6" + process $proc$libresoc.v:46828$2722 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46829.5-46829.29" + switch \initial + attribute \src "libresoc.v:46829.9-46829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$84[63:0]$2670 \fast_src1__data_o + assign { } { } + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } + case + assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + end case - assign $1\fus_src1_i$84[63:0]$2670 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 end sync always - update \fus_src1_i$84 $0\fus_src1_i$84[63:0]$2669 + update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] + update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] end - attribute \src "libresoc.v:45936.3-45944.6" - process $proc$libresoc.v:45936$2671 + attribute \src "libresoc.v:46858.3-46866.6" + process $proc$libresoc.v:46858$2723 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 - attribute \src "libresoc.v:45937.5-45937.29" + assign $0\wr_pick_dly$1010$next[0:0]$2724 $1\wr_pick_dly$1010$next[0:0]$2725 + attribute \src "libresoc.v:46859.5-46859.29" switch \initial - attribute \src "libresoc.v:45937.9-45937.17" + attribute \src "libresoc.v:46859.9-46859.17" case 1'1 case end @@ -80273,89 +81489,102 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 1'0 + assign $1\wr_pick_dly$1010$next[0:0]$2725 1'0 case - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 \rp_FAST_fast1_trap0_1 + assign $1\wr_pick_dly$1010$next[0:0]$2725 \wr_pick$1007 end sync always - update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 + update \wr_pick_dly$1010$next $0\wr_pick_dly$1010$next[0:0]$2724 end - attribute \src "libresoc.v:45945.3-45954.6" - process $proc$libresoc.v:45945$2674 + attribute \src "libresoc.v:46867.3-46875.6" + process $proc$libresoc.v:46867$2726 assign { } { } assign { } { } - assign $0\fus_src3_i$85[63:0]$2675 $1\fus_src3_i$85[63:0]$2676 - attribute \src "libresoc.v:45946.5-45946.29" + assign $0\wr_pick_dly$1031$next[0:0]$2727 $1\wr_pick_dly$1031$next[0:0]$2728 + attribute \src "libresoc.v:46868.5-46868.29" switch \initial - attribute \src "libresoc.v:45946.9-45946.17" + attribute \src "libresoc.v:46868.9-46868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$85[63:0]$2676 \fast_src1__data_o + assign $1\wr_pick_dly$1031$next[0:0]$2728 1'0 case - assign $1\fus_src3_i$85[63:0]$2676 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1031$next[0:0]$2728 \wr_pick$1028 end sync always - update \fus_src3_i$85 $0\fus_src3_i$85[63:0]$2675 + update \wr_pick_dly$1031$next $0\wr_pick_dly$1031$next[0:0]$2727 end - attribute \src "libresoc.v:45955.3-45983.6" - process $proc$libresoc.v:45955$2677 + attribute \src "libresoc.v:46876.3-46905.6" + process $proc$libresoc.v:46876$2729 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:45956.5-45956.29" + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46877.5-46877.29" switch \initial - attribute \src "libresoc.v:45956.9-45956.17" + attribute \src "libresoc.v:46877.9-46877.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign { } { } + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign { } { } + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in + assign { } { } + assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } case - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 end sync always - update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] + update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] + update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] end - attribute \src "libresoc.v:45984.3-45992.6" - process $proc$libresoc.v:45984$2678 + attribute \src "libresoc.v:46906.3-46914.6" + process $proc$libresoc.v:46906$2730 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 - attribute \src "libresoc.v:45985.5-45985.29" + assign $0\wr_pick_dly$1049$next[0:0]$2731 $1\wr_pick_dly$1049$next[0:0]$2732 + attribute \src "libresoc.v:46907.5-46907.29" switch \initial - attribute \src "libresoc.v:45985.9-45985.17" + attribute \src "libresoc.v:46907.9-46907.17" case 1'1 case end @@ -80364,89 +81593,112 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 1'0 + assign $1\wr_pick_dly$1049$next[0:0]$2732 1'0 case - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 \rp_FAST_fast1_spr0_2 + assign $1\wr_pick_dly$1049$next[0:0]$2732 \wr_pick$1046 end sync always - update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 + update \wr_pick_dly$1049$next $0\wr_pick_dly$1049$next[0:0]$2731 end - attribute \src "libresoc.v:45993.3-46002.6" - process $proc$libresoc.v:45993$2681 + attribute \src "libresoc.v:46915.3-46923.6" + process $proc$libresoc.v:46915$2733 assign { } { } assign { } { } - assign $0\fus_src3_i$86[63:0]$2682 $1\fus_src3_i$86[63:0]$2683 - attribute \src "libresoc.v:45994.5-45994.29" + assign $0\wr_pick_dly$1071$next[0:0]$2734 $1\wr_pick_dly$1071$next[0:0]$2735 + attribute \src "libresoc.v:46916.5-46916.29" switch \initial - attribute \src "libresoc.v:45994.9-45994.17" + attribute \src "libresoc.v:46916.9-46916.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$86[63:0]$2683 \fast_src1__data_o + assign $1\wr_pick_dly$1071$next[0:0]$2735 1'0 case - assign $1\fus_src3_i$86[63:0]$2683 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1071$next[0:0]$2735 \wr_pick$1068 end sync always - update \fus_src3_i$86 $0\fus_src3_i$86[63:0]$2682 + update \wr_pick_dly$1071$next $0\wr_pick_dly$1071$next[0:0]$2734 end - attribute \src "libresoc.v:46003.3-46031.6" - process $proc$libresoc.v:46003$2684 + attribute \src "libresoc.v:46924.3-46932.6" + process $proc$libresoc.v:46924$2736 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46004.5-46004.29" + assign $0\wr_pick_dly$1091$next[0:0]$2737 $1\wr_pick_dly$1091$next[0:0]$2738 + attribute \src "libresoc.v:46925.5-46925.29" switch \initial - attribute \src "libresoc.v:46004.9-46004.17" + attribute \src "libresoc.v:46925.9-46925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1091$next[0:0]$2738 1'0 + case + assign $1\wr_pick_dly$1091$next[0:0]$2738 \wr_pick$1088 + end + sync always + update \wr_pick_dly$1091$next $0\wr_pick_dly$1091$next[0:0]$2737 + end + attribute \src "libresoc.v:46933.3-46961.6" + process $proc$libresoc.v:46933$2739 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46934.5-46934.29" + switch \initial + attribute \src "libresoc.v:46934.9-46934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in case - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 end sync always - update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] + update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] end - attribute \src "libresoc.v:46032.3-46040.6" - process $proc$libresoc.v:46032$2685 + attribute \src "libresoc.v:46962.3-46970.6" + process $proc$libresoc.v:46962$2740 assign { } { } assign { } { } - assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 - attribute \src "libresoc.v:46033.5-46033.29" + assign $0\wr_pick_dly$1111$next[0:0]$2741 $1\wr_pick_dly$1111$next[0:0]$2742 + attribute \src "libresoc.v:46963.5-46963.29" switch \initial - attribute \src "libresoc.v:46033.9-46033.17" + attribute \src "libresoc.v:46963.9-46963.17" case 1'1 case end @@ -80455,100 +81707,122 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 1'0 + assign $1\wr_pick_dly$1111$next[0:0]$2742 1'0 case - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 \rp_FAST_fast2_branch0_0 + assign $1\wr_pick_dly$1111$next[0:0]$2742 \wr_pick$1108 end sync always - update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 + update \wr_pick_dly$1111$next $0\wr_pick_dly$1111$next[0:0]$2741 end - attribute \src "libresoc.v:46041.3-46050.6" - process $proc$libresoc.v:46041$2688 + attribute \src "libresoc.v:46971.3-46979.6" + process $proc$libresoc.v:46971$2743 assign { } { } assign { } { } - assign $0\fus_src2_i$87[63:0]$2689 $1\fus_src2_i$87[63:0]$2690 - attribute \src "libresoc.v:46042.5-46042.29" + assign $0\wr_pick_dly$1130$next[0:0]$2744 $1\wr_pick_dly$1130$next[0:0]$2745 + attribute \src "libresoc.v:46972.5-46972.29" switch \initial - attribute \src "libresoc.v:46042.9-46042.17" + attribute \src "libresoc.v:46972.9-46972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$87[63:0]$2690 \fast_src2__data_o + assign $1\wr_pick_dly$1130$next[0:0]$2745 1'0 case - assign $1\fus_src2_i$87[63:0]$2690 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1130$next[0:0]$2745 \wr_pick$1127 end sync always - update \fus_src2_i$87 $0\fus_src2_i$87[63:0]$2689 + update \wr_pick_dly$1130$next $0\wr_pick_dly$1130$next[0:0]$2744 end - attribute \src "libresoc.v:46051.3-46059.6" - process $proc$libresoc.v:46051$2691 + attribute \src "libresoc.v:46980.3-47008.6" + process $proc$libresoc.v:46980$2746 assign { } { } assign { } { } - assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 - attribute \src "libresoc.v:46052.5-46052.29" + assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46981.5-46981.29" switch \initial - attribute \src "libresoc.v:46052.9-46052.17" + attribute \src "libresoc.v:46981.9-46981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 1'0 + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a + case + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + end case - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 \rp_FAST_fast2_trap0_1 + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 end sync always - update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 + update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] end - attribute \src "libresoc.v:46060.3-46069.6" - process $proc$libresoc.v:46060$2694 + attribute \src "libresoc.v:47009.3-47017.6" + process $proc$libresoc.v:47009$2747 assign { } { } assign { } { } - assign $0\fus_src4_i$88[63:0]$2695 $1\fus_src4_i$88[63:0]$2696 - attribute \src "libresoc.v:46061.5-46061.29" + assign $0\wr_pick_dly$1148$next[0:0]$2748 $1\wr_pick_dly$1148$next[0:0]$2749 + attribute \src "libresoc.v:47010.5-47010.29" switch \initial - attribute \src "libresoc.v:46061.9-46061.17" + attribute \src "libresoc.v:47010.9-47010.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$88[63:0]$2696 \fast_src2__data_o + assign $1\wr_pick_dly$1148$next[0:0]$2749 1'0 case - assign $1\fus_src4_i$88[63:0]$2696 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1148$next[0:0]$2749 \wr_pick$1145 end sync always - update \fus_src4_i$88 $0\fus_src4_i$88[63:0]$2695 + update \wr_pick_dly$1148$next $0\wr_pick_dly$1148$next[0:0]$2748 end - attribute \src "libresoc.v:46070.3-46098.6" - process $proc$libresoc.v:46070$2697 + attribute \src "libresoc.v:47018.3-47046.6" + process $proc$libresoc.v:47018$2750 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46071.5-46071.29" + attribute \src "libresoc.v:47019.5-47019.29" switch \initial - attribute \src "libresoc.v:46071.9-46071.17" + attribute \src "libresoc.v:47019.9-47019.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80560,7 +81834,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80576,14 +81850,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] end - attribute \src "libresoc.v:46099.3-46107.6" - process $proc$libresoc.v:46099$2698 + attribute \src "libresoc.v:47047.3-47055.6" + process $proc$libresoc.v:47047$2751 assign { } { } assign { } { } - assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 - attribute \src "libresoc.v:46100.5-46100.29" + assign $0\wr_pick_dly$1222$next[0:0]$2752 $1\wr_pick_dly$1222$next[0:0]$2753 + attribute \src "libresoc.v:47048.5-47048.29" switch \initial - attribute \src "libresoc.v:46100.9-46100.17" + attribute \src "libresoc.v:47048.9-47048.17" case 1'1 case end @@ -80592,54 +81866,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 1'0 + assign $1\wr_pick_dly$1222$next[0:0]$2753 1'0 case - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 \rp_SPR_spr1_spr0_0 + assign $1\wr_pick_dly$1222$next[0:0]$2753 \wr_pick$1219 end sync always - update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 + update \wr_pick_dly$1222$next $0\wr_pick_dly$1222$next[0:0]$2752 end - attribute \src "libresoc.v:46108.3-46117.6" - process $proc$libresoc.v:46108$2701 - assign { } { } - assign { } { } - assign $0\fus_src2_i$89[63:0]$2702 $1\fus_src2_i$89[63:0]$2703 - attribute \src "libresoc.v:46109.5-46109.29" - switch \initial - attribute \src "libresoc.v:46109.9-46109.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_SPR_spr1_spr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$89[63:0]$2703 \spr_spr1__data_o - case - assign $1\fus_src2_i$89[63:0]$2703 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2702 - end - attribute \src "libresoc.v:46118.3-46146.6" - process $proc$libresoc.v:46118$2704 + attribute \src "libresoc.v:47056.3-47084.6" + process $proc$libresoc.v:47056$2754 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46119.5-46119.29" + attribute \src "libresoc.v:47057.5-47057.29" switch \initial - attribute \src "libresoc.v:46119.9-46119.17" + attribute \src "libresoc.v:47057.9-47057.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80651,7 +81902,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80667,14 +81918,14 @@ module \core sync always update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] end - attribute \src "libresoc.v:46147.3-46155.6" - process $proc$libresoc.v:46147$2705 + attribute \src "libresoc.v:47085.3-47093.6" + process $proc$libresoc.v:47085$2755 assign { } { } assign { } { } - assign $0\wr_pick_dly$next[0:0]$2706 $1\wr_pick_dly$next[0:0]$2707 - attribute \src "libresoc.v:46148.5-46148.29" + assign $0\wr_pick_dly$1250$next[0:0]$2756 $1\wr_pick_dly$1250$next[0:0]$2757 + attribute \src "libresoc.v:47086.5-47086.29" switch \initial - attribute \src "libresoc.v:46148.9-46148.17" + attribute \src "libresoc.v:47086.9-47086.17" case 1'1 case end @@ -80683,31 +81934,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$next[0:0]$2707 1'0 + assign $1\wr_pick_dly$1250$next[0:0]$2757 1'0 case - assign $1\wr_pick_dly$next[0:0]$2707 \wr_pick + assign $1\wr_pick_dly$1250$next[0:0]$2757 \wr_pick$1247 end sync always - update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2706 + update \wr_pick_dly$1250$next $0\wr_pick_dly$1250$next[0:0]$2756 end - attribute \src "libresoc.v:46156.3-46184.6" - process $proc$libresoc.v:46156$2708 + attribute \src "libresoc.v:47094.3-47122.6" + process $proc$libresoc.v:47094$2758 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46157.5-46157.29" + attribute \src "libresoc.v:47095.5-47095.29" switch \initial - attribute \src "libresoc.v:46157.9-46157.17" + attribute \src "libresoc.v:47095.9-47095.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80719,7 +81970,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80735,14 +81986,14 @@ module \core sync always update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] end - attribute \src "libresoc.v:46185.3-46193.6" - process $proc$libresoc.v:46185$2709 + attribute \src "libresoc.v:47123.3-47131.6" + process $proc$libresoc.v:47123$2759 assign { } { } assign { } { } - assign $0\wr_pick_dly$981$next[0:0]$2710 $1\wr_pick_dly$981$next[0:0]$2711 - attribute \src "libresoc.v:46186.5-46186.29" + assign $0\wr_pick_dly$1270$next[0:0]$2760 $1\wr_pick_dly$1270$next[0:0]$2761 + attribute \src "libresoc.v:47124.5-47124.29" switch \initial - attribute \src "libresoc.v:46186.9-46186.17" + attribute \src "libresoc.v:47124.9-47124.17" case 1'1 case end @@ -80751,21 +82002,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$981$next[0:0]$2711 1'0 + assign $1\wr_pick_dly$1270$next[0:0]$2761 1'0 case - assign $1\wr_pick_dly$981$next[0:0]$2711 \wr_pick$978 + assign $1\wr_pick_dly$1270$next[0:0]$2761 \wr_pick$1267 end sync always - update \wr_pick_dly$981$next $0\wr_pick_dly$981$next[0:0]$2710 + update \wr_pick_dly$1270$next $0\wr_pick_dly$1270$next[0:0]$2760 end - attribute \src "libresoc.v:46194.3-46202.6" - process $proc$libresoc.v:46194$2712 + attribute \src "libresoc.v:47132.3-47140.6" + process $proc$libresoc.v:47132$2762 assign { } { } assign { } { } - assign $0\wr_pick_dly$1000$next[0:0]$2713 $1\wr_pick_dly$1000$next[0:0]$2714 - attribute \src "libresoc.v:46195.5-46195.29" + assign $0\wr_pick_dly$1290$next[0:0]$2763 $1\wr_pick_dly$1290$next[0:0]$2764 + attribute \src "libresoc.v:47133.5-47133.29" switch \initial - attribute \src "libresoc.v:46195.9-46195.17" + attribute \src "libresoc.v:47133.9-47133.17" case 1'1 case end @@ -80774,31 +82025,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1000$next[0:0]$2714 1'0 + assign $1\wr_pick_dly$1290$next[0:0]$2764 1'0 case - assign $1\wr_pick_dly$1000$next[0:0]$2714 \wr_pick$997 + assign $1\wr_pick_dly$1290$next[0:0]$2764 \wr_pick$1287 end sync always - update \wr_pick_dly$1000$next $0\wr_pick_dly$1000$next[0:0]$2713 + update \wr_pick_dly$1290$next $0\wr_pick_dly$1290$next[0:0]$2763 end - attribute \src "libresoc.v:46203.3-46231.6" - process $proc$libresoc.v:46203$2715 + attribute \src "libresoc.v:47141.3-47169.6" + process $proc$libresoc.v:47141$2765 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46204.5-46204.29" + attribute \src "libresoc.v:47142.5-47142.29" switch \initial - attribute \src "libresoc.v:46204.9-46204.17" + attribute \src "libresoc.v:47142.9-47142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80810,7 +82061,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80826,14 +82077,14 @@ module \core sync always update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] end - attribute \src "libresoc.v:46232.3-46240.6" - process $proc$libresoc.v:46232$2716 + attribute \src "libresoc.v:47170.3-47178.6" + process $proc$libresoc.v:47170$2766 assign { } { } assign { } { } - assign $0\wr_pick_dly$1021$next[0:0]$2717 $1\wr_pick_dly$1021$next[0:0]$2718 - attribute \src "libresoc.v:46233.5-46233.29" + assign $0\wr_pick_dly$1310$next[0:0]$2767 $1\wr_pick_dly$1310$next[0:0]$2768 + attribute \src "libresoc.v:47171.5-47171.29" switch \initial - attribute \src "libresoc.v:46233.9-46233.17" + attribute \src "libresoc.v:47171.9-47171.17" case 1'1 case end @@ -80842,31 +82093,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1021$next[0:0]$2718 1'0 + assign $1\wr_pick_dly$1310$next[0:0]$2768 1'0 case - assign $1\wr_pick_dly$1021$next[0:0]$2718 \wr_pick$1018 + assign $1\wr_pick_dly$1310$next[0:0]$2768 \wr_pick$1307 end sync always - update \wr_pick_dly$1021$next $0\wr_pick_dly$1021$next[0:0]$2717 + update \wr_pick_dly$1310$next $0\wr_pick_dly$1310$next[0:0]$2767 end - attribute \src "libresoc.v:46241.3-46269.6" - process $proc$libresoc.v:46241$2719 + attribute \src "libresoc.v:47179.3-47187.6" + process $proc$libresoc.v:47179$2769 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1330$next[0:0]$2770 $1\wr_pick_dly$1330$next[0:0]$2771 + attribute \src "libresoc.v:47180.5-47180.29" + switch \initial + attribute \src "libresoc.v:47180.9-47180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1330$next[0:0]$2771 1'0 + case + assign $1\wr_pick_dly$1330$next[0:0]$2771 \wr_pick$1327 + end + sync always + update \wr_pick_dly$1330$next $0\wr_pick_dly$1330$next[0:0]$2770 + end + attribute \src "libresoc.v:47188.3-47216.6" + process $proc$libresoc.v:47188$2772 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46242.5-46242.29" + attribute \src "libresoc.v:47189.5-47189.29" switch \initial - attribute \src "libresoc.v:46242.9-46242.17" + attribute \src "libresoc.v:47189.9-47189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80878,7 +82152,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80894,37 +82168,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] end - attribute \src "libresoc.v:46270.3-46278.6" - process $proc$libresoc.v:46270$2720 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1039$next[0:0]$2721 $1\wr_pick_dly$1039$next[0:0]$2722 - attribute \src "libresoc.v:46271.5-46271.29" - switch \initial - attribute \src "libresoc.v:46271.9-46271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1039$next[0:0]$2722 1'0 - case - assign $1\wr_pick_dly$1039$next[0:0]$2722 \wr_pick$1036 - end - sync always - update \wr_pick_dly$1039$next $0\wr_pick_dly$1039$next[0:0]$2721 - end - attribute \src "libresoc.v:46279.3-46287.6" - process $proc$libresoc.v:46279$2723 + attribute \src "libresoc.v:47217.3-47225.6" + process $proc$libresoc.v:47217$2773 assign { } { } assign { } { } - assign $0\wr_pick_dly$1061$next[0:0]$2724 $1\wr_pick_dly$1061$next[0:0]$2725 - attribute \src "libresoc.v:46280.5-46280.29" + assign $0\wr_pick_dly$1350$next[0:0]$2774 $1\wr_pick_dly$1350$next[0:0]$2775 + attribute \src "libresoc.v:47218.5-47218.29" switch \initial - attribute \src "libresoc.v:46280.9-46280.17" + attribute \src "libresoc.v:47218.9-47218.17" case 1'1 case end @@ -80933,31 +82184,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1061$next[0:0]$2725 1'0 + assign $1\wr_pick_dly$1350$next[0:0]$2775 1'0 case - assign $1\wr_pick_dly$1061$next[0:0]$2725 \wr_pick$1058 + assign $1\wr_pick_dly$1350$next[0:0]$2775 \wr_pick$1347 end sync always - update \wr_pick_dly$1061$next $0\wr_pick_dly$1061$next[0:0]$2724 + update \wr_pick_dly$1350$next $0\wr_pick_dly$1350$next[0:0]$2774 end - attribute \src "libresoc.v:46288.3-46316.6" - process $proc$libresoc.v:46288$2726 + attribute \src "libresoc.v:47226.3-47254.6" + process $proc$libresoc.v:47226$2776 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46289.5-46289.29" + attribute \src "libresoc.v:47227.5-47227.29" switch \initial - attribute \src "libresoc.v:46289.9-46289.17" + attribute \src "libresoc.v:47227.9-47227.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80969,7 +82220,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80985,14 +82236,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] end - attribute \src "libresoc.v:46317.3-46325.6" - process $proc$libresoc.v:46317$2727 + attribute \src "libresoc.v:47255.3-47263.6" + process $proc$libresoc.v:47255$2777 assign { } { } assign { } { } - assign $0\wr_pick_dly$1081$next[0:0]$2728 $1\wr_pick_dly$1081$next[0:0]$2729 - attribute \src "libresoc.v:46318.5-46318.29" + assign $0\wr_pick_dly$1397$next[0:0]$2778 $1\wr_pick_dly$1397$next[0:0]$2779 + attribute \src "libresoc.v:47256.5-47256.29" switch \initial - attribute \src "libresoc.v:46318.9-46318.17" + attribute \src "libresoc.v:47256.9-47256.17" case 1'1 case end @@ -81001,31 +82252,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1081$next[0:0]$2729 1'0 + assign $1\wr_pick_dly$1397$next[0:0]$2779 1'0 case - assign $1\wr_pick_dly$1081$next[0:0]$2729 \wr_pick$1078 + assign $1\wr_pick_dly$1397$next[0:0]$2779 \wr_pick$1394 end sync always - update \wr_pick_dly$1081$next $0\wr_pick_dly$1081$next[0:0]$2728 + update \wr_pick_dly$1397$next $0\wr_pick_dly$1397$next[0:0]$2778 end - attribute \src "libresoc.v:46326.3-46354.6" - process $proc$libresoc.v:46326$2730 + attribute \src "libresoc.v:47264.3-47272.6" + process $proc$libresoc.v:47264$2780 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1413$next[0:0]$2781 $1\wr_pick_dly$1413$next[0:0]$2782 + attribute \src "libresoc.v:47265.5-47265.29" + switch \initial + attribute \src "libresoc.v:47265.9-47265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1413$next[0:0]$2782 1'0 + case + assign $1\wr_pick_dly$1413$next[0:0]$2782 \wr_pick$1410 + end + sync always + update \wr_pick_dly$1413$next $0\wr_pick_dly$1413$next[0:0]$2781 + end + attribute \src "libresoc.v:47273.3-47301.6" + process $proc$libresoc.v:47273$2783 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46327.5-46327.29" + attribute \src "libresoc.v:47274.5-47274.29" switch \initial - attribute \src "libresoc.v:46327.9-46327.17" + attribute \src "libresoc.v:47274.9-47274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81037,7 +82311,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81053,14 +82327,14 @@ module \core sync always update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] end - attribute \src "libresoc.v:46355.3-46363.6" - process $proc$libresoc.v:46355$2731 + attribute \src "libresoc.v:47302.3-47310.6" + process $proc$libresoc.v:47302$2784 assign { } { } assign { } { } - assign $0\wr_pick_dly$1101$next[0:0]$2732 $1\wr_pick_dly$1101$next[0:0]$2733 - attribute \src "libresoc.v:46356.5-46356.29" + assign $0\wr_pick_dly$1429$next[0:0]$2785 $1\wr_pick_dly$1429$next[0:0]$2786 + attribute \src "libresoc.v:47303.5-47303.29" switch \initial - attribute \src "libresoc.v:46356.9-46356.17" + attribute \src "libresoc.v:47303.9-47303.17" case 1'1 case end @@ -81069,54 +82343,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1101$next[0:0]$2733 1'0 + assign $1\wr_pick_dly$1429$next[0:0]$2786 1'0 case - assign $1\wr_pick_dly$1101$next[0:0]$2733 \wr_pick$1098 + assign $1\wr_pick_dly$1429$next[0:0]$2786 \wr_pick$1426 end sync always - update \wr_pick_dly$1101$next $0\wr_pick_dly$1101$next[0:0]$2732 + update \wr_pick_dly$1429$next $0\wr_pick_dly$1429$next[0:0]$2785 end - attribute \src "libresoc.v:46364.3-46372.6" - process $proc$libresoc.v:46364$2734 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1120$next[0:0]$2735 $1\wr_pick_dly$1120$next[0:0]$2736 - attribute \src "libresoc.v:46365.5-46365.29" - switch \initial - attribute \src "libresoc.v:46365.9-46365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1120$next[0:0]$2736 1'0 - case - assign $1\wr_pick_dly$1120$next[0:0]$2736 \wr_pick$1117 - end - sync always - update \wr_pick_dly$1120$next $0\wr_pick_dly$1120$next[0:0]$2735 - end - attribute \src "libresoc.v:46373.3-46401.6" - process $proc$libresoc.v:46373$2737 + attribute \src "libresoc.v:47311.3-47339.6" + process $proc$libresoc.v:47311$2787 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46374.5-46374.29" + attribute \src "libresoc.v:47312.5-47312.29" switch \initial - attribute \src "libresoc.v:46374.9-46374.17" + attribute \src "libresoc.v:47312.9-47312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81128,7 +82379,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81144,14 +82395,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] end - attribute \src "libresoc.v:46402.3-46410.6" - process $proc$libresoc.v:46402$2738 + attribute \src "libresoc.v:47340.3-47348.6" + process $proc$libresoc.v:47340$2788 assign { } { } assign { } { } - assign $0\wr_pick_dly$1138$next[0:0]$2739 $1\wr_pick_dly$1138$next[0:0]$2740 - attribute \src "libresoc.v:46403.5-46403.29" + assign $0\wr_pick_dly$1463$next[0:0]$2789 $1\wr_pick_dly$1463$next[0:0]$2790 + attribute \src "libresoc.v:47341.5-47341.29" switch \initial - attribute \src "libresoc.v:46403.9-46403.17" + attribute \src "libresoc.v:47341.9-47341.17" case 1'1 case end @@ -81160,31 +82411,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1138$next[0:0]$2740 1'0 + assign $1\wr_pick_dly$1463$next[0:0]$2790 1'0 case - assign $1\wr_pick_dly$1138$next[0:0]$2740 \wr_pick$1135 + assign $1\wr_pick_dly$1463$next[0:0]$2790 \wr_pick$1460 end sync always - update \wr_pick_dly$1138$next $0\wr_pick_dly$1138$next[0:0]$2739 + update \wr_pick_dly$1463$next $0\wr_pick_dly$1463$next[0:0]$2789 end - attribute \src "libresoc.v:46411.3-46439.6" - process $proc$libresoc.v:46411$2741 + attribute \src "libresoc.v:47349.3-47377.6" + process $proc$libresoc.v:47349$2791 assign { } { } assign { } { } assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46412.5-46412.29" + attribute \src "libresoc.v:47350.5-47350.29" switch \initial - attribute \src "libresoc.v:46412.9-46412.17" + attribute \src "libresoc.v:47350.9-47350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81196,7 +82447,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81212,14 +82463,37 @@ module \core sync always update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] end - attribute \src "libresoc.v:46440.3-46448.6" - process $proc$libresoc.v:46440$2742 + attribute \src "libresoc.v:47378.3-47386.6" + process $proc$libresoc.v:47378$2792 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1479$next[0:0]$2793 $1\wr_pick_dly$1479$next[0:0]$2794 + attribute \src "libresoc.v:47379.5-47379.29" + switch \initial + attribute \src "libresoc.v:47379.9-47379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1479$next[0:0]$2794 1'0 + case + assign $1\wr_pick_dly$1479$next[0:0]$2794 \wr_pick$1476 + end + sync always + update \wr_pick_dly$1479$next $0\wr_pick_dly$1479$next[0:0]$2793 + end + attribute \src "libresoc.v:47387.3-47395.6" + process $proc$libresoc.v:47387$2795 assign { } { } assign { } { } - assign $0\wr_pick_dly$1211$next[0:0]$2743 $1\wr_pick_dly$1211$next[0:0]$2744 - attribute \src "libresoc.v:46441.5-46441.29" + assign $0\wr_pick_dly$1495$next[0:0]$2796 $1\wr_pick_dly$1495$next[0:0]$2797 + attribute \src "libresoc.v:47388.5-47388.29" switch \initial - attribute \src "libresoc.v:46441.9-46441.17" + attribute \src "libresoc.v:47388.9-47388.17" case 1'1 case end @@ -81228,31 +82502,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1211$next[0:0]$2744 1'0 + assign $1\wr_pick_dly$1495$next[0:0]$2797 1'0 case - assign $1\wr_pick_dly$1211$next[0:0]$2744 \wr_pick$1208 + assign $1\wr_pick_dly$1495$next[0:0]$2797 \wr_pick$1492 end sync always - update \wr_pick_dly$1211$next $0\wr_pick_dly$1211$next[0:0]$2743 + update \wr_pick_dly$1495$next $0\wr_pick_dly$1495$next[0:0]$2796 end - attribute \src "libresoc.v:46449.3-46477.6" - process $proc$libresoc.v:46449$2745 + attribute \src "libresoc.v:47396.3-47424.6" + process $proc$libresoc.v:47396$2798 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46450.5-46450.29" + attribute \src "libresoc.v:47397.5-47397.29" switch \initial - attribute \src "libresoc.v:46450.9-46450.17" + attribute \src "libresoc.v:47397.9-47397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81264,12 +82538,12 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i[3:0] \$221 + assign $3\fus_cu_rdmaskn_i[3:0] \$228 case assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 end @@ -81280,14 +82554,14 @@ module \core sync always update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] end - attribute \src "libresoc.v:46478.3-46486.6" - process $proc$libresoc.v:46478$2746 + attribute \src "libresoc.v:47425.3-47433.6" + process $proc$libresoc.v:47425$2799 assign { } { } assign { } { } - assign $0\wr_pick_dly$1239$next[0:0]$2747 $1\wr_pick_dly$1239$next[0:0]$2748 - attribute \src "libresoc.v:46479.5-46479.29" + assign $0\wr_pick_dly$1511$next[0:0]$2800 $1\wr_pick_dly$1511$next[0:0]$2801 + attribute \src "libresoc.v:47426.5-47426.29" switch \initial - attribute \src "libresoc.v:46479.9-46479.17" + attribute \src "libresoc.v:47426.9-47426.17" case 1'1 case end @@ -81296,31 +82570,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1239$next[0:0]$2748 1'0 + assign $1\wr_pick_dly$1511$next[0:0]$2801 1'0 case - assign $1\wr_pick_dly$1239$next[0:0]$2748 \wr_pick$1236 + assign $1\wr_pick_dly$1511$next[0:0]$2801 \wr_pick$1508 end sync always - update \wr_pick_dly$1239$next $0\wr_pick_dly$1239$next[0:0]$2747 + update \wr_pick_dly$1511$next $0\wr_pick_dly$1511$next[0:0]$2800 end - attribute \src "libresoc.v:46487.3-46515.6" - process $proc$libresoc.v:46487$2749 + attribute \src "libresoc.v:47434.3-47462.6" + process $proc$libresoc.v:47434$2802 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:46488.5-46488.29" + attribute \src "libresoc.v:47435.5-47435.29" switch \initial - attribute \src "libresoc.v:46488.9-46488.17" + attribute \src "libresoc.v:47435.9-47435.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81332,7 +82606,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81348,14 +82622,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] end - attribute \src "libresoc.v:46516.3-46524.6" - process $proc$libresoc.v:46516$2750 + attribute \src "libresoc.v:47463.3-47471.6" + process $proc$libresoc.v:47463$2803 assign { } { } assign { } { } - assign $0\wr_pick_dly$1259$next[0:0]$2751 $1\wr_pick_dly$1259$next[0:0]$2752 - attribute \src "libresoc.v:46517.5-46517.29" + assign $0\wr_pick_dly$1547$next[0:0]$2804 $1\wr_pick_dly$1547$next[0:0]$2805 + attribute \src "libresoc.v:47464.5-47464.29" switch \initial - attribute \src "libresoc.v:46517.9-46517.17" + attribute \src "libresoc.v:47464.9-47464.17" case 1'1 case end @@ -81364,21 +82638,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1259$next[0:0]$2752 1'0 + assign $1\wr_pick_dly$1547$next[0:0]$2805 1'0 case - assign $1\wr_pick_dly$1259$next[0:0]$2752 \wr_pick$1256 + assign $1\wr_pick_dly$1547$next[0:0]$2805 \wr_pick$1544 end sync always - update \wr_pick_dly$1259$next $0\wr_pick_dly$1259$next[0:0]$2751 + update \wr_pick_dly$1547$next $0\wr_pick_dly$1547$next[0:0]$2804 end - attribute \src "libresoc.v:46525.3-46533.6" - process $proc$libresoc.v:46525$2753 + attribute \src "libresoc.v:47472.3-47480.6" + process $proc$libresoc.v:47472$2806 assign { } { } assign { } { } - assign $0\wr_pick_dly$1279$next[0:0]$2754 $1\wr_pick_dly$1279$next[0:0]$2755 - attribute \src "libresoc.v:46526.5-46526.29" + assign $0\wr_pick_dly$1563$next[0:0]$2807 $1\wr_pick_dly$1563$next[0:0]$2808 + attribute \src "libresoc.v:47473.5-47473.29" switch \initial - attribute \src "libresoc.v:46526.9-46526.17" + attribute \src "libresoc.v:47473.9-47473.17" case 1'1 case end @@ -81387,66 +82661,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1279$next[0:0]$2755 1'0 + assign $1\wr_pick_dly$1563$next[0:0]$2808 1'0 case - assign $1\wr_pick_dly$1279$next[0:0]$2755 \wr_pick$1276 + assign $1\wr_pick_dly$1563$next[0:0]$2808 \wr_pick$1560 end sync always - update \wr_pick_dly$1279$next $0\wr_pick_dly$1279$next[0:0]$2754 + update \wr_pick_dly$1563$next $0\wr_pick_dly$1563$next[0:0]$2807 end - attribute \src "libresoc.v:46534.3-46562.6" - process $proc$libresoc.v:46534$2756 + attribute \src "libresoc.v:47481.3-47509.6" + process $proc$libresoc.v:47481$2809 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_cr0__fn_unit[11:0] $1\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46535.5-46535.29" + assign $0\fus_oper_i_alu_cr0__fn_unit[13:0] $1\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47482.5-47482.29" switch \initial - attribute \src "libresoc.v:46535.9-46535.17" + attribute \src "libresoc.v:47482.9-47482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] $2\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] $2\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] $3\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] $3\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] \dec_CR_CR__fn_unit + assign $3\fus_oper_i_alu_cr0__fn_unit[13:0] \dec_CR_CR__fn_unit case - assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + assign $3\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[11:0] + update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[13:0] end - attribute \src "libresoc.v:46563.3-46571.6" - process $proc$libresoc.v:46563$2757 + attribute \src "libresoc.v:47510.3-47518.6" + process $proc$libresoc.v:47510$2810 assign { } { } assign { } { } - assign $0\wr_pick_dly$1299$next[0:0]$2758 $1\wr_pick_dly$1299$next[0:0]$2759 - attribute \src "libresoc.v:46564.5-46564.29" + assign $0\wr_pick_dly$1579$next[0:0]$2811 $1\wr_pick_dly$1579$next[0:0]$2812 + attribute \src "libresoc.v:47511.5-47511.29" switch \initial - attribute \src "libresoc.v:46564.9-46564.17" + attribute \src "libresoc.v:47511.9-47511.17" case 1'1 case end @@ -81455,21 +82729,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1299$next[0:0]$2759 1'0 + assign $1\wr_pick_dly$1579$next[0:0]$2812 1'0 case - assign $1\wr_pick_dly$1299$next[0:0]$2759 \wr_pick$1296 + assign $1\wr_pick_dly$1579$next[0:0]$2812 \wr_pick$1576 end sync always - update \wr_pick_dly$1299$next $0\wr_pick_dly$1299$next[0:0]$2758 + update \wr_pick_dly$1579$next $0\wr_pick_dly$1579$next[0:0]$2811 end - attribute \src "libresoc.v:46572.3-46580.6" - process $proc$libresoc.v:46572$2760 + attribute \src "libresoc.v:47519.3-47527.6" + process $proc$libresoc.v:47519$2813 assign { } { } assign { } { } - assign $0\wr_pick_dly$1319$next[0:0]$2761 $1\wr_pick_dly$1319$next[0:0]$2762 - attribute \src "libresoc.v:46573.5-46573.29" + assign $0\wr_pick_dly$1595$next[0:0]$2814 $1\wr_pick_dly$1595$next[0:0]$2815 + attribute \src "libresoc.v:47520.5-47520.29" switch \initial - attribute \src "libresoc.v:46573.9-46573.17" + attribute \src "libresoc.v:47520.9-47520.17" case 1'1 case end @@ -81478,31 +82752,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1319$next[0:0]$2762 1'0 + assign $1\wr_pick_dly$1595$next[0:0]$2815 1'0 case - assign $1\wr_pick_dly$1319$next[0:0]$2762 \wr_pick$1316 + assign $1\wr_pick_dly$1595$next[0:0]$2815 \wr_pick$1592 end sync always - update \wr_pick_dly$1319$next $0\wr_pick_dly$1319$next[0:0]$2761 + update \wr_pick_dly$1595$next $0\wr_pick_dly$1595$next[0:0]$2814 end - attribute \src "libresoc.v:46581.3-46609.6" - process $proc$libresoc.v:46581$2763 + attribute \src "libresoc.v:47528.3-47556.6" + process $proc$libresoc.v:47528$2816 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46582.5-46582.29" + attribute \src "libresoc.v:47529.5-47529.29" switch \initial - attribute \src "libresoc.v:46582.9-46582.17" + attribute \src "libresoc.v:47529.9-47529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81514,7 +82788,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81530,14 +82804,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] end - attribute \src "libresoc.v:46610.3-46618.6" - process $proc$libresoc.v:46610$2764 + attribute \src "libresoc.v:47557.3-47565.6" + process $proc$libresoc.v:47557$2817 assign { } { } assign { } { } - assign $0\wr_pick_dly$1339$next[0:0]$2765 $1\wr_pick_dly$1339$next[0:0]$2766 - attribute \src "libresoc.v:46611.5-46611.29" + assign $0\wr_pick_dly$1637$next[0:0]$2818 $1\wr_pick_dly$1637$next[0:0]$2819 + attribute \src "libresoc.v:47558.5-47558.29" switch \initial - attribute \src "libresoc.v:46611.9-46611.17" + attribute \src "libresoc.v:47558.9-47558.17" case 1'1 case end @@ -81546,66 +82820,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1339$next[0:0]$2766 1'0 + assign $1\wr_pick_dly$1637$next[0:0]$2819 1'0 case - assign $1\wr_pick_dly$1339$next[0:0]$2766 \wr_pick$1336 + assign $1\wr_pick_dly$1637$next[0:0]$2819 \wr_pick$1634 end sync always - update \wr_pick_dly$1339$next $0\wr_pick_dly$1339$next[0:0]$2765 + update \wr_pick_dly$1637$next $0\wr_pick_dly$1637$next[0:0]$2818 end - attribute \src "libresoc.v:46619.3-46647.6" - process $proc$libresoc.v:46619$2767 + attribute \src "libresoc.v:47566.3-47594.6" + process $proc$libresoc.v:47566$2820 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$11[0:0]$2768 $1\fus_cu_issue_i$11[0:0]$2769 - attribute \src "libresoc.v:46620.5-46620.29" + assign $0\fus_cu_issue_i$13[0:0]$2821 $1\fus_cu_issue_i$13[0:0]$2822 + attribute \src "libresoc.v:47567.5-47567.29" switch \initial - attribute \src "libresoc.v:46620.9-46620.17" + attribute \src "libresoc.v:47567.9-47567.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$11[0:0]$2769 $2\fus_cu_issue_i$11[0:0]$2770 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_issue_i$13[0:0]$2822 $2\fus_cu_issue_i$13[0:0]$2823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$11[0:0]$2770 1'0 + assign $2\fus_cu_issue_i$13[0:0]$2823 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$11[0:0]$2770 1'0 + assign $2\fus_cu_issue_i$13[0:0]$2823 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$11[0:0]$2770 $3\fus_cu_issue_i$11[0:0]$2771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_issue_i$13[0:0]$2823 $3\fus_cu_issue_i$13[0:0]$2824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$11[0:0]$2771 \issue_i + assign $3\fus_cu_issue_i$13[0:0]$2824 \issue_i case - assign $3\fus_cu_issue_i$11[0:0]$2771 1'0 + assign $3\fus_cu_issue_i$13[0:0]$2824 1'0 end end case - assign $1\fus_cu_issue_i$11[0:0]$2769 1'0 + assign $1\fus_cu_issue_i$13[0:0]$2822 1'0 end sync always - update \fus_cu_issue_i$11 $0\fus_cu_issue_i$11[0:0]$2768 + update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2821 end - attribute \src "libresoc.v:46648.3-46656.6" - process $proc$libresoc.v:46648$2772 + attribute \src "libresoc.v:47595.3-47603.6" + process $proc$libresoc.v:47595$2825 assign { } { } assign { } { } - assign $0\wr_pick_dly$1386$next[0:0]$2773 $1\wr_pick_dly$1386$next[0:0]$2774 - attribute \src "libresoc.v:46649.5-46649.29" + assign $0\wr_pick_dly$1656$next[0:0]$2826 $1\wr_pick_dly$1656$next[0:0]$2827 + attribute \src "libresoc.v:47596.5-47596.29" switch \initial - attribute \src "libresoc.v:46649.9-46649.17" + attribute \src "libresoc.v:47596.9-47596.17" case 1'1 case end @@ -81614,66 +82888,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1386$next[0:0]$2774 1'0 + assign $1\wr_pick_dly$1656$next[0:0]$2827 1'0 case - assign $1\wr_pick_dly$1386$next[0:0]$2774 \wr_pick$1383 + assign $1\wr_pick_dly$1656$next[0:0]$2827 \wr_pick$1653 end sync always - update \wr_pick_dly$1386$next $0\wr_pick_dly$1386$next[0:0]$2773 + update \wr_pick_dly$1656$next $0\wr_pick_dly$1656$next[0:0]$2826 end - attribute \src "libresoc.v:46657.3-46685.6" - process $proc$libresoc.v:46657$2775 + attribute \src "libresoc.v:47604.3-47632.6" + process $proc$libresoc.v:47604$2828 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$13[5:0]$2776 $1\fus_cu_rdmaskn_i$13[5:0]$2777 - attribute \src "libresoc.v:46658.5-46658.29" + assign $0\fus_cu_rdmaskn_i$15[5:0]$2829 $1\fus_cu_rdmaskn_i$15[5:0]$2830 + attribute \src "libresoc.v:47605.5-47605.29" switch \initial - attribute \src "libresoc.v:46658.9-46658.17" + attribute \src "libresoc.v:47605.9-47605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$13[5:0]$2777 $2\fus_cu_rdmaskn_i$13[5:0]$2778 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 $2\fus_cu_rdmaskn_i$15[5:0]$2831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$13[5:0]$2778 6'000000 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$13[5:0]$2778 6'000000 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$13[5:0]$2778 $3\fus_cu_rdmaskn_i$13[5:0]$2779 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 $3\fus_cu_rdmaskn_i$15[5:0]$2832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$13[5:0]$2779 \$243 + assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 \$250 case - assign $3\fus_cu_rdmaskn_i$13[5:0]$2779 6'000000 + assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 6'000000 end end case - assign $1\fus_cu_rdmaskn_i$13[5:0]$2777 6'000000 + assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 6'000000 end sync always - update \fus_cu_rdmaskn_i$13 $0\fus_cu_rdmaskn_i$13[5:0]$2776 + update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2829 end - attribute \src "libresoc.v:46686.3-46694.6" - process $proc$libresoc.v:46686$2780 + attribute \src "libresoc.v:47633.3-47641.6" + process $proc$libresoc.v:47633$2833 assign { } { } assign { } { } - assign $0\wr_pick_dly$1402$next[0:0]$2781 $1\wr_pick_dly$1402$next[0:0]$2782 - attribute \src "libresoc.v:46687.5-46687.29" + assign $0\wr_pick_dly$1672$next[0:0]$2834 $1\wr_pick_dly$1672$next[0:0]$2835 + attribute \src "libresoc.v:47634.5-47634.29" switch \initial - attribute \src "libresoc.v:46687.9-46687.17" + attribute \src "libresoc.v:47634.9-47634.17" case 1'1 case end @@ -81682,21 +82956,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1402$next[0:0]$2782 1'0 + assign $1\wr_pick_dly$1672$next[0:0]$2835 1'0 case - assign $1\wr_pick_dly$1402$next[0:0]$2782 \wr_pick$1399 + assign $1\wr_pick_dly$1672$next[0:0]$2835 \wr_pick$1669 end sync always - update \wr_pick_dly$1402$next $0\wr_pick_dly$1402$next[0:0]$2781 + update \wr_pick_dly$1672$next $0\wr_pick_dly$1672$next[0:0]$2834 end - attribute \src "libresoc.v:46695.3-46703.6" - process $proc$libresoc.v:46695$2783 + attribute \src "libresoc.v:47642.3-47650.6" + process $proc$libresoc.v:47642$2836 assign { } { } assign { } { } - assign $0\wr_pick_dly$1418$next[0:0]$2784 $1\wr_pick_dly$1418$next[0:0]$2785 - attribute \src "libresoc.v:46696.5-46696.29" + assign $0\wr_pick_dly$1688$next[0:0]$2837 $1\wr_pick_dly$1688$next[0:0]$2838 + attribute \src "libresoc.v:47643.5-47643.29" switch \initial - attribute \src "libresoc.v:46696.9-46696.17" + attribute \src "libresoc.v:47643.9-47643.17" case 1'1 case end @@ -81705,31 +82979,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1418$next[0:0]$2785 1'0 + assign $1\wr_pick_dly$1688$next[0:0]$2838 1'0 case - assign $1\wr_pick_dly$1418$next[0:0]$2785 \wr_pick$1415 + assign $1\wr_pick_dly$1688$next[0:0]$2838 \wr_pick$1685 end sync always - update \wr_pick_dly$1418$next $0\wr_pick_dly$1418$next[0:0]$2784 + update \wr_pick_dly$1688$next $0\wr_pick_dly$1688$next[0:0]$2837 end - attribute \src "libresoc.v:46704.3-46732.6" - process $proc$libresoc.v:46704$2786 + attribute \src "libresoc.v:47651.3-47679.6" + process $proc$libresoc.v:47651$2839 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46705.5-46705.29" + attribute \src "libresoc.v:47652.5-47652.29" switch \initial - attribute \src "libresoc.v:46705.9-46705.17" + attribute \src "libresoc.v:47652.9-47652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81741,7 +83015,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81757,14 +83031,14 @@ module \core sync always update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] end - attribute \src "libresoc.v:46733.3-46741.6" - process $proc$libresoc.v:46733$2787 + attribute \src "libresoc.v:47680.3-47688.6" + process $proc$libresoc.v:47680$2840 assign { } { } assign { } { } - assign $0\wr_pick_dly$1452$next[0:0]$2788 $1\wr_pick_dly$1452$next[0:0]$2789 - attribute \src "libresoc.v:46734.5-46734.29" + assign $0\wr_pick_dly$1704$next[0:0]$2841 $1\wr_pick_dly$1704$next[0:0]$2842 + attribute \src "libresoc.v:47681.5-47681.29" switch \initial - attribute \src "libresoc.v:46734.9-46734.17" + attribute \src "libresoc.v:47681.9-47681.17" case 1'1 case end @@ -81773,31 +83047,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1452$next[0:0]$2789 1'0 + assign $1\wr_pick_dly$1704$next[0:0]$2842 1'0 case - assign $1\wr_pick_dly$1452$next[0:0]$2789 \wr_pick$1449 + assign $1\wr_pick_dly$1704$next[0:0]$2842 \wr_pick$1701 end sync always - update \wr_pick_dly$1452$next $0\wr_pick_dly$1452$next[0:0]$2788 + update \wr_pick_dly$1704$next $0\wr_pick_dly$1704$next[0:0]$2841 end - attribute \src "libresoc.v:46742.3-46770.6" - process $proc$libresoc.v:46742$2790 + attribute \src "libresoc.v:47689.3-47717.6" + process $proc$libresoc.v:47689$2843 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46743.5-46743.29" + attribute \src "libresoc.v:47690.5-47690.29" switch \initial - attribute \src "libresoc.v:46743.9-46743.17" + attribute \src "libresoc.v:47690.9-47690.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81809,7 +83083,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81825,14 +83099,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] end - attribute \src "libresoc.v:46771.3-46779.6" - process $proc$libresoc.v:46771$2791 + attribute \src "libresoc.v:47718.3-47726.6" + process $proc$libresoc.v:47718$2844 assign { } { } assign { } { } - assign $0\wr_pick_dly$1468$next[0:0]$2792 $1\wr_pick_dly$1468$next[0:0]$2793 - attribute \src "libresoc.v:46772.5-46772.29" + assign $0\wr_pick_dly$1748$next[0:0]$2845 $1\wr_pick_dly$1748$next[0:0]$2846 + attribute \src "libresoc.v:47719.5-47719.29" switch \initial - attribute \src "libresoc.v:46772.9-46772.17" + attribute \src "libresoc.v:47719.9-47719.17" case 1'1 case end @@ -81841,21 +83115,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1468$next[0:0]$2793 1'0 + assign $1\wr_pick_dly$1748$next[0:0]$2846 1'0 case - assign $1\wr_pick_dly$1468$next[0:0]$2793 \wr_pick$1465 + assign $1\wr_pick_dly$1748$next[0:0]$2846 \wr_pick$1745 end sync always - update \wr_pick_dly$1468$next $0\wr_pick_dly$1468$next[0:0]$2792 + update \wr_pick_dly$1748$next $0\wr_pick_dly$1748$next[0:0]$2845 end - attribute \src "libresoc.v:46780.3-46788.6" - process $proc$libresoc.v:46780$2794 + attribute \src "libresoc.v:47727.3-47735.6" + process $proc$libresoc.v:47727$2847 assign { } { } assign { } { } - assign $0\wr_pick_dly$1484$next[0:0]$2795 $1\wr_pick_dly$1484$next[0:0]$2796 - attribute \src "libresoc.v:46781.5-46781.29" + assign $0\wr_pick_dly$1764$next[0:0]$2848 $1\wr_pick_dly$1764$next[0:0]$2849 + attribute \src "libresoc.v:47728.5-47728.29" switch \initial - attribute \src "libresoc.v:46781.9-46781.17" + attribute \src "libresoc.v:47728.9-47728.17" case 1'1 case end @@ -81864,66 +83138,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1484$next[0:0]$2796 1'0 + assign $1\wr_pick_dly$1764$next[0:0]$2849 1'0 case - assign $1\wr_pick_dly$1484$next[0:0]$2796 \wr_pick$1481 + assign $1\wr_pick_dly$1764$next[0:0]$2849 \wr_pick$1761 end sync always - update \wr_pick_dly$1484$next $0\wr_pick_dly$1484$next[0:0]$2795 + update \wr_pick_dly$1764$next $0\wr_pick_dly$1764$next[0:0]$2848 end - attribute \src "libresoc.v:46789.3-46817.6" - process $proc$libresoc.v:46789$2797 + attribute \src "libresoc.v:47736.3-47764.6" + process $proc$libresoc.v:47736$2850 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_branch0__fn_unit[11:0] $1\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46790.5-46790.29" + assign $0\fus_oper_i_alu_branch0__fn_unit[13:0] $1\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47737.5-47737.29" switch \initial - attribute \src "libresoc.v:46790.9-46790.17" + attribute \src "libresoc.v:47737.9-47737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] $2\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] $2\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] $3\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] $3\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] \dec_BRANCH_BRANCH__fn_unit + assign $3\fus_oper_i_alu_branch0__fn_unit[13:0] \dec_BRANCH_BRANCH__fn_unit case - assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + assign $3\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[11:0] + update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[13:0] end - attribute \src "libresoc.v:46818.3-46826.6" - process $proc$libresoc.v:46818$2798 + attribute \src "libresoc.v:47765.3-47773.6" + process $proc$libresoc.v:47765$2851 assign { } { } assign { } { } - assign $0\wr_pick_dly$1500$next[0:0]$2799 $1\wr_pick_dly$1500$next[0:0]$2800 - attribute \src "libresoc.v:46819.5-46819.29" + assign $0\wr_pick_dly$1788$next[0:0]$2852 $1\wr_pick_dly$1788$next[0:0]$2853 + attribute \src "libresoc.v:47766.5-47766.29" switch \initial - attribute \src "libresoc.v:46819.9-46819.17" + attribute \src "libresoc.v:47766.9-47766.17" case 1'1 case end @@ -81932,31 +83206,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1500$next[0:0]$2800 1'0 + assign $1\wr_pick_dly$1788$next[0:0]$2853 1'0 case - assign $1\wr_pick_dly$1500$next[0:0]$2800 \wr_pick$1497 + assign $1\wr_pick_dly$1788$next[0:0]$2853 \wr_pick$1785 end sync always - update \wr_pick_dly$1500$next $0\wr_pick_dly$1500$next[0:0]$2799 + update \wr_pick_dly$1788$next $0\wr_pick_dly$1788$next[0:0]$2852 end - attribute \src "libresoc.v:46827.3-46855.6" - process $proc$libresoc.v:46827$2801 + attribute \src "libresoc.v:47774.3-47802.6" + process $proc$libresoc.v:47774$2854 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46828.5-46828.29" + attribute \src "libresoc.v:47775.5-47775.29" switch \initial - attribute \src "libresoc.v:46828.9-46828.17" + attribute \src "libresoc.v:47775.9-47775.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81968,7 +83242,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81984,14 +83258,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] end - attribute \src "libresoc.v:46856.3-46864.6" - process $proc$libresoc.v:46856$2802 + attribute \src "libresoc.v:47803.3-47811.6" + process $proc$libresoc.v:47803$2855 assign { } { } assign { } { } - assign $0\wr_pick_dly$1536$next[0:0]$2803 $1\wr_pick_dly$1536$next[0:0]$2804 - attribute \src "libresoc.v:46857.5-46857.29" + assign $0\wr_pick_dly$1808$next[0:0]$2856 $1\wr_pick_dly$1808$next[0:0]$2857 + attribute \src "libresoc.v:47804.5-47804.29" switch \initial - attribute \src "libresoc.v:46857.9-46857.17" + attribute \src "libresoc.v:47804.9-47804.17" case 1'1 case end @@ -82000,51 +83274,28 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1536$next[0:0]$2804 1'0 + assign $1\wr_pick_dly$1808$next[0:0]$2857 1'0 case - assign $1\wr_pick_dly$1536$next[0:0]$2804 \wr_pick$1533 + assign $1\wr_pick_dly$1808$next[0:0]$2857 \wr_pick$1805 end sync always - update \wr_pick_dly$1536$next $0\wr_pick_dly$1536$next[0:0]$2803 + update \wr_pick_dly$1808$next $0\wr_pick_dly$1808$next[0:0]$2856 end - attribute \src "libresoc.v:46865.3-46873.6" - process $proc$libresoc.v:46865$2805 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1552$next[0:0]$2806 $1\wr_pick_dly$1552$next[0:0]$2807 - attribute \src "libresoc.v:46866.5-46866.29" - switch \initial - attribute \src "libresoc.v:46866.9-46866.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1552$next[0:0]$2807 1'0 - case - assign $1\wr_pick_dly$1552$next[0:0]$2807 \wr_pick$1549 - end - sync always - update \wr_pick_dly$1552$next $0\wr_pick_dly$1552$next[0:0]$2806 - end - attribute \src "libresoc.v:46874.3-46903.6" - process $proc$libresoc.v:46874$2808 + attribute \src "libresoc.v:47812.3-47841.6" + process $proc$libresoc.v:47812$2858 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46875.5-46875.29" + attribute \src "libresoc.v:47813.5-47813.29" switch \initial - attribute \src "libresoc.v:46875.9-46875.17" + attribute \src "libresoc.v:47813.9-47813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82052,7 +83303,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82068,7 +83319,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82088,93 +83339,24 @@ module \core update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] end - attribute \src "libresoc.v:46904.3-46912.6" - process $proc$libresoc.v:46904$2809 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1568$next[0:0]$2810 $1\wr_pick_dly$1568$next[0:0]$2811 - attribute \src "libresoc.v:46905.5-46905.29" - switch \initial - attribute \src "libresoc.v:46905.9-46905.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1568$next[0:0]$2811 1'0 - case - assign $1\wr_pick_dly$1568$next[0:0]$2811 \wr_pick$1565 - end - sync always - update \wr_pick_dly$1568$next $0\wr_pick_dly$1568$next[0:0]$2810 - end - attribute \src "libresoc.v:46913.3-46921.6" - process $proc$libresoc.v:46913$2812 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1584$next[0:0]$2813 $1\wr_pick_dly$1584$next[0:0]$2814 - attribute \src "libresoc.v:46914.5-46914.29" - switch \initial - attribute \src "libresoc.v:46914.9-46914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1584$next[0:0]$2814 1'0 - case - assign $1\wr_pick_dly$1584$next[0:0]$2814 \wr_pick$1581 - end - sync always - update \wr_pick_dly$1584$next $0\wr_pick_dly$1584$next[0:0]$2813 - end - attribute \src "libresoc.v:46922.3-46930.6" - process $proc$libresoc.v:46922$2815 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1626$next[0:0]$2816 $1\wr_pick_dly$1626$next[0:0]$2817 - attribute \src "libresoc.v:46923.5-46923.29" - switch \initial - attribute \src "libresoc.v:46923.9-46923.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1626$next[0:0]$2817 1'0 - case - assign $1\wr_pick_dly$1626$next[0:0]$2817 \wr_pick$1623 - end - sync always - update \wr_pick_dly$1626$next $0\wr_pick_dly$1626$next[0:0]$2816 - end - attribute \src "libresoc.v:46931.3-46959.6" - process $proc$libresoc.v:46931$2818 + attribute \src "libresoc.v:47842.3-47870.6" + process $proc$libresoc.v:47842$2859 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46932.5-46932.29" + attribute \src "libresoc.v:47843.5-47843.29" switch \initial - attribute \src "libresoc.v:46932.9-46932.17" + attribute \src "libresoc.v:47843.9-47843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82186,7 +83368,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82202,47 +83384,24 @@ module \core sync always update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] end - attribute \src "libresoc.v:46960.3-46968.6" - process $proc$libresoc.v:46960$2819 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1645$next[0:0]$2820 $1\wr_pick_dly$1645$next[0:0]$2821 - attribute \src "libresoc.v:46961.5-46961.29" - switch \initial - attribute \src "libresoc.v:46961.9-46961.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1645$next[0:0]$2821 1'0 - case - assign $1\wr_pick_dly$1645$next[0:0]$2821 \wr_pick$1642 - end - sync always - update \wr_pick_dly$1645$next $0\wr_pick_dly$1645$next[0:0]$2820 - end - attribute \src "libresoc.v:46969.3-46997.6" - process $proc$libresoc.v:46969$2822 + attribute \src "libresoc.v:47871.3-47899.6" + process $proc$libresoc.v:47871$2860 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46970.5-46970.29" + attribute \src "libresoc.v:47872.5-47872.29" switch \initial - attribute \src "libresoc.v:46970.9-46970.17" + attribute \src "libresoc.v:47872.9-47872.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82254,7 +83413,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82270,206 +83429,114 @@ module \core sync always update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] end - attribute \src "libresoc.v:46998.3-47006.6" - process $proc$libresoc.v:46998$2823 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1661$next[0:0]$2824 $1\wr_pick_dly$1661$next[0:0]$2825 - attribute \src "libresoc.v:46999.5-46999.29" - switch \initial - attribute \src "libresoc.v:46999.9-46999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1661$next[0:0]$2825 1'0 - case - assign $1\wr_pick_dly$1661$next[0:0]$2825 \wr_pick$1658 - end - sync always - update \wr_pick_dly$1661$next $0\wr_pick_dly$1661$next[0:0]$2824 - end - attribute \src "libresoc.v:47007.3-47015.6" - process $proc$libresoc.v:47007$2826 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1677$next[0:0]$2827 $1\wr_pick_dly$1677$next[0:0]$2828 - attribute \src "libresoc.v:47008.5-47008.29" - switch \initial - attribute \src "libresoc.v:47008.9-47008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1677$next[0:0]$2828 1'0 - case - assign $1\wr_pick_dly$1677$next[0:0]$2828 \wr_pick$1674 - end - sync always - update \wr_pick_dly$1677$next $0\wr_pick_dly$1677$next[0:0]$2827 - end - attribute \src "libresoc.v:47016.3-47044.6" - process $proc$libresoc.v:47016$2829 + attribute \src "libresoc.v:47900.3-47928.6" + process $proc$libresoc.v:47900$2861 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$14[0:0]$2830 $1\fus_cu_issue_i$14[0:0]$2831 - attribute \src "libresoc.v:47017.5-47017.29" + assign $0\fus_cu_issue_i$16[0:0]$2862 $1\fus_cu_issue_i$16[0:0]$2863 + attribute \src "libresoc.v:47901.5-47901.29" switch \initial - attribute \src "libresoc.v:47017.9-47017.17" + attribute \src "libresoc.v:47901.9-47901.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$14[0:0]$2831 $2\fus_cu_issue_i$14[0:0]$2832 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_issue_i$16[0:0]$2863 $2\fus_cu_issue_i$16[0:0]$2864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$14[0:0]$2832 1'0 + assign $2\fus_cu_issue_i$16[0:0]$2864 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$14[0:0]$2832 1'0 + assign $2\fus_cu_issue_i$16[0:0]$2864 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$14[0:0]$2832 $3\fus_cu_issue_i$14[0:0]$2833 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_issue_i$16[0:0]$2864 $3\fus_cu_issue_i$16[0:0]$2865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$14[0:0]$2833 \issue_i + assign $3\fus_cu_issue_i$16[0:0]$2865 \issue_i case - assign $3\fus_cu_issue_i$14[0:0]$2833 1'0 + assign $3\fus_cu_issue_i$16[0:0]$2865 1'0 end end case - assign $1\fus_cu_issue_i$14[0:0]$2831 1'0 + assign $1\fus_cu_issue_i$16[0:0]$2863 1'0 end sync always - update \fus_cu_issue_i$14 $0\fus_cu_issue_i$14[0:0]$2830 + update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2862 end - attribute \src "libresoc.v:47045.3-47053.6" - process $proc$libresoc.v:47045$2834 + attribute \src "libresoc.v:47929.3-47957.6" + process $proc$libresoc.v:47929$2866 assign { } { } assign { } { } - assign $0\wr_pick_dly$1693$next[0:0]$2835 $1\wr_pick_dly$1693$next[0:0]$2836 - attribute \src "libresoc.v:47046.5-47046.29" + assign $0\fus_cu_rdmaskn_i$18[2:0]$2867 $1\fus_cu_rdmaskn_i$18[2:0]$2868 + attribute \src "libresoc.v:47930.5-47930.29" switch \initial - attribute \src "libresoc.v:47046.9-47046.17" + attribute \src "libresoc.v:47930.9-47930.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1693$next[0:0]$2836 1'0 - case - assign $1\wr_pick_dly$1693$next[0:0]$2836 \wr_pick$1690 - end - sync always - update \wr_pick_dly$1693$next $0\wr_pick_dly$1693$next[0:0]$2835 - end - attribute \src "libresoc.v:47054.3-47082.6" - process $proc$libresoc.v:47054$2837 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$16[2:0]$2838 $1\fus_cu_rdmaskn_i$16[2:0]$2839 - attribute \src "libresoc.v:47055.5-47055.29" - switch \initial - attribute \src "libresoc.v:47055.9-47055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$16[2:0]$2839 $2\fus_cu_rdmaskn_i$16[2:0]$2840 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 $2\fus_cu_rdmaskn_i$18[2:0]$2869 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$16[2:0]$2840 3'000 + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$16[2:0]$2840 3'000 + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$16[2:0]$2840 $3\fus_cu_rdmaskn_i$16[2:0]$2841 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 $3\fus_cu_rdmaskn_i$18[2:0]$2870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$16[2:0]$2841 \$245 + assign $3\fus_cu_rdmaskn_i$18[2:0]$2870 \$252 case - assign $3\fus_cu_rdmaskn_i$16[2:0]$2841 3'000 + assign $3\fus_cu_rdmaskn_i$18[2:0]$2870 3'000 end end case - assign $1\fus_cu_rdmaskn_i$16[2:0]$2839 3'000 - end - sync always - update \fus_cu_rdmaskn_i$16 $0\fus_cu_rdmaskn_i$16[2:0]$2838 - end - attribute \src "libresoc.v:47083.3-47091.6" - process $proc$libresoc.v:47083$2842 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1737$next[0:0]$2843 $1\wr_pick_dly$1737$next[0:0]$2844 - attribute \src "libresoc.v:47084.5-47084.29" - switch \initial - attribute \src "libresoc.v:47084.9-47084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1737$next[0:0]$2844 1'0 - case - assign $1\wr_pick_dly$1737$next[0:0]$2844 \wr_pick$1734 + assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 3'000 end sync always - update \wr_pick_dly$1737$next $0\wr_pick_dly$1737$next[0:0]$2843 + update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2867 end - attribute \src "libresoc.v:47092.3-47120.6" - process $proc$libresoc.v:47092$2845 + attribute \src "libresoc.v:47958.3-47986.6" + process $proc$libresoc.v:47958$2871 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47093.5-47093.29" + attribute \src "libresoc.v:47959.5-47959.29" switch \initial - attribute \src "libresoc.v:47093.9-47093.17" + attribute \src "libresoc.v:47959.9-47959.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82481,7 +83548,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82497,138 +83564,69 @@ module \core sync always update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] end - attribute \src "libresoc.v:47121.3-47129.6" - process $proc$libresoc.v:47121$2846 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1753$next[0:0]$2847 $1\wr_pick_dly$1753$next[0:0]$2848 - attribute \src "libresoc.v:47122.5-47122.29" - switch \initial - attribute \src "libresoc.v:47122.9-47122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1753$next[0:0]$2848 1'0 - case - assign $1\wr_pick_dly$1753$next[0:0]$2848 \wr_pick$1750 - end - sync always - update \wr_pick_dly$1753$next $0\wr_pick_dly$1753$next[0:0]$2847 - end - attribute \src "libresoc.v:47130.3-47138.6" - process $proc$libresoc.v:47130$2849 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1777$next[0:0]$2850 $1\wr_pick_dly$1777$next[0:0]$2851 - attribute \src "libresoc.v:47131.5-47131.29" - switch \initial - attribute \src "libresoc.v:47131.9-47131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1777$next[0:0]$2851 1'0 - case - assign $1\wr_pick_dly$1777$next[0:0]$2851 \wr_pick$1774 - end - sync always - update \wr_pick_dly$1777$next $0\wr_pick_dly$1777$next[0:0]$2850 - end - attribute \src "libresoc.v:47139.3-47167.6" - process $proc$libresoc.v:47139$2852 + attribute \src "libresoc.v:47987.3-48015.6" + process $proc$libresoc.v:47987$2872 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_trap0__fn_unit[11:0] $1\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:47140.5-47140.29" + assign $0\fus_oper_i_alu_trap0__fn_unit[13:0] $1\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:47988.5-47988.29" switch \initial - attribute \src "libresoc.v:47140.9-47140.17" + attribute \src "libresoc.v:47988.9-47988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] $2\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] $2\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] $3\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] $3\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] \core_core_fn_unit + assign $3\fus_oper_i_alu_trap0__fn_unit[13:0] \core_core_fn_unit case - assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + assign $3\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[11:0] + update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[13:0] end - attribute \src "libresoc.v:47168.3-47176.6" - process $proc$libresoc.v:47168$2853 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1797$next[0:0]$2854 $1\wr_pick_dly$1797$next[0:0]$2855 - attribute \src "libresoc.v:47169.5-47169.29" - switch \initial - attribute \src "libresoc.v:47169.9-47169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1797$next[0:0]$2855 1'0 - case - assign $1\wr_pick_dly$1797$next[0:0]$2855 \wr_pick$1794 - end - sync always - update \wr_pick_dly$1797$next $0\wr_pick_dly$1797$next[0:0]$2854 - end - attribute \src "libresoc.v:47177.3-47205.6" - process $proc$libresoc.v:47177$2856 + attribute \src "libresoc.v:48016.3-48044.6" + process $proc$libresoc.v:48016$2873 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47178.5-47178.29" + attribute \src "libresoc.v:48017.5-48017.29" switch \initial - attribute \src "libresoc.v:47178.9-47178.17" + attribute \src "libresoc.v:48017.9-48017.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82640,7 +83638,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82656,24 +83654,24 @@ module \core sync always update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] end - attribute \src "libresoc.v:47206.3-47234.6" - process $proc$libresoc.v:47206$2857 + attribute \src "libresoc.v:48045.3-48073.6" + process $proc$libresoc.v:48045$2874 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47207.5-47207.29" + attribute \src "libresoc.v:48046.5-48046.29" switch \initial - attribute \src "libresoc.v:47207.9-47207.17" + attribute \src "libresoc.v:48046.9-48046.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82685,7 +83683,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82701,24 +83699,24 @@ module \core sync always update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] end - attribute \src "libresoc.v:47235.3-47263.6" - process $proc$libresoc.v:47235$2858 + attribute \src "libresoc.v:48074.3-48102.6" + process $proc$libresoc.v:48074$2875 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47236.5-47236.29" + attribute \src "libresoc.v:48075.5-48075.29" switch \initial - attribute \src "libresoc.v:47236.9-47236.17" + attribute \src "libresoc.v:48075.9-48075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82730,7 +83728,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82746,24 +83744,24 @@ module \core sync always update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] end - attribute \src "libresoc.v:47264.3-47292.6" - process $proc$libresoc.v:47264$2859 + attribute \src "libresoc.v:48103.3-48131.6" + process $proc$libresoc.v:48103$2876 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47265.5-47265.29" + attribute \src "libresoc.v:48104.5-48104.29" switch \initial - attribute \src "libresoc.v:47265.9-47265.17" + attribute \src "libresoc.v:48104.9-48104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82775,7 +83773,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82791,24 +83789,24 @@ module \core sync always update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] end - attribute \src "libresoc.v:47293.3-47321.6" - process $proc$libresoc.v:47293$2860 + attribute \src "libresoc.v:48132.3-48160.6" + process $proc$libresoc.v:48132$2877 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:47294.5-47294.29" + attribute \src "libresoc.v:48133.5-48133.29" switch \initial - attribute \src "libresoc.v:47294.9-47294.17" + attribute \src "libresoc.v:48133.9-48133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82820,7 +83818,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82836,24 +83834,24 @@ module \core sync always update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] end - attribute \src "libresoc.v:47322.3-47350.6" - process $proc$libresoc.v:47322$2861 + attribute \src "libresoc.v:48161.3-48189.6" + process $proc$libresoc.v:48161$2878 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47323.5-47323.29" + attribute \src "libresoc.v:48162.5-48162.29" switch \initial - attribute \src "libresoc.v:47323.9-47323.17" + attribute \src "libresoc.v:48162.9-48162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82865,7 +83863,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82881,24 +83879,24 @@ module \core sync always update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] end - attribute \src "libresoc.v:47351.3-47379.6" - process $proc$libresoc.v:47351$2862 + attribute \src "libresoc.v:48190.3-48218.6" + process $proc$libresoc.v:48190$2879 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47352.5-47352.29" + attribute \src "libresoc.v:48191.5-48191.29" switch \initial - attribute \src "libresoc.v:47352.9-47352.17" + attribute \src "libresoc.v:48191.9-48191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82910,7 +83908,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82926,114 +83924,114 @@ module \core sync always update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] end - attribute \src "libresoc.v:47380.3-47408.6" - process $proc$libresoc.v:47380$2863 + attribute \src "libresoc.v:48219.3-48247.6" + process $proc$libresoc.v:48219$2880 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$17[0:0]$2864 $1\fus_cu_issue_i$17[0:0]$2865 - attribute \src "libresoc.v:47381.5-47381.29" + assign $0\fus_cu_issue_i$19[0:0]$2881 $1\fus_cu_issue_i$19[0:0]$2882 + attribute \src "libresoc.v:48220.5-48220.29" switch \initial - attribute \src "libresoc.v:47381.9-47381.17" + attribute \src "libresoc.v:48220.9-48220.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$17[0:0]$2865 $2\fus_cu_issue_i$17[0:0]$2866 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_issue_i$19[0:0]$2882 $2\fus_cu_issue_i$19[0:0]$2883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$17[0:0]$2866 1'0 + assign $2\fus_cu_issue_i$19[0:0]$2883 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$17[0:0]$2866 1'0 + assign $2\fus_cu_issue_i$19[0:0]$2883 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$17[0:0]$2866 $3\fus_cu_issue_i$17[0:0]$2867 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_issue_i$19[0:0]$2883 $3\fus_cu_issue_i$19[0:0]$2884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$17[0:0]$2867 \issue_i + assign $3\fus_cu_issue_i$19[0:0]$2884 \issue_i case - assign $3\fus_cu_issue_i$17[0:0]$2867 1'0 + assign $3\fus_cu_issue_i$19[0:0]$2884 1'0 end end case - assign $1\fus_cu_issue_i$17[0:0]$2865 1'0 + assign $1\fus_cu_issue_i$19[0:0]$2882 1'0 end sync always - update \fus_cu_issue_i$17 $0\fus_cu_issue_i$17[0:0]$2864 + update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2881 end - attribute \src "libresoc.v:47409.3-47437.6" - process $proc$libresoc.v:47409$2868 + attribute \src "libresoc.v:48248.3-48276.6" + process $proc$libresoc.v:48248$2885 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$19[3:0]$2869 $1\fus_cu_rdmaskn_i$19[3:0]$2870 - attribute \src "libresoc.v:47410.5-47410.29" + assign $0\fus_cu_rdmaskn_i$21[3:0]$2886 $1\fus_cu_rdmaskn_i$21[3:0]$2887 + attribute \src "libresoc.v:48249.5-48249.29" switch \initial - attribute \src "libresoc.v:47410.9-47410.17" + attribute \src "libresoc.v:48249.9-48249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$19[3:0]$2870 $2\fus_cu_rdmaskn_i$19[3:0]$2871 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 $2\fus_cu_rdmaskn_i$21[3:0]$2888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$19[3:0]$2871 4'0000 + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$19[3:0]$2871 4'0000 + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$19[3:0]$2871 $3\fus_cu_rdmaskn_i$19[3:0]$2872 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 $3\fus_cu_rdmaskn_i$21[3:0]$2889 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$19[3:0]$2872 \$247 + assign $3\fus_cu_rdmaskn_i$21[3:0]$2889 \$254 case - assign $3\fus_cu_rdmaskn_i$19[3:0]$2872 4'0000 + assign $3\fus_cu_rdmaskn_i$21[3:0]$2889 4'0000 end end case - assign $1\fus_cu_rdmaskn_i$19[3:0]$2870 4'0000 + assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 4'0000 end sync always - update \fus_cu_rdmaskn_i$19 $0\fus_cu_rdmaskn_i$19[3:0]$2869 + update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2886 end - attribute \src "libresoc.v:47438.3-47466.6" - process $proc$libresoc.v:47438$2873 + attribute \src "libresoc.v:48277.3-48305.6" + process $proc$libresoc.v:48277$2890 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47439.5-47439.29" + attribute \src "libresoc.v:48278.5-48278.29" switch \initial - attribute \src "libresoc.v:47439.9-47439.17" + attribute \src "libresoc.v:48278.9-48278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83045,7 +84043,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83061,66 +84059,66 @@ module \core sync always update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] end - attribute \src "libresoc.v:47467.3-47495.6" - process $proc$libresoc.v:47467$2874 + attribute \src "libresoc.v:48306.3-48334.6" + process $proc$libresoc.v:48306$2891 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_logical0__fn_unit[11:0] $1\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47468.5-47468.29" + assign $0\fus_oper_i_alu_logical0__fn_unit[13:0] $1\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48307.5-48307.29" switch \initial - attribute \src "libresoc.v:47468.9-47468.17" + attribute \src "libresoc.v:48307.9-48307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] $2\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] $2\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] $3\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] $3\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] \dec_LOGICAL_LOGICAL__fn_unit + assign $3\fus_oper_i_alu_logical0__fn_unit[13:0] \dec_LOGICAL_LOGICAL__fn_unit case - assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + assign $3\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[11:0] + update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[13:0] end - attribute \src "libresoc.v:47496.3-47525.6" - process $proc$libresoc.v:47496$2875 + attribute \src "libresoc.v:48335.3-48364.6" + process $proc$libresoc.v:48335$2892 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47497.5-47497.29" + attribute \src "libresoc.v:48336.5-48336.29" switch \initial - attribute \src "libresoc.v:47497.9-47497.17" + attribute \src "libresoc.v:48336.9-48336.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83128,7 +84126,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83144,7 +84142,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83164,21 +84162,21 @@ module \core update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] end - attribute \src "libresoc.v:47526.3-47555.6" - process $proc$libresoc.v:47526$2876 + attribute \src "libresoc.v:48365.3-48394.6" + process $proc$libresoc.v:48365$2893 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47527.5-47527.29" + attribute \src "libresoc.v:48366.5-48366.29" switch \initial - attribute \src "libresoc.v:47527.9-47527.17" + attribute \src "libresoc.v:48366.9-48366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83186,7 +84184,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83202,7 +84200,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83222,21 +84220,21 @@ module \core update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] end - attribute \src "libresoc.v:47556.3-47585.6" - process $proc$libresoc.v:47556$2877 + attribute \src "libresoc.v:48395.3-48424.6" + process $proc$libresoc.v:48395$2894 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47557.5-47557.29" + attribute \src "libresoc.v:48396.5-48396.29" switch \initial - attribute \src "libresoc.v:47557.9-47557.17" + attribute \src "libresoc.v:48396.9-48396.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83244,7 +84242,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83260,7 +84258,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83280,24 +84278,24 @@ module \core update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] end - attribute \src "libresoc.v:47586.3-47614.6" - process $proc$libresoc.v:47586$2878 + attribute \src "libresoc.v:48425.3-48453.6" + process $proc$libresoc.v:48425$2895 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47587.5-47587.29" + attribute \src "libresoc.v:48426.5-48426.29" switch \initial - attribute \src "libresoc.v:47587.9-47587.17" + attribute \src "libresoc.v:48426.9-48426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83309,7 +84307,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83325,24 +84323,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] end - attribute \src "libresoc.v:47615.3-47643.6" - process $proc$libresoc.v:47615$2879 + attribute \src "libresoc.v:48454.3-48482.6" + process $proc$libresoc.v:48454$2896 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:47616.5-47616.29" + attribute \src "libresoc.v:48455.5-48455.29" switch \initial - attribute \src "libresoc.v:47616.9-47616.17" + attribute \src "libresoc.v:48455.9-48455.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83354,7 +84352,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83370,24 +84368,24 @@ module \core sync always update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] end - attribute \src "libresoc.v:47644.3-47672.6" - process $proc$libresoc.v:47644$2880 + attribute \src "libresoc.v:48483.3-48511.6" + process $proc$libresoc.v:48483$2897 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47645.5-47645.29" + attribute \src "libresoc.v:48484.5-48484.29" switch \initial - attribute \src "libresoc.v:47645.9-47645.17" + attribute \src "libresoc.v:48484.9-48484.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83399,7 +84397,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83415,24 +84413,24 @@ module \core sync always update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] end - attribute \src "libresoc.v:47673.3-47701.6" - process $proc$libresoc.v:47673$2881 + attribute \src "libresoc.v:48512.3-48540.6" + process $proc$libresoc.v:48512$2898 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47674.5-47674.29" + attribute \src "libresoc.v:48513.5-48513.29" switch \initial - attribute \src "libresoc.v:47674.9-47674.17" + attribute \src "libresoc.v:48513.9-48513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83444,7 +84442,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83460,24 +84458,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] end - attribute \src "libresoc.v:47702.3-47730.6" - process $proc$libresoc.v:47702$2882 + attribute \src "libresoc.v:48541.3-48569.6" + process $proc$libresoc.v:48541$2899 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47703.5-47703.29" + attribute \src "libresoc.v:48542.5-48542.29" switch \initial - attribute \src "libresoc.v:47703.9-47703.17" + attribute \src "libresoc.v:48542.9-48542.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83489,7 +84487,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83505,1570 +84503,1169 @@ module \core sync always update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] end - attribute \src "libresoc.v:47731.3-47759.6" - process $proc$libresoc.v:47731$2883 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47732.5-47732.29" - switch \initial - attribute \src "libresoc.v:47732.9-47732.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry - case - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] - end - attribute \src "libresoc.v:47760.3-47788.6" - process $proc$libresoc.v:47760$2884 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47761.5-47761.29" - switch \initial - attribute \src "libresoc.v:47761.9-47761.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit - case - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] - end - attribute \src "libresoc.v:47789.3-47817.6" - process $proc$libresoc.v:47789$2885 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47790.5-47790.29" - switch \initial - attribute \src "libresoc.v:47790.9-47790.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed - case - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] - end - attribute \src "libresoc.v:47818.3-47846.6" - process $proc$libresoc.v:47818$2886 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47819.5-47819.29" - switch \initial - attribute \src "libresoc.v:47819.9-47819.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len - case - assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] - end - attribute \src "libresoc.v:47847.3-47875.6" - process $proc$libresoc.v:47847$2887 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47848.5-47848.29" - switch \initial - attribute \src "libresoc.v:47848.9-47848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn - case - assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] - end - attribute \src "libresoc.v:47876.3-47904.6" - process $proc$libresoc.v:47876$2888 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$20[0:0]$2889 $1\fus_cu_issue_i$20[0:0]$2890 - attribute \src "libresoc.v:47877.5-47877.29" - switch \initial - attribute \src "libresoc.v:47877.9-47877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$20[0:0]$2890 $2\fus_cu_issue_i$20[0:0]$2891 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$20[0:0]$2891 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$20[0:0]$2891 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$20[0:0]$2891 $3\fus_cu_issue_i$20[0:0]$2892 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$20[0:0]$2892 \issue_i - case - assign $3\fus_cu_issue_i$20[0:0]$2892 1'0 - end - end - case - assign $1\fus_cu_issue_i$20[0:0]$2890 1'0 - end - sync always - update \fus_cu_issue_i$20 $0\fus_cu_issue_i$20[0:0]$2889 - end - attribute \src "libresoc.v:47905.3-47933.6" - process $proc$libresoc.v:47905$2893 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$22[2:0]$2894 $1\fus_cu_rdmaskn_i$22[2:0]$2895 - attribute \src "libresoc.v:47906.5-47906.29" - switch \initial - attribute \src "libresoc.v:47906.9-47906.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$22[2:0]$2895 $2\fus_cu_rdmaskn_i$22[2:0]$2896 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$22[2:0]$2896 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$22[2:0]$2896 3'000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$22[2:0]$2896 $3\fus_cu_rdmaskn_i$22[2:0]$2897 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$22[2:0]$2897 \$249 - case - assign $3\fus_cu_rdmaskn_i$22[2:0]$2897 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$22[2:0]$2895 3'000 - end - sync always - update \fus_cu_rdmaskn_i$22 $0\fus_cu_rdmaskn_i$22[2:0]$2894 - end - attribute \src "libresoc.v:47934.3-47962.6" - process $proc$libresoc.v:47934$2898 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:47935.5-47935.29" - switch \initial - attribute \src "libresoc.v:47935.9-47935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type - case - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] - end - attribute \src "libresoc.v:47963.3-47991.6" - process $proc$libresoc.v:47963$2899 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__fn_unit[11:0] $1\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:47964.5-47964.29" - switch \initial - attribute \src "libresoc.v:47964.9-47964.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] $2\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] $3\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] \dec_SPR_SPR__fn_unit - case - assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[11:0] - end - connect \$1002 $not$libresoc.v:41533$1506_Y - connect \$1004 $and$libresoc.v:41534$1507_Y - connect \$1011 $and$libresoc.v:41535$1508_Y - connect \$1014 $ternary$libresoc.v:41536$1509_Y - connect \$1016 $and$libresoc.v:41537$1510_Y - connect \$1019 $and$libresoc.v:41538$1511_Y - connect \$1023 $not$libresoc.v:41539$1512_Y - connect \$1025 $and$libresoc.v:41540$1513_Y - connect \$1029 $and$libresoc.v:41541$1514_Y - connect \$1032 $ternary$libresoc.v:41542$1515_Y - connect \$1034 $and$libresoc.v:41543$1516_Y - connect \$1037 $and$libresoc.v:41544$1517_Y - connect \$1041 $not$libresoc.v:41545$1518_Y - connect \$1043 $and$libresoc.v:41546$1519_Y - connect \$1051 $and$libresoc.v:41547$1520_Y - connect \$1054 $ternary$libresoc.v:41548$1521_Y - connect \$1056 $and$libresoc.v:41549$1522_Y - connect \$1059 $and$libresoc.v:41550$1523_Y - connect \$1063 $not$libresoc.v:41551$1524_Y - connect \$1065 $and$libresoc.v:41552$1525_Y - connect \$1071 $and$libresoc.v:41553$1526_Y - connect \$1074 $ternary$libresoc.v:41554$1527_Y - connect \$1076 $and$libresoc.v:41555$1528_Y - connect \$1079 $and$libresoc.v:41556$1529_Y - connect \$1083 $not$libresoc.v:41557$1530_Y - connect \$1085 $and$libresoc.v:41558$1531_Y - connect \$1091 $and$libresoc.v:41559$1532_Y - connect \$1094 $ternary$libresoc.v:41560$1533_Y - connect \$1096 $and$libresoc.v:41561$1534_Y - connect \$1099 $and$libresoc.v:41562$1535_Y - connect \$1103 $not$libresoc.v:41563$1536_Y - connect \$1105 $and$libresoc.v:41564$1537_Y - connect \$1110 $and$libresoc.v:41565$1538_Y - connect \$1113 $ternary$libresoc.v:41566$1539_Y - connect \$1115 $and$libresoc.v:41567$1540_Y - connect \$1118 $and$libresoc.v:41568$1541_Y - connect \$1122 $not$libresoc.v:41569$1542_Y - connect \$1124 $and$libresoc.v:41570$1543_Y - connect \$1128 $and$libresoc.v:41571$1544_Y - connect \$1131 $ternary$libresoc.v:41572$1545_Y - connect \$1133 $and$libresoc.v:41573$1546_Y - connect \$1136 $and$libresoc.v:41574$1547_Y - connect \$1139 $not$libresoc.v:41575$1548_Y - connect \$1141 $and$libresoc.v:41576$1549_Y - connect \$1144 $and$libresoc.v:41577$1550_Y - connect \$1147 $ternary$libresoc.v:41578$1551_Y - connect \$1150 $or$libresoc.v:41579$1552_Y - connect \$1152 $or$libresoc.v:41580$1553_Y - connect \$1154 $or$libresoc.v:41581$1554_Y - connect \$1156 $or$libresoc.v:41582$1555_Y - connect \$1158 $or$libresoc.v:41583$1556_Y - connect \$1160 $or$libresoc.v:41584$1557_Y - connect \$1162 $or$libresoc.v:41585$1558_Y - connect \$1164 $or$libresoc.v:41586$1559_Y - connect \$1166 $or$libresoc.v:41587$1560_Y - connect \$1168 $or$libresoc.v:41588$1561_Y - connect \$1170 $or$libresoc.v:41589$1562_Y - connect \$1172 $or$libresoc.v:41590$1563_Y - connect \$1174 $or$libresoc.v:41591$1564_Y - connect \$1176 $or$libresoc.v:41592$1565_Y - connect \$1178 $or$libresoc.v:41593$1566_Y - connect \$1180 $or$libresoc.v:41594$1567_Y - connect \$1182 $or$libresoc.v:41595$1568_Y - connect \$1184 $or$libresoc.v:41596$1569_Y - connect \$1186 $or$libresoc.v:41597$1570_Y - connect \$1188 $or$libresoc.v:41598$1571_Y - connect \$1190 $or$libresoc.v:41599$1572_Y - connect \$1192 $or$libresoc.v:41600$1573_Y - connect \$1194 $or$libresoc.v:41601$1574_Y - connect \$1196 $or$libresoc.v:41602$1575_Y - connect \$1198 $or$libresoc.v:41603$1576_Y - connect \$1200 $or$libresoc.v:41604$1577_Y - connect \$1202 $or$libresoc.v:41605$1578_Y - connect \$1204 $and$libresoc.v:41606$1579_Y - connect \$1206 $and$libresoc.v:41607$1580_Y - connect \$1209 $and$libresoc.v:41608$1581_Y - connect \$1212 $not$libresoc.v:41609$1582_Y - connect \$1214 $and$libresoc.v:41610$1583_Y - connect \$1217 $and$libresoc.v:41611$1584_Y - connect \$1220 $ternary$libresoc.v:41612$1585_Y - connect \$1222 $and$libresoc.v:41613$1586_Y - connect \$1224 $and$libresoc.v:41614$1587_Y - connect \$1226 $and$libresoc.v:41615$1588_Y - connect \$1228 $and$libresoc.v:41616$1589_Y - connect \$1230 $and$libresoc.v:41617$1590_Y - connect \$1232 $and$libresoc.v:41618$1591_Y - connect \$1234 $and$libresoc.v:41619$1592_Y - connect \$1237 $and$libresoc.v:41620$1593_Y - connect \$1240 $not$libresoc.v:41621$1594_Y - connect \$1242 $and$libresoc.v:41622$1595_Y - connect \$1245 $and$libresoc.v:41623$1596_Y - connect \$1248 $sub$libresoc.v:41624$1597_Y - connect \$1250 $sshl$libresoc.v:41625$1598_Y - connect \$1252 $ternary$libresoc.v:41626$1599_Y - connect \$1254 $and$libresoc.v:41627$1600_Y - connect \$1257 $and$libresoc.v:41628$1601_Y - connect \$1260 $not$libresoc.v:41629$1602_Y - connect \$1262 $and$libresoc.v:41630$1603_Y - connect \$1265 $and$libresoc.v:41631$1604_Y - connect \$1268 $sub$libresoc.v:41632$1605_Y - connect \$1270 $sshl$libresoc.v:41633$1606_Y - connect \$1272 $ternary$libresoc.v:41634$1607_Y - connect \$1274 $and$libresoc.v:41635$1608_Y - connect \$1277 $and$libresoc.v:41636$1609_Y - connect \$1280 $not$libresoc.v:41637$1610_Y - connect \$1282 $and$libresoc.v:41638$1611_Y - connect \$1285 $and$libresoc.v:41639$1612_Y - connect \$1288 $sub$libresoc.v:41640$1613_Y - connect \$1290 $sshl$libresoc.v:41641$1614_Y - connect \$1292 $ternary$libresoc.v:41642$1615_Y - connect \$1294 $and$libresoc.v:41643$1616_Y - connect \$1297 $and$libresoc.v:41644$1617_Y - connect \$1300 $not$libresoc.v:41645$1618_Y - connect \$1302 $and$libresoc.v:41646$1619_Y - connect \$1305 $and$libresoc.v:41647$1620_Y - connect \$1308 $sub$libresoc.v:41648$1621_Y - connect \$1310 $sshl$libresoc.v:41649$1622_Y - connect \$1312 $ternary$libresoc.v:41650$1623_Y - connect \$1314 $and$libresoc.v:41651$1624_Y - connect \$1317 $and$libresoc.v:41652$1625_Y - connect \$1320 $not$libresoc.v:41653$1626_Y - connect \$1322 $and$libresoc.v:41654$1627_Y - connect \$1325 $and$libresoc.v:41655$1628_Y - connect \$1328 $sub$libresoc.v:41656$1629_Y - connect \$1330 $sshl$libresoc.v:41657$1630_Y - connect \$1332 $ternary$libresoc.v:41658$1631_Y - connect \$1334 $and$libresoc.v:41659$1632_Y - connect \$1337 $and$libresoc.v:41660$1633_Y - connect \$1340 $not$libresoc.v:41661$1634_Y - connect \$1342 $and$libresoc.v:41662$1635_Y - connect \$1345 $and$libresoc.v:41663$1636_Y - connect \$1348 $sub$libresoc.v:41664$1637_Y - connect \$1350 $sshl$libresoc.v:41665$1638_Y - connect \$1352 $ternary$libresoc.v:41666$1639_Y - connect \$1354 $or$libresoc.v:41667$1640_Y - connect \$1356 $or$libresoc.v:41668$1641_Y - connect \$1358 $or$libresoc.v:41669$1642_Y - connect \$1360 $or$libresoc.v:41670$1643_Y - connect \$1362 $or$libresoc.v:41671$1644_Y - connect \$1365 $or$libresoc.v:41672$1645_Y - connect \$1367 $or$libresoc.v:41673$1646_Y - connect \$1369 $or$libresoc.v:41674$1647_Y - connect \$1371 $or$libresoc.v:41675$1648_Y - connect \$1373 $or$libresoc.v:41676$1649_Y - connect \$1375 $and$libresoc.v:41677$1650_Y - connect \$1377 $and$libresoc.v:41678$1651_Y - connect \$1379 $and$libresoc.v:41679$1652_Y - connect \$1381 $and$libresoc.v:41680$1653_Y - connect \$1384 $and$libresoc.v:41681$1654_Y - connect \$1387 $not$libresoc.v:41682$1655_Y - connect \$1389 $and$libresoc.v:41683$1656_Y - connect \$1392 $and$libresoc.v:41684$1657_Y - connect \$1395 $ternary$libresoc.v:41685$1658_Y - connect \$1397 $and$libresoc.v:41686$1659_Y - connect \$1400 $and$libresoc.v:41687$1660_Y - connect \$1403 $not$libresoc.v:41688$1661_Y - connect \$1405 $and$libresoc.v:41689$1662_Y - connect \$1408 $and$libresoc.v:41690$1663_Y - connect \$1411 $ternary$libresoc.v:41691$1664_Y - connect \$1413 $and$libresoc.v:41692$1665_Y - connect \$1416 $and$libresoc.v:41693$1666_Y - connect \$1419 $not$libresoc.v:41694$1667_Y - connect \$1421 $and$libresoc.v:41695$1668_Y - connect \$1424 $and$libresoc.v:41696$1669_Y - connect \$1427 $ternary$libresoc.v:41697$1670_Y - connect \$1429 $or$libresoc.v:41698$1671_Y - connect \$1431 $or$libresoc.v:41699$1672_Y - connect \$1434 $or$libresoc.v:41700$1673_Y - connect \$1436 $or$libresoc.v:41701$1674_Y - connect \$1433 $pos$libresoc.v:41702$1676_Y - connect \$1439 $and$libresoc.v:41703$1677_Y - connect \$1441 $and$libresoc.v:41704$1678_Y - connect \$1443 $and$libresoc.v:41705$1679_Y - connect \$1445 $and$libresoc.v:41706$1680_Y - connect \$1447 $and$libresoc.v:41707$1681_Y - connect \$1450 $and$libresoc.v:41708$1682_Y - connect \$1453 $not$libresoc.v:41709$1683_Y - connect \$1455 $and$libresoc.v:41710$1684_Y - connect \$1458 $and$libresoc.v:41711$1685_Y - connect \$1461 $ternary$libresoc.v:41712$1686_Y - connect \$1463 $and$libresoc.v:41713$1687_Y - connect \$1466 $and$libresoc.v:41714$1688_Y - connect \$1469 $not$libresoc.v:41715$1689_Y - connect \$1471 $and$libresoc.v:41716$1690_Y - connect \$1474 $and$libresoc.v:41717$1691_Y - connect \$1477 $ternary$libresoc.v:41718$1692_Y - connect \$1479 $and$libresoc.v:41719$1693_Y - connect \$1482 $and$libresoc.v:41720$1694_Y - connect \$1485 $not$libresoc.v:41721$1695_Y - connect \$1487 $and$libresoc.v:41722$1696_Y - connect \$1490 $and$libresoc.v:41723$1697_Y - connect \$1493 $ternary$libresoc.v:41724$1698_Y - connect \$1495 $and$libresoc.v:41725$1699_Y - connect \$1498 $and$libresoc.v:41726$1700_Y - connect \$1501 $not$libresoc.v:41727$1701_Y - connect \$1503 $and$libresoc.v:41728$1702_Y - connect \$1506 $and$libresoc.v:41729$1703_Y - connect \$1509 $ternary$libresoc.v:41730$1704_Y - connect \$1511 $or$libresoc.v:41731$1705_Y - connect \$1513 $or$libresoc.v:41732$1706_Y - connect \$1515 $or$libresoc.v:41733$1707_Y - connect \$1517 $or$libresoc.v:41734$1708_Y - connect \$1519 $or$libresoc.v:41735$1709_Y - connect \$1521 $or$libresoc.v:41736$1710_Y - connect \$1523 $and$libresoc.v:41737$1711_Y - connect \$1525 $and$libresoc.v:41738$1712_Y - connect \$1527 $and$libresoc.v:41739$1713_Y - connect \$1529 $and$libresoc.v:41740$1714_Y - connect \$1531 $and$libresoc.v:41741$1715_Y - connect \$1534 $and$libresoc.v:41742$1716_Y - connect \$1537 $not$libresoc.v:41743$1717_Y - connect \$1539 $and$libresoc.v:41744$1718_Y - connect \$1542 $and$libresoc.v:41745$1719_Y - connect \$1545 $ternary$libresoc.v:41746$1720_Y - connect \$1547 $and$libresoc.v:41747$1721_Y - connect \$1550 $and$libresoc.v:41748$1722_Y - connect \$1553 $not$libresoc.v:41749$1723_Y - connect \$1555 $and$libresoc.v:41750$1724_Y - connect \$1558 $and$libresoc.v:41751$1725_Y - connect \$1561 $ternary$libresoc.v:41752$1726_Y - connect \$1563 $and$libresoc.v:41753$1727_Y - connect \$1566 $and$libresoc.v:41754$1728_Y - connect \$1569 $not$libresoc.v:41755$1729_Y - connect \$1571 $and$libresoc.v:41756$1730_Y - connect \$1574 $and$libresoc.v:41757$1731_Y - connect \$1577 $ternary$libresoc.v:41758$1732_Y - connect \$1579 $and$libresoc.v:41759$1733_Y - connect \$1582 $and$libresoc.v:41760$1734_Y - connect \$1585 $not$libresoc.v:41761$1735_Y - connect \$1587 $and$libresoc.v:41762$1736_Y - connect \$1590 $and$libresoc.v:41763$1737_Y - connect \$1593 $ternary$libresoc.v:41764$1738_Y - connect \$1596 $or$libresoc.v:41765$1739_Y - connect \$1598 $or$libresoc.v:41766$1740_Y - connect \$1600 $or$libresoc.v:41767$1741_Y - connect \$1595 $pos$libresoc.v:41768$1743_Y - connect \$1604 $or$libresoc.v:41769$1744_Y - connect \$1606 $or$libresoc.v:41770$1745_Y - connect \$1608 $or$libresoc.v:41771$1746_Y - connect \$1603 $pos$libresoc.v:41772$1748_Y - connect \$1611 $and$libresoc.v:41773$1749_Y - connect \$1613 $and$libresoc.v:41774$1750_Y - connect \$1615 $and$libresoc.v:41775$1751_Y - connect \$1617 $and$libresoc.v:41776$1752_Y - connect \$1619 $and$libresoc.v:41777$1753_Y - connect \$1621 $and$libresoc.v:41778$1754_Y - connect \$1624 $and$libresoc.v:41779$1755_Y - connect \$1628 $not$libresoc.v:41780$1756_Y - connect \$1630 $and$libresoc.v:41781$1757_Y - connect \$1635 $and$libresoc.v:41782$1758_Y - connect \$1638 $ternary$libresoc.v:41783$1759_Y - connect \$1640 $and$libresoc.v:41784$1760_Y - connect \$1643 $and$libresoc.v:41785$1761_Y - connect \$1646 $not$libresoc.v:41786$1762_Y - connect \$1648 $and$libresoc.v:41787$1763_Y - connect \$1651 $and$libresoc.v:41788$1764_Y - connect \$1654 $ternary$libresoc.v:41789$1765_Y - connect \$1656 $and$libresoc.v:41790$1766_Y - connect \$1659 $and$libresoc.v:41791$1767_Y - connect \$1662 $not$libresoc.v:41792$1768_Y - connect \$1664 $and$libresoc.v:41793$1769_Y - connect \$1667 $and$libresoc.v:41794$1770_Y - connect \$1670 $ternary$libresoc.v:41795$1771_Y - connect \$1672 $and$libresoc.v:41796$1772_Y - connect \$1675 $and$libresoc.v:41797$1773_Y - connect \$1678 $not$libresoc.v:41798$1774_Y - connect \$1680 $and$libresoc.v:41799$1775_Y - connect \$1683 $and$libresoc.v:41800$1776_Y - connect \$1686 $ternary$libresoc.v:41801$1777_Y - connect \$1688 $and$libresoc.v:41802$1778_Y - connect \$1691 $and$libresoc.v:41803$1779_Y - connect \$1694 $not$libresoc.v:41804$1780_Y - connect \$1696 $and$libresoc.v:41805$1781_Y - connect \$1699 $and$libresoc.v:41806$1782_Y - connect \$1702 $ternary$libresoc.v:41807$1783_Y - connect \$1704 $or$libresoc.v:41808$1784_Y - connect \$1706 $or$libresoc.v:41809$1785_Y - connect \$1708 $or$libresoc.v:41810$1786_Y - connect \$1710 $or$libresoc.v:41811$1787_Y - connect \$1712 $or$libresoc.v:41812$1788_Y - connect \$1714 $or$libresoc.v:41813$1789_Y - connect \$1716 $or$libresoc.v:41814$1790_Y - connect \$1718 $or$libresoc.v:41815$1791_Y - connect \$1720 $or$libresoc.v:41816$1792_Y - connect \$1722 $or$libresoc.v:41817$1793_Y - connect \$1724 $or$libresoc.v:41818$1794_Y - connect \$1726 $or$libresoc.v:41819$1795_Y - connect \$1728 $and$libresoc.v:41820$1796_Y - connect \$1730 $and$libresoc.v:41821$1797_Y - connect \$1732 $and$libresoc.v:41822$1798_Y - connect \$1735 $and$libresoc.v:41823$1799_Y - connect \$1738 $not$libresoc.v:41824$1800_Y - connect \$1740 $and$libresoc.v:41825$1801_Y - connect \$1743 $and$libresoc.v:41826$1802_Y - connect \$1746 $ternary$libresoc.v:41827$1803_Y - connect \$1748 $and$libresoc.v:41828$1804_Y - connect \$1751 $and$libresoc.v:41829$1805_Y - connect \$1754 $not$libresoc.v:41830$1806_Y - connect \$1756 $and$libresoc.v:41831$1807_Y - connect \$175 $and$libresoc.v:41832$1808_Y - connect \$1759 $and$libresoc.v:41833$1809_Y - connect \$1762 $ternary$libresoc.v:41834$1810_Y - connect \$1764 $or$libresoc.v:41835$1811_Y - connect \$1767 $or$libresoc.v:41836$1812_Y - connect \$1766 $pos$libresoc.v:41837$1814_Y - connect \$174 $reduce_or$libresoc.v:41838$1815_Y - connect \$1770 $and$libresoc.v:41839$1816_Y - connect \$1772 $and$libresoc.v:41840$1817_Y - connect \$1775 $and$libresoc.v:41841$1818_Y - connect \$1778 $not$libresoc.v:41842$1819_Y - connect \$1780 $and$libresoc.v:41843$1820_Y - connect \$1783 $and$libresoc.v:41844$1821_Y - connect \$1786 $ternary$libresoc.v:41845$1822_Y - connect \$1788 $pos$libresoc.v:41846$1824_Y - connect \$1790 $and$libresoc.v:41847$1825_Y - connect \$1792 $and$libresoc.v:41848$1826_Y - connect \$1795 $and$libresoc.v:41849$1827_Y - connect \$1798 $not$libresoc.v:41850$1828_Y - connect \$179 $and$libresoc.v:41851$1829_Y - connect \$1800 $and$libresoc.v:41852$1830_Y - connect \$1803 $and$libresoc.v:41853$1831_Y - connect \$1806 $ternary$libresoc.v:41854$1832_Y - connect \$178 $reduce_or$libresoc.v:41855$1833_Y - connect \$183 $and$libresoc.v:41856$1834_Y - connect \$182 $reduce_or$libresoc.v:41857$1835_Y - connect \$187 $and$libresoc.v:41858$1836_Y - connect \$186 $reduce_or$libresoc.v:41859$1837_Y - connect \$191 $and$libresoc.v:41860$1838_Y - connect \$190 $reduce_or$libresoc.v:41861$1839_Y - connect \$195 $and$libresoc.v:41862$1840_Y - connect \$194 $reduce_or$libresoc.v:41863$1841_Y - connect \$199 $and$libresoc.v:41864$1842_Y - connect \$198 $reduce_or$libresoc.v:41865$1843_Y - connect \$203 $and$libresoc.v:41866$1844_Y - connect \$202 $reduce_or$libresoc.v:41867$1845_Y - connect \$207 $and$libresoc.v:41868$1846_Y - connect \$206 $reduce_or$libresoc.v:41869$1847_Y - connect \$211 $and$libresoc.v:41870$1848_Y - connect \$210 $reduce_or$libresoc.v:41871$1849_Y - connect \$214 $ne$libresoc.v:41872$1850_Y - connect \$217 $sub$libresoc.v:41873$1851_Y - connect \$219 $ne$libresoc.v:41874$1852_Y - connect \$222 $and$libresoc.v:41875$1853_Y - connect \$224 $and$libresoc.v:41876$1854_Y - connect \$226 $eq$libresoc.v:41877$1855_Y - connect \$228 $or$libresoc.v:41878$1856_Y - connect \$230 $and$libresoc.v:41879$1857_Y - connect \$232 $or$libresoc.v:41880$1858_Y - connect \$234 $eq$libresoc.v:41881$1859_Y - connect \$236 $and$libresoc.v:41882$1860_Y - connect \$238 $eq$libresoc.v:41883$1861_Y - connect \$240 $or$libresoc.v:41884$1862_Y - connect \$221 $not$libresoc.v:41885$1863_Y - connect \$243 $not$libresoc.v:41886$1864_Y - connect \$245 $not$libresoc.v:41887$1865_Y - connect \$247 $not$libresoc.v:41888$1866_Y - connect \$250 $and$libresoc.v:41889$1867_Y - connect \$252 $and$libresoc.v:41890$1868_Y - connect \$254 $eq$libresoc.v:41891$1869_Y - connect \$256 $or$libresoc.v:41892$1870_Y - connect \$258 $and$libresoc.v:41893$1871_Y - connect \$260 $or$libresoc.v:41894$1872_Y - connect \$249 $not$libresoc.v:41895$1873_Y - connect \$264 $and$libresoc.v:41896$1874_Y - connect \$266 $and$libresoc.v:41897$1875_Y - connect \$268 $eq$libresoc.v:41898$1876_Y - connect \$270 $or$libresoc.v:41899$1877_Y - connect \$272 $and$libresoc.v:41900$1878_Y - connect \$274 $or$libresoc.v:41901$1879_Y - connect \$276 $and$libresoc.v:41902$1880_Y - connect \$278 $and$libresoc.v:41903$1881_Y - connect \$280 $eq$libresoc.v:41904$1882_Y - connect \$282 $or$libresoc.v:41905$1883_Y - connect \$284 $eq$libresoc.v:41906$1884_Y - connect \$286 $and$libresoc.v:41907$1885_Y - connect \$288 $eq$libresoc.v:41908$1886_Y - connect \$290 $or$libresoc.v:41909$1887_Y - connect \$263 $not$libresoc.v:41910$1888_Y - connect \$294 $and$libresoc.v:41911$1889_Y - connect \$296 $and$libresoc.v:41912$1890_Y - connect \$298 $eq$libresoc.v:41913$1891_Y - connect \$300 $or$libresoc.v:41914$1892_Y - connect \$302 $and$libresoc.v:41915$1893_Y - connect \$304 $or$libresoc.v:41916$1894_Y - connect \$293 $not$libresoc.v:41917$1895_Y - connect \$308 $and$libresoc.v:41918$1896_Y - connect \$310 $and$libresoc.v:41919$1897_Y - connect \$312 $eq$libresoc.v:41920$1898_Y - connect \$314 $or$libresoc.v:41921$1899_Y - connect \$316 $and$libresoc.v:41922$1900_Y - connect \$318 $or$libresoc.v:41923$1901_Y - connect \$307 $not$libresoc.v:41924$1902_Y - connect \$322 $and$libresoc.v:41925$1903_Y - connect \$324 $and$libresoc.v:41926$1904_Y - connect \$326 $eq$libresoc.v:41927$1905_Y - connect \$328 $or$libresoc.v:41928$1906_Y - connect \$330 $and$libresoc.v:41929$1907_Y - connect \$332 $or$libresoc.v:41930$1908_Y - connect \$334 $eq$libresoc.v:41931$1909_Y - connect \$336 $and$libresoc.v:41932$1910_Y - connect \$338 $eq$libresoc.v:41933$1911_Y - connect \$340 $or$libresoc.v:41934$1912_Y - connect \$321 $not$libresoc.v:41935$1913_Y - connect \$343 $not$libresoc.v:41936$1914_Y - connect \$345 $and$libresoc.v:41937$1915_Y - connect \$347 $and$libresoc.v:41938$1916_Y - connect \$349 $not$libresoc.v:41939$1917_Y - connect \$351 $and$libresoc.v:41940$1918_Y - connect \$353 $and$libresoc.v:41941$1919_Y - connect \$355 $ternary$libresoc.v:41942$1920_Y - connect \$357 $and$libresoc.v:41943$1921_Y - connect \$359 $and$libresoc.v:41944$1922_Y - connect \$361 $not$libresoc.v:41945$1923_Y - connect \$363 $and$libresoc.v:41946$1924_Y - connect \$365 $and$libresoc.v:41947$1925_Y - connect \$367 $ternary$libresoc.v:41948$1926_Y - connect \$369 $and$libresoc.v:41949$1927_Y - connect \$371 $and$libresoc.v:41950$1928_Y - connect \$373 $not$libresoc.v:41951$1929_Y - connect \$375 $and$libresoc.v:41952$1930_Y - connect \$377 $and$libresoc.v:41953$1931_Y - connect \$379 $ternary$libresoc.v:41954$1932_Y - connect \$381 $and$libresoc.v:41955$1933_Y - connect \$383 $and$libresoc.v:41956$1934_Y - connect \$385 $not$libresoc.v:41957$1935_Y - connect \$387 $and$libresoc.v:41958$1936_Y - connect \$389 $and$libresoc.v:41959$1937_Y - connect \$391 $ternary$libresoc.v:41960$1938_Y - connect \$393 $and$libresoc.v:41961$1939_Y - connect \$395 $and$libresoc.v:41962$1940_Y - connect \$397 $not$libresoc.v:41963$1941_Y - connect \$399 $and$libresoc.v:41964$1942_Y - connect \$401 $and$libresoc.v:41965$1943_Y - connect \$403 $ternary$libresoc.v:41966$1944_Y - connect \$405 $and$libresoc.v:41967$1945_Y - connect \$407 $and$libresoc.v:41968$1946_Y - connect \$409 $not$libresoc.v:41969$1947_Y - connect \$411 $and$libresoc.v:41970$1948_Y - connect \$413 $and$libresoc.v:41971$1949_Y - connect \$415 $ternary$libresoc.v:41972$1950_Y - connect \$417 $and$libresoc.v:41973$1951_Y - connect \$419 $and$libresoc.v:41974$1952_Y - connect \$421 $not$libresoc.v:41975$1953_Y - connect \$423 $and$libresoc.v:41976$1954_Y - connect \$425 $and$libresoc.v:41977$1955_Y - connect \$427 $ternary$libresoc.v:41978$1956_Y - connect \$429 $and$libresoc.v:41979$1957_Y - connect \$431 $and$libresoc.v:41980$1958_Y - connect \$433 $not$libresoc.v:41981$1959_Y - connect \$435 $and$libresoc.v:41982$1960_Y - connect \$437 $and$libresoc.v:41983$1961_Y - connect \$439 $ternary$libresoc.v:41984$1962_Y - connect \$441 $and$libresoc.v:41985$1963_Y - connect \$443 $and$libresoc.v:41986$1964_Y - connect \$445 $not$libresoc.v:41987$1965_Y - connect \$447 $and$libresoc.v:41988$1966_Y - connect \$449 $and$libresoc.v:41989$1967_Y - connect \$451 $ternary$libresoc.v:41990$1968_Y - connect \$453 $or$libresoc.v:41991$1969_Y - connect \$455 $or$libresoc.v:41992$1970_Y - connect \$457 $or$libresoc.v:41993$1971_Y - connect \$459 $or$libresoc.v:41994$1972_Y - connect \$461 $or$libresoc.v:41995$1973_Y - connect \$463 $or$libresoc.v:41996$1974_Y - connect \$465 $or$libresoc.v:41997$1975_Y - connect \$467 $or$libresoc.v:41998$1976_Y - connect \$469 $reduce_or$libresoc.v:41999$1977_Y - connect \$471 $and$libresoc.v:42000$1978_Y - connect \$473 $and$libresoc.v:42001$1979_Y - connect \$475 $not$libresoc.v:42002$1980_Y - connect \$477 $and$libresoc.v:42003$1981_Y - connect \$479 $and$libresoc.v:42004$1982_Y - connect \$481 $ternary$libresoc.v:42005$1983_Y - connect \$483 $and$libresoc.v:42006$1984_Y - connect \$485 $and$libresoc.v:42007$1985_Y - connect \$487 $not$libresoc.v:42008$1986_Y - connect \$489 $and$libresoc.v:42009$1987_Y - connect \$491 $and$libresoc.v:42010$1988_Y - connect \$493 $ternary$libresoc.v:42011$1989_Y - connect \$495 $and$libresoc.v:42012$1990_Y - connect \$497 $and$libresoc.v:42013$1991_Y - connect \$499 $not$libresoc.v:42014$1992_Y - connect \$501 $and$libresoc.v:42015$1993_Y - connect \$503 $and$libresoc.v:42016$1994_Y - connect \$505 $ternary$libresoc.v:42017$1995_Y - connect \$507 $and$libresoc.v:42018$1996_Y - connect \$509 $and$libresoc.v:42019$1997_Y - connect \$511 $not$libresoc.v:42020$1998_Y - connect \$513 $and$libresoc.v:42021$1999_Y - connect \$515 $and$libresoc.v:42022$2000_Y - connect \$517 $ternary$libresoc.v:42023$2001_Y - connect \$519 $and$libresoc.v:42024$2002_Y - connect \$521 $and$libresoc.v:42025$2003_Y - connect \$523 $not$libresoc.v:42026$2004_Y - connect \$525 $and$libresoc.v:42027$2005_Y - connect \$527 $and$libresoc.v:42028$2006_Y - connect \$529 $ternary$libresoc.v:42029$2007_Y - connect \$531 $and$libresoc.v:42030$2008_Y - connect \$533 $and$libresoc.v:42031$2009_Y - connect \$535 $not$libresoc.v:42032$2010_Y - connect \$537 $and$libresoc.v:42033$2011_Y - connect \$539 $and$libresoc.v:42034$2012_Y - connect \$541 $ternary$libresoc.v:42035$2013_Y - connect \$543 $and$libresoc.v:42036$2014_Y - connect \$545 $and$libresoc.v:42037$2015_Y - connect \$547 $not$libresoc.v:42038$2016_Y - connect \$549 $and$libresoc.v:42039$2017_Y - connect \$551 $and$libresoc.v:42040$2018_Y - connect \$553 $ternary$libresoc.v:42041$2019_Y - connect \$555 $and$libresoc.v:42042$2020_Y - connect \$557 $and$libresoc.v:42043$2021_Y - connect \$559 $not$libresoc.v:42044$2022_Y - connect \$561 $and$libresoc.v:42045$2023_Y - connect \$563 $and$libresoc.v:42046$2024_Y - connect \$565 $ternary$libresoc.v:42047$2025_Y - connect \$567 $or$libresoc.v:42048$2026_Y - connect \$569 $or$libresoc.v:42049$2027_Y - connect \$571 $or$libresoc.v:42050$2028_Y - connect \$573 $or$libresoc.v:42051$2029_Y - connect \$575 $or$libresoc.v:42052$2030_Y - connect \$577 $or$libresoc.v:42053$2031_Y - connect \$579 $or$libresoc.v:42054$2032_Y - connect \$581 $reduce_or$libresoc.v:42055$2033_Y - connect \$583 $and$libresoc.v:42056$2034_Y - connect \$585 $and$libresoc.v:42057$2035_Y - connect \$587 $not$libresoc.v:42058$2036_Y - connect \$589 $and$libresoc.v:42059$2037_Y - connect \$591 $and$libresoc.v:42060$2038_Y - connect \$593 $ternary$libresoc.v:42061$2039_Y - connect \$595 $and$libresoc.v:42062$2040_Y - connect \$597 $and$libresoc.v:42063$2041_Y - connect \$599 $not$libresoc.v:42064$2042_Y - connect \$601 $and$libresoc.v:42065$2043_Y - connect \$603 $and$libresoc.v:42066$2044_Y - connect \$605 $ternary$libresoc.v:42067$2045_Y - connect \$607 $or$libresoc.v:42068$2046_Y - connect \$609 $reduce_or$libresoc.v:42069$2047_Y - connect \$611 $and$libresoc.v:42070$2048_Y - connect \$613 $and$libresoc.v:42071$2049_Y - connect \$615 $eq$libresoc.v:42072$2050_Y - connect \$617 $or$libresoc.v:42073$2051_Y - connect \$619 $and$libresoc.v:42074$2052_Y - connect \$621 $or$libresoc.v:42075$2053_Y - connect \$623 $and$libresoc.v:42076$2054_Y - connect \$625 $and$libresoc.v:42077$2055_Y - connect \$627 $not$libresoc.v:42078$2056_Y - connect \$629 $and$libresoc.v:42079$2057_Y - connect \$631 $and$libresoc.v:42080$2058_Y - connect \$633 $ternary$libresoc.v:42081$2059_Y - connect \$635 $and$libresoc.v:42082$2060_Y - connect \$637 $and$libresoc.v:42083$2061_Y - connect \$639 $not$libresoc.v:42084$2062_Y - connect \$641 $and$libresoc.v:42085$2063_Y - connect \$643 $and$libresoc.v:42086$2064_Y - connect \$645 $ternary$libresoc.v:42087$2065_Y - connect \$647 $and$libresoc.v:42088$2066_Y - connect \$649 $and$libresoc.v:42089$2067_Y - connect \$651 $not$libresoc.v:42090$2068_Y - connect \$653 $and$libresoc.v:42091$2069_Y - connect \$655 $and$libresoc.v:42092$2070_Y - connect \$657 $ternary$libresoc.v:42093$2071_Y - connect \$659 $and$libresoc.v:42094$2072_Y - connect \$661 $and$libresoc.v:42095$2073_Y - connect \$663 $not$libresoc.v:42096$2074_Y - connect \$665 $and$libresoc.v:42097$2075_Y - connect \$667 $and$libresoc.v:42098$2076_Y - connect \$669 $ternary$libresoc.v:42099$2077_Y - connect \$671 $and$libresoc.v:42100$2078_Y - connect \$673 $and$libresoc.v:42101$2079_Y - connect \$675 $not$libresoc.v:42102$2080_Y - connect \$677 $and$libresoc.v:42103$2081_Y - connect \$679 $and$libresoc.v:42104$2082_Y - connect \$681 $ternary$libresoc.v:42105$2083_Y - connect \$683 $and$libresoc.v:42106$2084_Y - connect \$685 $and$libresoc.v:42107$2085_Y - connect \$687 $not$libresoc.v:42108$2086_Y - connect \$689 $and$libresoc.v:42109$2087_Y - connect \$691 $and$libresoc.v:42110$2088_Y - connect \$693 $ternary$libresoc.v:42111$2089_Y - connect \$696 $or$libresoc.v:42112$2090_Y - connect \$698 $or$libresoc.v:42113$2091_Y - connect \$700 $or$libresoc.v:42114$2092_Y - connect \$702 $or$libresoc.v:42115$2093_Y - connect \$704 $or$libresoc.v:42116$2094_Y - connect \$695 $pos$libresoc.v:42117$2096_Y - connect \$707 $eq$libresoc.v:42118$2097_Y - connect \$709 $and$libresoc.v:42119$2098_Y - connect \$711 $eq$libresoc.v:42120$2099_Y - connect \$713 $or$libresoc.v:42121$2100_Y - connect \$715 $and$libresoc.v:42122$2101_Y - connect \$717 $and$libresoc.v:42123$2102_Y - connect \$719 $not$libresoc.v:42124$2103_Y - connect \$721 $and$libresoc.v:42125$2104_Y - connect \$723 $and$libresoc.v:42126$2105_Y - connect \$725 $ternary$libresoc.v:42127$2106_Y - connect \$727 $and$libresoc.v:42128$2107_Y - connect \$729 $and$libresoc.v:42129$2108_Y - connect \$731 $not$libresoc.v:42130$2109_Y - connect \$733 $and$libresoc.v:42131$2110_Y - connect \$735 $and$libresoc.v:42132$2111_Y - connect \$737 $ternary$libresoc.v:42133$2112_Y - connect \$739 $and$libresoc.v:42134$2113_Y - connect \$741 $and$libresoc.v:42135$2114_Y - connect \$743 $not$libresoc.v:42136$2115_Y - connect \$745 $and$libresoc.v:42137$2116_Y - connect \$747 $and$libresoc.v:42138$2117_Y - connect \$749 $ternary$libresoc.v:42139$2118_Y - connect \$752 $or$libresoc.v:42140$2119_Y - connect \$754 $or$libresoc.v:42141$2120_Y - connect \$751 $pos$libresoc.v:42142$2122_Y - connect \$757 $and$libresoc.v:42143$2123_Y - connect \$759 $and$libresoc.v:42144$2124_Y - connect \$761 $eq$libresoc.v:42145$2125_Y - connect \$763 $or$libresoc.v:42146$2126_Y - connect \$765 $and$libresoc.v:42147$2127_Y - connect \$767 $and$libresoc.v:42148$2128_Y - connect \$769 $not$libresoc.v:42149$2129_Y - connect \$771 $and$libresoc.v:42150$2130_Y - connect \$773 $and$libresoc.v:42151$2131_Y - connect \$775 $ternary$libresoc.v:42152$2132_Y - connect \$777 $and$libresoc.v:42153$2133_Y - connect \$779 $and$libresoc.v:42154$2134_Y - connect \$781 $not$libresoc.v:42155$2135_Y - connect \$783 $and$libresoc.v:42156$2136_Y - connect \$785 $and$libresoc.v:42157$2137_Y - connect \$787 $ternary$libresoc.v:42158$2138_Y - connect \$789 $and$libresoc.v:42159$2139_Y - connect \$791 $and$libresoc.v:42160$2140_Y - connect \$793 $not$libresoc.v:42161$2141_Y - connect \$795 $and$libresoc.v:42162$2142_Y - connect \$797 $and$libresoc.v:42163$2143_Y - connect \$799 $sub$libresoc.v:42164$2144_Y - connect \$801 $sshl$libresoc.v:42165$2145_Y - connect \$803 $ternary$libresoc.v:42166$2146_Y - connect \$805 $and$libresoc.v:42167$2147_Y - connect \$807 $and$libresoc.v:42168$2148_Y - connect \$809 $not$libresoc.v:42169$2149_Y - connect \$811 $and$libresoc.v:42170$2150_Y - connect \$813 $and$libresoc.v:42171$2151_Y - connect \$815 $sub$libresoc.v:42172$2152_Y - connect \$817 $sshl$libresoc.v:42173$2153_Y - connect \$819 $ternary$libresoc.v:42174$2154_Y - connect \$822 $or$libresoc.v:42175$2155_Y - connect \$824 $and$libresoc.v:42176$2156_Y - connect \$826 $and$libresoc.v:42177$2157_Y - connect \$828 $not$libresoc.v:42178$2158_Y - connect \$830 $and$libresoc.v:42179$2159_Y - connect \$832 $and$libresoc.v:42180$2160_Y - connect \$834 $sub$libresoc.v:42181$2161_Y - connect \$836 $sshl$libresoc.v:42182$2162_Y - connect \$838 $ternary$libresoc.v:42183$2163_Y - connect \$840 $and$libresoc.v:42184$2164_Y - connect \$842 $and$libresoc.v:42185$2165_Y - connect \$844 $not$libresoc.v:42186$2166_Y - connect \$846 $and$libresoc.v:42187$2167_Y - connect \$848 $and$libresoc.v:42188$2168_Y - connect \$850 $sub$libresoc.v:42189$2169_Y - connect \$852 $sshl$libresoc.v:42190$2170_Y - connect \$854 $ternary$libresoc.v:42191$2171_Y - connect \$856 $and$libresoc.v:42192$2172_Y - connect \$858 $and$libresoc.v:42193$2173_Y - connect \$860 $not$libresoc.v:42194$2174_Y - connect \$862 $and$libresoc.v:42195$2175_Y - connect \$864 $and$libresoc.v:42196$2176_Y - connect \$866 $ternary$libresoc.v:42197$2177_Y - connect \$868 $and$libresoc.v:42198$2178_Y - connect \$870 $and$libresoc.v:42199$2179_Y - connect \$872 $not$libresoc.v:42200$2180_Y - connect \$874 $and$libresoc.v:42201$2181_Y - connect \$876 $and$libresoc.v:42202$2182_Y - connect \$878 $ternary$libresoc.v:42203$2183_Y - connect \$880 $and$libresoc.v:42204$2184_Y - connect \$882 $and$libresoc.v:42205$2185_Y - connect \$884 $not$libresoc.v:42206$2186_Y - connect \$886 $and$libresoc.v:42207$2187_Y - connect \$888 $and$libresoc.v:42208$2188_Y - connect \$890 $ternary$libresoc.v:42209$2189_Y - connect \$892 $or$libresoc.v:42210$2190_Y - connect \$894 $or$libresoc.v:42211$2191_Y - connect \$896 $reduce_or$libresoc.v:42212$2192_Y - connect \$898 $and$libresoc.v:42213$2193_Y - connect \$900 $and$libresoc.v:42214$2194_Y - connect \$902 $not$libresoc.v:42215$2195_Y - connect \$904 $and$libresoc.v:42216$2196_Y - connect \$906 $and$libresoc.v:42217$2197_Y - connect \$908 $ternary$libresoc.v:42218$2198_Y - connect \$910 $and$libresoc.v:42219$2199_Y - connect \$912 $and$libresoc.v:42220$2200_Y - connect \$914 $not$libresoc.v:42221$2201_Y - connect \$916 $and$libresoc.v:42222$2202_Y - connect \$918 $and$libresoc.v:42223$2203_Y - connect \$920 $ternary$libresoc.v:42224$2204_Y - connect \$922 $or$libresoc.v:42225$2205_Y - connect \$924 $reduce_or$libresoc.v:42226$2206_Y - connect \$926 $and$libresoc.v:42227$2207_Y - connect \$928 $and$libresoc.v:42228$2208_Y - connect \$930 $not$libresoc.v:42229$2209_Y - connect \$932 $and$libresoc.v:42230$2210_Y - connect \$934 $and$libresoc.v:42231$2211_Y - connect \$936 $ternary$libresoc.v:42232$2212_Y - connect \$938 $reduce_or$libresoc.v:42233$2213_Y - connect \$940 $and$libresoc.v:42234$2214_Y - connect \$942 $and$libresoc.v:42235$2215_Y - connect \$944 $and$libresoc.v:42236$2216_Y - connect \$946 $and$libresoc.v:42237$2217_Y - connect \$948 $and$libresoc.v:42238$2218_Y - connect \$950 $and$libresoc.v:42239$2219_Y - connect \$952 $and$libresoc.v:42240$2220_Y - connect \$954 $and$libresoc.v:42241$2221_Y - connect \$956 $and$libresoc.v:42242$2222_Y - connect \$958 $and$libresoc.v:42243$2223_Y - connect \$960 $and$libresoc.v:42244$2224_Y - connect \$962 $and$libresoc.v:42245$2225_Y - connect \$964 $not$libresoc.v:42246$2226_Y - connect \$966 $and$libresoc.v:42247$2227_Y - connect \$972 $and$libresoc.v:42248$2228_Y - connect \$974 $ternary$libresoc.v:42249$2229_Y - connect \$976 $and$libresoc.v:42250$2230_Y - connect \$979 $and$libresoc.v:42251$2231_Y - connect \$983 $not$libresoc.v:42252$2232_Y - connect \$985 $and$libresoc.v:42253$2233_Y - connect \$990 $and$libresoc.v:42254$2234_Y - connect \$993 $ternary$libresoc.v:42255$2235_Y - connect \$995 $and$libresoc.v:42256$2236_Y - connect \$998 $and$libresoc.v:42257$2237_Y - connect \$216 \$217 - connect \$821 \$822 - connect \$1149 \$1166 - connect \$1364 \$1373 + connect \$1000 $and$libresoc.v:42103$1506_Y + connect \$1003 $ternary$libresoc.v:42104$1507_Y + connect \$1005 $and$libresoc.v:42105$1508_Y + connect \$1008 $and$libresoc.v:42106$1509_Y + connect \$1012 $not$libresoc.v:42107$1510_Y + connect \$1014 $and$libresoc.v:42108$1511_Y + connect \$1021 $and$libresoc.v:42109$1512_Y + connect \$1024 $ternary$libresoc.v:42110$1513_Y + connect \$1026 $and$libresoc.v:42111$1514_Y + connect \$1029 $and$libresoc.v:42112$1515_Y + connect \$1033 $not$libresoc.v:42113$1516_Y + connect \$1035 $and$libresoc.v:42114$1517_Y + connect \$1039 $and$libresoc.v:42115$1518_Y + connect \$1042 $ternary$libresoc.v:42116$1519_Y + connect \$1044 $and$libresoc.v:42117$1520_Y + connect \$1047 $and$libresoc.v:42118$1521_Y + connect \$1051 $not$libresoc.v:42119$1522_Y + connect \$1053 $and$libresoc.v:42120$1523_Y + connect \$1061 $and$libresoc.v:42121$1524_Y + connect \$1064 $ternary$libresoc.v:42122$1525_Y + connect \$1066 $and$libresoc.v:42123$1526_Y + connect \$1069 $and$libresoc.v:42124$1527_Y + connect \$1073 $not$libresoc.v:42125$1528_Y + connect \$1075 $and$libresoc.v:42126$1529_Y + connect \$1081 $and$libresoc.v:42127$1530_Y + connect \$1084 $ternary$libresoc.v:42128$1531_Y + connect \$1086 $and$libresoc.v:42129$1532_Y + connect \$1089 $and$libresoc.v:42130$1533_Y + connect \$1093 $not$libresoc.v:42131$1534_Y + connect \$1095 $and$libresoc.v:42132$1535_Y + connect \$1101 $and$libresoc.v:42133$1536_Y + connect \$1104 $ternary$libresoc.v:42134$1537_Y + connect \$1106 $and$libresoc.v:42135$1538_Y + connect \$1109 $and$libresoc.v:42136$1539_Y + connect \$1113 $not$libresoc.v:42137$1540_Y + connect \$1115 $and$libresoc.v:42138$1541_Y + connect \$1120 $and$libresoc.v:42139$1542_Y + connect \$1123 $ternary$libresoc.v:42140$1543_Y + connect \$1125 $and$libresoc.v:42141$1544_Y + connect \$1128 $and$libresoc.v:42142$1545_Y + connect \$1132 $not$libresoc.v:42143$1546_Y + connect \$1134 $and$libresoc.v:42144$1547_Y + connect \$1138 $and$libresoc.v:42145$1548_Y + connect \$1141 $ternary$libresoc.v:42146$1549_Y + connect \$1143 $and$libresoc.v:42147$1550_Y + connect \$1146 $and$libresoc.v:42148$1551_Y + connect \$1149 $not$libresoc.v:42149$1552_Y + connect \$1151 $and$libresoc.v:42150$1553_Y + connect \$1154 $and$libresoc.v:42151$1554_Y + connect \$1157 $ternary$libresoc.v:42152$1555_Y + connect \$1160 $or$libresoc.v:42153$1556_Y + connect \$1162 $or$libresoc.v:42154$1557_Y + connect \$1164 $or$libresoc.v:42155$1558_Y + connect \$1166 $or$libresoc.v:42156$1559_Y + connect \$1168 $or$libresoc.v:42157$1560_Y + connect \$1170 $or$libresoc.v:42158$1561_Y + connect \$1172 $or$libresoc.v:42159$1562_Y + connect \$1174 $or$libresoc.v:42160$1563_Y + connect \$1176 $or$libresoc.v:42161$1564_Y + connect \$1179 $or$libresoc.v:42162$1565_Y + connect \$1181 $or$libresoc.v:42163$1566_Y + connect \$1183 $or$libresoc.v:42164$1567_Y + connect \$1185 $or$libresoc.v:42165$1568_Y + connect \$1187 $or$libresoc.v:42166$1569_Y + connect \$1189 $or$libresoc.v:42167$1570_Y + connect \$1191 $or$libresoc.v:42168$1571_Y + connect \$1193 $or$libresoc.v:42169$1572_Y + connect \$1195 $or$libresoc.v:42170$1573_Y + connect \$1197 $or$libresoc.v:42171$1574_Y + connect \$1199 $or$libresoc.v:42172$1575_Y + connect \$1201 $or$libresoc.v:42173$1576_Y + connect \$1203 $or$libresoc.v:42174$1577_Y + connect \$1205 $or$libresoc.v:42175$1578_Y + connect \$1207 $or$libresoc.v:42176$1579_Y + connect \$1209 $or$libresoc.v:42177$1580_Y + connect \$1211 $or$libresoc.v:42178$1581_Y + connect \$1213 $or$libresoc.v:42179$1582_Y + connect \$1215 $and$libresoc.v:42180$1583_Y + connect \$1217 $and$libresoc.v:42181$1584_Y + connect \$1220 $and$libresoc.v:42182$1585_Y + connect \$1223 $not$libresoc.v:42183$1586_Y + connect \$1225 $and$libresoc.v:42184$1587_Y + connect \$1228 $and$libresoc.v:42185$1588_Y + connect \$1231 $ternary$libresoc.v:42186$1589_Y + connect \$1233 $and$libresoc.v:42187$1590_Y + connect \$1235 $and$libresoc.v:42188$1591_Y + connect \$1237 $and$libresoc.v:42189$1592_Y + connect \$1239 $and$libresoc.v:42190$1593_Y + connect \$1241 $and$libresoc.v:42191$1594_Y + connect \$1243 $and$libresoc.v:42192$1595_Y + connect \$1245 $and$libresoc.v:42193$1596_Y + connect \$1248 $and$libresoc.v:42194$1597_Y + connect \$1251 $not$libresoc.v:42195$1598_Y + connect \$1253 $and$libresoc.v:42196$1599_Y + connect \$1256 $and$libresoc.v:42197$1600_Y + connect \$1259 $sub$libresoc.v:42198$1601_Y + connect \$1261 $sshl$libresoc.v:42199$1602_Y + connect \$1263 $ternary$libresoc.v:42200$1603_Y + connect \$1265 $and$libresoc.v:42201$1604_Y + connect \$1268 $and$libresoc.v:42202$1605_Y + connect \$1271 $not$libresoc.v:42203$1606_Y + connect \$1273 $and$libresoc.v:42204$1607_Y + connect \$1276 $and$libresoc.v:42205$1608_Y + connect \$1279 $sub$libresoc.v:42206$1609_Y + connect \$1281 $sshl$libresoc.v:42207$1610_Y + connect \$1283 $ternary$libresoc.v:42208$1611_Y + connect \$1285 $and$libresoc.v:42209$1612_Y + connect \$1288 $and$libresoc.v:42210$1613_Y + connect \$1291 $not$libresoc.v:42211$1614_Y + connect \$1293 $and$libresoc.v:42212$1615_Y + connect \$1296 $and$libresoc.v:42213$1616_Y + connect \$1299 $sub$libresoc.v:42214$1617_Y + connect \$1301 $sshl$libresoc.v:42215$1618_Y + connect \$1303 $ternary$libresoc.v:42216$1619_Y + connect \$1305 $and$libresoc.v:42217$1620_Y + connect \$1308 $and$libresoc.v:42218$1621_Y + connect \$1311 $not$libresoc.v:42219$1622_Y + connect \$1313 $and$libresoc.v:42220$1623_Y + connect \$1316 $and$libresoc.v:42221$1624_Y + connect \$1319 $sub$libresoc.v:42222$1625_Y + connect \$1321 $sshl$libresoc.v:42223$1626_Y + connect \$1323 $ternary$libresoc.v:42224$1627_Y + connect \$1325 $and$libresoc.v:42225$1628_Y + connect \$1328 $and$libresoc.v:42226$1629_Y + connect \$1331 $not$libresoc.v:42227$1630_Y + connect \$1333 $and$libresoc.v:42228$1631_Y + connect \$1336 $and$libresoc.v:42229$1632_Y + connect \$1339 $sub$libresoc.v:42230$1633_Y + connect \$1341 $sshl$libresoc.v:42231$1634_Y + connect \$1343 $ternary$libresoc.v:42232$1635_Y + connect \$1345 $and$libresoc.v:42233$1636_Y + connect \$1348 $and$libresoc.v:42234$1637_Y + connect \$1351 $not$libresoc.v:42235$1638_Y + connect \$1353 $and$libresoc.v:42236$1639_Y + connect \$1356 $and$libresoc.v:42237$1640_Y + connect \$1359 $sub$libresoc.v:42238$1641_Y + connect \$1361 $sshl$libresoc.v:42239$1642_Y + connect \$1363 $ternary$libresoc.v:42240$1643_Y + connect \$1365 $or$libresoc.v:42241$1644_Y + connect \$1367 $or$libresoc.v:42242$1645_Y + connect \$1369 $or$libresoc.v:42243$1646_Y + connect \$1371 $or$libresoc.v:42244$1647_Y + connect \$1373 $or$libresoc.v:42245$1648_Y + connect \$1376 $or$libresoc.v:42246$1649_Y + connect \$1378 $or$libresoc.v:42247$1650_Y + connect \$1380 $or$libresoc.v:42248$1651_Y + connect \$1382 $or$libresoc.v:42249$1652_Y + connect \$1384 $or$libresoc.v:42250$1653_Y + connect \$1386 $and$libresoc.v:42251$1654_Y + connect \$1388 $and$libresoc.v:42252$1655_Y + connect \$1390 $and$libresoc.v:42253$1656_Y + connect \$1392 $and$libresoc.v:42254$1657_Y + connect \$1395 $and$libresoc.v:42255$1658_Y + connect \$1398 $not$libresoc.v:42256$1659_Y + connect \$1400 $and$libresoc.v:42257$1660_Y + connect \$1403 $and$libresoc.v:42258$1661_Y + connect \$1406 $ternary$libresoc.v:42259$1662_Y + connect \$1408 $and$libresoc.v:42260$1663_Y + connect \$1411 $and$libresoc.v:42261$1664_Y + connect \$1414 $not$libresoc.v:42262$1665_Y + connect \$1416 $and$libresoc.v:42263$1666_Y + connect \$1419 $and$libresoc.v:42264$1667_Y + connect \$1422 $ternary$libresoc.v:42265$1668_Y + connect \$1424 $and$libresoc.v:42266$1669_Y + connect \$1427 $and$libresoc.v:42267$1670_Y + connect \$1430 $not$libresoc.v:42268$1671_Y + connect \$1432 $and$libresoc.v:42269$1672_Y + connect \$1435 $and$libresoc.v:42270$1673_Y + connect \$1438 $ternary$libresoc.v:42271$1674_Y + connect \$1440 $or$libresoc.v:42272$1675_Y + connect \$1442 $or$libresoc.v:42273$1676_Y + connect \$1445 $or$libresoc.v:42274$1677_Y + connect \$1447 $or$libresoc.v:42275$1678_Y + connect \$1444 $pos$libresoc.v:42276$1680_Y + connect \$1450 $and$libresoc.v:42277$1681_Y + connect \$1452 $and$libresoc.v:42278$1682_Y + connect \$1454 $and$libresoc.v:42279$1683_Y + connect \$1456 $and$libresoc.v:42280$1684_Y + connect \$1458 $and$libresoc.v:42281$1685_Y + connect \$1461 $and$libresoc.v:42282$1686_Y + connect \$1464 $not$libresoc.v:42283$1687_Y + connect \$1466 $and$libresoc.v:42284$1688_Y + connect \$1469 $and$libresoc.v:42285$1689_Y + connect \$1472 $ternary$libresoc.v:42286$1690_Y + connect \$1474 $and$libresoc.v:42287$1691_Y + connect \$1477 $and$libresoc.v:42288$1692_Y + connect \$1480 $not$libresoc.v:42289$1693_Y + connect \$1482 $and$libresoc.v:42290$1694_Y + connect \$1485 $and$libresoc.v:42291$1695_Y + connect \$1488 $ternary$libresoc.v:42292$1696_Y + connect \$1490 $and$libresoc.v:42293$1697_Y + connect \$1493 $and$libresoc.v:42294$1698_Y + connect \$1496 $not$libresoc.v:42295$1699_Y + connect \$1498 $and$libresoc.v:42296$1700_Y + connect \$1501 $and$libresoc.v:42297$1701_Y + connect \$1504 $ternary$libresoc.v:42298$1702_Y + connect \$1506 $and$libresoc.v:42299$1703_Y + connect \$1509 $and$libresoc.v:42300$1704_Y + connect \$1512 $not$libresoc.v:42301$1705_Y + connect \$1514 $and$libresoc.v:42302$1706_Y + connect \$1517 $and$libresoc.v:42303$1707_Y + connect \$1520 $ternary$libresoc.v:42304$1708_Y + connect \$1522 $or$libresoc.v:42305$1709_Y + connect \$1524 $or$libresoc.v:42306$1710_Y + connect \$1526 $or$libresoc.v:42307$1711_Y + connect \$1528 $or$libresoc.v:42308$1712_Y + connect \$1530 $or$libresoc.v:42309$1713_Y + connect \$1532 $or$libresoc.v:42310$1714_Y + connect \$1534 $and$libresoc.v:42311$1715_Y + connect \$1536 $and$libresoc.v:42312$1716_Y + connect \$1538 $and$libresoc.v:42313$1717_Y + connect \$1540 $and$libresoc.v:42314$1718_Y + connect \$1542 $and$libresoc.v:42315$1719_Y + connect \$1545 $and$libresoc.v:42316$1720_Y + connect \$1548 $not$libresoc.v:42317$1721_Y + connect \$1550 $and$libresoc.v:42318$1722_Y + connect \$1553 $and$libresoc.v:42319$1723_Y + connect \$1556 $ternary$libresoc.v:42320$1724_Y + connect \$1558 $and$libresoc.v:42321$1725_Y + connect \$1561 $and$libresoc.v:42322$1726_Y + connect \$1564 $not$libresoc.v:42323$1727_Y + connect \$1566 $and$libresoc.v:42324$1728_Y + connect \$1569 $and$libresoc.v:42325$1729_Y + connect \$1572 $ternary$libresoc.v:42326$1730_Y + connect \$1574 $and$libresoc.v:42327$1731_Y + connect \$1577 $and$libresoc.v:42328$1732_Y + connect \$1580 $not$libresoc.v:42329$1733_Y + connect \$1582 $and$libresoc.v:42330$1734_Y + connect \$1585 $and$libresoc.v:42331$1735_Y + connect \$1588 $ternary$libresoc.v:42332$1736_Y + connect \$1590 $and$libresoc.v:42333$1737_Y + connect \$1593 $and$libresoc.v:42334$1738_Y + connect \$1596 $not$libresoc.v:42335$1739_Y + connect \$1598 $and$libresoc.v:42336$1740_Y + connect \$1601 $and$libresoc.v:42337$1741_Y + connect \$1604 $ternary$libresoc.v:42338$1742_Y + connect \$1607 $or$libresoc.v:42339$1743_Y + connect \$1609 $or$libresoc.v:42340$1744_Y + connect \$1611 $or$libresoc.v:42341$1745_Y + connect \$1606 $pos$libresoc.v:42342$1747_Y + connect \$1615 $or$libresoc.v:42343$1748_Y + connect \$1617 $or$libresoc.v:42344$1749_Y + connect \$1619 $or$libresoc.v:42345$1750_Y + connect \$1614 $pos$libresoc.v:42346$1752_Y + connect \$1622 $and$libresoc.v:42347$1753_Y + connect \$1624 $and$libresoc.v:42348$1754_Y + connect \$1626 $and$libresoc.v:42349$1755_Y + connect \$1628 $and$libresoc.v:42350$1756_Y + connect \$1630 $and$libresoc.v:42351$1757_Y + connect \$1632 $and$libresoc.v:42352$1758_Y + connect \$1635 $and$libresoc.v:42353$1759_Y + connect \$1639 $not$libresoc.v:42354$1760_Y + connect \$1641 $and$libresoc.v:42355$1761_Y + connect \$1646 $and$libresoc.v:42356$1762_Y + connect \$1649 $ternary$libresoc.v:42357$1763_Y + connect \$1651 $and$libresoc.v:42358$1764_Y + connect \$1654 $and$libresoc.v:42359$1765_Y + connect \$1657 $not$libresoc.v:42360$1766_Y + connect \$1659 $and$libresoc.v:42361$1767_Y + connect \$1662 $and$libresoc.v:42362$1768_Y + connect \$1665 $ternary$libresoc.v:42363$1769_Y + connect \$1667 $and$libresoc.v:42364$1770_Y + connect \$1670 $and$libresoc.v:42365$1771_Y + connect \$1673 $not$libresoc.v:42366$1772_Y + connect \$1675 $and$libresoc.v:42367$1773_Y + connect \$1678 $and$libresoc.v:42368$1774_Y + connect \$1681 $ternary$libresoc.v:42369$1775_Y + connect \$1683 $and$libresoc.v:42370$1776_Y + connect \$1686 $and$libresoc.v:42371$1777_Y + connect \$1689 $not$libresoc.v:42372$1778_Y + connect \$1691 $and$libresoc.v:42373$1779_Y + connect \$1694 $and$libresoc.v:42374$1780_Y + connect \$1697 $ternary$libresoc.v:42375$1781_Y + connect \$1699 $and$libresoc.v:42376$1782_Y + connect \$1702 $and$libresoc.v:42377$1783_Y + connect \$1705 $not$libresoc.v:42378$1784_Y + connect \$1707 $and$libresoc.v:42379$1785_Y + connect \$1710 $and$libresoc.v:42380$1786_Y + connect \$1713 $ternary$libresoc.v:42381$1787_Y + connect \$1715 $or$libresoc.v:42382$1788_Y + connect \$1717 $or$libresoc.v:42383$1789_Y + connect \$1719 $or$libresoc.v:42384$1790_Y + connect \$1721 $or$libresoc.v:42385$1791_Y + connect \$1723 $or$libresoc.v:42386$1792_Y + connect \$1725 $or$libresoc.v:42387$1793_Y + connect \$1727 $or$libresoc.v:42388$1794_Y + connect \$1729 $or$libresoc.v:42389$1795_Y + connect \$1731 $or$libresoc.v:42390$1796_Y + connect \$1733 $or$libresoc.v:42391$1797_Y + connect \$1735 $or$libresoc.v:42392$1798_Y + connect \$1737 $or$libresoc.v:42393$1799_Y + connect \$1739 $and$libresoc.v:42394$1800_Y + connect \$1741 $and$libresoc.v:42395$1801_Y + connect \$1743 $and$libresoc.v:42396$1802_Y + connect \$1746 $and$libresoc.v:42397$1803_Y + connect \$1749 $not$libresoc.v:42398$1804_Y + connect \$1751 $and$libresoc.v:42399$1805_Y + connect \$1754 $and$libresoc.v:42400$1806_Y + connect \$1757 $ternary$libresoc.v:42401$1807_Y + connect \$1759 $and$libresoc.v:42402$1808_Y + connect \$1762 $and$libresoc.v:42403$1809_Y + connect \$1765 $not$libresoc.v:42404$1810_Y + connect \$1767 $and$libresoc.v:42405$1811_Y + connect \$1770 $and$libresoc.v:42406$1812_Y + connect \$1773 $ternary$libresoc.v:42407$1813_Y + connect \$1775 $or$libresoc.v:42408$1814_Y + connect \$1778 $or$libresoc.v:42409$1815_Y + connect \$1777 $pos$libresoc.v:42410$1817_Y + connect \$1781 $and$libresoc.v:42411$1818_Y + connect \$1783 $and$libresoc.v:42412$1819_Y + connect \$1786 $and$libresoc.v:42413$1820_Y + connect \$1789 $not$libresoc.v:42414$1821_Y + connect \$1791 $and$libresoc.v:42415$1822_Y + connect \$1794 $and$libresoc.v:42416$1823_Y + connect \$1797 $ternary$libresoc.v:42417$1824_Y + connect \$1799 $pos$libresoc.v:42418$1826_Y + connect \$1801 $and$libresoc.v:42419$1827_Y + connect \$1803 $and$libresoc.v:42420$1828_Y + connect \$1806 $and$libresoc.v:42421$1829_Y + connect \$1809 $not$libresoc.v:42422$1830_Y + connect \$1811 $and$libresoc.v:42423$1831_Y + connect \$1814 $and$libresoc.v:42424$1832_Y + connect \$1817 $ternary$libresoc.v:42425$1833_Y + connect \$182 $and$libresoc.v:42426$1834_Y + connect \$181 $reduce_or$libresoc.v:42427$1835_Y + connect \$186 $and$libresoc.v:42428$1836_Y + connect \$185 $reduce_or$libresoc.v:42429$1837_Y + connect \$190 $and$libresoc.v:42430$1838_Y + connect \$189 $reduce_or$libresoc.v:42431$1839_Y + connect \$194 $and$libresoc.v:42432$1840_Y + connect \$193 $reduce_or$libresoc.v:42433$1841_Y + connect \$198 $and$libresoc.v:42434$1842_Y + connect \$197 $reduce_or$libresoc.v:42435$1843_Y + connect \$202 $and$libresoc.v:42436$1844_Y + connect \$201 $reduce_or$libresoc.v:42437$1845_Y + connect \$206 $and$libresoc.v:42438$1846_Y + connect \$205 $reduce_or$libresoc.v:42439$1847_Y + connect \$210 $and$libresoc.v:42440$1848_Y + connect \$209 $reduce_or$libresoc.v:42441$1849_Y + connect \$214 $and$libresoc.v:42442$1850_Y + connect \$213 $reduce_or$libresoc.v:42443$1851_Y + connect \$218 $and$libresoc.v:42444$1852_Y + connect \$217 $reduce_or$libresoc.v:42445$1853_Y + connect \$221 $ne$libresoc.v:42446$1854_Y + connect \$224 $sub$libresoc.v:42447$1855_Y + connect \$226 $ne$libresoc.v:42448$1856_Y + connect \$229 $and$libresoc.v:42449$1857_Y + connect \$231 $and$libresoc.v:42450$1858_Y + connect \$233 $eq$libresoc.v:42451$1859_Y + connect \$235 $or$libresoc.v:42452$1860_Y + connect \$237 $and$libresoc.v:42453$1861_Y + connect \$239 $or$libresoc.v:42454$1862_Y + connect \$241 $eq$libresoc.v:42455$1863_Y + connect \$243 $and$libresoc.v:42456$1864_Y + connect \$245 $eq$libresoc.v:42457$1865_Y + connect \$247 $or$libresoc.v:42458$1866_Y + connect \$228 $not$libresoc.v:42459$1867_Y + connect \$250 $not$libresoc.v:42460$1868_Y + connect \$252 $not$libresoc.v:42461$1869_Y + connect \$254 $not$libresoc.v:42462$1870_Y + connect \$257 $and$libresoc.v:42463$1871_Y + connect \$259 $and$libresoc.v:42464$1872_Y + connect \$261 $eq$libresoc.v:42465$1873_Y + connect \$263 $or$libresoc.v:42466$1874_Y + connect \$265 $and$libresoc.v:42467$1875_Y + connect \$267 $or$libresoc.v:42468$1876_Y + connect \$256 $not$libresoc.v:42469$1877_Y + connect \$271 $and$libresoc.v:42470$1878_Y + connect \$273 $and$libresoc.v:42471$1879_Y + connect \$275 $eq$libresoc.v:42472$1880_Y + connect \$277 $or$libresoc.v:42473$1881_Y + connect \$279 $and$libresoc.v:42474$1882_Y + connect \$281 $or$libresoc.v:42475$1883_Y + connect \$283 $and$libresoc.v:42476$1884_Y + connect \$285 $and$libresoc.v:42477$1885_Y + connect \$287 $eq$libresoc.v:42478$1886_Y + connect \$289 $or$libresoc.v:42479$1887_Y + connect \$291 $eq$libresoc.v:42480$1888_Y + connect \$293 $and$libresoc.v:42481$1889_Y + connect \$295 $eq$libresoc.v:42482$1890_Y + connect \$297 $or$libresoc.v:42483$1891_Y + connect \$270 $not$libresoc.v:42484$1892_Y + connect \$301 $and$libresoc.v:42485$1893_Y + connect \$303 $and$libresoc.v:42486$1894_Y + connect \$305 $eq$libresoc.v:42487$1895_Y + connect \$307 $or$libresoc.v:42488$1896_Y + connect \$309 $and$libresoc.v:42489$1897_Y + connect \$311 $or$libresoc.v:42490$1898_Y + connect \$300 $not$libresoc.v:42491$1899_Y + connect \$315 $and$libresoc.v:42492$1900_Y + connect \$317 $and$libresoc.v:42493$1901_Y + connect \$319 $eq$libresoc.v:42494$1902_Y + connect \$321 $or$libresoc.v:42495$1903_Y + connect \$323 $and$libresoc.v:42496$1904_Y + connect \$325 $or$libresoc.v:42497$1905_Y + connect \$314 $not$libresoc.v:42498$1906_Y + connect \$329 $and$libresoc.v:42499$1907_Y + connect \$331 $and$libresoc.v:42500$1908_Y + connect \$333 $eq$libresoc.v:42501$1909_Y + connect \$335 $or$libresoc.v:42502$1910_Y + connect \$337 $and$libresoc.v:42503$1911_Y + connect \$339 $or$libresoc.v:42504$1912_Y + connect \$341 $eq$libresoc.v:42505$1913_Y + connect \$343 $and$libresoc.v:42506$1914_Y + connect \$345 $eq$libresoc.v:42507$1915_Y + connect \$347 $or$libresoc.v:42508$1916_Y + connect \$328 $not$libresoc.v:42509$1917_Y + connect \$350 $not$libresoc.v:42510$1918_Y + connect \$352 $and$libresoc.v:42511$1919_Y + connect \$354 $and$libresoc.v:42512$1920_Y + connect \$356 $not$libresoc.v:42513$1921_Y + connect \$358 $and$libresoc.v:42514$1922_Y + connect \$360 $and$libresoc.v:42515$1923_Y + connect \$362 $ternary$libresoc.v:42516$1924_Y + connect \$364 $and$libresoc.v:42517$1925_Y + connect \$366 $and$libresoc.v:42518$1926_Y + connect \$368 $not$libresoc.v:42519$1927_Y + connect \$370 $and$libresoc.v:42520$1928_Y + connect \$372 $and$libresoc.v:42521$1929_Y + connect \$374 $ternary$libresoc.v:42522$1930_Y + connect \$376 $and$libresoc.v:42523$1931_Y + connect \$378 $and$libresoc.v:42524$1932_Y + connect \$380 $not$libresoc.v:42525$1933_Y + connect \$382 $and$libresoc.v:42526$1934_Y + connect \$384 $and$libresoc.v:42527$1935_Y + connect \$386 $ternary$libresoc.v:42528$1936_Y + connect \$388 $and$libresoc.v:42529$1937_Y + connect \$390 $and$libresoc.v:42530$1938_Y + connect \$392 $not$libresoc.v:42531$1939_Y + connect \$394 $and$libresoc.v:42532$1940_Y + connect \$396 $and$libresoc.v:42533$1941_Y + connect \$398 $ternary$libresoc.v:42534$1942_Y + connect \$400 $and$libresoc.v:42535$1943_Y + connect \$402 $and$libresoc.v:42536$1944_Y + connect \$404 $not$libresoc.v:42537$1945_Y + connect \$406 $and$libresoc.v:42538$1946_Y + connect \$408 $and$libresoc.v:42539$1947_Y + connect \$410 $ternary$libresoc.v:42540$1948_Y + connect \$412 $and$libresoc.v:42541$1949_Y + connect \$414 $and$libresoc.v:42542$1950_Y + connect \$416 $not$libresoc.v:42543$1951_Y + connect \$418 $and$libresoc.v:42544$1952_Y + connect \$420 $and$libresoc.v:42545$1953_Y + connect \$422 $ternary$libresoc.v:42546$1954_Y + connect \$424 $and$libresoc.v:42547$1955_Y + connect \$426 $and$libresoc.v:42548$1956_Y + connect \$428 $not$libresoc.v:42549$1957_Y + connect \$430 $and$libresoc.v:42550$1958_Y + connect \$432 $and$libresoc.v:42551$1959_Y + connect \$434 $ternary$libresoc.v:42552$1960_Y + connect \$436 $and$libresoc.v:42553$1961_Y + connect \$438 $and$libresoc.v:42554$1962_Y + connect \$440 $not$libresoc.v:42555$1963_Y + connect \$442 $and$libresoc.v:42556$1964_Y + connect \$444 $and$libresoc.v:42557$1965_Y + connect \$446 $ternary$libresoc.v:42558$1966_Y + connect \$448 $and$libresoc.v:42559$1967_Y + connect \$450 $and$libresoc.v:42560$1968_Y + connect \$452 $not$libresoc.v:42561$1969_Y + connect \$454 $and$libresoc.v:42562$1970_Y + connect \$456 $and$libresoc.v:42563$1971_Y + connect \$458 $ternary$libresoc.v:42564$1972_Y + connect \$461 $or$libresoc.v:42565$1973_Y + connect \$463 $or$libresoc.v:42566$1974_Y + connect \$465 $or$libresoc.v:42567$1975_Y + connect \$467 $or$libresoc.v:42568$1976_Y + connect \$469 $or$libresoc.v:42569$1977_Y + connect \$471 $or$libresoc.v:42570$1978_Y + connect \$473 $or$libresoc.v:42571$1979_Y + connect \$475 $or$libresoc.v:42572$1980_Y + connect \$477 $reduce_or$libresoc.v:42573$1981_Y + connect \$479 $and$libresoc.v:42574$1982_Y + connect \$481 $and$libresoc.v:42575$1983_Y + connect \$483 $not$libresoc.v:42576$1984_Y + connect \$485 $and$libresoc.v:42577$1985_Y + connect \$487 $and$libresoc.v:42578$1986_Y + connect \$489 $ternary$libresoc.v:42579$1987_Y + connect \$491 $and$libresoc.v:42580$1988_Y + connect \$493 $and$libresoc.v:42581$1989_Y + connect \$495 $not$libresoc.v:42582$1990_Y + connect \$497 $and$libresoc.v:42583$1991_Y + connect \$499 $and$libresoc.v:42584$1992_Y + connect \$501 $ternary$libresoc.v:42585$1993_Y + connect \$503 $and$libresoc.v:42586$1994_Y + connect \$505 $and$libresoc.v:42587$1995_Y + connect \$507 $not$libresoc.v:42588$1996_Y + connect \$509 $and$libresoc.v:42589$1997_Y + connect \$511 $and$libresoc.v:42590$1998_Y + connect \$513 $ternary$libresoc.v:42591$1999_Y + connect \$515 $and$libresoc.v:42592$2000_Y + connect \$517 $and$libresoc.v:42593$2001_Y + connect \$519 $not$libresoc.v:42594$2002_Y + connect \$521 $and$libresoc.v:42595$2003_Y + connect \$523 $and$libresoc.v:42596$2004_Y + connect \$525 $ternary$libresoc.v:42597$2005_Y + connect \$527 $and$libresoc.v:42598$2006_Y + connect \$529 $and$libresoc.v:42599$2007_Y + connect \$531 $not$libresoc.v:42600$2008_Y + connect \$533 $and$libresoc.v:42601$2009_Y + connect \$535 $and$libresoc.v:42602$2010_Y + connect \$537 $ternary$libresoc.v:42603$2011_Y + connect \$539 $and$libresoc.v:42604$2012_Y + connect \$541 $and$libresoc.v:42605$2013_Y + connect \$543 $not$libresoc.v:42606$2014_Y + connect \$545 $and$libresoc.v:42607$2015_Y + connect \$547 $and$libresoc.v:42608$2016_Y + connect \$549 $ternary$libresoc.v:42609$2017_Y + connect \$551 $and$libresoc.v:42610$2018_Y + connect \$553 $and$libresoc.v:42611$2019_Y + connect \$555 $not$libresoc.v:42612$2020_Y + connect \$557 $and$libresoc.v:42613$2021_Y + connect \$559 $and$libresoc.v:42614$2022_Y + connect \$561 $ternary$libresoc.v:42615$2023_Y + connect \$563 $and$libresoc.v:42616$2024_Y + connect \$565 $and$libresoc.v:42617$2025_Y + connect \$567 $not$libresoc.v:42618$2026_Y + connect \$569 $and$libresoc.v:42619$2027_Y + connect \$571 $and$libresoc.v:42620$2028_Y + connect \$573 $ternary$libresoc.v:42621$2029_Y + connect \$576 $or$libresoc.v:42622$2030_Y + connect \$578 $or$libresoc.v:42623$2031_Y + connect \$580 $or$libresoc.v:42624$2032_Y + connect \$582 $or$libresoc.v:42625$2033_Y + connect \$584 $or$libresoc.v:42626$2034_Y + connect \$586 $or$libresoc.v:42627$2035_Y + connect \$588 $or$libresoc.v:42628$2036_Y + connect \$590 $reduce_or$libresoc.v:42629$2037_Y + connect \$592 $and$libresoc.v:42630$2038_Y + connect \$594 $and$libresoc.v:42631$2039_Y + connect \$596 $not$libresoc.v:42632$2040_Y + connect \$598 $and$libresoc.v:42633$2041_Y + connect \$600 $and$libresoc.v:42634$2042_Y + connect \$602 $ternary$libresoc.v:42635$2043_Y + connect \$604 $and$libresoc.v:42636$2044_Y + connect \$606 $and$libresoc.v:42637$2045_Y + connect \$608 $not$libresoc.v:42638$2046_Y + connect \$610 $and$libresoc.v:42639$2047_Y + connect \$612 $and$libresoc.v:42640$2048_Y + connect \$614 $ternary$libresoc.v:42641$2049_Y + connect \$617 $or$libresoc.v:42642$2050_Y + connect \$619 $reduce_or$libresoc.v:42643$2051_Y + connect \$621 $and$libresoc.v:42644$2052_Y + connect \$623 $and$libresoc.v:42645$2053_Y + connect \$625 $eq$libresoc.v:42646$2054_Y + connect \$627 $or$libresoc.v:42647$2055_Y + connect \$629 $and$libresoc.v:42648$2056_Y + connect \$631 $or$libresoc.v:42649$2057_Y + connect \$633 $and$libresoc.v:42650$2058_Y + connect \$635 $and$libresoc.v:42651$2059_Y + connect \$637 $not$libresoc.v:42652$2060_Y + connect \$639 $and$libresoc.v:42653$2061_Y + connect \$641 $and$libresoc.v:42654$2062_Y + connect \$643 $ternary$libresoc.v:42655$2063_Y + connect \$645 $and$libresoc.v:42656$2064_Y + connect \$647 $and$libresoc.v:42657$2065_Y + connect \$649 $not$libresoc.v:42658$2066_Y + connect \$651 $and$libresoc.v:42659$2067_Y + connect \$653 $and$libresoc.v:42660$2068_Y + connect \$655 $ternary$libresoc.v:42661$2069_Y + connect \$657 $and$libresoc.v:42662$2070_Y + connect \$659 $and$libresoc.v:42663$2071_Y + connect \$661 $not$libresoc.v:42664$2072_Y + connect \$663 $and$libresoc.v:42665$2073_Y + connect \$665 $and$libresoc.v:42666$2074_Y + connect \$667 $ternary$libresoc.v:42667$2075_Y + connect \$669 $and$libresoc.v:42668$2076_Y + connect \$671 $and$libresoc.v:42669$2077_Y + connect \$673 $not$libresoc.v:42670$2078_Y + connect \$675 $and$libresoc.v:42671$2079_Y + connect \$677 $and$libresoc.v:42672$2080_Y + connect \$679 $ternary$libresoc.v:42673$2081_Y + connect \$681 $and$libresoc.v:42674$2082_Y + connect \$683 $and$libresoc.v:42675$2083_Y + connect \$685 $not$libresoc.v:42676$2084_Y + connect \$687 $and$libresoc.v:42677$2085_Y + connect \$689 $and$libresoc.v:42678$2086_Y + connect \$691 $ternary$libresoc.v:42679$2087_Y + connect \$693 $and$libresoc.v:42680$2088_Y + connect \$695 $and$libresoc.v:42681$2089_Y + connect \$697 $not$libresoc.v:42682$2090_Y + connect \$699 $and$libresoc.v:42683$2091_Y + connect \$701 $and$libresoc.v:42684$2092_Y + connect \$703 $ternary$libresoc.v:42685$2093_Y + connect \$706 $or$libresoc.v:42686$2094_Y + connect \$708 $or$libresoc.v:42687$2095_Y + connect \$710 $or$libresoc.v:42688$2096_Y + connect \$712 $or$libresoc.v:42689$2097_Y + connect \$714 $or$libresoc.v:42690$2098_Y + connect \$705 $pos$libresoc.v:42691$2100_Y + connect \$717 $eq$libresoc.v:42692$2101_Y + connect \$719 $and$libresoc.v:42693$2102_Y + connect \$721 $eq$libresoc.v:42694$2103_Y + connect \$723 $or$libresoc.v:42695$2104_Y + connect \$725 $and$libresoc.v:42696$2105_Y + connect \$727 $and$libresoc.v:42697$2106_Y + connect \$729 $not$libresoc.v:42698$2107_Y + connect \$731 $and$libresoc.v:42699$2108_Y + connect \$733 $and$libresoc.v:42700$2109_Y + connect \$735 $ternary$libresoc.v:42701$2110_Y + connect \$737 $and$libresoc.v:42702$2111_Y + connect \$739 $and$libresoc.v:42703$2112_Y + connect \$741 $not$libresoc.v:42704$2113_Y + connect \$743 $and$libresoc.v:42705$2114_Y + connect \$745 $and$libresoc.v:42706$2115_Y + connect \$747 $ternary$libresoc.v:42707$2116_Y + connect \$749 $and$libresoc.v:42708$2117_Y + connect \$751 $and$libresoc.v:42709$2118_Y + connect \$753 $not$libresoc.v:42710$2119_Y + connect \$755 $and$libresoc.v:42711$2120_Y + connect \$757 $and$libresoc.v:42712$2121_Y + connect \$759 $ternary$libresoc.v:42713$2122_Y + connect \$762 $or$libresoc.v:42714$2123_Y + connect \$764 $or$libresoc.v:42715$2124_Y + connect \$761 $pos$libresoc.v:42716$2126_Y + connect \$767 $and$libresoc.v:42717$2127_Y + connect \$769 $and$libresoc.v:42718$2128_Y + connect \$771 $eq$libresoc.v:42719$2129_Y + connect \$773 $or$libresoc.v:42720$2130_Y + connect \$775 $and$libresoc.v:42721$2131_Y + connect \$777 $and$libresoc.v:42722$2132_Y + connect \$779 $not$libresoc.v:42723$2133_Y + connect \$781 $and$libresoc.v:42724$2134_Y + connect \$783 $and$libresoc.v:42725$2135_Y + connect \$785 $ternary$libresoc.v:42726$2136_Y + connect \$787 $and$libresoc.v:42727$2137_Y + connect \$789 $and$libresoc.v:42728$2138_Y + connect \$791 $not$libresoc.v:42729$2139_Y + connect \$793 $and$libresoc.v:42730$2140_Y + connect \$795 $and$libresoc.v:42731$2141_Y + connect \$797 $ternary$libresoc.v:42732$2142_Y + connect \$799 $and$libresoc.v:42733$2143_Y + connect \$801 $and$libresoc.v:42734$2144_Y + connect \$803 $not$libresoc.v:42735$2145_Y + connect \$805 $and$libresoc.v:42736$2146_Y + connect \$807 $and$libresoc.v:42737$2147_Y + connect \$809 $sub$libresoc.v:42738$2148_Y + connect \$811 $sshl$libresoc.v:42739$2149_Y + connect \$813 $ternary$libresoc.v:42740$2150_Y + connect \$815 $and$libresoc.v:42741$2151_Y + connect \$817 $and$libresoc.v:42742$2152_Y + connect \$819 $not$libresoc.v:42743$2153_Y + connect \$821 $and$libresoc.v:42744$2154_Y + connect \$823 $and$libresoc.v:42745$2155_Y + connect \$825 $sub$libresoc.v:42746$2156_Y + connect \$827 $sshl$libresoc.v:42747$2157_Y + connect \$829 $ternary$libresoc.v:42748$2158_Y + connect \$832 $or$libresoc.v:42749$2159_Y + connect \$834 $and$libresoc.v:42750$2160_Y + connect \$836 $and$libresoc.v:42751$2161_Y + connect \$838 $not$libresoc.v:42752$2162_Y + connect \$840 $and$libresoc.v:42753$2163_Y + connect \$842 $and$libresoc.v:42754$2164_Y + connect \$844 $sub$libresoc.v:42755$2165_Y + connect \$846 $sshl$libresoc.v:42756$2166_Y + connect \$848 $ternary$libresoc.v:42757$2167_Y + connect \$850 $and$libresoc.v:42758$2168_Y + connect \$852 $and$libresoc.v:42759$2169_Y + connect \$854 $not$libresoc.v:42760$2170_Y + connect \$856 $and$libresoc.v:42761$2171_Y + connect \$858 $and$libresoc.v:42762$2172_Y + connect \$860 $sub$libresoc.v:42763$2173_Y + connect \$862 $sshl$libresoc.v:42764$2174_Y + connect \$864 $ternary$libresoc.v:42765$2175_Y + connect \$866 $and$libresoc.v:42766$2176_Y + connect \$868 $and$libresoc.v:42767$2177_Y + connect \$870 $not$libresoc.v:42768$2178_Y + connect \$872 $and$libresoc.v:42769$2179_Y + connect \$874 $and$libresoc.v:42770$2180_Y + connect \$876 $ternary$libresoc.v:42771$2181_Y + connect \$878 $and$libresoc.v:42772$2182_Y + connect \$880 $and$libresoc.v:42773$2183_Y + connect \$882 $not$libresoc.v:42774$2184_Y + connect \$884 $and$libresoc.v:42775$2185_Y + connect \$886 $and$libresoc.v:42776$2186_Y + connect \$888 $ternary$libresoc.v:42777$2187_Y + connect \$890 $and$libresoc.v:42778$2188_Y + connect \$892 $and$libresoc.v:42779$2189_Y + connect \$894 $not$libresoc.v:42780$2190_Y + connect \$896 $and$libresoc.v:42781$2191_Y + connect \$898 $and$libresoc.v:42782$2192_Y + connect \$900 $ternary$libresoc.v:42783$2193_Y + connect \$902 $or$libresoc.v:42784$2194_Y + connect \$904 $or$libresoc.v:42785$2195_Y + connect \$906 $reduce_or$libresoc.v:42786$2196_Y + connect \$908 $and$libresoc.v:42787$2197_Y + connect \$910 $and$libresoc.v:42788$2198_Y + connect \$912 $not$libresoc.v:42789$2199_Y + connect \$914 $and$libresoc.v:42790$2200_Y + connect \$916 $and$libresoc.v:42791$2201_Y + connect \$918 $ternary$libresoc.v:42792$2202_Y + connect \$920 $and$libresoc.v:42793$2203_Y + connect \$922 $and$libresoc.v:42794$2204_Y + connect \$924 $not$libresoc.v:42795$2205_Y + connect \$926 $and$libresoc.v:42796$2206_Y + connect \$928 $and$libresoc.v:42797$2207_Y + connect \$930 $ternary$libresoc.v:42798$2208_Y + connect \$932 $or$libresoc.v:42799$2209_Y + connect \$934 $reduce_or$libresoc.v:42800$2210_Y + connect \$936 $and$libresoc.v:42801$2211_Y + connect \$938 $and$libresoc.v:42802$2212_Y + connect \$940 $not$libresoc.v:42803$2213_Y + connect \$942 $and$libresoc.v:42804$2214_Y + connect \$944 $and$libresoc.v:42805$2215_Y + connect \$946 $ternary$libresoc.v:42806$2216_Y + connect \$948 $reduce_or$libresoc.v:42807$2217_Y + connect \$950 $and$libresoc.v:42808$2218_Y + connect \$952 $and$libresoc.v:42809$2219_Y + connect \$954 $and$libresoc.v:42810$2220_Y + connect \$956 $and$libresoc.v:42811$2221_Y + connect \$958 $and$libresoc.v:42812$2222_Y + connect \$960 $and$libresoc.v:42813$2223_Y + connect \$962 $and$libresoc.v:42814$2224_Y + connect \$964 $and$libresoc.v:42815$2225_Y + connect \$966 $and$libresoc.v:42816$2226_Y + connect \$968 $and$libresoc.v:42817$2227_Y + connect \$970 $and$libresoc.v:42818$2228_Y + connect \$972 $and$libresoc.v:42819$2229_Y + connect \$974 $not$libresoc.v:42820$2230_Y + connect \$976 $and$libresoc.v:42821$2231_Y + connect \$982 $and$libresoc.v:42822$2232_Y + connect \$984 $ternary$libresoc.v:42823$2233_Y + connect \$986 $and$libresoc.v:42824$2234_Y + connect \$989 $and$libresoc.v:42825$2235_Y + connect \$993 $not$libresoc.v:42826$2236_Y + connect \$995 $and$libresoc.v:42827$2237_Y + connect \$223 \$224 + connect \$460 \$475 + connect \$575 \$588 + connect \$616 \$617 + connect \$831 \$832 + connect \$1159 \$1176 + connect \$1178 \$1195 + connect \$1375 \$1384 connect \o_ok 1'0 connect \ea_ok 1'0 - connect \spr_spr1__wen \wp$1802 - connect \spr_spr1__addr$173 \addr_en$1805 [6:0] - connect \spr_spr1__data_i \fus_dest2_o$160 - connect \addr_en$1805 \$1806 - connect \wp$1802 \$1803 - connect \wr_pick_rise$1049 \$1800 - connect \wr_pick$1794 \$1795 - connect \wrpick_SPR_spr1_i \$1792 - connect \wrflag_spr0_spr1_1 \$1790 - connect \state_wen \$1788 - connect \state_data_i$172 \fus_dest5_o$159 - connect \addr_en$1785 \$1786 - connect \wp$1782 \$1783 - connect \wr_pick_rise$1009 \$1780 - connect \wr_pick$1774 \$1775 - connect \wrpick_STATE_msr_i \$1772 - connect \wrflag_trap0_msr_4 \$1770 - connect \state_nia_wen \$1766 - connect \state_data_i \$1764 - connect \addr_en$1761 \$1762 - connect \wp$1758 \$1759 - connect \wr_pick_rise$1008 \$1756 - connect \wr_pick$1750 \$1751 - connect \wrflag_trap0_nia_3 \$1748 - connect \addr_en$1745 \$1746 - connect \wp$1742 \$1743 - connect \wr_pick_rise$1633 \$1740 - connect \wr_pick$1734 \$1735 - connect \wrpick_STATE_nia_i [1] \$1732 - connect \wrpick_STATE_nia_i [0] \$1730 - connect \wrflag_branch0_nia_2 \$1728 - connect \fast_dest1__wen \$1726 - connect \fast_dest1__addr \$1718 - connect \fast_dest1__data_i \$1710 - connect \addr_en$1701 \$1702 - connect \wp$1698 \$1699 - connect \wr_pick_rise$1007 \$1696 - connect \wr_pick$1690 \$1691 - connect \wrflag_trap0_fast1_2 \$1688 - connect \addr_en$1685 \$1686 - connect \wp$1682 \$1683 - connect \wr_pick_rise$1632 \$1680 - connect \wr_pick$1674 \$1675 - connect \wrflag_branch0_fast1_1 \$1672 - connect \addr_en$1669 \$1670 - connect \wp$1666 \$1667 - connect \wr_pick_rise$1048 \$1664 - connect \wr_pick$1658 \$1659 - connect \wrflag_spr0_fast1_2 \$1656 - connect \addr_en$1653 \$1654 - connect \wp$1650 \$1651 - connect \wr_pick_rise$1006 \$1648 - connect \wr_pick$1642 \$1643 - connect \wrflag_trap0_fast1_1 \$1640 - connect \addr_en$1637 \$1638 - connect \wp$1634 \$1635 - connect \fus_cu_wr__go_i$147 [2] \wr_pick_rise$1633 - connect \fus_cu_wr__go_i$147 [1] \wr_pick_rise$1632 - connect \fus_cu_wr__go_i$147 [0] \wr_pick_rise$1627 - connect \wr_pick_rise$1627 \$1630 - connect \wr_pick$1623 \$1624 - connect \wrpick_FAST_fast1_i [4] \$1621 - connect \wrpick_FAST_fast1_i [3] \$1619 - connect \wrpick_FAST_fast1_i [2] \$1617 - connect \wrpick_FAST_fast1_i [1] \$1615 - connect \wrpick_FAST_fast1_i [0] \$1613 - connect \wrflag_branch0_fast1_0 \$1611 - connect \xer_wen$171 \$1603 - connect \xer_data_i$170 \$1595 - connect \addr_en$1592 \$1593 - connect \wp$1589 \$1590 - connect \wr_pick_rise$1089 \$1587 - connect \wr_pick$1581 \$1582 - connect \wrflag_mul0_xer_so_3 \$1579 - connect \addr_en$1576 \$1577 - connect \wp$1573 \$1574 - connect \wr_pick_rise$1069 \$1571 - connect \wr_pick$1565 \$1566 - connect \wrflag_div0_xer_so_3 \$1563 - connect \addr_en$1560 \$1561 - connect \wp$1557 \$1558 - connect \wr_pick_rise$1047 \$1555 - connect \wr_pick$1549 \$1550 - connect \wrflag_spr0_xer_so_3 \$1547 - connect \addr_en$1544 \$1545 - connect \wp$1541 \$1542 - connect \wr_pick_rise$971 \$1539 - connect \wr_pick$1533 \$1534 - connect \wrpick_XER_xer_so_i [3] \$1531 - connect \wrpick_XER_xer_so_i [2] \$1529 - connect \wrpick_XER_xer_so_i [1] \$1527 - connect \wrpick_XER_xer_so_i [0] \$1525 - connect \wrflag_alu0_xer_so_4 \$1523 - connect \xer_wen$169 \$1521 - connect \xer_data_i$168 \$1515 - connect \addr_en$1508 \$1509 - connect \wp$1505 \$1506 - connect \wr_pick_rise$1088 \$1503 - connect \wr_pick$1497 \$1498 - connect \wrflag_mul0_xer_ov_2 \$1495 - connect \addr_en$1492 \$1493 - connect \wp$1489 \$1490 - connect \wr_pick_rise$1068 \$1487 - connect \wr_pick$1481 \$1482 - connect \wrflag_div0_xer_ov_2 \$1479 - connect \addr_en$1476 \$1477 - connect \wp$1473 \$1474 - connect \wr_pick_rise$1046 \$1471 - connect \wr_pick$1465 \$1466 - connect \wrflag_spr0_xer_ov_4 \$1463 - connect \addr_en$1460 \$1461 - connect \wp$1457 \$1458 - connect \wr_pick_rise$970 \$1455 - connect \wr_pick$1449 \$1450 - connect \wrpick_XER_xer_ov_i [3] \$1447 - connect \wrpick_XER_xer_ov_i [2] \$1445 - connect \wrpick_XER_xer_ov_i [1] \$1443 - connect \wrpick_XER_xer_ov_i [0] \$1441 - connect \wrflag_alu0_xer_ov_3 \$1439 - connect \xer_wen \$1433 - connect \xer_data_i \$1431 - connect \addr_en$1426 \$1427 - connect \wp$1423 \$1424 - connect \wr_pick_rise$1108 \$1421 - connect \wr_pick$1415 \$1416 - connect \wrflag_shiftrot0_xer_ca_2 \$1413 - connect \addr_en$1410 \$1411 - connect \wp$1407 \$1408 - connect \wr_pick_rise$1045 \$1405 - connect \wr_pick$1399 \$1400 - connect \wrflag_spr0_xer_ca_5 \$1397 - connect \addr_en$1394 \$1395 - connect \wp$1391 \$1392 - connect \wr_pick_rise$969 \$1389 - connect \wr_pick$1383 \$1384 - connect \wrpick_XER_xer_ca_i [2] \$1381 - connect \wrpick_XER_xer_ca_i [1] \$1379 - connect \wrpick_XER_xer_ca_i [0] \$1377 - connect \wrflag_alu0_xer_ca_2 \$1375 - connect \cr_wen \$1373 [7:0] - connect \cr_data_i \$1362 - connect \addr_en$1347 \$1352 - connect \wp$1344 \$1345 - connect \wr_pick_rise$1107 \$1342 - connect \wr_pick$1336 \$1337 - connect \wrflag_shiftrot0_cr_a_1 \$1334 - connect \addr_en$1327 \$1332 - connect \wp$1324 \$1325 - connect \wr_pick_rise$1087 \$1322 - connect \wr_pick$1316 \$1317 - connect \wrflag_mul0_cr_a_1 \$1314 - connect \addr_en$1307 \$1312 - connect \wp$1304 \$1305 - connect \wr_pick_rise$1067 \$1302 - connect \wr_pick$1296 \$1297 - connect \wrflag_div0_cr_a_1 \$1294 - connect \addr_en$1287 \$1292 - connect \wp$1284 \$1285 - connect \wr_pick_rise$1027 \$1282 - connect \wr_pick$1276 \$1277 - connect \wrflag_logical0_cr_a_1 \$1274 - connect \addr_en$1267 \$1272 - connect \wp$1264 \$1265 - connect \wr_pick_rise$988 \$1262 - connect \wr_pick$1256 \$1257 - connect \wrflag_cr0_cr_a_2 \$1254 - connect \addr_en$1247 \$1252 - connect \wp$1244 \$1245 - connect \wr_pick_rise$968 \$1242 - connect \wr_pick$1236 \$1237 - connect \wrpick_CR_cr_a_i [5] \$1234 - connect \wrpick_CR_cr_a_i [4] \$1232 - connect \wrpick_CR_cr_a_i [3] \$1230 - connect \wrpick_CR_cr_a_i [2] \$1228 - connect \wrpick_CR_cr_a_i [1] \$1226 - connect \wrpick_CR_cr_a_i [0] \$1224 - connect \wrflag_alu0_cr_a_1 \$1222 - connect \cr_full_wr__wen \addr_en$1219 + connect \spr_spr1__wen \wp$1813 + connect \spr_spr1__addr$175 \addr_en$1816 [6:0] + connect \spr_spr1__data_i \fus_dest2_o$162 + connect \addr_en$1816 \$1817 + connect \wp$1813 \$1814 + connect \wr_pick_rise$1059 \$1811 + connect \wr_pick$1805 \$1806 + connect \wrpick_SPR_spr1_i \$1803 + connect \wrflag_spr0_spr1_1 \$1801 + connect \state_wen \$1799 + connect \state_data_i$174 \fus_dest5_o$161 + connect \addr_en$1796 \$1797 + connect \wp$1793 \$1794 + connect \wr_pick_rise$1019 \$1791 + connect \wr_pick$1785 \$1786 + connect \wrpick_STATE_msr_i \$1783 + connect \wrflag_trap0_msr_4 \$1781 + connect \state_nia_wen \$1777 + connect \state_data_i \$1775 + connect \addr_en$1772 \$1773 + connect \wp$1769 \$1770 + connect \wr_pick_rise$1018 \$1767 + connect \wr_pick$1761 \$1762 + connect \wrflag_trap0_nia_3 \$1759 + connect \addr_en$1756 \$1757 + connect \wp$1753 \$1754 + connect \wr_pick_rise$1644 \$1751 + connect \wr_pick$1745 \$1746 + connect \wrpick_STATE_nia_i [1] \$1743 + connect \wrpick_STATE_nia_i [0] \$1741 + connect \wrflag_branch0_nia_2 \$1739 + connect \fast_dest1__wen \$1737 + connect \fast_dest1__addr \$1729 + connect \fast_dest1__data_i \$1721 + connect \addr_en$1712 \$1713 + connect \wp$1709 \$1710 + connect \wr_pick_rise$1017 \$1707 + connect \wr_pick$1701 \$1702 + connect \wrflag_trap0_fast1_2 \$1699 + connect \addr_en$1696 \$1697 + connect \wp$1693 \$1694 + connect \wr_pick_rise$1643 \$1691 + connect \wr_pick$1685 \$1686 + connect \wrflag_branch0_fast1_1 \$1683 + connect \addr_en$1680 \$1681 + connect \wp$1677 \$1678 + connect \wr_pick_rise$1058 \$1675 + connect \wr_pick$1669 \$1670 + connect \wrflag_spr0_fast1_2 \$1667 + connect \addr_en$1664 \$1665 + connect \wp$1661 \$1662 + connect \wr_pick_rise$1016 \$1659 + connect \wr_pick$1653 \$1654 + connect \wrflag_trap0_fast1_1 \$1651 + connect \addr_en$1648 \$1649 + connect \wp$1645 \$1646 + connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1644 + connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1643 + connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1638 + connect \wr_pick_rise$1638 \$1641 + connect \wr_pick$1634 \$1635 + connect \wrpick_FAST_fast1_i [4] \$1632 + connect \wrpick_FAST_fast1_i [3] \$1630 + connect \wrpick_FAST_fast1_i [2] \$1628 + connect \wrpick_FAST_fast1_i [1] \$1626 + connect \wrpick_FAST_fast1_i [0] \$1624 + connect \wrflag_branch0_fast1_0 \$1622 + connect \xer_wen$173 \$1614 + connect \xer_data_i$172 \$1606 + connect \addr_en$1603 \$1604 + connect \wp$1600 \$1601 + connect \wr_pick_rise$1099 \$1598 + connect \wr_pick$1592 \$1593 + connect \wrflag_mul0_xer_so_3 \$1590 + connect \addr_en$1587 \$1588 + connect \wp$1584 \$1585 + connect \wr_pick_rise$1079 \$1582 + connect \wr_pick$1576 \$1577 + connect \wrflag_div0_xer_so_3 \$1574 + connect \addr_en$1571 \$1572 + connect \wp$1568 \$1569 + connect \wr_pick_rise$1057 \$1566 + connect \wr_pick$1560 \$1561 + connect \wrflag_spr0_xer_so_3 \$1558 + connect \addr_en$1555 \$1556 + connect \wp$1552 \$1553 + connect \wr_pick_rise$981 \$1550 + connect \wr_pick$1544 \$1545 + connect \wrpick_XER_xer_so_i [3] \$1542 + connect \wrpick_XER_xer_so_i [2] \$1540 + connect \wrpick_XER_xer_so_i [1] \$1538 + connect \wrpick_XER_xer_so_i [0] \$1536 + connect \wrflag_alu0_xer_so_4 \$1534 + connect \xer_wen$171 \$1532 + connect \xer_data_i$170 \$1526 + connect \addr_en$1519 \$1520 + connect \wp$1516 \$1517 + connect \wr_pick_rise$1098 \$1514 + connect \wr_pick$1508 \$1509 + connect \wrflag_mul0_xer_ov_2 \$1506 + connect \addr_en$1503 \$1504 + connect \wp$1500 \$1501 + connect \wr_pick_rise$1078 \$1498 + connect \wr_pick$1492 \$1493 + connect \wrflag_div0_xer_ov_2 \$1490 + connect \addr_en$1487 \$1488 + connect \wp$1484 \$1485 + connect \wr_pick_rise$1056 \$1482 + connect \wr_pick$1476 \$1477 + connect \wrflag_spr0_xer_ov_4 \$1474 + connect \addr_en$1471 \$1472 + connect \wp$1468 \$1469 + connect \wr_pick_rise$980 \$1466 + connect \wr_pick$1460 \$1461 + connect \wrpick_XER_xer_ov_i [3] \$1458 + connect \wrpick_XER_xer_ov_i [2] \$1456 + connect \wrpick_XER_xer_ov_i [1] \$1454 + connect \wrpick_XER_xer_ov_i [0] \$1452 + connect \wrflag_alu0_xer_ov_3 \$1450 + connect \xer_wen \$1444 + connect \xer_data_i \$1442 + connect \addr_en$1437 \$1438 + connect \wp$1434 \$1435 + connect \wr_pick_rise$1118 \$1432 + connect \wr_pick$1426 \$1427 + connect \wrflag_shiftrot0_xer_ca_2 \$1424 + connect \addr_en$1421 \$1422 + connect \wp$1418 \$1419 + connect \wr_pick_rise$1055 \$1416 + connect \wr_pick$1410 \$1411 + connect \wrflag_spr0_xer_ca_5 \$1408 + connect \addr_en$1405 \$1406 + connect \wp$1402 \$1403 + connect \wr_pick_rise$979 \$1400 + connect \wr_pick$1394 \$1395 + connect \wrpick_XER_xer_ca_i [2] \$1392 + connect \wrpick_XER_xer_ca_i [1] \$1390 + connect \wrpick_XER_xer_ca_i [0] \$1388 + connect \wrflag_alu0_xer_ca_2 \$1386 + connect \cr_wen \$1384 [7:0] + connect \cr_data_i \$1373 + connect \addr_en$1358 \$1363 + connect \wp$1355 \$1356 + connect \wr_pick_rise$1117 \$1353 + connect \wr_pick$1347 \$1348 + connect \wrflag_shiftrot0_cr_a_1 \$1345 + connect \addr_en$1338 \$1343 + connect \wp$1335 \$1336 + connect \wr_pick_rise$1097 \$1333 + connect \wr_pick$1327 \$1328 + connect \wrflag_mul0_cr_a_1 \$1325 + connect \addr_en$1318 \$1323 + connect \wp$1315 \$1316 + connect \wr_pick_rise$1077 \$1313 + connect \wr_pick$1307 \$1308 + connect \wrflag_div0_cr_a_1 \$1305 + connect \addr_en$1298 \$1303 + connect \wp$1295 \$1296 + connect \wr_pick_rise$1037 \$1293 + connect \wr_pick$1287 \$1288 + connect \wrflag_logical0_cr_a_1 \$1285 + connect \addr_en$1278 \$1283 + connect \wp$1275 \$1276 + connect \wr_pick_rise$998 \$1273 + connect \wr_pick$1267 \$1268 + connect \wrflag_cr0_cr_a_2 \$1265 + connect \addr_en$1258 \$1263 + connect \wp$1255 \$1256 + connect \wr_pick_rise$978 \$1253 + connect \wr_pick$1247 \$1248 + connect \wrpick_CR_cr_a_i [5] \$1245 + connect \wrpick_CR_cr_a_i [4] \$1243 + connect \wrpick_CR_cr_a_i [3] \$1241 + connect \wrpick_CR_cr_a_i [2] \$1239 + connect \wrpick_CR_cr_a_i [1] \$1237 + connect \wrpick_CR_cr_a_i [0] \$1235 + connect \wrflag_alu0_cr_a_1 \$1233 + connect \cr_full_wr__wen \addr_en$1230 connect \cr_full_wr__data_i \fus_dest2_o - connect \addr_en$1219 \$1220 - connect \wp$1216 \$1217 - connect \wr_pick_rise$987 \$1214 - connect \wr_pick$1208 \$1209 - connect \wrpick_CR_full_cr_i \$1206 - connect \wrflag_cr0_full_cr_1 \$1204 - connect \int_dest1__wen \$1202 - connect \int_dest1__addr \$1184 - connect \int_dest1__data_i \$1166 [63:0] - connect \addr_en$1146 \$1147 - connect \wp$1143 \$1144 - connect \wr_pick_rise$1126 \$1141 - connect \wr_pick$1135 \$1136 - connect \wrflag_ldst0_o_1 \$1133 - connect \addr_en$1130 \$1131 - connect \wp$1127 \$1128 - connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1126 - connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1121 - connect \wr_pick_rise$1121 \$1124 - connect \wr_pick$1117 \$1118 - connect \wrflag_ldst0_o_0 \$1115 - connect \addr_en$1112 \$1113 - connect \wp$1109 \$1110 - connect \fus_cu_wr__go_i$110 [2] \wr_pick_rise$1108 - connect \fus_cu_wr__go_i$110 [1] \wr_pick_rise$1107 - connect \fus_cu_wr__go_i$110 [0] \wr_pick_rise$1102 - connect \wr_pick_rise$1102 \$1105 - connect \wr_pick$1098 \$1099 - connect \wrflag_shiftrot0_o_0 \$1096 - connect \addr_en$1093 \$1094 - connect \wp$1090 \$1091 - connect \fus_cu_wr__go_i$107 [3] \wr_pick_rise$1089 - connect \fus_cu_wr__go_i$107 [2] \wr_pick_rise$1088 - connect \fus_cu_wr__go_i$107 [1] \wr_pick_rise$1087 - connect \fus_cu_wr__go_i$107 [0] \wr_pick_rise$1082 - connect \wr_pick_rise$1082 \$1085 - connect \wr_pick$1078 \$1079 - connect \wrflag_mul0_o_0 \$1076 - connect \addr_en$1073 \$1074 - connect \wp$1070 \$1071 - connect \fus_cu_wr__go_i$104 [3] \wr_pick_rise$1069 - connect \fus_cu_wr__go_i$104 [2] \wr_pick_rise$1068 - connect \fus_cu_wr__go_i$104 [1] \wr_pick_rise$1067 - connect \fus_cu_wr__go_i$104 [0] \wr_pick_rise$1062 - connect \wr_pick_rise$1062 \$1065 - connect \wr_pick$1058 \$1059 - connect \wrflag_div0_o_0 \$1056 - connect \addr_en$1053 \$1054 - connect \wp$1050 \$1051 - connect \fus_cu_wr__go_i$101 [1] \wr_pick_rise$1049 - connect \fus_cu_wr__go_i$101 [2] \wr_pick_rise$1048 - connect \fus_cu_wr__go_i$101 [3] \wr_pick_rise$1047 - connect \fus_cu_wr__go_i$101 [4] \wr_pick_rise$1046 - connect \fus_cu_wr__go_i$101 [5] \wr_pick_rise$1045 - connect \fus_cu_wr__go_i$101 [0] \wr_pick_rise$1040 - connect \wr_pick_rise$1040 \$1043 - connect \wr_pick$1036 \$1037 - connect \wrflag_spr0_o_0 \$1034 - connect \addr_en$1031 \$1032 - connect \wp$1028 \$1029 - connect \fus_cu_wr__go_i$98 [1] \wr_pick_rise$1027 - connect \fus_cu_wr__go_i$98 [0] \wr_pick_rise$1022 - connect \wr_pick_rise$1022 \$1025 - connect \wr_pick$1018 \$1019 - connect \wrflag_logical0_o_0 \$1016 - connect \addr_en$1013 \$1014 - connect \wp$1010 \$1011 - connect \fus_cu_wr__go_i$95 [4] \wr_pick_rise$1009 - connect \fus_cu_wr__go_i$95 [3] \wr_pick_rise$1008 - connect \fus_cu_wr__go_i$95 [2] \wr_pick_rise$1007 - connect \fus_cu_wr__go_i$95 [1] \wr_pick_rise$1006 - connect \fus_cu_wr__go_i$95 [0] \wr_pick_rise$1001 - connect \wr_pick_rise$1001 \$1004 - connect \wr_pick$997 \$998 - connect \wrflag_trap0_o_0 \$995 - connect \addr_en$992 \$993 - connect \wp$989 \$990 - connect \fus_cu_wr__go_i$92 [2] \wr_pick_rise$988 - connect \fus_cu_wr__go_i$92 [1] \wr_pick_rise$987 - connect \fus_cu_wr__go_i$92 [0] \wr_pick_rise$982 - connect \wr_pick_rise$982 \$985 - connect \wr_pick$978 \$979 - connect \wrflag_cr0_o_0 \$976 - connect \addr_en \$974 - connect \wp \$972 - connect \fus_cu_wr__go_i [4] \wr_pick_rise$971 - connect \fus_cu_wr__go_i [3] \wr_pick_rise$970 - connect \fus_cu_wr__go_i [2] \wr_pick_rise$969 - connect \fus_cu_wr__go_i [1] \wr_pick_rise$968 + connect \addr_en$1230 \$1231 + connect \wp$1227 \$1228 + connect \wr_pick_rise$997 \$1225 + connect \wr_pick$1219 \$1220 + connect \wrpick_CR_full_cr_i \$1217 + connect \wrflag_cr0_full_cr_1 \$1215 + connect \int_dest1__wen \$1213 + connect \int_dest1__addr \$1195 [4:0] + connect \int_dest1__data_i \$1176 [63:0] + connect \addr_en$1156 \$1157 + connect \wp$1153 \$1154 + connect \wr_pick_rise$1136 \$1151 + connect \wr_pick$1145 \$1146 + connect \wrflag_ldst0_o_1 \$1143 + connect \addr_en$1140 \$1141 + connect \wp$1137 \$1138 + connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1136 + connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1131 + connect \wr_pick_rise$1131 \$1134 + connect \wr_pick$1127 \$1128 + connect \wrflag_ldst0_o_0 \$1125 + connect \addr_en$1122 \$1123 + connect \wp$1119 \$1120 + connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1118 + connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1117 + connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1112 + connect \wr_pick_rise$1112 \$1115 + connect \wr_pick$1108 \$1109 + connect \wrflag_shiftrot0_o_0 \$1106 + connect \addr_en$1103 \$1104 + connect \wp$1100 \$1101 + connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1099 + connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1098 + connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1097 + connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1092 + connect \wr_pick_rise$1092 \$1095 + connect \wr_pick$1088 \$1089 + connect \wrflag_mul0_o_0 \$1086 + connect \addr_en$1083 \$1084 + connect \wp$1080 \$1081 + connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1079 + connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1078 + connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1077 + connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1072 + connect \wr_pick_rise$1072 \$1075 + connect \wr_pick$1068 \$1069 + connect \wrflag_div0_o_0 \$1066 + connect \addr_en$1063 \$1064 + connect \wp$1060 \$1061 + connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1059 + connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1058 + connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1057 + connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1056 + connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1055 + connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1050 + connect \wr_pick_rise$1050 \$1053 + connect \wr_pick$1046 \$1047 + connect \wrflag_spr0_o_0 \$1044 + connect \addr_en$1041 \$1042 + connect \wp$1038 \$1039 + connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1037 + connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1032 + connect \wr_pick_rise$1032 \$1035 + connect \wr_pick$1028 \$1029 + connect \wrflag_logical0_o_0 \$1026 + connect \addr_en$1023 \$1024 + connect \wp$1020 \$1021 + connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1019 + connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1018 + connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1017 + connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1016 + connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1011 + connect \wr_pick_rise$1011 \$1014 + connect \wr_pick$1007 \$1008 + connect \wrflag_trap0_o_0 \$1005 + connect \addr_en$1002 \$1003 + connect \wp$999 \$1000 + connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$998 + connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$997 + connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$992 + connect \wr_pick_rise$992 \$995 + connect \wr_pick$988 \$989 + connect \wrflag_cr0_o_0 \$986 + connect \addr_en \$984 + connect \wp \$982 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$981 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$980 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$979 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$978 connect \fus_cu_wr__go_i [0] \wr_pick_rise - connect \wr_pick_rise \$966 - connect \wr_pick \$962 - connect \wrpick_INT_o_i [9] \$960 - connect \wrpick_INT_o_i [8] \$958 - connect \wrpick_INT_o_i [7] \$956 - connect \wrpick_INT_o_i [6] \$954 - connect \wrpick_INT_o_i [5] \$952 - connect \wrpick_INT_o_i [4] \$950 - connect \wrpick_INT_o_i [3] \$948 - connect \wrpick_INT_o_i [2] \$946 - connect \wrpick_INT_o_i [1] \$944 - connect \wrpick_INT_o_i [0] \$942 - connect \wrflag_alu0_o_0 \$940 - connect \spr_spr1__ren \$938 + connect \wr_pick_rise \$976 + connect \wr_pick \$972 + connect \wrpick_INT_o_i [9] \$970 + connect \wrpick_INT_o_i [8] \$968 + connect \wrpick_INT_o_i [7] \$966 + connect \wrpick_INT_o_i [6] \$964 + connect \wrpick_INT_o_i [5] \$962 + connect \wrpick_INT_o_i [4] \$960 + connect \wrpick_INT_o_i [3] \$958 + connect \wrpick_INT_o_i [2] \$956 + connect \wrpick_INT_o_i [1] \$954 + connect \wrpick_INT_o_i [0] \$952 + connect \wrflag_alu0_o_0 \$950 + connect \spr_spr1__ren \$948 connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] - connect \addr_en_SPR_spr1_spr0_0 \$936 - connect \rp_SPR_spr1_spr0_0 \$934 + connect \addr_en_SPR_spr1_spr0_0 \$946 + connect \rp_SPR_spr1_spr0_0 \$944 connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 - connect \pick_SPR_spr1_spr0_0 \$932 + connect \pick_SPR_spr1_spr0_0 \$942 connect \rdflag_SPR_spr1_0 \core_spr1_ok - connect \fast_src2__ren \$924 - connect \fast_src2__addr \$922 - connect \addr_en_FAST_fast2_trap0_1 \$920 - connect \rp_FAST_fast2_trap0_1 \$918 - connect \pick_FAST_fast2_trap0_1 \$916 - connect \addr_en_FAST_fast2_branch0_0 \$908 - connect \rp_FAST_fast2_branch0_0 \$906 + connect \fast_src2__ren \$934 + connect \fast_src2__addr \$932 + connect \addr_en_FAST_fast2_trap0_1 \$930 + connect \rp_FAST_fast2_trap0_1 \$928 + connect \pick_FAST_fast2_trap0_1 \$926 + connect \addr_en_FAST_fast2_branch0_0 \$918 + connect \rp_FAST_fast2_branch0_0 \$916 connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 - connect \pick_FAST_fast2_branch0_0 \$904 + connect \pick_FAST_fast2_branch0_0 \$914 connect \rdflag_FAST_fast2_0 \core_fast2_ok - connect \fast_src1__ren \$896 - connect \fast_src1__addr \$894 - connect \addr_en_FAST_fast1_spr0_2 \$890 - connect \rp_FAST_fast1_spr0_2 \$888 - connect \pick_FAST_fast1_spr0_2 \$886 - connect \addr_en_FAST_fast1_trap0_1 \$878 - connect \rp_FAST_fast1_trap0_1 \$876 - connect \pick_FAST_fast1_trap0_1 \$874 - connect \addr_en_FAST_fast1_branch0_0 \$866 - connect \rp_FAST_fast1_branch0_0 \$864 + connect \fast_src1__ren \$906 + connect \fast_src1__addr \$904 + connect \addr_en_FAST_fast1_spr0_2 \$900 + connect \rp_FAST_fast1_spr0_2 \$898 + connect \pick_FAST_fast1_spr0_2 \$896 + connect \addr_en_FAST_fast1_trap0_1 \$888 + connect \rp_FAST_fast1_trap0_1 \$886 + connect \pick_FAST_fast1_trap0_1 \$884 + connect \addr_en_FAST_fast1_branch0_0 \$876 + connect \rp_FAST_fast1_branch0_0 \$874 connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 - connect \pick_FAST_fast1_branch0_0 \$862 + connect \pick_FAST_fast1_branch0_0 \$872 connect \rdflag_FAST_fast1_0 \core_fast1_ok connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] - connect \addr_en_CR_cr_c_cr0_0 \$854 - connect \rp_CR_cr_c_cr0_0 \$848 + connect \addr_en_CR_cr_c_cr0_0 \$864 + connect \rp_CR_cr_c_cr0_0 \$858 connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 - connect \pick_CR_cr_c_cr0_0 \$846 + connect \pick_CR_cr_c_cr0_0 \$856 connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] - connect \addr_en_CR_cr_b_cr0_0 \$838 - connect \rp_CR_cr_b_cr0_0 \$832 + connect \addr_en_CR_cr_b_cr0_0 \$848 + connect \rp_CR_cr_b_cr0_0 \$842 connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 - connect \pick_CR_cr_b_cr0_0 \$830 + connect \pick_CR_cr_b_cr0_0 \$840 connect \rdflag_CR_cr_b_0 \core_cr_in2_ok - connect \cr_src1__ren \$822 [7:0] - connect \addr_en_CR_cr_a_branch0_1 \$819 - connect \rp_CR_cr_a_branch0_1 \$813 - connect \fus_cu_rd__go_i$80 [1] \dp_FAST_fast2_branch0_0 - connect \fus_cu_rd__go_i$80 [0] \dp_FAST_fast1_branch0_0 - connect \fus_cu_rd__go_i$80 [2] \dp_CR_cr_a_branch0_1 - connect \pick_CR_cr_a_branch0_1 \$811 - connect \addr_en_CR_cr_a_cr0_0 \$803 - connect \rp_CR_cr_a_cr0_0 \$797 + connect \cr_src1__ren \$832 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$829 + connect \rp_CR_cr_a_branch0_1 \$823 + connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast2_branch0_0 + connect \fus_cu_rd__go_i$82 [0] \dp_FAST_fast1_branch0_0 + connect \fus_cu_rd__go_i$82 [2] \dp_CR_cr_a_branch0_1 + connect \pick_CR_cr_a_branch0_1 \$821 + connect \addr_en_CR_cr_a_cr0_0 \$813 + connect \rp_CR_cr_a_cr0_0 \$807 connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 - connect \pick_CR_cr_a_cr0_0 \$795 + connect \pick_CR_cr_a_cr0_0 \$805 connect \rdflag_CR_cr_a_0 \core_cr_in1_ok connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 - connect \addr_en_CR_full_cr_cr0_0 \$787 - connect \rp_CR_full_cr_cr0_0 \$785 + connect \addr_en_CR_full_cr_cr0_0 \$797 + connect \rp_CR_full_cr_cr0_0 \$795 connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 - connect \pick_CR_full_cr_cr0_0 \$783 + connect \pick_CR_full_cr_cr0_0 \$793 connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 - connect \addr_en_XER_xer_ov_spr0_0 \$775 - connect \rp_XER_xer_ov_spr0_0 \$773 + connect \addr_en_XER_xer_ov_spr0_0 \$785 + connect \rp_XER_xer_ov_spr0_0 \$783 connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 - connect \pick_XER_xer_ov_spr0_0 \$771 - connect \rdflag_XER_xer_ov_0 \$763 - connect \xer_src2__ren \$751 - connect \addr_en_XER_xer_ca_shiftrot0_2 \$749 - connect \rp_XER_xer_ca_shiftrot0_2 \$747 - connect \pick_XER_xer_ca_shiftrot0_2 \$745 - connect \addr_en_XER_xer_ca_spr0_1 \$737 - connect \rp_XER_xer_ca_spr0_1 \$735 - connect \pick_XER_xer_ca_spr0_1 \$733 - connect \addr_en_XER_xer_ca_alu0_0 \$725 - connect \rp_XER_xer_ca_alu0_0 \$723 + connect \pick_XER_xer_ov_spr0_0 \$781 + connect \rdflag_XER_xer_ov_0 \$773 + connect \xer_src2__ren \$761 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$759 + connect \rp_XER_xer_ca_shiftrot0_2 \$757 + connect \pick_XER_xer_ca_shiftrot0_2 \$755 + connect \addr_en_XER_xer_ca_spr0_1 \$747 + connect \rp_XER_xer_ca_spr0_1 \$745 + connect \pick_XER_xer_ca_spr0_1 \$743 + connect \addr_en_XER_xer_ca_alu0_0 \$735 + connect \rp_XER_xer_ca_alu0_0 \$733 connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 - connect \pick_XER_xer_ca_alu0_0 \$721 - connect \rdflag_XER_xer_ca_0 \$713 - connect \xer_src1__ren \$695 - connect \addr_en_XER_xer_so_shiftrot0_5 \$693 - connect \rp_XER_xer_so_shiftrot0_5 \$691 - connect \pick_XER_xer_so_shiftrot0_5 \$689 - connect \addr_en_XER_xer_so_mul0_4 \$681 - connect \rp_XER_xer_so_mul0_4 \$679 - connect \pick_XER_xer_so_mul0_4 \$677 - connect \addr_en_XER_xer_so_div0_3 \$669 - connect \rp_XER_xer_so_div0_3 \$667 - connect \pick_XER_xer_so_div0_3 \$665 - connect \addr_en_XER_xer_so_spr0_2 \$657 - connect \rp_XER_xer_so_spr0_2 \$655 - connect \pick_XER_xer_so_spr0_2 \$653 - connect \addr_en_XER_xer_so_logical0_1 \$645 - connect \rp_XER_xer_so_logical0_1 \$643 - connect \pick_XER_xer_so_logical0_1 \$641 - connect \addr_en_XER_xer_so_alu0_0 \$633 - connect \rp_XER_xer_so_alu0_0 \$631 + connect \pick_XER_xer_ca_alu0_0 \$731 + connect \rdflag_XER_xer_ca_0 \$723 + connect \xer_src1__ren \$705 + connect \addr_en_XER_xer_so_shiftrot0_5 \$703 + connect \rp_XER_xer_so_shiftrot0_5 \$701 + connect \pick_XER_xer_so_shiftrot0_5 \$699 + connect \addr_en_XER_xer_so_mul0_4 \$691 + connect \rp_XER_xer_so_mul0_4 \$689 + connect \pick_XER_xer_so_mul0_4 \$687 + connect \addr_en_XER_xer_so_div0_3 \$679 + connect \rp_XER_xer_so_div0_3 \$677 + connect \pick_XER_xer_so_div0_3 \$675 + connect \addr_en_XER_xer_so_spr0_2 \$667 + connect \rp_XER_xer_so_spr0_2 \$665 + connect \pick_XER_xer_so_spr0_2 \$663 + connect \addr_en_XER_xer_so_logical0_1 \$655 + connect \rp_XER_xer_so_logical0_1 \$653 + connect \pick_XER_xer_so_logical0_1 \$651 + connect \addr_en_XER_xer_so_alu0_0 \$643 + connect \rp_XER_xer_so_alu0_0 \$641 connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 - connect \pick_XER_xer_so_alu0_0 \$629 - connect \rdflag_XER_xer_so_0 \$621 - connect \int_src3__ren \$609 - connect \int_src3__addr \$607 - connect \addr_en_INT_rc_ldst0_1 \$605 - connect \rp_INT_rc_ldst0_1 \$603 - connect \pick_INT_rc_ldst0_1 \$601 - connect \addr_en_INT_rc_shiftrot0_0 \$593 - connect \rp_INT_rc_shiftrot0_0 \$591 + connect \pick_XER_xer_so_alu0_0 \$639 + connect \rdflag_XER_xer_so_0 \$631 + connect \int_src3__ren \$619 + connect \int_src3__addr \$617 [4:0] + connect \addr_en_INT_rc_ldst0_1 \$614 + connect \rp_INT_rc_ldst0_1 \$612 + connect \pick_INT_rc_ldst0_1 \$610 + connect \addr_en_INT_rc_shiftrot0_0 \$602 + connect \rp_INT_rc_shiftrot0_0 \$600 connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 - connect \pick_INT_rc_shiftrot0_0 \$589 + connect \pick_INT_rc_shiftrot0_0 \$598 connect \rdflag_INT_rc_0 \core_reg3_ok - connect \int_src2__ren \$581 - connect \int_src2__addr \$579 - connect \addr_en_INT_rb_ldst0_7 \$565 - connect \rp_INT_rb_ldst0_7 \$563 - connect \pick_INT_rb_ldst0_7 \$561 - connect \addr_en_INT_rb_shiftrot0_6 \$553 - connect \rp_INT_rb_shiftrot0_6 \$551 - connect \pick_INT_rb_shiftrot0_6 \$549 - connect \addr_en_INT_rb_mul0_5 \$541 - connect \rp_INT_rb_mul0_5 \$539 - connect \pick_INT_rb_mul0_5 \$537 - connect \addr_en_INT_rb_div0_4 \$529 - connect \rp_INT_rb_div0_4 \$527 - connect \pick_INT_rb_div0_4 \$525 - connect \addr_en_INT_rb_logical0_3 \$517 - connect \rp_INT_rb_logical0_3 \$515 - connect \pick_INT_rb_logical0_3 \$513 - connect \addr_en_INT_rb_trap0_2 \$505 - connect \rp_INT_rb_trap0_2 \$503 - connect \pick_INT_rb_trap0_2 \$501 - connect \addr_en_INT_rb_cr0_1 \$493 - connect \rp_INT_rb_cr0_1 \$491 - connect \pick_INT_rb_cr0_1 \$489 - connect \addr_en_INT_rb_alu0_0 \$481 - connect \rp_INT_rb_alu0_0 \$479 + connect \int_src2__ren \$590 + connect \int_src2__addr \$588 [4:0] + connect \addr_en_INT_rb_ldst0_7 \$573 + connect \rp_INT_rb_ldst0_7 \$571 + connect \pick_INT_rb_ldst0_7 \$569 + connect \addr_en_INT_rb_shiftrot0_6 \$561 + connect \rp_INT_rb_shiftrot0_6 \$559 + connect \pick_INT_rb_shiftrot0_6 \$557 + connect \addr_en_INT_rb_mul0_5 \$549 + connect \rp_INT_rb_mul0_5 \$547 + connect \pick_INT_rb_mul0_5 \$545 + connect \addr_en_INT_rb_div0_4 \$537 + connect \rp_INT_rb_div0_4 \$535 + connect \pick_INT_rb_div0_4 \$533 + connect \addr_en_INT_rb_logical0_3 \$525 + connect \rp_INT_rb_logical0_3 \$523 + connect \pick_INT_rb_logical0_3 \$521 + connect \addr_en_INT_rb_trap0_2 \$513 + connect \rp_INT_rb_trap0_2 \$511 + connect \pick_INT_rb_trap0_2 \$509 + connect \addr_en_INT_rb_cr0_1 \$501 + connect \rp_INT_rb_cr0_1 \$499 + connect \pick_INT_rb_cr0_1 \$497 + connect \addr_en_INT_rb_alu0_0 \$489 + connect \rp_INT_rb_alu0_0 \$487 connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 @@ -85077,69 +85674,69 @@ module \core connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 - connect \pick_INT_rb_alu0_0 \$477 + connect \pick_INT_rb_alu0_0 \$485 connect \rdflag_INT_rb_0 \core_reg2_ok - connect \int_src1__ren \$469 - connect \int_src1__addr \$467 - connect \addr_en_INT_ra_ldst0_8 \$451 - connect \rp_INT_ra_ldst0_8 \$449 - connect \fus_cu_rd__go_i$60 [2] \dp_INT_rc_ldst0_1 - connect \fus_cu_rd__go_i$60 [1] \dp_INT_rb_ldst0_7 - connect \fus_cu_rd__go_i$60 [0] \dp_INT_ra_ldst0_8 - connect \pick_INT_ra_ldst0_8 \$447 - connect \addr_en_INT_ra_shiftrot0_7 \$439 - connect \rp_INT_ra_shiftrot0_7 \$437 - connect \fus_cu_rd__go_i$57 [4] \dp_XER_xer_ca_shiftrot0_2 - connect \fus_cu_rd__go_i$57 [3] \dp_XER_xer_so_shiftrot0_5 - connect \fus_cu_rd__go_i$57 [2] \dp_INT_rc_shiftrot0_0 - connect \fus_cu_rd__go_i$57 [1] \dp_INT_rb_shiftrot0_6 - connect \fus_cu_rd__go_i$57 [0] \dp_INT_ra_shiftrot0_7 - connect \pick_INT_ra_shiftrot0_7 \$435 - connect \addr_en_INT_ra_mul0_6 \$427 - connect \rp_INT_ra_mul0_6 \$425 - connect \fus_cu_rd__go_i$54 [2] \dp_XER_xer_so_mul0_4 - connect \fus_cu_rd__go_i$54 [1] \dp_INT_rb_mul0_5 - connect \fus_cu_rd__go_i$54 [0] \dp_INT_ra_mul0_6 - connect \pick_INT_ra_mul0_6 \$423 - connect \addr_en_INT_ra_div0_5 \$415 - connect \rp_INT_ra_div0_5 \$413 - connect \fus_cu_rd__go_i$51 [2] \dp_XER_xer_so_div0_3 - connect \fus_cu_rd__go_i$51 [1] \dp_INT_rb_div0_4 - connect \fus_cu_rd__go_i$51 [0] \dp_INT_ra_div0_5 - connect \pick_INT_ra_div0_5 \$411 - connect \addr_en_INT_ra_spr0_4 \$403 - connect \rp_INT_ra_spr0_4 \$401 - connect \fus_cu_rd__go_i$48 [1] \dp_SPR_spr1_spr0_0 - connect \fus_cu_rd__go_i$48 [2] \dp_FAST_fast1_spr0_2 - connect \fus_cu_rd__go_i$48 [4] \dp_XER_xer_ov_spr0_0 - connect \fus_cu_rd__go_i$48 [5] \dp_XER_xer_ca_spr0_1 - connect \fus_cu_rd__go_i$48 [3] \dp_XER_xer_so_spr0_2 - connect \fus_cu_rd__go_i$48 [0] \dp_INT_ra_spr0_4 - connect \pick_INT_ra_spr0_4 \$399 - connect \addr_en_INT_ra_logical0_3 \$391 - connect \rp_INT_ra_logical0_3 \$389 - connect \fus_cu_rd__go_i$45 [2] \dp_XER_xer_so_logical0_1 - connect \fus_cu_rd__go_i$45 [1] \dp_INT_rb_logical0_3 - connect \fus_cu_rd__go_i$45 [0] \dp_INT_ra_logical0_3 - connect \pick_INT_ra_logical0_3 \$387 - connect \addr_en_INT_ra_trap0_2 \$379 - connect \rp_INT_ra_trap0_2 \$377 - connect \fus_cu_rd__go_i$42 [3] \dp_FAST_fast2_trap0_1 - connect \fus_cu_rd__go_i$42 [2] \dp_FAST_fast1_trap0_1 - connect \fus_cu_rd__go_i$42 [1] \dp_INT_rb_trap0_2 - connect \fus_cu_rd__go_i$42 [0] \dp_INT_ra_trap0_2 - connect \pick_INT_ra_trap0_2 \$375 - connect \addr_en_INT_ra_cr0_1 \$367 - connect \rp_INT_ra_cr0_1 \$365 - connect \fus_cu_rd__go_i$39 [5] \dp_CR_cr_c_cr0_0 - connect \fus_cu_rd__go_i$39 [4] \dp_CR_cr_b_cr0_0 - connect \fus_cu_rd__go_i$39 [3] \dp_CR_cr_a_cr0_0 - connect \fus_cu_rd__go_i$39 [2] \dp_CR_full_cr_cr0_0 - connect \fus_cu_rd__go_i$39 [1] \dp_INT_rb_cr0_1 - connect \fus_cu_rd__go_i$39 [0] \dp_INT_ra_cr0_1 - connect \pick_INT_ra_cr0_1 \$363 - connect \addr_en_INT_ra_alu0_0 \$355 - connect \rp_INT_ra_alu0_0 \$353 + connect \int_src1__ren \$477 + connect \int_src1__addr \$475 [4:0] + connect \addr_en_INT_ra_ldst0_8 \$458 + connect \rp_INT_ra_ldst0_8 \$456 + connect \fus_cu_rd__go_i$62 [2] \dp_INT_rc_ldst0_1 + connect \fus_cu_rd__go_i$62 [1] \dp_INT_rb_ldst0_7 + connect \fus_cu_rd__go_i$62 [0] \dp_INT_ra_ldst0_8 + connect \pick_INT_ra_ldst0_8 \$454 + connect \addr_en_INT_ra_shiftrot0_7 \$446 + connect \rp_INT_ra_shiftrot0_7 \$444 + connect \fus_cu_rd__go_i$59 [4] \dp_XER_xer_ca_shiftrot0_2 + connect \fus_cu_rd__go_i$59 [3] \dp_XER_xer_so_shiftrot0_5 + connect \fus_cu_rd__go_i$59 [2] \dp_INT_rc_shiftrot0_0 + connect \fus_cu_rd__go_i$59 [1] \dp_INT_rb_shiftrot0_6 + connect \fus_cu_rd__go_i$59 [0] \dp_INT_ra_shiftrot0_7 + connect \pick_INT_ra_shiftrot0_7 \$442 + connect \addr_en_INT_ra_mul0_6 \$434 + connect \rp_INT_ra_mul0_6 \$432 + connect \fus_cu_rd__go_i$56 [2] \dp_XER_xer_so_mul0_4 + connect \fus_cu_rd__go_i$56 [1] \dp_INT_rb_mul0_5 + connect \fus_cu_rd__go_i$56 [0] \dp_INT_ra_mul0_6 + connect \pick_INT_ra_mul0_6 \$430 + connect \addr_en_INT_ra_div0_5 \$422 + connect \rp_INT_ra_div0_5 \$420 + connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_div0_3 + connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_div0_4 + connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_div0_5 + connect \pick_INT_ra_div0_5 \$418 + connect \addr_en_INT_ra_spr0_4 \$410 + connect \rp_INT_ra_spr0_4 \$408 + connect \fus_cu_rd__go_i$50 [1] \dp_SPR_spr1_spr0_0 + connect \fus_cu_rd__go_i$50 [2] \dp_FAST_fast1_spr0_2 + connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ov_spr0_0 + connect \fus_cu_rd__go_i$50 [5] \dp_XER_xer_ca_spr0_1 + connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_spr0_2 + connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_spr0_4 + connect \pick_INT_ra_spr0_4 \$406 + connect \addr_en_INT_ra_logical0_3 \$398 + connect \rp_INT_ra_logical0_3 \$396 + connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_logical0_1 + connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_logical0_3 + connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_logical0_3 + connect \pick_INT_ra_logical0_3 \$394 + connect \addr_en_INT_ra_trap0_2 \$386 + connect \rp_INT_ra_trap0_2 \$384 + connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast2_trap0_1 + connect \fus_cu_rd__go_i$44 [2] \dp_FAST_fast1_trap0_1 + connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_trap0_2 + connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_trap0_2 + connect \pick_INT_ra_trap0_2 \$382 + connect \addr_en_INT_ra_cr0_1 \$374 + connect \rp_INT_ra_cr0_1 \$372 + connect \fus_cu_rd__go_i$41 [5] \dp_CR_cr_c_cr0_0 + connect \fus_cu_rd__go_i$41 [4] \dp_CR_cr_b_cr0_0 + connect \fus_cu_rd__go_i$41 [3] \dp_CR_cr_a_cr0_0 + connect \fus_cu_rd__go_i$41 [2] \dp_CR_full_cr_cr0_0 + connect \fus_cu_rd__go_i$41 [1] \dp_INT_rb_cr0_1 + connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_cr0_1 + connect \pick_INT_ra_cr0_1 \$370 + connect \addr_en_INT_ra_alu0_0 \$362 + connect \rp_INT_ra_alu0_0 \$360 connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 @@ -85153,17 +85750,17 @@ module \core connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 - connect \pick_INT_ra_alu0_0 \$351 + connect \pick_INT_ra_alu0_0 \$358 connect \rdflag_INT_ra_0 \core_reg1_ok - connect \en_ldst0 \$210 - connect \en_shiftrot0 \$206 - connect \en_mul0 \$202 - connect \en_div0 \$198 - connect \en_spr0 \$194 - connect \en_logical0 \$190 - connect \en_trap0 \$186 - connect \en_branch0 \$182 - connect \en_cr0 \$178 + connect \en_ldst0 \$217 + connect \en_shiftrot0 \$213 + connect \en_mul0 \$209 + connect \en_div0 \$205 + connect \en_spr0 \$201 + connect \en_logical0 \$197 + connect \en_trap0 \$193 + connect \en_branch0 \$189 + connect \en_cr0 \$185 connect \fu_enable [9] \en_ldst0 connect \fu_enable [8] \en_shiftrot0 connect \fu_enable [7] \en_mul0 @@ -85174,442 +85771,451 @@ module \core connect \fu_enable [2] \en_branch0 connect \fu_enable [1] \en_cr0 connect \fu_enable [0] \en_alu0 - connect \en_alu0 \$174 + connect \en_alu0 \$181 + connect \dec_LDST_sv_a_nz \sv_a_nz connect \dec_LDST_bigendian \bigendian_i connect \dec_LDST_raw_opcode_in \raw_insn_i + connect \sv_a_nz$180 \sv_a_nz connect \dec_SHIFT_ROT_bigendian \bigendian_i connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i + connect \sv_a_nz$179 \sv_a_nz connect \dec_MUL_bigendian \bigendian_i connect \dec_MUL_raw_opcode_in \raw_insn_i + connect \dec_DIV_sv_a_nz \sv_a_nz connect \dec_DIV_bigendian \bigendian_i connect \dec_DIV_raw_opcode_in \raw_insn_i + connect \sv_a_nz$178 \sv_a_nz connect \dec_SPR_bigendian \bigendian_i connect \dec_SPR_raw_opcode_in \raw_insn_i + connect \dec_LOGICAL_sv_a_nz \sv_a_nz connect \dec_LOGICAL_bigendian \bigendian_i connect \dec_LOGICAL_raw_opcode_in \raw_insn_i + connect \sv_a_nz$177 \sv_a_nz connect \dec_BRANCH_bigendian \bigendian_i connect \dec_BRANCH_raw_opcode_in \raw_insn_i + connect \sv_a_nz$176 \sv_a_nz connect \dec_CR_bigendian \bigendian_i connect \dec_CR_raw_opcode_in \raw_insn_i + connect \dec_ALU_sv_a_nz \sv_a_nz connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:48554.1-49187.10" +attribute \src "libresoc.v:49145.1-49778.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr - attribute \src "libresoc.v:48555.7-48555.20" + attribute \src "libresoc.v:49146.7-49146.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49101.3-49109.6" + attribute \src "libresoc.v:49692.3-49700.6" wire width 8 $0\ren_delay$17$next[7:0]$3046 - attribute \src "libresoc.v:48937.3-48938.43" + attribute \src "libresoc.v:49528.3-49529.43" wire width 8 $0\ren_delay$17[7:0]$3043 - attribute \src "libresoc.v:48883.13-48883.35" + attribute \src "libresoc.v:49474.13-49474.35" wire width 8 $0\ren_delay$17[7:0]$3060 - attribute \src "libresoc.v:49120.3-49128.6" + attribute \src "libresoc.v:49711.3-49719.6" wire width 8 $0\ren_delay$34$next[7:0]$3050 - attribute \src "libresoc.v:48935.3-48936.43" + attribute \src "libresoc.v:49526.3-49527.43" wire width 8 $0\ren_delay$34[7:0]$3041 - attribute \src "libresoc.v:48887.13-48887.35" + attribute \src "libresoc.v:49478.13-49478.35" wire width 8 $0\ren_delay$34[7:0]$3062 - attribute \src "libresoc.v:49139.3-49147.6" + attribute \src "libresoc.v:49730.3-49738.6" wire width 8 $0\ren_delay$next[7:0]$3054 - attribute \src "libresoc.v:48939.3-48940.35" + attribute \src "libresoc.v:49530.3-49531.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:49148.3-49157.6" + attribute \src "libresoc.v:49739.3-49748.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:49110.3-49119.6" + attribute \src "libresoc.v:49701.3-49710.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:49129.3-49138.6" + attribute \src "libresoc.v:49720.3-49729.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:49101.3-49109.6" + attribute \src "libresoc.v:49692.3-49700.6" wire width 8 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49120.3-49128.6" + attribute \src "libresoc.v:49711.3-49719.6" wire width 8 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49139.3-49147.6" + attribute \src "libresoc.v:49730.3-49738.6" wire width 8 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:48881.13-48881.30" + attribute \src "libresoc.v:49472.13-49472.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:49148.3-49157.6" + attribute \src "libresoc.v:49739.3-49748.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:49110.3-49119.6" + attribute \src "libresoc.v:49701.3-49710.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:49129.3-49138.6" + attribute \src "libresoc.v:49720.3-49729.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:48911.17-48911.125" - wire width 4 $or$libresoc.v:48911$3016_Y - attribute \src "libresoc.v:48912.18-48912.126" - wire width 4 $or$libresoc.v:48912$3017_Y - attribute \src "libresoc.v:48913.18-48913.96" - wire width 4 $or$libresoc.v:48913$3018_Y - attribute \src "libresoc.v:48914.18-48914.96" - wire width 4 $or$libresoc.v:48914$3019_Y - attribute \src "libresoc.v:48917.18-48917.126" - wire width 4 $or$libresoc.v:48917$3022_Y - attribute \src "libresoc.v:48918.18-48918.126" - wire width 4 $or$libresoc.v:48918$3023_Y - attribute \src "libresoc.v:48919.18-48919.97" - wire width 4 $or$libresoc.v:48919$3024_Y - attribute \src "libresoc.v:48920.18-48920.126" - wire width 4 $or$libresoc.v:48920$3025_Y - attribute \src "libresoc.v:48921.18-48921.126" - wire width 4 $or$libresoc.v:48921$3026_Y - attribute \src "libresoc.v:48922.18-48922.97" - wire width 4 $or$libresoc.v:48922$3027_Y - attribute \src "libresoc.v:48923.18-48923.97" - wire width 4 $or$libresoc.v:48923$3028_Y - attribute \src "libresoc.v:48925.18-48925.126" - wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 14 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \data_i$52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 3 \full_rd2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 2 \full_rd2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 4 \full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 5 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 input 12 \full_wr__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 13 \full_wr__wen - attribute \src "libresoc.v:48555.7-48555.15" + attribute \src "libresoc.v:49146.7-49146.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_r0__data_o - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_w0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_r21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_r21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_w1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_r22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_r22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_w2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_dest23__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_r23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_r23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_r3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_r3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_src23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_src23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_src33__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_src33__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_w3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_w3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_dest14__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_dest14__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_dest24__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_r24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_r24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_r4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_r4__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_src24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_src24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_src34__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_src34__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_w4__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_w4__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_dest15__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_dest25__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_r25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_r25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_r5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_r5__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_src15__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_src15__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_src25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_src25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_src35__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_src35__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_w5__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_w5__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_dest16__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_dest16__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_dest26__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_r26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_r26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_r6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_r6__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_src16__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_src16__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_src26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_w6__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_dest27__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_r27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_r27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_r7__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_w7__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay @@ -85623,24 +86229,24 @@ module \cr wire width 8 \ren_delay$34$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 6 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 7 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 8 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 9 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 10 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 11 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 15 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \wen$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48911$3016 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49502$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85648,10 +86254,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src14__data_o connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:48911$3016_Y + connect \Y $or$libresoc.v:49502$3016_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48912$3017 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49503$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85659,10 +86265,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src16__data_o connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:48912$3017_Y + connect \Y $or$libresoc.v:49503$3017_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48913$3018 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49504$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85670,10 +86276,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:48913$3018_Y + connect \Y $or$libresoc.v:49504$3018_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48914$3019 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49505$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85681,10 +86287,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:48914$3019_Y + connect \Y $or$libresoc.v:49505$3019_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48917$3022 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49508$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85692,10 +86298,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src20__data_o connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:48917$3022_Y + connect \Y $or$libresoc.v:49508$3022_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48918$3023 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49509$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85703,10 +86309,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src22__data_o connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:48918$3023_Y + connect \Y $or$libresoc.v:49509$3023_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48919$3024 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49510$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85714,10 +86320,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:48919$3024_Y + connect \Y $or$libresoc.v:49510$3024_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48920$3025 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49511$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85725,10 +86331,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src24__data_o connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:48920$3025_Y + connect \Y $or$libresoc.v:49511$3025_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48921$3026 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49512$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85736,10 +86342,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src26__data_o connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:48921$3026_Y + connect \Y $or$libresoc.v:49512$3026_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48922$3027 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49513$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85747,10 +86353,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:48922$3027_Y + connect \Y $or$libresoc.v:49513$3027_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48923$3028 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49514$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85758,10 +86364,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:48923$3028_Y + connect \Y $or$libresoc.v:49514$3028_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48925$3030 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49516$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85769,10 +86375,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src30__data_o connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:48925$3030_Y + connect \Y $or$libresoc.v:49516$3030_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48926$3031 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49517$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85780,10 +86386,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src10__data_o connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:48926$3031_Y + connect \Y $or$libresoc.v:49517$3031_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48927$3032 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49518$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85791,10 +86397,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src32__data_o connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:48927$3032_Y + connect \Y $or$libresoc.v:49518$3032_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48928$3033 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49519$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85802,10 +86408,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:48928$3033_Y + connect \Y $or$libresoc.v:49519$3033_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48929$3034 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49520$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85813,10 +86419,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src34__data_o connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:48929$3034_Y + connect \Y $or$libresoc.v:49520$3034_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48930$3035 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49521$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85824,10 +86430,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src36__data_o connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:48930$3035_Y + connect \Y $or$libresoc.v:49521$3035_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48931$3036 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49522$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85835,10 +86441,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:48931$3036_Y + connect \Y $or$libresoc.v:49522$3036_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48932$3037 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49523$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85846,10 +86452,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:48932$3037_Y + connect \Y $or$libresoc.v:49523$3037_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48933$3038 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49524$3038 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85857,10 +86463,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src12__data_o connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:48933$3038_Y + connect \Y $or$libresoc.v:49524$3038_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48934$3039 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49525$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85868,34 +86474,34 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:48934$3039_Y + connect \Y $or$libresoc.v:49525$3039_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:48915$3020 + cell $reduce_or $reduce_or$libresoc.v:49506$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:48915$3020_Y + connect \Y $reduce_or$libresoc.v:49506$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:48916$3021 + cell $reduce_or $reduce_or$libresoc.v:49507$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:48916$3021_Y + connect \Y $reduce_or$libresoc.v:49507$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:48924$3029 + cell $reduce_or $reduce_or$libresoc.v:49515$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:48924$3029_Y + connect \Y $reduce_or$libresoc.v:49515$3029_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:48941.9-48960.4" + attribute \src "libresoc.v:49532.9-49551.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85917,7 +86523,7 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48961.9-48980.4" + attribute \src "libresoc.v:49552.9-49571.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85939,7 +86545,7 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48981.9-49000.4" + attribute \src "libresoc.v:49572.9-49591.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85961,7 +86567,7 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49001.9-49020.4" + attribute \src "libresoc.v:49592.9-49611.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85983,7 +86589,7 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49021.9-49040.4" + attribute \src "libresoc.v:49612.9-49631.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86005,7 +86611,7 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49041.9-49060.4" + attribute \src "libresoc.v:49632.9-49651.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86027,7 +86633,7 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49061.9-49080.4" + attribute \src "libresoc.v:49652.9-49671.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86049,7 +86655,7 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49081.9-49100.4" + attribute \src "libresoc.v:49672.9-49691.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86070,67 +86676,67 @@ module \cr connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end - attribute \src "libresoc.v:48555.7-48555.20" - process $proc$libresoc.v:48555$3057 + attribute \src "libresoc.v:49146.7-49146.20" + process $proc$libresoc.v:49146$3057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:48881.13-48881.30" - process $proc$libresoc.v:48881$3058 + attribute \src "libresoc.v:49472.13-49472.30" + process $proc$libresoc.v:49472$3058 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:48883.13-48883.35" - process $proc$libresoc.v:48883$3059 + attribute \src "libresoc.v:49474.13-49474.35" + process $proc$libresoc.v:49474$3059 assign { } { } assign $0\ren_delay$17[7:0]$3060 8'00000000 sync always sync init update \ren_delay$17 $0\ren_delay$17[7:0]$3060 end - attribute \src "libresoc.v:48887.13-48887.35" - process $proc$libresoc.v:48887$3061 + attribute \src "libresoc.v:49478.13-49478.35" + process $proc$libresoc.v:49478$3061 assign { } { } assign $0\ren_delay$34[7:0]$3062 8'00000000 sync always sync init update \ren_delay$34 $0\ren_delay$34[7:0]$3062 end - attribute \src "libresoc.v:48935.3-48936.43" - process $proc$libresoc.v:48935$3040 + attribute \src "libresoc.v:49526.3-49527.43" + process $proc$libresoc.v:49526$3040 assign { } { } assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next sync posedge \coresync_clk update \ren_delay$34 $0\ren_delay$34[7:0]$3041 end - attribute \src "libresoc.v:48937.3-48938.43" - process $proc$libresoc.v:48937$3042 + attribute \src "libresoc.v:49528.3-49529.43" + process $proc$libresoc.v:49528$3042 assign { } { } assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next sync posedge \coresync_clk update \ren_delay$17 $0\ren_delay$17[7:0]$3043 end - attribute \src "libresoc.v:48939.3-48940.35" - process $proc$libresoc.v:48939$3044 + attribute \src "libresoc.v:49530.3-49531.35" + process $proc$libresoc.v:49530$3044 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:49101.3-49109.6" - process $proc$libresoc.v:49101$3045 + attribute \src "libresoc.v:49692.3-49700.6" + process $proc$libresoc.v:49692$3045 assign { } { } assign { } { } assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49102.5-49102.29" + attribute \src "libresoc.v:49693.5-49693.29" switch \initial - attribute \src "libresoc.v:49102.9-49102.17" + attribute \src "libresoc.v:49693.9-49693.17" case 1'1 case end @@ -86146,14 +86752,14 @@ module \cr sync always update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 end - attribute \src "libresoc.v:49110.3-49119.6" - process $proc$libresoc.v:49110$3048 + attribute \src "libresoc.v:49701.3-49710.6" + process $proc$libresoc.v:49701$3048 assign { } { } assign { } { } assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49111.5-49111.29" + attribute \src "libresoc.v:49702.5-49702.29" switch \initial - attribute \src "libresoc.v:49111.9-49111.17" + attribute \src "libresoc.v:49702.9-49702.17" case 1'1 case end @@ -86169,14 +86775,14 @@ module \cr sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:49120.3-49128.6" - process $proc$libresoc.v:49120$3049 + attribute \src "libresoc.v:49711.3-49719.6" + process $proc$libresoc.v:49711$3049 assign { } { } assign { } { } assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49121.5-49121.29" + attribute \src "libresoc.v:49712.5-49712.29" switch \initial - attribute \src "libresoc.v:49121.9-49121.17" + attribute \src "libresoc.v:49712.9-49712.17" case 1'1 case end @@ -86192,14 +86798,14 @@ module \cr sync always update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 end - attribute \src "libresoc.v:49129.3-49138.6" - process $proc$libresoc.v:49129$3052 + attribute \src "libresoc.v:49720.3-49729.6" + process $proc$libresoc.v:49720$3052 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49130.5-49130.29" + attribute \src "libresoc.v:49721.5-49721.29" switch \initial - attribute \src "libresoc.v:49130.9-49130.17" + attribute \src "libresoc.v:49721.9-49721.17" case 1'1 case end @@ -86215,14 +86821,14 @@ module \cr sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:49139.3-49147.6" - process $proc$libresoc.v:49139$3053 + attribute \src "libresoc.v:49730.3-49738.6" + process $proc$libresoc.v:49730$3053 assign { } { } assign { } { } assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49140.5-49140.29" + attribute \src "libresoc.v:49731.5-49731.29" switch \initial - attribute \src "libresoc.v:49140.9-49140.17" + attribute \src "libresoc.v:49731.9-49731.17" case 1'1 case end @@ -86238,14 +86844,14 @@ module \cr sync always update \ren_delay$next $0\ren_delay$next[7:0]$3054 end - attribute \src "libresoc.v:49148.3-49157.6" - process $proc$libresoc.v:49148$3056 + attribute \src "libresoc.v:49739.3-49748.6" + process $proc$libresoc.v:49739$3056 assign { } { } assign { } { } assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49149.5-49149.29" + attribute \src "libresoc.v:49740.5-49740.29" switch \initial - attribute \src "libresoc.v:49149.9-49149.17" + attribute \src "libresoc.v:49740.9-49740.17" case 1'1 case end @@ -86261,30 +86867,30 @@ module \cr sync always update \src1__data_o $0\src1__data_o[3:0] end - connect \$9 $or$libresoc.v:48911$3016_Y - connect \$11 $or$libresoc.v:48912$3017_Y - connect \$13 $or$libresoc.v:48913$3018_Y - connect \$15 $or$libresoc.v:48914$3019_Y - connect \$18 $reduce_or$libresoc.v:48915$3020_Y - connect \$1 $reduce_or$libresoc.v:48916$3021_Y - connect \$20 $or$libresoc.v:48917$3022_Y - connect \$22 $or$libresoc.v:48918$3023_Y - connect \$24 $or$libresoc.v:48919$3024_Y - connect \$26 $or$libresoc.v:48920$3025_Y - connect \$28 $or$libresoc.v:48921$3026_Y - connect \$30 $or$libresoc.v:48922$3027_Y - connect \$32 $or$libresoc.v:48923$3028_Y - connect \$35 $reduce_or$libresoc.v:48924$3029_Y - connect \$37 $or$libresoc.v:48925$3030_Y - connect \$3 $or$libresoc.v:48926$3031_Y - connect \$39 $or$libresoc.v:48927$3032_Y - connect \$41 $or$libresoc.v:48928$3033_Y - connect \$43 $or$libresoc.v:48929$3034_Y - connect \$45 $or$libresoc.v:48930$3035_Y - connect \$47 $or$libresoc.v:48931$3036_Y - connect \$49 $or$libresoc.v:48932$3037_Y - connect \$5 $or$libresoc.v:48933$3038_Y - connect \$7 $or$libresoc.v:48934$3039_Y + connect \$9 $or$libresoc.v:49502$3016_Y + connect \$11 $or$libresoc.v:49503$3017_Y + connect \$13 $or$libresoc.v:49504$3018_Y + connect \$15 $or$libresoc.v:49505$3019_Y + connect \$18 $reduce_or$libresoc.v:49506$3020_Y + connect \$1 $reduce_or$libresoc.v:49507$3021_Y + connect \$20 $or$libresoc.v:49508$3022_Y + connect \$22 $or$libresoc.v:49509$3023_Y + connect \$24 $or$libresoc.v:49510$3024_Y + connect \$26 $or$libresoc.v:49511$3025_Y + connect \$28 $or$libresoc.v:49512$3026_Y + connect \$30 $or$libresoc.v:49513$3027_Y + connect \$32 $or$libresoc.v:49514$3028_Y + connect \$35 $reduce_or$libresoc.v:49515$3029_Y + connect \$37 $or$libresoc.v:49516$3030_Y + connect \$3 $or$libresoc.v:49517$3031_Y + connect \$39 $or$libresoc.v:49518$3032_Y + connect \$41 $or$libresoc.v:49519$3033_Y + connect \$43 $or$libresoc.v:49520$3034_Y + connect \$45 $or$libresoc.v:49521$3035_Y + connect \$47 $or$libresoc.v:49522$3036_Y + connect \$49 $or$libresoc.v:49523$3037_Y + connect \$5 $or$libresoc.v:49524$3038_Y + connect \$7 $or$libresoc.v:49525$3039_Y connect \wen$51 8'00000000 connect \data_i$52 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen @@ -86315,393 +86921,393 @@ module \cr connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:49191.1-50242.10" +attribute \src "libresoc.v:49782.1-50839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:49843.3-49844.25" + attribute \src "libresoc.v:50440.3-50441.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50016.3-50027.6" - wire width 12 $0\alu_cr0_cr_op__fn_unit$next[11:0]$3182 - attribute \src "libresoc.v:49815.3-49816.61" - wire width 12 $0\alu_cr0_cr_op__fn_unit[11:0] - attribute \src "libresoc.v:50016.3-50027.6" + attribute \src "libresoc.v:50613.3-50624.6" + wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 + attribute \src "libresoc.v:50412.3-50413.61" + wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] + attribute \src "libresoc.v:50613.3-50624.6" wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 - attribute \src "libresoc.v:49817.3-49818.55" + attribute \src "libresoc.v:50414.3-50415.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50016.3-50027.6" + attribute \src "libresoc.v:50613.3-50624.6" wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 - attribute \src "libresoc.v:49813.3-49814.65" + attribute \src "libresoc.v:50410.3-50411.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:49841.3-49842.39" + attribute \src "libresoc.v:50438.3-50439.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50163.3-50171.6" + attribute \src "libresoc.v:50760.3-50768.6" wire $0\alu_l_r_alu$next[0:0]$3234 - attribute \src "libresoc.v:49785.3-49786.39" + attribute \src "libresoc.v:50382.3-50383.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50154.3-50162.6" + attribute \src "libresoc.v:50751.3-50759.6" wire $0\alui_l_r_alui$next[0:0]$3231 - attribute \src "libresoc.v:49787.3-49788.43" + attribute \src "libresoc.v:50384.3-50385.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50028.3-50049.6" + attribute \src "libresoc.v:50625.3-50646.6" wire width 64 $0\data_r0__o$next[63:0]$3189 - attribute \src "libresoc.v:49809.3-49810.37" + attribute \src "libresoc.v:50406.3-50407.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50028.3-50049.6" + attribute \src "libresoc.v:50625.3-50646.6" wire $0\data_r0__o_ok$next[0:0]$3190 - attribute \src "libresoc.v:49811.3-49812.43" + attribute \src "libresoc.v:50408.3-50409.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50050.3-50071.6" + attribute \src "libresoc.v:50647.3-50668.6" wire width 32 $0\data_r1__full_cr$next[31:0]$3197 - attribute \src "libresoc.v:49805.3-49806.49" + attribute \src "libresoc.v:50402.3-50403.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50050.3-50071.6" + attribute \src "libresoc.v:50647.3-50668.6" wire $0\data_r1__full_cr_ok$next[0:0]$3198 - attribute \src "libresoc.v:49807.3-49808.55" + attribute \src "libresoc.v:50404.3-50405.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50072.3-50093.6" + attribute \src "libresoc.v:50669.3-50690.6" wire width 4 $0\data_r2__cr_a$next[3:0]$3205 - attribute \src "libresoc.v:49801.3-49802.43" + attribute \src "libresoc.v:50398.3-50399.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50072.3-50093.6" + attribute \src "libresoc.v:50669.3-50690.6" wire $0\data_r2__cr_a_ok$next[0:0]$3206 - attribute \src "libresoc.v:49803.3-49804.49" + attribute \src "libresoc.v:50400.3-50401.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50172.3-50181.6" + attribute \src "libresoc.v:50769.3-50778.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50182.3-50191.6" + attribute \src "libresoc.v:50779.3-50788.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50192.3-50201.6" + attribute \src "libresoc.v:50789.3-50798.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49192.7-49192.20" + attribute \src "libresoc.v:49783.7-49783.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49971.3-49979.6" + attribute \src "libresoc.v:50568.3-50576.6" wire $0\opc_l_r_opc$next[0:0]$3167 - attribute \src "libresoc.v:49827.3-49828.39" + attribute \src "libresoc.v:50424.3-50425.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:49962.3-49970.6" + attribute \src "libresoc.v:50559.3-50567.6" wire $0\opc_l_s_opc$next[0:0]$3164 - attribute \src "libresoc.v:49829.3-49830.39" + attribute \src "libresoc.v:50426.3-50427.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50202.3-50210.6" + attribute \src "libresoc.v:50799.3-50807.6" wire width 3 $0\prev_wr_go$next[2:0]$3240 - attribute \src "libresoc.v:49839.3-49840.37" + attribute \src "libresoc.v:50436.3-50437.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:49916.3-49925.6" + attribute \src "libresoc.v:50513.3-50522.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:50007.3-50015.6" + attribute \src "libresoc.v:50604.3-50612.6" wire width 3 $0\req_l_r_req$next[2:0]$3179 - attribute \src "libresoc.v:49819.3-49820.39" + attribute \src "libresoc.v:50416.3-50417.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:49998.3-50006.6" + attribute \src "libresoc.v:50595.3-50603.6" wire width 3 $0\req_l_s_req$next[2:0]$3176 - attribute \src "libresoc.v:49821.3-49822.39" + attribute \src "libresoc.v:50418.3-50419.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:49935.3-49943.6" + attribute \src "libresoc.v:50532.3-50540.6" wire $0\rok_l_r_rdok$next[0:0]$3155 - attribute \src "libresoc.v:49835.3-49836.41" + attribute \src "libresoc.v:50432.3-50433.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:49926.3-49934.6" + attribute \src "libresoc.v:50523.3-50531.6" wire $0\rok_l_s_rdok$next[0:0]$3152 - attribute \src "libresoc.v:49837.3-49838.41" + attribute \src "libresoc.v:50434.3-50435.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:49953.3-49961.6" + attribute \src "libresoc.v:50550.3-50558.6" wire $0\rst_l_r_rst$next[0:0]$3161 - attribute \src "libresoc.v:49831.3-49832.39" + attribute \src "libresoc.v:50428.3-50429.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:49944.3-49952.6" + attribute \src "libresoc.v:50541.3-50549.6" wire $0\rst_l_s_rst$next[0:0]$3158 - attribute \src "libresoc.v:49833.3-49834.39" + attribute \src "libresoc.v:50430.3-50431.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:49989.3-49997.6" + attribute \src "libresoc.v:50586.3-50594.6" wire width 6 $0\src_l_r_src$next[5:0]$3173 - attribute \src "libresoc.v:49823.3-49824.39" + attribute \src "libresoc.v:50420.3-50421.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:49980.3-49988.6" + attribute \src "libresoc.v:50577.3-50585.6" wire width 6 $0\src_l_s_src$next[5:0]$3170 - attribute \src "libresoc.v:49825.3-49826.39" + attribute \src "libresoc.v:50422.3-50423.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:50094.3-50103.6" + attribute \src "libresoc.v:50691.3-50700.6" wire width 64 $0\src_r0$next[63:0]$3213 - attribute \src "libresoc.v:49799.3-49800.29" + attribute \src "libresoc.v:50396.3-50397.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:50104.3-50113.6" + attribute \src "libresoc.v:50701.3-50710.6" wire width 64 $0\src_r1$next[63:0]$3216 - attribute \src "libresoc.v:49797.3-49798.29" + attribute \src "libresoc.v:50394.3-50395.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:50114.3-50123.6" + attribute \src "libresoc.v:50711.3-50720.6" wire width 32 $0\src_r2$next[31:0]$3219 - attribute \src "libresoc.v:49795.3-49796.29" + attribute \src "libresoc.v:50392.3-50393.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:50124.3-50133.6" + attribute \src "libresoc.v:50721.3-50730.6" wire width 4 $0\src_r3$next[3:0]$3222 - attribute \src "libresoc.v:49793.3-49794.29" + attribute \src "libresoc.v:50390.3-50391.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:50134.3-50143.6" + attribute \src "libresoc.v:50731.3-50740.6" wire width 4 $0\src_r4$next[3:0]$3225 - attribute \src "libresoc.v:49791.3-49792.29" + attribute \src "libresoc.v:50388.3-50389.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:50144.3-50153.6" + attribute \src "libresoc.v:50741.3-50750.6" wire width 4 $0\src_r5$next[3:0]$3228 - attribute \src "libresoc.v:49789.3-49790.29" + attribute \src "libresoc.v:50386.3-50387.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:49310.7-49310.24" + attribute \src "libresoc.v:49901.7-49901.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:50016.3-50027.6" - wire width 12 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3185 - attribute \src "libresoc.v:49339.14-49339.46" - wire width 12 $1\alu_cr0_cr_op__fn_unit[11:0] - attribute \src "libresoc.v:50016.3-50027.6" + attribute \src "libresoc.v:50613.3-50624.6" + wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 + attribute \src "libresoc.v:49932.14-49932.47" + wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] + attribute \src "libresoc.v:50613.3-50624.6" wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 - attribute \src "libresoc.v:49343.14-49343.41" + attribute \src "libresoc.v:49936.14-49936.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50016.3-50027.6" + attribute \src "libresoc.v:50613.3-50624.6" wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:49421.13-49421.45" + attribute \src "libresoc.v:50015.13-50015.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:49445.7-49445.26" + attribute \src "libresoc.v:50039.7-50039.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:50163.3-50171.6" + attribute \src "libresoc.v:50760.3-50768.6" wire $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:49453.7-49453.25" + attribute \src "libresoc.v:50047.7-50047.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50154.3-50162.6" + attribute \src "libresoc.v:50751.3-50759.6" wire $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:49465.7-49465.27" + attribute \src "libresoc.v:50059.7-50059.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50028.3-50049.6" + attribute \src "libresoc.v:50625.3-50646.6" wire width 64 $1\data_r0__o$next[63:0]$3191 - attribute \src "libresoc.v:49499.14-49499.47" + attribute \src "libresoc.v:50093.14-50093.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:50028.3-50049.6" + attribute \src "libresoc.v:50625.3-50646.6" wire $1\data_r0__o_ok$next[0:0]$3192 - attribute \src "libresoc.v:49503.7-49503.27" + attribute \src "libresoc.v:50097.7-50097.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50050.3-50071.6" + attribute \src "libresoc.v:50647.3-50668.6" wire width 32 $1\data_r1__full_cr$next[31:0]$3199 - attribute \src "libresoc.v:49507.14-49507.38" + attribute \src "libresoc.v:50101.14-50101.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50050.3-50071.6" + attribute \src "libresoc.v:50647.3-50668.6" wire $1\data_r1__full_cr_ok$next[0:0]$3200 - attribute \src "libresoc.v:49511.7-49511.33" + attribute \src "libresoc.v:50105.7-50105.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50072.3-50093.6" + attribute \src "libresoc.v:50669.3-50690.6" wire width 4 $1\data_r2__cr_a$next[3:0]$3207 - attribute \src "libresoc.v:49515.13-49515.33" + attribute \src "libresoc.v:50109.13-50109.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50072.3-50093.6" + attribute \src "libresoc.v:50669.3-50690.6" wire $1\data_r2__cr_a_ok$next[0:0]$3208 - attribute \src "libresoc.v:49519.7-49519.30" + attribute \src "libresoc.v:50113.7-50113.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50172.3-50181.6" + attribute \src "libresoc.v:50769.3-50778.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:50182.3-50191.6" + attribute \src "libresoc.v:50779.3-50788.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:50192.3-50201.6" + attribute \src "libresoc.v:50789.3-50798.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:49971.3-49979.6" + attribute \src "libresoc.v:50568.3-50576.6" wire $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:49538.7-49538.25" + attribute \src "libresoc.v:50132.7-50132.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:49962.3-49970.6" + attribute \src "libresoc.v:50559.3-50567.6" wire $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:49542.7-49542.25" + attribute \src "libresoc.v:50136.7-50136.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50202.3-50210.6" + attribute \src "libresoc.v:50799.3-50807.6" wire width 3 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:49639.13-49639.30" + attribute \src "libresoc.v:50236.13-50236.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:49916.3-49925.6" + attribute \src "libresoc.v:50513.3-50522.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:50007.3-50015.6" + attribute \src "libresoc.v:50604.3-50612.6" wire width 3 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:49647.13-49647.31" + attribute \src "libresoc.v:50244.13-50244.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:49998.3-50006.6" + attribute \src "libresoc.v:50595.3-50603.6" wire width 3 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:49651.13-49651.31" + attribute \src "libresoc.v:50248.13-50248.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:49935.3-49943.6" + attribute \src "libresoc.v:50532.3-50540.6" wire $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:49663.7-49663.26" + attribute \src "libresoc.v:50260.7-50260.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:49926.3-49934.6" + attribute \src "libresoc.v:50523.3-50531.6" wire $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:49667.7-49667.26" + attribute \src "libresoc.v:50264.7-50264.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:49953.3-49961.6" + attribute \src "libresoc.v:50550.3-50558.6" wire $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:49671.7-49671.25" + attribute \src "libresoc.v:50268.7-50268.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:49944.3-49952.6" + attribute \src "libresoc.v:50541.3-50549.6" wire $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:49675.7-49675.25" + attribute \src "libresoc.v:50272.7-50272.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:49989.3-49997.6" + attribute \src "libresoc.v:50586.3-50594.6" wire width 6 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:49695.13-49695.32" + attribute \src "libresoc.v:50292.13-50292.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:49980.3-49988.6" + attribute \src "libresoc.v:50577.3-50585.6" wire width 6 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:49699.13-49699.32" + attribute \src "libresoc.v:50296.13-50296.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:50094.3-50103.6" + attribute \src "libresoc.v:50691.3-50700.6" wire width 64 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:49703.14-49703.43" + attribute \src "libresoc.v:50300.14-50300.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:50104.3-50113.6" + attribute \src "libresoc.v:50701.3-50710.6" wire width 64 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:49707.14-49707.43" + attribute \src "libresoc.v:50304.14-50304.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:50114.3-50123.6" + attribute \src "libresoc.v:50711.3-50720.6" wire width 32 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:49711.14-49711.28" + attribute \src "libresoc.v:50308.14-50308.28" wire width 32 $1\src_r2[31:0] - attribute \src "libresoc.v:50124.3-50133.6" + attribute \src "libresoc.v:50721.3-50730.6" wire width 4 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:49715.13-49715.26" + attribute \src "libresoc.v:50312.13-50312.26" wire width 4 $1\src_r3[3:0] - attribute \src "libresoc.v:50134.3-50143.6" + attribute \src "libresoc.v:50731.3-50740.6" wire width 4 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:49719.13-49719.26" + attribute \src "libresoc.v:50316.13-50316.26" wire width 4 $1\src_r4[3:0] - attribute \src "libresoc.v:50144.3-50153.6" + attribute \src "libresoc.v:50741.3-50750.6" wire width 4 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:49723.13-49723.26" + attribute \src "libresoc.v:50320.13-50320.26" wire width 4 $1\src_r5[3:0] - attribute \src "libresoc.v:50028.3-50049.6" + attribute \src "libresoc.v:50625.3-50646.6" wire width 64 $2\data_r0__o$next[63:0]$3193 - attribute \src "libresoc.v:50028.3-50049.6" + attribute \src "libresoc.v:50625.3-50646.6" wire $2\data_r0__o_ok$next[0:0]$3194 - attribute \src "libresoc.v:50050.3-50071.6" + attribute \src "libresoc.v:50647.3-50668.6" wire width 32 $2\data_r1__full_cr$next[31:0]$3201 - attribute \src "libresoc.v:50050.3-50071.6" + attribute \src "libresoc.v:50647.3-50668.6" wire $2\data_r1__full_cr_ok$next[0:0]$3202 - attribute \src "libresoc.v:50072.3-50093.6" + attribute \src "libresoc.v:50669.3-50690.6" wire width 4 $2\data_r2__cr_a$next[3:0]$3209 - attribute \src "libresoc.v:50072.3-50093.6" + attribute \src "libresoc.v:50669.3-50690.6" wire $2\data_r2__cr_a_ok$next[0:0]$3210 - attribute \src "libresoc.v:50028.3-50049.6" + attribute \src "libresoc.v:50625.3-50646.6" wire $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50050.3-50071.6" + attribute \src "libresoc.v:50647.3-50668.6" wire $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50072.3-50093.6" + attribute \src "libresoc.v:50669.3-50690.6" wire $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:49729.18-49729.112" - wire width 6 $and$libresoc.v:49729$3064_Y - attribute \src "libresoc.v:49730.19-49730.125" - wire $and$libresoc.v:49730$3065_Y - attribute \src "libresoc.v:49731.19-49731.125" - wire $and$libresoc.v:49731$3066_Y - attribute \src "libresoc.v:49732.19-49732.125" - wire $and$libresoc.v:49732$3067_Y - attribute \src "libresoc.v:49733.19-49733.141" - wire width 3 $and$libresoc.v:49733$3068_Y - attribute \src "libresoc.v:49734.19-49734.121" - wire width 3 $and$libresoc.v:49734$3069_Y - attribute \src "libresoc.v:49735.19-49735.127" - wire $and$libresoc.v:49735$3070_Y - attribute \src "libresoc.v:49736.19-49736.127" - wire $and$libresoc.v:49736$3071_Y - attribute \src "libresoc.v:49737.19-49737.127" - wire $and$libresoc.v:49737$3072_Y - attribute \src "libresoc.v:49738.18-49738.110" - wire $and$libresoc.v:49738$3073_Y - attribute \src "libresoc.v:49740.18-49740.98" - wire $and$libresoc.v:49740$3075_Y - attribute \src "libresoc.v:49742.18-49742.100" - wire $and$libresoc.v:49742$3077_Y - attribute \src "libresoc.v:49743.18-49743.149" - wire width 3 $and$libresoc.v:49743$3078_Y - attribute \src "libresoc.v:49745.18-49745.119" - wire width 3 $and$libresoc.v:49745$3080_Y - attribute \src "libresoc.v:49748.18-49748.116" - wire $and$libresoc.v:49748$3083_Y - attribute \src "libresoc.v:49752.17-49752.123" - wire $and$libresoc.v:49752$3087_Y - attribute \src "libresoc.v:49754.18-49754.113" - wire $and$libresoc.v:49754$3089_Y - attribute \src "libresoc.v:49755.18-49755.125" - wire width 3 $and$libresoc.v:49755$3090_Y - attribute \src "libresoc.v:49757.18-49757.112" - wire $and$libresoc.v:49757$3092_Y - attribute \src "libresoc.v:49759.18-49759.125" - wire $and$libresoc.v:49759$3094_Y - attribute \src "libresoc.v:49760.18-49760.125" - wire $and$libresoc.v:49760$3095_Y - attribute \src "libresoc.v:49761.18-49761.117" - wire $and$libresoc.v:49761$3096_Y - attribute \src "libresoc.v:49766.18-49766.129" - wire $and$libresoc.v:49766$3101_Y - attribute \src "libresoc.v:49767.18-49767.124" - wire width 3 $and$libresoc.v:49767$3102_Y - attribute \src "libresoc.v:49770.18-49770.116" - wire $and$libresoc.v:49770$3105_Y - attribute \src "libresoc.v:49771.18-49771.122" - wire $and$libresoc.v:49771$3106_Y - attribute \src "libresoc.v:49772.18-49772.119" - wire $and$libresoc.v:49772$3107_Y - attribute \src "libresoc.v:49780.18-49780.133" - wire $and$libresoc.v:49780$3115_Y - attribute \src "libresoc.v:49781.18-49781.131" - wire $and$libresoc.v:49781$3116_Y - attribute \src "libresoc.v:49782.18-49782.182" - wire width 6 $and$libresoc.v:49782$3117_Y - attribute \src "libresoc.v:49783.18-49783.113" - wire width 6 $and$libresoc.v:49783$3118_Y - attribute \src "libresoc.v:49756.18-49756.113" - wire $eq$libresoc.v:49756$3091_Y - attribute \src "libresoc.v:49758.18-49758.119" - wire $eq$libresoc.v:49758$3093_Y - attribute \src "libresoc.v:49739.18-49739.97" - wire $not$libresoc.v:49739$3074_Y - attribute \src "libresoc.v:49741.18-49741.99" - wire $not$libresoc.v:49741$3076_Y - attribute \src "libresoc.v:49744.18-49744.113" - wire width 3 $not$libresoc.v:49744$3079_Y - attribute \src "libresoc.v:49747.18-49747.106" - wire $not$libresoc.v:49747$3082_Y - attribute \src "libresoc.v:49753.18-49753.119" - wire $not$libresoc.v:49753$3088_Y - attribute \src "libresoc.v:49768.17-49768.113" - wire width 6 $not$libresoc.v:49768$3103_Y - attribute \src "libresoc.v:49784.18-49784.114" - wire width 6 $not$libresoc.v:49784$3119_Y - attribute \src "libresoc.v:49751.18-49751.112" - wire $or$libresoc.v:49751$3086_Y - attribute \src "libresoc.v:49762.18-49762.122" - wire $or$libresoc.v:49762$3097_Y - attribute \src "libresoc.v:49763.18-49763.124" - wire $or$libresoc.v:49763$3098_Y - attribute \src "libresoc.v:49764.18-49764.155" - wire width 3 $or$libresoc.v:49764$3099_Y - attribute \src "libresoc.v:49765.18-49765.194" - wire width 6 $or$libresoc.v:49765$3100_Y - attribute \src "libresoc.v:49769.18-49769.120" - wire width 3 $or$libresoc.v:49769$3104_Y - attribute \src "libresoc.v:49779.17-49779.117" - wire width 6 $or$libresoc.v:49779$3114_Y - attribute \src "libresoc.v:49728.17-49728.104" - wire $reduce_and$libresoc.v:49728$3063_Y - attribute \src "libresoc.v:49746.18-49746.106" - wire $reduce_or$libresoc.v:49746$3081_Y - attribute \src "libresoc.v:49749.18-49749.113" - wire $reduce_or$libresoc.v:49749$3084_Y - attribute \src "libresoc.v:49750.18-49750.112" - wire $reduce_or$libresoc.v:49750$3085_Y - attribute \src "libresoc.v:49773.18-49773.118" - wire width 64 $ternary$libresoc.v:49773$3108_Y - attribute \src "libresoc.v:49774.18-49774.118" - wire width 64 $ternary$libresoc.v:49774$3109_Y - attribute \src "libresoc.v:49775.18-49775.118" - wire width 32 $ternary$libresoc.v:49775$3110_Y - attribute \src "libresoc.v:49776.18-49776.118" - wire width 4 $ternary$libresoc.v:49776$3111_Y - attribute \src "libresoc.v:49777.18-49777.118" - wire width 4 $ternary$libresoc.v:49777$3112_Y - attribute \src "libresoc.v:49778.18-49778.118" - wire width 4 $ternary$libresoc.v:49778$3113_Y + attribute \src "libresoc.v:50326.18-50326.112" + wire width 6 $and$libresoc.v:50326$3064_Y + attribute \src "libresoc.v:50327.19-50327.125" + wire $and$libresoc.v:50327$3065_Y + attribute \src "libresoc.v:50328.19-50328.125" + wire $and$libresoc.v:50328$3066_Y + attribute \src "libresoc.v:50329.19-50329.125" + wire $and$libresoc.v:50329$3067_Y + attribute \src "libresoc.v:50330.19-50330.141" + wire width 3 $and$libresoc.v:50330$3068_Y + attribute \src "libresoc.v:50331.19-50331.121" + wire width 3 $and$libresoc.v:50331$3069_Y + attribute \src "libresoc.v:50332.19-50332.127" + wire $and$libresoc.v:50332$3070_Y + attribute \src "libresoc.v:50333.19-50333.127" + wire $and$libresoc.v:50333$3071_Y + attribute \src "libresoc.v:50334.19-50334.127" + wire $and$libresoc.v:50334$3072_Y + attribute \src "libresoc.v:50335.18-50335.110" + wire $and$libresoc.v:50335$3073_Y + attribute \src "libresoc.v:50337.18-50337.98" + wire $and$libresoc.v:50337$3075_Y + attribute \src "libresoc.v:50339.18-50339.100" + wire $and$libresoc.v:50339$3077_Y + attribute \src "libresoc.v:50340.18-50340.149" + wire width 3 $and$libresoc.v:50340$3078_Y + attribute \src "libresoc.v:50342.18-50342.119" + wire width 3 $and$libresoc.v:50342$3080_Y + attribute \src "libresoc.v:50345.18-50345.116" + wire $and$libresoc.v:50345$3083_Y + attribute \src "libresoc.v:50349.17-50349.123" + wire $and$libresoc.v:50349$3087_Y + attribute \src "libresoc.v:50351.18-50351.113" + wire $and$libresoc.v:50351$3089_Y + attribute \src "libresoc.v:50352.18-50352.125" + wire width 3 $and$libresoc.v:50352$3090_Y + attribute \src "libresoc.v:50354.18-50354.112" + wire $and$libresoc.v:50354$3092_Y + attribute \src "libresoc.v:50356.18-50356.125" + wire $and$libresoc.v:50356$3094_Y + attribute \src "libresoc.v:50357.18-50357.125" + wire $and$libresoc.v:50357$3095_Y + attribute \src "libresoc.v:50358.18-50358.117" + wire $and$libresoc.v:50358$3096_Y + attribute \src "libresoc.v:50363.18-50363.129" + wire $and$libresoc.v:50363$3101_Y + attribute \src "libresoc.v:50364.18-50364.124" + wire width 3 $and$libresoc.v:50364$3102_Y + attribute \src "libresoc.v:50367.18-50367.116" + wire $and$libresoc.v:50367$3105_Y + attribute \src "libresoc.v:50368.18-50368.122" + wire $and$libresoc.v:50368$3106_Y + attribute \src "libresoc.v:50369.18-50369.119" + wire $and$libresoc.v:50369$3107_Y + attribute \src "libresoc.v:50377.18-50377.133" + wire $and$libresoc.v:50377$3115_Y + attribute \src "libresoc.v:50378.18-50378.131" + wire $and$libresoc.v:50378$3116_Y + attribute \src "libresoc.v:50379.18-50379.182" + wire width 6 $and$libresoc.v:50379$3117_Y + attribute \src "libresoc.v:50380.18-50380.113" + wire width 6 $and$libresoc.v:50380$3118_Y + attribute \src "libresoc.v:50353.18-50353.113" + wire $eq$libresoc.v:50353$3091_Y + attribute \src "libresoc.v:50355.18-50355.119" + wire $eq$libresoc.v:50355$3093_Y + attribute \src "libresoc.v:50336.18-50336.97" + wire $not$libresoc.v:50336$3074_Y + attribute \src "libresoc.v:50338.18-50338.99" + wire $not$libresoc.v:50338$3076_Y + attribute \src "libresoc.v:50341.18-50341.113" + wire width 3 $not$libresoc.v:50341$3079_Y + attribute \src "libresoc.v:50344.18-50344.106" + wire $not$libresoc.v:50344$3082_Y + attribute \src "libresoc.v:50350.18-50350.119" + wire $not$libresoc.v:50350$3088_Y + attribute \src "libresoc.v:50365.17-50365.113" + wire width 6 $not$libresoc.v:50365$3103_Y + attribute \src "libresoc.v:50381.18-50381.114" + wire width 6 $not$libresoc.v:50381$3119_Y + attribute \src "libresoc.v:50348.18-50348.112" + wire $or$libresoc.v:50348$3086_Y + attribute \src "libresoc.v:50359.18-50359.122" + wire $or$libresoc.v:50359$3097_Y + attribute \src "libresoc.v:50360.18-50360.124" + wire $or$libresoc.v:50360$3098_Y + attribute \src "libresoc.v:50361.18-50361.155" + wire width 3 $or$libresoc.v:50361$3099_Y + attribute \src "libresoc.v:50362.18-50362.194" + wire width 6 $or$libresoc.v:50362$3100_Y + attribute \src "libresoc.v:50366.18-50366.120" + wire width 3 $or$libresoc.v:50366$3104_Y + attribute \src "libresoc.v:50376.17-50376.117" + wire width 6 $or$libresoc.v:50376$3114_Y + attribute \src "libresoc.v:50325.17-50325.104" + wire $reduce_and$libresoc.v:50325$3063_Y + attribute \src "libresoc.v:50343.18-50343.106" + wire $reduce_or$libresoc.v:50343$3081_Y + attribute \src "libresoc.v:50346.18-50346.113" + wire $reduce_or$libresoc.v:50346$3084_Y + attribute \src "libresoc.v:50347.18-50347.112" + wire $reduce_or$libresoc.v:50347$3085_Y + attribute \src "libresoc.v:50370.18-50370.118" + wire width 64 $ternary$libresoc.v:50370$3108_Y + attribute \src "libresoc.v:50371.18-50371.118" + wire width 64 $ternary$libresoc.v:50371$3109_Y + attribute \src "libresoc.v:50372.18-50372.118" + wire width 32 $ternary$libresoc.v:50372$3110_Y + attribute \src "libresoc.v:50373.18-50373.118" + wire width 4 $ternary$libresoc.v:50373$3111_Y + attribute \src "libresoc.v:50374.18-50374.118" + wire width 4 $ternary$libresoc.v:50374$3112_Y + attribute \src "libresoc.v:50375.18-50375.118" + wire width 4 $ternary$libresoc.v:50375$3113_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -86720,13 +87326,13 @@ module \cr0 wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 3 \$21 @@ -86790,19 +87396,19 @@ module \cr0 wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 6 \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 32 \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 4 \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 4 \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 4 \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$89 @@ -86818,13 +87424,13 @@ module \cr0 wire width 6 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_cr0_cr_a @@ -86835,22 +87441,24 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_cr0_cr_c attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_cr0_cr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_cr0_cr_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_cr0_cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_cr0_cr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_cr0_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -86929,6 +87537,7 @@ module \cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_cr0_cr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -86937,15 +87546,15 @@ module \cr0 wire width 32 \alu_cr0_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \alu_cr0_full_cr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_cr0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_cr0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_cr0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_cr0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_cr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_cr0_ra @@ -86953,35 +87562,35 @@ module \cr0 wire width 64 \alu_cr0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 3 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \cr_a_ok @@ -87039,35 +87648,37 @@ module \cr0 wire width 4 output 23 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 20 \full_cr_ok - attribute \src "libresoc.v:49192.7-49192.15" + attribute \src "libresoc.v:49783.7-49783.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 16 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_cr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" @@ -87144,6 +87755,7 @@ module \cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -87152,15 +87764,15 @@ module \cr0 wire width 3 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -87168,23 +87780,23 @@ module \cr0 wire width 6 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -87200,44 +87812,44 @@ module \cr0 wire width 4 input 14 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 15 \src6_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 32 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 32 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:49729$3064 + cell $and $and$libresoc.v:50326$3064 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87245,10 +87857,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:49729$3064_Y + connect \Y $and$libresoc.v:50326$3064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:49730$3065 + cell $and $and$libresoc.v:50327$3065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87256,10 +87868,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:49730$3065_Y + connect \Y $and$libresoc.v:50327$3065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:49731$3066 + cell $and $and$libresoc.v:50328$3066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87267,10 +87879,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:49731$3066_Y + connect \Y $and$libresoc.v:50328$3066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:49732$3067 + cell $and $and$libresoc.v:50329$3067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87278,10 +87890,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:49732$3067_Y + connect \Y $and$libresoc.v:50329$3067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:49733$3068 + cell $and $and$libresoc.v:50330$3068 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87289,10 +87901,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:49733$3068_Y + connect \Y $and$libresoc.v:50330$3068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:49734$3069 + cell $and $and$libresoc.v:50331$3069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87300,10 +87912,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:49734$3069_Y + connect \Y $and$libresoc.v:50331$3069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:49735$3070 + cell $and $and$libresoc.v:50332$3070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87311,10 +87923,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:49735$3070_Y + connect \Y $and$libresoc.v:50332$3070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:49736$3071 + cell $and $and$libresoc.v:50333$3071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87322,10 +87934,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:49736$3071_Y + connect \Y $and$libresoc.v:50333$3071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:49737$3072 + cell $and $and$libresoc.v:50334$3072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87333,10 +87945,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:49737$3072_Y + connect \Y $and$libresoc.v:50334$3072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:49738$3073 + cell $and $and$libresoc.v:50335$3073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87344,10 +87956,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:49738$3073_Y + connect \Y $and$libresoc.v:50335$3073_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:49740$3075 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:50337$3075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87355,10 +87967,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:49740$3075_Y + connect \Y $and$libresoc.v:50337$3075_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:49742$3077 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:50339$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87366,10 +87978,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:49742$3077_Y + connect \Y $and$libresoc.v:50339$3077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:49743$3078 + cell $and $and$libresoc.v:50340$3078 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87377,10 +87989,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:49743$3078_Y + connect \Y $and$libresoc.v:50340$3078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:49745$3080 + cell $and $and$libresoc.v:50342$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87388,10 +88000,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:49745$3080_Y + connect \Y $and$libresoc.v:50342$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:49748$3083 + cell $and $and$libresoc.v:50345$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87399,10 +88011,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:49748$3083_Y + connect \Y $and$libresoc.v:50345$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:49752$3087 + cell $and $and$libresoc.v:50349$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87410,10 +88022,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:49752$3087_Y + connect \Y $and$libresoc.v:50349$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:49754$3089 + cell $and $and$libresoc.v:50351$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87421,10 +88033,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:49754$3089_Y + connect \Y $and$libresoc.v:50351$3089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:49755$3090 + cell $and $and$libresoc.v:50352$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87432,10 +88044,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:49755$3090_Y + connect \Y $and$libresoc.v:50352$3090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:49757$3092 + cell $and $and$libresoc.v:50354$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87443,10 +88055,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:49757$3092_Y + connect \Y $and$libresoc.v:50354$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:49759$3094 + cell $and $and$libresoc.v:50356$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87454,10 +88066,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:49759$3094_Y + connect \Y $and$libresoc.v:50356$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:49760$3095 + cell $and $and$libresoc.v:50357$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87465,10 +88077,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:49760$3095_Y + connect \Y $and$libresoc.v:50357$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:49761$3096 + cell $and $and$libresoc.v:50358$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87476,10 +88088,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:49761$3096_Y + connect \Y $and$libresoc.v:50358$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:49766$3101 + cell $and $and$libresoc.v:50363$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87487,10 +88099,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:49766$3101_Y + connect \Y $and$libresoc.v:50363$3101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:49767$3102 + cell $and $and$libresoc.v:50364$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87498,10 +88110,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:49767$3102_Y + connect \Y $and$libresoc.v:50364$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:49770$3105 + cell $and $and$libresoc.v:50367$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87509,10 +88121,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:49770$3105_Y + connect \Y $and$libresoc.v:50367$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:49771$3106 + cell $and $and$libresoc.v:50368$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87520,10 +88132,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:49771$3106_Y + connect \Y $and$libresoc.v:50368$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:49772$3107 + cell $and $and$libresoc.v:50369$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87531,10 +88143,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:49772$3107_Y + connect \Y $and$libresoc.v:50369$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:49780$3115 + cell $and $and$libresoc.v:50377$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87542,10 +88154,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:49780$3115_Y + connect \Y $and$libresoc.v:50377$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:49781$3116 + cell $and $and$libresoc.v:50378$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87553,10 +88165,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:49781$3116_Y + connect \Y $and$libresoc.v:50378$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:49782$3117 + cell $and $and$libresoc.v:50379$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87564,10 +88176,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:49782$3117_Y + connect \Y $and$libresoc.v:50379$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:49783$3118 + cell $and $and$libresoc.v:50380$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87575,10 +88187,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:49783$3118_Y + connect \Y $and$libresoc.v:50380$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:49756$3091 + cell $eq $eq$libresoc.v:50353$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87586,10 +88198,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:49756$3091_Y + connect \Y $eq$libresoc.v:50353$3091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:49758$3093 + cell $eq $eq$libresoc.v:50355$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87597,66 +88209,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:49758$3093_Y + connect \Y $eq$libresoc.v:50355$3093_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:49739$3074 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:50336$3074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:49739$3074_Y + connect \Y $not$libresoc.v:50336$3074_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:49741$3076 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:50338$3076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:49741$3076_Y + connect \Y $not$libresoc.v:50338$3076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:49744$3079 + cell $not $not$libresoc.v:50341$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:49744$3079_Y + connect \Y $not$libresoc.v:50341$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:49747$3082 + cell $not $not$libresoc.v:50344$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:49747$3082_Y + connect \Y $not$libresoc.v:50344$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:49753$3088 + cell $not $not$libresoc.v:50350$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:49753$3088_Y + connect \Y $not$libresoc.v:50350$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:49768$3103 + cell $not $not$libresoc.v:50365$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:49768$3103_Y + connect \Y $not$libresoc.v:50365$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:49784$3119 + cell $not $not$libresoc.v:50381$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:49784$3119_Y + connect \Y $not$libresoc.v:50381$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:49751$3086 + cell $or $or$libresoc.v:50348$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87664,10 +88276,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:49751$3086_Y + connect \Y $or$libresoc.v:50348$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:49762$3097 + cell $or $or$libresoc.v:50359$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87675,10 +88287,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:49762$3097_Y + connect \Y $or$libresoc.v:50359$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:49763$3098 + cell $or $or$libresoc.v:50360$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87686,10 +88298,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:49763$3098_Y + connect \Y $or$libresoc.v:50360$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:49764$3099 + cell $or $or$libresoc.v:50361$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87697,10 +88309,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:49764$3099_Y + connect \Y $or$libresoc.v:50361$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:49765$3100 + cell $or $or$libresoc.v:50362$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87708,10 +88320,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:49765$3100_Y + connect \Y $or$libresoc.v:50362$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:49769$3104 + cell $or $or$libresoc.v:50366$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87719,10 +88331,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:49769$3104_Y + connect \Y $or$libresoc.v:50366$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:49779$3114 + cell $or $or$libresoc.v:50376$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87730,90 +88342,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:49779$3114_Y + connect \Y $or$libresoc.v:50376$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:49728$3063 + cell $reduce_and $reduce_and$libresoc.v:50325$3063 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:49728$3063_Y + connect \Y $reduce_and$libresoc.v:50325$3063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:49746$3081 + cell $reduce_or $reduce_or$libresoc.v:50343$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:49746$3081_Y + connect \Y $reduce_or$libresoc.v:50343$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:49749$3084 + cell $reduce_or $reduce_or$libresoc.v:50346$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:49749$3084_Y + connect \Y $reduce_or$libresoc.v:50346$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:49750$3085 + cell $reduce_or $reduce_or$libresoc.v:50347$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:49750$3085_Y + connect \Y $reduce_or$libresoc.v:50347$3085_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49773$3108 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50370$3108 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:49773$3108_Y + connect \Y $ternary$libresoc.v:50370$3108_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49774$3109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50371$3109 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:49774$3109_Y + connect \Y $ternary$libresoc.v:50371$3109_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49775$3110 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50372$3110 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:49775$3110_Y + connect \Y $ternary$libresoc.v:50372$3110_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49776$3111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50373$3111 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:49776$3111_Y + connect \Y $ternary$libresoc.v:50373$3111_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49777$3112 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50374$3112 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:49777$3112_Y + connect \Y $ternary$libresoc.v:50374$3112_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49778$3113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50375$3113 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:49778$3113_Y + connect \Y $ternary$libresoc.v:50375$3113_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49845.11-49867.4" + attribute \src "libresoc.v:50442.11-50464.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87838,7 +88450,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:49868.14-49874.4" + attribute \src "libresoc.v:50465.14-50471.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87847,7 +88459,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:49875.15-49881.4" + attribute \src "libresoc.v:50472.15-50478.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87856,7 +88468,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:49882.14-49888.4" + attribute \src "libresoc.v:50479.14-50485.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87865,7 +88477,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:49889.14-49895.4" + attribute \src "libresoc.v:50486.14-50492.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87874,7 +88486,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:49896.14-49902.4" + attribute \src "libresoc.v:50493.14-50499.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87883,7 +88495,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:49903.14-49908.4" + attribute \src "libresoc.v:50500.14-50505.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87891,7 +88503,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:49909.14-49915.4" + attribute \src "libresoc.v:50506.14-50512.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87899,472 +88511,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49192.7-49192.20" - process $proc$libresoc.v:49192$3242 + attribute \src "libresoc.v:49783.7-49783.20" + process $proc$libresoc.v:49783$3242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49310.7-49310.24" - process $proc$libresoc.v:49310$3243 + attribute \src "libresoc.v:49901.7-49901.24" + process $proc$libresoc.v:49901$3243 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:49339.14-49339.46" - process $proc$libresoc.v:49339$3244 + attribute \src "libresoc.v:49932.14-49932.47" + process $proc$libresoc.v:49932$3244 assign { } { } - assign $1\alu_cr0_cr_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[11:0] + update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:49343.14-49343.41" - process $proc$libresoc.v:49343$3245 + attribute \src "libresoc.v:49936.14-49936.41" + process $proc$libresoc.v:49936$3245 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:49421.13-49421.45" - process $proc$libresoc.v:49421$3246 + attribute \src "libresoc.v:50015.13-50015.45" + process $proc$libresoc.v:50015$3246 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:49445.7-49445.26" - process $proc$libresoc.v:49445$3247 + attribute \src "libresoc.v:50039.7-50039.26" + process $proc$libresoc.v:50039$3247 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:49453.7-49453.25" - process $proc$libresoc.v:49453$3248 + attribute \src "libresoc.v:50047.7-50047.25" + process $proc$libresoc.v:50047$3248 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:49465.7-49465.27" - process $proc$libresoc.v:49465$3249 + attribute \src "libresoc.v:50059.7-50059.27" + process $proc$libresoc.v:50059$3249 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:49499.14-49499.47" - process $proc$libresoc.v:49499$3250 + attribute \src "libresoc.v:50093.14-50093.47" + process $proc$libresoc.v:50093$3250 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:49503.7-49503.27" - process $proc$libresoc.v:49503$3251 + attribute \src "libresoc.v:50097.7-50097.27" + process $proc$libresoc.v:50097$3251 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:49507.14-49507.38" - process $proc$libresoc.v:49507$3252 + attribute \src "libresoc.v:50101.14-50101.38" + process $proc$libresoc.v:50101$3252 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:49511.7-49511.33" - process $proc$libresoc.v:49511$3253 + attribute \src "libresoc.v:50105.7-50105.33" + process $proc$libresoc.v:50105$3253 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:49515.13-49515.33" - process $proc$libresoc.v:49515$3254 + attribute \src "libresoc.v:50109.13-50109.33" + process $proc$libresoc.v:50109$3254 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:49519.7-49519.30" - process $proc$libresoc.v:49519$3255 + attribute \src "libresoc.v:50113.7-50113.30" + process $proc$libresoc.v:50113$3255 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:49538.7-49538.25" - process $proc$libresoc.v:49538$3256 + attribute \src "libresoc.v:50132.7-50132.25" + process $proc$libresoc.v:50132$3256 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:49542.7-49542.25" - process $proc$libresoc.v:49542$3257 + attribute \src "libresoc.v:50136.7-50136.25" + process $proc$libresoc.v:50136$3257 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:49639.13-49639.30" - process $proc$libresoc.v:49639$3258 + attribute \src "libresoc.v:50236.13-50236.30" + process $proc$libresoc.v:50236$3258 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:49647.13-49647.31" - process $proc$libresoc.v:49647$3259 + attribute \src "libresoc.v:50244.13-50244.31" + process $proc$libresoc.v:50244$3259 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:49651.13-49651.31" - process $proc$libresoc.v:49651$3260 + attribute \src "libresoc.v:50248.13-50248.31" + process $proc$libresoc.v:50248$3260 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:49663.7-49663.26" - process $proc$libresoc.v:49663$3261 + attribute \src "libresoc.v:50260.7-50260.26" + process $proc$libresoc.v:50260$3261 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:49667.7-49667.26" - process $proc$libresoc.v:49667$3262 + attribute \src "libresoc.v:50264.7-50264.26" + process $proc$libresoc.v:50264$3262 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:49671.7-49671.25" - process $proc$libresoc.v:49671$3263 + attribute \src "libresoc.v:50268.7-50268.25" + process $proc$libresoc.v:50268$3263 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:49675.7-49675.25" - process $proc$libresoc.v:49675$3264 + attribute \src "libresoc.v:50272.7-50272.25" + process $proc$libresoc.v:50272$3264 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:49695.13-49695.32" - process $proc$libresoc.v:49695$3265 + attribute \src "libresoc.v:50292.13-50292.32" + process $proc$libresoc.v:50292$3265 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:49699.13-49699.32" - process $proc$libresoc.v:49699$3266 + attribute \src "libresoc.v:50296.13-50296.32" + process $proc$libresoc.v:50296$3266 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:49703.14-49703.43" - process $proc$libresoc.v:49703$3267 + attribute \src "libresoc.v:50300.14-50300.43" + process $proc$libresoc.v:50300$3267 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:49707.14-49707.43" - process $proc$libresoc.v:49707$3268 + attribute \src "libresoc.v:50304.14-50304.43" + process $proc$libresoc.v:50304$3268 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:49711.14-49711.28" - process $proc$libresoc.v:49711$3269 + attribute \src "libresoc.v:50308.14-50308.28" + process $proc$libresoc.v:50308$3269 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:49715.13-49715.26" - process $proc$libresoc.v:49715$3270 + attribute \src "libresoc.v:50312.13-50312.26" + process $proc$libresoc.v:50312$3270 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:49719.13-49719.26" - process $proc$libresoc.v:49719$3271 + attribute \src "libresoc.v:50316.13-50316.26" + process $proc$libresoc.v:50316$3271 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:49723.13-49723.26" - process $proc$libresoc.v:49723$3272 + attribute \src "libresoc.v:50320.13-50320.26" + process $proc$libresoc.v:50320$3272 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:49785.3-49786.39" - process $proc$libresoc.v:49785$3120 + attribute \src "libresoc.v:50382.3-50383.39" + process $proc$libresoc.v:50382$3120 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:49787.3-49788.43" - process $proc$libresoc.v:49787$3121 + attribute \src "libresoc.v:50384.3-50385.43" + process $proc$libresoc.v:50384$3121 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:49789.3-49790.29" - process $proc$libresoc.v:49789$3122 + attribute \src "libresoc.v:50386.3-50387.29" + process $proc$libresoc.v:50386$3122 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:49791.3-49792.29" - process $proc$libresoc.v:49791$3123 + attribute \src "libresoc.v:50388.3-50389.29" + process $proc$libresoc.v:50388$3123 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:49793.3-49794.29" - process $proc$libresoc.v:49793$3124 + attribute \src "libresoc.v:50390.3-50391.29" + process $proc$libresoc.v:50390$3124 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:49795.3-49796.29" - process $proc$libresoc.v:49795$3125 + attribute \src "libresoc.v:50392.3-50393.29" + process $proc$libresoc.v:50392$3125 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:49797.3-49798.29" - process $proc$libresoc.v:49797$3126 + attribute \src "libresoc.v:50394.3-50395.29" + process $proc$libresoc.v:50394$3126 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:49799.3-49800.29" - process $proc$libresoc.v:49799$3127 + attribute \src "libresoc.v:50396.3-50397.29" + process $proc$libresoc.v:50396$3127 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:49801.3-49802.43" - process $proc$libresoc.v:49801$3128 + attribute \src "libresoc.v:50398.3-50399.43" + process $proc$libresoc.v:50398$3128 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:49803.3-49804.49" - process $proc$libresoc.v:49803$3129 + attribute \src "libresoc.v:50400.3-50401.49" + process $proc$libresoc.v:50400$3129 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:49805.3-49806.49" - process $proc$libresoc.v:49805$3130 + attribute \src "libresoc.v:50402.3-50403.49" + process $proc$libresoc.v:50402$3130 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:49807.3-49808.55" - process $proc$libresoc.v:49807$3131 + attribute \src "libresoc.v:50404.3-50405.55" + process $proc$libresoc.v:50404$3131 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:49809.3-49810.37" - process $proc$libresoc.v:49809$3132 + attribute \src "libresoc.v:50406.3-50407.37" + process $proc$libresoc.v:50406$3132 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:49811.3-49812.43" - process $proc$libresoc.v:49811$3133 + attribute \src "libresoc.v:50408.3-50409.43" + process $proc$libresoc.v:50408$3133 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:49813.3-49814.65" - process $proc$libresoc.v:49813$3134 + attribute \src "libresoc.v:50410.3-50411.65" + process $proc$libresoc.v:50410$3134 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:49815.3-49816.61" - process $proc$libresoc.v:49815$3135 + attribute \src "libresoc.v:50412.3-50413.61" + process $proc$libresoc.v:50412$3135 assign { } { } - assign $0\alu_cr0_cr_op__fn_unit[11:0] \alu_cr0_cr_op__fn_unit$next + assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk - update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[11:0] + update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:49817.3-49818.55" - process $proc$libresoc.v:49817$3136 + attribute \src "libresoc.v:50414.3-50415.55" + process $proc$libresoc.v:50414$3136 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:49819.3-49820.39" - process $proc$libresoc.v:49819$3137 + attribute \src "libresoc.v:50416.3-50417.39" + process $proc$libresoc.v:50416$3137 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:49821.3-49822.39" - process $proc$libresoc.v:49821$3138 + attribute \src "libresoc.v:50418.3-50419.39" + process $proc$libresoc.v:50418$3138 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:49823.3-49824.39" - process $proc$libresoc.v:49823$3139 + attribute \src "libresoc.v:50420.3-50421.39" + process $proc$libresoc.v:50420$3139 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:49825.3-49826.39" - process $proc$libresoc.v:49825$3140 + attribute \src "libresoc.v:50422.3-50423.39" + process $proc$libresoc.v:50422$3140 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:49827.3-49828.39" - process $proc$libresoc.v:49827$3141 + attribute \src "libresoc.v:50424.3-50425.39" + process $proc$libresoc.v:50424$3141 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:49829.3-49830.39" - process $proc$libresoc.v:49829$3142 + attribute \src "libresoc.v:50426.3-50427.39" + process $proc$libresoc.v:50426$3142 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:49831.3-49832.39" - process $proc$libresoc.v:49831$3143 + attribute \src "libresoc.v:50428.3-50429.39" + process $proc$libresoc.v:50428$3143 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:49833.3-49834.39" - process $proc$libresoc.v:49833$3144 + attribute \src "libresoc.v:50430.3-50431.39" + process $proc$libresoc.v:50430$3144 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:49835.3-49836.41" - process $proc$libresoc.v:49835$3145 + attribute \src "libresoc.v:50432.3-50433.41" + process $proc$libresoc.v:50432$3145 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:49837.3-49838.41" - process $proc$libresoc.v:49837$3146 + attribute \src "libresoc.v:50434.3-50435.41" + process $proc$libresoc.v:50434$3146 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:49839.3-49840.37" - process $proc$libresoc.v:49839$3147 + attribute \src "libresoc.v:50436.3-50437.37" + process $proc$libresoc.v:50436$3147 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:49841.3-49842.39" - process $proc$libresoc.v:49841$3148 + attribute \src "libresoc.v:50438.3-50439.39" + process $proc$libresoc.v:50438$3148 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:49843.3-49844.25" - process $proc$libresoc.v:49843$3149 + attribute \src "libresoc.v:50440.3-50441.25" + process $proc$libresoc.v:50440$3149 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:49916.3-49925.6" - process $proc$libresoc.v:49916$3150 + attribute \src "libresoc.v:50513.3-50522.6" + process $proc$libresoc.v:50513$3150 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:49917.5-49917.29" + attribute \src "libresoc.v:50514.5-50514.29" switch \initial - attribute \src "libresoc.v:49917.9-49917.17" + attribute \src "libresoc.v:50514.9-50514.17" case 1'1 case end @@ -88380,14 +88992,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:49926.3-49934.6" - process $proc$libresoc.v:49926$3151 + attribute \src "libresoc.v:50523.3-50531.6" + process $proc$libresoc.v:50523$3151 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:49927.5-49927.29" + attribute \src "libresoc.v:50524.5-50524.29" switch \initial - attribute \src "libresoc.v:49927.9-49927.17" + attribute \src "libresoc.v:50524.9-50524.17" case 1'1 case end @@ -88403,14 +89015,14 @@ module \cr0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 end - attribute \src "libresoc.v:49935.3-49943.6" - process $proc$libresoc.v:49935$3154 + attribute \src "libresoc.v:50532.3-50540.6" + process $proc$libresoc.v:50532$3154 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:49936.5-49936.29" + attribute \src "libresoc.v:50533.5-50533.29" switch \initial - attribute \src "libresoc.v:49936.9-49936.17" + attribute \src "libresoc.v:50533.9-50533.17" case 1'1 case end @@ -88426,14 +89038,14 @@ module \cr0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 end - attribute \src "libresoc.v:49944.3-49952.6" - process $proc$libresoc.v:49944$3157 + attribute \src "libresoc.v:50541.3-50549.6" + process $proc$libresoc.v:50541$3157 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:49945.5-49945.29" + attribute \src "libresoc.v:50542.5-50542.29" switch \initial - attribute \src "libresoc.v:49945.9-49945.17" + attribute \src "libresoc.v:50542.9-50542.17" case 1'1 case end @@ -88449,14 +89061,14 @@ module \cr0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 end - attribute \src "libresoc.v:49953.3-49961.6" - process $proc$libresoc.v:49953$3160 + attribute \src "libresoc.v:50550.3-50558.6" + process $proc$libresoc.v:50550$3160 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:49954.5-49954.29" + attribute \src "libresoc.v:50551.5-50551.29" switch \initial - attribute \src "libresoc.v:49954.9-49954.17" + attribute \src "libresoc.v:50551.9-50551.17" case 1'1 case end @@ -88472,14 +89084,14 @@ module \cr0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 end - attribute \src "libresoc.v:49962.3-49970.6" - process $proc$libresoc.v:49962$3163 + attribute \src "libresoc.v:50559.3-50567.6" + process $proc$libresoc.v:50559$3163 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:49963.5-49963.29" + attribute \src "libresoc.v:50560.5-50560.29" switch \initial - attribute \src "libresoc.v:49963.9-49963.17" + attribute \src "libresoc.v:50560.9-50560.17" case 1'1 case end @@ -88495,14 +89107,14 @@ module \cr0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 end - attribute \src "libresoc.v:49971.3-49979.6" - process $proc$libresoc.v:49971$3166 + attribute \src "libresoc.v:50568.3-50576.6" + process $proc$libresoc.v:50568$3166 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:49972.5-49972.29" + attribute \src "libresoc.v:50569.5-50569.29" switch \initial - attribute \src "libresoc.v:49972.9-49972.17" + attribute \src "libresoc.v:50569.9-50569.17" case 1'1 case end @@ -88518,14 +89130,14 @@ module \cr0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 end - attribute \src "libresoc.v:49980.3-49988.6" - process $proc$libresoc.v:49980$3169 + attribute \src "libresoc.v:50577.3-50585.6" + process $proc$libresoc.v:50577$3169 assign { } { } assign { } { } assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:49981.5-49981.29" + attribute \src "libresoc.v:50578.5-50578.29" switch \initial - attribute \src "libresoc.v:49981.9-49981.17" + attribute \src "libresoc.v:50578.9-50578.17" case 1'1 case end @@ -88541,14 +89153,14 @@ module \cr0 sync always update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 end - attribute \src "libresoc.v:49989.3-49997.6" - process $proc$libresoc.v:49989$3172 + attribute \src "libresoc.v:50586.3-50594.6" + process $proc$libresoc.v:50586$3172 assign { } { } assign { } { } assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:49990.5-49990.29" + attribute \src "libresoc.v:50587.5-50587.29" switch \initial - attribute \src "libresoc.v:49990.9-49990.17" + attribute \src "libresoc.v:50587.9-50587.17" case 1'1 case end @@ -88564,14 +89176,14 @@ module \cr0 sync always update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 end - attribute \src "libresoc.v:49998.3-50006.6" - process $proc$libresoc.v:49998$3175 + attribute \src "libresoc.v:50595.3-50603.6" + process $proc$libresoc.v:50595$3175 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:49999.5-49999.29" + attribute \src "libresoc.v:50596.5-50596.29" switch \initial - attribute \src "libresoc.v:49999.9-49999.17" + attribute \src "libresoc.v:50596.9-50596.17" case 1'1 case end @@ -88587,14 +89199,14 @@ module \cr0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 end - attribute \src "libresoc.v:50007.3-50015.6" - process $proc$libresoc.v:50007$3178 + attribute \src "libresoc.v:50604.3-50612.6" + process $proc$libresoc.v:50604$3178 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50008.5-50008.29" + attribute \src "libresoc.v:50605.5-50605.29" switch \initial - attribute \src "libresoc.v:50008.9-50008.17" + attribute \src "libresoc.v:50605.9-50605.17" case 1'1 case end @@ -88610,20 +89222,20 @@ module \cr0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 end - attribute \src "libresoc.v:50016.3-50027.6" - process $proc$libresoc.v:50016$3181 + attribute \src "libresoc.v:50613.3-50624.6" + process $proc$libresoc.v:50613$3181 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_cr0_cr_op__fn_unit$next[11:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3185 + assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:50017.5-50017.29" + attribute \src "libresoc.v:50614.5-50614.29" switch \initial - attribute \src "libresoc.v:50017.9-50017.17" + attribute \src "libresoc.v:50614.9-50614.17" case 1'1 case end @@ -88634,19 +89246,19 @@ module \cr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } case - assign $1\alu_cr0_cr_op__fn_unit$next[11:0]$3185 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 \alu_cr0_cr_op__fn_unit assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type end sync always - update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[11:0]$3182 + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 end - attribute \src "libresoc.v:50028.3-50049.6" - process $proc$libresoc.v:50028$3188 + attribute \src "libresoc.v:50625.3-50646.6" + process $proc$libresoc.v:50625$3188 assign { } { } assign { } { } assign { } { } @@ -88656,9 +89268,9 @@ module \cr0 assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 assign { } { } assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50029.5-50029.29" + attribute \src "libresoc.v:50626.5-50626.29" switch \initial - attribute \src "libresoc.v:50029.9-50029.17" + attribute \src "libresoc.v:50626.9-50626.17" case 1'1 case end @@ -88697,8 +89309,8 @@ module \cr0 update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 end - attribute \src "libresoc.v:50050.3-50071.6" - process $proc$libresoc.v:50050$3196 + attribute \src "libresoc.v:50647.3-50668.6" + process $proc$libresoc.v:50647$3196 assign { } { } assign { } { } assign { } { } @@ -88708,9 +89320,9 @@ module \cr0 assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 assign { } { } assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50051.5-50051.29" + attribute \src "libresoc.v:50648.5-50648.29" switch \initial - attribute \src "libresoc.v:50051.9-50051.17" + attribute \src "libresoc.v:50648.9-50648.17" case 1'1 case end @@ -88749,8 +89361,8 @@ module \cr0 update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 end - attribute \src "libresoc.v:50072.3-50093.6" - process $proc$libresoc.v:50072$3204 + attribute \src "libresoc.v:50669.3-50690.6" + process $proc$libresoc.v:50669$3204 assign { } { } assign { } { } assign { } { } @@ -88760,9 +89372,9 @@ module \cr0 assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 assign { } { } assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50073.5-50073.29" + attribute \src "libresoc.v:50670.5-50670.29" switch \initial - attribute \src "libresoc.v:50073.9-50073.17" + attribute \src "libresoc.v:50670.9-50670.17" case 1'1 case end @@ -88801,18 +89413,18 @@ module \cr0 update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 end - attribute \src "libresoc.v:50094.3-50103.6" - process $proc$libresoc.v:50094$3212 + attribute \src "libresoc.v:50691.3-50700.6" + process $proc$libresoc.v:50691$3212 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50095.5-50095.29" + attribute \src "libresoc.v:50692.5-50692.29" switch \initial - attribute \src "libresoc.v:50095.9-50095.17" + attribute \src "libresoc.v:50692.9-50692.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -88824,18 +89436,18 @@ module \cr0 sync always update \src_r0$next $0\src_r0$next[63:0]$3213 end - attribute \src "libresoc.v:50104.3-50113.6" - process $proc$libresoc.v:50104$3215 + attribute \src "libresoc.v:50701.3-50710.6" + process $proc$libresoc.v:50701$3215 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50105.5-50105.29" + attribute \src "libresoc.v:50702.5-50702.29" switch \initial - attribute \src "libresoc.v:50105.9-50105.17" + attribute \src "libresoc.v:50702.9-50702.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -88847,18 +89459,18 @@ module \cr0 sync always update \src_r1$next $0\src_r1$next[63:0]$3216 end - attribute \src "libresoc.v:50114.3-50123.6" - process $proc$libresoc.v:50114$3218 + attribute \src "libresoc.v:50711.3-50720.6" + process $proc$libresoc.v:50711$3218 assign { } { } assign { } { } assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50115.5-50115.29" + attribute \src "libresoc.v:50712.5-50712.29" switch \initial - attribute \src "libresoc.v:50115.9-50115.17" + attribute \src "libresoc.v:50712.9-50712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -88870,18 +89482,18 @@ module \cr0 sync always update \src_r2$next $0\src_r2$next[31:0]$3219 end - attribute \src "libresoc.v:50124.3-50133.6" - process $proc$libresoc.v:50124$3221 + attribute \src "libresoc.v:50721.3-50730.6" + process $proc$libresoc.v:50721$3221 assign { } { } assign { } { } assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50125.5-50125.29" + attribute \src "libresoc.v:50722.5-50722.29" switch \initial - attribute \src "libresoc.v:50125.9-50125.17" + attribute \src "libresoc.v:50722.9-50722.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -88893,18 +89505,18 @@ module \cr0 sync always update \src_r3$next $0\src_r3$next[3:0]$3222 end - attribute \src "libresoc.v:50134.3-50143.6" - process $proc$libresoc.v:50134$3224 + attribute \src "libresoc.v:50731.3-50740.6" + process $proc$libresoc.v:50731$3224 assign { } { } assign { } { } assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50135.5-50135.29" + attribute \src "libresoc.v:50732.5-50732.29" switch \initial - attribute \src "libresoc.v:50135.9-50135.17" + attribute \src "libresoc.v:50732.9-50732.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -88916,18 +89528,18 @@ module \cr0 sync always update \src_r4$next $0\src_r4$next[3:0]$3225 end - attribute \src "libresoc.v:50144.3-50153.6" - process $proc$libresoc.v:50144$3227 + attribute \src "libresoc.v:50741.3-50750.6" + process $proc$libresoc.v:50741$3227 assign { } { } assign { } { } assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50145.5-50145.29" + attribute \src "libresoc.v:50742.5-50742.29" switch \initial - attribute \src "libresoc.v:50145.9-50145.17" + attribute \src "libresoc.v:50742.9-50742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -88939,14 +89551,14 @@ module \cr0 sync always update \src_r5$next $0\src_r5$next[3:0]$3228 end - attribute \src "libresoc.v:50154.3-50162.6" - process $proc$libresoc.v:50154$3230 + attribute \src "libresoc.v:50751.3-50759.6" + process $proc$libresoc.v:50751$3230 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50155.5-50155.29" + attribute \src "libresoc.v:50752.5-50752.29" switch \initial - attribute \src "libresoc.v:50155.9-50155.17" + attribute \src "libresoc.v:50752.9-50752.17" case 1'1 case end @@ -88962,14 +89574,14 @@ module \cr0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 end - attribute \src "libresoc.v:50163.3-50171.6" - process $proc$libresoc.v:50163$3233 + attribute \src "libresoc.v:50760.3-50768.6" + process $proc$libresoc.v:50760$3233 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50164.5-50164.29" + attribute \src "libresoc.v:50761.5-50761.29" switch \initial - attribute \src "libresoc.v:50164.9-50164.17" + attribute \src "libresoc.v:50761.9-50761.17" case 1'1 case end @@ -88985,14 +89597,14 @@ module \cr0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 end - attribute \src "libresoc.v:50172.3-50181.6" - process $proc$libresoc.v:50172$3236 + attribute \src "libresoc.v:50769.3-50778.6" + process $proc$libresoc.v:50769$3236 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50173.5-50173.29" + attribute \src "libresoc.v:50770.5-50770.29" switch \initial - attribute \src "libresoc.v:50173.9-50173.17" + attribute \src "libresoc.v:50770.9-50770.17" case 1'1 case end @@ -89008,14 +89620,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:50182.3-50191.6" - process $proc$libresoc.v:50182$3237 + attribute \src "libresoc.v:50779.3-50788.6" + process $proc$libresoc.v:50779$3237 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50183.5-50183.29" + attribute \src "libresoc.v:50780.5-50780.29" switch \initial - attribute \src "libresoc.v:50183.9-50183.17" + attribute \src "libresoc.v:50780.9-50780.17" case 1'1 case end @@ -89031,14 +89643,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:50192.3-50201.6" - process $proc$libresoc.v:50192$3238 + attribute \src "libresoc.v:50789.3-50798.6" + process $proc$libresoc.v:50789$3238 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50193.5-50193.29" + attribute \src "libresoc.v:50790.5-50790.29" switch \initial - attribute \src "libresoc.v:50193.9-50193.17" + attribute \src "libresoc.v:50790.9-50790.17" case 1'1 case end @@ -89054,14 +89666,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:50202.3-50210.6" - process $proc$libresoc.v:50202$3239 + attribute \src "libresoc.v:50799.3-50807.6" + process $proc$libresoc.v:50799$3239 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50203.5-50203.29" + attribute \src "libresoc.v:50800.5-50800.29" switch \initial - attribute \src "libresoc.v:50203.9-50203.17" + attribute \src "libresoc.v:50800.9-50800.17" case 1'1 case end @@ -89077,63 +89689,63 @@ module \cr0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 end - connect \$5 $reduce_and$libresoc.v:49728$3063_Y - connect \$99 $and$libresoc.v:49729$3064_Y - connect \$101 $and$libresoc.v:49730$3065_Y - connect \$103 $and$libresoc.v:49731$3066_Y - connect \$105 $and$libresoc.v:49732$3067_Y - connect \$107 $and$libresoc.v:49733$3068_Y - connect \$109 $and$libresoc.v:49734$3069_Y - connect \$111 $and$libresoc.v:49735$3070_Y - connect \$113 $and$libresoc.v:49736$3071_Y - connect \$115 $and$libresoc.v:49737$3072_Y - connect \$11 $and$libresoc.v:49738$3073_Y - connect \$13 $not$libresoc.v:49739$3074_Y - connect \$15 $and$libresoc.v:49740$3075_Y - connect \$17 $not$libresoc.v:49741$3076_Y - connect \$19 $and$libresoc.v:49742$3077_Y - connect \$21 $and$libresoc.v:49743$3078_Y - connect \$25 $not$libresoc.v:49744$3079_Y - connect \$27 $and$libresoc.v:49745$3080_Y - connect \$24 $reduce_or$libresoc.v:49746$3081_Y - connect \$23 $not$libresoc.v:49747$3082_Y - connect \$31 $and$libresoc.v:49748$3083_Y - connect \$33 $reduce_or$libresoc.v:49749$3084_Y - connect \$35 $reduce_or$libresoc.v:49750$3085_Y - connect \$37 $or$libresoc.v:49751$3086_Y - connect \$3 $and$libresoc.v:49752$3087_Y - connect \$39 $not$libresoc.v:49753$3088_Y - connect \$41 $and$libresoc.v:49754$3089_Y - connect \$43 $and$libresoc.v:49755$3090_Y - connect \$45 $eq$libresoc.v:49756$3091_Y - connect \$47 $and$libresoc.v:49757$3092_Y - connect \$49 $eq$libresoc.v:49758$3093_Y - connect \$51 $and$libresoc.v:49759$3094_Y - connect \$53 $and$libresoc.v:49760$3095_Y - connect \$55 $and$libresoc.v:49761$3096_Y - connect \$57 $or$libresoc.v:49762$3097_Y - connect \$59 $or$libresoc.v:49763$3098_Y - connect \$61 $or$libresoc.v:49764$3099_Y - connect \$63 $or$libresoc.v:49765$3100_Y - connect \$65 $and$libresoc.v:49766$3101_Y - connect \$67 $and$libresoc.v:49767$3102_Y - connect \$6 $not$libresoc.v:49768$3103_Y - connect \$69 $or$libresoc.v:49769$3104_Y - connect \$71 $and$libresoc.v:49770$3105_Y - connect \$73 $and$libresoc.v:49771$3106_Y - connect \$75 $and$libresoc.v:49772$3107_Y - connect \$77 $ternary$libresoc.v:49773$3108_Y - connect \$79 $ternary$libresoc.v:49774$3109_Y - connect \$81 $ternary$libresoc.v:49775$3110_Y - connect \$83 $ternary$libresoc.v:49776$3111_Y - connect \$85 $ternary$libresoc.v:49777$3112_Y - connect \$87 $ternary$libresoc.v:49778$3113_Y - connect \$8 $or$libresoc.v:49779$3114_Y - connect \$89 $and$libresoc.v:49780$3115_Y - connect \$91 $and$libresoc.v:49781$3116_Y - connect \$93 $and$libresoc.v:49782$3117_Y - connect \$95 $and$libresoc.v:49783$3118_Y - connect \$97 $not$libresoc.v:49784$3119_Y + connect \$5 $reduce_and$libresoc.v:50325$3063_Y + connect \$99 $and$libresoc.v:50326$3064_Y + connect \$101 $and$libresoc.v:50327$3065_Y + connect \$103 $and$libresoc.v:50328$3066_Y + connect \$105 $and$libresoc.v:50329$3067_Y + connect \$107 $and$libresoc.v:50330$3068_Y + connect \$109 $and$libresoc.v:50331$3069_Y + connect \$111 $and$libresoc.v:50332$3070_Y + connect \$113 $and$libresoc.v:50333$3071_Y + connect \$115 $and$libresoc.v:50334$3072_Y + connect \$11 $and$libresoc.v:50335$3073_Y + connect \$13 $not$libresoc.v:50336$3074_Y + connect \$15 $and$libresoc.v:50337$3075_Y + connect \$17 $not$libresoc.v:50338$3076_Y + connect \$19 $and$libresoc.v:50339$3077_Y + connect \$21 $and$libresoc.v:50340$3078_Y + connect \$25 $not$libresoc.v:50341$3079_Y + connect \$27 $and$libresoc.v:50342$3080_Y + connect \$24 $reduce_or$libresoc.v:50343$3081_Y + connect \$23 $not$libresoc.v:50344$3082_Y + connect \$31 $and$libresoc.v:50345$3083_Y + connect \$33 $reduce_or$libresoc.v:50346$3084_Y + connect \$35 $reduce_or$libresoc.v:50347$3085_Y + connect \$37 $or$libresoc.v:50348$3086_Y + connect \$3 $and$libresoc.v:50349$3087_Y + connect \$39 $not$libresoc.v:50350$3088_Y + connect \$41 $and$libresoc.v:50351$3089_Y + connect \$43 $and$libresoc.v:50352$3090_Y + connect \$45 $eq$libresoc.v:50353$3091_Y + connect \$47 $and$libresoc.v:50354$3092_Y + connect \$49 $eq$libresoc.v:50355$3093_Y + connect \$51 $and$libresoc.v:50356$3094_Y + connect \$53 $and$libresoc.v:50357$3095_Y + connect \$55 $and$libresoc.v:50358$3096_Y + connect \$57 $or$libresoc.v:50359$3097_Y + connect \$59 $or$libresoc.v:50360$3098_Y + connect \$61 $or$libresoc.v:50361$3099_Y + connect \$63 $or$libresoc.v:50362$3100_Y + connect \$65 $and$libresoc.v:50363$3101_Y + connect \$67 $and$libresoc.v:50364$3102_Y + connect \$6 $not$libresoc.v:50365$3103_Y + connect \$69 $or$libresoc.v:50366$3104_Y + connect \$71 $and$libresoc.v:50367$3105_Y + connect \$73 $and$libresoc.v:50368$3106_Y + connect \$75 $and$libresoc.v:50369$3107_Y + connect \$77 $ternary$libresoc.v:50370$3108_Y + connect \$79 $ternary$libresoc.v:50371$3109_Y + connect \$81 $ternary$libresoc.v:50372$3110_Y + connect \$83 $ternary$libresoc.v:50373$3111_Y + connect \$85 $ternary$libresoc.v:50374$3112_Y + connect \$87 $ternary$libresoc.v:50375$3113_Y + connect \$8 $or$libresoc.v:50376$3114_Y + connect \$89 $and$libresoc.v:50377$3115_Y + connect \$91 $and$libresoc.v:50378$3116_Y + connect \$93 $and$libresoc.v:50379$3117_Y + connect \$95 $and$libresoc.v:50380$3118_Y + connect \$97 $not$libresoc.v:50381$3119_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -89166,63 +89778,63 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:50246.1-50295.10" +attribute \src "libresoc.v:50843.1-50892.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:50247.7-50247.20" + attribute \src "libresoc.v:50844.7-50844.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50283.3-50291.6" + attribute \src "libresoc.v:50880.3-50888.6" wire $0\q_int$next[0:0]$3280 - attribute \src "libresoc.v:50281.3-50282.27" + attribute \src "libresoc.v:50878.3-50879.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:50283.3-50291.6" + attribute \src "libresoc.v:50880.3-50888.6" wire $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50265.7-50265.19" + attribute \src "libresoc.v:50862.7-50862.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:50278.17-50278.96" - wire $and$libresoc.v:50278$3275_Y - attribute \src "libresoc.v:50277.17-50277.92" - wire $not$libresoc.v:50277$3274_Y - attribute \src "libresoc.v:50280.17-50280.92" - wire $not$libresoc.v:50280$3277_Y - attribute \src "libresoc.v:50276.17-50276.98" - wire $or$libresoc.v:50276$3273_Y - attribute \src "libresoc.v:50279.17-50279.97" - wire $or$libresoc.v:50279$3276_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:50875.17-50875.96" + wire $and$libresoc.v:50875$3275_Y + attribute \src "libresoc.v:50874.17-50874.92" + wire $not$libresoc.v:50874$3274_Y + attribute \src "libresoc.v:50877.17-50877.92" + wire $not$libresoc.v:50877$3277_Y + attribute \src "libresoc.v:50873.17-50873.98" + wire $or$libresoc.v:50873$3273_Y + attribute \src "libresoc.v:50876.17-50876.97" + wire $or$libresoc.v:50876$3276_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:50247.7-50247.15" + attribute \src "libresoc.v:50844.7-50844.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:50278$3275 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:50875$3275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89230,26 +89842,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:50278$3275_Y + connect \Y $and$libresoc.v:50875$3275_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:50277$3274 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:50874$3274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:50277$3274_Y + connect \Y $not$libresoc.v:50874$3274_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:50280$3277 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:50877$3277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:50280$3277_Y + connect \Y $not$libresoc.v:50877$3277_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:50276$3273 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:50873$3273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89257,10 +89869,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:50276$3273_Y + connect \Y $or$libresoc.v:50873$3273_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:50279$3276 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:50876$3276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89268,39 +89880,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:50279$3276_Y + connect \Y $or$libresoc.v:50876$3276_Y end - attribute \src "libresoc.v:50247.7-50247.20" - process $proc$libresoc.v:50247$3282 + attribute \src "libresoc.v:50844.7-50844.20" + process $proc$libresoc.v:50844$3282 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50265.7-50265.19" - process $proc$libresoc.v:50265$3283 + attribute \src "libresoc.v:50862.7-50862.19" + process $proc$libresoc.v:50862$3283 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:50281.3-50282.27" - process $proc$libresoc.v:50281$3278 + attribute \src "libresoc.v:50878.3-50879.27" + process $proc$libresoc.v:50878$3278 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:50283.3-50291.6" - process $proc$libresoc.v:50283$3279 + attribute \src "libresoc.v:50880.3-50888.6" + process $proc$libresoc.v:50880$3279 assign { } { } assign { } { } assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50284.5-50284.29" + attribute \src "libresoc.v:50881.5-50881.29" switch \initial - attribute \src "libresoc.v:50284.9-50284.17" + attribute \src "libresoc.v:50881.9-50881.17" case 1'1 case end @@ -89316,554 +89928,570 @@ module \cyc_l sync always update \q_int$next $0\q_int$next[0:0]$3280 end - connect \$9 $or$libresoc.v:50276$3273_Y - connect \$1 $not$libresoc.v:50277$3274_Y - connect \$3 $and$libresoc.v:50278$3275_Y - connect \$5 $or$libresoc.v:50279$3276_Y - connect \$7 $not$libresoc.v:50280$3277_Y + connect \$9 $or$libresoc.v:50873$3273_Y + connect \$1 $not$libresoc.v:50874$3274_Y + connect \$3 $and$libresoc.v:50875$3275_Y + connect \$5 $or$libresoc.v:50876$3276_Y + connect \$7 $not$libresoc.v:50877$3277_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:50299.1-51013.10" +attribute \src "libresoc.v:50896.1-51628.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:50829.3-50838.6" + attribute \src "libresoc.v:51441.3-51450.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:50636.3-50645.6" + attribute \src "libresoc.v:51248.3-51257.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:50839.3-50848.6" + attribute \src "libresoc.v:51451.3-51460.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:50618.3-50635.6" + attribute \src "libresoc.v:51230.3-51247.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:50849.3-50879.6" + attribute \src "libresoc.v:51461.3-51494.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:50820.3-50828.6" - wire $0\dmi_read_log_data$next[0:0]$3397 - attribute \src "libresoc.v:50596.3-50597.51" + attribute \src "libresoc.v:51432.3-51440.6" + wire $0\dmi_read_log_data$next[0:0]$3398 + attribute \src "libresoc.v:51208.3-51209.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:50811.3-50819.6" - wire $0\dmi_read_log_data_1$next[0:0]$3394 - attribute \src "libresoc.v:50598.3-50599.55" + attribute \src "libresoc.v:51423.3-51431.6" + wire $0\dmi_read_log_data_1$next[0:0]$3395 + attribute \src "libresoc.v:51210.3-51211.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:50646.3-50654.6" - wire $0\dmi_req_i_1$next[0:0]$3360 - attribute \src "libresoc.v:50608.3-50609.39" + attribute \src "libresoc.v:51258.3-51266.6" + wire $0\dmi_req_i_1$next[0:0]$3361 + attribute \src "libresoc.v:51220.3-51221.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:50970.3-51003.6" - wire $0\do_dmi_log_rd$next[0:0]$3424 - attribute \src "libresoc.v:50610.3-50611.43" + attribute \src "libresoc.v:51585.3-51618.6" + wire $0\do_dmi_log_rd$next[0:0]$3425 + attribute \src "libresoc.v:51222.3-51223.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:50940.3-50969.6" - wire $0\do_icreset$next[0:0]$3417 - attribute \src "libresoc.v:50612.3-50613.37" + attribute \src "libresoc.v:51555.3-51584.6" + wire $0\do_icreset$next[0:0]$3418 + attribute \src "libresoc.v:51224.3-51225.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:50910.3-50939.6" - wire $0\do_reset$next[0:0]$3410 - attribute \src "libresoc.v:50614.3-50615.33" + attribute \src "libresoc.v:51525.3-51554.6" + wire $0\do_reset$next[0:0]$3411 + attribute \src "libresoc.v:51226.3-51227.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:50880.3-50909.6" - wire $0\do_step$next[0:0]$3403 - attribute \src "libresoc.v:50616.3-50617.31" + attribute \src "libresoc.v:51495.3-51524.6" + wire $0\do_step$next[0:0]$3404 + attribute \src "libresoc.v:51228.3-51229.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:50749.3-50776.6" - wire width 7 $0\gspr_index$next[6:0]$3382 - attribute \src "libresoc.v:50602.3-50603.37" + attribute \src "libresoc.v:51361.3-51388.6" + wire width 7 $0\gspr_index$next[6:0]$3383 + attribute \src "libresoc.v:51214.3-51215.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:50300.7-50300.20" + attribute \src "libresoc.v:50897.7-50897.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50777.3-50810.6" - wire width 32 $0\log_dmi_addr$next[31:0]$3388 - attribute \src "libresoc.v:50600.3-50601.41" + attribute \src "libresoc.v:51389.3-51422.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3389 + attribute \src "libresoc.v:51212.3-51213.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:50705.3-50748.6" - wire $0\stopping$next[0:0]$3373 - attribute \src "libresoc.v:50604.3-50605.33" + attribute \src "libresoc.v:51317.3-51360.6" + wire $0\stopping$next[0:0]$3374 + attribute \src "libresoc.v:51216.3-51217.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:50655.3-50704.6" - wire $0\terminated$next[0:0]$3363 - attribute \src "libresoc.v:50606.3-50607.37" + attribute \src "libresoc.v:51267.3-51316.6" + wire $0\terminated$next[0:0]$3364 + attribute \src "libresoc.v:51218.3-51219.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:50829.3-50838.6" + attribute \src "libresoc.v:51441.3-51450.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:50636.3-50645.6" + attribute \src "libresoc.v:51248.3-51257.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:50839.3-50848.6" + attribute \src "libresoc.v:51451.3-51460.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:50618.3-50635.6" + attribute \src "libresoc.v:51230.3-51247.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:50849.3-50879.6" + attribute \src "libresoc.v:51461.3-51494.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:50820.3-50828.6" - wire $1\dmi_read_log_data$next[0:0]$3398 - attribute \src "libresoc.v:50473.7-50473.31" + attribute \src "libresoc.v:51432.3-51440.6" + wire $1\dmi_read_log_data$next[0:0]$3399 + attribute \src "libresoc.v:51084.7-51084.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:50811.3-50819.6" - wire $1\dmi_read_log_data_1$next[0:0]$3395 - attribute \src "libresoc.v:50477.7-50477.33" + attribute \src "libresoc.v:51423.3-51431.6" + wire $1\dmi_read_log_data_1$next[0:0]$3396 + attribute \src "libresoc.v:51088.7-51088.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:50646.3-50654.6" - wire $1\dmi_req_i_1$next[0:0]$3361 - attribute \src "libresoc.v:50483.7-50483.25" + attribute \src "libresoc.v:51258.3-51266.6" + wire $1\dmi_req_i_1$next[0:0]$3362 + attribute \src "libresoc.v:51094.7-51094.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:50970.3-51003.6" - wire $1\do_dmi_log_rd$next[0:0]$3425 - attribute \src "libresoc.v:50489.7-50489.27" + attribute \src "libresoc.v:51585.3-51618.6" + wire $1\do_dmi_log_rd$next[0:0]$3426 + attribute \src "libresoc.v:51100.7-51100.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:50940.3-50969.6" - wire $1\do_icreset$next[0:0]$3418 - attribute \src "libresoc.v:50493.7-50493.24" + attribute \src "libresoc.v:51555.3-51584.6" + wire $1\do_icreset$next[0:0]$3419 + attribute \src "libresoc.v:51104.7-51104.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:50910.3-50939.6" - wire $1\do_reset$next[0:0]$3411 - attribute \src "libresoc.v:50497.7-50497.22" + attribute \src "libresoc.v:51525.3-51554.6" + wire $1\do_reset$next[0:0]$3412 + attribute \src "libresoc.v:51108.7-51108.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:50880.3-50909.6" - wire $1\do_step$next[0:0]$3404 - attribute \src "libresoc.v:50501.7-50501.21" + attribute \src "libresoc.v:51495.3-51524.6" + wire $1\do_step$next[0:0]$3405 + attribute \src "libresoc.v:51112.7-51112.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:50749.3-50776.6" - wire width 7 $1\gspr_index$next[6:0]$3383 - attribute \src "libresoc.v:50505.13-50505.31" + attribute \src "libresoc.v:51361.3-51388.6" + wire width 7 $1\gspr_index$next[6:0]$3384 + attribute \src "libresoc.v:51116.13-51116.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:50777.3-50810.6" - wire width 32 $1\log_dmi_addr$next[31:0]$3389 - attribute \src "libresoc.v:50511.14-50511.34" + attribute \src "libresoc.v:51389.3-51422.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3390 + attribute \src "libresoc.v:51122.14-51122.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:50705.3-50748.6" - wire $1\stopping$next[0:0]$3374 - attribute \src "libresoc.v:50523.7-50523.22" + attribute \src "libresoc.v:51317.3-51360.6" + wire $1\stopping$next[0:0]$3375 + attribute \src "libresoc.v:51134.7-51134.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:50655.3-50704.6" - wire $1\terminated$next[0:0]$3364 - attribute \src "libresoc.v:50529.7-50529.24" + attribute \src "libresoc.v:51267.3-51316.6" + wire $1\terminated$next[0:0]$3365 + attribute \src "libresoc.v:51140.7-51140.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:50970.3-51003.6" - wire $2\do_dmi_log_rd$next[0:0]$3426 - attribute \src "libresoc.v:50940.3-50969.6" - wire $2\do_icreset$next[0:0]$3419 - attribute \src "libresoc.v:50910.3-50939.6" - wire $2\do_reset$next[0:0]$3412 - attribute \src "libresoc.v:50880.3-50909.6" - wire $2\do_step$next[0:0]$3405 - attribute \src "libresoc.v:50749.3-50776.6" - wire width 7 $2\gspr_index$next[6:0]$3384 - attribute \src "libresoc.v:50777.3-50810.6" - wire width 32 $2\log_dmi_addr$next[31:0]$3390 - attribute \src "libresoc.v:50705.3-50748.6" - wire $2\stopping$next[0:0]$3375 - attribute \src "libresoc.v:50655.3-50704.6" - wire $2\terminated$next[0:0]$3365 - attribute \src "libresoc.v:50970.3-51003.6" - wire $3\do_dmi_log_rd$next[0:0]$3427 - attribute \src "libresoc.v:50940.3-50969.6" - wire $3\do_icreset$next[0:0]$3420 - attribute \src "libresoc.v:50910.3-50939.6" - wire $3\do_reset$next[0:0]$3413 - attribute \src "libresoc.v:50880.3-50909.6" - wire $3\do_step$next[0:0]$3406 - attribute \src "libresoc.v:50749.3-50776.6" - wire width 7 $3\gspr_index$next[6:0]$3385 - attribute \src "libresoc.v:50777.3-50810.6" - wire width 32 $3\log_dmi_addr$next[31:0]$3391 - attribute \src "libresoc.v:50705.3-50748.6" - wire $3\stopping$next[0:0]$3376 - attribute \src "libresoc.v:50655.3-50704.6" - wire $3\terminated$next[0:0]$3366 - attribute \src "libresoc.v:50970.3-51003.6" - wire $4\do_dmi_log_rd$next[0:0]$3428 - attribute \src "libresoc.v:50940.3-50969.6" - wire $4\do_icreset$next[0:0]$3421 - attribute \src "libresoc.v:50910.3-50939.6" - wire $4\do_reset$next[0:0]$3414 - attribute \src "libresoc.v:50880.3-50909.6" - wire $4\do_step$next[0:0]$3407 - attribute \src "libresoc.v:50749.3-50776.6" - wire width 7 $4\gspr_index$next[6:0]$3386 - attribute \src "libresoc.v:50777.3-50810.6" - wire width 32 $4\log_dmi_addr$next[31:0]$3392 - attribute \src "libresoc.v:50705.3-50748.6" - wire $4\stopping$next[0:0]$3377 - attribute \src "libresoc.v:50655.3-50704.6" - wire $4\terminated$next[0:0]$3367 - attribute \src "libresoc.v:50940.3-50969.6" - wire $5\do_icreset$next[0:0]$3422 - attribute \src "libresoc.v:50910.3-50939.6" - wire $5\do_reset$next[0:0]$3415 - attribute \src "libresoc.v:50880.3-50909.6" - wire $5\do_step$next[0:0]$3408 - attribute \src "libresoc.v:50705.3-50748.6" - wire $5\stopping$next[0:0]$3378 - attribute \src "libresoc.v:50655.3-50704.6" - wire $5\terminated$next[0:0]$3368 - attribute \src "libresoc.v:50705.3-50748.6" - wire $6\stopping$next[0:0]$3379 - attribute \src "libresoc.v:50655.3-50704.6" - wire $6\terminated$next[0:0]$3369 - attribute \src "libresoc.v:50705.3-50748.6" - wire $7\stopping$next[0:0]$3380 - attribute \src "libresoc.v:50655.3-50704.6" - wire $7\terminated$next[0:0]$3370 - attribute \src "libresoc.v:50655.3-50704.6" - wire $8\terminated$next[0:0]$3371 - attribute \src "libresoc.v:50543.19-50543.110" - wire width 3 $add$libresoc.v:50543$3293_Y - attribute \src "libresoc.v:50534.17-50534.109" - wire $and$libresoc.v:50534$3284_Y - attribute \src "libresoc.v:50537.19-50537.103" - wire $and$libresoc.v:50537$3287_Y - attribute \src "libresoc.v:50539.19-50539.113" - wire $and$libresoc.v:50539$3289_Y - attribute \src "libresoc.v:50546.19-50546.103" - wire $and$libresoc.v:50546$3296_Y - attribute \src "libresoc.v:50548.19-50548.102" - wire $and$libresoc.v:50548$3298_Y - attribute \src "libresoc.v:50553.18-50553.101" - wire $and$libresoc.v:50553$3303_Y - attribute \src "libresoc.v:50555.18-50555.111" - wire $and$libresoc.v:50555$3305_Y - attribute \src "libresoc.v:50560.18-50560.101" - wire $and$libresoc.v:50560$3310_Y - attribute \src "libresoc.v:50562.18-50562.111" - wire $and$libresoc.v:50562$3312_Y - attribute \src "libresoc.v:50568.18-50568.101" - wire $and$libresoc.v:50568$3318_Y - attribute \src "libresoc.v:50570.18-50570.111" - wire $and$libresoc.v:50570$3320_Y - attribute \src "libresoc.v:50574.17-50574.99" - wire $and$libresoc.v:50574$3324_Y - attribute \src "libresoc.v:50576.18-50576.101" - wire $and$libresoc.v:50576$3326_Y - attribute \src "libresoc.v:50578.18-50578.111" - wire $and$libresoc.v:50578$3328_Y - attribute \src "libresoc.v:50583.18-50583.101" - wire $and$libresoc.v:50583$3333_Y - attribute \src "libresoc.v:50586.18-50586.111" - wire $and$libresoc.v:50586$3336_Y - attribute \src "libresoc.v:50591.18-50591.101" - wire $and$libresoc.v:50591$3341_Y - attribute \src "libresoc.v:50593.18-50593.111" - wire $and$libresoc.v:50593$3343_Y - attribute \src "libresoc.v:50535.18-50535.103" - wire $eq$libresoc.v:50535$3285_Y - attribute \src "libresoc.v:50540.19-50540.104" - wire $eq$libresoc.v:50540$3290_Y - attribute \src "libresoc.v:50541.19-50541.104" - wire $eq$libresoc.v:50541$3291_Y - attribute \src "libresoc.v:50542.19-50542.104" - wire $eq$libresoc.v:50542$3292_Y - attribute \src "libresoc.v:50544.19-50544.104" - wire $eq$libresoc.v:50544$3294_Y - attribute \src "libresoc.v:50545.18-50545.103" - wire $eq$libresoc.v:50545$3295_Y - attribute \src "libresoc.v:50549.18-50549.103" - wire $eq$libresoc.v:50549$3299_Y - attribute \src "libresoc.v:50550.18-50550.103" - wire $eq$libresoc.v:50550$3300_Y - attribute \src "libresoc.v:50556.18-50556.103" - wire $eq$libresoc.v:50556$3306_Y - attribute \src "libresoc.v:50557.18-50557.103" - wire $eq$libresoc.v:50557$3307_Y - attribute \src "libresoc.v:50558.18-50558.103" - wire $eq$libresoc.v:50558$3308_Y - attribute \src "libresoc.v:50564.18-50564.103" - wire $eq$libresoc.v:50564$3314_Y - attribute \src "libresoc.v:50565.18-50565.103" - wire $eq$libresoc.v:50565$3315_Y - attribute \src "libresoc.v:50566.18-50566.103" - wire $eq$libresoc.v:50566$3316_Y - attribute \src "libresoc.v:50571.18-50571.103" - wire $eq$libresoc.v:50571$3321_Y - attribute \src "libresoc.v:50572.18-50572.103" - wire $eq$libresoc.v:50572$3322_Y - attribute \src "libresoc.v:50573.18-50573.103" - wire $eq$libresoc.v:50573$3323_Y - attribute \src "libresoc.v:50579.18-50579.103" - wire $eq$libresoc.v:50579$3329_Y - attribute \src "libresoc.v:50580.18-50580.103" - wire $eq$libresoc.v:50580$3330_Y - attribute \src "libresoc.v:50581.18-50581.103" - wire $eq$libresoc.v:50581$3331_Y - attribute \src "libresoc.v:50587.18-50587.103" - wire $eq$libresoc.v:50587$3337_Y - attribute \src "libresoc.v:50588.18-50588.103" - wire $eq$libresoc.v:50588$3338_Y - attribute \src "libresoc.v:50589.18-50589.103" - wire $eq$libresoc.v:50589$3339_Y - attribute \src "libresoc.v:50594.18-50594.103" - wire $eq$libresoc.v:50594$3344_Y - attribute \src "libresoc.v:50595.18-50595.103" - wire $eq$libresoc.v:50595$3345_Y - attribute \src "libresoc.v:50536.19-50536.99" - wire $not$libresoc.v:50536$3286_Y - attribute \src "libresoc.v:50538.19-50538.105" - wire $not$libresoc.v:50538$3288_Y - attribute \src "libresoc.v:50547.19-50547.95" - wire $not$libresoc.v:50547$3297_Y - attribute \src "libresoc.v:50551.18-50551.98" - wire $not$libresoc.v:50551$3301_Y - attribute \src "libresoc.v:50554.18-50554.104" - wire $not$libresoc.v:50554$3304_Y - attribute \src "libresoc.v:50559.18-50559.98" - wire $not$libresoc.v:50559$3309_Y - attribute \src "libresoc.v:50561.18-50561.104" - wire $not$libresoc.v:50561$3311_Y - attribute \src "libresoc.v:50563.17-50563.97" - wire $not$libresoc.v:50563$3313_Y - attribute \src "libresoc.v:50567.18-50567.98" - wire $not$libresoc.v:50567$3317_Y - attribute \src "libresoc.v:50569.18-50569.104" - wire $not$libresoc.v:50569$3319_Y - attribute \src "libresoc.v:50575.18-50575.98" - wire $not$libresoc.v:50575$3325_Y - attribute \src "libresoc.v:50577.18-50577.104" - wire $not$libresoc.v:50577$3327_Y - attribute \src "libresoc.v:50582.18-50582.98" - wire $not$libresoc.v:50582$3332_Y - attribute \src "libresoc.v:50584.18-50584.104" - wire $not$libresoc.v:50584$3334_Y - attribute \src "libresoc.v:50585.17-50585.103" - wire $not$libresoc.v:50585$3335_Y - attribute \src "libresoc.v:50590.18-50590.98" - wire $not$libresoc.v:50590$3340_Y - attribute \src "libresoc.v:50592.18-50592.104" - wire $not$libresoc.v:50592$3342_Y - attribute \src "libresoc.v:50552.17-50552.126" - wire width 64 $pos$libresoc.v:50552$3302_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + attribute \src "libresoc.v:51585.3-51618.6" + wire $2\do_dmi_log_rd$next[0:0]$3427 + attribute \src "libresoc.v:51555.3-51584.6" + wire $2\do_icreset$next[0:0]$3420 + attribute \src "libresoc.v:51525.3-51554.6" + wire $2\do_reset$next[0:0]$3413 + attribute \src "libresoc.v:51495.3-51524.6" + wire $2\do_step$next[0:0]$3406 + attribute \src "libresoc.v:51361.3-51388.6" + wire width 7 $2\gspr_index$next[6:0]$3385 + attribute \src "libresoc.v:51389.3-51422.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3391 + attribute \src "libresoc.v:51317.3-51360.6" + wire $2\stopping$next[0:0]$3376 + attribute \src "libresoc.v:51267.3-51316.6" + wire $2\terminated$next[0:0]$3366 + attribute \src "libresoc.v:51585.3-51618.6" + wire $3\do_dmi_log_rd$next[0:0]$3428 + attribute \src "libresoc.v:51555.3-51584.6" + wire $3\do_icreset$next[0:0]$3421 + attribute \src "libresoc.v:51525.3-51554.6" + wire $3\do_reset$next[0:0]$3414 + attribute \src "libresoc.v:51495.3-51524.6" + wire $3\do_step$next[0:0]$3407 + attribute \src "libresoc.v:51361.3-51388.6" + wire width 7 $3\gspr_index$next[6:0]$3386 + attribute \src "libresoc.v:51389.3-51422.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3392 + attribute \src "libresoc.v:51317.3-51360.6" + wire $3\stopping$next[0:0]$3377 + attribute \src "libresoc.v:51267.3-51316.6" + wire $3\terminated$next[0:0]$3367 + attribute \src "libresoc.v:51585.3-51618.6" + wire $4\do_dmi_log_rd$next[0:0]$3429 + attribute \src "libresoc.v:51555.3-51584.6" + wire $4\do_icreset$next[0:0]$3422 + attribute \src "libresoc.v:51525.3-51554.6" + wire $4\do_reset$next[0:0]$3415 + attribute \src "libresoc.v:51495.3-51524.6" + wire $4\do_step$next[0:0]$3408 + attribute \src "libresoc.v:51361.3-51388.6" + wire width 7 $4\gspr_index$next[6:0]$3387 + attribute \src "libresoc.v:51389.3-51422.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3393 + attribute \src "libresoc.v:51317.3-51360.6" + wire $4\stopping$next[0:0]$3378 + attribute \src "libresoc.v:51267.3-51316.6" + wire $4\terminated$next[0:0]$3368 + attribute \src "libresoc.v:51555.3-51584.6" + wire $5\do_icreset$next[0:0]$3423 + attribute \src "libresoc.v:51525.3-51554.6" + wire $5\do_reset$next[0:0]$3416 + attribute \src "libresoc.v:51495.3-51524.6" + wire $5\do_step$next[0:0]$3409 + attribute \src "libresoc.v:51317.3-51360.6" + wire $5\stopping$next[0:0]$3379 + attribute \src "libresoc.v:51267.3-51316.6" + wire $5\terminated$next[0:0]$3369 + attribute \src "libresoc.v:51317.3-51360.6" + wire $6\stopping$next[0:0]$3380 + attribute \src "libresoc.v:51267.3-51316.6" + wire $6\terminated$next[0:0]$3370 + attribute \src "libresoc.v:51317.3-51360.6" + wire $7\stopping$next[0:0]$3381 + attribute \src "libresoc.v:51267.3-51316.6" + wire $7\terminated$next[0:0]$3371 + attribute \src "libresoc.v:51267.3-51316.6" + wire $8\terminated$next[0:0]$3372 + attribute \src "libresoc.v:51155.19-51155.110" + wire width 3 $add$libresoc.v:51155$3294_Y + attribute \src "libresoc.v:51149.19-51149.103" + wire $and$libresoc.v:51149$3288_Y + attribute \src "libresoc.v:51151.19-51151.113" + wire $and$libresoc.v:51151$3290_Y + attribute \src "libresoc.v:51156.18-51156.110" + wire $and$libresoc.v:51156$3295_Y + attribute \src "libresoc.v:51158.19-51158.103" + wire $and$libresoc.v:51158$3297_Y + attribute \src "libresoc.v:51160.19-51160.102" + wire $and$libresoc.v:51160$3299_Y + attribute \src "libresoc.v:51166.18-51166.101" + wire $and$libresoc.v:51166$3305_Y + attribute \src "libresoc.v:51168.18-51168.111" + wire $and$libresoc.v:51168$3307_Y + attribute \src "libresoc.v:51173.18-51173.101" + wire $and$libresoc.v:51173$3312_Y + attribute \src "libresoc.v:51176.18-51176.111" + wire $and$libresoc.v:51176$3315_Y + attribute \src "libresoc.v:51181.18-51181.101" + wire $and$libresoc.v:51181$3320_Y + attribute \src "libresoc.v:51183.18-51183.111" + wire $and$libresoc.v:51183$3322_Y + attribute \src "libresoc.v:51189.18-51189.101" + wire $and$libresoc.v:51189$3328_Y + attribute \src "libresoc.v:51191.18-51191.111" + wire $and$libresoc.v:51191$3330_Y + attribute \src "libresoc.v:51196.18-51196.101" + wire $and$libresoc.v:51196$3335_Y + attribute \src "libresoc.v:51197.17-51197.99" + wire $and$libresoc.v:51197$3336_Y + attribute \src "libresoc.v:51199.18-51199.111" + wire $and$libresoc.v:51199$3338_Y + attribute \src "libresoc.v:51204.18-51204.101" + wire $and$libresoc.v:51204$3343_Y + attribute \src "libresoc.v:51206.18-51206.111" + wire $and$libresoc.v:51206$3345_Y + attribute \src "libresoc.v:51146.18-51146.103" + wire $eq$libresoc.v:51146$3285_Y + attribute \src "libresoc.v:51147.19-51147.104" + wire $eq$libresoc.v:51147$3286_Y + attribute \src "libresoc.v:51152.19-51152.104" + wire $eq$libresoc.v:51152$3291_Y + attribute \src "libresoc.v:51153.19-51153.104" + wire $eq$libresoc.v:51153$3292_Y + attribute \src "libresoc.v:51154.19-51154.104" + wire $eq$libresoc.v:51154$3293_Y + attribute \src "libresoc.v:51157.19-51157.104" + wire $eq$libresoc.v:51157$3296_Y + attribute \src "libresoc.v:51161.18-51161.103" + wire $eq$libresoc.v:51161$3300_Y + attribute \src "libresoc.v:51162.18-51162.103" + wire $eq$libresoc.v:51162$3301_Y + attribute \src "libresoc.v:51163.18-51163.103" + wire $eq$libresoc.v:51163$3302_Y + attribute \src "libresoc.v:51169.18-51169.103" + wire $eq$libresoc.v:51169$3308_Y + attribute \src "libresoc.v:51170.18-51170.103" + wire $eq$libresoc.v:51170$3309_Y + attribute \src "libresoc.v:51171.18-51171.103" + wire $eq$libresoc.v:51171$3310_Y + attribute \src "libresoc.v:51177.18-51177.103" + wire $eq$libresoc.v:51177$3316_Y + attribute \src "libresoc.v:51178.18-51178.103" + wire $eq$libresoc.v:51178$3317_Y + attribute \src "libresoc.v:51179.18-51179.103" + wire $eq$libresoc.v:51179$3318_Y + attribute \src "libresoc.v:51184.18-51184.103" + wire $eq$libresoc.v:51184$3323_Y + attribute \src "libresoc.v:51185.18-51185.103" + wire $eq$libresoc.v:51185$3324_Y + attribute \src "libresoc.v:51187.18-51187.103" + wire $eq$libresoc.v:51187$3326_Y + attribute \src "libresoc.v:51192.18-51192.103" + wire $eq$libresoc.v:51192$3331_Y + attribute \src "libresoc.v:51193.18-51193.103" + wire $eq$libresoc.v:51193$3332_Y + attribute \src "libresoc.v:51194.18-51194.103" + wire $eq$libresoc.v:51194$3333_Y + attribute \src "libresoc.v:51200.18-51200.103" + wire $eq$libresoc.v:51200$3339_Y + attribute \src "libresoc.v:51201.18-51201.103" + wire $eq$libresoc.v:51201$3340_Y + attribute \src "libresoc.v:51202.18-51202.103" + wire $eq$libresoc.v:51202$3341_Y + attribute \src "libresoc.v:51207.18-51207.103" + wire $eq$libresoc.v:51207$3346_Y + attribute \src "libresoc.v:51145.17-51145.103" + wire $not$libresoc.v:51145$3284_Y + attribute \src "libresoc.v:51148.19-51148.99" + wire $not$libresoc.v:51148$3287_Y + attribute \src "libresoc.v:51150.19-51150.105" + wire $not$libresoc.v:51150$3289_Y + attribute \src "libresoc.v:51159.19-51159.95" + wire $not$libresoc.v:51159$3298_Y + attribute \src "libresoc.v:51165.18-51165.98" + wire $not$libresoc.v:51165$3304_Y + attribute \src "libresoc.v:51167.18-51167.104" + wire $not$libresoc.v:51167$3306_Y + attribute \src "libresoc.v:51172.18-51172.98" + wire $not$libresoc.v:51172$3311_Y + attribute \src "libresoc.v:51174.18-51174.104" + wire $not$libresoc.v:51174$3313_Y + attribute \src "libresoc.v:51180.18-51180.98" + wire $not$libresoc.v:51180$3319_Y + attribute \src "libresoc.v:51182.18-51182.104" + wire $not$libresoc.v:51182$3321_Y + attribute \src "libresoc.v:51186.17-51186.97" + wire $not$libresoc.v:51186$3325_Y + attribute \src "libresoc.v:51188.18-51188.98" + wire $not$libresoc.v:51188$3327_Y + attribute \src "libresoc.v:51190.18-51190.104" + wire $not$libresoc.v:51190$3329_Y + attribute \src "libresoc.v:51195.18-51195.98" + wire $not$libresoc.v:51195$3334_Y + attribute \src "libresoc.v:51198.18-51198.104" + wire $not$libresoc.v:51198$3337_Y + attribute \src "libresoc.v:51203.18-51203.98" + wire $not$libresoc.v:51203$3342_Y + attribute \src "libresoc.v:51205.18-51205.104" + wire $not$libresoc.v:51205$3344_Y + attribute \src "libresoc.v:51164.17-51164.126" + wire width 64 $pos$libresoc.v:51164$3303_Y + attribute \src "libresoc.v:51175.17-51175.245" + wire width 64 $pos$libresoc.v:51175$3314_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - wire width 3 \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - wire width 3 \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" + wire width 3 \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" + wire width 3 \$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" wire \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" + wire \$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 24 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 11 \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 30 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 input 13 \core_dbg_core_dbg_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 input 16 \core_dbg_core_dbg_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 input 14 \core_dbg_core_dbg_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 input 12 \core_dbg_core_dbg_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 input 11 \core_dbg_core_dbg_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 input 15 \core_dbg_core_dbg_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" + wire width 64 input 17 \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 10 \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" wire output 8 \core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" - wire output 12 \core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" - wire input 13 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire output 18 \core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" + wire input 19 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire input 26 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + wire width 64 input 25 \d_cr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 20 \d_cr_ack + wire output 24 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire input 23 \d_gpr_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 19 \d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 18 \d_cr_req + wire width 7 output 21 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + wire width 64 input 22 \d_gpr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 17 \d_gpr_ack + wire output 20 \d_gpr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" - wire width 7 output 15 \d_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 16 \d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 14 \d_gpr_req + wire input 29 \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + wire width 64 input 28 \d_xer_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 23 \d_xer_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 22 \d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 21 \d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire output 27 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" wire output 6 \dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 input 2 \dmi_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 input 5 \dmi_din + wire width 4 input 2 \dmi_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 input 5 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" wire width 64 output 7 \dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" wire \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" - wire \dmi_read_log_data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" wire \dmi_read_log_data_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" wire \dmi_read_log_data_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" wire input 3 \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire \dmi_req_i_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire \dmi_req_i_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" wire input 4 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" wire \do_dmi_log_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" wire \do_dmi_log_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" wire \do_icreset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" wire \do_icreset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" wire \do_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" wire \do_reset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" wire \do_step - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" wire \do_step$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144" wire width 7 \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144" wire width 7 \gspr_index$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" wire \icache_rst_o - attribute \src "libresoc.v:50300.7-50300.15" + attribute \src "libresoc.v:50897.7-50897.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" - wire width 32 \log_dmi_addr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + wire width 32 \log_dmi_addr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" wire width 64 \log_dmi_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 64 \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" wire \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" wire \stopping$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" wire input 9 \terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" wire \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" wire \terminated$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire \terminated_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $add $add$libresoc.v:50543$3293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" + cell $add $add$libresoc.v:51155$3294 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -89871,208 +90499,219 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:50543$3293_Y + connect \Y $add$libresoc.v:51155$3294_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50534$3284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $and $and$libresoc.v:51149$3288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$7 - connect \Y $and$libresoc.v:50534$3284_Y + connect \A \dmi_req_i + connect \B \$103 + connect \Y $and$libresoc.v:51149$3288_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50537$3287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $and $and$libresoc.v:51151$3290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$101 - connect \Y $and$libresoc.v:50537$3287_Y + connect \A \dmi_read_log_data_1 + connect \B \$107 + connect \Y $and$libresoc.v:51151$3290_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50539$3289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $and $and$libresoc.v:51156$3295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B \$105 - connect \Y $and$libresoc.v:50539$3289_Y + connect \B \$9 + connect \Y $and$libresoc.v:51156$3295_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $and $and$libresoc.v:50546$3296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" + cell $and $and$libresoc.v:51158$3297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B \$118 - connect \Y $and$libresoc.v:50546$3296_Y + connect \B \$120 + connect \Y $and$libresoc.v:51158$3297_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $and $and$libresoc.v:50548$3298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" + cell $and $and$libresoc.v:51160$3299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \stopping - connect \B \$122 - connect \Y $and$libresoc.v:50548$3298_Y + connect \B \$124 + connect \Y $and$libresoc.v:51160$3299_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50553$3303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $and $and$libresoc.v:51166$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B \$17 - connect \Y $and$libresoc.v:50553$3303_Y + connect \B \$19 + connect \Y $and$libresoc.v:51166$3305_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50555$3305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $and $and$libresoc.v:51168$3307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B \$21 - connect \Y $and$libresoc.v:50555$3305_Y + connect \B \$23 + connect \Y $and$libresoc.v:51168$3307_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50560$3310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $and $and$libresoc.v:51173$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B \$31 - connect \Y $and$libresoc.v:50560$3310_Y + connect \B \$33 + connect \Y $and$libresoc.v:51173$3312_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50562$3312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $and $and$libresoc.v:51176$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B \$35 - connect \Y $and$libresoc.v:50562$3312_Y + connect \B \$37 + connect \Y $and$libresoc.v:51176$3315_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50568$3318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $and $and$libresoc.v:51181$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B \$45 - connect \Y $and$libresoc.v:50568$3318_Y + connect \B \$47 + connect \Y $and$libresoc.v:51181$3320_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50570$3320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $and $and$libresoc.v:51183$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B \$49 - connect \Y $and$libresoc.v:50570$3320_Y + connect \B \$51 + connect \Y $and$libresoc.v:51183$3322_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50574$3324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $and $and$libresoc.v:51189$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B \$3 - connect \Y $and$libresoc.v:50574$3324_Y + connect \B \$61 + connect \Y $and$libresoc.v:51189$3328_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50576$3326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $and $and$libresoc.v:51191$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$59 - connect \Y $and$libresoc.v:50576$3326_Y + connect \A \dmi_read_log_data_1 + connect \B \$65 + connect \Y $and$libresoc.v:51191$3330_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50578$3328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $and $and$libresoc.v:51196$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$63 - connect \Y $and$libresoc.v:50578$3328_Y + connect \A \dmi_req_i + connect \B \$75 + connect \Y $and$libresoc.v:51196$3335_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50583$3333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $and $and$libresoc.v:51197$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B \$73 - connect \Y $and$libresoc.v:50583$3333_Y + connect \B \$5 + connect \Y $and$libresoc.v:51197$3336_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50586$3336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $and $and$libresoc.v:51199$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B \$77 - connect \Y $and$libresoc.v:50586$3336_Y + connect \B \$79 + connect \Y $and$libresoc.v:51199$3338_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50591$3341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $and $and$libresoc.v:51204$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B \$87 - connect \Y $and$libresoc.v:50591$3341_Y + connect \B \$89 + connect \Y $and$libresoc.v:51204$3343_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50593$3343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $and $and$libresoc.v:51206$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B \$91 - connect \Y $and$libresoc.v:50593$3343_Y + connect \B \$93 + connect \Y $and$libresoc.v:51206$3345_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50535$3285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51146$3285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51146$3285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51147$3286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90080,10 +90719,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50535$3285_Y + connect \Y $eq$libresoc.v:51147$3286_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50540$3290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51152$3291 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90091,10 +90730,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50540$3290_Y + connect \Y $eq$libresoc.v:51152$3291_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50541$3291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51153$3292 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90102,10 +90741,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50541$3291_Y + connect \Y $eq$libresoc.v:51153$3292_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50542$3292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51154$3293 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90113,10 +90752,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50542$3292_Y + connect \Y $eq$libresoc.v:51154$3293_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $eq $eq$libresoc.v:50544$3294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" + cell $eq $eq$libresoc.v:51157$3296 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90124,10 +90763,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:50544$3294_Y + connect \Y $eq$libresoc.v:51157$3296_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50545$3295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51161$3300 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90135,10 +90774,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50545$3295_Y + connect \Y $eq$libresoc.v:51161$3300_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50549$3299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51162$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90146,10 +90785,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50549$3299_Y + connect \Y $eq$libresoc.v:51162$3301_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50550$3300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51163$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90157,10 +90796,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50550$3300_Y + connect \Y $eq$libresoc.v:51163$3302_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50556$3306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51169$3308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90168,10 +90807,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50556$3306_Y + connect \Y $eq$libresoc.v:51169$3308_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50557$3307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51170$3309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90179,10 +90818,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50557$3307_Y + connect \Y $eq$libresoc.v:51170$3309_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50558$3308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51171$3310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90190,10 +90829,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50558$3308_Y + connect \Y $eq$libresoc.v:51171$3310_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50564$3314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51177$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90201,10 +90840,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50564$3314_Y + connect \Y $eq$libresoc.v:51177$3316_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50565$3315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51178$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90212,10 +90851,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50565$3315_Y + connect \Y $eq$libresoc.v:51178$3317_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50566$3316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51179$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90223,10 +90862,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50566$3316_Y + connect \Y $eq$libresoc.v:51179$3318_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50571$3321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51184$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90234,10 +90873,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50571$3321_Y + connect \Y $eq$libresoc.v:51184$3323_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50572$3322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51185$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90245,10 +90884,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50572$3322_Y + connect \Y $eq$libresoc.v:51185$3324_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50573$3323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51187$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90256,10 +90895,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50573$3323_Y + connect \Y $eq$libresoc.v:51187$3326_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50579$3329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51192$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90267,10 +90906,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50579$3329_Y + connect \Y $eq$libresoc.v:51192$3331_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50580$3330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51193$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90278,10 +90917,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50580$3330_Y + connect \Y $eq$libresoc.v:51193$3332_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50581$3331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51194$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90289,10 +90928,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50581$3331_Y + connect \Y $eq$libresoc.v:51194$3333_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50587$3337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51200$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90300,10 +90939,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50587$3337_Y + connect \Y $eq$libresoc.v:51200$3339_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50588$3338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51201$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90311,10 +90950,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50588$3338_Y + connect \Y $eq$libresoc.v:51201$3340_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50589$3339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51202$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90322,10 +90961,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50589$3339_Y + connect \Y $eq$libresoc.v:51202$3341_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50594$3344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51207$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90333,347 +90972,344 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50594$3344_Y + connect \Y $eq$libresoc.v:51207$3346_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50595$3345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51145$3284 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:50595$3345_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51145$3284_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50536$3286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51148$3287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50536$3286_Y + connect \Y $not$libresoc.v:51148$3287_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50538$3288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51150$3289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50538$3288_Y + connect \Y $not$libresoc.v:51150$3289_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $not $not$libresoc.v:50547$3297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" + cell $not $not$libresoc.v:51159$3298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:50547$3297_Y + connect \Y $not$libresoc.v:51159$3298_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50551$3301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51165$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50551$3301_Y + connect \Y $not$libresoc.v:51165$3304_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50554$3304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51167$3306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50554$3304_Y + connect \Y $not$libresoc.v:51167$3306_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50559$3309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51172$3311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50559$3309_Y + connect \Y $not$libresoc.v:51172$3311_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50561$3311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51174$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50561$3311_Y + connect \Y $not$libresoc.v:51174$3313_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50563$3313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51180$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50563$3313_Y + connect \Y $not$libresoc.v:51180$3319_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50567$3317 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51182$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50567$3317_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51182$3321_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50569$3319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51186$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50569$3319_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51186$3325_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50575$3325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51188$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50575$3325_Y + connect \Y $not$libresoc.v:51188$3327_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50577$3327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51190$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50577$3327_Y + connect \Y $not$libresoc.v:51190$3329_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50582$3332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51195$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50582$3332_Y + connect \Y $not$libresoc.v:51195$3334_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50584$3334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50584$3334_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50585$3335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51198$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50585$3335_Y + connect \Y $not$libresoc.v:51198$3337_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50590$3340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51203$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50590$3340_Y + connect \Y $not$libresoc.v:51203$3342_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50592$3342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51205$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50592$3342_Y + connect \Y $not$libresoc.v:51205$3344_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" - cell $pos $pos$libresoc.v:50552$3302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $pos $pos$libresoc.v:51164$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:50552$3302_Y + connect \Y $pos$libresoc.v:51164$3303_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:51175$3314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } + connect \Y $pos$libresoc.v:51175$3314_Y end - attribute \src "libresoc.v:50300.7-50300.20" - process $proc$libresoc.v:50300$3429 + attribute \src "libresoc.v:50897.7-50897.20" + process $proc$libresoc.v:50897$3430 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50473.7-50473.31" - process $proc$libresoc.v:50473$3430 + attribute \src "libresoc.v:51084.7-51084.31" + process $proc$libresoc.v:51084$3431 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:50477.7-50477.33" - process $proc$libresoc.v:50477$3431 + attribute \src "libresoc.v:51088.7-51088.33" + process $proc$libresoc.v:51088$3432 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:50483.7-50483.25" - process $proc$libresoc.v:50483$3432 + attribute \src "libresoc.v:51094.7-51094.25" + process $proc$libresoc.v:51094$3433 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:50489.7-50489.27" - process $proc$libresoc.v:50489$3433 + attribute \src "libresoc.v:51100.7-51100.27" + process $proc$libresoc.v:51100$3434 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:50493.7-50493.24" - process $proc$libresoc.v:50493$3434 + attribute \src "libresoc.v:51104.7-51104.24" + process $proc$libresoc.v:51104$3435 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:50497.7-50497.22" - process $proc$libresoc.v:50497$3435 + attribute \src "libresoc.v:51108.7-51108.22" + process $proc$libresoc.v:51108$3436 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:50501.7-50501.21" - process $proc$libresoc.v:50501$3436 + attribute \src "libresoc.v:51112.7-51112.21" + process $proc$libresoc.v:51112$3437 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:50505.13-50505.31" - process $proc$libresoc.v:50505$3437 + attribute \src "libresoc.v:51116.13-51116.31" + process $proc$libresoc.v:51116$3438 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:50511.14-50511.34" - process $proc$libresoc.v:50511$3438 + attribute \src "libresoc.v:51122.14-51122.34" + process $proc$libresoc.v:51122$3439 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:50523.7-50523.22" - process $proc$libresoc.v:50523$3439 + attribute \src "libresoc.v:51134.7-51134.22" + process $proc$libresoc.v:51134$3440 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:50529.7-50529.24" - process $proc$libresoc.v:50529$3440 + attribute \src "libresoc.v:51140.7-51140.24" + process $proc$libresoc.v:51140$3441 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:50596.3-50597.51" - process $proc$libresoc.v:50596$3346 + attribute \src "libresoc.v:51208.3-51209.51" + process $proc$libresoc.v:51208$3347 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:50598.3-50599.55" - process $proc$libresoc.v:50598$3347 + attribute \src "libresoc.v:51210.3-51211.55" + process $proc$libresoc.v:51210$3348 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:50600.3-50601.41" - process $proc$libresoc.v:50600$3348 + attribute \src "libresoc.v:51212.3-51213.41" + process $proc$libresoc.v:51212$3349 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:50602.3-50603.37" - process $proc$libresoc.v:50602$3349 + attribute \src "libresoc.v:51214.3-51215.37" + process $proc$libresoc.v:51214$3350 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:50604.3-50605.33" - process $proc$libresoc.v:50604$3350 + attribute \src "libresoc.v:51216.3-51217.33" + process $proc$libresoc.v:51216$3351 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:50606.3-50607.37" - process $proc$libresoc.v:50606$3351 + attribute \src "libresoc.v:51218.3-51219.37" + process $proc$libresoc.v:51218$3352 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:50608.3-50609.39" - process $proc$libresoc.v:50608$3352 + attribute \src "libresoc.v:51220.3-51221.39" + process $proc$libresoc.v:51220$3353 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:50610.3-50611.43" - process $proc$libresoc.v:50610$3353 + attribute \src "libresoc.v:51222.3-51223.43" + process $proc$libresoc.v:51222$3354 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:50612.3-50613.37" - process $proc$libresoc.v:50612$3354 + attribute \src "libresoc.v:51224.3-51225.37" + process $proc$libresoc.v:51224$3355 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:50614.3-50615.33" - process $proc$libresoc.v:50614$3355 + attribute \src "libresoc.v:51226.3-51227.33" + process $proc$libresoc.v:51226$3356 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:50616.3-50617.31" - process $proc$libresoc.v:50616$3356 + attribute \src "libresoc.v:51228.3-51229.31" + process $proc$libresoc.v:51228$3357 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:50618.3-50635.6" - process $proc$libresoc.v:50618$3357 + attribute \src "libresoc.v:51230.3-51247.6" + process $proc$libresoc.v:51230$3358 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:50619.5-50619.29" + attribute \src "libresoc.v:51231.5-51231.29" switch \initial - attribute \src "libresoc.v:50619.9-50619.17" + attribute \src "libresoc.v:51231.9-51231.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -90695,18 +91331,18 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:50636.3-50645.6" - process $proc$libresoc.v:50636$3358 + attribute \src "libresoc.v:51248.3-51257.6" + process $proc$libresoc.v:51248$3359 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:50637.5-50637.29" + attribute \src "libresoc.v:51249.5-51249.29" switch \initial - attribute \src "libresoc.v:50637.9-50637.17" + attribute \src "libresoc.v:51249.9-51249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -90718,14 +91354,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:50646.3-50654.6" - process $proc$libresoc.v:50646$3359 + attribute \src "libresoc.v:51258.3-51266.6" + process $proc$libresoc.v:51258$3360 assign { } { } assign { } { } - assign $0\dmi_req_i_1$next[0:0]$3360 $1\dmi_req_i_1$next[0:0]$3361 - attribute \src "libresoc.v:50647.5-50647.29" + assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362 + attribute \src "libresoc.v:51259.5-51259.29" switch \initial - attribute \src "libresoc.v:50647.9-50647.17" + attribute \src "libresoc.v:51259.9-51259.17" case 1'1 case end @@ -90734,306 +91370,306 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_req_i_1$next[0:0]$3361 1'0 + assign $1\dmi_req_i_1$next[0:0]$3362 1'0 case - assign $1\dmi_req_i_1$next[0:0]$3361 \dmi_req_i + assign $1\dmi_req_i_1$next[0:0]$3362 \dmi_req_i end sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3360 + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361 end - attribute \src "libresoc.v:50655.3-50704.6" - process $proc$libresoc.v:50655$3362 + attribute \src "libresoc.v:51267.3-51316.6" + process $proc$libresoc.v:51267$3363 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\terminated$next[0:0]$3363 $8\terminated$next[0:0]$3371 - attribute \src "libresoc.v:50656.5-50656.29" + assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372 + attribute \src "libresoc.v:51268.5-51268.29" switch \initial - attribute \src "libresoc.v:50656.9-50656.17" + attribute \src "libresoc.v:51268.9-51268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$65 \$61 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$67 \$63 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\terminated$next[0:0]$3364 $2\terminated$next[0:0]$3365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + assign $1\terminated$next[0:0]$3365 $2\terminated$next[0:0]$3366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\terminated$next[0:0]$3365 $3\terminated$next[0:0]$3366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$71 \$69 \$67 } + assign $2\terminated$next[0:0]$3366 $3\terminated$next[0:0]$3367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$73 \$71 \$69 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } assign { } { } - assign $3\terminated$next[0:0]$3366 $6\terminated$next[0:0]$3369 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + assign $3\terminated$next[0:0]$3367 $6\terminated$next[0:0]$3370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\terminated$next[0:0]$3367 1'0 + assign $4\terminated$next[0:0]$3368 1'0 case - assign $4\terminated$next[0:0]$3367 \terminated + assign $4\terminated$next[0:0]$3368 \terminated end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\terminated$next[0:0]$3368 1'0 + assign $5\terminated$next[0:0]$3369 1'0 case - assign $5\terminated$next[0:0]$3368 $4\terminated$next[0:0]$3367 + assign $5\terminated$next[0:0]$3369 $4\terminated$next[0:0]$3368 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\terminated$next[0:0]$3369 1'0 + assign $6\terminated$next[0:0]$3370 1'0 case - assign $6\terminated$next[0:0]$3369 $5\terminated$next[0:0]$3368 + assign $6\terminated$next[0:0]$3370 $5\terminated$next[0:0]$3369 end case - assign $3\terminated$next[0:0]$3366 \terminated + assign $3\terminated$next[0:0]$3367 \terminated end case - assign $2\terminated$next[0:0]$3365 \terminated + assign $2\terminated$next[0:0]$3366 \terminated end case - assign $1\terminated$next[0:0]$3364 \terminated + assign $1\terminated$next[0:0]$3365 \terminated end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\terminated$next[0:0]$3370 1'1 + assign $7\terminated$next[0:0]$3371 1'1 case - assign $7\terminated$next[0:0]$3370 $1\terminated$next[0:0]$3364 + assign $7\terminated$next[0:0]$3371 $1\terminated$next[0:0]$3365 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\terminated$next[0:0]$3371 1'0 + assign $8\terminated$next[0:0]$3372 1'0 case - assign $8\terminated$next[0:0]$3371 $7\terminated$next[0:0]$3370 + assign $8\terminated$next[0:0]$3372 $7\terminated$next[0:0]$3371 end sync always - update \terminated$next $0\terminated$next[0:0]$3363 + update \terminated$next $0\terminated$next[0:0]$3364 end - attribute \src "libresoc.v:50705.3-50748.6" - process $proc$libresoc.v:50705$3372 + attribute \src "libresoc.v:51317.3-51360.6" + process $proc$libresoc.v:51317$3373 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\stopping$next[0:0]$3373 $7\stopping$next[0:0]$3380 - attribute \src "libresoc.v:50706.5-50706.29" + assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381 + attribute \src "libresoc.v:51318.5-51318.29" switch \initial - attribute \src "libresoc.v:50706.9-50706.17" + attribute \src "libresoc.v:51318.9-51318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$79 \$75 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$81 \$77 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\stopping$next[0:0]$3374 $2\stopping$next[0:0]$3375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + assign $1\stopping$next[0:0]$3375 $2\stopping$next[0:0]$3376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\stopping$next[0:0]$3375 $3\stopping$next[0:0]$3376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$85 \$83 \$81 } + assign $2\stopping$next[0:0]$3376 $3\stopping$next[0:0]$3377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$87 \$85 \$83 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } - assign $3\stopping$next[0:0]$3376 $5\stopping$next[0:0]$3378 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + assign $3\stopping$next[0:0]$3377 $5\stopping$next[0:0]$3379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" switch \dmi_din [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\stopping$next[0:0]$3377 1'1 + assign $4\stopping$next[0:0]$3378 1'1 case - assign $4\stopping$next[0:0]$3377 \stopping + assign $4\stopping$next[0:0]$3378 \stopping end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\stopping$next[0:0]$3378 1'0 + assign $5\stopping$next[0:0]$3379 1'0 case - assign $5\stopping$next[0:0]$3378 $4\stopping$next[0:0]$3377 + assign $5\stopping$next[0:0]$3379 $4\stopping$next[0:0]$3378 end case - assign $3\stopping$next[0:0]$3376 \stopping + assign $3\stopping$next[0:0]$3377 \stopping end case - assign $2\stopping$next[0:0]$3375 \stopping + assign $2\stopping$next[0:0]$3376 \stopping end case - assign $1\stopping$next[0:0]$3374 \stopping + assign $1\stopping$next[0:0]$3375 \stopping end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\stopping$next[0:0]$3379 1'1 + assign $6\stopping$next[0:0]$3380 1'1 case - assign $6\stopping$next[0:0]$3379 $1\stopping$next[0:0]$3374 + assign $6\stopping$next[0:0]$3380 $1\stopping$next[0:0]$3375 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\stopping$next[0:0]$3380 1'0 + assign $7\stopping$next[0:0]$3381 1'0 case - assign $7\stopping$next[0:0]$3380 $6\stopping$next[0:0]$3379 + assign $7\stopping$next[0:0]$3381 $6\stopping$next[0:0]$3380 end sync always - update \stopping$next $0\stopping$next[0:0]$3373 + update \stopping$next $0\stopping$next[0:0]$3374 end - attribute \src "libresoc.v:50749.3-50776.6" - process $proc$libresoc.v:50749$3381 + attribute \src "libresoc.v:51361.3-51388.6" + process $proc$libresoc.v:51361$3382 assign { } { } assign { } { } assign { } { } - assign $0\gspr_index$next[6:0]$3382 $4\gspr_index$next[6:0]$3386 - attribute \src "libresoc.v:50750.5-50750.29" + assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387 + attribute \src "libresoc.v:51362.5-51362.29" switch \initial - attribute \src "libresoc.v:50750.9-50750.17" + attribute \src "libresoc.v:51362.9-51362.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$93 \$89 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$95 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\gspr_index$next[6:0]$3383 $2\gspr_index$next[6:0]$3384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + assign $1\gspr_index$next[6:0]$3384 $2\gspr_index$next[6:0]$3385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\gspr_index$next[6:0]$3384 $3\gspr_index$next[6:0]$3385 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$99 \$97 \$95 } + assign $2\gspr_index$next[6:0]$3385 $3\gspr_index$next[6:0]$3386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$101 \$99 \$97 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\gspr_index$next[6:0]$3385 \gspr_index + assign $3\gspr_index$next[6:0]$3386 \gspr_index attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $3\gspr_index$next[6:0]$3385 \dmi_din [6:0] + assign $3\gspr_index$next[6:0]$3386 \dmi_din [6:0] case - assign $3\gspr_index$next[6:0]$3385 \gspr_index + assign $3\gspr_index$next[6:0]$3386 \gspr_index end case - assign $2\gspr_index$next[6:0]$3384 \gspr_index + assign $2\gspr_index$next[6:0]$3385 \gspr_index end case - assign $1\gspr_index$next[6:0]$3383 \gspr_index + assign $1\gspr_index$next[6:0]$3384 \gspr_index end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\gspr_index$next[6:0]$3386 7'0000000 + assign $4\gspr_index$next[6:0]$3387 7'0000000 case - assign $4\gspr_index$next[6:0]$3386 $1\gspr_index$next[6:0]$3383 + assign $4\gspr_index$next[6:0]$3387 $1\gspr_index$next[6:0]$3384 end sync always - update \gspr_index$next $0\gspr_index$next[6:0]$3382 + update \gspr_index$next $0\gspr_index$next[6:0]$3383 end - attribute \src "libresoc.v:50777.3-50810.6" - process $proc$libresoc.v:50777$3387 + attribute \src "libresoc.v:51389.3-51422.6" + process $proc$libresoc.v:51389$3388 assign { } { } assign { } { } assign { } { } - assign $0\log_dmi_addr$next[31:0]$3388 $4\log_dmi_addr$next[31:0]$3392 - attribute \src "libresoc.v:50778.5-50778.29" + assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393 + attribute \src "libresoc.v:51390.5-51390.29" switch \initial - attribute \src "libresoc.v:50778.9-50778.17" + attribute \src "libresoc.v:51390.9-51390.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$107 \$103 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$109 \$105 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\log_dmi_addr$next[31:0]$3389 $2\log_dmi_addr$next[31:0]$3390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + assign $1\log_dmi_addr$next[31:0]$3390 $2\log_dmi_addr$next[31:0]$3391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\log_dmi_addr$next[31:0]$3390 $3\log_dmi_addr$next[31:0]$3391 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$113 \$111 \$109 } + assign $2\log_dmi_addr$next[31:0]$3391 $3\log_dmi_addr$next[31:0]$3392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$115 \$113 \$111 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\log_dmi_addr$next[31:0]$3391 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\log_dmi_addr$next[31:0]$3391 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\log_dmi_addr$next[31:0]$3391 \dmi_din [31:0] + assign $3\log_dmi_addr$next[31:0]$3392 \dmi_din [31:0] case - assign $3\log_dmi_addr$next[31:0]$3391 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr end case - assign $2\log_dmi_addr$next[31:0]$3390 \log_dmi_addr + assign $2\log_dmi_addr$next[31:0]$3391 \log_dmi_addr end attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign $1\log_dmi_addr$next[31:0]$3389 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$3389 [1:0] \$115 [1:0] + assign $1\log_dmi_addr$next[31:0]$3390 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3390 [1:0] \$117 [1:0] case - assign $1\log_dmi_addr$next[31:0]$3389 \log_dmi_addr + assign $1\log_dmi_addr$next[31:0]$3390 \log_dmi_addr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\log_dmi_addr$next[31:0]$3392 0 + assign $4\log_dmi_addr$next[31:0]$3393 0 case - assign $4\log_dmi_addr$next[31:0]$3392 $1\log_dmi_addr$next[31:0]$3389 + assign $4\log_dmi_addr$next[31:0]$3393 $1\log_dmi_addr$next[31:0]$3390 end sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3388 + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389 end - attribute \src "libresoc.v:50811.3-50819.6" - process $proc$libresoc.v:50811$3393 + attribute \src "libresoc.v:51423.3-51431.6" + process $proc$libresoc.v:51423$3394 assign { } { } assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$3394 $1\dmi_read_log_data_1$next[0:0]$3395 - attribute \src "libresoc.v:50812.5-50812.29" + assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396 + attribute \src "libresoc.v:51424.5-51424.29" switch \initial - attribute \src "libresoc.v:50812.9-50812.17" + attribute \src "libresoc.v:51424.9-51424.17" case 1'1 case end @@ -91042,21 +91678,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$3395 1'0 + assign $1\dmi_read_log_data_1$next[0:0]$3396 1'0 case - assign $1\dmi_read_log_data_1$next[0:0]$3395 \dmi_read_log_data + assign $1\dmi_read_log_data_1$next[0:0]$3396 \dmi_read_log_data end sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3394 + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395 end - attribute \src "libresoc.v:50820.3-50828.6" - process $proc$libresoc.v:50820$3396 + attribute \src "libresoc.v:51432.3-51440.6" + process $proc$libresoc.v:51432$3397 assign { } { } assign { } { } - assign $0\dmi_read_log_data$next[0:0]$3397 $1\dmi_read_log_data$next[0:0]$3398 - attribute \src "libresoc.v:50821.5-50821.29" + assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399 + attribute \src "libresoc.v:51433.5-51433.29" switch \initial - attribute \src "libresoc.v:50821.9-50821.17" + attribute \src "libresoc.v:51433.9-51433.17" case 1'1 case end @@ -91065,25 +91701,25 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data$next[0:0]$3398 1'0 + assign $1\dmi_read_log_data$next[0:0]$3399 1'0 case - assign $1\dmi_read_log_data$next[0:0]$3398 \$120 + assign $1\dmi_read_log_data$next[0:0]$3399 \$122 end sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3397 + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398 end - attribute \src "libresoc.v:50829.3-50838.6" - process $proc$libresoc.v:50829$3399 + attribute \src "libresoc.v:51441.3-51450.6" + process $proc$libresoc.v:51441$3400 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:50830.5-50830.29" + attribute \src "libresoc.v:51442.5-51442.29" switch \initial - attribute \src "libresoc.v:50830.9-50830.17" + attribute \src "libresoc.v:51442.9-51442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -91095,18 +91731,18 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:50839.3-50848.6" - process $proc$libresoc.v:50839$3400 + attribute \src "libresoc.v:51451.3-51460.6" + process $proc$libresoc.v:51451$3401 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:50840.5-50840.29" + attribute \src "libresoc.v:51452.5-51452.29" switch \initial - attribute \src "libresoc.v:50840.9-50840.17" + attribute \src "libresoc.v:51452.9-51452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'1001 @@ -91118,18 +91754,18 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:50849.3-50879.6" - process $proc$libresoc.v:50849$3401 + attribute \src "libresoc.v:51461.3-51494.6" + process $proc$libresoc.v:51461$3402 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:50850.5-50850.29" + attribute \src "libresoc.v:51462.5-51462.29" switch \initial - attribute \src "libresoc.v:50850.9-50850.17" + attribute \src "libresoc.v:51462.9-51462.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:174" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -91144,6 +91780,10 @@ module \dbg assign { } { } assign $1\dmi_dout[63:0] \core_dbg_msr attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\dmi_dout[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dmi_dout[63:0] \d_gpr_data @@ -91169,451 +91809,454 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:50880.3-50909.6" - process $proc$libresoc.v:50880$3402 + attribute \src "libresoc.v:51495.3-51524.6" + process $proc$libresoc.v:51495$3403 assign { } { } assign { } { } assign { } { } - assign $0\do_step$next[0:0]$3403 $5\do_step$next[0:0]$3408 - attribute \src "libresoc.v:50881.5-50881.29" + assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409 + attribute \src "libresoc.v:51496.5-51496.29" switch \initial - attribute \src "libresoc.v:50881.9-50881.17" + attribute \src "libresoc.v:51496.9-51496.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$9 \$5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$11 \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_step$next[0:0]$3404 $2\do_step$next[0:0]$3405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + assign $1\do_step$next[0:0]$3405 $2\do_step$next[0:0]$3406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_step$next[0:0]$3405 $3\do_step$next[0:0]$3406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$15 \$13 \$11 } + assign $2\do_step$next[0:0]$3406 $3\do_step$next[0:0]$3407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$17 \$15 \$13 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_step$next[0:0]$3406 $4\do_step$next[0:0]$3407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + assign $3\do_step$next[0:0]$3407 $4\do_step$next[0:0]$3408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_step$next[0:0]$3407 1'1 + assign $4\do_step$next[0:0]$3408 1'1 case - assign $4\do_step$next[0:0]$3407 1'0 + assign $4\do_step$next[0:0]$3408 1'0 end case - assign $3\do_step$next[0:0]$3406 1'0 + assign $3\do_step$next[0:0]$3407 1'0 end case - assign $2\do_step$next[0:0]$3405 1'0 + assign $2\do_step$next[0:0]$3406 1'0 end case - assign $1\do_step$next[0:0]$3404 1'0 + assign $1\do_step$next[0:0]$3405 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_step$next[0:0]$3408 1'0 + assign $5\do_step$next[0:0]$3409 1'0 case - assign $5\do_step$next[0:0]$3408 $1\do_step$next[0:0]$3404 + assign $5\do_step$next[0:0]$3409 $1\do_step$next[0:0]$3405 end sync always - update \do_step$next $0\do_step$next[0:0]$3403 + update \do_step$next $0\do_step$next[0:0]$3404 end - attribute \src "libresoc.v:50910.3-50939.6" - process $proc$libresoc.v:50910$3409 + attribute \src "libresoc.v:51525.3-51554.6" + process $proc$libresoc.v:51525$3410 assign { } { } assign { } { } assign { } { } - assign $0\do_reset$next[0:0]$3410 $5\do_reset$next[0:0]$3415 - attribute \src "libresoc.v:50911.5-50911.29" + assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416 + attribute \src "libresoc.v:51526.5-51526.29" switch \initial - attribute \src "libresoc.v:50911.9-50911.17" + attribute \src "libresoc.v:51526.9-51526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$23 \$19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$25 \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_reset$next[0:0]$3411 $2\do_reset$next[0:0]$3412 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + assign $1\do_reset$next[0:0]$3412 $2\do_reset$next[0:0]$3413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_reset$next[0:0]$3412 $3\do_reset$next[0:0]$3413 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$29 \$27 \$25 } + assign $2\do_reset$next[0:0]$3413 $3\do_reset$next[0:0]$3414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$31 \$29 \$27 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_reset$next[0:0]$3413 $4\do_reset$next[0:0]$3414 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + assign $3\do_reset$next[0:0]$3414 $4\do_reset$next[0:0]$3415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_reset$next[0:0]$3414 1'1 + assign $4\do_reset$next[0:0]$3415 1'1 case - assign $4\do_reset$next[0:0]$3414 1'0 + assign $4\do_reset$next[0:0]$3415 1'0 end case - assign $3\do_reset$next[0:0]$3413 1'0 + assign $3\do_reset$next[0:0]$3414 1'0 end case - assign $2\do_reset$next[0:0]$3412 1'0 + assign $2\do_reset$next[0:0]$3413 1'0 end case - assign $1\do_reset$next[0:0]$3411 1'0 + assign $1\do_reset$next[0:0]$3412 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_reset$next[0:0]$3415 1'0 + assign $5\do_reset$next[0:0]$3416 1'0 case - assign $5\do_reset$next[0:0]$3415 $1\do_reset$next[0:0]$3411 + assign $5\do_reset$next[0:0]$3416 $1\do_reset$next[0:0]$3412 end sync always - update \do_reset$next $0\do_reset$next[0:0]$3410 + update \do_reset$next $0\do_reset$next[0:0]$3411 end - attribute \src "libresoc.v:50940.3-50969.6" - process $proc$libresoc.v:50940$3416 + attribute \src "libresoc.v:51555.3-51584.6" + process $proc$libresoc.v:51555$3417 assign { } { } assign { } { } assign { } { } - assign $0\do_icreset$next[0:0]$3417 $5\do_icreset$next[0:0]$3422 - attribute \src "libresoc.v:50941.5-50941.29" + assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423 + attribute \src "libresoc.v:51556.5-51556.29" switch \initial - attribute \src "libresoc.v:50941.9-50941.17" + attribute \src "libresoc.v:51556.9-51556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$37 \$33 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$39 \$35 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_icreset$next[0:0]$3418 $2\do_icreset$next[0:0]$3419 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + assign $1\do_icreset$next[0:0]$3419 $2\do_icreset$next[0:0]$3420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_icreset$next[0:0]$3419 $3\do_icreset$next[0:0]$3420 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$43 \$41 \$39 } + assign $2\do_icreset$next[0:0]$3420 $3\do_icreset$next[0:0]$3421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$45 \$43 \$41 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_icreset$next[0:0]$3420 $4\do_icreset$next[0:0]$3421 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + assign $3\do_icreset$next[0:0]$3421 $4\do_icreset$next[0:0]$3422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" switch \dmi_din [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_icreset$next[0:0]$3421 1'1 + assign $4\do_icreset$next[0:0]$3422 1'1 case - assign $4\do_icreset$next[0:0]$3421 1'0 + assign $4\do_icreset$next[0:0]$3422 1'0 end case - assign $3\do_icreset$next[0:0]$3420 1'0 + assign $3\do_icreset$next[0:0]$3421 1'0 end case - assign $2\do_icreset$next[0:0]$3419 1'0 + assign $2\do_icreset$next[0:0]$3420 1'0 end case - assign $1\do_icreset$next[0:0]$3418 1'0 + assign $1\do_icreset$next[0:0]$3419 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_icreset$next[0:0]$3422 1'0 + assign $5\do_icreset$next[0:0]$3423 1'0 case - assign $5\do_icreset$next[0:0]$3422 $1\do_icreset$next[0:0]$3418 + assign $5\do_icreset$next[0:0]$3423 $1\do_icreset$next[0:0]$3419 end sync always - update \do_icreset$next $0\do_icreset$next[0:0]$3417 + update \do_icreset$next $0\do_icreset$next[0:0]$3418 end - attribute \src "libresoc.v:50970.3-51003.6" - process $proc$libresoc.v:50970$3423 + attribute \src "libresoc.v:51585.3-51618.6" + process $proc$libresoc.v:51585$3424 assign { } { } assign { } { } assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$3424 $4\do_dmi_log_rd$next[0:0]$3428 - attribute \src "libresoc.v:50971.5-50971.29" + assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429 + attribute \src "libresoc.v:51586.5-51586.29" switch \initial - attribute \src "libresoc.v:50971.9-50971.17" + attribute \src "libresoc.v:51586.9-51586.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$51 \$47 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$53 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3425 $2\do_dmi_log_rd$next[0:0]$3426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + assign $1\do_dmi_log_rd$next[0:0]$3426 $2\do_dmi_log_rd$next[0:0]$3427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$3426 $3\do_dmi_log_rd$next[0:0]$3427 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$57 \$55 \$53 } + assign $2\do_dmi_log_rd$next[0:0]$3427 $3\do_dmi_log_rd$next[0:0]$3428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$59 \$57 \$55 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$3427 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$3427 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$3427 1'1 + assign $3\do_dmi_log_rd$next[0:0]$3428 1'1 case - assign $3\do_dmi_log_rd$next[0:0]$3427 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 end case - assign $2\do_dmi_log_rd$next[0:0]$3426 1'0 + assign $2\do_dmi_log_rd$next[0:0]$3427 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3425 1'1 + assign $1\do_dmi_log_rd$next[0:0]$3426 1'1 case - assign $1\do_dmi_log_rd$next[0:0]$3425 1'0 + assign $1\do_dmi_log_rd$next[0:0]$3426 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$3428 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$3428 $1\do_dmi_log_rd$next[0:0]$3425 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3424 - end - connect \$9 $and$libresoc.v:50534$3284_Y - connect \$99 $eq$libresoc.v:50535$3285_Y - connect \$101 $not$libresoc.v:50536$3286_Y - connect \$103 $and$libresoc.v:50537$3287_Y - connect \$105 $not$libresoc.v:50538$3288_Y - connect \$107 $and$libresoc.v:50539$3289_Y - connect \$109 $eq$libresoc.v:50540$3290_Y - connect \$111 $eq$libresoc.v:50541$3291_Y - connect \$113 $eq$libresoc.v:50542$3292_Y - connect \$116 $add$libresoc.v:50543$3293_Y - connect \$118 $eq$libresoc.v:50544$3294_Y - connect \$11 $eq$libresoc.v:50545$3295_Y - connect \$120 $and$libresoc.v:50546$3296_Y - connect \$122 $not$libresoc.v:50547$3297_Y - connect \$124 $and$libresoc.v:50548$3298_Y - connect \$13 $eq$libresoc.v:50549$3299_Y - connect \$15 $eq$libresoc.v:50550$3300_Y - connect \$17 $not$libresoc.v:50551$3301_Y - connect \$1 $pos$libresoc.v:50552$3302_Y - connect \$19 $and$libresoc.v:50553$3303_Y - connect \$21 $not$libresoc.v:50554$3304_Y - connect \$23 $and$libresoc.v:50555$3305_Y - connect \$25 $eq$libresoc.v:50556$3306_Y - connect \$27 $eq$libresoc.v:50557$3307_Y - connect \$29 $eq$libresoc.v:50558$3308_Y - connect \$31 $not$libresoc.v:50559$3309_Y - connect \$33 $and$libresoc.v:50560$3310_Y - connect \$35 $not$libresoc.v:50561$3311_Y - connect \$37 $and$libresoc.v:50562$3312_Y - connect \$3 $not$libresoc.v:50563$3313_Y - connect \$39 $eq$libresoc.v:50564$3314_Y - connect \$41 $eq$libresoc.v:50565$3315_Y - connect \$43 $eq$libresoc.v:50566$3316_Y - connect \$45 $not$libresoc.v:50567$3317_Y - connect \$47 $and$libresoc.v:50568$3318_Y - connect \$49 $not$libresoc.v:50569$3319_Y - connect \$51 $and$libresoc.v:50570$3320_Y - connect \$53 $eq$libresoc.v:50571$3321_Y - connect \$55 $eq$libresoc.v:50572$3322_Y - connect \$57 $eq$libresoc.v:50573$3323_Y - connect \$5 $and$libresoc.v:50574$3324_Y - connect \$59 $not$libresoc.v:50575$3325_Y - connect \$61 $and$libresoc.v:50576$3326_Y - connect \$63 $not$libresoc.v:50577$3327_Y - connect \$65 $and$libresoc.v:50578$3328_Y - connect \$67 $eq$libresoc.v:50579$3329_Y - connect \$69 $eq$libresoc.v:50580$3330_Y - connect \$71 $eq$libresoc.v:50581$3331_Y - connect \$73 $not$libresoc.v:50582$3332_Y - connect \$75 $and$libresoc.v:50583$3333_Y - connect \$77 $not$libresoc.v:50584$3334_Y - connect \$7 $not$libresoc.v:50585$3335_Y - connect \$79 $and$libresoc.v:50586$3336_Y - connect \$81 $eq$libresoc.v:50587$3337_Y - connect \$83 $eq$libresoc.v:50588$3338_Y - connect \$85 $eq$libresoc.v:50589$3339_Y - connect \$87 $not$libresoc.v:50590$3340_Y - connect \$89 $and$libresoc.v:50591$3341_Y - connect \$91 $not$libresoc.v:50592$3342_Y - connect \$93 $and$libresoc.v:50593$3343_Y - connect \$95 $eq$libresoc.v:50594$3344_Y - connect \$97 $eq$libresoc.v:50595$3345_Y - connect \$115 \$116 + assign $4\do_dmi_log_rd$next[0:0]$3429 1'0 + case + assign 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"libresoc.v:52532.3-52565.6" + attribute \src "libresoc.v:53107.3-53140.6" + wire width 14 $1\ALU_function_unit[13:0] + attribute \src "libresoc.v:53175.3-53208.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52566.3-52599.6" + attribute \src "libresoc.v:53209.3-53242.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:52498.3-52531.6" + attribute \src "libresoc.v:53141.3-53174.6" wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:52294.3-52327.6" + attribute \src "libresoc.v:52937.3-52970.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52328.3-52361.6" + attribute \src "libresoc.v:52971.3-53004.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52396.3-52429.6" + attribute \src "libresoc.v:53039.3-53072.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:52668.3-52701.6" + attribute \src "libresoc.v:53311.3-53344.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52226.3-52259.6" + attribute \src "libresoc.v:52869.3-52902.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52430.3-52463.6" + attribute \src "libresoc.v:53073.3-53106.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52191.17-52191.211" - wire width 32 $ternary$libresoc.v:52191$3441_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:52834.17-52834.211" + wire width 32 $ternary$libresoc.v:52834$3442_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \ALU_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 27 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 26 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 32 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 output 25 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \ALU_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \ALU_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 30 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 28 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \ALU_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \ALU_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 31 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 29 \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 26 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \ALU_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 output 22 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \ALU_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 24 \ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \ALU_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 17 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 23 \ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 20 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 18 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \ALU_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \ALU_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 19 \ALU_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -91623,23 +92266,25 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \ALU_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \ALU_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 13 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -91649,7 +92294,8 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec19_ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -91657,38 +92303,41 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec19_ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec19_ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec19_ALU_dec19_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \ALU_dec19_ALU_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec19_ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec19_ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -91705,7 +92354,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec19_ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -91781,13 +92430,14 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec19_ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec19_ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec19_ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec19_ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -91795,17 +92445,17 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec19_ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec19_ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec19_ALU_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -91815,7 +92465,8 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -91823,38 +92474,41 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_ALU_dec31_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \ALU_dec31_ALU_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \ALU_dec31_ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -91871,7 +92525,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -91947,13 +92601,14 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -91961,41 +92616,43 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ALU_dec31_ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \ALU_dec31_ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_ALU_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \ALU_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 8 \ALU_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -92011,8 +92668,8 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 9 \ALU_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -92087,13 +92744,14 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 15 \ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -92101,622 +92759,634 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 10 \ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 16 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 output 21 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:51018.7-51018.15" + attribute \src "libresoc.v:51633.7-51633.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:52191$3441 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 27 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:52834$3442 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:52191$3441_Y + connect \Y $ternary$libresoc.v:52834$3442_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:52192.13-52208.4" + attribute \src "libresoc.v:52835.13-52851.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -92735,7 +93405,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:52209.13-52225.4" + attribute \src "libresoc.v:52852.13-52868.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -92753,26 +93423,26 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:51018.7-51018.20" - process $proc$libresoc.v:51018$3456 + attribute \src "libresoc.v:51633.7-51633.20" + process $proc$libresoc.v:51633$3457 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52226.3-52259.6" - process $proc$libresoc.v:52226$3442 + attribute \src "libresoc.v:52869.3-52902.6" + process $proc$libresoc.v:52869$3443 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52227.5-52227.29" + attribute \src "libresoc.v:52870.5-52870.29" switch \initial - attribute \src "libresoc.v:52227.9-52227.17" + attribute \src "libresoc.v:52870.9-52870.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92816,18 +93486,18 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:52260.3-52293.6" - process $proc$libresoc.v:52260$3443 + attribute \src "libresoc.v:52903.3-52936.6" + process $proc$libresoc.v:52903$3444 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52261.5-52261.29" + attribute \src "libresoc.v:52904.5-52904.29" switch \initial - attribute \src "libresoc.v:52261.9-52261.17" + attribute \src "libresoc.v:52904.9-52904.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92871,18 +93541,18 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:52294.3-52327.6" - process $proc$libresoc.v:52294$3444 + attribute \src "libresoc.v:52937.3-52970.6" + process $proc$libresoc.v:52937$3445 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52295.5-52295.29" + attribute \src "libresoc.v:52938.5-52938.29" switch \initial - attribute \src "libresoc.v:52295.9-52295.17" + attribute \src "libresoc.v:52938.9-52938.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92926,18 +93596,18 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:52328.3-52361.6" - process $proc$libresoc.v:52328$3445 + attribute \src "libresoc.v:52971.3-53004.6" + process $proc$libresoc.v:52971$3446 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52329.5-52329.29" + attribute \src "libresoc.v:52972.5-52972.29" switch \initial - attribute \src "libresoc.v:52329.9-52329.17" + attribute \src "libresoc.v:52972.9-52972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92981,18 +93651,18 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:52362.3-52395.6" - process $proc$libresoc.v:52362$3446 + attribute \src "libresoc.v:53005.3-53038.6" + process $proc$libresoc.v:53005$3447 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:52363.5-52363.29" + attribute \src "libresoc.v:53006.5-53006.29" switch \initial - attribute \src "libresoc.v:52363.9-52363.17" + attribute \src "libresoc.v:53006.9-53006.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93036,18 +93706,18 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:52396.3-52429.6" - process $proc$libresoc.v:52396$3447 + attribute \src "libresoc.v:53039.3-53072.6" + process $proc$libresoc.v:53039$3448 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:52397.5-52397.29" + attribute \src "libresoc.v:53040.5-53040.29" switch \initial - attribute \src "libresoc.v:52397.9-52397.17" + attribute \src "libresoc.v:53040.9-53040.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93091,18 +93761,18 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:52430.3-52463.6" - process $proc$libresoc.v:52430$3448 + attribute \src "libresoc.v:53073.3-53106.6" + process $proc$libresoc.v:53073$3449 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52431.5-52431.29" + attribute \src "libresoc.v:53074.5-53074.29" switch \initial - attribute \src "libresoc.v:52431.9-52431.17" + attribute \src "libresoc.v:53074.9-53074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93146,73 +93816,73 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:52464.3-52497.6" - process $proc$libresoc.v:52464$3449 + attribute \src "libresoc.v:53107.3-53140.6" + process $proc$libresoc.v:53107$3450 assign { } { } assign { } { } - assign $0\ALU_function_unit[11:0] $1\ALU_function_unit[11:0] - attribute \src "libresoc.v:52465.5-52465.29" + assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] + attribute \src "libresoc.v:53108.5-53108.29" switch \initial - attribute \src "libresoc.v:52465.9-52465.17" + attribute \src "libresoc.v:53108.9-53108.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\ALU_function_unit[11:0] \ALU_dec19_ALU_dec19_function_unit + assign $1\ALU_function_unit[13:0] \ALU_dec19_ALU_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\ALU_function_unit[11:0] \ALU_dec31_ALU_dec31_function_unit + assign $1\ALU_function_unit[13:0] \ALU_dec31_ALU_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_function_unit[11:0] 12'000000000000 + assign $1\ALU_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_function_unit $0\ALU_function_unit[11:0] + update \ALU_function_unit $0\ALU_function_unit[13:0] end - attribute \src "libresoc.v:52498.3-52531.6" - process $proc$libresoc.v:52498$3450 + attribute \src "libresoc.v:53141.3-53174.6" + process $proc$libresoc.v:53141$3451 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:52499.5-52499.29" + attribute \src "libresoc.v:53142.5-53142.29" switch \initial - attribute \src "libresoc.v:52499.9-52499.17" + attribute \src "libresoc.v:53142.9-53142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93256,18 +93926,18 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:52532.3-52565.6" - process $proc$libresoc.v:52532$3451 + attribute \src "libresoc.v:53175.3-53208.6" + process $proc$libresoc.v:53175$3452 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52533.5-52533.29" + attribute \src "libresoc.v:53176.5-53176.29" switch \initial - attribute \src "libresoc.v:52533.9-52533.17" + attribute \src "libresoc.v:53176.9-53176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93311,18 +93981,18 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:52566.3-52599.6" - process $proc$libresoc.v:52566$3452 + attribute \src "libresoc.v:53209.3-53242.6" + process $proc$libresoc.v:53209$3453 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:52567.5-52567.29" + attribute \src "libresoc.v:53210.5-53210.29" switch \initial - attribute \src "libresoc.v:52567.9-52567.17" + attribute \src "libresoc.v:53210.9-53210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93366,18 +94036,18 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:52600.3-52633.6" - process $proc$libresoc.v:52600$3453 + attribute \src "libresoc.v:53243.3-53276.6" + process $proc$libresoc.v:53243$3454 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:52601.5-52601.29" + attribute \src "libresoc.v:53244.5-53244.29" switch \initial - attribute \src "libresoc.v:52601.9-52601.17" + attribute \src "libresoc.v:53244.9-53244.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93421,18 +94091,18 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:52634.3-52667.6" - process $proc$libresoc.v:52634$3454 + attribute \src "libresoc.v:53277.3-53310.6" + process $proc$libresoc.v:53277$3455 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52635.5-52635.29" + attribute \src "libresoc.v:53278.5-53278.29" switch \initial - attribute \src "libresoc.v:52635.9-52635.17" + attribute \src "libresoc.v:53278.9-53278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93476,18 +94146,18 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:52668.3-52701.6" - process $proc$libresoc.v:52668$3455 + attribute \src "libresoc.v:53311.3-53344.6" + process $proc$libresoc.v:53311$3456 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52669.5-52669.29" + attribute \src "libresoc.v:53312.5-53312.29" switch \initial - attribute \src "libresoc.v:52669.9-52669.17" + attribute \src "libresoc.v:53312.9-53312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93531,7 +94201,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:52191$3441_Y + connect \$1 $ternary$libresoc.v:52834$3442_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -93559,14 +94229,20 @@ module \dec connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -93858,137 +94534,140 @@ module \dec connect \ALU_RA \opcode_in [20:16] connect \ALU_RT \opcode_in [25:21] connect \ALU_RS \opcode_in [25:21] + connect \ALU_PO \opcode_in [31:26] connect \opcode_in \$1 connect \ALU_dec31_opcode_in \opcode_in connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53036.1-54466.10" +attribute \src "libresoc.v:53686.1-55151.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" -module \dec$140 - attribute \src "libresoc.v:54097.3-54109.6" +module \dec$138 + attribute \src "libresoc.v:54775.3-54787.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:54110.3-54122.6" + attribute \src "libresoc.v:54788.3-54800.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:54071.3-54083.6" - wire width 12 $0\CR_function_unit[11:0] - attribute \src "libresoc.v:54084.3-54096.6" + attribute \src "libresoc.v:54749.3-54761.6" + wire width 14 $0\CR_function_unit[13:0] + attribute \src "libresoc.v:54762.3-54774.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:54123.3-54135.6" + attribute \src "libresoc.v:54801.3-54813.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:53037.7-53037.20" + attribute \src "libresoc.v:53687.7-53687.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54097.3-54109.6" + attribute \src "libresoc.v:54775.3-54787.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54110.3-54122.6" + attribute \src "libresoc.v:54788.3-54800.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54071.3-54083.6" - wire width 12 $1\CR_function_unit[11:0] - attribute \src "libresoc.v:54084.3-54096.6" + attribute \src "libresoc.v:54749.3-54761.6" + wire width 14 $1\CR_function_unit[13:0] + attribute \src "libresoc.v:54762.3-54774.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54123.3-54135.6" + attribute \src "libresoc.v:54801.3-54813.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54054.17-54054.211" - wire width 32 $ternary$libresoc.v:54054$3457_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:54732.17-54732.211" + wire width 32 $ternary$libresoc.v:54732$3458_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \CR_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 11 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 10 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 15 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \CR_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \CR_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \CR_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 14 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 12 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \CR_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \CR_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \CR_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 13 \CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \CR_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \CR_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \CR_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 9 \CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \CR_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 8 \CR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \CR_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \CR_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \CR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \CR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -93998,16 +94677,18 @@ module \dec$140 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \CR_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \CR_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \CR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -94016,7 +94697,8 @@ module \dec$140 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec19_CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -94024,23 +94706,26 @@ module \dec$140 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec19_CR_dec19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \CR_dec19_CR_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec19_CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94115,15 +94800,16 @@ module \dec$140 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec19_CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \CR_dec19_CR_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \CR_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -94133,7 +94819,8 @@ module \dec$140 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -94141,23 +94828,26 @@ module \dec$140 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_CR_dec31_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \CR_dec31_CR_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94232,31 +94922,34 @@ module \dec$140 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \CR_dec31_CR_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \CR_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \CR_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94331,590 +95024,603 @@ module \dec$140 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \CR_internal_op + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \CR_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 18 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 16 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 17 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:53037.7-53037.15" + attribute \src "libresoc.v:53687.7-53687.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:54054$3457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 10 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:54732$3458 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54054$3457_Y + connect \Y $ternary$libresoc.v:54732$3458_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54055.12-54062.4" + attribute \src "libresoc.v:54733.12-54740.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -94924,7 +95630,7 @@ module \dec$140 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:54063.12-54070.4" + attribute \src "libresoc.v:54741.12-54748.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -94933,53 +95639,53 @@ module \dec$140 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:53037.7-53037.20" - process $proc$libresoc.v:53037$3463 + attribute \src "libresoc.v:53687.7-53687.20" + process $proc$libresoc.v:53687$3464 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54071.3-54083.6" - process $proc$libresoc.v:54071$3458 + attribute \src "libresoc.v:54749.3-54761.6" + process $proc$libresoc.v:54749$3459 assign { } { } assign { } { } - assign $0\CR_function_unit[11:0] $1\CR_function_unit[11:0] - attribute \src "libresoc.v:54072.5-54072.29" + assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] + attribute \src "libresoc.v:54750.5-54750.29" switch \initial - attribute \src "libresoc.v:54072.9-54072.17" + attribute \src "libresoc.v:54750.9-54750.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\CR_function_unit[11:0] \CR_dec19_CR_dec19_function_unit + assign $1\CR_function_unit[13:0] \CR_dec19_CR_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\CR_function_unit[11:0] \CR_dec31_CR_dec31_function_unit + assign $1\CR_function_unit[13:0] \CR_dec31_CR_dec31_function_unit case - assign $1\CR_function_unit[11:0] 12'000000000000 + assign $1\CR_function_unit[13:0] 14'00000000000000 end sync always - update \CR_function_unit $0\CR_function_unit[11:0] + update \CR_function_unit $0\CR_function_unit[13:0] end - attribute \src "libresoc.v:54084.3-54096.6" - process $proc$libresoc.v:54084$3459 + attribute \src "libresoc.v:54762.3-54774.6" + process $proc$libresoc.v:54762$3460 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54085.5-54085.29" + attribute \src "libresoc.v:54763.5-54763.29" switch \initial - attribute \src "libresoc.v:54085.9-54085.17" + attribute \src "libresoc.v:54763.9-54763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94995,18 +95701,18 @@ module \dec$140 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:54097.3-54109.6" - process $proc$libresoc.v:54097$3460 + attribute \src "libresoc.v:54775.3-54787.6" + process $proc$libresoc.v:54775$3461 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54098.5-54098.29" + attribute \src "libresoc.v:54776.5-54776.29" switch \initial - attribute \src "libresoc.v:54098.9-54098.17" + attribute \src "libresoc.v:54776.9-54776.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95022,18 +95728,18 @@ module \dec$140 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:54110.3-54122.6" - process $proc$libresoc.v:54110$3461 + attribute \src "libresoc.v:54788.3-54800.6" + process $proc$libresoc.v:54788$3462 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54111.5-54111.29" + attribute \src "libresoc.v:54789.5-54789.29" switch \initial - attribute \src "libresoc.v:54111.9-54111.17" + attribute \src "libresoc.v:54789.9-54789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95049,18 +95755,18 @@ module \dec$140 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:54123.3-54135.6" - process $proc$libresoc.v:54123$3462 + attribute \src "libresoc.v:54801.3-54813.6" + process $proc$libresoc.v:54801$3463 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54124.5-54124.29" + attribute \src "libresoc.v:54802.5-54802.29" switch \initial - attribute \src "libresoc.v:54124.9-54124.17" + attribute \src "libresoc.v:54802.9-54802.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95076,7 +95782,7 @@ module \dec$140 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:54054$3457_Y + connect \$1 $ternary$libresoc.v:54732$3458_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -95104,14 +95810,20 @@ module \dec$140 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -95403,139 +96115,142 @@ module \dec$140 connect \CR_RA \opcode_in [20:16] connect \CR_RT \opcode_in [25:21] connect \CR_RS \opcode_in [25:21] + connect \CR_PO \opcode_in [31:26] connect \opcode_in \$1 connect \CR_dec31_opcode_in \opcode_in connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:54470.1-55885.10" +attribute \src "libresoc.v:55155.1-56600.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" -module \dec$147 - attribute \src "libresoc.v:55476.3-55491.6" +module \dec$141 + attribute \src "libresoc.v:56184.3-56199.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:55492.3-55507.6" + attribute \src "libresoc.v:56200.3-56215.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:55428.3-55443.6" - wire width 12 $0\BRANCH_function_unit[11:0] - attribute \src "libresoc.v:55460.3-55475.6" + attribute \src "libresoc.v:56136.3-56151.6" + wire width 14 $0\BRANCH_function_unit[13:0] + attribute \src "libresoc.v:56168.3-56183.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:55444.3-55459.6" + attribute \src "libresoc.v:56152.3-56167.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55524.3-55539.6" + attribute \src "libresoc.v:56232.3-56247.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55540.3-55555.6" + attribute \src "libresoc.v:56248.3-56263.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:55508.3-55523.6" + attribute \src "libresoc.v:56216.3-56231.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:54471.7-54471.20" + attribute \src "libresoc.v:55156.7-55156.20" wire $0\initial[0:0] - attribute \src "libresoc.v:55476.3-55491.6" + attribute \src "libresoc.v:56184.3-56199.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:55492.3-55507.6" + attribute \src "libresoc.v:56200.3-56215.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:55428.3-55443.6" - wire width 12 $1\BRANCH_function_unit[11:0] - attribute \src "libresoc.v:55460.3-55475.6" + attribute \src "libresoc.v:56136.3-56151.6" + wire width 14 $1\BRANCH_function_unit[13:0] + attribute \src "libresoc.v:56168.3-56183.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:55444.3-55459.6" + attribute \src "libresoc.v:56152.3-56167.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55524.3-55539.6" + attribute \src "libresoc.v:56232.3-56247.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55540.3-55555.6" + attribute \src "libresoc.v:56248.3-56263.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:55508.3-55523.6" + attribute \src "libresoc.v:56216.3-56231.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55416.17-55416.211" - wire width 32 $ternary$libresoc.v:55416$3464_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:56124.17-56124.211" + wire width 32 $ternary$libresoc.v:56124$3465_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \BRANCH_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 21 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 20 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 26 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 output 19 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \BRANCH_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \BRANCH_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 24 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 22 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \BRANCH_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \BRANCH_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 25 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 23 \BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 20 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \BRANCH_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 output 16 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 11 \BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 18 \BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \BRANCH_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 17 \BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 14 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 12 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \BRANCH_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \BRANCH_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 13 \BRANCH_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -95545,16 +96260,18 @@ module \dec$147 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \BRANCH_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \BRANCH_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 8 \BRANCH_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -95563,7 +96280,8 @@ module \dec$147 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -95571,23 +96289,26 @@ module \dec$147 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \BRANCH_dec19_BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -95603,7 +96324,7 @@ module \dec$147 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -95679,35 +96400,38 @@ module \dec$147 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \BRANCH_dec19_BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \BRANCH_dec19_BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \BRANCH_dec19_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \BRANCH_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -95723,8 +96447,8 @@ module \dec$147 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 8 \BRANCH_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -95799,604 +96523,617 @@ module \dec$147 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 output 15 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 29 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 27 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 28 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src 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\X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:54471.7-54471.15" + attribute \src "libresoc.v:55156.7-55156.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 30 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:55416$3464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:56124$3465 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:55416$3464_Y + connect \Y $ternary$libresoc.v:56124$3465_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:55417.16-55427.4" + attribute \src "libresoc.v:56125.16-56135.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -96408,57 +97145,57 @@ module \dec$147 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:54471.7-54471.20" - process $proc$libresoc.v:54471$3473 + attribute \src "libresoc.v:55156.7-55156.20" + process $proc$libresoc.v:55156$3474 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:55428.3-55443.6" - process $proc$libresoc.v:55428$3465 + attribute \src "libresoc.v:56136.3-56151.6" + process $proc$libresoc.v:56136$3466 assign { } { } assign { } { } - assign $0\BRANCH_function_unit[11:0] $1\BRANCH_function_unit[11:0] - attribute \src "libresoc.v:55429.5-55429.29" + assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] + attribute \src "libresoc.v:56137.5-56137.29" switch \initial - attribute \src "libresoc.v:55429.9-55429.17" + attribute \src "libresoc.v:56137.9-56137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\BRANCH_function_unit[11:0] \BRANCH_dec19_BRANCH_dec19_function_unit + assign $1\BRANCH_function_unit[13:0] \BRANCH_dec19_BRANCH_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } - assign $1\BRANCH_function_unit[11:0] 12'000000100000 + assign $1\BRANCH_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } - assign $1\BRANCH_function_unit[11:0] 12'000000100000 + assign $1\BRANCH_function_unit[13:0] 14'00000000100000 case - assign $1\BRANCH_function_unit[11:0] 12'000000000000 + assign $1\BRANCH_function_unit[13:0] 14'00000000000000 end sync always - update \BRANCH_function_unit $0\BRANCH_function_unit[11:0] + update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] end - attribute \src "libresoc.v:55444.3-55459.6" - process $proc$libresoc.v:55444$3466 + attribute \src "libresoc.v:56152.3-56167.6" + process $proc$libresoc.v:56152$3467 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55445.5-55445.29" + attribute \src "libresoc.v:56153.5-56153.29" switch \initial - attribute \src "libresoc.v:55445.9-55445.17" + attribute \src "libresoc.v:56153.9-56153.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96478,18 +97215,18 @@ module \dec$147 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:55460.3-55475.6" - process $proc$libresoc.v:55460$3467 + attribute \src "libresoc.v:56168.3-56183.6" + process $proc$libresoc.v:56168$3468 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:55461.5-55461.29" + attribute \src "libresoc.v:56169.5-56169.29" switch \initial - attribute \src "libresoc.v:55461.9-55461.17" + attribute \src "libresoc.v:56169.9-56169.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96509,18 +97246,18 @@ module \dec$147 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:55476.3-55491.6" - process $proc$libresoc.v:55476$3468 + attribute \src "libresoc.v:56184.3-56199.6" + process $proc$libresoc.v:56184$3469 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:55477.5-55477.29" + attribute \src "libresoc.v:56185.5-56185.29" switch \initial - attribute \src "libresoc.v:55477.9-55477.17" + attribute \src "libresoc.v:56185.9-56185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96540,18 +97277,18 @@ module \dec$147 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:55492.3-55507.6" - process $proc$libresoc.v:55492$3469 + attribute \src "libresoc.v:56200.3-56215.6" + process $proc$libresoc.v:56200$3470 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:55493.5-55493.29" + attribute \src "libresoc.v:56201.5-56201.29" switch \initial - attribute \src "libresoc.v:55493.9-55493.17" + attribute \src "libresoc.v:56201.9-56201.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96571,18 +97308,18 @@ module \dec$147 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:55508.3-55523.6" - process $proc$libresoc.v:55508$3470 + attribute \src "libresoc.v:56216.3-56231.6" + process $proc$libresoc.v:56216$3471 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55509.5-55509.29" + attribute \src "libresoc.v:56217.5-56217.29" switch \initial - attribute \src "libresoc.v:55509.9-55509.17" + attribute \src "libresoc.v:56217.9-56217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96602,18 +97339,18 @@ module \dec$147 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:55524.3-55539.6" - process $proc$libresoc.v:55524$3471 + attribute \src "libresoc.v:56232.3-56247.6" + process $proc$libresoc.v:56232$3472 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55525.5-55525.29" + attribute \src "libresoc.v:56233.5-56233.29" switch \initial - attribute \src "libresoc.v:55525.9-55525.17" + attribute \src "libresoc.v:56233.9-56233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96633,18 +97370,18 @@ module \dec$147 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:55540.3-55555.6" - process $proc$libresoc.v:55540$3472 + attribute \src "libresoc.v:56248.3-56263.6" + process $proc$libresoc.v:56248$3473 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:55541.5-55541.29" + attribute \src "libresoc.v:56249.5-56249.29" switch \initial - attribute \src "libresoc.v:55541.9-55541.17" + attribute \src "libresoc.v:56249.9-56249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96664,7 +97401,7 @@ module \dec$147 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:55416$3464_Y + connect \$1 $ternary$libresoc.v:56124$3465_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -96692,14 +97429,20 @@ module \dec$147 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -96991,262 +97734,265 @@ module \dec$147 connect \BRANCH_RA \opcode_in [20:16] connect \BRANCH_RT \opcode_in [25:21] connect \BRANCH_RS \opcode_in [25:21] + connect \BRANCH_PO \opcode_in [31:26] connect \opcode_in \$1 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:55889.1-57636.10" +attribute \src "libresoc.v:56604.1-58381.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" -module \dec$155 - attribute \src "libresoc.v:57195.3-57222.6" +module \dec$145 + attribute \src "libresoc.v:57933.3-57960.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57223.3-57250.6" + attribute \src "libresoc.v:57961.3-57988.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:56915.3-56942.6" + attribute \src "libresoc.v:57653.3-57680.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:56999.3-57026.6" + attribute \src "libresoc.v:57737.3-57764.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57083.3-57110.6" - wire width 12 $0\LOGICAL_function_unit[11:0] - attribute \src "libresoc.v:57139.3-57166.6" + attribute \src "libresoc.v:57821.3-57848.6" + wire width 14 $0\LOGICAL_function_unit[13:0] + attribute \src "libresoc.v:57877.3-57904.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57167.3-57194.6" + attribute \src "libresoc.v:57905.3-57932.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57111.3-57138.6" + attribute \src "libresoc.v:57849.3-57876.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:56943.3-56970.6" + attribute \src "libresoc.v:57681.3-57708.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:56971.3-56998.6" + attribute \src "libresoc.v:57709.3-57736.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57027.3-57054.6" + attribute \src "libresoc.v:57765.3-57792.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57251.3-57278.6" + attribute \src "libresoc.v:57989.3-58016.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57279.3-57306.6" + attribute \src "libresoc.v:58017.3-58044.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57055.3-57082.6" + attribute \src "libresoc.v:57793.3-57820.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:55890.7-55890.20" + attribute \src "libresoc.v:56605.7-56605.20" wire $0\initial[0:0] - attribute \src "libresoc.v:57195.3-57222.6" + attribute \src "libresoc.v:57933.3-57960.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57223.3-57250.6" + attribute \src "libresoc.v:57961.3-57988.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:56915.3-56942.6" + attribute \src "libresoc.v:57653.3-57680.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:56999.3-57026.6" + attribute \src "libresoc.v:57737.3-57764.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57083.3-57110.6" - wire width 12 $1\LOGICAL_function_unit[11:0] - attribute \src "libresoc.v:57139.3-57166.6" + attribute \src "libresoc.v:57821.3-57848.6" + wire width 14 $1\LOGICAL_function_unit[13:0] + attribute \src "libresoc.v:57877.3-57904.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57167.3-57194.6" + attribute \src "libresoc.v:57905.3-57932.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57111.3-57138.6" + attribute \src "libresoc.v:57849.3-57876.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:56943.3-56970.6" + attribute \src "libresoc.v:57681.3-57708.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:56971.3-56998.6" + attribute \src "libresoc.v:57709.3-57736.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57027.3-57054.6" + attribute \src "libresoc.v:57765.3-57792.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57251.3-57278.6" + attribute \src "libresoc.v:57989.3-58016.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57279.3-57306.6" + attribute \src "libresoc.v:58017.3-58044.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57055.3-57082.6" + attribute \src "libresoc.v:57793.3-57820.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56897.17-56897.211" - wire width 32 $ternary$libresoc.v:56897$3474_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:57635.17-57635.211" + wire width 32 $ternary$libresoc.v:57635$3475_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LOGICAL_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 27 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 26 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 32 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 output 25 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \LOGICAL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \LOGICAL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 30 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 28 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \LOGICAL_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \LOGICAL_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 31 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 29 \LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 26 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LOGICAL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 output 22 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LOGICAL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 24 \LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \LOGICAL_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 17 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 23 \LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 20 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 18 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \LOGICAL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \LOGICAL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 19 \LOGICAL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -97256,23 +98002,25 @@ module \dec$155 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \LOGICAL_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LOGICAL_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 13 \LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \LOGICAL_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -97282,7 +98030,8 @@ module \dec$155 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -97290,38 +98039,41 @@ module \dec$155 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_LOGICAL_dec31_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -97338,7 +98090,7 @@ module \dec$155 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -97414,13 +98166,14 @@ module \dec$155 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_LOGICAL_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_LOGICAL_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -97428,41 +98181,43 @@ module \dec$155 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_LOGICAL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LOGICAL_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \LOGICAL_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 8 \LOGICAL_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -97478,8 +98233,8 @@ module \dec$155 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 9 \LOGICAL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -97554,13 +98309,14 @@ module \dec$155 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 15 \LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -97568,502 +98324,514 @@ module \dec$155 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 10 \LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 16 \LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 output 21 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src 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\X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:55890.7-55890.15" + attribute \src "libresoc.v:56605.7-56605.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:56897$3474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 27 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:57635$3475 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:56897$3474_Y + connect \Y $ternary$libresoc.v:57635$3475_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:56898.17-56914.4" + attribute \src "libresoc.v:57636.17-57652.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -98081,26 +98849,26 @@ module \dec$155 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:55890.7-55890.20" - process $proc$libresoc.v:55890$3489 + attribute \src "libresoc.v:56605.7-56605.20" + process $proc$libresoc.v:56605$3490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:56915.3-56942.6" - process $proc$libresoc.v:56915$3475 + attribute \src "libresoc.v:57653.3-57680.6" + process $proc$libresoc.v:57653$3476 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:56916.5-56916.29" + attribute \src "libresoc.v:57654.5-57654.29" switch \initial - attribute \src "libresoc.v:56916.9-56916.17" + attribute \src "libresoc.v:57654.9-57654.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98136,18 +98904,18 @@ module \dec$155 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:56943.3-56970.6" - process $proc$libresoc.v:56943$3476 + attribute \src "libresoc.v:57681.3-57708.6" + process $proc$libresoc.v:57681$3477 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:56944.5-56944.29" + attribute \src "libresoc.v:57682.5-57682.29" switch \initial - attribute \src "libresoc.v:56944.9-56944.17" + attribute \src "libresoc.v:57682.9-57682.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98183,18 +98951,18 @@ module \dec$155 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:56971.3-56998.6" - process $proc$libresoc.v:56971$3477 + attribute \src "libresoc.v:57709.3-57736.6" + process $proc$libresoc.v:57709$3478 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:56972.5-56972.29" + attribute \src "libresoc.v:57710.5-57710.29" switch \initial - attribute \src "libresoc.v:56972.9-56972.17" + attribute \src "libresoc.v:57710.9-57710.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98230,18 +98998,18 @@ module \dec$155 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:56999.3-57026.6" - process $proc$libresoc.v:56999$3478 + attribute \src "libresoc.v:57737.3-57764.6" + process $proc$libresoc.v:57737$3479 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57000.5-57000.29" + attribute \src "libresoc.v:57738.5-57738.29" switch \initial - attribute \src "libresoc.v:57000.9-57000.17" + attribute \src "libresoc.v:57738.9-57738.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98277,18 +99045,18 @@ module \dec$155 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:57027.3-57054.6" - process $proc$libresoc.v:57027$3479 + attribute \src "libresoc.v:57765.3-57792.6" + process $proc$libresoc.v:57765$3480 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57028.5-57028.29" + attribute \src "libresoc.v:57766.5-57766.29" switch \initial - attribute \src "libresoc.v:57028.9-57028.17" + attribute \src "libresoc.v:57766.9-57766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98324,18 +99092,18 @@ module \dec$155 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:57055.3-57082.6" - process $proc$libresoc.v:57055$3480 + attribute \src "libresoc.v:57793.3-57820.6" + process $proc$libresoc.v:57793$3481 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57056.5-57056.29" + attribute \src "libresoc.v:57794.5-57794.29" switch \initial - attribute \src "libresoc.v:57056.9-57056.17" + attribute \src "libresoc.v:57794.9-57794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98371,65 +99139,65 @@ module \dec$155 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:57083.3-57110.6" - process $proc$libresoc.v:57083$3481 + attribute \src "libresoc.v:57821.3-57848.6" + process $proc$libresoc.v:57821$3482 assign { } { } assign { } { } - assign $0\LOGICAL_function_unit[11:0] $1\LOGICAL_function_unit[11:0] - attribute \src "libresoc.v:57084.5-57084.29" + assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] + attribute \src "libresoc.v:57822.5-57822.29" switch \initial - attribute \src "libresoc.v:57084.9-57084.17" + attribute \src "libresoc.v:57822.9-57822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\LOGICAL_function_unit[11:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit + assign $1\LOGICAL_function_unit[13:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 case - assign $1\LOGICAL_function_unit[11:0] 12'000000000000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000000000 end sync always - update \LOGICAL_function_unit $0\LOGICAL_function_unit[11:0] + update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] end - attribute \src "libresoc.v:57111.3-57138.6" - process $proc$libresoc.v:57111$3482 + attribute \src "libresoc.v:57849.3-57876.6" + process $proc$libresoc.v:57849$3483 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57112.5-57112.29" + attribute \src "libresoc.v:57850.5-57850.29" switch \initial - attribute \src "libresoc.v:57112.9-57112.17" + attribute \src "libresoc.v:57850.9-57850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98465,18 +99233,18 @@ module \dec$155 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:57139.3-57166.6" - process $proc$libresoc.v:57139$3483 + attribute \src "libresoc.v:57877.3-57904.6" + process $proc$libresoc.v:57877$3484 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57140.5-57140.29" + attribute \src "libresoc.v:57878.5-57878.29" switch \initial - attribute \src "libresoc.v:57140.9-57140.17" + attribute \src "libresoc.v:57878.9-57878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98512,18 +99280,18 @@ module \dec$155 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:57167.3-57194.6" - process $proc$libresoc.v:57167$3484 + attribute \src "libresoc.v:57905.3-57932.6" + process $proc$libresoc.v:57905$3485 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57168.5-57168.29" + attribute \src "libresoc.v:57906.5-57906.29" switch \initial - attribute \src "libresoc.v:57168.9-57168.17" + attribute \src "libresoc.v:57906.9-57906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98559,18 +99327,18 @@ module \dec$155 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:57195.3-57222.6" - process $proc$libresoc.v:57195$3485 + attribute \src "libresoc.v:57933.3-57960.6" + process $proc$libresoc.v:57933$3486 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57196.5-57196.29" + attribute \src "libresoc.v:57934.5-57934.29" switch \initial - attribute \src "libresoc.v:57196.9-57196.17" + attribute \src "libresoc.v:57934.9-57934.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98606,18 +99374,18 @@ module \dec$155 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:57223.3-57250.6" - process $proc$libresoc.v:57223$3486 + attribute \src "libresoc.v:57961.3-57988.6" + process $proc$libresoc.v:57961$3487 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57224.5-57224.29" + attribute \src "libresoc.v:57962.5-57962.29" switch \initial - attribute \src "libresoc.v:57224.9-57224.17" + attribute \src "libresoc.v:57962.9-57962.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98653,18 +99421,18 @@ module \dec$155 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:57251.3-57278.6" - process $proc$libresoc.v:57251$3487 + attribute \src "libresoc.v:57989.3-58016.6" + process $proc$libresoc.v:57989$3488 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57252.5-57252.29" + attribute \src "libresoc.v:57990.5-57990.29" switch \initial - attribute \src "libresoc.v:57252.9-57252.17" + attribute \src "libresoc.v:57990.9-57990.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98700,18 +99468,18 @@ module \dec$155 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:57279.3-57306.6" - process $proc$libresoc.v:57279$3488 + attribute \src "libresoc.v:58017.3-58044.6" + process $proc$libresoc.v:58017$3489 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57280.5-57280.29" + attribute \src "libresoc.v:58018.5-58018.29" switch \initial - attribute \src "libresoc.v:57280.9-57280.17" + attribute \src "libresoc.v:58018.9-58018.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98747,7 +99515,7 @@ module \dec$155 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:56897$3474_Y + connect \$1 $ternary$libresoc.v:57635$3475_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -98775,14 +99543,20 @@ module \dec$155 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -99074,286 +99848,289 @@ module \dec$155 connect \LOGICAL_RA \opcode_in [20:16] connect \LOGICAL_RT \opcode_in [25:21] connect \LOGICAL_RS \opcode_in [25:21] + connect \LOGICAL_PO \opcode_in [31:26] connect \opcode_in \$1 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:57640.1-58945.10" +attribute \src "libresoc.v:58385.1-59720.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" -module \dec$164 - attribute \src "libresoc.v:58576.3-58585.6" +module \dec$150 + attribute \src "libresoc.v:59344.3-59353.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:58586.3-58595.6" + attribute \src "libresoc.v:59354.3-59363.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:58556.3-58565.6" - wire width 12 $0\SPR_function_unit[11:0] - attribute \src "libresoc.v:58566.3-58575.6" + attribute \src "libresoc.v:59324.3-59333.6" + wire width 14 $0\SPR_function_unit[13:0] + attribute \src "libresoc.v:59334.3-59343.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:58606.3-58615.6" + attribute \src "libresoc.v:59374.3-59383.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:58596.3-58605.6" + attribute \src "libresoc.v:59364.3-59373.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:57641.7-57641.20" + attribute \src "libresoc.v:58386.7-58386.20" wire $0\initial[0:0] - attribute \src "libresoc.v:58576.3-58585.6" + attribute \src "libresoc.v:59344.3-59353.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:58586.3-58595.6" + attribute \src "libresoc.v:59354.3-59363.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:58556.3-58565.6" - wire width 12 $1\SPR_function_unit[11:0] - attribute \src "libresoc.v:58566.3-58575.6" + attribute \src "libresoc.v:59324.3-59333.6" + wire width 14 $1\SPR_function_unit[13:0] + attribute \src "libresoc.v:59334.3-59343.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:58606.3-58615.6" + attribute \src "libresoc.v:59374.3-59383.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:58596.3-58605.6" + attribute \src "libresoc.v:59364.3-59373.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58546.17-58546.211" - wire width 32 $ternary$libresoc.v:58546$3490_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:59314.17-59314.211" + wire width 32 $ternary$libresoc.v:59314$3491_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SPR_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 12 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 11 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 16 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \SPR_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \SPR_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \SPR_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 15 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 13 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \SPR_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \SPR_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \SPR_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 14 \SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SPR_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \SPR_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SPR_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 10 \SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \SPR_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 9 \SPR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \SPR_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \SPR_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \SPR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \SPR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -99363,16 +100140,18 @@ module \dec$164 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SPR_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SPR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \SPR_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \SPR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -99381,7 +100160,8 @@ module \dec$164 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SPR_dec31_SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -99389,23 +100169,26 @@ module \dec$164 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SPR_dec31_SPR_dec31_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SPR_dec31_SPR_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SPR_dec31_SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -99480,33 +100263,36 @@ module \dec$164 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SPR_dec31_SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SPR_dec31_SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SPR_dec31_SPR_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SPR_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \SPR_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -99581,446 +100367,459 @@ module \dec$164 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \SPR_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 19 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 17 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 18 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:57641.7-57641.15" + attribute \src "libresoc.v:58386.7-58386.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:58546$3490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 11 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:59314$3491 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:58546$3490_Y + connect \Y $ternary$libresoc.v:59314$3491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:58547.13-58555.4" + attribute \src "libresoc.v:59315.13-59323.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -100030,49 +100829,49 @@ module \dec$164 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:57641.7-57641.20" - process $proc$libresoc.v:57641$3497 + attribute \src "libresoc.v:58386.7-58386.20" + process $proc$libresoc.v:58386$3498 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:58556.3-58565.6" - process $proc$libresoc.v:58556$3491 + attribute \src "libresoc.v:59324.3-59333.6" + process $proc$libresoc.v:59324$3492 assign { } { } assign { } { } - assign $0\SPR_function_unit[11:0] $1\SPR_function_unit[11:0] - attribute \src "libresoc.v:58557.5-58557.29" + assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] + attribute \src "libresoc.v:59325.5-59325.29" switch \initial - attribute \src "libresoc.v:58557.9-58557.17" + attribute \src "libresoc.v:59325.9-59325.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\SPR_function_unit[11:0] \SPR_dec31_SPR_dec31_function_unit + assign $1\SPR_function_unit[13:0] \SPR_dec31_SPR_dec31_function_unit case - assign $1\SPR_function_unit[11:0] 12'000000000000 + assign $1\SPR_function_unit[13:0] 14'00000000000000 end sync always - update \SPR_function_unit $0\SPR_function_unit[11:0] + update \SPR_function_unit $0\SPR_function_unit[13:0] end - attribute \src "libresoc.v:58566.3-58575.6" - process $proc$libresoc.v:58566$3492 + attribute \src "libresoc.v:59334.3-59343.6" + process $proc$libresoc.v:59334$3493 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:58567.5-58567.29" + attribute \src "libresoc.v:59335.5-59335.29" switch \initial - attribute \src "libresoc.v:58567.9-58567.17" + attribute \src "libresoc.v:59335.9-59335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100084,18 +100883,18 @@ module \dec$164 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:58576.3-58585.6" - process $proc$libresoc.v:58576$3493 + attribute \src "libresoc.v:59344.3-59353.6" + process $proc$libresoc.v:59344$3494 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:58577.5-58577.29" + attribute \src "libresoc.v:59345.5-59345.29" switch \initial - attribute \src "libresoc.v:58577.9-58577.17" + attribute \src "libresoc.v:59345.9-59345.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100107,18 +100906,18 @@ module \dec$164 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:58586.3-58595.6" - process $proc$libresoc.v:58586$3494 + attribute \src "libresoc.v:59354.3-59363.6" + process $proc$libresoc.v:59354$3495 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:58587.5-58587.29" + attribute \src "libresoc.v:59355.5-59355.29" switch \initial - attribute \src "libresoc.v:58587.9-58587.17" + attribute \src "libresoc.v:59355.9-59355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100130,18 +100929,18 @@ module \dec$164 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:58596.3-58605.6" - process $proc$libresoc.v:58596$3495 + attribute \src "libresoc.v:59364.3-59373.6" + process $proc$libresoc.v:59364$3496 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58597.5-58597.29" + attribute \src "libresoc.v:59365.5-59365.29" switch \initial - attribute \src "libresoc.v:58597.9-58597.17" + attribute \src "libresoc.v:59365.9-59365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100153,18 +100952,18 @@ module \dec$164 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:58606.3-58615.6" - process $proc$libresoc.v:58606$3496 + attribute \src "libresoc.v:59374.3-59383.6" + process $proc$libresoc.v:59374$3497 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:58607.5-58607.29" + attribute \src "libresoc.v:59375.5-59375.29" switch \initial - attribute \src "libresoc.v:58607.9-58607.17" + attribute \src "libresoc.v:59375.9-59375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100176,7 +100975,7 @@ module \dec$164 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:58546$3490_Y + connect \$1 $ternary$libresoc.v:59314$3491_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -100204,14 +101003,20 @@ module \dec$164 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -100503,172 +101308,175 @@ module \dec$164 connect \SPR_RA \opcode_in [20:16] connect \SPR_RT \opcode_in [25:21] connect \SPR_RS \opcode_in [25:21] + connect \SPR_PO \opcode_in [31:26] connect \opcode_in \$1 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58949.1-60444.10" +attribute \src "libresoc.v:59724.1-61249.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" -module \dec$171 - attribute \src "libresoc.v:60075.3-60084.6" +module \dec$153 + attribute \src "libresoc.v:60873.3-60882.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60085.3-60094.6" + attribute \src "libresoc.v:60883.3-60892.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:59975.3-59984.6" + attribute \src "libresoc.v:60773.3-60782.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60005.3-60014.6" + attribute \src "libresoc.v:60803.3-60812.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60035.3-60044.6" - wire width 12 $0\DIV_function_unit[11:0] - attribute \src "libresoc.v:60055.3-60064.6" + attribute \src "libresoc.v:60833.3-60842.6" + wire width 14 $0\DIV_function_unit[13:0] + attribute \src "libresoc.v:60853.3-60862.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60065.3-60074.6" + attribute \src "libresoc.v:60863.3-60872.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60045.3-60054.6" + attribute \src "libresoc.v:60843.3-60852.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:59985.3-59994.6" + attribute \src "libresoc.v:60783.3-60792.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:59995.3-60004.6" + attribute \src "libresoc.v:60793.3-60802.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:60015.3-60024.6" + attribute \src "libresoc.v:60813.3-60822.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:60095.3-60104.6" + attribute \src "libresoc.v:60893.3-60902.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60105.3-60114.6" + attribute \src "libresoc.v:60903.3-60912.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60025.3-60034.6" + attribute \src "libresoc.v:60823.3-60832.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:58950.7-58950.20" + attribute \src "libresoc.v:59725.7-59725.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60075.3-60084.6" + attribute \src "libresoc.v:60873.3-60882.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60085.3-60094.6" + attribute \src "libresoc.v:60883.3-60892.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:59975.3-59984.6" + attribute \src "libresoc.v:60773.3-60782.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60005.3-60014.6" + attribute \src "libresoc.v:60803.3-60812.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60035.3-60044.6" - wire width 12 $1\DIV_function_unit[11:0] - attribute \src "libresoc.v:60055.3-60064.6" + attribute \src "libresoc.v:60833.3-60842.6" + wire width 14 $1\DIV_function_unit[13:0] + attribute \src "libresoc.v:60853.3-60862.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60065.3-60074.6" + attribute \src "libresoc.v:60863.3-60872.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60045.3-60054.6" + attribute \src "libresoc.v:60843.3-60852.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:59985.3-59994.6" + attribute \src "libresoc.v:60783.3-60792.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:59995.3-60004.6" + attribute \src "libresoc.v:60793.3-60802.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60015.3-60024.6" + attribute \src "libresoc.v:60813.3-60822.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60095.3-60104.6" + attribute \src "libresoc.v:60893.3-60902.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60105.3-60114.6" + attribute \src "libresoc.v:60903.3-60912.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60025.3-60034.6" + attribute \src "libresoc.v:60823.3-60832.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:59957.17-59957.211" - wire width 32 $ternary$libresoc.v:59957$3498_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:60755.17-60755.211" + wire width 32 $ternary$libresoc.v:60755$3499_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \DIV_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 27 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 26 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 32 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 output 25 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \DIV_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \DIV_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 30 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 28 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \DIV_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \DIV_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 31 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 29 \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 26 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \DIV_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 output 22 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \DIV_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 24 \DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \DIV_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 17 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 23 \DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 20 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 18 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \DIV_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \DIV_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 19 \DIV_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -100678,23 +101486,25 @@ module \dec$171 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \DIV_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \DIV_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \DIV_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 13 \DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \DIV_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -100704,7 +101514,8 @@ module \dec$171 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -100712,38 +101523,41 @@ module \dec$171 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \DIV_dec31_DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_DIV_dec31_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \DIV_dec31_DIV_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \DIV_dec31_DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \DIV_dec31_DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -100760,7 +101574,7 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \DIV_dec31_DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -100836,13 +101650,14 @@ module \dec$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \DIV_dec31_DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -100850,41 +101665,43 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \DIV_dec31_DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \DIV_dec31_DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_DIV_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \DIV_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \DIV_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 8 \DIV_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -100900,8 +101717,8 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 9 \DIV_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100976,13 +101793,14 @@ module \dec$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 15 \DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -100990,592 +101808,604 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 10 \DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 16 \DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 output 21 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:58950.7-58950.15" + attribute \src "libresoc.v:59725.7-59725.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:59957$3498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 27 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:60755$3499 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:59957$3498_Y + connect \Y $ternary$libresoc.v:60755$3499_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:59958.13-59974.4" + attribute \src "libresoc.v:60756.13-60772.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -101593,26 +102423,26 @@ module \dec$171 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:58950.7-58950.20" - process $proc$libresoc.v:58950$3513 + attribute \src "libresoc.v:59725.7-59725.20" + process $proc$libresoc.v:59725$3514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:59975.3-59984.6" - process $proc$libresoc.v:59975$3499 + attribute \src "libresoc.v:60773.3-60782.6" + process $proc$libresoc.v:60773$3500 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:59976.5-59976.29" + attribute \src "libresoc.v:60774.5-60774.29" switch \initial - attribute \src "libresoc.v:59976.9-59976.17" + attribute \src "libresoc.v:60774.9-60774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101624,18 +102454,18 @@ module \dec$171 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:59985.3-59994.6" - process $proc$libresoc.v:59985$3500 + attribute \src "libresoc.v:60783.3-60792.6" + process $proc$libresoc.v:60783$3501 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:59986.5-59986.29" + attribute \src "libresoc.v:60784.5-60784.29" switch \initial - attribute \src "libresoc.v:59986.9-59986.17" + attribute \src "libresoc.v:60784.9-60784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101647,18 +102477,18 @@ module \dec$171 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:59995.3-60004.6" - process $proc$libresoc.v:59995$3501 + attribute \src "libresoc.v:60793.3-60802.6" + process $proc$libresoc.v:60793$3502 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:59996.5-59996.29" + attribute \src "libresoc.v:60794.5-60794.29" switch \initial - attribute \src "libresoc.v:59996.9-59996.17" + attribute \src "libresoc.v:60794.9-60794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101670,18 +102500,18 @@ module \dec$171 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:60005.3-60014.6" - process $proc$libresoc.v:60005$3502 + attribute \src "libresoc.v:60803.3-60812.6" + process $proc$libresoc.v:60803$3503 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60006.5-60006.29" + attribute \src "libresoc.v:60804.5-60804.29" switch \initial - attribute \src "libresoc.v:60006.9-60006.17" + attribute \src "libresoc.v:60804.9-60804.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101693,18 +102523,18 @@ module \dec$171 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:60015.3-60024.6" - process $proc$libresoc.v:60015$3503 + attribute \src "libresoc.v:60813.3-60822.6" + process $proc$libresoc.v:60813$3504 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60016.5-60016.29" + attribute \src "libresoc.v:60814.5-60814.29" switch \initial - attribute \src "libresoc.v:60016.9-60016.17" + attribute \src "libresoc.v:60814.9-60814.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101716,18 +102546,18 @@ module \dec$171 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:60025.3-60034.6" - process $proc$libresoc.v:60025$3504 + attribute \src "libresoc.v:60823.3-60832.6" + process $proc$libresoc.v:60823$3505 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60026.5-60026.29" + attribute \src "libresoc.v:60824.5-60824.29" switch \initial - attribute \src "libresoc.v:60026.9-60026.17" + attribute \src "libresoc.v:60824.9-60824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101739,41 +102569,41 @@ module \dec$171 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:60035.3-60044.6" - process $proc$libresoc.v:60035$3505 + attribute \src "libresoc.v:60833.3-60842.6" + process $proc$libresoc.v:60833$3506 assign { } { } assign { } { } - assign $0\DIV_function_unit[11:0] $1\DIV_function_unit[11:0] - attribute \src "libresoc.v:60036.5-60036.29" + assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] + attribute \src "libresoc.v:60834.5-60834.29" switch \initial - attribute \src "libresoc.v:60036.9-60036.17" + attribute \src "libresoc.v:60834.9-60834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\DIV_function_unit[11:0] \DIV_dec31_DIV_dec31_function_unit + assign $1\DIV_function_unit[13:0] \DIV_dec31_DIV_dec31_function_unit case - assign $1\DIV_function_unit[11:0] 12'000000000000 + assign $1\DIV_function_unit[13:0] 14'00000000000000 end sync always - update \DIV_function_unit $0\DIV_function_unit[11:0] + update \DIV_function_unit $0\DIV_function_unit[13:0] end - attribute \src "libresoc.v:60045.3-60054.6" - process $proc$libresoc.v:60045$3506 + attribute \src "libresoc.v:60843.3-60852.6" + process $proc$libresoc.v:60843$3507 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60046.5-60046.29" + attribute \src "libresoc.v:60844.5-60844.29" switch \initial - attribute \src "libresoc.v:60046.9-60046.17" + attribute \src "libresoc.v:60844.9-60844.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101785,18 +102615,18 @@ module \dec$171 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:60055.3-60064.6" - process $proc$libresoc.v:60055$3507 + attribute \src "libresoc.v:60853.3-60862.6" + process $proc$libresoc.v:60853$3508 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60056.5-60056.29" + attribute \src "libresoc.v:60854.5-60854.29" switch \initial - attribute \src "libresoc.v:60056.9-60056.17" + attribute \src "libresoc.v:60854.9-60854.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101808,18 +102638,18 @@ module \dec$171 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:60065.3-60074.6" - process $proc$libresoc.v:60065$3508 + attribute \src "libresoc.v:60863.3-60872.6" + process $proc$libresoc.v:60863$3509 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60066.5-60066.29" + attribute \src "libresoc.v:60864.5-60864.29" switch \initial - attribute \src "libresoc.v:60066.9-60066.17" + attribute \src "libresoc.v:60864.9-60864.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101831,18 +102661,18 @@ module \dec$171 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:60075.3-60084.6" - process $proc$libresoc.v:60075$3509 + attribute \src "libresoc.v:60873.3-60882.6" + process $proc$libresoc.v:60873$3510 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60076.5-60076.29" + attribute \src "libresoc.v:60874.5-60874.29" switch \initial - attribute \src "libresoc.v:60076.9-60076.17" + attribute \src "libresoc.v:60874.9-60874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101854,18 +102684,18 @@ module \dec$171 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:60085.3-60094.6" - process $proc$libresoc.v:60085$3510 + attribute \src "libresoc.v:60883.3-60892.6" + process $proc$libresoc.v:60883$3511 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60086.5-60086.29" + attribute \src "libresoc.v:60884.5-60884.29" switch \initial - attribute \src "libresoc.v:60086.9-60086.17" + attribute \src "libresoc.v:60884.9-60884.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101877,18 +102707,18 @@ module \dec$171 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:60095.3-60104.6" - process $proc$libresoc.v:60095$3511 + attribute \src "libresoc.v:60893.3-60902.6" + process $proc$libresoc.v:60893$3512 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60096.5-60096.29" + attribute \src "libresoc.v:60894.5-60894.29" switch \initial - attribute \src "libresoc.v:60096.9-60096.17" + attribute \src "libresoc.v:60894.9-60894.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101900,18 +102730,18 @@ module \dec$171 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:60105.3-60114.6" - process $proc$libresoc.v:60105$3512 + attribute \src "libresoc.v:60903.3-60912.6" + process $proc$libresoc.v:60903$3513 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60106.5-60106.29" + attribute \src "libresoc.v:60904.5-60904.29" switch \initial - attribute \src "libresoc.v:60106.9-60106.17" + attribute \src "libresoc.v:60904.9-60904.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101923,7 +102753,7 @@ module \dec$171 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:59957$3498_Y + connect \$1 $ternary$libresoc.v:60755$3499_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -101951,14 +102781,20 @@ module \dec$171 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -102250,274 +103086,277 @@ module \dec$171 connect \DIV_RA \opcode_in [20:16] connect \DIV_RT \opcode_in [25:21] connect \DIV_RS \opcode_in [25:21] + connect \DIV_PO \opcode_in [31:26] connect \opcode_in \$1 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:60448.1-61839.10" +attribute \src "libresoc.v:61253.1-62674.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" -module \dec$180 - attribute \src "libresoc.v:61445.3-61457.6" +module \dec$158 + attribute \src "libresoc.v:62273.3-62285.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:61458.3-61470.6" + attribute \src "libresoc.v:62286.3-62298.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:61406.3-61418.6" - wire width 12 $0\MUL_function_unit[11:0] - attribute \src "libresoc.v:61432.3-61444.6" + attribute \src "libresoc.v:62234.3-62246.6" + wire width 14 $0\MUL_function_unit[13:0] + attribute \src "libresoc.v:62260.3-62272.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:61419.3-61431.6" + attribute \src "libresoc.v:62247.3-62259.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:61484.3-61496.6" + attribute \src "libresoc.v:62312.3-62324.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:61471.3-61483.6" + attribute \src "libresoc.v:62299.3-62311.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:61497.3-61509.6" + attribute \src "libresoc.v:62325.3-62337.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:60449.7-60449.20" + attribute \src "libresoc.v:61254.7-61254.20" wire $0\initial[0:0] - attribute \src "libresoc.v:61445.3-61457.6" + attribute \src "libresoc.v:62273.3-62285.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:61458.3-61470.6" + attribute \src "libresoc.v:62286.3-62298.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:61406.3-61418.6" - wire width 12 $1\MUL_function_unit[11:0] - attribute \src "libresoc.v:61432.3-61444.6" + attribute \src "libresoc.v:62234.3-62246.6" + wire width 14 $1\MUL_function_unit[13:0] + attribute \src "libresoc.v:62260.3-62272.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:61419.3-61431.6" + attribute \src "libresoc.v:62247.3-62259.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:61484.3-61496.6" + attribute \src "libresoc.v:62312.3-62324.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:61471.3-61483.6" + attribute \src "libresoc.v:62299.3-62311.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:61497.3-61509.6" + attribute \src "libresoc.v:62325.3-62337.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:61394.17-61394.211" - wire width 32 $ternary$libresoc.v:61394$3514_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:62222.17-62222.211" + wire width 32 $ternary$libresoc.v:62222$3515_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \MUL_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 20 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 19 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 25 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 output 18 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \MUL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \MUL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 23 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 21 \MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \MUL_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \MUL_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 24 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 22 \MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 19 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \MUL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 output 15 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \MUL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 17 \MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \MUL_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 16 \MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 13 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 11 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \MUL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 12 \MUL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -102527,16 +103366,18 @@ module \dec$180 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \MUL_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \MUL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \MUL_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 8 \MUL_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -102545,7 +103386,8 @@ module \dec$180 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -102553,23 +103395,26 @@ module \dec$180 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_MUL_dec31_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \MUL_dec31_MUL_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \MUL_dec31_MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -102585,7 +103430,7 @@ module \dec$180 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \MUL_dec31_MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -102661,35 +103506,38 @@ module \dec$180 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \MUL_dec31_MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \MUL_dec31_MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \MUL_dec31_MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \MUL_dec31_MUL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \MUL_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \MUL_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -102705,8 +103553,8 @@ module \dec$180 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 8 \MUL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -102781,468 +103629,481 @@ module \dec$180 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 output 14 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 28 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 26 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 27 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:60449.7-60449.15" + attribute \src "libresoc.v:61254.7-61254.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 29 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:61394$3514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:62222$3515 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:61394$3514_Y + connect \Y $ternary$libresoc.v:62222$3515_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:61395.13-61405.4" + attribute \src "libresoc.v:62223.13-62233.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -103254,53 +104115,53 @@ module \dec$180 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:60449.7-60449.20" - process $proc$libresoc.v:60449$3523 + attribute \src "libresoc.v:61254.7-61254.20" + process $proc$libresoc.v:61254$3524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:61406.3-61418.6" - process $proc$libresoc.v:61406$3515 + attribute \src "libresoc.v:62234.3-62246.6" + process $proc$libresoc.v:62234$3516 assign { } { } assign { } { } - assign $0\MUL_function_unit[11:0] $1\MUL_function_unit[11:0] - attribute \src "libresoc.v:61407.5-61407.29" + assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] + attribute \src "libresoc.v:62235.5-62235.29" switch \initial - attribute \src "libresoc.v:61407.9-61407.17" + attribute \src "libresoc.v:62235.9-62235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\MUL_function_unit[11:0] \MUL_dec31_MUL_dec31_function_unit + assign $1\MUL_function_unit[13:0] \MUL_dec31_MUL_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } - assign $1\MUL_function_unit[11:0] 12'000100000000 + assign $1\MUL_function_unit[13:0] 14'00000100000000 case - assign $1\MUL_function_unit[11:0] 12'000000000000 + assign $1\MUL_function_unit[13:0] 14'00000000000000 end sync always - update \MUL_function_unit $0\MUL_function_unit[11:0] + update \MUL_function_unit $0\MUL_function_unit[13:0] end - attribute \src "libresoc.v:61419.3-61431.6" - process $proc$libresoc.v:61419$3516 + attribute \src "libresoc.v:62247.3-62259.6" + process $proc$libresoc.v:62247$3517 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:61420.5-61420.29" + attribute \src "libresoc.v:62248.5-62248.29" switch \initial - attribute \src "libresoc.v:61420.9-61420.17" + attribute \src "libresoc.v:62248.9-62248.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -103316,18 +104177,18 @@ module \dec$180 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:61432.3-61444.6" - process $proc$libresoc.v:61432$3517 + attribute \src "libresoc.v:62260.3-62272.6" + process $proc$libresoc.v:62260$3518 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:61433.5-61433.29" + attribute \src "libresoc.v:62261.5-62261.29" switch \initial - attribute \src "libresoc.v:61433.9-61433.17" + attribute \src "libresoc.v:62261.9-62261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -103343,18 +104204,18 @@ module \dec$180 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:61445.3-61457.6" - process $proc$libresoc.v:61445$3518 + attribute \src "libresoc.v:62273.3-62285.6" + process $proc$libresoc.v:62273$3519 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:61446.5-61446.29" + attribute \src "libresoc.v:62274.5-62274.29" switch \initial - attribute \src "libresoc.v:61446.9-61446.17" + attribute \src "libresoc.v:62274.9-62274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -103370,18 +104231,18 @@ module \dec$180 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:61458.3-61470.6" - process $proc$libresoc.v:61458$3519 + attribute \src "libresoc.v:62286.3-62298.6" + process $proc$libresoc.v:62286$3520 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:61459.5-61459.29" + attribute \src "libresoc.v:62287.5-62287.29" switch \initial - attribute \src "libresoc.v:61459.9-61459.17" + attribute \src "libresoc.v:62287.9-62287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -103397,18 +104258,18 @@ module \dec$180 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:61471.3-61483.6" - process $proc$libresoc.v:61471$3520 + attribute \src "libresoc.v:62299.3-62311.6" + process $proc$libresoc.v:62299$3521 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:61472.5-61472.29" + attribute \src "libresoc.v:62300.5-62300.29" switch \initial - attribute \src "libresoc.v:61472.9-61472.17" + attribute \src "libresoc.v:62300.9-62300.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -103424,18 +104285,18 @@ module \dec$180 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:61484.3-61496.6" - process $proc$libresoc.v:61484$3521 + attribute \src "libresoc.v:62312.3-62324.6" + process $proc$libresoc.v:62312$3522 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:61485.5-61485.29" + attribute \src "libresoc.v:62313.5-62313.29" switch \initial - attribute \src "libresoc.v:61485.9-61485.17" + attribute \src "libresoc.v:62313.9-62313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -103451,18 +104312,18 @@ module \dec$180 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:61497.3-61509.6" - process $proc$libresoc.v:61497$3522 + attribute \src "libresoc.v:62325.3-62337.6" + process $proc$libresoc.v:62325$3523 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:61498.5-61498.29" + attribute \src "libresoc.v:62326.5-62326.29" switch \initial - attribute \src "libresoc.v:61498.9-61498.17" + attribute \src "libresoc.v:62326.9-62326.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -103478,7 +104339,7 @@ module \dec$180 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:61394$3514_Y + connect \$1 $ternary$libresoc.v:62222$3515_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -103506,14 +104367,20 @@ module \dec$180 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -103805,307 +104672,310 @@ module \dec$180 connect \MUL_RA \opcode_in [20:16] connect \MUL_RT \opcode_in [25:21] connect \MUL_RS \opcode_in [25:21] + connect \MUL_PO \opcode_in [31:26] connect \opcode_in \$1 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:61843.1-63561.10" +attribute \src "libresoc.v:62678.1-64432.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" -module \dec$188 - attribute \src "libresoc.v:63143.3-63164.6" +module \dec$162 + attribute \src "libresoc.v:64007.3-64028.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63165.3-63186.6" + attribute \src "libresoc.v:64029.3-64050.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63209.3-63230.6" + attribute \src "libresoc.v:64073.3-64094.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63011.3-63032.6" + attribute \src "libresoc.v:63875.3-63896.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63077.3-63098.6" - wire width 12 $0\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:63121.3-63142.6" + attribute \src "libresoc.v:63941.3-63962.6" + wire width 14 $0\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:63985.3-64006.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63099.3-63120.6" + attribute \src "libresoc.v:63963.3-63984.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:62989.3-63010.6" + attribute \src "libresoc.v:63853.3-63874.6" wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63033.3-63054.6" + attribute \src "libresoc.v:63897.3-63918.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63187.3-63208.6" + attribute \src "libresoc.v:64051.3-64072.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63055.3-63076.6" + attribute \src "libresoc.v:63919.3-63940.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:61844.7-61844.20" + attribute \src "libresoc.v:62679.7-62679.20" wire $0\initial[0:0] - attribute \src "libresoc.v:63143.3-63164.6" + attribute \src "libresoc.v:64007.3-64028.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63165.3-63186.6" + attribute \src "libresoc.v:64029.3-64050.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63209.3-63230.6" + attribute \src "libresoc.v:64073.3-64094.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63011.3-63032.6" + attribute \src "libresoc.v:63875.3-63896.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63077.3-63098.6" - wire width 12 $1\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:63121.3-63142.6" + attribute \src "libresoc.v:63941.3-63962.6" + wire width 14 $1\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:63985.3-64006.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63099.3-63120.6" + attribute \src "libresoc.v:63963.3-63984.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:62989.3-63010.6" + attribute \src "libresoc.v:63853.3-63874.6" wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63033.3-63054.6" + attribute \src "libresoc.v:63897.3-63918.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63187.3-63208.6" + attribute \src "libresoc.v:64051.3-64072.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63055.3-63076.6" + attribute \src "libresoc.v:63919.3-63940.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62960.17-62960.211" - wire width 32 $ternary$libresoc.v:62960$3524_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:63824.17-63824.211" + wire width 32 $ternary$libresoc.v:63824$3525_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SHIFT_ROT_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 23 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 22 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 28 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 21 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 22 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \SHIFT_ROT_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \SHIFT_ROT_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 26 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 24 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \SHIFT_ROT_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \SHIFT_ROT_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 27 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 25 \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 23 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SHIFT_ROT_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 output 18 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 output 19 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SHIFT_ROT_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 20 \SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 21 \SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \SHIFT_ROT_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 19 \SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 20 \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 16 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 output 14 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \SHIFT_ROT_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 17 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 15 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 output 15 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 16 \SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -104114,24 +104984,26 @@ module \dec$188 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 8 \SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 10 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 11 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \SHIFT_ROT_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -104140,7 +105012,8 @@ module \dec$188 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -104148,31 +105021,34 @@ module \dec$188 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -104188,7 +105064,7 @@ module \dec$188 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -104264,21 +105140,22 @@ module \dec$188 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SHIFT_ROT_dec30_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -104288,7 +105165,8 @@ module \dec$188 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -104296,31 +105174,34 @@ module \dec$188 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -104336,7 +105217,7 @@ module \dec$188 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -104412,37 +105293,40 @@ module \dec$188 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SHIFT_ROT_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \SHIFT_ROT_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -104458,8 +105342,8 @@ module \dec$188 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 8 \SHIFT_ROT_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -104534,450 +105418,463 @@ module \dec$188 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \SHIFT_ROT_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \SHIFT_ROT_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 output 17 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 output 18 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 31 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 29 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 30 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:61844.7-61844.15" + attribute \src "libresoc.v:62679.7-62679.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 32 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:62960$3524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 24 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:63824$3525 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:62960$3524_Y + connect \Y $ternary$libresoc.v:63824$3525_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:62961.19-62974.4" + attribute \src "libresoc.v:63825.19-63838.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -104993,7 +105890,7 @@ module \dec$188 connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:62975.19-62988.4" + attribute \src "libresoc.v:63839.19-63852.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -105008,26 +105905,26 @@ module \dec$188 connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:61844.7-61844.20" - process $proc$libresoc.v:61844$3536 + attribute \src "libresoc.v:62679.7-62679.20" + process $proc$libresoc.v:62679$3537 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:62989.3-63010.6" - process $proc$libresoc.v:62989$3525 + attribute \src "libresoc.v:63853.3-63874.6" + process $proc$libresoc.v:63853$3526 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:62990.5-62990.29" + attribute \src "libresoc.v:63854.5-63854.29" switch \initial - attribute \src "libresoc.v:62990.9-62990.17" + attribute \src "libresoc.v:63854.9-63854.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105055,18 +105952,18 @@ module \dec$188 sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end - attribute \src "libresoc.v:63011.3-63032.6" - process $proc$libresoc.v:63011$3526 + attribute \src "libresoc.v:63875.3-63896.6" + process $proc$libresoc.v:63875$3527 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63012.5-63012.29" + attribute \src "libresoc.v:63876.5-63876.29" switch \initial - attribute \src "libresoc.v:63012.9-63012.17" + attribute \src "libresoc.v:63876.9-63876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105094,18 +105991,18 @@ module \dec$188 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:63033.3-63054.6" - process $proc$libresoc.v:63033$3527 + attribute \src "libresoc.v:63897.3-63918.6" + process $proc$libresoc.v:63897$3528 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63034.5-63034.29" + attribute \src "libresoc.v:63898.5-63898.29" switch \initial - attribute \src "libresoc.v:63034.9-63034.17" + attribute \src "libresoc.v:63898.9-63898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105133,18 +106030,18 @@ module \dec$188 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:63055.3-63076.6" - process $proc$libresoc.v:63055$3528 + attribute \src "libresoc.v:63919.3-63940.6" + process $proc$libresoc.v:63919$3529 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63056.5-63056.29" + attribute \src "libresoc.v:63920.5-63920.29" switch \initial - attribute \src "libresoc.v:63056.9-63056.17" + attribute \src "libresoc.v:63920.9-63920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105172,57 +106069,57 @@ module \dec$188 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:63077.3-63098.6" - process $proc$libresoc.v:63077$3529 + attribute \src "libresoc.v:63941.3-63962.6" + process $proc$libresoc.v:63941$3530 assign { } { } assign { } { } - assign $0\SHIFT_ROT_function_unit[11:0] $1\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:63078.5-63078.29" + assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:63942.5-63942.29" switch \initial - attribute \src "libresoc.v:63078.9-63078.17" + attribute \src "libresoc.v:63942.9-63942.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + assign $1\SHIFT_ROT_function_unit[13:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + assign $1\SHIFT_ROT_function_unit[13:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000000000 + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[11:0] + update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] end - attribute \src "libresoc.v:63099.3-63120.6" - process $proc$libresoc.v:63099$3530 + attribute \src "libresoc.v:63963.3-63984.6" + process $proc$libresoc.v:63963$3531 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63100.5-63100.29" + attribute \src "libresoc.v:63964.5-63964.29" switch \initial - attribute \src "libresoc.v:63100.9-63100.17" + attribute \src "libresoc.v:63964.9-63964.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105250,18 +106147,18 @@ module \dec$188 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:63121.3-63142.6" - process $proc$libresoc.v:63121$3531 + attribute \src "libresoc.v:63985.3-64006.6" + process $proc$libresoc.v:63985$3532 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63122.5-63122.29" + attribute \src "libresoc.v:63986.5-63986.29" switch \initial - attribute \src "libresoc.v:63122.9-63122.17" + attribute \src "libresoc.v:63986.9-63986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105289,18 +106186,18 @@ module \dec$188 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:63143.3-63164.6" - process $proc$libresoc.v:63143$3532 + attribute \src "libresoc.v:64007.3-64028.6" + process $proc$libresoc.v:64007$3533 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63144.5-63144.29" + attribute \src "libresoc.v:64008.5-64008.29" switch \initial - attribute \src "libresoc.v:63144.9-63144.17" + attribute \src "libresoc.v:64008.9-64008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105328,18 +106225,18 @@ module \dec$188 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:63165.3-63186.6" - process $proc$libresoc.v:63165$3533 + attribute \src "libresoc.v:64029.3-64050.6" + process $proc$libresoc.v:64029$3534 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63166.5-63166.29" + attribute \src "libresoc.v:64030.5-64030.29" switch \initial - attribute \src "libresoc.v:63166.9-63166.17" + attribute \src "libresoc.v:64030.9-64030.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105367,18 +106264,18 @@ module \dec$188 sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:63187.3-63208.6" - process $proc$libresoc.v:63187$3534 + attribute \src "libresoc.v:64051.3-64072.6" + process $proc$libresoc.v:64051$3535 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63188.5-63188.29" + attribute \src "libresoc.v:64052.5-64052.29" switch \initial - attribute \src "libresoc.v:63188.9-63188.17" + attribute \src "libresoc.v:64052.9-64052.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105406,18 +106303,18 @@ module \dec$188 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:63209.3-63230.6" - process $proc$libresoc.v:63209$3535 + attribute \src "libresoc.v:64073.3-64094.6" + process $proc$libresoc.v:64073$3536 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63210.5-63210.29" + attribute \src "libresoc.v:64074.5-64074.29" switch \initial - attribute \src "libresoc.v:63210.9-63210.17" + attribute \src "libresoc.v:64074.9-64074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105445,7 +106342,7 @@ module \dec$188 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:62960$3524_Y + connect \$1 $ternary$libresoc.v:63824$3525_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -105473,14 +106370,20 @@ module \dec$188 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -105772,261 +106675,264 @@ module \dec$188 connect \SHIFT_ROT_RA \opcode_in [20:16] connect \SHIFT_ROT_RT \opcode_in [25:21] connect \SHIFT_ROT_RS \opcode_in [25:21] + connect \SHIFT_ROT_PO \opcode_in [31:26] connect \opcode_in \$1 connect \SHIFT_ROT_dec31_opcode_in \opcode_in connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:63565.1-66034.10" +attribute \src "libresoc.v:64436.1-66945.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" -module \dec$196 - attribute \src "libresoc.v:65123.3-65180.6" +module \dec$166 + attribute \src "libresoc.v:66027.3-66084.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:65587.3-65644.6" + attribute \src "libresoc.v:66491.3-66548.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:65645.3-65702.6" + attribute \src "libresoc.v:66549.3-66606.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:65355.3-65412.6" - wire width 12 $0\LDST_function_unit[11:0] - attribute \src "libresoc.v:65471.3-65528.6" + attribute \src "libresoc.v:66259.3-66316.6" + wire width 14 $0\LDST_function_unit[13:0] + attribute \src "libresoc.v:66375.3-66432.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:65529.3-65586.6" + attribute \src "libresoc.v:66433.3-66490.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:65413.3-65470.6" + attribute \src "libresoc.v:66317.3-66374.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:65239.3-65296.6" + attribute \src "libresoc.v:66143.3-66200.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:64949.3-65006.6" + attribute \src "libresoc.v:65853.3-65910.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65065.3-65122.6" + attribute \src "libresoc.v:65969.3-66026.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65297.3-65354.6" + attribute \src "libresoc.v:66201.3-66258.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:65181.3-65238.6" + attribute \src "libresoc.v:66085.3-66142.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65007.3-65064.6" + attribute \src "libresoc.v:65911.3-65968.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:63566.7-63566.20" + attribute \src "libresoc.v:64437.7-64437.20" wire $0\initial[0:0] - attribute \src "libresoc.v:65123.3-65180.6" + attribute \src "libresoc.v:66027.3-66084.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:65587.3-65644.6" + attribute \src "libresoc.v:66491.3-66548.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:65645.3-65702.6" + attribute \src "libresoc.v:66549.3-66606.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:65355.3-65412.6" - wire width 12 $1\LDST_function_unit[11:0] - attribute \src "libresoc.v:65471.3-65528.6" + attribute \src "libresoc.v:66259.3-66316.6" + wire width 14 $1\LDST_function_unit[13:0] + attribute \src "libresoc.v:66375.3-66432.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:65529.3-65586.6" + attribute \src "libresoc.v:66433.3-66490.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:65413.3-65470.6" + attribute \src "libresoc.v:66317.3-66374.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:65239.3-65296.6" + attribute \src "libresoc.v:66143.3-66200.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:64949.3-65006.6" + attribute \src "libresoc.v:65853.3-65910.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65065.3-65122.6" + attribute \src "libresoc.v:65969.3-66026.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65297.3-65354.6" + attribute \src "libresoc.v:66201.3-66258.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:65181.3-65238.6" + attribute \src "libresoc.v:66085.3-66142.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65007.3-65064.6" + attribute \src "libresoc.v:65911.3-65968.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:64900.17-64900.211" - wire width 32 $ternary$libresoc.v:64900$3537_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:65804.17-65804.211" + wire width 32 $ternary$libresoc.v:65804$3538_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LDST_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 26 \LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 25 \LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 31 \LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 output 24 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \LDST_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \LDST_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 29 \LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 27 \LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \LDST_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \LDST_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 30 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 28 \LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 25 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LDST_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 output 21 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LDST_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 23 \LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \LDST_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 16 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 22 \LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 19 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 17 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \LDST_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \LDST_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 18 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 13 \LDST_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -106036,17 +106942,19 @@ module \dec$196 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \LDST_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -106056,7 +106964,8 @@ module \dec$196 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -106064,30 +106973,33 @@ module \dec$196 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_LDST_dec31_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LDST_dec31_LDST_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -106104,7 +107016,7 @@ module \dec$196 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -106180,9 +107092,10 @@ module \dec$196 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_LDST_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -106190,28 +107103,28 @@ module \dec$196 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec31_LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_LDST_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_LDST_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec31_LDST_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec31_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec58_LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -106221,7 +107134,8 @@ module \dec$196 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec58_LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -106229,30 +107143,33 @@ module \dec$196 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec58_LDST_dec58_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LDST_dec58_LDST_dec58_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec58_LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec58_LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -106269,7 +107186,7 @@ module \dec$196 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec58_LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -106345,9 +107262,10 @@ module \dec$196 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec58_LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec58_LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -106355,28 +107273,28 @@ module \dec$196 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec58_LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec58_LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec58_LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec58_LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec58_LDST_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec58_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec62_LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -106386,7 +107304,8 @@ module \dec$196 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec62_LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -106394,30 +107313,33 @@ module \dec$196 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec62_LDST_dec62_cr_out attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LDST_dec62_LDST_dec62_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec62_LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec62_LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -106434,7 +107356,7 @@ module \dec$196 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec62_LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -106510,9 +107432,10 @@ module \dec$196 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec62_LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec62_LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -106520,50 +107443,52 @@ module \dec$196 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \LDST_dec62_LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec62_LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec62_LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec62_LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \LDST_dec62_LDST_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec62_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \LDST_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 8 \LDST_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -106579,8 +107504,8 @@ module \dec$196 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 9 \LDST_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -106655,9 +107580,10 @@ module \dec$196 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -106665,511 +107591,523 @@ module \dec$196 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 output 10 \LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 output 20 \LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 15 \LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_IMM8 - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:63566.7-63566.15" + attribute \src "libresoc.v:64437.7-64437.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 35 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:64900$3537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 26 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:65804$3538 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:64900$3537_Y + connect \Y $ternary$libresoc.v:65804$3538_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:64901.14-64916.4" + attribute \src "libresoc.v:65805.14-65820.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -107187,7 +108125,7 @@ module \dec$196 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:64917.14-64932.4" + attribute \src "libresoc.v:65821.14-65836.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -107205,7 +108143,7 @@ module \dec$196 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:64933.14-64948.4" + attribute \src "libresoc.v:65837.14-65852.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -107222,26 +108160,26 @@ module \dec$196 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:63566.7-63566.20" - process $proc$libresoc.v:63566$3551 + attribute \src "libresoc.v:64437.7-64437.20" + process $proc$libresoc.v:64437$3552 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:64949.3-65006.6" - process $proc$libresoc.v:64949$3538 + attribute \src "libresoc.v:65853.3-65910.6" + process $proc$libresoc.v:65853$3539 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:64950.5-64950.29" + attribute \src "libresoc.v:65854.5-65854.29" switch \initial - attribute \src "libresoc.v:64950.9-64950.17" + attribute \src "libresoc.v:65854.9-65854.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107317,18 +108255,18 @@ module \dec$196 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:65007.3-65064.6" - process $proc$libresoc.v:65007$3539 + attribute \src "libresoc.v:65911.3-65968.6" + process $proc$libresoc.v:65911$3540 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:65008.5-65008.29" + attribute \src "libresoc.v:65912.5-65912.29" switch \initial - attribute \src "libresoc.v:65008.9-65008.17" + attribute \src "libresoc.v:65912.9-65912.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107404,18 +108342,18 @@ module \dec$196 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:65065.3-65122.6" - process $proc$libresoc.v:65065$3540 + attribute \src "libresoc.v:65969.3-66026.6" + process $proc$libresoc.v:65969$3541 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65066.5-65066.29" + attribute \src "libresoc.v:65970.5-65970.29" switch \initial - attribute \src "libresoc.v:65066.9-65066.17" + attribute \src "libresoc.v:65970.9-65970.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107491,18 +108429,18 @@ module \dec$196 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:65123.3-65180.6" - process $proc$libresoc.v:65123$3541 + attribute \src "libresoc.v:66027.3-66084.6" + process $proc$libresoc.v:66027$3542 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:65124.5-65124.29" + attribute \src "libresoc.v:66028.5-66028.29" switch \initial - attribute \src "libresoc.v:65124.9-65124.17" + attribute \src "libresoc.v:66028.9-66028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107578,18 +108516,18 @@ module \dec$196 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:65181.3-65238.6" - process $proc$libresoc.v:65181$3542 + attribute \src "libresoc.v:66085.3-66142.6" + process $proc$libresoc.v:66085$3543 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65182.5-65182.29" + attribute \src "libresoc.v:66086.5-66086.29" switch \initial - attribute \src "libresoc.v:65182.9-65182.17" + attribute \src "libresoc.v:66086.9-66086.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107665,18 +108603,18 @@ module \dec$196 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:65239.3-65296.6" - process $proc$libresoc.v:65239$3543 + attribute \src "libresoc.v:66143.3-66200.6" + process $proc$libresoc.v:66143$3544 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65240.5-65240.29" + attribute \src "libresoc.v:66144.5-66144.29" switch \initial - attribute \src "libresoc.v:65240.9-65240.17" + attribute \src "libresoc.v:66144.9-66144.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107752,18 +108690,18 @@ module \dec$196 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:65297.3-65354.6" - process $proc$libresoc.v:65297$3544 + attribute \src "libresoc.v:66201.3-66258.6" + process $proc$libresoc.v:66201$3545 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:65298.5-65298.29" + attribute \src "libresoc.v:66202.5-66202.29" switch \initial - attribute \src "libresoc.v:65298.9-65298.17" + attribute \src "libresoc.v:66202.9-66202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107839,105 +108777,105 @@ module \dec$196 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:65355.3-65412.6" - process $proc$libresoc.v:65355$3545 + attribute \src "libresoc.v:66259.3-66316.6" + process $proc$libresoc.v:66259$3546 assign { } { } assign { } { } - assign $0\LDST_function_unit[11:0] $1\LDST_function_unit[11:0] - attribute \src "libresoc.v:65356.5-65356.29" + assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] + attribute \src "libresoc.v:66260.5-66260.29" switch \initial - attribute \src "libresoc.v:65356.9-65356.17" + attribute \src "libresoc.v:66260.9-66260.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec31_LDST_dec31_function_unit + assign $1\LDST_function_unit[13:0] \LDST_dec31_LDST_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec58_LDST_dec58_function_unit + assign $1\LDST_function_unit[13:0] \LDST_dec58_LDST_dec58_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec62_LDST_dec62_function_unit + assign $1\LDST_function_unit[13:0] \LDST_dec62_LDST_dec62_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_function_unit[11:0] 12'000000000000 + assign $1\LDST_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_function_unit $0\LDST_function_unit[11:0] + update \LDST_function_unit $0\LDST_function_unit[13:0] end - attribute \src "libresoc.v:65413.3-65470.6" - process $proc$libresoc.v:65413$3546 + attribute \src "libresoc.v:66317.3-66374.6" + process $proc$libresoc.v:66317$3547 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:65414.5-65414.29" + attribute \src "libresoc.v:66318.5-66318.29" switch \initial - attribute \src "libresoc.v:65414.9-65414.17" + attribute \src "libresoc.v:66318.9-66318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108013,18 +108951,18 @@ module \dec$196 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:65471.3-65528.6" - process $proc$libresoc.v:65471$3547 + attribute \src "libresoc.v:66375.3-66432.6" + process $proc$libresoc.v:66375$3548 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:65472.5-65472.29" + attribute \src "libresoc.v:66376.5-66376.29" switch \initial - attribute \src "libresoc.v:65472.9-65472.17" + attribute \src "libresoc.v:66376.9-66376.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108100,18 +109038,18 @@ module \dec$196 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:65529.3-65586.6" - process $proc$libresoc.v:65529$3548 + attribute \src "libresoc.v:66433.3-66490.6" + process $proc$libresoc.v:66433$3549 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:65530.5-65530.29" + attribute \src "libresoc.v:66434.5-66434.29" switch \initial - attribute \src "libresoc.v:65530.9-65530.17" + attribute \src "libresoc.v:66434.9-66434.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108187,18 +109125,18 @@ module \dec$196 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:65587.3-65644.6" - process $proc$libresoc.v:65587$3549 + attribute \src "libresoc.v:66491.3-66548.6" + process $proc$libresoc.v:66491$3550 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:65588.5-65588.29" + attribute \src "libresoc.v:66492.5-66492.29" switch \initial - attribute \src "libresoc.v:65588.9-65588.17" + attribute \src "libresoc.v:66492.9-66492.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108274,18 +109212,18 @@ module \dec$196 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:65645.3-65702.6" - process $proc$libresoc.v:65645$3550 + attribute \src "libresoc.v:66549.3-66606.6" + process $proc$libresoc.v:66549$3551 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:65646.5-65646.29" + attribute \src "libresoc.v:66550.5-66550.29" switch \initial - attribute \src "libresoc.v:65646.9-65646.17" + attribute \src "libresoc.v:66550.9-66550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108361,7 +109299,7 @@ module \dec$196 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:64900$3537_Y + connect \$1 $ternary$libresoc.v:65804$3538_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -108389,14 +109327,20 @@ module \dec$196 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -108688,822 +109632,897 @@ module \dec$196 connect \LDST_RA \opcode_in [20:16] connect \LDST_RT \opcode_in [25:21] connect \LDST_RS \opcode_in [25:21] + connect \LDST_PO \opcode_in [31:26] connect \opcode_in \$1 connect \LDST_dec62_opcode_in \opcode_in connect \LDST_dec58_opcode_in \opcode_in connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:66038.1-71971.10" +attribute \src "libresoc.v:66949.1-74952.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" -module \dec$205 - attribute \src "libresoc.v:68232.3-68370.6" +module \dec$171 + attribute \src "libresoc.v:70260.3-70404.6" + wire width 2 $0\SV_Etype[1:0] + attribute \src "libresoc.v:70405.3-70549.6" + wire width 2 $0\SV_Ptype[1:0] + attribute \src "libresoc.v:70118.3-70259.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:70217.3-70358.6" + attribute \src "libresoc.v:73305.3-73449.6" wire $0\br[0:0] - attribute \src "libresoc.v:68939.3-69080.6" + attribute \src "libresoc.v:71130.3-71274.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:69081.3-69222.6" + attribute \src "libresoc.v:71275.3-71419.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:69649.3-69790.6" + attribute \src "libresoc.v:72725.3-72869.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:70075.3-70216.6" + attribute \src "libresoc.v:73160.3-73304.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:71495.3-71636.6" + attribute \src "libresoc.v:69973.3-70117.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:71211.3-71352.6" - wire width 12 $0\function_unit[11:0] - attribute \src "libresoc.v:68371.3-68512.6" + attribute \src "libresoc.v:74320.3-74464.6" + wire width 14 $0\function_unit[13:0] + attribute \src "libresoc.v:70550.3-70694.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:68513.3-68654.6" + attribute \src "libresoc.v:70695.3-70839.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:68655.3-68796.6" + attribute \src "libresoc.v:70840.3-70984.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:66039.7-66039.20" + attribute \src "libresoc.v:66950.7-66950.20" wire $0\initial[0:0] - attribute \src "libresoc.v:71353.3-71494.6" + attribute \src "libresoc.v:74465.3-74609.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:69791.3-69932.6" + attribute \src "libresoc.v:72870.3-73014.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:69933.3-70074.6" + attribute \src "libresoc.v:73015.3-73159.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:70643.3-70784.6" + attribute \src "libresoc.v:73740.3-73884.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:69223.3-69364.6" + attribute \src "libresoc.v:72290.3-72434.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:70927.3-71068.6" + attribute \src "libresoc.v:74030.3-74174.6" wire $0\lk[0:0] - attribute \src "libresoc.v:68797.3-68938.6" - wire width 2 $0\out_sel[1:0] - attribute \src "libresoc.v:69507.3-69648.6" + attribute \src "libresoc.v:70985.3-71129.6" + wire width 3 $0\out_sel[2:0] + attribute \src "libresoc.v:72580.3-72724.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:70501.3-70642.6" + attribute \src "libresoc.v:73595.3-73739.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:71069.3-71210.6" + attribute \src "libresoc.v:74175.3-74319.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:70785.3-70926.6" + attribute \src "libresoc.v:73885.3-74029.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:70359.3-70500.6" + attribute \src "libresoc.v:73450.3-73594.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:69365.3-69506.6" + attribute \src "libresoc.v:72000.3-72144.6" + wire width 3 $0\sv_cr_in[2:0] + attribute \src "libresoc.v:72145.3-72289.6" + wire width 3 $0\sv_cr_out[2:0] + attribute \src "libresoc.v:71420.3-71564.6" + wire width 3 $0\sv_in1[2:0] + attribute \src "libresoc.v:71565.3-71709.6" + wire width 3 $0\sv_in2[2:0] + attribute \src "libresoc.v:71710.3-71854.6" + wire width 3 $0\sv_in3[2:0] + attribute \src "libresoc.v:71855.3-71999.6" + wire width 3 $0\sv_out[2:0] + attribute \src "libresoc.v:72435.3-72579.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:68232.3-68370.6" + attribute \src "libresoc.v:70260.3-70404.6" + wire width 2 $1\SV_Etype[1:0] + attribute \src "libresoc.v:70405.3-70549.6" + wire width 2 $1\SV_Ptype[1:0] + attribute \src "libresoc.v:70118.3-70259.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:70217.3-70358.6" + attribute \src "libresoc.v:73305.3-73449.6" wire $1\br[0:0] - attribute \src "libresoc.v:68939.3-69080.6" + attribute \src "libresoc.v:71130.3-71274.6" wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:69081.3-69222.6" + attribute \src "libresoc.v:71275.3-71419.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:69649.3-69790.6" + attribute \src "libresoc.v:72725.3-72869.6" wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:70075.3-70216.6" + attribute \src "libresoc.v:73160.3-73304.6" wire $1\cry_out[0:0] - attribute \src "libresoc.v:71495.3-71636.6" + attribute \src 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attribute \src "libresoc.v:69365.3-69506.6" + attribute \src "libresoc.v:72000.3-72144.6" + wire width 3 $1\sv_cr_in[2:0] + attribute \src "libresoc.v:72145.3-72289.6" + wire width 3 $1\sv_cr_out[2:0] + attribute \src "libresoc.v:71420.3-71564.6" + wire width 3 $1\sv_in1[2:0] + attribute \src "libresoc.v:71565.3-71709.6" + wire width 3 $1\sv_in2[2:0] + attribute \src "libresoc.v:71710.3-71854.6" + wire width 3 $1\sv_in3[2:0] + attribute \src "libresoc.v:71855.3-71999.6" + wire width 3 $1\sv_out[2:0] + attribute \src "libresoc.v:72435.3-72579.6" wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:68232.3-68370.6" + attribute \src "libresoc.v:70260.3-70404.6" + wire width 2 $2\SV_Etype[1:0] + attribute \src "libresoc.v:70405.3-70549.6" + wire width 2 $2\SV_Ptype[1:0] + attribute \src "libresoc.v:70118.3-70259.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:70217.3-70358.6" + attribute \src "libresoc.v:73305.3-73449.6" wire $2\br[0:0] - attribute \src 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wire width 3 $2\sv_out[2:0] + attribute \src "libresoc.v:72435.3-72579.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:68096.17-68096.211" - wire width 32 $ternary$libresoc.v:68096$3552_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + attribute \src "libresoc.v:69762.17-69762.211" + wire width 32 $ternary$libresoc.v:69762$3553_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 25 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 24 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 30 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 26 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 25 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 31 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 29 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 28 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 26 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 30 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 29 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 27 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 27 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 28 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 11 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 23 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 20 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 21 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 18 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 19 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 22 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 24 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 21 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 22 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 19 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 20 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 23 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 output 31 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 5 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 output 35 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 16 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 17 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 36 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -109513,27 +110532,41 @@ module \dec$205 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec19_dec19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec19_dec19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec19_dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -109543,7 +110576,8 @@ module \dec$205 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec19_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -109551,15 +110585,16 @@ module \dec$205 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec19_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec19_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -109591,30 +110626,33 @@ module \dec$205 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec19_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec19_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec19_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -109631,13 +110669,13 @@ module \dec$205 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec19_dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec19_dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -109713,13 +110751,14 @@ module \dec$205 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec19_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -109727,44 +110766,111 @@ module \dec$205 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec19_dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec19_dec19_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec19_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec19_dec19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec19_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec30_dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_br + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 \dec22_dec22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -109773,24 +110879,26 @@ module \dec$205 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec30_dec30_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec30_dec30_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -109821,31 +110929,34 @@ module \dec$205 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec30_dec30_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 \dec22_dec22_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec30_dec30_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec22_dec22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec30_dec30_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -109861,14 +110972,14 @@ module \dec$205 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec30_dec30_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec22_dec22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -109943,288 +111054,126 @@ module \dec$205 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec30_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec22_dec22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec30_dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec22_dec22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec30_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_br - attribute \enum_base_type "CRInSel" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_sgn_ext + attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec31_cr_in - attribute \enum_base_type "CROutSel" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_cr_in + attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec31_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec31_function_unit - attribute \enum_base_type "In1Sel" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_cr_out + attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec31_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_sgn_ext + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec58_dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec22_opcode_in + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec30_dec30_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec30_dec30_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 \dec30_dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -110233,24 +111182,26 @@ module \dec$205 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec58_dec58_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec58_dec58_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec30_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -110281,31 +111232,34 @@ module \dec$205 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec58_dec58_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 \dec30_dec30_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec58_dec58_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec30_dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec58_dec58_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -110321,14 +111275,14 @@ module \dec$205 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec58_dec58_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec30_dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec30_dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -110403,58 +111357,126 @@ module \dec$205 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec58_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec30_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec58_dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec30_dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec30_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec30_dec30_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec30_dec30_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec58_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec62_dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec30_dec30_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec30_opcode_in + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec31_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec31_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 \dec31_dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -110463,24 +111485,26 @@ module \dec$205 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec62_dec62_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec62_dec62_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec62_dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -110511,30 +111535,639 @@ module \dec$205 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 \dec31_dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec31_dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec31_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec31_dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec31_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec31_sv_out + attribute \enum_base_type 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+ wire width 3 \dec58_dec58_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec58_dec58_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec58_opcode_in + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec62_dec62_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec62_dec62_SV_Ptype + attribute \src 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\dec62_dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec62_dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec62_dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec62_dec62_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec62_dec62_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec62_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec62_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -110551,13 +112184,13 @@ module \dec$205 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec62_dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec62_dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -110633,13 +112266,14 @@ module \dec$205 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec62_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -110647,39 +112281,94 @@ module \dec$205 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec62_dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec62_dec62_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec62_dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec62_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec62_dec62_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec62_dec62_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec62_dec62_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec62_dec62_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec62_dec62_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec62_dec62_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec62_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec62_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -110711,31 +112400,34 @@ module \dec$205 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 12 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -110751,15 +112443,15 @@ module \dec$205 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 13 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 14 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \in3_sel - attribute \src "libresoc.v:66039.7-66039.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 15 \in3_sel + attribute \src "libresoc.v:66950.7-66950.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -110835,13 +112527,14 @@ module \dec$205 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 4 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -110849,59 +112542,116 @@ module \dec$205 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 32 \opcode_switch$1 attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 15 \out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 1 \raw_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \sh + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 17 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:68096$3552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 18 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:69762$3553 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:68096$3552_Y + connect \Y $ternary$libresoc.v:69762$3553_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:68097.9-68123.4" + attribute \src "libresoc.v:69763.9-69797.4" cell \dec19 \dec19 + connect \dec19_SV_Etype \dec19_dec19_SV_Etype + connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype connect \dec19_asmcode \dec19_dec19_asmcode connect \dec19_br \dec19_dec19_br connect \dec19_cr_in \dec19_dec19_cr_in @@ -110925,12 +112675,57 @@ module \dec$205 connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe connect \dec19_sgn \dec19_dec19_sgn connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_sv_cr_in \dec19_dec19_sv_cr_in + connect \dec19_sv_cr_out \dec19_dec19_sv_cr_out + connect \dec19_sv_in1 \dec19_dec19_sv_in1 + connect \dec19_sv_in2 \dec19_dec19_sv_in2 + connect \dec19_sv_in3 \dec19_dec19_sv_in3 + connect \dec19_sv_out \dec19_dec19_sv_out connect \dec19_upd \dec19_dec19_upd connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:68124.9-68150.4" + attribute \src "libresoc.v:69798.9-69832.4" + cell \dec22 \dec22 + connect \dec22_SV_Etype \dec22_dec22_SV_Etype + connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype + connect \dec22_asmcode \dec22_dec22_asmcode + connect \dec22_br \dec22_dec22_br + connect \dec22_cr_in \dec22_dec22_cr_in + connect \dec22_cr_out \dec22_dec22_cr_out + connect \dec22_cry_in \dec22_dec22_cry_in + connect \dec22_cry_out \dec22_dec22_cry_out + connect \dec22_form \dec22_dec22_form + connect \dec22_function_unit \dec22_dec22_function_unit + connect \dec22_in1_sel \dec22_dec22_in1_sel + connect \dec22_in2_sel \dec22_dec22_in2_sel + connect \dec22_in3_sel \dec22_dec22_in3_sel + connect \dec22_internal_op \dec22_dec22_internal_op + connect \dec22_inv_a \dec22_dec22_inv_a + connect \dec22_inv_out \dec22_dec22_inv_out + connect \dec22_is_32b \dec22_dec22_is_32b + connect \dec22_ldst_len \dec22_dec22_ldst_len + connect \dec22_lk \dec22_dec22_lk + connect \dec22_out_sel \dec22_dec22_out_sel + connect \dec22_rc_sel \dec22_dec22_rc_sel + connect \dec22_rsrv \dec22_dec22_rsrv + connect \dec22_sgl_pipe \dec22_dec22_sgl_pipe + connect \dec22_sgn \dec22_dec22_sgn + connect \dec22_sgn_ext \dec22_dec22_sgn_ext + connect \dec22_sv_cr_in \dec22_dec22_sv_cr_in + connect \dec22_sv_cr_out \dec22_dec22_sv_cr_out + connect \dec22_sv_in1 \dec22_dec22_sv_in1 + connect \dec22_sv_in2 \dec22_dec22_sv_in2 + connect \dec22_sv_in3 \dec22_dec22_sv_in3 + connect \dec22_sv_out \dec22_dec22_sv_out + connect \dec22_upd \dec22_dec22_upd + connect \opcode_in \dec22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69833.9-69867.4" cell \dec30 \dec30 + connect \dec30_SV_Etype \dec30_dec30_SV_Etype + connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype connect \dec30_asmcode \dec30_dec30_asmcode connect \dec30_br \dec30_dec30_br connect \dec30_cr_in \dec30_dec30_cr_in @@ -110954,12 +112749,20 @@ module \dec$205 connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe connect \dec30_sgn \dec30_dec30_sgn connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_sv_cr_in \dec30_dec30_sv_cr_in + connect \dec30_sv_cr_out \dec30_dec30_sv_cr_out + connect \dec30_sv_in1 \dec30_dec30_sv_in1 + connect \dec30_sv_in2 \dec30_dec30_sv_in2 + connect \dec30_sv_in3 \dec30_dec30_sv_in3 + connect \dec30_sv_out \dec30_dec30_sv_out connect \dec30_upd \dec30_dec30_upd connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:68151.9-68177.4" + attribute \src "libresoc.v:69868.9-69902.4" cell \dec31 \dec31 + connect \dec31_SV_Etype \dec31_dec31_SV_Etype + connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype connect \dec31_asmcode \dec31_dec31_asmcode connect \dec31_br \dec31_dec31_br connect \dec31_cr_in \dec31_dec31_cr_in @@ -110983,12 +112786,20 @@ module \dec$205 connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe connect \dec31_sgn \dec31_dec31_sgn connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_sv_cr_in \dec31_dec31_sv_cr_in + connect \dec31_sv_cr_out \dec31_dec31_sv_cr_out + connect \dec31_sv_in1 \dec31_dec31_sv_in1 + connect \dec31_sv_in2 \dec31_dec31_sv_in2 + connect \dec31_sv_in3 \dec31_dec31_sv_in3 + connect \dec31_sv_out \dec31_dec31_sv_out connect \dec31_upd \dec31_dec31_upd connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:68178.9-68204.4" + attribute \src "libresoc.v:69903.9-69937.4" cell \dec58 \dec58 + connect \dec58_SV_Etype \dec58_dec58_SV_Etype + connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype connect \dec58_asmcode \dec58_dec58_asmcode connect \dec58_br \dec58_dec58_br connect \dec58_cr_in \dec58_dec58_cr_in @@ -111012,12 +112823,20 @@ module \dec$205 connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe connect \dec58_sgn \dec58_dec58_sgn connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_sv_cr_in \dec58_dec58_sv_cr_in + connect \dec58_sv_cr_out \dec58_dec58_sv_cr_out + connect \dec58_sv_in1 \dec58_dec58_sv_in1 + connect \dec58_sv_in2 \dec58_dec58_sv_in2 + connect \dec58_sv_in3 \dec58_dec58_sv_in3 + connect \dec58_sv_out \dec58_dec58_sv_out connect \dec58_upd \dec58_dec58_upd connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:68205.9-68231.4" + attribute \src "libresoc.v:69938.9-69972.4" cell \dec62 \dec62 + connect \dec62_SV_Etype \dec62_dec62_SV_Etype + connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype connect \dec62_asmcode \dec62_dec62_asmcode connect \dec62_br \dec62_dec62_br connect \dec62_cr_in \dec62_dec62_cr_in @@ -111041,30 +112860,241 @@ module \dec$205 connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe connect \dec62_sgn \dec62_dec62_sgn connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_sv_cr_in \dec62_dec62_sv_cr_in + connect \dec62_sv_cr_out \dec62_dec62_sv_cr_out + connect \dec62_sv_in1 \dec62_dec62_sv_in1 + connect \dec62_sv_in2 \dec62_dec62_sv_in2 + connect \dec62_sv_in3 \dec62_dec62_sv_in3 + connect \dec62_sv_out \dec62_dec62_sv_out connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:66039.7-66039.20" - process $proc$libresoc.v:66039$3577 + attribute \src "libresoc.v:66950.7-66950.20" + process $proc$libresoc.v:66950$3586 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:68232.3-68370.6" - process $proc$libresoc.v:68232$3553 + attribute \src "libresoc.v:69973.3-70117.6" + process $proc$libresoc.v:69973$3554 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:69974.5-69974.29" + switch \initial + attribute \src "libresoc.v:69974.9-69974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\form[4:0] \dec22_dec22_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + attribute \src "libresoc.v:70118.3-70259.6" + process $proc$libresoc.v:70118$3555 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:68233.5-68233.29" + attribute \src "libresoc.v:70119.5-70119.29" switch \initial - attribute \src "libresoc.v:68233.9-68233.17" + attribute \src "libresoc.v:70119.9-70119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111087,6 +113117,10 @@ module \dec$205 assign { } { } assign $1\asmcode[7:0] \dec62_dec62_asmcode attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\asmcode[7:0] \dec22_dec22_asmcode + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\asmcode[7:0] 8'00000111 @@ -111185,51 +113219,51 @@ module \dec$205 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\asmcode[7:0] 8'10100110 + assign $1\asmcode[7:0] 8'10100111 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\asmcode[7:0] 8'10101001 + assign $1\asmcode[7:0] 8'10101010 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\asmcode[7:0] 8'10110010 + assign $1\asmcode[7:0] 8'10110011 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\asmcode[7:0] 8'10110101 + assign $1\asmcode[7:0] 8'10110110 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\asmcode[7:0] 8'10111000 + assign $1\asmcode[7:0] 8'10111001 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\asmcode[7:0] 8'10111011 + assign $1\asmcode[7:0] 8'10111100 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\asmcode[7:0] 8'11000011 + assign $1\asmcode[7:0] 8'11000100 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } - assign $1\asmcode[7:0] 8'11001011 + assign $1\asmcode[7:0] 8'11001100 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } - assign $1\asmcode[7:0] 8'11001111 + assign $1\asmcode[7:0] 8'11010000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\asmcode[7:0] 8'11010001 + assign $1\asmcode[7:0] 8'11010010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\asmcode[7:0] 8'11010010 + assign $1\asmcode[7:0] 8'11010011 case assign $1\asmcode[7:0] 8'00000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111242,26 +113276,436 @@ module \dec$205 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } - assign $2\asmcode[7:0] 8'10011100 + assign $2\asmcode[7:0] 8'10011101 case assign $2\asmcode[7:0] $1\asmcode[7:0] end sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:68371.3-68512.6" - process $proc$libresoc.v:68371$3554 + attribute \src "libresoc.v:70260.3-70404.6" + process $proc$libresoc.v:70260$3556 + assign { } { } + assign { } { } + assign { } { } + assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] + attribute \src "libresoc.v:70261.5-70261.29" + switch \initial + attribute \src "libresoc.v:70261.9-70261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\SV_Etype[1:0] \dec19_dec19_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SV_Etype[1:0] \dec30_dec30_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SV_Etype[1:0] \dec31_dec31_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\SV_Etype[1:0] \dec58_dec58_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\SV_Etype[1:0] \dec62_dec62_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\SV_Etype[1:0] \dec22_dec22_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + case + assign $1\SV_Etype[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + case + assign $2\SV_Etype[1:0] $1\SV_Etype[1:0] + end + sync always + update \SV_Etype $0\SV_Etype[1:0] + end + attribute \src "libresoc.v:70405.3-70549.6" + process $proc$libresoc.v:70405$3557 + assign { } { } + assign { } { } + assign { } { } + assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] + attribute \src "libresoc.v:70406.5-70406.29" + switch \initial + attribute \src "libresoc.v:70406.9-70406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\SV_Ptype[1:0] \dec19_dec19_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec30_dec30_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SV_Ptype[1:0] \dec31_dec31_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\SV_Ptype[1:0] \dec58_dec58_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec62_dec62_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec22_dec22_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + case + assign $1\SV_Ptype[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + case + assign $2\SV_Ptype[1:0] $1\SV_Ptype[1:0] + end + sync always + update \SV_Ptype $0\SV_Ptype[1:0] + end + attribute \src "libresoc.v:70550.3-70694.6" + process $proc$libresoc.v:70550$3558 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:68372.5-68372.29" + attribute \src "libresoc.v:70551.5-70551.29" switch \initial - attribute \src "libresoc.v:68372.9-68372.17" + attribute \src "libresoc.v:70551.9-70551.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111284,6 +113728,10 @@ module \dec$205 assign { } { } assign $1\in1_sel[2:0] \dec62_dec62_in1_sel attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in1_sel[2:0] \dec22_dec22_in1_sel + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in1_sel[2:0] 3'001 @@ -111430,7 +113878,7 @@ module \dec$205 case assign $1\in1_sel[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111450,19 +113898,19 @@ module \dec$205 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:68513.3-68654.6" - process $proc$libresoc.v:68513$3555 + attribute \src "libresoc.v:70695.3-70839.6" + process $proc$libresoc.v:70695$3559 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:68514.5-68514.29" + attribute \src "libresoc.v:70696.5-70696.29" switch \initial - attribute \src "libresoc.v:68514.9-68514.17" + attribute \src "libresoc.v:70696.9-70696.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111485,6 +113933,10 @@ module \dec$205 assign { } { } assign $1\in2_sel[3:0] \dec62_dec62_in2_sel attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in2_sel[3:0] \dec22_dec22_in2_sel + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in2_sel[3:0] 4'0011 @@ -111631,7 +114083,7 @@ module \dec$205 case assign $1\in2_sel[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111651,19 +114103,19 @@ module \dec$205 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:68655.3-68796.6" - process $proc$libresoc.v:68655$3556 + attribute \src "libresoc.v:70840.3-70984.6" + process $proc$libresoc.v:70840$3560 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:68656.5-68656.29" + attribute \src "libresoc.v:70841.5-70841.29" switch \initial - attribute \src "libresoc.v:68656.9-68656.17" + attribute \src "libresoc.v:70841.9-70841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111686,6 +114138,10 @@ module \dec$205 assign { } { } assign $1\in3_sel[1:0] \dec62_dec62_in3_sel attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in3_sel[1:0] \dec22_dec22_in3_sel + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in3_sel[1:0] 2'00 @@ -111832,7 +114288,7 @@ module \dec$205 case assign $1\in3_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111852,220 +114308,224 @@ module \dec$205 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:68797.3-68938.6" - process $proc$libresoc.v:68797$3557 + attribute \src "libresoc.v:70985.3-71129.6" + process $proc$libresoc.v:70985$3561 assign { } { } assign { } { } assign { } { } - assign $0\out_sel[1:0] $2\out_sel[1:0] - attribute \src "libresoc.v:68798.5-68798.29" + assign $0\out_sel[2:0] $2\out_sel[2:0] + attribute \src "libresoc.v:70986.5-70986.29" switch \initial - attribute \src "libresoc.v:68798.9-68798.17" + attribute \src "libresoc.v:70986.9-70986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\out_sel[1:0] \dec19_dec19_out_sel + assign $1\out_sel[2:0] \dec19_dec19_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } - assign $1\out_sel[1:0] \dec30_dec30_out_sel + assign $1\out_sel[2:0] \dec30_dec30_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\out_sel[1:0] \dec31_dec31_out_sel + assign $1\out_sel[2:0] \dec31_dec31_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } - assign $1\out_sel[1:0] \dec58_dec58_out_sel + assign $1\out_sel[2:0] \dec58_dec58_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } - assign $1\out_sel[1:0] \dec62_dec62_out_sel + assign $1\out_sel[2:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\out_sel[2:0] \dec22_dec22_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } - assign $1\out_sel[1:0] 2'11 + assign $1\out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 case - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } - assign $2\out_sel[1:0] 2'00 + assign $2\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } - assign $2\out_sel[1:0] 2'00 + assign $2\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } - assign $2\out_sel[1:0] 2'01 + assign $2\out_sel[2:0] 3'001 case - assign $2\out_sel[1:0] $1\out_sel[1:0] + assign $2\out_sel[2:0] $1\out_sel[2:0] end sync always - update \out_sel $0\out_sel[1:0] + update \out_sel $0\out_sel[2:0] end - attribute \src "libresoc.v:68939.3-69080.6" - process $proc$libresoc.v:68939$3558 + attribute \src "libresoc.v:71130.3-71274.6" + process $proc$libresoc.v:71130$3562 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:68940.5-68940.29" + attribute \src "libresoc.v:71131.5-71131.29" switch \initial - attribute \src "libresoc.v:68940.9-68940.17" + attribute \src "libresoc.v:71131.9-71131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -112088,6 +114548,10 @@ module \dec$205 assign { } { } assign $1\cr_in[2:0] \dec62_dec62_cr_in attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cr_in[2:0] \dec22_dec22_cr_in + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cr_in[2:0] 3'000 @@ -112234,7 +114698,7 @@ module \dec$205 case assign $1\cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -112254,19 +114718,19 @@ module \dec$205 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:69081.3-69222.6" - process $proc$libresoc.v:69081$3559 + attribute \src "libresoc.v:71275.3-71419.6" + process $proc$libresoc.v:71275$3563 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:69082.5-69082.29" + attribute \src "libresoc.v:71276.5-71276.29" switch \initial - attribute \src "libresoc.v:69082.9-69082.17" + attribute \src "libresoc.v:71276.9-71276.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -112289,6 +114753,10 @@ module \dec$205 assign { } { } assign $1\cr_out[2:0] \dec62_dec62_cr_out attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cr_out[2:0] \dec22_dec22_cr_out + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cr_out[2:0] 3'000 @@ -112435,7 +114903,7 @@ module \dec$205 case assign $1\cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -112455,421 +114923,1659 @@ module \dec$205 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:69223.3-69364.6" - process $proc$libresoc.v:69223$3560 + attribute \src "libresoc.v:71420.3-71564.6" + process $proc$libresoc.v:71420$3564 assign { } { } assign { } { } assign { } { } - assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:69224.5-69224.29" + assign $0\sv_in1[2:0] $2\sv_in1[2:0] + attribute \src "libresoc.v:71421.5-71421.29" switch \initial - attribute \src "libresoc.v:69224.9-69224.17" + attribute \src "libresoc.v:71421.9-71421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + assign $1\sv_in1[2:0] \dec19_dec19_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } - assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + assign $1\sv_in1[2:0] \dec30_dec30_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + assign $1\sv_in1[2:0] \dec31_dec31_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } - assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + assign $1\sv_in1[2:0] \dec58_dec58_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } - assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + assign $1\sv_in1[2:0] \dec62_dec62_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in1[2:0] \dec22_dec22_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } - assign $1\ldst_len[3:0] 4'0001 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } - assign $1\ldst_len[3:0] 4'0001 + assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } - assign $1\ldst_len[3:0] 4'0100 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } - assign $1\ldst_len[3:0] 4'0100 + assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\ldst_len[3:0] 4'0001 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\ldst_len[3:0] 4'0001 + assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\ldst_len[3:0] 4'0100 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\ldst_len[3:0] 4'0100 + assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'010 case - assign $1\ldst_len[3:0] 4'0000 + assign $1\sv_in1[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } - assign $2\ldst_len[3:0] 4'0000 + assign $2\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } - assign $2\ldst_len[3:0] 4'0000 + assign $2\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } - assign $2\ldst_len[3:0] 4'0000 + assign $2\sv_in1[2:0] 3'000 case - assign $2\ldst_len[3:0] $1\ldst_len[3:0] + assign $2\sv_in1[2:0] $1\sv_in1[2:0] end sync always - update \ldst_len $0\ldst_len[3:0] + update \sv_in1 $0\sv_in1[2:0] end - attribute \src "libresoc.v:69365.3-69506.6" - process $proc$libresoc.v:69365$3561 + attribute \src "libresoc.v:71565.3-71709.6" + process $proc$libresoc.v:71565$3565 assign { } { } assign { } { } assign { } { } - assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:69366.5-69366.29" + assign $0\sv_in2[2:0] $2\sv_in2[2:0] + attribute \src "libresoc.v:71566.5-71566.29" switch \initial - attribute \src "libresoc.v:69366.9-69366.17" + attribute \src "libresoc.v:71566.9-71566.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\upd[1:0] \dec19_dec19_upd + assign $1\sv_in2[2:0] \dec19_dec19_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } - assign $1\upd[1:0] \dec30_dec30_upd + assign $1\sv_in2[2:0] \dec30_dec30_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\upd[1:0] \dec31_dec31_upd + assign $1\sv_in2[2:0] \dec31_dec31_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } - assign $1\upd[1:0] \dec58_dec58_upd + assign $1\sv_in2[2:0] \dec58_dec58_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } - assign $1\upd[1:0] \dec62_dec62_upd + assign $1\sv_in2[2:0] \dec62_dec62_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in2[2:0] \dec22_dec22_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 case - assign $1\upd[1:0] 2'00 + assign $1\sv_in2[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } - assign $2\upd[1:0] 2'00 + assign $2\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } - assign $2\upd[1:0] 2'00 + assign $2\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } - assign $2\upd[1:0] 2'00 + assign $2\sv_in2[2:0] 3'000 + case + assign $2\sv_in2[2:0] $1\sv_in2[2:0] + end + sync always + update \sv_in2 $0\sv_in2[2:0] + end + attribute \src "libresoc.v:71710.3-71854.6" + process $proc$libresoc.v:71710$3566 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_in3[2:0] $2\sv_in3[2:0] + attribute \src "libresoc.v:71711.5-71711.29" + switch \initial + attribute \src "libresoc.v:71711.9-71711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_in3[2:0] \dec19_dec19_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_in3[2:0] \dec30_dec30_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_in3[2:0] \dec31_dec31_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_in3[2:0] \dec58_dec58_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_in3[2:0] \dec62_dec62_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in3[2:0] \dec22_dec22_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + case + assign $1\sv_in3[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_in3[2:0] 3'000 + case + assign $2\sv_in3[2:0] $1\sv_in3[2:0] + end + sync always + update \sv_in3 $0\sv_in3[2:0] + end + attribute \src "libresoc.v:71855.3-71999.6" + process $proc$libresoc.v:71855$3567 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_out[2:0] $2\sv_out[2:0] + attribute \src "libresoc.v:71856.5-71856.29" + switch \initial + attribute \src "libresoc.v:71856.9-71856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_out[2:0] \dec19_dec19_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_out[2:0] \dec30_dec30_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_out[2:0] \dec31_dec31_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_out[2:0] \dec58_dec58_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_out[2:0] \dec62_dec62_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_out[2:0] \dec22_dec22_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + case + assign $1\sv_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_out[2:0] 3'000 + case + assign $2\sv_out[2:0] $1\sv_out[2:0] + end + sync always + update \sv_out $0\sv_out[2:0] + end + attribute \src "libresoc.v:72000.3-72144.6" + process $proc$libresoc.v:72000$3568 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] + attribute \src "libresoc.v:72001.5-72001.29" + switch \initial + attribute \src "libresoc.v:72001.9-72001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_cr_in[2:0] \dec19_dec19_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec30_dec30_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_cr_in[2:0] \dec31_dec31_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_cr_in[2:0] \dec58_dec58_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec62_dec62_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec22_dec22_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + case + assign $1\sv_cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + case + assign $2\sv_cr_in[2:0] $1\sv_cr_in[2:0] + end + sync always + update \sv_cr_in $0\sv_cr_in[2:0] + end + attribute \src "libresoc.v:72145.3-72289.6" + process $proc$libresoc.v:72145$3569 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] + attribute \src "libresoc.v:72146.5-72146.29" + switch \initial + attribute \src "libresoc.v:72146.9-72146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_cr_out[2:0] \dec19_dec19_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec30_dec30_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_cr_out[2:0] \dec31_dec31_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_cr_out[2:0] \dec58_dec58_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec62_dec62_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec22_dec22_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + case + assign $1\sv_cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + case + assign $2\sv_cr_out[2:0] $1\sv_cr_out[2:0] + end + sync always + update \sv_cr_out $0\sv_cr_out[2:0] + end + attribute \src "libresoc.v:72290.3-72434.6" + process $proc$libresoc.v:72290$3570 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:72291.5-72291.29" + switch \initial + attribute \src "libresoc.v:72291.9-72291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\ldst_len[3:0] \dec22_dec22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + case + assign $2\ldst_len[3:0] $1\ldst_len[3:0] + end + sync always + update \ldst_len $0\ldst_len[3:0] + end + attribute \src "libresoc.v:72435.3-72579.6" + process $proc$libresoc.v:72435$3571 + assign { } { } + assign { } { } + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:72436.5-72436.29" + switch \initial + attribute \src "libresoc.v:72436.9-72436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\upd[1:0] \dec22_dec22_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 case assign $2\upd[1:0] $1\upd[1:0] end sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:69507.3-69648.6" - process $proc$libresoc.v:69507$3562 + attribute \src "libresoc.v:72580.3-72724.6" + process $proc$libresoc.v:72580$3572 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:69508.5-69508.29" + attribute \src "libresoc.v:72581.5-72581.29" switch \initial - attribute \src "libresoc.v:69508.9-69508.17" + attribute \src "libresoc.v:72581.9-72581.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -112892,6 +116598,10 @@ module \dec$205 assign { } { } assign $1\rc_sel[1:0] \dec62_dec62_rc_sel attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\rc_sel[1:0] \dec22_dec22_rc_sel + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\rc_sel[1:0] 2'00 @@ -113038,7 +116748,7 @@ module \dec$205 case assign $1\rc_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113058,19 +116768,19 @@ module \dec$205 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:69649.3-69790.6" - process $proc$libresoc.v:69649$3563 + attribute \src "libresoc.v:72725.3-72869.6" + process $proc$libresoc.v:72725$3573 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:69650.5-69650.29" + attribute \src "libresoc.v:72726.5-72726.29" switch \initial - attribute \src "libresoc.v:69650.9-69650.17" + attribute \src "libresoc.v:72726.9-72726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113093,6 +116803,10 @@ module \dec$205 assign { } { } assign $1\cry_in[1:0] \dec62_dec62_cry_in attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cry_in[1:0] \dec22_dec22_cry_in + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cry_in[1:0] 2'00 @@ -113239,7 +116953,7 @@ module \dec$205 case assign $1\cry_in[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113259,19 +116973,19 @@ module \dec$205 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:69791.3-69932.6" - process $proc$libresoc.v:69791$3564 + attribute \src "libresoc.v:72870.3-73014.6" + process $proc$libresoc.v:72870$3574 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:69792.5-69792.29" + attribute \src "libresoc.v:72871.5-72871.29" switch \initial - attribute \src "libresoc.v:69792.9-69792.17" + attribute \src "libresoc.v:72871.9-72871.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113294,6 +117008,10 @@ module \dec$205 assign { } { } assign $1\inv_a[0:0] \dec62_dec62_inv_a attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\inv_a[0:0] \dec22_dec22_inv_a + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\inv_a[0:0] 1'0 @@ -113440,7 +117158,7 @@ module \dec$205 case assign $1\inv_a[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113460,19 +117178,19 @@ module \dec$205 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:69933.3-70074.6" - process $proc$libresoc.v:69933$3565 + attribute \src "libresoc.v:73015.3-73159.6" + process $proc$libresoc.v:73015$3575 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:69934.5-69934.29" + attribute \src "libresoc.v:73016.5-73016.29" switch \initial - attribute \src "libresoc.v:69934.9-69934.17" + attribute \src "libresoc.v:73016.9-73016.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113495,6 +117213,10 @@ module \dec$205 assign { } { } assign $1\inv_out[0:0] \dec62_dec62_inv_out attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\inv_out[0:0] \dec22_dec22_inv_out + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\inv_out[0:0] 1'0 @@ -113641,7 +117363,7 @@ module \dec$205 case assign $1\inv_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113661,19 +117383,19 @@ module \dec$205 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:70075.3-70216.6" - process $proc$libresoc.v:70075$3566 + attribute \src "libresoc.v:73160.3-73304.6" + process $proc$libresoc.v:73160$3576 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:70076.5-70076.29" + attribute \src "libresoc.v:73161.5-73161.29" switch \initial - attribute \src "libresoc.v:70076.9-70076.17" + attribute \src "libresoc.v:73161.9-73161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113696,6 +117418,10 @@ module \dec$205 assign { } { } assign $1\cry_out[0:0] \dec62_dec62_cry_out attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cry_out[0:0] \dec22_dec22_cry_out + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cry_out[0:0] 1'1 @@ -113842,7 +117568,7 @@ module \dec$205 case assign $1\cry_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113862,19 +117588,19 @@ module \dec$205 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:70217.3-70358.6" - process $proc$libresoc.v:70217$3567 + attribute \src "libresoc.v:73305.3-73449.6" + process $proc$libresoc.v:73305$3577 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:70218.5-70218.29" + attribute \src "libresoc.v:73306.5-73306.29" switch \initial - attribute \src "libresoc.v:70218.9-70218.17" + attribute \src "libresoc.v:73306.9-73306.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113897,6 +117623,10 @@ module \dec$205 assign { } { } assign $1\br[0:0] \dec62_dec62_br attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\br[0:0] \dec22_dec22_br + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\br[0:0] 1'0 @@ -114043,7 +117773,7 @@ module \dec$205 case assign $1\br[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114063,19 +117793,19 @@ module \dec$205 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:70359.3-70500.6" - process $proc$libresoc.v:70359$3568 + attribute \src "libresoc.v:73450.3-73594.6" + process $proc$libresoc.v:73450$3578 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:70360.5-70360.29" + attribute \src "libresoc.v:73451.5-73451.29" switch \initial - attribute \src "libresoc.v:70360.9-70360.17" + attribute \src "libresoc.v:73451.9-73451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114098,6 +117828,10 @@ module \dec$205 assign { } { } assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgn_ext[0:0] \dec22_dec22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgn_ext[0:0] 1'0 @@ -114244,7 +117978,7 @@ module \dec$205 case assign $1\sgn_ext[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114264,19 +117998,19 @@ module \dec$205 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:70501.3-70642.6" - process $proc$libresoc.v:70501$3569 + attribute \src "libresoc.v:73595.3-73739.6" + process $proc$libresoc.v:73595$3579 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:70502.5-70502.29" + attribute \src "libresoc.v:73596.5-73596.29" switch \initial - attribute \src "libresoc.v:70502.9-70502.17" + attribute \src "libresoc.v:73596.9-73596.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114299,6 +118033,10 @@ module \dec$205 assign { } { } assign $1\rsrv[0:0] \dec62_dec62_rsrv attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\rsrv[0:0] \dec22_dec22_rsrv + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\rsrv[0:0] 1'0 @@ -114445,7 +118183,7 @@ module \dec$205 case assign $1\rsrv[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114465,19 +118203,19 @@ module \dec$205 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:70643.3-70784.6" - process $proc$libresoc.v:70643$3570 + attribute \src "libresoc.v:73740.3-73884.6" + process $proc$libresoc.v:73740$3580 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:70644.5-70644.29" + attribute \src "libresoc.v:73741.5-73741.29" switch \initial - attribute \src "libresoc.v:70644.9-70644.17" + attribute \src "libresoc.v:73741.9-73741.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114500,6 +118238,10 @@ module \dec$205 assign { } { } assign $1\is_32b[0:0] \dec62_dec62_is_32b attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\is_32b[0:0] \dec22_dec22_is_32b + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\is_32b[0:0] 1'0 @@ -114646,7 +118388,7 @@ module \dec$205 case assign $1\is_32b[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114666,19 +118408,19 @@ module \dec$205 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:70785.3-70926.6" - process $proc$libresoc.v:70785$3571 + attribute \src "libresoc.v:73885.3-74029.6" + process $proc$libresoc.v:73885$3581 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:70786.5-70786.29" + attribute \src "libresoc.v:73886.5-73886.29" switch \initial - attribute \src "libresoc.v:70786.9-70786.17" + attribute \src "libresoc.v:73886.9-73886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114701,6 +118443,10 @@ module \dec$205 assign { } { } assign $1\sgn[0:0] \dec62_dec62_sgn attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgn[0:0] \dec22_dec22_sgn + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgn[0:0] 1'0 @@ -114847,7 +118593,7 @@ module \dec$205 case assign $1\sgn[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114867,19 +118613,19 @@ module \dec$205 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:70927.3-71068.6" - process $proc$libresoc.v:70927$3572 + attribute \src "libresoc.v:74030.3-74174.6" + process $proc$libresoc.v:74030$3582 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:70928.5-70928.29" + attribute \src "libresoc.v:74031.5-74031.29" switch \initial - attribute \src "libresoc.v:70928.9-70928.17" + attribute \src "libresoc.v:74031.9-74031.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114902,6 +118648,10 @@ module \dec$205 assign { } { } assign $1\lk[0:0] \dec62_dec62_lk attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\lk[0:0] \dec22_dec22_lk + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\lk[0:0] 1'0 @@ -115048,7 +118798,7 @@ module \dec$205 case assign $1\lk[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115068,19 +118818,19 @@ module \dec$205 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:71069.3-71210.6" - process $proc$libresoc.v:71069$3573 + attribute \src "libresoc.v:74175.3-74319.6" + process $proc$libresoc.v:74175$3583 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:71070.5-71070.29" + attribute \src "libresoc.v:74176.5-74176.29" switch \initial - attribute \src "libresoc.v:71070.9-71070.17" + attribute \src "libresoc.v:74176.9-74176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115103,6 +118853,10 @@ module \dec$205 assign { } { } assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec22_dec22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgl_pipe[0:0] 1'0 @@ -115249,7 +119003,7 @@ module \dec$205 case assign $1\sgl_pipe[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115269,220 +119023,224 @@ module \dec$205 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:71211.3-71352.6" - process $proc$libresoc.v:71211$3574 + attribute \src "libresoc.v:74320.3-74464.6" + process $proc$libresoc.v:74320$3584 assign { } { } assign { } { } assign { } { } - assign $0\function_unit[11:0] $2\function_unit[11:0] - attribute \src "libresoc.v:71212.5-71212.29" + assign $0\function_unit[13:0] $2\function_unit[13:0] + attribute \src "libresoc.v:74321.5-74321.29" switch \initial - attribute \src "libresoc.v:71212.9-71212.17" + attribute \src "libresoc.v:74321.9-74321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\function_unit[11:0] \dec19_dec19_function_unit + assign $1\function_unit[13:0] \dec19_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } - assign $1\function_unit[11:0] \dec30_dec30_function_unit + assign $1\function_unit[13:0] \dec30_dec30_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\function_unit[11:0] \dec31_dec31_function_unit + assign $1\function_unit[13:0] \dec31_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } - assign $1\function_unit[11:0] \dec58_dec58_function_unit + assign $1\function_unit[13:0] \dec58_dec58_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } - assign $1\function_unit[11:0] \dec62_dec62_function_unit + assign $1\function_unit[13:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\function_unit[13:0] \dec22_dec22_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } - assign $1\function_unit[11:0] 12'000010000000 + assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } - assign $1\function_unit[11:0] 12'000000100000 + assign $1\function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } - assign $1\function_unit[11:0] 12'000000100000 + assign $1\function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } - assign $1\function_unit[11:0] 12'000100000000 + assign $1\function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\function_unit[11:0] 12'000000001000 + assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\function_unit[11:0] 12'000000001000 + assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\function_unit[11:0] 12'000000001000 + assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } - assign $1\function_unit[11:0] 12'000010000000 + assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } - assign $1\function_unit[11:0] 12'000010000000 + assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\function_unit[13:0] 14'00000000010000 case - assign $1\function_unit[11:0] 12'000000000000 + assign $1\function_unit[13:0] 14'00000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } - assign $2\function_unit[11:0] 12'000000000000 + assign $2\function_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } - assign $2\function_unit[11:0] 12'000000000000 + assign $2\function_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } - assign $2\function_unit[11:0] 12'000000000000 + assign $2\function_unit[13:0] 14'00000000000000 case - assign $2\function_unit[11:0] $1\function_unit[11:0] + assign $2\function_unit[13:0] $1\function_unit[13:0] end sync always - update \function_unit $0\function_unit[11:0] + update \function_unit $0\function_unit[13:0] end - attribute \src "libresoc.v:71353.3-71494.6" - process $proc$libresoc.v:71353$3575 + attribute \src "libresoc.v:74465.3-74609.6" + process $proc$libresoc.v:74465$3585 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:71354.5-71354.29" + attribute \src "libresoc.v:74466.5-74466.29" switch \initial - attribute \src "libresoc.v:71354.9-71354.17" + attribute \src "libresoc.v:74466.9-74466.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115505,6 +119263,10 @@ module \dec$205 assign { } { } assign $1\internal_op[6:0] \dec62_dec62_internal_op attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\internal_op[6:0] \dec22_dec22_internal_op + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\internal_op[6:0] 7'0000010 @@ -115651,7 +119413,7 @@ module \dec$205 case assign $1\internal_op[6:0] 7'0000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115671,208 +119433,7 @@ module \dec$205 sync always update \internal_op $0\internal_op[6:0] end - attribute \src "libresoc.v:71495.3-71636.6" - process $proc$libresoc.v:71495$3576 - assign { } { } - assign { } { } - assign { } { } - assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:71496.5-71496.29" - switch \initial - attribute \src "libresoc.v:71496.9-71496.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\form[4:0] \dec19_dec19_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\form[4:0] \dec30_dec30_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\form[4:0] \dec31_dec31_form - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\form[4:0] \dec58_dec58_form - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\form[4:0] \dec62_dec62_form - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\form[4:0] 5'00011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\form[4:0] 5'00001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\form[4:0] 5'00100 - case - assign $1\form[4:0] 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\form[4:0] 5'00000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\form[4:0] 5'00000 - case - assign $2\form[4:0] $1\form[4:0] - end - sync always - update \form $0\form[4:0] - end - connect \$2 $ternary$libresoc.v:68096$3552_Y + connect \$2 $ternary$libresoc.v:69762$3553_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -115900,14 +119461,20 @@ module \dec$205 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] @@ -116199,8 +119766,10 @@ module \dec$205 connect \RA \opcode_in [20:16] connect \RT \opcode_in [25:21] connect \RS \opcode_in [25:21] + connect \PO \opcode_in [31:26] connect \opcode_in \$2 connect \opcode_switch$1 \opcode_in + connect \dec22_opcode_in \opcode_in connect \dec62_opcode_in \opcode_in connect \dec58_opcode_in \opcode_in connect \dec31_opcode_in \opcode_in @@ -116208,113 +119777,157 @@ module \dec$205 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:71975.1-73482.10" +attribute \src "libresoc.v:74956.1-76960.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:72493.3-72544.6" + attribute \src "libresoc.v:76647.3-76698.6" + wire width 2 $0\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:76699.3-76750.6" + wire width 2 $0\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:76023.3-76074.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:72701.3-72752.6" + attribute \src "libresoc.v:76231.3-76282.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:73377.3-73428.6" + attribute \src "libresoc.v:75347.3-75398.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:73429.3-73480.6" + attribute \src "libresoc.v:75399.3-75450.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:72441.3-72492.6" + attribute \src "libresoc.v:75971.3-76022.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:72649.3-72700.6" + attribute \src "libresoc.v:76179.3-76230.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:73117.3-73168.6" + attribute \src "libresoc.v:76439.3-76490.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:72233.3-72284.6" - wire width 12 $0\dec19_function_unit[11:0] - attribute \src "libresoc.v:73169.3-73220.6" + attribute \src "libresoc.v:75295.3-75346.6" + wire width 14 $0\dec19_function_unit[13:0] + attribute \src "libresoc.v:76751.3-76802.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:73221.3-73272.6" + attribute \src "libresoc.v:76803.3-76854.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:73273.3-73324.6" + attribute \src "libresoc.v:76855.3-76906.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:72805.3-72856.6" + attribute \src "libresoc.v:75867.3-75918.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:72545.3-72596.6" + attribute \src "libresoc.v:76075.3-76126.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:72597.3-72648.6" + attribute \src "libresoc.v:76127.3-76178.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:72909.3-72960.6" + attribute \src "libresoc.v:76387.3-76438.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:72285.3-72336.6" + attribute \src "libresoc.v:75763.3-75814.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:73013.3-73064.6" + attribute \src "libresoc.v:76543.3-76594.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:73325.3-73376.6" - wire width 2 $0\dec19_out_sel[1:0] - attribute \src "libresoc.v:72389.3-72440.6" + attribute \src "libresoc.v:76907.3-76958.6" + wire width 3 $0\dec19_out_sel[2:0] + attribute \src "libresoc.v:75919.3-75970.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:72857.3-72908.6" + attribute \src "libresoc.v:76335.3-76386.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:73065.3-73116.6" + attribute \src "libresoc.v:76595.3-76646.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:72961.3-73012.6" + attribute \src "libresoc.v:76491.3-76542.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:72753.3-72804.6" + attribute \src "libresoc.v:76283.3-76334.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:72337.3-72388.6" + attribute \src "libresoc.v:75659.3-75710.6" + wire width 3 $0\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:75711.3-75762.6" + wire width 3 $0\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:75451.3-75502.6" + wire width 3 $0\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75503.3-75554.6" + wire width 3 $0\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75555.3-75606.6" + wire width 3 $0\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75607.3-75658.6" + wire width 3 $0\dec19_sv_out[2:0] + attribute \src "libresoc.v:75815.3-75866.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:71976.7-71976.20" + attribute \src "libresoc.v:74957.7-74957.20" wire $0\initial[0:0] - attribute \src "libresoc.v:72493.3-72544.6" + attribute \src "libresoc.v:76647.3-76698.6" + wire width 2 $1\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:76699.3-76750.6" + wire width 2 $1\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:76023.3-76074.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:72701.3-72752.6" + attribute \src "libresoc.v:76231.3-76282.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:73377.3-73428.6" + attribute \src "libresoc.v:75347.3-75398.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:73429.3-73480.6" + attribute \src "libresoc.v:75399.3-75450.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:72441.3-72492.6" + attribute \src "libresoc.v:75971.3-76022.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:72649.3-72700.6" + attribute \src "libresoc.v:76179.3-76230.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:73117.3-73168.6" + attribute \src "libresoc.v:76439.3-76490.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:72233.3-72284.6" - wire width 12 $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:73169.3-73220.6" + attribute \src "libresoc.v:75295.3-75346.6" + wire width 14 $1\dec19_function_unit[13:0] + attribute \src "libresoc.v:76751.3-76802.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:73221.3-73272.6" + attribute \src "libresoc.v:76803.3-76854.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:73273.3-73324.6" + attribute \src "libresoc.v:76855.3-76906.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:72805.3-72856.6" + attribute \src "libresoc.v:75867.3-75918.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:72545.3-72596.6" + attribute \src "libresoc.v:76075.3-76126.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:72597.3-72648.6" + attribute \src "libresoc.v:76127.3-76178.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:72909.3-72960.6" + attribute \src "libresoc.v:76387.3-76438.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:72285.3-72336.6" + attribute \src "libresoc.v:75763.3-75814.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:73013.3-73064.6" + attribute \src "libresoc.v:76543.3-76594.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:73325.3-73376.6" - wire width 2 $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:72389.3-72440.6" + attribute \src "libresoc.v:76907.3-76958.6" + wire width 3 $1\dec19_out_sel[2:0] + attribute \src "libresoc.v:75919.3-75970.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:72857.3-72908.6" + attribute \src "libresoc.v:76335.3-76386.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:73065.3-73116.6" + attribute \src "libresoc.v:76595.3-76646.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:72961.3-73012.6" + attribute \src "libresoc.v:76491.3-76542.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:72753.3-72804.6" + attribute \src "libresoc.v:76283.3-76334.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:72337.3-72388.6" + attribute \src "libresoc.v:75659.3-75710.6" + wire width 3 $1\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:75711.3-75762.6" + wire width 3 $1\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:75451.3-75502.6" + wire width 3 $1\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75503.3-75554.6" + wire width 3 $1\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75555.3-75606.6" + wire width 3 $1\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75607.3-75658.6" + wire width 3 $1\dec19_sv_out[2:0] + attribute \src "libresoc.v:75815.3-75866.6" wire width 2 $1\dec19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 output 4 \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -116323,24 +119936,26 @@ module \dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec19_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec19_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -116371,31 +119986,34 @@ module \dec19 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec19_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec19_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -116411,14 +120029,14 @@ module \dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec19_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec19_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -116493,947 +120111,1003 @@ module \dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec19_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec19_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec19_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec19_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec19_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec19_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec19_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec19_upd - attribute \src "libresoc.v:71976.7-71976.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec19_upd + attribute \src "libresoc.v:74957.7-74957.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:71976.7-71976.20" - process $proc$libresoc.v:71976$3602 + attribute \src "libresoc.v:74957.7-74957.20" + process $proc$libresoc.v:74957$3619 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:72233.3-72284.6" - process $proc$libresoc.v:72233$3578 + attribute \src "libresoc.v:75295.3-75346.6" + process $proc$libresoc.v:75295$3587 assign { } { } assign { } { } - assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:72234.5-72234.29" + assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] + attribute \src "libresoc.v:75296.5-75296.29" switch \initial - attribute \src "libresoc.v:72234.9-72234.17" + attribute \src "libresoc.v:75296.9-75296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 + assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 + assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 + assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000000010 + assign $1\dec19_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 + assign $1\dec19_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 + assign $1\dec19_function_unit[13:0] 14'00000010000000 case - assign $1\dec19_function_unit[11:0] 12'000000000000 + assign $1\dec19_function_unit[13:0] 14'00000000000000 end sync always - update \dec19_function_unit $0\dec19_function_unit[11:0] + update \dec19_function_unit $0\dec19_function_unit[13:0] end - attribute \src "libresoc.v:72285.3-72336.6" - process $proc$libresoc.v:72285$3579 + attribute \src "libresoc.v:75347.3-75398.6" + process $proc$libresoc.v:75347$3588 assign { } { } assign { } { } - assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:72286.5-72286.29" + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:75348.5-75348.29" switch \initial - attribute \src "libresoc.v:72286.9-72286.17" + attribute \src "libresoc.v:75348.9-75348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'000 case - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec19_cr_in[2:0] 3'000 end sync always - update \dec19_ldst_len $0\dec19_ldst_len[3:0] + update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:72337.3-72388.6" - process $proc$libresoc.v:72337$3580 + attribute \src "libresoc.v:75399.3-75450.6" + process $proc$libresoc.v:75399$3589 assign { } { } assign { } { } - assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:72338.5-72338.29" + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:75400.5-75400.29" switch \initial - attribute \src "libresoc.v:72338.9-72338.17" + attribute \src "libresoc.v:75400.9-75400.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 case - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 end sync always - update \dec19_upd $0\dec19_upd[1:0] + update \dec19_cr_out $0\dec19_cr_out[2:0] end - attribute \src "libresoc.v:72389.3-72440.6" - process $proc$libresoc.v:72389$3581 + attribute \src "libresoc.v:75451.3-75502.6" + process $proc$libresoc.v:75451$3590 assign { } { } assign { } { } - assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:72390.5-72390.29" + assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75452.5-75452.29" switch \initial - attribute \src "libresoc.v:72390.9-72390.17" + attribute \src "libresoc.v:75452.9-75452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 case - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec19_sv_in1[2:0] 3'000 end sync always - update \dec19_rc_sel $0\dec19_rc_sel[1:0] + update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end - attribute \src "libresoc.v:72441.3-72492.6" - process $proc$libresoc.v:72441$3582 + attribute \src "libresoc.v:75503.3-75554.6" + process $proc$libresoc.v:75503$3591 assign { } { } assign { } { } - assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:72442.5-72442.29" + assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75504.5-75504.29" switch \initial - attribute \src "libresoc.v:72442.9-72442.17" + attribute \src "libresoc.v:75504.9-75504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 case - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec19_sv_in2[2:0] 3'000 end sync always - update \dec19_cry_in $0\dec19_cry_in[1:0] + update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end - attribute \src "libresoc.v:72493.3-72544.6" - process $proc$libresoc.v:72493$3583 + attribute \src "libresoc.v:75555.3-75606.6" + process $proc$libresoc.v:75555$3592 assign { } { } assign { } { } - assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:72494.5-72494.29" + assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75556.5-75556.29" switch \initial - attribute \src "libresoc.v:72494.9-72494.17" + attribute \src "libresoc.v:75556.9-75556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_asmcode[7:0] 8'01101100 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100101 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100110 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100111 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101000 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101001 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101010 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101011 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101100 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010110 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010111 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00011000 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001100 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_asmcode[7:0] 8'10010001 + assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001000 + assign $1\dec19_sv_in3[2:0] 3'000 case - assign $1\dec19_asmcode[7:0] 8'00000000 + assign $1\dec19_sv_in3[2:0] 3'000 end sync always - update \dec19_asmcode $0\dec19_asmcode[7:0] + update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end - attribute \src "libresoc.v:72545.3-72596.6" - process $proc$libresoc.v:72545$3584 + attribute \src "libresoc.v:75607.3-75658.6" + process $proc$libresoc.v:75607$3593 assign { } { } assign { } { } - assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:72546.5-72546.29" + assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] + attribute \src "libresoc.v:75608.5-75608.29" switch \initial - attribute \src "libresoc.v:72546.9-72546.17" + attribute \src "libresoc.v:75608.9-75608.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 case - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec19_sv_out[2:0] 3'000 end sync always - update \dec19_inv_a $0\dec19_inv_a[0:0] + update \dec19_sv_out $0\dec19_sv_out[2:0] end - attribute \src "libresoc.v:72597.3-72648.6" - process $proc$libresoc.v:72597$3585 + attribute \src "libresoc.v:75659.3-75710.6" + process $proc$libresoc.v:75659$3594 assign { } { } assign { } { } - assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:72598.5-72598.29" + assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:75660.5-75660.29" switch \initial - attribute \src "libresoc.v:72598.9-72598.17" + attribute \src "libresoc.v:75660.9-75660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'000 case - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec19_sv_cr_in[2:0] 3'000 end sync always - update \dec19_inv_out $0\dec19_inv_out[0:0] + update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end - attribute \src "libresoc.v:72649.3-72700.6" - process $proc$libresoc.v:72649$3586 + attribute \src "libresoc.v:75711.3-75762.6" + process $proc$libresoc.v:75711$3595 assign { } { } assign { } { } - assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:72650.5-72650.29" + assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:75712.5-75712.29" switch \initial - attribute \src "libresoc.v:72650.9-72650.17" + attribute \src "libresoc.v:75712.9-75712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'000 case - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec19_sv_cr_out[2:0] 3'000 end sync always - update \dec19_cry_out $0\dec19_cry_out[0:0] + update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end - attribute \src "libresoc.v:72701.3-72752.6" - process $proc$libresoc.v:72701$3587 + attribute \src "libresoc.v:75763.3-75814.6" + process $proc$libresoc.v:75763$3596 assign { } { } assign { } { } - assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:72702.5-72702.29" + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:75764.5-75764.29" switch \initial - attribute \src "libresoc.v:72702.9-72702.17" + attribute \src "libresoc.v:75764.9-75764.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 case - assign $1\dec19_br[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 end sync always - update \dec19_br $0\dec19_br[0:0] + update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:72753.3-72804.6" - process $proc$libresoc.v:72753$3588 + attribute \src "libresoc.v:75815.3-75866.6" + process $proc$libresoc.v:75815$3597 assign { } { } assign { } { } - assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:72754.5-72754.29" + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:75816.5-75816.29" switch \initial - attribute \src "libresoc.v:72754.9-72754.17" + attribute \src "libresoc.v:75816.9-75816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 case - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec19_upd[1:0] 2'00 end sync always - update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:72805.3-72856.6" - process $proc$libresoc.v:72805$3589 + attribute \src "libresoc.v:75867.3-75918.6" + process $proc$libresoc.v:75867$3598 assign { } { } assign { } { } assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:72806.5-72806.29" + attribute \src "libresoc.v:75868.5-75868.29" switch \initial - attribute \src "libresoc.v:72806.9-72806.17" + attribute \src "libresoc.v:75868.9-75868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117501,18 +121175,650 @@ module \dec19 sync always update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:72857.3-72908.6" - process $proc$libresoc.v:72857$3590 + attribute \src "libresoc.v:75919.3-75970.6" + process $proc$libresoc.v:75919$3599 + assign { } { } + assign { } { } + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:75920.5-75920.29" + switch \initial + attribute \src "libresoc.v:75920.9-75920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end + sync always + update \dec19_rc_sel $0\dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:75971.3-76022.6" + process $proc$libresoc.v:75971$3600 + assign { } { } + assign { } { } + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:75972.5-75972.29" + switch \initial + attribute \src "libresoc.v:75972.9-75972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end + sync always + update \dec19_cry_in $0\dec19_cry_in[1:0] + end + attribute \src "libresoc.v:76023.3-76074.6" + process $proc$libresoc.v:76023$3601 + assign { } { } + assign { } { } + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:76024.5-76024.29" + switch \initial + attribute \src "libresoc.v:76024.9-76024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end + sync always + update \dec19_asmcode $0\dec19_asmcode[7:0] + end + attribute \src "libresoc.v:76075.3-76126.6" + process $proc$libresoc.v:76075$3602 + assign { } { } + assign { } { } + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:76076.5-76076.29" + switch \initial + attribute \src "libresoc.v:76076.9-76076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end + sync always + update \dec19_inv_a $0\dec19_inv_a[0:0] + end + attribute \src "libresoc.v:76127.3-76178.6" + process $proc$libresoc.v:76127$3603 + assign { } { } + assign { } { } + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:76128.5-76128.29" + switch \initial + attribute \src "libresoc.v:76128.9-76128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end + sync always + update \dec19_inv_out $0\dec19_inv_out[0:0] + end + attribute \src "libresoc.v:76179.3-76230.6" + process $proc$libresoc.v:76179$3604 + assign { } { } + assign { } { } + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:76180.5-76180.29" + switch \initial + attribute \src "libresoc.v:76180.9-76180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end + sync always + update \dec19_cry_out $0\dec19_cry_out[0:0] + end + attribute \src "libresoc.v:76231.3-76282.6" + process $proc$libresoc.v:76231$3605 + assign { } { } + assign { } { } + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:76232.5-76232.29" + switch \initial + attribute \src "libresoc.v:76232.9-76232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + case + assign $1\dec19_br[0:0] 1'0 + end + sync always + update \dec19_br $0\dec19_br[0:0] + end + attribute \src "libresoc.v:76283.3-76334.6" + process $proc$libresoc.v:76283$3606 + assign { } { } + assign { } { } + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:76284.5-76284.29" + switch \initial + attribute \src "libresoc.v:76284.9-76284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "libresoc.v:76335.3-76386.6" + process $proc$libresoc.v:76335$3607 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:72858.5-72858.29" + attribute \src "libresoc.v:76336.5-76336.29" switch \initial - attribute \src "libresoc.v:72858.9-72858.17" + attribute \src "libresoc.v:76336.9-76336.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117580,18 +121886,18 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:72909.3-72960.6" - process $proc$libresoc.v:72909$3591 + attribute \src "libresoc.v:76387.3-76438.6" + process $proc$libresoc.v:76387$3608 assign { } { } assign { } { } assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:72910.5-72910.29" + attribute \src "libresoc.v:76388.5-76388.29" switch \initial - attribute \src "libresoc.v:72910.9-72910.17" + attribute \src "libresoc.v:76388.9-76388.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117659,1503 +121965,1655 @@ module \dec19 sync always update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:72961.3-73012.6" - process $proc$libresoc.v:72961$3592 + attribute \src "libresoc.v:76439.3-76490.6" + process $proc$libresoc.v:76439$3609 assign { } { } assign { } { } - assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:72962.5-72962.29" + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:76440.5-76440.29" switch \initial - attribute \src "libresoc.v:72962.9-72962.17" + attribute \src "libresoc.v:76440.9-76440.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 case - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec19_form[4:0] 5'00000 end sync always - update \dec19_sgn $0\dec19_sgn[0:0] + update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:73013.3-73064.6" - process $proc$libresoc.v:73013$3593 + attribute \src "libresoc.v:76491.3-76542.6" + process $proc$libresoc.v:76491$3610 assign { } { } assign { } { } - assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:73014.5-73014.29" + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:76492.5-76492.29" switch \initial - attribute \src "libresoc.v:73014.9-73014.17" + attribute \src "libresoc.v:76492.9-76492.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_lk[0:0] 1'1 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_lk[0:0] 1'1 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_lk[0:0] 1'1 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 case - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 end sync always - update \dec19_lk $0\dec19_lk[0:0] + update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:73065.3-73116.6" - process $proc$libresoc.v:73065$3594 + attribute \src "libresoc.v:76543.3-76594.6" + process $proc$libresoc.v:76543$3611 assign { } { } assign { } { } - assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:73066.5-73066.29" + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:76544.5-76544.29" switch \initial - attribute \src "libresoc.v:73066.9-73066.17" + attribute \src "libresoc.v:76544.9-76544.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'1 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 case - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 end sync always - update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:73117.3-73168.6" - process $proc$libresoc.v:73117$3595 + attribute \src "libresoc.v:76595.3-76646.6" + process $proc$libresoc.v:76595$3612 assign { } { } assign { } { } - assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:73118.5-73118.29" + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:76596.5-76596.29" switch \initial - attribute \src "libresoc.v:73118.9-73118.17" + attribute \src "libresoc.v:76596.9-76596.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_sgl_pipe[0:0] 1'0 case - assign $1\dec19_form[4:0] 5'00000 + assign $1\dec19_sgl_pipe[0:0] 1'0 end sync always - update \dec19_form $0\dec19_form[4:0] + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:73169.3-73220.6" - process $proc$libresoc.v:73169$3596 + attribute \src "libresoc.v:76647.3-76698.6" + process $proc$libresoc.v:76647$3613 assign { } { } assign { } { } - assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:73170.5-73170.29" + assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:76648.5-76648.29" switch \initial - attribute \src "libresoc.v:73170.9-73170.17" + attribute \src "libresoc.v:76648.9-76648.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec19_SV_Etype[1:0] 2'00 case - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec19_SV_Etype[1:0] 2'00 end sync always - update \dec19_in1_sel $0\dec19_in1_sel[2:0] + update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end - attribute \src "libresoc.v:73221.3-73272.6" - process $proc$libresoc.v:73221$3597 + attribute \src "libresoc.v:76699.3-76750.6" + process $proc$libresoc.v:76699$3614 assign { } { } assign { } { } - assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:73222.5-73222.29" + assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:76700.5-76700.29" switch \initial - attribute \src "libresoc.v:73222.9-73222.17" + attribute \src "libresoc.v:76700.9-76700.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec19_SV_Ptype[1:0] 2'00 case - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec19_SV_Ptype[1:0] 2'00 end sync always - update \dec19_in2_sel $0\dec19_in2_sel[3:0] + update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end - attribute \src "libresoc.v:73273.3-73324.6" - process $proc$libresoc.v:73273$3598 + attribute \src "libresoc.v:76751.3-76802.6" + process $proc$libresoc.v:76751$3615 assign { } { } assign { } { } - assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:73274.5-73274.29" + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:76752.5-76752.29" switch \initial - attribute \src "libresoc.v:73274.9-73274.17" + attribute \src "libresoc.v:76752.9-76752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'011 case - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec19_in1_sel[2:0] 3'000 end sync always - update \dec19_in3_sel $0\dec19_in3_sel[1:0] + update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:73325.3-73376.6" - process $proc$libresoc.v:73325$3599 + attribute \src "libresoc.v:76803.3-76854.6" + process $proc$libresoc.v:76803$3616 assign { } { } assign { } { } - assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:73326.5-73326.29" + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:76804.5-76804.29" switch \initial - attribute \src "libresoc.v:73326.9-73326.17" + attribute \src "libresoc.v:76804.9-76804.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'1100 case - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_in2_sel[3:0] 4'0000 end sync always - update \dec19_out_sel $0\dec19_out_sel[1:0] + update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:73377.3-73428.6" - process $proc$libresoc.v:73377$3600 + attribute \src "libresoc.v:76855.3-76906.6" + process $proc$libresoc.v:76855$3617 assign { } { } assign { } { } - assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:73378.5-73378.29" + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:76856.5-76856.29" switch \initial - attribute \src "libresoc.v:73378.9-73378.17" + attribute \src "libresoc.v:76856.9-76856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_cr_in[2:0] 3'011 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 + assign $1\dec19_in3_sel[1:0] 2'00 case - assign $1\dec19_cr_in[2:0] 3'000 + assign $1\dec19_in3_sel[1:0] 2'00 end sync always - update \dec19_cr_in $0\dec19_cr_in[2:0] + update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:73429.3-73480.6" - process $proc$libresoc.v:73429$3601 + attribute \src "libresoc.v:76907.3-76958.6" + process $proc$libresoc.v:76907$3618 assign { } { } assign { } { } - assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:73430.5-73430.29" + assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] + attribute \src "libresoc.v:76908.5-76908.29" switch \initial - attribute \src "libresoc.v:73430.9-73430.17" + attribute \src "libresoc.v:76908.9-76908.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_cr_out[2:0] 3'010 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec19_out_sel[2:0] 3'000 case - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec19_out_sel[2:0] 3'000 end sync always - update \dec19_cr_out $0\dec19_cr_out[2:0] + update \dec19_out_sel $0\dec19_out_sel[2:0] end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:73486.1-75523.10" +attribute \src "libresoc.v:76964.1-79185.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $0\cr_in1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\cr_in1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $0\cr_in2$1[2:0]$3621 - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $0\cr_in2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\cr_in2_ok$2[0:0]$3622 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\cr_in2$1[6:0]$3680 + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\cr_in2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\cr_in2_ok$2[0:0]$3681 + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\cr_out[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $0\ea[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\ea[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\exc_$signal$3[0:0]$3624 - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\exc_$signal$4[0:0]$3625 - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\exc_$signal$5[0:0]$3626 - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\exc_$signal$6[0:0]$3627 - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\exc_$signal$7[0:0]$3628 - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\exc_$signal$8[0:0]$3629 - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\exc_$signal$9[0:0]$3630 - attribute \src "libresoc.v:75297.3-75454.6" - wire $0\exc_$signal[0:0]$3623 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\exc_$signal$3[0:0]$3683 + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\exc_$signal$4[0:0]$3684 + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\exc_$signal$5[0:0]$3685 + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\exc_$signal$6[0:0]$3686 + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\exc_$signal$7[0:0]$3687 + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\exc_$signal$8[0:0]$3688 + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\exc_$signal$9[0:0]$3689 + attribute \src "libresoc.v:78948.3-79105.6" + wire $0\exc_$signal[0:0]$3682 + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 12 $0\fn_unit[11:0] - attribute \src "libresoc.v:73487.7-73487.20" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $0\fn_unit[13:0] + attribute \src "libresoc.v:76965.7-76965.20" wire $0\initial[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:75277.3-75296.6" + attribute \src "libresoc.v:78924.3-78947.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\lk[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\oe[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\rc[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $0\reg1[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\reg1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $0\reg2[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\reg2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $0\reg3[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\reg3[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $0\rego[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $0\rego[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:75231.3-75240.6" + attribute \src "libresoc.v:78850.3-78864.6" + wire width 14 $0\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:78875.3-78887.6" + wire width 7 $0\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:78865.3-78874.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:75267.3-75276.6" + attribute \src "libresoc.v:78914.3-78923.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:75241.3-75256.6" + attribute \src "libresoc.v:78888.3-78903.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:75257.3-75266.6" + attribute \src "libresoc.v:78904.3-78913.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $1\cr_in1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\cr_in1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $1\cr_in2$1[2:0]$3631 - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $1\cr_in2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\cr_in2_ok$2[0:0]$3632 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\cr_in2$1[6:0]$3690 + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\cr_in2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\cr_in2_ok$2[0:0]$3691 + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\cr_out[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $1\ea[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\ea[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\exc_$signal$3[0:0]$3634 - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\exc_$signal$4[0:0]$3635 - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\exc_$signal$5[0:0]$3636 - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\exc_$signal$6[0:0]$3637 - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\exc_$signal$7[0:0]$3638 - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\exc_$signal$8[0:0]$3639 - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\exc_$signal$9[0:0]$3640 - attribute \src "libresoc.v:75297.3-75454.6" - wire $1\exc_$signal[0:0]$3633 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\exc_$signal$3[0:0]$3693 + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\exc_$signal$4[0:0]$3694 + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\exc_$signal$5[0:0]$3695 + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\exc_$signal$6[0:0]$3696 + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\exc_$signal$7[0:0]$3697 + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\exc_$signal$8[0:0]$3698 + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\exc_$signal$9[0:0]$3699 + attribute \src "libresoc.v:78948.3-79105.6" + wire $1\exc_$signal[0:0]$3692 + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 12 $1\fn_unit[11:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $1\fn_unit[13:0] + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:75277.3-75296.6" + attribute \src "libresoc.v:78924.3-78947.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\lk[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\oe[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\rc[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $1\reg1[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\reg1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $1\reg2[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\reg2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $1\reg3[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\reg3[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $1\rego[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $1\rego[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:75231.3-75240.6" + attribute \src "libresoc.v:78850.3-78864.6" + wire width 14 $1\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:78875.3-78887.6" + wire width 7 $1\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:78865.3-78874.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:75267.3-75276.6" + attribute \src "libresoc.v:78914.3-78923.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:75241.3-75256.6" + attribute \src "libresoc.v:78888.3-78903.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:75257.3-75266.6" + attribute \src "libresoc.v:78904.3-78913.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $2\cr_in1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\cr_in1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $2\cr_in2$1[2:0]$3641 - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $2\cr_in2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\cr_in2_ok$2[0:0]$3642 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\cr_in2$1[6:0]$3700 + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\cr_in2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\cr_in2_ok$2[0:0]$3701 + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\cr_out[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $2\ea[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\ea[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $2\ea_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\exc_$signal$3[0:0]$3644 - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\exc_$signal$4[0:0]$3645 - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\exc_$signal$5[0:0]$3646 - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\exc_$signal$6[0:0]$3647 - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\exc_$signal$7[0:0]$3648 - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\exc_$signal$8[0:0]$3649 - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\exc_$signal$9[0:0]$3650 - attribute \src "libresoc.v:75297.3-75454.6" - wire $2\exc_$signal[0:0]$3643 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\exc_$signal$3[0:0]$3703 + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\exc_$signal$4[0:0]$3704 + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\exc_$signal$5[0:0]$3705 + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\exc_$signal$6[0:0]$3706 + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\exc_$signal$7[0:0]$3707 + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\exc_$signal$8[0:0]$3708 + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\exc_$signal$9[0:0]$3709 + attribute \src "libresoc.v:78948.3-79105.6" + wire $2\exc_$signal[0:0]$3702 + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 12 $2\fn_unit[11:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $2\fn_unit[13:0] + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\is_32bit[0:0] - attribute \src "libresoc.v:75277.3-75296.6" + attribute \src "libresoc.v:78924.3-78947.6" wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\lk[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\oe[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\oe_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\rc[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\rc_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $2\reg1[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\reg1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $2\reg2[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\reg2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $2\reg3[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\reg3[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $2\rego[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $2\rego[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $2\rego_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\spro_ok[0:0] - attribute \src "libresoc.v:75241.3-75256.6" + attribute \src "libresoc.v:78888.3-78903.6" wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\xer_out[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $3\cr_in1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\cr_in1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $3\cr_in2$1[2:0]$3651 - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $3\cr_in2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\cr_in2_ok$2[0:0]$3652 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\cr_in2$1[6:0]$3710 + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\cr_in2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\cr_in2_ok$2[0:0]$3711 + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $3\cr_out[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\cr_out[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $3\ea[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\ea[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $3\ea_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\exc_$signal$3[0:0]$3654 - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\exc_$signal$4[0:0]$3655 - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\exc_$signal$5[0:0]$3656 - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\exc_$signal$6[0:0]$3657 - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\exc_$signal$7[0:0]$3658 - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\exc_$signal$8[0:0]$3659 - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\exc_$signal$9[0:0]$3660 - attribute \src "libresoc.v:75297.3-75454.6" - wire $3\exc_$signal[0:0]$3653 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\exc_$signal$3[0:0]$3713 + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\exc_$signal$4[0:0]$3714 + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\exc_$signal$5[0:0]$3715 + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\exc_$signal$6[0:0]$3716 + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\exc_$signal$7[0:0]$3717 + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\exc_$signal$8[0:0]$3718 + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\exc_$signal$9[0:0]$3719 + attribute \src "libresoc.v:78948.3-79105.6" + wire $3\exc_$signal[0:0]$3712 + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 12 $3\fn_unit[11:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $3\fn_unit[13:0] + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\is_32bit[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\lk[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\oe[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\oe_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\rc[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\rc_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $3\reg1[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\reg1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $3\reg2[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\reg2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $3\reg3[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\reg3[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $3\rego[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $3\rego[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $3\rego_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\spro_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\xer_out[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $4\asmcode[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $4\cia[63:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $4\cr_in1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\cr_in1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_in1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $4\cr_in2$1[2:0]$3661 - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $4\cr_in2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\cr_in2_ok$2[0:0]$3662 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\cr_in2$1[6:0]$3720 + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\cr_in2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\cr_in2_ok$2[0:0]$3721 + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_in2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 3 $4\cr_out[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\cr_out[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_out_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $4\cr_rd[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_rd_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $4\cr_wr[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_wr_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $4\ea[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\ea[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $4\ea_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\exc_$signal$3[0:0]$3664 - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\exc_$signal$4[0:0]$3665 - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\exc_$signal$5[0:0]$3666 - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\exc_$signal$6[0:0]$3667 - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\exc_$signal$7[0:0]$3668 - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\exc_$signal$8[0:0]$3669 - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\exc_$signal$9[0:0]$3670 - attribute \src "libresoc.v:75297.3-75454.6" - wire $4\exc_$signal[0:0]$3663 - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\exc_$signal$3[0:0]$3723 + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\exc_$signal$4[0:0]$3724 + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\exc_$signal$5[0:0]$3725 + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\exc_$signal$6[0:0]$3726 + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\exc_$signal$7[0:0]$3727 + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\exc_$signal$8[0:0]$3728 + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\exc_$signal$9[0:0]$3729 + attribute \src "libresoc.v:78948.3-79105.6" + wire $4\exc_$signal[0:0]$3722 + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\fast1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\fast1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\fast2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\fast2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\fasto1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\fasto1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\fasto2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\fasto2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 12 $4\fn_unit[11:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $4\fn_unit[13:0] + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $4\input_carry[1:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $4\insn[31:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\insn_type[6:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\is_32bit[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\lk[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $4\msr[63:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\oe[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\oe_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\rc[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\rc_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $4\reg1[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\reg1[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $4\reg1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $4\reg2[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\reg2[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $4\reg2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $4\reg3[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\reg3[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $4\reg3_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" - wire width 5 $4\rego[4:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 7 $4\rego[6:0] + attribute \src "libresoc.v:78948.3-79105.6" wire $4\rego_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $4\spr1[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\spr1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $4\spro[9:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\spro_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $4\trapaddr[12:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $4\traptype[7:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\xer_in[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\xer_out[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $5\fast1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $5\fast1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $5\fast2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $5\fast2_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $5\fasto1[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $5\fasto1_ok[0:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $5\fasto2[2:0] - attribute \src "libresoc.v:75297.3-75454.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $5\fasto2_ok[0:0] - attribute \src "libresoc.v:75086.18-75086.120" - wire $and$libresoc.v:75086$3611_Y - attribute \src "libresoc.v:75087.18-75087.123" - wire $and$libresoc.v:75087$3612_Y - attribute \src "libresoc.v:75088.18-75088.124" - wire $and$libresoc.v:75088$3613_Y - attribute \src "libresoc.v:75078.18-75078.116" - wire $eq$libresoc.v:75078$3603_Y - attribute \src "libresoc.v:75079.18-75079.116" - wire $eq$libresoc.v:75079$3604_Y - attribute \src "libresoc.v:75081.18-75081.116" - wire $eq$libresoc.v:75081$3606_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 output 5 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 output 39 \cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 30 \cr_in1 + wire width 7 output 30 \cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 31 \cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 32 \cr_in2 + wire width 7 output 32 \cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 34 \cr_in2$1 + wire width 7 output 34 \cr_in2$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \cr_in2_ok$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 36 \cr_out + wire width 7 output 36 \cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 37 \cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -119166,13 +123624,13 @@ module \dec2 wire width 8 output 61 \cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 62 \cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 input 64 \cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire input 65 \cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" + wire input 66 \cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 input 3 \cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 2 \cur_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal @@ -119190,43 +123648,43 @@ module \dec2 wire \dec2_exc_$signal$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 8 \dec_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \dec_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \dec_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 10 \dec_XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 \dec_X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_a_fast_a @@ -119242,7 +123700,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" wire width 3 \dec_a_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -119309,6 +123767,9 @@ module \dec2 attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -119359,14 +123820,16 @@ module \dec2 wire width 10 \dec_a_spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + wire \dec_a_sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_b_fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_b_fast_b_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec_b_reg_b + wire width 7 \dec_b_reg_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_b_reg_b_ok attribute \enum_base_type "In2Sel" @@ -119384,7 +123847,7 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_c_reg_c @@ -119394,7 +123857,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298" wire width 2 \dec_c_sel_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -119404,7 +123867,8 @@ module \dec2 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_cr_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_in_cr_bitfield @@ -119422,7 +123886,7 @@ module \dec2 wire width 8 \dec_cr_in_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -119432,7 +123896,8 @@ module \dec2 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520" wire width 3 \dec_cr_in_sel_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -119440,7 +123905,8 @@ module \dec2 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_out_cr_bitfield @@ -119450,9 +123916,9 @@ module \dec2 wire width 8 \dec_cr_out_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -119460,36 +123926,39 @@ module \dec2 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_cry_in attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -119506,13 +123975,13 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -119588,24 +124057,25 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:904" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" wire \dec_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec_o2_fast_o + wire width 3 \dec_o2_fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_o2_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" + wire \dec_o2_fast_o2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" wire \dec_o2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec_o2_reg_o + wire width 5 \dec_o2_reg_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_o2_reg_o_ok + wire \dec_o2_reg_o2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_o_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -119615,12 +124085,13 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o_reg_o_ok attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - wire width 2 \dec_o_sel_in + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 3 \dec_o_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -119686,6 +124157,9 @@ module \dec2 attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -119744,17 +124218,18 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_out_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -119763,23 +124238,23 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 8 \ea + wire width 7 output 8 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 9 \ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" @@ -119798,7 +124273,7 @@ module \dec2 wire output 56 \exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 57 \exc_$signal$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1196" wire \ext_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 22 \fast1 @@ -119817,23 +124292,25 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \fasto2_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 output 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906" + wire width 14 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1199" wire \illeg_ok - attribute \src "libresoc.v:73487.7-73487.15" + attribute \src "libresoc.v:76965.7-76965.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -119843,20 +124320,20 @@ module \dec2 wire width 2 output 48 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 output 40 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" - wire width 32 \insn_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" - wire width 32 \insn_in$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:283" - wire width 32 \insn_in$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312" - wire width 32 \insn_in$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" - wire width 32 \insn_in$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" + wire width 32 \insn_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + wire width 32 \insn_in$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + wire width 32 \insn_in$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + wire width 32 \insn_in$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + wire width 32 \insn_in$89 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -119931,12 +124408,17 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 output 41 \insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire output 63 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:51" wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire output 43 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" @@ -119945,37 +124427,40 @@ module \dec2 wire output 46 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1198" wire \priv_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 4 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 10 \reg1 + wire width 7 output 10 \reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 11 \reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 12 \reg2 + wire width 7 output 12 \reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 13 \reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 14 \reg3 + wire width 7 output 14 \reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 15 \reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 6 \rego + wire width 7 output 6 \rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 7 \rego_ok attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" - wire width 2 \sel_in + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -120041,6 +124526,9 @@ module \dec2 attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -120156,6 +124644,9 @@ module \dec2 attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -120206,26 +124697,28 @@ module \dec2 wire width 10 output 16 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 65 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \tmp_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \tmp_cr_in1 + wire width 7 \tmp_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \tmp_cr_in2 + wire width 7 \tmp_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \tmp_cr_in2$19 + wire width 7 \tmp_cr_in2$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_cr_in2_ok$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \tmp_cr_out + wire width 7 \tmp_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \tmp_ea + wire width 7 \tmp_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -120245,19 +124738,19 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_fasto2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \tmp_reg1 + wire width 7 \tmp_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \tmp_reg2 + wire width 7 \tmp_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \tmp_reg3 + wire width 7 \tmp_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \tmp_rego + wire width 7 \tmp_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_rego_ok attribute \enum_base_type "SPR" @@ -120325,6 +124818,9 @@ module \dec2 attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -120440,6 +124936,9 @@ module \dec2 attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -120517,20 +125016,22 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$27 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 \tmp_tmp_fn_unit + wire width 14 \tmp_tmp_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -120613,6 +125114,7 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \tmp_tmp_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" @@ -120645,8 +125147,8 @@ module \dec2 wire width 3 output 20 \xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909" - cell $and $and$libresoc.v:75086$3611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" + cell $and $and$libresoc.v:78671$3630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -120654,10 +125156,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] - connect \Y $and$libresoc.v:75086$3611_Y + connect \Y $and$libresoc.v:78671$3630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" - cell $and $and$libresoc.v:75087$3612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1203" + cell $and $and$libresoc.v:78672$3631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -120665,10 +125167,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:75087$3612_Y + connect \Y $and$libresoc.v:78672$3631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911" - cell $and $and$libresoc.v:75088$3613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" + cell $and $and$libresoc.v:78673$3632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -120676,43 +125178,98 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:75088$3613_Y + connect \Y $and$libresoc.v:78673$3632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960" - cell $eq $eq$libresoc.v:75078$3603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:78680$3639 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'0111111 - connect \Y $eq$libresoc.v:75078$3603_Y + connect \A \is_spr_mv + connect \B \$37 + connect \Y $and$libresoc.v:78680$3639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" - cell $eq $eq$libresoc.v:75079$3604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:78681$3640 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1001001 - connect \Y $eq$libresoc.v:75079$3604_Y + connect \A \$39 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:78681$3640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" - cell $eq $eq$libresoc.v:75081$3606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:78683$3642 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1000110 - connect \Y $eq$libresoc.v:75081$3606_Y + connect \A \is_spr_mv + connect \B \$43 + connect \Y $and$libresoc.v:78683$3642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:78685$3644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \B \$47 + connect \Y $and$libresoc.v:78685$3644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:78697$3656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$71 + connect \Y $and$libresoc.v:78697$3656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:78698$3657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:78698$3657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:78700$3659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$77 + connect \Y $and$libresoc.v:78700$3659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" - cell $eq $eq$libresoc.v:75082$3607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:78702$3661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:78702$3661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" + cell $eq $eq$libresoc.v:78667$3626 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -120720,10 +125277,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:75082$3607_Y + connect \Y $eq$libresoc.v:78667$3626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" - cell $eq $eq$libresoc.v:75083$3608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" + cell $eq $eq$libresoc.v:78668$3627 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -120731,10 +125288,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 - connect \Y $eq$libresoc.v:75083$3608_Y + connect \Y $eq$libresoc.v:78668$3627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" - cell $eq $eq$libresoc.v:75084$3609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" + cell $eq $eq$libresoc.v:78669$3628 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -120742,10 +125299,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:75084$3609_Y + connect \Y $eq$libresoc.v:78669$3628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - cell $eq $eq$libresoc.v:75085$3610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + cell $eq $eq$libresoc.v:78670$3629 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -120753,10 +125310,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $eq$libresoc.v:75085$3610_Y + connect \Y $eq$libresoc.v:78670$3629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" - cell $eq $eq$libresoc.v:75089$3614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" + cell $eq $eq$libresoc.v:78674$3633 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -120764,10 +125321,233 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 - connect \Y $eq$libresoc.v:75089$3614_Y + connect \Y $eq$libresoc.v:78674$3633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1253" + cell $eq $eq$libresoc.v:78675$3634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:78675$3634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + cell $eq $eq$libresoc.v:78676$3635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:78676$3635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" + cell $eq $eq$libresoc.v:78678$3637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:78678$3637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:78679$3638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:78679$3638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:78682$3641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:78682$3641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:78686$3645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:78686$3645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:78687$3646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:78687$3646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:78689$3648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:78689$3648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:78690$3649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:78690$3649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:78692$3651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:78692$3651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:78694$3653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:78694$3653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:78696$3655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:78696$3655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:78699$3658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:78699$3658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:78664$3620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 7 + connect \A \dec_cr_in_cr_bitfield_b + connect \Y $extend$libresoc.v:78664$3620_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:78665$3622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 7 + connect \A \dec_cr_in_cr_bitfield_o + connect \Y $extend$libresoc.v:78665$3622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:78666$3624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 7 + connect \A \dec_cr_out_cr_bitfield + connect \Y $extend$libresoc.v:78666$3624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:78703$3662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \dec_a_reg_a + connect \Y $extend$libresoc.v:78703$3662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:78704$3664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \dec_c_reg_c + connect \Y $extend$libresoc.v:78704$3664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:78705$3666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \dec_o_reg_o + connect \Y $extend$libresoc.v:78705$3666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:78706$3668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \dec_o2_reg_o2 + connect \Y $extend$libresoc.v:78706$3668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:78707$3670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 7 + connect \A \dec_cr_in_cr_bitfield + connect \Y $extend$libresoc.v:78707$3670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:78684$3643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:78684$3643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:78701$3660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:78701$3660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" - cell $or $or$libresoc.v:75080$3605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + cell $or $or$libresoc.v:78677$3636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -120775,11 +125555,119 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 - connect \Y $or$libresoc.v:75080$3605_Y + connect \Y $or$libresoc.v:78677$3636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:78688$3647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \$53 + connect \Y $or$libresoc.v:78688$3647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:78691$3650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$57 + connect \B \$59 + connect \Y $or$libresoc.v:78691$3650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:78693$3652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$61 + connect \B \$63 + connect \Y $or$libresoc.v:78693$3652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:78695$3654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \B \$67 + connect \Y $or$libresoc.v:78695$3654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:78664$3621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:78664$3620_Y + connect \Y $pos$libresoc.v:78664$3621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:78665$3623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:78665$3622_Y + connect \Y $pos$libresoc.v:78665$3623_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:78666$3625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:78666$3624_Y + connect \Y $pos$libresoc.v:78666$3625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:78703$3663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:78703$3662_Y + connect \Y $pos$libresoc.v:78703$3663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:78704$3665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:78704$3664_Y + connect \Y $pos$libresoc.v:78704$3665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:78705$3667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:78705$3666_Y + connect \Y $pos$libresoc.v:78705$3667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:78706$3669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:78706$3668_Y + connect \Y $pos$libresoc.v:78706$3669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:78707$3671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:78707$3670_Y + connect \Y $pos$libresoc.v:78707$3671_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:75090.13-75127.4" - cell \dec$205 \dec + attribute \src "libresoc.v:78708.13-78745.4" + cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB connect \BC \dec_BC @@ -120818,7 +125706,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:75128.9-75142.4" + attribute \src "libresoc.v:78746.9-78761.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -120833,9 +125721,10 @@ module \dec2 connect \sel_in \dec_a_sel_in connect \spr_a \dec_a_spr_a connect \spr_a_ok \dec_a_spr_a_ok + connect \sv_nz \dec_a_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:75143.9-75153.4" + attribute \src "libresoc.v:78762.9-78772.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -120848,7 +125737,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:75154.9-75160.4" + attribute \src "libresoc.v:78773.9-78779.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -120857,8 +125746,8 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:75161.19-75180.4" - cell \dec_cr_in$208 \dec_cr_in$10 + attribute \src "libresoc.v:78780.13-78799.4" + cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB connect \BC \dec_BC @@ -120879,8 +125768,8 @@ module \dec2 connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:75181.20-75193.4" - cell \dec_cr_out$210 \dec_cr_out$11 + attribute \src "libresoc.v:78800.14-78812.4" + cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT connect \X_BF \dec_X_BF @@ -120894,7 +125783,7 @@ module \dec2 connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:75194.9-75207.4" + attribute \src "libresoc.v:78813.9-78826.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -120910,20 +125799,20 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:75208.10-75217.4" + attribute \src "libresoc.v:78827.10-78836.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA - connect \fast_o \dec_o2_fast_o - connect \fast_o_ok \dec_o2_fast_o_ok + connect \fast_o2 \dec_o2_fast_o2 + connect \fast_o2_ok \dec_o2_fast_o2_ok connect \internal_op \dec_internal_op connect \lk \dec_o2_lk - connect \reg_o \dec_o2_reg_o - connect \reg_o_ok \dec_o2_reg_o_ok + connect \reg_o2 \dec_o2_reg_o2 + connect \reg_o2_ok \dec_o2_reg_o2_ok connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:75218.16-75224.4" - cell \dec_oe$207 \dec_oe + attribute \src "libresoc.v:78837.16-78843.4" + cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op connect \oe \dec_oe_oe @@ -120931,33 +125820,61 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:75225.16-75230.4" - cell \dec_rc$206 \dec_rc + attribute \src "libresoc.v:78844.16-78849.4" + cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:73487.7-73487.20" - process $proc$libresoc.v:73487$3671 + attribute \src "libresoc.v:76965.7-76965.20" + process $proc$libresoc.v:76965$3730 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:75231.3-75240.6" - process $proc$libresoc.v:75231$3615 + attribute \src "libresoc.v:78850.3-78864.6" + process $proc$libresoc.v:78850$3672 + assign { } { } + assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:78851.5-78851.29" + switch \initial + attribute \src "libresoc.v:78851.9-78851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$83 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\tmp_tmp_fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\tmp_tmp_fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_tmp_fn_unit[13:0] \dec_function_unit + end + sync always + update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] + end + attribute \src "libresoc.v:78865.3-78874.6" + process $proc$libresoc.v:78865$3673 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:75232.5-75232.29" + attribute \src "libresoc.v:78866.5-78866.29" switch \initial - attribute \src "libresoc.v:75232.9-75232.17" + attribute \src "libresoc.v:78866.9-78866.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:869" switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -120969,20 +125886,47 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:75241.3-75256.6" - process $proc$libresoc.v:75241$3616 + attribute \src "libresoc.v:78875.3-78887.6" + process $proc$libresoc.v:78875$3674 + assign { } { } + assign { } { } + assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:78876.5-78876.29" + switch \initial + attribute \src "libresoc.v:78876.9-78876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$49 \$41 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\tmp_tmp_insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\tmp_tmp_insn_type[6:0] 7'0000000 + case + assign $1\tmp_tmp_insn_type[6:0] \dec_internal_op + end + sync always + update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] + end + attribute \src "libresoc.v:78888.3-78903.6" + process $proc$libresoc.v:78888$3675 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:75242.5-75242.29" + attribute \src "libresoc.v:78889.5-78889.29" switch \initial - attribute \src "libresoc.v:75242.9-75242.17" + attribute \src "libresoc.v:78889.9-78889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" - switch \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" + switch \$106 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -120990,8 +125934,8 @@ module \dec2 case assign $1\tmp_xer_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" - switch \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" + switch \$108 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -121002,19 +125946,19 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:75257.3-75266.6" - process $proc$libresoc.v:75257$3617 + attribute \src "libresoc.v:78904.3-78913.6" + process $proc$libresoc.v:78904$3676 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:75258.5-75258.29" + attribute \src "libresoc.v:78905.5-78905.29" switch \initial - attribute \src "libresoc.v:75258.9-75258.17" + attribute \src "libresoc.v:78905.9-78905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" - switch \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" + switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -121025,19 +125969,19 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:75267.3-75276.6" - process $proc$libresoc.v:75267$3618 + attribute \src "libresoc.v:78914.3-78923.6" + process $proc$libresoc.v:78914$3677 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:75268.5-75268.29" + attribute \src "libresoc.v:78915.5-78915.29" switch \initial - attribute \src "libresoc.v:75268.9-75268.17" + attribute \src "libresoc.v:78915.9-78915.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - switch \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + switch \$112 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -121048,28 +125992,32 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:75277.3-75296.6" - process $proc$libresoc.v:75277$3619 + attribute \src "libresoc.v:78924.3-78947.6" + process $proc$libresoc.v:78924$3678 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:75278.5-75278.29" + attribute \src "libresoc.v:78925.5-78925.29" switch \initial - attribute \src "libresoc.v:75278.9-75278.17" + attribute \src "libresoc.v:78925.9-78925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" switch \dec_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 assign { } { } assign $1\is_priv_insn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 7'1001011 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 , 7'0110001 assign { } { } assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58" switch \tmp_tmp_insn [20] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -121084,8 +126032,8 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:75297.3-75454.6" - process $proc$libresoc.v:75297$3620 + attribute \src "libresoc.v:78948.3-79105.6" + process $proc$libresoc.v:78948$3679 assign { } { } assign { } { } assign { } { } @@ -121154,35 +126102,35 @@ module \dec2 assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] assign $0\msr[63:0] $1\msr[63:0] assign $0\ea_ok[0:0] $1\ea_ok[0:0] - assign $0\ea[4:0] $1\ea[4:0] + assign $0\ea[6:0] $1\ea[6:0] assign { } { } - assign $0\cr_out[2:0] $1\cr_out[2:0] + assign $0\cr_out[6:0] $1\cr_out[6:0] assign $0\lk[0:0] $1\lk[0:0] assign $0\cia[63:0] $1\cia[63:0] - assign $0\cr_in1[2:0] $1\cr_in1[2:0] + assign $0\cr_in1[6:0] $1\cr_in1[6:0] assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] - assign $0\cr_in2[2:0] $1\cr_in2[2:0] - assign $0\cr_in2$1[2:0]$3621 $1\cr_in2$1[2:0]$3631 + assign $0\cr_in2[6:0] $1\cr_in2[6:0] + assign $0\cr_in2$1[6:0]$3680 $1\cr_in2$1[6:0]$3690 assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$3622 $1\cr_in2_ok$2[0:0]$3632 + assign $0\cr_in2_ok$2[0:0]$3681 $1\cr_in2_ok$2[0:0]$3691 assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] assign $0\cr_rd[7:0] $1\cr_rd[7:0] assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] assign $0\cr_wr[7:0] $1\cr_wr[7:0] assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign $0\exc_$signal[0:0]$3623 $1\exc_$signal[0:0]$3633 - assign $0\exc_$signal$3[0:0]$3624 $1\exc_$signal$3[0:0]$3634 - assign $0\exc_$signal$4[0:0]$3625 $1\exc_$signal$4[0:0]$3635 - assign $0\exc_$signal$5[0:0]$3626 $1\exc_$signal$5[0:0]$3636 - assign $0\exc_$signal$6[0:0]$3627 $1\exc_$signal$6[0:0]$3637 - assign $0\exc_$signal$7[0:0]$3628 $1\exc_$signal$7[0:0]$3638 - assign $0\exc_$signal$8[0:0]$3629 $1\exc_$signal$8[0:0]$3639 - assign $0\exc_$signal$9[0:0]$3630 $1\exc_$signal$9[0:0]$3640 + assign $0\exc_$signal[0:0]$3682 $1\exc_$signal[0:0]$3692 + assign $0\exc_$signal$3[0:0]$3683 $1\exc_$signal$3[0:0]$3693 + assign $0\exc_$signal$4[0:0]$3684 $1\exc_$signal$4[0:0]$3694 + assign $0\exc_$signal$5[0:0]$3685 $1\exc_$signal$5[0:0]$3695 + assign $0\exc_$signal$6[0:0]$3686 $1\exc_$signal$6[0:0]$3696 + assign $0\exc_$signal$7[0:0]$3687 $1\exc_$signal$7[0:0]$3697 + assign $0\exc_$signal$8[0:0]$3688 $1\exc_$signal$8[0:0]$3698 + assign $0\exc_$signal$9[0:0]$3689 $1\exc_$signal$9[0:0]$3699 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fn_unit[11:0] $1\fn_unit[11:0] + assign $0\fn_unit[13:0] $1\fn_unit[13:0] assign $0\input_carry[1:0] $1\input_carry[1:0] assign $0\insn[31:0] $1\insn[31:0] assign $0\insn_type[6:0] $1\insn_type[6:0] @@ -121190,13 +126138,13 @@ module \dec2 assign $0\oe[0:0] $1\oe[0:0] assign $0\oe_ok[0:0] $1\oe_ok[0:0] assign $0\rc_ok[0:0] $1\rc_ok[0:0] - assign $0\reg1[4:0] $1\reg1[4:0] + assign $0\reg1[6:0] $1\reg1[6:0] assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] - assign $0\reg2[4:0] $1\reg2[4:0] + assign $0\reg2[6:0] $1\reg2[6:0] assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] - assign $0\reg3[4:0] $1\reg3[4:0] + assign $0\reg3[6:0] $1\reg3[6:0] assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] - assign $0\rego[4:0] $1\rego[4:0] + assign $0\rego[6:0] $1\rego[6:0] assign $0\rego_ok[0:0] $1\rego_ok[0:0] assign $0\spro[9:0] $1\spro[9:0] assign $0\spro_ok[0:0] $1\spro_ok[0:0] @@ -121213,13 +126161,13 @@ module \dec2 assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:75298.5-75298.29" + attribute \src "libresoc.v:78949.5-78949.29" switch \initial - attribute \src "libresoc.v:75298.9-75298.17" + attribute \src "libresoc.v:78949.9-78949.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:916" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1209" switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" case 5'----1 @@ -121291,35 +126239,35 @@ module \dec2 assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] assign $1\msr[63:0] $2\msr[63:0] assign $1\ea_ok[0:0] $2\ea_ok[0:0] - assign $1\ea[4:0] $2\ea[4:0] + assign $1\ea[6:0] $2\ea[6:0] assign $1\asmcode[7:0] $2\asmcode[7:0] - assign $1\cr_out[2:0] $2\cr_out[2:0] + assign $1\cr_out[6:0] $2\cr_out[6:0] assign $1\lk[0:0] $2\lk[0:0] assign $1\cia[63:0] $2\cia[63:0] - assign $1\cr_in1[2:0] $2\cr_in1[2:0] + assign $1\cr_in1[6:0] $2\cr_in1[6:0] assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] - assign $1\cr_in2[2:0] $2\cr_in2[2:0] - assign $1\cr_in2$1[2:0]$3631 $2\cr_in2$1[2:0]$3641 + assign $1\cr_in2[6:0] $2\cr_in2[6:0] + assign $1\cr_in2$1[6:0]$3690 $2\cr_in2$1[6:0]$3700 assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] - assign $1\cr_in2_ok$2[0:0]$3632 $2\cr_in2_ok$2[0:0]$3642 + assign $1\cr_in2_ok$2[0:0]$3691 $2\cr_in2_ok$2[0:0]$3701 assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] assign $1\cr_rd[7:0] $2\cr_rd[7:0] assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] assign $1\cr_wr[7:0] $2\cr_wr[7:0] assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] - assign $1\exc_$signal[0:0]$3633 $2\exc_$signal[0:0]$3643 - assign $1\exc_$signal$3[0:0]$3634 $2\exc_$signal$3[0:0]$3644 - assign $1\exc_$signal$4[0:0]$3635 $2\exc_$signal$4[0:0]$3645 - assign $1\exc_$signal$5[0:0]$3636 $2\exc_$signal$5[0:0]$3646 - assign $1\exc_$signal$6[0:0]$3637 $2\exc_$signal$6[0:0]$3647 - assign $1\exc_$signal$7[0:0]$3638 $2\exc_$signal$7[0:0]$3648 - assign $1\exc_$signal$8[0:0]$3639 $2\exc_$signal$8[0:0]$3649 - assign $1\exc_$signal$9[0:0]$3640 $2\exc_$signal$9[0:0]$3650 + assign $1\exc_$signal[0:0]$3692 $2\exc_$signal[0:0]$3702 + assign $1\exc_$signal$3[0:0]$3693 $2\exc_$signal$3[0:0]$3703 + assign $1\exc_$signal$4[0:0]$3694 $2\exc_$signal$4[0:0]$3704 + assign $1\exc_$signal$5[0:0]$3695 $2\exc_$signal$5[0:0]$3705 + assign $1\exc_$signal$6[0:0]$3696 $2\exc_$signal$6[0:0]$3706 + assign $1\exc_$signal$7[0:0]$3697 $2\exc_$signal$7[0:0]$3707 + assign $1\exc_$signal$8[0:0]$3698 $2\exc_$signal$8[0:0]$3708 + assign $1\exc_$signal$9[0:0]$3699 $2\exc_$signal$9[0:0]$3709 assign $1\fasto1[2:0] $2\fasto1[2:0] assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] assign $1\fasto2[2:0] $2\fasto2[2:0] assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] - assign $1\fn_unit[11:0] $2\fn_unit[11:0] + assign $1\fn_unit[13:0] $2\fn_unit[13:0] assign $1\input_carry[1:0] $2\input_carry[1:0] assign $1\insn[31:0] $2\insn[31:0] assign $1\insn_type[6:0] $2\insn_type[6:0] @@ -121327,13 +126275,13 @@ module \dec2 assign $1\oe[0:0] $2\oe[0:0] assign $1\oe_ok[0:0] $2\oe_ok[0:0] assign $1\rc_ok[0:0] $2\rc_ok[0:0] - assign $1\reg1[4:0] $2\reg1[4:0] + assign $1\reg1[6:0] $2\reg1[6:0] assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] - assign $1\reg2[4:0] $2\reg2[4:0] + assign $1\reg2[6:0] $2\reg2[6:0] assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] - assign $1\reg3[4:0] $2\reg3[4:0] + assign $1\reg3[6:0] $2\reg3[6:0] assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] - assign $1\rego[4:0] $2\rego[4:0] + assign $1\rego[6:0] $2\rego[6:0] assign $1\rego_ok[0:0] $2\rego_ok[0:0] assign $1\spro[9:0] $2\spro[9:0] assign $1\spro_ok[0:0] $2\spro_ok[0:0] @@ -121341,7 +126289,7 @@ module \dec2 assign $1\traptype[7:0] $2\traptype[7:0] assign $1\xer_in[2:0] $2\xer_in[2:0] assign $1\xer_out[0:0] $2\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1210" switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -121404,10 +126352,10 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3650 $2\exc_$signal$8[0:0]$3649 $2\exc_$signal$7[0:0]$3648 $2\exc_$signal$6[0:0]$3647 $2\exc_$signal$5[0:0]$3646 $2\exc_$signal$4[0:0]$3645 $2\exc_$signal$3[0:0]$3644 $2\exc_$signal[0:0]$3643 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[2:0] $2\cr_in2_ok$2[0:0]$3642 $2\cr_in2$1[2:0]$3641 $2\cr_in2_ok[0:0] $2\cr_in2[2:0] $2\cr_in1_ok[0:0] $2\cr_in1[2:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[4:0] $2\reg2_ok[0:0] $2\reg2[4:0] $2\reg1_ok[0:0] $2\reg1[4:0] $2\ea_ok[0:0] $2\ea[4:0] $2\rego_ok[0:0] $2\rego[4:0] $2\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3709 $2\exc_$signal$8[0:0]$3708 $2\exc_$signal$7[0:0]$3707 $2\exc_$signal$6[0:0]$3706 $2\exc_$signal$5[0:0]$3705 $2\exc_$signal$4[0:0]$3704 $2\exc_$signal$3[0:0]$3703 $2\exc_$signal[0:0]$3702 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3701 $2\cr_in2$1[6:0]$3700 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $2\insn[31:0] \dec_opcode_in assign $2\insn_type[6:0] 7'0111111 - assign $2\fn_unit[11:0] 12'000010000000 + assign $2\fn_unit[13:0] 14'00000010000000 assign $2\trapaddr[12:0] 13'0000001100000 assign $2\traptype[7:0] 8'00000010 assign $2\msr[63:0] \cur_msr @@ -121482,35 +126430,35 @@ module \dec2 assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] assign $2\msr[63:0] $3\msr[63:0] assign $2\ea_ok[0:0] $3\ea_ok[0:0] - assign $2\ea[4:0] $3\ea[4:0] + assign $2\ea[6:0] $3\ea[6:0] assign $2\asmcode[7:0] $3\asmcode[7:0] - assign $2\cr_out[2:0] $3\cr_out[2:0] + assign $2\cr_out[6:0] $3\cr_out[6:0] assign $2\lk[0:0] $3\lk[0:0] assign $2\cia[63:0] $3\cia[63:0] - assign $2\cr_in1[2:0] $3\cr_in1[2:0] + assign $2\cr_in1[6:0] $3\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] - assign $2\cr_in2[2:0] $3\cr_in2[2:0] - assign $2\cr_in2$1[2:0]$3641 $3\cr_in2$1[2:0]$3651 + assign $2\cr_in2[6:0] $3\cr_in2[6:0] + assign $2\cr_in2$1[6:0]$3700 $3\cr_in2$1[6:0]$3710 assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3642 $3\cr_in2_ok$2[0:0]$3652 + assign $2\cr_in2_ok$2[0:0]$3701 $3\cr_in2_ok$2[0:0]$3711 assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] assign $2\cr_rd[7:0] $3\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $3\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3643 $3\exc_$signal[0:0]$3653 - assign $2\exc_$signal$3[0:0]$3644 $3\exc_$signal$3[0:0]$3654 - assign $2\exc_$signal$4[0:0]$3645 $3\exc_$signal$4[0:0]$3655 - assign $2\exc_$signal$5[0:0]$3646 $3\exc_$signal$5[0:0]$3656 - assign $2\exc_$signal$6[0:0]$3647 $3\exc_$signal$6[0:0]$3657 - assign $2\exc_$signal$7[0:0]$3648 $3\exc_$signal$7[0:0]$3658 - assign $2\exc_$signal$8[0:0]$3649 $3\exc_$signal$8[0:0]$3659 - assign $2\exc_$signal$9[0:0]$3650 $3\exc_$signal$9[0:0]$3660 + assign $2\exc_$signal[0:0]$3702 $3\exc_$signal[0:0]$3712 + assign $2\exc_$signal$3[0:0]$3703 $3\exc_$signal$3[0:0]$3713 + assign $2\exc_$signal$4[0:0]$3704 $3\exc_$signal$4[0:0]$3714 + assign $2\exc_$signal$5[0:0]$3705 $3\exc_$signal$5[0:0]$3715 + assign $2\exc_$signal$6[0:0]$3706 $3\exc_$signal$6[0:0]$3716 + assign $2\exc_$signal$7[0:0]$3707 $3\exc_$signal$7[0:0]$3717 + assign $2\exc_$signal$8[0:0]$3708 $3\exc_$signal$8[0:0]$3718 + assign $2\exc_$signal$9[0:0]$3709 $3\exc_$signal$9[0:0]$3719 assign $2\fasto1[2:0] $3\fasto1[2:0] assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] assign $2\fasto2[2:0] $3\fasto2[2:0] assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] - assign $2\fn_unit[11:0] $3\fn_unit[11:0] + assign $2\fn_unit[13:0] $3\fn_unit[13:0] assign $2\input_carry[1:0] $3\input_carry[1:0] assign $2\insn[31:0] $3\insn[31:0] assign $2\insn_type[6:0] $3\insn_type[6:0] @@ -121518,13 +126466,13 @@ module \dec2 assign $2\oe[0:0] $3\oe[0:0] assign $2\oe_ok[0:0] $3\oe_ok[0:0] assign $2\rc_ok[0:0] $3\rc_ok[0:0] - assign $2\reg1[4:0] $3\reg1[4:0] + assign $2\reg1[6:0] $3\reg1[6:0] assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] - assign $2\reg2[4:0] $3\reg2[4:0] + assign $2\reg2[6:0] $3\reg2[6:0] assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] - assign $2\reg3[4:0] $3\reg3[4:0] + assign $2\reg3[6:0] $3\reg3[6:0] assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] - assign $2\rego[4:0] $3\rego[4:0] + assign $2\rego[6:0] $3\rego[6:0] assign $2\rego_ok[0:0] $3\rego_ok[0:0] assign $2\spro[9:0] $3\spro[9:0] assign $2\spro_ok[0:0] $3\spro_ok[0:0] @@ -121532,7 +126480,7 @@ module \dec2 assign $2\traptype[7:0] $3\traptype[7:0] assign $2\xer_in[2:0] $3\xer_in[2:0] assign $2\xer_out[0:0] $3\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1213" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -121595,10 +126543,10 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3660 $3\exc_$signal$8[0:0]$3659 $3\exc_$signal$7[0:0]$3658 $3\exc_$signal$6[0:0]$3657 $3\exc_$signal$5[0:0]$3656 $3\exc_$signal$4[0:0]$3655 $3\exc_$signal$3[0:0]$3654 $3\exc_$signal[0:0]$3653 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$3652 $3\cr_in2$1[2:0]$3651 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 - assign $3\fn_unit[11:0] 12'000010000000 + assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001001000 assign $3\traptype[7:0] 8'00000010 assign $3\msr[63:0] \cur_msr @@ -121664,13 +126612,13 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$3652 $3\cr_in2$1[2:0]$3651 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 - assign $3\fn_unit[11:0] 12'000010000000 + assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001000000 assign $3\traptype[7:0] 8'01000000 - assign { $3\exc_$signal$9[0:0]$3660 $3\exc_$signal$8[0:0]$3659 $3\exc_$signal$7[0:0]$3658 $3\exc_$signal$6[0:0]$3657 $3\exc_$signal$5[0:0]$3656 $3\exc_$signal$4[0:0]$3655 $3\exc_$signal$3[0:0]$3654 $3\exc_$signal[0:0]$3653 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign { $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } assign $3\msr[63:0] \cur_msr assign $3\cia[63:0] \cur_pc end @@ -121744,35 +126692,35 @@ module \dec2 assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] assign $2\msr[63:0] $4\msr[63:0] assign $2\ea_ok[0:0] $4\ea_ok[0:0] - assign $2\ea[4:0] $4\ea[4:0] + assign $2\ea[6:0] $4\ea[6:0] assign $2\asmcode[7:0] $4\asmcode[7:0] - assign $2\cr_out[2:0] $4\cr_out[2:0] + assign $2\cr_out[6:0] $4\cr_out[6:0] assign $2\lk[0:0] $4\lk[0:0] assign $2\cia[63:0] $4\cia[63:0] - assign $2\cr_in1[2:0] $4\cr_in1[2:0] + assign $2\cr_in1[6:0] $4\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] - assign $2\cr_in2[2:0] $4\cr_in2[2:0] - assign $2\cr_in2$1[2:0]$3641 $4\cr_in2$1[2:0]$3661 + assign $2\cr_in2[6:0] $4\cr_in2[6:0] + assign $2\cr_in2$1[6:0]$3700 $4\cr_in2$1[6:0]$3720 assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3642 $4\cr_in2_ok$2[0:0]$3662 + assign $2\cr_in2_ok$2[0:0]$3701 $4\cr_in2_ok$2[0:0]$3721 assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] assign $2\cr_rd[7:0] $4\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $4\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3643 $4\exc_$signal[0:0]$3663 - assign $2\exc_$signal$3[0:0]$3644 $4\exc_$signal$3[0:0]$3664 - assign $2\exc_$signal$4[0:0]$3645 $4\exc_$signal$4[0:0]$3665 - assign $2\exc_$signal$5[0:0]$3646 $4\exc_$signal$5[0:0]$3666 - assign $2\exc_$signal$6[0:0]$3647 $4\exc_$signal$6[0:0]$3667 - assign $2\exc_$signal$7[0:0]$3648 $4\exc_$signal$7[0:0]$3668 - assign $2\exc_$signal$8[0:0]$3649 $4\exc_$signal$8[0:0]$3669 - assign $2\exc_$signal$9[0:0]$3650 $4\exc_$signal$9[0:0]$3670 + assign $2\exc_$signal[0:0]$3702 $4\exc_$signal[0:0]$3722 + assign $2\exc_$signal$3[0:0]$3703 $4\exc_$signal$3[0:0]$3723 + assign $2\exc_$signal$4[0:0]$3704 $4\exc_$signal$4[0:0]$3724 + assign $2\exc_$signal$5[0:0]$3705 $4\exc_$signal$5[0:0]$3725 + assign $2\exc_$signal$6[0:0]$3706 $4\exc_$signal$6[0:0]$3726 + assign $2\exc_$signal$7[0:0]$3707 $4\exc_$signal$7[0:0]$3727 + assign $2\exc_$signal$8[0:0]$3708 $4\exc_$signal$8[0:0]$3728 + assign $2\exc_$signal$9[0:0]$3709 $4\exc_$signal$9[0:0]$3729 assign $2\fasto1[2:0] $4\fasto1[2:0] assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] assign $2\fasto2[2:0] $4\fasto2[2:0] assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] - assign $2\fn_unit[11:0] $4\fn_unit[11:0] + assign $2\fn_unit[13:0] $4\fn_unit[13:0] assign $2\input_carry[1:0] $4\input_carry[1:0] assign $2\insn[31:0] $4\insn[31:0] assign $2\insn_type[6:0] $4\insn_type[6:0] @@ -121780,13 +126728,13 @@ module \dec2 assign $2\oe[0:0] $4\oe[0:0] assign $2\oe_ok[0:0] $4\oe_ok[0:0] assign $2\rc_ok[0:0] $4\rc_ok[0:0] - assign $2\reg1[4:0] $4\reg1[4:0] + assign $2\reg1[6:0] $4\reg1[6:0] assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] - assign $2\reg2[4:0] $4\reg2[4:0] + assign $2\reg2[6:0] $4\reg2[6:0] assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] - assign $2\reg3[4:0] $4\reg3[4:0] + assign $2\reg3[6:0] $4\reg3[6:0] assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] - assign $2\rego[4:0] $4\rego[4:0] + assign $2\rego[6:0] $4\rego[6:0] assign $2\rego_ok[0:0] $4\rego_ok[0:0] assign $2\spro[9:0] $4\spro[9:0] assign $2\spro_ok[0:0] $4\spro_ok[0:0] @@ -121794,7 +126742,7 @@ module \dec2 assign $2\traptype[7:0] $4\traptype[7:0] assign $2\xer_in[2:0] $4\xer_in[2:0] assign $2\xer_out[0:0] $4\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:926" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1219" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -121857,10 +126805,10 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3670 $4\exc_$signal$8[0:0]$3669 $4\exc_$signal$7[0:0]$3668 $4\exc_$signal$6[0:0]$3667 $4\exc_$signal$5[0:0]$3666 $4\exc_$signal$4[0:0]$3665 $4\exc_$signal$3[0:0]$3664 $4\exc_$signal[0:0]$3663 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$3662 $4\cr_in2$1[2:0]$3661 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 - assign $4\fn_unit[11:0] 12'000010000000 + assign $4\fn_unit[13:0] 14'00000010000000 assign $4\trapaddr[12:0] 13'0000000111000 assign $4\traptype[7:0] 8'00000010 assign $4\msr[63:0] \cur_msr @@ -121926,10 +126874,10 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3670 $4\exc_$signal$8[0:0]$3669 $4\exc_$signal$7[0:0]$3668 $4\exc_$signal$6[0:0]$3667 $4\exc_$signal$5[0:0]$3666 $4\exc_$signal$4[0:0]$3665 $4\exc_$signal$3[0:0]$3664 $4\exc_$signal[0:0]$3663 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$3662 $4\cr_in2$1[2:0]$3661 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 - assign $4\fn_unit[11:0] 12'000010000000 + assign $4\fn_unit[13:0] 14'00000010000000 assign $4\trapaddr[12:0] 13'0000000110000 assign $4\traptype[7:0] 8'00000010 assign $4\msr[63:0] \cur_msr @@ -121997,10 +126945,10 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 + assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000010010000 assign $1\traptype[7:0] 8'00100000 assign $1\msr[63:0] \cur_msr @@ -122066,10 +127014,10 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 + assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001010000 assign $1\traptype[7:0] 8'00010000 assign $1\msr[63:0] \cur_msr @@ -122135,10 +127083,10 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 + assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001110000 assign $1\traptype[7:0] 8'00000010 assign $1\msr[63:0] \cur_msr @@ -122204,10 +127152,10 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 + assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001110000 assign $1\traptype[7:0] 8'10000000 assign $1\msr[63:0] \cur_msr @@ -122273,9 +127221,9 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -122293,7 +127241,7 @@ module \dec2 assign $5\fasto2[2:0] $1\fasto2[2:0] assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -122321,35 +127269,35 @@ module \dec2 update \spr1_ok $0\spr1_ok[0:0] update \msr $0\msr[63:0] update \ea_ok $0\ea_ok[0:0] - update \ea $0\ea[4:0] + update \ea $0\ea[6:0] update \asmcode $0\asmcode[7:0] - update \cr_out $0\cr_out[2:0] + update \cr_out $0\cr_out[6:0] update \lk $0\lk[0:0] update \cia $0\cia[63:0] - update \cr_in1 $0\cr_in1[2:0] + update \cr_in1 $0\cr_in1[6:0] update \cr_in1_ok $0\cr_in1_ok[0:0] - update \cr_in2 $0\cr_in2[2:0] - update \cr_in2$1 $0\cr_in2$1[2:0]$3621 + update \cr_in2 $0\cr_in2[6:0] + update \cr_in2$1 $0\cr_in2$1[6:0]$3680 update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3622 + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3681 update \cr_out_ok $0\cr_out_ok[0:0] update \cr_rd $0\cr_rd[7:0] update \cr_rd_ok $0\cr_rd_ok[0:0] update \cr_wr $0\cr_wr[7:0] update \cr_wr_ok $0\cr_wr_ok[0:0] - update \exc_$signal $0\exc_$signal[0:0]$3623 - update \exc_$signal$3 $0\exc_$signal$3[0:0]$3624 - update \exc_$signal$4 $0\exc_$signal$4[0:0]$3625 - update \exc_$signal$5 $0\exc_$signal$5[0:0]$3626 - update \exc_$signal$6 $0\exc_$signal$6[0:0]$3627 - update \exc_$signal$7 $0\exc_$signal$7[0:0]$3628 - update \exc_$signal$8 $0\exc_$signal$8[0:0]$3629 - update \exc_$signal$9 $0\exc_$signal$9[0:0]$3630 + update \exc_$signal $0\exc_$signal[0:0]$3682 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3683 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3684 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3685 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3686 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3687 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3688 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3689 update \fasto1 $0\fasto1[2:0] update \fasto1_ok $0\fasto1_ok[0:0] update \fasto2 $0\fasto2[2:0] update \fasto2_ok $0\fasto2_ok[0:0] - update \fn_unit $0\fn_unit[11:0] + update \fn_unit $0\fn_unit[13:0] update \input_carry $0\input_carry[1:0] update \insn $0\insn[31:0] update \insn_type $0\insn_type[6:0] @@ -122357,13 +127305,13 @@ module \dec2 update \oe $0\oe[0:0] update \oe_ok $0\oe_ok[0:0] update \rc_ok $0\rc_ok[0:0] - update \reg1 $0\reg1[4:0] + update \reg1 $0\reg1[6:0] update \reg1_ok $0\reg1_ok[0:0] - update \reg2 $0\reg2[4:0] + update \reg2 $0\reg2[6:0] update \reg2_ok $0\reg2_ok[0:0] - update \reg3 $0\reg3[4:0] + update \reg3 $0\reg3[6:0] update \reg3_ok $0\reg3_ok[0:0] - update \rego $0\rego[4:0] + update \rego $0\rego[6:0] update \rego_ok $0\rego_ok[0:0] update \spro $0\spro[9:0] update \spro_ok $0\spro_ok[0:0] @@ -122372,18 +127320,50 @@ module \dec2 update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - connect \$28 $eq$libresoc.v:75078$3603_Y - connect \$30 $eq$libresoc.v:75079$3604_Y - connect \$32 $or$libresoc.v:75080$3605_Y - connect \$34 $eq$libresoc.v:75081$3606_Y - connect \$42 $eq$libresoc.v:75082$3607_Y - connect \$44 $eq$libresoc.v:75083$3608_Y - connect \$46 $eq$libresoc.v:75084$3609_Y - connect \$48 $eq$libresoc.v:75085$3610_Y - connect \$50 $and$libresoc.v:75086$3611_Y - connect \$52 $and$libresoc.v:75087$3612_Y - connect \$54 $and$libresoc.v:75088$3613_Y - connect \$56 $eq$libresoc.v:75089$3614_Y + connect \$100 $pos$libresoc.v:78664$3621_Y + connect \$102 $pos$libresoc.v:78665$3623_Y + connect \$104 $pos$libresoc.v:78666$3625_Y + connect \$106 $eq$libresoc.v:78667$3626_Y + connect \$108 $eq$libresoc.v:78668$3627_Y + connect \$110 $eq$libresoc.v:78669$3628_Y + connect \$112 $eq$libresoc.v:78670$3629_Y + connect \$114 $and$libresoc.v:78671$3630_Y + connect \$116 $and$libresoc.v:78672$3631_Y + connect \$118 $and$libresoc.v:78673$3632_Y + connect \$120 $eq$libresoc.v:78674$3633_Y + connect \$28 $eq$libresoc.v:78675$3634_Y + connect \$30 $eq$libresoc.v:78676$3635_Y + connect \$32 $or$libresoc.v:78677$3636_Y + connect \$34 $eq$libresoc.v:78678$3637_Y + connect \$37 $eq$libresoc.v:78679$3638_Y + connect \$39 $and$libresoc.v:78680$3639_Y + connect \$41 $and$libresoc.v:78681$3640_Y + connect \$43 $eq$libresoc.v:78682$3641_Y + connect \$45 $and$libresoc.v:78683$3642_Y + connect \$47 $not$libresoc.v:78684$3643_Y + connect \$49 $and$libresoc.v:78685$3644_Y + connect \$51 $eq$libresoc.v:78686$3645_Y + connect \$53 $eq$libresoc.v:78687$3646_Y + connect \$55 $or$libresoc.v:78688$3647_Y + connect \$57 $eq$libresoc.v:78689$3648_Y + connect \$59 $eq$libresoc.v:78690$3649_Y + connect \$61 $or$libresoc.v:78691$3650_Y + connect \$63 $eq$libresoc.v:78692$3651_Y + connect \$65 $or$libresoc.v:78693$3652_Y + connect \$67 $eq$libresoc.v:78694$3653_Y + connect \$69 $or$libresoc.v:78695$3654_Y + connect \$71 $eq$libresoc.v:78696$3655_Y + connect \$73 $and$libresoc.v:78697$3656_Y + connect \$75 $and$libresoc.v:78698$3657_Y + connect \$77 $eq$libresoc.v:78699$3658_Y + connect \$79 $and$libresoc.v:78700$3659_Y + connect \$81 $not$libresoc.v:78701$3660_Y + connect \$83 $and$libresoc.v:78702$3661_Y + connect \$90 $pos$libresoc.v:78703$3663_Y + connect \$92 $pos$libresoc.v:78704$3665_Y + connect \$94 $pos$libresoc.v:78705$3667_Y + connect \$96 $pos$libresoc.v:78706$3669_Y + connect \$98 $pos$libresoc.v:78707$3671_Y connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 @@ -122402,164 +127382,1407 @@ module \dec2 connect \tmp_tmp_exc_$signal$25 1'0 connect \tmp_tmp_exc_$signal$26 1'0 connect \tmp_tmp_exc_$signal$27 1'0 - connect \illeg_ok \$56 - connect \priv_ok \$54 - connect \dec_irq_ok \$52 - connect \ext_irq_ok \$50 - connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - connect { \tmp_cr_in2_ok$20 \tmp_cr_in2$19 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } - connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } - connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } - connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + connect \illeg_ok \$120 + connect \priv_ok \$118 + connect \dec_irq_ok \$116 + connect \ext_irq_ok \$114 + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o2_ok \dec_o2_fast_o2 } connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } - connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } - connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } - connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } - connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + connect \tmp_cr_out_ok \dec_cr_out_cr_bitfield_ok + connect \tmp_cr_out \$104 + connect \tmp_cr_in2_ok$20 \dec_cr_in_cr_bitfield_o_ok + connect \tmp_cr_in2$19 \$102 + connect \tmp_cr_in2_ok \dec_cr_in_cr_bitfield_b_ok + connect \tmp_cr_in2 \$100 + connect \tmp_cr_in1_ok \dec_cr_in_cr_bitfield_ok + connect \tmp_cr_in1 \$98 + connect \tmp_ea_ok \dec_o2_reg_o2_ok + connect \tmp_ea \$96 + connect \tmp_rego_ok \dec_o_reg_o_ok + connect \tmp_rego \$94 + connect \tmp_reg3_ok \dec_c_reg_c_ok + connect \tmp_reg3 \$92 + connect \tmp_reg2_ok \dec_b_reg_b_ok + connect \tmp_reg2 \dec_b_reg_b + connect \tmp_reg1_ok \dec_a_reg_a_ok + connect \tmp_reg1 \$90 connect \dec_o2_lk \tmp_tmp_lk connect \sel_in \dec_out_sel connect \dec_o_sel_in \dec_out_sel connect \dec_c_sel_in \dec_in3_sel connect \dec_b_sel_in \dec_in2_sel connect \dec_a_sel_in \dec_in1_sel - connect \insn_in$41 \dec_opcode_in - connect \insn_in$40 \dec_opcode_in - connect \insn_in$39 \dec_opcode_in - connect \insn_in$38 \dec_opcode_in - connect \insn_in$37 \dec_opcode_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \insn_in$89 \dec_opcode_in + connect \insn_in$88 \dec_opcode_in + connect \insn_in$87 \dec_opcode_in + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$86 \dec_opcode_in + connect \insn_in$85 \dec_opcode_in connect \tmp_tmp_insn \dec_opcode_in + connect \dec_a_sv_nz \sv_a_nz connect \tmp_tmp_is_32bit \dec_is_32b connect \tmp_tmp_input_carry \dec_cry_in - connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } - connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } - connect \tmp_tmp_fn_unit \dec_function_unit - connect \tmp_tmp_insn_type \dec_internal_op + connect \is_mmu_spr \$69 + connect \is_spr_mv \$55 + connect \spr { \dec_SPR [4:0] \dec_SPR [9:5] } connect \tmp_tmp_cia \cur_pc connect \tmp_tmp_msr \cur_msr - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_cr_out - connect \dec_cr_in_sel_in \dec_cr_in connect \dec_oe_sel_in \dec_rc_sel connect \dec_rc_sel_in \dec_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:75527.1-76674.10" +attribute \src "libresoc.v:79189.1-79849.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" +attribute \generator "nMigen" +module \dec22 + attribute \src "libresoc.v:79788.3-79797.6" + wire width 2 $0\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:79798.3-79807.6" + wire width 2 $0\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:79668.3-79677.6" + wire width 8 $0\dec22_asmcode[7:0] + attribute \src "libresoc.v:79708.3-79717.6" + wire $0\dec22_br[0:0] + attribute \src "libresoc.v:79538.3-79547.6" + wire width 3 $0\dec22_cr_in[2:0] + attribute \src "libresoc.v:79548.3-79557.6" + wire width 3 $0\dec22_cr_out[2:0] + attribute \src "libresoc.v:79658.3-79667.6" + wire width 2 $0\dec22_cry_in[1:0] + attribute \src "libresoc.v:79698.3-79707.6" + wire $0\dec22_cry_out[0:0] + attribute \src "libresoc.v:79748.3-79757.6" + wire width 5 $0\dec22_form[4:0] + attribute \src "libresoc.v:79528.3-79537.6" + wire width 14 $0\dec22_function_unit[13:0] + attribute \src "libresoc.v:79808.3-79817.6" + wire width 3 $0\dec22_in1_sel[2:0] + attribute \src "libresoc.v:79818.3-79827.6" + wire width 4 $0\dec22_in2_sel[3:0] + attribute \src "libresoc.v:79828.3-79837.6" + wire width 2 $0\dec22_in3_sel[1:0] + attribute \src "libresoc.v:79638.3-79647.6" + wire width 7 $0\dec22_internal_op[6:0] + attribute \src "libresoc.v:79678.3-79687.6" + wire $0\dec22_inv_a[0:0] + attribute \src "libresoc.v:79688.3-79697.6" + wire $0\dec22_inv_out[0:0] + attribute \src "libresoc.v:79738.3-79747.6" + wire $0\dec22_is_32b[0:0] + attribute \src "libresoc.v:79618.3-79627.6" + wire width 4 $0\dec22_ldst_len[3:0] + attribute \src "libresoc.v:79768.3-79777.6" + wire $0\dec22_lk[0:0] + attribute \src "libresoc.v:79838.3-79847.6" + wire width 3 $0\dec22_out_sel[2:0] + attribute \src "libresoc.v:79648.3-79657.6" + wire width 2 $0\dec22_rc_sel[1:0] + attribute \src "libresoc.v:79728.3-79737.6" + wire $0\dec22_rsrv[0:0] + attribute \src "libresoc.v:79778.3-79787.6" + wire $0\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:79758.3-79767.6" + wire $0\dec22_sgn[0:0] + attribute \src "libresoc.v:79718.3-79727.6" + wire $0\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:79598.3-79607.6" + wire width 3 $0\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:79608.3-79617.6" + wire width 3 $0\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:79558.3-79567.6" + wire width 3 $0\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79568.3-79577.6" + wire width 3 $0\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79578.3-79587.6" + wire width 3 $0\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79588.3-79597.6" + wire width 3 $0\dec22_sv_out[2:0] + attribute \src "libresoc.v:79628.3-79637.6" + wire width 2 $0\dec22_upd[1:0] + attribute \src "libresoc.v:79190.7-79190.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:79788.3-79797.6" + wire width 2 $1\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:79798.3-79807.6" + wire width 2 $1\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:79668.3-79677.6" + wire width 8 $1\dec22_asmcode[7:0] + attribute \src "libresoc.v:79708.3-79717.6" + wire $1\dec22_br[0:0] + attribute \src "libresoc.v:79538.3-79547.6" + wire width 3 $1\dec22_cr_in[2:0] + attribute \src "libresoc.v:79548.3-79557.6" + wire width 3 $1\dec22_cr_out[2:0] + attribute \src "libresoc.v:79658.3-79667.6" + wire width 2 $1\dec22_cry_in[1:0] + attribute \src "libresoc.v:79698.3-79707.6" + wire $1\dec22_cry_out[0:0] + attribute \src "libresoc.v:79748.3-79757.6" + wire width 5 $1\dec22_form[4:0] + attribute \src "libresoc.v:79528.3-79537.6" + wire width 14 $1\dec22_function_unit[13:0] + attribute \src "libresoc.v:79808.3-79817.6" + wire width 3 $1\dec22_in1_sel[2:0] + attribute \src "libresoc.v:79818.3-79827.6" + wire width 4 $1\dec22_in2_sel[3:0] + attribute \src "libresoc.v:79828.3-79837.6" + wire width 2 $1\dec22_in3_sel[1:0] + attribute \src "libresoc.v:79638.3-79647.6" + wire width 7 $1\dec22_internal_op[6:0] + attribute \src "libresoc.v:79678.3-79687.6" + wire $1\dec22_inv_a[0:0] + attribute \src "libresoc.v:79688.3-79697.6" + wire $1\dec22_inv_out[0:0] + attribute \src "libresoc.v:79738.3-79747.6" + wire $1\dec22_is_32b[0:0] + attribute \src "libresoc.v:79618.3-79627.6" + wire width 4 $1\dec22_ldst_len[3:0] + attribute \src "libresoc.v:79768.3-79777.6" + wire $1\dec22_lk[0:0] + attribute \src "libresoc.v:79838.3-79847.6" + wire width 3 $1\dec22_out_sel[2:0] + attribute \src "libresoc.v:79648.3-79657.6" + wire width 2 $1\dec22_rc_sel[1:0] + attribute \src "libresoc.v:79728.3-79737.6" + wire $1\dec22_rsrv[0:0] + attribute \src "libresoc.v:79778.3-79787.6" + wire $1\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:79758.3-79767.6" + wire $1\dec22_sgn[0:0] + attribute \src "libresoc.v:79718.3-79727.6" + wire $1\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:79598.3-79607.6" + wire width 3 $1\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:79608.3-79617.6" + wire width 3 $1\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:79558.3-79567.6" + wire width 3 $1\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79568.3-79577.6" + wire width 3 $1\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79578.3-79587.6" + wire width 3 $1\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79588.3-79597.6" + wire width 3 $1\dec22_sv_out[2:0] + attribute \src "libresoc.v:79628.3-79637.6" + wire width 2 $1\dec22_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec22_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec22_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec22_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec22_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec22_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec22_upd + attribute \src "libresoc.v:79190.7-79190.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 4 \opcode_switch + attribute \src "libresoc.v:79190.7-79190.20" + process $proc$libresoc.v:79190$3763 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:79528.3-79537.6" + process $proc$libresoc.v:79528$3731 + assign { } { } + assign { } { } + assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] + attribute \src "libresoc.v:79529.5-79529.29" + switch \initial + attribute \src "libresoc.v:79529.9-79529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_function_unit[13:0] 14'10000000000000 + case + assign $1\dec22_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec22_function_unit $0\dec22_function_unit[13:0] + end + attribute \src "libresoc.v:79538.3-79547.6" + process $proc$libresoc.v:79538$3732 + assign { } { } + assign { } { } + assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] + attribute \src "libresoc.v:79539.5-79539.29" + switch \initial + attribute \src "libresoc.v:79539.9-79539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cr_in[2:0] 3'000 + case + assign $1\dec22_cr_in[2:0] 3'000 + end + sync always + update \dec22_cr_in $0\dec22_cr_in[2:0] + end + attribute \src "libresoc.v:79548.3-79557.6" + process $proc$libresoc.v:79548$3733 + assign { } { } + assign { } { } + assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] + attribute \src "libresoc.v:79549.5-79549.29" + switch \initial + attribute \src "libresoc.v:79549.9-79549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cr_out[2:0] 3'001 + case + assign $1\dec22_cr_out[2:0] 3'000 + end + sync always + update \dec22_cr_out $0\dec22_cr_out[2:0] + end + attribute \src "libresoc.v:79558.3-79567.6" + process $proc$libresoc.v:79558$3734 + assign { } { } + assign { } { } + assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79559.5-79559.29" + switch \initial + attribute \src "libresoc.v:79559.9-79559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in1[2:0] 3'000 + case + assign $1\dec22_sv_in1[2:0] 3'000 + end + sync always + update \dec22_sv_in1 $0\dec22_sv_in1[2:0] + end + attribute \src "libresoc.v:79568.3-79577.6" + process $proc$libresoc.v:79568$3735 + assign { } { } + assign { } { } + assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79569.5-79569.29" + switch \initial + attribute \src "libresoc.v:79569.9-79569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in2[2:0] 3'000 + case + assign $1\dec22_sv_in2[2:0] 3'000 + end + sync always + update \dec22_sv_in2 $0\dec22_sv_in2[2:0] + end + attribute \src "libresoc.v:79578.3-79587.6" + process $proc$libresoc.v:79578$3736 + assign { } { } + assign { } { } + assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79579.5-79579.29" + switch \initial + attribute \src "libresoc.v:79579.9-79579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in3[2:0] 3'000 + case + assign $1\dec22_sv_in3[2:0] 3'000 + end + sync always + update \dec22_sv_in3 $0\dec22_sv_in3[2:0] + end + attribute \src "libresoc.v:79588.3-79597.6" + process $proc$libresoc.v:79588$3737 + assign { } { } + assign { } { } + assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] + attribute \src "libresoc.v:79589.5-79589.29" + switch \initial + attribute \src "libresoc.v:79589.9-79589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_out[2:0] 3'000 + case + assign $1\dec22_sv_out[2:0] 3'000 + end + sync always + update \dec22_sv_out $0\dec22_sv_out[2:0] + end + attribute \src "libresoc.v:79598.3-79607.6" + process $proc$libresoc.v:79598$3738 + assign { } { } + assign { } { } + assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:79599.5-79599.29" + switch \initial + attribute \src "libresoc.v:79599.9-79599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_cr_in[2:0] 3'000 + case + assign $1\dec22_sv_cr_in[2:0] 3'000 + end + sync always + update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] + end + attribute \src "libresoc.v:79608.3-79617.6" + process $proc$libresoc.v:79608$3739 + assign { } { } + assign { } { } + assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:79609.5-79609.29" + switch \initial + attribute \src "libresoc.v:79609.9-79609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_cr_out[2:0] 3'000 + case + assign $1\dec22_sv_cr_out[2:0] 3'000 + end + sync always + update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] + end + attribute \src "libresoc.v:79618.3-79627.6" + process $proc$libresoc.v:79618$3740 + assign { } { } + assign { } { } + assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] + attribute \src "libresoc.v:79619.5-79619.29" + switch \initial + attribute \src "libresoc.v:79619.9-79619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_ldst_len[3:0] 4'0000 + case + assign $1\dec22_ldst_len[3:0] 4'0000 + end + sync always + update \dec22_ldst_len $0\dec22_ldst_len[3:0] + end + attribute \src "libresoc.v:79628.3-79637.6" + process $proc$libresoc.v:79628$3741 + assign { } { } + assign { } { } + assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] + attribute \src "libresoc.v:79629.5-79629.29" + switch \initial + attribute \src "libresoc.v:79629.9-79629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_upd[1:0] 2'00 + case + assign $1\dec22_upd[1:0] 2'00 + end + sync always + update \dec22_upd $0\dec22_upd[1:0] + end + attribute \src "libresoc.v:79638.3-79647.6" + process $proc$libresoc.v:79638$3742 + assign { } { } + assign { } { } + assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] + attribute \src "libresoc.v:79639.5-79639.29" + switch \initial + attribute \src "libresoc.v:79639.9-79639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_internal_op[6:0] 7'1001100 + case + assign $1\dec22_internal_op[6:0] 7'0000000 + end + sync always + update \dec22_internal_op $0\dec22_internal_op[6:0] + end + attribute \src "libresoc.v:79648.3-79657.6" + process $proc$libresoc.v:79648$3743 + assign { } { } + assign { } { } + assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] + attribute \src "libresoc.v:79649.5-79649.29" + switch \initial + attribute \src "libresoc.v:79649.9-79649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_rc_sel[1:0] 2'10 + case + assign $1\dec22_rc_sel[1:0] 2'00 + end + sync always + update \dec22_rc_sel $0\dec22_rc_sel[1:0] + end + attribute \src "libresoc.v:79658.3-79667.6" + process $proc$libresoc.v:79658$3744 + assign { } { } + assign { } { } + assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] + attribute \src "libresoc.v:79659.5-79659.29" + switch \initial + attribute \src "libresoc.v:79659.9-79659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cry_in[1:0] 2'00 + case + assign $1\dec22_cry_in[1:0] 2'00 + end + sync always + update \dec22_cry_in $0\dec22_cry_in[1:0] + end + attribute \src "libresoc.v:79668.3-79677.6" + process $proc$libresoc.v:79668$3745 + assign { } { } + assign { } { } + assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] + attribute \src "libresoc.v:79669.5-79669.29" + switch \initial + attribute \src "libresoc.v:79669.9-79669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_asmcode[7:0] 8'10011100 + case + assign $1\dec22_asmcode[7:0] 8'00000000 + end + sync always + update \dec22_asmcode $0\dec22_asmcode[7:0] + end + attribute \src "libresoc.v:79678.3-79687.6" + process $proc$libresoc.v:79678$3746 + assign { } { } + assign { } { } + assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] + attribute \src "libresoc.v:79679.5-79679.29" + switch \initial + attribute \src "libresoc.v:79679.9-79679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_inv_a[0:0] 1'0 + case + assign $1\dec22_inv_a[0:0] 1'0 + end + sync always + update \dec22_inv_a $0\dec22_inv_a[0:0] + end + attribute \src "libresoc.v:79688.3-79697.6" + process $proc$libresoc.v:79688$3747 + assign { } { } + assign { } { } + assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] + attribute \src "libresoc.v:79689.5-79689.29" + switch \initial + attribute \src "libresoc.v:79689.9-79689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_inv_out[0:0] 1'0 + case + assign $1\dec22_inv_out[0:0] 1'0 + end + sync always + update \dec22_inv_out $0\dec22_inv_out[0:0] + end + attribute \src "libresoc.v:79698.3-79707.6" + process $proc$libresoc.v:79698$3748 + assign { } { } + assign { } { } + assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] + attribute \src "libresoc.v:79699.5-79699.29" + switch \initial + attribute \src "libresoc.v:79699.9-79699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cry_out[0:0] 1'0 + case + assign $1\dec22_cry_out[0:0] 1'0 + end + sync always + update \dec22_cry_out $0\dec22_cry_out[0:0] + end + attribute \src "libresoc.v:79708.3-79717.6" + process $proc$libresoc.v:79708$3749 + assign { } { } + assign { } { } + assign $0\dec22_br[0:0] $1\dec22_br[0:0] + attribute \src "libresoc.v:79709.5-79709.29" + switch \initial + attribute \src "libresoc.v:79709.9-79709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_br[0:0] 1'0 + case + assign $1\dec22_br[0:0] 1'0 + end + sync always + update \dec22_br $0\dec22_br[0:0] + end + attribute \src "libresoc.v:79718.3-79727.6" + process $proc$libresoc.v:79718$3750 + assign { } { } + assign { } { } + assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:79719.5-79719.29" + switch \initial + attribute \src "libresoc.v:79719.9-79719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgn_ext[0:0] 1'0 + case + assign $1\dec22_sgn_ext[0:0] 1'0 + end + sync always + update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] + end + attribute \src "libresoc.v:79728.3-79737.6" + process $proc$libresoc.v:79728$3751 + assign { } { } + assign { } { } + assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] + attribute \src "libresoc.v:79729.5-79729.29" + switch \initial + attribute \src "libresoc.v:79729.9-79729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_rsrv[0:0] 1'0 + case + assign $1\dec22_rsrv[0:0] 1'0 + end + sync always + update \dec22_rsrv $0\dec22_rsrv[0:0] + end + attribute \src "libresoc.v:79738.3-79747.6" + process $proc$libresoc.v:79738$3752 + assign { } { } + assign { } { } + assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] + attribute \src "libresoc.v:79739.5-79739.29" + switch \initial + attribute \src "libresoc.v:79739.9-79739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_is_32b[0:0] 1'0 + case + assign $1\dec22_is_32b[0:0] 1'0 + end + sync always + update \dec22_is_32b $0\dec22_is_32b[0:0] + end + attribute \src "libresoc.v:79748.3-79757.6" + process $proc$libresoc.v:79748$3753 + assign { } { } + assign { } { } + assign $0\dec22_form[4:0] $1\dec22_form[4:0] + attribute \src "libresoc.v:79749.5-79749.29" + switch \initial + attribute \src "libresoc.v:79749.9-79749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_form[4:0] 5'11101 + case + assign $1\dec22_form[4:0] 5'00000 + end + sync always + update \dec22_form $0\dec22_form[4:0] + end + attribute \src "libresoc.v:79758.3-79767.6" + process $proc$libresoc.v:79758$3754 + assign { } { } + assign { } { } + assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] + attribute \src "libresoc.v:79759.5-79759.29" + switch \initial + attribute \src "libresoc.v:79759.9-79759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgn[0:0] 1'0 + case + assign $1\dec22_sgn[0:0] 1'0 + end + sync always + update \dec22_sgn $0\dec22_sgn[0:0] + end + attribute \src "libresoc.v:79768.3-79777.6" + process $proc$libresoc.v:79768$3755 + assign { } { } + assign { } { } + assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] + attribute \src "libresoc.v:79769.5-79769.29" + switch \initial + attribute \src "libresoc.v:79769.9-79769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_lk[0:0] 1'0 + case + assign $1\dec22_lk[0:0] 1'0 + end + sync always + update \dec22_lk $0\dec22_lk[0:0] + end + attribute \src "libresoc.v:79778.3-79787.6" + process $proc$libresoc.v:79778$3756 + assign { } { } + assign { } { } + assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:79779.5-79779.29" + switch \initial + attribute \src "libresoc.v:79779.9-79779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgl_pipe[0:0] 1'0 + case + assign $1\dec22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:79788.3-79797.6" + process $proc$libresoc.v:79788$3757 + assign { } { } + assign { } { } + assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:79789.5-79789.29" + switch \initial + attribute \src "libresoc.v:79789.9-79789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_SV_Etype[1:0] 2'00 + case + assign $1\dec22_SV_Etype[1:0] 2'00 + end + sync always + update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] + end + attribute \src "libresoc.v:79798.3-79807.6" + process $proc$libresoc.v:79798$3758 + assign { } { } + assign { } { } + assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:79799.5-79799.29" + switch \initial + attribute \src "libresoc.v:79799.9-79799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_SV_Ptype[1:0] 2'00 + case + assign $1\dec22_SV_Ptype[1:0] 2'00 + end + sync always + update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] + end + attribute \src "libresoc.v:79808.3-79817.6" + process $proc$libresoc.v:79808$3759 + assign { } { } + assign { } { } + assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] + attribute \src "libresoc.v:79809.5-79809.29" + switch \initial + attribute \src "libresoc.v:79809.9-79809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in1_sel[2:0] 3'010 + case + assign $1\dec22_in1_sel[2:0] 3'000 + end + sync always + update \dec22_in1_sel $0\dec22_in1_sel[2:0] + end + attribute \src "libresoc.v:79818.3-79827.6" + process $proc$libresoc.v:79818$3760 + assign { } { } + assign { } { } + assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] + attribute \src "libresoc.v:79819.5-79819.29" + switch \initial + attribute \src "libresoc.v:79819.9-79819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in2_sel[3:0] 4'0000 + case + assign $1\dec22_in2_sel[3:0] 4'0000 + end + sync always + update \dec22_in2_sel $0\dec22_in2_sel[3:0] + end + attribute \src "libresoc.v:79828.3-79837.6" + process $proc$libresoc.v:79828$3761 + assign { } { } + assign { } { } + assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] + attribute \src "libresoc.v:79829.5-79829.29" + switch \initial + attribute \src "libresoc.v:79829.9-79829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in3_sel[1:0] 2'00 + case + assign $1\dec22_in3_sel[1:0] 2'00 + end + sync always + update \dec22_in3_sel $0\dec22_in3_sel[1:0] + end + attribute \src "libresoc.v:79838.3-79847.6" + process $proc$libresoc.v:79838$3762 + assign { } { } + assign { } { } + assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] + attribute \src "libresoc.v:79839.5-79839.29" + switch \initial + attribute \src "libresoc.v:79839.9-79839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_out_sel[2:0] 3'100 + case + assign $1\dec22_out_sel[2:0] 3'000 + end + sync always + update \dec22_out_sel $0\dec22_out_sel[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:79853.1-81377.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:75970.3-76006.6" + attribute \src "libresoc.v:81154.3-81190.6" + wire width 2 $0\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:81191.3-81227.6" + wire width 2 $0\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:80710.3-80746.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:76118.3-76154.6" + attribute \src "libresoc.v:80858.3-80894.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:76599.3-76635.6" + attribute \src "libresoc.v:80229.3-80265.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:76636.3-76672.6" + attribute \src "libresoc.v:80266.3-80302.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:75933.3-75969.6" + attribute \src "libresoc.v:80673.3-80709.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:76081.3-76117.6" + attribute \src "libresoc.v:80821.3-80857.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:76414.3-76450.6" + attribute \src "libresoc.v:81006.3-81042.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:75785.3-75821.6" - wire width 12 $0\dec30_function_unit[11:0] - attribute \src "libresoc.v:76451.3-76487.6" + attribute \src "libresoc.v:80192.3-80228.6" + wire width 14 $0\dec30_function_unit[13:0] + attribute \src "libresoc.v:81228.3-81264.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:76488.3-76524.6" + attribute \src "libresoc.v:81265.3-81301.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:76525.3-76561.6" + attribute \src "libresoc.v:81302.3-81338.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:76192.3-76228.6" + attribute \src "libresoc.v:80599.3-80635.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:76007.3-76043.6" + attribute \src "libresoc.v:80747.3-80783.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:76044.3-76080.6" + attribute \src "libresoc.v:80784.3-80820.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:76266.3-76302.6" + attribute \src "libresoc.v:80969.3-81005.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:75822.3-75858.6" + attribute \src "libresoc.v:80525.3-80561.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:76340.3-76376.6" + attribute \src "libresoc.v:81080.3-81116.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:76562.3-76598.6" - wire width 2 $0\dec30_out_sel[1:0] - attribute \src "libresoc.v:75896.3-75932.6" + attribute \src "libresoc.v:81339.3-81375.6" + wire width 3 $0\dec30_out_sel[2:0] + attribute \src "libresoc.v:80636.3-80672.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:76229.3-76265.6" + attribute \src "libresoc.v:80932.3-80968.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:76377.3-76413.6" + attribute \src "libresoc.v:81117.3-81153.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:76303.3-76339.6" + attribute \src "libresoc.v:81043.3-81079.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:76155.3-76191.6" + attribute \src "libresoc.v:80895.3-80931.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:75859.3-75895.6" + attribute \src "libresoc.v:80451.3-80487.6" + wire width 3 $0\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:80488.3-80524.6" + wire width 3 $0\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:80303.3-80339.6" + wire width 3 $0\dec30_sv_in1[2:0] + attribute \src "libresoc.v:80340.3-80376.6" + wire width 3 $0\dec30_sv_in2[2:0] + attribute \src "libresoc.v:80377.3-80413.6" + wire width 3 $0\dec30_sv_in3[2:0] + attribute \src "libresoc.v:80414.3-80450.6" + wire width 3 $0\dec30_sv_out[2:0] + attribute \src "libresoc.v:80562.3-80598.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:75528.7-75528.20" + attribute \src "libresoc.v:79854.7-79854.20" wire $0\initial[0:0] - attribute \src "libresoc.v:75970.3-76006.6" + attribute \src "libresoc.v:81154.3-81190.6" + wire width 2 $1\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:81191.3-81227.6" + wire width 2 $1\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:80710.3-80746.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:76118.3-76154.6" + attribute \src "libresoc.v:80858.3-80894.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:76599.3-76635.6" + attribute \src "libresoc.v:80229.3-80265.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:76636.3-76672.6" + attribute \src "libresoc.v:80266.3-80302.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:75933.3-75969.6" + attribute \src "libresoc.v:80673.3-80709.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:76081.3-76117.6" + attribute \src "libresoc.v:80821.3-80857.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:76414.3-76450.6" + attribute \src "libresoc.v:81006.3-81042.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:75785.3-75821.6" - wire width 12 $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:76451.3-76487.6" + attribute \src "libresoc.v:80192.3-80228.6" + wire width 14 $1\dec30_function_unit[13:0] + attribute \src "libresoc.v:81228.3-81264.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:76488.3-76524.6" + attribute \src "libresoc.v:81265.3-81301.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:76525.3-76561.6" + attribute \src "libresoc.v:81302.3-81338.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:76192.3-76228.6" + attribute \src "libresoc.v:80599.3-80635.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:76007.3-76043.6" + attribute \src "libresoc.v:80747.3-80783.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:76044.3-76080.6" + attribute \src "libresoc.v:80784.3-80820.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:76266.3-76302.6" + attribute \src "libresoc.v:80969.3-81005.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:75822.3-75858.6" + attribute \src "libresoc.v:80525.3-80561.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:76340.3-76376.6" + attribute \src "libresoc.v:81080.3-81116.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:76562.3-76598.6" - wire width 2 $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:75896.3-75932.6" + attribute \src "libresoc.v:81339.3-81375.6" + wire width 3 $1\dec30_out_sel[2:0] + attribute \src "libresoc.v:80636.3-80672.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:76229.3-76265.6" + attribute \src "libresoc.v:80932.3-80968.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:76377.3-76413.6" + attribute \src "libresoc.v:81117.3-81153.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:76303.3-76339.6" + attribute \src "libresoc.v:81043.3-81079.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:76155.3-76191.6" + attribute \src "libresoc.v:80895.3-80931.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:75859.3-75895.6" + attribute \src "libresoc.v:80451.3-80487.6" + wire width 3 $1\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:80488.3-80524.6" + wire width 3 $1\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:80303.3-80339.6" + wire width 3 $1\dec30_sv_in1[2:0] + attribute \src "libresoc.v:80340.3-80376.6" + wire width 3 $1\dec30_sv_in2[2:0] + attribute \src "libresoc.v:80377.3-80413.6" + wire width 3 $1\dec30_sv_in3[2:0] + attribute \src "libresoc.v:80414.3-80450.6" + wire width 3 $1\dec30_sv_out[2:0] + attribute \src "libresoc.v:80562.3-80598.6" wire width 2 $1\dec30_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec30_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec30_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 output 4 \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec30_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -122568,24 +128791,26 @@ module \dec30 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec30_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec30_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec30_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -122616,31 +128841,34 @@ module \dec30 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec30_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec30_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -122656,14 +128884,14 @@ module \dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec30_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec30_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -122738,727 +128966,783 @@ module \dec30 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec30_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec30_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec30_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec30_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec30_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec30_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec30_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec30_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec30_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec30_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec30_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec30_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec30_upd - attribute \src "libresoc.v:75528.7-75528.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec30_upd + attribute \src "libresoc.v:79854.7-79854.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 4 \opcode_switch - attribute \src "libresoc.v:75528.7-75528.20" - process $proc$libresoc.v:75528$3696 + attribute \src "libresoc.v:79854.7-79854.20" + process $proc$libresoc.v:79854$3796 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:75785.3-75821.6" - process $proc$libresoc.v:75785$3672 + attribute \src "libresoc.v:80192.3-80228.6" + process $proc$libresoc.v:80192$3764 assign { } { } assign { } { } - assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:75786.5-75786.29" + assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] + attribute \src "libresoc.v:80193.5-80193.29" switch \initial - attribute \src "libresoc.v:75786.9-75786.17" + attribute \src "libresoc.v:80193.9-80193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 case - assign $1\dec30_function_unit[11:0] 12'000000000000 + assign $1\dec30_function_unit[13:0] 14'00000000000000 end sync always - update \dec30_function_unit $0\dec30_function_unit[11:0] + update \dec30_function_unit $0\dec30_function_unit[13:0] end - attribute \src "libresoc.v:75822.3-75858.6" - process $proc$libresoc.v:75822$3673 + attribute \src "libresoc.v:80229.3-80265.6" + process $proc$libresoc.v:80229$3765 assign { } { } assign { } { } - assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:75823.5-75823.29" + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:80230.5-80230.29" switch \initial - attribute \src "libresoc.v:75823.9-75823.17" + attribute \src "libresoc.v:80230.9-80230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 case - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec30_cr_in[2:0] 3'000 end sync always - update \dec30_ldst_len $0\dec30_ldst_len[3:0] + update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:75859.3-75895.6" - process $proc$libresoc.v:75859$3674 + attribute \src "libresoc.v:80266.3-80302.6" + process $proc$libresoc.v:80266$3766 assign { } { } assign { } { } - assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:75860.5-75860.29" + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:80267.5-80267.29" switch \initial - attribute \src "libresoc.v:75860.9-75860.17" + attribute \src "libresoc.v:80267.9-80267.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 case - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'000 end sync always - update \dec30_upd $0\dec30_upd[1:0] + update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "libresoc.v:75896.3-75932.6" - process $proc$libresoc.v:75896$3675 + attribute \src "libresoc.v:80303.3-80339.6" + process $proc$libresoc.v:80303$3767 assign { } { } assign { } { } - assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:75897.5-75897.29" + assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] + attribute \src "libresoc.v:80304.5-80304.29" switch \initial - attribute \src "libresoc.v:75897.9-75897.17" + attribute \src "libresoc.v:80304.9-80304.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec30_sv_in1[2:0] 3'000 case - assign $1\dec30_rc_sel[1:0] 2'00 + assign $1\dec30_sv_in1[2:0] 3'000 end sync always - update \dec30_rc_sel $0\dec30_rc_sel[1:0] + update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end - attribute \src "libresoc.v:75933.3-75969.6" - process $proc$libresoc.v:75933$3676 + attribute \src "libresoc.v:80340.3-80376.6" + process $proc$libresoc.v:80340$3768 assign { } { } assign { } { } - assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:75934.5-75934.29" + assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] + attribute \src "libresoc.v:80341.5-80341.29" switch \initial - attribute \src "libresoc.v:75934.9-75934.17" + attribute \src "libresoc.v:80341.9-80341.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'010 case - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec30_sv_in2[2:0] 3'000 end sync always - update \dec30_cry_in $0\dec30_cry_in[1:0] + update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end - attribute \src "libresoc.v:75970.3-76006.6" - process $proc$libresoc.v:75970$3677 + attribute \src "libresoc.v:80377.3-80413.6" + process $proc$libresoc.v:80377$3769 assign { } { } assign { } { } - assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:75971.5-75971.29" + assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] + attribute \src "libresoc.v:80378.5-80378.29" switch \initial - attribute \src "libresoc.v:75971.9-75971.17" + attribute \src "libresoc.v:80378.9-80378.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 + assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 + assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 + assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 + assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 + assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 + assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 + assign $1\dec30_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 + assign $1\dec30_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010010 + assign $1\dec30_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010011 + assign $1\dec30_sv_in3[2:0] 3'011 case - assign $1\dec30_asmcode[7:0] 8'00000000 + assign $1\dec30_sv_in3[2:0] 3'000 end sync always - update \dec30_asmcode $0\dec30_asmcode[7:0] + update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end - attribute \src "libresoc.v:76007.3-76043.6" - process $proc$libresoc.v:76007$3678 + attribute \src "libresoc.v:80414.3-80450.6" + process $proc$libresoc.v:80414$3770 assign { } { } assign { } { } - assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:76008.5-76008.29" + assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] + attribute \src "libresoc.v:80415.5-80415.29" switch \initial - attribute \src "libresoc.v:76008.9-76008.17" + attribute \src "libresoc.v:80415.9-80415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'001 case - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec30_sv_out[2:0] 3'000 end sync always - update \dec30_inv_a $0\dec30_inv_a[0:0] + update \dec30_sv_out $0\dec30_sv_out[2:0] end - attribute \src "libresoc.v:76044.3-76080.6" - process $proc$libresoc.v:76044$3679 + attribute \src "libresoc.v:80451.3-80487.6" + process $proc$libresoc.v:80451$3771 assign { } { } assign { } { } - assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:76045.5-76045.29" + assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:80452.5-80452.29" switch \initial - attribute \src "libresoc.v:76045.9-76045.17" + attribute \src "libresoc.v:80452.9-80452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 case - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec30_sv_cr_in[2:0] 3'000 end sync always - update \dec30_inv_out $0\dec30_inv_out[0:0] + update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end - attribute \src "libresoc.v:76081.3-76117.6" - process $proc$libresoc.v:76081$3680 + attribute \src "libresoc.v:80488.3-80524.6" + process $proc$libresoc.v:80488$3772 assign { } { } assign { } { } - assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:76082.5-76082.29" + assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:80489.5-80489.29" switch \initial - attribute \src "libresoc.v:76082.9-76082.17" + attribute \src "libresoc.v:80489.9-80489.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'001 case - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec30_sv_cr_out[2:0] 3'000 end sync always - update \dec30_cry_out $0\dec30_cry_out[0:0] + update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end - attribute \src "libresoc.v:76118.3-76154.6" - process $proc$libresoc.v:76118$3681 + attribute \src "libresoc.v:80525.3-80561.6" + process $proc$libresoc.v:80525$3773 assign { } { } assign { } { } - assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:76119.5-76119.29" + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:80526.5-80526.29" switch \initial - attribute \src "libresoc.v:76119.9-76119.17" + attribute \src "libresoc.v:80526.9-80526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 case - assign $1\dec30_br[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 end sync always - update \dec30_br $0\dec30_br[0:0] + update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:76155.3-76191.6" - process $proc$libresoc.v:76155$3682 + attribute \src "libresoc.v:80562.3-80598.6" + process $proc$libresoc.v:80562$3774 assign { } { } assign { } { } - assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:76156.5-76156.29" + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:80563.5-80563.29" switch \initial - attribute \src "libresoc.v:76156.9-76156.17" + attribute \src "libresoc.v:80563.9-80563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 case - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 end sync always - update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:76192.3-76228.6" - process $proc$libresoc.v:76192$3683 + attribute \src "libresoc.v:80599.3-80635.6" + process $proc$libresoc.v:80599$3775 assign { } { } assign { } { } assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:76193.5-76193.29" + attribute \src "libresoc.v:80600.5-80600.29" switch \initial - attribute \src "libresoc.v:76193.9-76193.17" + attribute \src "libresoc.v:80600.9-80600.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -123506,823 +129790,1339 @@ module \dec30 sync always update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:76229.3-76265.6" - process $proc$libresoc.v:76229$3684 + attribute \src "libresoc.v:80636.3-80672.6" + process $proc$libresoc.v:80636$3776 assign { } { } assign { } { } - assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:76230.5-76230.29" + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:80637.5-80637.29" switch \initial - attribute \src "libresoc.v:76230.9-76230.17" + attribute \src "libresoc.v:80637.9-80637.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 case - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'00 end sync always - update \dec30_rsrv $0\dec30_rsrv[0:0] + update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:76266.3-76302.6" - process $proc$libresoc.v:76266$3685 + attribute \src "libresoc.v:80673.3-80709.6" + process $proc$libresoc.v:80673$3777 assign { } { } assign { } { } - assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:76267.5-76267.29" + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:80674.5-80674.29" switch \initial - attribute \src "libresoc.v:76267.9-76267.17" + attribute \src "libresoc.v:80674.9-80674.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 case - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_cry_in[1:0] 2'00 end sync always - update \dec30_is_32b $0\dec30_is_32b[0:0] + update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:76303.3-76339.6" - process $proc$libresoc.v:76303$3686 + attribute \src "libresoc.v:80710.3-80746.6" + process $proc$libresoc.v:80710$3778 assign { } { } assign { } { } - assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:76304.5-76304.29" + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:80711.5-80711.29" switch \initial - attribute \src "libresoc.v:76304.9-76304.17" + attribute \src "libresoc.v:80711.9-80711.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010100 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010100 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010101 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010101 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010110 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010110 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010111 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010111 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010010 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'10010011 case - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec30_asmcode[7:0] 8'00000000 end sync always - update \dec30_sgn $0\dec30_sgn[0:0] + update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:76340.3-76376.6" - process $proc$libresoc.v:76340$3687 + attribute \src "libresoc.v:80747.3-80783.6" + process $proc$libresoc.v:80747$3779 assign { } { } assign { } { } - assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:76341.5-76341.29" + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:80748.5-80748.29" switch \initial - attribute \src "libresoc.v:76341.9-76341.17" + attribute \src "libresoc.v:80748.9-80748.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 case - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec30_inv_a[0:0] 1'0 end sync always - update \dec30_lk $0\dec30_lk[0:0] + update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:76377.3-76413.6" - process $proc$libresoc.v:76377$3688 + attribute \src "libresoc.v:80784.3-80820.6" + process $proc$libresoc.v:80784$3780 assign { } { } assign { } { } - assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:76378.5-76378.29" + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:80785.5-80785.29" switch \initial - attribute \src "libresoc.v:76378.9-76378.17" + attribute \src "libresoc.v:80785.9-80785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 case - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec30_inv_out[0:0] 1'0 end sync always - update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:76414.3-76450.6" - process $proc$libresoc.v:76414$3689 + attribute \src "libresoc.v:80821.3-80857.6" + process $proc$libresoc.v:80821$3781 assign { } { } assign { } { } - assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:76415.5-76415.29" + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:80822.5-80822.29" switch \initial - attribute \src "libresoc.v:76415.9-76415.17" + attribute \src "libresoc.v:80822.9-80822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_form[4:0] 5'10101 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_form[4:0] 5'10101 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_cry_out[0:0] 1'0 case - assign $1\dec30_form[4:0] 5'00000 + assign $1\dec30_cry_out[0:0] 1'0 end sync always - update \dec30_form $0\dec30_form[4:0] + update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:76451.3-76487.6" - process $proc$libresoc.v:76451$3690 + attribute \src "libresoc.v:80858.3-80894.6" + process $proc$libresoc.v:80858$3782 assign { } { } assign { } { } - assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:76452.5-76452.29" + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:80859.5-80859.29" switch \initial - attribute \src "libresoc.v:76452.9-76452.17" + attribute \src "libresoc.v:80859.9-80859.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 case - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec30_br[0:0] 1'0 end sync always - update \dec30_in1_sel $0\dec30_in1_sel[2:0] + update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:76488.3-76524.6" - process $proc$libresoc.v:76488$3691 + attribute \src "libresoc.v:80895.3-80931.6" + process $proc$libresoc.v:80895$3783 assign { } { } assign { } { } - assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:76489.5-76489.29" + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:80896.5-80896.29" switch \initial - attribute \src "libresoc.v:76489.9-76489.17" + attribute \src "libresoc.v:80896.9-80896.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 + assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 + assign $1\dec30_sgn_ext[0:0] 1'0 case - assign $1\dec30_in2_sel[3:0] 4'0000 + assign $1\dec30_sgn_ext[0:0] 1'0 end sync always - update \dec30_in2_sel $0\dec30_in2_sel[3:0] + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:76525.3-76561.6" - process $proc$libresoc.v:76525$3692 + attribute \src "libresoc.v:80932.3-80968.6" + process $proc$libresoc.v:80932$3784 assign { } { } assign { } { } - assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:76526.5-76526.29" + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:80933.5-80933.29" switch \initial - attribute \src "libresoc.v:76526.9-76526.17" + attribute \src "libresoc.v:80933.9-80933.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec30_rsrv[0:0] 1'0 case - assign $1\dec30_in3_sel[1:0] 2'00 + assign $1\dec30_rsrv[0:0] 1'0 end sync always - update \dec30_in3_sel $0\dec30_in3_sel[1:0] + update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:76562.3-76598.6" - process $proc$libresoc.v:76562$3693 + attribute \src "libresoc.v:80969.3-81005.6" + process $proc$libresoc.v:80969$3785 assign { } { } assign { } { } - assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:76563.5-76563.29" + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:80970.5-80970.29" switch \initial - attribute \src "libresoc.v:76563.9-76563.17" + attribute \src "libresoc.v:80970.9-80970.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_is_32b[0:0] 1'0 case - assign $1\dec30_out_sel[1:0] 2'00 + assign $1\dec30_is_32b[0:0] 1'0 end sync always - update \dec30_out_sel $0\dec30_out_sel[1:0] + update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:76599.3-76635.6" - process $proc$libresoc.v:76599$3694 + attribute \src "libresoc.v:81006.3-81042.6" + process $proc$libresoc.v:81006$3786 assign { } { } assign { } { } - assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:76600.5-76600.29" + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:81007.5-81007.29" switch \initial - attribute \src "libresoc.v:76600.9-76600.17" + attribute \src "libresoc.v:81007.9-81007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10101 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10101 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'10100 case - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec30_form[4:0] 5'00000 end sync always - update \dec30_cr_in $0\dec30_cr_in[2:0] + update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:76636.3-76672.6" - process $proc$libresoc.v:76636$3695 + attribute \src "libresoc.v:81043.3-81079.6" + process $proc$libresoc.v:81043$3787 assign { } { } assign { } { } - assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:76637.5-76637.29" + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:81044.5-81044.29" switch \initial - attribute \src "libresoc.v:76637.9-76637.17" + attribute \src "libresoc.v:81044.9-81044.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec30_sgn[0:0] 1'0 case - assign $1\dec30_cr_out[2:0] 3'000 + assign $1\dec30_sgn[0:0] 1'0 end sync always - update \dec30_cr_out $0\dec30_cr_out[2:0] + update \dec30_sgn $0\dec30_sgn[0:0] + end + attribute \src "libresoc.v:81080.3-81116.6" + process $proc$libresoc.v:81080$3788 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:81081.5-81081.29" + switch \initial + attribute \src "libresoc.v:81081.9-81081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] + end + attribute \src "libresoc.v:81117.3-81153.6" + process $proc$libresoc.v:81117$3789 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:81118.5-81118.29" + switch \initial + attribute \src "libresoc.v:81118.9-81118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + end + attribute \src "libresoc.v:81154.3-81190.6" + process $proc$libresoc.v:81154$3790 + assign { } { } + assign { } { } + assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:81155.5-81155.29" + switch \initial + attribute \src "libresoc.v:81155.9-81155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + case + assign $1\dec30_SV_Etype[1:0] 2'00 + end + sync always + update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] + end + attribute \src "libresoc.v:81191.3-81227.6" + process $proc$libresoc.v:81191$3791 + assign { } { } + assign { } { } + assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:81192.5-81192.29" + switch \initial + attribute \src "libresoc.v:81192.9-81192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + case + assign $1\dec30_SV_Ptype[1:0] 2'00 + end + sync always + update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] + end + attribute \src "libresoc.v:81228.3-81264.6" + process $proc$libresoc.v:81228$3792 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:81229.5-81229.29" + switch \initial + attribute \src "libresoc.v:81229.9-81229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] + end + attribute \src "libresoc.v:81265.3-81301.6" + process $proc$libresoc.v:81265$3793 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:81266.5-81266.29" + switch \initial + attribute \src "libresoc.v:81266.9-81266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:81302.3-81338.6" + process $proc$libresoc.v:81302$3794 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:81303.5-81303.29" + switch \initial + attribute \src "libresoc.v:81303.9-81303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] + end + attribute \src "libresoc.v:81339.3-81375.6" + process $proc$libresoc.v:81339$3795 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] + attribute \src "libresoc.v:81340.5-81340.29" + switch \initial + attribute \src "libresoc.v:81340.9-81340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + case + assign $1\dec30_out_sel[2:0] 3'000 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[2:0] end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:76678.1-83048.10" +attribute \src "libresoc.v:81381.1-89778.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:81747.3-81807.6" + attribute \src "libresoc.v:88050.3-88110.6" + wire width 2 $0\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:88111.3-88171.6" + wire width 2 $0\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:87989.3-88049.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:82601.3-82661.6" + attribute \src "libresoc.v:89331.3-89391.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:82052.3-82112.6" + attribute \src "libresoc.v:88416.3-88476.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:82113.3-82173.6" + attribute \src "libresoc.v:88477.3-88537.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:82357.3-82417.6" + attribute \src "libresoc.v:89087.3-89147.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:82540.3-82600.6" + attribute \src "libresoc.v:89270.3-89330.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:81686.3-81746.6" + attribute \src "libresoc.v:87928.3-87988.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:81564.3-81624.6" - wire width 12 $0\dec31_function_unit[11:0] - attribute \src "libresoc.v:81808.3-81868.6" + attribute \src "libresoc.v:87806.3-87866.6" + wire width 14 $0\dec31_function_unit[13:0] + attribute \src "libresoc.v:88172.3-88232.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:81869.3-81929.6" + attribute \src "libresoc.v:88233.3-88293.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:81930.3-81990.6" + attribute \src "libresoc.v:88294.3-88354.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:81625.3-81685.6" + attribute \src "libresoc.v:87867.3-87927.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:82418.3-82478.6" + attribute \src "libresoc.v:89148.3-89208.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:82479.3-82539.6" + attribute \src "libresoc.v:89209.3-89269.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:82784.3-82844.6" + attribute \src "libresoc.v:89514.3-89574.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:82174.3-82234.6" + attribute \src "libresoc.v:88904.3-88964.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:82906.3-82966.6" + attribute \src "libresoc.v:89636.3-89696.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:81991.3-82051.6" - wire width 2 $0\dec31_out_sel[1:0] - attribute \src "libresoc.v:82296.3-82356.6" + attribute \src "libresoc.v:88355.3-88415.6" + wire width 3 $0\dec31_out_sel[2:0] + attribute \src "libresoc.v:89026.3-89086.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:82723.3-82783.6" + attribute \src "libresoc.v:89453.3-89513.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:82967.3-83027.6" + attribute \src "libresoc.v:89697.3-89757.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:82845.3-82905.6" + attribute \src "libresoc.v:89575.3-89635.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:82662.3-82722.6" + attribute \src "libresoc.v:89392.3-89452.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:82235.3-82295.6" + attribute \src "libresoc.v:88782.3-88842.6" + wire width 3 $0\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:88843.3-88903.6" + wire width 3 $0\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:88538.3-88598.6" + wire width 3 $0\dec31_sv_in1[2:0] + attribute \src "libresoc.v:88599.3-88659.6" + wire width 3 $0\dec31_sv_in2[2:0] + attribute \src "libresoc.v:88660.3-88720.6" + wire width 3 $0\dec31_sv_in3[2:0] + attribute \src "libresoc.v:88721.3-88781.6" + wire width 3 $0\dec31_sv_out[2:0] + attribute \src "libresoc.v:88965.3-89025.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:76679.7-76679.20" + attribute \src "libresoc.v:81382.7-81382.20" wire $0\initial[0:0] - attribute \src "libresoc.v:81747.3-81807.6" + attribute \src "libresoc.v:88050.3-88110.6" + wire width 2 $1\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:88111.3-88171.6" + wire width 2 $1\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:87989.3-88049.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:82601.3-82661.6" + attribute \src "libresoc.v:89331.3-89391.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:82052.3-82112.6" + attribute \src "libresoc.v:88416.3-88476.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:82113.3-82173.6" + attribute \src "libresoc.v:88477.3-88537.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:82357.3-82417.6" + attribute \src "libresoc.v:89087.3-89147.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:82540.3-82600.6" + attribute \src "libresoc.v:89270.3-89330.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:81686.3-81746.6" + attribute \src "libresoc.v:87928.3-87988.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:81564.3-81624.6" - wire width 12 $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:81808.3-81868.6" + attribute \src "libresoc.v:87806.3-87866.6" + wire width 14 $1\dec31_function_unit[13:0] + attribute \src "libresoc.v:88172.3-88232.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:81869.3-81929.6" + attribute \src "libresoc.v:88233.3-88293.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:81930.3-81990.6" + attribute \src "libresoc.v:88294.3-88354.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:81625.3-81685.6" + attribute \src "libresoc.v:87867.3-87927.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:82418.3-82478.6" + attribute \src "libresoc.v:89148.3-89208.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:82479.3-82539.6" + attribute \src "libresoc.v:89209.3-89269.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:82784.3-82844.6" + attribute \src "libresoc.v:89514.3-89574.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:82174.3-82234.6" + attribute \src "libresoc.v:88904.3-88964.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:82906.3-82966.6" + attribute \src "libresoc.v:89636.3-89696.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:81991.3-82051.6" - wire width 2 $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:82296.3-82356.6" + attribute \src "libresoc.v:88355.3-88415.6" + wire width 3 $1\dec31_out_sel[2:0] + attribute \src "libresoc.v:89026.3-89086.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:82723.3-82783.6" + attribute \src "libresoc.v:89453.3-89513.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:82967.3-83027.6" + attribute \src "libresoc.v:89697.3-89757.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:82845.3-82905.6" + attribute \src "libresoc.v:89575.3-89635.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:82662.3-82722.6" + attribute \src "libresoc.v:89392.3-89452.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:82235.3-82295.6" + attribute \src "libresoc.v:88782.3-88842.6" + wire width 3 $1\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:88843.3-88903.6" + wire width 3 $1\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:88538.3-88598.6" + wire width 3 $1\dec31_sv_in1[2:0] + attribute \src "libresoc.v:88599.3-88659.6" + wire width 3 $1\dec31_sv_in2[2:0] + attribute \src "libresoc.v:88660.3-88720.6" + wire width 3 $1\dec31_sv_in3[2:0] + attribute \src "libresoc.v:88721.3-88781.6" + wire width 3 $1\dec31_sv_out[2:0] + attribute \src "libresoc.v:88965.3-89025.6" wire width 2 $1\dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 output 4 \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -124331,27 +131131,41 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_cry_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124361,7 +131175,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124369,15 +131184,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -124409,30 +131225,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124449,13 +131268,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124531,13 +131350,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -124545,43 +131365,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub0_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124591,7 +131478,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124599,15 +131487,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -124639,30 +131528,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124679,13 +131571,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124761,13 +131653,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -124775,43 +131668,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub10_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124821,7 +131781,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124829,15 +131790,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -124869,30 +131831,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub11_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124909,13 +131874,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124991,13 +131956,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125005,43 +131971,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub11_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125051,7 +132084,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125059,15 +132093,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -125099,30 +132134,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -125139,13 +132177,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125221,13 +132259,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125235,43 +132274,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub15_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125281,7 +132387,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125289,15 +132396,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -125329,30 +132437,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -125369,13 +132480,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125451,13 +132562,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125465,43 +132577,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub16_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125511,7 +132690,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125519,15 +132699,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -125559,30 +132740,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub18_dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -125599,13 +132783,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125681,13 +132865,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125695,43 +132880,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub18_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125741,7 +132993,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125749,15 +133002,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -125789,30 +133043,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub19_dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -125829,13 +133086,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125911,13 +133168,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125925,43 +133183,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub19_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125971,7 +133296,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125979,15 +133305,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126019,30 +133346,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub20_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126059,13 +133389,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -126141,13 +133471,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -126155,43 +133486,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub20_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -126201,7 +133599,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -126209,15 +133608,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126249,30 +133649,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub21_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126289,13 +133692,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -126371,13 +133774,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -126385,43 +133789,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -126431,7 +133902,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -126439,15 +133911,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126479,30 +133952,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub22_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126519,13 +133995,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -126601,13 +134077,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -126615,43 +134092,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -126661,7 +134205,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -126669,15 +134214,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126709,30 +134255,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub23_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126749,13 +134298,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -126831,13 +134380,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -126845,43 +134395,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub23_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -126891,7 +134508,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -126899,15 +134517,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126939,30 +134558,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub24_dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126979,13 +134601,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -127061,13 +134683,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -127075,43 +134698,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub24_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -127121,7 +134811,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -127129,15 +134820,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -127169,30 +134861,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub26_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -127209,13 +134904,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -127291,13 +134986,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -127305,43 +135001,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub26_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -127351,7 +135114,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -127359,15 +135123,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -127399,30 +135164,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub27_dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -127439,13 +135207,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -127521,13 +135289,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -127535,43 +135304,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub27_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -127581,7 +135417,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -127589,15 +135426,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -127629,30 +135467,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub28_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -127669,13 +135510,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -127751,13 +135592,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -127765,43 +135607,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub28_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -127811,7 +135720,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -127819,15 +135729,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -127859,30 +135770,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub4_dec31_dec_sub4_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub4_dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -127899,13 +135813,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -127981,13 +135895,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -127995,43 +135910,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub4_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -128041,7 +136023,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -128049,15 +136032,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -128089,30 +136073,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub8_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -128129,13 +136116,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -128211,13 +136198,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -128225,43 +136213,110 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub8_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -128271,7 +136326,8 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -128279,15 +136335,16 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -128319,30 +136376,33 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub9_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -128359,13 +136419,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -128441,13 +136501,14 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -128455,39 +136516,94 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec31_dec_sub9_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -128519,31 +136635,34 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -128559,14 +136678,14 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -128641,63 +136760,121 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_upd - attribute \src "libresoc.v:76679.7-76679.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_upd + attribute \src "libresoc.v:81382.7-81382.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:81078.18-81104.4" + attribute \src "libresoc.v:87176.18-87210.4" cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in @@ -128721,12 +136898,20 @@ module \dec31 connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_sv_cr_in \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in + connect \dec31_dec_sub0_sv_cr_out \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out + connect \dec31_dec_sub0_sv_in1 \dec31_dec_sub0_dec31_dec_sub0_sv_in1 + connect \dec31_dec_sub0_sv_in2 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 + connect \dec31_dec_sub0_sv_in3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 + connect \dec31_dec_sub0_sv_out \dec31_dec_sub0_dec31_dec_sub0_sv_out connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81105.19-81131.4" + attribute \src "libresoc.v:87211.19-87245.4" cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype + connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in @@ -128750,12 +136935,20 @@ module \dec31 connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_sv_cr_in \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in + connect \dec31_dec_sub10_sv_cr_out \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out + connect \dec31_dec_sub10_sv_in1 \dec31_dec_sub10_dec31_dec_sub10_sv_in1 + connect \dec31_dec_sub10_sv_in2 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 + connect \dec31_dec_sub10_sv_in3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 + connect \dec31_dec_sub10_sv_out \dec31_dec_sub10_dec31_dec_sub10_sv_out connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81132.19-81158.4" + attribute \src "libresoc.v:87246.19-87280.4" cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype + connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in @@ -128779,12 +136972,20 @@ module \dec31 connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_sv_cr_in \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in + connect \dec31_dec_sub11_sv_cr_out \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out + connect \dec31_dec_sub11_sv_in1 \dec31_dec_sub11_dec31_dec_sub11_sv_in1 + connect \dec31_dec_sub11_sv_in2 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 + connect \dec31_dec_sub11_sv_in3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 + connect \dec31_dec_sub11_sv_out \dec31_dec_sub11_dec31_dec_sub11_sv_out connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81159.19-81185.4" + attribute \src "libresoc.v:87281.19-87315.4" cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype + connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in @@ -128808,12 +137009,20 @@ module \dec31 connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_sv_cr_in \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in + connect \dec31_dec_sub15_sv_cr_out \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out + connect \dec31_dec_sub15_sv_in1 \dec31_dec_sub15_dec31_dec_sub15_sv_in1 + connect \dec31_dec_sub15_sv_in2 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 + connect \dec31_dec_sub15_sv_in3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 + connect \dec31_dec_sub15_sv_out \dec31_dec_sub15_dec31_dec_sub15_sv_out connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81186.19-81212.4" + attribute \src "libresoc.v:87316.19-87350.4" cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype + connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in @@ -128837,12 +137046,20 @@ module \dec31 connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_sv_cr_in \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in + connect \dec31_dec_sub16_sv_cr_out \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out + connect \dec31_dec_sub16_sv_in1 \dec31_dec_sub16_dec31_dec_sub16_sv_in1 + connect \dec31_dec_sub16_sv_in2 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 + connect \dec31_dec_sub16_sv_in3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 + connect \dec31_dec_sub16_sv_out \dec31_dec_sub16_dec31_dec_sub16_sv_out connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81213.19-81239.4" + attribute \src "libresoc.v:87351.19-87385.4" cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype + connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in @@ -128866,12 +137083,20 @@ module \dec31 connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_sv_cr_in \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in + connect \dec31_dec_sub18_sv_cr_out \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out + connect \dec31_dec_sub18_sv_in1 \dec31_dec_sub18_dec31_dec_sub18_sv_in1 + connect \dec31_dec_sub18_sv_in2 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 + connect \dec31_dec_sub18_sv_in3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 + connect \dec31_dec_sub18_sv_out \dec31_dec_sub18_dec31_dec_sub18_sv_out connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81240.19-81266.4" + attribute \src "libresoc.v:87386.19-87420.4" cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype + connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in @@ -128895,12 +137120,20 @@ module \dec31 connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_sv_cr_in \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in + connect \dec31_dec_sub19_sv_cr_out \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out + connect \dec31_dec_sub19_sv_in1 \dec31_dec_sub19_dec31_dec_sub19_sv_in1 + connect \dec31_dec_sub19_sv_in2 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 + connect \dec31_dec_sub19_sv_in3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 + connect \dec31_dec_sub19_sv_out \dec31_dec_sub19_dec31_dec_sub19_sv_out connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81267.19-81293.4" + attribute \src "libresoc.v:87421.19-87455.4" cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype + connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in @@ -128924,12 +137157,20 @@ module \dec31 connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_sv_cr_in \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in + connect \dec31_dec_sub20_sv_cr_out \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out + connect \dec31_dec_sub20_sv_in1 \dec31_dec_sub20_dec31_dec_sub20_sv_in1 + connect \dec31_dec_sub20_sv_in2 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 + connect \dec31_dec_sub20_sv_in3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 + connect \dec31_dec_sub20_sv_out \dec31_dec_sub20_dec31_dec_sub20_sv_out connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81294.19-81320.4" + attribute \src "libresoc.v:87456.19-87490.4" cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype + connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in @@ -128953,12 +137194,20 @@ module \dec31 connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_sv_cr_in \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in + connect \dec31_dec_sub21_sv_cr_out \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out + connect \dec31_dec_sub21_sv_in1 \dec31_dec_sub21_dec31_dec_sub21_sv_in1 + connect \dec31_dec_sub21_sv_in2 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 + connect \dec31_dec_sub21_sv_in3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 + connect \dec31_dec_sub21_sv_out \dec31_dec_sub21_dec31_dec_sub21_sv_out connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81321.19-81347.4" + attribute \src "libresoc.v:87491.19-87525.4" cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype + connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in @@ -128982,12 +137231,20 @@ module \dec31 connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_sv_cr_in \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in + connect \dec31_dec_sub22_sv_cr_out \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out + connect \dec31_dec_sub22_sv_in1 \dec31_dec_sub22_dec31_dec_sub22_sv_in1 + connect \dec31_dec_sub22_sv_in2 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 + connect \dec31_dec_sub22_sv_in3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 + connect \dec31_dec_sub22_sv_out \dec31_dec_sub22_dec31_dec_sub22_sv_out connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81348.19-81374.4" + attribute \src "libresoc.v:87526.19-87560.4" cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype + connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in @@ -129011,12 +137268,20 @@ module \dec31 connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_sv_cr_in \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in + connect \dec31_dec_sub23_sv_cr_out \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out + connect \dec31_dec_sub23_sv_in1 \dec31_dec_sub23_dec31_dec_sub23_sv_in1 + connect \dec31_dec_sub23_sv_in2 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 + connect \dec31_dec_sub23_sv_in3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 + connect \dec31_dec_sub23_sv_out \dec31_dec_sub23_dec31_dec_sub23_sv_out connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81375.19-81401.4" + attribute \src "libresoc.v:87561.19-87595.4" cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype + connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in @@ -129040,12 +137305,20 @@ module \dec31 connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_sv_cr_in \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in + connect \dec31_dec_sub24_sv_cr_out \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out + connect \dec31_dec_sub24_sv_in1 \dec31_dec_sub24_dec31_dec_sub24_sv_in1 + connect \dec31_dec_sub24_sv_in2 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 + connect \dec31_dec_sub24_sv_in3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 + connect \dec31_dec_sub24_sv_out \dec31_dec_sub24_dec31_dec_sub24_sv_out connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81402.19-81428.4" + attribute \src "libresoc.v:87596.19-87630.4" cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype + connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in @@ -129069,12 +137342,20 @@ module \dec31 connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_sv_cr_in \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in + connect \dec31_dec_sub26_sv_cr_out \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out + connect \dec31_dec_sub26_sv_in1 \dec31_dec_sub26_dec31_dec_sub26_sv_in1 + connect \dec31_dec_sub26_sv_in2 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 + connect \dec31_dec_sub26_sv_in3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 + connect \dec31_dec_sub26_sv_out \dec31_dec_sub26_dec31_dec_sub26_sv_out connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81429.19-81455.4" + attribute \src "libresoc.v:87631.19-87665.4" cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype + connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in @@ -129098,12 +137379,20 @@ module \dec31 connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_sv_cr_in \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in + connect \dec31_dec_sub27_sv_cr_out \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out + connect \dec31_dec_sub27_sv_in1 \dec31_dec_sub27_dec31_dec_sub27_sv_in1 + connect \dec31_dec_sub27_sv_in2 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 + connect \dec31_dec_sub27_sv_in3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 + connect \dec31_dec_sub27_sv_out \dec31_dec_sub27_dec31_dec_sub27_sv_out connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81456.19-81482.4" + attribute \src "libresoc.v:87666.19-87700.4" cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype + connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in @@ -129127,12 +137416,20 @@ module \dec31 connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_sv_cr_in \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in + connect \dec31_dec_sub28_sv_cr_out \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out + connect \dec31_dec_sub28_sv_in1 \dec31_dec_sub28_dec31_dec_sub28_sv_in1 + connect \dec31_dec_sub28_sv_in2 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 + connect \dec31_dec_sub28_sv_in3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 + connect \dec31_dec_sub28_sv_out \dec31_dec_sub28_dec31_dec_sub28_sv_out connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81483.18-81509.4" + attribute \src "libresoc.v:87701.18-87735.4" cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype + connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in @@ -129156,12 +137453,20 @@ module \dec31 connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_sv_cr_in \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in + connect \dec31_dec_sub4_sv_cr_out \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out + connect \dec31_dec_sub4_sv_in1 \dec31_dec_sub4_dec31_dec_sub4_sv_in1 + connect \dec31_dec_sub4_sv_in2 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 + connect \dec31_dec_sub4_sv_in3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 + connect \dec31_dec_sub4_sv_out \dec31_dec_sub4_dec31_dec_sub4_sv_out connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81510.18-81536.4" + attribute \src "libresoc.v:87736.18-87770.4" cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype + connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in @@ -129185,12 +137490,20 @@ module \dec31 connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_sv_cr_in \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in + connect \dec31_dec_sub8_sv_cr_out \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out + connect \dec31_dec_sub8_sv_in1 \dec31_dec_sub8_dec31_dec_sub8_sv_in1 + connect \dec31_dec_sub8_sv_in2 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 + connect \dec31_dec_sub8_sv_in3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 + connect \dec31_dec_sub8_sv_out \dec31_dec_sub8_dec31_dec_sub8_sv_out connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:81537.18-81563.4" + attribute \src "libresoc.v:87771.18-87805.4" cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype + connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in @@ -129214,120 +137527,126 @@ module \dec31 connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_sv_cr_in \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in + connect \dec31_dec_sub9_sv_cr_out \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out + connect \dec31_dec_sub9_sv_in1 \dec31_dec_sub9_dec31_dec_sub9_sv_in1 + connect \dec31_dec_sub9_sv_in2 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 + connect \dec31_dec_sub9_sv_in3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 + connect \dec31_dec_sub9_sv_out \dec31_dec_sub9_dec31_dec_sub9_sv_out connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:76679.7-76679.20" - process $proc$libresoc.v:76679$3721 + attribute \src "libresoc.v:81382.7-81382.20" + process $proc$libresoc.v:81382$3829 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:81564.3-81624.6" - process $proc$libresoc.v:81564$3697 + attribute \src "libresoc.v:87806.3-87866.6" + process $proc$libresoc.v:87806$3797 assign { } { } assign { } { } - assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:81565.5-81565.29" + assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] + attribute \src "libresoc.v:87807.5-87807.29" switch \initial - attribute \src "libresoc.v:81565.9-81565.17" + attribute \src "libresoc.v:87807.9-87807.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit case - assign $1\dec31_function_unit[11:0] 12'000000000000 + assign $1\dec31_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_function_unit $0\dec31_function_unit[11:0] + update \dec31_function_unit $0\dec31_function_unit[13:0] end - attribute \src "libresoc.v:81625.3-81685.6" - process $proc$libresoc.v:81625$3698 + attribute \src "libresoc.v:87867.3-87927.6" + process $proc$libresoc.v:87867$3798 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:81626.5-81626.29" + attribute \src "libresoc.v:87868.5-87868.29" switch \initial - attribute \src "libresoc.v:81626.9-81626.17" + attribute \src "libresoc.v:87868.9-87868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129407,18 +137726,18 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:81686.3-81746.6" - process $proc$libresoc.v:81686$3699 + attribute \src "libresoc.v:87928.3-87988.6" + process $proc$libresoc.v:87928$3799 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:81687.5-81687.29" + attribute \src "libresoc.v:87929.5-87929.29" switch \initial - attribute \src "libresoc.v:81687.9-81687.17" + attribute \src "libresoc.v:87929.9-87929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129498,18 +137817,18 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:81747.3-81807.6" - process $proc$libresoc.v:81747$3700 + attribute \src "libresoc.v:87989.3-88049.6" + process $proc$libresoc.v:87989$3800 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:81748.5-81748.29" + attribute \src "libresoc.v:87990.5-87990.29" switch \initial - attribute \src "libresoc.v:81748.9-81748.17" + attribute \src "libresoc.v:87990.9-87990.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129589,18 +137908,200 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:81808.3-81868.6" - process $proc$libresoc.v:81808$3701 + attribute \src "libresoc.v:88050.3-88110.6" + process $proc$libresoc.v:88050$3801 + assign { } { } + assign { } { } + assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:88051.5-88051.29" + switch \initial + attribute \src "libresoc.v:88051.9-88051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub10_dec31_dec_sub10_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub28_dec31_dec_sub28_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub26_dec31_dec_sub26_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub19_dec31_dec_sub19_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub22_dec31_dec_sub22_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub9_dec31_dec_sub9_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub11_dec31_dec_sub11_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub27_dec31_dec_sub27_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub15_dec31_dec_sub15_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub20_dec31_dec_sub20_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub21_dec31_dec_sub21_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub23_dec31_dec_sub23_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub16_dec31_dec_sub16_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub18_dec31_dec_sub18_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub8_dec31_dec_sub8_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub24_dec31_dec_sub24_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub4_dec31_dec_sub4_SV_Etype + case + assign $1\dec31_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] + end + attribute \src "libresoc.v:88111.3-88171.6" + process $proc$libresoc.v:88111$3802 + assign { } { } + assign { } { } + assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:88112.5-88112.29" + switch \initial + attribute \src "libresoc.v:88112.9-88112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype + case + assign $1\dec31_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] + end + attribute \src "libresoc.v:88172.3-88232.6" + process $proc$libresoc.v:88172$3803 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:81809.5-81809.29" + attribute \src "libresoc.v:88173.5-88173.29" switch \initial - attribute \src "libresoc.v:81809.9-81809.17" + attribute \src "libresoc.v:88173.9-88173.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129680,18 +138181,18 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:81869.3-81929.6" - process $proc$libresoc.v:81869$3702 + attribute \src "libresoc.v:88233.3-88293.6" + process $proc$libresoc.v:88233$3804 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:81870.5-81870.29" + attribute \src "libresoc.v:88234.5-88234.29" switch \initial - attribute \src "libresoc.v:81870.9-81870.17" + attribute \src "libresoc.v:88234.9-88234.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129771,18 +138272,18 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:81930.3-81990.6" - process $proc$libresoc.v:81930$3703 + attribute \src "libresoc.v:88294.3-88354.6" + process $proc$libresoc.v:88294$3805 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:81931.5-81931.29" + attribute \src "libresoc.v:88295.5-88295.29" switch \initial - attribute \src "libresoc.v:81931.9-81931.17" + attribute \src "libresoc.v:88295.9-88295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129862,109 +138363,109 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:81991.3-82051.6" - process $proc$libresoc.v:81991$3704 + attribute \src "libresoc.v:88355.3-88415.6" + process $proc$libresoc.v:88355$3806 assign { } { } assign { } { } - assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:81992.5-81992.29" + assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] + attribute \src "libresoc.v:88356.5-88356.29" switch \initial - attribute \src "libresoc.v:81992.9-81992.17" + attribute \src "libresoc.v:88356.9-88356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel case - assign $1\dec31_out_sel[1:0] 2'00 + assign $1\dec31_out_sel[2:0] 3'000 end sync always - update \dec31_out_sel $0\dec31_out_sel[1:0] + update \dec31_out_sel $0\dec31_out_sel[2:0] end - attribute \src "libresoc.v:82052.3-82112.6" - process $proc$libresoc.v:82052$3705 + attribute \src "libresoc.v:88416.3-88476.6" + process $proc$libresoc.v:88416$3807 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:82053.5-82053.29" + attribute \src "libresoc.v:88417.5-88417.29" switch \initial - attribute \src "libresoc.v:82053.9-82053.17" + attribute \src "libresoc.v:88417.9-88417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130044,18 +138545,18 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:82113.3-82173.6" - process $proc$libresoc.v:82113$3706 + attribute \src "libresoc.v:88477.3-88537.6" + process $proc$libresoc.v:88477$3808 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:82114.5-82114.29" + attribute \src "libresoc.v:88478.5-88478.29" switch \initial - attribute \src "libresoc.v:82114.9-82114.17" + attribute \src "libresoc.v:88478.9-88478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130135,18 +138636,564 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:82174.3-82234.6" - process $proc$libresoc.v:82174$3707 + attribute \src "libresoc.v:88538.3-88598.6" + process $proc$libresoc.v:88538$3809 + assign { } { } + assign { } { } + assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] + attribute \src "libresoc.v:88539.5-88539.29" + switch \initial + attribute \src "libresoc.v:88539.9-88539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in1 + case + assign $1\dec31_sv_in1[2:0] 3'000 + end + sync always + update \dec31_sv_in1 $0\dec31_sv_in1[2:0] + end + attribute \src "libresoc.v:88599.3-88659.6" + process $proc$libresoc.v:88599$3810 + assign { } { } + assign { } { } + assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] + attribute \src "libresoc.v:88600.5-88600.29" + switch \initial + attribute \src "libresoc.v:88600.9-88600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in2 + case + assign $1\dec31_sv_in2[2:0] 3'000 + end + sync always + update \dec31_sv_in2 $0\dec31_sv_in2[2:0] + end + attribute \src "libresoc.v:88660.3-88720.6" + process $proc$libresoc.v:88660$3811 + assign { } { } + assign { } { } + assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] + attribute \src "libresoc.v:88661.5-88661.29" + switch \initial + attribute \src "libresoc.v:88661.9-88661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in3 + case + assign $1\dec31_sv_in3[2:0] 3'000 + end + sync always + update \dec31_sv_in3 $0\dec31_sv_in3[2:0] + end + attribute \src "libresoc.v:88721.3-88781.6" + process $proc$libresoc.v:88721$3812 + assign { } { } + assign { } { } + assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] + attribute \src "libresoc.v:88722.5-88722.29" + switch \initial + attribute \src "libresoc.v:88722.9-88722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_out + case + assign $1\dec31_sv_out[2:0] 3'000 + end + sync always + update \dec31_sv_out $0\dec31_sv_out[2:0] + end + attribute \src "libresoc.v:88782.3-88842.6" + process $proc$libresoc.v:88782$3813 + assign { } { } + assign { } { } + assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:88783.5-88783.29" + switch \initial + attribute \src "libresoc.v:88783.9-88783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in + case + assign $1\dec31_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] + end + attribute \src "libresoc.v:88843.3-88903.6" + process $proc$libresoc.v:88843$3814 + assign { } { } + assign { } { } + assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:88844.5-88844.29" + switch \initial + attribute \src "libresoc.v:88844.9-88844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out + case + assign $1\dec31_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] + end + attribute \src "libresoc.v:88904.3-88964.6" + process $proc$libresoc.v:88904$3815 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:82175.5-82175.29" + attribute \src "libresoc.v:88905.5-88905.29" switch \initial - attribute \src "libresoc.v:82175.9-82175.17" + attribute \src "libresoc.v:88905.9-88905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130226,18 +139273,18 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:82235.3-82295.6" - process $proc$libresoc.v:82235$3708 + attribute \src "libresoc.v:88965.3-89025.6" + process $proc$libresoc.v:88965$3816 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:82236.5-82236.29" + attribute \src "libresoc.v:88966.5-88966.29" switch \initial - attribute \src "libresoc.v:82236.9-82236.17" + attribute \src "libresoc.v:88966.9-88966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130317,18 +139364,18 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:82296.3-82356.6" - process $proc$libresoc.v:82296$3709 + attribute \src "libresoc.v:89026.3-89086.6" + process $proc$libresoc.v:89026$3817 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:82297.5-82297.29" + attribute \src "libresoc.v:89027.5-89027.29" switch \initial - attribute \src "libresoc.v:82297.9-82297.17" + attribute \src "libresoc.v:89027.9-89027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130408,18 +139455,18 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:82357.3-82417.6" - process $proc$libresoc.v:82357$3710 + attribute \src "libresoc.v:89087.3-89147.6" + process $proc$libresoc.v:89087$3818 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:82358.5-82358.29" + attribute \src "libresoc.v:89088.5-89088.29" switch \initial - attribute \src "libresoc.v:82358.9-82358.17" + attribute \src "libresoc.v:89088.9-89088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130499,18 +139546,18 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:82418.3-82478.6" - process $proc$libresoc.v:82418$3711 + attribute \src "libresoc.v:89148.3-89208.6" + process $proc$libresoc.v:89148$3819 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:82419.5-82419.29" + attribute \src "libresoc.v:89149.5-89149.29" switch \initial - attribute \src "libresoc.v:82419.9-82419.17" + attribute \src "libresoc.v:89149.9-89149.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130590,18 +139637,18 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:82479.3-82539.6" - process $proc$libresoc.v:82479$3712 + attribute \src "libresoc.v:89209.3-89269.6" + process $proc$libresoc.v:89209$3820 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:82480.5-82480.29" + attribute \src "libresoc.v:89210.5-89210.29" switch \initial - attribute \src "libresoc.v:82480.9-82480.17" + attribute \src "libresoc.v:89210.9-89210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130681,18 +139728,18 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:82540.3-82600.6" - process $proc$libresoc.v:82540$3713 + attribute \src "libresoc.v:89270.3-89330.6" + process $proc$libresoc.v:89270$3821 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:82541.5-82541.29" + attribute \src "libresoc.v:89271.5-89271.29" switch \initial - attribute \src "libresoc.v:82541.9-82541.17" + attribute \src "libresoc.v:89271.9-89271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130772,18 +139819,18 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:82601.3-82661.6" - process $proc$libresoc.v:82601$3714 + attribute \src "libresoc.v:89331.3-89391.6" + process $proc$libresoc.v:89331$3822 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:82602.5-82602.29" + attribute \src "libresoc.v:89332.5-89332.29" switch \initial - attribute \src "libresoc.v:82602.9-82602.17" + attribute \src "libresoc.v:89332.9-89332.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130863,18 +139910,18 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:82662.3-82722.6" - process $proc$libresoc.v:82662$3715 + attribute \src "libresoc.v:89392.3-89452.6" + process $proc$libresoc.v:89392$3823 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:82663.5-82663.29" + attribute \src "libresoc.v:89393.5-89393.29" switch \initial - attribute \src "libresoc.v:82663.9-82663.17" + attribute \src "libresoc.v:89393.9-89393.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -130954,18 +140001,18 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:82723.3-82783.6" - process $proc$libresoc.v:82723$3716 + attribute \src "libresoc.v:89453.3-89513.6" + process $proc$libresoc.v:89453$3824 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:82724.5-82724.29" + attribute \src "libresoc.v:89454.5-89454.29" switch \initial - attribute \src "libresoc.v:82724.9-82724.17" + attribute \src "libresoc.v:89454.9-89454.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -131045,18 +140092,18 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:82784.3-82844.6" - process $proc$libresoc.v:82784$3717 + attribute \src "libresoc.v:89514.3-89574.6" + process $proc$libresoc.v:89514$3825 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:82785.5-82785.29" + attribute \src "libresoc.v:89515.5-89515.29" switch \initial - attribute \src "libresoc.v:82785.9-82785.17" + attribute \src "libresoc.v:89515.9-89515.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -131136,18 +140183,18 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:82845.3-82905.6" - process $proc$libresoc.v:82845$3718 + attribute \src "libresoc.v:89575.3-89635.6" + process $proc$libresoc.v:89575$3826 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:82846.5-82846.29" + attribute \src "libresoc.v:89576.5-89576.29" switch \initial - attribute \src "libresoc.v:82846.9-82846.17" + attribute \src "libresoc.v:89576.9-89576.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -131227,18 +140274,18 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:82906.3-82966.6" - process $proc$libresoc.v:82906$3719 + attribute \src "libresoc.v:89636.3-89696.6" + process $proc$libresoc.v:89636$3827 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:82907.5-82907.29" + attribute \src "libresoc.v:89637.5-89637.29" switch \initial - attribute \src "libresoc.v:82907.9-82907.17" + attribute \src "libresoc.v:89637.9-89637.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -131318,18 +140365,18 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:82967.3-83027.6" - process $proc$libresoc.v:82967$3720 + attribute \src "libresoc.v:89697.3-89757.6" + process $proc$libresoc.v:89697$3828 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:82968.5-82968.29" + attribute \src "libresoc.v:89698.5-89698.29" switch \initial - attribute \src "libresoc.v:82968.9-82968.17" + attribute \src "libresoc.v:89698.9-89698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -131430,113 +140477,157 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:83052.1-83767.10" +attribute \src "libresoc.v:89782.1-90730.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:83405.3-83423.6" + attribute \src "libresoc.v:90615.3-90633.6" + wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:90634.3-90652.6" + wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:90387.3-90405.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:83481.3-83499.6" + attribute \src "libresoc.v:90463.3-90481.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:83728.3-83746.6" + attribute \src "libresoc.v:90140.3-90158.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83747.3-83765.6" + attribute \src "libresoc.v:90159.3-90177.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:83386.3-83404.6" + attribute \src "libresoc.v:90368.3-90386.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:83462.3-83480.6" + attribute \src "libresoc.v:90444.3-90462.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:83633.3-83651.6" + attribute \src "libresoc.v:90539.3-90557.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:83310.3-83328.6" - wire width 12 $0\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:83652.3-83670.6" + attribute \src "libresoc.v:90121.3-90139.6" + wire width 14 $0\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:90653.3-90671.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:83671.3-83689.6" + attribute \src "libresoc.v:90672.3-90690.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:83690.3-83708.6" + attribute \src "libresoc.v:90691.3-90709.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:83519.3-83537.6" + attribute \src "libresoc.v:90330.3-90348.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:83424.3-83442.6" + attribute \src "libresoc.v:90406.3-90424.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:83443.3-83461.6" + attribute \src "libresoc.v:90425.3-90443.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:83557.3-83575.6" + attribute \src "libresoc.v:90520.3-90538.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:83329.3-83347.6" + attribute \src "libresoc.v:90292.3-90310.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:83595.3-83613.6" + attribute \src "libresoc.v:90577.3-90595.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:83709.3-83727.6" - wire width 2 $0\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:83367.3-83385.6" + attribute \src "libresoc.v:90710.3-90728.6" + wire width 3 $0\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:90349.3-90367.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:83538.3-83556.6" + attribute \src "libresoc.v:90501.3-90519.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:83614.3-83632.6" + attribute \src "libresoc.v:90596.3-90614.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:83576.3-83594.6" + attribute \src "libresoc.v:90558.3-90576.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:83500.3-83518.6" + attribute \src "libresoc.v:90482.3-90500.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:83348.3-83366.6" + attribute \src "libresoc.v:90254.3-90272.6" + wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:90273.3-90291.6" + wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:90178.3-90196.6" + wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:90197.3-90215.6" + wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:90216.3-90234.6" + wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:90235.3-90253.6" + wire width 3 $0\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:90311.3-90329.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:83053.7-83053.20" + attribute \src "libresoc.v:89783.7-89783.20" wire $0\initial[0:0] - attribute \src "libresoc.v:83405.3-83423.6" + attribute \src "libresoc.v:90615.3-90633.6" + wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:90634.3-90652.6" + wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:90387.3-90405.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:83481.3-83499.6" + attribute \src "libresoc.v:90463.3-90481.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:83728.3-83746.6" + attribute \src "libresoc.v:90140.3-90158.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83747.3-83765.6" + attribute \src "libresoc.v:90159.3-90177.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:83386.3-83404.6" + attribute \src "libresoc.v:90368.3-90386.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:83462.3-83480.6" + attribute \src "libresoc.v:90444.3-90462.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:83633.3-83651.6" + attribute \src "libresoc.v:90539.3-90557.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:83310.3-83328.6" - wire width 12 $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:83652.3-83670.6" + attribute \src "libresoc.v:90121.3-90139.6" + wire width 14 $1\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:90653.3-90671.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:83671.3-83689.6" + attribute \src "libresoc.v:90672.3-90690.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:83690.3-83708.6" + attribute \src "libresoc.v:90691.3-90709.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:83519.3-83537.6" + attribute \src "libresoc.v:90330.3-90348.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:83424.3-83442.6" + attribute \src "libresoc.v:90406.3-90424.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:83443.3-83461.6" + attribute \src "libresoc.v:90425.3-90443.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:83557.3-83575.6" + attribute \src "libresoc.v:90520.3-90538.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:83329.3-83347.6" + attribute \src "libresoc.v:90292.3-90310.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:83595.3-83613.6" + attribute \src "libresoc.v:90577.3-90595.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:83709.3-83727.6" - wire width 2 $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:83367.3-83385.6" + attribute \src "libresoc.v:90710.3-90728.6" + wire width 3 $1\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:90349.3-90367.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:83538.3-83556.6" + attribute \src "libresoc.v:90501.3-90519.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:83614.3-83632.6" + attribute \src "libresoc.v:90596.3-90614.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:83576.3-83594.6" + attribute \src "libresoc.v:90558.3-90576.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:83500.3-83518.6" + attribute \src "libresoc.v:90482.3-90500.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:83348.3-83366.6" + attribute \src "libresoc.v:90254.3-90272.6" + wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:90273.3-90291.6" + wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:90178.3-90196.6" + wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:90197.3-90215.6" + wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:90216.3-90234.6" + wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:90235.3-90253.6" + wire width 3 $1\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:90311.3-90329.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub0_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub0_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 output 4 \dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub0_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -131545,24 +140636,26 @@ module \dec31_dec_sub0 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub0_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub0_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub0_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -131593,31 +140686,34 @@ module \dec31_dec_sub0 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub0_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub0_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -131633,14 +140729,14 @@ module \dec31_dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub0_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub0_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -131715,113 +140811,449 @@ module \dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub0_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub0_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub0_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub0_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub0_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub0_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub0_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub0_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub0_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub0_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub0_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub0_upd - attribute \src "libresoc.v:83053.7-83053.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub0_upd + attribute \src "libresoc.v:89783.7-89783.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:83053.7-83053.20" - process $proc$libresoc.v:83053$3746 + attribute \src "libresoc.v:89783.7-89783.20" + process $proc$libresoc.v:89783$3862 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:83310.3-83328.6" - process $proc$libresoc.v:83310$3722 + attribute \src "libresoc.v:90121.3-90139.6" + process $proc$libresoc.v:90121$3830 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:90122.5-90122.29" + switch \initial + attribute \src "libresoc.v:90122.9-90122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000001000000 + case + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] + end + attribute \src "libresoc.v:90140.3-90158.6" + process $proc$libresoc.v:90140$3831 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:90141.5-90141.29" + switch \initial + attribute \src "libresoc.v:90141.9-90141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:90159.3-90177.6" + process $proc$libresoc.v:90159$3832 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:90160.5-90160.29" + switch \initial + attribute \src "libresoc.v:90160.9-90160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:90178.3-90196.6" + process $proc$libresoc.v:90178$3833 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:90179.5-90179.29" + switch \initial + attribute \src "libresoc.v:90179.9-90179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] + end + attribute \src "libresoc.v:90197.3-90215.6" + process $proc$libresoc.v:90197$3834 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:83311.5-83311.29" + assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:90198.5-90198.29" switch \initial - attribute \src "libresoc.v:83311.9-83311.17" + attribute \src "libresoc.v:90198.9-90198.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'000 case - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] + update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end - attribute \src "libresoc.v:83329.3-83347.6" - process $proc$libresoc.v:83329$3723 + attribute \src "libresoc.v:90216.3-90234.6" + process $proc$libresoc.v:90216$3835 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:90217.5-90217.29" + switch \initial + attribute \src "libresoc.v:90217.9-90217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] + end + attribute \src "libresoc.v:90235.3-90253.6" + process $proc$libresoc.v:90235$3836 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:90236.5-90236.29" + switch \initial + attribute \src "libresoc.v:90236.9-90236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] + end + attribute \src "libresoc.v:90254.3-90272.6" + process $proc$libresoc.v:90254$3837 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:90255.5-90255.29" + switch \initial + attribute \src "libresoc.v:90255.9-90255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'010 + case + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] + end + attribute \src "libresoc.v:90273.3-90291.6" + process $proc$libresoc.v:90273$3838 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:90274.5-90274.29" + switch \initial + attribute \src "libresoc.v:90274.9-90274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] + end + attribute \src "libresoc.v:90292.3-90310.6" + process $proc$libresoc.v:90292$3839 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:83330.5-83330.29" + attribute \src "libresoc.v:90293.5-90293.29" switch \initial - attribute \src "libresoc.v:83330.9-83330.17" + attribute \src "libresoc.v:90293.9-90293.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -131845,18 +141277,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:83348.3-83366.6" - process $proc$libresoc.v:83348$3724 + attribute \src "libresoc.v:90311.3-90329.6" + process $proc$libresoc.v:90311$3840 assign { } { } assign { } { } assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:83349.5-83349.29" + attribute \src "libresoc.v:90312.5-90312.29" switch \initial - attribute \src "libresoc.v:83349.9-83349.17" + attribute \src "libresoc.v:90312.9-90312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -131880,18 +141312,53 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:83367.3-83385.6" - process $proc$libresoc.v:83367$3725 + attribute \src "libresoc.v:90330.3-90348.6" + process $proc$libresoc.v:90330$3841 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:90331.5-90331.29" + switch \initial + attribute \src "libresoc.v:90331.9-90331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:90349.3-90367.6" + process $proc$libresoc.v:90349$3842 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:83368.5-83368.29" + attribute \src "libresoc.v:90350.5-90350.29" switch \initial - attribute \src "libresoc.v:83368.9-83368.17" + attribute \src "libresoc.v:90350.9-90350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -131915,18 +141382,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:83386.3-83404.6" - process $proc$libresoc.v:83386$3726 + attribute \src "libresoc.v:90368.3-90386.6" + process $proc$libresoc.v:90368$3843 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:83387.5-83387.29" + attribute \src "libresoc.v:90369.5-90369.29" switch \initial - attribute \src "libresoc.v:83387.9-83387.17" + attribute \src "libresoc.v:90369.9-90369.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -131950,18 +141417,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:83405.3-83423.6" - process $proc$libresoc.v:83405$3727 + attribute \src "libresoc.v:90387.3-90405.6" + process $proc$libresoc.v:90387$3844 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:83406.5-83406.29" + attribute \src "libresoc.v:90388.5-90388.29" switch \initial - attribute \src "libresoc.v:83406.9-83406.17" + attribute \src "libresoc.v:90388.9-90388.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -131985,18 +141452,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:83424.3-83442.6" - process $proc$libresoc.v:83424$3728 + attribute \src "libresoc.v:90406.3-90424.6" + process $proc$libresoc.v:90406$3845 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:83425.5-83425.29" + attribute \src "libresoc.v:90407.5-90407.29" switch \initial - attribute \src "libresoc.v:83425.9-83425.17" + attribute \src "libresoc.v:90407.9-90407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -132020,18 +141487,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:83443.3-83461.6" - process $proc$libresoc.v:83443$3729 + attribute \src "libresoc.v:90425.3-90443.6" + process $proc$libresoc.v:90425$3846 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:83444.5-83444.29" + attribute \src "libresoc.v:90426.5-90426.29" switch \initial - attribute \src "libresoc.v:83444.9-83444.17" + attribute \src "libresoc.v:90426.9-90426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -132055,18 +141522,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:83462.3-83480.6" - process $proc$libresoc.v:83462$3730 + attribute \src "libresoc.v:90444.3-90462.6" + process $proc$libresoc.v:90444$3847 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:83463.5-83463.29" + attribute \src "libresoc.v:90445.5-90445.29" switch \initial - attribute \src "libresoc.v:83463.9-83463.17" + attribute \src "libresoc.v:90445.9-90445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -132090,18 +141557,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:83481.3-83499.6" - process $proc$libresoc.v:83481$3731 + attribute \src "libresoc.v:90463.3-90481.6" + process $proc$libresoc.v:90463$3848 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:83482.5-83482.29" + attribute \src "libresoc.v:90464.5-90464.29" switch \initial - attribute \src "libresoc.v:83482.9-83482.17" + attribute \src "libresoc.v:90464.9-90464.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -132125,18 +141592,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:83500.3-83518.6" - process $proc$libresoc.v:83500$3732 + attribute \src "libresoc.v:90482.3-90500.6" + process $proc$libresoc.v:90482$3849 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:83501.5-83501.29" + attribute \src "libresoc.v:90483.5-90483.29" switch \initial - attribute \src "libresoc.v:83501.9-83501.17" + attribute \src "libresoc.v:90483.9-90483.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -132160,53 +141627,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:83519.3-83537.6" - process $proc$libresoc.v:83519$3733 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:83520.5-83520.29" - switch \initial - attribute \src "libresoc.v:83520.9-83520.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 - case - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] - end - attribute \src "libresoc.v:83538.3-83556.6" - process $proc$libresoc.v:83538$3734 + attribute \src "libresoc.v:90501.3-90519.6" + process $proc$libresoc.v:90501$3850 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:83539.5-83539.29" + attribute \src "libresoc.v:90502.5-90502.29" switch \initial - attribute \src "libresoc.v:83539.9-83539.17" + attribute \src "libresoc.v:90502.9-90502.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -132230,18 +141662,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:83557.3-83575.6" - process $proc$libresoc.v:83557$3735 + attribute \src "libresoc.v:90520.3-90538.6" + process $proc$libresoc.v:90520$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:83558.5-83558.29" + attribute \src "libresoc.v:90521.5-90521.29" switch \initial - attribute \src "libresoc.v:83558.9-83558.17" + attribute \src "libresoc.v:90521.9-90521.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -132265,465 +141697,509 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:83576.3-83594.6" - process $proc$libresoc.v:83576$3736 + attribute \src "libresoc.v:90539.3-90557.6" + process $proc$libresoc.v:90539$3852 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:83577.5-83577.29" + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:90540.5-90540.29" switch \initial - attribute \src "libresoc.v:83577.9-83577.17" + attribute \src "libresoc.v:90540.9-90540.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'11000 case - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'00000 end sync always - update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:83595.3-83613.6" - process $proc$libresoc.v:83595$3737 + attribute \src "libresoc.v:90558.3-90576.6" + process $proc$libresoc.v:90558$3853 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:83596.5-83596.29" + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:90559.5-90559.29" switch \initial - attribute \src "libresoc.v:83596.9-83596.17" + attribute \src "libresoc.v:90559.9-90559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:83614.3-83632.6" - process $proc$libresoc.v:83614$3738 + attribute \src "libresoc.v:90577.3-90595.6" + process $proc$libresoc.v:90577$3854 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:83615.5-83615.29" + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:90578.5-90578.29" switch \initial - attribute \src "libresoc.v:83615.9-83615.17" + attribute \src "libresoc.v:90578.9-90578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub0_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub0_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub0_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub0_lk[0:0] 1'0 case - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub0_lk[0:0] 1'0 end sync always - update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:83633.3-83651.6" - process $proc$libresoc.v:83633$3739 + attribute \src "libresoc.v:90596.3-90614.6" + process $proc$libresoc.v:90596$3855 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:83634.5-83634.29" + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:90597.5-90597.29" switch \initial - attribute \src "libresoc.v:83634.9-83634.17" + attribute \src "libresoc.v:90597.9-90597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'11000 + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 case - assign $1\dec31_dec_sub0_form[4:0] 5'00000 + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:83652.3-83670.6" - process $proc$libresoc.v:83652$3740 + attribute \src "libresoc.v:90615.3-90633.6" + process $proc$libresoc.v:90615$3856 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:83653.5-83653.29" + assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:90616.5-90616.29" switch \initial - attribute \src "libresoc.v:83653.9-83653.17" + attribute \src "libresoc.v:90616.9-90616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 case - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'00 end sync always - update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end - attribute \src "libresoc.v:83671.3-83689.6" - process $proc$libresoc.v:83671$3741 + attribute \src "libresoc.v:90634.3-90652.6" + process $proc$libresoc.v:90634$3857 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:83672.5-83672.29" + assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:90635.5-90635.29" switch \initial - attribute \src "libresoc.v:83672.9-83672.17" + attribute \src "libresoc.v:90635.9-90635.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'10 case - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end - attribute \src "libresoc.v:83690.3-83708.6" - process $proc$libresoc.v:83690$3742 + attribute \src "libresoc.v:90653.3-90671.6" + process $proc$libresoc.v:90653$3858 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:83691.5-83691.29" + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:90654.5-90654.29" switch \initial - attribute \src "libresoc.v:83691.9-83691.17" + attribute \src "libresoc.v:90654.9-90654.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 case - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 end sync always - update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:83709.3-83727.6" - process $proc$libresoc.v:83709$3743 + attribute \src "libresoc.v:90672.3-90690.6" + process $proc$libresoc.v:90672$3859 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:83710.5-83710.29" + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:90673.5-90673.29" switch \initial - attribute \src "libresoc.v:83710.9-83710.17" + attribute \src "libresoc.v:90673.9-90673.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 case - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 end sync always - update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:83728.3-83746.6" - process $proc$libresoc.v:83728$3744 + attribute \src "libresoc.v:90691.3-90709.6" + process $proc$libresoc.v:90691$3860 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83729.5-83729.29" + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:90692.5-90692.29" switch \initial - attribute \src "libresoc.v:83729.9-83729.17" + attribute \src "libresoc.v:90692.9-90692.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 case - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 end sync always - update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:83747.3-83765.6" - process $proc$libresoc.v:83747$3745 + attribute \src "libresoc.v:90710.3-90728.6" + process $proc$libresoc.v:90710$3861 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:83748.5-83748.29" + assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:90711.5-90711.29" switch \initial - attribute \src "libresoc.v:83748.9-83748.17" + attribute \src "libresoc.v:90711.9-90711.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:83771.1-84918.10" +attribute \src "libresoc.v:90734.1-92258.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:84214.3-84250.6" + attribute \src "libresoc.v:92035.3-92071.6" + wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:92072.3-92108.6" + wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:91591.3-91627.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:84362.3-84398.6" + attribute \src "libresoc.v:91739.3-91775.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:84843.3-84879.6" + attribute \src "libresoc.v:91110.3-91146.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:84880.3-84916.6" + attribute \src "libresoc.v:91147.3-91183.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:84177.3-84213.6" + attribute \src "libresoc.v:91554.3-91590.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:84325.3-84361.6" + attribute \src "libresoc.v:91702.3-91738.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:84658.3-84694.6" + attribute \src "libresoc.v:91887.3-91923.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:84029.3-84065.6" - wire width 12 $0\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:84695.3-84731.6" + attribute \src "libresoc.v:91073.3-91109.6" + wire width 14 $0\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:92109.3-92145.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84732.3-84768.6" + attribute \src "libresoc.v:92146.3-92182.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84769.3-84805.6" + attribute \src "libresoc.v:92183.3-92219.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:84436.3-84472.6" + attribute \src "libresoc.v:91480.3-91516.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:84251.3-84287.6" + attribute \src "libresoc.v:91628.3-91664.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:84288.3-84324.6" + attribute \src "libresoc.v:91665.3-91701.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:84510.3-84546.6" + attribute \src "libresoc.v:91850.3-91886.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:84066.3-84102.6" + attribute \src "libresoc.v:91406.3-91442.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:84584.3-84620.6" + attribute \src "libresoc.v:91961.3-91997.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:84806.3-84842.6" - wire width 2 $0\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:84140.3-84176.6" + attribute \src "libresoc.v:92220.3-92256.6" + wire width 3 $0\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:91517.3-91553.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:84473.3-84509.6" + attribute \src "libresoc.v:91813.3-91849.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:84621.3-84657.6" + attribute \src "libresoc.v:91998.3-92034.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:84547.3-84583.6" + attribute \src "libresoc.v:91924.3-91960.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:84399.3-84435.6" + attribute \src "libresoc.v:91776.3-91812.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:84103.3-84139.6" + attribute \src "libresoc.v:91332.3-91368.6" + wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:91369.3-91405.6" + wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:91184.3-91220.6" + wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:91221.3-91257.6" + wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:91258.3-91294.6" + wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:91295.3-91331.6" + wire width 3 $0\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:91443.3-91479.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:83772.7-83772.20" + attribute \src "libresoc.v:90735.7-90735.20" wire $0\initial[0:0] - attribute \src "libresoc.v:84214.3-84250.6" + attribute \src "libresoc.v:92035.3-92071.6" + wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:92072.3-92108.6" + wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:91591.3-91627.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:84362.3-84398.6" + attribute \src "libresoc.v:91739.3-91775.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:84843.3-84879.6" + attribute \src "libresoc.v:91110.3-91146.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:84880.3-84916.6" + attribute \src "libresoc.v:91147.3-91183.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:84177.3-84213.6" + attribute \src "libresoc.v:91554.3-91590.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:84325.3-84361.6" + attribute \src "libresoc.v:91702.3-91738.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:84658.3-84694.6" + attribute \src "libresoc.v:91887.3-91923.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:84029.3-84065.6" - wire width 12 $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:84695.3-84731.6" + attribute \src "libresoc.v:91073.3-91109.6" + wire width 14 $1\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:92109.3-92145.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84732.3-84768.6" + attribute \src "libresoc.v:92146.3-92182.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84769.3-84805.6" + attribute \src "libresoc.v:92183.3-92219.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:84436.3-84472.6" + attribute \src "libresoc.v:91480.3-91516.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:84251.3-84287.6" + attribute \src "libresoc.v:91628.3-91664.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:84288.3-84324.6" + attribute \src "libresoc.v:91665.3-91701.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:84510.3-84546.6" + attribute \src "libresoc.v:91850.3-91886.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:84066.3-84102.6" + attribute \src "libresoc.v:91406.3-91442.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:84584.3-84620.6" + attribute \src "libresoc.v:91961.3-91997.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:84806.3-84842.6" - wire width 2 $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:84140.3-84176.6" + attribute \src "libresoc.v:92220.3-92256.6" + wire width 3 $1\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:91517.3-91553.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:84473.3-84509.6" + attribute \src "libresoc.v:91813.3-91849.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:84621.3-84657.6" + attribute \src "libresoc.v:91998.3-92034.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:84547.3-84583.6" + attribute \src "libresoc.v:91924.3-91960.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:84399.3-84435.6" + attribute \src "libresoc.v:91776.3-91812.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:84103.3-84139.6" + attribute \src "libresoc.v:91332.3-91368.6" + wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:91369.3-91405.6" + wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:91184.3-91220.6" + wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:91221.3-91257.6" + wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:91258.3-91294.6" + wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:91295.3-91331.6" + wire width 3 $1\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:91443.3-91479.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub10_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub10_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 output 4 \dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub10_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -132732,24 +142208,26 @@ module \dec31_dec_sub10 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub10_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub10_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub10_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -132780,31 +142258,34 @@ module \dec31_dec_sub10 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub10_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub10_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub10_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -132820,14 +142301,14 @@ module \dec31_dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub10_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub10_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -132902,727 +142383,783 @@ module \dec31_dec_sub10 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub10_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub10_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub10_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub10_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub10_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub10_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub10_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub10_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub10_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub10_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub10_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub10_upd - attribute \src "libresoc.v:83772.7-83772.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub10_upd + attribute \src "libresoc.v:90735.7-90735.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:83772.7-83772.20" - process $proc$libresoc.v:83772$3771 + attribute \src "libresoc.v:90735.7-90735.20" + process $proc$libresoc.v:90735$3895 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:84029.3-84065.6" - process $proc$libresoc.v:84029$3747 + attribute \src "libresoc.v:91073.3-91109.6" + process $proc$libresoc.v:91073$3863 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:84030.5-84030.29" + assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:91074.5-91074.29" switch \initial - attribute \src "libresoc.v:84030.9-84030.17" + attribute \src "libresoc.v:91074.9-91074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 case - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:84066.3-84102.6" - process $proc$libresoc.v:84066$3748 + attribute \src "libresoc.v:91110.3-91146.6" + process $proc$libresoc.v:91110$3864 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:84067.5-84067.29" + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:91111.5-91111.29" switch \initial - attribute \src "libresoc.v:84067.9-84067.17" + attribute \src "libresoc.v:91111.9-91111.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:84103.3-84139.6" - process $proc$libresoc.v:84103$3749 + attribute \src "libresoc.v:91147.3-91183.6" + process $proc$libresoc.v:91147$3865 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:84104.5-84104.29" + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:91148.5-91148.29" switch \initial - attribute \src "libresoc.v:84104.9-84104.17" + attribute \src "libresoc.v:91148.9-91148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:84140.3-84176.6" - process $proc$libresoc.v:84140$3750 + attribute \src "libresoc.v:91184.3-91220.6" + process $proc$libresoc.v:91184$3866 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:84141.5-84141.29" + assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:91185.5-91185.29" switch \initial - attribute \src "libresoc.v:84141.9-84141.17" + attribute \src "libresoc.v:91185.9-91185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 case - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end - attribute \src "libresoc.v:84177.3-84213.6" - process $proc$libresoc.v:84177$3751 + attribute \src "libresoc.v:91221.3-91257.6" + process $proc$libresoc.v:91221$3867 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:84178.5-84178.29" + assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:91222.5-91222.29" switch \initial - attribute \src "libresoc.v:84178.9-84178.17" + attribute \src "libresoc.v:91222.9-91222.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 case - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end - attribute \src "libresoc.v:84214.3-84250.6" - process $proc$libresoc.v:84214$3752 + attribute \src "libresoc.v:91258.3-91294.6" + process $proc$libresoc.v:91258$3868 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:84215.5-84215.29" + assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:91259.5-91259.29" switch \initial - attribute \src "libresoc.v:84215.9-84215.17" + attribute \src "libresoc.v:91259.9-91259.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end - attribute \src "libresoc.v:84251.3-84287.6" - process $proc$libresoc.v:84251$3753 + attribute \src "libresoc.v:91295.3-91331.6" + process $proc$libresoc.v:91295$3869 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:84252.5-84252.29" + assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:91296.5-91296.29" switch \initial - attribute \src "libresoc.v:84252.9-84252.17" + attribute \src "libresoc.v:91296.9-91296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 case - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end - attribute \src "libresoc.v:84288.3-84324.6" - process $proc$libresoc.v:84288$3754 + attribute \src "libresoc.v:91332.3-91368.6" + process $proc$libresoc.v:91332$3870 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:84289.5-84289.29" + assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:91333.5-91333.29" switch \initial - attribute \src "libresoc.v:84289.9-84289.17" + attribute \src "libresoc.v:91333.9-91333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end - attribute \src "libresoc.v:84325.3-84361.6" - process $proc$libresoc.v:84325$3755 + attribute \src "libresoc.v:91369.3-91405.6" + process $proc$libresoc.v:91369$3871 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:84326.5-84326.29" + assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:91370.5-91370.29" switch \initial - attribute \src "libresoc.v:84326.9-84326.17" + attribute \src "libresoc.v:91370.9-91370.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end - attribute \src "libresoc.v:84362.3-84398.6" - process $proc$libresoc.v:84362$3756 + attribute \src "libresoc.v:91406.3-91442.6" + process $proc$libresoc.v:91406$3872 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:84363.5-84363.29" + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:91407.5-91407.29" switch \initial - attribute \src "libresoc.v:84363.9-84363.17" + attribute \src "libresoc.v:91407.9-91407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:84399.3-84435.6" - process $proc$libresoc.v:84399$3757 + attribute \src "libresoc.v:91443.3-91479.6" + process $proc$libresoc.v:91443$3873 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:84400.5-84400.29" + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:91444.5-91444.29" switch \initial - attribute \src "libresoc.v:84400.9-84400.17" + attribute \src "libresoc.v:91444.9-91444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 case - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 end sync always - update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:84436.3-84472.6" - process $proc$libresoc.v:84436$3758 + attribute \src "libresoc.v:91480.3-91516.6" + process $proc$libresoc.v:91480$3874 assign { } { } assign { } { } assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:84437.5-84437.29" + attribute \src "libresoc.v:91481.5-91481.29" switch \initial - attribute \src "libresoc.v:84437.9-84437.17" + attribute \src "libresoc.v:91481.9-91481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -133670,18 +143207,490 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:84473.3-84509.6" - process $proc$libresoc.v:84473$3759 + attribute \src "libresoc.v:91517.3-91553.6" + process $proc$libresoc.v:91517$3875 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:91518.5-91518.29" + switch \initial + attribute \src "libresoc.v:91518.9-91518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:91554.3-91590.6" + process $proc$libresoc.v:91554$3876 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:91555.5-91555.29" + switch \initial + attribute \src "libresoc.v:91555.9-91555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + end + attribute \src "libresoc.v:91591.3-91627.6" + process $proc$libresoc.v:91591$3877 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:91592.5-91592.29" + switch \initial + attribute \src "libresoc.v:91592.9-91592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + end + attribute \src "libresoc.v:91628.3-91664.6" + process $proc$libresoc.v:91628$3878 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:91629.5-91629.29" + switch \initial + attribute \src "libresoc.v:91629.9-91629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:91665.3-91701.6" + process $proc$libresoc.v:91665$3879 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:91666.5-91666.29" + switch \initial + attribute \src "libresoc.v:91666.9-91666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:91702.3-91738.6" + process $proc$libresoc.v:91702$3880 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:91703.5-91703.29" + switch \initial + attribute \src "libresoc.v:91703.9-91703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:91739.3-91775.6" + process $proc$libresoc.v:91739$3881 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:91740.5-91740.29" + switch \initial + attribute \src "libresoc.v:91740.9-91740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + end + attribute \src "libresoc.v:91776.3-91812.6" + process $proc$libresoc.v:91776$3882 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:91777.5-91777.29" + switch \initial + attribute \src "libresoc.v:91777.9-91777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + end + attribute \src "libresoc.v:91813.3-91849.6" + process $proc$libresoc.v:91813$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:84474.5-84474.29" + attribute \src "libresoc.v:91814.5-91814.29" switch \initial - attribute \src "libresoc.v:84474.9-84474.17" + attribute \src "libresoc.v:91814.9-91814.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -133729,18 +143738,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:84510.3-84546.6" - process $proc$libresoc.v:84510$3760 + attribute \src "libresoc.v:91850.3-91886.6" + process $proc$libresoc.v:91850$3884 assign { } { } assign { } { } assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:84511.5-84511.29" + attribute \src "libresoc.v:91851.5-91851.29" switch \initial - attribute \src "libresoc.v:84511.9-84511.17" + attribute \src "libresoc.v:91851.9-91851.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -133788,705 +143797,749 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:84547.3-84583.6" - process $proc$libresoc.v:84547$3761 + attribute \src "libresoc.v:91887.3-91923.6" + process $proc$libresoc.v:91887$3885 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:84548.5-84548.29" + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:91888.5-91888.29" switch \initial - attribute \src "libresoc.v:84548.9-84548.17" + attribute \src "libresoc.v:91888.9-91888.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 case - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'00000 end sync always - update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:84584.3-84620.6" - process $proc$libresoc.v:84584$3762 + attribute \src "libresoc.v:91924.3-91960.6" + process $proc$libresoc.v:91924$3886 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:84585.5-84585.29" + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:91925.5-91925.29" switch \initial - attribute \src "libresoc.v:84585.9-84585.17" + attribute \src "libresoc.v:91925.9-91925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:84621.3-84657.6" - process $proc$libresoc.v:84621$3763 + attribute \src "libresoc.v:91961.3-91997.6" + process $proc$libresoc.v:91961$3887 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:84622.5-84622.29" + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:91962.5-91962.29" switch \initial - attribute \src "libresoc.v:84622.9-84622.17" + attribute \src "libresoc.v:91962.9-91962.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 case - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub10_lk[0:0] 1'0 end sync always - update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:84658.3-84694.6" - process $proc$libresoc.v:84658$3764 + attribute \src "libresoc.v:91998.3-92034.6" + process $proc$libresoc.v:91998$3888 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:84659.5-84659.29" + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:91999.5-91999.29" switch \initial - attribute \src "libresoc.v:84659.9-84659.17" + attribute \src "libresoc.v:91999.9-91999.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 case - assign $1\dec31_dec_sub10_form[4:0] 5'00000 + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:84695.3-84731.6" - process $proc$libresoc.v:84695$3765 + attribute \src "libresoc.v:92035.3-92071.6" + process $proc$libresoc.v:92035$3889 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84696.5-84696.29" + assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:92036.5-92036.29" switch \initial - attribute \src "libresoc.v:84696.9-84696.17" + attribute \src "libresoc.v:92036.9-92036.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 case - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'00 end sync always - update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] + update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end - attribute \src "libresoc.v:84732.3-84768.6" - process $proc$libresoc.v:84732$3766 + attribute \src "libresoc.v:92072.3-92108.6" + process $proc$libresoc.v:92072$3890 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84733.5-84733.29" + assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:92073.5-92073.29" switch \initial - attribute \src "libresoc.v:84733.9-84733.17" + attribute \src "libresoc.v:92073.9-92073.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 case - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] + update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end - attribute \src "libresoc.v:84769.3-84805.6" - process $proc$libresoc.v:84769$3767 + attribute \src "libresoc.v:92109.3-92145.6" + process $proc$libresoc.v:92109$3891 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:84770.5-84770.29" + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:92110.5-92110.29" switch \initial - attribute \src "libresoc.v:84770.9-84770.17" + attribute \src "libresoc.v:92110.9-92110.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 case - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 end sync always - update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:84806.3-84842.6" - process $proc$libresoc.v:84806$3768 + attribute \src "libresoc.v:92146.3-92182.6" + process $proc$libresoc.v:92146$3892 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:84807.5-84807.29" + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:92147.5-92147.29" switch \initial - attribute \src "libresoc.v:84807.9-84807.17" + attribute \src "libresoc.v:92147.9-92147.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 case - assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 end sync always - update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:84843.3-84879.6" - process $proc$libresoc.v:84843$3769 + attribute \src "libresoc.v:92183.3-92219.6" + process $proc$libresoc.v:92183$3893 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:84844.5-84844.29" + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:92184.5-92184.29" switch \initial - attribute \src "libresoc.v:84844.9-84844.17" + attribute \src "libresoc.v:92184.9-92184.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 case - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 end sync always - update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:84880.3-84916.6" - process $proc$libresoc.v:84880$3770 + attribute \src "libresoc.v:92220.3-92256.6" + process $proc$libresoc.v:92220$3894 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:84881.5-84881.29" + assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:92221.5-92221.29" switch \initial - attribute \src "libresoc.v:84881.9-84881.17" + attribute \src "libresoc.v:92221.9-92221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:84922.1-86501.10" +attribute \src "libresoc.v:92262.1-94362.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:85455.3-85509.6" + attribute \src "libresoc.v:94031.3-94085.6" + wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:94086.3-94140.6" + wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:93371.3-93425.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:85675.3-85729.6" + attribute \src "libresoc.v:93591.3-93645.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:86390.3-86444.6" + attribute \src "libresoc.v:92656.3-92710.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:86445.3-86499.6" + attribute \src "libresoc.v:92711.3-92765.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:85400.3-85454.6" + attribute \src "libresoc.v:93316.3-93370.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:85620.3-85674.6" + attribute \src "libresoc.v:93536.3-93590.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:86115.3-86169.6" + attribute \src "libresoc.v:93811.3-93865.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:85180.3-85234.6" - wire width 12 $0\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:86170.3-86224.6" + attribute \src "libresoc.v:92601.3-92655.6" + wire width 14 $0\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:94141.3-94195.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:86225.3-86279.6" + attribute \src "libresoc.v:94196.3-94250.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:86280.3-86334.6" + attribute \src "libresoc.v:94251.3-94305.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:85785.3-85839.6" + attribute \src "libresoc.v:93206.3-93260.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:85510.3-85564.6" + attribute \src "libresoc.v:93426.3-93480.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:85565.3-85619.6" + attribute \src "libresoc.v:93481.3-93535.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:85895.3-85949.6" + attribute \src "libresoc.v:93756.3-93810.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:85235.3-85289.6" + attribute \src "libresoc.v:93096.3-93150.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:86005.3-86059.6" + attribute \src "libresoc.v:93921.3-93975.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:86335.3-86389.6" - wire width 2 $0\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:85345.3-85399.6" + attribute \src "libresoc.v:94306.3-94360.6" + wire width 3 $0\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:93261.3-93315.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:85840.3-85894.6" + attribute \src "libresoc.v:93701.3-93755.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:86060.3-86114.6" + attribute \src "libresoc.v:93976.3-94030.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:85950.3-86004.6" + attribute \src "libresoc.v:93866.3-93920.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:85730.3-85784.6" + attribute \src "libresoc.v:93646.3-93700.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:85290.3-85344.6" + attribute \src "libresoc.v:92986.3-93040.6" + wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:93041.3-93095.6" + wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:92766.3-92820.6" + wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:92821.3-92875.6" + wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:92876.3-92930.6" + wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:92931.3-92985.6" + wire width 3 $0\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:93151.3-93205.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:84923.7-84923.20" + attribute \src "libresoc.v:92263.7-92263.20" wire $0\initial[0:0] - attribute \src "libresoc.v:85455.3-85509.6" + attribute \src "libresoc.v:94031.3-94085.6" + wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:94086.3-94140.6" + wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:93371.3-93425.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:85675.3-85729.6" + attribute \src "libresoc.v:93591.3-93645.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:86390.3-86444.6" + attribute \src "libresoc.v:92656.3-92710.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:86445.3-86499.6" + attribute \src "libresoc.v:92711.3-92765.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:85400.3-85454.6" + attribute \src "libresoc.v:93316.3-93370.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:85620.3-85674.6" + attribute \src "libresoc.v:93536.3-93590.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:86115.3-86169.6" + attribute \src "libresoc.v:93811.3-93865.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:85180.3-85234.6" - wire width 12 $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:86170.3-86224.6" + attribute \src "libresoc.v:92601.3-92655.6" + wire width 14 $1\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:94141.3-94195.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:86225.3-86279.6" + attribute \src "libresoc.v:94196.3-94250.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:86280.3-86334.6" + attribute \src "libresoc.v:94251.3-94305.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:85785.3-85839.6" + attribute \src "libresoc.v:93206.3-93260.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:85510.3-85564.6" + attribute \src "libresoc.v:93426.3-93480.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:85565.3-85619.6" + attribute \src "libresoc.v:93481.3-93535.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:85895.3-85949.6" + attribute \src "libresoc.v:93756.3-93810.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:85235.3-85289.6" + attribute \src "libresoc.v:93096.3-93150.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:86005.3-86059.6" + attribute \src "libresoc.v:93921.3-93975.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:86335.3-86389.6" - wire width 2 $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:85345.3-85399.6" + attribute \src "libresoc.v:94306.3-94360.6" + wire width 3 $1\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:93261.3-93315.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:85840.3-85894.6" + attribute \src "libresoc.v:93701.3-93755.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:86060.3-86114.6" + attribute \src "libresoc.v:93976.3-94030.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:85950.3-86004.6" + attribute \src "libresoc.v:93866.3-93920.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:85730.3-85784.6" + attribute \src "libresoc.v:93646.3-93700.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:85290.3-85344.6" + attribute \src "libresoc.v:92986.3-93040.6" + wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:93041.3-93095.6" + wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:92766.3-92820.6" + wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:92821.3-92875.6" + wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:92876.3-92930.6" + wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:92931.3-92985.6" + wire width 3 $1\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:93151.3-93205.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub11_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub11_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 output 4 \dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub11_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -134495,24 +144548,26 @@ module \dec31_dec_sub11 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub11_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub11_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub11_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -134543,31 +144598,34 @@ module \dec31_dec_sub11 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub11_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub11_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -134583,14 +144641,14 @@ module \dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub11_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub11_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -134665,991 +144723,1047 @@ module \dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub11_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub11_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub11_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub11_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub11_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub11_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub11_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub11_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub11_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub11_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub11_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub11_upd - attribute \src "libresoc.v:84923.7-84923.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub11_upd + attribute \src "libresoc.v:92263.7-92263.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:84923.7-84923.20" - process $proc$libresoc.v:84923$3796 + attribute \src "libresoc.v:92263.7-92263.20" + process $proc$libresoc.v:92263$3928 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:85180.3-85234.6" - process $proc$libresoc.v:85180$3772 + attribute \src "libresoc.v:92601.3-92655.6" + process $proc$libresoc.v:92601$3896 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:85181.5-85181.29" + assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:92602.5-92602.29" switch \initial - attribute \src "libresoc.v:85181.9-85181.17" + attribute \src "libresoc.v:92602.9-92602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 case - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:85235.3-85289.6" - process $proc$libresoc.v:85235$3773 + attribute \src "libresoc.v:92656.3-92710.6" + process $proc$libresoc.v:92656$3897 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:85236.5-85236.29" + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:92657.5-92657.29" switch \initial - attribute \src "libresoc.v:85236.9-85236.17" + attribute \src "libresoc.v:92657.9-92657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:85290.3-85344.6" - process $proc$libresoc.v:85290$3774 + attribute \src "libresoc.v:92711.3-92765.6" + process $proc$libresoc.v:92711$3898 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:85291.5-85291.29" + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:92712.5-92712.29" switch \initial - attribute \src "libresoc.v:85291.9-85291.17" + attribute \src "libresoc.v:92712.9-92712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:85345.3-85399.6" - process $proc$libresoc.v:85345$3775 + attribute \src "libresoc.v:92766.3-92820.6" + process $proc$libresoc.v:92766$3899 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:85346.5-85346.29" + assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:92767.5-92767.29" switch \initial - attribute \src "libresoc.v:85346.9-85346.17" + attribute \src "libresoc.v:92767.9-92767.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 case - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] + update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end - attribute \src "libresoc.v:85400.3-85454.6" - process $proc$libresoc.v:85400$3776 + attribute \src "libresoc.v:92821.3-92875.6" + process $proc$libresoc.v:92821$3900 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:85401.5-85401.29" + assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:92822.5-92822.29" switch \initial - attribute \src "libresoc.v:85401.9-85401.17" + attribute \src "libresoc.v:92822.9-92822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 case - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] + update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end - attribute \src "libresoc.v:85455.3-85509.6" - process $proc$libresoc.v:85455$3777 + attribute \src "libresoc.v:92876.3-92930.6" + process $proc$libresoc.v:92876$3901 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:85456.5-85456.29" + assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:92877.5-92877.29" switch \initial - attribute \src "libresoc.v:85456.9-85456.17" + attribute \src "libresoc.v:92877.9-92877.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] + update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end - attribute \src "libresoc.v:85510.3-85564.6" - process $proc$libresoc.v:85510$3778 + attribute \src "libresoc.v:92931.3-92985.6" + process $proc$libresoc.v:92931$3902 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:85511.5-85511.29" + assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:92932.5-92932.29" switch \initial - attribute \src "libresoc.v:85511.9-85511.17" + attribute \src "libresoc.v:92932.9-92932.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 case - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] + update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end - attribute \src "libresoc.v:85565.3-85619.6" - process $proc$libresoc.v:85565$3779 + attribute \src "libresoc.v:92986.3-93040.6" + process $proc$libresoc.v:92986$3903 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:85566.5-85566.29" + assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:92987.5-92987.29" switch \initial - attribute \src "libresoc.v:85566.9-85566.17" + attribute \src "libresoc.v:92987.9-92987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end - attribute \src "libresoc.v:85620.3-85674.6" - process $proc$libresoc.v:85620$3780 + attribute \src "libresoc.v:93041.3-93095.6" + process $proc$libresoc.v:93041$3904 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:85621.5-85621.29" + assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:93042.5-93042.29" switch \initial - attribute \src "libresoc.v:85621.9-85621.17" + attribute \src "libresoc.v:93042.9-93042.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end - attribute \src "libresoc.v:85675.3-85729.6" - process $proc$libresoc.v:85675$3781 + attribute \src "libresoc.v:93096.3-93150.6" + process $proc$libresoc.v:93096$3905 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:85676.5-85676.29" + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:93097.5-93097.29" switch \initial - attribute \src "libresoc.v:85676.9-85676.17" + attribute \src "libresoc.v:93097.9-93097.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:85730.3-85784.6" - process $proc$libresoc.v:85730$3782 + attribute \src "libresoc.v:93151.3-93205.6" + process $proc$libresoc.v:93151$3906 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:85731.5-85731.29" + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:93152.5-93152.29" switch \initial - attribute \src "libresoc.v:85731.9-85731.17" + attribute \src "libresoc.v:93152.9-93152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 case - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 end sync always - update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:85785.3-85839.6" - process $proc$libresoc.v:85785$3783 + attribute \src "libresoc.v:93206.3-93260.6" + process $proc$libresoc.v:93206$3907 assign { } { } assign { } { } assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:85786.5-85786.29" + attribute \src "libresoc.v:93207.5-93207.29" switch \initial - attribute \src "libresoc.v:85786.9-85786.17" + attribute \src "libresoc.v:93207.9-93207.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -135721,433 +145835,848 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:85840.3-85894.6" - process $proc$libresoc.v:85840$3784 + attribute \src "libresoc.v:93261.3-93315.6" + process $proc$libresoc.v:93261$3908 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:85841.5-85841.29" + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:93262.5-93262.29" switch \initial - attribute \src "libresoc.v:85841.9-85841.17" + attribute \src "libresoc.v:93262.9-93262.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 case - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:85895.3-85949.6" - process $proc$libresoc.v:85895$3785 + attribute \src "libresoc.v:93316.3-93370.6" + process $proc$libresoc.v:93316$3909 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:85896.5-85896.29" + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:93317.5-93317.29" switch \initial - attribute \src "libresoc.v:85896.9-85896.17" + attribute \src "libresoc.v:93317.9-93317.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:85950.3-86004.6" - process $proc$libresoc.v:85950$3786 + attribute \src "libresoc.v:93371.3-93425.6" + process $proc$libresoc.v:93371$3910 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:85951.5-85951.29" + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:93372.5-93372.29" switch \initial - attribute \src "libresoc.v:85951.9-85951.17" + attribute \src "libresoc.v:93372.9-93372.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 case - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:86005.3-86059.6" - process $proc$libresoc.v:86005$3787 + attribute \src "libresoc.v:93426.3-93480.6" + process $proc$libresoc.v:93426$3911 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:86006.5-86006.29" + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:93427.5-93427.29" switch \initial - attribute \src "libresoc.v:86006.9-86006.17" + attribute \src "libresoc.v:93427.9-93427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:86060.3-86114.6" - process $proc$libresoc.v:86060$3788 + attribute \src "libresoc.v:93481.3-93535.6" + process $proc$libresoc.v:93481$3912 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:86061.5-86061.29" + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:93482.5-93482.29" switch \initial - attribute \src "libresoc.v:86061.9-86061.17" + attribute \src "libresoc.v:93482.9-93482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:93536.3-93590.6" + process $proc$libresoc.v:93536$3913 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:93537.5-93537.29" + switch \initial + attribute \src "libresoc.v:93537.9-93537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:93591.3-93645.6" + process $proc$libresoc.v:93591$3914 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:93592.5-93592.29" + switch \initial + attribute \src "libresoc.v:93592.9-93592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + end + attribute \src "libresoc.v:93646.3-93700.6" + process $proc$libresoc.v:93646$3915 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:93647.5-93647.29" + switch \initial + attribute \src "libresoc.v:93647.9-93647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + end + attribute \src "libresoc.v:93701.3-93755.6" + process $proc$libresoc.v:93701$3916 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:93702.5-93702.29" + switch \initial + attribute \src "libresoc.v:93702.9-93702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + end + attribute \src "libresoc.v:93756.3-93810.6" + process $proc$libresoc.v:93756$3917 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:93757.5-93757.29" + switch \initial + attribute \src "libresoc.v:93757.9-93757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:86115.3-86169.6" - process $proc$libresoc.v:86115$3789 + attribute \src "libresoc.v:93811.3-93865.6" + process $proc$libresoc.v:93811$3918 assign { } { } assign { } { } assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:86116.5-86116.29" + attribute \src "libresoc.v:93812.5-93812.29" switch \initial - attribute \src "libresoc.v:86116.9-86116.17" + attribute \src "libresoc.v:93812.9-93812.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -136219,613 +146748,906 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:86170.3-86224.6" - process $proc$libresoc.v:86170$3790 + attribute \src "libresoc.v:93866.3-93920.6" + process $proc$libresoc.v:93866$3919 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:86171.5-86171.29" + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:93867.5-93867.29" switch \initial - attribute \src "libresoc.v:86171.9-86171.17" + attribute \src "libresoc.v:93867.9-93867.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 case - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:86225.3-86279.6" - process $proc$libresoc.v:86225$3791 + attribute \src "libresoc.v:93921.3-93975.6" + process $proc$libresoc.v:93921$3920 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:86226.5-86226.29" + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:93922.5-93922.29" switch \initial - attribute \src "libresoc.v:86226.9-86226.17" + attribute \src "libresoc.v:93922.9-93922.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 case - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub11_lk[0:0] 1'0 end sync always - update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:86280.3-86334.6" - process $proc$libresoc.v:86280$3792 + attribute \src "libresoc.v:93976.3-94030.6" + process $proc$libresoc.v:93976$3921 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:86281.5-86281.29" + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:93977.5-93977.29" switch \initial - attribute \src "libresoc.v:86281.9-86281.17" + attribute \src "libresoc.v:93977.9-93977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 case - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:86335.3-86389.6" - process $proc$libresoc.v:86335$3793 + attribute \src "libresoc.v:94031.3-94085.6" + process $proc$libresoc.v:94031$3922 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:86336.5-86336.29" + assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:94032.5-94032.29" switch \initial - attribute \src "libresoc.v:86336.9-86336.17" + attribute \src "libresoc.v:94032.9-94032.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 case - assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'00 end sync always - update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] + update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end - attribute \src "libresoc.v:86390.3-86444.6" - process $proc$libresoc.v:86390$3794 + attribute \src "libresoc.v:94086.3-94140.6" + process $proc$libresoc.v:94086$3923 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:86391.5-86391.29" + assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:94087.5-94087.29" switch \initial - attribute \src "libresoc.v:86391.9-86391.17" + attribute \src "libresoc.v:94087.9-94087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 case - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end - attribute \src "libresoc.v:86445.3-86499.6" - process $proc$libresoc.v:86445$3795 + attribute \src "libresoc.v:94141.3-94195.6" + process $proc$libresoc.v:94141$3924 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:86446.5-86446.29" + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:94142.5-94142.29" switch \initial - attribute \src "libresoc.v:86446.9-86446.17" + attribute \src "libresoc.v:94142.9-94142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 case - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 end sync always - update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:94196.3-94250.6" + process $proc$libresoc.v:94196$3925 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:94197.5-94197.29" + switch \initial + attribute \src "libresoc.v:94197.9-94197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:94251.3-94305.6" + process $proc$libresoc.v:94251$3926 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:94252.5-94252.29" + switch \initial + attribute \src "libresoc.v:94252.9-94252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + end + attribute \src "libresoc.v:94306.3-94360.6" + process $proc$libresoc.v:94306$3927 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:94307.5-94307.29" + switch \initial + attribute \src "libresoc.v:94307.9-94307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:86505.1-89236.10" +attribute \src "libresoc.v:94366.1-98002.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:87278.3-87380.6" + attribute \src "libresoc.v:97383.3-97485.6" + wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:97486.3-97588.6" + wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:96147.3-96249.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:87690.3-87792.6" + attribute \src "libresoc.v:96559.3-96661.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:89029.3-89131.6" + attribute \src "libresoc.v:94808.3-94910.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:89132.3-89234.6" + attribute \src "libresoc.v:94911.3-95013.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:87175.3-87277.6" + attribute \src "libresoc.v:96044.3-96146.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:87587.3-87689.6" + attribute \src "libresoc.v:96456.3-96558.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:88514.3-88616.6" + attribute \src "libresoc.v:96971.3-97073.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:86763.3-86865.6" - wire width 12 $0\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:88617.3-88719.6" + attribute \src "libresoc.v:94705.3-94807.6" + wire width 14 $0\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:97589.3-97691.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:88720.3-88822.6" + attribute \src "libresoc.v:97692.3-97794.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:88823.3-88925.6" + attribute \src "libresoc.v:97795.3-97897.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:87896.3-87998.6" + attribute \src "libresoc.v:95838.3-95940.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:87381.3-87483.6" + attribute \src "libresoc.v:96250.3-96352.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:87484.3-87586.6" + attribute \src "libresoc.v:96353.3-96455.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:88102.3-88204.6" + attribute \src "libresoc.v:96868.3-96970.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:86866.3-86968.6" + attribute \src "libresoc.v:95632.3-95734.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:88308.3-88410.6" + attribute \src "libresoc.v:97177.3-97279.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:88926.3-89028.6" - wire width 2 $0\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:87072.3-87174.6" + attribute \src "libresoc.v:97898.3-98000.6" + wire width 3 $0\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:95941.3-96043.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:87999.3-88101.6" + attribute \src "libresoc.v:96765.3-96867.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:88411.3-88513.6" + attribute \src "libresoc.v:97280.3-97382.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:88205.3-88307.6" + attribute \src "libresoc.v:97074.3-97176.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:87793.3-87895.6" + attribute \src "libresoc.v:96662.3-96764.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:86969.3-87071.6" + attribute \src "libresoc.v:95426.3-95528.6" + wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:95529.3-95631.6" + wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:95014.3-95116.6" + wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:95117.3-95219.6" + wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:95220.3-95322.6" + wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:95323.3-95425.6" + wire width 3 $0\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:95735.3-95837.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:86506.7-86506.20" + attribute \src "libresoc.v:94367.7-94367.20" wire $0\initial[0:0] - attribute \src "libresoc.v:87278.3-87380.6" + attribute \src "libresoc.v:97383.3-97485.6" + wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:97486.3-97588.6" + wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:96147.3-96249.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:87690.3-87792.6" + attribute \src "libresoc.v:96559.3-96661.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:89029.3-89131.6" + attribute \src "libresoc.v:94808.3-94910.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:89132.3-89234.6" + attribute \src "libresoc.v:94911.3-95013.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:87175.3-87277.6" + attribute \src "libresoc.v:96044.3-96146.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:87587.3-87689.6" + attribute \src "libresoc.v:96456.3-96558.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:88514.3-88616.6" + attribute \src "libresoc.v:96971.3-97073.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:86763.3-86865.6" - wire width 12 $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:88617.3-88719.6" + attribute \src "libresoc.v:94705.3-94807.6" + wire width 14 $1\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:97589.3-97691.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:88720.3-88822.6" + attribute \src "libresoc.v:97692.3-97794.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:88823.3-88925.6" + attribute \src "libresoc.v:97795.3-97897.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:87896.3-87998.6" + attribute \src "libresoc.v:95838.3-95940.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:87381.3-87483.6" + attribute \src "libresoc.v:96250.3-96352.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:87484.3-87586.6" + attribute \src "libresoc.v:96353.3-96455.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:88102.3-88204.6" + attribute \src "libresoc.v:96868.3-96970.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:86866.3-86968.6" + attribute \src "libresoc.v:95632.3-95734.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:88308.3-88410.6" + attribute \src "libresoc.v:97177.3-97279.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:88926.3-89028.6" - wire width 2 $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:87072.3-87174.6" + attribute \src "libresoc.v:97898.3-98000.6" + wire width 3 $1\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:95941.3-96043.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:87999.3-88101.6" + attribute \src "libresoc.v:96765.3-96867.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:88411.3-88513.6" + attribute \src "libresoc.v:97280.3-97382.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:88205.3-88307.6" + attribute \src "libresoc.v:97074.3-97176.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:87793.3-87895.6" + attribute \src "libresoc.v:96662.3-96764.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:86969.3-87071.6" + attribute \src "libresoc.v:95426.3-95528.6" + wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:95529.3-95631.6" + wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:95014.3-95116.6" + wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:95117.3-95219.6" + wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:95220.3-95322.6" + wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:95323.3-95425.6" + wire width 3 $1\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:95735.3-95837.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub15_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub15_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 output 4 \dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub15_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -136834,24 +147656,26 @@ module \dec31_dec_sub15 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub15_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub15_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub15_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -136882,31 +147706,34 @@ module \dec31_dec_sub15 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub15_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub15_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub15_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -136922,14 +147749,14 @@ module \dec31_dec_sub15 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub15_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub15_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -137004,1695 +147831,1751 @@ module \dec31_dec_sub15 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub15_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub15_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub15_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub15_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub15_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub15_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub15_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub15_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub15_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub15_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub15_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub15_upd - attribute \src "libresoc.v:86506.7-86506.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub15_upd + attribute \src "libresoc.v:94367.7-94367.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:86506.7-86506.20" - process $proc$libresoc.v:86506$3821 + attribute \src "libresoc.v:94367.7-94367.20" + process $proc$libresoc.v:94367$3961 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:86763.3-86865.6" - process $proc$libresoc.v:86763$3797 + attribute \src "libresoc.v:94705.3-94807.6" + process $proc$libresoc.v:94705$3929 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:86764.5-86764.29" + assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:94706.5-94706.29" switch \initial - attribute \src "libresoc.v:86764.9-86764.17" + attribute \src "libresoc.v:94706.9-94706.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 case - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:86866.3-86968.6" - process $proc$libresoc.v:86866$3798 + attribute \src "libresoc.v:94808.3-94910.6" + process $proc$libresoc.v:94808$3930 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:86867.5-86867.29" + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:94809.5-94809.29" switch \initial - attribute \src "libresoc.v:86867.9-86867.17" + attribute \src "libresoc.v:94809.9-94809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 case - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:86969.3-87071.6" - process $proc$libresoc.v:86969$3799 + attribute \src "libresoc.v:94911.3-95013.6" + process $proc$libresoc.v:94911$3931 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:86970.5-86970.29" + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:94912.5-94912.29" switch \initial - attribute \src "libresoc.v:86970.9-86970.17" + attribute \src "libresoc.v:94912.9-94912.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:87072.3-87174.6" - process $proc$libresoc.v:87072$3800 + attribute \src "libresoc.v:95014.3-95116.6" + process $proc$libresoc.v:95014$3932 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:87073.5-87073.29" + assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:95015.5-95015.29" switch \initial - attribute \src "libresoc.v:87073.9-87073.17" + attribute \src "libresoc.v:95015.9-95015.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 case - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end - attribute \src "libresoc.v:87175.3-87277.6" - process $proc$libresoc.v:87175$3801 + attribute \src "libresoc.v:95117.3-95219.6" + process $proc$libresoc.v:95117$3933 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:87176.5-87176.29" + assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:95118.5-95118.29" switch \initial - attribute \src "libresoc.v:87176.9-87176.17" + attribute \src "libresoc.v:95118.9-95118.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 case - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] + update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end - attribute \src "libresoc.v:87278.3-87380.6" - process $proc$libresoc.v:87278$3802 + attribute \src "libresoc.v:95220.3-95322.6" + process $proc$libresoc.v:95220$3934 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:87279.5-87279.29" + assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:95221.5-95221.29" switch \initial - attribute \src "libresoc.v:87279.9-87279.17" + attribute \src "libresoc.v:95221.9-95221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] + update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end - attribute \src "libresoc.v:87381.3-87483.6" - process $proc$libresoc.v:87381$3803 + attribute \src "libresoc.v:95323.3-95425.6" + process $proc$libresoc.v:95323$3935 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:87382.5-87382.29" + assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:95324.5-95324.29" switch \initial - attribute \src "libresoc.v:87382.9-87382.17" + attribute \src "libresoc.v:95324.9-95324.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 case - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] + update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end - attribute \src "libresoc.v:87484.3-87586.6" - process $proc$libresoc.v:87484$3804 + attribute \src "libresoc.v:95426.3-95528.6" + process $proc$libresoc.v:95426$3936 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:87485.5-87485.29" + assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:95427.5-95427.29" switch \initial - attribute \src "libresoc.v:87485.9-87485.17" + attribute \src "libresoc.v:95427.9-95427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 case - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] + update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end - attribute \src "libresoc.v:87587.3-87689.6" - process $proc$libresoc.v:87587$3805 + attribute \src "libresoc.v:95529.3-95631.6" + process $proc$libresoc.v:95529$3937 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:87588.5-87588.29" + assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:95530.5-95530.29" switch \initial - attribute \src "libresoc.v:87588.9-87588.17" + attribute \src "libresoc.v:95530.9-95530.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] + update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end - attribute \src "libresoc.v:87690.3-87792.6" - process $proc$libresoc.v:87690$3806 + attribute \src "libresoc.v:95632.3-95734.6" + process $proc$libresoc.v:95632$3938 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:87691.5-87691.29" + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:95633.5-95633.29" switch \initial - attribute \src "libresoc.v:87691.9-87691.17" + attribute \src "libresoc.v:95633.9-95633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:87793.3-87895.6" - process $proc$libresoc.v:87793$3807 + attribute \src "libresoc.v:95735.3-95837.6" + process $proc$libresoc.v:95735$3939 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:87794.5-87794.29" + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:95736.5-95736.29" switch \initial - attribute \src "libresoc.v:87794.9-87794.17" + attribute \src "libresoc.v:95736.9-95736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 case - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 end sync always - update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:87896.3-87998.6" - process $proc$libresoc.v:87896$3808 + attribute \src "libresoc.v:95838.3-95940.6" + process $proc$libresoc.v:95838$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:87897.5-87897.29" + attribute \src "libresoc.v:95839.5-95839.29" switch \initial - attribute \src "libresoc.v:87897.9-87897.17" + attribute \src "libresoc.v:95839.9-95839.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -138828,4061 +149711,3099 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:87999.3-88101.6" - process $proc$libresoc.v:87999$3809 + attribute \src "libresoc.v:95941.3-96043.6" + process $proc$libresoc.v:95941$3941 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:88000.5-88000.29" + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:95942.5-95942.29" switch \initial - attribute \src "libresoc.v:88000.9-88000.17" + attribute \src "libresoc.v:95942.9-95942.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 case - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:88102.3-88204.6" - process $proc$libresoc.v:88102$3810 + attribute \src "libresoc.v:96044.3-96146.6" + process $proc$libresoc.v:96044$3942 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:88103.5-88103.29" + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:96045.5-96045.29" switch \initial - attribute \src "libresoc.v:88103.9-88103.17" + attribute \src "libresoc.v:96045.9-96045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:88205.3-88307.6" - process $proc$libresoc.v:88205$3811 + attribute \src "libresoc.v:96147.3-96249.6" + process $proc$libresoc.v:96147$3943 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:88206.5-88206.29" + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:96148.5-96148.29" switch \initial - attribute \src "libresoc.v:88206.9-88206.17" + attribute \src "libresoc.v:96148.9-96148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 case - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:88308.3-88410.6" - process $proc$libresoc.v:88308$3812 + attribute \src "libresoc.v:96250.3-96352.6" + process $proc$libresoc.v:96250$3944 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:88309.5-88309.29" + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:96251.5-96251.29" switch \initial - attribute \src "libresoc.v:88309.9-88309.17" + attribute \src "libresoc.v:96251.9-96251.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:88411.3-88513.6" - process $proc$libresoc.v:88411$3813 + attribute \src "libresoc.v:96353.3-96455.6" + process $proc$libresoc.v:96353$3945 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:88412.5-88412.29" + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:96354.5-96354.29" switch \initial - attribute \src "libresoc.v:88412.9-88412.17" + attribute \src "libresoc.v:96354.9-96354.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:88514.3-88616.6" - process $proc$libresoc.v:88514$3814 + attribute \src "libresoc.v:96456.3-96558.6" + process $proc$libresoc.v:96456$3946 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:88515.5-88515.29" + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:96457.5-96457.29" switch \initial - attribute \src "libresoc.v:88515.9-88515.17" + attribute \src "libresoc.v:96457.9-96457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub15_form[4:0] 5'00000 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:88617.3-88719.6" - process $proc$libresoc.v:88617$3815 + attribute \src "libresoc.v:96559.3-96661.6" + process $proc$libresoc.v:96559$3947 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:88618.5-88618.29" + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:96560.5-96560.29" switch \initial - attribute \src "libresoc.v:88618.9-88618.17" + attribute \src "libresoc.v:96560.9-96560.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub15_br[0:0] 1'0 case - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub15_br[0:0] 1'0 end sync always - update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:88720.3-88822.6" - process $proc$libresoc.v:88720$3816 + attribute \src "libresoc.v:96662.3-96764.6" + process $proc$libresoc.v:96662$3948 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:88721.5-88721.29" + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:96663.5-96663.29" switch \initial - attribute \src "libresoc.v:88721.9-88721.17" + attribute \src "libresoc.v:96663.9-96663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:88823.3-88925.6" - process $proc$libresoc.v:88823$3817 + attribute \src "libresoc.v:96765.3-96867.6" + process $proc$libresoc.v:96765$3949 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:88824.5-88824.29" + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:96766.5-96766.29" switch \initial - attribute \src "libresoc.v:88824.9-88824.17" + attribute \src "libresoc.v:96766.9-96766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:88926.3-89028.6" - process $proc$libresoc.v:88926$3818 + attribute \src "libresoc.v:96868.3-96970.6" + process $proc$libresoc.v:96868$3950 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:88927.5-88927.29" + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:96869.5-96869.29" switch \initial - attribute \src "libresoc.v:88927.9-88927.17" + attribute \src "libresoc.v:96869.9-96869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:89029.3-89131.6" - process $proc$libresoc.v:89029$3819 + attribute \src "libresoc.v:96971.3-97073.6" + process $proc$libresoc.v:96971$3951 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:89030.5-89030.29" + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:96972.5-96972.29" switch \initial - attribute \src "libresoc.v:89030.9-89030.17" + attribute \src "libresoc.v:96972.9-96972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 case - assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub15_form[4:0] 5'00000 end sync always - update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:89132.3-89234.6" - process $proc$libresoc.v:89132$3820 + attribute \src "libresoc.v:97074.3-97176.6" + process $proc$libresoc.v:97074$3952 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:89133.5-89133.29" + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:97075.5-97075.29" switch \initial - attribute \src "libresoc.v:89133.9-89133.17" + attribute \src "libresoc.v:97075.9-97075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:89240.1-89739.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" -attribute \generator "nMigen" -module \dec31_dec_sub16 - attribute \src "libresoc.v:89548.3-89557.6" - wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:89588.3-89597.6" - wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:89718.3-89727.6" - wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89728.3-89737.6" - wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:89538.3-89547.6" - wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:89578.3-89587.6" - wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:89668.3-89677.6" - wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:89498.3-89507.6" - wire width 12 $0\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:89678.3-89687.6" - wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:89688.3-89697.6" - wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:89698.3-89707.6" - wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:89608.3-89617.6" - wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:89558.3-89567.6" - wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:89568.3-89577.6" - wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:89628.3-89637.6" - wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:89508.3-89517.6" - wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:89648.3-89657.6" - wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:89708.3-89717.6" - wire width 2 $0\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:89528.3-89537.6" - wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:89618.3-89627.6" - wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:89658.3-89667.6" - wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:89638.3-89647.6" - wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:89598.3-89607.6" - wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:89518.3-89527.6" - wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:89241.7-89241.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:89548.3-89557.6" - wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:89588.3-89597.6" - wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:89718.3-89727.6" - wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89728.3-89737.6" - wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:89538.3-89547.6" - wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:89578.3-89587.6" - wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:89668.3-89677.6" - wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:89498.3-89507.6" - wire width 12 $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:89678.3-89687.6" - wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:89688.3-89697.6" - wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:89698.3-89707.6" - wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:89608.3-89617.6" - wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:89558.3-89567.6" - wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:89568.3-89577.6" - wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:89628.3-89637.6" - wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:89508.3-89517.6" - wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:89648.3-89657.6" - wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:89708.3-89717.6" - wire width 2 $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:89528.3-89537.6" - wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:89618.3-89627.6" - wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:89658.3-89667.6" - wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:89638.3-89647.6" - wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:89598.3-89607.6" - wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:89518.3-89527.6" - wire width 2 $1\dec31_dec_sub16_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub16_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub16_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub16_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub16_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub16_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub16_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub16_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub16_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub16_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub16_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub16_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub16_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub16_upd - attribute \src "libresoc.v:89241.7-89241.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:89241.7-89241.20" - process $proc$libresoc.v:89241$3846 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:89498.3-89507.6" - process $proc$libresoc.v:89498$3822 + attribute \src "libresoc.v:97177.3-97279.6" + process $proc$libresoc.v:97177$3953 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:89499.5-89499.29" + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:97178.5-97178.29" switch \initial - attribute \src "libresoc.v:89499.9-89499.17" + attribute \src "libresoc.v:97178.9-97178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] - end - attribute \src "libresoc.v:89508.3-89517.6" - process $proc$libresoc.v:89508$3823 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:89509.5-89509.29" - switch \initial - attribute \src "libresoc.v:89509.9-89509.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] - end - attribute \src "libresoc.v:89518.3-89527.6" - process $proc$libresoc.v:89518$3824 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:89519.5-89519.29" - switch \initial - attribute \src "libresoc.v:89519.9-89519.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub16_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub16_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] - end - attribute \src "libresoc.v:89528.3-89537.6" - process $proc$libresoc.v:89528$3825 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:89529.5-89529.29" - switch \initial - attribute \src "libresoc.v:89529.9-89529.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] - end - attribute \src "libresoc.v:89538.3-89547.6" - process $proc$libresoc.v:89538$3826 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:89539.5-89539.29" - switch \initial - attribute \src "libresoc.v:89539.9-89539.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] - end - attribute \src "libresoc.v:89548.3-89557.6" - process $proc$libresoc.v:89548$3827 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:89549.5-89549.29" - switch \initial - attribute \src "libresoc.v:89549.9-89549.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 - case - assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] - end - attribute \src "libresoc.v:89558.3-89567.6" - process $proc$libresoc.v:89558$3828 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:89559.5-89559.29" - switch \initial - attribute \src "libresoc.v:89559.9-89559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] - end - attribute \src "libresoc.v:89568.3-89577.6" - process $proc$libresoc.v:89568$3829 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:89569.5-89569.29" - switch \initial - attribute \src "libresoc.v:89569.9-89569.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] - end - attribute \src "libresoc.v:89578.3-89587.6" - process $proc$libresoc.v:89578$3830 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:89579.5-89579.29" - switch \initial - attribute \src "libresoc.v:89579.9-89579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] - end - attribute \src "libresoc.v:89588.3-89597.6" - process $proc$libresoc.v:89588$3831 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:89589.5-89589.29" - switch \initial - attribute \src "libresoc.v:89589.9-89589.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub16_br[0:0] 1'0 - case - assign $1\dec31_dec_sub16_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] - end - attribute \src "libresoc.v:89598.3-89607.6" - process $proc$libresoc.v:89598$3832 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:89599.5-89599.29" - switch \initial - attribute \src "libresoc.v:89599.9-89599.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] - end - attribute \src "libresoc.v:89608.3-89617.6" - process $proc$libresoc.v:89608$3833 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:89609.5-89609.29" - switch \initial - attribute \src "libresoc.v:89609.9-89609.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 - case - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] - end - attribute \src "libresoc.v:89618.3-89627.6" - process $proc$libresoc.v:89618$3834 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:89619.5-89619.29" - switch \initial - attribute \src "libresoc.v:89619.9-89619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] - end - attribute \src "libresoc.v:89628.3-89637.6" - process $proc$libresoc.v:89628$3835 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:89629.5-89629.29" - switch \initial - attribute \src "libresoc.v:89629.9-89629.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] - end - attribute \src "libresoc.v:89638.3-89647.6" - process $proc$libresoc.v:89638$3836 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:89639.5-89639.29" - switch \initial - attribute \src "libresoc.v:89639.9-89639.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] - end - attribute \src "libresoc.v:89648.3-89657.6" - process $proc$libresoc.v:89648$3837 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:89649.5-89649.29" - switch \initial - attribute \src "libresoc.v:89649.9-89649.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub16_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub16_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] - end - attribute \src "libresoc.v:89658.3-89667.6" - process $proc$libresoc.v:89658$3838 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:89659.5-89659.29" - switch \initial - attribute \src "libresoc.v:89659.9-89659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] - end - attribute \src "libresoc.v:89668.3-89677.6" - process $proc$libresoc.v:89668$3839 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:89669.5-89669.29" - switch \initial - attribute \src "libresoc.v:89669.9-89669.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub16_form[4:0] 5'01010 - case - assign $1\dec31_dec_sub16_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] - end - attribute \src "libresoc.v:89678.3-89687.6" - process $proc$libresoc.v:89678$3840 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:89679.5-89679.29" - switch \initial - attribute \src "libresoc.v:89679.9-89679.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10010 assign { } { } - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] - end - attribute \src "libresoc.v:89688.3-89697.6" - process $proc$libresoc.v:89688$3841 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:89689.5-89689.29" - switch \initial - attribute \src "libresoc.v:89689.9-89689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] - end - attribute \src "libresoc.v:89698.3-89707.6" - process $proc$libresoc.v:89698$3842 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:89699.5-89699.29" - switch \initial - attribute \src "libresoc.v:89699.9-89699.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] - end - attribute \src "libresoc.v:89708.3-89717.6" - process $proc$libresoc.v:89708$3843 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:89709.5-89709.29" - switch \initial - attribute \src "libresoc.v:89709.9-89709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] - end - attribute \src "libresoc.v:89718.3-89727.6" - process $proc$libresoc.v:89718$3844 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89719.5-89719.29" - switch \initial - attribute \src "libresoc.v:89719.9-89719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 - case - assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] - end - attribute \src "libresoc.v:89728.3-89737.6" - process $proc$libresoc.v:89728$3845 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:89729.5-89729.29" - switch \initial - attribute \src "libresoc.v:89729.9-89729.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 - case - assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:89743.1-90530.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" -attribute \generator "nMigen" -module \dec31_dec_sub18 - attribute \src "libresoc.v:90111.3-90132.6" - wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:90199.3-90220.6" - wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:90485.3-90506.6" - wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:90507.3-90528.6" - wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:90089.3-90110.6" - wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:90177.3-90198.6" - wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:90375.3-90396.6" - wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:90001.3-90022.6" - wire width 12 $0\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:90397.3-90418.6" - wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:90419.3-90440.6" - wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:90441.3-90462.6" - wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:90243.3-90264.6" - wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:90133.3-90154.6" - wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:90155.3-90176.6" - wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:90287.3-90308.6" - wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:90023.3-90044.6" - wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:90331.3-90352.6" - wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:90463.3-90484.6" - wire width 2 $0\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:90067.3-90088.6" - wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:90265.3-90286.6" - wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:90353.3-90374.6" - wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:90309.3-90330.6" - wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:90221.3-90242.6" - wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:90045.3-90066.6" - wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:89744.7-89744.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:90111.3-90132.6" - wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:90199.3-90220.6" - wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:90485.3-90506.6" - wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:90507.3-90528.6" - wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:90089.3-90110.6" - wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:90177.3-90198.6" - wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:90375.3-90396.6" - wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:90001.3-90022.6" - wire width 12 $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:90397.3-90418.6" - wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:90419.3-90440.6" - wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:90441.3-90462.6" - wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:90243.3-90264.6" - wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:90133.3-90154.6" - wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:90155.3-90176.6" - wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:90287.3-90308.6" - wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:90023.3-90044.6" - wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:90331.3-90352.6" - wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:90463.3-90484.6" - wire width 2 $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:90067.3-90088.6" - wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:90265.3-90286.6" - wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:90353.3-90374.6" - wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:90309.3-90330.6" - wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:90221.3-90242.6" - wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:90045.3-90066.6" - wire width 2 $1\dec31_dec_sub18_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub18_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub18_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub18_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub18_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub18_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub18_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub18_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub18_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub18_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub18_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub18_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub18_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub18_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub18_upd - attribute \src "libresoc.v:89744.7-89744.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:89744.7-89744.20" - process $proc$libresoc.v:89744$3871 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:90001.3-90022.6" - process $proc$libresoc.v:90001$3847 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:90002.5-90002.29" - switch \initial - attribute \src "libresoc.v:90002.9-90002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 case - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 end sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:90023.3-90044.6" - process $proc$libresoc.v:90023$3848 + attribute \src "libresoc.v:97280.3-97382.6" + process $proc$libresoc.v:97280$3954 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:90024.5-90024.29" + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:97281.5-97281.29" switch \initial - attribute \src "libresoc.v:90024.9-90024.17" + attribute \src "libresoc.v:97281.9-97281.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] - end - attribute \src "libresoc.v:90045.3-90066.6" - process $proc$libresoc.v:90045$3849 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:90046.5-90046.29" - switch \initial - attribute \src "libresoc.v:90046.9-90046.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] - end - attribute \src "libresoc.v:90067.3-90088.6" - process $proc$libresoc.v:90067$3850 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:90068.5-90068.29" - switch \initial - attribute \src "libresoc.v:90068.9-90068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] - end - attribute \src "libresoc.v:90089.3-90110.6" - process $proc$libresoc.v:90089$3851 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:90090.5-90090.29" - switch \initial - attribute \src "libresoc.v:90090.9-90090.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10010 assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] - end - attribute \src "libresoc.v:90111.3-90132.6" - process $proc$libresoc.v:90111$3852 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:90112.5-90112.29" - switch \initial - attribute \src "libresoc.v:90112.9-90112.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 case - assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:90133.3-90154.6" - process $proc$libresoc.v:90133$3853 + attribute \src "libresoc.v:97383.3-97485.6" + process $proc$libresoc.v:97383$3955 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:90134.5-90134.29" + assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:97384.5-97384.29" switch \initial - attribute \src "libresoc.v:90134.9-90134.17" + attribute \src "libresoc.v:97384.9-97384.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] - end - attribute \src "libresoc.v:90155.3-90176.6" - process $proc$libresoc.v:90155$3854 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:90156.5-90156.29" - switch \initial - attribute \src "libresoc.v:90156.9-90156.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] - end - attribute \src "libresoc.v:90177.3-90198.6" - process $proc$libresoc.v:90177$3855 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:90178.5-90178.29" - switch \initial - attribute \src "libresoc.v:90178.9-90178.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] - end - attribute \src "libresoc.v:90199.3-90220.6" - process $proc$libresoc.v:90199$3856 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:90200.5-90200.29" - switch \initial - attribute \src "libresoc.v:90200.9-90200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10010 assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - case - assign $1\dec31_dec_sub18_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] - end - attribute \src "libresoc.v:90221.3-90242.6" - process $proc$libresoc.v:90221$3857 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:90222.5-90222.29" - switch \initial - attribute \src "libresoc.v:90222.9-90222.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 case - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'00 end sync always - update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end - attribute \src "libresoc.v:90243.3-90264.6" - process $proc$libresoc.v:90243$3858 + attribute \src "libresoc.v:97486.3-97588.6" + process $proc$libresoc.v:97486$3956 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:90244.5-90244.29" + assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:97487.5-97487.29" switch \initial - attribute \src "libresoc.v:90244.9-90244.17" + attribute \src "libresoc.v:97487.9-97487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] - end - attribute \src "libresoc.v:90265.3-90286.6" - process $proc$libresoc.v:90265$3859 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:90266.5-90266.29" - switch \initial - attribute \src "libresoc.v:90266.9-90266.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] - end - attribute \src "libresoc.v:90287.3-90308.6" - process $proc$libresoc.v:90287$3860 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:90288.5-90288.29" - switch \initial - attribute \src "libresoc.v:90288.9-90288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] - end - attribute \src "libresoc.v:90309.3-90330.6" - process $proc$libresoc.v:90309$3861 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:90310.5-90310.29" - switch \initial - attribute \src "libresoc.v:90310.9-90310.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10010 assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] - end - attribute \src "libresoc.v:90331.3-90352.6" - process $proc$libresoc.v:90331$3862 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:90332.5-90332.29" - switch \initial - attribute \src "libresoc.v:90332.9-90332.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 case - assign $1\dec31_dec_sub18_lk[0:0] 1'0 + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end - attribute \src "libresoc.v:90353.3-90374.6" - process $proc$libresoc.v:90353$3863 + attribute \src "libresoc.v:97589.3-97691.6" + process $proc$libresoc.v:97589$3957 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:90354.5-90354.29" + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:97590.5-97590.29" switch \initial - attribute \src "libresoc.v:90354.9-90354.17" + attribute \src "libresoc.v:97590.9-97590.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] - end - attribute \src "libresoc.v:90375.3-90396.6" - process $proc$libresoc.v:90375$3864 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:90376.5-90376.29" - switch \initial - attribute \src "libresoc.v:90376.9-90376.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 case - assign $1\dec31_dec_sub18_form[4:0] 5'00000 + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 end sync always - update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:90397.3-90418.6" - process $proc$libresoc.v:90397$3865 + attribute \src "libresoc.v:97692.3-97794.6" + process $proc$libresoc.v:97692$3958 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:90398.5-90398.29" + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:97693.5-97693.29" switch \initial - attribute \src "libresoc.v:90398.9-90398.17" + attribute \src "libresoc.v:97693.9-97693.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] - end - attribute \src "libresoc.v:90419.3-90440.6" - process $proc$libresoc.v:90419$3866 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:90420.5-90420.29" - switch \initial - attribute \src "libresoc.v:90420.9-90420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 case - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 end sync always - update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:90441.3-90462.6" - process $proc$libresoc.v:90441$3867 + attribute \src "libresoc.v:97795.3-97897.6" + process $proc$libresoc.v:97795$3959 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:90442.5-90442.29" + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:97796.5-97796.29" switch \initial - attribute \src "libresoc.v:90442.9-90442.17" + attribute \src "libresoc.v:97796.9-97796.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] - end - attribute \src "libresoc.v:90463.3-90484.6" - process $proc$libresoc.v:90463$3868 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:90464.5-90464.29" - switch \initial - attribute \src "libresoc.v:90464.9-90464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 case - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 end sync always - update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:90485.3-90506.6" - process $proc$libresoc.v:90485$3869 + attribute \src "libresoc.v:97898.3-98000.6" + process $proc$libresoc.v:97898$3960 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:90486.5-90486.29" + assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:97899.5-97899.29" switch \initial - attribute \src "libresoc.v:90486.9-90486.17" + attribute \src "libresoc.v:97899.9-97899.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] - end - attribute \src "libresoc.v:90507.3-90528.6" - process $proc$libresoc.v:90507$3870 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:90508.5-90508.29" - switch \initial - attribute \src "libresoc.v:90508.9-90508.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:90534.1-91249.10" +attribute \src "libresoc.v:98006.1-98666.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" -module \dec31_dec_sub19 - attribute \src "libresoc.v:90887.3-90905.6" - wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:90963.3-90981.6" - wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:91210.3-91228.6" - wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:91229.3-91247.6" - wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:90868.3-90886.6" - wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:90944.3-90962.6" - wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:91115.3-91133.6" - wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:90792.3-90810.6" - wire width 12 $0\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:91134.3-91152.6" - wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:91153.3-91171.6" - wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:91172.3-91190.6" - wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:91001.3-91019.6" - wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:90906.3-90924.6" - wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:90925.3-90943.6" - wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:91039.3-91057.6" - wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:90811.3-90829.6" - wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:91077.3-91095.6" - wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:91191.3-91209.6" - wire width 2 $0\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:90849.3-90867.6" - wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:91020.3-91038.6" - wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:91096.3-91114.6" - wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:91058.3-91076.6" - wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:90982.3-91000.6" - wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:90830.3-90848.6" - wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:90535.7-90535.20" +module \dec31_dec_sub16 + attribute \src "libresoc.v:98605.3-98614.6" + wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:98615.3-98624.6" + wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:98485.3-98494.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:98525.3-98534.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:98355.3-98364.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:98365.3-98374.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:98475.3-98484.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:98515.3-98524.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:98565.3-98574.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:98345.3-98354.6" + wire width 14 $0\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:98625.3-98634.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:98635.3-98644.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:98645.3-98654.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:98455.3-98464.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:98495.3-98504.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:98505.3-98514.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:98555.3-98564.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:98435.3-98444.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:98585.3-98594.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:98655.3-98664.6" + wire width 3 $0\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:98465.3-98474.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:98545.3-98554.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:98595.3-98604.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:98575.3-98584.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:98535.3-98544.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:98415.3-98424.6" + wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:98425.3-98434.6" + wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:98375.3-98384.6" + wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:98385.3-98394.6" + wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:98395.3-98404.6" + wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:98405.3-98414.6" + wire width 3 $0\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:98445.3-98454.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:98007.7-98007.20" wire $0\initial[0:0] - attribute \src "libresoc.v:90887.3-90905.6" - wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:90963.3-90981.6" - wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:91210.3-91228.6" - wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:91229.3-91247.6" - wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:90868.3-90886.6" - wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:90944.3-90962.6" - wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:91115.3-91133.6" - wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:90792.3-90810.6" - wire width 12 $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:91134.3-91152.6" - wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:91153.3-91171.6" - wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:91172.3-91190.6" - wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:91001.3-91019.6" - wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:90906.3-90924.6" - wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:90925.3-90943.6" - wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:91039.3-91057.6" - wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:90811.3-90829.6" - wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:91077.3-91095.6" - wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:91191.3-91209.6" - wire width 2 $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:90849.3-90867.6" - wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:91020.3-91038.6" - wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:91096.3-91114.6" - wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:91058.3-91076.6" - wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:90982.3-91000.6" - wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:90830.3-90848.6" - wire width 2 $1\dec31_dec_sub19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub19_br + attribute \src "libresoc.v:98605.3-98614.6" + wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:98615.3-98624.6" + wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:98485.3-98494.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:98525.3-98534.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:98355.3-98364.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:98365.3-98374.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:98475.3-98484.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:98515.3-98524.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:98565.3-98574.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:98345.3-98354.6" + wire width 14 $1\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:98625.3-98634.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:98635.3-98644.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:98645.3-98654.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:98455.3-98464.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:98495.3-98504.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:98505.3-98514.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:98555.3-98564.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:98435.3-98444.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:98585.3-98594.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:98655.3-98664.6" + wire width 3 $1\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:98465.3-98474.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:98545.3-98554.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:98595.3-98604.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:98575.3-98584.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:98535.3-98544.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:98415.3-98424.6" + wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:98425.3-98434.6" + wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:98375.3-98384.6" + wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:98385.3-98394.6" + wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:98395.3-98404.6" + wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:98405.3-98414.6" + wire width 3 $1\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:98445.3-98454.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub16_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub16_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -142891,24 +152812,26 @@ module \dec31_dec_sub19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub19_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub19_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -142939,31 +152862,34 @@ module \dec31_dec_sub19 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub19_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub16_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub19_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -142979,14 +152905,14 @@ module \dec31_dec_sub19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub19_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub19_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -143061,1015 +152987,1011 @@ module \dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub19_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub16_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub19_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub16_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub16_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub16_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub16_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub16_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub16_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub19_upd - attribute \src "libresoc.v:90535.7-90535.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub16_upd + attribute \src "libresoc.v:98007.7-98007.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:90535.7-90535.20" - process $proc$libresoc.v:90535$3896 + attribute \src "libresoc.v:98007.7-98007.20" + process $proc$libresoc.v:98007$3994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90792.3-90810.6" - process $proc$libresoc.v:90792$3872 + attribute \src "libresoc.v:98345.3-98354.6" + process $proc$libresoc.v:98345$3962 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:90793.5-90793.29" + assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:98346.5-98346.29" switch \initial - attribute \src "libresoc.v:90793.9-90793.17" + attribute \src "libresoc.v:98346.9-98346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + assign $1\dec31_dec_sub16_function_unit[13:0] 14'00000001000000 case - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub16_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:90811.3-90829.6" - process $proc$libresoc.v:90811$3873 + attribute \src "libresoc.v:98355.3-98364.6" + process $proc$libresoc.v:98355$3963 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:90812.5-90812.29" + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:98356.5-98356.29" switch \initial - attribute \src "libresoc.v:90812.9-90812.17" + attribute \src "libresoc.v:98356.9-98356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 case - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:90830.3-90848.6" - process $proc$libresoc.v:90830$3874 + attribute \src "libresoc.v:98365.3-98374.6" + process $proc$libresoc.v:98365$3964 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:90831.5-90831.29" + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:98366.5-98366.29" switch \initial - attribute \src "libresoc.v:90831.9-90831.17" + attribute \src "libresoc.v:98366.9-98366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 case - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:90849.3-90867.6" - process $proc$libresoc.v:90849$3875 + attribute \src "libresoc.v:98375.3-98384.6" + process $proc$libresoc.v:98375$3965 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:90850.5-90850.29" + assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:98376.5-98376.29" switch \initial - attribute \src "libresoc.v:90850.9-90850.17" + attribute \src "libresoc.v:98376.9-98376.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub16_sv_in1[2:0] 3'010 case - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub16_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end - attribute \src "libresoc.v:90868.3-90886.6" - process $proc$libresoc.v:90868$3876 + attribute \src "libresoc.v:98385.3-98394.6" + process $proc$libresoc.v:98385$3966 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:90869.5-90869.29" + assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:98386.5-98386.29" switch \initial - attribute \src "libresoc.v:90869.9-90869.17" + attribute \src "libresoc.v:98386.9-98386.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub16_sv_in2[2:0] 3'000 case - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub16_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end - attribute \src "libresoc.v:90887.3-90905.6" - process $proc$libresoc.v:90887$3877 + attribute \src "libresoc.v:98395.3-98404.6" + process $proc$libresoc.v:98395$3967 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:90888.5-90888.29" + assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:98396.5-98396.29" switch \initial - attribute \src "libresoc.v:90888.9-90888.17" + attribute \src "libresoc.v:98396.9-98396.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + assign $1\dec31_dec_sub16_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub16_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end - attribute \src "libresoc.v:90906.3-90924.6" - process $proc$libresoc.v:90906$3878 + attribute \src "libresoc.v:98405.3-98414.6" + process $proc$libresoc.v:98405$3968 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:90907.5-90907.29" + assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:98406.5-98406.29" switch \initial - attribute \src "libresoc.v:90907.9-90907.17" + attribute \src "libresoc.v:98406.9-98406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub16_sv_out[2:0] 3'000 case - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub16_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end - attribute \src "libresoc.v:90925.3-90943.6" - process $proc$libresoc.v:90925$3879 + attribute \src "libresoc.v:98415.3-98424.6" + process $proc$libresoc.v:98415$3969 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:90926.5-90926.29" + assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:98416.5-98416.29" switch \initial - attribute \src "libresoc.v:90926.9-90926.17" + attribute \src "libresoc.v:98416.9-98416.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub16_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub16_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end - attribute \src "libresoc.v:90944.3-90962.6" - process $proc$libresoc.v:90944$3880 + attribute \src "libresoc.v:98425.3-98434.6" + process $proc$libresoc.v:98425$3970 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:90945.5-90945.29" + assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:98426.5-98426.29" switch \initial - attribute \src "libresoc.v:90945.9-90945.17" + attribute \src "libresoc.v:98426.9-98426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub16_sv_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub16_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end - attribute \src "libresoc.v:90963.3-90981.6" - process $proc$libresoc.v:90963$3881 + attribute \src "libresoc.v:98435.3-98444.6" + process $proc$libresoc.v:98435$3971 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:90964.5-90964.29" + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:98436.5-98436.29" switch \initial - attribute \src "libresoc.v:90964.9-90964.17" + attribute \src "libresoc.v:98436.9-98436.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub19_br[0:0] 1'0 + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:90982.3-91000.6" - process $proc$libresoc.v:90982$3882 + attribute \src "libresoc.v:98445.3-98454.6" + process $proc$libresoc.v:98445$3972 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:90983.5-90983.29" + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:98446.5-98446.29" switch \initial - attribute \src "libresoc.v:90983.9-90983.17" + attribute \src "libresoc.v:98446.9-98446.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub16_upd[1:0] 2'00 case - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub16_upd[1:0] 2'00 end sync always - update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:91001.3-91019.6" - process $proc$libresoc.v:91001$3883 + attribute \src "libresoc.v:98455.3-98464.6" + process $proc$libresoc.v:98455$3973 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:91002.5-91002.29" + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:98456.5-98456.29" switch \initial - attribute \src "libresoc.v:91002.9-91002.17" + attribute \src "libresoc.v:98456.9-98456.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 case - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:91020.3-91038.6" - process $proc$libresoc.v:91020$3884 + attribute \src "libresoc.v:98465.3-98474.6" + process $proc$libresoc.v:98465$3974 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:91021.5-91021.29" + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:98466.5-98466.29" switch \initial - attribute \src "libresoc.v:91021.9-91021.17" + attribute \src "libresoc.v:98466.9-98466.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 case - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:91039.3-91057.6" - process $proc$libresoc.v:91039$3885 + attribute \src "libresoc.v:98475.3-98484.6" + process $proc$libresoc.v:98475$3975 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:91040.5-91040.29" + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:98476.5-98476.29" switch \initial - attribute \src "libresoc.v:91040.9-91040.17" + attribute \src "libresoc.v:98476.9-98476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:91058.3-91076.6" - process $proc$libresoc.v:91058$3886 + attribute \src "libresoc.v:98485.3-98494.6" + process $proc$libresoc.v:98485$3976 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:91059.5-91059.29" + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:98486.5-98486.29" switch \initial - attribute \src "libresoc.v:91059.9-91059.17" + attribute \src "libresoc.v:98486.9-98486.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 case - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:91077.3-91095.6" - process $proc$libresoc.v:91077$3887 + attribute \src "libresoc.v:98495.3-98504.6" + process $proc$libresoc.v:98495$3977 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:91078.5-91078.29" + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:98496.5-98496.29" switch \initial - attribute \src "libresoc.v:91078.9-91078.17" + attribute \src "libresoc.v:98496.9-98496.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub19_lk[0:0] 1'0 + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:91096.3-91114.6" - process $proc$libresoc.v:91096$3888 + attribute \src "libresoc.v:98505.3-98514.6" + process $proc$libresoc.v:98505$3978 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:91097.5-91097.29" + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:98506.5-98506.29" switch \initial - attribute \src "libresoc.v:91097.9-91097.17" + attribute \src "libresoc.v:98506.9-98506.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:91115.3-91133.6" - process $proc$libresoc.v:91115$3889 + attribute \src "libresoc.v:98515.3-98524.6" + process $proc$libresoc.v:98515$3979 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:91116.5-91116.29" + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:98516.5-98516.29" switch \initial - attribute \src "libresoc.v:91116.9-91116.17" + attribute \src "libresoc.v:98516.9-98516.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub19_form[4:0] 5'00000 + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:91134.3-91152.6" - process $proc$libresoc.v:91134$3890 + attribute \src "libresoc.v:98525.3-98534.6" + process $proc$libresoc.v:98525$3980 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:91135.5-91135.29" + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:98526.5-98526.29" switch \initial - attribute \src "libresoc.v:91135.9-91135.17" + attribute \src "libresoc.v:98526.9-98526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub16_br[0:0] 1'0 case - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub16_br[0:0] 1'0 end sync always - update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:91153.3-91171.6" - process $proc$libresoc.v:91153$3891 + attribute \src "libresoc.v:98535.3-98544.6" + process $proc$libresoc.v:98535$3981 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:91154.5-91154.29" + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:98536.5-98536.29" switch \initial - attribute \src "libresoc.v:91154.9-91154.17" + attribute \src "libresoc.v:98536.9-98536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:91172.3-91190.6" - process $proc$libresoc.v:91172$3892 + attribute \src "libresoc.v:98545.3-98554.6" + process $proc$libresoc.v:98545$3982 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:91173.5-91173.29" + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:98546.5-98546.29" switch \initial - attribute \src "libresoc.v:91173.9-91173.17" + attribute \src "libresoc.v:98546.9-98546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:91191.3-91209.6" - process $proc$libresoc.v:91191$3893 + attribute \src "libresoc.v:98555.3-98564.6" + process $proc$libresoc.v:98555$3983 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:91192.5-91192.29" + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:98556.5-98556.29" switch \initial - attribute \src "libresoc.v:91192.9-91192.17" + attribute \src "libresoc.v:98556.9-98556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "libresoc.v:98565.3-98574.6" + process $proc$libresoc.v:98565$3984 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:98566.5-98566.29" + switch \initial + attribute \src "libresoc.v:98566.9-98566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "libresoc.v:98575.3-98584.6" + process $proc$libresoc.v:98575$3985 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:98576.5-98576.29" + switch \initial + attribute \src "libresoc.v:98576.9-98576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:91210.3-91228.6" - process $proc$libresoc.v:91210$3894 + attribute \src "libresoc.v:98585.3-98594.6" + process $proc$libresoc.v:98585$3986 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:91211.5-91211.29" + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:98586.5-98586.29" switch \initial - attribute \src "libresoc.v:91211.9-91211.17" + attribute \src "libresoc.v:98586.9-98586.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "libresoc.v:98595.3-98604.6" + process $proc$libresoc.v:98595$3987 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:98596.5-98596.29" + switch \initial + attribute \src "libresoc.v:98596.9-98596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "libresoc.v:98605.3-98614.6" + process $proc$libresoc.v:98605$3988 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:98606.5-98606.29" + switch \initial + attribute \src "libresoc.v:98606.9-98606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub16_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub16_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] + end + attribute \src "libresoc.v:98615.3-98624.6" + process $proc$libresoc.v:98615$3989 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:98616.5-98616.29" + switch \initial + attribute \src "libresoc.v:98616.9-98616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub16_SV_Ptype[1:0] 2'10 case - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub16_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end - attribute \src "libresoc.v:91229.3-91247.6" - process $proc$libresoc.v:91229$3895 + attribute \src "libresoc.v:98625.3-98634.6" + process $proc$libresoc.v:98625$3990 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:91230.5-91230.29" + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:98626.5-98626.29" switch \initial - attribute \src "libresoc.v:91230.9-91230.17" + attribute \src "libresoc.v:98626.9-98626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "libresoc.v:98635.3-98644.6" + process $proc$libresoc.v:98635$3991 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:98636.5-98636.29" + switch \initial + attribute \src "libresoc.v:98636.9-98636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "libresoc.v:98645.3-98654.6" + process $proc$libresoc.v:98645$3992 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:98646.5-98646.29" + switch \initial + attribute \src "libresoc.v:98646.9-98646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "libresoc.v:98655.3-98664.6" + process $proc$libresoc.v:98655$3993 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:98656.5-98656.29" + switch \initial + attribute \src "libresoc.v:98656.9-98656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub16_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub16_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:91253.1-92112.10" +attribute \src "libresoc.v:98670.1-99714.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" -module \dec31_dec_sub20 - attribute \src "libresoc.v:91636.3-91660.6" - wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:91736.3-91760.6" - wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:92061.3-92085.6" - wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:92086.3-92110.6" - wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:91611.3-91635.6" - wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:91711.3-91735.6" - wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:91936.3-91960.6" - wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:91511.3-91535.6" - wire width 12 $0\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:91961.3-91985.6" - wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:91986.3-92010.6" - wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:92011.3-92035.6" - wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:91786.3-91810.6" - wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:91661.3-91685.6" - wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:91686.3-91710.6" - wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:91836.3-91860.6" - wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:91536.3-91560.6" - wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:91886.3-91910.6" - wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:92036.3-92060.6" - wire width 2 $0\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:91586.3-91610.6" - wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:91811.3-91835.6" - wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:91911.3-91935.6" - wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:91861.3-91885.6" - wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:91761.3-91785.6" - wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:91561.3-91585.6" - wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:91254.7-91254.20" +module \dec31_dec_sub18 + attribute \src "libresoc.v:99581.3-99602.6" + wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:99603.3-99624.6" + wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:99317.3-99338.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:99405.3-99426.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:99031.3-99052.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:99053.3-99074.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:99295.3-99316.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:99383.3-99404.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:99493.3-99514.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:99009.3-99030.6" + wire width 14 $0\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99625.3-99646.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:99647.3-99668.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:99669.3-99690.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:99251.3-99272.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:99339.3-99360.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:99361.3-99382.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:99471.3-99492.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:99207.3-99228.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:99537.3-99558.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:99691.3-99712.6" + wire width 3 $0\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:99273.3-99294.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:99449.3-99470.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:99559.3-99580.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:99515.3-99536.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:99427.3-99448.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:99163.3-99184.6" + wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:99185.3-99206.6" + wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:99075.3-99096.6" + wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:99097.3-99118.6" + wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:99119.3-99140.6" + wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:99141.3-99162.6" + wire width 3 $0\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:99229.3-99250.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:98671.7-98671.20" wire $0\initial[0:0] - attribute \src "libresoc.v:91636.3-91660.6" - wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:91736.3-91760.6" - wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:92061.3-92085.6" - wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:92086.3-92110.6" - wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:91611.3-91635.6" - wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:91711.3-91735.6" - wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:91936.3-91960.6" - wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:91511.3-91535.6" - wire width 12 $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:91961.3-91985.6" - wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:91986.3-92010.6" - wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:92011.3-92035.6" - wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:91786.3-91810.6" - wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:91661.3-91685.6" - wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:91686.3-91710.6" - wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:91836.3-91860.6" - wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:91536.3-91560.6" - wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:91886.3-91910.6" - wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:92036.3-92060.6" - wire width 2 $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:91586.3-91610.6" - wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:91811.3-91835.6" - wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:91911.3-91935.6" - wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:91861.3-91885.6" - wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:91761.3-91785.6" - wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:91561.3-91585.6" - wire width 2 $1\dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub20_br + attribute \src "libresoc.v:99581.3-99602.6" + wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:99603.3-99624.6" + wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:99317.3-99338.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:99405.3-99426.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:99031.3-99052.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:99053.3-99074.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:99295.3-99316.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:99383.3-99404.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:99493.3-99514.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:99009.3-99030.6" + wire width 14 $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99625.3-99646.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:99647.3-99668.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:99669.3-99690.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:99251.3-99272.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:99339.3-99360.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:99361.3-99382.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:99471.3-99492.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:99207.3-99228.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:99537.3-99558.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:99691.3-99712.6" + wire width 3 $1\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:99273.3-99294.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:99449.3-99470.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:99559.3-99580.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:99515.3-99536.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:99427.3-99448.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:99163.3-99184.6" + wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:99185.3-99206.6" + wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:99075.3-99096.6" + wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:99097.3-99118.6" + wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:99119.3-99140.6" + wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:99141.3-99162.6" + wire width 3 $1\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:99229.3-99250.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub18_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub18_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -144078,24 +154000,26 @@ module \dec31_dec_sub20 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub20_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub20_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub20_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -144126,31 +154050,34 @@ module \dec31_dec_sub20 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub20_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub20_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -144166,14 +154093,14 @@ module \dec31_dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub20_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub20_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -144248,1207 +154175,1523 @@ module \dec31_dec_sub20 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub20_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub20_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub18_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub20_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub20_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub18_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub18_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub18_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub18_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub18_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub18_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub18_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub20_upd - attribute \src "libresoc.v:91254.7-91254.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub18_upd + attribute \src "libresoc.v:98671.7-98671.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:91254.7-91254.20" - process $proc$libresoc.v:91254$3921 + attribute \src "libresoc.v:98671.7-98671.20" + process $proc$libresoc.v:98671$4027 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91511.3-91535.6" - process $proc$libresoc.v:91511$3897 + attribute \src "libresoc.v:99009.3-99030.6" + process $proc$libresoc.v:99009$3995 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:91512.5-91512.29" + assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99010.5-99010.29" switch \initial - attribute \src "libresoc.v:91512.9-91512.17" + attribute \src "libresoc.v:99010.9-99010.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 case - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] end - attribute \src "libresoc.v:91536.3-91560.6" - process $proc$libresoc.v:91536$3898 + attribute \src "libresoc.v:99031.3-99052.6" + process $proc$libresoc.v:99031$3996 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:91537.5-91537.29" + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:99032.5-99032.29" switch \initial - attribute \src "libresoc.v:91537.9-91537.17" + attribute \src "libresoc.v:99032.9-99032.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "libresoc.v:91561.3-91585.6" - process $proc$libresoc.v:91561$3899 + attribute \src "libresoc.v:99053.3-99074.6" + process $proc$libresoc.v:99053$3997 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:91562.5-91562.29" + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:99054.5-99054.29" switch \initial - attribute \src "libresoc.v:91562.9-91562.17" + attribute \src "libresoc.v:99054.9-99054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end - attribute \src "libresoc.v:91586.3-91610.6" - process $proc$libresoc.v:91586$3900 + attribute \src "libresoc.v:99075.3-99096.6" + process $proc$libresoc.v:99075$3998 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:91587.5-91587.29" + assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:99076.5-99076.29" switch \initial - attribute \src "libresoc.v:91587.9-91587.17" + attribute \src "libresoc.v:99076.9-99076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 case - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] end - attribute \src "libresoc.v:91611.3-91635.6" - process $proc$libresoc.v:91611$3901 + attribute \src "libresoc.v:99097.3-99118.6" + process $proc$libresoc.v:99097$3999 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:91612.5-91612.29" + assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:99098.5-99098.29" switch \initial - attribute \src "libresoc.v:91612.9-91612.17" + attribute \src "libresoc.v:99098.9-99098.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 case - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] end - attribute \src "libresoc.v:91636.3-91660.6" - process $proc$libresoc.v:91636$3902 + attribute \src "libresoc.v:99119.3-99140.6" + process $proc$libresoc.v:99119$4000 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:91637.5-91637.29" + assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:99120.5-99120.29" switch \initial - attribute \src "libresoc.v:91637.9-91637.17" + attribute \src "libresoc.v:99120.9-99120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] end - attribute \src "libresoc.v:91661.3-91685.6" - process $proc$libresoc.v:91661$3903 + attribute \src "libresoc.v:99141.3-99162.6" + process $proc$libresoc.v:99141$4001 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:91662.5-91662.29" + assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:99142.5-99142.29" switch \initial - attribute \src "libresoc.v:91662.9-91662.17" + attribute \src "libresoc.v:99142.9-99142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 case - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] end - attribute \src "libresoc.v:91686.3-91710.6" - process $proc$libresoc.v:91686$3904 + attribute \src "libresoc.v:99163.3-99184.6" + process $proc$libresoc.v:99163$4002 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:91687.5-91687.29" + assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:99164.5-99164.29" switch \initial - attribute \src "libresoc.v:91687.9-91687.17" + attribute \src "libresoc.v:99164.9-99164.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] end - attribute \src "libresoc.v:91711.3-91735.6" - process $proc$libresoc.v:91711$3905 + attribute \src "libresoc.v:99185.3-99206.6" + process $proc$libresoc.v:99185$4003 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:91712.5-91712.29" + assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:99186.5-99186.29" switch \initial - attribute \src "libresoc.v:91712.9-91712.17" + attribute \src "libresoc.v:99186.9-99186.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] end - attribute \src "libresoc.v:91736.3-91760.6" - process $proc$libresoc.v:91736$3906 + attribute \src "libresoc.v:99207.3-99228.6" + process $proc$libresoc.v:99207$4004 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:91737.5-91737.29" + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:99208.5-99208.29" switch \initial - attribute \src "libresoc.v:91737.9-91737.17" + attribute \src "libresoc.v:99208.9-99208.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub20_br[0:0] 1'0 + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end - attribute \src "libresoc.v:91761.3-91785.6" - process $proc$libresoc.v:91761$3907 + attribute \src "libresoc.v:99229.3-99250.6" + process $proc$libresoc.v:99229$4005 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:91762.5-91762.29" + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:99230.5-99230.29" switch \initial - attribute \src "libresoc.v:91762.9-91762.17" + attribute \src "libresoc.v:99230.9-99230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 case - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 end sync always - update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end - attribute \src "libresoc.v:91786.3-91810.6" - process $proc$libresoc.v:91786$3908 + attribute \src "libresoc.v:99251.3-99272.6" + process $proc$libresoc.v:99251$4006 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:91787.5-91787.29" + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:99252.5-99252.29" switch \initial - attribute \src "libresoc.v:91787.9-91787.17" + attribute \src "libresoc.v:99252.9-99252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 case - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end - attribute \src "libresoc.v:91811.3-91835.6" - process $proc$libresoc.v:91811$3909 + attribute \src "libresoc.v:99273.3-99294.6" + process $proc$libresoc.v:99273$4007 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:91812.5-91812.29" + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:99274.5-99274.29" switch \initial - attribute \src "libresoc.v:91812.9-91812.17" + attribute \src "libresoc.v:99274.9-99274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 case - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end - attribute \src "libresoc.v:91836.3-91860.6" - process $proc$libresoc.v:91836$3910 + attribute \src "libresoc.v:99295.3-99316.6" + process $proc$libresoc.v:99295$4008 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:91837.5-91837.29" + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:99296.5-99296.29" switch \initial - attribute \src "libresoc.v:91837.9-91837.17" + attribute \src "libresoc.v:99296.9-99296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end - attribute \src "libresoc.v:91861.3-91885.6" - process $proc$libresoc.v:91861$3911 + attribute \src "libresoc.v:99317.3-99338.6" + process $proc$libresoc.v:99317$4009 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:91862.5-91862.29" + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:99318.5-99318.29" switch \initial - attribute \src "libresoc.v:91862.9-91862.17" + attribute \src "libresoc.v:99318.9-99318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011110 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001110 case - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:91886.3-91910.6" - process $proc$libresoc.v:91886$3912 + attribute \src "libresoc.v:99339.3-99360.6" + process $proc$libresoc.v:99339$4010 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:91887.5-91887.29" + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:99340.5-99340.29" switch \initial - attribute \src "libresoc.v:91887.9-91887.17" + attribute \src "libresoc.v:99340.9-99340.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:91911.3-91935.6" - process $proc$libresoc.v:91911$3913 + attribute \src "libresoc.v:99361.3-99382.6" + process $proc$libresoc.v:99361$4011 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:91912.5-91912.29" + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:99362.5-99362.29" switch \initial - attribute \src "libresoc.v:91912.9-91912.17" + attribute \src "libresoc.v:99362.9-99362.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:91936.3-91960.6" - process $proc$libresoc.v:91936$3914 + attribute \src "libresoc.v:99383.3-99404.6" + process $proc$libresoc.v:99383$4012 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:91937.5-91937.29" + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:99384.5-99384.29" switch \initial - attribute \src "libresoc.v:91937.9-91937.17" + attribute \src "libresoc.v:99384.9-99384.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub20_form[4:0] 5'00000 + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:91961.3-91985.6" - process $proc$libresoc.v:91961$3915 + attribute \src "libresoc.v:99405.3-99426.6" + process $proc$libresoc.v:99405$4013 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:91962.5-91962.29" + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:99406.5-99406.29" switch \initial - attribute \src "libresoc.v:91962.9-91962.17" + attribute \src "libresoc.v:99406.9-99406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub18_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub18_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub18_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub18_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub18_br[0:0] 1'0 case - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub18_br[0:0] 1'0 end sync always - update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:91986.3-92010.6" - process $proc$libresoc.v:91986$3916 + attribute \src "libresoc.v:99427.3-99448.6" + process $proc$libresoc.v:99427$4014 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:91987.5-91987.29" + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:99428.5-99428.29" switch \initial - attribute \src "libresoc.v:91987.9-91987.17" + attribute \src "libresoc.v:99428.9-99428.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:92011.3-92035.6" - process $proc$libresoc.v:92011$3917 + attribute \src "libresoc.v:99449.3-99470.6" + process $proc$libresoc.v:99449$4015 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:92012.5-92012.29" + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:99450.5-99450.29" switch \initial - attribute \src "libresoc.v:92012.9-92012.17" + attribute \src "libresoc.v:99450.9-99450.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:92036.3-92060.6" - process $proc$libresoc.v:92036$3918 + attribute \src "libresoc.v:99471.3-99492.6" + process $proc$libresoc.v:99471$4016 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:92037.5-92037.29" + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:99472.5-99472.29" switch \initial - attribute \src "libresoc.v:92037.9-92037.17" + attribute \src "libresoc.v:99472.9-99472.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "libresoc.v:99493.3-99514.6" + process $proc$libresoc.v:99493$4017 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:99494.5-99494.29" + switch \initial + attribute \src "libresoc.v:99494.9-99494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 case - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_form[4:0] 5'00000 end sync always - update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:92061.3-92085.6" - process $proc$libresoc.v:92061$3919 + attribute \src "libresoc.v:99515.3-99536.6" + process $proc$libresoc.v:99515$4018 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:92062.5-92062.29" + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:99516.5-99516.29" switch \initial - attribute \src "libresoc.v:92062.9-92062.17" + attribute \src "libresoc.v:99516.9-99516.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "libresoc.v:99537.3-99558.6" + process $proc$libresoc.v:99537$4019 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:99538.5-99538.29" + switch \initial + attribute \src "libresoc.v:99538.9-99538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 case - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub18_lk[0:0] 1'0 end sync always - update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:92086.3-92110.6" - process $proc$libresoc.v:92086$3920 + attribute \src "libresoc.v:99559.3-99580.6" + process $proc$libresoc.v:99559$4020 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:92087.5-92087.29" + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:99560.5-99560.29" switch \initial - attribute \src "libresoc.v:92087.9-92087.17" + attribute \src "libresoc.v:99560.9-99560.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "libresoc.v:99581.3-99602.6" + process $proc$libresoc.v:99581$4021 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:99582.5-99582.29" + switch \initial + attribute \src "libresoc.v:99582.9-99582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 case - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 end sync always - update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] + end + attribute \src "libresoc.v:99603.3-99624.6" + process $proc$libresoc.v:99603$4022 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:99604.5-99604.29" + switch \initial + attribute \src "libresoc.v:99604.9-99604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + case + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] + end + attribute \src "libresoc.v:99625.3-99646.6" + process $proc$libresoc.v:99625$4023 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:99626.5-99626.29" + switch \initial + attribute \src "libresoc.v:99626.9-99626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "libresoc.v:99647.3-99668.6" + process $proc$libresoc.v:99647$4024 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:99648.5-99648.29" + switch \initial + attribute \src "libresoc.v:99648.9-99648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "libresoc.v:99669.3-99690.6" + process $proc$libresoc.v:99669$4025 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:99670.5-99670.29" + switch \initial + attribute \src "libresoc.v:99670.9-99670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "libresoc.v:99691.3-99712.6" + process $proc$libresoc.v:99691$4026 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:99692.5-99692.29" + switch \initial + attribute \src "libresoc.v:99692.9-99692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:92116.1-93533.10" +attribute \src "libresoc.v:99718.1-100666.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" -module \dec31_dec_sub21 - attribute \src "libresoc.v:93158.3-93188.6" - wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:92766.3-92814.6" - wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:93434.3-93482.6" - wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:93483.3-93531.6" - wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:92570.3-92618.6" - wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:92717.3-92765.6" - wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:93189.3-93237.6" - wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:92374.3-92422.6" - wire width 12 $0\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:93238.3-93286.6" - wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:93287.3-93335.6" - wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:93336.3-93384.6" - wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:92913.3-92961.6" - wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:92619.3-92667.6" - wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:92668.3-92716.6" - wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:92962.3-93010.6" - wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:92423.3-92471.6" - wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:93060.3-93108.6" - wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:93385.3-93433.6" - wire width 2 $0\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:92521.3-92569.6" - wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:92864.3-92912.6" - wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:93109.3-93157.6" - wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:93011.3-93059.6" - wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:92815.3-92863.6" - wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:92472.3-92520.6" - wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:92117.7-92117.20" +module \dec31_dec_sub19 + attribute \src "libresoc.v:100551.3-100569.6" + wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:100570.3-100588.6" + wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:100323.3-100341.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:100399.3-100417.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:100076.3-100094.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:100095.3-100113.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:100304.3-100322.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:100380.3-100398.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:100475.3-100493.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:100057.3-100075.6" + wire width 14 $0\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:100589.3-100607.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:100608.3-100626.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:100627.3-100645.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:100266.3-100284.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:100342.3-100360.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:100361.3-100379.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:100456.3-100474.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:100228.3-100246.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:100513.3-100531.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:100646.3-100664.6" + wire width 3 $0\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:100285.3-100303.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:100437.3-100455.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:100532.3-100550.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:100494.3-100512.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:100418.3-100436.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:100190.3-100208.6" + wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:100209.3-100227.6" + wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:100114.3-100132.6" + wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:100133.3-100151.6" + wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:100152.3-100170.6" + wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:100171.3-100189.6" + wire width 3 $0\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:100247.3-100265.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:99719.7-99719.20" wire $0\initial[0:0] - attribute \src "libresoc.v:93158.3-93188.6" - wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:92766.3-92814.6" - wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:93434.3-93482.6" - wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:93483.3-93531.6" - wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:92570.3-92618.6" - wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:92717.3-92765.6" - wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:93189.3-93237.6" - wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:92374.3-92422.6" - wire width 12 $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:93238.3-93286.6" - wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:93287.3-93335.6" - wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:93336.3-93384.6" - wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:92913.3-92961.6" - wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:92619.3-92667.6" - wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:92668.3-92716.6" - wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:92962.3-93010.6" - wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:92423.3-92471.6" - wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:93060.3-93108.6" - wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:93385.3-93433.6" - wire width 2 $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:92521.3-92569.6" - wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:92864.3-92912.6" - wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:93109.3-93157.6" - wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:93011.3-93059.6" - wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:92815.3-92863.6" - wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:92472.3-92520.6" - wire width 2 $1\dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub21_br + attribute \src "libresoc.v:100551.3-100569.6" + wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:100570.3-100588.6" + wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:100323.3-100341.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:100399.3-100417.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:100076.3-100094.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:100095.3-100113.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:100304.3-100322.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:100380.3-100398.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:100475.3-100493.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:100057.3-100075.6" + wire width 14 $1\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:100589.3-100607.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:100608.3-100626.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:100627.3-100645.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:100266.3-100284.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:100342.3-100360.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:100361.3-100379.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:100456.3-100474.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:100228.3-100246.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:100513.3-100531.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:100646.3-100664.6" + wire width 3 $1\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:100285.3-100303.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:100437.3-100455.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:100532.3-100550.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:100494.3-100512.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:100418.3-100436.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:100190.3-100208.6" + wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:100209.3-100227.6" + wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:100114.3-100132.6" + wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:100133.3-100151.6" + wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:100152.3-100170.6" + wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:100171.3-100189.6" + wire width 3 $1\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:100247.3-100265.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -145457,24 +155700,26 @@ module \dec31_dec_sub21 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub21_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub21_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub21_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -145505,31 +155750,34 @@ module \dec31_dec_sub21 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub21_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub21_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub21_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -145545,14 +155793,14 @@ module \dec31_dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub21_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub21_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -145627,1951 +155875,3223 @@ module \dec31_dec_sub21 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub21_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub21_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub19_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub21_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub21_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub19_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub19_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub19_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub19_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub19_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub21_upd - attribute \src "libresoc.v:92117.7-92117.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub19_upd + attribute \src "libresoc.v:99719.7-99719.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:92117.7-92117.20" - process $proc$libresoc.v:92117$3946 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:92374.3-92422.6" - process $proc$libresoc.v:92374$3922 + attribute \src "libresoc.v:100057.3-100075.6" + process $proc$libresoc.v:100057$4028 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:92375.5-92375.29" + assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:100058.5-100058.29" switch \initial - attribute \src "libresoc.v:92375.9-92375.17" + attribute \src "libresoc.v:100058.9-100058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00010000000000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00010000000000 + case + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] + end + attribute \src "libresoc.v:100076.3-100094.6" + process $proc$libresoc.v:100076$4029 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:100077.5-100077.29" + switch \initial + attribute \src "libresoc.v:100077.9-100077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:100095.3-100113.6" + process $proc$libresoc.v:100095$4030 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:100096.5-100096.29" + switch \initial + attribute \src "libresoc.v:100096.9-100096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:92423.3-92471.6" - process $proc$libresoc.v:92423$3923 + attribute \src "libresoc.v:100114.3-100132.6" + process $proc$libresoc.v:100114$4031 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:92424.5-92424.29" + assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:100115.5-100115.29" switch \initial - attribute \src "libresoc.v:92424.9-92424.17" + attribute \src "libresoc.v:100115.9-100115.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] + end + attribute \src "libresoc.v:100133.3-100151.6" + process $proc$libresoc.v:100133$4032 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:100134.5-100134.29" + switch \initial + attribute \src "libresoc.v:100134.9-100134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] + end + attribute \src "libresoc.v:100152.3-100170.6" + process $proc$libresoc.v:100152$4033 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:100153.5-100153.29" + switch \initial + attribute \src "libresoc.v:100153.9-100153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] end - attribute \src "libresoc.v:92472.3-92520.6" - process $proc$libresoc.v:92472$3924 + attribute \src "libresoc.v:100171.3-100189.6" + process $proc$libresoc.v:100171$4034 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:92473.5-92473.29" + assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:100172.5-100172.29" switch \initial - attribute \src "libresoc.v:92473.9-92473.17" + attribute \src "libresoc.v:100172.9-100172.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] + end + attribute \src "libresoc.v:100190.3-100208.6" + process $proc$libresoc.v:100190$4035 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:100191.5-100191.29" + switch \initial + attribute \src "libresoc.v:100191.9-100191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] + end + attribute \src "libresoc.v:100209.3-100227.6" + process $proc$libresoc.v:100209$4036 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:100210.5-100210.29" + switch \initial + attribute \src "libresoc.v:100210.9-100210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end - attribute \src "libresoc.v:92521.3-92569.6" - process $proc$libresoc.v:92521$3925 + attribute \src "libresoc.v:100228.3-100246.6" + process $proc$libresoc.v:100228$4037 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:92522.5-92522.29" + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:100229.5-100229.29" switch \initial - attribute \src "libresoc.v:92522.9-92522.17" + attribute \src "libresoc.v:100229.9-100229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "libresoc.v:100247.3-100265.6" + process $proc$libresoc.v:100247$4038 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:100248.5-100248.29" + switch \initial + attribute \src "libresoc.v:100248.9-100248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "libresoc.v:100266.3-100284.6" + process $proc$libresoc.v:100266$4039 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:100267.5-100267.29" + switch \initial + attribute \src "libresoc.v:100267.9-100267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 case - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:92570.3-92618.6" - process $proc$libresoc.v:92570$3926 + attribute \src "libresoc.v:100285.3-100303.6" + process $proc$libresoc.v:100285$4040 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:92571.5-92571.29" + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:100286.5-100286.29" switch \initial - attribute \src "libresoc.v:92571.9-92571.17" + attribute \src "libresoc.v:100286.9-100286.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:100304.3-100322.6" + process $proc$libresoc.v:100304$4041 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:100305.5-100305.29" + switch \initial + attribute \src "libresoc.v:100305.9-100305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "libresoc.v:100323.3-100341.6" + process $proc$libresoc.v:100323$4042 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:100324.5-100324.29" + switch \initial + attribute \src "libresoc.v:100324.9-100324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 case - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:92619.3-92667.6" - process $proc$libresoc.v:92619$3927 + attribute \src "libresoc.v:100342.3-100360.6" + process $proc$libresoc.v:100342$4043 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:92620.5-92620.29" + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:100343.5-100343.29" switch \initial - attribute \src "libresoc.v:92620.9-92620.17" + attribute \src "libresoc.v:100343.9-100343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "libresoc.v:100361.3-100379.6" + process $proc$libresoc.v:100361$4044 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:100362.5-100362.29" + switch \initial + attribute \src "libresoc.v:100362.9-100362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "libresoc.v:100380.3-100398.6" + process $proc$libresoc.v:100380$4045 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:100381.5-100381.29" + switch \initial + attribute \src "libresoc.v:100381.9-100381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:92668.3-92716.6" - process $proc$libresoc.v:92668$3928 + attribute \src "libresoc.v:100399.3-100417.6" + process $proc$libresoc.v:100399$4046 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:92669.5-92669.29" + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:100400.5-100400.29" switch \initial - attribute \src "libresoc.v:92669.9-92669.17" + attribute \src "libresoc.v:100400.9-100400.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "libresoc.v:100418.3-100436.6" + process $proc$libresoc.v:100418$4047 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:100419.5-100419.29" + switch \initial + attribute \src "libresoc.v:100419.9-100419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "libresoc.v:100437.3-100455.6" + process $proc$libresoc.v:100437$4048 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:100438.5-100438.29" + switch \initial + attribute \src "libresoc.v:100438.9-100438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:92717.3-92765.6" - process $proc$libresoc.v:92717$3929 + attribute \src "libresoc.v:100456.3-100474.6" + process $proc$libresoc.v:100456$4049 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:92718.5-92718.29" + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:100457.5-100457.29" switch \initial - attribute \src "libresoc.v:92718.9-92718.17" + attribute \src "libresoc.v:100457.9-100457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "libresoc.v:100475.3-100493.6" + process $proc$libresoc.v:100475$4050 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:100476.5-100476.29" + switch \initial + attribute \src "libresoc.v:100476.9-100476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "libresoc.v:100494.3-100512.6" + process $proc$libresoc.v:100494$4051 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:100495.5-100495.29" + switch \initial + attribute \src "libresoc.v:100495.9-100495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:92766.3-92814.6" - process $proc$libresoc.v:92766$3930 + attribute \src "libresoc.v:100513.3-100531.6" + process $proc$libresoc.v:100513$4052 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:92767.5-92767.29" + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:100514.5-100514.29" switch \initial - attribute \src "libresoc.v:92767.9-92767.17" + attribute \src "libresoc.v:100514.9-100514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "libresoc.v:100532.3-100550.6" + process $proc$libresoc.v:100532$4053 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:100533.5-100533.29" + switch \initial + attribute \src "libresoc.v:100533.9-100533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:100551.3-100569.6" + process $proc$libresoc.v:100551$4054 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:100552.5-100552.29" + switch \initial + attribute \src "libresoc.v:100552.9-100552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 case - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00 end sync always - update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end - attribute \src "libresoc.v:92815.3-92863.6" - process $proc$libresoc.v:92815$3931 + attribute \src "libresoc.v:100570.3-100588.6" + process $proc$libresoc.v:100570$4055 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:92816.5-92816.29" + assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:100571.5-100571.29" switch \initial - attribute \src "libresoc.v:92816.9-92816.17" + attribute \src "libresoc.v:100571.9-100571.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] + end + attribute \src "libresoc.v:100589.3-100607.6" + process $proc$libresoc.v:100589$4056 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:100590.5-100590.29" + switch \initial + attribute \src "libresoc.v:100590.9-100590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "libresoc.v:100608.3-100626.6" + process $proc$libresoc.v:100608$4057 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:100609.5-100609.29" + switch \initial + attribute \src "libresoc.v:100609.9-100609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 case - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 end sync always - update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:92864.3-92912.6" - process $proc$libresoc.v:92864$3932 + attribute \src "libresoc.v:100627.3-100645.6" + process $proc$libresoc.v:100627$4058 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:92865.5-92865.29" + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:100628.5-100628.29" switch \initial - attribute \src "libresoc.v:92865.9-92865.17" + attribute \src "libresoc.v:100628.9-100628.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "libresoc.v:100646.3-100664.6" + process $proc$libresoc.v:100646$4059 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:100647.5-100647.29" + switch \initial + attribute \src "libresoc.v:100647.9-100647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'011 + case + assign $1\dec31_dec_sub19_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[2:0] + end + attribute \src "libresoc.v:99719.7-99719.20" + process $proc$libresoc.v:99719$4060 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:100670.1-101810.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "libresoc.v:101659.3-101683.6" + wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:101684.3-101708.6" + wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:101359.3-101383.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:101459.3-101483.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:101034.3-101058.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:101059.3-101083.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:101334.3-101358.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:101434.3-101458.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:101559.3-101583.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:101009.3-101033.6" + wire width 14 $0\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:101709.3-101733.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:101734.3-101758.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:101759.3-101783.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:101284.3-101308.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:101384.3-101408.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:101409.3-101433.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:101534.3-101558.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:101234.3-101258.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:101609.3-101633.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:101784.3-101808.6" + wire width 3 $0\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:101309.3-101333.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:101509.3-101533.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:101634.3-101658.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:101584.3-101608.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:101484.3-101508.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:101184.3-101208.6" + wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:101209.3-101233.6" + wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:101084.3-101108.6" + wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:101109.3-101133.6" + wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:101134.3-101158.6" + wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:101159.3-101183.6" + wire width 3 $0\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:101259.3-101283.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:100671.7-100671.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:101659.3-101683.6" + wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:101684.3-101708.6" + wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:101359.3-101383.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:101459.3-101483.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:101034.3-101058.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:101059.3-101083.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:101334.3-101358.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:101434.3-101458.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:101559.3-101583.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:101009.3-101033.6" + wire width 14 $1\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:101709.3-101733.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:101734.3-101758.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:101759.3-101783.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:101284.3-101308.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:101384.3-101408.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:101409.3-101433.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:101534.3-101558.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:101234.3-101258.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:101609.3-101633.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:101784.3-101808.6" + wire width 3 $1\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:101309.3-101333.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:101509.3-101533.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:101634.3-101658.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:101584.3-101608.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:101484.3-101508.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:101184.3-101208.6" + wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:101209.3-101233.6" + wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:101084.3-101108.6" + wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:101109.3-101133.6" + wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:101134.3-101158.6" + wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:101159.3-101183.6" + wire width 3 $1\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:101259.3-101283.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub20_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub20_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub20_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub20_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub20_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub20_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub20_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub20_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub20_upd + attribute \src "libresoc.v:100671.7-100671.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:100671.7-100671.20" + process $proc$libresoc.v:100671$4093 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:101009.3-101033.6" + process $proc$libresoc.v:101009$4061 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:101010.5-101010.29" + switch \initial + attribute \src "libresoc.v:101010.9-101010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 case - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:92913.3-92961.6" - process $proc$libresoc.v:92913$3933 + attribute \src "libresoc.v:101034.3-101058.6" + process $proc$libresoc.v:101034$4062 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:92914.5-92914.29" + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:101035.5-101035.29" switch \initial - attribute \src "libresoc.v:92914.9-92914.17" + attribute \src "libresoc.v:101035.9-101035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:101059.3-101083.6" + process $proc$libresoc.v:101059$4063 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:101060.5-101060.29" + switch \initial + attribute \src "libresoc.v:101060.9-101060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:92962.3-93010.6" - process $proc$libresoc.v:92962$3934 + attribute \src "libresoc.v:101084.3-101108.6" + process $proc$libresoc.v:101084$4064 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:92963.5-92963.29" + assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:101085.5-101085.29" switch \initial - attribute \src "libresoc.v:92963.9-92963.17" + attribute \src "libresoc.v:101085.9-101085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] + end + attribute \src "libresoc.v:101109.3-101133.6" + process $proc$libresoc.v:101109$4065 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:101110.5-101110.29" + switch \initial + attribute \src "libresoc.v:101110.9-101110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 case - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end - attribute \src "libresoc.v:93011.3-93059.6" - process $proc$libresoc.v:93011$3935 + attribute \src "libresoc.v:101134.3-101158.6" + process $proc$libresoc.v:101134$4066 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:93012.5-93012.29" + assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:101135.5-101135.29" switch \initial - attribute \src "libresoc.v:93012.9-93012.17" + attribute \src "libresoc.v:101135.9-101135.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'001 + case + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] + end + attribute \src "libresoc.v:101159.3-101183.6" + process $proc$libresoc.v:101159$4067 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:101160.5-101160.29" + switch \initial + attribute \src "libresoc.v:101160.9-101160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_out[2:0] 3'000 case - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end - attribute \src "libresoc.v:93060.3-93108.6" - process $proc$libresoc.v:93060$3936 + attribute \src "libresoc.v:101184.3-101208.6" + process $proc$libresoc.v:101184$4068 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:93061.5-93061.29" + assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:101185.5-101185.29" switch \initial - attribute \src "libresoc.v:93061.9-93061.17" + attribute \src "libresoc.v:101185.9-101185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] + end + attribute \src "libresoc.v:101209.3-101233.6" + process $proc$libresoc.v:101209$4069 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:101210.5-101210.29" + switch \initial + attribute \src "libresoc.v:101210.9-101210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub21_lk[0:0] 1'0 + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end - attribute \src "libresoc.v:93109.3-93157.6" - process $proc$libresoc.v:93109$3937 + attribute \src "libresoc.v:101234.3-101258.6" + process $proc$libresoc.v:101234$4070 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:93110.5-93110.29" + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:101235.5-101235.29" switch \initial - attribute \src "libresoc.v:93110.9-93110.17" + attribute \src "libresoc.v:101235.9-101235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:101259.3-101283.6" + process $proc$libresoc.v:101259$4071 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:101260.5-101260.29" + switch \initial + attribute \src "libresoc.v:101260.9-101260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 case - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 end sync always - update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:93158.3-93188.6" - process $proc$libresoc.v:93158$3938 + attribute \src "libresoc.v:101284.3-101308.6" + process $proc$libresoc.v:101284$4072 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:93159.5-93159.29" + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:101285.5-101285.29" switch \initial - attribute \src "libresoc.v:93159.9-93159.17" + attribute \src "libresoc.v:101285.9-101285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:93189.3-93237.6" - process $proc$libresoc.v:93189$3939 + attribute \src "libresoc.v:101309.3-101333.6" + process $proc$libresoc.v:101309$4073 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:93190.5-93190.29" + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:101310.5-101310.29" switch \initial - attribute \src "libresoc.v:93190.9-93190.17" + attribute \src "libresoc.v:101310.9-101310.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "libresoc.v:101334.3-101358.6" + process $proc$libresoc.v:101334$4074 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:101335.5-101335.29" + switch \initial + attribute \src "libresoc.v:101335.9-101335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub21_form[4:0] 5'00000 + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:93238.3-93286.6" - process $proc$libresoc.v:93238$3940 + attribute \src "libresoc.v:101359.3-101383.6" + process $proc$libresoc.v:101359$4075 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:93239.5-93239.29" + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:101360.5-101360.29" switch \initial - attribute \src "libresoc.v:93239.9-93239.17" + attribute \src "libresoc.v:101360.9-101360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101110 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "libresoc.v:101384.3-101408.6" + process $proc$libresoc.v:101384$4076 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:101385.5-101385.29" + switch \initial + attribute \src "libresoc.v:101385.9-101385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:93287.3-93335.6" - process $proc$libresoc.v:93287$3941 + attribute \src "libresoc.v:101409.3-101433.6" + process $proc$libresoc.v:101409$4077 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:93288.5-93288.29" + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:101410.5-101410.29" switch \initial - attribute \src "libresoc.v:93288.9-93288.17" + attribute \src "libresoc.v:101410.9-101410.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "libresoc.v:101434.3-101458.6" + process $proc$libresoc.v:101434$4078 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:101435.5-101435.29" + switch \initial + attribute \src "libresoc.v:101435.9-101435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "libresoc.v:101459.3-101483.6" + process $proc$libresoc.v:101459$4079 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:101460.5-101460.29" + switch \initial + attribute \src "libresoc.v:101460.9-101460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 case - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub20_br[0:0] 1'0 end sync always - update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:93336.3-93384.6" - process $proc$libresoc.v:93336$3942 + attribute \src "libresoc.v:101484.3-101508.6" + process $proc$libresoc.v:101484$4080 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:93337.5-93337.29" + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:101485.5-101485.29" switch \initial - attribute \src "libresoc.v:93337.9-93337.17" + attribute \src "libresoc.v:101485.9-101485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:101509.3-101533.6" + process $proc$libresoc.v:101509$4081 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:101510.5-101510.29" + switch \initial + attribute \src "libresoc.v:101510.9-101510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "libresoc.v:101534.3-101558.6" + process $proc$libresoc.v:101534$4082 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:101535.5-101535.29" + switch \initial + attribute \src "libresoc.v:101535.9-101535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:93385.3-93433.6" - process $proc$libresoc.v:93385$3943 + attribute \src "libresoc.v:101559.3-101583.6" + process $proc$libresoc.v:101559$4083 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:93386.5-93386.29" + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:101560.5-101560.29" switch \initial - attribute \src "libresoc.v:93386.9-93386.17" + attribute \src "libresoc.v:101560.9-101560.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "libresoc.v:101584.3-101608.6" + process $proc$libresoc.v:101584$4084 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:101585.5-101585.29" + switch \initial + attribute \src "libresoc.v:101585.9-101585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:101609.3-101633.6" + process $proc$libresoc.v:101609$4085 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:101610.5-101610.29" + switch \initial + attribute \src "libresoc.v:101610.9-101610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_lk[0:0] 1'0 case - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub20_lk[0:0] 1'0 end sync always - update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "libresoc.v:93434.3-93482.6" - process $proc$libresoc.v:93434$3944 + attribute \src "libresoc.v:101634.3-101658.6" + process $proc$libresoc.v:101634$4086 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:93435.5-93435.29" + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:101635.5-101635.29" switch \initial - attribute \src "libresoc.v:93435.9-93435.17" + attribute \src "libresoc.v:101635.9-101635.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:101659.3-101683.6" + process $proc$libresoc.v:101659$4087 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:101660.5-101660.29" + switch \initial + attribute \src "libresoc.v:101660.9-101660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] + end + attribute \src "libresoc.v:101684.3-101708.6" + process $proc$libresoc.v:101684$4088 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:101685.5-101685.29" + switch \initial + attribute \src "libresoc.v:101685.9-101685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 case - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] end - attribute \src "libresoc.v:93483.3-93531.6" - process $proc$libresoc.v:93483$3945 + attribute \src "libresoc.v:101709.3-101733.6" + process $proc$libresoc.v:101709$4089 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:93484.5-93484.29" + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:101710.5-101710.29" switch \initial - attribute \src "libresoc.v:93484.9-93484.17" + attribute \src "libresoc.v:101710.9-101710.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:101734.3-101758.6" + process $proc$libresoc.v:101734$4090 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:101735.5-101735.29" + switch \initial + attribute \src "libresoc.v:101735.9-101735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:101759.3-101783.6" + process $proc$libresoc.v:101759$4091 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:101760.5-101760.29" + switch \initial + attribute \src "libresoc.v:101760.9-101760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:101784.3-101808.6" + process $proc$libresoc.v:101784$4092 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:101785.5-101785.29" + switch \initial + attribute \src "libresoc.v:101785.9-101785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub20_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:93537.1-95116.10" +attribute \src "libresoc.v:101814.1-103704.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" -module \dec31_dec_sub22 - attribute \src "libresoc.v:94070.3-94124.6" - wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:94290.3-94344.6" - wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:95005.3-95059.6" - wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:95060.3-95114.6" - wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:94015.3-94069.6" - wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:94235.3-94289.6" - wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:94730.3-94784.6" - wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:93795.3-93849.6" - wire width 12 $0\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:94785.3-94839.6" - wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:94840.3-94894.6" - wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:94895.3-94949.6" - wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:94400.3-94454.6" - wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:94125.3-94179.6" - wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:94180.3-94234.6" - wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:94510.3-94564.6" - wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:93850.3-93904.6" - wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:94620.3-94674.6" - wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:94950.3-95004.6" - wire width 2 $0\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:93960.3-94014.6" - wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:94455.3-94509.6" - wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:94675.3-94729.6" - wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:94565.3-94619.6" - wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:94345.3-94399.6" - wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:93905.3-93959.6" - wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:93538.7-93538.20" +module \dec31_dec_sub21 + attribute \src "libresoc.v:103409.3-103457.6" + wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] + attribute \src "libresoc.v:103458.3-103506.6" + wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] + attribute \src "libresoc.v:103378.3-103408.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:102986.3-103034.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:102202.3-102250.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:102251.3-102299.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:102790.3-102838.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:102937.3-102985.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:103231.3-103279.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:102153.3-102201.6" + wire width 14 $0\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:103507.3-103555.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:103556.3-103604.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:103605.3-103653.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:102692.3-102740.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:102839.3-102887.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:102888.3-102936.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:103133.3-103181.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:102594.3-102642.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:103280.3-103328.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:103654.3-103702.6" + wire width 3 $0\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:102741.3-102789.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:103084.3-103132.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:103329.3-103377.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:103182.3-103230.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:103035.3-103083.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:102496.3-102544.6" + wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:102545.3-102593.6" + wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:102300.3-102348.6" + wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:102349.3-102397.6" + wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:102398.3-102446.6" + wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:102447.3-102495.6" + wire width 3 $0\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:102643.3-102691.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:101815.7-101815.20" wire $0\initial[0:0] - attribute \src "libresoc.v:94070.3-94124.6" - wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:94290.3-94344.6" - wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:95005.3-95059.6" - wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:95060.3-95114.6" - wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:94015.3-94069.6" - wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:94235.3-94289.6" - wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:94730.3-94784.6" - wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:93795.3-93849.6" - wire width 12 $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:94785.3-94839.6" - wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:94840.3-94894.6" - wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:94895.3-94949.6" - wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:94400.3-94454.6" - wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:94125.3-94179.6" - wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:94180.3-94234.6" - wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:94510.3-94564.6" - wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:93850.3-93904.6" - wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:94620.3-94674.6" - wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:94950.3-95004.6" - wire width 2 $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:93960.3-94014.6" - wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:94455.3-94509.6" - wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:94675.3-94729.6" - wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:94565.3-94619.6" - wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:94345.3-94399.6" - wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:93905.3-93959.6" - wire width 2 $1\dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub22_br + attribute \src "libresoc.v:103409.3-103457.6" + wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] + attribute \src "libresoc.v:103458.3-103506.6" + wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] + attribute \src "libresoc.v:103378.3-103408.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:102986.3-103034.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:102202.3-102250.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:102251.3-102299.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:102790.3-102838.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:102937.3-102985.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:103231.3-103279.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:102153.3-102201.6" + wire width 14 $1\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:103507.3-103555.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:103556.3-103604.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:103605.3-103653.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:102692.3-102740.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:102839.3-102887.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:102888.3-102936.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:103133.3-103181.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:102594.3-102642.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:103280.3-103328.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:103654.3-103702.6" + wire width 3 $1\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:102741.3-102789.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:103084.3-103132.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:103329.3-103377.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:103182.3-103230.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:103035.3-103083.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:102496.3-102544.6" + wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:102545.3-102593.6" + wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:102300.3-102348.6" + wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:102349.3-102397.6" + wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:102398.3-102446.6" + wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:102447.3-102495.6" + wire width 3 $1\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:102643.3-102691.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub21_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub21_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -147580,24 +159100,26 @@ module \dec31_dec_sub22 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub22_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub22_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub22_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -147628,31 +159150,34 @@ module \dec31_dec_sub22 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub22_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -147668,14 +159193,14 @@ module \dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub22_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub22_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -147750,2167 +159275,2651 @@ module \dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub22_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub22_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub21_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub22_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub22_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub21_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub21_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub21_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub21_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub21_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub21_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub21_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub22_upd - attribute \src "libresoc.v:93538.7-93538.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub21_upd + attribute \src "libresoc.v:101815.7-101815.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:93538.7-93538.20" - process $proc$libresoc.v:93538$3971 + attribute \src "libresoc.v:101815.7-101815.20" + process $proc$libresoc.v:101815$4126 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:93795.3-93849.6" - process $proc$libresoc.v:93795$3947 + attribute \src "libresoc.v:102153.3-102201.6" + process $proc$libresoc.v:102153$4094 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:93796.5-93796.29" + assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:102154.5-102154.29" switch \initial - attribute \src "libresoc.v:93796.9-93796.17" + attribute \src "libresoc.v:102154.9-102154.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 case - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:93850.3-93904.6" - process $proc$libresoc.v:93850$3948 + attribute \src "libresoc.v:102202.3-102250.6" + process $proc$libresoc.v:102202$4095 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:93851.5-93851.29" + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:102203.5-102203.29" switch \initial - attribute \src "libresoc.v:93851.9-93851.17" + attribute \src "libresoc.v:102203.9-102203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:93905.3-93959.6" - process $proc$libresoc.v:93905$3949 + attribute \src "libresoc.v:102251.3-102299.6" + process $proc$libresoc.v:102251$4096 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:93906.5-93906.29" + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:102252.5-102252.29" switch \initial - attribute \src "libresoc.v:93906.9-93906.17" + attribute \src "libresoc.v:102252.9-102252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:93960.3-94014.6" - process $proc$libresoc.v:93960$3950 + attribute \src "libresoc.v:102300.3-102348.6" + process $proc$libresoc.v:102300$4097 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:93961.5-93961.29" + assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:102301.5-102301.29" switch \initial - attribute \src "libresoc.v:93961.9-93961.17" + attribute \src "libresoc.v:102301.9-102301.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 case - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end - attribute \src "libresoc.v:94015.3-94069.6" - process $proc$libresoc.v:94015$3951 + attribute \src "libresoc.v:102349.3-102397.6" + process $proc$libresoc.v:102349$4098 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:94016.5-94016.29" + assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:102350.5-102350.29" switch \initial - attribute \src "libresoc.v:94016.9-94016.17" + attribute \src "libresoc.v:102350.9-102350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 case - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end - attribute \src "libresoc.v:94070.3-94124.6" - process $proc$libresoc.v:94070$3952 + attribute \src "libresoc.v:102398.3-102446.6" + process $proc$libresoc.v:102398$4099 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:94071.5-94071.29" + assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:102399.5-102399.29" switch \initial - attribute \src "libresoc.v:94071.9-94071.17" + attribute \src "libresoc.v:102399.9-102399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 case - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end - attribute \src "libresoc.v:94125.3-94179.6" - process $proc$libresoc.v:94125$3953 + attribute \src "libresoc.v:102447.3-102495.6" + process $proc$libresoc.v:102447$4100 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:94126.5-94126.29" + assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:102448.5-102448.29" switch \initial - attribute \src "libresoc.v:94126.9-94126.17" + attribute \src "libresoc.v:102448.9-102448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 case - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end - attribute \src "libresoc.v:94180.3-94234.6" - process $proc$libresoc.v:94180$3954 + attribute \src "libresoc.v:102496.3-102544.6" + process $proc$libresoc.v:102496$4101 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:94181.5-94181.29" + assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:102497.5-102497.29" switch \initial - attribute \src "libresoc.v:94181.9-94181.17" + attribute \src "libresoc.v:102497.9-102497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] + update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end - attribute \src "libresoc.v:94235.3-94289.6" - process $proc$libresoc.v:94235$3955 + attribute \src "libresoc.v:102545.3-102593.6" + process $proc$libresoc.v:102545$4102 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:94236.5-94236.29" + assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:102546.5-102546.29" switch \initial - attribute \src "libresoc.v:94236.9-94236.17" + attribute \src "libresoc.v:102546.9-102546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] + update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end - attribute \src "libresoc.v:94290.3-94344.6" - process $proc$libresoc.v:94290$3956 + attribute \src "libresoc.v:102594.3-102642.6" + process $proc$libresoc.v:102594$4103 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:94291.5-94291.29" + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:102595.5-102595.29" switch \initial - attribute \src "libresoc.v:94291.9-94291.17" + attribute \src "libresoc.v:102595.9-102595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 case - assign $1\dec31_dec_sub22_br[0:0] 1'0 + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:94345.3-94399.6" - process $proc$libresoc.v:94345$3957 + attribute \src "libresoc.v:102643.3-102691.6" + process $proc$libresoc.v:102643$4104 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:94346.5-94346.29" + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:102644.5-102644.29" switch \initial - attribute \src "libresoc.v:94346.9-94346.17" + attribute \src "libresoc.v:102644.9-102644.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 case - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 end sync always - update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:94400.3-94454.6" - process $proc$libresoc.v:94400$3958 + attribute \src "libresoc.v:102692.3-102740.6" + process $proc$libresoc.v:102692$4105 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:94401.5-94401.29" + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:102693.5-102693.29" switch \initial - attribute \src "libresoc.v:94401.9-94401.17" + attribute \src "libresoc.v:102693.9-102693.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:94455.3-94509.6" - process $proc$libresoc.v:94455$3959 + attribute \src "libresoc.v:102741.3-102789.6" + process $proc$libresoc.v:102741$4106 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:94456.5-94456.29" + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:102742.5-102742.29" switch \initial - attribute \src "libresoc.v:94456.9-94456.17" + attribute \src "libresoc.v:102742.9-102742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 case - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:94510.3-94564.6" - process $proc$libresoc.v:94510$3960 + attribute \src "libresoc.v:102790.3-102838.6" + process $proc$libresoc.v:102790$4107 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:94511.5-94511.29" + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:102791.5-102791.29" switch \initial - attribute \src "libresoc.v:94511.9-94511.17" + attribute \src "libresoc.v:102791.9-102791.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:94565.3-94619.6" - process $proc$libresoc.v:94565$3961 + attribute \src "libresoc.v:102839.3-102887.6" + process $proc$libresoc.v:102839$4108 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:94566.5-94566.29" + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:102840.5-102840.29" switch \initial - attribute \src "libresoc.v:94566.9-94566.17" + attribute \src "libresoc.v:102840.9-102840.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:94620.3-94674.6" - process $proc$libresoc.v:94620$3962 + attribute \src "libresoc.v:102888.3-102936.6" + process $proc$libresoc.v:102888$4109 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:94621.5-94621.29" + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:102889.5-102889.29" switch \initial - attribute \src "libresoc.v:94621.9-94621.17" + attribute \src "libresoc.v:102889.9-102889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:94675.3-94729.6" - process $proc$libresoc.v:94675$3963 + attribute \src "libresoc.v:102937.3-102985.6" + process $proc$libresoc.v:102937$4110 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:94676.5-94676.29" + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:102938.5-102938.29" switch \initial - attribute \src "libresoc.v:94676.9-94676.17" + attribute \src "libresoc.v:102938.9-102938.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:94730.3-94784.6" - process $proc$libresoc.v:94730$3964 + attribute \src "libresoc.v:102986.3-103034.6" + process $proc$libresoc.v:102986$4111 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:94731.5-94731.29" + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:102987.5-102987.29" switch \initial - attribute \src "libresoc.v:94731.9-94731.17" + attribute \src "libresoc.v:102987.9-102987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 case - assign $1\dec31_dec_sub22_form[4:0] 5'00000 + assign $1\dec31_dec_sub21_br[0:0] 1'0 end sync always - update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:94785.3-94839.6" - process $proc$libresoc.v:94785$3965 + attribute \src "libresoc.v:103035.3-103083.6" + process $proc$libresoc.v:103035$4112 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:94786.5-94786.29" + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:103036.5-103036.29" switch \initial - attribute \src "libresoc.v:94786.9-94786.17" + attribute \src "libresoc.v:103036.9-103036.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:94840.3-94894.6" - process $proc$libresoc.v:94840$3966 + attribute \src "libresoc.v:103084.3-103132.6" + process $proc$libresoc.v:103084$4113 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:94841.5-94841.29" + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:103085.5-103085.29" switch \initial - attribute \src "libresoc.v:94841.9-94841.17" + attribute \src "libresoc.v:103085.9-103085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:94895.3-94949.6" - process $proc$libresoc.v:94895$3967 + attribute \src "libresoc.v:103133.3-103181.6" + process $proc$libresoc.v:103133$4114 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:94896.5-94896.29" + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:103134.5-103134.29" switch \initial - attribute \src "libresoc.v:94896.9-94896.17" + attribute \src "libresoc.v:103134.9-103134.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:94950.3-95004.6" - process $proc$libresoc.v:94950$3968 + attribute \src "libresoc.v:103182.3-103230.6" + process $proc$libresoc.v:103182$4115 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:94951.5-94951.29" + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:103183.5-103183.29" switch \initial - attribute \src "libresoc.v:94951.9-94951.17" + attribute \src "libresoc.v:103183.9-103183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:95005.3-95059.6" - process $proc$libresoc.v:95005$3969 + attribute \src "libresoc.v:103231.3-103279.6" + process $proc$libresoc.v:103231$4116 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:95006.5-95006.29" + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:103232.5-103232.29" switch \initial - attribute \src "libresoc.v:95006.9-95006.17" + attribute \src "libresoc.v:103232.9-103232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 case - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub21_form[4:0] 5'00000 end sync always - update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:95060.3-95114.6" - process $proc$libresoc.v:95060$3970 + attribute \src "libresoc.v:103280.3-103328.6" + process $proc$libresoc.v:103280$4117 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:95061.5-95061.29" + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:103281.5-103281.29" switch \initial - attribute \src "libresoc.v:95061.9-95061.17" + attribute \src "libresoc.v:103281.9-103281.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'11001 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "libresoc.v:103329.3-103377.6" + process $proc$libresoc.v:103329$4118 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:103330.5-103330.29" + switch \initial + attribute \src "libresoc.v:103330.9-103330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'11010 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 case - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "libresoc.v:103378.3-103408.6" + process $proc$libresoc.v:103378$4119 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:103379.5-103379.29" + switch \initial + attribute \src "libresoc.v:103379.9-103379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110010 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + end + attribute \src "libresoc.v:103409.3-103457.6" + process $proc$libresoc.v:103409$4120 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] + attribute \src "libresoc.v:103410.5-103410.29" + switch \initial + attribute \src "libresoc.v:103410.9-103410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] + end + attribute \src "libresoc.v:103458.3-103506.6" + process $proc$libresoc.v:103458$4121 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] + attribute \src "libresoc.v:103459.5-103459.29" + switch \initial + attribute \src "libresoc.v:103459.9-103459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] + end + attribute \src "libresoc.v:103507.3-103555.6" + process $proc$libresoc.v:103507$4122 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:103508.5-103508.29" + switch \initial + attribute \src "libresoc.v:103508.9-103508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:103556.3-103604.6" + process $proc$libresoc.v:103556$4123 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:103557.5-103557.29" + switch \initial + attribute \src "libresoc.v:103557.9-103557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:103605.3-103653.6" + process $proc$libresoc.v:103605$4124 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:103606.5-103606.29" + switch \initial + attribute \src "libresoc.v:103606.9-103606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + end + attribute \src "libresoc.v:103654.3-103702.6" + process $proc$libresoc.v:103654$4125 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:103655.5-103655.29" + switch \initial + attribute \src "libresoc.v:103655.9-103655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:95120.1-96555.10" +attribute \src "libresoc.v:103708.1-105808.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" -module \dec31_dec_sub23 - attribute \src "libresoc.v:95623.3-95671.6" - wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:95819.3-95867.6" - wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:96456.3-96504.6" - wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:96505.3-96553.6" - wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:95574.3-95622.6" - wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:95770.3-95818.6" - wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:96211.3-96259.6" - wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:95378.3-95426.6" - wire width 12 $0\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:96260.3-96308.6" - wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:96309.3-96357.6" - wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:96358.3-96406.6" - wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:95917.3-95965.6" - wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:95672.3-95720.6" - wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:95721.3-95769.6" - wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:96015.3-96063.6" - wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:95427.3-95475.6" - wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:96113.3-96161.6" - wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:96407.3-96455.6" - wire width 2 $0\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:95525.3-95573.6" - wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:95966.3-96014.6" - wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:96162.3-96210.6" - wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:96064.3-96112.6" - wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:95868.3-95916.6" - wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:95476.3-95524.6" - wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:95121.7-95121.20" +module \dec31_dec_sub22 + attribute \src "libresoc.v:105477.3-105531.6" + wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:105532.3-105586.6" + wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:104817.3-104871.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:105037.3-105091.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:104102.3-104156.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:104157.3-104211.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:104762.3-104816.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:104982.3-105036.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:105257.3-105311.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:104047.3-104101.6" + wire width 14 $0\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:105587.3-105641.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:105642.3-105696.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:105697.3-105751.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:104652.3-104706.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:104872.3-104926.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:104927.3-104981.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:105202.3-105256.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:104542.3-104596.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:105367.3-105421.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:105752.3-105806.6" + wire width 3 $0\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:104707.3-104761.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:105147.3-105201.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:105422.3-105476.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:105312.3-105366.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:105092.3-105146.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:104432.3-104486.6" + wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:104487.3-104541.6" + wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:104212.3-104266.6" + wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:104267.3-104321.6" + wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:104322.3-104376.6" + wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:104377.3-104431.6" + wire width 3 $0\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:104597.3-104651.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:103709.7-103709.20" wire $0\initial[0:0] - attribute \src "libresoc.v:95623.3-95671.6" - wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:95819.3-95867.6" - wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:96456.3-96504.6" - wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:96505.3-96553.6" - wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:95574.3-95622.6" - wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:95770.3-95818.6" - wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:96211.3-96259.6" - wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:95378.3-95426.6" - wire width 12 $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:96260.3-96308.6" - wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:96309.3-96357.6" - wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:96358.3-96406.6" - wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:95917.3-95965.6" - wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:95672.3-95720.6" - wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:95721.3-95769.6" - wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:96015.3-96063.6" - wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:95427.3-95475.6" - wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:96113.3-96161.6" - wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:96407.3-96455.6" - wire width 2 $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:95525.3-95573.6" - wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:95966.3-96014.6" - wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:96162.3-96210.6" - wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:96064.3-96112.6" - wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:95868.3-95916.6" - wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:95476.3-95524.6" - wire width 2 $1\dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub23_br + attribute \src "libresoc.v:105477.3-105531.6" + wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:105532.3-105586.6" + wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:104817.3-104871.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:105037.3-105091.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:104102.3-104156.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:104157.3-104211.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:104762.3-104816.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:104982.3-105036.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:105257.3-105311.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:104047.3-104101.6" + wire width 14 $1\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:105587.3-105641.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:105642.3-105696.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:105697.3-105751.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:104652.3-104706.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:104872.3-104926.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:104927.3-104981.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:105202.3-105256.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:104542.3-104596.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:105367.3-105421.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:105752.3-105806.6" + wire width 3 $1\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:104707.3-104761.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:105147.3-105201.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:105422.3-105476.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:105312.3-105366.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:105092.3-105146.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:104432.3-104486.6" + wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:104487.3-104541.6" + wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:104212.3-104266.6" + wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:104267.3-104321.6" + wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:104322.3-104376.6" + wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:104377.3-104431.6" + wire width 3 $1\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:104597.3-104651.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -149919,24 +161928,26 @@ module \dec31_dec_sub23 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub23_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub23_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub23_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -149967,31 +161978,34 @@ module \dec31_dec_sub23 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub22_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub23_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub23_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -150007,14 +162021,14 @@ module \dec31_dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub23_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub23_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -150089,3162 +162103,2931 @@ module \dec31_dec_sub23 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub23_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub23_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub22_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub23_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub23_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub22_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub22_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub22_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub23_upd - attribute \src "libresoc.v:95121.7-95121.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub22_upd + attribute \src "libresoc.v:103709.7-103709.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:95121.7-95121.20" - process $proc$libresoc.v:95121$3996 + attribute \src "libresoc.v:103709.7-103709.20" + process $proc$libresoc.v:103709$4159 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:95378.3-95426.6" - process $proc$libresoc.v:95378$3972 + attribute \src "libresoc.v:104047.3-104101.6" + process $proc$libresoc.v:104047$4127 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:95379.5-95379.29" + assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:104048.5-104048.29" switch \initial - attribute \src "libresoc.v:95379.9-95379.17" + attribute \src "libresoc.v:104048.9-104048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 case - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:95427.3-95475.6" - process $proc$libresoc.v:95427$3973 + attribute \src "libresoc.v:104102.3-104156.6" + process $proc$libresoc.v:104102$4128 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:95428.5-95428.29" + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:104103.5-104103.29" switch \initial - attribute \src "libresoc.v:95428.9-95428.17" + attribute \src "libresoc.v:104103.9-104103.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:95476.3-95524.6" - process $proc$libresoc.v:95476$3974 + attribute \src "libresoc.v:104157.3-104211.6" + process $proc$libresoc.v:104157$4129 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:95477.5-95477.29" + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:104158.5-104158.29" switch \initial - attribute \src "libresoc.v:95477.9-95477.17" + attribute \src "libresoc.v:104158.9-104158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:95525.3-95573.6" - process $proc$libresoc.v:95525$3975 + attribute \src "libresoc.v:104212.3-104266.6" + process $proc$libresoc.v:104212$4130 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:95526.5-95526.29" + assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:104213.5-104213.29" switch \initial - attribute \src "libresoc.v:95526.9-95526.17" + attribute \src "libresoc.v:104213.9-104213.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 case - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end - attribute \src "libresoc.v:95574.3-95622.6" - process $proc$libresoc.v:95574$3976 + attribute \src "libresoc.v:104267.3-104321.6" + process $proc$libresoc.v:104267$4131 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:95575.5-95575.29" + assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:104268.5-104268.29" switch \initial - attribute \src "libresoc.v:95575.9-95575.17" + attribute \src "libresoc.v:104268.9-104268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 case - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] + update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end - attribute \src "libresoc.v:95623.3-95671.6" - process $proc$libresoc.v:95623$3977 + attribute \src "libresoc.v:104322.3-104376.6" + process $proc$libresoc.v:104322$4132 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:95624.5-95624.29" + assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:104323.5-104323.29" switch \initial - attribute \src "libresoc.v:95624.9-95624.17" + attribute \src "libresoc.v:104323.9-104323.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end - attribute \src "libresoc.v:95672.3-95720.6" - process $proc$libresoc.v:95672$3978 + attribute \src "libresoc.v:104377.3-104431.6" + process $proc$libresoc.v:104377$4133 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:95673.5-95673.29" + assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:104378.5-104378.29" switch \initial - attribute \src "libresoc.v:95673.9-95673.17" + attribute \src "libresoc.v:104378.9-104378.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 case - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end - attribute \src "libresoc.v:95721.3-95769.6" - process $proc$libresoc.v:95721$3979 + attribute \src "libresoc.v:104432.3-104486.6" + process $proc$libresoc.v:104432$4134 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:95722.5-95722.29" + assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:104433.5-104433.29" switch \initial - attribute \src "libresoc.v:95722.9-95722.17" + attribute \src "libresoc.v:104433.9-104433.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] + update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end - attribute \src "libresoc.v:95770.3-95818.6" - process $proc$libresoc.v:95770$3980 + attribute \src "libresoc.v:104487.3-104541.6" + process $proc$libresoc.v:104487$4135 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:95771.5-95771.29" + assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:104488.5-104488.29" switch \initial - attribute \src "libresoc.v:95771.9-95771.17" + attribute \src "libresoc.v:104488.9-104488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] + update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end - attribute \src "libresoc.v:95819.3-95867.6" - process $proc$libresoc.v:95819$3981 + attribute \src "libresoc.v:104542.3-104596.6" + process $proc$libresoc.v:104542$4136 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:95820.5-95820.29" + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:104543.5-104543.29" switch \initial - attribute \src "libresoc.v:95820.9-95820.17" + attribute \src "libresoc.v:104543.9-104543.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub23_br[0:0] 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:95868.3-95916.6" - process $proc$libresoc.v:95868$3982 + attribute \src "libresoc.v:104597.3-104651.6" + process $proc$libresoc.v:104597$4137 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:95869.5-95869.29" + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:104598.5-104598.29" switch \initial - attribute \src "libresoc.v:95869.9-95869.17" + attribute \src "libresoc.v:104598.9-104598.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 case - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 end sync always - update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:95917.3-95965.6" - process $proc$libresoc.v:95917$3983 + attribute \src "libresoc.v:104652.3-104706.6" + process $proc$libresoc.v:104652$4138 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:95918.5-95918.29" + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:104653.5-104653.29" switch \initial - attribute \src "libresoc.v:95918.9-95918.17" + attribute \src "libresoc.v:104653.9-104653.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 case - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:95966.3-96014.6" - process $proc$libresoc.v:95966$3984 + attribute \src "libresoc.v:104707.3-104761.6" + process $proc$libresoc.v:104707$4139 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:95967.5-95967.29" + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:104708.5-104708.29" switch \initial - attribute \src "libresoc.v:95967.9-95967.17" + attribute \src "libresoc.v:104708.9-104708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 case - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:96015.3-96063.6" - process $proc$libresoc.v:96015$3985 + attribute \src "libresoc.v:104762.3-104816.6" + process $proc$libresoc.v:104762$4140 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:96016.5-96016.29" + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:104763.5-104763.29" switch \initial - attribute \src "libresoc.v:96016.9-96016.17" + attribute \src "libresoc.v:104763.9-104763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:96064.3-96112.6" - process $proc$libresoc.v:96064$3986 + attribute \src "libresoc.v:104817.3-104871.6" + process $proc$libresoc.v:104817$4141 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:96065.5-96065.29" + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:104818.5-104818.29" switch \initial - attribute \src "libresoc.v:96065.9-96065.17" + attribute \src "libresoc.v:104818.9-104818.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101111 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110101 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001010 case - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:96113.3-96161.6" - process $proc$libresoc.v:96113$3987 + attribute \src "libresoc.v:104872.3-104926.6" + process $proc$libresoc.v:104872$4142 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:96114.5-96114.29" + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:104873.5-104873.29" switch \initial - attribute \src "libresoc.v:96114.9-96114.17" + attribute \src "libresoc.v:104873.9-104873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub23_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:96162.3-96210.6" - process $proc$libresoc.v:96162$3988 + attribute \src "libresoc.v:104927.3-104981.6" + process $proc$libresoc.v:104927$4143 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:96163.5-96163.29" + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:104928.5-104928.29" switch \initial - attribute \src "libresoc.v:96163.9-96163.17" + attribute \src "libresoc.v:104928.9-104928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:96211.3-96259.6" - process $proc$libresoc.v:96211$3989 + attribute \src "libresoc.v:104982.3-105036.6" + process $proc$libresoc.v:104982$4144 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:96212.5-96212.29" + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:104983.5-104983.29" switch \initial - attribute \src "libresoc.v:96212.9-96212.17" + attribute \src "libresoc.v:104983.9-104983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub23_form[4:0] 5'00000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:96260.3-96308.6" - process $proc$libresoc.v:96260$3990 + attribute \src "libresoc.v:105037.3-105091.6" + process $proc$libresoc.v:105037$4145 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:96261.5-96261.29" + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:105038.5-105038.29" switch \initial - attribute \src "libresoc.v:96261.9-96261.17" + attribute \src "libresoc.v:105038.9-105038.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 case - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_br[0:0] 1'0 end sync always - update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:96309.3-96357.6" - process $proc$libresoc.v:96309$3991 + attribute \src "libresoc.v:105092.3-105146.6" + process $proc$libresoc.v:105092$4146 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:96310.5-96310.29" + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:105093.5-105093.29" switch \initial - attribute \src "libresoc.v:96310.9-96310.17" + attribute \src "libresoc.v:105093.9-105093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:96358.3-96406.6" - process $proc$libresoc.v:96358$3992 + attribute \src "libresoc.v:105147.3-105201.6" + process $proc$libresoc.v:105147$4147 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:96359.5-96359.29" + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:105148.5-105148.29" switch \initial - attribute \src "libresoc.v:96359.9-96359.17" + attribute \src "libresoc.v:105148.9-105148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:96407.3-96455.6" - process $proc$libresoc.v:96407$3993 + attribute \src "libresoc.v:105202.3-105256.6" + process $proc$libresoc.v:105202$4148 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:96408.5-96408.29" + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:105203.5-105203.29" switch \initial - attribute \src "libresoc.v:96408.9-96408.17" + attribute \src "libresoc.v:105203.9-105203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:96456.3-96504.6" - process $proc$libresoc.v:96456$3994 + attribute \src "libresoc.v:105257.3-105311.6" + process $proc$libresoc.v:105257$4149 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:96457.5-96457.29" + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:105258.5-105258.29" switch \initial - attribute \src "libresoc.v:96457.9-96457.17" + attribute \src "libresoc.v:105258.9-105258.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 case - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'00000 end sync always - update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:96505.3-96553.6" - process $proc$libresoc.v:96505$3995 + attribute \src "libresoc.v:105312.3-105366.6" + process $proc$libresoc.v:105312$4150 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:96506.5-96506.29" + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:105313.5-105313.29" switch \initial - attribute \src "libresoc.v:96506.9-96506.17" + attribute \src "libresoc.v:105313.9-105313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11111 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:96559.1-97274.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" -attribute \generator "nMigen" -module \dec31_dec_sub24 - attribute \src "libresoc.v:96912.3-96930.6" - wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:96988.3-97006.6" - wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:97235.3-97253.6" - wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:97254.3-97272.6" - wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:96893.3-96911.6" - wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:96969.3-96987.6" - wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:97140.3-97158.6" - wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:96817.3-96835.6" - wire width 12 $0\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:97159.3-97177.6" - wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:97178.3-97196.6" - wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:97197.3-97215.6" - wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:97026.3-97044.6" - wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:96931.3-96949.6" - wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:96950.3-96968.6" - wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:97064.3-97082.6" - wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:96836.3-96854.6" - wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:97102.3-97120.6" - wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:97216.3-97234.6" - wire width 2 $0\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:96874.3-96892.6" - wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:97045.3-97063.6" - wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:97121.3-97139.6" - wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:97083.3-97101.6" - wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:97007.3-97025.6" - wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:96855.3-96873.6" - wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:96560.7-96560.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:96912.3-96930.6" - wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:96988.3-97006.6" - wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:97235.3-97253.6" - wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:97254.3-97272.6" - wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:96893.3-96911.6" - wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:96969.3-96987.6" - wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:97140.3-97158.6" - wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:96817.3-96835.6" - wire width 12 $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:97159.3-97177.6" - wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:97178.3-97196.6" - wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:97197.3-97215.6" - wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:97026.3-97044.6" - wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:96931.3-96949.6" - wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:96950.3-96968.6" - wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:97064.3-97082.6" - wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:96836.3-96854.6" - wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:97102.3-97120.6" - wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:97216.3-97234.6" - wire width 2 $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:96874.3-96892.6" - wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:97045.3-97063.6" - wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:97121.3-97139.6" - wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:97083.3-97101.6" - wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:97007.3-97025.6" - wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:96855.3-96873.6" - wire width 2 $1\dec31_dec_sub24_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub24_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub24_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub24_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub24_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub24_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub24_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub24_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub24_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub24_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub24_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub24_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub24_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub24_upd - attribute \src "libresoc.v:96560.7-96560.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:96560.7-96560.20" - process $proc$libresoc.v:96560$4021 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:96817.3-96835.6" - process $proc$libresoc.v:96817$3997 + attribute \src "libresoc.v:105367.3-105421.6" + process $proc$libresoc.v:105367$4151 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:96818.5-96818.29" + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:105368.5-105368.29" switch \initial - attribute \src "libresoc.v:96818.9-96818.17" + attribute \src "libresoc.v:105368.9-105368.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] - end - attribute \src "libresoc.v:96836.3-96854.6" - process $proc$libresoc.v:96836$3998 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:96837.5-96837.29" - switch \initial - attribute \src "libresoc.v:96837.9-96837.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] - end - attribute \src "libresoc.v:96855.3-96873.6" - process $proc$libresoc.v:96855$3999 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:96856.5-96856.29" - switch \initial - attribute \src "libresoc.v:96856.9-96856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 case - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 end sync always - update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:96874.3-96892.6" - process $proc$libresoc.v:96874$4000 + attribute \src "libresoc.v:105422.3-105476.6" + process $proc$libresoc.v:105422$4152 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:96875.5-96875.29" + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:105423.5-105423.29" switch \initial - attribute \src "libresoc.v:96875.9-96875.17" + attribute \src "libresoc.v:105423.9-105423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] - end - attribute \src "libresoc.v:96893.3-96911.6" - process $proc$libresoc.v:96893$4001 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:96894.5-96894.29" - switch \initial - attribute \src "libresoc.v:96894.9-96894.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] - end - attribute \src "libresoc.v:96912.3-96930.6" - process $proc$libresoc.v:96912$4002 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:96913.5-96913.29" - switch \initial - attribute \src "libresoc.v:96913.9-96913.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 case - assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:96931.3-96949.6" - process $proc$libresoc.v:96931$4003 + attribute \src "libresoc.v:105477.3-105531.6" + process $proc$libresoc.v:105477$4153 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:96932.5-96932.29" + assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:105478.5-105478.29" switch \initial - attribute \src "libresoc.v:96932.9-96932.17" + attribute \src "libresoc.v:105478.9-105478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] - end - attribute \src "libresoc.v:96950.3-96968.6" - process $proc$libresoc.v:96950$4004 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:96951.5-96951.29" - switch \initial - attribute \src "libresoc.v:96951.9-96951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] - end - attribute \src "libresoc.v:96969.3-96987.6" - process $proc$libresoc.v:96969$4005 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:96970.5-96970.29" - switch \initial - attribute \src "libresoc.v:96970.9-96970.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 case - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 end sync always - update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end - attribute \src "libresoc.v:96988.3-97006.6" - process $proc$libresoc.v:96988$4006 + attribute \src "libresoc.v:105532.3-105586.6" + process $proc$libresoc.v:105532$4154 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:96989.5-96989.29" + assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:105533.5-105533.29" switch \initial - attribute \src "libresoc.v:96989.9-96989.17" + attribute \src "libresoc.v:105533.9-105533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - case - assign $1\dec31_dec_sub24_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] - end - attribute \src "libresoc.v:97007.3-97025.6" - process $proc$libresoc.v:97007$4007 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:97008.5-97008.29" - switch \initial - attribute \src "libresoc.v:97008.9-97008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] - end - attribute \src "libresoc.v:97026.3-97044.6" - process $proc$libresoc.v:97026$4008 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:97027.5-97027.29" - switch \initial - attribute \src "libresoc.v:97027.9-97027.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 case - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end - attribute \src "libresoc.v:97045.3-97063.6" - process $proc$libresoc.v:97045$4009 + attribute \src "libresoc.v:105587.3-105641.6" + process $proc$libresoc.v:105587$4155 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:97046.5-97046.29" + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:105588.5-105588.29" switch \initial - attribute \src "libresoc.v:97046.9-97046.17" + attribute \src "libresoc.v:105588.9-105588.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] - end - attribute \src "libresoc.v:97064.3-97082.6" - process $proc$libresoc.v:97064$4010 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:97065.5-97065.29" - switch \initial - attribute \src "libresoc.v:97065.9-97065.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] - end - attribute \src "libresoc.v:97083.3-97101.6" - process $proc$libresoc.v:97083$4011 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:97084.5-97084.29" - switch \initial - attribute \src "libresoc.v:97084.9-97084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 case - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 end sync always - update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:97102.3-97120.6" - process $proc$libresoc.v:97102$4012 + attribute \src "libresoc.v:105642.3-105696.6" + process $proc$libresoc.v:105642$4156 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:97103.5-97103.29" + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:105643.5-105643.29" switch \initial - attribute \src "libresoc.v:97103.9-97103.17" + attribute \src "libresoc.v:105643.9-105643.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] - end - attribute \src "libresoc.v:97121.3-97139.6" - process $proc$libresoc.v:97121$4013 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:97122.5-97122.29" - switch \initial - attribute \src "libresoc.v:97122.9-97122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] - end - attribute \src "libresoc.v:97140.3-97158.6" - process $proc$libresoc.v:97140$4014 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:97141.5-97141.29" - switch \initial - attribute \src "libresoc.v:97141.9-97141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 case - assign $1\dec31_dec_sub24_form[4:0] 5'00000 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 end sync always - update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:97159.3-97177.6" - process $proc$libresoc.v:97159$4015 + attribute \src "libresoc.v:105697.3-105751.6" + process $proc$libresoc.v:105697$4157 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:97160.5-97160.29" + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:105698.5-105698.29" switch \initial - attribute \src "libresoc.v:97160.9-97160.17" + attribute \src "libresoc.v:105698.9-105698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] - end - attribute \src "libresoc.v:97178.3-97196.6" - process $proc$libresoc.v:97178$4016 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:97179.5-97179.29" - switch \initial - attribute \src "libresoc.v:97179.9-97179.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] - end - attribute \src "libresoc.v:97197.3-97215.6" - process $proc$libresoc.v:97197$4017 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:97198.5-97198.29" - switch \initial - attribute \src "libresoc.v:97198.9-97198.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 case - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 end sync always - update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:97216.3-97234.6" - process $proc$libresoc.v:97216$4018 + attribute \src "libresoc.v:105752.3-105806.6" + process $proc$libresoc.v:105752$4158 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:97217.5-97217.29" + assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:105753.5-105753.29" switch \initial - attribute \src "libresoc.v:97217.9-97217.17" + attribute \src "libresoc.v:105753.9-105753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] - end - attribute \src "libresoc.v:97235.3-97253.6" - process $proc$libresoc.v:97235$4019 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:97236.5-97236.29" - switch \initial - attribute \src "libresoc.v:97236.9-97236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10101 assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] - end - attribute \src "libresoc.v:97254.3-97272.6" - process $proc$libresoc.v:97254$4020 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:97255.5-97255.29" - switch \initial - attribute \src "libresoc.v:97255.9-97255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:97278.1-98785.10" +attribute \src "libresoc.v:105812.1-107720.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" -module \dec31_dec_sub26 - attribute \src "libresoc.v:97796.3-97847.6" - wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:98004.3-98055.6" - wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:98680.3-98731.6" - wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:98732.3-98783.6" - wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:97744.3-97795.6" - wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:97952.3-98003.6" - wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:98420.3-98471.6" - wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:97536.3-97587.6" - wire width 12 $0\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:98472.3-98523.6" - wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:98524.3-98575.6" - wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:98576.3-98627.6" - wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:98108.3-98159.6" - wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:97848.3-97899.6" - wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:97900.3-97951.6" - wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:98212.3-98263.6" - wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:97588.3-97639.6" - wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:98316.3-98367.6" - wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:98628.3-98679.6" - wire width 2 $0\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:97692.3-97743.6" - wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:98160.3-98211.6" - wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:98368.3-98419.6" - wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:98264.3-98315.6" - wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:98056.3-98107.6" - wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:97640.3-97691.6" - wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:97279.7-97279.20" +module \dec31_dec_sub23 + attribute \src "libresoc.v:107425.3-107473.6" + wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:107474.3-107522.6" + wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:106837.3-106885.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:107033.3-107081.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:106200.3-106248.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:106249.3-106297.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:106788.3-106836.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:106984.3-107032.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:107229.3-107277.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:106151.3-106199.6" + wire width 14 $0\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:107523.3-107571.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:107572.3-107620.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:107621.3-107669.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:106690.3-106738.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:106886.3-106934.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:106935.3-106983.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:107180.3-107228.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:106592.3-106640.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:107327.3-107375.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:107670.3-107718.6" + wire width 3 $0\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:106739.3-106787.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:107131.3-107179.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:107376.3-107424.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:107278.3-107326.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:107082.3-107130.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:106494.3-106542.6" + wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:106543.3-106591.6" + wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:106298.3-106346.6" + wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:106347.3-106395.6" + wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:106396.3-106444.6" + wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:106445.3-106493.6" + wire width 3 $0\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:106641.3-106689.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:105813.7-105813.20" wire $0\initial[0:0] - attribute \src "libresoc.v:97796.3-97847.6" - wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:98004.3-98055.6" - wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:98680.3-98731.6" - wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:98732.3-98783.6" - wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:97744.3-97795.6" - wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:97952.3-98003.6" - wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:98420.3-98471.6" - wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:97536.3-97587.6" - wire width 12 $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:98472.3-98523.6" - wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:98524.3-98575.6" - wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:98576.3-98627.6" - wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:98108.3-98159.6" - wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:97848.3-97899.6" - wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:97900.3-97951.6" - wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:98212.3-98263.6" - wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:97588.3-97639.6" - wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:98316.3-98367.6" - wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:98628.3-98679.6" - wire width 2 $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:97692.3-97743.6" - wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:98160.3-98211.6" - wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:98368.3-98419.6" - wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:98264.3-98315.6" - wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:98056.3-98107.6" - wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:97640.3-97691.6" - wire width 2 $1\dec31_dec_sub26_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub26_br + attribute \src "libresoc.v:107425.3-107473.6" + wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:107474.3-107522.6" + wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:106837.3-106885.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:107033.3-107081.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:106200.3-106248.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:106249.3-106297.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:106788.3-106836.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:106984.3-107032.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:107229.3-107277.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:106151.3-106199.6" + wire width 14 $1\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:107523.3-107571.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:107572.3-107620.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:107621.3-107669.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:106690.3-106738.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:106886.3-106934.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:106935.3-106983.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:107180.3-107228.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:106592.3-106640.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:107327.3-107375.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:107670.3-107718.6" + wire width 3 $1\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:106739.3-106787.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:107131.3-107179.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:107376.3-107424.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:107278.3-107326.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:107082.3-107130.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:106494.3-106542.6" + wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:106543.3-106591.6" + wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:106298.3-106346.6" + wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:106347.3-106395.6" + wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:106396.3-106444.6" + wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:106445.3-106493.6" + wire width 3 $1\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:106641.3-106689.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub23_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub23_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -153253,24 +165036,26 @@ module \dec31_dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub26_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub26_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub26_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -153301,31 +165086,34 @@ module \dec31_dec_sub26 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub23_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub26_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -153341,14 +165129,14 @@ module \dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub26_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub26_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -153423,2071 +165211,2675 @@ module \dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub26_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub26_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub23_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub26_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub26_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub23_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub23_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub23_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub23_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub23_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub23_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub26_upd - attribute \src "libresoc.v:97279.7-97279.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub23_upd + attribute \src "libresoc.v:105813.7-105813.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:97279.7-97279.20" - process $proc$libresoc.v:97279$4046 + attribute \src "libresoc.v:105813.7-105813.20" + process $proc$libresoc.v:105813$4192 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:97536.3-97587.6" - process $proc$libresoc.v:97536$4022 + attribute \src "libresoc.v:106151.3-106199.6" + process $proc$libresoc.v:106151$4160 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:97537.5-97537.29" + assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:106152.5-106152.29" switch \initial - attribute \src "libresoc.v:97537.9-97537.17" + attribute \src "libresoc.v:106152.9-106152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 case - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:97588.3-97639.6" - process $proc$libresoc.v:97588$4023 + attribute \src "libresoc.v:106200.3-106248.6" + process $proc$libresoc.v:106200$4161 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:97589.5-97589.29" + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:106201.5-106201.29" switch \initial - attribute \src "libresoc.v:97589.9-97589.17" + attribute \src "libresoc.v:106201.9-106201.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:97640.3-97691.6" - process $proc$libresoc.v:97640$4024 + attribute \src "libresoc.v:106249.3-106297.6" + process $proc$libresoc.v:106249$4162 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:97641.5-97641.29" + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:106250.5-106250.29" switch \initial - attribute \src "libresoc.v:97641.9-97641.17" + attribute \src "libresoc.v:106250.9-106250.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:97692.3-97743.6" - process $proc$libresoc.v:97692$4025 + attribute \src "libresoc.v:106298.3-106346.6" + process $proc$libresoc.v:106298$4163 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:97693.5-97693.29" + assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:106299.5-106299.29" switch \initial - attribute \src "libresoc.v:97693.9-97693.17" + attribute \src "libresoc.v:106299.9-106299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 case - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] + update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end - attribute \src "libresoc.v:97744.3-97795.6" - process $proc$libresoc.v:97744$4026 + attribute \src "libresoc.v:106347.3-106395.6" + process $proc$libresoc.v:106347$4164 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:97745.5-97745.29" + assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:106348.5-106348.29" switch \initial - attribute \src "libresoc.v:97745.9-97745.17" + attribute \src "libresoc.v:106348.9-106348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 case - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end - attribute \src "libresoc.v:97796.3-97847.6" - process $proc$libresoc.v:97796$4027 + attribute \src "libresoc.v:106396.3-106444.6" + process $proc$libresoc.v:106396$4165 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:97797.5-97797.29" + assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:106397.5-106397.29" switch \initial - attribute \src "libresoc.v:97797.9-97797.17" + attribute \src "libresoc.v:106397.9-106397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 case - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end - attribute \src "libresoc.v:97848.3-97899.6" - process $proc$libresoc.v:97848$4028 + attribute \src "libresoc.v:106445.3-106493.6" + process $proc$libresoc.v:106445$4166 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:97849.5-97849.29" + assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:106446.5-106446.29" switch \initial - attribute \src "libresoc.v:97849.9-97849.17" + attribute \src "libresoc.v:106446.9-106446.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 case - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] + update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end - attribute \src "libresoc.v:97900.3-97951.6" - process $proc$libresoc.v:97900$4029 + attribute \src "libresoc.v:106494.3-106542.6" + process $proc$libresoc.v:106494$4167 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:97901.5-97901.29" + assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:106495.5-106495.29" switch \initial - attribute \src "libresoc.v:97901.9-97901.17" + attribute \src "libresoc.v:106495.9-106495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end - attribute \src "libresoc.v:97952.3-98003.6" - process $proc$libresoc.v:97952$4030 + attribute \src "libresoc.v:106543.3-106591.6" + process $proc$libresoc.v:106543$4168 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:97953.5-97953.29" + assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:106544.5-106544.29" switch \initial - attribute \src "libresoc.v:97953.9-97953.17" + attribute \src "libresoc.v:106544.9-106544.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end - attribute \src "libresoc.v:98004.3-98055.6" - process $proc$libresoc.v:98004$4031 + attribute \src "libresoc.v:106592.3-106640.6" + process $proc$libresoc.v:106592$4169 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:98005.5-98005.29" + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:106593.5-106593.29" switch \initial - attribute \src "libresoc.v:98005.9-98005.17" + attribute \src "libresoc.v:106593.9-106593.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 case - assign $1\dec31_dec_sub26_br[0:0] 1'0 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:98056.3-98107.6" - process $proc$libresoc.v:98056$4032 + attribute \src "libresoc.v:106641.3-106689.6" + process $proc$libresoc.v:106641$4170 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:98057.5-98057.29" + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:106642.5-106642.29" switch \initial - attribute \src "libresoc.v:98057.9-98057.17" + attribute \src "libresoc.v:106642.9-106642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 case - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 end sync always - update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:98108.3-98159.6" - process $proc$libresoc.v:98108$4033 + attribute \src "libresoc.v:106690.3-106738.6" + process $proc$libresoc.v:106690$4171 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:98109.5-98109.29" + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:106691.5-106691.29" switch \initial - attribute \src "libresoc.v:98109.9-98109.17" + attribute \src "libresoc.v:106691.9-106691.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:98160.3-98211.6" - process $proc$libresoc.v:98160$4034 + attribute \src "libresoc.v:106739.3-106787.6" + process $proc$libresoc.v:106739$4172 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:98161.5-98161.29" + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:106740.5-106740.29" switch \initial - attribute \src "libresoc.v:98161.9-98161.17" + attribute \src "libresoc.v:106740.9-106740.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 case - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:98212.3-98263.6" - process $proc$libresoc.v:98212$4035 + attribute \src "libresoc.v:106788.3-106836.6" + process $proc$libresoc.v:106788$4173 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:98213.5-98213.29" + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:106789.5-106789.29" switch \initial - attribute \src "libresoc.v:98213.9-98213.17" + attribute \src "libresoc.v:106789.9-106789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:98264.3-98315.6" - process $proc$libresoc.v:98264$4036 + attribute \src "libresoc.v:106837.3-106885.6" + process $proc$libresoc.v:106837$4174 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:98265.5-98265.29" + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:106838.5-106838.29" switch \initial - attribute \src "libresoc.v:98265.9-98265.17" + attribute \src "libresoc.v:106838.9-106838.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101100 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111110 case - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:98316.3-98367.6" - process $proc$libresoc.v:98316$4037 + attribute \src "libresoc.v:106886.3-106934.6" + process $proc$libresoc.v:106886$4175 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:98317.5-98317.29" + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:106887.5-106887.29" switch \initial - attribute \src "libresoc.v:98317.9-98317.17" + attribute \src "libresoc.v:106887.9-106887.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub26_lk[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:98368.3-98419.6" - process $proc$libresoc.v:98368$4038 + attribute \src "libresoc.v:106935.3-106983.6" + process $proc$libresoc.v:106935$4176 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:98369.5-98369.29" + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:106936.5-106936.29" switch \initial - attribute \src "libresoc.v:98369.9-98369.17" + attribute \src "libresoc.v:106936.9-106936.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:98420.3-98471.6" - process $proc$libresoc.v:98420$4039 + attribute \src "libresoc.v:106984.3-107032.6" + process $proc$libresoc.v:106984$4177 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:98421.5-98421.29" + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:106985.5-106985.29" switch \initial - attribute \src "libresoc.v:98421.9-98421.17" + attribute \src "libresoc.v:106985.9-106985.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub26_form[4:0] 5'00000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:98472.3-98523.6" - process $proc$libresoc.v:98472$4040 + attribute \src "libresoc.v:107033.3-107081.6" + process $proc$libresoc.v:107033$4178 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:98473.5-98473.29" + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:107034.5-107034.29" switch \initial - attribute \src "libresoc.v:98473.9-98473.17" + attribute \src "libresoc.v:107034.9-107034.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:107082.3-107130.6" + process $proc$libresoc.v:107082$4179 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:107083.5-107083.29" + switch \initial + attribute \src "libresoc.v:107083.9-107083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:98524.3-98575.6" - process $proc$libresoc.v:98524$4041 + attribute \src "libresoc.v:107131.3-107179.6" + process $proc$libresoc.v:107131$4180 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:98525.5-98525.29" + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:107132.5-107132.29" switch \initial - attribute \src "libresoc.v:98525.9-98525.17" + attribute \src "libresoc.v:107132.9-107132.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + end + attribute \src "libresoc.v:107180.3-107228.6" + process $proc$libresoc.v:107180$4181 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:107181.5-107181.29" + switch \initial + attribute \src "libresoc.v:107181.9-107181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:98576.3-98627.6" - process $proc$libresoc.v:98576$4042 + attribute \src "libresoc.v:107229.3-107277.6" + process $proc$libresoc.v:107229$4182 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:98577.5-98577.29" + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:107230.5-107230.29" switch \initial - attribute \src "libresoc.v:98577.9-98577.17" + attribute \src "libresoc.v:107230.9-107230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + end + attribute \src "libresoc.v:107278.3-107326.6" + process $proc$libresoc.v:107278$4183 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:107279.5-107279.29" + switch \initial + attribute \src "libresoc.v:107279.9-107279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01010 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:98628.3-98679.6" - process $proc$libresoc.v:98628$4043 + attribute \src "libresoc.v:107327.3-107375.6" + process $proc$libresoc.v:107327$4184 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:98629.5-98629.29" + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:107328.5-107328.29" switch \initial - attribute \src "libresoc.v:98629.9-98629.17" + attribute \src "libresoc.v:107328.9-107328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + end + attribute \src "libresoc.v:107376.3-107424.6" + process $proc$libresoc.v:107376$4185 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:107377.5-107377.29" + switch \initial + attribute \src "libresoc.v:107377.9-107377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 case - assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:98680.3-98731.6" - process $proc$libresoc.v:98680$4044 + attribute \src "libresoc.v:107425.3-107473.6" + process $proc$libresoc.v:107425$4186 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:98681.5-98681.29" + assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:107426.5-107426.29" switch \initial - attribute \src "libresoc.v:98681.9-98681.17" + attribute \src "libresoc.v:107426.9-107426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] + end + attribute \src "libresoc.v:107474.3-107522.6" + process $proc$libresoc.v:107474$4187 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:107475.5-107475.29" + switch \initial + attribute \src "libresoc.v:107475.9-107475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] + end + attribute \src "libresoc.v:107523.3-107571.6" + process $proc$libresoc.v:107523$4188 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:107524.5-107524.29" + switch \initial + attribute \src "libresoc.v:107524.9-107524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 case - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 end sync always - update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:98732.3-98783.6" - process $proc$libresoc.v:98732$4045 + attribute \src "libresoc.v:107572.3-107620.6" + process $proc$libresoc.v:107572$4189 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:98733.5-98733.29" + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:107573.5-107573.29" switch \initial - attribute \src "libresoc.v:98733.9-98733.17" + attribute \src "libresoc.v:107573.9-107573.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:107621.3-107669.6" + process $proc$libresoc.v:107621$4190 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:107622.5-107622.29" + switch \initial + attribute \src "libresoc.v:107622.9-107622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + end + attribute \src "libresoc.v:107670.3-107718.6" + process $proc$libresoc.v:107670$4191 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:107671.5-107671.29" + switch \initial + attribute \src "libresoc.v:107671.9-107671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98789.1-99504.10" +attribute \src "libresoc.v:107724.1-108672.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" -module \dec31_dec_sub27 - attribute \src "libresoc.v:99142.3-99160.6" - wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:99218.3-99236.6" - wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:99465.3-99483.6" - wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:99484.3-99502.6" - wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:99123.3-99141.6" - wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:99199.3-99217.6" - wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:99370.3-99388.6" - wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:99047.3-99065.6" - wire width 12 $0\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:99389.3-99407.6" - wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:99408.3-99426.6" - wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:99427.3-99445.6" - wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:99256.3-99274.6" - wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:99161.3-99179.6" - wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:99180.3-99198.6" - wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:99294.3-99312.6" - wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:99066.3-99084.6" - wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:99332.3-99350.6" - wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:99446.3-99464.6" - wire width 2 $0\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:99104.3-99122.6" - wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:99275.3-99293.6" - wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:99351.3-99369.6" - wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:99313.3-99331.6" - wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:99237.3-99255.6" - wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:99085.3-99103.6" - wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:98790.7-98790.20" +module \dec31_dec_sub24 + attribute \src "libresoc.v:108557.3-108575.6" + wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:108576.3-108594.6" + wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:108329.3-108347.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:108405.3-108423.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:108082.3-108100.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:108101.3-108119.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:108310.3-108328.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:108386.3-108404.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:108481.3-108499.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:108063.3-108081.6" + wire width 14 $0\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:108595.3-108613.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:108614.3-108632.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:108633.3-108651.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:108272.3-108290.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:108348.3-108366.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:108367.3-108385.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:108462.3-108480.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:108234.3-108252.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:108519.3-108537.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:108652.3-108670.6" + wire width 3 $0\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:108291.3-108309.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:108443.3-108461.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:108538.3-108556.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:108500.3-108518.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:108424.3-108442.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:108196.3-108214.6" + wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:108215.3-108233.6" + wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:108120.3-108138.6" + wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:108139.3-108157.6" + wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:108158.3-108176.6" + wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:108177.3-108195.6" + wire width 3 $0\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:108253.3-108271.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:107725.7-107725.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99142.3-99160.6" - wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:99218.3-99236.6" - wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:99465.3-99483.6" - wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:99484.3-99502.6" - wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:99123.3-99141.6" - wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:99199.3-99217.6" - wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:99370.3-99388.6" - wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:99047.3-99065.6" - wire width 12 $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:99389.3-99407.6" - wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:99408.3-99426.6" - wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:99427.3-99445.6" - wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:99256.3-99274.6" - wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:99161.3-99179.6" - wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:99180.3-99198.6" - wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:99294.3-99312.6" - wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:99066.3-99084.6" - wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:99332.3-99350.6" - wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:99446.3-99464.6" - wire width 2 $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:99104.3-99122.6" - wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:99275.3-99293.6" - wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:99351.3-99369.6" - wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:99313.3-99331.6" - wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:99237.3-99255.6" - wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:99085.3-99103.6" - wire width 2 $1\dec31_dec_sub27_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub27_br + attribute \src "libresoc.v:108557.3-108575.6" + wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:108576.3-108594.6" + wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:108329.3-108347.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:108405.3-108423.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:108082.3-108100.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:108101.3-108119.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:108310.3-108328.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:108386.3-108404.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:108481.3-108499.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:108063.3-108081.6" + wire width 14 $1\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:108595.3-108613.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:108614.3-108632.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:108633.3-108651.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:108272.3-108290.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:108348.3-108366.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:108367.3-108385.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:108462.3-108480.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:108234.3-108252.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:108519.3-108537.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:108652.3-108670.6" + wire width 3 $1\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:108291.3-108309.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:108443.3-108461.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:108538.3-108556.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:108500.3-108518.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:108424.3-108442.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:108196.3-108214.6" + wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:108215.3-108233.6" + wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:108120.3-108138.6" + wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:108139.3-108157.6" + wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:108158.3-108176.6" + wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:108177.3-108195.6" + wire width 3 $1\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:108253.3-108271.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub24_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub24_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -155496,24 +167888,26 @@ module \dec31_dec_sub27 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub27_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub27_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub27_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -155544,31 +167938,34 @@ module \dec31_dec_sub27 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub24_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub27_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub27_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -155584,14 +167981,14 @@ module \dec31_dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub27_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub27_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -155666,1015 +168063,1395 @@ module \dec31_dec_sub27 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub27_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub27_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub24_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub27_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub27_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub24_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub24_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub24_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub24_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub24_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub24_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub27_upd - attribute \src "libresoc.v:98790.7-98790.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub24_upd + attribute \src "libresoc.v:107725.7-107725.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:98790.7-98790.20" - process $proc$libresoc.v:98790$4071 + attribute \src "libresoc.v:107725.7-107725.20" + process $proc$libresoc.v:107725$4225 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:99047.3-99065.6" - process $proc$libresoc.v:99047$4047 + attribute \src "libresoc.v:108063.3-108081.6" + process $proc$libresoc.v:108063$4193 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:99048.5-99048.29" + assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:108064.5-108064.29" switch \initial - attribute \src "libresoc.v:99048.9-99048.17" + attribute \src "libresoc.v:108064.9-108064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 case - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:99066.3-99084.6" - process $proc$libresoc.v:99066$4048 + attribute \src "libresoc.v:108082.3-108100.6" + process $proc$libresoc.v:108082$4194 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:99067.5-99067.29" + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:108083.5-108083.29" switch \initial - attribute \src "libresoc.v:99067.9-99067.17" + attribute \src "libresoc.v:108083.9-108083.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:99085.3-99103.6" - process $proc$libresoc.v:99085$4049 + attribute \src "libresoc.v:108101.3-108119.6" + process $proc$libresoc.v:108101$4195 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:99086.5-99086.29" + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:108102.5-108102.29" switch \initial - attribute \src "libresoc.v:99086.9-99086.17" + attribute \src "libresoc.v:108102.9-108102.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:99104.3-99122.6" - process $proc$libresoc.v:99104$4050 + attribute \src "libresoc.v:108120.3-108138.6" + process $proc$libresoc.v:108120$4196 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:99105.5-99105.29" + assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:108121.5-108121.29" switch \initial - attribute \src "libresoc.v:99105.9-99105.17" + attribute \src "libresoc.v:108121.9-108121.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 case - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end - attribute \src "libresoc.v:99123.3-99141.6" - process $proc$libresoc.v:99123$4051 + attribute \src "libresoc.v:108139.3-108157.6" + process $proc$libresoc.v:108139$4197 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:99124.5-99124.29" + assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:108140.5-108140.29" switch \initial - attribute \src "libresoc.v:99124.9-99124.17" + attribute \src "libresoc.v:108140.9-108140.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 case - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end - attribute \src "libresoc.v:99142.3-99160.6" - process $proc$libresoc.v:99142$4052 + attribute \src "libresoc.v:108158.3-108176.6" + process $proc$libresoc.v:108158$4198 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:99143.5-99143.29" + assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:108159.5-108159.29" switch \initial - attribute \src "libresoc.v:99143.9-99143.17" + attribute \src "libresoc.v:108159.9-108159.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 case - assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end - attribute \src "libresoc.v:99161.3-99179.6" - process $proc$libresoc.v:99161$4053 + attribute \src "libresoc.v:108177.3-108195.6" + process $proc$libresoc.v:108177$4199 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:99162.5-99162.29" + assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:108178.5-108178.29" switch \initial - attribute \src "libresoc.v:99162.9-99162.17" + attribute \src "libresoc.v:108178.9-108178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 case - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end - attribute \src "libresoc.v:99180.3-99198.6" - process $proc$libresoc.v:99180$4054 + attribute \src "libresoc.v:108196.3-108214.6" + process $proc$libresoc.v:108196$4200 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:99181.5-99181.29" + assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:108197.5-108197.29" switch \initial - attribute \src "libresoc.v:99181.9-99181.17" + attribute \src "libresoc.v:108197.9-108197.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end - attribute \src "libresoc.v:99199.3-99217.6" - process $proc$libresoc.v:99199$4055 + attribute \src "libresoc.v:108215.3-108233.6" + process $proc$libresoc.v:108215$4201 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:99200.5-99200.29" + assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:108216.5-108216.29" switch \initial - attribute \src "libresoc.v:99200.9-99200.17" + attribute \src "libresoc.v:108216.9-108216.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end - attribute \src "libresoc.v:99218.3-99236.6" - process $proc$libresoc.v:99218$4056 + attribute \src "libresoc.v:108234.3-108252.6" + process $proc$libresoc.v:108234$4202 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:99219.5-99219.29" + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:108235.5-108235.29" switch \initial - attribute \src "libresoc.v:99219.9-99219.17" + attribute \src "libresoc.v:108235.9-108235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub27_br[0:0] 1'0 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:99237.3-99255.6" - process $proc$libresoc.v:99237$4057 + attribute \src "libresoc.v:108253.3-108271.6" + process $proc$libresoc.v:108253$4203 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:99238.5-99238.29" + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:108254.5-108254.29" switch \initial - attribute \src "libresoc.v:99238.9-99238.17" + attribute \src "libresoc.v:108254.9-108254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 case - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 end sync always - update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:99256.3-99274.6" - process $proc$libresoc.v:99256$4058 + attribute \src "libresoc.v:108272.3-108290.6" + process $proc$libresoc.v:108272$4204 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:99257.5-99257.29" + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:108273.5-108273.29" switch \initial - attribute \src "libresoc.v:99257.9-99257.17" + attribute \src "libresoc.v:108273.9-108273.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:99275.3-99293.6" - process $proc$libresoc.v:99275$4059 + attribute \src "libresoc.v:108291.3-108309.6" + process $proc$libresoc.v:108291$4205 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:99276.5-99276.29" + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:108292.5-108292.29" switch \initial - attribute \src "libresoc.v:99276.9-99276.17" + attribute \src "libresoc.v:108292.9-108292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 case - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:99294.3-99312.6" - process $proc$libresoc.v:99294$4060 + attribute \src "libresoc.v:108310.3-108328.6" + process $proc$libresoc.v:108310$4206 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:99295.5-99295.29" + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:108311.5-108311.29" switch \initial - attribute \src "libresoc.v:99295.9-99295.17" + attribute \src "libresoc.v:108311.9-108311.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:99313.3-99331.6" - process $proc$libresoc.v:99313$4061 + attribute \src "libresoc.v:108329.3-108347.6" + process $proc$libresoc.v:108329$4207 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:99314.5-99314.29" + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:108330.5-108330.29" switch \initial - attribute \src "libresoc.v:99314.9-99314.17" + attribute \src "libresoc.v:108330.9-108330.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100110 case - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:99332.3-99350.6" - process $proc$libresoc.v:99332$4062 + attribute \src "libresoc.v:108348.3-108366.6" + process $proc$libresoc.v:108348$4208 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:99333.5-99333.29" + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:108349.5-108349.29" switch \initial - attribute \src "libresoc.v:99333.9-99333.17" + attribute \src "libresoc.v:108349.9-108349.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'11000 assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub27_lk[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:99351.3-99369.6" - process $proc$libresoc.v:99351$4063 + attribute \src "libresoc.v:108367.3-108385.6" + process $proc$libresoc.v:108367$4209 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:99352.5-99352.29" + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:108368.5-108368.29" switch \initial - attribute \src "libresoc.v:99352.9-99352.17" + attribute \src "libresoc.v:108368.9-108368.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + end + attribute \src "libresoc.v:108386.3-108404.6" + process $proc$libresoc.v:108386$4210 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:108387.5-108387.29" + switch \initial + attribute \src "libresoc.v:108387.9-108387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:99370.3-99388.6" - process $proc$libresoc.v:99370$4064 + attribute \src "libresoc.v:108405.3-108423.6" + process $proc$libresoc.v:108405$4211 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:99371.5-99371.29" + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:108406.5-108406.29" switch \initial - attribute \src "libresoc.v:99371.9-99371.17" + attribute \src "libresoc.v:108406.9-108406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + end + attribute \src "libresoc.v:108424.3-108442.6" + process $proc$libresoc.v:108424$4212 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:108425.5-108425.29" + switch \initial + attribute \src "libresoc.v:108425.9-108425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub27_form[4:0] 5'00000 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:99389.3-99407.6" - process $proc$libresoc.v:99389$4065 + attribute \src "libresoc.v:108443.3-108461.6" + process $proc$libresoc.v:108443$4213 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:99390.5-99390.29" + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:108444.5-108444.29" switch \initial - attribute \src "libresoc.v:99390.9-99390.17" + attribute \src "libresoc.v:108444.9-108444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + end + attribute \src "libresoc.v:108462.3-108480.6" + process $proc$libresoc.v:108462$4214 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:108463.5-108463.29" + switch \initial + attribute \src "libresoc.v:108463.9-108463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 case - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:99408.3-99426.6" - process $proc$libresoc.v:99408$4066 + attribute \src "libresoc.v:108481.3-108499.6" + process $proc$libresoc.v:108481$4215 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:99409.5-99409.29" + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:108482.5-108482.29" switch \initial - attribute \src "libresoc.v:99409.9-99409.17" + attribute \src "libresoc.v:108482.9-108482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + end + attribute \src "libresoc.v:108500.3-108518.6" + process $proc$libresoc.v:108500$4216 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:108501.5-108501.29" + switch \initial + attribute \src "libresoc.v:108501.9-108501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:99427.3-99445.6" - process $proc$libresoc.v:99427$4067 + attribute \src "libresoc.v:108519.3-108537.6" + process $proc$libresoc.v:108519$4217 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:99428.5-99428.29" + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:108520.5-108520.29" switch \initial - attribute \src "libresoc.v:99428.9-99428.17" + attribute \src "libresoc.v:108520.9-108520.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "libresoc.v:108538.3-108556.6" + process $proc$libresoc.v:108538$4218 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:108539.5-108539.29" + switch \initial + attribute \src "libresoc.v:108539.9-108539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 case - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:99446.3-99464.6" - process $proc$libresoc.v:99446$4068 + attribute \src "libresoc.v:108557.3-108575.6" + process $proc$libresoc.v:108557$4219 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:99447.5-99447.29" + assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:108558.5-108558.29" switch \initial - attribute \src "libresoc.v:99447.9-99447.17" + attribute \src "libresoc.v:108558.9-108558.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] + end + attribute \src "libresoc.v:108576.3-108594.6" + process $proc$libresoc.v:108576$4220 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:108577.5-108577.29" + switch \initial + attribute \src "libresoc.v:108577.9-108577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 case - assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end - attribute \src "libresoc.v:99465.3-99483.6" - process $proc$libresoc.v:99465$4069 + attribute \src "libresoc.v:108595.3-108613.6" + process $proc$libresoc.v:108595$4221 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:99466.5-99466.29" + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:108596.5-108596.29" switch \initial - attribute \src "libresoc.v:99466.9-99466.17" + attribute \src "libresoc.v:108596.9-108596.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "libresoc.v:108614.3-108632.6" + process $proc$libresoc.v:108614$4222 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:108615.5-108615.29" + switch \initial + attribute \src "libresoc.v:108615.9-108615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 case - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 end sync always - update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:99484.3-99502.6" - process $proc$libresoc.v:99484$4070 + attribute \src "libresoc.v:108633.3-108651.6" + process $proc$libresoc.v:108633$4223 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:99485.5-99485.29" + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:108634.5-108634.29" switch \initial - attribute \src "libresoc.v:99485.9-99485.17" + attribute \src "libresoc.v:108634.9-108634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + end + attribute \src "libresoc.v:108652.3-108670.6" + process $proc$libresoc.v:108652$4224 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:108653.5-108653.29" + switch \initial + attribute \src "libresoc.v:108653.9-108653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 case - assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99508.1-100655.10" +attribute \src "libresoc.v:108676.1-110680.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" -module \dec31_dec_sub28 - attribute \src "libresoc.v:99951.3-99987.6" - wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:100099.3-100135.6" - wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:100580.3-100616.6" - wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:100617.3-100653.6" - wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:99914.3-99950.6" - wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:100062.3-100098.6" - wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:100395.3-100431.6" - wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:99766.3-99802.6" - wire width 12 $0\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:100432.3-100468.6" - wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:100469.3-100505.6" - wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:100506.3-100542.6" - wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:100173.3-100209.6" - wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:99988.3-100024.6" - wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:100025.3-100061.6" - wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:100247.3-100283.6" - wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:99803.3-99839.6" - wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:100321.3-100357.6" - wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:100543.3-100579.6" - wire width 2 $0\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:99877.3-99913.6" - wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:100210.3-100246.6" - wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:100358.3-100394.6" - wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:100284.3-100320.6" - wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:100136.3-100172.6" - wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:99840.3-99876.6" - wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:99509.7-99509.20" +module \dec31_dec_sub26 + attribute \src "libresoc.v:110367.3-110418.6" + wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:110419.3-110470.6" + wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:109743.3-109794.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:109951.3-110002.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:109067.3-109118.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:109119.3-109170.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:109691.3-109742.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:109899.3-109950.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:110159.3-110210.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:109015.3-109066.6" + wire width 14 $0\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:110471.3-110522.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:110523.3-110574.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:110575.3-110626.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:109587.3-109638.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:109795.3-109846.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:109847.3-109898.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:110107.3-110158.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:109483.3-109534.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:110263.3-110314.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:110627.3-110678.6" + wire width 3 $0\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:109639.3-109690.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:110055.3-110106.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:110315.3-110366.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:110211.3-110262.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:110003.3-110054.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:109379.3-109430.6" + wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:109431.3-109482.6" + wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:109171.3-109222.6" + wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:109223.3-109274.6" + wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:109275.3-109326.6" + wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:109327.3-109378.6" + wire width 3 $0\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:109535.3-109586.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:108677.7-108677.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99951.3-99987.6" - wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:100099.3-100135.6" - wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:100580.3-100616.6" - wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:100617.3-100653.6" - wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:99914.3-99950.6" - wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:100062.3-100098.6" - wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:100395.3-100431.6" - wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:99766.3-99802.6" - wire width 12 $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:100432.3-100468.6" - wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:100469.3-100505.6" - wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:100506.3-100542.6" - wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:100173.3-100209.6" - wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:99988.3-100024.6" - wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:100025.3-100061.6" - wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:100247.3-100283.6" - wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:99803.3-99839.6" - wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:100321.3-100357.6" - wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:100543.3-100579.6" - wire width 2 $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:99877.3-99913.6" - wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:100210.3-100246.6" - wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:100358.3-100394.6" - wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:100284.3-100320.6" - wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:100136.3-100172.6" - wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:99840.3-99876.6" - wire width 2 $1\dec31_dec_sub28_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub28_br + attribute \src "libresoc.v:110367.3-110418.6" + wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:110419.3-110470.6" + wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:109743.3-109794.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:109951.3-110002.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:109067.3-109118.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:109119.3-109170.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:109691.3-109742.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:109899.3-109950.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:110159.3-110210.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:109015.3-109066.6" + wire width 14 $1\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:110471.3-110522.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:110523.3-110574.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:110575.3-110626.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:109587.3-109638.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:109795.3-109846.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:109847.3-109898.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:110107.3-110158.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:109483.3-109534.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:110263.3-110314.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:110627.3-110678.6" + wire width 3 $1\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:109639.3-109690.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:110055.3-110106.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:110315.3-110366.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:110211.3-110262.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:110003.3-110054.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:109379.3-109430.6" + wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:109431.3-109482.6" + wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:109171.3-109222.6" + wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:109223.3-109274.6" + wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:109275.3-109326.6" + wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:109327.3-109378.6" + wire width 3 $1\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:109535.3-109586.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub26_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub26_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -156683,24 +169460,26 @@ module \dec31_dec_sub28 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub28_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub28_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub28_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -156731,31 +169510,34 @@ module \dec31_dec_sub28 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub26_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub28_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub28_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -156771,14 +169553,14 @@ module \dec31_dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub28_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub28_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -156853,1617 +169635,2831 @@ module \dec31_dec_sub28 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub28_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub28_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub26_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub28_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub28_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub26_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub26_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub26_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub26_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub26_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub26_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub28_upd - attribute \src "libresoc.v:99509.7-99509.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub26_upd + attribute \src "libresoc.v:108677.7-108677.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:100025.3-100061.6" - process $proc$libresoc.v:100025$4079 + attribute \src "libresoc.v:108677.7-108677.20" + process $proc$libresoc.v:108677$4258 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109015.3-109066.6" + process $proc$libresoc.v:109015$4226 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:100026.5-100026.29" + assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:109016.5-109016.29" switch \initial - attribute \src "libresoc.v:100026.9-100026.17" + attribute \src "libresoc.v:109016.9-109016.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 case - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:100062.3-100098.6" - process $proc$libresoc.v:100062$4080 + attribute \src "libresoc.v:109067.3-109118.6" + process $proc$libresoc.v:109067$4227 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:100063.5-100063.29" + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:109068.5-109068.29" switch \initial - attribute \src "libresoc.v:100063.9-100063.17" + attribute \src "libresoc.v:109068.9-109068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:100099.3-100135.6" - process $proc$libresoc.v:100099$4081 + attribute \src "libresoc.v:109119.3-109170.6" + process $proc$libresoc.v:109119$4228 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:100100.5-100100.29" + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:109120.5-109120.29" switch \initial - attribute \src "libresoc.v:100100.9-100100.17" + attribute \src "libresoc.v:109120.9-109120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub28_br[0:0] 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:100136.3-100172.6" - process $proc$libresoc.v:100136$4082 + attribute \src "libresoc.v:109171.3-109222.6" + process $proc$libresoc.v:109171$4229 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:100137.5-100137.29" + assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:109172.5-109172.29" switch \initial - attribute \src "libresoc.v:100137.9-100137.17" + attribute \src "libresoc.v:109172.9-109172.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 case - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] + update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end - attribute \src "libresoc.v:100173.3-100209.6" - process $proc$libresoc.v:100173$4083 + attribute \src "libresoc.v:109223.3-109274.6" + process $proc$libresoc.v:109223$4230 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:100174.5-100174.29" + assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:109224.5-109224.29" switch \initial - attribute \src "libresoc.v:100174.9-100174.17" + attribute \src "libresoc.v:109224.9-109224.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 case - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end - attribute \src "libresoc.v:100210.3-100246.6" - process $proc$libresoc.v:100210$4084 + attribute \src "libresoc.v:109275.3-109326.6" + process $proc$libresoc.v:109275$4231 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:100211.5-100211.29" + assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:109276.5-109276.29" switch \initial - attribute \src "libresoc.v:100211.9-100211.17" + attribute \src "libresoc.v:109276.9-109276.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'010 case - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end - attribute \src "libresoc.v:100247.3-100283.6" - process $proc$libresoc.v:100247$4085 + attribute \src "libresoc.v:109327.3-109378.6" + process $proc$libresoc.v:109327$4232 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:100248.5-100248.29" + assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:109328.5-109328.29" switch \initial - attribute \src "libresoc.v:100248.9-100248.17" + attribute \src "libresoc.v:109328.9-109328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 case - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end - attribute \src "libresoc.v:100284.3-100320.6" - process $proc$libresoc.v:100284$4086 + attribute \src "libresoc.v:109379.3-109430.6" + process $proc$libresoc.v:109379$4233 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:100285.5-100285.29" + assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:109380.5-109380.29" switch \initial - attribute \src "libresoc.v:100285.9-100285.17" + attribute \src "libresoc.v:109380.9-109380.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] + update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end - attribute \src "libresoc.v:100321.3-100357.6" - process $proc$libresoc.v:100321$4087 + attribute \src "libresoc.v:109431.3-109482.6" + process $proc$libresoc.v:109431$4234 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:100322.5-100322.29" + assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:109432.5-109432.29" switch \initial - attribute \src "libresoc.v:100322.9-100322.17" + attribute \src "libresoc.v:109432.9-109432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub28_lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end - attribute \src "libresoc.v:100358.3-100394.6" - process $proc$libresoc.v:100358$4088 + attribute \src "libresoc.v:109483.3-109534.6" + process $proc$libresoc.v:109483$4235 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:100359.5-100359.29" + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:109484.5-109484.29" switch \initial - attribute \src "libresoc.v:100359.9-100359.17" + attribute \src "libresoc.v:109484.9-109484.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:100395.3-100431.6" - process $proc$libresoc.v:100395$4089 + attribute \src "libresoc.v:109535.3-109586.6" + process $proc$libresoc.v:109535$4236 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:100396.5-100396.29" + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:109536.5-109536.29" switch \initial - attribute \src "libresoc.v:100396.9-100396.17" + attribute \src "libresoc.v:109536.9-109536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 case - assign $1\dec31_dec_sub28_form[4:0] 5'00000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 end sync always - update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:100432.3-100468.6" - process $proc$libresoc.v:100432$4090 + attribute \src "libresoc.v:109587.3-109638.6" + process $proc$libresoc.v:109587$4237 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:100433.5-100433.29" + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:109588.5-109588.29" switch \initial - attribute \src "libresoc.v:100433.9-100433.17" + attribute \src "libresoc.v:109588.9-109588.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:100469.3-100505.6" - process $proc$libresoc.v:100469$4091 + attribute \src "libresoc.v:109639.3-109690.6" + process $proc$libresoc.v:109639$4238 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:100470.5-100470.29" + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:109640.5-109640.29" switch \initial - attribute \src "libresoc.v:100470.9-100470.17" + attribute \src "libresoc.v:109640.9-109640.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 case - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:100506.3-100542.6" - process $proc$libresoc.v:100506$4092 + attribute \src "libresoc.v:109691.3-109742.6" + process $proc$libresoc.v:109691$4239 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:100507.5-100507.29" + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:109692.5-109692.29" switch \initial - attribute \src "libresoc.v:100507.9-100507.17" + attribute \src "libresoc.v:109692.9-109692.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:100543.3-100579.6" - process $proc$libresoc.v:100543$4093 + attribute \src "libresoc.v:109743.3-109794.6" + process $proc$libresoc.v:109743$4240 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:100544.5-100544.29" + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:109744.5-109744.29" switch \initial - attribute \src "libresoc.v:100544.9-100544.17" + attribute \src "libresoc.v:109744.9-109744.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100010 case - assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:100580.3-100616.6" - process $proc$libresoc.v:100580$4094 + attribute \src "libresoc.v:109795.3-109846.6" + process $proc$libresoc.v:109795$4241 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:100581.5-100581.29" + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:109796.5-109796.29" switch \initial - attribute \src "libresoc.v:100581.9-100581.17" + attribute \src "libresoc.v:109796.9-109796.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:100617.3-100653.6" - process $proc$libresoc.v:100617$4095 + attribute \src "libresoc.v:109847.3-109898.6" + process $proc$libresoc.v:109847$4242 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:100618.5-100618.29" + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:109848.5-109848.29" switch \initial - attribute \src "libresoc.v:100618.9-100618.17" + attribute \src "libresoc.v:109848.9-109848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:99509.7-99509.20" - process $proc$libresoc.v:99509$4096 + attribute \src "libresoc.v:109899.3-109950.6" + process $proc$libresoc.v:109899$4243 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:109900.5-109900.29" + switch \initial + attribute \src "libresoc.v:109900.9-109900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:99766.3-99802.6" - process $proc$libresoc.v:99766$4072 + attribute \src "libresoc.v:109951.3-110002.6" + process $proc$libresoc.v:109951$4244 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:99767.5-99767.29" + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:109952.5-109952.29" switch \initial - attribute \src "libresoc.v:99767.9-99767.17" + attribute \src "libresoc.v:109952.9-109952.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 case - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 end sync always - update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:99803.3-99839.6" - process $proc$libresoc.v:99803$4073 + attribute \src "libresoc.v:110003.3-110054.6" + process $proc$libresoc.v:110003$4245 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:99804.5-99804.29" + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:110004.5-110004.29" switch \initial - attribute \src "libresoc.v:99804.9-99804.17" + attribute \src "libresoc.v:110004.9-110004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:99840.3-99876.6" - process $proc$libresoc.v:99840$4074 + attribute \src "libresoc.v:110055.3-110106.6" + process $proc$libresoc.v:110055$4246 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:99841.5-99841.29" + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:110056.5-110056.29" switch \initial - attribute \src "libresoc.v:99841.9-99841.17" + attribute \src "libresoc.v:110056.9-110056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:99877.3-99913.6" - process $proc$libresoc.v:99877$4075 + attribute \src "libresoc.v:110107.3-110158.6" + process $proc$libresoc.v:110107$4247 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:99878.5-99878.29" + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:110108.5-110108.29" switch \initial - attribute \src "libresoc.v:99878.9-99878.17" + attribute \src "libresoc.v:110108.9-110108.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:99914.3-99950.6" - process $proc$libresoc.v:99914$4076 + attribute \src "libresoc.v:110159.3-110210.6" + process $proc$libresoc.v:110159$4248 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:99915.5-99915.29" + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:110160.5-110160.29" switch \initial - attribute \src "libresoc.v:99915.9-99915.17" + attribute \src "libresoc.v:110160.9-110160.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 case - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub26_form[4:0] 5'00000 end sync always - update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:99951.3-99987.6" - process $proc$libresoc.v:99951$4077 + attribute \src "libresoc.v:110211.3-110262.6" + process $proc$libresoc.v:110211$4249 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:99952.5-99952.29" + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:110212.5-110212.29" switch \initial - attribute \src "libresoc.v:99952.9-99952.17" + attribute \src "libresoc.v:110212.9-110212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 case - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:99988.3-100024.6" - process $proc$libresoc.v:99988$4078 + attribute \src "libresoc.v:110263.3-110314.6" + process $proc$libresoc.v:110263$4250 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:99989.5-99989.29" + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:110264.5-110264.29" switch \initial - attribute \src "libresoc.v:99989.9-99989.17" + attribute \src "libresoc.v:110264.9-110264.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'11101 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'11100 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'11110 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'01011 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 5'00101 assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 case - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 end sync always - update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:100659.1-101230.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" -attribute \generator "nMigen" -module \dec31_dec_sub4 - attribute \src "libresoc.v:100982.3-100994.6" - wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:101034.3-101046.6" - wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:101203.3-101215.6" - wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:101216.3-101228.6" - wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:100969.3-100981.6" - wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:101021.3-101033.6" - wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:101138.3-101150.6" - wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:100917.3-100929.6" - wire width 12 $0\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:101151.3-101163.6" - wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:101164.3-101176.6" - wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:101177.3-101189.6" - wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:101060.3-101072.6" - wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:100995.3-101007.6" - wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:101008.3-101020.6" - wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:101086.3-101098.6" - wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:100930.3-100942.6" - wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:101112.3-101124.6" - wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:101190.3-101202.6" - wire width 2 $0\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:100956.3-100968.6" - wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:101073.3-101085.6" - wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:101125.3-101137.6" - wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:101099.3-101111.6" - wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:101047.3-101059.6" - wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:100943.3-100955.6" - wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:100660.7-100660.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:100982.3-100994.6" - wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:101034.3-101046.6" - wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:101203.3-101215.6" - wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:101216.3-101228.6" - wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:100969.3-100981.6" - wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:101021.3-101033.6" - wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:101138.3-101150.6" - wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:100917.3-100929.6" - wire width 12 $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:101151.3-101163.6" - wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:101164.3-101176.6" - wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:101177.3-101189.6" - wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:101060.3-101072.6" - wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:100995.3-101007.6" - wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:101008.3-101020.6" - wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:101086.3-101098.6" - wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:100930.3-100942.6" - wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:101112.3-101124.6" - wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:101190.3-101202.6" - wire width 2 $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:100956.3-100968.6" - wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:101073.3-101085.6" - wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:101125.3-101137.6" - wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:101099.3-101111.6" - wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:101047.3-101059.6" - wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:100943.3-100955.6" - wire width 2 $1\dec31_dec_sub4_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub4_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" + attribute \src "libresoc.v:110315.3-110366.6" + process $proc$libresoc.v:110315$4251 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:110316.5-110316.29" + switch \initial + attribute \src "libresoc.v:110316.9-110316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + end + attribute \src "libresoc.v:110367.3-110418.6" + process $proc$libresoc.v:110367$4252 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:110368.5-110368.29" + switch \initial + attribute \src "libresoc.v:110368.9-110368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] + end + attribute \src "libresoc.v:110419.3-110470.6" + process $proc$libresoc.v:110419$4253 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:110420.5-110420.29" + switch \initial + attribute \src "libresoc.v:110420.9-110420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] + end + attribute \src "libresoc.v:110471.3-110522.6" + process $proc$libresoc.v:110471$4254 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:110472.5-110472.29" + switch \initial + attribute \src "libresoc.v:110472.9-110472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:110523.3-110574.6" + process $proc$libresoc.v:110523$4255 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:110524.5-110524.29" + switch \initial + attribute \src "libresoc.v:110524.9-110524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:110575.3-110626.6" + process $proc$libresoc.v:110575$4256 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:110576.5-110576.29" + switch \initial + attribute \src "libresoc.v:110576.9-110576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + end + attribute \src "libresoc.v:110627.3-110678.6" + process $proc$libresoc.v:110627$4257 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:110628.5-110628.29" + switch \initial + attribute \src "libresoc.v:110628.9-110628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub26_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:110684.1-111632.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "libresoc.v:111517.3-111535.6" + wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:111536.3-111554.6" + wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:111289.3-111307.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:111365.3-111383.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:111042.3-111060.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:111061.3-111079.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:111270.3-111288.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:111346.3-111364.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:111441.3-111459.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:111023.3-111041.6" + wire width 14 $0\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:111555.3-111573.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:111574.3-111592.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:111593.3-111611.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:111232.3-111250.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:111308.3-111326.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:111327.3-111345.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:111422.3-111440.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:111194.3-111212.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:111479.3-111497.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:111612.3-111630.6" + wire width 3 $0\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:111251.3-111269.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:111403.3-111421.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:111498.3-111516.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:111460.3-111478.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:111384.3-111402.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:111156.3-111174.6" + wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:111175.3-111193.6" + wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:111080.3-111098.6" + wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:111099.3-111117.6" + wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:111118.3-111136.6" + wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:111137.3-111155.6" + wire width 3 $0\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:111213.3-111231.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:110685.7-110685.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111517.3-111535.6" + wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:111536.3-111554.6" + wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:111289.3-111307.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:111365.3-111383.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:111042.3-111060.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:111061.3-111079.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:111270.3-111288.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:111346.3-111364.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:111441.3-111459.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:111023.3-111041.6" + wire width 14 $1\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:111555.3-111573.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:111574.3-111592.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:111593.3-111611.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:111232.3-111250.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:111308.3-111326.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:111327.3-111345.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:111422.3-111440.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:111194.3-111212.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:111479.3-111497.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:111612.3-111630.6" + wire width 3 $1\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:111251.3-111269.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:111403.3-111421.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:111498.3-111516.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:111460.3-111478.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:111384.3-111402.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:111156.3-111174.6" + wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:111175.3-111193.6" + wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:111080.3-111098.6" + wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:111099.3-111117.6" + wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:111118.3-111136.6" + wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:111137.3-111155.6" + wire width 3 $1\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:111213.3-111231.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub27_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub27_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub4_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub4_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub4_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -158494,31 +172490,34 @@ module \dec31_dec_sub4 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub4_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub27_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub4_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub4_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -158534,14 +172533,14 @@ module \dec31_dec_sub4 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub4_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub4_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -158616,849 +172615,1423 @@ module \dec31_dec_sub4 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub4_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub4_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub27_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub4_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub4_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub27_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub27_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub27_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub27_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub27_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub27_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub4_upd - attribute \src "libresoc.v:100660.7-100660.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub27_upd + attribute \src "libresoc.v:110685.7-110685.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:100660.7-100660.20" - process $proc$libresoc.v:100660$4121 + attribute \src "libresoc.v:110685.7-110685.20" + process $proc$libresoc.v:110685$4291 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:100917.3-100929.6" - process $proc$libresoc.v:100917$4097 + attribute \src "libresoc.v:111023.3-111041.6" + process $proc$libresoc.v:111023$4259 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:100918.5-100918.29" + assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:111024.5-111024.29" switch \initial - attribute \src "libresoc.v:100918.9-100918.17" + attribute \src "libresoc.v:111024.9-111024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 case - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:100930.3-100942.6" - process $proc$libresoc.v:100930$4098 + attribute \src "libresoc.v:111042.3-111060.6" + process $proc$libresoc.v:111042$4260 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:100931.5-100931.29" + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:111043.5-111043.29" switch \initial - attribute \src "libresoc.v:100931.9-100931.17" + attribute \src "libresoc.v:111043.9-111043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:100943.3-100955.6" - process $proc$libresoc.v:100943$4099 + attribute \src "libresoc.v:111061.3-111079.6" + process $proc$libresoc.v:111061$4261 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:100944.5-100944.29" + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:111062.5-111062.29" switch \initial - attribute \src "libresoc.v:100944.9-100944.17" + attribute \src "libresoc.v:111062.9-111062.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:100956.3-100968.6" - process $proc$libresoc.v:100956$4100 + attribute \src "libresoc.v:111080.3-111098.6" + process $proc$libresoc.v:111080$4262 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:100957.5-100957.29" + assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:111081.5-111081.29" switch \initial - attribute \src "libresoc.v:100957.9-100957.17" + attribute \src "libresoc.v:111081.9-111081.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 case - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end - attribute \src "libresoc.v:100969.3-100981.6" - process $proc$libresoc.v:100969$4101 + attribute \src "libresoc.v:111099.3-111117.6" + process $proc$libresoc.v:111099$4263 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:100970.5-100970.29" + assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:111100.5-111100.29" switch \initial - attribute \src "libresoc.v:100970.9-100970.17" + attribute \src "libresoc.v:111100.9-111100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'010 case - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end - attribute \src "libresoc.v:100982.3-100994.6" - process $proc$libresoc.v:100982$4102 + attribute \src "libresoc.v:111118.3-111136.6" + process $proc$libresoc.v:111118$4264 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:100983.5-100983.29" + assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:111119.5-111119.29" switch \initial - attribute \src "libresoc.v:100983.9-100983.17" + attribute \src "libresoc.v:111119.9-111119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'011 case - assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end - attribute \src "libresoc.v:100995.3-101007.6" - process $proc$libresoc.v:100995$4103 + attribute \src "libresoc.v:111137.3-111155.6" + process $proc$libresoc.v:111137$4265 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:100996.5-100996.29" + assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:111138.5-111138.29" switch \initial - attribute \src "libresoc.v:100996.9-100996.17" + attribute \src "libresoc.v:111138.9-111138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 case - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end - attribute \src "libresoc.v:101008.3-101020.6" - process $proc$libresoc.v:101008$4104 + attribute \src "libresoc.v:111156.3-111174.6" + process $proc$libresoc.v:111156$4266 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:101009.5-101009.29" + assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:111157.5-111157.29" switch \initial - attribute \src "libresoc.v:101009.9-101009.17" + attribute \src "libresoc.v:111157.9-111157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end - attribute \src "libresoc.v:101021.3-101033.6" - process $proc$libresoc.v:101021$4105 + attribute \src "libresoc.v:111175.3-111193.6" + process $proc$libresoc.v:111175$4267 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:101022.5-101022.29" + assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:111176.5-111176.29" switch \initial - attribute \src "libresoc.v:101022.9-101022.17" + attribute \src "libresoc.v:111176.9-111176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end - attribute \src "libresoc.v:101034.3-101046.6" - process $proc$libresoc.v:101034$4106 + attribute \src "libresoc.v:111194.3-111212.6" + process $proc$libresoc.v:111194$4268 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:101035.5-101035.29" + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:111195.5-111195.29" switch \initial - attribute \src "libresoc.v:101035.9-101035.17" + attribute \src "libresoc.v:111195.9-111195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub4_br[0:0] 1'0 + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:101047.3-101059.6" - process $proc$libresoc.v:101047$4107 + attribute \src "libresoc.v:111213.3-111231.6" + process $proc$libresoc.v:111213$4269 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:101048.5-101048.29" + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:111214.5-111214.29" switch \initial - attribute \src "libresoc.v:101048.9-101048.17" + attribute \src "libresoc.v:111214.9-111214.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 case - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 end sync always - update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:101060.3-101072.6" - process $proc$libresoc.v:101060$4108 + attribute \src "libresoc.v:111232.3-111250.6" + process $proc$libresoc.v:111232$4270 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:101061.5-101061.29" + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:111233.5-111233.29" switch \initial - attribute \src "libresoc.v:101061.9-101061.17" + attribute \src "libresoc.v:111233.9-111233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:101073.3-101085.6" - process $proc$libresoc.v:101073$4109 + attribute \src "libresoc.v:111251.3-111269.6" + process $proc$libresoc.v:111251$4271 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:101074.5-101074.29" + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:111252.5-111252.29" switch \initial - attribute \src "libresoc.v:101074.9-101074.17" + attribute \src "libresoc.v:111252.9-111252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 case - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:101086.3-101098.6" - process $proc$libresoc.v:101086$4110 + attribute \src "libresoc.v:111270.3-111288.6" + process $proc$libresoc.v:111270$4272 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:101087.5-101087.29" + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:111271.5-111271.29" switch \initial - attribute \src "libresoc.v:101087.9-101087.17" + attribute \src "libresoc.v:111271.9-111271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:101099.3-101111.6" - process $proc$libresoc.v:101099$4111 + attribute \src "libresoc.v:111289.3-111307.6" + process $proc$libresoc.v:111289$4273 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:101100.5-101100.29" + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:111290.5-111290.29" switch \initial - attribute \src "libresoc.v:101100.9-101100.17" + attribute \src "libresoc.v:111290.9-111290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100101 case - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:101112.3-101124.6" - process $proc$libresoc.v:101112$4112 + attribute \src "libresoc.v:111308.3-111326.6" + process $proc$libresoc.v:111308$4274 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:101113.5-101113.29" + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:111309.5-111309.29" switch \initial - attribute \src "libresoc.v:101113.9-101113.17" + attribute \src "libresoc.v:111309.9-111309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub4_lk[0:0] 1'0 + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:101125.3-101137.6" - process $proc$libresoc.v:101125$4113 + attribute \src "libresoc.v:111327.3-111345.6" + process $proc$libresoc.v:111327$4275 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:101126.5-101126.29" + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:111328.5-111328.29" switch \initial - attribute \src "libresoc.v:101126.9-101126.17" + attribute \src "libresoc.v:111328.9-111328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:101138.3-101150.6" - process $proc$libresoc.v:101138$4114 + attribute \src "libresoc.v:111346.3-111364.6" + process $proc$libresoc.v:111346$4276 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:101139.5-101139.29" + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:111347.5-111347.29" switch \initial - attribute \src "libresoc.v:101139.9-101139.17" + attribute \src "libresoc.v:111347.9-111347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub4_form[4:0] 5'00000 + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:101151.3-101163.6" - process $proc$libresoc.v:101151$4115 + attribute \src "libresoc.v:111365.3-111383.6" + process $proc$libresoc.v:111365$4277 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:101152.5-101152.29" + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:111366.5-111366.29" switch \initial - attribute \src "libresoc.v:101152.9-101152.17" + attribute \src "libresoc.v:111366.9-111366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub27_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 case - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub27_br[0:0] 1'0 end sync always - update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:101164.3-101176.6" - process $proc$libresoc.v:101164$4116 + attribute \src "libresoc.v:111384.3-111402.6" + process $proc$libresoc.v:111384$4278 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:101165.5-101165.29" + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:111385.5-111385.29" switch \initial - attribute \src "libresoc.v:101165.9-101165.17" + attribute \src "libresoc.v:111385.9-111385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:101177.3-101189.6" - process $proc$libresoc.v:101177$4117 + attribute \src "libresoc.v:111403.3-111421.6" + process $proc$libresoc.v:111403$4279 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:101178.5-101178.29" + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:111404.5-111404.29" switch \initial - attribute \src "libresoc.v:101178.9-101178.17" + attribute \src "libresoc.v:111404.9-111404.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:101190.3-101202.6" - process $proc$libresoc.v:101190$4118 + attribute \src "libresoc.v:111422.3-111440.6" + process $proc$libresoc.v:111422$4280 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:101191.5-101191.29" + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:111423.5-111423.29" switch \initial - attribute \src "libresoc.v:101191.9-101191.17" + attribute \src "libresoc.v:111423.9-111423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:101203.3-101215.6" - process $proc$libresoc.v:101203$4119 + attribute \src "libresoc.v:111441.3-111459.6" + process $proc$libresoc.v:111441$4281 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:101204.5-101204.29" + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:111442.5-111442.29" switch \initial - attribute \src "libresoc.v:101204.9-101204.17" + attribute \src "libresoc.v:111442.9-111442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 case - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub27_form[4:0] 5'00000 end sync always - update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:101216.3-101228.6" - process $proc$libresoc.v:101216$4120 + attribute \src "libresoc.v:111460.3-111478.6" + process $proc$libresoc.v:111460$4282 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:101217.5-101217.29" + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:111461.5-111461.29" switch \initial - attribute \src "libresoc.v:101217.9-101217.17" + attribute \src "libresoc.v:111461.9-111461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'11011 assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:101234.1-102525.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" -attribute \generator "nMigen" -module \dec31_dec_sub8 - attribute \src "libresoc.v:101707.3-101749.6" - wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:101879.3-101921.6" - wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:102438.3-102480.6" - wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:102481.3-102523.6" - wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:101664.3-101706.6" - wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:101836.3-101878.6" - wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:102223.3-102265.6" - wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:101492.3-101534.6" - wire width 12 $0\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:102266.3-102308.6" - wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:102309.3-102351.6" - wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:102352.3-102394.6" - wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:101965.3-102007.6" - wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:101750.3-101792.6" - wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101793.3-101835.6" - wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:102051.3-102093.6" - wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:101535.3-101577.6" - wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:102137.3-102179.6" - wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:102395.3-102437.6" - wire width 2 $0\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:101621.3-101663.6" - wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:102008.3-102050.6" - wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:102180.3-102222.6" - wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:102094.3-102136.6" - wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:101922.3-101964.6" - wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:101578.3-101620.6" - wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:101235.7-101235.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:101707.3-101749.6" - wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:101879.3-101921.6" - wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:102438.3-102480.6" - wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:102481.3-102523.6" - wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:101664.3-101706.6" - wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:101836.3-101878.6" - wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:102223.3-102265.6" - wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:101492.3-101534.6" - wire width 12 $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:102266.3-102308.6" - wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:102309.3-102351.6" - wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:102352.3-102394.6" - wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:101965.3-102007.6" - wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:101750.3-101792.6" - wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101793.3-101835.6" - wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:102051.3-102093.6" - wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:101535.3-101577.6" - wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:102137.3-102179.6" - wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:102395.3-102437.6" - wire width 2 $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:101621.3-101663.6" - wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:102008.3-102050.6" - wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:102180.3-102222.6" - wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:102094.3-102136.6" - wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:101922.3-101964.6" - wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:101578.3-101620.6" - wire width 2 $1\dec31_dec_sub8_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub8_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub8_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub8_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "libresoc.v:111479.3-111497.6" + process $proc$libresoc.v:111479$4283 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:111480.5-111480.29" + switch \initial + attribute \src "libresoc.v:111480.9-111480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + end + attribute \src "libresoc.v:111498.3-111516.6" + process $proc$libresoc.v:111498$4284 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:111499.5-111499.29" + switch \initial + attribute \src "libresoc.v:111499.9-111499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + end + attribute \src "libresoc.v:111517.3-111535.6" + process $proc$libresoc.v:111517$4285 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:111518.5-111518.29" + switch \initial + attribute \src "libresoc.v:111518.9-111518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] + end + attribute \src "libresoc.v:111536.3-111554.6" + process $proc$libresoc.v:111536$4286 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:111537.5-111537.29" + switch \initial + attribute \src "libresoc.v:111537.9-111537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] + end + attribute \src "libresoc.v:111555.3-111573.6" + process $proc$libresoc.v:111555$4287 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:111556.5-111556.29" + switch \initial + attribute \src "libresoc.v:111556.9-111556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + end + attribute \src "libresoc.v:111574.3-111592.6" + process $proc$libresoc.v:111574$4288 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:111575.5-111575.29" + switch \initial + attribute \src "libresoc.v:111575.9-111575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:111593.3-111611.6" + process $proc$libresoc.v:111593$4289 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:111594.5-111594.29" + switch \initial + attribute \src "libresoc.v:111594.9-111594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + end + attribute \src "libresoc.v:111612.3-111630.6" + process $proc$libresoc.v:111612$4290 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:111613.5-111613.29" + switch \initial + attribute \src "libresoc.v:111613.9-111613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub27_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:111636.1-113160.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "libresoc.v:112937.3-112973.6" + wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:112974.3-113010.6" + wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:112493.3-112529.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:112641.3-112677.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:112012.3-112048.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:112049.3-112085.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:112456.3-112492.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:112604.3-112640.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:112789.3-112825.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:111975.3-112011.6" + wire width 14 $0\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:113011.3-113047.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:113048.3-113084.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:113085.3-113121.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:112382.3-112418.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:112530.3-112566.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:112567.3-112603.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:112752.3-112788.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:112308.3-112344.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:112863.3-112899.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:113122.3-113158.6" + wire width 3 $0\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:112419.3-112455.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:112715.3-112751.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:112900.3-112936.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:112826.3-112862.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:112678.3-112714.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:112234.3-112270.6" + wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:112271.3-112307.6" + wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:112086.3-112122.6" + wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:112123.3-112159.6" + wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:112160.3-112196.6" + wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:112197.3-112233.6" + wire width 3 $0\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:112345.3-112381.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:111637.7-111637.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112937.3-112973.6" + wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:112974.3-113010.6" + wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:112493.3-112529.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:112641.3-112677.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:112012.3-112048.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:112049.3-112085.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:112456.3-112492.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:112604.3-112640.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:112789.3-112825.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:111975.3-112011.6" + wire width 14 $1\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:113011.3-113047.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:113048.3-113084.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:113085.3-113121.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:112382.3-112418.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:112530.3-112566.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:112567.3-112603.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:112752.3-112788.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:112308.3-112344.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:112863.3-112899.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:113122.3-113158.6" + wire width 3 $1\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:112419.3-112455.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:112715.3-112751.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:112900.3-112936.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:112826.3-112862.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:112678.3-112714.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:112234.3-112270.6" + wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:112271.3-112307.6" + wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:112086.3-112122.6" + wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:112123.3-112159.6" + wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:112160.3-112196.6" + wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:112197.3-112233.6" + wire width 3 $1\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:112345.3-112381.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub28_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub28_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub8_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -159489,31 +174062,34 @@ module \dec31_dec_sub8 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub28_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub8_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub8_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -159529,14 +174105,14 @@ module \dec31_dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub8_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub8_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -159611,1783 +174187,2163 @@ module \dec31_dec_sub8 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub8_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub8_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub28_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub8_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub8_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub28_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub28_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub28_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub28_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub28_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub28_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub8_upd - attribute \src "libresoc.v:101235.7-101235.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub28_upd + attribute \src "libresoc.v:111637.7-111637.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:101235.7-101235.20" - process $proc$libresoc.v:101235$4146 + attribute \src "libresoc.v:111637.7-111637.20" + process $proc$libresoc.v:111637$4324 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:101492.3-101534.6" - process $proc$libresoc.v:101492$4122 + attribute \src "libresoc.v:111975.3-112011.6" + process $proc$libresoc.v:111975$4292 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:101493.5-101493.29" + assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:111976.5-111976.29" switch \initial - attribute \src "libresoc.v:101493.9-101493.17" + attribute \src "libresoc.v:111976.9-111976.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 case - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:101535.3-101577.6" - process $proc$libresoc.v:101535$4123 + attribute \src "libresoc.v:112012.3-112048.6" + process $proc$libresoc.v:112012$4293 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:101536.5-101536.29" + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:112013.5-112013.29" switch \initial - attribute \src "libresoc.v:101536.9-101536.17" + attribute \src "libresoc.v:112013.9-112013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:101578.3-101620.6" - process $proc$libresoc.v:101578$4124 + attribute \src "libresoc.v:112049.3-112085.6" + process $proc$libresoc.v:112049$4294 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:101579.5-101579.29" + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:112050.5-112050.29" switch \initial - attribute \src "libresoc.v:101579.9-101579.17" + attribute \src "libresoc.v:112050.9-112050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:101621.3-101663.6" - process $proc$libresoc.v:101621$4125 + attribute \src "libresoc.v:112086.3-112122.6" + process $proc$libresoc.v:112086$4295 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:101622.5-101622.29" + assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:112087.5-112087.29" switch \initial - attribute \src "libresoc.v:101622.9-101622.17" + attribute \src "libresoc.v:112087.9-112087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 case - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end - attribute \src "libresoc.v:101664.3-101706.6" - process $proc$libresoc.v:101664$4126 + attribute \src "libresoc.v:112123.3-112159.6" + process $proc$libresoc.v:112123$4296 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:101665.5-101665.29" + assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:112124.5-112124.29" switch \initial - attribute \src "libresoc.v:101665.9-101665.17" + attribute \src "libresoc.v:112124.9-112124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 case - assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end - attribute \src "libresoc.v:101707.3-101749.6" - process $proc$libresoc.v:101707$4127 + attribute \src "libresoc.v:112160.3-112196.6" + process $proc$libresoc.v:112160$4297 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:101708.5-101708.29" + assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:112161.5-112161.29" switch \initial - attribute \src "libresoc.v:101708.9-101708.17" + attribute \src "libresoc.v:112161.9-112161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end - attribute \src "libresoc.v:101750.3-101792.6" - process $proc$libresoc.v:101750$4128 + attribute \src "libresoc.v:112197.3-112233.6" + process $proc$libresoc.v:112197$4298 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101751.5-101751.29" + assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:112198.5-112198.29" switch \initial - attribute \src "libresoc.v:101751.9-101751.17" + attribute \src "libresoc.v:112198.9-112198.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 case - assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end - attribute \src "libresoc.v:101793.3-101835.6" - process $proc$libresoc.v:101793$4129 + attribute \src "libresoc.v:112234.3-112270.6" + process $proc$libresoc.v:112234$4299 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:101794.5-101794.29" + assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:112235.5-112235.29" switch \initial - attribute \src "libresoc.v:101794.9-101794.17" + attribute \src "libresoc.v:112235.9-112235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end - attribute \src "libresoc.v:101836.3-101878.6" - process $proc$libresoc.v:101836$4130 + attribute \src "libresoc.v:112271.3-112307.6" + process $proc$libresoc.v:112271$4300 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:101837.5-101837.29" + assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:112272.5-112272.29" switch \initial - attribute \src "libresoc.v:101837.9-101837.17" + attribute \src "libresoc.v:112272.9-112272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end - attribute \src "libresoc.v:101879.3-101921.6" - process $proc$libresoc.v:101879$4131 + attribute \src "libresoc.v:112308.3-112344.6" + process $proc$libresoc.v:112308$4301 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:101880.5-101880.29" + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:112309.5-112309.29" switch \initial - attribute \src "libresoc.v:101880.9-101880.17" + attribute \src "libresoc.v:112309.9-112309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub8_br[0:0] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:101922.3-101964.6" - process $proc$libresoc.v:101922$4132 + attribute \src "libresoc.v:112345.3-112381.6" + process $proc$libresoc.v:112345$4302 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:101923.5-101923.29" + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:112346.5-112346.29" switch \initial - attribute \src "libresoc.v:101923.9-101923.17" + attribute \src "libresoc.v:112346.9-112346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 case - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 end sync always - update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:101965.3-102007.6" - process $proc$libresoc.v:101965$4133 + attribute \src "libresoc.v:112382.3-112418.6" + process $proc$libresoc.v:112382$4303 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:101966.5-101966.29" + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:112383.5-112383.29" switch \initial - attribute \src "libresoc.v:101966.9-101966.17" + attribute \src "libresoc.v:112383.9-112383.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 case - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:102008.3-102050.6" - process $proc$libresoc.v:102008$4134 + attribute \src "libresoc.v:112419.3-112455.6" + process $proc$libresoc.v:112419$4304 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:102009.5-102009.29" + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:112420.5-112420.29" switch \initial - attribute \src "libresoc.v:102009.9-102009.17" + attribute \src "libresoc.v:112420.9-112420.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 case - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:102051.3-102093.6" - process $proc$libresoc.v:102051$4135 + attribute \src "libresoc.v:112456.3-112492.6" + process $proc$libresoc.v:112456$4305 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:102052.5-102052.29" + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:112457.5-112457.29" switch \initial - attribute \src "libresoc.v:102052.9-102052.17" + attribute \src "libresoc.v:112457.9-112457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:102094.3-102136.6" - process $proc$libresoc.v:102094$4136 + attribute \src "libresoc.v:112493.3-112529.6" + process $proc$libresoc.v:112493$4306 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:102095.5-102095.29" + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:112494.5-112494.29" switch \initial - attribute \src "libresoc.v:102095.9-102095.17" + attribute \src "libresoc.v:112494.9-112494.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010001 case - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:102137.3-102179.6" - process $proc$libresoc.v:102137$4137 + attribute \src "libresoc.v:112530.3-112566.6" + process $proc$libresoc.v:112530$4307 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:102138.5-102138.29" + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:112531.5-112531.29" switch \initial - attribute \src "libresoc.v:102138.9-102138.17" + attribute \src "libresoc.v:112531.9-112531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 case - assign $1\dec31_dec_sub8_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 end sync always - update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:102180.3-102222.6" - process $proc$libresoc.v:102180$4138 + attribute \src "libresoc.v:112567.3-112603.6" + process $proc$libresoc.v:112567$4308 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:102181.5-102181.29" + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:112568.5-112568.29" switch \initial - attribute \src "libresoc.v:102181.9-102181.17" + attribute \src "libresoc.v:112568.9-112568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:112604.3-112640.6" + process $proc$libresoc.v:112604$4309 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:112605.5-112605.29" + switch \initial + attribute \src "libresoc.v:112605.9-112605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 case - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 end sync always - update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:102223.3-102265.6" - process $proc$libresoc.v:102223$4139 + attribute \src "libresoc.v:112641.3-112677.6" + process $proc$libresoc.v:112641$4310 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:102224.5-102224.29" + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:112642.5-112642.29" switch \initial - attribute \src "libresoc.v:102224.9-102224.17" + attribute \src "libresoc.v:112642.9-112642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_br[0:0] 1'0 + case + assign $1\dec31_dec_sub28_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + end + attribute \src "libresoc.v:112678.3-112714.6" + process $proc$libresoc.v:112678$4311 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:112679.5-112679.29" + switch \initial + attribute \src "libresoc.v:112679.9-112679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub8_form[4:0] 5'00000 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 end sync always - update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:102266.3-102308.6" - process $proc$libresoc.v:102266$4140 + attribute \src "libresoc.v:112715.3-112751.6" + process $proc$libresoc.v:112715$4312 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:102267.5-102267.29" + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:112716.5-112716.29" switch \initial - attribute \src "libresoc.v:102267.9-102267.17" + attribute \src "libresoc.v:112716.9-112716.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + end + attribute \src "libresoc.v:112752.3-112788.6" + process $proc$libresoc.v:112752$4313 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:112753.5-112753.29" + switch \initial + attribute \src "libresoc.v:112753.9-112753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:102309.3-102351.6" - process $proc$libresoc.v:102309$4141 + attribute \src "libresoc.v:112789.3-112825.6" + process $proc$libresoc.v:112789$4314 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:102310.5-102310.29" + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:112790.5-112790.29" switch \initial - attribute \src "libresoc.v:102310.9-102310.17" + attribute \src "libresoc.v:112790.9-112790.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub28_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + end + attribute \src "libresoc.v:112826.3-112862.6" + process $proc$libresoc.v:112826$4315 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:112827.5-112827.29" + switch \initial + attribute \src "libresoc.v:112827.9-112827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:102352.3-102394.6" - process $proc$libresoc.v:102352$4142 + attribute \src "libresoc.v:112863.3-112899.6" + process $proc$libresoc.v:112863$4316 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:102353.5-102353.29" + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:112864.5-112864.29" switch \initial - attribute \src "libresoc.v:102353.9-102353.17" + attribute \src "libresoc.v:112864.9-112864.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + end + attribute \src "libresoc.v:112900.3-112936.6" + process $proc$libresoc.v:112900$4317 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:112901.5-112901.29" + switch \initial + attribute \src "libresoc.v:112901.9-112901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 case - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 end sync always - update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:102395.3-102437.6" - process $proc$libresoc.v:102395$4143 + attribute \src "libresoc.v:112937.3-112973.6" + process $proc$libresoc.v:112937$4318 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:102396.5-102396.29" + assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:112938.5-112938.29" switch \initial - attribute \src "libresoc.v:102396.9-102396.17" + attribute \src "libresoc.v:112938.9-112938.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] + end + attribute \src "libresoc.v:112974.3-113010.6" + process $proc$libresoc.v:112974$4319 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:112975.5-112975.29" + switch \initial + attribute \src "libresoc.v:112975.9-112975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 case - assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'00 end sync always - update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end - attribute \src "libresoc.v:102438.3-102480.6" - process $proc$libresoc.v:102438$4144 + attribute \src "libresoc.v:113011.3-113047.6" + process $proc$libresoc.v:113011$4320 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:102439.5-102439.29" + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:113012.5-113012.29" switch \initial - attribute \src "libresoc.v:102439.9-102439.17" + attribute \src "libresoc.v:113012.9-113012.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:113048.3-113084.6" + process $proc$libresoc.v:113048$4321 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:113049.5-113049.29" + switch \initial + attribute \src "libresoc.v:113049.9-113049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 case - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 end sync always - update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:102481.3-102523.6" - process $proc$libresoc.v:102481$4145 + attribute \src "libresoc.v:113085.3-113121.6" + process $proc$libresoc.v:113085$4322 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:102482.5-102482.29" + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:113086.5-113086.29" switch \initial - attribute \src "libresoc.v:102482.9-102482.17" + attribute \src "libresoc.v:113086.9-113086.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 5'01100 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 5'01001 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + end + attribute \src "libresoc.v:113122.3-113158.6" + process $proc$libresoc.v:113122$4323 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:113123.5-113123.29" + switch \initial + attribute \src "libresoc.v:113123.9-113123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 5'01111 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'01000 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'01110 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 5'01101 assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 case - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:102529.1-104108.10" +attribute \src "libresoc.v:113164.1-113920.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" -module \dec31_dec_sub9 - attribute \src "libresoc.v:103062.3-103116.6" - wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:103282.3-103336.6" - wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:103997.3-104051.6" - wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:104052.3-104106.6" - wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:103007.3-103061.6" - wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:103227.3-103281.6" - wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:103722.3-103776.6" - wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:102787.3-102841.6" - wire width 12 $0\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:103777.3-103831.6" - wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:103832.3-103886.6" - wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:103887.3-103941.6" - wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:103392.3-103446.6" - wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:103117.3-103171.6" - wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:103172.3-103226.6" - wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:103502.3-103556.6" - wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:102842.3-102896.6" - wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:103612.3-103666.6" - wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:103942.3-103996.6" - wire width 2 $0\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:102952.3-103006.6" - wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:103447.3-103501.6" - wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:103667.3-103721.6" - wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:103557.3-103611.6" - wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:103337.3-103391.6" - wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:102897.3-102951.6" - wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:102530.7-102530.20" +module \dec31_dec_sub4 + attribute \src "libresoc.v:113841.3-113853.6" + wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:113854.3-113866.6" + wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:113685.3-113697.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:113737.3-113749.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:113516.3-113528.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:113529.3-113541.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:113672.3-113684.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:113724.3-113736.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:113789.3-113801.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:113503.3-113515.6" + wire width 14 $0\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:113867.3-113879.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:113880.3-113892.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:113893.3-113905.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:113646.3-113658.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:113698.3-113710.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:113711.3-113723.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:113776.3-113788.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:113620.3-113632.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:113815.3-113827.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:113906.3-113918.6" + wire width 3 $0\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:113659.3-113671.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:113763.3-113775.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:113828.3-113840.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:113802.3-113814.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:113750.3-113762.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:113594.3-113606.6" + wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:113607.3-113619.6" + wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:113542.3-113554.6" + wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:113555.3-113567.6" + wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:113568.3-113580.6" + wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:113581.3-113593.6" + wire width 3 $0\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:113633.3-113645.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:113165.7-113165.20" wire $0\initial[0:0] - attribute \src "libresoc.v:103062.3-103116.6" - wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:103282.3-103336.6" - wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:103997.3-104051.6" - wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:104052.3-104106.6" - wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:103007.3-103061.6" - wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:103227.3-103281.6" - wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:103722.3-103776.6" - wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:102787.3-102841.6" - wire width 12 $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:103777.3-103831.6" - wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:103832.3-103886.6" - wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:103887.3-103941.6" - wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:103392.3-103446.6" - wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:103117.3-103171.6" - wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:103172.3-103226.6" - wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:103502.3-103556.6" - wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:102842.3-102896.6" - wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:103612.3-103666.6" - wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:103942.3-103996.6" - wire width 2 $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:102952.3-103006.6" - wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:103447.3-103501.6" - wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:103667.3-103721.6" - wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:103557.3-103611.6" - wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:103337.3-103391.6" - wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:102897.3-102951.6" - wire width 2 $1\dec31_dec_sub9_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub9_br + attribute \src "libresoc.v:113841.3-113853.6" + wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:113854.3-113866.6" + wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:113685.3-113697.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:113737.3-113749.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:113516.3-113528.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:113529.3-113541.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:113672.3-113684.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:113724.3-113736.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:113789.3-113801.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:113503.3-113515.6" + wire width 14 $1\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:113867.3-113879.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:113880.3-113892.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:113893.3-113905.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:113646.3-113658.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:113698.3-113710.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:113711.3-113723.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:113776.3-113788.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:113620.3-113632.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:113815.3-113827.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:113906.3-113918.6" + wire width 3 $1\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:113659.3-113671.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:113763.3-113775.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:113828.3-113840.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:113802.3-113814.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:113750.3-113762.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:113594.3-113606.6" + wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:113607.3-113619.6" + wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:113542.3-113554.6" + wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:113555.3-113567.6" + wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:113568.3-113580.6" + wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:113581.3-113593.6" + wire width 3 $1\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:113633.3-113645.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub4_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub4_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -161396,24 +176352,26 @@ module \dec31_dec_sub9 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub9_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub9_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub9_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -161444,31 +176402,34 @@ module \dec31_dec_sub9 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub9_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -161484,14 +176445,14 @@ module \dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub9_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub9_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -161566,3258 +176527,3735 @@ module \dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub9_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub9_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub4_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub9_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub9_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub4_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub4_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub4_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub4_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub4_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub4_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub9_upd - attribute \src "libresoc.v:102530.7-102530.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub4_upd + attribute \src "libresoc.v:113165.7-113165.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:102530.7-102530.20" - process $proc$libresoc.v:102530$4171 + attribute \src "libresoc.v:113165.7-113165.20" + process $proc$libresoc.v:113165$4357 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:102787.3-102841.6" - process $proc$libresoc.v:102787$4147 + attribute \src "libresoc.v:113503.3-113515.6" + process $proc$libresoc.v:113503$4325 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:102788.5-102788.29" + assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:113504.5-113504.29" switch \initial - attribute \src "libresoc.v:102788.9-102788.17" + attribute \src "libresoc.v:113504.9-113504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000010000000 + case + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] + end + attribute \src "libresoc.v:113516.3-113528.6" + process $proc$libresoc.v:113516$4326 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:113517.5-113517.29" + switch \initial + attribute \src "libresoc.v:113517.9-113517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:102842.3-102896.6" - process $proc$libresoc.v:102842$4148 + attribute \src "libresoc.v:113529.3-113541.6" + process $proc$libresoc.v:113529$4327 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:102843.5-102843.29" + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:113530.5-113530.29" switch \initial - attribute \src "libresoc.v:102843.9-102843.17" + attribute \src "libresoc.v:113530.9-113530.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + attribute \src "libresoc.v:113542.3-113554.6" + process $proc$libresoc.v:113542$4328 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:113543.5-113543.29" + switch \initial + attribute \src "libresoc.v:113543.9-113543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] + end + attribute \src "libresoc.v:113555.3-113567.6" + process $proc$libresoc.v:113555$4329 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:113556.5-113556.29" + switch \initial + attribute \src "libresoc.v:113556.9-113556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] + end + attribute \src "libresoc.v:113568.3-113580.6" + process $proc$libresoc.v:113568$4330 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:113569.5-113569.29" + switch \initial + attribute \src "libresoc.v:113569.9-113569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] + end + attribute \src "libresoc.v:113581.3-113593.6" + process $proc$libresoc.v:113581$4331 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:113582.5-113582.29" + switch \initial + attribute \src "libresoc.v:113582.9-113582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] + end + attribute \src "libresoc.v:113594.3-113606.6" + process $proc$libresoc.v:113594$4332 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:113595.5-113595.29" + switch \initial + attribute \src "libresoc.v:113595.9-113595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] + end + attribute \src "libresoc.v:113607.3-113619.6" + process $proc$libresoc.v:113607$4333 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:113608.5-113608.29" + switch \initial + attribute \src "libresoc.v:113608.9-113608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] + end + attribute \src "libresoc.v:113620.3-113632.6" + process $proc$libresoc.v:113620$4334 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:113621.5-113621.29" + switch \initial + attribute \src "libresoc.v:113621.9-113621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:102897.3-102951.6" - process $proc$libresoc.v:102897$4149 + attribute \src "libresoc.v:113633.3-113645.6" + process $proc$libresoc.v:113633$4335 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:102898.5-102898.29" + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:113634.5-113634.29" switch \initial - attribute \src "libresoc.v:102898.9-102898.17" + attribute \src "libresoc.v:113634.9-113634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + end + attribute \src "libresoc.v:113646.3-113658.6" + process $proc$libresoc.v:113646$4336 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:113647.5-113647.29" + switch \initial + attribute \src "libresoc.v:113647.9-113647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + end + attribute \src "libresoc.v:113659.3-113671.6" + process $proc$libresoc.v:113659$4337 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:113660.5-113660.29" + switch \initial + attribute \src "libresoc.v:113660.9-113660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + end + attribute \src "libresoc.v:113672.3-113684.6" + process $proc$libresoc.v:113672$4338 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:113673.5-113673.29" + switch \initial + attribute \src "libresoc.v:113673.9-113673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 case - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:102952.3-103006.6" - process $proc$libresoc.v:102952$4150 + attribute \src "libresoc.v:113685.3-113697.6" + process $proc$libresoc.v:113685$4339 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:102953.5-102953.29" + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:113686.5-113686.29" switch \initial - attribute \src "libresoc.v:102953.9-102953.17" + attribute \src "libresoc.v:113686.9-113686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001011 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001111 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + end + attribute \src "libresoc.v:113698.3-113710.6" + process $proc$libresoc.v:113698$4340 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:113699.5-113699.29" + switch \initial + attribute \src "libresoc.v:113699.9-113699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + end + attribute \src "libresoc.v:113711.3-113723.6" + process $proc$libresoc.v:113711$4341 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:113712.5-113712.29" + switch \initial + attribute \src "libresoc.v:113712.9-113712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + end + attribute \src "libresoc.v:113724.3-113736.6" + process $proc$libresoc.v:113724$4342 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:113725.5-113725.29" + switch \initial + attribute \src "libresoc.v:113725.9-113725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + end + attribute \src "libresoc.v:113737.3-113749.6" + process $proc$libresoc.v:113737$4343 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:113738.5-113738.29" + switch \initial + attribute \src "libresoc.v:113738.9-113738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub4_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + end + attribute \src "libresoc.v:113750.3-113762.6" + process $proc$libresoc.v:113750$4344 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:113751.5-113751.29" + switch \initial + attribute \src "libresoc.v:113751.9-113751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + end + attribute \src "libresoc.v:113763.3-113775.6" + process $proc$libresoc.v:113763$4345 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:113764.5-113764.29" + switch \initial + attribute \src "libresoc.v:113764.9-113764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + end + attribute \src "libresoc.v:113776.3-113788.6" + process $proc$libresoc.v:113776$4346 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:113777.5-113777.29" + switch \initial + attribute \src "libresoc.v:113777.9-113777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 case - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:103007.3-103061.6" - process $proc$libresoc.v:103007$4151 + attribute \src "libresoc.v:113789.3-113801.6" + process $proc$libresoc.v:113789$4347 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:103008.5-103008.29" + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:113790.5-113790.29" switch \initial - attribute \src "libresoc.v:103008.9-103008.17" + attribute \src "libresoc.v:113790.9-113790.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + end + attribute \src "libresoc.v:113802.3-113814.6" + process $proc$libresoc.v:113802$4348 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:113803.5-113803.29" + switch \initial + attribute \src "libresoc.v:113803.9-113803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + end + attribute \src "libresoc.v:113815.3-113827.6" + process $proc$libresoc.v:113815$4349 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:113816.5-113816.29" + switch \initial + attribute \src "libresoc.v:113816.9-113816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + end + attribute \src "libresoc.v:113828.3-113840.6" + process $proc$libresoc.v:113828$4350 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:113829.5-113829.29" + switch \initial + attribute \src "libresoc.v:113829.9-113829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + end + attribute \src "libresoc.v:113841.3-113853.6" + process $proc$libresoc.v:113841$4351 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:113842.5-113842.29" + switch \initial + attribute \src "libresoc.v:113842.9-113842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 + case + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] + end + attribute \src "libresoc.v:113854.3-113866.6" + process $proc$libresoc.v:113854$4352 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:113855.5-113855.29" + switch \initial + attribute \src "libresoc.v:113855.9-113855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 + case + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] + end + attribute \src "libresoc.v:113867.3-113879.6" + process $proc$libresoc.v:113867$4353 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:113868.5-113868.29" + switch \initial + attribute \src "libresoc.v:113868.9-113868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + end + attribute \src "libresoc.v:113880.3-113892.6" + process $proc$libresoc.v:113880$4354 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:113881.5-113881.29" + switch \initial + attribute \src "libresoc.v:113881.9-113881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 case - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 end sync always - update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:103062.3-103116.6" - process $proc$libresoc.v:103062$4152 + attribute \src "libresoc.v:113893.3-113905.6" + process $proc$libresoc.v:113893$4355 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:103063.5-103063.29" + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:113894.5-113894.29" switch \initial - attribute \src "libresoc.v:103063.9-103063.17" + attribute \src "libresoc.v:113894.9-113894.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + end + attribute \src "libresoc.v:113906.3-113918.6" + process $proc$libresoc.v:113906$4356 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:113907.5-113907.29" + switch \initial + attribute \src "libresoc.v:113907.9-113907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:113924.1-115640.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "libresoc.v:115381.3-115423.6" + wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:115424.3-115466.6" + wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:114865.3-114907.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:115037.3-115079.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:114306.3-114348.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:114349.3-114391.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:114822.3-114864.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:114994.3-115036.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:115209.3-115251.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:114263.3-114305.6" + wire width 14 $0\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:115467.3-115509.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:115510.3-115552.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:115553.3-115595.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:114736.3-114778.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:114908.3-114950.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:114951.3-114993.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:115166.3-115208.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:114650.3-114692.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:115295.3-115337.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:115596.3-115638.6" + wire width 3 $0\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:114779.3-114821.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:115123.3-115165.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:115338.3-115380.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:115252.3-115294.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:115080.3-115122.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:114564.3-114606.6" + wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:114607.3-114649.6" + wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:114392.3-114434.6" + wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:114435.3-114477.6" + wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:114478.3-114520.6" + wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:114521.3-114563.6" + wire width 3 $0\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:114693.3-114735.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:113925.7-113925.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115381.3-115423.6" + wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:115424.3-115466.6" + wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:114865.3-114907.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:115037.3-115079.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:114306.3-114348.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:114349.3-114391.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:114822.3-114864.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:114994.3-115036.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:115209.3-115251.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:114263.3-114305.6" + wire width 14 $1\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:115467.3-115509.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:115510.3-115552.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:115553.3-115595.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:114736.3-114778.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:114908.3-114950.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:114951.3-114993.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:115166.3-115208.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:114650.3-114692.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:115295.3-115337.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:115596.3-115638.6" + wire width 3 $1\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:114779.3-114821.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:115123.3-115165.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:115338.3-115380.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:115252.3-115294.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:115080.3-115122.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:114564.3-114606.6" + wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:114607.3-114649.6" + wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:114392.3-114434.6" + wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:114435.3-114477.6" + wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:114478.3-114520.6" + wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:114521.3-114563.6" + wire width 3 $1\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:114693.3-114735.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub8_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub8_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub8_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub8_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub8_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub8_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub8_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub8_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub8_upd + attribute \src "libresoc.v:113925.7-113925.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:113925.7-113925.20" + process $proc$libresoc.v:113925$4390 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:114263.3-114305.6" + process $proc$libresoc.v:114263$4358 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:114264.5-114264.29" + switch \initial + attribute \src "libresoc.v:114264.9-114264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 case - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:103117.3-103171.6" - process $proc$libresoc.v:103117$4153 + attribute \src "libresoc.v:114306.3-114348.6" + process $proc$libresoc.v:114306$4359 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:103118.5-103118.29" + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:114307.5-114307.29" switch \initial - attribute \src "libresoc.v:103118.9-103118.17" + attribute \src "libresoc.v:114307.9-114307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:103172.3-103226.6" - process $proc$libresoc.v:103172$4154 + attribute \src "libresoc.v:114349.3-114391.6" + process $proc$libresoc.v:114349$4360 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:103173.5-103173.29" + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:114350.5-114350.29" switch \initial - attribute \src "libresoc.v:103173.9-103173.17" + attribute \src "libresoc.v:114350.9-114350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:103227.3-103281.6" - process $proc$libresoc.v:103227$4155 + attribute \src "libresoc.v:114392.3-114434.6" + process $proc$libresoc.v:114392$4361 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:103228.5-103228.29" + assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:114393.5-114393.29" switch \initial - attribute \src "libresoc.v:103228.9-103228.17" + attribute \src "libresoc.v:114393.9-114393.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 case - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'000 end sync always - update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] + update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end - attribute \src "libresoc.v:103282.3-103336.6" - process $proc$libresoc.v:103282$4156 + attribute \src "libresoc.v:114435.3-114477.6" + process $proc$libresoc.v:114435$4362 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:103283.5-103283.29" + assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:114436.5-114436.29" switch \initial - attribute \src "libresoc.v:103283.9-103283.17" + attribute \src "libresoc.v:114436.9-114436.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 case - assign $1\dec31_dec_sub9_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 end sync always - update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] + update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end - attribute \src "libresoc.v:103337.3-103391.6" - process $proc$libresoc.v:103337$4157 + attribute \src "libresoc.v:114478.3-114520.6" + process $proc$libresoc.v:114478$4363 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:103338.5-103338.29" + assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:114479.5-114479.29" switch \initial - attribute \src "libresoc.v:103338.9-103338.17" + attribute \src "libresoc.v:114479.9-114479.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 case - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 end sync always - update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] + update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end - attribute \src "libresoc.v:103392.3-103446.6" - process $proc$libresoc.v:103392$4158 + attribute \src "libresoc.v:114521.3-114563.6" + process $proc$libresoc.v:114521$4364 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:103393.5-103393.29" + assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:114522.5-114522.29" switch \initial - attribute \src "libresoc.v:103393.9-103393.17" + attribute \src "libresoc.v:114522.9-114522.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 case - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub8_sv_out[2:0] 3'000 end sync always - update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end - attribute \src "libresoc.v:103447.3-103501.6" - process $proc$libresoc.v:103447$4159 + attribute \src "libresoc.v:114564.3-114606.6" + process $proc$libresoc.v:114564$4365 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:103448.5-103448.29" + assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:114565.5-114565.29" switch \initial - attribute \src "libresoc.v:103448.9-103448.17" + attribute \src "libresoc.v:114565.9-114565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 end sync always - update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] + update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end - attribute \src "libresoc.v:103502.3-103556.6" - process $proc$libresoc.v:103502$4160 + attribute \src "libresoc.v:114607.3-114649.6" + process $proc$libresoc.v:114607$4366 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:103503.5-103503.29" + assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:114608.5-114608.29" switch \initial - attribute \src "libresoc.v:103503.9-103503.17" + attribute \src "libresoc.v:114608.9-114608.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 case - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 end sync always - update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end - attribute \src "libresoc.v:103557.3-103611.6" - process $proc$libresoc.v:103557$4161 + attribute \src "libresoc.v:114650.3-114692.6" + process $proc$libresoc.v:114650$4367 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:103558.5-103558.29" + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:114651.5-114651.29" switch \initial - attribute \src "libresoc.v:103558.9-103558.17" + attribute \src "libresoc.v:114651.9-114651.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 case - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 end sync always - update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:103612.3-103666.6" - process $proc$libresoc.v:103612$4162 + attribute \src "libresoc.v:114693.3-114735.6" + process $proc$libresoc.v:114693$4368 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:103613.5-103613.29" + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:114694.5-114694.29" switch \initial - attribute \src "libresoc.v:103613.9-103613.17" + attribute \src "libresoc.v:114694.9-114694.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 case - assign $1\dec31_dec_sub9_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 end sync always - update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:103667.3-103721.6" - process $proc$libresoc.v:103667$4163 + attribute \src "libresoc.v:114736.3-114778.6" + process $proc$libresoc.v:114736$4369 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:103668.5-103668.29" + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:114737.5-114737.29" switch \initial - attribute \src "libresoc.v:103668.9-103668.17" + attribute \src "libresoc.v:114737.9-114737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 case - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:103722.3-103776.6" - process $proc$libresoc.v:103722$4164 + attribute \src "libresoc.v:114779.3-114821.6" + process $proc$libresoc.v:114779$4370 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:103723.5-103723.29" + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:114780.5-114780.29" switch \initial - attribute \src "libresoc.v:103723.9-103723.17" + attribute \src "libresoc.v:114780.9-114780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 case - assign $1\dec31_dec_sub9_form[4:0] 5'00000 + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 end sync always - update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:103777.3-103831.6" - process $proc$libresoc.v:103777$4165 + attribute \src "libresoc.v:114822.3-114864.6" + process $proc$libresoc.v:114822$4371 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:103778.5-103778.29" + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:114823.5-114823.29" switch \initial - attribute \src "libresoc.v:103778.9-103778.17" + attribute \src "libresoc.v:114823.9-114823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 case - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 end sync always - update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:103832.3-103886.6" - process $proc$libresoc.v:103832$4166 + attribute \src "libresoc.v:114865.3-114907.6" + process $proc$libresoc.v:114865$4372 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:103833.5-103833.29" + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:114866.5-114866.29" switch \initial - attribute \src "libresoc.v:103833.9-103833.17" + attribute \src "libresoc.v:114866.9-114866.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000011 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001001 case - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 end sync always - update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:103887.3-103941.6" - process $proc$libresoc.v:103887$4167 + attribute \src "libresoc.v:114908.3-114950.6" + process $proc$libresoc.v:114908$4373 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:103888.5-103888.29" + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:114909.5-114909.29" switch \initial - attribute \src "libresoc.v:103888.9-103888.17" + attribute \src "libresoc.v:114909.9-114909.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:114951.3-114993.6" + process $proc$libresoc.v:114951$4374 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:114952.5-114952.29" + switch \initial + attribute \src "libresoc.v:114952.9-114952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 case - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 end sync always - update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:103942.3-103996.6" - process $proc$libresoc.v:103942$4168 + attribute \src "libresoc.v:114994.3-115036.6" + process $proc$libresoc.v:114994$4375 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:103943.5-103943.29" + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:114995.5-114995.29" switch \initial - attribute \src "libresoc.v:103943.9-103943.17" + attribute \src "libresoc.v:114995.9-114995.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:115037.3-115079.6" + process $proc$libresoc.v:115037$4376 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:115038.5-115038.29" + switch \initial + attribute \src "libresoc.v:115038.9-115038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 case - assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_br[0:0] 1'0 end sync always - update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:103997.3-104051.6" - process $proc$libresoc.v:103997$4169 + attribute \src "libresoc.v:115080.3-115122.6" + process $proc$libresoc.v:115080$4377 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:103998.5-103998.29" + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:115081.5-115081.29" switch \initial - attribute \src "libresoc.v:103998.9-103998.17" + attribute \src "libresoc.v:115081.9-115081.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + end + attribute \src "libresoc.v:115123.3-115165.6" + process $proc$libresoc.v:115123$4378 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:115124.5-115124.29" + switch \initial + attribute \src "libresoc.v:115124.9-115124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 case - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 end sync always - update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:104052.3-104106.6" - process $proc$libresoc.v:104052$4170 + attribute \src "libresoc.v:115166.3-115208.6" + process $proc$libresoc.v:115166$4379 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:104053.5-104053.29" + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:115167.5-115167.29" switch \initial - attribute \src "libresoc.v:104053.9-104053.17" + attribute \src "libresoc.v:115167.9-115167.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 5'10011 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 5'00001 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 5'10001 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 5'00100 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 5'10100 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 5'00110 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 5'10110 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:115209.3-115251.6" + process $proc$libresoc.v:115209$4380 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:115210.5-115210.29" + switch \initial + attribute \src "libresoc.v:115210.9-115210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 5'00011 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 case - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub8_form[4:0] 5'00000 end sync always - update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:104112.1-104755.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" -attribute \generator "nMigen" -module \dec58 - attribute \src "libresoc.v:104450.3-104465.6" - wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:104514.3-104529.6" - wire $0\dec58_br[0:0] - attribute \src "libresoc.v:104722.3-104737.6" - wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:104738.3-104753.6" - wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:104434.3-104449.6" - wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:104498.3-104513.6" - wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:104642.3-104657.6" - wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:104370.3-104385.6" - wire width 12 $0\dec58_function_unit[11:0] - attribute \src "libresoc.v:104658.3-104673.6" - wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:104674.3-104689.6" - wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:104690.3-104705.6" - wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:104546.3-104561.6" - wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:104466.3-104481.6" - wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:104482.3-104497.6" - wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:104578.3-104593.6" - wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:104386.3-104401.6" - wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:104610.3-104625.6" - wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:104706.3-104721.6" - wire width 2 $0\dec58_out_sel[1:0] - attribute \src "libresoc.v:104418.3-104433.6" - wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:104562.3-104577.6" - wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:104626.3-104641.6" - wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:104594.3-104609.6" - wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:104530.3-104545.6" - wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:104402.3-104417.6" - wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:104113.7-104113.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:104450.3-104465.6" - wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:104514.3-104529.6" - wire $1\dec58_br[0:0] - attribute \src "libresoc.v:104722.3-104737.6" - wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:104738.3-104753.6" - wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:104434.3-104449.6" - wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:104498.3-104513.6" - wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:104642.3-104657.6" - wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:104370.3-104385.6" - wire width 12 $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:104658.3-104673.6" - wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:104674.3-104689.6" - wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:104690.3-104705.6" - wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:104546.3-104561.6" - wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:104466.3-104481.6" - wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:104482.3-104497.6" - wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:104578.3-104593.6" - wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:104386.3-104401.6" - wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:104610.3-104625.6" - wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:104706.3-104721.6" - wire width 2 $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:104418.3-104433.6" - wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:104562.3-104577.6" - wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:104626.3-104641.6" - wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:104594.3-104609.6" - wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:104530.3-104545.6" - wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:104402.3-104417.6" - wire width 2 $1\dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec58_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec58_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec58_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec58_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec58_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec58_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec58_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec58_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec58_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec58_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec58_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec58_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec58_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec58_upd - attribute \src "libresoc.v:104113.7-104113.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 2 \opcode_switch - attribute \src "libresoc.v:104113.7-104113.20" - process $proc$libresoc.v:104113$4196 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:104370.3-104385.6" - process $proc$libresoc.v:104370$4172 + attribute \src "libresoc.v:115252.3-115294.6" + process $proc$libresoc.v:115252$4381 assign { } { } assign { } { } - assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:104371.5-104371.29" + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:115253.5-115253.29" switch \initial - attribute \src "libresoc.v:104371.9-104371.17" + attribute \src "libresoc.v:115253.9-115253.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - case - assign $1\dec58_function_unit[11:0] 12'000000000000 - end - sync always - update \dec58_function_unit $0\dec58_function_unit[11:0] - end - attribute \src "libresoc.v:104386.3-104401.6" - process $proc$libresoc.v:104386$4173 - assign { } { } - assign { } { } - assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:104387.5-104387.29" - switch \initial - attribute \src "libresoc.v:104387.9-104387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10001 assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00000 assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10000 assign { } { } - assign $1\dec58_ldst_len[3:0] 4'0100 - case - assign $1\dec58_ldst_len[3:0] 4'0000 - end - sync always - update \dec58_ldst_len $0\dec58_ldst_len[3:0] - end - attribute \src "libresoc.v:104402.3-104417.6" - process $proc$libresoc.v:104402$4174 - assign { } { } - assign { } { } - assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:104403.5-104403.29" - switch \initial - attribute \src "libresoc.v:104403.9-104403.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00100 assign { } { } - assign $1\dec58_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10100 assign { } { } - assign $1\dec58_upd[1:0] 2'01 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00111 assign { } { } - assign $1\dec58_upd[1:0] 2'00 - case - assign $1\dec58_upd[1:0] 2'00 - end - sync always - update \dec58_upd $0\dec58_upd[1:0] - end - attribute \src "libresoc.v:104418.3-104433.6" - process $proc$libresoc.v:104418$4175 - assign { } { } - assign { } { } - assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:104419.5-104419.29" - switch \initial - attribute \src "libresoc.v:104419.9-104419.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10111 assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00110 assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10110 assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 case - assign $1\dec58_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 end sync always - update \dec58_rc_sel $0\dec58_rc_sel[1:0] + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:104434.3-104449.6" - process $proc$libresoc.v:104434$4176 + attribute \src "libresoc.v:115295.3-115337.6" + process $proc$libresoc.v:115295$4382 assign { } { } assign { } { } - assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:104435.5-104435.29" + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:115296.5-115296.29" switch \initial - attribute \src "libresoc.v:104435.9-104435.17" + attribute \src "libresoc.v:115296.9-115296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - case - assign $1\dec58_cry_in[1:0] 2'00 - end - sync always - update \dec58_cry_in $0\dec58_cry_in[1:0] - end - attribute \src "libresoc.v:104450.3-104465.6" - process $proc$libresoc.v:104450$4177 - assign { } { } - assign { } { } - assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:104451.5-104451.29" - switch \initial - attribute \src "libresoc.v:104451.9-104451.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10001 assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010010 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00000 assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010101 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10000 assign { } { } - assign $1\dec58_asmcode[7:0] 8'01100010 - case - assign $1\dec58_asmcode[7:0] 8'00000000 - end - sync always - update \dec58_asmcode $0\dec58_asmcode[7:0] - end - attribute \src "libresoc.v:104466.3-104481.6" - process $proc$libresoc.v:104466$4178 - assign { } { } - assign { } { } - assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:104467.5-104467.29" - switch \initial - attribute \src "libresoc.v:104467.9-104467.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00100 assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10100 assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00111 assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - case - assign $1\dec58_inv_a[0:0] 1'0 - end - sync always - update \dec58_inv_a $0\dec58_inv_a[0:0] - end - attribute \src "libresoc.v:104482.3-104497.6" - process $proc$libresoc.v:104482$4179 - assign { } { } - assign { } { } - assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:104483.5-104483.29" - switch \initial - attribute \src "libresoc.v:104483.9-104483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10111 assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00110 assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10110 assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 case - assign $1\dec58_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub8_lk[0:0] 1'0 end sync always - update \dec58_inv_out $0\dec58_inv_out[0:0] + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:104498.3-104513.6" - process $proc$libresoc.v:104498$4180 + attribute \src "libresoc.v:115338.3-115380.6" + process $proc$libresoc.v:115338$4383 assign { } { } assign { } { } - assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:104499.5-104499.29" + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:115339.5-115339.29" switch \initial - attribute \src "libresoc.v:104499.9-104499.17" + attribute \src "libresoc.v:115339.9-115339.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - case - assign $1\dec58_cry_out[0:0] 1'0 - end - sync always - update \dec58_cry_out $0\dec58_cry_out[0:0] - end - attribute \src "libresoc.v:104514.3-104529.6" - process $proc$libresoc.v:104514$4181 - assign { } { } - assign { } { } - assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:104515.5-104515.29" - switch \initial - attribute \src "libresoc.v:104515.9-104515.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10001 assign { } { } - assign $1\dec58_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00000 assign { } { } - assign $1\dec58_br[0:0] 1'0 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10000 assign { } { } - assign $1\dec58_br[0:0] 1'0 - case - assign $1\dec58_br[0:0] 1'0 - end - sync always - update \dec58_br $0\dec58_br[0:0] - end - attribute \src "libresoc.v:104530.3-104545.6" - process $proc$libresoc.v:104530$4182 - assign { } { } - assign { } { } - assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:104531.5-104531.29" - switch \initial - attribute \src "libresoc.v:104531.9-104531.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00100 assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10100 assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00111 assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'1 - case - assign $1\dec58_sgn_ext[0:0] 1'0 - end - sync always - update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] - end - attribute \src "libresoc.v:104546.3-104561.6" - process $proc$libresoc.v:104546$4183 - assign { } { } - assign { } { } - assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:104547.5-104547.29" - switch \initial - attribute \src "libresoc.v:104547.9-104547.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10111 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00110 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10110 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 case - assign $1\dec58_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 end sync always - update \dec58_internal_op $0\dec58_internal_op[6:0] + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:104562.3-104577.6" - process $proc$libresoc.v:104562$4184 + attribute \src "libresoc.v:115381.3-115423.6" + process $proc$libresoc.v:115381$4384 assign { } { } assign { } { } - assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:104563.5-104563.29" + assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:115382.5-115382.29" switch \initial - attribute \src "libresoc.v:104563.9-104563.17" + attribute \src "libresoc.v:115382.9-115382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - case - assign $1\dec58_rsrv[0:0] 1'0 - end - sync always - update \dec58_rsrv $0\dec58_rsrv[0:0] - end - attribute \src "libresoc.v:104578.3-104593.6" - process $proc$libresoc.v:104578$4185 - assign { } { } - assign { } { } - assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:104579.5-104579.29" - switch \initial - attribute \src "libresoc.v:104579.9-104579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10001 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00000 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10000 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - case - assign $1\dec58_is_32b[0:0] 1'0 - end - sync always - update \dec58_is_32b $0\dec58_is_32b[0:0] - end - attribute \src "libresoc.v:104594.3-104609.6" - process $proc$libresoc.v:104594$4186 - assign { } { } - assign { } { } - assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:104595.5-104595.29" - switch \initial - attribute \src "libresoc.v:104595.9-104595.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00100 assign { } { } - assign $1\dec58_sgn[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10100 assign { } { } - assign $1\dec58_sgn[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00111 assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - case - assign $1\dec58_sgn[0:0] 1'0 - end - sync always - update \dec58_sgn $0\dec58_sgn[0:0] - end - attribute \src "libresoc.v:104610.3-104625.6" - process $proc$libresoc.v:104610$4187 - assign { } { } - assign { } { } - assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:104611.5-104611.29" - switch \initial - attribute \src "libresoc.v:104611.9-104611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10111 assign { } { } - assign $1\dec58_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00110 assign { } { } - assign $1\dec58_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10110 assign { } { } - assign $1\dec58_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 case - assign $1\dec58_lk[0:0] 1'0 + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'00 end sync always - update \dec58_lk $0\dec58_lk[0:0] + update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end - attribute \src "libresoc.v:104626.3-104641.6" - process $proc$libresoc.v:104626$4188 + attribute \src "libresoc.v:115424.3-115466.6" + process $proc$libresoc.v:115424$4385 assign { } { } assign { } { } - assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:104627.5-104627.29" + assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:115425.5-115425.29" switch \initial - attribute \src "libresoc.v:104627.9-104627.17" + attribute \src "libresoc.v:115425.9-115425.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - case - assign $1\dec58_sgl_pipe[0:0] 1'0 - end - sync always - update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] - end - attribute \src "libresoc.v:104642.3-104657.6" - process $proc$libresoc.v:104642$4189 - assign { } { } - assign { } { } - assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:104643.5-104643.29" - switch \initial - attribute \src "libresoc.v:104643.9-104643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10001 assign { } { } - assign $1\dec58_form[4:0] 5'00101 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00000 assign { } { } - assign $1\dec58_form[4:0] 5'00101 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10000 assign { } { } - assign $1\dec58_form[4:0] 5'00101 - case - assign $1\dec58_form[4:0] 5'00000 - end - sync always - update \dec58_form $0\dec58_form[4:0] - end - attribute \src "libresoc.v:104658.3-104673.6" - process $proc$libresoc.v:104658$4190 - assign { } { } - assign { } { } - assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:104659.5-104659.29" - switch \initial - attribute \src "libresoc.v:104659.9-104659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00100 assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10100 assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00111 assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - case - assign $1\dec58_in1_sel[2:0] 3'000 - end - sync always - update \dec58_in1_sel $0\dec58_in1_sel[2:0] - end - attribute \src "libresoc.v:104674.3-104689.6" - process $proc$libresoc.v:104674$4191 - assign { } { } - assign { } { } - assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:104675.5-104675.29" - switch \initial - attribute \src "libresoc.v:104675.9-104675.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10111 assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00110 assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'10110 assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 case - assign $1\dec58_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'00 end sync always - update \dec58_in2_sel $0\dec58_in2_sel[3:0] + update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end - attribute \src "libresoc.v:104690.3-104705.6" - process $proc$libresoc.v:104690$4192 + attribute \src "libresoc.v:115467.3-115509.6" + process $proc$libresoc.v:115467$4386 assign { } { } assign { } { } - assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:104691.5-104691.29" + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:115468.5-115468.29" switch \initial - attribute \src "libresoc.v:104691.9-104691.17" + attribute \src "libresoc.v:115468.9-115468.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 case - assign $1\dec58_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 end sync always - update \dec58_in3_sel $0\dec58_in3_sel[1:0] + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:104706.3-104721.6" - process $proc$libresoc.v:104706$4193 + attribute \src "libresoc.v:115510.3-115552.6" + process $proc$libresoc.v:115510$4387 assign { } { } assign { } { } - assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:104707.5-104707.29" + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:115511.5-115511.29" switch \initial - attribute \src "libresoc.v:104707.9-104707.17" + attribute \src "libresoc.v:115511.9-115511.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 case - assign $1\dec58_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 end sync always - update \dec58_out_sel $0\dec58_out_sel[1:0] + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:104722.3-104737.6" - process $proc$libresoc.v:104722$4194 + attribute \src "libresoc.v:115553.3-115595.6" + process $proc$libresoc.v:115553$4388 assign { } { } assign { } { } - assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:104723.5-104723.29" + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:115554.5-115554.29" switch \initial - attribute \src "libresoc.v:104723.9-104723.17" + attribute \src "libresoc.v:115554.9-115554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 case - assign $1\dec58_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 end sync always - update \dec58_cr_in $0\dec58_cr_in[2:0] + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:104738.3-104753.6" - process $proc$libresoc.v:104738$4195 + attribute \src "libresoc.v:115596.3-115638.6" + process $proc$libresoc.v:115596$4389 assign { } { } assign { } { } - assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:104739.5-104739.29" + assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:115597.5-115597.29" switch \initial - attribute \src "libresoc.v:104739.9-104739.17" + attribute \src "libresoc.v:115597.9-115597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00011 assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10011 assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'00001 assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 case - assign $1\dec58_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'000 end sync always - update \dec58_cr_out $0\dec58_cr_out[2:0] + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[2:0] end - connect \opcode_switch \opcode_in [1:0] + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:104759.1-105330.10" +attribute \src "libresoc.v:115644.1-117744.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" -module \dec62 - attribute \src "libresoc.v:105082.3-105094.6" - wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:105134.3-105146.6" - wire $0\dec62_br[0:0] - attribute \src "libresoc.v:105303.3-105315.6" - wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:105316.3-105328.6" - wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:105069.3-105081.6" - wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:105121.3-105133.6" - wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:105238.3-105250.6" - wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:105017.3-105029.6" - wire width 12 $0\dec62_function_unit[11:0] - attribute \src "libresoc.v:105251.3-105263.6" - wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:105264.3-105276.6" - wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:105277.3-105289.6" - wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:105160.3-105172.6" - wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:105095.3-105107.6" - wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:105108.3-105120.6" - wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:105186.3-105198.6" - wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:105030.3-105042.6" - wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:105212.3-105224.6" - wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:105290.3-105302.6" - wire width 2 $0\dec62_out_sel[1:0] - attribute \src "libresoc.v:105056.3-105068.6" - wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:105173.3-105185.6" - wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:105225.3-105237.6" - wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:105199.3-105211.6" - wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:105147.3-105159.6" - wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:105043.3-105055.6" - wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:104760.7-104760.20" +module \dec31_dec_sub9 + attribute \src "libresoc.v:117413.3-117467.6" + wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:117468.3-117522.6" + wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:116753.3-116807.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:116973.3-117027.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:116038.3-116092.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:116093.3-116147.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:116698.3-116752.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:116918.3-116972.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:117193.3-117247.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:115983.3-116037.6" + wire width 14 $0\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:117523.3-117577.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:117578.3-117632.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:117633.3-117687.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:116588.3-116642.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:116808.3-116862.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:116863.3-116917.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:117138.3-117192.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:116478.3-116532.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:117303.3-117357.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:117688.3-117742.6" + wire width 3 $0\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:116643.3-116697.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:117083.3-117137.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:117358.3-117412.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:117248.3-117302.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:117028.3-117082.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:116368.3-116422.6" + wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:116423.3-116477.6" + wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:116148.3-116202.6" + wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:116203.3-116257.6" + wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:116258.3-116312.6" + wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:116313.3-116367.6" + wire width 3 $0\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:116533.3-116587.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:115645.7-115645.20" wire $0\initial[0:0] - attribute \src "libresoc.v:105082.3-105094.6" - wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:105134.3-105146.6" - wire $1\dec62_br[0:0] - attribute \src "libresoc.v:105303.3-105315.6" - wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:105316.3-105328.6" - wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:105069.3-105081.6" - wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:105121.3-105133.6" - wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:105238.3-105250.6" - wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:105017.3-105029.6" - wire width 12 $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:105251.3-105263.6" - wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:105264.3-105276.6" - wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:105277.3-105289.6" - wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:105160.3-105172.6" - wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:105095.3-105107.6" - wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:105108.3-105120.6" - wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:105186.3-105198.6" - wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:105030.3-105042.6" - wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:105212.3-105224.6" - wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:105290.3-105302.6" - wire width 2 $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:105056.3-105068.6" - wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:105173.3-105185.6" - wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:105225.3-105237.6" - wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:105199.3-105211.6" - wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:105147.3-105159.6" - wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:105043.3-105055.6" - wire width 2 $1\dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec62_br + attribute \src "libresoc.v:117413.3-117467.6" + wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:117468.3-117522.6" + wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:116753.3-116807.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:116973.3-117027.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:116038.3-116092.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:116093.3-116147.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:116698.3-116752.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:116918.3-116972.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:117193.3-117247.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:115983.3-116037.6" + wire width 14 $1\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:117523.3-117577.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:117578.3-117632.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:117633.3-117687.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:116588.3-116642.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:116808.3-116862.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:116863.3-116917.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:117138.3-117192.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:116478.3-116532.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:117303.3-117357.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:117688.3-117742.6" + wire width 3 $1\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:116643.3-116697.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:117083.3-117137.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:117358.3-117412.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:117248.3-117302.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:117028.3-117082.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:116368.3-116422.6" + wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:116423.3-116477.6" + wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:116148.3-116202.6" + wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:116203.3-116257.6" + wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:116258.3-116312.6" + wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:116313.3-116367.6" + wire width 3 $1\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:116533.3-116587.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub9_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub9_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -164826,24 +180264,26 @@ module \dec62 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec62_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec62_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec62_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -164874,31 +180314,34 @@ module \dec62 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec62_form + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub9_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec62_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec62_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -164914,14 +180357,14 @@ module \dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec62_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec62_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -164996,4403 +180439,2931 @@ module \dec62 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec62_is_32b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec62_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub9_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec62_out_sel + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec62_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub9_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub9_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub9_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub9_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub9_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub9_sv_out attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec62_upd - attribute \src "libresoc.v:104760.7-104760.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub9_upd + attribute \src "libresoc.v:115645.7-115645.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 2 \opcode_switch - attribute \src "libresoc.v:104760.7-104760.20" - process $proc$libresoc.v:104760$4221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:115645.7-115645.20" + process $proc$libresoc.v:115645$4423 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:105017.3-105029.6" - process $proc$libresoc.v:105017$4197 + attribute \src "libresoc.v:115983.3-116037.6" + process $proc$libresoc.v:115983$4391 assign { } { } assign { } { } - assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:105018.5-105018.29" + assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:115984.5-115984.29" switch \initial - attribute \src "libresoc.v:105018.9-105018.17" + attribute \src "libresoc.v:115984.9-115984.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - case - assign $1\dec62_function_unit[11:0] 12'000000000000 - end - sync always - update \dec62_function_unit $0\dec62_function_unit[11:0] - end - attribute \src "libresoc.v:105030.3-105042.6" - process $proc$libresoc.v:105030$4198 - assign { } { } - assign { } { } - assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:105031.5-105031.29" - switch \initial - attribute \src "libresoc.v:105031.9-105031.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01101 assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11101 assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - case - assign $1\dec62_ldst_len[3:0] 4'0000 - end - sync always - update \dec62_ldst_len $0\dec62_ldst_len[3:0] - end - attribute \src "libresoc.v:105043.3-105055.6" - process $proc$libresoc.v:105043$4199 - assign { } { } - assign { } { } - assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:105044.5-105044.29" - switch \initial - attribute \src "libresoc.v:105044.9-105044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01110 assign { } { } - assign $1\dec62_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11110 assign { } { } - assign $1\dec62_upd[1:0] 2'01 - case - assign $1\dec62_upd[1:0] 2'00 - end - sync always - update \dec62_upd $0\dec62_upd[1:0] - end - attribute \src "libresoc.v:105056.3-105068.6" - process $proc$libresoc.v:105056$4200 - assign { } { } - assign { } { } - assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:105057.5-105057.29" - switch \initial - attribute \src "libresoc.v:105057.9-105057.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01111 assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11111 assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - case - assign $1\dec62_rc_sel[1:0] 2'00 - end - sync always - update \dec62_rc_sel $0\dec62_rc_sel[1:0] - end - attribute \src "libresoc.v:105069.3-105081.6" - process $proc$libresoc.v:105069$4201 - assign { } { } - assign { } { } - assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:105070.5-105070.29" - switch \initial - attribute \src "libresoc.v:105070.9-105070.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01000 assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11000 assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - case - assign $1\dec62_cry_in[1:0] 2'00 - end - sync always - update \dec62_cry_in $0\dec62_cry_in[1:0] - end - attribute \src "libresoc.v:105082.3-105094.6" - process $proc$libresoc.v:105082$4202 - assign { } { } - assign { } { } - assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:105083.5-105083.29" - switch \initial - attribute \src "libresoc.v:105083.9-105083.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'00010 assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101100 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00000 assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101111 - case - assign $1\dec62_asmcode[7:0] 8'00000000 - end - sync always - update \dec62_asmcode $0\dec62_asmcode[7:0] - end - attribute \src "libresoc.v:105095.3-105107.6" - process $proc$libresoc.v:105095$4203 - assign { } { } - assign { } { } - assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:105096.5-105096.29" - switch \initial - attribute \src "libresoc.v:105096.9-105096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'10010 assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'10000 assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 case - assign $1\dec62_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always - update \dec62_inv_a $0\dec62_inv_a[0:0] + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:105108.3-105120.6" - process $proc$libresoc.v:105108$4204 + attribute \src "libresoc.v:116038.3-116092.6" + process $proc$libresoc.v:116038$4392 assign { } { } assign { } { } - assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:105109.5-105109.29" + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:116039.5-116039.29" switch \initial - attribute \src "libresoc.v:105109.9-105109.17" + attribute \src "libresoc.v:116039.9-116039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 case - assign $1\dec62_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 end sync always - update \dec62_inv_out $0\dec62_inv_out[0:0] + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:105121.3-105133.6" - process $proc$libresoc.v:105121$4205 + attribute \src "libresoc.v:116093.3-116147.6" + process $proc$libresoc.v:116093$4393 assign { } { } assign { } { } - assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:105122.5-105122.29" + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:116094.5-116094.29" switch \initial - attribute \src "libresoc.v:105122.9-105122.17" + attribute \src "libresoc.v:116094.9-116094.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 case - assign $1\dec62_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 end sync always - update \dec62_cry_out $0\dec62_cry_out[0:0] + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:105134.3-105146.6" - process $proc$libresoc.v:105134$4206 + attribute \src "libresoc.v:116148.3-116202.6" + process $proc$libresoc.v:116148$4394 assign { } { } assign { } { } - assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:105135.5-105135.29" + assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:116149.5-116149.29" switch \initial - attribute \src "libresoc.v:105135.9-105135.17" + attribute \src "libresoc.v:116149.9-116149.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_br[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_br[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 case - assign $1\dec62_br[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'000 end sync always - update \dec62_br $0\dec62_br[0:0] + update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end - attribute \src "libresoc.v:105147.3-105159.6" - process $proc$libresoc.v:105147$4207 + attribute \src "libresoc.v:116203.3-116257.6" + process $proc$libresoc.v:116203$4395 assign { } { } assign { } { } - assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:105148.5-105148.29" + assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:116204.5-116204.29" switch \initial - attribute \src "libresoc.v:105148.9-105148.17" + attribute \src "libresoc.v:116204.9-116204.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 case - assign $1\dec62_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'000 end sync always - update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end - attribute \src "libresoc.v:105160.3-105172.6" - process $proc$libresoc.v:105160$4208 + attribute \src "libresoc.v:116258.3-116312.6" + process $proc$libresoc.v:116258$4396 assign { } { } assign { } { } - assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:105161.5-105161.29" + assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:116259.5-116259.29" switch \initial - attribute \src "libresoc.v:105161.9-105161.17" + attribute \src "libresoc.v:116259.9-116259.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 case - assign $1\dec62_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 end sync always - update \dec62_internal_op $0\dec62_internal_op[6:0] + update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end - attribute \src "libresoc.v:105173.3-105185.6" - process $proc$libresoc.v:105173$4209 + attribute \src "libresoc.v:116313.3-116367.6" + process $proc$libresoc.v:116313$4397 assign { } { } assign { } { } - assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:105174.5-105174.29" + assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:116314.5-116314.29" switch \initial - attribute \src "libresoc.v:105174.9-105174.17" + attribute \src "libresoc.v:116314.9-116314.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 case - assign $1\dec62_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_out[2:0] 3'000 end sync always - update \dec62_rsrv $0\dec62_rsrv[0:0] + update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end - attribute \src "libresoc.v:105186.3-105198.6" - process $proc$libresoc.v:105186$4210 + attribute \src "libresoc.v:116368.3-116422.6" + process $proc$libresoc.v:116368$4398 assign { } { } assign { } { } - assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:105187.5-105187.29" + assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:116369.5-116369.29" switch \initial - attribute \src "libresoc.v:105187.9-105187.17" + attribute \src "libresoc.v:116369.9-116369.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 case - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 end sync always - update \dec62_is_32b $0\dec62_is_32b[0:0] + update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end - attribute \src "libresoc.v:105199.3-105211.6" - process $proc$libresoc.v:105199$4211 + attribute \src "libresoc.v:116423.3-116477.6" + process $proc$libresoc.v:116423$4399 assign { } { } assign { } { } - assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:105200.5-105200.29" + assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:116424.5-116424.29" switch \initial - attribute \src "libresoc.v:105200.9-105200.17" + attribute \src "libresoc.v:116424.9-116424.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 case - assign $1\dec62_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 end sync always - update \dec62_sgn $0\dec62_sgn[0:0] + update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end - attribute \src "libresoc.v:105212.3-105224.6" - process $proc$libresoc.v:105212$4212 + attribute \src "libresoc.v:116478.3-116532.6" + process $proc$libresoc.v:116478$4400 assign { } { } assign { } { } - assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:105213.5-105213.29" + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:116479.5-116479.29" switch \initial - attribute \src "libresoc.v:105213.9-105213.17" + attribute \src "libresoc.v:116479.9-116479.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 case - assign $1\dec62_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 end sync always - update \dec62_lk $0\dec62_lk[0:0] + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:105225.3-105237.6" - process $proc$libresoc.v:105225$4213 + attribute \src "libresoc.v:116533.3-116587.6" + process $proc$libresoc.v:116533$4401 assign { } { } assign { } { } - assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:105226.5-105226.29" + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:116534.5-116534.29" switch \initial - attribute \src "libresoc.v:105226.9-105226.17" + attribute \src "libresoc.v:116534.9-116534.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 case - assign $1\dec62_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 end sync always - update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:105238.3-105250.6" - process $proc$libresoc.v:105238$4214 + attribute \src "libresoc.v:116588.3-116642.6" + process $proc$libresoc.v:116588$4402 assign { } { } assign { } { } - assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:105239.5-105239.29" + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:116589.5-116589.29" switch \initial - attribute \src "libresoc.v:105239.9-105239.17" + attribute \src "libresoc.v:116589.9-116589.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_form[4:0] 5'00101 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_form[4:0] 5'00101 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 case - assign $1\dec62_form[4:0] 5'00000 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 end sync always - update \dec62_form $0\dec62_form[4:0] + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:105251.3-105263.6" - process $proc$libresoc.v:105251$4215 + attribute \src "libresoc.v:116643.3-116697.6" + process $proc$libresoc.v:116643$4403 assign { } { } assign { } { } - assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:105252.5-105252.29" + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:116644.5-116644.29" switch \initial - attribute \src "libresoc.v:105252.9-105252.17" + attribute \src "libresoc.v:116644.9-116644.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 case - assign $1\dec62_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 end sync always - update \dec62_in1_sel $0\dec62_in1_sel[2:0] + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:105264.3-105276.6" - process $proc$libresoc.v:105264$4216 + attribute \src "libresoc.v:116698.3-116752.6" + process $proc$libresoc.v:116698$4404 assign { } { } assign { } { } - assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:105265.5-105265.29" + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:116699.5-116699.29" switch \initial - attribute \src "libresoc.v:105265.9-105265.17" + attribute \src "libresoc.v:116699.9-116699.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 case - assign $1\dec62_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 end sync always - update \dec62_in2_sel $0\dec62_in2_sel[3:0] + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:105277.3-105289.6" - process $proc$libresoc.v:105277$4217 + attribute \src "libresoc.v:116753.3-116807.6" + process $proc$libresoc.v:116753$4405 assign { } { } assign { } { } - assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:105278.5-105278.29" + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:116754.5-116754.29" switch \initial - attribute \src "libresoc.v:105278.9-105278.17" + attribute \src "libresoc.v:116754.9-116754.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 case - assign $1\dec62_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 end sync always - update \dec62_in3_sel $0\dec62_in3_sel[1:0] + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:105290.3-105302.6" - process $proc$libresoc.v:105290$4218 + attribute \src "libresoc.v:116808.3-116862.6" + process $proc$libresoc.v:116808$4406 assign { } { } assign { } { } - assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:105291.5-105291.29" + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:116809.5-116809.29" switch \initial - attribute \src "libresoc.v:105291.9-105291.17" + attribute \src "libresoc.v:116809.9-116809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 case - assign $1\dec62_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 end sync always - update \dec62_out_sel $0\dec62_out_sel[1:0] + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:105303.3-105315.6" - process $proc$libresoc.v:105303$4219 + attribute \src "libresoc.v:116863.3-116917.6" + process $proc$libresoc.v:116863$4407 assign { } { } assign { } { } - assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:105304.5-105304.29" + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:116864.5-116864.29" switch \initial - attribute \src "libresoc.v:105304.9-105304.17" + attribute \src "libresoc.v:116864.9-116864.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 case - assign $1\dec62_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 end sync always - update \dec62_cr_in $0\dec62_cr_in[2:0] + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:105316.3-105328.6" - process $proc$libresoc.v:105316$4220 + attribute \src "libresoc.v:116918.3-116972.6" + process $proc$libresoc.v:116918$4408 assign { } { } assign { } { } - assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:105317.5-105317.29" + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:116919.5-116919.29" switch \initial - attribute \src "libresoc.v:105317.9-105317.17" + attribute \src "libresoc.v:116919.9-116919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01100 assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'11100 assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 case - assign $1\dec62_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 end sync always - update \dec62_cr_out $0\dec62_cr_out[2:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:105334.1-105867.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" -attribute \generator "nMigen" -module \dec_ALU - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \ALU__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \ALU__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \ALU__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \ALU__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 14 \ALU__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \ALU__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \ALU__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \ALU__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \ALU__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \ALU__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \ALU__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \ALU__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \ALU__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \ALU__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \ALU__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \ALU__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \ALU__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_ALU_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_ALU_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_ALU_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_ALU_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_ALU_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_ALU_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_ALU_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 20 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:105751.7-105788.4" - cell \dec \dec - connect \ALU_BA \dec_ALU_BA - connect \ALU_BB \dec_ALU_BB - connect \ALU_BC \dec_ALU_BC - connect \ALU_BD \dec_ALU_BD - connect \ALU_BI \dec_ALU_BI - connect \ALU_BT \dec_ALU_BT - connect \ALU_DS \dec_ALU_DS - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_LI \dec_ALU_LI - connect \ALU_OE \dec_ALU_OE - connect \ALU_RA \dec_ALU_RA - connect \ALU_Rc \dec_ALU_Rc - connect \ALU_SH32 \dec_ALU_SH32 - connect \ALU_SI \dec_ALU_SI - connect \ALU_UI \dec_ALU_UI - connect \ALU_cr_in \dec_ALU_cr_in - connect \ALU_cr_out \dec_ALU_cr_out - connect \ALU_cry_in \dec_ALU_cry_in - connect \ALU_cry_out \dec_ALU_cry_out - connect \ALU_function_unit \dec_ALU_function_unit - connect \ALU_in1_sel \dec_ALU_in1_sel - connect \ALU_in2_sel \dec_ALU_in2_sel - connect \ALU_internal_op \dec_ALU_internal_op - connect \ALU_inv_a \dec_ALU_inv_a - connect \ALU_inv_out \dec_ALU_inv_out - connect \ALU_is_32b \dec_ALU_is_32b - connect \ALU_ldst_len \dec_ALU_ldst_len - connect \ALU_rc_sel \dec_ALU_rc_sel - connect \ALU_sgn \dec_ALU_sgn - connect \ALU_sh \dec_ALU_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105789.10-105793.4" - cell \dec_ai \dec_ai - connect \ALU_RA \dec_ALU_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105794.10-105805.4" - cell \dec_bi \dec_bi - connect \ALU_BD \dec_ALU_BD - connect \ALU_DS \dec_ALU_DS - connect \ALU_LI \dec_ALU_LI - connect \ALU_SH32 \dec_ALU_SH32 - connect \ALU_SI \dec_ALU_SI - connect \ALU_UI \dec_ALU_UI - connect \ALU_sh \dec_ALU_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105806.13-105817.4" - cell \dec_cr_in \dec_cr_in - connect \ALU_BA \dec_ALU_BA - connect \ALU_BB \dec_ALU_BB - connect \ALU_BC \dec_ALU_BC - connect \ALU_BI \dec_ALU_BI - connect \ALU_BT \dec_ALU_BT - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_internal_op \dec_ALU_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105818.14-105827.4" - cell \dec_cr_out \dec_cr_out - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_internal_op \dec_ALU_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105828.10-105834.4" - cell \dec_oe \dec_oe - connect \ALU_OE \dec_ALU_OE - connect \ALU_internal_op \dec_ALU_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105835.10-105840.4" - cell \dec_rc \dec_rc - connect \ALU_Rc \dec_ALU_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \ALU__is_signed \dec_ALU_sgn - connect \ALU__is_32bit \dec_ALU_is_32b - connect \ALU__output_carry \dec_ALU_cry_out - connect \ALU__input_carry \dec_ALU_cry_in - connect \ALU__invert_out \dec_ALU_inv_out - connect \ALU__invert_in \dec_ALU_inv_a - connect \ALU__data_len \dec_ALU_ldst_len - connect \ALU__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \ALU__oe__ok \ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \ALU__rc__ok \ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \ALU__imm_data__ok \ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_ALU_in2_sel - connect \ALU__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_ALU_in1_sel - connect \ALU__fn_unit \dec_ALU_function_unit - connect \ALU__insn_type \dec_ALU_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_ALU_cr_out - connect \dec_cr_in_sel_in \dec_ALU_cr_in - connect \dec_oe_sel_in \dec_ALU_rc_sel - connect \dec_rc_sel_in \dec_ALU_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \ALU__insn \dec_opcode_in -end -attribute \src "libresoc.v:105871.1-106323.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" -attribute \generator "nMigen" -module \dec_BRANCH - attribute \src "libresoc.v:106297.3-106306.6" - wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:105872.7-105872.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:106297.3-106306.6" - wire $1\BRANCH__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 3 \BRANCH__cia - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 5 \BRANCH__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \BRANCH__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \BRANCH__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 6 \BRANCH__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 4 \BRANCH__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \BRANCH__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 2 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 11 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_BRANCH_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_BRANCH_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_BRANCH_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_BRANCH_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_BRANCH_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_BRANCH_lk - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:105872.7-105872.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 1 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:106222.13-106253.4" - cell \dec$147 \dec - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BC \dec_BRANCH_BC - connect \BRANCH_BD \dec_BRANCH_BD - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BT \dec_BRANCH_BT - connect \BRANCH_DS \dec_BRANCH_DS - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_LI \dec_BRANCH_LI - connect \BRANCH_LK \dec_BRANCH_LK - connect \BRANCH_OE \dec_BRANCH_OE - connect \BRANCH_Rc \dec_BRANCH_Rc - connect \BRANCH_SH32 \dec_BRANCH_SH32 - connect \BRANCH_SI \dec_BRANCH_SI - connect \BRANCH_UI \dec_BRANCH_UI - connect \BRANCH_cr_in \dec_BRANCH_cr_in - connect \BRANCH_cr_out \dec_BRANCH_cr_out - connect \BRANCH_function_unit \dec_BRANCH_function_unit - connect \BRANCH_in2_sel \dec_BRANCH_in2_sel - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \BRANCH_is_32b \dec_BRANCH_is_32b - connect \BRANCH_lk \dec_BRANCH_lk - connect \BRANCH_rc_sel \dec_BRANCH_rc_sel - connect \BRANCH_sh \dec_BRANCH_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106254.16-106265.4" - cell \dec_bi$154 \dec_bi - connect \BRANCH_BD \dec_BRANCH_BD - connect \BRANCH_DS \dec_BRANCH_DS - connect \BRANCH_LI \dec_BRANCH_LI - connect \BRANCH_SH32 \dec_BRANCH_SH32 - connect \BRANCH_SI \dec_BRANCH_SI - connect \BRANCH_UI \dec_BRANCH_UI - connect \BRANCH_sh \dec_BRANCH_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106266.19-106277.4" - cell \dec_cr_in$150 \dec_cr_in - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BC \dec_BRANCH_BC - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BT \dec_BRANCH_BT - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106278.20-106286.4" - cell \dec_cr_out$152 \dec_cr_out - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106287.16-106291.4" - cell \dec_oe$149 \dec_oe - connect \BRANCH_OE \dec_BRANCH_OE - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106292.16-106296.4" - cell \dec_rc$148 \dec_rc - connect \BRANCH_Rc \dec_BRANCH_Rc - connect \rc \dec_rc_rc - connect \sel_in \dec_rc_sel_in - end - attribute \src "libresoc.v:105872.7-105872.20" - process $proc$libresoc.v:105872$4223 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:106297.3-106306.6" - process $proc$libresoc.v:106297$4222 + attribute \src "libresoc.v:116973.3-117027.6" + process $proc$libresoc.v:116973$4409 assign { } { } assign { } { } - assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:106298.5-106298.29" + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:116974.5-116974.29" switch \initial - attribute \src "libresoc.v:106298.9-106298.17" + attribute \src "libresoc.v:116974.9-116974.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" - switch \dec_BRANCH_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $1\BRANCH__lk[0:0] \dec_BRANCH_LK + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 case - assign $1\BRANCH__lk[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 end sync always - update \BRANCH__lk $0\BRANCH__lk[0:0] + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - connect \BRANCH__is_32bit \dec_BRANCH_is_32b - connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_BRANCH_in2_sel - connect \BRANCH__fn_unit \dec_BRANCH_function_unit - connect \BRANCH__insn_type \dec_BRANCH_internal_op - connect \BRANCH__cia \core_pc - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_BRANCH_cr_out - connect \dec_cr_in_sel_in \dec_BRANCH_cr_in - connect \dec_oe_sel_in \dec_BRANCH_rc_sel - connect \dec_rc_sel_in \dec_BRANCH_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \BRANCH__insn \dec_opcode_in -end -attribute \src "libresoc.v:106327.1-106670.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" -attribute \generator "nMigen" -module \dec_CR - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \CR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 4 \CR__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute 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\enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_CR_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_CR_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_CR_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 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attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 5 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:106606.13-106626.4" - cell \dec$140 \dec - connect \CR_BA \dec_CR_BA - connect \CR_BB \dec_CR_BB - connect \CR_BC \dec_CR_BC - connect \CR_BI \dec_CR_BI - connect \CR_BT \dec_CR_BT - connect \CR_FXM \dec_CR_FXM - connect \CR_OE \dec_CR_OE - connect \CR_Rc \dec_CR_Rc - connect \CR_cr_in \dec_CR_cr_in - connect \CR_cr_out \dec_CR_cr_out - connect \CR_function_unit \dec_CR_function_unit - connect \CR_internal_op \dec_CR_internal_op - connect \CR_rc_sel \dec_CR_rc_sel - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src 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attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \DIV__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \DIV__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \DIV__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \DIV__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \DIV__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \DIV__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \DIV__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \DIV__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \DIV__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \DIV__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \DIV__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \DIV__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_DIV_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_DIV_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_DIV_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_DIV_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_DIV_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_DIV_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_DIV_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 20 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:107091.13-107128.4" - cell \dec$171 \dec - connect \DIV_BA \dec_DIV_BA - connect \DIV_BB \dec_DIV_BB - connect \DIV_BC \dec_DIV_BC - connect \DIV_BD \dec_DIV_BD - connect \DIV_BI \dec_DIV_BI - connect \DIV_BT \dec_DIV_BT - connect \DIV_DS \dec_DIV_DS - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_LI \dec_DIV_LI - connect \DIV_OE \dec_DIV_OE - connect \DIV_RA \dec_DIV_RA - connect \DIV_Rc \dec_DIV_Rc - connect \DIV_SH32 \dec_DIV_SH32 - connect \DIV_SI \dec_DIV_SI - connect \DIV_UI \dec_DIV_UI - connect \DIV_cr_in \dec_DIV_cr_in - connect \DIV_cr_out \dec_DIV_cr_out - connect \DIV_cry_in \dec_DIV_cry_in - connect \DIV_cry_out \dec_DIV_cry_out - connect \DIV_function_unit \dec_DIV_function_unit - connect \DIV_in1_sel \dec_DIV_in1_sel - connect \DIV_in2_sel \dec_DIV_in2_sel - connect \DIV_internal_op \dec_DIV_internal_op - connect \DIV_inv_a \dec_DIV_inv_a - connect \DIV_inv_out \dec_DIV_inv_out - connect \DIV_is_32b \dec_DIV_is_32b - connect \DIV_ldst_len \dec_DIV_ldst_len - connect \DIV_rc_sel \dec_DIV_rc_sel - connect \DIV_sgn \dec_DIV_sgn - connect \DIV_sh \dec_DIV_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107129.16-107133.4" - cell \dec_ai$178 \dec_ai - connect \DIV_RA \dec_DIV_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107134.16-107145.4" - cell \dec_bi$179 \dec_bi - connect \DIV_BD \dec_DIV_BD - connect \DIV_DS \dec_DIV_DS - connect \DIV_LI \dec_DIV_LI - connect \DIV_SH32 \dec_DIV_SH32 - connect \DIV_SI \dec_DIV_SI - connect \DIV_UI \dec_DIV_UI - connect \DIV_sh \dec_DIV_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107146.19-107157.4" - cell \dec_cr_in$174 \dec_cr_in - connect \DIV_BA \dec_DIV_BA - connect \DIV_BB \dec_DIV_BB - connect \DIV_BC \dec_DIV_BC - connect \DIV_BI \dec_DIV_BI - connect \DIV_BT \dec_DIV_BT - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_internal_op \dec_DIV_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107158.20-107167.4" - cell \dec_cr_out$176 \dec_cr_out - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_internal_op \dec_DIV_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107168.16-107174.4" - cell \dec_oe$173 \dec_oe - connect \DIV_OE \dec_DIV_OE - connect \DIV_internal_op \dec_DIV_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107175.16-107180.4" - cell \dec_rc$172 \dec_rc - connect \DIV_Rc \dec_DIV_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \DIV__is_signed \dec_DIV_sgn - connect \DIV__is_32bit \dec_DIV_is_32b - connect \DIV__output_carry \dec_DIV_cry_out - connect \DIV__input_carry \dec_DIV_cry_in - connect \DIV__invert_out \dec_DIV_inv_out - connect \DIV__invert_in \dec_DIV_inv_a - connect \DIV__data_len \dec_DIV_ldst_len - connect \DIV__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_DIV_in2_sel - connect \DIV__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_DIV_in1_sel - connect \DIV__fn_unit \dec_DIV_function_unit - connect \DIV__insn_type \dec_DIV_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_DIV_cr_out - connect \dec_cr_in_sel_in \dec_DIV_cr_in - connect \dec_oe_sel_in \dec_DIV_rc_sel - connect \dec_rc_sel_in \dec_DIV_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \DIV__insn \dec_opcode_in -end -attribute \src "libresoc.v:107211.1-107734.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" -attribute \generator "nMigen" -module \dec_LDST - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LDST__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 13 \LDST__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \LDST__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \LDST__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \LDST__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \LDST__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LDST__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LDST__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \LDST__is_signed - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 16 \LDST__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LDST__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LDST__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LDST__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LDST__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LDST__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LDST_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LDST_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LDST_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_LDST_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LDST_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_LDST_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LDST_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_LDST_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_LDST_sh - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 18 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:107622.13-107658.4" - cell \dec$196 \dec - connect \LDST_BA \dec_LDST_BA - connect \LDST_BB \dec_LDST_BB - connect \LDST_BC \dec_LDST_BC - connect \LDST_BD \dec_LDST_BD - connect \LDST_BI \dec_LDST_BI - connect \LDST_BT \dec_LDST_BT - connect \LDST_DS \dec_LDST_DS - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_LI \dec_LDST_LI - connect \LDST_OE \dec_LDST_OE - connect \LDST_RA \dec_LDST_RA - connect \LDST_Rc \dec_LDST_Rc - connect \LDST_SH32 \dec_LDST_SH32 - connect \LDST_SI \dec_LDST_SI - connect \LDST_UI \dec_LDST_UI - connect \LDST_br \dec_LDST_br - connect \LDST_cr_in \dec_LDST_cr_in - connect \LDST_cr_out \dec_LDST_cr_out - connect \LDST_function_unit \dec_LDST_function_unit - connect \LDST_in1_sel \dec_LDST_in1_sel - connect \LDST_in2_sel \dec_LDST_in2_sel - connect \LDST_internal_op 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"ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \LOGICAL__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \LOGICAL__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LOGICAL__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LOGICAL__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \LOGICAL__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \LOGICAL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \LOGICAL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LOGICAL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LOGICAL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LOGICAL__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LOGICAL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LOGICAL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LOGICAL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_LOGICAL_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LOGICAL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LOGICAL_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_LOGICAL_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LOGICAL_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_LOGICAL_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_LOGICAL_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 20 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:108155.13-108192.4" - cell \dec$155 \dec - connect \LOGICAL_BA \dec_LOGICAL_BA - connect \LOGICAL_BB \dec_LOGICAL_BB - connect \LOGICAL_BC \dec_LOGICAL_BC - connect \LOGICAL_BD \dec_LOGICAL_BD - connect \LOGICAL_BI \dec_LOGICAL_BI - connect \LOGICAL_BT \dec_LOGICAL_BT - connect \LOGICAL_DS \dec_LOGICAL_DS - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_LI \dec_LOGICAL_LI - connect \LOGICAL_OE \dec_LOGICAL_OE - connect \LOGICAL_RA \dec_LOGICAL_RA - connect \LOGICAL_Rc \dec_LOGICAL_Rc - connect \LOGICAL_SH32 \dec_LOGICAL_SH32 - connect \LOGICAL_SI \dec_LOGICAL_SI - connect \LOGICAL_UI \dec_LOGICAL_UI - connect \LOGICAL_cr_in \dec_LOGICAL_cr_in - connect \LOGICAL_cr_out \dec_LOGICAL_cr_out - connect \LOGICAL_cry_in \dec_LOGICAL_cry_in - connect \LOGICAL_cry_out \dec_LOGICAL_cry_out - connect \LOGICAL_function_unit \dec_LOGICAL_function_unit - connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel - connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \LOGICAL_inv_a \dec_LOGICAL_inv_a - connect \LOGICAL_inv_out \dec_LOGICAL_inv_out - connect \LOGICAL_is_32b \dec_LOGICAL_is_32b - connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len - connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel - connect \LOGICAL_sgn \dec_LOGICAL_sgn - connect \LOGICAL_sh \dec_LOGICAL_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in + attribute \src "libresoc.v:117028.3-117082.6" + process $proc$libresoc.v:117028$4410 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:117029.5-117029.29" + switch \initial + attribute \src "libresoc.v:117029.9-117029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108193.16-108197.4" - cell \dec_ai$162 \dec_ai - connect \LOGICAL_RA \dec_LOGICAL_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in + attribute \src "libresoc.v:117083.3-117137.6" + process $proc$libresoc.v:117083$4411 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:117084.5-117084.29" + switch \initial + attribute \src "libresoc.v:117084.9-117084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108198.16-108209.4" - cell \dec_bi$163 \dec_bi - connect \LOGICAL_BD \dec_LOGICAL_BD - connect \LOGICAL_DS \dec_LOGICAL_DS - connect \LOGICAL_LI \dec_LOGICAL_LI - connect \LOGICAL_SH32 \dec_LOGICAL_SH32 - connect \LOGICAL_SI \dec_LOGICAL_SI - connect \LOGICAL_UI \dec_LOGICAL_UI - connect \LOGICAL_sh \dec_LOGICAL_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in + attribute \src "libresoc.v:117138.3-117192.6" + process $proc$libresoc.v:117138$4412 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:117139.5-117139.29" + switch \initial + attribute \src "libresoc.v:117139.9-117139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108210.19-108221.4" - cell \dec_cr_in$158 \dec_cr_in - connect \LOGICAL_BA \dec_LOGICAL_BA - connect \LOGICAL_BB \dec_LOGICAL_BB - connect \LOGICAL_BC \dec_LOGICAL_BC - connect \LOGICAL_BI \dec_LOGICAL_BI - connect \LOGICAL_BT \dec_LOGICAL_BT - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in + attribute \src "libresoc.v:117193.3-117247.6" + process $proc$libresoc.v:117193$4413 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:117194.5-117194.29" + switch \initial + attribute \src "libresoc.v:117194.9-117194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub9_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108222.20-108231.4" - cell \dec_cr_out$160 \dec_cr_out - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in + attribute \src "libresoc.v:117248.3-117302.6" + process $proc$libresoc.v:117248$4414 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:117249.5-117249.29" + switch \initial + attribute \src "libresoc.v:117249.9-117249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108232.16-108238.4" - cell \dec_oe$157 \dec_oe - connect \LOGICAL_OE \dec_LOGICAL_OE - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in + attribute \src "libresoc.v:117303.3-117357.6" + process $proc$libresoc.v:117303$4415 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:117304.5-117304.29" + switch \initial + attribute \src "libresoc.v:117304.9-117304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108239.16-108244.4" - cell \dec_rc$156 \dec_rc - connect \LOGICAL_Rc \dec_LOGICAL_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in + attribute \src "libresoc.v:117358.3-117412.6" + process $proc$libresoc.v:117358$4416 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:117359.5-117359.29" + switch \initial + attribute \src "libresoc.v:117359.9-117359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - connect \LOGICAL__is_signed \dec_LOGICAL_sgn - connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b - connect \LOGICAL__output_carry \dec_LOGICAL_cry_out - connect \LOGICAL__input_carry \dec_LOGICAL_cry_in - connect \LOGICAL__invert_out \dec_LOGICAL_inv_out - connect \LOGICAL__invert_in \dec_LOGICAL_inv_a - connect \LOGICAL__data_len \dec_LOGICAL_ldst_len - connect \LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \LOGICAL__oe__ok \LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \LOGICAL__rc__ok \LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \LOGICAL__imm_data__ok \LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_LOGICAL_in2_sel - connect \LOGICAL__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_LOGICAL_in1_sel - connect \LOGICAL__fn_unit \dec_LOGICAL_function_unit - connect \LOGICAL__insn_type \dec_LOGICAL_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_LOGICAL_cr_out - connect \dec_cr_in_sel_in \dec_LOGICAL_cr_in - connect \dec_oe_sel_in \dec_LOGICAL_rc_sel - connect \dec_rc_sel_in \dec_LOGICAL_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \LOGICAL__insn \dec_opcode_in -end -attribute \src "libresoc.v:108275.1-108733.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" -attribute \generator "nMigen" -module \dec_MUL - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \MUL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \MUL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \MUL__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 13 \MUL__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \MUL__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \MUL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \MUL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \MUL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \MUL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \MUL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \MUL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_MUL_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_MUL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_MUL_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_MUL_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_MUL_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_MUL_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 14 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:108636.13-108666.4" - cell \dec$180 \dec - connect \MUL_BA \dec_MUL_BA - connect \MUL_BB \dec_MUL_BB - connect \MUL_BC \dec_MUL_BC - connect \MUL_BD \dec_MUL_BD - connect \MUL_BI \dec_MUL_BI - connect \MUL_BT \dec_MUL_BT - connect \MUL_DS \dec_MUL_DS - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_LI \dec_MUL_LI - connect \MUL_OE \dec_MUL_OE - connect \MUL_Rc \dec_MUL_Rc - connect \MUL_SH32 \dec_MUL_SH32 - connect \MUL_SI \dec_MUL_SI - connect \MUL_UI \dec_MUL_UI - connect \MUL_cr_in \dec_MUL_cr_in - connect \MUL_cr_out \dec_MUL_cr_out - connect \MUL_function_unit \dec_MUL_function_unit - connect \MUL_in2_sel \dec_MUL_in2_sel - connect \MUL_internal_op \dec_MUL_internal_op - connect \MUL_is_32b \dec_MUL_is_32b - connect \MUL_rc_sel \dec_MUL_rc_sel - connect \MUL_sgn \dec_MUL_sgn - connect \MUL_sh \dec_MUL_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in + attribute \src "libresoc.v:117413.3-117467.6" + process $proc$libresoc.v:117413$4417 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:117414.5-117414.29" + switch \initial + attribute \src "libresoc.v:117414.9-117414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108667.16-108678.4" - cell \dec_bi$187 \dec_bi - connect \MUL_BD \dec_MUL_BD - connect \MUL_DS \dec_MUL_DS - connect \MUL_LI \dec_MUL_LI - connect \MUL_SH32 \dec_MUL_SH32 - connect \MUL_SI \dec_MUL_SI - connect \MUL_UI \dec_MUL_UI - connect \MUL_sh \dec_MUL_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in + attribute \src "libresoc.v:117468.3-117522.6" + process $proc$libresoc.v:117468$4418 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:117469.5-117469.29" + switch \initial + attribute \src "libresoc.v:117469.9-117469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108679.19-108690.4" - cell \dec_cr_in$183 \dec_cr_in - connect \MUL_BA \dec_MUL_BA - connect \MUL_BB \dec_MUL_BB - connect \MUL_BC \dec_MUL_BC - connect \MUL_BI \dec_MUL_BI - connect \MUL_BT \dec_MUL_BT - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_internal_op \dec_MUL_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in + attribute \src "libresoc.v:117523.3-117577.6" + process $proc$libresoc.v:117523$4419 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:117524.5-117524.29" + switch \initial + attribute \src "libresoc.v:117524.9-117524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108691.20-108700.4" - cell \dec_cr_out$185 \dec_cr_out - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_internal_op \dec_MUL_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in + attribute \src "libresoc.v:117578.3-117632.6" + process $proc$libresoc.v:117578$4420 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:117579.5-117579.29" + switch \initial + attribute \src "libresoc.v:117579.9-117579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108701.16-108707.4" - cell \dec_oe$182 \dec_oe - connect \MUL_OE \dec_MUL_OE - connect \MUL_internal_op \dec_MUL_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in + attribute \src "libresoc.v:117633.3-117687.6" + process $proc$libresoc.v:117633$4421 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:117634.5-117634.29" + switch \initial + attribute \src "libresoc.v:117634.9-117634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108708.16-108713.4" - cell \dec_rc$181 \dec_rc - connect \MUL_Rc \dec_MUL_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in + attribute \src "libresoc.v:117688.3-117742.6" + process $proc$libresoc.v:117688$4422 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:117689.5-117689.29" + switch \initial + attribute \src "libresoc.v:117689.9-117689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[2:0] end - connect \MUL__is_signed \dec_MUL_sgn - connect \MUL__is_32bit \dec_MUL_is_32b - connect \MUL__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_MUL_in2_sel - connect \MUL__fn_unit \dec_MUL_function_unit - connect \MUL__insn_type \dec_MUL_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_MUL_cr_out - connect \dec_cr_in_sel_in \dec_MUL_cr_in - connect \dec_oe_sel_in \dec_MUL_rc_sel - connect \dec_rc_sel_in \dec_MUL_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \MUL__insn \dec_opcode_in + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:108737.1-109227.10" +attribute \src "libresoc.v:117748.1-118600.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" -module \dec_SHIFT_ROT - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \SHIFT_ROT__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \SHIFT_ROT__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \SHIFT_ROT__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \SHIFT_ROT__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \SHIFT_ROT__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 18 \SHIFT_ROT__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SHIFT_ROT__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \SHIFT_ROT__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \SHIFT_ROT__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \SHIFT_ROT__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \SHIFT_ROT__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \SHIFT_ROT__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \SHIFT_ROT__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \SHIFT_ROT__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \SHIFT_ROT__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \SHIFT_ROT__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_SHIFT_ROT_UI +module \dec58 + attribute \src "libresoc.v:118503.3-118518.6" + wire width 2 $0\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:118519.3-118534.6" + wire width 2 $0\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:118311.3-118326.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:118375.3-118390.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:118103.3-118118.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:118119.3-118134.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:118295.3-118310.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:118359.3-118374.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:118439.3-118454.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:118087.3-118102.6" + wire width 14 $0\dec58_function_unit[13:0] + attribute \src "libresoc.v:118535.3-118550.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:118551.3-118566.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:118567.3-118582.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:118263.3-118278.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:118327.3-118342.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:118343.3-118358.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:118423.3-118438.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:118231.3-118246.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:118471.3-118486.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:118583.3-118598.6" + wire width 3 $0\dec58_out_sel[2:0] + attribute \src "libresoc.v:118279.3-118294.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:118407.3-118422.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:118487.3-118502.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:118455.3-118470.6" + wire $0\dec58_sgn[0:0] + attribute \src "libresoc.v:118391.3-118406.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:118199.3-118214.6" + wire width 3 $0\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:118215.3-118230.6" + wire width 3 $0\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:118135.3-118150.6" + wire width 3 $0\dec58_sv_in1[2:0] + attribute \src "libresoc.v:118151.3-118166.6" + wire width 3 $0\dec58_sv_in2[2:0] + attribute \src "libresoc.v:118167.3-118182.6" + wire width 3 $0\dec58_sv_in3[2:0] + attribute \src "libresoc.v:118183.3-118198.6" + wire width 3 $0\dec58_sv_out[2:0] + attribute \src "libresoc.v:118247.3-118262.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "libresoc.v:117749.7-117749.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118503.3-118518.6" + wire width 2 $1\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:118519.3-118534.6" + wire width 2 $1\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:118311.3-118326.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:118375.3-118390.6" + wire $1\dec58_br[0:0] + attribute \src "libresoc.v:118103.3-118118.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:118119.3-118134.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:118295.3-118310.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:118359.3-118374.6" + wire $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:118439.3-118454.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "libresoc.v:118087.3-118102.6" + wire width 14 $1\dec58_function_unit[13:0] + attribute \src "libresoc.v:118535.3-118550.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:118551.3-118566.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:118567.3-118582.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:118263.3-118278.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:118327.3-118342.6" + wire $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:118343.3-118358.6" + wire $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:118423.3-118438.6" + wire $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:118231.3-118246.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:118471.3-118486.6" + wire $1\dec58_lk[0:0] + attribute \src "libresoc.v:118583.3-118598.6" + wire width 3 $1\dec58_out_sel[2:0] + attribute \src "libresoc.v:118279.3-118294.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:118407.3-118422.6" + wire $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:118487.3-118502.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:118455.3-118470.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:118391.3-118406.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:118199.3-118214.6" + wire width 3 $1\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:118215.3-118230.6" + wire width 3 $1\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:118135.3-118150.6" + wire width 3 $1\dec58_sv_in1[2:0] + attribute \src "libresoc.v:118151.3-118166.6" + wire width 3 $1\dec58_sv_in2[2:0] + attribute \src "libresoc.v:118167.3-118182.6" + wire width 3 $1\dec58_sv_in3[2:0] + attribute \src "libresoc.v:118183.3-118198.6" + wire width 3 $1\dec58_sv_out[2:0] + attribute \src "libresoc.v:118247.3-118262.6" + wire width 2 $1\dec58_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec58_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec58_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -169401,156 +183372,84 @@ module \dec_SHIFT_ROT attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_SHIFT_ROT_cr_in + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_SHIFT_ROT_cr_out + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec58_form attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_SHIFT_ROT_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_SHIFT_ROT_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SHIFT_ROT_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SHIFT_ROT_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -169566,671 +183465,14 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 19 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:109122.13-109155.4" - cell \dec$188 \dec - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI - connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE - connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc - connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 - connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI - connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI - connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out - connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out - connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit - connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \SHIFT_ROT_inv_a \dec_SHIFT_ROT_inv_a - connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b - connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn - connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109156.16-109167.4" - cell \dec_bi$195 \dec_bi - connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI - connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 - connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI - connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI - connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109168.19-109179.4" - cell \dec_cr_in$191 \dec_cr_in - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109180.20-109189.4" - cell \dec_cr_out$193 \dec_cr_out - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109190.16-109196.4" - cell \dec_oe$190 \dec_oe - connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109197.16-109202.4" - cell \dec_rc$189 \dec_rc - connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn - connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b - connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out - connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in - connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a - connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] - connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] - connect \SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel - connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit - connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out - connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in - connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel - connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \SHIFT_ROT__insn \dec_opcode_in -end -attribute \src "libresoc.v:109231.1-109580.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" -attribute \generator "nMigen" -module \dec_SPR - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \SPR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 4 \SPR__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SPR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_SPR_Rc - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_SPR_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_SPR_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_SPR_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SPR_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" 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attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $and $and$libresoc.v:109970$4230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \$17 - connect \Y $and$libresoc.v:109970$4230_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" - cell $and $and$libresoc.v:109975$4235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B 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$eq$libresoc.v:109966$4226_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" - cell $eq $eq$libresoc.v:109967$4227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:109967$4227_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - cell $eq $eq$libresoc.v:109969$4229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'001 - connect \Y $eq$libresoc.v:109969$4229_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - cell $eq $eq$libresoc.v:109972$4232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 - connect \Y $eq$libresoc.v:109972$4232_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" - cell $eq $eq$libresoc.v:109976$4236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:109976$4236_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $ne $ne$libresoc.v:109968$4228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $ne$libresoc.v:109968$4228_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $ne $ne$libresoc.v:109977$4237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $ne$libresoc.v:109977$4237_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" - cell $not $not$libresoc.v:109973$4233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $not$libresoc.v:109973$4233_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" - cell $not $not$libresoc.v:109974$4234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [5] - connect \Y $not$libresoc.v:109974$4234_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $or $or$libresoc.v:109964$4224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$7 - connect \Y $or$libresoc.v:109964$4224_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $or $or$libresoc.v:109971$4231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$13 - connect \B \$19 - connect \Y $or$libresoc.v:109971$4231_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109979.10-109985.4" - cell \sprmap \sprmap - connect \fast_o \sprmap_fast_o - connect \fast_o_ok \sprmap_fast_o_ok - connect \spr_i \sprmap_spr_i - connect \spr_o \sprmap_spr_o - connect \spr_o_ok \sprmap_spr_o_ok - end - attribute \src "libresoc.v:109585.7-109585.20" - process $proc$libresoc.v:109585$4245 + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec58_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec58_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec58_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec58_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec58_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec58_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec58_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec58_upd + attribute \src "libresoc.v:117749.7-117749.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 2 \opcode_switch + attribute \src "libresoc.v:117749.7-117749.20" + process $proc$libresoc.v:117749$4456 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109986.3-110001.6" - process $proc$libresoc.v:109986$4239 + attribute \src "libresoc.v:118087.3-118102.6" + process $proc$libresoc.v:118087$4424 assign { } { } assign { } { } - assign { } { } - assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:109987.5-109987.29" + assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] + attribute \src "libresoc.v:118088.5-118088.29" switch \initial - attribute \src "libresoc.v:109987.9-109987.17" + attribute \src "libresoc.v:118088.9-118088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'00 assign { } { } - assign $1\reg_a[4:0] \ra + assign $1\dec58_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[13:0] 14'00000000000100 case - assign $1\reg_a[4:0] 5'00000 + assign $1\dec58_function_unit[13:0] 14'00000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec58_function_unit $0\dec58_function_unit[13:0] + end + attribute \src "libresoc.v:118103.3-118118.6" + process $proc$libresoc.v:118103$4425 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:118104.5-118104.29" + switch \initial + attribute \src "libresoc.v:118104.9-118104.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign $2\reg_a[4:0] \RS + assign $1\dec58_cr_in[2:0] 3'000 case - assign $2\reg_a[4:0] $1\reg_a[4:0] + assign $1\dec58_cr_in[2:0] 3'000 end sync always - update \reg_a $0\reg_a[4:0] + update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:110002.3-110017.6" - process $proc$libresoc.v:110002$4240 + attribute \src "libresoc.v:118119.3-118134.6" + process $proc$libresoc.v:118119$4426 assign { } { } assign { } { } - assign { } { } - assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:110003.5-110003.29" + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:118120.5-118120.29" switch \initial - attribute \src "libresoc.v:110003.9-110003.17" + attribute \src "libresoc.v:118120.9-118120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'00 assign { } { } - assign $1\reg_a_ok[0:0] 1'1 + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 case - assign $1\reg_a_ok[0:0] 1'0 + assign $1\dec58_cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + attribute \src "libresoc.v:118135.3-118150.6" + process $proc$libresoc.v:118135$4427 + assign { } { } + assign { } { } + assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] + attribute \src "libresoc.v:118136.5-118136.29" + switch \initial + attribute \src "libresoc.v:118136.9-118136.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 assign { } { } - assign $2\reg_a_ok[0:0] 1'1 + assign $1\dec58_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_in1[2:0] 3'010 case - assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] + assign $1\dec58_sv_in1[2:0] 3'000 end sync always - update \reg_a_ok $0\reg_a_ok[0:0] + update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end - attribute \src "libresoc.v:110018.3-110053.6" - process $proc$libresoc.v:110018$4241 + attribute \src "libresoc.v:118151.3-118166.6" + process $proc$libresoc.v:118151$4428 assign { } { } assign { } { } + assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] + attribute \src "libresoc.v:118152.5-118152.29" + switch \initial + attribute \src "libresoc.v:118152.9-118152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + case + assign $1\dec58_sv_in2[2:0] 3'000 + end + sync always + update \dec58_sv_in2 $0\dec58_sv_in2[2:0] + end + attribute \src "libresoc.v:118167.3-118182.6" + process $proc$libresoc.v:118167$4429 assign { } { } assign { } { } - assign $0\fast_a[2:0] $1\fast_a[2:0] - assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:110019.5-110019.29" + assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] + attribute \src "libresoc.v:118168.5-118168.29" switch \initial - attribute \src "libresoc.v:110019.9-110019.17" + attribute \src "libresoc.v:118168.9-118168.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 + case 2'00 assign { } { } + assign $1\dec58_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 assign { } { } - assign $1\fast_a[2:0] $2\fast_a[2:0] - assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $2\fast_a[2:0] 3'000 - assign $2\fast_a_ok[0:0] 1'1 - case - assign $2\fast_a[2:0] 3'000 - assign $2\fast_a_ok[0:0] 1'0 - end + assign $1\dec58_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 + case 2'10 assign { } { } + assign $1\dec58_sv_in3[2:0] 3'000 + case + assign $1\dec58_sv_in3[2:0] 3'000 + end + sync always + update \dec58_sv_in3 $0\dec58_sv_in3[2:0] + end + attribute \src "libresoc.v:118183.3-118198.6" + process $proc$libresoc.v:118183$4430 + assign { } { } + assign { } { } + assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] + attribute \src "libresoc.v:118184.5-118184.29" + switch \initial + attribute \src "libresoc.v:118184.9-118184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 assign { } { } - assign $1\fast_a[2:0] $3\fast_a[2:0] - assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $3\fast_a[2:0] 3'000 - assign $3\fast_a_ok[0:0] 1'1 - case - assign $3\fast_a[2:0] 3'000 - assign $3\fast_a_ok[0:0] 1'0 - end + assign $1\dec58_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 2'01 assign { } { } + assign $1\dec58_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + assign $1\dec58_sv_out[2:0] 3'001 case - assign $1\fast_a[2:0] 3'000 - assign $1\fast_a_ok[0:0] 1'0 + assign $1\dec58_sv_out[2:0] 3'000 end sync always - update \fast_a $0\fast_a[2:0] - update \fast_a_ok $0\fast_a_ok[0:0] + update \dec58_sv_out $0\dec58_sv_out[2:0] end - attribute \src "libresoc.v:110054.3-110064.6" - process $proc$libresoc.v:110054$4242 + attribute \src "libresoc.v:118199.3-118214.6" + process $proc$libresoc.v:118199$4431 assign { } { } assign { } { } - assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:110055.5-110055.29" + assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:118200.5-118200.29" switch \initial - attribute \src "libresoc.v:110055.9-110055.17" + attribute \src "libresoc.v:118200.9-118200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 2'00 assign { } { } - assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + assign $1\dec58_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_cr_in[2:0] 3'000 case - assign $1\spr[9:0] 10'0000000000 + assign $1\dec58_sv_cr_in[2:0] 3'000 end sync always - update \spr $0\spr[9:0] + update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end - attribute \src "libresoc.v:110065.3-110075.6" - process $proc$libresoc.v:110065$4243 + attribute \src "libresoc.v:118215.3-118230.6" + process $proc$libresoc.v:118215$4432 assign { } { } assign { } { } - assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:110066.5-110066.29" + assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:118216.5-118216.29" switch \initial - attribute \src "libresoc.v:110066.9-110066.17" + attribute \src "libresoc.v:118216.9-118216.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 2'00 assign { } { } - assign $1\sprmap_spr_i[9:0] \spr + assign $1\dec58_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_cr_out[2:0] 3'000 case - assign $1\sprmap_spr_i[9:0] 10'0000000000 + assign $1\dec58_sv_cr_out[2:0] 3'000 end sync always - update \sprmap_spr_i $0\sprmap_spr_i[9:0] + update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end - attribute \src "libresoc.v:110076.3-110087.6" - process $proc$libresoc.v:110076$4244 + attribute \src "libresoc.v:118231.3-118246.6" + process $proc$libresoc.v:118231$4433 assign { } { } assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:118232.5-118232.29" + switch \initial + attribute \src "libresoc.v:118232.9-118232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:118247.3-118262.6" + process $proc$libresoc.v:118247$4434 assign { } { } assign { } { } - assign $0\spr_a[9:0] $1\spr_a[9:0] - assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:110077.5-110077.29" + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:118248.5-118248.29" switch \initial - attribute \src "libresoc.v:110077.9-110077.17" + attribute \src "libresoc.v:118248.9-118248.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 2'00 assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 assign { } { } - assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 case - assign $1\spr_a[9:0] 10'0000000000 - assign $1\spr_a_ok[0:0] 1'0 + assign $1\dec58_upd[1:0] 2'00 end sync always - update \spr_a $0\spr_a[9:0] - update \spr_a_ok $0\spr_a_ok[0:0] - end - connect \$9 $or$libresoc.v:109964$4224_Y - connect \$11 $eq$libresoc.v:109965$4225_Y - connect \$13 $eq$libresoc.v:109966$4226_Y - connect \$15 $eq$libresoc.v:109967$4227_Y - connect \$17 $ne$libresoc.v:109968$4228_Y - connect \$1 $eq$libresoc.v:109969$4229_Y - connect \$19 $and$libresoc.v:109970$4230_Y - connect \$21 $or$libresoc.v:109971$4231_Y - connect \$23 $eq$libresoc.v:109972$4232_Y - connect \$25 $not$libresoc.v:109973$4233_Y - connect \$27 $not$libresoc.v:109974$4234_Y - connect \$29 $and$libresoc.v:109975$4235_Y - connect \$3 $eq$libresoc.v:109976$4236_Y - connect \$5 $ne$libresoc.v:109977$4237_Y - connect \$7 $and$libresoc.v:109978$4238_Y - connect \ra \RA -end -attribute \src "libresoc.v:110093.1-110130.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" -attribute \generator "nMigen" -module \dec_ai - attribute \src "libresoc.v:110119.3-110128.6" - wire $0\immz_out[0:0] - attribute \src "libresoc.v:110094.7-110094.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:110119.3-110128.6" - wire $1\immz_out[0:0] - attribute \src "libresoc.v:110118.17-110118.107" - wire $and$libresoc.v:110118$4248_Y - attribute \src "libresoc.v:110116.17-110116.111" - wire $eq$libresoc.v:110116$4246_Y - attribute \src "libresoc.v:110117.17-110117.108" - wire $eq$libresoc.v:110117$4247_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 2 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire output 1 \immz_out - attribute \src "libresoc.v:110094.7-110094.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" - wire width 5 \ra - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $and $and$libresoc.v:110118$4248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $and$libresoc.v:110118$4248_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $eq $eq$libresoc.v:110116$4246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:110116$4246_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $eq $eq$libresoc.v:110117$4247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $eq$libresoc.v:110117$4247_Y + update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:110094.7-110094.20" - process $proc$libresoc.v:110094$4250 + attribute \src "libresoc.v:118263.3-118278.6" + process $proc$libresoc.v:118263$4435 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:118264.5-118264.29" + switch \initial + attribute \src "libresoc.v:118264.9-118264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:110119.3-110128.6" - process $proc$libresoc.v:110119$4249 + attribute \src "libresoc.v:118279.3-118294.6" + process $proc$libresoc.v:118279$4436 assign { } { } assign { } { } - assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:110120.5-110120.29" + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:118280.5-118280.29" switch \initial - attribute \src "libresoc.v:110120.9-110120.17" + attribute \src "libresoc.v:118280.9-118280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "libresoc.v:118295.3-118310.6" + process $proc$libresoc.v:118295$4437 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:118296.5-118296.29" + switch \initial + attribute \src "libresoc.v:118296.9-118296.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 assign { } { } - assign $1\immz_out[0:0] 1'1 + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 case - assign $1\immz_out[0:0] 1'0 + assign $1\dec58_cry_in[1:0] 2'00 end sync always - update \immz_out $0\immz_out[0:0] + update \dec58_cry_in $0\dec58_cry_in[1:0] end - connect \$1 $eq$libresoc.v:110116$4246_Y - connect \$3 $eq$libresoc.v:110117$4247_Y - connect \$5 $and$libresoc.v:110118$4248_Y - connect \ra \ALU_RA -end -attribute \src "libresoc.v:110134.1-110171.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" -attribute \generator "nMigen" -module \dec_ai$162 - attribute \src "libresoc.v:110160.3-110169.6" - wire $0\immz_out[0:0] - attribute \src "libresoc.v:110135.7-110135.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:110160.3-110169.6" - wire $1\immz_out[0:0] - attribute \src "libresoc.v:110159.17-110159.107" - wire $and$libresoc.v:110159$4253_Y - attribute \src "libresoc.v:110157.17-110157.111" - wire $eq$libresoc.v:110157$4251_Y - attribute \src "libresoc.v:110158.17-110158.108" - wire $eq$libresoc.v:110158$4252_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 2 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire output 1 \immz_out - attribute \src "libresoc.v:110135.7-110135.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" - wire width 5 \ra - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $and $and$libresoc.v:110159$4253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $and$libresoc.v:110159$4253_Y + attribute \src "libresoc.v:118311.3-118326.6" + process $proc$libresoc.v:118311$4438 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:118312.5-118312.29" + switch \initial + attribute \src "libresoc.v:118312.9-118312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $eq $eq$libresoc.v:110157$4251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:110157$4251_Y + attribute \src "libresoc.v:118327.3-118342.6" + process $proc$libresoc.v:118327$4439 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:118328.5-118328.29" + switch \initial + attribute \src "libresoc.v:118328.9-118328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $eq $eq$libresoc.v:110158$4252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $eq$libresoc.v:110158$4252_Y + attribute \src "libresoc.v:118343.3-118358.6" + process $proc$libresoc.v:118343$4440 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:118344.5-118344.29" + switch \initial + attribute \src "libresoc.v:118344.9-118344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:110135.7-110135.20" - process $proc$libresoc.v:110135$4255 + attribute \src "libresoc.v:118359.3-118374.6" + process $proc$libresoc.v:118359$4441 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:118360.5-118360.29" + switch \initial + attribute \src "libresoc.v:118360.9-118360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:110160.3-110169.6" - process $proc$libresoc.v:110160$4254 + attribute \src "libresoc.v:118375.3-118390.6" + process $proc$libresoc.v:118375$4442 assign { } { } assign { } { } - assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:110161.5-110161.29" + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:118376.5-118376.29" switch \initial - attribute \src "libresoc.v:110161.9-110161.17" + attribute \src "libresoc.v:118376.9-118376.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "libresoc.v:118391.3-118406.6" + process $proc$libresoc.v:118391$4443 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:118392.5-118392.29" + switch \initial + attribute \src "libresoc.v:118392.9-118392.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 assign { } { } - assign $1\immz_out[0:0] 1'1 + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 case - assign $1\immz_out[0:0] 1'0 + assign $1\dec58_sgn_ext[0:0] 1'0 end sync always - update \immz_out $0\immz_out[0:0] + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - connect \$1 $eq$libresoc.v:110157$4251_Y - connect \$3 $eq$libresoc.v:110158$4252_Y - connect \$5 $and$libresoc.v:110159$4253_Y - connect \ra \LOGICAL_RA -end -attribute \src "libresoc.v:110175.1-110212.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" -attribute \generator "nMigen" -module \dec_ai$178 - attribute \src "libresoc.v:110201.3-110210.6" - wire $0\immz_out[0:0] - attribute \src "libresoc.v:110176.7-110176.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:110201.3-110210.6" - wire $1\immz_out[0:0] - attribute \src "libresoc.v:110200.17-110200.107" - wire $and$libresoc.v:110200$4258_Y - attribute \src "libresoc.v:110198.17-110198.111" - wire $eq$libresoc.v:110198$4256_Y - attribute \src "libresoc.v:110199.17-110199.108" - wire $eq$libresoc.v:110199$4257_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 2 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire output 1 \immz_out - attribute \src "libresoc.v:110176.7-110176.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" - wire width 5 \ra - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $and $and$libresoc.v:110200$4258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $and$libresoc.v:110200$4258_Y + attribute \src "libresoc.v:118407.3-118422.6" + process $proc$libresoc.v:118407$4444 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:118408.5-118408.29" + switch \initial + attribute \src "libresoc.v:118408.9-118408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $eq $eq$libresoc.v:110198$4256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:110198$4256_Y + attribute \src "libresoc.v:118423.3-118438.6" + process $proc$libresoc.v:118423$4445 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:118424.5-118424.29" + switch \initial + attribute \src "libresoc.v:118424.9-118424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $eq $eq$libresoc.v:110199$4257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $eq$libresoc.v:110199$4257_Y + attribute \src "libresoc.v:118439.3-118454.6" + process $proc$libresoc.v:118439$4446 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:118440.5-118440.29" + switch \initial + attribute \src "libresoc.v:118440.9-118440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:110176.7-110176.20" - process $proc$libresoc.v:110176$4260 + attribute \src "libresoc.v:118455.3-118470.6" + process $proc$libresoc.v:118455$4447 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:118456.5-118456.29" + switch \initial + attribute \src "libresoc.v:118456.9-118456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:110201.3-110210.6" - process $proc$libresoc.v:110201$4259 + attribute \src "libresoc.v:118471.3-118486.6" + process $proc$libresoc.v:118471$4448 assign { } { } assign { } { } - assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:110202.5-110202.29" + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:118472.5-118472.29" switch \initial - attribute \src "libresoc.v:110202.9-110202.17" + attribute \src "libresoc.v:118472.9-118472.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "libresoc.v:118487.3-118502.6" + process $proc$libresoc.v:118487$4449 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:118488.5-118488.29" + switch \initial + attribute \src "libresoc.v:118488.9-118488.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 assign { } { } - assign $1\immz_out[0:0] 1'1 + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 case - assign $1\immz_out[0:0] 1'0 + assign $1\dec58_sgl_pipe[0:0] 1'0 end sync always - update \immz_out $0\immz_out[0:0] + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - connect \$1 $eq$libresoc.v:110198$4256_Y - connect \$3 $eq$libresoc.v:110199$4257_Y - connect \$5 $and$libresoc.v:110200$4258_Y - connect \ra \DIV_RA -end -attribute \src "libresoc.v:110216.1-110253.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" -attribute \generator "nMigen" -module \dec_ai$203 - attribute \src "libresoc.v:110242.3-110251.6" - wire $0\immz_out[0:0] - attribute \src "libresoc.v:110217.7-110217.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:110242.3-110251.6" - wire $1\immz_out[0:0] - attribute \src "libresoc.v:110241.17-110241.107" - wire $and$libresoc.v:110241$4263_Y - attribute \src "libresoc.v:110239.17-110239.111" - wire $eq$libresoc.v:110239$4261_Y - attribute \src "libresoc.v:110240.17-110240.108" - wire $eq$libresoc.v:110240$4262_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 2 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire output 1 \immz_out - attribute \src "libresoc.v:110217.7-110217.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" - wire width 5 \ra - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $and $and$libresoc.v:110241$4263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $and$libresoc.v:110241$4263_Y + attribute \src "libresoc.v:118503.3-118518.6" + process $proc$libresoc.v:118503$4450 + assign { } { } + assign { } { } + assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:118504.5-118504.29" + switch \initial + attribute \src "libresoc.v:118504.9-118504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'10 + case + assign $1\dec58_SV_Etype[1:0] 2'00 + end + sync always + update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $eq $eq$libresoc.v:110239$4261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:110239$4261_Y + attribute \src "libresoc.v:118519.3-118534.6" + process $proc$libresoc.v:118519$4451 + assign { } { } + assign { } { } + assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:118520.5-118520.29" + switch \initial + attribute \src "libresoc.v:118520.9-118520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + case + assign $1\dec58_SV_Ptype[1:0] 2'00 + end + sync always + update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - cell $eq $eq$libresoc.v:110240$4262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $eq$libresoc.v:110240$4262_Y + attribute \src "libresoc.v:118535.3-118550.6" + process $proc$libresoc.v:118535$4452 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:118536.5-118536.29" + switch \initial + attribute \src "libresoc.v:118536.9-118536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:110217.7-110217.20" - process $proc$libresoc.v:110217$4265 + attribute \src "libresoc.v:118551.3-118566.6" + process $proc$libresoc.v:118551$4453 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:118552.5-118552.29" + switch \initial + attribute \src "libresoc.v:118552.9-118552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:110242.3-110251.6" - process $proc$libresoc.v:110242$4264 + attribute \src "libresoc.v:118567.3-118582.6" + process $proc$libresoc.v:118567$4454 assign { } { } assign { } { } - assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:110243.5-110243.29" + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:118568.5-118568.29" switch \initial - attribute \src "libresoc.v:110243.9-110243.17" + attribute \src "libresoc.v:118568.9-118568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "libresoc.v:118583.3-118598.6" + process $proc$libresoc.v:118583$4455 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] + attribute \src "libresoc.v:118584.5-118584.29" + switch \initial + attribute \src "libresoc.v:118584.9-118584.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 assign { } { } - assign $1\immz_out[0:0] 1'1 + assign $1\dec58_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[2:0] 3'001 case - assign $1\immz_out[0:0] 1'0 + assign $1\dec58_out_sel[2:0] 3'000 end sync always - update \immz_out $0\immz_out[0:0] + update \dec58_out_sel $0\dec58_out_sel[2:0] end - connect \$1 $eq$libresoc.v:110239$4261_Y - connect \$3 $eq$libresoc.v:110240$4262_Y - connect \$5 $and$libresoc.v:110241$4263_Y - connect \ra \LDST_RA + connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:110257.1-110448.10" +attribute \src "libresoc.v:118604.1-119360.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" -module \dec_b - attribute \src "libresoc.v:110412.3-110429.6" - wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:110430.3-110447.6" - wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:110258.7-110258.20" +module \dec62 + attribute \src "libresoc.v:119281.3-119293.6" + wire width 2 $0\dec62_SV_Etype[1:0] + attribute \src "libresoc.v:119294.3-119306.6" + wire width 2 $0\dec62_SV_Ptype[1:0] + attribute \src "libresoc.v:119125.3-119137.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:119177.3-119189.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:118956.3-118968.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:118969.3-118981.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:119112.3-119124.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:119164.3-119176.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:119229.3-119241.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:118943.3-118955.6" + wire width 14 $0\dec62_function_unit[13:0] + attribute \src "libresoc.v:119307.3-119319.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:119320.3-119332.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:119333.3-119345.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:119086.3-119098.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:119138.3-119150.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:119151.3-119163.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:119216.3-119228.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:119060.3-119072.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:119255.3-119267.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:119346.3-119358.6" + wire width 3 $0\dec62_out_sel[2:0] + attribute \src "libresoc.v:119099.3-119111.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:119203.3-119215.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:119268.3-119280.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:119242.3-119254.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:119190.3-119202.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:119034.3-119046.6" + wire width 3 $0\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:119047.3-119059.6" + wire width 3 $0\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:118982.3-118994.6" + wire width 3 $0\dec62_sv_in1[2:0] + attribute \src "libresoc.v:118995.3-119007.6" + wire width 3 $0\dec62_sv_in2[2:0] + attribute \src "libresoc.v:119008.3-119020.6" + wire width 3 $0\dec62_sv_in3[2:0] + attribute \src "libresoc.v:119021.3-119033.6" + wire width 3 $0\dec62_sv_out[2:0] + attribute \src "libresoc.v:119073.3-119085.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:118605.7-118605.20" wire $0\initial[0:0] - attribute \src "libresoc.v:110382.3-110396.6" - wire width 5 $0\reg_b[4:0] - attribute \src "libresoc.v:110397.3-110411.6" - wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:110412.3-110429.6" - wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:110430.3-110447.6" - wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:110382.3-110396.6" - wire width 5 $1\reg_b[4:0] - attribute \src "libresoc.v:110397.3-110411.6" - wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:110412.3-110429.6" - wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:110430.3-110447.6" - wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:110378.17-110378.117" - wire $eq$libresoc.v:110378$4266_Y - attribute \src "libresoc.v:110380.17-110380.117" - wire $eq$libresoc.v:110380$4268_Y - attribute \src "libresoc.v:110379.17-110379.107" - wire $not$libresoc.v:110379$4267_Y - attribute \src "libresoc.v:110381.17-110381.107" - wire $not$libresoc.v:110381$4269_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 6 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 input 8 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 4 \fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \fast_b_ok - attribute \src "libresoc.v:110258.7-110258.15" - wire \initial + attribute \src "libresoc.v:119281.3-119293.6" + wire width 2 $1\dec62_SV_Etype[1:0] + attribute \src "libresoc.v:119294.3-119306.6" + wire width 2 $1\dec62_SV_Ptype[1:0] + attribute \src "libresoc.v:119125.3-119137.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:119177.3-119189.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:118956.3-118968.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:118969.3-118981.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:119112.3-119124.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:119164.3-119176.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:119229.3-119241.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:118943.3-118955.6" + wire width 14 $1\dec62_function_unit[13:0] + attribute \src "libresoc.v:119307.3-119319.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:119320.3-119332.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:119333.3-119345.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:119086.3-119098.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:119138.3-119150.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:119151.3-119163.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:119216.3-119228.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:119060.3-119072.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:119255.3-119267.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:119346.3-119358.6" + wire width 3 $1\dec62_out_sel[2:0] + attribute \src "libresoc.v:119099.3-119111.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:119203.3-119215.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:119268.3-119280.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:119242.3-119254.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:119190.3-119202.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:119034.3-119046.6" + wire width 3 $1\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:119047.3-119059.6" + wire width 3 $1\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:118982.3-118994.6" + wire width 3 $1\dec62_sv_in1[2:0] + attribute \src "libresoc.v:118995.3-119007.6" + wire width 3 $1\dec62_sv_in2[2:0] + attribute \src "libresoc.v:119008.3-119020.6" + wire width 3 $1\dec62_sv_in3[2:0] + attribute \src "libresoc.v:119021.3-119033.6" + wire width 3 $1\dec62_sv_out[2:0] + attribute \src "libresoc.v:119073.3-119085.6" + wire width 2 $1\dec62_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec62_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec62_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -171519,1945 +184991,1431 @@ module \dec_b attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 9 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 2 \reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \reg_b_ok - attribute \enum_base_type "In2Sel" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec62_is_32b + attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178" - wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $eq $eq$libresoc.v:110378$4266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $eq$libresoc.v:110378$4266_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $eq $eq$libresoc.v:110380$4268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $eq$libresoc.v:110380$4268_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - cell $not $not$libresoc.v:110379$4267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $not$libresoc.v:110379$4267_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - cell $not $not$libresoc.v:110381$4269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $not$libresoc.v:110381$4269_Y - end - attribute \src "libresoc.v:110258.7-110258.20" - process $proc$libresoc.v:110258$4274 + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec62_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec62_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec62_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec62_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec62_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec62_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec62_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec62_upd + attribute \src "libresoc.v:118605.7-118605.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 2 \opcode_switch + attribute \src "libresoc.v:118605.7-118605.20" + process $proc$libresoc.v:118605$4489 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110382.3-110396.6" - process $proc$libresoc.v:110382$4270 + attribute \src "libresoc.v:118943.3-118955.6" + process $proc$libresoc.v:118943$4457 assign { } { } assign { } { } - assign $0\reg_b[4:0] $1\reg_b[4:0] - attribute \src "libresoc.v:110383.5-110383.29" + assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] + attribute \src "libresoc.v:118944.5-118944.29" switch \initial - attribute \src "libresoc.v:110383.9-110383.17" + attribute \src "libresoc.v:118944.9-118944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 2'00 assign { } { } - assign $1\reg_b[4:0] \RB + assign $1\dec62_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" - case 4'1101 + case 2'01 assign { } { } - assign $1\reg_b[4:0] \RS + assign $1\dec62_function_unit[13:0] 14'00000000000100 case - assign $1\reg_b[4:0] 5'00000 + assign $1\dec62_function_unit[13:0] 14'00000000000000 end sync always - update \reg_b $0\reg_b[4:0] + update \dec62_function_unit $0\dec62_function_unit[13:0] end - attribute \src "libresoc.v:110397.3-110411.6" - process $proc$libresoc.v:110397$4271 + attribute \src "libresoc.v:118956.3-118968.6" + process $proc$libresoc.v:118956$4458 assign { } { } assign { } { } - assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:110398.5-110398.29" + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:118957.5-118957.29" switch \initial - attribute \src "libresoc.v:110398.9-110398.17" + attribute \src "libresoc.v:118957.9-118957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 2'00 assign { } { } - assign $1\reg_b_ok[0:0] 1'1 + assign $1\dec62_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'1101 + case 2'01 assign { } { } - assign $1\reg_b_ok[0:0] 1'1 + assign $1\dec62_cr_in[2:0] 3'000 case - assign $1\reg_b_ok[0:0] 1'0 + assign $1\dec62_cr_in[2:0] 3'000 end sync always - update \reg_b_ok $0\reg_b_ok[0:0] + update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:110412.3-110429.6" - process $proc$libresoc.v:110412$4272 + attribute \src "libresoc.v:118969.3-118981.6" + process $proc$libresoc.v:118969$4459 assign { } { } assign { } { } - assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:110413.5-110413.29" + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:118970.5-118970.29" switch \initial - attribute \src "libresoc.v:110413.9-110413.17" + attribute \src "libresoc.v:118970.9-118970.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'00 assign { } { } - assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - switch { \XL_XO [5] \$3 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\fast_b[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\fast_b[2:0] 3'010 - case - assign $2\fast_b[2:0] 3'000 - end - case - assign $1\fast_b[2:0] 3'000 - end - sync always - update \fast_b $0\fast_b[2:0] - end - attribute \src "libresoc.v:110430.3-110447.6" - process $proc$libresoc.v:110430$4273 - assign { } { } - assign { } { } - assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:110431.5-110431.29" - switch \initial - attribute \src "libresoc.v:110431.9-110431.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch \$5 + assign $1\dec62_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 assign { } { } - assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - switch { \XL_XO [5] \$7 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\fast_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\fast_b_ok[0:0] 1'1 - case - assign $2\fast_b_ok[0:0] 1'0 - end + assign $1\dec62_cr_out[2:0] 3'000 case - assign $1\fast_b_ok[0:0] 1'0 + assign $1\dec62_cr_out[2:0] 3'000 end sync always - update \fast_b_ok $0\fast_b_ok[0:0] - end - connect \$1 $eq$libresoc.v:110378$4266_Y - connect \$3 $not$libresoc.v:110379$4267_Y - connect \$5 $eq$libresoc.v:110380$4268_Y - connect \$7 $not$libresoc.v:110381$4269_Y -end -attribute \src "libresoc.v:110452.1-110705.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" -attribute \generator "nMigen" -module \dec_bi - attribute \src "libresoc.v:110679.3-110689.6" - wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:110690.3-110700.6" - wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:110541.3-110587.6" - wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:110588.3-110634.6" - wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:110453.7-110453.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:110668.3-110678.6" - wire width 26 $0\li[25:0] - attribute \src "libresoc.v:110635.3-110645.6" - wire width 16 $0\si[15:0] - attribute \src "libresoc.v:110646.3-110656.6" - wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:110657.3-110667.6" - wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:110679.3-110689.6" - wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:110690.3-110700.6" - wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:110541.3-110587.6" - wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:110588.3-110634.6" - wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110668.3-110678.6" - wire width 26 $1\li[25:0] - attribute \src "libresoc.v:110635.3-110645.6" - wire width 16 $1\si[15:0] - attribute \src "libresoc.v:110646.3-110656.6" - wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:110657.3-110667.6" - wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:110531.17-110531.104" - wire width 64 $extend$libresoc.v:110531$4275_Y - attribute \src "libresoc.v:110532.18-110532.107" - wire width 64 $extend$libresoc.v:110532$4277_Y - attribute \src "libresoc.v:110535.17-110535.104" - wire width 64 $extend$libresoc.v:110535$4281_Y - attribute \src "libresoc.v:110539.17-110539.102" - wire width 64 $extend$libresoc.v:110539$4286_Y - attribute \src "libresoc.v:110531.17-110531.104" - wire width 64 $pos$libresoc.v:110531$4276_Y - attribute \src "libresoc.v:110532.18-110532.107" - wire width 64 $pos$libresoc.v:110532$4278_Y - attribute \src "libresoc.v:110535.17-110535.104" - wire width 64 $pos$libresoc.v:110535$4282_Y - attribute \src "libresoc.v:110539.17-110539.102" - wire width 64 $pos$libresoc.v:110539$4287_Y - attribute \src "libresoc.v:110533.18-110533.114" - wire width 47 $sshl$libresoc.v:110533$4279_Y - attribute \src "libresoc.v:110534.18-110534.113" - wire width 27 $sshl$libresoc.v:110534$4280_Y - attribute \src "libresoc.v:110536.18-110536.113" - wire width 17 $sshl$libresoc.v:110536$4283_Y - attribute \src "libresoc.v:110537.18-110537.113" - wire width 17 $sshl$libresoc.v:110537$4284_Y - attribute \src "libresoc.v:110538.17-110538.109" - wire width 47 $sshl$libresoc.v:110538$4285_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 8 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 9 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 input 7 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 3 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 4 \ALU_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:110453.7-110453.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:110531$4275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \ALU_sh - connect \Y $extend$libresoc.v:110531$4275_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:110532$4277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:110532$4277_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:110535$4281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \ALU_UI - connect \Y $extend$libresoc.v:110535$4281_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:110539$4286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:110539$4286_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:110531$4276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110531$4275_Y - connect \Y $pos$libresoc.v:110531$4276_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:110532$4278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110532$4277_Y - connect \Y $pos$libresoc.v:110532$4278_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:110535$4282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110535$4281_Y - connect \Y $pos$libresoc.v:110535$4282_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:110539$4287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110539$4286_Y - connect \Y $pos$libresoc.v:110539$4287_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:110533$4279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ALU_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:110533$4279_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:110534$4280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \ALU_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:110534$4280_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:110536$4283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \ALU_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:110536$4283_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:110537$4284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \ALU_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:110537$4284_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:110538$4285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:110538$4285_Y - end - attribute \src "libresoc.v:110453.7-110453.20" - process $proc$libresoc.v:110453$4296 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \dec62_cr_out $0\dec62_cr_out[2:0] end - attribute \src "libresoc.v:110541.3-110587.6" - process $proc$libresoc.v:110541$4288 + attribute \src "libresoc.v:118982.3-118994.6" + process $proc$libresoc.v:118982$4460 assign { } { } assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:110542.5-110542.29" + assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] + attribute \src "libresoc.v:118983.5-118983.29" switch \initial - attribute \src "libresoc.v:110542.9-110542.17" + attribute \src "libresoc.v:118983.9-118983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1010 + case 2'00 assign { } { } - assign $1\imm_b[63:0] \$9 + assign $1\dec62_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 4'1011 + case 2'01 assign { } { } - assign $1\imm_b[63:0] \$11 + assign $1\dec62_sv_in1[2:0] 3'011 case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec62_sv_in1[2:0] 3'000 end sync always - update \imm_b $0\imm_b[63:0] + update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end - attribute \src "libresoc.v:110588.3-110634.6" - process $proc$libresoc.v:110588$4289 + attribute \src "libresoc.v:118995.3-119007.6" + process $proc$libresoc.v:118995$4461 assign { } { } assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110589.5-110589.29" + assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] + attribute \src "libresoc.v:118996.5-118996.29" switch \initial - attribute \src "libresoc.v:110589.9-110589.17" + attribute \src "libresoc.v:118996.9-118996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1010 + case 2'00 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'1011 + case 2'01 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_sv_in2[2:0] 3'000 case - assign $1\imm_b_ok[0:0] 1'0 + assign $1\dec62_sv_in2[2:0] 3'000 end sync always - update \imm_b_ok $0\imm_b_ok[0:0] + update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end - attribute \src "libresoc.v:110635.3-110645.6" - process $proc$libresoc.v:110635$4290 + attribute \src "libresoc.v:119008.3-119020.6" + process $proc$libresoc.v:119008$4462 assign { } { } assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:110636.5-110636.29" + assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] + attribute \src "libresoc.v:119009.5-119009.29" switch \initial - attribute \src "libresoc.v:110636.9-110636.17" + attribute \src "libresoc.v:119009.9-119009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 2'00 assign { } { } - assign $1\si[15:0] \ALU_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "libresoc.v:110646.3-110656.6" - process $proc$libresoc.v:110646$4291 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:110647.5-110647.29" - switch \initial - attribute \src "libresoc.v:110647.9-110647.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\dec62_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 2'01 assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] + assign $1\dec62_sv_in3[2:0] 3'010 case - assign $1\si_hi[31:0] 0 + assign $1\dec62_sv_in3[2:0] 3'000 end sync always - update \si_hi $0\si_hi[31:0] + update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end - attribute \src "libresoc.v:110657.3-110667.6" - process $proc$libresoc.v:110657$4292 + attribute \src "libresoc.v:119021.3-119033.6" + process $proc$libresoc.v:119021$4463 assign { } { } assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:110658.5-110658.29" + assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] + attribute \src "libresoc.v:119022.5-119022.29" switch \initial - attribute \src "libresoc.v:110658.9-110658.17" + attribute \src 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[25:0] + assign $1\dec62_sv_out[2:0] 3'000 case - assign $1\li[25:0] 26'00000000000000000000000000 + assign $1\dec62_sv_out[2:0] 3'000 end sync always - update \li $0\li[25:0] + update \dec62_sv_out $0\dec62_sv_out[2:0] end - attribute \src "libresoc.v:110679.3-110689.6" - process $proc$libresoc.v:110679$4294 + attribute \src "libresoc.v:119034.3-119046.6" + process $proc$libresoc.v:119034$4464 assign { } { } assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:110680.5-110680.29" + assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:119035.5-119035.29" switch \initial - attribute \src "libresoc.v:110680.9-110680.17" + attribute \src "libresoc.v:119035.9-119035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 2'00 assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "libresoc.v:110690.3-110700.6" - process $proc$libresoc.v:110690$4295 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:110691.5-110691.29" - switch \initial - attribute \src "libresoc.v:110691.9-110691.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\dec62_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 2'01 assign { } { } - assign $1\ds[15:0] \$22 [15:0] + assign $1\dec62_sv_cr_in[2:0] 3'000 case - assign $1\ds[15:0] 16'0000000000000000 + assign $1\dec62_sv_cr_in[2:0] 3'000 end sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$libresoc.v:110531$4276_Y - connect \$11 $pos$libresoc.v:110532$4278_Y - connect \$14 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:110792$4304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110792$4303_Y - connect \Y $pos$libresoc.v:110792$4304_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:110796$4309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110796$4308_Y - connect \Y $pos$libresoc.v:110796$4309_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:110790$4301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \BRANCH_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:110790$4301_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:110791$4302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \BRANCH_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:110791$4302_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:110793$4305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \BRANCH_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:110793$4305_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:110794$4306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \BRANCH_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:110794$4306_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:110795$4307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:110795$4307_Y - end - attribute \src "libresoc.v:110710.7-110710.20" - process $proc$libresoc.v:110710$4318 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end - attribute \src "libresoc.v:110798.3-110844.6" - process $proc$libresoc.v:110798$4310 + attribute \src "libresoc.v:119047.3-119059.6" + process $proc$libresoc.v:119047$4465 assign { } { } assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:110799.5-110799.29" + assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:119048.5-119048.29" switch \initial - attribute \src "libresoc.v:110799.9-110799.17" + attribute \src "libresoc.v:119048.9-119048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1010 + case 2'00 assign { } { } - assign $1\imm_b[63:0] \$9 + assign $1\dec62_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'1011 + case 2'01 assign { } { } - assign $1\imm_b[63:0] \$11 + assign $1\dec62_sv_cr_out[2:0] 3'000 case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec62_sv_cr_out[2:0] 3'000 end sync always - update \imm_b $0\imm_b[63:0] + update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end - attribute \src "libresoc.v:110845.3-110891.6" - process $proc$libresoc.v:110845$4311 + attribute \src "libresoc.v:119060.3-119072.6" + process $proc$libresoc.v:119060$4466 assign { } { } assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110846.5-110846.29" + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:119061.5-119061.29" switch \initial - attribute \src "libresoc.v:110846.9-110846.17" + attribute \src "libresoc.v:119061.9-119061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1010 + case 2'00 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 4'1011 + case 2'01 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_ldst_len[3:0] 4'1000 case - assign $1\imm_b_ok[0:0] 1'0 + assign $1\dec62_ldst_len[3:0] 4'0000 end sync always - update \imm_b_ok $0\imm_b_ok[0:0] + update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:110892.3-110902.6" - process $proc$libresoc.v:110892$4312 + attribute \src "libresoc.v:119073.3-119085.6" + process $proc$libresoc.v:119073$4467 assign { } { } assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:110893.5-110893.29" + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:119074.5-119074.29" switch \initial - attribute \src "libresoc.v:110893.9-110893.17" + attribute \src "libresoc.v:119074.9-119074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 2'00 assign { } { } - assign $1\si[15:0] \BRANCH_SI + assign $1\dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 case - assign $1\si[15:0] 16'0000000000000000 + assign $1\dec62_upd[1:0] 2'00 end sync always - update \si $0\si[15:0] + update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:110903.3-110913.6" - process $proc$libresoc.v:110903$4313 + attribute \src "libresoc.v:119086.3-119098.6" + process $proc$libresoc.v:119086$4468 assign { } { } assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:110904.5-110904.29" + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:119087.5-119087.29" switch \initial - attribute \src "libresoc.v:110904.9-110904.17" + attribute \src "libresoc.v:119087.9-119087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 2'00 assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 case - assign $1\si_hi[31:0] 0 + assign $1\dec62_internal_op[6:0] 7'0000000 end sync always - update \si_hi $0\si_hi[31:0] + update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:110914.3-110924.6" - process $proc$libresoc.v:110914$4314 + attribute \src "libresoc.v:119099.3-119111.6" + process $proc$libresoc.v:119099$4469 assign { } { } assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:110915.5-110915.29" + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:119100.5-119100.29" switch \initial - attribute \src "libresoc.v:110915.9-110915.17" + attribute \src "libresoc.v:119100.9-119100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 2'00 assign { } { } - assign $1\ui[15:0] \BRANCH_UI + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 case - assign $1\ui[15:0] 16'0000000000000000 + assign $1\dec62_rc_sel[1:0] 2'00 end sync always - update \ui $0\ui[15:0] + update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:110925.3-110935.6" - process $proc$libresoc.v:110925$4315 + attribute \src "libresoc.v:119112.3-119124.6" + process $proc$libresoc.v:119112$4470 assign { } { } assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:110926.5-110926.29" + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:119113.5-119113.29" switch \initial - attribute \src "libresoc.v:110926.9-110926.17" + attribute \src "libresoc.v:119113.9-119113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 2'00 assign { } { } - assign $1\li[25:0] \$16 [25:0] + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 case - assign $1\li[25:0] 26'00000000000000000000000000 + assign $1\dec62_cry_in[1:0] 2'00 end sync always - update \li $0\li[25:0] + update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:110936.3-110946.6" - process $proc$libresoc.v:110936$4316 + attribute \src "libresoc.v:119125.3-119137.6" + process $proc$libresoc.v:119125$4471 assign { } { } assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:110937.5-110937.29" + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:119126.5-119126.29" switch \initial - attribute \src "libresoc.v:110937.9-110937.17" + attribute \src "libresoc.v:119126.9-119126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 2'00 assign { } { } - assign $1\bd[15:0] \$19 [15:0] + assign $1\dec62_asmcode[7:0] 8'10101101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10110000 case - assign $1\bd[15:0] 16'0000000000000000 + assign $1\dec62_asmcode[7:0] 8'00000000 end sync always - update \bd $0\bd[15:0] + update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:110947.3-110957.6" - process $proc$libresoc.v:110947$4317 + attribute \src "libresoc.v:119138.3-119150.6" + process $proc$libresoc.v:119138$4472 assign { } { } assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:110948.5-110948.29" + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:119139.5-119139.29" switch \initial - attribute \src "libresoc.v:110948.9-110948.17" + attribute \src "libresoc.v:119139.9-119139.17" case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$libresoc.v:110788$4298_Y - connect \$11 $pos$libresoc.v:110789$4300_Y - connect \$14 $sshl$libresoc.v:110790$4301_Y - connect \$17 $sshl$libresoc.v:110791$4302_Y - connect \$1 $pos$libresoc.v:110792$4304_Y - connect \$20 $sshl$libresoc.v:110793$4305_Y - connect \$23 $sshl$libresoc.v:110794$4306_Y - connect \$4 $sshl$libresoc.v:110795$4307_Y - connect \$3 $pos$libresoc.v:110796$4309_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "libresoc.v:110966.1-111219.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" -attribute \generator "nMigen" -module \dec_bi$163 - attribute \src "libresoc.v:111193.3-111203.6" - wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111204.3-111214.6" - wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:111055.3-111101.6" - wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:111102.3-111148.6" - wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:110967.7-110967.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:111182.3-111192.6" - wire width 26 $0\li[25:0] - attribute \src "libresoc.v:111149.3-111159.6" - wire width 16 $0\si[15:0] - attribute \src "libresoc.v:111160.3-111170.6" - wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:111171.3-111181.6" - wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:111193.3-111203.6" - wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:111204.3-111214.6" - wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:111055.3-111101.6" - wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:111102.3-111148.6" - wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111182.3-111192.6" - wire width 26 $1\li[25:0] - attribute \src "libresoc.v:111149.3-111159.6" - wire width 16 $1\si[15:0] - attribute \src "libresoc.v:111160.3-111170.6" - wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:111171.3-111181.6" - wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:111045.17-111045.108" - wire width 64 $extend$libresoc.v:111045$4319_Y - attribute \src "libresoc.v:111046.18-111046.111" - wire width 64 $extend$libresoc.v:111046$4321_Y - attribute \src "libresoc.v:111049.17-111049.108" - wire width 64 $extend$libresoc.v:111049$4325_Y - attribute \src "libresoc.v:111053.17-111053.102" - wire width 64 $extend$libresoc.v:111053$4330_Y - attribute \src "libresoc.v:111045.17-111045.108" - wire width 64 $pos$libresoc.v:111045$4320_Y - attribute \src "libresoc.v:111046.18-111046.111" - wire width 64 $pos$libresoc.v:111046$4322_Y - attribute \src "libresoc.v:111049.17-111049.108" - wire width 64 $pos$libresoc.v:111049$4326_Y - attribute \src "libresoc.v:111053.17-111053.102" - wire width 64 $pos$libresoc.v:111053$4331_Y - attribute \src "libresoc.v:111047.18-111047.118" - wire width 47 $sshl$libresoc.v:111047$4323_Y - attribute \src "libresoc.v:111048.18-111048.117" - wire width 27 $sshl$libresoc.v:111048$4324_Y - attribute \src "libresoc.v:111050.18-111050.117" - wire width 17 $sshl$libresoc.v:111050$4327_Y - attribute \src "libresoc.v:111051.18-111051.117" - wire width 17 $sshl$libresoc.v:111051$4328_Y - attribute \src "libresoc.v:111052.17-111052.109" - wire width 47 $sshl$libresoc.v:111052$4329_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 8 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 9 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 input 7 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 3 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 4 \LOGICAL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:110967.7-110967.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111045$4319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:111045$4319_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111046$4321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:111046$4321_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111049$4325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:111049$4325_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:111053$4330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:111053$4330_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111045$4320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111045$4319_Y - connect \Y $pos$libresoc.v:111045$4320_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111046$4322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111046$4321_Y - connect \Y $pos$libresoc.v:111046$4322_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111049$4326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111049$4325_Y - connect \Y $pos$libresoc.v:111049$4326_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:111053$4331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111053$4330_Y - connect \Y $pos$libresoc.v:111053$4331_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:111047$4323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \LOGICAL_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111047$4323_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:111048$4324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \LOGICAL_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:111048$4324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:111050$4327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LOGICAL_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:111050$4327_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:111051$4328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LOGICAL_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:111051$4328_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:111052$4329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111052$4329_Y - end - attribute \src "libresoc.v:110967.7-110967.20" - process $proc$libresoc.v:110967$4340 - assign { } { } - assign $0\initial[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:111055.3-111101.6" - process $proc$libresoc.v:111055$4332 + attribute \src "libresoc.v:119151.3-119163.6" + process $proc$libresoc.v:119151$4473 assign { } { } assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111056.5-111056.29" + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:119152.5-119152.29" switch \initial - attribute \src "libresoc.v:111056.9-111056.17" + attribute \src "libresoc.v:119152.9-119152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 2'00 assign { } { } - assign $1\imm_b[63:0] \$1 + assign $1\dec62_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 2'01 assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "libresoc.v:119164.3-119176.6" + process $proc$libresoc.v:119164$4474 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:119165.5-119165.29" + switch \initial + attribute \src "libresoc.v:119165.9-119165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 2'00 assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + assign $1\dec62_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 2'01 assign { } { } - assign $1\imm_b[63:0] \$3 + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "libresoc.v:119177.3-119189.6" + process $proc$libresoc.v:119177$4475 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:119178.5-119178.29" + switch \initial + attribute \src "libresoc.v:119178.9-119178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 2'00 assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + assign $1\dec62_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 2'01 assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "libresoc.v:119190.3-119202.6" + process $proc$libresoc.v:119190$4476 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:119191.5-119191.29" + switch \initial + attribute \src "libresoc.v:119191.9-119191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 2'00 assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + assign $1\dec62_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 2'01 assign { } { } - assign $1\imm_b[63:0] \$7 + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:119203.3-119215.6" + process $proc$libresoc.v:119203$4477 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:119204.5-119204.29" + switch \initial + attribute \src "libresoc.v:119204.9-119204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1010 + case 2'00 assign { } { } - assign $1\imm_b[63:0] \$9 + assign $1\dec62_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1011 + case 2'01 assign { } { } - assign $1\imm_b[63:0] \$11 + assign $1\dec62_rsrv[0:0] 1'0 case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec62_rsrv[0:0] 1'0 end sync always - update \imm_b $0\imm_b[63:0] + update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:111102.3-111148.6" - process $proc$libresoc.v:111102$4333 + attribute \src "libresoc.v:119216.3-119228.6" + process $proc$libresoc.v:119216$4478 assign { } { } assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111103.5-111103.29" + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:119217.5-119217.29" switch \initial - attribute \src "libresoc.v:111103.9-111103.17" + attribute \src "libresoc.v:119217.9-119217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 2'00 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 2'01 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "libresoc.v:119229.3-119241.6" + process $proc$libresoc.v:119229$4479 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:119230.5-119230.29" + switch \initial + attribute \src "libresoc.v:119230.9-119230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 2'00 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 2'01 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "libresoc.v:119242.3-119254.6" + process $proc$libresoc.v:119242$4480 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:119243.5-119243.29" + switch \initial + attribute \src "libresoc.v:119243.9-119243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 2'00 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 2'01 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "libresoc.v:119255.3-119267.6" + process $proc$libresoc.v:119255$4481 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:119256.5-119256.29" + switch \initial + attribute \src "libresoc.v:119256.9-119256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 2'00 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 2'01 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "libresoc.v:119268.3-119280.6" + process $proc$libresoc.v:119268$4482 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:119269.5-119269.29" + switch \initial + attribute \src "libresoc.v:119269.9-119269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1010 + case 2'00 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 4'1011 + case 2'01 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\dec62_sgl_pipe[0:0] 1'1 case - assign $1\imm_b_ok[0:0] 1'0 + assign $1\dec62_sgl_pipe[0:0] 1'0 end sync always - update \imm_b_ok $0\imm_b_ok[0:0] + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:111149.3-111159.6" - process $proc$libresoc.v:111149$4334 + attribute \src "libresoc.v:119281.3-119293.6" + process $proc$libresoc.v:119281$4483 assign { } { } assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111150.5-111150.29" + assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] + attribute \src "libresoc.v:119282.5-119282.29" switch \initial - attribute \src "libresoc.v:111150.9-111150.17" + attribute \src "libresoc.v:119282.9-119282.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 2'00 assign { } { } - assign $1\si[15:0] \LOGICAL_SI + assign $1\dec62_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_SV_Etype[1:0] 2'01 case - assign $1\si[15:0] 16'0000000000000000 + assign $1\dec62_SV_Etype[1:0] 2'00 end sync always - update \si $0\si[15:0] + update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end - attribute \src "libresoc.v:111160.3-111170.6" - process $proc$libresoc.v:111160$4335 + attribute \src "libresoc.v:119294.3-119306.6" + process $proc$libresoc.v:119294$4484 assign { } { } assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111161.5-111161.29" + assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] + attribute \src "libresoc.v:119295.5-119295.29" switch \initial - attribute \src "libresoc.v:111161.9-111161.17" + attribute \src "libresoc.v:119295.9-119295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 2'00 assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] + assign $1\dec62_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_SV_Ptype[1:0] 2'10 case - assign $1\si_hi[31:0] 0 + assign $1\dec62_SV_Ptype[1:0] 2'00 end sync always - update \si_hi $0\si_hi[31:0] + update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end - attribute \src "libresoc.v:111171.3-111181.6" - process $proc$libresoc.v:111171$4336 + attribute \src "libresoc.v:119307.3-119319.6" + process $proc$libresoc.v:119307$4485 assign { } { } assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:111172.5-111172.29" + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:119308.5-119308.29" switch \initial - attribute \src "libresoc.v:111172.9-111172.17" + attribute \src "libresoc.v:119308.9-119308.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 2'00 assign { } { } - assign $1\ui[15:0] \LOGICAL_UI + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 case - assign $1\ui[15:0] 16'0000000000000000 + assign $1\dec62_in1_sel[2:0] 3'000 end sync always - update \ui $0\ui[15:0] + update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:111182.3-111192.6" - process $proc$libresoc.v:111182$4337 + attribute \src "libresoc.v:119320.3-119332.6" + process $proc$libresoc.v:119320$4486 assign { } { } assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111183.5-111183.29" + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:119321.5-119321.29" switch \initial - attribute \src "libresoc.v:111183.9-111183.17" + attribute \src "libresoc.v:119321.9-119321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 2'00 assign { } { } - assign $1\li[25:0] \$16 [25:0] + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 case - assign $1\li[25:0] 26'00000000000000000000000000 + assign $1\dec62_in2_sel[3:0] 4'0000 end sync always - update \li $0\li[25:0] + update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:111193.3-111203.6" - process $proc$libresoc.v:111193$4338 + attribute \src "libresoc.v:119333.3-119345.6" + process $proc$libresoc.v:119333$4487 assign { } { } assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:111194.5-111194.29" + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:119334.5-119334.29" switch \initial - attribute \src "libresoc.v:111194.9-111194.17" + attribute \src "libresoc.v:119334.9-119334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 2'00 assign { } { } - assign $1\bd[15:0] \$19 [15:0] + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 case - assign $1\bd[15:0] 16'0000000000000000 + assign $1\dec62_in3_sel[1:0] 2'00 end sync always - update \bd $0\bd[15:0] + update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:111204.3-111214.6" - process $proc$libresoc.v:111204$4339 + attribute \src "libresoc.v:119346.3-119358.6" + process $proc$libresoc.v:119346$4488 assign { } { } assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:111205.5-111205.29" + assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] + attribute \src "libresoc.v:119347.5-119347.29" switch \initial - attribute \src "libresoc.v:111205.9-111205.17" + attribute \src "libresoc.v:119347.9-119347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 2'00 assign { } { } - assign $1\ds[15:0] \$22 [15:0] + assign $1\dec62_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[2:0] 3'000 case - assign $1\ds[15:0] 16'0000000000000000 + assign $1\dec62_out_sel[2:0] 3'000 end sync always - update \ds $0\ds[15:0] + update \dec62_out_sel $0\dec62_out_sel[2:0] end - connect \$9 $pos$libresoc.v:111045$4320_Y - connect \$11 $pos$libresoc.v:111046$4322_Y - connect \$14 $sshl$libresoc.v:111047$4323_Y - connect \$17 $sshl$libresoc.v:111048$4324_Y - connect \$1 $pos$libresoc.v:111049$4326_Y - connect \$20 $sshl$libresoc.v:111050$4327_Y - connect \$23 $sshl$libresoc.v:111051$4328_Y - connect \$4 $sshl$libresoc.v:111052$4329_Y - connect \$3 $pos$libresoc.v:111053$4331_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 + connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:111223.1-111476.10" +attribute \src "libresoc.v:119364.1-119947.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" -module \dec_bi$179 - attribute \src "libresoc.v:111450.3-111460.6" - wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111461.3-111471.6" - wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:111312.3-111358.6" - wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:111359.3-111405.6" - wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:111224.7-111224.20" +module \dec_ALU + attribute \src "libresoc.v:119910.3-119924.6" + wire width 14 $0\ALU__fn_unit[13:0] + attribute \src "libresoc.v:119897.3-119909.6" + wire width 7 $0\ALU__insn_type[6:0] + attribute \src "libresoc.v:119882.3-119896.6" + wire $0\ALU__write_cr0[0:0] + attribute \src "libresoc.v:119365.7-119365.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111439.3-111449.6" - wire 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"libresoc.v:111303.18-111303.107" - wire width 64 $extend$libresoc.v:111303$4343_Y - attribute \src "libresoc.v:111306.17-111306.104" - wire width 64 $extend$libresoc.v:111306$4347_Y - attribute \src "libresoc.v:111310.17-111310.102" - wire width 64 $extend$libresoc.v:111310$4352_Y - attribute \src "libresoc.v:111302.17-111302.104" - wire width 64 $pos$libresoc.v:111302$4342_Y - attribute \src "libresoc.v:111303.18-111303.107" - wire width 64 $pos$libresoc.v:111303$4344_Y - attribute \src "libresoc.v:111306.17-111306.104" - wire width 64 $pos$libresoc.v:111306$4348_Y - attribute \src "libresoc.v:111310.17-111310.102" - wire width 64 $pos$libresoc.v:111310$4353_Y - attribute \src "libresoc.v:111304.18-111304.114" - wire width 47 $sshl$libresoc.v:111304$4345_Y - attribute \src "libresoc.v:111305.18-111305.113" - wire width 27 $sshl$libresoc.v:111305$4346_Y - attribute \src "libresoc.v:111307.18-111307.113" - wire width 17 $sshl$libresoc.v:111307$4349_Y - attribute \src "libresoc.v:111308.18-111308.113" - wire width 17 $sshl$libresoc.v:111308$4350_Y - attribute \src "libresoc.v:111309.17-111309.109" - wire width 47 $sshl$libresoc.v:111309$4351_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$19 - attribute \src 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"TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \ALU__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \ALU__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 3 \ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_ALU_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_ALU_UI + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b + wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:111224.7-111224.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li + wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -173473,531 +186431,892 @@ module \dec_bi$179 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111302$4341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:119365.7-119365.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:119798$4490 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \DIV_sh - connect \Y $extend$libresoc.v:111302$4341_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:119798$4490_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111303$4343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:119800$4492 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:111303$4343_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:119800$4492_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111306$4347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:119813$4505 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \DIV_UI - connect \Y $extend$libresoc.v:111306$4347_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:119813$4505_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:111310$4352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:119814$4506 parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:111310$4352_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:119814$4506_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111302$4342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:119816$4508 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111302$4341_Y - connect \Y $pos$libresoc.v:111302$4342_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:119816$4508_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111303$4344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:119818$4510 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111303$4343_Y - connect \Y $pos$libresoc.v:111303$4344_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:119818$4510_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111306$4348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:119819$4511 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111306$4347_Y - connect \Y $pos$libresoc.v:111306$4348_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:119819$4511_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:111310$4353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:119820$4512 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111310$4352_Y - connect \Y $pos$libresoc.v:111310$4353_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:119820$4512_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:111304$4345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:119801$4493 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:119801$4493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:119802$4494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:119802$4494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:119804$4496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \DIV_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111304$4345_Y + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:119804$4496_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:111305$4346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:119805$4497 parameter \A_SIGNED 0 - parameter \A_WIDTH 24 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \DIV_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:111305$4346_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:119805$4497_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:111307$4349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:119807$4499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:119807$4499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:119808$4500 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DIV_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:111307$4349_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:119808$4500_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:111308$4350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:119810$4502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:119810$4502_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:119812$4504 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DIV_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:111308$4350_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:119812$4504_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:111309$4351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:119815$4507 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111309$4351_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:119815$4507_Y end - attribute \src "libresoc.v:111224.7-111224.20" - process $proc$libresoc.v:111224$4362 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:119821$4513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:119821$4513_Y end - attribute \src "libresoc.v:111312.3-111358.6" - process $proc$libresoc.v:111312$4354 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111313.5-111313.29" - switch \initial - attribute \src "libresoc.v:111313.9-111313.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:119799$4491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:119799$4491_Y end - attribute \src "libresoc.v:111359.3-111405.6" - process $proc$libresoc.v:111359$4355 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111360.5-111360.29" - switch \initial - attribute \src "libresoc.v:111360.9-111360.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:119817$4509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:119817$4509_Y end - attribute \src "libresoc.v:111406.3-111416.6" - process $proc$libresoc.v:111406$4356 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:119803$4495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:119803$4495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:119806$4498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:119806$4498_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:119809$4501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:119809$4501_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:119811$4503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:119811$4503_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119822.7-119850.4" + cell \dec \dec + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + connect \ALU_LI \dec_ALU_LI + connect \ALU_OE \dec_ALU_OE + connect \ALU_RA \dec_ALU_RA + connect \ALU_Rc \dec_ALU_Rc + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_SPR \dec_ALU_SPR + connect \ALU_UI \dec_ALU_UI + connect \ALU_cr_out \dec_ALU_cr_out + connect \ALU_cry_in \dec_ALU_cry_in + connect \ALU_cry_out \dec_ALU_cry_out + connect \ALU_function_unit \dec_ALU_function_unit + connect \ALU_in1_sel \dec_ALU_in1_sel + connect \ALU_in2_sel \dec_ALU_in2_sel + connect \ALU_internal_op \dec_ALU_internal_op + connect \ALU_inv_a \dec_ALU_inv_a + connect \ALU_inv_out \dec_ALU_inv_out + connect \ALU_is_32b \dec_ALU_is_32b + connect \ALU_ldst_len \dec_ALU_ldst_len + connect \ALU_rc_sel \dec_ALU_rc_sel + connect \ALU_sgn \dec_ALU_sgn + connect \ALU_sh \dec_ALU_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119851.10-119856.4" + cell \dec_ai \dec_ai + connect \ALU_RA \dec_ALU_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119857.10-119868.4" + cell \dec_bi \dec_bi + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + connect \ALU_LI \dec_ALU_LI + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_sh \dec_ALU_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119869.10-119875.4" + cell \dec_oe \dec_oe + connect \ALU_OE \dec_ALU_OE + connect \ALU_internal_op \dec_ALU_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119876.10-119881.4" + cell \dec_rc \dec_rc + connect \ALU_Rc \dec_ALU_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:119365.7-119365.20" + process $proc$libresoc.v:119365$4517 assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111407.5-111407.29" - switch \initial - attribute \src "libresoc.v:111407.9-111407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \DIV_SI - case - assign $1\si[15:0] 16'0000000000000000 - end + assign $0\initial[0:0] 1'0 sync always - update \si $0\si[15:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:111417.3-111427.6" - process $proc$libresoc.v:111417$4357 + attribute \src "libresoc.v:119882.3-119896.6" + process $proc$libresoc.v:119882$4514 assign { } { } assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111418.5-111418.29" + assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] + attribute \src "libresoc.v:119883.5-119883.29" switch \initial - attribute \src "libresoc.v:111418.9-111418.17" + attribute \src "libresoc.v:119883.9-119883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + switch \dec_ALU_cr_out attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 3'001 , 3'101 assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "libresoc.v:111428.3-111438.6" - process $proc$libresoc.v:111428$4358 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:111429.5-111429.29" - switch \initial - attribute \src "libresoc.v:111429.9-111429.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\ALU__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 3'010 , 3'011 assign { } { } - assign $1\ui[15:0] \DIV_UI + assign $1\ALU__write_cr0[0:0] 1'1 case - assign $1\ui[15:0] 16'0000000000000000 + assign $1\ALU__write_cr0[0:0] 1'0 end sync always - update \ui $0\ui[15:0] + update \ALU__write_cr0 $0\ALU__write_cr0[0:0] end - attribute \src "libresoc.v:111439.3-111449.6" - process $proc$libresoc.v:111439$4359 + attribute \src "libresoc.v:119897.3-119909.6" + process $proc$libresoc.v:119897$4515 assign { } { } assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111440.5-111440.29" + assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] + attribute \src "libresoc.v:119898.5-119898.29" switch \initial - attribute \src "libresoc.v:111440.9-111440.17" + attribute \src "libresoc.v:119898.9-119898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 2'-1 assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "libresoc.v:111450.3-111460.6" - process $proc$libresoc.v:111450$4360 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:111451.5-111451.29" - switch \initial - attribute \src "libresoc.v:111451.9-111451.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\ALU__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 2'1- assign { } { } - assign $1\bd[15:0] \$19 [15:0] + assign $1\ALU__insn_type[6:0] 7'0000000 case - assign $1\bd[15:0] 16'0000000000000000 + assign $1\ALU__insn_type[6:0] \dec_ALU_internal_op end sync always - update \bd $0\bd[15:0] + update \ALU__insn_type $0\ALU__insn_type[6:0] end - attribute \src "libresoc.v:111461.3-111471.6" - process $proc$libresoc.v:111461$4361 - assign { } { } + attribute \src "libresoc.v:119910.3-119924.6" + process $proc$libresoc.v:119910$4516 assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:111462.5-111462.29" + assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] + attribute \src "libresoc.v:119911.5-119911.29" switch \initial - attribute \src "libresoc.v:111462.9-111462.17" + attribute \src "libresoc.v:119911.9-119911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 2'-1 assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$libresoc.v:111302$4342_Y - connect \$11 $pos$libresoc.v:111303$4344_Y - connect \$14 $sshl$libresoc.v:111304$4345_Y - connect \$17 $sshl$libresoc.v:111305$4346_Y - connect \$1 $pos$libresoc.v:111306$4348_Y - connect \$20 $sshl$libresoc.v:111307$4349_Y - connect \$23 $sshl$libresoc.v:111308$4350_Y - connect \$4 $sshl$libresoc.v:111309$4351_Y - connect \$3 $pos$libresoc.v:111310$4353_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 + assign $1\ALU__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ALU__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ALU__fn_unit[13:0] \dec_ALU_function_unit + end + sync always + update \ALU__fn_unit $0\ALU__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:119798$4490_Y + connect \$12 $not$libresoc.v:119799$4491_Y + connect \$14 $and$libresoc.v:119800$4492_Y + connect \$16 $eq$libresoc.v:119801$4493_Y + connect \$18 $eq$libresoc.v:119802$4494_Y + connect \$20 $or$libresoc.v:119803$4495_Y + connect \$22 $eq$libresoc.v:119804$4496_Y + connect \$24 $eq$libresoc.v:119805$4497_Y + connect \$26 $or$libresoc.v:119806$4498_Y + connect \$28 $eq$libresoc.v:119807$4499_Y + connect \$2 $eq$libresoc.v:119808$4500_Y + connect \$30 $or$libresoc.v:119809$4501_Y + connect \$32 $eq$libresoc.v:119810$4502_Y + connect \$34 $or$libresoc.v:119811$4503_Y + connect \$36 $eq$libresoc.v:119812$4504_Y + connect \$38 $and$libresoc.v:119813$4505_Y + connect \$40 $and$libresoc.v:119814$4506_Y + connect \$42 $eq$libresoc.v:119815$4507_Y + connect \$44 $and$libresoc.v:119816$4508_Y + connect \$46 $not$libresoc.v:119817$4509_Y + connect \$48 $and$libresoc.v:119818$4510_Y + connect \$4 $and$libresoc.v:119819$4511_Y + connect \$6 $and$libresoc.v:119820$4512_Y + connect \$8 $eq$libresoc.v:119821$4513_Y + connect \ALU__is_signed \dec_ALU_sgn + connect \ALU__is_32bit \dec_ALU_is_32b + connect \ALU__output_carry \dec_ALU_cry_out + connect \ALU__input_carry \dec_ALU_cry_in + connect \ALU__invert_out \dec_ALU_inv_out + connect \ALU__invert_in \dec_ALU_inv_a + connect \ALU__data_len \dec_ALU_ldst_len + connect { \ALU__oe__ok \ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \ALU__rc__ok \ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \ALU__imm_data__ok \ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_ALU_in2_sel + connect \ALU__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_ALU_in1_sel + connect \dec_ai_sv_nz \sv_a_nz + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_ALU_SPR [4:0] \dec_ALU_SPR [9:5] } + connect \dec_oe_sel_in \dec_ALU_rc_sel + connect \dec_rc_sel_in \dec_ALU_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:111480.1-111733.10" +attribute \src "libresoc.v:119951.1-120431.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" -module \dec_bi$187 - attribute \src "libresoc.v:111707.3-111717.6" - wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111718.3-111728.6" - wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:111569.3-111615.6" - wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:111616.3-111662.6" - wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:111481.7-111481.20" +module \dec_BRANCH + attribute \src "libresoc.v:120381.3-120395.6" + wire width 14 $0\BRANCH__fn_unit[13:0] + attribute \src "libresoc.v:120406.3-120418.6" + wire width 7 $0\BRANCH__insn_type[6:0] + attribute \src "libresoc.v:120396.3-120405.6" + wire $0\BRANCH__lk[0:0] + attribute \src "libresoc.v:119952.7-119952.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111696.3-111706.6" - wire width 26 $0\li[25:0] - attribute \src "libresoc.v:111663.3-111673.6" - wire width 16 $0\si[15:0] - attribute \src "libresoc.v:111674.3-111684.6" - wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:111685.3-111695.6" - wire width 16 $0\ui[15:0] - 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\enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_BRANCH_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b + wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:111481.7-111481.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li + wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -174013,1071 +187332,1645 @@ module \dec_bi$187 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111559$4363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 \dec_bi_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:119952.7-119952.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 1 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120313$4518 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \MUL_sh - connect \Y $extend$libresoc.v:111559$4363_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:120313$4518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111560$4365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120315$4520 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:111560$4365_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:120315$4520_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111563$4369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120328$4533 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \MUL_UI - connect \Y $extend$libresoc.v:111563$4369_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:120328$4533_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:111567$4374 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120329$4534 parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:111567$4374_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:120329$4534_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111559$4364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120331$4536 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111559$4363_Y - connect \Y $pos$libresoc.v:111559$4364_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:120331$4536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111560$4366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120333$4538 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111560$4365_Y - connect \Y $pos$libresoc.v:111560$4366_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:120333$4538_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111563$4370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120334$4539 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111563$4369_Y - connect \Y $pos$libresoc.v:111563$4370_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:120334$4539_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:111567$4375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120335$4540 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111567$4374_Y - connect \Y $pos$libresoc.v:111567$4375_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:120335$4540_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:111561$4367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:120316$4521 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:120316$4521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:120317$4522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:120317$4522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120319$4524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \MUL_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111561$4367_Y + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:120319$4524_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:111562$4368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120320$4525 parameter \A_SIGNED 0 - parameter \A_WIDTH 24 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \MUL_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:111562$4368_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:120320$4525_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:111564$4371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120322$4527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:120322$4527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:120323$4528 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \MUL_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:111564$4371_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:120323$4528_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:111565$4372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:120325$4530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:120325$4530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:120327$4532 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \MUL_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:111565$4372_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:120327$4532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:111566$4373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:120330$4535 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111566$4373_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:120330$4535_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:120336$4541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:120336$4541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:120314$4519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120314$4519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:120332$4537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120332$4537_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:120318$4523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:120318$4523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:120321$4526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:120321$4526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:120324$4529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:120324$4529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:120326$4531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:120326$4531_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120337.13-120359.4" + cell \dec$141 \dec + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_LK \dec_BRANCH_LK + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_SPR \dec_BRANCH_SPR + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_cr_out \dec_BRANCH_cr_out + connect \BRANCH_function_unit \dec_BRANCH_function_unit + connect \BRANCH_in2_sel \dec_BRANCH_in2_sel + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_is_32b \dec_BRANCH_is_32b + connect \BRANCH_lk \dec_BRANCH_lk + connect \BRANCH_rc_sel \dec_BRANCH_rc_sel + connect \BRANCH_sh \dec_BRANCH_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120360.16-120371.4" + cell \dec_bi$144 \dec_bi + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_sh \dec_BRANCH_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120372.16-120376.4" + cell \dec_oe$143 \dec_oe + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \sel_in \dec_oe_sel_in end - attribute \src "libresoc.v:111481.7-111481.20" - process $proc$libresoc.v:111481$4384 + attribute \module_not_derived 1 + attribute \src "libresoc.v:120377.16-120380.4" + cell \dec_rc$142 \dec_rc + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:119952.7-119952.20" + process $proc$libresoc.v:119952$4545 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111569.3-111615.6" - process $proc$libresoc.v:111569$4376 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111570.5-111570.29" - switch \initial - attribute \src "libresoc.v:111570.9-111570.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "libresoc.v:111616.3-111662.6" - process $proc$libresoc.v:111616$4377 + attribute \src "libresoc.v:120381.3-120395.6" + process $proc$libresoc.v:120381$4542 assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111617.5-111617.29" + assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0] + attribute \src "libresoc.v:120382.5-120382.29" switch \initial - attribute \src "libresoc.v:111617.9-111617.17" + attribute \src "libresoc.v:120382.9-120382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 4'1010 + case 2'-1 assign { } { } - assign $1\imm_b_ok[0:0] 1'1 + assign $1\BRANCH__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'1011 + case 2'1- assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "libresoc.v:111663.3-111673.6" - process $proc$libresoc.v:111663$4378 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111664.5-111664.29" - switch \initial - attribute \src "libresoc.v:111664.9-111664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\BRANCH__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \MUL_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "libresoc.v:111674.3-111684.6" - process $proc$libresoc.v:111674$4379 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111675.5-111675.29" - switch \initial - attribute \src "libresoc.v:111675.9-111675.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 + assign $1\BRANCH__fn_unit[13:0] \dec_BRANCH_function_unit end sync always - update \si_hi $0\si_hi[31:0] + update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] end - attribute \src "libresoc.v:111685.3-111695.6" - process $proc$libresoc.v:111685$4380 + attribute \src "libresoc.v:120396.3-120405.6" + process $proc$libresoc.v:120396$4543 assign { } { } assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:111686.5-111686.29" + assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] + attribute \src "libresoc.v:120397.5-120397.29" switch \initial - attribute \src "libresoc.v:111686.9-111686.17" + attribute \src "libresoc.v:120397.9-120397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:869" + switch \dec_BRANCH_lk attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \MUL_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "libresoc.v:111696.3-111706.6" - process $proc$libresoc.v:111696$4381 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111697.5-111697.29" - switch \initial - attribute \src "libresoc.v:111697.9-111697.17" case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 assign { } { } - assign $1\li[25:0] \$16 [25:0] + assign $1\BRANCH__lk[0:0] \dec_BRANCH_LK case - assign $1\li[25:0] 26'00000000000000000000000000 + assign $1\BRANCH__lk[0:0] 1'0 end sync always - update \li $0\li[25:0] + update \BRANCH__lk $0\BRANCH__lk[0:0] end - attribute \src "libresoc.v:111707.3-111717.6" - process $proc$libresoc.v:111707$4382 + attribute \src "libresoc.v:120406.3-120418.6" + process $proc$libresoc.v:120406$4544 assign { } { } assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:111708.5-111708.29" + assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] + attribute \src "libresoc.v:120407.5-120407.29" switch \initial - attribute \src "libresoc.v:111708.9-111708.17" + attribute \src "libresoc.v:120407.9-120407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 2'-1 assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "libresoc.v:111718.3-111728.6" - process $proc$libresoc.v:111718$4383 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:111719.5-111719.29" - switch \initial - attribute \src "libresoc.v:111719.9-111719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\BRANCH__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 2'1- assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$libresoc.v:111559$4364_Y - connect \$11 $pos$libresoc.v:111560$4366_Y - connect \$14 $sshl$libresoc.v:111561$4367_Y - connect \$17 $sshl$libresoc.v:111562$4368_Y - connect \$1 $pos$libresoc.v:111563$4370_Y - connect \$20 $sshl$libresoc.v:111564$4371_Y - connect \$23 $sshl$libresoc.v:111565$4372_Y - connect \$4 $sshl$libresoc.v:111566$4373_Y - connect \$3 $pos$libresoc.v:111567$4375_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 + assign $1\BRANCH__insn_type[6:0] 7'0000000 + case + assign $1\BRANCH__insn_type[6:0] \dec_BRANCH_internal_op + end + sync always + update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] + end + connect \$10 $and$libresoc.v:120313$4518_Y + connect \$12 $not$libresoc.v:120314$4519_Y + connect \$14 $and$libresoc.v:120315$4520_Y + connect \$16 $eq$libresoc.v:120316$4521_Y + connect \$18 $eq$libresoc.v:120317$4522_Y + connect \$20 $or$libresoc.v:120318$4523_Y + connect \$22 $eq$libresoc.v:120319$4524_Y + connect \$24 $eq$libresoc.v:120320$4525_Y + connect \$26 $or$libresoc.v:120321$4526_Y + connect \$28 $eq$libresoc.v:120322$4527_Y + connect \$2 $eq$libresoc.v:120323$4528_Y + connect \$30 $or$libresoc.v:120324$4529_Y + connect \$32 $eq$libresoc.v:120325$4530_Y + connect \$34 $or$libresoc.v:120326$4531_Y + connect \$36 $eq$libresoc.v:120327$4532_Y + connect \$38 $and$libresoc.v:120328$4533_Y + connect \$40 $and$libresoc.v:120329$4534_Y + connect \$42 $eq$libresoc.v:120330$4535_Y + connect \$44 $and$libresoc.v:120331$4536_Y + connect \$46 $not$libresoc.v:120332$4537_Y + connect \$48 $and$libresoc.v:120333$4538_Y + connect \$4 $and$libresoc.v:120334$4539_Y + connect \$6 $and$libresoc.v:120335$4540_Y + connect \$8 $eq$libresoc.v:120336$4541_Y + connect \BRANCH__is_32bit \dec_BRANCH_is_32b + connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_BRANCH_in2_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_BRANCH_SPR [4:0] \dec_BRANCH_SPR [9:5] } + connect \BRANCH__cia \core_pc + connect \dec_oe_sel_in \dec_BRANCH_rc_sel + connect \dec_rc_sel_in \dec_BRANCH_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:111737.1-111990.10" +attribute \src "libresoc.v:120435.1-120807.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" -module \dec_bi$195 - attribute \src "libresoc.v:111964.3-111974.6" - wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111975.3-111985.6" - wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:111826.3-111872.6" - wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:111873.3-111919.6" - wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:111738.7-111738.20" +module \dec_CR + attribute \src "libresoc.v:120784.3-120798.6" + wire width 14 $0\CR__fn_unit[13:0] + attribute \src "libresoc.v:120771.3-120783.6" + wire width 7 $0\CR__insn_type[6:0] + attribute \src "libresoc.v:120436.7-120436.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111953.3-111963.6" - wire width 26 $0\li[25:0] - attribute \src "libresoc.v:111920.3-111930.6" - wire width 16 $0\si[15:0] - attribute \src "libresoc.v:111931.3-111941.6" - wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:111942.3-111952.6" - wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:111964.3-111974.6" - wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:111975.3-111985.6" - wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:111826.3-111872.6" - wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:111873.3-111919.6" - wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111953.3-111963.6" - wire width 26 $1\li[25:0] - attribute \src "libresoc.v:111920.3-111930.6" - wire width 16 $1\si[15:0] - attribute \src "libresoc.v:111931.3-111941.6" - wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:111942.3-111952.6" - wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:111816.17-111816.110" - wire width 64 $extend$libresoc.v:111816$4385_Y - attribute \src "libresoc.v:111817.18-111817.113" - wire width 64 $extend$libresoc.v:111817$4387_Y - attribute \src "libresoc.v:111820.17-111820.110" - wire width 64 $extend$libresoc.v:111820$4391_Y - attribute \src "libresoc.v:111824.17-111824.102" - wire width 64 $extend$libresoc.v:111824$4396_Y - attribute \src "libresoc.v:111816.17-111816.110" - wire width 64 $pos$libresoc.v:111816$4386_Y - attribute \src "libresoc.v:111817.18-111817.113" - wire width 64 $pos$libresoc.v:111817$4388_Y - attribute \src "libresoc.v:111820.17-111820.110" - wire width 64 $pos$libresoc.v:111820$4392_Y - attribute \src "libresoc.v:111824.17-111824.102" - wire width 64 $pos$libresoc.v:111824$4397_Y - attribute \src "libresoc.v:111818.18-111818.120" - wire width 47 $sshl$libresoc.v:111818$4389_Y - attribute \src "libresoc.v:111819.18-111819.119" - wire width 27 $sshl$libresoc.v:111819$4390_Y - attribute \src "libresoc.v:111821.18-111821.119" - wire width 17 $sshl$libresoc.v:111821$4393_Y - attribute \src "libresoc.v:111822.18-111822.119" - wire width 17 $sshl$libresoc.v:111822$4394_Y - attribute \src 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$pos $extend$libresoc.v:111816$4385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 5 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120726$4546 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:111816$4385_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:120726$4546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111817$4387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120728$4548 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:111817$4387_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:120728$4548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111820$4391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120741$4561 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:111820$4391_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:120741$4561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:111824$4396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120742$4562 parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:111824$4396_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:120742$4562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111816$4386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120744$4564 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111816$4385_Y - connect \Y $pos$libresoc.v:111816$4386_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:120744$4564_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111817$4388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120746$4566 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111817$4387_Y - connect \Y $pos$libresoc.v:111817$4388_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:120746$4566_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111820$4392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120747$4567 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111820$4391_Y - connect \Y $pos$libresoc.v:111820$4392_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:120747$4567_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:111824$4397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120748$4568 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111824$4396_Y - connect \Y $pos$libresoc.v:111824$4397_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:120748$4568_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:111818$4389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:120729$4549 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_CR_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:120729$4549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:120730$4550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_CR_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:120730$4550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120732$4552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \SHIFT_ROT_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111818$4389_Y + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:120732$4552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:111819$4390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120733$4553 parameter \A_SIGNED 0 - parameter \A_WIDTH 24 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \SHIFT_ROT_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:111819$4390_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:120733$4553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:111821$4393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120735$4555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:120735$4555_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:120736$4556 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \SHIFT_ROT_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:111821$4393_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_CR_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:120736$4556_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:111822$4394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:120738$4558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:120738$4558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:120740$4560 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \SHIFT_ROT_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:111822$4394_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_CR_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:120740$4560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:111823$4395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:120743$4563 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111823$4395_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_CR_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:120743$4563_Y end - attribute \src "libresoc.v:111738.7-111738.20" - process $proc$libresoc.v:111738$4406 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:120749$4569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_CR_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:120749$4569_Y end - attribute \src "libresoc.v:111826.3-111872.6" - process $proc$libresoc.v:111826$4398 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111827.5-111827.29" - switch \initial - attribute \src "libresoc.v:111827.9-111827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:120727$4547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120727$4547_Y end - attribute \src "libresoc.v:111873.3-111919.6" - process $proc$libresoc.v:111873$4399 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111874.5-111874.29" - switch \initial - attribute \src "libresoc.v:111874.9-111874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:120745$4565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120745$4565_Y end - attribute \src "libresoc.v:111920.3-111930.6" - process $proc$libresoc.v:111920$4400 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111921.5-111921.29" - switch \initial - attribute \src "libresoc.v:111921.9-111921.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \SHIFT_ROT_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:120731$4551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:120731$4551_Y end - attribute \src "libresoc.v:111931.3-111941.6" - process $proc$libresoc.v:111931$4401 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:120734$4554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:120734$4554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:120737$4557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:120737$4557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:120739$4559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:120739$4559_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120750.13-120761.4" + cell \dec$138 \dec + connect \CR_OE \dec_CR_OE + connect \CR_Rc \dec_CR_Rc + connect \CR_SPR \dec_CR_SPR + connect \CR_cr_out \dec_CR_cr_out + connect \CR_function_unit \dec_CR_function_unit + connect \CR_internal_op \dec_CR_internal_op + connect \CR_rc_sel \dec_CR_rc_sel + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120762.16-120766.4" + cell \dec_oe$140 \dec_oe + connect \CR_OE \dec_CR_OE + connect \CR_internal_op \dec_CR_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120767.16-120770.4" + cell \dec_rc$139 \dec_rc + connect \CR_Rc \dec_CR_Rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:120436.7-120436.20" + process $proc$libresoc.v:120436$4572 assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111932.5-111932.29" - switch \initial - attribute \src "libresoc.v:111932.9-111932.17" - case 1'1 - case - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 19 \DIV__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \DIV__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 13 \DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 3 \DIV__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_DIV_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_DIV_UI + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b + wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:111995.7-111995.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li + wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -175093,585 +188986,824 @@ module \dec_bi$204 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:112073$4407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:120812.7-120812.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121245$4573 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \LDST_sh - connect \Y $extend$libresoc.v:112073$4407_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:121245$4573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:112074$4409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121247$4575 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:112074$4409_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:121247$4575_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:112077$4413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121260$4588 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \LDST_UI - connect \Y $extend$libresoc.v:112077$4413_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:121260$4588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:112081$4418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121261$4589 parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:112081$4418_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121261$4589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:112073$4408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121263$4591 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:112073$4407_Y - connect \Y $pos$libresoc.v:112073$4408_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:121263$4591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:112074$4410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121265$4593 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:112074$4409_Y - connect \Y $pos$libresoc.v:112074$4410_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:121265$4593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:112077$4414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121266$4594 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:112077$4413_Y - connect \Y $pos$libresoc.v:112077$4414_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:121266$4594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:112081$4419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121267$4595 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:112081$4418_Y - connect \Y $pos$libresoc.v:112081$4419_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121267$4595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:112075$4411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:121248$4576 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:121248$4576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121249$4577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:121249$4577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121251$4579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \LDST_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:112075$4411_Y + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:121251$4579_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:112076$4412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121252$4580 parameter \A_SIGNED 0 - parameter \A_WIDTH 24 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \LDST_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:112076$4412_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:121252$4580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:112078$4415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121254$4582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:121254$4582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:121255$4583 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LDST_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:112078$4415_Y + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121255$4583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121257$4585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:121257$4585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:121259$4587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121259$4587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:121262$4590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121262$4590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:121268$4596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121268$4596_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:121246$4574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121246$4574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:121264$4592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121264$4592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:121250$4578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:121250$4578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:121253$4581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:121253$4581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:121256$4584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:121256$4584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121258$4586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:121258$4586_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121269.13-121297.4" + cell \dec$153 \dec + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + connect \DIV_LI \dec_DIV_LI + connect \DIV_OE \dec_DIV_OE + connect \DIV_RA \dec_DIV_RA + connect \DIV_Rc \dec_DIV_Rc + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_SPR \dec_DIV_SPR + connect \DIV_UI \dec_DIV_UI + connect \DIV_cr_out \dec_DIV_cr_out + connect \DIV_cry_in \dec_DIV_cry_in + connect \DIV_cry_out \dec_DIV_cry_out + connect \DIV_function_unit \dec_DIV_function_unit + connect \DIV_in1_sel \dec_DIV_in1_sel + connect \DIV_in2_sel \dec_DIV_in2_sel + connect \DIV_internal_op \dec_DIV_internal_op + connect \DIV_inv_a \dec_DIV_inv_a + connect \DIV_inv_out \dec_DIV_inv_out + connect \DIV_is_32b \dec_DIV_is_32b + connect \DIV_ldst_len \dec_DIV_ldst_len + connect \DIV_rc_sel \dec_DIV_rc_sel + connect \DIV_sgn \dec_DIV_sgn + connect \DIV_sh \dec_DIV_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121298.16-121303.4" + cell \dec_ai$156 \dec_ai + connect \DIV_RA \dec_DIV_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121304.16-121315.4" + cell \dec_bi$157 \dec_bi + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + connect \DIV_LI \dec_DIV_LI + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_sh \dec_DIV_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:112079$4416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LDST_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:112079$4416_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:121316.16-121322.4" + cell \dec_oe$155 \dec_oe + connect \DIV_OE \dec_DIV_OE + connect \DIV_internal_op \dec_DIV_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:112080$4417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:112080$4417_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:121323.16-121328.4" + cell \dec_rc$154 \dec_rc + connect \DIV_Rc \dec_DIV_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:111995.7-111995.20" - process $proc$libresoc.v:111995$4428 + attribute \src "libresoc.v:120812.7-120812.20" + process $proc$libresoc.v:120812$4600 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112083.3-112129.6" - process $proc$libresoc.v:112083$4420 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:112084.5-112084.29" - switch \initial - attribute \src "libresoc.v:112084.9-112084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "libresoc.v:112130.3-112176.6" - process $proc$libresoc.v:112130$4421 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:112131.5-112131.29" - switch \initial - attribute \src "libresoc.v:112131.9-112131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "libresoc.v:112177.3-112187.6" - process $proc$libresoc.v:112177$4422 + attribute \src "libresoc.v:121329.3-121343.6" + process $proc$libresoc.v:121329$4597 assign { } { } assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:112178.5-112178.29" + assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] + attribute \src "libresoc.v:121330.5-121330.29" switch \initial - attribute \src "libresoc.v:112178.9-112178.17" + attribute \src "libresoc.v:121330.9-121330.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + switch \dec_DIV_cr_out attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 3'001 , 3'101 assign { } { } - assign $1\si[15:0] \LDST_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "libresoc.v:112188.3-112198.6" - process $proc$libresoc.v:112188$4423 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:112189.5-112189.29" - switch \initial - attribute \src "libresoc.v:112189.9-112189.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\DIV__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 3'010 , 3'011 assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] + assign $1\DIV__write_cr0[0:0] 1'1 case - assign $1\si_hi[31:0] 0 + assign $1\DIV__write_cr0[0:0] 1'0 end sync always - update \si_hi $0\si_hi[31:0] + update \DIV__write_cr0 $0\DIV__write_cr0[0:0] end - attribute \src "libresoc.v:112199.3-112209.6" - process $proc$libresoc.v:112199$4424 + attribute \src "libresoc.v:121344.3-121356.6" + process $proc$libresoc.v:121344$4598 assign { } { } assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:112200.5-112200.29" + assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] + attribute \src "libresoc.v:121345.5-121345.29" switch \initial - attribute \src "libresoc.v:112200.9-112200.17" + attribute \src "libresoc.v:121345.9-121345.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 2'-1 assign { } { } - assign $1\ui[15:0] \LDST_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "libresoc.v:112210.3-112220.6" - process $proc$libresoc.v:112210$4425 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:112211.5-112211.29" - switch \initial - attribute \src "libresoc.v:112211.9-112211.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\DIV__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 2'1- assign { } { } - assign $1\li[25:0] \$16 [25:0] + assign $1\DIV__insn_type[6:0] 7'0000000 case - assign $1\li[25:0] 26'00000000000000000000000000 + assign $1\DIV__insn_type[6:0] \dec_DIV_internal_op end sync always - update \li $0\li[25:0] + update \DIV__insn_type $0\DIV__insn_type[6:0] end - attribute \src "libresoc.v:112221.3-112231.6" - process $proc$libresoc.v:112221$4426 + attribute \src "libresoc.v:121357.3-121371.6" + process $proc$libresoc.v:121357$4599 assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:112222.5-112222.29" + assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] + attribute \src "libresoc.v:121358.5-121358.29" switch \initial - attribute \src "libresoc.v:112222.9-112222.17" + attribute \src "libresoc.v:121358.9-121358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 2'-1 assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "libresoc.v:112232.3-112242.6" - process $proc$libresoc.v:112232$4427 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:112233.5-112233.29" - switch \initial - attribute \src "libresoc.v:112233.9-112233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in + assign $1\DIV__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 2'1- assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$libresoc.v:112073$4408_Y - connect \$11 $pos$libresoc.v:112074$4410_Y - connect \$14 $sshl$libresoc.v:112075$4411_Y - connect \$17 $sshl$libresoc.v:112076$4412_Y - connect \$1 $pos$libresoc.v:112077$4414_Y - connect \$20 $sshl$libresoc.v:112078$4415_Y - connect \$23 $sshl$libresoc.v:112079$4416_Y - connect \$4 $sshl$libresoc.v:112080$4417_Y - connect \$3 $pos$libresoc.v:112081$4419_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 + assign $1\DIV__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\DIV__fn_unit[13:0] \dec_DIV_function_unit + end + sync always + update \DIV__fn_unit $0\DIV__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:121245$4573_Y + connect \$12 $not$libresoc.v:121246$4574_Y + connect \$14 $and$libresoc.v:121247$4575_Y + connect \$16 $eq$libresoc.v:121248$4576_Y + connect \$18 $eq$libresoc.v:121249$4577_Y + connect \$20 $or$libresoc.v:121250$4578_Y + connect \$22 $eq$libresoc.v:121251$4579_Y + connect \$24 $eq$libresoc.v:121252$4580_Y + connect \$26 $or$libresoc.v:121253$4581_Y + connect \$28 $eq$libresoc.v:121254$4582_Y + connect \$2 $eq$libresoc.v:121255$4583_Y + connect \$30 $or$libresoc.v:121256$4584_Y + connect \$32 $eq$libresoc.v:121257$4585_Y + connect \$34 $or$libresoc.v:121258$4586_Y + connect \$36 $eq$libresoc.v:121259$4587_Y + connect \$38 $and$libresoc.v:121260$4588_Y + connect \$40 $and$libresoc.v:121261$4589_Y + connect \$42 $eq$libresoc.v:121262$4590_Y + connect \$44 $and$libresoc.v:121263$4591_Y + connect \$46 $not$libresoc.v:121264$4592_Y + connect \$48 $and$libresoc.v:121265$4593_Y + connect \$4 $and$libresoc.v:121266$4594_Y + connect \$6 $and$libresoc.v:121267$4595_Y + connect \$8 $eq$libresoc.v:121268$4596_Y + connect \DIV__is_signed \dec_DIV_sgn + connect \DIV__is_32bit \dec_DIV_is_32b + connect \DIV__output_carry \dec_DIV_cry_out + connect \DIV__input_carry \dec_DIV_cry_in + connect \DIV__invert_out \dec_DIV_inv_out + connect \DIV__invert_in \dec_DIV_inv_a + connect \DIV__data_len \dec_DIV_ldst_len + connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_DIV_in2_sel + connect \DIV__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_DIV_in1_sel + connect \dec_ai_sv_nz \sv_a_nz + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_DIV_SPR [4:0] \dec_DIV_SPR [9:5] } + connect \dec_oe_sel_in \dec_DIV_rc_sel + connect \dec_rc_sel_in \dec_DIV_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:112251.1-112299.10" +attribute \src "libresoc.v:121398.1-121959.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" -module \dec_c - attribute \src "libresoc.v:112252.7-112252.20" +module \dec_LDST + attribute \src "libresoc.v:121923.3-121937.6" + wire width 14 $0\LDST__fn_unit[13:0] + attribute \src "libresoc.v:121910.3-121922.6" + wire width 7 $0\LDST__insn_type[6:0] + attribute \src "libresoc.v:121399.7-121399.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112269.3-112283.6" - wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:112284.3-112298.6" - wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:112269.3-112283.6" - wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:112284.3-112298.6" - wire $1\reg_c_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \RS - attribute \src "libresoc.v:112252.7-112252.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 1 \reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \reg_c_ok - attribute \enum_base_type "In3Sel" + attribute \src "libresoc.v:121923.3-121937.6" + wire width 14 $1\LDST__fn_unit[13:0] + attribute \src "libresoc.v:121910.3-121922.6" + wire width 7 $1\LDST__insn_type[6:0] + attribute \src "libresoc.v:121827.18-121827.113" + wire $and$libresoc.v:121827$4601_Y + attribute \src "libresoc.v:121829.18-121829.110" + wire $and$libresoc.v:121829$4603_Y + attribute \src "libresoc.v:121842.18-121842.114" + wire $and$libresoc.v:121842$4616_Y + attribute \src "libresoc.v:121843.18-121843.116" + wire $and$libresoc.v:121843$4617_Y + attribute \src "libresoc.v:121845.18-121845.114" + wire $and$libresoc.v:121845$4619_Y + attribute \src "libresoc.v:121847.18-121847.110" + wire $and$libresoc.v:121847$4621_Y + attribute \src "libresoc.v:121848.17-121848.112" + wire $and$libresoc.v:121848$4622_Y + attribute \src "libresoc.v:121849.17-121849.114" + wire $and$libresoc.v:121849$4623_Y + attribute \src "libresoc.v:121830.18-121830.127" + wire $eq$libresoc.v:121830$4604_Y + attribute \src "libresoc.v:121831.18-121831.127" + wire $eq$libresoc.v:121831$4605_Y + attribute \src "libresoc.v:121833.18-121833.110" + wire $eq$libresoc.v:121833$4607_Y + attribute \src "libresoc.v:121834.18-121834.110" + wire $eq$libresoc.v:121834$4608_Y + attribute \src "libresoc.v:121836.18-121836.112" + wire $eq$libresoc.v:121836$4610_Y + attribute \src "libresoc.v:121837.17-121837.131" + wire $eq$libresoc.v:121837$4611_Y + attribute \src "libresoc.v:121839.18-121839.110" + wire $eq$libresoc.v:121839$4613_Y + attribute \src "libresoc.v:121841.18-121841.132" + wire $eq$libresoc.v:121841$4615_Y + attribute \src "libresoc.v:121844.18-121844.132" + wire $eq$libresoc.v:121844$4618_Y + attribute \src "libresoc.v:121850.17-121850.131" + wire $eq$libresoc.v:121850$4624_Y + attribute \src "libresoc.v:121828.18-121828.110" + wire $not$libresoc.v:121828$4602_Y + attribute \src "libresoc.v:121846.18-121846.110" + wire $not$libresoc.v:121846$4620_Y + attribute \src "libresoc.v:121832.18-121832.110" + wire $or$libresoc.v:121832$4606_Y + attribute \src "libresoc.v:121835.18-121835.110" + wire $or$libresoc.v:121835$4609_Y + attribute \src "libresoc.v:121838.18-121838.110" + wire $or$libresoc.v:121838$4612_Y + attribute \src "libresoc.v:121840.18-121840.110" + wire $or$libresoc.v:121840$4614_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 14 \LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 18 \LDST__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 3 \LDST__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \LDST__is_signed + attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:112252.7-112252.20" - process $proc$libresoc.v:112252$4431 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:112269.3-112283.6" - process $proc$libresoc.v:112269$4429 - assign { } { } - assign { } { } - assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:112270.5-112270.29" - switch \initial - attribute \src "libresoc.v:112270.9-112270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c[4:0] \RB - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_c[4:0] \RS - case - assign $1\reg_c[4:0] 5'00000 - end - sync always - update \reg_c $0\reg_c[4:0] - end - attribute \src "libresoc.v:112284.3-112298.6" - process $proc$libresoc.v:112284$4430 - assign { } { } - assign { } { } - assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:112285.5-112285.29" - switch \initial - attribute \src "libresoc.v:112285.9-112285.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 - case - assign $1\reg_c_ok[0:0] 1'0 - end - sync always - update \reg_c_ok $0\reg_c_ok[0:0] - end -end -attribute \src "libresoc.v:112303.1-112600.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in - attribute \src "libresoc.v:112494.3-112520.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:112521.3-112531.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112472.3-112482.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112532.3-112542.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112543.3-112553.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112445.3-112471.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112581.3-112599.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:112483.3-112493.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112304.7-112304.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:112554.3-112564.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:112565.3-112580.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:112494.3-112520.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112521.3-112531.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112472.3-112482.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112532.3-112542.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112543.3-112553.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112445.3-112471.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112581.3-112599.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:112483.3-112493.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112554.3-112564.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:112565.3-112580.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:112581.3-112599.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:112565.3-112580.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:112438.17-112438.112" - wire $and$libresoc.v:112438$4433_Y - attribute \src "libresoc.v:112440.17-112440.112" - wire $and$libresoc.v:112440$4435_Y - attribute \src "libresoc.v:112437.17-112437.121" - wire $eq$libresoc.v:112437$4432_Y - attribute \src "libresoc.v:112439.17-112439.121" - wire $eq$libresoc.v:112439$4434_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \ALU_FXM + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_LDST_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LDST_br + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LDST_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -175746,470 +189878,691 @@ module \dec_cr_in attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok + wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok + wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:112304.7-112304.15" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:121399.7-121399.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:112438$4433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121827$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:112438$4433_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:121827$4601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:112440$4435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121829$4603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:112440$4435_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:121829$4603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121842$4616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:121842$4616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121843$4617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121843$4617_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121845$4619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:121845$4619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121847$4621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:121847$4621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121848$4622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:121848$4622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121849$4623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121849$4623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:112437$4432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:121830$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:112437$4432_Y + connect \A \dec_LDST_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:121830$4604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:112439$4434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121831$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:112439$4434_Y + connect \A \dec_LDST_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:121831$4605_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:112441.9-112444.4" - cell \ppick \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121833$4607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:121833$4607_Y end - attribute \src "libresoc.v:112304.7-112304.20" - process $proc$libresoc.v:112304$4446 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121834$4608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:121834$4608_Y end - attribute \src "libresoc.v:112445.3-112471.6" - process $proc$libresoc.v:112445$4436 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112446.5-112446.29" - switch \initial - attribute \src "libresoc.v:112446.9-112446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121836$4610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:121836$4610_Y end - attribute \src "libresoc.v:112472.3-112482.6" - process $proc$libresoc.v:112472$4437 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112473.5-112473.29" - switch \initial - attribute \src "libresoc.v:112473.9-112473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:121837$4611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121837$4611_Y end - attribute \src "libresoc.v:112483.3-112493.6" - process $proc$libresoc.v:112483$4438 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112484.5-112484.29" - switch \initial - attribute \src "libresoc.v:112484.9-112484.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121839$4613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:121839$4613_Y end - attribute \src "libresoc.v:112494.3-112520.6" - process $proc$libresoc.v:112494$4439 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112495.5-112495.29" - switch \initial - attribute \src "libresoc.v:112495.9-112495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:121841$4615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121841$4615_Y end - attribute \src "libresoc.v:112521.3-112531.6" - process $proc$libresoc.v:112521$4440 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112522.5-112522.29" - switch \initial - attribute \src "libresoc.v:112522.9-112522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \ALU_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:121844$4618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121844$4618_Y end - attribute \src "libresoc.v:112532.3-112542.6" - process $proc$libresoc.v:112532$4441 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:121850$4624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121850$4624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:121828$4602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121828$4602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:121846$4620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121846$4620_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:121832$4606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:121832$4606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:121835$4609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:121835$4609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:121838$4612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:121838$4612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121840$4614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:121840$4614_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121851.13-121878.4" + cell \dec$166 \dec + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + connect \LDST_LI \dec_LDST_LI + connect \LDST_OE \dec_LDST_OE + connect \LDST_RA \dec_LDST_RA + connect \LDST_Rc \dec_LDST_Rc + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_SPR \dec_LDST_SPR + connect \LDST_UI \dec_LDST_UI + connect \LDST_br \dec_LDST_br + connect \LDST_cr_out \dec_LDST_cr_out + connect \LDST_function_unit \dec_LDST_function_unit + connect \LDST_in1_sel \dec_LDST_in1_sel + connect \LDST_in2_sel \dec_LDST_in2_sel + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_is_32b \dec_LDST_is_32b + connect \LDST_ldst_len \dec_LDST_ldst_len + connect \LDST_rc_sel \dec_LDST_rc_sel + connect \LDST_sgn \dec_LDST_sgn + connect \LDST_sgn_ext \dec_LDST_sgn_ext + connect \LDST_sh \dec_LDST_sh + connect \LDST_upd \dec_LDST_upd + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121879.16-121884.4" + cell \dec_ai$169 \dec_ai + connect \LDST_RA \dec_LDST_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121885.16-121896.4" + cell \dec_bi$170 \dec_bi + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + connect \LDST_LI \dec_LDST_LI + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_sh \dec_LDST_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121897.16-121903.4" + cell \dec_oe$168 \dec_oe + connect \LDST_OE \dec_LDST_OE + connect \LDST_internal_op \dec_LDST_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121904.16-121909.4" + cell \dec_rc$167 \dec_rc + connect \LDST_Rc \dec_LDST_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:121399.7-121399.20" + process $proc$libresoc.v:121399$4627 assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112533.5-112533.29" - switch \initial - attribute \src "libresoc.v:112533.9-112533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \ALU_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end + assign $0\initial[0:0] 1'0 sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:112543.3-112553.6" - process $proc$libresoc.v:112543$4442 + attribute \src "libresoc.v:121910.3-121922.6" + process $proc$libresoc.v:121910$4625 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112544.5-112544.29" + assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] + attribute \src "libresoc.v:121911.5-121911.29" switch \initial - attribute \src "libresoc.v:112544.9-112544.17" + attribute \src "libresoc.v:121911.9-121911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'-1 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:112554.3-112564.6" - process $proc$libresoc.v:112554$4443 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:112555.5-112555.29" - switch \initial - attribute \src "libresoc.v:112555.9-112555.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\LDST__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\LDST__insn_type[6:0] 7'0000000 case - assign $1\move_one[0:0] 1'0 + assign $1\LDST__insn_type[6:0] \dec_LDST_internal_op end sync always - update \move_one $0\move_one[0:0] + update \LDST__insn_type $0\LDST__insn_type[6:0] end - attribute \src "libresoc.v:112565.3-112580.6" - process $proc$libresoc.v:112565$4444 + attribute \src "libresoc.v:121923.3-121937.6" + process $proc$libresoc.v:121923$4626 assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:112566.5-112566.29" + assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0] + attribute \src "libresoc.v:121924.5-121924.29" switch \initial - attribute \src "libresoc.v:112566.9-112566.17" + attribute \src "libresoc.v:121924.9-121924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'-1 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \ALU_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:112581.3-112599.6" - process $proc$libresoc.v:112581$4445 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:112582.5-112582.29" - switch \initial - attribute \src "libresoc.v:112582.9-112582.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\LDST__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:112437$4432_Y - connect \$3 $and$libresoc.v:112438$4433_Y - connect \$5 $eq$libresoc.v:112439$4434_Y - connect \$7 $and$libresoc.v:112440$4435_Y -end -attribute \src "libresoc.v:112604.1-112901.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$143 - attribute \src "libresoc.v:112795.3-112821.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:112822.3-112832.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112773.3-112783.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112833.3-112843.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112844.3-112854.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112746.3-112772.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112882.3-112900.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:112784.3-112794.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112605.7-112605.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:112855.3-112865.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:112866.3-112881.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:112795.3-112821.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112822.3-112832.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112773.3-112783.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112833.3-112843.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112844.3-112854.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112746.3-112772.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112882.3-112900.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:112784.3-112794.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112855.3-112865.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:112866.3-112881.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:112882.3-112900.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:112866.3-112881.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:112739.17-112739.112" - wire $and$libresoc.v:112739$4448_Y - attribute \src "libresoc.v:112741.17-112741.112" - wire $and$libresoc.v:112741$4450_Y - attribute \src "libresoc.v:112738.17-112738.120" - wire $eq$libresoc.v:112738$4447_Y - attribute \src "libresoc.v:112740.17-112740.120" - wire $eq$libresoc.v:112740$4449_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \CR_FXM + assign $1\LDST__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\LDST__fn_unit[13:0] \dec_LDST_function_unit + end + sync always + update \LDST__fn_unit $0\LDST__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:121827$4601_Y + connect \$12 $not$libresoc.v:121828$4602_Y + connect \$14 $and$libresoc.v:121829$4603_Y + connect \$16 $eq$libresoc.v:121830$4604_Y + connect \$18 $eq$libresoc.v:121831$4605_Y + connect \$20 $or$libresoc.v:121832$4606_Y + connect \$22 $eq$libresoc.v:121833$4607_Y + connect \$24 $eq$libresoc.v:121834$4608_Y + connect \$26 $or$libresoc.v:121835$4609_Y + connect \$28 $eq$libresoc.v:121836$4610_Y + connect \$2 $eq$libresoc.v:121837$4611_Y + connect \$30 $or$libresoc.v:121838$4612_Y + connect \$32 $eq$libresoc.v:121839$4613_Y + connect \$34 $or$libresoc.v:121840$4614_Y + connect \$36 $eq$libresoc.v:121841$4615_Y + connect \$38 $and$libresoc.v:121842$4616_Y + connect \$40 $and$libresoc.v:121843$4617_Y + connect \$42 $eq$libresoc.v:121844$4618_Y + connect \$44 $and$libresoc.v:121845$4619_Y + connect \$46 $not$libresoc.v:121846$4620_Y + connect \$48 $and$libresoc.v:121847$4621_Y + connect \$4 $and$libresoc.v:121848$4622_Y + connect \$6 $and$libresoc.v:121849$4623_Y + connect \$8 $eq$libresoc.v:121850$4624_Y + connect \LDST__ldst_mode \dec_LDST_upd + connect \LDST__sign_extend \dec_LDST_sgn_ext + connect \LDST__byte_reverse \dec_LDST_br + connect \LDST__is_signed \dec_LDST_sgn + connect \LDST__is_32bit \dec_LDST_is_32b + connect \LDST__data_len \dec_LDST_ldst_len + connect { \LDST__oe__ok \LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LDST__rc__ok \LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LDST__imm_data__ok \LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LDST_in2_sel + connect \LDST__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LDST_in1_sel + connect \dec_ai_sv_nz \sv_a_nz + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_LDST_SPR [4:0] \dec_LDST_SPR [9:5] } + connect \dec_oe_sel_in \dec_LDST_rc_sel + connect \dec_rc_sel_in \dec_LDST_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LDST__insn \dec_opcode_in +end +attribute \src "libresoc.v:121963.1-122546.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" +attribute \generator "nMigen" +module \dec_LOGICAL + attribute \src "libresoc.v:122509.3-122523.6" + wire width 14 $0\LOGICAL__fn_unit[13:0] + attribute \src "libresoc.v:122496.3-122508.6" + wire width 7 $0\LOGICAL__insn_type[6:0] + attribute \src "libresoc.v:122481.3-122495.6" + wire $0\LOGICAL__write_cr0[0:0] + attribute \src "libresoc.v:121964.7-121964.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:122509.3-122523.6" + wire width 14 $1\LOGICAL__fn_unit[13:0] + attribute \src "libresoc.v:122496.3-122508.6" + wire width 7 $1\LOGICAL__insn_type[6:0] + attribute \src "libresoc.v:122481.3-122495.6" + wire $1\LOGICAL__write_cr0[0:0] + attribute \src "libresoc.v:122397.18-122397.113" + wire $and$libresoc.v:122397$4628_Y + attribute \src "libresoc.v:122399.18-122399.110" + wire $and$libresoc.v:122399$4630_Y + attribute \src "libresoc.v:122412.18-122412.114" + wire $and$libresoc.v:122412$4643_Y + attribute \src "libresoc.v:122413.18-122413.116" + wire $and$libresoc.v:122413$4644_Y + attribute \src "libresoc.v:122415.18-122415.114" + wire $and$libresoc.v:122415$4646_Y + attribute \src "libresoc.v:122417.18-122417.110" + wire $and$libresoc.v:122417$4648_Y + attribute \src "libresoc.v:122418.17-122418.112" + wire $and$libresoc.v:122418$4649_Y + attribute \src "libresoc.v:122419.17-122419.114" + wire $and$libresoc.v:122419$4650_Y + attribute \src "libresoc.v:122400.18-122400.130" + wire $eq$libresoc.v:122400$4631_Y + attribute \src "libresoc.v:122401.18-122401.130" + wire $eq$libresoc.v:122401$4632_Y + attribute \src "libresoc.v:122403.18-122403.110" + wire $eq$libresoc.v:122403$4634_Y + attribute \src "libresoc.v:122404.18-122404.110" + wire $eq$libresoc.v:122404$4635_Y + attribute \src "libresoc.v:122406.18-122406.112" + wire $eq$libresoc.v:122406$4637_Y + attribute \src "libresoc.v:122407.17-122407.134" + wire $eq$libresoc.v:122407$4638_Y + attribute \src "libresoc.v:122409.18-122409.110" + wire $eq$libresoc.v:122409$4640_Y + attribute \src "libresoc.v:122411.18-122411.135" + wire $eq$libresoc.v:122411$4642_Y + attribute \src "libresoc.v:122414.18-122414.135" + wire $eq$libresoc.v:122414$4645_Y + attribute \src "libresoc.v:122420.17-122420.134" + wire $eq$libresoc.v:122420$4651_Y + attribute \src "libresoc.v:122398.18-122398.110" + wire $not$libresoc.v:122398$4629_Y + attribute \src "libresoc.v:122416.18-122416.110" + wire $not$libresoc.v:122416$4647_Y + attribute \src "libresoc.v:122402.18-122402.110" + wire $or$libresoc.v:122402$4633_Y + attribute \src "libresoc.v:122405.18-122405.110" + wire $or$libresoc.v:122405$4636_Y + attribute \src "libresoc.v:122408.18-122408.110" + wire $or$libresoc.v:122408$4639_Y + attribute \src "libresoc.v:122410.18-122410.110" + wire $or$libresoc.v:122410$4641_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 19 \LOGICAL__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 13 \LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \LOGICAL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -176284,470 +190637,112 @@ module \dec_cr_in$143 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:112605.7-112605.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 3 \LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_LOGICAL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_LOGICAL_UI + attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:112739$4448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:112739$4448_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:112741$4450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:112741$4450_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:112738$4447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:112738$4447_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:112740$4449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:112740$4449_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:112742.15-112745.4" - cell \ppick$144 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:112605.7-112605.20" - process $proc$libresoc.v:112605$4461 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:112746.3-112772.6" - process $proc$libresoc.v:112746$4451 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112747.5-112747.29" - switch \initial - attribute \src "libresoc.v:112747.9-112747.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:112773.3-112783.6" - process $proc$libresoc.v:112773$4452 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112774.5-112774.29" - switch \initial - attribute \src "libresoc.v:112774.9-112774.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:112784.3-112794.6" - process $proc$libresoc.v:112784$4453 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112785.5-112785.29" - switch \initial - attribute \src "libresoc.v:112785.9-112785.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:112795.3-112821.6" - process $proc$libresoc.v:112795$4454 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112796.5-112796.29" - switch \initial - attribute \src "libresoc.v:112796.9-112796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:112822.3-112832.6" - process $proc$libresoc.v:112822$4455 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112823.5-112823.29" - switch \initial - attribute \src "libresoc.v:112823.9-112823.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \CR_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:112833.3-112843.6" - process $proc$libresoc.v:112833$4456 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112834.5-112834.29" - switch \initial - attribute \src "libresoc.v:112834.9-112834.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \CR_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:112844.3-112854.6" - process $proc$libresoc.v:112844$4457 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112845.5-112845.29" - switch \initial - attribute \src "libresoc.v:112845.9-112845.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:112855.3-112865.6" - process $proc$libresoc.v:112855$4458 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:112856.5-112856.29" - switch \initial - attribute \src "libresoc.v:112856.9-112856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:112866.3-112881.6" - process $proc$libresoc.v:112866$4459 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:112867.5-112867.29" - switch \initial - attribute \src "libresoc.v:112867.9-112867.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \CR_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:112882.3-112900.6" - process $proc$libresoc.v:112882$4460 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:112883.5-112883.29" - switch \initial - attribute \src "libresoc.v:112883.9-112883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:112738$4447_Y - connect \$3 $and$libresoc.v:112739$4448_Y - connect \$5 $eq$libresoc.v:112740$4449_Y - connect \$7 $and$libresoc.v:112741$4450_Y -end -attribute \src "libresoc.v:112905.1-113202.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$150 - attribute \src "libresoc.v:113096.3-113122.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113123.3-113133.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113074.3-113084.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113134.3-113144.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113145.3-113155.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113047.3-113073.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113183.3-113201.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113085.3-113095.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112906.7-112906.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:113156.3-113166.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:113167.3-113182.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113096.3-113122.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113123.3-113133.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113074.3-113084.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113134.3-113144.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113145.3-113155.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113047.3-113073.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113183.3-113201.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113085.3-113095.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113156.3-113166.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:113167.3-113182.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113183.3-113201.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113167.3-113182.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113040.17-113040.112" - wire $and$libresoc.v:113040$4463_Y - attribute \src "libresoc.v:113042.17-113042.112" - wire $and$libresoc.v:113042$4465_Y - attribute \src "libresoc.v:113039.17-113039.124" - wire $eq$libresoc.v:113039$4462_Y - attribute \src "libresoc.v:113041.17-113041.124" - wire $eq$libresoc.v:113041$4464_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \BRANCH_FXM + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -176822,470 +190817,861 @@ module \dec_cr_in$150 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok + wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok + wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:112906.7-112906.15" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:121964.7-121964.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113040$4463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122397$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:113040$4463_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:122397$4628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113042$4465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122399$4630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:113042$4465_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:122399$4630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122412$4643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:122412$4643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122413$4644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122413$4644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122415$4646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:122415$4646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122417$4648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:122417$4648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122418$4649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:122418$4649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122419$4650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122419$4650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113039$4462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:122400$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113039$4462_Y + connect \A \dec_LOGICAL_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:122400$4631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113041$4464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122401$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113041$4464_Y + connect \A \dec_LOGICAL_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:122401$4632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122403$4634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:122403$4634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122404$4635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:122404$4635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122406$4637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:122406$4637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:122407$4638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122407$4638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122409$4640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:122409$4640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:122411$4642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122411$4642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:122414$4645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122414$4645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:122420$4651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122420$4651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:122398$4629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122398$4629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:122416$4647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122416$4647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:122402$4633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:122402$4633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:122405$4636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:122405$4636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:122408$4639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:122408$4639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122410$4641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:122410$4641_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:113043.15-113046.4" - cell \ppick$151 \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "libresoc.v:122421.13-122449.4" + cell \dec$145 \dec + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_SPR \dec_LOGICAL_SPR + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_cr_out \dec_LOGICAL_cr_out + connect \LOGICAL_cry_in \dec_LOGICAL_cry_in + connect \LOGICAL_cry_out \dec_LOGICAL_cry_out + connect \LOGICAL_function_unit \dec_LOGICAL_function_unit + connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \LOGICAL_inv_a \dec_LOGICAL_inv_a + connect \LOGICAL_inv_out \dec_LOGICAL_inv_out + connect \LOGICAL_is_32b \dec_LOGICAL_is_32b + connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel + connect \LOGICAL_sgn \dec_LOGICAL_sgn + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in end - attribute \src "libresoc.v:112906.7-112906.20" - process $proc$libresoc.v:112906$4476 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \module_not_derived 1 + attribute \src "libresoc.v:122450.16-122455.4" + cell \dec_ai$148 \dec_ai + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz end - attribute \src "libresoc.v:113047.3-113073.6" - process $proc$libresoc.v:113047$4466 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113048.5-113048.29" - switch \initial - attribute \src "libresoc.v:113048.9-113048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:122456.16-122467.4" + cell \dec_bi$149 \dec_bi + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in end - attribute \src "libresoc.v:113074.3-113084.6" - process $proc$libresoc.v:113074$4467 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113075.5-113075.29" - switch \initial - attribute \src "libresoc.v:113075.9-113075.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:122468.16-122474.4" + cell \dec_oe$147 \dec_oe + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in end - attribute \src "libresoc.v:113085.3-113095.6" - process $proc$libresoc.v:113085$4468 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113086.5-113086.29" - switch \initial - attribute \src "libresoc.v:113086.9-113086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:122475.16-122480.4" + cell \dec_rc$146 \dec_rc + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:113096.3-113122.6" - process $proc$libresoc.v:113096$4469 + attribute \src "libresoc.v:121964.7-121964.20" + process $proc$libresoc.v:121964$4655 assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113097.5-113097.29" - switch \initial - attribute \src "libresoc.v:113097.9-113097.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end + assign $0\initial[0:0] 1'0 sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:113123.3-113133.6" - process $proc$libresoc.v:113123$4470 + attribute \src "libresoc.v:122481.3-122495.6" + process $proc$libresoc.v:122481$4652 assign { } { } assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113124.5-113124.29" + assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] + attribute \src "libresoc.v:122482.5-122482.29" switch \initial - attribute \src "libresoc.v:113124.9-113124.17" + attribute \src "libresoc.v:122482.9-122482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + switch \dec_LOGICAL_cr_out attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'001 , 3'101 assign { } { } - assign $1\cr_bitfield_b[2:0] \BRANCH_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:113134.3-113144.6" - process $proc$libresoc.v:113134$4471 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113135.5-113135.29" - switch \initial - attribute \src "libresoc.v:113135.9-113135.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\LOGICAL__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'010 , 3'011 assign { } { } - assign $1\cr_bitfield_o[2:0] \BRANCH_BT [4:2] + assign $1\LOGICAL__write_cr0[0:0] 1'1 case - assign $1\cr_bitfield_o[2:0] 3'000 + assign $1\LOGICAL__write_cr0[0:0] 1'0 end sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] end - attribute \src "libresoc.v:113145.3-113155.6" - process $proc$libresoc.v:113145$4472 + attribute \src "libresoc.v:122496.3-122508.6" + process $proc$libresoc.v:122496$4653 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113146.5-113146.29" + assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] + attribute \src "libresoc.v:122497.5-122497.29" switch \initial - attribute \src "libresoc.v:113146.9-113146.17" + attribute \src "libresoc.v:122497.9-122497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'-1 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:113156.3-113166.6" - process $proc$libresoc.v:113156$4473 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113157.5-113157.29" - switch \initial - attribute \src "libresoc.v:113157.9-113157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\LOGICAL__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\LOGICAL__insn_type[6:0] 7'0000000 case - assign $1\move_one[0:0] 1'0 + assign $1\LOGICAL__insn_type[6:0] \dec_LOGICAL_internal_op end sync always - update \move_one $0\move_one[0:0] + update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] end - attribute \src "libresoc.v:113167.3-113182.6" - process $proc$libresoc.v:113167$4474 - assign { } { } + attribute \src "libresoc.v:122509.3-122523.6" + process $proc$libresoc.v:122509$4654 assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113168.5-113168.29" + assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0] + attribute \src "libresoc.v:122510.5-122510.29" switch \initial - attribute \src "libresoc.v:113168.9-113168.17" + attribute \src "libresoc.v:122510.9-122510.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'-1 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \BRANCH_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:113183.3-113201.6" - process $proc$libresoc.v:113183$4475 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113184.5-113184.29" - switch \initial - attribute \src "libresoc.v:113184.9-113184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\LOGICAL__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:113039$4462_Y - connect \$3 $and$libresoc.v:113040$4463_Y - connect \$5 $eq$libresoc.v:113041$4464_Y - connect \$7 $and$libresoc.v:113042$4465_Y + assign $1\LOGICAL__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\LOGICAL__fn_unit[13:0] \dec_LOGICAL_function_unit + end + sync always + update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:122397$4628_Y + connect \$12 $not$libresoc.v:122398$4629_Y + connect \$14 $and$libresoc.v:122399$4630_Y + connect \$16 $eq$libresoc.v:122400$4631_Y + connect \$18 $eq$libresoc.v:122401$4632_Y + connect \$20 $or$libresoc.v:122402$4633_Y + connect \$22 $eq$libresoc.v:122403$4634_Y + connect \$24 $eq$libresoc.v:122404$4635_Y + connect \$26 $or$libresoc.v:122405$4636_Y + connect \$28 $eq$libresoc.v:122406$4637_Y + connect \$2 $eq$libresoc.v:122407$4638_Y + connect \$30 $or$libresoc.v:122408$4639_Y + connect \$32 $eq$libresoc.v:122409$4640_Y + connect \$34 $or$libresoc.v:122410$4641_Y + connect \$36 $eq$libresoc.v:122411$4642_Y + connect \$38 $and$libresoc.v:122412$4643_Y + connect \$40 $and$libresoc.v:122413$4644_Y + connect \$42 $eq$libresoc.v:122414$4645_Y + connect \$44 $and$libresoc.v:122415$4646_Y + connect \$46 $not$libresoc.v:122416$4647_Y + connect \$48 $and$libresoc.v:122417$4648_Y + connect \$4 $and$libresoc.v:122418$4649_Y + connect \$6 $and$libresoc.v:122419$4650_Y + connect \$8 $eq$libresoc.v:122420$4651_Y + connect \LOGICAL__is_signed \dec_LOGICAL_sgn + connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b + connect \LOGICAL__output_carry \dec_LOGICAL_cry_out + connect \LOGICAL__input_carry \dec_LOGICAL_cry_in + connect \LOGICAL__invert_out \dec_LOGICAL_inv_out + connect \LOGICAL__invert_in \dec_LOGICAL_inv_a + connect \LOGICAL__data_len \dec_LOGICAL_ldst_len + connect { \LOGICAL__oe__ok \LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LOGICAL__rc__ok \LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LOGICAL__imm_data__ok \LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LOGICAL_in2_sel + connect \LOGICAL__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LOGICAL_in1_sel + connect \dec_ai_sv_nz \sv_a_nz + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_LOGICAL_SPR [4:0] \dec_LOGICAL_SPR [9:5] } + connect \dec_oe_sel_in \dec_LOGICAL_rc_sel + connect \dec_rc_sel_in \dec_LOGICAL_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:113206.1-113503.10" +attribute \src "libresoc.v:122550.1-123052.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" -module \dec_cr_in$158 - attribute \src "libresoc.v:113397.3-113423.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113424.3-113434.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113375.3-113385.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113435.3-113445.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113446.3-113456.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113348.3-113374.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113484.3-113502.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113386.3-113396.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113207.7-113207.20" +module \dec_MUL + attribute \src "libresoc.v:123023.3-123037.6" + wire width 14 $0\MUL__fn_unit[13:0] + attribute \src "libresoc.v:123010.3-123022.6" + wire width 7 $0\MUL__insn_type[6:0] + attribute \src "libresoc.v:122995.3-123009.6" + wire $0\MUL__write_cr0[0:0] + attribute \src "libresoc.v:122551.7-122551.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113457.3-113467.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:113468.3-113483.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113397.3-113423.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113424.3-113434.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113375.3-113385.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113435.3-113445.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113446.3-113456.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113348.3-113374.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113484.3-113502.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113386.3-113396.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113457.3-113467.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:113468.3-113483.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113484.3-113502.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113468.3-113483.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113341.17-113341.112" - wire $and$libresoc.v:113341$4478_Y - attribute \src "libresoc.v:113343.17-113343.112" - wire $and$libresoc.v:113343$4480_Y - attribute \src "libresoc.v:113340.17-113340.125" - wire $eq$libresoc.v:113340$4477_Y - attribute \src "libresoc.v:113342.17-113342.125" - wire $eq$libresoc.v:113342$4479_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \LOGICAL_FXM + attribute \src "libresoc.v:123023.3-123037.6" + wire width 14 $1\MUL__fn_unit[13:0] + attribute \src "libresoc.v:123010.3-123022.6" + wire width 7 $1\MUL__insn_type[6:0] + attribute \src "libresoc.v:122995.3-123009.6" + wire $1\MUL__write_cr0[0:0] + attribute \src "libresoc.v:122924.18-122924.113" + wire $and$libresoc.v:122924$4656_Y + attribute \src "libresoc.v:122926.18-122926.110" + wire $and$libresoc.v:122926$4658_Y + attribute \src "libresoc.v:122939.18-122939.114" + wire $and$libresoc.v:122939$4671_Y + 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attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \MUL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_MUL_UI + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_MUL_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -177360,470 +191746,666 @@ module \dec_cr_in$158 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_MUL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok + wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122924$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:113341$4478_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:122924$4656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113343$4480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122926$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:113343$4480_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:122926$4658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122939$4671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:122939$4671_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122940$4672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122940$4672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122942$4674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:122942$4674_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122944$4676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:122944$4676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122945$4677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:122945$4677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122946$4678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122946$4678_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113340$4477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:122927$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113340$4477_Y + connect \A \dec_MUL_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:122927$4659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113342$4479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122928$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113342$4479_Y + connect \A \dec_MUL_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:122928$4660_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:113344.15-113347.4" - cell \ppick$159 \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122930$4662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:122930$4662_Y end - attribute \src "libresoc.v:113207.7-113207.20" - process $proc$libresoc.v:113207$4491 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122931$4663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:122931$4663_Y end - attribute \src "libresoc.v:113348.3-113374.6" - process $proc$libresoc.v:113348$4481 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113349.5-113349.29" - switch \initial - attribute \src "libresoc.v:113349.9-113349.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122933$4665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:122933$4665_Y end - attribute \src "libresoc.v:113375.3-113385.6" - process $proc$libresoc.v:113375$4482 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113376.5-113376.29" - switch \initial - attribute \src "libresoc.v:113376.9-113376.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:122934$4666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122934$4666_Y end - attribute \src "libresoc.v:113386.3-113396.6" - process $proc$libresoc.v:113386$4483 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113387.5-113387.29" - switch \initial - attribute \src "libresoc.v:113387.9-113387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122936$4668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:122936$4668_Y end - attribute \src "libresoc.v:113397.3-113423.6" - process $proc$libresoc.v:113397$4484 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:122938$4670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122938$4670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:122941$4673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122941$4673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:122947$4679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122947$4679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:122925$4657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122925$4657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:122943$4675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122943$4675_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:122929$4661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:122929$4661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:122932$4664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:122932$4664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:122935$4667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:122935$4667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122937$4669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:122937$4669_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122948.13-122969.4" + cell \dec$158 \dec + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + connect \MUL_LI \dec_MUL_LI + connect \MUL_OE \dec_MUL_OE + connect \MUL_Rc \dec_MUL_Rc + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_SPR \dec_MUL_SPR + connect \MUL_UI \dec_MUL_UI + connect \MUL_cr_out \dec_MUL_cr_out + connect \MUL_function_unit \dec_MUL_function_unit + connect \MUL_in2_sel \dec_MUL_in2_sel + connect \MUL_internal_op \dec_MUL_internal_op + connect \MUL_is_32b \dec_MUL_is_32b + connect \MUL_rc_sel \dec_MUL_rc_sel + connect \MUL_sgn \dec_MUL_sgn + connect \MUL_sh \dec_MUL_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122970.16-122981.4" + cell \dec_bi$161 \dec_bi + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + connect \MUL_LI \dec_MUL_LI + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_sh \dec_MUL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122982.16-122988.4" + cell \dec_oe$160 \dec_oe + connect \MUL_OE \dec_MUL_OE + connect \MUL_internal_op \dec_MUL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122989.16-122994.4" + cell \dec_rc$159 \dec_rc + connect \MUL_Rc \dec_MUL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:122551.7-122551.20" + process $proc$libresoc.v:122551$4683 assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113398.5-113398.29" - switch \initial - attribute \src "libresoc.v:113398.9-113398.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end + assign $0\initial[0:0] 1'0 sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:113424.3-113434.6" - process $proc$libresoc.v:113424$4485 + attribute \src "libresoc.v:122995.3-123009.6" + process $proc$libresoc.v:122995$4680 assign { } { } assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113425.5-113425.29" + assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] + attribute \src "libresoc.v:122996.5-122996.29" switch \initial - attribute \src "libresoc.v:113425.9-113425.17" + attribute \src "libresoc.v:122996.9-122996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + switch \dec_MUL_cr_out attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'001 , 3'101 assign { } { } - assign $1\cr_bitfield_b[2:0] \LOGICAL_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:113435.3-113445.6" - process $proc$libresoc.v:113435$4486 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113436.5-113436.29" - switch \initial - attribute \src "libresoc.v:113436.9-113436.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\MUL__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'010 , 3'011 assign { } { } - assign $1\cr_bitfield_o[2:0] \LOGICAL_BT [4:2] + assign $1\MUL__write_cr0[0:0] 1'1 case - assign $1\cr_bitfield_o[2:0] 3'000 + assign $1\MUL__write_cr0[0:0] 1'0 end sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \MUL__write_cr0 $0\MUL__write_cr0[0:0] end - attribute \src "libresoc.v:113446.3-113456.6" - process $proc$libresoc.v:113446$4487 + attribute \src "libresoc.v:123010.3-123022.6" + process $proc$libresoc.v:123010$4681 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113447.5-113447.29" + assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] + attribute \src "libresoc.v:123011.5-123011.29" switch \initial - attribute \src "libresoc.v:113447.9-113447.17" + attribute \src "libresoc.v:123011.9-123011.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'-1 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:113457.3-113467.6" - process $proc$libresoc.v:113457$4488 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113458.5-113458.29" - switch \initial - attribute \src "libresoc.v:113458.9-113458.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\MUL__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\MUL__insn_type[6:0] 7'0000000 case - assign $1\move_one[0:0] 1'0 + assign $1\MUL__insn_type[6:0] \dec_MUL_internal_op end sync always - update \move_one $0\move_one[0:0] + update \MUL__insn_type $0\MUL__insn_type[6:0] end - attribute \src "libresoc.v:113468.3-113483.6" - process $proc$libresoc.v:113468$4489 + attribute \src "libresoc.v:123023.3-123037.6" + process $proc$libresoc.v:123023$4682 assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113469.5-113469.29" + assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] + attribute \src "libresoc.v:123024.5-123024.29" switch \initial - attribute \src "libresoc.v:113469.9-113469.17" + attribute \src "libresoc.v:123024.9-123024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'-1 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \LOGICAL_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:113484.3-113502.6" - process $proc$libresoc.v:113484$4490 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113485.5-113485.29" - switch \initial - attribute \src "libresoc.v:113485.9-113485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\MUL__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:113340$4477_Y - connect \$3 $and$libresoc.v:113341$4478_Y - connect \$5 $eq$libresoc.v:113342$4479_Y - connect \$7 $and$libresoc.v:113343$4480_Y + assign $1\MUL__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\MUL__fn_unit[13:0] \dec_MUL_function_unit + end + sync always + update \MUL__fn_unit $0\MUL__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:122924$4656_Y + connect \$12 $not$libresoc.v:122925$4657_Y + connect \$14 $and$libresoc.v:122926$4658_Y + connect \$16 $eq$libresoc.v:122927$4659_Y + connect \$18 $eq$libresoc.v:122928$4660_Y + connect \$20 $or$libresoc.v:122929$4661_Y + connect \$22 $eq$libresoc.v:122930$4662_Y + connect \$24 $eq$libresoc.v:122931$4663_Y + connect \$26 $or$libresoc.v:122932$4664_Y + connect \$28 $eq$libresoc.v:122933$4665_Y + connect \$2 $eq$libresoc.v:122934$4666_Y + connect \$30 $or$libresoc.v:122935$4667_Y + connect \$32 $eq$libresoc.v:122936$4668_Y + connect \$34 $or$libresoc.v:122937$4669_Y + connect \$36 $eq$libresoc.v:122938$4670_Y + connect \$38 $and$libresoc.v:122939$4671_Y + connect \$40 $and$libresoc.v:122940$4672_Y + connect \$42 $eq$libresoc.v:122941$4673_Y + connect \$44 $and$libresoc.v:122942$4674_Y + connect \$46 $not$libresoc.v:122943$4675_Y + connect \$48 $and$libresoc.v:122944$4676_Y + connect \$4 $and$libresoc.v:122945$4677_Y + connect \$6 $and$libresoc.v:122946$4678_Y + connect \$8 $eq$libresoc.v:122947$4679_Y + connect \MUL__is_signed \dec_MUL_sgn + connect \MUL__is_32bit \dec_MUL_is_32b + connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_MUL_in2_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_MUL_SPR [4:0] \dec_MUL_SPR [9:5] } + connect \dec_oe_sel_in \dec_MUL_rc_sel + connect \dec_rc_sel_in \dec_MUL_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:113507.1-113804.10" +attribute \src "libresoc.v:123056.1-123602.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" -module \dec_cr_in$167 - attribute \src "libresoc.v:113698.3-113724.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113725.3-113735.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113676.3-113686.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113736.3-113746.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113747.3-113757.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113649.3-113675.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113785.3-113803.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113687.3-113697.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113508.7-113508.20" +module \dec_SHIFT_ROT + attribute \src "libresoc.v:123568.3-123582.6" + wire width 14 $0\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:123555.3-123567.6" + wire width 7 $0\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:123540.3-123554.6" + wire $0\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:123057.7-123057.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113758.3-113768.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:113769.3-113784.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113698.3-113724.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113725.3-113735.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113676.3-113686.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113736.3-113746.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113747.3-113757.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113649.3-113675.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113785.3-113803.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113687.3-113697.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113758.3-113768.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:113769.3-113784.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113785.3-113803.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113769.3-113784.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113642.17-113642.112" - wire $and$libresoc.v:113642$4493_Y - attribute \src "libresoc.v:113644.17-113644.112" - wire $and$libresoc.v:113644$4495_Y - attribute \src "libresoc.v:113641.17-113641.121" - wire $eq$libresoc.v:113641$4492_Y - attribute \src "libresoc.v:113643.17-113643.121" - wire $eq$libresoc.v:113643$4494_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \SPR_FXM + attribute \src "libresoc.v:123568.3-123582.6" + wire width 14 $1\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:123555.3-123567.6" + wire width 7 $1\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:123540.3-123554.6" + wire $1\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:123465.18-123465.113" + wire $and$libresoc.v:123465$4684_Y + attribute \src "libresoc.v:123467.18-123467.110" + wire $and$libresoc.v:123467$4686_Y + attribute \src "libresoc.v:123480.18-123480.114" + wire $and$libresoc.v:123480$4699_Y + attribute \src "libresoc.v:123481.18-123481.116" + wire $and$libresoc.v:123481$4700_Y + attribute \src "libresoc.v:123483.18-123483.114" + wire $and$libresoc.v:123483$4702_Y + attribute \src "libresoc.v:123485.18-123485.110" + wire $and$libresoc.v:123485$4704_Y + attribute \src "libresoc.v:123486.17-123486.112" + wire $and$libresoc.v:123486$4705_Y + attribute \src "libresoc.v:123487.17-123487.114" + wire $and$libresoc.v:123487$4706_Y + attribute \src "libresoc.v:123468.18-123468.132" + wire $eq$libresoc.v:123468$4687_Y + attribute \src "libresoc.v:123469.18-123469.132" + wire $eq$libresoc.v:123469$4688_Y + attribute \src "libresoc.v:123471.18-123471.110" + wire $eq$libresoc.v:123471$4690_Y + attribute \src "libresoc.v:123472.18-123472.110" + wire $eq$libresoc.v:123472$4691_Y + attribute \src "libresoc.v:123474.18-123474.112" + wire $eq$libresoc.v:123474$4693_Y + attribute \src "libresoc.v:123475.17-123475.136" + wire $eq$libresoc.v:123475$4694_Y + attribute \src "libresoc.v:123477.18-123477.110" + wire $eq$libresoc.v:123477$4696_Y + attribute \src "libresoc.v:123479.18-123479.137" + wire $eq$libresoc.v:123479$4698_Y + attribute \src "libresoc.v:123482.18-123482.137" + wire $eq$libresoc.v:123482$4701_Y + attribute \src "libresoc.v:123488.17-123488.136" + wire $eq$libresoc.v:123488$4707_Y + attribute \src "libresoc.v:123466.18-123466.110" + wire $not$libresoc.v:123466$4685_Y + attribute \src "libresoc.v:123484.18-123484.110" + wire $not$libresoc.v:123484$4703_Y + attribute \src "libresoc.v:123470.18-123470.110" + wire $or$libresoc.v:123470$4689_Y + attribute \src "libresoc.v:123473.18-123473.110" + wire $or$libresoc.v:123473$4692_Y + attribute \src "libresoc.v:123476.18-123476.110" + wire $or$libresoc.v:123476$4695_Y + attribute \src "libresoc.v:123478.18-123478.110" + wire $or$libresoc.v:123478$4697_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 3 \SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 18 \SHIFT_ROT__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -177898,36 +192480,49 @@ module \dec_cr_in$167 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:113508.7-113508.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \SHIFT_ROT__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -177936,432 +192531,789 @@ module \dec_cr_in$167 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113642$4493 + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SHIFT_ROT_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:123057.7-123057.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123465$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:113642$4493_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:123465$4684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113644$4495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123467$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:113644$4495_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:123467$4686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123480$4699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:123480$4699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123481$4700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123481$4700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123483$4702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:123483$4702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123485$4704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:123485$4704_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123486$4705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:123486$4705_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123487$4706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123487$4706_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113641$4492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:123468$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113641$4492_Y + connect \A \dec_SHIFT_ROT_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:123468$4687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113643$4494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:123469$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113643$4494_Y + connect \A \dec_SHIFT_ROT_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:123469$4688_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:113645.15-113648.4" - cell \ppick$168 \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123471$4690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:123471$4690_Y end - attribute \src "libresoc.v:113508.7-113508.20" - process $proc$libresoc.v:113508$4506 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123472$4691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:123472$4691_Y end - attribute \src "libresoc.v:113649.3-113675.6" - process $proc$libresoc.v:113649$4496 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113650.5-113650.29" - switch \initial - attribute \src "libresoc.v:113650.9-113650.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123474$4693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:123474$4693_Y end - attribute \src "libresoc.v:113676.3-113686.6" - process $proc$libresoc.v:113676$4497 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113677.5-113677.29" - switch \initial - attribute \src "libresoc.v:113677.9-113677.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:123475$4694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123475$4694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123477$4696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:123477$4696_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:123479$4698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123479$4698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:123482$4701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123482$4701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:123488$4707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123488$4707_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:123466$4685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123466$4685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:123484$4703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123484$4703_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:123470$4689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:123470$4689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:123473$4692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:123473$4692_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:123476$4695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:123476$4695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123478$4697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:123478$4697_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123489.13-123514.4" + cell \dec$162 \dec + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_SPR \dec_SHIFT_ROT_SPR + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out + connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_inv_a \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123515.16-123526.4" + cell \dec_bi$165 \dec_bi + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in end - attribute \src "libresoc.v:113687.3-113697.6" - process $proc$libresoc.v:113687$4498 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113688.5-113688.29" - switch \initial - attribute \src "libresoc.v:113688.9-113688.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:123527.16-123533.4" + cell \dec_oe$164 \dec_oe + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in end - attribute \src "libresoc.v:113698.3-113724.6" - process $proc$libresoc.v:113698$4499 - assign { } { } + attribute \module_not_derived 1 + attribute \src "libresoc.v:123534.16-123539.4" + cell \dec_rc$163 \dec_rc + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:123057.7-123057.20" + process $proc$libresoc.v:123057$4711 assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113699.5-113699.29" - switch \initial - attribute \src "libresoc.v:113699.9-113699.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end + assign $0\initial[0:0] 1'0 sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:113725.3-113735.6" - process $proc$libresoc.v:113725$4500 + attribute \src "libresoc.v:123540.3-123554.6" + process $proc$libresoc.v:123540$4708 assign { } { } assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113726.5-113726.29" + assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:123541.5-123541.29" switch \initial - attribute \src "libresoc.v:113726.9-113726.17" + attribute \src "libresoc.v:123541.9-123541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + switch \dec_SHIFT_ROT_cr_out attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'001 , 3'101 assign { } { } - assign $1\cr_bitfield_b[2:0] \SPR_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:113736.3-113746.6" - process $proc$libresoc.v:113736$4501 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113737.5-113737.29" - switch \initial - attribute \src "libresoc.v:113737.9-113737.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\SHIFT_ROT__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'010 , 3'011 assign { } { } - assign $1\cr_bitfield_o[2:0] \SPR_BT [4:2] + assign $1\SHIFT_ROT__write_cr0[0:0] 1'1 case - assign $1\cr_bitfield_o[2:0] 3'000 + assign $1\SHIFT_ROT__write_cr0[0:0] 1'0 end sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] end - attribute \src "libresoc.v:113747.3-113757.6" - process $proc$libresoc.v:113747$4502 + attribute \src "libresoc.v:123555.3-123567.6" + process $proc$libresoc.v:123555$4709 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113748.5-113748.29" + assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:123556.5-123556.29" switch \initial - attribute \src "libresoc.v:113748.9-113748.17" + attribute \src "libresoc.v:123556.9-123556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'-1 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:113758.3-113768.6" - process $proc$libresoc.v:113758$4503 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113759.5-113759.29" - switch \initial - attribute \src "libresoc.v:113759.9-113759.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\SHIFT_ROT__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\SHIFT_ROT__insn_type[6:0] 7'0000000 case - assign $1\move_one[0:0] 1'0 + assign $1\SHIFT_ROT__insn_type[6:0] \dec_SHIFT_ROT_internal_op end sync always - update \move_one $0\move_one[0:0] + update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] end - attribute \src "libresoc.v:113769.3-113784.6" - process $proc$libresoc.v:113769$4504 + attribute \src "libresoc.v:123568.3-123582.6" + process $proc$libresoc.v:123568$4710 assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113770.5-113770.29" + assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:123569.5-123569.29" switch \initial - attribute \src "libresoc.v:113770.9-113770.17" + attribute \src "libresoc.v:123569.9-123569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'-1 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \SPR_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:113785.3-113803.6" - process $proc$libresoc.v:113785$4505 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113786.5-113786.29" - switch \initial - attribute \src "libresoc.v:113786.9-113786.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\SHIFT_ROT__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:113641$4492_Y - connect \$3 $and$libresoc.v:113642$4493_Y - connect \$5 $eq$libresoc.v:113643$4494_Y - connect \$7 $and$libresoc.v:113644$4495_Y + assign $1\SHIFT_ROT__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\SHIFT_ROT__fn_unit[13:0] \dec_SHIFT_ROT_function_unit + end + sync always + update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:123465$4684_Y + connect \$12 $not$libresoc.v:123466$4685_Y + connect \$14 $and$libresoc.v:123467$4686_Y + connect \$16 $eq$libresoc.v:123468$4687_Y + connect \$18 $eq$libresoc.v:123469$4688_Y + connect \$20 $or$libresoc.v:123470$4689_Y + connect \$22 $eq$libresoc.v:123471$4690_Y + connect \$24 $eq$libresoc.v:123472$4691_Y + connect \$26 $or$libresoc.v:123473$4692_Y + connect \$28 $eq$libresoc.v:123474$4693_Y + connect \$2 $eq$libresoc.v:123475$4694_Y + connect \$30 $or$libresoc.v:123476$4695_Y + connect \$32 $eq$libresoc.v:123477$4696_Y + connect \$34 $or$libresoc.v:123478$4697_Y + connect \$36 $eq$libresoc.v:123479$4698_Y + connect \$38 $and$libresoc.v:123480$4699_Y + connect \$40 $and$libresoc.v:123481$4700_Y + connect \$42 $eq$libresoc.v:123482$4701_Y + connect \$44 $and$libresoc.v:123483$4702_Y + connect \$46 $not$libresoc.v:123484$4703_Y + connect \$48 $and$libresoc.v:123485$4704_Y + connect \$4 $and$libresoc.v:123486$4705_Y + connect \$6 $and$libresoc.v:123487$4706_Y + connect \$8 $eq$libresoc.v:123488$4707_Y + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] + connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_SHIFT_ROT_SPR [4:0] \dec_SHIFT_ROT_SPR [9:5] } + connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:113808.1-114105.10" +attribute \src "libresoc.v:123606.1-123984.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" -module \dec_cr_in$174 - attribute \src "libresoc.v:113999.3-114025.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114026.3-114036.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113977.3-113987.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114037.3-114047.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114048.3-114058.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113950.3-113976.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114086.3-114104.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113988.3-113998.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113809.7-113809.20" +module \dec_SPR + attribute \src "libresoc.v:123960.3-123974.6" + wire width 14 $0\SPR__fn_unit[13:0] + attribute \src "libresoc.v:123947.3-123959.6" + wire width 7 $0\SPR__insn_type[6:0] + attribute \src "libresoc.v:123607.7-123607.20" wire $0\initial[0:0] - attribute \src "libresoc.v:114059.3-114069.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:114070.3-114085.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113999.3-114025.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114026.3-114036.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113977.3-113987.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114037.3-114047.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114048.3-114058.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113950.3-113976.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114086.3-114104.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113988.3-113998.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114059.3-114069.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:114070.3-114085.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:114086.3-114104.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:114070.3-114085.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113943.17-113943.112" - wire $and$libresoc.v:113943$4508_Y - attribute \src "libresoc.v:113945.17-113945.112" - wire $and$libresoc.v:113945$4510_Y - attribute \src "libresoc.v:113942.17-113942.121" - wire $eq$libresoc.v:113942$4507_Y - attribute \src "libresoc.v:113944.17-113944.121" - wire $eq$libresoc.v:113944$4509_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \DIV_FXM + attribute \src "libresoc.v:123960.3-123974.6" + wire width 14 $1\SPR__fn_unit[13:0] + attribute \src "libresoc.v:123947.3-123959.6" + wire width 7 $1\SPR__insn_type[6:0] + attribute \src "libresoc.v:123901.18-123901.113" + wire $and$libresoc.v:123901$4712_Y + attribute \src "libresoc.v:123903.18-123903.110" + wire $and$libresoc.v:123903$4714_Y + attribute \src "libresoc.v:123916.18-123916.114" + wire $and$libresoc.v:123916$4727_Y + attribute \src "libresoc.v:123917.18-123917.116" + wire $and$libresoc.v:123917$4728_Y + attribute \src "libresoc.v:123919.18-123919.114" + wire $and$libresoc.v:123919$4730_Y + attribute \src "libresoc.v:123921.18-123921.110" + wire $and$libresoc.v:123921$4732_Y + attribute \src "libresoc.v:123922.17-123922.112" + wire $and$libresoc.v:123922$4733_Y + attribute \src "libresoc.v:123923.17-123923.114" + wire $and$libresoc.v:123923$4734_Y + attribute \src "libresoc.v:123904.18-123904.126" + wire $eq$libresoc.v:123904$4715_Y + attribute \src "libresoc.v:123905.18-123905.126" + wire $eq$libresoc.v:123905$4716_Y + attribute \src "libresoc.v:123907.18-123907.110" + wire $eq$libresoc.v:123907$4718_Y + attribute \src "libresoc.v:123908.18-123908.110" + wire $eq$libresoc.v:123908$4719_Y + attribute \src "libresoc.v:123910.18-123910.112" + wire $eq$libresoc.v:123910$4721_Y + attribute \src "libresoc.v:123911.17-123911.130" + wire $eq$libresoc.v:123911$4722_Y + attribute \src "libresoc.v:123913.18-123913.110" + wire $eq$libresoc.v:123913$4724_Y + attribute \src "libresoc.v:123915.18-123915.131" + wire $eq$libresoc.v:123915$4726_Y + attribute \src "libresoc.v:123918.18-123918.131" + wire $eq$libresoc.v:123918$4729_Y + attribute \src "libresoc.v:123924.17-123924.130" + wire $eq$libresoc.v:123924$4735_Y + attribute \src "libresoc.v:123902.18-123902.110" + wire $not$libresoc.v:123902$4713_Y + attribute \src "libresoc.v:123920.18-123920.110" + wire $not$libresoc.v:123920$4731_Y + attribute \src "libresoc.v:123906.18-123906.110" + wire $or$libresoc.v:123906$4717_Y + attribute \src "libresoc.v:123909.18-123909.110" + wire $or$libresoc.v:123909$4720_Y + attribute \src "libresoc.v:123912.18-123912.110" + wire $or$libresoc.v:123912$4723_Y + attribute \src "libresoc.v:123914.18-123914.110" + wire $or$libresoc.v:123914$4725_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + wire \$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 3 \SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \SPR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -178436,470 +193388,45 @@ module \dec_cr_in$174 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:113809.7-113809.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_SPR_SPR + attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113943$4508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:113943$4508_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113945$4510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:113945$4510_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113942$4507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113942$4507_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113944$4509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113944$4509_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:113946.15-113949.4" - cell \ppick$175 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:113809.7-113809.20" - process $proc$libresoc.v:113809$4521 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:113950.3-113976.6" - process $proc$libresoc.v:113950$4511 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113951.5-113951.29" - switch \initial - attribute \src "libresoc.v:113951.9-113951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:113977.3-113987.6" - process $proc$libresoc.v:113977$4512 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113978.5-113978.29" - switch \initial - attribute \src "libresoc.v:113978.9-113978.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:113988.3-113998.6" - process $proc$libresoc.v:113988$4513 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113989.5-113989.29" - switch \initial - attribute \src "libresoc.v:113989.9-113989.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:113999.3-114025.6" - process $proc$libresoc.v:113999$4514 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114000.5-114000.29" - switch \initial - attribute \src "libresoc.v:114000.9-114000.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:114026.3-114036.6" - process $proc$libresoc.v:114026$4515 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - 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case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:114048.3-114058.6" - process $proc$libresoc.v:114048$4517 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114049.5-114049.29" - switch \initial - attribute \src "libresoc.v:114049.9-114049.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:114059.3-114069.6" - process $proc$libresoc.v:114059$4518 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:114060.5-114060.29" - switch \initial - attribute \src "libresoc.v:114060.9-114060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:114070.3-114085.6" - process $proc$libresoc.v:114070$4519 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:114071.5-114071.29" - switch \initial - attribute \src "libresoc.v:114071.9-114071.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - 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- assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:113942$4507_Y - connect \$3 $and$libresoc.v:113943$4508_Y - connect \$5 $eq$libresoc.v:113944$4509_Y - connect \$7 $and$libresoc.v:113945$4510_Y -end -attribute \src "libresoc.v:114109.1-114406.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$183 - attribute \src "libresoc.v:114300.3-114326.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114327.3-114337.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114278.3-114288.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114338.3-114348.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114349.3-114359.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114251.3-114277.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114387.3-114405.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:114289.3-114299.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114110.7-114110.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:114360.3-114370.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:114371.3-114386.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:114300.3-114326.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114327.3-114337.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114278.3-114288.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114338.3-114348.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114349.3-114359.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114251.3-114277.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114387.3-114405.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:114289.3-114299.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114360.3-114370.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:114371.3-114386.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:114387.3-114405.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:114371.3-114386.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:114244.17-114244.112" - wire $and$libresoc.v:114244$4523_Y - attribute \src "libresoc.v:114246.17-114246.112" - wire $and$libresoc.v:114246$4525_Y - attribute \src "libresoc.v:114243.17-114243.121" - wire $eq$libresoc.v:114243$4522_Y - attribute \src "libresoc.v:114245.17-114245.121" - wire $eq$libresoc.v:114245$4524_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \MUL_FXM + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_SPR_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -178974,470 +193501,571 @@ module \dec_cr_in$183 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:114110.7-114110.15" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_SPR_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:123607.7-123607.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114244$4523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 6 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123901$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:114244$4523_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:123901$4712_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114246$4525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123903$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:114246$4525_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:123903$4714_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123916$4727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:123916$4727_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123917$4728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123917$4728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123919$4730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:123919$4730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123921$4732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:123921$4732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123922$4733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:123922$4733_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123923$4734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123923$4734_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114243$4522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:123904$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114243$4522_Y + connect \A \dec_SPR_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:123904$4715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114245$4524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:123905$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114245$4524_Y + connect \A \dec_SPR_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:123905$4716_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:114247.15-114250.4" - cell \ppick$184 \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123907$4718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:123907$4718_Y end - attribute \src "libresoc.v:114110.7-114110.20" - process $proc$libresoc.v:114110$4536 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123908$4719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:123908$4719_Y end - attribute \src "libresoc.v:114251.3-114277.6" - process $proc$libresoc.v:114251$4526 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114252.5-114252.29" - switch \initial - attribute \src "libresoc.v:114252.9-114252.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123910$4721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:123910$4721_Y end - attribute \src "libresoc.v:114278.3-114288.6" - process $proc$libresoc.v:114278$4527 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114279.5-114279.29" - switch \initial - attribute \src "libresoc.v:114279.9-114279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:123911$4722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123911$4722_Y end - attribute \src "libresoc.v:114289.3-114299.6" - process $proc$libresoc.v:114289$4528 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114290.5-114290.29" - switch \initial - attribute \src "libresoc.v:114290.9-114290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123913$4724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:123913$4724_Y end - attribute \src "libresoc.v:114300.3-114326.6" - process $proc$libresoc.v:114300$4529 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114301.5-114301.29" - switch \initial - attribute \src "libresoc.v:114301.9-114301.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:123915$4726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123915$4726_Y end - attribute \src "libresoc.v:114327.3-114337.6" - process $proc$libresoc.v:114327$4530 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114328.5-114328.29" - switch \initial - attribute \src "libresoc.v:114328.9-114328.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \MUL_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:123918$4729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123918$4729_Y end - attribute \src "libresoc.v:114338.3-114348.6" - process $proc$libresoc.v:114338$4531 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:123924$4735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123924$4735_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:123902$4713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123902$4713_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:123920$4731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123920$4731_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:123906$4717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:123906$4717_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:123909$4720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:123909$4720_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:123912$4723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:123912$4723_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123914$4725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:123914$4725_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123925.13-123937.4" + cell \dec$150 \dec + connect \SPR_OE \dec_SPR_OE + connect \SPR_Rc \dec_SPR_Rc + connect \SPR_SPR \dec_SPR_SPR + connect \SPR_cr_out \dec_SPR_cr_out + connect \SPR_function_unit \dec_SPR_function_unit + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_is_32b \dec_SPR_is_32b + connect \SPR_rc_sel \dec_SPR_rc_sel + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123938.16-123942.4" + cell \dec_oe$152 \dec_oe + connect \SPR_OE \dec_SPR_OE + connect \SPR_internal_op \dec_SPR_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123943.16-123946.4" + cell \dec_rc$151 \dec_rc + connect \SPR_Rc \dec_SPR_Rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:123607.7-123607.20" + process $proc$libresoc.v:123607$4738 assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114339.5-114339.29" - switch \initial - attribute \src "libresoc.v:114339.9-114339.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \MUL_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end + assign $0\initial[0:0] 1'0 sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:114349.3-114359.6" - process $proc$libresoc.v:114349$4532 + attribute \src "libresoc.v:123947.3-123959.6" + process $proc$libresoc.v:123947$4736 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114350.5-114350.29" + assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] + attribute \src "libresoc.v:123948.5-123948.29" switch \initial - attribute \src "libresoc.v:114350.9-114350.17" + attribute \src "libresoc.v:123948.9-123948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'-1 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:114360.3-114370.6" - process $proc$libresoc.v:114360$4533 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:114361.5-114361.29" - switch \initial - attribute \src "libresoc.v:114361.9-114361.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\SPR__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\SPR__insn_type[6:0] 7'0000000 case - assign $1\move_one[0:0] 1'0 + assign $1\SPR__insn_type[6:0] \dec_SPR_internal_op end sync always - update \move_one $0\move_one[0:0] + update \SPR__insn_type $0\SPR__insn_type[6:0] end - attribute \src "libresoc.v:114371.3-114386.6" - process $proc$libresoc.v:114371$4534 - assign { } { } + attribute \src "libresoc.v:123960.3-123974.6" + process $proc$libresoc.v:123960$4737 assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:114372.5-114372.29" + assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] + attribute \src "libresoc.v:123961.5-123961.29" switch \initial - attribute \src "libresoc.v:114372.9-114372.17" + attribute \src "libresoc.v:123961.9-123961.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'-1 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \MUL_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:114387.3-114405.6" - process $proc$libresoc.v:114387$4535 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:114388.5-114388.29" - switch \initial - attribute \src "libresoc.v:114388.9-114388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + assign $1\SPR__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'1- assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:114243$4522_Y - connect \$3 $and$libresoc.v:114244$4523_Y - connect \$5 $eq$libresoc.v:114245$4524_Y - connect \$7 $and$libresoc.v:114246$4525_Y + assign $1\SPR__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\SPR__fn_unit[13:0] \dec_SPR_function_unit + end + sync always + update \SPR__fn_unit $0\SPR__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:123901$4712_Y + connect \$12 $not$libresoc.v:123902$4713_Y + connect \$14 $and$libresoc.v:123903$4714_Y + connect \$16 $eq$libresoc.v:123904$4715_Y + connect \$18 $eq$libresoc.v:123905$4716_Y + connect \$20 $or$libresoc.v:123906$4717_Y + connect \$22 $eq$libresoc.v:123907$4718_Y + connect \$24 $eq$libresoc.v:123908$4719_Y + connect \$26 $or$libresoc.v:123909$4720_Y + connect \$28 $eq$libresoc.v:123910$4721_Y + connect \$2 $eq$libresoc.v:123911$4722_Y + connect \$30 $or$libresoc.v:123912$4723_Y + connect \$32 $eq$libresoc.v:123913$4724_Y + connect \$34 $or$libresoc.v:123914$4725_Y + connect \$36 $eq$libresoc.v:123915$4726_Y + connect \$38 $and$libresoc.v:123916$4727_Y + connect \$40 $and$libresoc.v:123917$4728_Y + connect \$42 $eq$libresoc.v:123918$4729_Y + connect \$44 $and$libresoc.v:123919$4730_Y + connect \$46 $not$libresoc.v:123920$4731_Y + connect \$48 $and$libresoc.v:123921$4732_Y + connect \$4 $and$libresoc.v:123922$4733_Y + connect \$6 $and$libresoc.v:123923$4734_Y + connect \$8 $eq$libresoc.v:123924$4735_Y + connect \SPR__is_32bit \dec_SPR_is_32b + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_SPR_SPR [4:0] \dec_SPR_SPR [9:5] } + connect \dec_oe_sel_in \dec_SPR_rc_sel + connect \dec_rc_sel_in \dec_SPR_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:114410.1-114707.10" +attribute \src "libresoc.v:123988.1-124517.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" -module \dec_cr_in$191 - attribute \src "libresoc.v:114601.3-114627.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114628.3-114638.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114579.3-114589.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114639.3-114649.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114650.3-114660.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114552.3-114578.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114688.3-114706.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:114590.3-114600.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114411.7-114411.20" +module \dec_a + attribute \src "libresoc.v:124445.3-124480.6" + wire width 3 $0\fast_a[2:0] + attribute \src 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+ attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute 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\enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok + wire width 10 output 6 \spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o + wire output 7 \spr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok + wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + wire width 10 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0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \$25 + connect \Y $and$libresoc.v:124397$4749_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + cell $and $and$libresoc.v:124402$4754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \B \$35 + connect \Y $and$libresoc.v:124402$4754_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $eq $eq$libresoc.v:124390$4742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:124390$4742_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" + cell $eq $eq$libresoc.v:124391$4743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:124391$4743_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" + cell $eq $eq$libresoc.v:124392$4744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:124392$4744_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $eq $eq$libresoc.v:124393$4745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:124393$4745_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $eq $eq$libresoc.v:124399$4751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:124399$4751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $eq $eq$libresoc.v:124403$4755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:124403$4755_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $ne $ne$libresoc.v:124394$4746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:124394$4746_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $ne $ne$libresoc.v:124395$4747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $ne$libresoc.v:124395$4747_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $ne $ne$libresoc.v:124404$4756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:124404$4756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114547$4540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $ne $ne$libresoc.v:124405$4757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $ne$libresoc.v:124405$4757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $not $not$libresoc.v:124400$4752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:124400$4752_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + cell $not $not$libresoc.v:124401$4753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [5] + connect \Y $not$libresoc.v:124401$4753_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $or $or$libresoc.v:124387$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:114547$4540_Y + connect \B \$7 + connect \Y $or$libresoc.v:124387$4739_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114544$4537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $or $or$libresoc.v:124389$4741 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114544$4537_Y + connect \A \$1 + connect \B \$11 + connect \Y $or$libresoc.v:124389$4741_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114546$4539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $or $or$libresoc.v:124396$4748 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114546$4539_Y + connect \A \$21 + connect \B \$23 + connect \Y $or$libresoc.v:124396$4748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $or $or$libresoc.v:124398$4750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \$27 + connect \Y $or$libresoc.v:124398$4750_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:114548.15-114551.4" - cell \ppick$192 \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "libresoc.v:124406.10-124412.4" + cell \sprmap \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:114411.7-114411.20" - process $proc$libresoc.v:114411$4551 + attribute \src "libresoc.v:123989.7-123989.20" + process $proc$libresoc.v:123989$4764 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114552.3-114578.6" - process $proc$libresoc.v:114552$4541 + attribute \src "libresoc.v:124413.3-124428.6" + process $proc$libresoc.v:124413$4758 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114553.5-114553.29" + assign { } { } + assign $0\reg_a[4:0] $2\reg_a[4:0] + attribute \src "libresoc.v:124414.5-124414.29" switch \initial - attribute \src "libresoc.v:114553.9-114553.17" + attribute \src "libresoc.v:124414.9-124414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + switch \$13 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\reg_a[4:0] \ra + case + assign $1\reg_a[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + switch \$15 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 1'1 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $2\reg_a[4:0] \rs case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $2\reg_a[4:0] $1\reg_a[4:0] end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:114579.3-114589.6" - process $proc$libresoc.v:114579$4542 + attribute \src "libresoc.v:124429.3-124444.6" + process $proc$libresoc.v:124429$4759 assign { } { } assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114580.5-114580.29" + assign { } { } + assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] + attribute \src "libresoc.v:124430.5-124430.29" switch \initial - attribute \src "libresoc.v:114580.9-114580.17" + attribute \src "libresoc.v:124430.9-124430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + switch \$29 attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:114590.3-114600.6" - process $proc$libresoc.v:114590$4543 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114591.5-114591.29" - switch \initial - attribute \src "libresoc.v:114591.9-114591.17" case 1'1 + assign { } { } + assign $1\reg_a_ok[0:0] 1'1 case + assign $1\reg_a_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + switch \$31 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 1'1 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $2\reg_a_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:114601.3-114627.6" - process $proc$libresoc.v:114601$4544 + attribute \src "libresoc.v:124445.3-124480.6" + process $proc$libresoc.v:124445$4760 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114602.5-114602.29" + assign { } { } + assign { } { } + assign $0\fast_a[2:0] $1\fast_a[2:0] + assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] + attribute \src "libresoc.v:124446.5-124446.29" switch \initial - attribute \src "libresoc.v:114602.9-114602.17" + attribute \src "libresoc.v:124446.9-124446.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 7'0000111 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BI [4:2] + assign $1\fast_a[2:0] $2\fast_a[2:0] + assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'1 + case + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 7'0001000 assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BA [4:2] + assign $1\fast_a[2:0] $3\fast_a[2:0] + assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'1 + case + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 7'0101110 assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:114628.3-114638.6" - process $proc$libresoc.v:114628$4545 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114629.5-114629.29" - switch \initial - attribute \src "libresoc.v:114629.9-114629.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\cr_bitfield_b[2:0] \SHIFT_ROT_BB [4:2] + assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } case - assign $1\cr_bitfield_b[2:0] 3'000 + assign $1\fast_a[2:0] 3'000 + assign $1\fast_a_ok[0:0] 1'0 end sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] + update \fast_a $0\fast_a[2:0] + update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:114639.3-114649.6" - process $proc$libresoc.v:114639$4546 + attribute \src "libresoc.v:124481.3-124491.6" + process $proc$libresoc.v:124481$4761 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114640.5-114640.29" + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:124482.5-124482.29" switch \initial - attribute \src "libresoc.v:114640.9-114640.17" + attribute \src "libresoc.v:124482.9-124482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 7'0101110 assign { } { } - assign $1\cr_bitfield_o[2:0] \SHIFT_ROT_BT [4:2] + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case - assign $1\cr_bitfield_o[2:0] 3'000 + assign $1\spr[9:0] 10'0000000000 end sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \spr $0\spr[9:0] end - attribute \src "libresoc.v:114650.3-114660.6" - process $proc$libresoc.v:114650$4547 + attribute \src "libresoc.v:124492.3-124502.6" + process $proc$libresoc.v:124492$4762 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114651.5-114651.29" + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:124493.5-124493.29" switch \initial - attribute \src "libresoc.v:114651.9-114651.17" + attribute \src "libresoc.v:124493.9-124493.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 7'0101110 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 + assign $1\sprmap_spr_i[9:0] \spr case - assign $1\cr_bitfield_o_ok[0:0] 1'0 + assign $1\sprmap_spr_i[9:0] 10'0000000000 end sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:114661.3-114671.6" - process $proc$libresoc.v:114661$4548 + attribute \src "libresoc.v:124503.3-124514.6" + process $proc$libresoc.v:124503$4763 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:114662.5-114662.29" - switch \initial - attribute \src "libresoc.v:114662.9-114662.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:114672.3-114687.6" - process $proc$libresoc.v:114672$4549 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:114673.5-114673.29" + assign $0\spr_a[9:0] $1\spr_a[9:0] + assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] + attribute \src "libresoc.v:124504.5-124504.29" switch \initial - attribute \src "libresoc.v:114673.9-114673.17" + attribute \src "libresoc.v:124504.9-124504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 7'0101110 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \SHIFT_ROT_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:114688.3-114706.6" - process $proc$libresoc.v:114688$4550 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:114689.5-114689.29" - switch \initial - attribute \src "libresoc.v:114689.9-114689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \spr_a $0\spr_a[9:0] + update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$1 $eq$libresoc.v:114544$4537_Y - connect \$3 $and$libresoc.v:114545$4538_Y - connect \$5 $eq$libresoc.v:114546$4539_Y - connect \$7 $and$libresoc.v:114547$4540_Y + connect \$9 $or$libresoc.v:124387$4739_Y + connect \$11 $and$libresoc.v:124388$4740_Y + connect \$13 $or$libresoc.v:124389$4741_Y + connect \$15 $eq$libresoc.v:124390$4742_Y + connect \$17 $eq$libresoc.v:124391$4743_Y + connect \$1 $eq$libresoc.v:124392$4744_Y + connect \$19 $eq$libresoc.v:124393$4745_Y + connect \$21 $ne$libresoc.v:124394$4746_Y + connect \$23 $ne$libresoc.v:124395$4747_Y + connect \$25 $or$libresoc.v:124396$4748_Y + connect \$27 $and$libresoc.v:124397$4749_Y + connect \$29 $or$libresoc.v:124398$4750_Y + connect \$31 $eq$libresoc.v:124399$4751_Y + connect \$33 $not$libresoc.v:124400$4752_Y + connect \$35 $not$libresoc.v:124401$4753_Y + connect \$37 $and$libresoc.v:124402$4754_Y + connect \$3 $eq$libresoc.v:124403$4755_Y + connect \$5 $ne$libresoc.v:124404$4756_Y + connect \$7 $ne$libresoc.v:124405$4757_Y + connect \rs \RS + connect \ra \RA end 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire output 2 \immz_out + attribute \src "libresoc.v:124522.7-124522.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + wire width 5 \ra + attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114846$4553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire input 4 \sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:124550$4765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:114846$4553_Y + connect \A \$5 + connect \B \$7 + connect \Y $and$libresoc.v:124550$4765_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114848$4555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $and $and$libresoc.v:124553$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:114848$4555_Y + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:124553$4768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114845$4552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124551$4766 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114845$4552_Y + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:124551$4766_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114847$4554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124552$4767 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114847$4554_Y + connect \A \ra + connect \B 5'00000 + connect \Y $eq$libresoc.v:124552$4767_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:114849.15-114852.4" - cell \ppick$200 \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:124554$4769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $eq$libresoc.v:124554$4769_Y end - attribute \src "libresoc.v:114712.7-114712.20" - process $proc$libresoc.v:114712$4566 + attribute \src "libresoc.v:124522.7-124522.20" + process $proc$libresoc.v:124522$4771 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114853.3-114879.6" - process $proc$libresoc.v:114853$4556 + attribute \src "libresoc.v:124555.3-124564.6" + process $proc$libresoc.v:124555$4770 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114854.5-114854.29" + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "libresoc.v:124556.5-124556.29" switch \initial - attribute \src "libresoc.v:114854.9-114854.17" + attribute \src "libresoc.v:124556.9-124556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + switch \$9 attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:114880.3-114890.6" - process $proc$libresoc.v:114880$4557 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114881.5-114881.29" - switch \initial - attribute \src "libresoc.v:114881.9-114881.17" case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 + assign $1\immz_out[0:0] 1'1 case - assign $1\cr_bitfield_b_ok[0:0] 1'0 + assign $1\immz_out[0:0] 1'0 end sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + update \immz_out $0\immz_out[0:0] end - attribute \src "libresoc.v:114891.3-114901.6" - process $proc$libresoc.v:114891$4558 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114892.5-114892.29" - switch \initial - attribute \src "libresoc.v:114892.9-114892.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + connect \$9 $and$libresoc.v:124550$4765_Y + connect \$1 $eq$libresoc.v:124551$4766_Y + connect \$3 $eq$libresoc.v:124552$4767_Y + connect \$5 $and$libresoc.v:124553$4768_Y + connect \$7 $eq$libresoc.v:124554$4769_Y + connect \ra \ALU_RA +end +attribute \src "libresoc.v:124570.1-124615.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" +attribute \generator "nMigen" +module \dec_ai$148 + attribute \src "libresoc.v:124604.3-124613.6" + wire $0\immz_out[0:0] + attribute \src "libresoc.v:124571.7-124571.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:124604.3-124613.6" + wire $1\immz_out[0:0] + attribute \src "libresoc.v:124599.17-124599.107" + wire $and$libresoc.v:124599$4772_Y + attribute \src "libresoc.v:124602.17-124602.107" + wire $and$libresoc.v:124602$4775_Y + attribute \src "libresoc.v:124600.17-124600.111" + wire $eq$libresoc.v:124600$4773_Y + attribute \src "libresoc.v:124601.17-124601.108" + wire $eq$libresoc.v:124601$4774_Y + attribute \src "libresoc.v:124603.17-124603.110" + wire $eq$libresoc.v:124603$4776_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire output 2 \immz_out + attribute \src "libresoc.v:124571.7-124571.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire input 4 \sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:124599$4772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $and$libresoc.v:124599$4772_Y end - attribute \src "libresoc.v:114902.3-114928.6" - process $proc$libresoc.v:114902$4559 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114903.5-114903.29" - switch \initial - attribute \src "libresoc.v:114903.9-114903.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $and $and$libresoc.v:124602$4775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:124602$4775_Y end - attribute \src "libresoc.v:114929.3-114939.6" - process $proc$libresoc.v:114929$4560 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124600$4773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:124600$4773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124601$4774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$libresoc.v:124601$4774_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:124603$4776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $eq$libresoc.v:124603$4776_Y + end + attribute \src "libresoc.v:124571.7-124571.20" + process $proc$libresoc.v:124571$4778 assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114930.5-114930.29" - switch \initial - attribute \src "libresoc.v:114930.9-114930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \LDST_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end + assign $0\initial[0:0] 1'0 sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:114940.3-114950.6" - process $proc$libresoc.v:114940$4561 + attribute \src "libresoc.v:124604.3-124613.6" + process $proc$libresoc.v:124604$4777 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114941.5-114941.29" + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "libresoc.v:124605.5-124605.29" switch \initial - attribute \src "libresoc.v:114941.9-114941.17" + attribute \src "libresoc.v:124605.9-124605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + switch \$9 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_bitfield_o[2:0] \LDST_BT [4:2] + assign $1\immz_out[0:0] 1'1 case - assign $1\cr_bitfield_o[2:0] 3'000 + assign $1\immz_out[0:0] 1'0 end sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \immz_out $0\immz_out[0:0] end - attribute \src "libresoc.v:114951.3-114961.6" - process $proc$libresoc.v:114951$4562 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114952.5-114952.29" - switch \initial - attribute \src "libresoc.v:114952.9-114952.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end + connect \$9 $and$libresoc.v:124599$4772_Y + connect \$1 $eq$libresoc.v:124600$4773_Y + connect \$3 $eq$libresoc.v:124601$4774_Y + connect \$5 $and$libresoc.v:124602$4775_Y + connect \$7 $eq$libresoc.v:124603$4776_Y + connect \ra \LOGICAL_RA +end +attribute \src "libresoc.v:124619.1-124664.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" +attribute \generator "nMigen" +module \dec_ai$156 + attribute \src "libresoc.v:124653.3-124662.6" + wire $0\immz_out[0:0] + attribute \src "libresoc.v:124620.7-124620.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:124653.3-124662.6" + wire $1\immz_out[0:0] + attribute \src "libresoc.v:124648.17-124648.107" + wire $and$libresoc.v:124648$4779_Y + attribute \src "libresoc.v:124651.17-124651.107" + wire $and$libresoc.v:124651$4782_Y + attribute \src "libresoc.v:124649.17-124649.111" + wire $eq$libresoc.v:124649$4780_Y + attribute \src "libresoc.v:124650.17-124650.108" + wire $eq$libresoc.v:124650$4781_Y + attribute \src "libresoc.v:124652.17-124652.110" + wire $eq$libresoc.v:124652$4783_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire output 2 \immz_out + attribute \src "libresoc.v:124620.7-124620.15" + wire \initial + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 2 \reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \reg_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + wire width 4 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124845$4795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \RB + connect \Y $extend$libresoc.v:124845$4795_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124846$4797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \RS + connect \Y $extend$libresoc.v:124846$4797_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + cell $not $not$libresoc.v:124844$4794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:124844$4794_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + cell $not $not$libresoc.v:124848$4800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:124848$4800_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124845$4796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:124845$4795_Y + connect \Y $pos$libresoc.v:124845$4796_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124846$4798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:124846$4797_Y + connect \Y $pos$libresoc.v:124846$4798_Y end - attribute \src "libresoc.v:115013.7-115013.20" - process $proc$libresoc.v:115013$4581 + attribute \src "libresoc.v:124718.7-124718.20" + process $proc$libresoc.v:124718$4805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115162.3-115188.6" - process $proc$libresoc.v:115162$4571 + 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"libresoc.v:124880.5-124880.29" + switch \initial + attribute \src "libresoc.v:124880.9-124880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + switch \$5 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 1'1 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\fast_b[2:0] $2\fast_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + switch { \XL_XO [5] \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b[2:0] 3'010 + case + assign $2\fast_b[2:0] 3'000 + end case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\fast_b[2:0] 3'000 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:115189.3-115199.6" - process $proc$libresoc.v:115189$4572 + attribute \src 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1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + case + assign $2\fast_b_ok[0:0] 1'0 + end case - assign $1\cr_bitfield_b_ok[0:0] 1'0 + assign $1\fast_b_ok[0:0] 1'0 end sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + update \fast_b_ok $0\fast_b_ok[0:0] + end + connect \$9 $eq$libresoc.v:124843$4793_Y + connect \$11 $not$libresoc.v:124844$4794_Y + connect \$1 $pos$libresoc.v:124845$4796_Y + connect \$3 $pos$libresoc.v:124846$4798_Y + connect \$5 $eq$libresoc.v:124847$4799_Y + connect \$7 $not$libresoc.v:124848$4800_Y +end +attribute \src "libresoc.v:124919.1-125172.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" +attribute \generator "nMigen" +module \dec_bi + attribute \src "libresoc.v:125146.3-125156.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:125157.3-125167.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:125008.3-125054.6" + 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+ parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \ALU_UI + connect \Y $extend$libresoc.v:125002$4812_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:125006$4817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:125006$4817_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124998$4807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124998$4806_Y + connect \Y $pos$libresoc.v:124998$4807_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124999$4809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124999$4808_Y + connect \Y $pos$libresoc.v:124999$4809_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125002$4813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125002$4812_Y + connect \Y $pos$libresoc.v:125002$4813_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:125006$4818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125006$4817_Y + connect \Y $pos$libresoc.v:125006$4818_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:125000$4810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ALU_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125000$4810_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:125001$4811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \ALU_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:125001$4811_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:125003$4814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:125003$4814_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:125004$4815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:125004$4815_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125005$4816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125005$4816_Y + end + attribute \src "libresoc.v:124920.7-124920.20" + process $proc$libresoc.v:124920$4827 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:115200.3-115210.6" - process $proc$libresoc.v:115200$4573 + attribute \src "libresoc.v:125008.3-125054.6" + process $proc$libresoc.v:125008$4819 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115201.5-115201.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:125009.5-125009.29" switch \initial - attribute \src "libresoc.v:115201.9-115201.17" + attribute \src "libresoc.v:125009.9-125009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 4'0010 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:115211.3-115237.6" - process $proc$libresoc.v:115211$4574 + attribute \src "libresoc.v:125055.3-125101.6" + process $proc$libresoc.v:125055$4820 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115212.5-115212.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125056.5-125056.29" switch \initial - attribute \src "libresoc.v:115212.9-115212.17" + attribute \src "libresoc.v:125056.9-125056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0010 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0011 assign { } { } - assign $1\cr_bitfield[2:0] \BI [4:2] + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0101 assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0100 assign { } { } - assign $1\cr_bitfield[2:0] \BA [4:2] + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 4'0110 assign { } { } - assign $1\cr_bitfield[2:0] \BC [4:2] + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:115238.3-115248.6" - process $proc$libresoc.v:115238$4575 + attribute \src "libresoc.v:125102.3-125112.6" + process $proc$libresoc.v:125102$4821 assign { } { } assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:115239.5-115239.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:125103.5-125103.29" switch \initial - attribute \src "libresoc.v:115239.9-115239.17" + attribute \src "libresoc.v:125103.9-125103.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0011 assign { } { } - assign $1\cr_bitfield_b[2:0] \BB [4:2] + assign $1\si[15:0] \ALU_SI case - assign $1\cr_bitfield_b[2:0] 3'000 + assign $1\si[15:0] 16'0000000000000000 end sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] + update \si $0\si[15:0] end - attribute \src "libresoc.v:115249.3-115259.6" - process $proc$libresoc.v:115249$4576 + attribute \src "libresoc.v:125113.3-125123.6" + process $proc$libresoc.v:125113$4822 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:115250.5-115250.29" + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:125114.5-125114.29" switch \initial - attribute \src "libresoc.v:115250.9-115250.17" + attribute \src "libresoc.v:125114.9-125114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0101 assign { } { } - assign $1\cr_bitfield_o[2:0] \BT [4:2] + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\cr_bitfield_o[2:0] 3'000 + assign $1\si_hi[31:0] 0 end sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:115260.3-115270.6" - process $proc$libresoc.v:115260$4577 + attribute \src "libresoc.v:125124.3-125134.6" + process $proc$libresoc.v:125124$4823 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:115261.5-115261.29" + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:125125.5-125125.29" switch \initial - attribute \src "libresoc.v:115261.9-115261.17" + attribute \src "libresoc.v:125125.9-125125.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0100 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 + assign $1\ui[15:0] \ALU_UI case - assign $1\cr_bitfield_o_ok[0:0] 1'0 + assign $1\ui[15:0] 16'0000000000000000 end sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + update \ui $0\ui[15:0] end - attribute \src "libresoc.v:115271.3-115281.6" - process $proc$libresoc.v:115271$4578 + attribute \src "libresoc.v:125135.3-125145.6" + process $proc$libresoc.v:125135$4824 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115272.5-115272.29" + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:125136.5-125136.29" switch \initial - attribute \src "libresoc.v:115272.9-115272.17" + attribute \src "libresoc.v:125136.9-125136.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 4'0110 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\li[25:0] \$16 [25:0] case - assign $1\move_one[0:0] 1'0 + assign $1\li[25:0] 26'00000000000000000000000000 end sync always - update \move_one $0\move_one[0:0] + update \li $0\li[25:0] end - attribute \src "libresoc.v:115282.3-115297.6" - process $proc$libresoc.v:115282$4579 + attribute \src "libresoc.v:125146.3-125156.6" + process $proc$libresoc.v:125146$4825 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:115283.5-115283.29" + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:125147.5-125147.29" switch \initial - attribute \src "libresoc.v:115283.9-115283.17" + attribute \src "libresoc.v:125147.9-125147.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 4'0111 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\bd[15:0] \$19 [15:0] case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\bd[15:0] 16'0000000000000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \bd $0\bd[15:0] end - attribute \src "libresoc.v:115298.3-115316.6" - process $proc$libresoc.v:115298$4580 + attribute \src "libresoc.v:125157.3-125167.6" + process $proc$libresoc.v:125157$4826 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:115299.5-115299.29" + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:125158.5-125158.29" switch \initial - attribute \src "libresoc.v:115299.9-115299.17" + attribute \src "libresoc.v:125158.9-125158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 4'1000 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\ds[15:0] \$22 [15:0] case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \ds $0\ds[15:0] end - connect \$1 $eq$libresoc.v:115154$4567_Y - connect \$3 $and$libresoc.v:115155$4568_Y - connect \$5 $eq$libresoc.v:115156$4569_Y - connect \$7 $and$libresoc.v:115157$4570_Y + connect \$9 $pos$libresoc.v:124998$4807_Y + connect \$11 $pos$libresoc.v:124999$4809_Y + connect \$14 $sshl$libresoc.v:125000$4810_Y + connect \$17 $sshl$libresoc.v:125001$4811_Y + connect \$1 $pos$libresoc.v:125002$4813_Y + connect \$20 $sshl$libresoc.v:125003$4814_Y + connect \$23 $sshl$libresoc.v:125004$4815_Y + connect \$4 $sshl$libresoc.v:125005$4816_Y + connect \$3 $pos$libresoc.v:125006$4818_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 end -attribute \src "libresoc.v:115321.1-115561.10" +attribute \src "libresoc.v:125176.1-125429.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" -module \dec_cr_out - attribute \src "libresoc.v:115475.3-115493.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:115445.3-115463.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115526.3-115560.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115464.3-115474.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115322.7-115322.20" +module \dec_bi$144 + attribute \src "libresoc.v:125403.3-125413.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:125414.3-125424.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:125265.3-125311.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:125312.3-125358.6" + wire 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connect \A \BRANCH_sh + connect \Y $extend$libresoc.v:125255$4828_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125256$4830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \BRANCH_SH32 + connect \Y $extend$libresoc.v:125256$4830_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125259$4834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \BRANCH_UI + connect \Y $extend$libresoc.v:125259$4834_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:125263$4839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:125263$4839_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125255$4829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125255$4828_Y + connect \Y $pos$libresoc.v:125255$4829_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125256$4831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125256$4830_Y + connect \Y $pos$libresoc.v:125256$4831_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125259$4835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125259$4834_Y + connect \Y $pos$libresoc.v:125259$4835_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:125263$4840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125263$4839_Y + connect \Y $pos$libresoc.v:125263$4840_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:125257$4832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:115438$4582_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \BRANCH_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125257$4832_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:115439$4583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:125258$4833 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:115439$4583_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \BRANCH_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:125258$4833_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:115440.15-115444.4" - cell \ppick$139 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:125260$4836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:125260$4836_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:125261$4837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:125261$4837_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125262$4838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125262$4838_Y end - attribute \src "libresoc.v:115322.7-115322.20" - process $proc$libresoc.v:115322$4590 + attribute \src "libresoc.v:125177.7-125177.20" + process $proc$libresoc.v:125177$4849 assign { } { } assign $0\initial[0:0] 1'0 sync always - update \initial $0\initial[0:0] - sync init + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125265.3-125311.6" + process $proc$libresoc.v:125265$4841 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:125266.5-125266.29" + switch \initial + attribute \src "libresoc.v:125266.9-125266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:125312.3-125358.6" + process $proc$libresoc.v:125312$4842 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125313.5-125313.29" + switch \initial + attribute \src "libresoc.v:125313.9-125313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:115445.3-115463.6" - process $proc$libresoc.v:115445$4584 + attribute \src "libresoc.v:125359.3-125369.6" + process $proc$libresoc.v:125359$4843 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115446.5-115446.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:125360.5-125360.29" switch \initial - attribute \src "libresoc.v:115446.9-115446.17" + attribute \src "libresoc.v:125360.9-125360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0011 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\si[15:0] \BRANCH_SI case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\si[15:0] 16'0000000000000000 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \si $0\si[15:0] end - attribute \src "libresoc.v:115464.3-115474.6" - process $proc$libresoc.v:115464$4585 + attribute \src "libresoc.v:125370.3-125380.6" + process $proc$libresoc.v:125370$4844 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115465.5-115465.29" + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:125371.5-125371.29" switch \initial - attribute \src "libresoc.v:115465.9-115465.17" + attribute \src "libresoc.v:125371.9-125371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0101 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\si_hi[31:0] 0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:115475.3-115493.6" - process $proc$libresoc.v:115475$4586 + attribute \src "libresoc.v:125381.3-125391.6" + process $proc$libresoc.v:125381$4845 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115476.5-115476.29" + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:125382.5-125382.29" switch \initial - attribute \src "libresoc.v:115476.9-115476.17" + attribute \src "libresoc.v:125382.9-125382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0100 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\ui[15:0] \BRANCH_UI case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\ui[15:0] 16'0000000000000000 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \ui $0\ui[15:0] end - attribute \src "libresoc.v:115494.3-115504.6" - process $proc$libresoc.v:115494$4587 + attribute \src "libresoc.v:125392.3-125402.6" + process $proc$libresoc.v:125392$4846 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115495.5-115495.29" + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:125393.5-125393.29" switch \initial - attribute \src "libresoc.v:115495.9-115495.17" + attribute \src "libresoc.v:125393.9-125393.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0110 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\li[25:0] \$16 [25:0] case - assign $1\move_one[0:0] 1'0 + assign $1\li[25:0] 26'00000000000000000000000000 end sync always - update \move_one $0\move_one[0:0] + update \li $0\li[25:0] end - attribute \src "libresoc.v:115505.3-115525.6" - process $proc$libresoc.v:115505$4588 + attribute \src "libresoc.v:125403.3-125413.6" + process $proc$libresoc.v:125403$4847 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:115506.5-115506.29" + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:125404.5-125404.29" switch \initial - attribute \src "libresoc.v:115506.9-115506.17" + attribute \src "libresoc.v:125404.9-125404.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0111 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \ALU_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\bd[15:0] \$19 [15:0] case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\bd[15:0] 16'0000000000000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \bd $0\bd[15:0] end - attribute \src "libresoc.v:115526.3-115560.6" - process $proc$libresoc.v:115526$4589 + attribute \src "libresoc.v:125414.3-125424.6" + process $proc$libresoc.v:125414$4848 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:115527.5-115527.29" + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:125415.5-125415.29" switch \initial - attribute \src "libresoc.v:115527.9-115527.17" + attribute \src "libresoc.v:125415.9-125415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'1000 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \ALU_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\ds[15:0] \$22 [15:0] case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \ds $0\ds[15:0] end - connect \$1 $eq$libresoc.v:115438$4582_Y - connect \$3 $eq$libresoc.v:115439$4583_Y + connect \$9 $pos$libresoc.v:125255$4829_Y + connect \$11 $pos$libresoc.v:125256$4831_Y + connect \$14 $sshl$libresoc.v:125257$4832_Y + connect \$17 $sshl$libresoc.v:125258$4833_Y + connect \$1 $pos$libresoc.v:125259$4835_Y + connect \$20 $sshl$libresoc.v:125260$4836_Y + connect \$23 $sshl$libresoc.v:125261$4837_Y + connect \$4 $sshl$libresoc.v:125262$4838_Y + connect \$3 $pos$libresoc.v:125263$4840_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 end -attribute \src "libresoc.v:115565.1-115804.10" +attribute \src "libresoc.v:125433.1-125686.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" -module \dec_cr_out$145 - attribute \src "libresoc.v:115718.3-115736.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:115688.3-115706.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115769.3-115803.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115707.3-115717.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115566.7-115566.20" +module \dec_bi$149 + attribute \src "libresoc.v:125660.3-125670.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:125671.3-125681.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:125522.3-125568.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:125569.3-125615.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:125434.7-125434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115737.3-115747.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:115748.3-115768.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:115718.3-115736.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115688.3-115706.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115769.3-115803.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:115707.3-115717.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115737.3-115747.6" - wire $1\move_one[0:0] - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 32 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\A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125516$4856_Y + connect \Y $pos$libresoc.v:125516$4857_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:125520$4862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125520$4861_Y + connect \Y $pos$libresoc.v:125520$4862_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:125514$4854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:115681$4591_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LOGICAL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125514$4854_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:115682$4592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:125515$4855 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:115682$4592_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LOGICAL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:125515$4855_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:115683.15-115687.4" - cell \ppick$146 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:125517$4858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:125517$4858_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:125518$4859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:125518$4859_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125519$4860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125519$4860_Y end - attribute \src "libresoc.v:115566.7-115566.20" - process $proc$libresoc.v:115566$4599 + attribute \src "libresoc.v:125434.7-125434.20" + process $proc$libresoc.v:125434$4871 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115688.3-115706.6" - process $proc$libresoc.v:115688$4593 + attribute \src "libresoc.v:125522.3-125568.6" + process $proc$libresoc.v:125522$4863 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115689.5-115689.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:125523.5-125523.29" switch \initial - attribute \src "libresoc.v:115689.9-115689.17" + attribute \src "libresoc.v:125523.9-125523.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0010 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0011 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0101 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:115707.3-115717.6" - process $proc$libresoc.v:115707$4594 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115708.5-115708.29" - switch \initial - attribute \src "libresoc.v:115708.9-115708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0100 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:115718.3-115736.6" - process $proc$libresoc.v:115718$4595 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115719.5-115719.29" - switch \initial - attribute \src "libresoc.v:115719.9-115719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0110 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0111 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'1000 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:115737.3-115747.6" - process $proc$libresoc.v:115737$4596 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115738.5-115738.29" - switch \initial - attribute \src "libresoc.v:115738.9-115738.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'1001 assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:115748.3-115768.6" - process $proc$libresoc.v:115748$4597 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:115749.5-115749.29" - switch \initial - attribute \src "libresoc.v:115749.9-115749.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'1010 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \CR_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:115769.3-115803.6" - process $proc$libresoc.v:115769$4598 + attribute \src "libresoc.v:125569.3-125615.6" + process $proc$libresoc.v:125569$4864 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:115770.5-115770.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125570.5-125570.29" switch \initial - attribute \src "libresoc.v:115770.9-115770.17" + attribute \src "libresoc.v:125570.9-125570.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0010 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \CR_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:115681$4591_Y - connect \$3 $eq$libresoc.v:115682$4592_Y -end -attribute \src "libresoc.v:115808.1-116047.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$152 - attribute \src "libresoc.v:115961.3-115979.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:115931.3-115949.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116012.3-116046.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115950.3-115960.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115809.7-115809.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:115980.3-115990.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:115991.3-116011.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:115961.3-115979.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115931.3-115949.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116012.3-116046.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:115950.3-115960.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115980.3-115990.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:115991.3-116011.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116012.3-116046.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:115991.3-116011.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116012.3-116046.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:115991.3-116011.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116012.3-116046.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:115924.17-115924.124" - wire $eq$libresoc.v:115924$4600_Y - attribute \src "libresoc.v:115925.17-115925.124" - wire $eq$libresoc.v:115925$4601_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 4 \BRANCH_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:115809.7-115809.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:115924$4600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:115924$4600_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:115925$4601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:115925$4601_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:115926.15-115930.4" - cell \ppick$153 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:115809.7-115809.20" - process $proc$libresoc.v:115809$4608 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:115931.3-115949.6" - process $proc$libresoc.v:115931$4602 + attribute \src "libresoc.v:125616.3-125626.6" + process $proc$libresoc.v:125616$4865 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115932.5-115932.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:125617.5-125617.29" switch \initial - attribute \src "libresoc.v:115932.9-115932.17" + attribute \src "libresoc.v:125617.9-125617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0011 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\si[15:0] \LOGICAL_SI case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\si[15:0] 16'0000000000000000 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \si $0\si[15:0] end - attribute \src "libresoc.v:115950.3-115960.6" - process $proc$libresoc.v:115950$4603 + attribute \src "libresoc.v:125627.3-125637.6" + process $proc$libresoc.v:125627$4866 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115951.5-115951.29" + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:125628.5-125628.29" switch \initial - attribute \src "libresoc.v:115951.9-115951.17" + attribute \src "libresoc.v:125628.9-125628.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0101 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\si_hi[31:0] 0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:115961.3-115979.6" - process $proc$libresoc.v:115961$4604 + attribute \src "libresoc.v:125638.3-125648.6" + process $proc$libresoc.v:125638$4867 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115962.5-115962.29" + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:125639.5-125639.29" switch \initial - attribute \src "libresoc.v:115962.9-115962.17" + attribute \src "libresoc.v:125639.9-125639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0100 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\ui[15:0] \LOGICAL_UI case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\ui[15:0] 16'0000000000000000 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \ui $0\ui[15:0] end - attribute \src "libresoc.v:115980.3-115990.6" - process $proc$libresoc.v:115980$4605 + attribute \src "libresoc.v:125649.3-125659.6" + process $proc$libresoc.v:125649$4868 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115981.5-115981.29" + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:125650.5-125650.29" switch \initial - attribute \src "libresoc.v:115981.9-115981.17" + attribute \src "libresoc.v:125650.9-125650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0110 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\li[25:0] \$16 [25:0] case - assign $1\move_one[0:0] 1'0 + assign $1\li[25:0] 26'00000000000000000000000000 end sync always - update \move_one $0\move_one[0:0] + update \li $0\li[25:0] end - attribute \src "libresoc.v:115991.3-116011.6" - process $proc$libresoc.v:115991$4606 + attribute \src "libresoc.v:125660.3-125670.6" + process $proc$libresoc.v:125660$4869 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:115992.5-115992.29" + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:125661.5-125661.29" switch \initial - attribute \src "libresoc.v:115992.9-115992.17" + attribute \src "libresoc.v:125661.9-125661.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0111 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \BRANCH_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\bd[15:0] \$19 [15:0] case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\bd[15:0] 16'0000000000000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \bd $0\bd[15:0] end - attribute \src "libresoc.v:116012.3-116046.6" - process $proc$libresoc.v:116012$4607 + attribute \src "libresoc.v:125671.3-125681.6" + process $proc$libresoc.v:125671$4870 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116013.5-116013.29" + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:125672.5-125672.29" switch \initial - attribute \src "libresoc.v:116013.9-116013.17" + attribute \src "libresoc.v:125672.9-125672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'1000 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \BRANCH_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\ds[15:0] \$22 [15:0] case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \ds $0\ds[15:0] end - connect \$1 $eq$libresoc.v:115924$4600_Y - connect \$3 $eq$libresoc.v:115925$4601_Y + connect \$9 $pos$libresoc.v:125512$4851_Y + connect \$11 $pos$libresoc.v:125513$4853_Y + connect \$14 $sshl$libresoc.v:125514$4854_Y + connect \$17 $sshl$libresoc.v:125515$4855_Y + connect \$1 $pos$libresoc.v:125516$4857_Y + connect \$20 $sshl$libresoc.v:125517$4858_Y + connect \$23 $sshl$libresoc.v:125518$4859_Y + connect \$4 $sshl$libresoc.v:125519$4860_Y + connect \$3 $pos$libresoc.v:125520$4862_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 end -attribute \src "libresoc.v:116051.1-116291.10" +attribute \src "libresoc.v:125690.1-125943.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" -module \dec_cr_out$160 - attribute \src "libresoc.v:116205.3-116223.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116175.3-116193.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116256.3-116290.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116194.3-116204.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116052.7-116052.20" +module \dec_bi$157 + attribute \src "libresoc.v:125917.3-125927.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:125928.3-125938.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:125779.3-125825.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:125826.3-125872.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:125691.7-125691.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116224.3-116234.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:116235.3-116255.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116205.3-116223.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116175.3-116193.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116256.3-116290.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116194.3-116204.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116224.3-116234.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:116235.3-116255.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116256.3-116290.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116235.3-116255.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116256.3-116290.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:116235.3-116255.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116256.3-116290.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:116168.17-116168.125" - wire $eq$libresoc.v:116168$4609_Y - attribute \src "libresoc.v:116169.17-116169.125" - wire $eq$libresoc.v:116169$4610_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 5 \LOGICAL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:116052.7-116052.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116168$4609 + attribute \src "libresoc.v:125906.3-125916.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:125873.3-125883.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:125884.3-125894.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:125895.3-125905.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:125917.3-125927.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:125928.3-125938.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:125779.3-125825.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:125826.3-125872.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125906.3-125916.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:125873.3-125883.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:125884.3-125894.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:125895.3-125905.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:125769.17-125769.104" + wire width 64 $extend$libresoc.v:125769$4872_Y + attribute \src "libresoc.v:125770.18-125770.107" + wire width 64 $extend$libresoc.v:125770$4874_Y + attribute \src "libresoc.v:125773.17-125773.104" + wire width 64 $extend$libresoc.v:125773$4878_Y + attribute \src "libresoc.v:125777.17-125777.102" + wire width 64 $extend$libresoc.v:125777$4883_Y + attribute \src "libresoc.v:125769.17-125769.104" + wire width 64 $pos$libresoc.v:125769$4873_Y + attribute \src "libresoc.v:125770.18-125770.107" + wire width 64 $pos$libresoc.v:125770$4875_Y + attribute \src "libresoc.v:125773.17-125773.104" + wire width 64 $pos$libresoc.v:125773$4879_Y + attribute \src "libresoc.v:125777.17-125777.102" + wire width 64 $pos$libresoc.v:125777$4884_Y + attribute \src "libresoc.v:125771.18-125771.114" + wire width 47 $sshl$libresoc.v:125771$4876_Y + attribute \src "libresoc.v:125772.18-125772.113" + wire width 27 $sshl$libresoc.v:125772$4877_Y + attribute \src "libresoc.v:125774.18-125774.113" + wire width 17 $sshl$libresoc.v:125774$4880_Y + attribute \src "libresoc.v:125775.18-125775.113" + wire width 17 $sshl$libresoc.v:125775$4881_Y + attribute \src "libresoc.v:125776.17-125776.109" + wire width 47 $sshl$libresoc.v:125776$4882_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:125691.7-125691.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125769$4872 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \DIV_sh + connect \Y $extend$libresoc.v:125769$4872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125770$4874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \DIV_SH32 + connect \Y $extend$libresoc.v:125770$4874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125773$4878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \DIV_UI + connect \Y $extend$libresoc.v:125773$4878_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:125777$4883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:125777$4883_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125769$4873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125769$4872_Y + connect \Y $pos$libresoc.v:125769$4873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125770$4875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125770$4874_Y + connect \Y $pos$libresoc.v:125770$4875_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125773$4879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125773$4878_Y + connect \Y $pos$libresoc.v:125773$4879_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:125777$4884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125777$4883_Y + connect \Y $pos$libresoc.v:125777$4884_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:125771$4876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116168$4609_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \DIV_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125771$4876_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116169$4610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:125772$4877 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116169$4610_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \DIV_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:125772$4877_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:116170.15-116174.4" - cell \ppick$161 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:125774$4880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:125774$4880_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:125775$4881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:125775$4881_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125776$4882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125776$4882_Y end - attribute \src "libresoc.v:116052.7-116052.20" - process $proc$libresoc.v:116052$4617 + attribute \src "libresoc.v:125691.7-125691.20" + process $proc$libresoc.v:125691$4893 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116175.3-116193.6" - process $proc$libresoc.v:116175$4611 + attribute \src "libresoc.v:125779.3-125825.6" + process $proc$libresoc.v:125779$4885 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116176.5-116176.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:125780.5-125780.29" switch \initial - attribute \src "libresoc.v:116176.9-116176.17" + attribute \src "libresoc.v:125780.9-125780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0010 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0011 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0101 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:116194.3-116204.6" - process $proc$libresoc.v:116194$4612 + attribute \src "libresoc.v:125826.3-125872.6" + process $proc$libresoc.v:125826$4886 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116195.5-116195.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125827.5-125827.29" switch \initial - attribute \src "libresoc.v:116195.9-116195.17" + attribute \src "libresoc.v:125827.9-125827.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0010 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:116205.3-116223.6" - process $proc$libresoc.v:116205$4613 + attribute \src "libresoc.v:125873.3-125883.6" + process $proc$libresoc.v:125873$4887 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116206.5-116206.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:125874.5-125874.29" switch \initial - attribute \src "libresoc.v:116206.9-116206.17" + attribute \src "libresoc.v:125874.9-125874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0011 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\si[15:0] \DIV_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:125884.3-125894.6" + process $proc$libresoc.v:125884$4888 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:125885.5-125885.29" + switch \initial + attribute \src "libresoc.v:125885.9-125885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0101 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:125895.3-125905.6" + process $proc$libresoc.v:125895$4889 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:125896.5-125896.29" + switch \initial + attribute \src "libresoc.v:125896.9-125896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0100 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\ui[15:0] \DIV_UI case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\ui[15:0] 16'0000000000000000 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \ui $0\ui[15:0] end - attribute \src "libresoc.v:116224.3-116234.6" - process $proc$libresoc.v:116224$4614 + attribute \src "libresoc.v:125906.3-125916.6" + process $proc$libresoc.v:125906$4890 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116225.5-116225.29" + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:125907.5-125907.29" switch \initial - attribute \src "libresoc.v:116225.9-116225.17" + attribute \src "libresoc.v:125907.9-125907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0110 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\li[25:0] \$16 [25:0] case - assign $1\move_one[0:0] 1'0 + assign $1\li[25:0] 26'00000000000000000000000000 end sync always - update \move_one $0\move_one[0:0] + update \li $0\li[25:0] end - attribute \src "libresoc.v:116235.3-116255.6" - process $proc$libresoc.v:116235$4615 + attribute \src "libresoc.v:125917.3-125927.6" + process $proc$libresoc.v:125917$4891 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116236.5-116236.29" + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:125918.5-125918.29" switch \initial - attribute \src "libresoc.v:116236.9-116236.17" + attribute \src "libresoc.v:125918.9-125918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0111 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \LOGICAL_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\bd[15:0] \$19 [15:0] case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\bd[15:0] 16'0000000000000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \bd $0\bd[15:0] end - attribute \src "libresoc.v:116256.3-116290.6" - process $proc$libresoc.v:116256$4616 + attribute \src "libresoc.v:125928.3-125938.6" + process $proc$libresoc.v:125928$4892 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116257.5-116257.29" + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:125929.5-125929.29" switch \initial - attribute \src "libresoc.v:116257.9-116257.17" + attribute \src "libresoc.v:125929.9-125929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'1000 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \LOGICAL_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\ds[15:0] \$22 [15:0] case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \ds $0\ds[15:0] end - connect \$1 $eq$libresoc.v:116168$4609_Y - connect \$3 $eq$libresoc.v:116169$4610_Y + connect \$9 $pos$libresoc.v:125769$4873_Y + connect \$11 $pos$libresoc.v:125770$4875_Y + connect \$14 $sshl$libresoc.v:125771$4876_Y + connect \$17 $sshl$libresoc.v:125772$4877_Y + connect \$1 $pos$libresoc.v:125773$4879_Y + connect \$20 $sshl$libresoc.v:125774$4880_Y + connect \$23 $sshl$libresoc.v:125775$4881_Y + connect \$4 $sshl$libresoc.v:125776$4882_Y + connect \$3 $pos$libresoc.v:125777$4884_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 end -attribute \src "libresoc.v:116295.1-116534.10" +attribute \src "libresoc.v:125947.1-126200.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" -module \dec_cr_out$169 - attribute \src "libresoc.v:116448.3-116466.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116418.3-116436.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116499.3-116533.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116437.3-116447.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116296.7-116296.20" +module \dec_bi$161 + attribute \src "libresoc.v:126174.3-126184.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:126185.3-126195.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:126036.3-126082.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:126083.3-126129.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:125948.7-125948.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116467.3-116477.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:116478.3-116498.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116448.3-116466.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116418.3-116436.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116499.3-116533.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116437.3-116447.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116467.3-116477.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:116478.3-116498.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116499.3-116533.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116478.3-116498.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116499.3-116533.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:116478.3-116498.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116499.3-116533.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:116411.17-116411.121" - wire $eq$libresoc.v:116411$4618_Y - attribute \src "libresoc.v:116412.17-116412.121" - wire $eq$libresoc.v:116412$4619_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 4 \SPR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + attribute \src "libresoc.v:126163.3-126173.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:126130.3-126140.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:126141.3-126151.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:126152.3-126162.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:126174.3-126184.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:126185.3-126195.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:126036.3-126082.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:126083.3-126129.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:126163.3-126173.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:126130.3-126140.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:126141.3-126151.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:126152.3-126162.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:126026.17-126026.104" + wire width 64 $extend$libresoc.v:126026$4894_Y + attribute \src "libresoc.v:126027.18-126027.107" + wire width 64 $extend$libresoc.v:126027$4896_Y + attribute \src "libresoc.v:126030.17-126030.104" + wire width 64 $extend$libresoc.v:126030$4900_Y + attribute \src "libresoc.v:126034.17-126034.102" + wire width 64 $extend$libresoc.v:126034$4905_Y + attribute \src "libresoc.v:126026.17-126026.104" + wire width 64 $pos$libresoc.v:126026$4895_Y + attribute \src "libresoc.v:126027.18-126027.107" + wire width 64 $pos$libresoc.v:126027$4897_Y + attribute \src "libresoc.v:126030.17-126030.104" + wire width 64 $pos$libresoc.v:126030$4901_Y + attribute \src "libresoc.v:126034.17-126034.102" + wire width 64 $pos$libresoc.v:126034$4906_Y + attribute \src "libresoc.v:126028.18-126028.114" + wire width 47 $sshl$libresoc.v:126028$4898_Y + attribute \src "libresoc.v:126029.18-126029.113" + wire width 27 $sshl$libresoc.v:126029$4899_Y + attribute \src "libresoc.v:126031.18-126031.113" + wire width 17 $sshl$libresoc.v:126031$4902_Y + attribute \src "libresoc.v:126032.18-126032.113" + wire width 17 $sshl$libresoc.v:126032$4903_Y + attribute \src "libresoc.v:126033.17-126033.109" + wire width 47 $sshl$libresoc.v:126033$4904_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:116296.7-116296.15" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:125948.7-125948.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116411$4618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126026$4894 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \MUL_sh + connect \Y $extend$libresoc.v:126026$4894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126027$4896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \MUL_SH32 + connect \Y $extend$libresoc.v:126027$4896_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126030$4900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \MUL_UI + connect \Y $extend$libresoc.v:126030$4900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:126034$4905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:126034$4905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126026$4895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126026$4894_Y + connect \Y $pos$libresoc.v:126026$4895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126027$4897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126027$4896_Y + connect \Y $pos$libresoc.v:126027$4897_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126030$4901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126030$4900_Y + connect \Y $pos$libresoc.v:126030$4901_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:126034$4906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126034$4905_Y + connect \Y $pos$libresoc.v:126034$4906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:126028$4898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116411$4618_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \MUL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126028$4898_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116412$4619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:126029$4899 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116412$4619_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \MUL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:126029$4899_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:116413.15-116417.4" - cell \ppick$170 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:126031$4902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:126031$4902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:126032$4903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:126032$4903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:126033$4904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126033$4904_Y end - attribute \src "libresoc.v:116296.7-116296.20" - process $proc$libresoc.v:116296$4626 + attribute \src "libresoc.v:125948.7-125948.20" + process $proc$libresoc.v:125948$4915 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116418.3-116436.6" - process $proc$libresoc.v:116418$4620 + attribute \src "libresoc.v:126036.3-126082.6" + process $proc$libresoc.v:126036$4907 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116419.5-116419.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:126037.5-126037.29" switch \initial - attribute \src "libresoc.v:116419.9-116419.17" + attribute \src "libresoc.v:126037.9-126037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0010 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0011 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0101 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:116437.3-116447.6" - process $proc$libresoc.v:116437$4621 + attribute \src "libresoc.v:126083.3-126129.6" + process $proc$libresoc.v:126083$4908 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116438.5-116438.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:126084.5-126084.29" switch \initial - attribute \src "libresoc.v:116438.9-116438.17" + attribute \src "libresoc.v:126084.9-126084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0010 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:116448.3-116466.6" - process $proc$libresoc.v:116448$4622 + attribute \src "libresoc.v:126130.3-126140.6" + process $proc$libresoc.v:126130$4909 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116449.5-116449.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:126131.5-126131.29" switch \initial - attribute \src "libresoc.v:116449.9-116449.17" + attribute \src "libresoc.v:126131.9-126131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0011 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\si[15:0] \MUL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:126141.3-126151.6" + process $proc$libresoc.v:126141$4910 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:126142.5-126142.29" + switch \initial + attribute \src "libresoc.v:126142.9-126142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0101 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:126152.3-126162.6" + process $proc$libresoc.v:126152$4911 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:126153.5-126153.29" + switch \initial + attribute \src "libresoc.v:126153.9-126153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0100 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\ui[15:0] \MUL_UI case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\ui[15:0] 16'0000000000000000 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \ui $0\ui[15:0] end - attribute \src "libresoc.v:116467.3-116477.6" - process $proc$libresoc.v:116467$4623 + attribute \src "libresoc.v:126163.3-126173.6" + process $proc$libresoc.v:126163$4912 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116468.5-116468.29" + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:126164.5-126164.29" switch \initial - attribute \src "libresoc.v:116468.9-116468.17" + attribute \src "libresoc.v:126164.9-126164.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0110 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\li[25:0] \$16 [25:0] case - assign $1\move_one[0:0] 1'0 + assign $1\li[25:0] 26'00000000000000000000000000 end sync always - update \move_one $0\move_one[0:0] + update \li $0\li[25:0] end - attribute \src "libresoc.v:116478.3-116498.6" - process $proc$libresoc.v:116478$4624 + attribute \src "libresoc.v:126174.3-126184.6" + process $proc$libresoc.v:126174$4913 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116479.5-116479.29" + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:126175.5-126175.29" switch \initial - attribute \src "libresoc.v:116479.9-116479.17" + attribute \src "libresoc.v:126175.9-126175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0111 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \SPR_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\bd[15:0] \$19 [15:0] case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\bd[15:0] 16'0000000000000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \bd $0\bd[15:0] end - attribute \src "libresoc.v:116499.3-116533.6" - process $proc$libresoc.v:116499$4625 + attribute \src "libresoc.v:126185.3-126195.6" + process $proc$libresoc.v:126185$4914 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116500.5-116500.29" + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:126186.5-126186.29" switch \initial - attribute \src "libresoc.v:116500.9-116500.17" + attribute \src "libresoc.v:126186.9-126186.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'1000 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \SPR_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\ds[15:0] \$22 [15:0] case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \ds $0\ds[15:0] end - connect \$1 $eq$libresoc.v:116411$4618_Y - connect \$3 $eq$libresoc.v:116412$4619_Y + connect \$9 $pos$libresoc.v:126026$4895_Y + connect \$11 $pos$libresoc.v:126027$4897_Y + connect \$14 $sshl$libresoc.v:126028$4898_Y + connect \$17 $sshl$libresoc.v:126029$4899_Y + connect \$1 $pos$libresoc.v:126030$4901_Y + connect \$20 $sshl$libresoc.v:126031$4902_Y + connect \$23 $sshl$libresoc.v:126032$4903_Y + connect \$4 $sshl$libresoc.v:126033$4904_Y + connect \$3 $pos$libresoc.v:126034$4906_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 end -attribute \src "libresoc.v:116538.1-116778.10" +attribute \src "libresoc.v:126204.1-126457.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" -module \dec_cr_out$176 - attribute \src "libresoc.v:116692.3-116710.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116662.3-116680.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116743.3-116777.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116681.3-116691.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116539.7-116539.20" +module \dec_bi$165 + attribute \src "libresoc.v:126431.3-126441.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:126442.3-126452.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:126293.3-126339.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:126340.3-126386.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:126205.7-126205.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116711.3-116721.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:116722.3-116742.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116692.3-116710.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116662.3-116680.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116743.3-116777.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116681.3-116691.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116711.3-116721.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:116722.3-116742.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116743.3-116777.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116722.3-116742.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116743.3-116777.6" - wire width 8 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:116539.7-116539.15" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:126205.7-126205.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116655$4627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126283$4916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_sh + connect \Y $extend$libresoc.v:126283$4916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126284$4918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_SH32 + connect \Y $extend$libresoc.v:126284$4918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126287$4922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_UI + connect \Y $extend$libresoc.v:126287$4922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:126291$4927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:126291$4927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126283$4917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126283$4916_Y + connect \Y $pos$libresoc.v:126283$4917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126284$4919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126284$4918_Y + connect \Y $pos$libresoc.v:126284$4919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126287$4923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126287$4922_Y + connect \Y $pos$libresoc.v:126287$4923_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:126291$4928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126291$4927_Y + connect \Y $pos$libresoc.v:126291$4928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:126285$4920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \SHIFT_ROT_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126285$4920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:126286$4921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \SHIFT_ROT_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:126286$4921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:126288$4924 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116655$4627_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:126288$4924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116656$4628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:126289$4925 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116656$4628_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:126289$4925_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:116657.15-116661.4" - cell \ppick$177 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:126290$4926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126290$4926_Y end - attribute \src "libresoc.v:116539.7-116539.20" - process $proc$libresoc.v:116539$4635 + attribute \src "libresoc.v:126205.7-126205.20" + process $proc$libresoc.v:126205$4937 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116662.3-116680.6" - process $proc$libresoc.v:116662$4629 + attribute \src "libresoc.v:126293.3-126339.6" + process $proc$libresoc.v:126293$4929 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116663.5-116663.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:126294.5-126294.29" switch \initial - attribute \src "libresoc.v:116663.9-116663.17" + attribute \src "libresoc.v:126294.9-126294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0010 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0011 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0101 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:116681.3-116691.6" - process $proc$libresoc.v:116681$4630 + attribute \src "libresoc.v:126340.3-126386.6" + process $proc$libresoc.v:126340$4930 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116682.5-116682.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:126341.5-126341.29" switch \initial - attribute \src "libresoc.v:116682.9-116682.17" + attribute \src "libresoc.v:126341.9-126341.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0010 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:116692.3-116710.6" - process $proc$libresoc.v:116692$4631 + attribute \src "libresoc.v:126387.3-126397.6" + process $proc$libresoc.v:126387$4931 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116693.5-116693.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:126388.5-126388.29" switch \initial - attribute \src "libresoc.v:116693.9-116693.17" + attribute \src "libresoc.v:126388.9-126388.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0011 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\si[15:0] \SHIFT_ROT_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:126398.3-126408.6" + process $proc$libresoc.v:126398$4932 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:126399.5-126399.29" + switch \initial + attribute \src "libresoc.v:126399.9-126399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0101 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:126409.3-126419.6" + process $proc$libresoc.v:126409$4933 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:126410.5-126410.29" + switch \initial + attribute \src "libresoc.v:126410.9-126410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0100 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\ui[15:0] \SHIFT_ROT_UI case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\ui[15:0] 16'0000000000000000 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \ui $0\ui[15:0] end - attribute \src "libresoc.v:116711.3-116721.6" - process $proc$libresoc.v:116711$4632 + attribute \src "libresoc.v:126420.3-126430.6" + process $proc$libresoc.v:126420$4934 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116712.5-116712.29" + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:126421.5-126421.29" switch \initial - attribute \src "libresoc.v:116712.9-116712.17" + attribute \src "libresoc.v:126421.9-126421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0110 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\li[25:0] \$16 [25:0] case - assign $1\move_one[0:0] 1'0 + assign $1\li[25:0] 26'00000000000000000000000000 end sync always - update \move_one $0\move_one[0:0] + update \li $0\li[25:0] end - attribute \src "libresoc.v:116722.3-116742.6" - process $proc$libresoc.v:116722$4633 + attribute \src "libresoc.v:126431.3-126441.6" + process $proc$libresoc.v:126431$4935 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116723.5-116723.29" + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:126432.5-126432.29" switch \initial - attribute \src "libresoc.v:116723.9-116723.17" + attribute \src "libresoc.v:126432.9-126432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0111 assign { } { } - assign $1\ppick_i[7:0] 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\src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:116783.7-116783.15" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:126462.7-126462.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116899$4636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126540$4938 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LDST_sh + connect \Y $extend$libresoc.v:126540$4938_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126541$4940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LDST_SH32 + connect \Y $extend$libresoc.v:126541$4940_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:126544$4944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LDST_UI + connect \Y $extend$libresoc.v:126544$4944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:126548$4949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:126548$4949_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126540$4939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126540$4938_Y + connect \Y $pos$libresoc.v:126540$4939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126541$4941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126541$4940_Y + connect \Y $pos$libresoc.v:126541$4941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:126544$4945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126544$4944_Y + connect \Y $pos$libresoc.v:126544$4945_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:126548$4950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126548$4949_Y + connect \Y $pos$libresoc.v:126548$4950_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:126542$4942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116899$4636_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LDST_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126542$4942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116900$4637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:126543$4943 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116900$4637_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LDST_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:126543$4943_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:116901.15-116905.4" - cell \ppick$186 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:126545$4946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:126545$4946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:126546$4947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:126546$4947_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:126547$4948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126547$4948_Y end - attribute \src "libresoc.v:116783.7-116783.20" - process $proc$libresoc.v:116783$4644 + attribute \src "libresoc.v:126462.7-126462.20" + process $proc$libresoc.v:126462$4959 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116906.3-116924.6" - process $proc$libresoc.v:116906$4638 + attribute \src "libresoc.v:126550.3-126596.6" + process $proc$libresoc.v:126550$4951 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116907.5-116907.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:126551.5-126551.29" switch \initial - attribute \src "libresoc.v:116907.9-116907.17" + attribute \src "libresoc.v:126551.9-126551.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0010 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0011 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0101 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:116925.3-116935.6" - process $proc$libresoc.v:116925$4639 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116926.5-116926.29" - switch \initial - attribute \src "libresoc.v:116926.9-116926.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0100 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:116936.3-116954.6" - process $proc$libresoc.v:116936$4640 + attribute \src "libresoc.v:126597.3-126643.6" + process $proc$libresoc.v:126597$4952 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116937.5-116937.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:126598.5-126598.29" switch \initial - attribute \src "libresoc.v:116937.9-116937.17" + attribute \src "libresoc.v:126598.9-126598.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 4'0010 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 4'0011 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0101 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:116955.3-116965.6" - process $proc$libresoc.v:116955$4641 + attribute \src "libresoc.v:126644.3-126654.6" + process $proc$libresoc.v:126644$4953 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116956.5-116956.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:126645.5-126645.29" switch \initial - attribute \src "libresoc.v:116956.9-116956.17" + attribute \src "libresoc.v:126645.9-126645.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0011 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\si[15:0] \LDST_SI case - assign $1\move_one[0:0] 1'0 + assign $1\si[15:0] 16'0000000000000000 end sync always - update \move_one $0\move_one[0:0] + update \si $0\si[15:0] end - attribute \src "libresoc.v:116966.3-116986.6" - process $proc$libresoc.v:116966$4642 + attribute \src "libresoc.v:126655.3-126665.6" + process $proc$libresoc.v:126655$4954 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116967.5-116967.29" + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:126656.5-126656.29" switch \initial - attribute \src "libresoc.v:116967.9-116967.17" + attribute \src "libresoc.v:126656.9-126656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0101 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \MUL_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\si_hi[31:0] 0 end sync always - update \ppick_i $0\ppick_i[7:0] + update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:116987.3-117021.6" - process $proc$libresoc.v:116987$4643 + attribute \src "libresoc.v:126666.3-126676.6" + process $proc$libresoc.v:126666$4955 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116988.5-116988.29" + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:126667.5-126667.29" switch \initial - attribute \src "libresoc.v:116988.9-116988.17" + attribute \src "libresoc.v:126667.9-126667.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0100 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \MUL_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\ui[15:0] \LDST_UI case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\ui[15:0] 16'0000000000000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:116899$4636_Y - connect \$3 $eq$libresoc.v:116900$4637_Y -end -attribute \src "libresoc.v:117026.1-117266.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$193 - attribute \src "libresoc.v:117180.3-117198.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:117150.3-117168.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117231.3-117265.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:117169.3-117179.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117027.7-117027.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:117199.3-117209.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:117210.3-117230.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:117180.3-117198.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117150.3-117168.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117231.3-117265.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:117169.3-117179.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117199.3-117209.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:117210.3-117230.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:117231.3-117265.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:117210.3-117230.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:117231.3-117265.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:117210.3-117230.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:117231.3-117265.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:117143.17-117143.127" - wire $eq$libresoc.v:117143$4645_Y - attribute \src "libresoc.v:117144.17-117144.127" - wire $eq$libresoc.v:117144$4646_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 5 \SHIFT_ROT_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:117027.7-117027.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117143$4645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117143$4645_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117144$4646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117144$4646_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:117145.15-117149.4" - cell \ppick$194 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:117027.7-117027.20" - process $proc$libresoc.v:117027$4653 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \ui $0\ui[15:0] end - attribute \src "libresoc.v:117150.3-117168.6" - process $proc$libresoc.v:117150$4647 + attribute \src "libresoc.v:126677.3-126687.6" + process $proc$libresoc.v:126677$4956 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117151.5-117151.29" + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:126678.5-126678.29" switch \initial - attribute \src "libresoc.v:117151.9-117151.17" + attribute \src "libresoc.v:126678.9-126678.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'0110 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\li[25:0] \$16 [25:0] case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\li[25:0] 26'00000000000000000000000000 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \li $0\li[25:0] end - attribute \src "libresoc.v:117169.3-117179.6" - process $proc$libresoc.v:117169$4648 + attribute \src "libresoc.v:126688.3-126698.6" + process $proc$libresoc.v:126688$4957 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117170.5-117170.29" + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:126689.5-126689.29" switch \initial - attribute \src "libresoc.v:117170.9-117170.17" + attribute \src "libresoc.v:126689.9-126689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 4'0111 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\bd[15:0] \$19 [15:0] case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\bd[15:0] 16'0000000000000000 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \bd $0\bd[15:0] end - attribute \src "libresoc.v:117180.3-117198.6" - process $proc$libresoc.v:117180$4649 + attribute \src "libresoc.v:126699.3-126709.6" + process $proc$libresoc.v:126699$4958 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117181.5-117181.29" + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:126700.5-126700.29" switch \initial - attribute \src "libresoc.v:117181.9-117181.17" + attribute \src "libresoc.v:126700.9-126700.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 4'1000 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\ds[15:0] \$22 [15:0] case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \ds $0\ds[15:0] end - attribute \src "libresoc.v:117199.3-117209.6" - process $proc$libresoc.v:117199$4650 - assign { } { } + connect \$9 $pos$libresoc.v:126540$4939_Y + connect \$11 $pos$libresoc.v:126541$4941_Y + connect \$14 $sshl$libresoc.v:126542$4942_Y + connect \$17 $sshl$libresoc.v:126543$4943_Y + connect \$1 $pos$libresoc.v:126544$4945_Y + connect \$20 $sshl$libresoc.v:126545$4946_Y + connect \$23 $sshl$libresoc.v:126546$4947_Y + connect \$4 $sshl$libresoc.v:126547$4948_Y + connect \$3 $pos$libresoc.v:126548$4950_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:126718.1-126766.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" +attribute \generator "nMigen" +module \dec_c + attribute \src "libresoc.v:126719.7-126719.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:126736.3-126750.6" + wire width 5 $0\reg_c[4:0] + attribute \src "libresoc.v:126751.3-126765.6" + wire $0\reg_c_ok[0:0] + attribute \src "libresoc.v:126736.3-126750.6" + wire width 5 $1\reg_c[4:0] + attribute \src "libresoc.v:126751.3-126765.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \RS + attribute \src "libresoc.v:126719.7-126719.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:126719.7-126719.20" + process $proc$libresoc.v:126719$4962 assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:117200.5-117200.29" - switch \initial - attribute \src "libresoc.v:117200.9-117200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end + assign $0\initial[0:0] 1'0 sync always - update \move_one $0\move_one[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:117210.3-117230.6" - process $proc$libresoc.v:117210$4651 + attribute \src "libresoc.v:126736.3-126750.6" + process $proc$libresoc.v:126736$4960 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:117211.5-117211.29" + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "libresoc.v:126737.5-126737.29" switch \initial - attribute \src "libresoc.v:117211.9-117211.17" + attribute \src "libresoc.v:126737.9-126737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \SHIFT_ROT_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\reg_c[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c[4:0] \RS case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\reg_c[4:0] 5'00000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:117231.3-117265.6" - process $proc$libresoc.v:117231$4652 + attribute \src "libresoc.v:126751.3-126765.6" + process $proc$libresoc.v:126751$4961 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:117232.5-117232.29" + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "libresoc.v:126752.5-126752.29" switch \initial - attribute \src "libresoc.v:117232.9-117232.17" + attribute \src "libresoc.v:126752.9-126752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \SHIFT_ROT_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\reg_c_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\reg_c_ok[0:0] 1'0 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \reg_c_ok $0\reg_c_ok[0:0] end - connect \$1 $eq$libresoc.v:117143$4645_Y - connect \$3 $eq$libresoc.v:117144$4646_Y end -attribute \src "libresoc.v:117270.1-117509.10" +attribute \src "libresoc.v:126770.1-127102.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_out$201 - attribute \src "libresoc.v:117423.3-117441.6" +module \dec_cr_in + attribute \src "libresoc.v:127022.3-127052.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:117393.3-117411.6" + attribute \src "libresoc.v:127053.3-127063.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126955.3-126965.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:127064.3-127074.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126985.3-126995.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126924.3-126954.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117474.3-117508.6" + attribute \src "libresoc.v:126966.3-126984.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:117412.3-117422.6" + attribute \src "libresoc.v:126996.3-127006.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117271.7-117271.20" + attribute \src "libresoc.v:126771.7-126771.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117442.3-117452.6" + attribute \src "libresoc.v:127075.3-127085.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:117453.3-117473.6" + attribute \src "libresoc.v:127086.3-127101.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:117423.3-117441.6" + attribute \src "libresoc.v:127007.3-127021.6" + wire width 2 $0\sv_override[1:0] + attribute \src "libresoc.v:127022.3-127052.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117393.3-117411.6" + attribute \src "libresoc.v:127053.3-127063.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126955.3-126965.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:127064.3-127074.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126985.3-126995.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126924.3-126954.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117474.3-117508.6" + attribute \src "libresoc.v:126966.3-126984.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:117412.3-117422.6" + attribute \src "libresoc.v:126996.3-127006.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117442.3-117452.6" + attribute \src "libresoc.v:127075.3-127085.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:117453.3-117473.6" + attribute \src "libresoc.v:127086.3-127101.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:117474.3-117508.6" + attribute \src "libresoc.v:127007.3-127021.6" + wire width 2 $1\sv_override[1:0] + attribute \src "libresoc.v:126966.3-126984.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:117453.3-117473.6" + attribute \src "libresoc.v:127086.3-127101.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:117474.3-117508.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:117453.3-117473.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:117474.3-117508.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:117386.17-117386.122" - wire $eq$libresoc.v:117386$4654_Y - attribute \src "libresoc.v:117387.17-117387.122" - wire $eq$libresoc.v:117387$4655_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + attribute \src "libresoc.v:126917.17-126917.112" + wire $and$libresoc.v:126917$4964_Y + attribute \src "libresoc.v:126919.17-126919.112" + wire $and$libresoc.v:126919$4966_Y + attribute \src "libresoc.v:126916.17-126916.117" + wire $eq$libresoc.v:126916$4963_Y + attribute \src "libresoc.v:126918.17-126918.117" + wire $eq$libresoc.v:126918$4965_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 4 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 12 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 11 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 16 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 15 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 13 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 14 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 5 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 7 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 8 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 9 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 10 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 3 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_fxm_ok + attribute \src "libresoc.v:126771.7-126771.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -184346,96 +199850,107 @@ module \dec_cr_out$201 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:117271.7-117271.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 18 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" + attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117386$4654 + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 2 \sv_override + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + cell $and $and$libresoc.v:126917$4964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:126917$4964_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + cell $and $and$libresoc.v:126919$4966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:126919$4966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + cell $eq $eq$libresoc.v:126916$4963 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117386$4654_Y + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:126916$4963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117387$4655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + cell $eq $eq$libresoc.v:126918$4965 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117387$4655_Y + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:126918$4965_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:117388.15-117392.4" - cell \ppick$202 \ppick - connect \en_o \ppick_en_o + attribute \src "libresoc.v:126920.9-126923.4" + cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:117271.7-117271.20" - process $proc$libresoc.v:117271$4662 + attribute \src "libresoc.v:126771.7-126771.20" + process $proc$libresoc.v:126771$4978 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117393.3-117411.6" - process $proc$libresoc.v:117393$4656 + attribute \src "libresoc.v:126924.3-126954.6" + process $proc$libresoc.v:126924$4967 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117394.5-117394.29" + attribute \src "libresoc.v:126925.5-126925.29" switch \initial - attribute \src "libresoc.v:117394.9-117394.17" + attribute \src "libresoc.v:126925.9-126925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } @@ -184444,27 +199959,115 @@ module \dec_cr_out$201 case 3'011 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 case assign $1\cr_bitfield_ok[0:0] 1'0 end sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:117412.3-117422.6" - process $proc$libresoc.v:117412$4657 + attribute \src "libresoc.v:126955.3-126965.6" + process $proc$libresoc.v:126955$4968 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117413.5-117413.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126956.5-126956.29" + switch \initial + attribute \src "libresoc.v:126956.9-126956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:126966.3-126984.6" + process $proc$libresoc.v:126966$4969 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:126967.5-126967.29" + switch \initial + attribute \src "libresoc.v:126967.9-126967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + attribute \src "libresoc.v:126985.3-126995.6" + process $proc$libresoc.v:126985$4970 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126986.5-126986.29" switch \initial - attribute \src "libresoc.v:117413.9-117413.17" + attribute \src "libresoc.v:126986.9-126986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:126996.3-127006.6" + process $proc$libresoc.v:126996$4971 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126997.5-126997.29" + switch \initial + attribute \src "libresoc.v:126997.9-126997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\cr_fxm_ok[0:0] 1'1 case @@ -184473,214 +200076,240 @@ module \dec_cr_out$201 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:117423.3-117441.6" - process $proc$libresoc.v:117423$4658 + attribute \src "libresoc.v:127007.3-127021.6" + process $proc$libresoc.v:127007$4972 + assign { } { } + assign { } { } + assign $0\sv_override[1:0] $1\sv_override[1:0] + attribute \src "libresoc.v:127008.5-127008.29" + switch \initial + attribute \src "libresoc.v:127008.9-127008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\sv_override[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign { } { } + assign $1\sv_override[1:0] 2'10 + case + assign $1\sv_override[1:0] 2'00 + end + sync always + update \sv_override $0\sv_override[1:0] + end + attribute \src "libresoc.v:127022.3-127052.6" + process $proc$libresoc.v:127022$4973 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117424.5-117424.29" + attribute \src "libresoc.v:127023.5-127023.29" switch \initial - attribute \src "libresoc.v:117424.9-117424.17" + attribute \src "libresoc.v:127023.9-127023.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign { } { } + assign $1\cr_bitfield[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\cr_bitfield[2:0] \BI [4:2] attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BC [4:2] case assign $1\cr_bitfield[2:0] 3'000 end sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:117442.3-117452.6" - process $proc$libresoc.v:117442$4659 + attribute \src "libresoc.v:127053.3-127063.6" + process $proc$libresoc.v:127053$4974 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:117443.5-117443.29" + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:127054.5-127054.29" switch \initial - attribute \src "libresoc.v:117443.9-117443.17" + attribute \src "libresoc.v:127054.9-127054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\cr_bitfield_b[2:0] \BB [4:2] case - assign $1\move_one[0:0] 1'0 + assign $1\cr_bitfield_b[2:0] 3'000 end sync always - update \move_one $0\move_one[0:0] + update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:117453.3-117473.6" - process $proc$libresoc.v:117453$4660 + attribute \src "libresoc.v:127064.3-127074.6" + process $proc$libresoc.v:127064$4975 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:117454.5-117454.29" + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:127065.5-127065.29" switch \initial - attribute \src "libresoc.v:117454.9-117454.17" + attribute \src "libresoc.v:127065.9-127065.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \LDST_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\cr_bitfield_o[2:0] \BT [4:2] case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\cr_bitfield_o[2:0] 3'000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:117474.3-117508.6" - process $proc$libresoc.v:117474$4661 + attribute \src "libresoc.v:127075.3-127085.6" + process $proc$libresoc.v:127075$4976 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:117475.5-117475.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:127076.5-127076.29" switch \initial - attribute \src "libresoc.v:117475.9-117475.17" + attribute \src "libresoc.v:127076.9-127076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:127086.3-127101.6" + process $proc$libresoc.v:127086$4977 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:127087.5-127087.29" + switch \initial + attribute \src "libresoc.v:127087.9-127087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \LDST_FXM - end - attribute \src "libresoc.v:0.0-0.0" + assign $2\ppick_i[7:0] \FXM case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\ppick_i[7:0] 8'00000000 end case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \ppick_i $0\ppick_i[7:0] end - connect \$1 $eq$libresoc.v:117386$4654_Y - connect \$3 $eq$libresoc.v:117387$4655_Y + connect \$1 $eq$libresoc.v:126916$4963_Y + connect \$3 $and$libresoc.v:126917$4964_Y + connect \$5 $eq$libresoc.v:126918$4965_Y + connect \$7 $and$libresoc.v:126919$4966_Y end -attribute \src "libresoc.v:117513.1-117756.10" +attribute \src "libresoc.v:127106.1-127376.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$210 - attribute \src "libresoc.v:117670.3-117688.6" +module \dec_cr_out + attribute \src "libresoc.v:127286.3-127308.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:117640.3-117658.6" + attribute \src "libresoc.v:127237.3-127259.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117721.3-117755.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:117659.3-117669.6" + attribute \src "libresoc.v:127260.3-127270.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117514.7-117514.20" + attribute \src "libresoc.v:127107.7-127107.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117689.3-117699.6" + attribute \src "libresoc.v:127309.3-127319.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:117700.3-117720.6" + attribute \src "libresoc.v:127320.3-127340.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:117670.3-117688.6" + attribute \src "libresoc.v:127271.3-127285.6" + wire width 2 $0\sv_override[1:0] + attribute \src "libresoc.v:127286.3-127308.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117640.3-117658.6" + attribute \src "libresoc.v:127237.3-127259.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117721.3-117755.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:117659.3-117669.6" + attribute \src "libresoc.v:127260.3-127270.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117689.3-117699.6" + attribute \src "libresoc.v:127309.3-127319.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:117700.3-117720.6" + attribute \src "libresoc.v:127320.3-127340.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:117721.3-117755.6" + attribute \src "libresoc.v:127271.3-127285.6" + wire width 2 $1\sv_override[1:0] + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:117700.3-117720.6" + attribute \src "libresoc.v:127320.3-127340.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:117721.3-117755.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:117700.3-117720.6" + attribute \src "libresoc.v:127320.3-127340.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:117721.3-117755.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:117633.17-117633.117" - wire $eq$libresoc.v:117633$4663_Y - attribute \src "libresoc.v:117634.17-117634.117" - wire $eq$libresoc.v:117634$4664_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + attribute \src "libresoc.v:127230.17-127230.117" + wire $eq$libresoc.v:127230$4979_Y + attribute \src "libresoc.v:127231.17-127231.117" + wire $eq$libresoc.v:127231$4980_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 3 input 9 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 6 \cr_bitfield @@ -184690,10 +200319,10 @@ module \dec_cr_out$210 wire width 8 output 4 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:117514.7-117514.15" + attribute \src "libresoc.v:127107.7-127107.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 11 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -184768,28 +200397,32 @@ module \dec_cr_out$210 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 11 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:637" wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" + wire input 3 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117633$4663 + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:599" + wire width 2 \sv_override + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + cell $eq $eq$libresoc.v:127230$4979 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -184797,10 +200430,10 @@ module \dec_cr_out$210 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:117633$4663_Y + connect \Y $eq$libresoc.v:127230$4979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117634$4664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + cell $eq $eq$libresoc.v:127231$4980 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -184808,41 +200441,45 @@ module \dec_cr_out$210 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:117634$4664_Y + connect \Y $eq$libresoc.v:127231$4980_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:117635.15-117639.4" - cell \ppick$211 \ppick + attribute \src "libresoc.v:127232.15-127236.4" + cell \ppick$175 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:117514.7-117514.20" - process $proc$libresoc.v:117514$4671 + attribute \src "libresoc.v:127107.7-127107.20" + process $proc$libresoc.v:127107$4988 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117640.3-117658.6" - process $proc$libresoc.v:117640$4665 + attribute \src "libresoc.v:127237.3-127259.6" + process $proc$libresoc.v:127237$4981 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117641.5-117641.29" + attribute \src "libresoc.v:127238.5-127238.29" switch \initial - attribute \src "libresoc.v:117641.9-117641.17" + attribute \src "libresoc.v:127238.9-127238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 @@ -184856,18 +200493,18 @@ module \dec_cr_out$210 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:117659.3-117669.6" - process $proc$libresoc.v:117659$4666 + attribute \src "libresoc.v:127260.3-127270.6" + process $proc$libresoc.v:127260$4982 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117660.5-117660.29" + attribute \src "libresoc.v:127261.5-127261.29" switch \initial - attribute \src "libresoc.v:117660.9-117660.17" + attribute \src "libresoc.v:127261.9-127261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -184879,24 +200516,55 @@ module \dec_cr_out$210 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:117670.3-117688.6" - process $proc$libresoc.v:117670$4667 + attribute \src "libresoc.v:127271.3-127285.6" + process $proc$libresoc.v:127271$4983 + assign { } { } + assign { } { } + assign $0\sv_override[1:0] $1\sv_override[1:0] + attribute \src "libresoc.v:127272.5-127272.29" + switch \initial + attribute \src "libresoc.v:127272.9-127272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\sv_override[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\sv_override[1:0] 2'10 + case + assign $1\sv_override[1:0] 2'00 + end + sync always + update \sv_override $0\sv_override[1:0] + end + attribute \src "libresoc.v:127286.3-127308.6" + process $proc$libresoc.v:127286$4984 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117671.5-117671.29" + attribute \src "libresoc.v:127287.5-127287.29" switch \initial - attribute \src "libresoc.v:117671.9-117671.17" + attribute \src "libresoc.v:127287.9-127287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\cr_bitfield[2:0] \X_BF @@ -184910,18 +200578,18 @@ module \dec_cr_out$210 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:117689.3-117699.6" - process $proc$libresoc.v:117689$4668 + attribute \src "libresoc.v:127309.3-127319.6" + process $proc$libresoc.v:127309$4985 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:117690.5-117690.29" + attribute \src "libresoc.v:127310.5-127310.29" switch \initial - attribute \src "libresoc.v:117690.9-117690.17" + attribute \src "libresoc.v:127310.9-127310.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -184933,30 +200601,30 @@ module \dec_cr_out$210 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:117700.3-117720.6" - process $proc$libresoc.v:117700$4669 + attribute \src "libresoc.v:127320.3-127340.6" + process $proc$libresoc.v:127320$4986 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:117701.5-117701.29" + attribute \src "libresoc.v:127321.5-127321.29" switch \initial - attribute \src "libresoc.v:117701.9-117701.17" + attribute \src "libresoc.v:127321.9-127321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -184974,36 +200642,36 @@ module \dec_cr_out$210 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:117721.3-117755.6" - process $proc$libresoc.v:117721$4670 + attribute \src "libresoc.v:127341.3-127375.6" + process $proc$libresoc.v:127341$4987 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:117722.5-117722.29" + attribute \src "libresoc.v:127342.5-127342.29" switch \initial - attribute \src "libresoc.v:117722.9-117722.17" + attribute \src "libresoc.v:127342.9-127342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -185030,95 +200698,95 @@ module \dec_cr_out$210 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:117633$4663_Y - connect \$3 $eq$libresoc.v:117634$4664_Y + connect \$1 $eq$libresoc.v:127230$4979_Y + connect \$3 $eq$libresoc.v:127231$4980_Y end -attribute \src "libresoc.v:117760.1-118237.10" +attribute \src "libresoc.v:127380.1-127865.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:117761.7-117761.20" + attribute \src "libresoc.v:127381.7-127381.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118124.3-118138.6" + attribute \src "libresoc.v:127752.3-127766.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:118139.3-118153.6" + attribute \src "libresoc.v:127767.3-127781.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:118154.3-118164.6" + attribute \src "libresoc.v:127782.3-127792.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:118181.3-118197.6" + attribute \src "libresoc.v:127809.3-127825.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:118181.3-118197.6" + attribute \src "libresoc.v:127809.3-127825.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:118165.3-118180.6" + attribute \src "libresoc.v:127793.3-127808.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:118124.3-118138.6" + attribute \src "libresoc.v:127752.3-127766.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:118139.3-118153.6" + attribute \src "libresoc.v:127767.3-127781.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:118154.3-118164.6" + attribute \src "libresoc.v:127782.3-127792.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:118181.3-118197.6" + attribute \src "libresoc.v:127809.3-127825.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:118181.3-118197.6" + attribute \src "libresoc.v:127809.3-127825.6" wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:118165.3-118180.6" + attribute \src "libresoc.v:127793.3-127808.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:118181.3-118197.6" + attribute \src "libresoc.v:127809.3-127825.6" wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:118181.3-118197.6" + attribute \src "libresoc.v:127809.3-127825.6" wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:118165.3-118180.6" + attribute \src "libresoc.v:127793.3-127808.6" wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:118198.3-118236.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:118113.17-118113.117" - wire $eq$libresoc.v:118113$4672_Y - attribute \src "libresoc.v:118114.17-118114.117" - wire $eq$libresoc.v:118114$4673_Y - attribute \src "libresoc.v:118115.17-118115.117" - wire $eq$libresoc.v:118115$4674_Y - attribute \src "libresoc.v:118116.17-118116.104" - wire $not$libresoc.v:118116$4675_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + attribute \src "libresoc.v:127741.17-127741.117" + wire $eq$libresoc.v:127741$4989_Y + attribute \src "libresoc.v:127742.17-127742.117" + wire $eq$libresoc.v:127742$4990_Y + attribute \src "libresoc.v:127743.17-127743.117" + wire $eq$libresoc.v:127743$4991_Y + attribute \src "libresoc.v:127744.17-127744.104" + wire $not$libresoc.v:127744$4992_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 10 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 9 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 input 11 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 6 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 7 \fast_o_ok - attribute \src "libresoc.v:117761.7-117761.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 11 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 10 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 9 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 input 1 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 7 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 8 \fast_o_ok + attribute \src "libresoc.v:127381.7-127381.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -185194,20 +200862,22 @@ module \dec_o attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 12 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 2 \reg_o + wire width 5 output 3 \reg_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \reg_o_ok + wire output 4 \reg_o_ok attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - wire width 2 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -185274,6 +200944,9 @@ module \dec_o attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -185321,14 +200994,14 @@ module \dec_o attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 output 4 \spr_o + wire width 10 output 5 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \spr_o_ok + wire output 6 \spr_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -185395,6 +201068,9 @@ module \dec_o attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -185445,8 +201121,8 @@ module \dec_o wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - cell $eq $eq$libresoc.v:118113$4672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + cell $eq $eq$libresoc.v:127741$4989 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185454,10 +201130,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:118113$4672_Y + connect \Y $eq$libresoc.v:127741$4989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - cell $eq $eq$libresoc.v:118114$4673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + cell $eq $eq$libresoc.v:127742$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185465,10 +201141,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:118114$4673_Y + connect \Y $eq$libresoc.v:127742$4990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - cell $eq $eq$libresoc.v:118115$4674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + cell $eq $eq$libresoc.v:127743$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185476,52 +201152,52 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:118115$4674_Y + connect \Y $eq$libresoc.v:127743$4991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" - cell $not $not$libresoc.v:118116$4675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + cell $not $not$libresoc.v:127744$4992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:118116$4675_Y + connect \Y $not$libresoc.v:127744$4992_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:118117.16-118123.4" - cell \sprmap$212 \sprmap + attribute \src "libresoc.v:127745.16-127751.4" + cell \sprmap$174 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok connect \spr_i \sprmap_spr_i connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:117761.7-117761.20" - process $proc$libresoc.v:117761$4682 + attribute \src "libresoc.v:127381.7-127381.20" + process $proc$libresoc.v:127381$4999 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118124.3-118138.6" - process $proc$libresoc.v:118124$4676 + attribute \src "libresoc.v:127752.3-127766.6" + process $proc$libresoc.v:127752$4993 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:118125.5-118125.29" + attribute \src "libresoc.v:127753.5-127753.29" switch \initial - attribute \src "libresoc.v:118125.9-118125.17" + attribute \src "libresoc.v:127753.9-127753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'001 assign { } { } assign $1\reg_o[4:0] \RT attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 3'010 assign { } { } assign $1\reg_o[4:0] \RA case @@ -185530,25 +201206,25 @@ module \dec_o sync always update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:118139.3-118153.6" - process $proc$libresoc.v:118139$4677 + attribute \src "libresoc.v:127767.3-127781.6" + process $proc$libresoc.v:127767$4994 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:118140.5-118140.29" + attribute \src "libresoc.v:127768.5-127768.29" switch \initial - attribute \src "libresoc.v:118140.9-118140.17" + attribute \src "libresoc.v:127768.9-127768.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'001 assign { } { } assign $1\reg_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 3'010 assign { } { } assign $1\reg_o_ok[0:0] 1'1 case @@ -185557,21 +201233,21 @@ module \dec_o sync always update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:118154.3-118164.6" - process $proc$libresoc.v:118154$4678 + attribute \src "libresoc.v:127782.3-127792.6" + process $proc$libresoc.v:127782$4995 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:118155.5-118155.29" + attribute \src "libresoc.v:127783.5-127783.29" switch \initial - attribute \src "libresoc.v:118155.9-118155.17" + attribute \src "libresoc.v:127783.9-127783.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 assign { } { } assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case @@ -185580,24 +201256,24 @@ module \dec_o sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:118165.3-118180.6" - process $proc$libresoc.v:118165$4679 + attribute \src "libresoc.v:127793.3-127808.6" + process $proc$libresoc.v:127793$4996 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:118166.5-118166.29" + attribute \src "libresoc.v:127794.5-127794.29" switch \initial - attribute \src "libresoc.v:118166.9-118166.17" + attribute \src "libresoc.v:127794.9-127794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 assign { } { } assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -185612,29 +201288,29 @@ module \dec_o sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:118181.3-118197.6" - process $proc$libresoc.v:118181$4680 + attribute \src "libresoc.v:127809.3-127825.6" + process $proc$libresoc.v:127809$4997 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:118182.5-118182.29" + attribute \src "libresoc.v:127810.5-127810.29" switch \initial - attribute \src "libresoc.v:118182.9-118182.17" + attribute \src "libresoc.v:127810.9-127810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 assign { } { } assign { } { } assign $1\spr_o[9:0] $2\spr_o[9:0] assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -185653,8 +201329,8 @@ module \dec_o update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:118198.3-118236.6" - process $proc$libresoc.v:118198$4681 + attribute \src "libresoc.v:127826.3-127864.6" + process $proc$libresoc.v:127826$4998 assign { } { } assign { } { } assign { } { } @@ -185663,21 +201339,21 @@ module \dec_o assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:118199.5-118199.29" + attribute \src "libresoc.v:127827.5-127827.29" switch \initial - attribute \src "libresoc.v:118199.9-118199.17" + attribute \src "libresoc.v:127827.9-127827.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 assign { } { } assign { } { } assign $1\fast_o[2:0] $2\fast_o[2:0] assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -185692,7 +201368,7 @@ module \dec_o assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0001000 @@ -185700,7 +201376,7 @@ module \dec_o assign { } { } assign $3\fast_o[2:0] $4\fast_o[2:0] assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -185726,55 +201402,53 @@ module \dec_o update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:118113$4672_Y - connect \$3 $eq$libresoc.v:118114$4673_Y - connect \$5 $eq$libresoc.v:118115$4674_Y - connect \$7 $not$libresoc.v:118116$4675_Y + connect \$1 $eq$libresoc.v:127741$4989_Y + connect \$3 $eq$libresoc.v:127742$4990_Y + connect \$5 $eq$libresoc.v:127743$4991_Y + connect \$7 $not$libresoc.v:127744$4992_Y end -attribute \src "libresoc.v:118241.1-118402.10" +attribute \src "libresoc.v:127869.1-128037.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 - attribute \src "libresoc.v:118362.3-118381.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:118382.3-118401.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:118242.7-118242.20" + attribute \src "libresoc.v:127997.3-128016.6" + wire width 3 $0\fast_o2[2:0] + attribute \src "libresoc.v:128017.3-128036.6" + wire $0\fast_o2_ok[0:0] + attribute \src "libresoc.v:127870.7-127870.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118348.3-118361.6" - wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:118348.3-118361.6" - wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:118362.3-118381.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:118382.3-118401.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:118348.3-118361.6" - wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:118348.3-118361.6" - wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:118362.3-118381.6" - wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:118382.3-118401.6" - wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:118346.17-118346.108" - wire $eq$libresoc.v:118346$4683_Y - attribute \src "libresoc.v:118347.17-118347.100" - wire width 6 $extend$libresoc.v:118347$4684_Y - attribute \src "libresoc.v:118347.17-118347.100" - wire width 6 $pos$libresoc.v:118347$4685_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + attribute \src "libresoc.v:127977.3-127986.6" + wire width 5 $0\reg_o2[4:0] + attribute \src "libresoc.v:127987.3-127996.6" + wire $0\reg_o2_ok[0:0] + attribute \src "libresoc.v:127997.3-128016.6" + wire width 3 $1\fast_o2[2:0] + attribute \src "libresoc.v:128017.3-128036.6" + wire $1\fast_o2_ok[0:0] + attribute \src "libresoc.v:127977.3-127986.6" + wire width 5 $1\reg_o2[4:0] + attribute \src "libresoc.v:127987.3-127996.6" + wire $1\reg_o2_ok[0:0] + attribute \src "libresoc.v:127997.3-128016.6" + wire width 3 $2\fast_o2[2:0] + attribute \src "libresoc.v:128017.3-128036.6" + wire $2\fast_o2_ok[0:0] + attribute \src "libresoc.v:127975.17-127975.108" + wire $eq$libresoc.v:127975$5000_Y + attribute \src "libresoc.v:127976.17-127976.108" + wire $eq$libresoc.v:127976$5001_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 7 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 4 \fast_o + wire width 3 output 4 \fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \fast_o_ok - attribute \src "libresoc.v:118242.7-118242.15" + wire output 5 \fast_o2_ok + attribute \src "libresoc.v:127870.7-127870.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -185850,23 +201524,24 @@ module \dec_o2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" wire input 1 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 2 \reg_o + wire width 5 output 2 \reg_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \reg_o_ok + wire output 3 \reg_o2_ok attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" - cell $eq $eq$libresoc.v:118346$4683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + cell $eq $eq$libresoc.v:127975$5000 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -185874,157 +201549,168 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:118346$4683_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:118347$4684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A \RA - connect \Y $extend$libresoc.v:118347$4684_Y + connect \Y $eq$libresoc.v:127975$5000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:118347$4685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + cell $eq $eq$libresoc.v:127976$5001 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $extend$libresoc.v:118347$4684_Y - connect \Y $pos$libresoc.v:118347$4685_Y + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:127976$5001_Y end - attribute \src "libresoc.v:118242.7-118242.20" - process $proc$libresoc.v:118242$4689 + attribute \src "libresoc.v:127870.7-127870.20" + process $proc$libresoc.v:127870$5006 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118348.3-118361.6" - process $proc$libresoc.v:118348$4686 - assign { } { } - assign { } { } + attribute \src "libresoc.v:127977.3-127986.6" + process $proc$libresoc.v:127977$5002 assign { } { } assign { } { } - assign $0\reg_o[4:0] $1\reg_o[4:0] - assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:118349.5-118349.29" + assign $0\reg_o2[4:0] $1\reg_o2[4:0] + attribute \src "libresoc.v:127978.5-127978.29" switch \initial - attribute \src "libresoc.v:118349.9-118349.17" + attribute \src "libresoc.v:127978.9-127978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $1\reg_o2[4:0] \RA + case + assign $1\reg_o2[4:0] 5'00000 + end + sync always + update \reg_o2 $0\reg_o2[4:0] + end + attribute \src "libresoc.v:127987.3-127996.6" + process $proc$libresoc.v:127987$5003 + assign { } { } + assign { } { } + assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] + attribute \src "libresoc.v:127988.5-127988.29" + switch \initial + attribute \src "libresoc.v:127988.9-127988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\reg_o[4:0] \$3 [4:0] - assign $1\reg_o_ok[0:0] 1'1 + assign $1\reg_o2_ok[0:0] 1'1 case - assign $1\reg_o[4:0] 5'00000 - assign $1\reg_o_ok[0:0] 1'0 + assign $1\reg_o2_ok[0:0] 1'0 end sync always - update \reg_o $0\reg_o[4:0] - update \reg_o_ok $0\reg_o_ok[0:0] + update \reg_o2_ok $0\reg_o2_ok[0:0] end - attribute \src "libresoc.v:118362.3-118381.6" - process $proc$libresoc.v:118362$4687 + attribute \src "libresoc.v:127997.3-128016.6" + process $proc$libresoc.v:127997$5004 assign { } { } assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:118363.5-118363.29" + assign $0\fast_o2[2:0] $1\fast_o2[2:0] + attribute \src "libresoc.v:127998.5-127998.29" switch \initial - attribute \src "libresoc.v:118363.9-118363.17" + attribute \src "libresoc.v:127998.9-127998.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + assign $1\fast_o2[2:0] $2\fast_o2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast_o[2:0] 3'001 + assign $2\fast_o2[2:0] 3'001 case - assign $2\fast_o[2:0] 3'000 + assign $2\fast_o2[2:0] 3'000 end attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign { } { } - assign $1\fast_o[2:0] 3'100 + assign $1\fast_o2[2:0] 3'100 case - assign $1\fast_o[2:0] 3'000 + assign $1\fast_o2[2:0] 3'000 end sync always - update \fast_o $0\fast_o[2:0] + update \fast_o2 $0\fast_o2[2:0] end - attribute \src "libresoc.v:118382.3-118401.6" - process $proc$libresoc.v:118382$4688 + attribute \src "libresoc.v:128017.3-128036.6" + process $proc$libresoc.v:128017$5005 assign { } { } assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:118383.5-118383.29" + assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] + attribute \src "libresoc.v:128018.5-128018.29" switch \initial - attribute \src "libresoc.v:118383.9-118383.17" + attribute \src "libresoc.v:128018.9-128018.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast_o_ok[0:0] 1'1 + assign $2\fast_o2_ok[0:0] 1'1 case - assign $2\fast_o_ok[0:0] 1'0 + assign $2\fast_o2_ok[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\fast_o2_ok[0:0] 1'1 case - assign $1\fast_o_ok[0:0] 1'0 + assign $1\fast_o2_ok[0:0] 1'0 end sync always - update \fast_o_ok $0\fast_o_ok[0:0] + update \fast_o2_ok $0\fast_o2_ok[0:0] end - connect \$1 $eq$libresoc.v:118346$4683_Y - connect \$3 $pos$libresoc.v:118347$4685_Y + connect \$1 $eq$libresoc.v:127975$5000_Y + connect \$3 $eq$libresoc.v:127976$5001_Y end -attribute \src "libresoc.v:118406.1-118540.10" +attribute \src "libresoc.v:128041.1-128176.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe - attribute \src "libresoc.v:118407.7-118407.20" + attribute \src "libresoc.v:128042.7-128042.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118498.3-118518.6" + attribute \src "libresoc.v:128134.3-128154.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118519.3-118539.6" + attribute \src "libresoc.v:128155.3-128175.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118498.3-118518.6" + attribute \src "libresoc.v:128134.3-128154.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118519.3-118539.6" + attribute \src "libresoc.v:128155.3-128175.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118498.3-118518.6" + attribute \src "libresoc.v:128134.3-128154.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118519.3-118539.6" + attribute \src "libresoc.v:128155.3-128175.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \ALU_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -186100,9 +201786,10 @@ module \dec_oe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:118407.7-118407.15" + attribute \src "libresoc.v:128042.7-128042.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -186112,28 +201799,28 @@ module \dec_oe attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118407.7-118407.20" - process $proc$libresoc.v:118407$4692 + attribute \src "libresoc.v:128042.7-128042.20" + process $proc$libresoc.v:128042$5009 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118498.3-118518.6" - process $proc$libresoc.v:118498$4690 + attribute \src "libresoc.v:128134.3-128154.6" + process $proc$libresoc.v:128134$5007 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118499.5-118499.29" + attribute \src "libresoc.v:128135.5-128135.29" switch \initial - attribute \src "libresoc.v:118499.9-118499.17" + attribute \src "libresoc.v:128135.9-128135.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186142,7 +201829,7 @@ module \dec_oe case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186155,18 +201842,18 @@ module \dec_oe sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118519.3-118539.6" - process $proc$libresoc.v:118519$4691 + attribute \src "libresoc.v:128155.3-128175.6" + process $proc$libresoc.v:128155$5008 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118520.5-118520.29" + attribute \src "libresoc.v:128156.5-128156.29" switch \initial - attribute \src "libresoc.v:118520.9-118520.17" + attribute \src "libresoc.v:128156.9-128156.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186175,7 +201862,7 @@ module \dec_oe case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186189,26 +201876,26 @@ module \dec_oe update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118544.1-118676.10" +attribute \src "libresoc.v:128180.1-128313.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" -module \dec_oe$142 - attribute \src "libresoc.v:118545.7-118545.20" +module \dec_oe$140 + attribute \src "libresoc.v:128181.7-128181.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118634.3-118654.6" + attribute \src "libresoc.v:128271.3-128291.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118655.3-118675.6" + attribute \src "libresoc.v:128292.3-128312.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118634.3-118654.6" + attribute \src "libresoc.v:128271.3-128291.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118655.3-118675.6" + attribute \src "libresoc.v:128292.3-128312.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118634.3-118654.6" + attribute \src "libresoc.v:128271.3-128291.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118655.3-118675.6" + attribute \src "libresoc.v:128292.3-128312.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 2 \CR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -186284,9 +201971,10 @@ module \dec_oe$142 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:118545.7-118545.15" + attribute \src "libresoc.v:128181.7-128181.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -186296,28 +201984,28 @@ module \dec_oe$142 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:118545.7-118545.20" - process $proc$libresoc.v:118545$4695 + attribute \src "libresoc.v:128181.7-128181.20" + process $proc$libresoc.v:128181$5012 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118634.3-118654.6" - process $proc$libresoc.v:118634$4693 + attribute \src "libresoc.v:128271.3-128291.6" + process $proc$libresoc.v:128271$5010 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118635.5-118635.29" + attribute \src "libresoc.v:128272.5-128272.29" switch \initial - attribute \src "libresoc.v:118635.9-118635.17" + attribute \src "libresoc.v:128272.9-128272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186326,7 +202014,7 @@ module \dec_oe$142 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186339,18 +202027,18 @@ module \dec_oe$142 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118655.3-118675.6" - process $proc$libresoc.v:118655$4694 + attribute \src "libresoc.v:128292.3-128312.6" + process $proc$libresoc.v:128292$5011 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118656.5-118656.29" + attribute \src "libresoc.v:128293.5-128293.29" switch \initial - attribute \src "libresoc.v:118656.9-118656.17" + attribute \src "libresoc.v:128293.9-128293.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186359,7 +202047,7 @@ module \dec_oe$142 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186373,26 +202061,26 @@ module \dec_oe$142 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118680.1-118812.10" +attribute \src "libresoc.v:128317.1-128450.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" -module \dec_oe$149 - attribute \src "libresoc.v:118681.7-118681.20" +module \dec_oe$143 + attribute \src "libresoc.v:128318.7-128318.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118770.3-118790.6" + attribute \src "libresoc.v:128408.3-128428.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118791.3-118811.6" + attribute \src "libresoc.v:128429.3-128449.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118770.3-118790.6" + attribute \src "libresoc.v:128408.3-128428.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118791.3-118811.6" + attribute \src "libresoc.v:128429.3-128449.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118770.3-118790.6" + attribute \src "libresoc.v:128408.3-128428.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118791.3-118811.6" + attribute \src "libresoc.v:128429.3-128449.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 2 \BRANCH_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -186468,9 +202156,10 @@ module \dec_oe$149 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:118681.7-118681.15" + attribute \src "libresoc.v:128318.7-128318.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -186480,28 +202169,28 @@ module \dec_oe$149 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:118681.7-118681.20" - process $proc$libresoc.v:118681$4698 + attribute \src "libresoc.v:128318.7-128318.20" + process $proc$libresoc.v:128318$5015 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118770.3-118790.6" - process $proc$libresoc.v:118770$4696 + attribute \src "libresoc.v:128408.3-128428.6" + process $proc$libresoc.v:128408$5013 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118771.5-118771.29" + attribute \src "libresoc.v:128409.5-128409.29" switch \initial - attribute \src "libresoc.v:118771.9-118771.17" + attribute \src "libresoc.v:128409.9-128409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186510,7 +202199,7 @@ module \dec_oe$149 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186523,18 +202212,18 @@ module \dec_oe$149 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118791.3-118811.6" - process $proc$libresoc.v:118791$4697 + attribute \src "libresoc.v:128429.3-128449.6" + process $proc$libresoc.v:128429$5014 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118792.5-118792.29" + attribute \src "libresoc.v:128430.5-128430.29" switch \initial - attribute \src "libresoc.v:118792.9-118792.17" + attribute \src "libresoc.v:128430.9-128430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186543,7 +202232,7 @@ module \dec_oe$149 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186557,26 +202246,26 @@ module \dec_oe$149 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118816.1-118950.10" +attribute \src "libresoc.v:128454.1-128589.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" -module \dec_oe$157 - attribute \src "libresoc.v:118817.7-118817.20" +module \dec_oe$147 + attribute \src "libresoc.v:128455.7-128455.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118908.3-118928.6" + attribute \src "libresoc.v:128547.3-128567.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118929.3-118949.6" + attribute \src "libresoc.v:128568.3-128588.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118908.3-118928.6" + attribute \src "libresoc.v:128547.3-128567.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118929.3-118949.6" + attribute \src "libresoc.v:128568.3-128588.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118908.3-118928.6" + attribute \src "libresoc.v:128547.3-128567.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118929.3-118949.6" + attribute \src "libresoc.v:128568.3-128588.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \LOGICAL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -186652,9 +202341,10 @@ module \dec_oe$157 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:118817.7-118817.15" + attribute \src "libresoc.v:128455.7-128455.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -186664,28 +202354,28 @@ module \dec_oe$157 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118817.7-118817.20" - process $proc$libresoc.v:118817$4701 + attribute \src "libresoc.v:128455.7-128455.20" + process $proc$libresoc.v:128455$5018 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118908.3-118928.6" - process $proc$libresoc.v:118908$4699 + attribute \src "libresoc.v:128547.3-128567.6" + process $proc$libresoc.v:128547$5016 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118909.5-118909.29" + attribute \src "libresoc.v:128548.5-128548.29" switch \initial - attribute \src "libresoc.v:118909.9-118909.17" + attribute \src "libresoc.v:128548.9-128548.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186694,7 +202384,7 @@ module \dec_oe$157 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186707,18 +202397,18 @@ module \dec_oe$157 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118929.3-118949.6" - process $proc$libresoc.v:118929$4700 + attribute \src "libresoc.v:128568.3-128588.6" + process $proc$libresoc.v:128568$5017 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118930.5-118930.29" + attribute \src "libresoc.v:128569.5-128569.29" switch \initial - attribute \src "libresoc.v:118930.9-118930.17" + attribute \src "libresoc.v:128569.9-128569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186727,7 +202417,7 @@ module \dec_oe$157 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186741,26 +202431,26 @@ module \dec_oe$157 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118954.1-119086.10" +attribute \src "libresoc.v:128593.1-128726.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" -module \dec_oe$166 - attribute \src "libresoc.v:118955.7-118955.20" +module \dec_oe$152 + attribute \src "libresoc.v:128594.7-128594.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119044.3-119064.6" + attribute \src "libresoc.v:128684.3-128704.6" wire $0\oe[0:0] - attribute \src "libresoc.v:119065.3-119085.6" + attribute \src "libresoc.v:128705.3-128725.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119044.3-119064.6" + attribute \src "libresoc.v:128684.3-128704.6" wire $1\oe[0:0] - attribute \src "libresoc.v:119065.3-119085.6" + attribute \src "libresoc.v:128705.3-128725.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119044.3-119064.6" + attribute \src "libresoc.v:128684.3-128704.6" wire $2\oe[0:0] - attribute \src "libresoc.v:119065.3-119085.6" + attribute \src "libresoc.v:128705.3-128725.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 2 \SPR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -186836,9 +202526,10 @@ module \dec_oe$166 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:118955.7-118955.15" + attribute \src "libresoc.v:128594.7-128594.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -186848,28 +202539,28 @@ module \dec_oe$166 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:118955.7-118955.20" - process $proc$libresoc.v:118955$4704 + attribute \src "libresoc.v:128594.7-128594.20" + process $proc$libresoc.v:128594$5021 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119044.3-119064.6" - process $proc$libresoc.v:119044$4702 + attribute \src "libresoc.v:128684.3-128704.6" + process $proc$libresoc.v:128684$5019 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119045.5-119045.29" + attribute \src "libresoc.v:128685.5-128685.29" switch \initial - attribute \src "libresoc.v:119045.9-119045.17" + attribute \src "libresoc.v:128685.9-128685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186878,7 +202569,7 @@ module \dec_oe$166 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186891,18 +202582,18 @@ module \dec_oe$166 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:119065.3-119085.6" - process $proc$libresoc.v:119065$4703 + attribute \src "libresoc.v:128705.3-128725.6" + process $proc$libresoc.v:128705$5020 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119066.5-119066.29" + attribute \src "libresoc.v:128706.5-128706.29" switch \initial - attribute \src "libresoc.v:119066.9-119066.17" + attribute \src "libresoc.v:128706.9-128706.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186911,7 +202602,7 @@ module \dec_oe$166 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186925,26 +202616,26 @@ module \dec_oe$166 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:119090.1-119224.10" +attribute \src "libresoc.v:128730.1-128865.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" -module \dec_oe$173 - attribute \src "libresoc.v:119091.7-119091.20" +module \dec_oe$155 + attribute \src "libresoc.v:128731.7-128731.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119182.3-119202.6" + attribute \src "libresoc.v:128823.3-128843.6" wire $0\oe[0:0] - attribute \src "libresoc.v:119203.3-119223.6" + attribute \src "libresoc.v:128844.3-128864.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119182.3-119202.6" + attribute \src "libresoc.v:128823.3-128843.6" wire $1\oe[0:0] - attribute \src "libresoc.v:119203.3-119223.6" + attribute \src "libresoc.v:128844.3-128864.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119182.3-119202.6" + attribute \src "libresoc.v:128823.3-128843.6" wire $2\oe[0:0] - attribute \src "libresoc.v:119203.3-119223.6" + attribute \src "libresoc.v:128844.3-128864.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \DIV_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -187020,9 +202711,10 @@ module \dec_oe$173 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:119091.7-119091.15" + attribute \src "libresoc.v:128731.7-128731.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -187032,28 +202724,28 @@ module \dec_oe$173 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119091.7-119091.20" - process $proc$libresoc.v:119091$4707 + attribute \src "libresoc.v:128731.7-128731.20" + process $proc$libresoc.v:128731$5024 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119182.3-119202.6" - process $proc$libresoc.v:119182$4705 + attribute \src "libresoc.v:128823.3-128843.6" + process $proc$libresoc.v:128823$5022 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119183.5-119183.29" + attribute \src "libresoc.v:128824.5-128824.29" switch \initial - attribute \src "libresoc.v:119183.9-119183.17" + attribute \src "libresoc.v:128824.9-128824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187062,7 +202754,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187075,18 +202767,18 @@ module \dec_oe$173 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:119203.3-119223.6" - process $proc$libresoc.v:119203$4706 + attribute \src "libresoc.v:128844.3-128864.6" + process $proc$libresoc.v:128844$5023 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119204.5-119204.29" + attribute \src "libresoc.v:128845.5-128845.29" switch \initial - attribute \src "libresoc.v:119204.9-119204.17" + attribute \src "libresoc.v:128845.9-128845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187095,7 +202787,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187109,26 +202801,26 @@ module \dec_oe$173 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:119228.1-119362.10" +attribute \src "libresoc.v:128869.1-129004.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" -module \dec_oe$182 - attribute \src "libresoc.v:119229.7-119229.20" +module \dec_oe$160 + attribute \src "libresoc.v:128870.7-128870.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119320.3-119340.6" + attribute \src "libresoc.v:128962.3-128982.6" wire $0\oe[0:0] - attribute \src "libresoc.v:119341.3-119361.6" + attribute \src "libresoc.v:128983.3-129003.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119320.3-119340.6" + attribute \src "libresoc.v:128962.3-128982.6" wire $1\oe[0:0] - attribute \src "libresoc.v:119341.3-119361.6" + attribute \src "libresoc.v:128983.3-129003.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119320.3-119340.6" + attribute \src "libresoc.v:128962.3-128982.6" wire $2\oe[0:0] - attribute \src "libresoc.v:119341.3-119361.6" + attribute \src "libresoc.v:128983.3-129003.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \MUL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -187204,9 +202896,10 @@ module \dec_oe$182 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:119229.7-119229.15" + attribute \src "libresoc.v:128870.7-128870.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -187216,28 +202909,28 @@ module \dec_oe$182 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119229.7-119229.20" - process $proc$libresoc.v:119229$4710 + attribute \src "libresoc.v:128870.7-128870.20" + process $proc$libresoc.v:128870$5027 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119320.3-119340.6" - process $proc$libresoc.v:119320$4708 + attribute \src "libresoc.v:128962.3-128982.6" + process $proc$libresoc.v:128962$5025 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119321.5-119321.29" + attribute \src "libresoc.v:128963.5-128963.29" switch \initial - attribute \src "libresoc.v:119321.9-119321.17" + attribute \src "libresoc.v:128963.9-128963.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187246,7 +202939,7 @@ module \dec_oe$182 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187259,18 +202952,18 @@ module \dec_oe$182 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:119341.3-119361.6" - process $proc$libresoc.v:119341$4709 + attribute \src "libresoc.v:128983.3-129003.6" + process $proc$libresoc.v:128983$5026 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119342.5-119342.29" + attribute \src "libresoc.v:128984.5-128984.29" switch \initial - attribute \src "libresoc.v:119342.9-119342.17" + attribute \src "libresoc.v:128984.9-128984.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187279,7 +202972,7 @@ module \dec_oe$182 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187293,26 +202986,26 @@ module \dec_oe$182 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:119366.1-119500.10" +attribute \src "libresoc.v:129008.1-129143.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" -module \dec_oe$190 - attribute \src "libresoc.v:119367.7-119367.20" +module \dec_oe$164 + attribute \src "libresoc.v:129009.7-129009.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119458.3-119478.6" + attribute \src "libresoc.v:129101.3-129121.6" wire $0\oe[0:0] - attribute \src "libresoc.v:119479.3-119499.6" + attribute \src "libresoc.v:129122.3-129142.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119458.3-119478.6" + attribute \src "libresoc.v:129101.3-129121.6" wire $1\oe[0:0] - attribute \src "libresoc.v:119479.3-119499.6" + attribute \src "libresoc.v:129122.3-129142.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119458.3-119478.6" + attribute \src "libresoc.v:129101.3-129121.6" wire $2\oe[0:0] - attribute \src "libresoc.v:119479.3-119499.6" + attribute \src "libresoc.v:129122.3-129142.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \SHIFT_ROT_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -187388,9 +203081,10 @@ module \dec_oe$190 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:119367.7-119367.15" + attribute \src "libresoc.v:129009.7-129009.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -187400,28 +203094,28 @@ module \dec_oe$190 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119367.7-119367.20" - process $proc$libresoc.v:119367$4713 + attribute \src "libresoc.v:129009.7-129009.20" + process $proc$libresoc.v:129009$5030 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119458.3-119478.6" - process $proc$libresoc.v:119458$4711 + attribute \src "libresoc.v:129101.3-129121.6" + process $proc$libresoc.v:129101$5028 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119459.5-119459.29" + attribute \src "libresoc.v:129102.5-129102.29" switch \initial - attribute \src "libresoc.v:119459.9-119459.17" + attribute \src "libresoc.v:129102.9-129102.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187430,7 +203124,7 @@ module \dec_oe$190 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187443,18 +203137,18 @@ module \dec_oe$190 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:119479.3-119499.6" - process $proc$libresoc.v:119479$4712 + attribute \src "libresoc.v:129122.3-129142.6" + process $proc$libresoc.v:129122$5029 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119480.5-119480.29" + attribute \src "libresoc.v:129123.5-129123.29" switch \initial - attribute \src "libresoc.v:119480.9-119480.17" + attribute \src "libresoc.v:129123.9-129123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187463,7 +203157,7 @@ module \dec_oe$190 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187477,26 +203171,26 @@ module \dec_oe$190 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:119504.1-119638.10" +attribute \src "libresoc.v:129147.1-129282.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" -module \dec_oe$198 - attribute \src "libresoc.v:119505.7-119505.20" +module \dec_oe$168 + attribute \src "libresoc.v:129148.7-129148.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119596.3-119616.6" + attribute \src "libresoc.v:129240.3-129260.6" wire $0\oe[0:0] - attribute \src "libresoc.v:119617.3-119637.6" + attribute \src "libresoc.v:129261.3-129281.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119596.3-119616.6" + attribute \src "libresoc.v:129240.3-129260.6" wire $1\oe[0:0] - attribute \src "libresoc.v:119617.3-119637.6" + attribute \src "libresoc.v:129261.3-129281.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119596.3-119616.6" + attribute \src "libresoc.v:129240.3-129260.6" wire $2\oe[0:0] - attribute \src "libresoc.v:119617.3-119637.6" + attribute \src "libresoc.v:129261.3-129281.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \LDST_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -187572,9 +203266,10 @@ module \dec_oe$198 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:119505.7-119505.15" + attribute \src "libresoc.v:129148.7-129148.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -187584,28 +203279,28 @@ module \dec_oe$198 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119505.7-119505.20" - process $proc$libresoc.v:119505$4716 + attribute \src "libresoc.v:129148.7-129148.20" + process $proc$libresoc.v:129148$5033 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119596.3-119616.6" - process $proc$libresoc.v:119596$4714 + attribute \src "libresoc.v:129240.3-129260.6" + process $proc$libresoc.v:129240$5031 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119597.5-119597.29" + attribute \src "libresoc.v:129241.5-129241.29" switch \initial - attribute \src "libresoc.v:119597.9-119597.17" + attribute \src "libresoc.v:129241.9-129241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187614,7 +203309,7 @@ module \dec_oe$198 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187627,18 +203322,18 @@ module \dec_oe$198 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:119617.3-119637.6" - process $proc$libresoc.v:119617$4715 + attribute \src "libresoc.v:129261.3-129281.6" + process $proc$libresoc.v:129261$5032 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119618.5-119618.29" + attribute \src "libresoc.v:129262.5-129262.29" switch \initial - attribute \src "libresoc.v:119618.9-119618.17" + attribute \src "libresoc.v:129262.9-129262.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187647,7 +203342,7 @@ module \dec_oe$198 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187661,28 +203356,28 @@ module \dec_oe$198 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:119642.1-119776.10" +attribute \src "libresoc.v:129286.1-129421.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" -module \dec_oe$207 - attribute \src "libresoc.v:119643.7-119643.20" +module \dec_oe$173 + attribute \src "libresoc.v:129287.7-129287.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119734.3-119754.6" + attribute \src "libresoc.v:129379.3-129399.6" wire $0\oe[0:0] - attribute \src "libresoc.v:119755.3-119775.6" + attribute \src "libresoc.v:129400.3-129420.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119734.3-119754.6" + attribute \src "libresoc.v:129379.3-129399.6" wire $1\oe[0:0] - attribute \src "libresoc.v:119755.3-119775.6" + attribute \src "libresoc.v:129400.3-129420.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119734.3-119754.6" + attribute \src "libresoc.v:129379.3-129399.6" wire $2\oe[0:0] - attribute \src "libresoc.v:119755.3-119775.6" + attribute \src "libresoc.v:129400.3-129420.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \OE - attribute \src "libresoc.v:119643.7-119643.15" + attribute \src "libresoc.v:129287.7-129287.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -187758,7 +203453,8 @@ module \dec_oe$207 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -187768,28 +203464,28 @@ module \dec_oe$207 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119643.7-119643.20" - process $proc$libresoc.v:119643$4719 + attribute \src "libresoc.v:129287.7-129287.20" + process $proc$libresoc.v:129287$5036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119734.3-119754.6" - process $proc$libresoc.v:119734$4717 + attribute \src "libresoc.v:129379.3-129399.6" + process $proc$libresoc.v:129379$5034 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119735.5-119735.29" + attribute \src "libresoc.v:129380.5-129380.29" switch \initial - attribute \src "libresoc.v:119735.9-119735.17" + attribute \src "libresoc.v:129380.9-129380.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187798,7 +203494,7 @@ module \dec_oe$207 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187811,18 +203507,18 @@ module \dec_oe$207 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:119755.3-119775.6" - process $proc$libresoc.v:119755$4718 + attribute \src "libresoc.v:129400.3-129420.6" + process $proc$libresoc.v:129400$5035 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119756.5-119756.29" + attribute \src "libresoc.v:129401.5-129401.29" switch \initial - attribute \src "libresoc.v:119756.9-119756.17" + attribute \src "libresoc.v:129401.9-129401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -187831,7 +203527,7 @@ module \dec_oe$207 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187845,24 +203541,24 @@ module \dec_oe$207 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:119780.1-119834.10" +attribute \src "libresoc.v:129425.1-129479.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc - attribute \src "libresoc.v:119781.7-119781.20" + attribute \src "libresoc.v:129426.7-129426.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119796.3-119814.6" + attribute \src "libresoc.v:129441.3-129459.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119815.3-119833.6" + attribute \src "libresoc.v:129460.3-129478.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119796.3-119814.6" + attribute \src "libresoc.v:129441.3-129459.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119815.3-119833.6" + attribute \src "libresoc.v:129460.3-129478.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \ALU_Rc - attribute \src "libresoc.v:119781.7-119781.15" + attribute \src "libresoc.v:129426.7-129426.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -187872,28 +203568,28 @@ module \dec_rc attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119781.7-119781.20" - process $proc$libresoc.v:119781$4722 + attribute \src "libresoc.v:129426.7-129426.20" + process $proc$libresoc.v:129426$5039 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119796.3-119814.6" - process $proc$libresoc.v:119796$4720 + attribute \src "libresoc.v:129441.3-129459.6" + process $proc$libresoc.v:129441$5037 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119797.5-119797.29" + attribute \src "libresoc.v:129442.5-129442.29" switch \initial - attribute \src "libresoc.v:119797.9-119797.17" + attribute \src "libresoc.v:129442.9-129442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187913,18 +203609,18 @@ module \dec_rc sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119815.3-119833.6" - process $proc$libresoc.v:119815$4721 + attribute \src "libresoc.v:129460.3-129478.6" + process $proc$libresoc.v:129460$5038 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119816.5-119816.29" + attribute \src "libresoc.v:129461.5-129461.29" switch \initial - attribute \src "libresoc.v:119816.9-119816.17" + attribute \src "libresoc.v:129461.9-129461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187945,55 +203641,55 @@ module \dec_rc update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119838.1-119891.10" +attribute \src "libresoc.v:129483.1-129535.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" -module \dec_rc$141 - attribute \src "libresoc.v:119839.7-119839.20" +module \dec_rc$139 + attribute \src "libresoc.v:129484.7-129484.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119853.3-119871.6" + attribute \src "libresoc.v:129497.3-129515.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119872.3-119890.6" + attribute \src "libresoc.v:129516.3-129534.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119853.3-119871.6" + attribute \src "libresoc.v:129497.3-129515.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119872.3-119890.6" + attribute \src "libresoc.v:129516.3-129534.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \CR_Rc - attribute \src "libresoc.v:119839.7-119839.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 1 \CR_Rc + attribute \src "libresoc.v:129484.7-129484.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc + wire \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:119839.7-119839.20" - process $proc$libresoc.v:119839$4725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:129484.7-129484.20" + process $proc$libresoc.v:129484$5042 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119853.3-119871.6" - process $proc$libresoc.v:119853$4723 + attribute \src "libresoc.v:129497.3-129515.6" + process $proc$libresoc.v:129497$5040 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119854.5-119854.29" + attribute \src "libresoc.v:129498.5-129498.29" switch \initial - attribute \src "libresoc.v:119854.9-119854.17" + attribute \src "libresoc.v:129498.9-129498.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188013,18 +203709,18 @@ module \dec_rc$141 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119872.3-119890.6" - process $proc$libresoc.v:119872$4724 + attribute \src "libresoc.v:129516.3-129534.6" + process $proc$libresoc.v:129516$5041 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119873.5-119873.29" + attribute \src "libresoc.v:129517.5-129517.29" switch \initial - attribute \src "libresoc.v:119873.9-119873.17" + attribute \src "libresoc.v:129517.9-129517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188045,55 +203741,55 @@ module \dec_rc$141 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119895.1-119948.10" +attribute \src "libresoc.v:129539.1-129591.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" -module \dec_rc$148 - attribute \src "libresoc.v:119896.7-119896.20" +module \dec_rc$142 + attribute \src "libresoc.v:129540.7-129540.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119910.3-119928.6" + attribute \src "libresoc.v:129553.3-129571.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119929.3-119947.6" + attribute \src "libresoc.v:129572.3-129590.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119910.3-119928.6" + attribute \src "libresoc.v:129553.3-129571.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119929.3-119947.6" + attribute \src "libresoc.v:129572.3-129590.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \BRANCH_Rc - attribute \src "libresoc.v:119896.7-119896.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 1 \BRANCH_Rc + attribute \src "libresoc.v:129540.7-129540.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc + wire \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:119896.7-119896.20" - process $proc$libresoc.v:119896$4728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:129540.7-129540.20" + process $proc$libresoc.v:129540$5045 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119910.3-119928.6" - process $proc$libresoc.v:119910$4726 + attribute \src "libresoc.v:129553.3-129571.6" + process $proc$libresoc.v:129553$5043 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119911.5-119911.29" + attribute \src "libresoc.v:129554.5-129554.29" switch \initial - attribute \src "libresoc.v:119911.9-119911.17" + attribute \src "libresoc.v:129554.9-129554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188113,18 +203809,18 @@ module \dec_rc$148 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119929.3-119947.6" - process $proc$libresoc.v:119929$4727 + attribute \src "libresoc.v:129572.3-129590.6" + process $proc$libresoc.v:129572$5044 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119930.5-119930.29" + attribute \src "libresoc.v:129573.5-129573.29" switch \initial - attribute \src "libresoc.v:119930.9-119930.17" + attribute \src "libresoc.v:129573.9-129573.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188145,24 +203841,24 @@ module \dec_rc$148 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119952.1-120006.10" +attribute \src "libresoc.v:129595.1-129649.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" -module \dec_rc$156 - attribute \src "libresoc.v:119953.7-119953.20" +module \dec_rc$146 + attribute \src "libresoc.v:129596.7-129596.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119968.3-119986.6" + attribute \src "libresoc.v:129611.3-129629.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119987.3-120005.6" + attribute \src "libresoc.v:129630.3-129648.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119968.3-119986.6" + attribute \src "libresoc.v:129611.3-129629.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119987.3-120005.6" + attribute \src "libresoc.v:129630.3-129648.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:119953.7-119953.15" + attribute \src "libresoc.v:129596.7-129596.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -188172,28 +203868,28 @@ module \dec_rc$156 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119953.7-119953.20" - process $proc$libresoc.v:119953$4731 + attribute \src "libresoc.v:129596.7-129596.20" + process $proc$libresoc.v:129596$5048 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119968.3-119986.6" - process $proc$libresoc.v:119968$4729 + attribute \src "libresoc.v:129611.3-129629.6" + process $proc$libresoc.v:129611$5046 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119969.5-119969.29" + attribute \src "libresoc.v:129612.5-129612.29" switch \initial - attribute \src "libresoc.v:119969.9-119969.17" + attribute \src "libresoc.v:129612.9-129612.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188213,18 +203909,18 @@ module \dec_rc$156 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119987.3-120005.6" - process $proc$libresoc.v:119987$4730 + attribute \src "libresoc.v:129630.3-129648.6" + process $proc$libresoc.v:129630$5047 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119988.5-119988.29" + attribute \src "libresoc.v:129631.5-129631.29" switch \initial - attribute \src "libresoc.v:119988.9-119988.17" + attribute \src "libresoc.v:129631.9-129631.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188245,55 +203941,55 @@ module \dec_rc$156 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:120010.1-120063.10" +attribute \src "libresoc.v:129653.1-129705.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" -module \dec_rc$165 - attribute \src "libresoc.v:120011.7-120011.20" +module \dec_rc$151 + attribute \src "libresoc.v:129654.7-129654.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120025.3-120043.6" + attribute \src "libresoc.v:129667.3-129685.6" wire $0\rc[0:0] - attribute \src "libresoc.v:120044.3-120062.6" + attribute \src "libresoc.v:129686.3-129704.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120025.3-120043.6" + attribute \src "libresoc.v:129667.3-129685.6" wire $1\rc[0:0] - attribute \src "libresoc.v:120044.3-120062.6" + attribute \src "libresoc.v:129686.3-129704.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \SPR_Rc - attribute \src "libresoc.v:120011.7-120011.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 1 \SPR_Rc + attribute \src "libresoc.v:129654.7-129654.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc + wire \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:120011.7-120011.20" - process $proc$libresoc.v:120011$4734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:129654.7-129654.20" + process $proc$libresoc.v:129654$5051 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120025.3-120043.6" - process $proc$libresoc.v:120025$4732 + attribute \src "libresoc.v:129667.3-129685.6" + process $proc$libresoc.v:129667$5049 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120026.5-120026.29" + attribute \src "libresoc.v:129668.5-129668.29" switch \initial - attribute \src "libresoc.v:120026.9-120026.17" + attribute \src "libresoc.v:129668.9-129668.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188313,18 +204009,18 @@ module \dec_rc$165 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:120044.3-120062.6" - process $proc$libresoc.v:120044$4733 + attribute \src "libresoc.v:129686.3-129704.6" + process $proc$libresoc.v:129686$5050 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120045.5-120045.29" + attribute \src "libresoc.v:129687.5-129687.29" switch \initial - attribute \src "libresoc.v:120045.9-120045.17" + attribute \src "libresoc.v:129687.9-129687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188345,24 +204041,24 @@ module \dec_rc$165 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:120067.1-120121.10" +attribute \src "libresoc.v:129709.1-129763.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" -module \dec_rc$172 - attribute \src "libresoc.v:120068.7-120068.20" +module \dec_rc$154 + attribute \src "libresoc.v:129710.7-129710.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120083.3-120101.6" + attribute \src "libresoc.v:129725.3-129743.6" wire $0\rc[0:0] - attribute \src "libresoc.v:120102.3-120120.6" + attribute \src "libresoc.v:129744.3-129762.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120083.3-120101.6" + attribute \src "libresoc.v:129725.3-129743.6" wire $1\rc[0:0] - attribute \src "libresoc.v:120102.3-120120.6" + attribute \src "libresoc.v:129744.3-129762.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \DIV_Rc - attribute \src "libresoc.v:120068.7-120068.15" + attribute \src "libresoc.v:129710.7-129710.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -188372,28 +204068,28 @@ module \dec_rc$172 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120068.7-120068.20" - process $proc$libresoc.v:120068$4737 + attribute \src "libresoc.v:129710.7-129710.20" + process $proc$libresoc.v:129710$5054 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120083.3-120101.6" - process $proc$libresoc.v:120083$4735 + attribute \src "libresoc.v:129725.3-129743.6" + process $proc$libresoc.v:129725$5052 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120084.5-120084.29" + attribute \src "libresoc.v:129726.5-129726.29" switch \initial - attribute \src "libresoc.v:120084.9-120084.17" + attribute \src "libresoc.v:129726.9-129726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188413,18 +204109,18 @@ module \dec_rc$172 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:120102.3-120120.6" - process $proc$libresoc.v:120102$4736 + attribute \src "libresoc.v:129744.3-129762.6" + process $proc$libresoc.v:129744$5053 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120103.5-120103.29" + attribute \src "libresoc.v:129745.5-129745.29" switch \initial - attribute \src "libresoc.v:120103.9-120103.17" + attribute \src "libresoc.v:129745.9-129745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188445,24 +204141,24 @@ module \dec_rc$172 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:120125.1-120179.10" +attribute \src "libresoc.v:129767.1-129821.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" -module \dec_rc$181 - attribute \src "libresoc.v:120126.7-120126.20" +module \dec_rc$159 + attribute \src "libresoc.v:129768.7-129768.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120141.3-120159.6" + attribute \src "libresoc.v:129783.3-129801.6" wire $0\rc[0:0] - attribute \src "libresoc.v:120160.3-120178.6" + attribute \src "libresoc.v:129802.3-129820.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120141.3-120159.6" + attribute \src "libresoc.v:129783.3-129801.6" wire $1\rc[0:0] - attribute \src "libresoc.v:120160.3-120178.6" + attribute \src "libresoc.v:129802.3-129820.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \MUL_Rc - attribute \src "libresoc.v:120126.7-120126.15" + attribute \src "libresoc.v:129768.7-129768.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -188472,28 +204168,28 @@ module \dec_rc$181 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120126.7-120126.20" - process $proc$libresoc.v:120126$4740 + attribute \src "libresoc.v:129768.7-129768.20" + process $proc$libresoc.v:129768$5057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120141.3-120159.6" - process $proc$libresoc.v:120141$4738 + attribute \src "libresoc.v:129783.3-129801.6" + process $proc$libresoc.v:129783$5055 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120142.5-120142.29" + attribute \src "libresoc.v:129784.5-129784.29" switch \initial - attribute \src "libresoc.v:120142.9-120142.17" + attribute \src "libresoc.v:129784.9-129784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188513,18 +204209,18 @@ module \dec_rc$181 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:120160.3-120178.6" - process $proc$libresoc.v:120160$4739 + attribute \src "libresoc.v:129802.3-129820.6" + process $proc$libresoc.v:129802$5056 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120161.5-120161.29" + attribute \src "libresoc.v:129803.5-129803.29" switch \initial - attribute \src "libresoc.v:120161.9-120161.17" + attribute \src "libresoc.v:129803.9-129803.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188545,24 +204241,24 @@ module \dec_rc$181 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:120183.1-120237.10" +attribute \src "libresoc.v:129825.1-129879.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" -module \dec_rc$189 - attribute \src "libresoc.v:120184.7-120184.20" +module \dec_rc$163 + attribute \src "libresoc.v:129826.7-129826.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120199.3-120217.6" + attribute \src "libresoc.v:129841.3-129859.6" wire $0\rc[0:0] - attribute \src "libresoc.v:120218.3-120236.6" + attribute \src "libresoc.v:129860.3-129878.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120199.3-120217.6" + attribute \src "libresoc.v:129841.3-129859.6" wire $1\rc[0:0] - attribute \src "libresoc.v:120218.3-120236.6" + attribute \src "libresoc.v:129860.3-129878.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:120184.7-120184.15" + attribute \src "libresoc.v:129826.7-129826.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -188572,28 +204268,28 @@ module \dec_rc$189 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120184.7-120184.20" - process $proc$libresoc.v:120184$4743 + attribute \src "libresoc.v:129826.7-129826.20" + process $proc$libresoc.v:129826$5060 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120199.3-120217.6" - process $proc$libresoc.v:120199$4741 + attribute \src "libresoc.v:129841.3-129859.6" + process $proc$libresoc.v:129841$5058 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120200.5-120200.29" + attribute \src "libresoc.v:129842.5-129842.29" switch \initial - attribute \src "libresoc.v:120200.9-120200.17" + attribute \src "libresoc.v:129842.9-129842.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188613,18 +204309,18 @@ module \dec_rc$189 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:120218.3-120236.6" - process $proc$libresoc.v:120218$4742 + attribute \src "libresoc.v:129860.3-129878.6" + process $proc$libresoc.v:129860$5059 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120219.5-120219.29" + attribute \src "libresoc.v:129861.5-129861.29" switch \initial - attribute \src "libresoc.v:120219.9-120219.17" + attribute \src "libresoc.v:129861.9-129861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188645,24 +204341,24 @@ module \dec_rc$189 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:120241.1-120295.10" +attribute \src "libresoc.v:129883.1-129937.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" -module \dec_rc$197 - attribute \src "libresoc.v:120242.7-120242.20" +module \dec_rc$167 + attribute \src "libresoc.v:129884.7-129884.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120257.3-120275.6" + attribute \src "libresoc.v:129899.3-129917.6" wire $0\rc[0:0] - attribute \src "libresoc.v:120276.3-120294.6" + attribute \src "libresoc.v:129918.3-129936.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120257.3-120275.6" + attribute \src "libresoc.v:129899.3-129917.6" wire $1\rc[0:0] - attribute \src "libresoc.v:120276.3-120294.6" + attribute \src "libresoc.v:129918.3-129936.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \LDST_Rc - attribute \src "libresoc.v:120242.7-120242.15" + attribute \src "libresoc.v:129884.7-129884.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -188672,28 +204368,28 @@ module \dec_rc$197 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120242.7-120242.20" - process $proc$libresoc.v:120242$4746 + attribute \src "libresoc.v:129884.7-129884.20" + process $proc$libresoc.v:129884$5063 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120257.3-120275.6" - process $proc$libresoc.v:120257$4744 + attribute \src "libresoc.v:129899.3-129917.6" + process $proc$libresoc.v:129899$5061 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120258.5-120258.29" + attribute \src "libresoc.v:129900.5-129900.29" switch \initial - attribute \src "libresoc.v:120258.9-120258.17" + attribute \src "libresoc.v:129900.9-129900.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188713,18 +204409,18 @@ module \dec_rc$197 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:120276.3-120294.6" - process $proc$libresoc.v:120276$4745 + attribute \src "libresoc.v:129918.3-129936.6" + process $proc$libresoc.v:129918$5062 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120277.5-120277.29" + attribute \src "libresoc.v:129919.5-129919.29" switch \initial - attribute \src "libresoc.v:120277.9-120277.17" + attribute \src "libresoc.v:129919.9-129919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188745,24 +204441,24 @@ module \dec_rc$197 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:120299.1-120353.10" +attribute \src "libresoc.v:129941.1-129995.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" -module \dec_rc$206 - attribute \src "libresoc.v:120300.7-120300.20" +module \dec_rc$172 + attribute \src "libresoc.v:129942.7-129942.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120315.3-120333.6" + attribute \src "libresoc.v:129957.3-129975.6" wire $0\rc[0:0] - attribute \src "libresoc.v:120334.3-120352.6" + attribute \src "libresoc.v:129976.3-129994.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120315.3-120333.6" + attribute \src "libresoc.v:129957.3-129975.6" wire $1\rc[0:0] - attribute \src "libresoc.v:120334.3-120352.6" + attribute \src "libresoc.v:129976.3-129994.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \Rc - attribute \src "libresoc.v:120300.7-120300.15" + attribute \src "libresoc.v:129942.7-129942.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -188772,28 +204468,28 @@ module \dec_rc$206 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120300.7-120300.20" - process $proc$libresoc.v:120300$4749 + attribute \src "libresoc.v:129942.7-129942.20" + process $proc$libresoc.v:129942$5066 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120315.3-120333.6" - process $proc$libresoc.v:120315$4747 + attribute \src "libresoc.v:129957.3-129975.6" + process $proc$libresoc.v:129957$5064 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120316.5-120316.29" + attribute \src "libresoc.v:129958.5-129958.29" switch \initial - attribute \src "libresoc.v:120316.9-120316.17" + attribute \src "libresoc.v:129958.9-129958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188813,18 +204509,18 @@ module \dec_rc$206 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:120334.3-120352.6" - process $proc$libresoc.v:120334$4748 + attribute \src "libresoc.v:129976.3-129994.6" + process $proc$libresoc.v:129976$5065 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120335.5-120335.29" + attribute \src "libresoc.v:129977.5-129977.29" switch \initial - attribute \src "libresoc.v:120335.9-120335.17" + attribute \src "libresoc.v:129977.9-129977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -188845,539 +204541,539 @@ module \dec_rc$206 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:120357.1-121595.10" +attribute \src "libresoc.v:129999.1-131243.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 - attribute \src "libresoc.v:121152.3-121153.25" + attribute \src "libresoc.v:130800.3-130801.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$4889 - attribute \src "libresoc.v:121124.3-121125.75" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5206 + attribute \src "libresoc.v:130772.3-130773.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 12 $0\alu_div0_logical_op__fn_unit$next[11:0]$4890 - attribute \src "libresoc.v:121094.3-121095.73" - wire width 12 $0\alu_div0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$4891 - attribute \src "libresoc.v:121096.3-121097.87" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 + attribute \src "libresoc.v:130742.3-130743.73" + wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:130987.3-131025.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 + attribute \src "libresoc.v:130744.3-130745.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4892 - attribute \src "libresoc.v:121098.3-121099.83" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 + attribute \src "libresoc.v:130746.3-130747.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$4893 - attribute \src "libresoc.v:121112.3-121113.81" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5210 + attribute \src "libresoc.v:130760.3-130761.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$4894 - attribute \src "libresoc.v:121126.3-121127.67" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5211 + attribute \src "libresoc.v:130774.3-130775.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$4895 - attribute \src "libresoc.v:121092.3-121093.77" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5212 + attribute \src "libresoc.v:130740.3-130741.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$4896 - attribute \src "libresoc.v:121108.3-121109.77" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$5213 + attribute \src "libresoc.v:130756.3-130757.77" wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$4897 - attribute \src "libresoc.v:121114.3-121115.79" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$5214 + attribute \src "libresoc.v:130762.3-130763.79" wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$4898 - attribute \src "libresoc.v:121120.3-121121.75" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 + attribute \src "libresoc.v:130768.3-130769.75" wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$4899 - attribute \src "libresoc.v:121122.3-121123.77" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$5216 + attribute \src "libresoc.v:130770.3-130771.77" wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$4900 - attribute \src "libresoc.v:121104.3-121105.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 + attribute \src "libresoc.v:130752.3-130753.71" wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$4901 - attribute \src "libresoc.v:121106.3-121107.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 + attribute \src "libresoc.v:130754.3-130755.71" wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$4902 - attribute \src "libresoc.v:121118.3-121119.83" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$5219 + attribute \src "libresoc.v:130766.3-130767.83" wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$4903 - attribute \src "libresoc.v:121102.3-121103.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 + attribute \src "libresoc.v:130750.3-130751.71" wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$4904 - attribute \src "libresoc.v:121100.3-121101.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 + attribute \src "libresoc.v:130748.3-130749.71" wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$4905 - attribute \src "libresoc.v:121116.3-121117.77" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 + attribute \src "libresoc.v:130764.3-130765.77" wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$4906 - attribute \src "libresoc.v:121110.3-121111.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$5223 + attribute \src "libresoc.v:130758.3-130759.71" wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:121150.3-121151.40" + attribute \src "libresoc.v:130798.3-130799.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:121505.3-121513.6" - wire $0\alu_l_r_alu$next[0:0]$4976 - attribute \src "libresoc.v:121066.3-121067.39" + attribute \src "libresoc.v:131153.3-131161.6" + wire $0\alu_l_r_alu$next[0:0]$5293 + attribute \src "libresoc.v:130714.3-130715.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:121496.3-121504.6" - wire $0\alui_l_r_alui$next[0:0]$4973 - attribute \src "libresoc.v:121068.3-121069.43" + attribute \src "libresoc.v:131144.3-131152.6" + wire $0\alui_l_r_alui$next[0:0]$5290 + attribute \src "libresoc.v:130716.3-130717.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:121378.3-121399.6" - wire width 64 $0\data_r0__o$next[63:0]$4932 - attribute \src "libresoc.v:121088.3-121089.37" + attribute \src "libresoc.v:131026.3-131047.6" + wire width 64 $0\data_r0__o$next[63:0]$5249 + attribute \src "libresoc.v:130736.3-130737.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:121378.3-121399.6" - wire $0\data_r0__o_ok$next[0:0]$4933 - attribute \src "libresoc.v:121090.3-121091.43" + attribute \src "libresoc.v:131026.3-131047.6" + wire $0\data_r0__o_ok$next[0:0]$5250 + attribute \src "libresoc.v:130738.3-130739.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:121400.3-121421.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$4940 - attribute \src "libresoc.v:121084.3-121085.43" + attribute \src "libresoc.v:131048.3-131069.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5257 + attribute \src "libresoc.v:130732.3-130733.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:121400.3-121421.6" - wire $0\data_r1__cr_a_ok$next[0:0]$4941 - attribute \src "libresoc.v:121086.3-121087.49" + attribute \src "libresoc.v:131048.3-131069.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5258 + attribute \src "libresoc.v:130734.3-130735.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:121422.3-121443.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$4948 - attribute \src "libresoc.v:121080.3-121081.47" + attribute \src "libresoc.v:131070.3-131091.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$5265 + attribute \src "libresoc.v:130728.3-130729.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:121422.3-121443.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$4949 - attribute \src "libresoc.v:121082.3-121083.53" + attribute \src "libresoc.v:131070.3-131091.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$5266 + attribute \src "libresoc.v:130730.3-130731.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:121444.3-121465.6" - wire $0\data_r3__xer_so$next[0:0]$4956 - attribute \src "libresoc.v:121076.3-121077.47" + attribute \src "libresoc.v:131092.3-131113.6" + wire $0\data_r3__xer_so$next[0:0]$5273 + attribute \src "libresoc.v:130724.3-130725.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:121444.3-121465.6" - wire $0\data_r3__xer_so_ok$next[0:0]$4957 - attribute \src "libresoc.v:121078.3-121079.53" + attribute \src "libresoc.v:131092.3-131113.6" + wire $0\data_r3__xer_so_ok$next[0:0]$5274 + attribute \src "libresoc.v:130726.3-130727.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:121514.3-121523.6" + attribute \src "libresoc.v:131162.3-131171.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:121524.3-121533.6" + attribute \src "libresoc.v:131172.3-131181.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:121534.3-121543.6" + attribute \src "libresoc.v:131182.3-131191.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:121544.3-121553.6" + attribute \src "libresoc.v:131192.3-131201.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:120358.7-120358.20" + attribute \src "libresoc.v:130000.7-130000.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121294.3-121302.6" - wire $0\opc_l_r_opc$next[0:0]$4874 - attribute \src "libresoc.v:121136.3-121137.39" + attribute \src "libresoc.v:130942.3-130950.6" + wire $0\opc_l_r_opc$next[0:0]$5191 + attribute \src "libresoc.v:130784.3-130785.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:121285.3-121293.6" - wire $0\opc_l_s_opc$next[0:0]$4871 - attribute \src "libresoc.v:121138.3-121139.39" + attribute \src "libresoc.v:130933.3-130941.6" + wire $0\opc_l_s_opc$next[0:0]$5188 + attribute \src "libresoc.v:130786.3-130787.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:121554.3-121562.6" - wire width 4 $0\prev_wr_go$next[3:0]$4983 - attribute \src "libresoc.v:121148.3-121149.37" + attribute \src "libresoc.v:131202.3-131210.6" + wire width 4 $0\prev_wr_go$next[3:0]$5300 + attribute \src "libresoc.v:130796.3-130797.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:121239.3-121248.6" + attribute \src "libresoc.v:130887.3-130896.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:121330.3-121338.6" - wire width 4 $0\req_l_r_req$next[3:0]$4886 - attribute \src "libresoc.v:121128.3-121129.39" + attribute \src "libresoc.v:130978.3-130986.6" + wire width 4 $0\req_l_r_req$next[3:0]$5203 + attribute \src "libresoc.v:130776.3-130777.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:121321.3-121329.6" - wire width 4 $0\req_l_s_req$next[3:0]$4883 - attribute \src "libresoc.v:121130.3-121131.39" + attribute \src "libresoc.v:130969.3-130977.6" + wire width 4 $0\req_l_s_req$next[3:0]$5200 + attribute \src "libresoc.v:130778.3-130779.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:121258.3-121266.6" - wire $0\rok_l_r_rdok$next[0:0]$4862 - attribute \src "libresoc.v:121144.3-121145.41" + attribute \src "libresoc.v:130906.3-130914.6" + wire $0\rok_l_r_rdok$next[0:0]$5179 + attribute \src "libresoc.v:130792.3-130793.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:121249.3-121257.6" - wire $0\rok_l_s_rdok$next[0:0]$4859 - attribute \src "libresoc.v:121146.3-121147.41" + attribute \src "libresoc.v:130897.3-130905.6" + wire $0\rok_l_s_rdok$next[0:0]$5176 + attribute \src "libresoc.v:130794.3-130795.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:121276.3-121284.6" - wire $0\rst_l_r_rst$next[0:0]$4868 - attribute \src "libresoc.v:121140.3-121141.39" + attribute \src "libresoc.v:130924.3-130932.6" + wire $0\rst_l_r_rst$next[0:0]$5185 + attribute \src "libresoc.v:130788.3-130789.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:121267.3-121275.6" - wire $0\rst_l_s_rst$next[0:0]$4865 - attribute \src "libresoc.v:121142.3-121143.39" + attribute \src "libresoc.v:130915.3-130923.6" + wire $0\rst_l_s_rst$next[0:0]$5182 + attribute \src "libresoc.v:130790.3-130791.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:121312.3-121320.6" - wire width 3 $0\src_l_r_src$next[2:0]$4880 - attribute \src "libresoc.v:121132.3-121133.39" + attribute \src "libresoc.v:130960.3-130968.6" + wire width 3 $0\src_l_r_src$next[2:0]$5197 + attribute \src "libresoc.v:130780.3-130781.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:121303.3-121311.6" - wire width 3 $0\src_l_s_src$next[2:0]$4877 - attribute \src "libresoc.v:121134.3-121135.39" + attribute \src "libresoc.v:130951.3-130959.6" + wire width 3 $0\src_l_s_src$next[2:0]$5194 + attribute \src "libresoc.v:130782.3-130783.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:121466.3-121475.6" - wire width 64 $0\src_r0$next[63:0]$4964 - attribute \src "libresoc.v:121074.3-121075.29" + attribute \src "libresoc.v:131114.3-131123.6" + wire width 64 $0\src_r0$next[63:0]$5281 + attribute \src "libresoc.v:130722.3-130723.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:121476.3-121485.6" - wire width 64 $0\src_r1$next[63:0]$4967 - attribute \src "libresoc.v:121072.3-121073.29" + attribute \src "libresoc.v:131124.3-131133.6" + wire width 64 $0\src_r1$next[63:0]$5284 + attribute \src "libresoc.v:130720.3-130721.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:121486.3-121495.6" - wire $0\src_r2$next[0:0]$4970 - attribute \src "libresoc.v:121070.3-121071.29" + attribute \src "libresoc.v:131134.3-131143.6" + wire $0\src_r2$next[0:0]$5287 + attribute \src "libresoc.v:130718.3-130719.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:120488.7-120488.24" + attribute \src "libresoc.v:130130.7-130130.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$4907 - attribute \src "libresoc.v:120498.13-120498.49" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5224 + attribute \src "libresoc.v:130140.13-130140.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 12 $1\alu_div0_logical_op__fn_unit$next[11:0]$4908 - attribute \src "libresoc.v:120515.14-120515.52" - wire width 12 $1\alu_div0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4909 - attribute \src "libresoc.v:120519.14-120519.72" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 + attribute \src "libresoc.v:130159.14-130159.53" + wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:130987.3-131025.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 + attribute \src "libresoc.v:130163.14-130163.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4910 - attribute \src "libresoc.v:120523.7-120523.47" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 + attribute \src "libresoc.v:130167.7-130167.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$4911 - attribute \src "libresoc.v:120531.13-120531.52" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 + attribute \src "libresoc.v:130175.13-130175.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$4912 - attribute \src "libresoc.v:120535.14-120535.47" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5229 + attribute \src "libresoc.v:130179.14-130179.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$4913 - attribute \src "libresoc.v:120613.13-120613.51" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 + attribute \src "libresoc.v:130258.13-130258.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$4914 - attribute \src "libresoc.v:120617.7-120617.44" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$5231 + attribute \src "libresoc.v:130262.7-130262.44" wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$4915 - attribute \src "libresoc.v:120621.7-120621.45" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$5232 + attribute \src "libresoc.v:130266.7-130266.45" wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$4916 - attribute \src "libresoc.v:120625.7-120625.43" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 + attribute \src "libresoc.v:130270.7-130270.43" wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$4917 - attribute \src "libresoc.v:120629.7-120629.44" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$5234 + attribute \src "libresoc.v:130274.7-130274.44" wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$4918 - attribute \src "libresoc.v:120633.7-120633.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 + attribute \src "libresoc.v:130278.7-130278.41" wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$4919 - attribute \src "libresoc.v:120637.7-120637.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 + attribute \src "libresoc.v:130282.7-130282.41" wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$4920 - attribute \src "libresoc.v:120641.7-120641.47" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$5237 + attribute \src "libresoc.v:130286.7-130286.47" wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$4921 - attribute \src "libresoc.v:120645.7-120645.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 + attribute \src "libresoc.v:130290.7-130290.41" wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$4922 - attribute \src "libresoc.v:120649.7-120649.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 + attribute \src "libresoc.v:130294.7-130294.41" wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$4923 - attribute \src "libresoc.v:120653.7-120653.44" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 + attribute \src "libresoc.v:130298.7-130298.44" wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$4924 - attribute \src "libresoc.v:120657.7-120657.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$5241 + attribute \src "libresoc.v:130302.7-130302.41" wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:120683.7-120683.26" + attribute \src "libresoc.v:130328.7-130328.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:121505.3-121513.6" - wire $1\alu_l_r_alu$next[0:0]$4977 - attribute \src "libresoc.v:120691.7-120691.25" + attribute \src "libresoc.v:131153.3-131161.6" + wire $1\alu_l_r_alu$next[0:0]$5294 + attribute \src "libresoc.v:130336.7-130336.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:121496.3-121504.6" - wire $1\alui_l_r_alui$next[0:0]$4974 - attribute \src "libresoc.v:120703.7-120703.27" + attribute \src "libresoc.v:131144.3-131152.6" + wire $1\alui_l_r_alui$next[0:0]$5291 + attribute \src "libresoc.v:130348.7-130348.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:121378.3-121399.6" - wire width 64 $1\data_r0__o$next[63:0]$4934 - attribute \src "libresoc.v:120737.14-120737.47" + attribute \src "libresoc.v:131026.3-131047.6" + wire width 64 $1\data_r0__o$next[63:0]$5251 + attribute \src "libresoc.v:130382.14-130382.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:121378.3-121399.6" - wire $1\data_r0__o_ok$next[0:0]$4935 - attribute \src "libresoc.v:120741.7-120741.27" + attribute \src "libresoc.v:131026.3-131047.6" + wire $1\data_r0__o_ok$next[0:0]$5252 + attribute \src "libresoc.v:130386.7-130386.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:121400.3-121421.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$4942 - attribute \src "libresoc.v:120745.13-120745.33" + attribute \src "libresoc.v:131048.3-131069.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5259 + attribute \src "libresoc.v:130390.13-130390.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:121400.3-121421.6" - wire $1\data_r1__cr_a_ok$next[0:0]$4943 - attribute \src "libresoc.v:120749.7-120749.30" + attribute \src "libresoc.v:131048.3-131069.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5260 + attribute \src "libresoc.v:130394.7-130394.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:121422.3-121443.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$4950 - attribute \src "libresoc.v:120753.13-120753.35" + attribute \src "libresoc.v:131070.3-131091.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$5267 + attribute \src "libresoc.v:130398.13-130398.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:121422.3-121443.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$4951 - attribute \src "libresoc.v:120757.7-120757.32" + attribute \src "libresoc.v:131070.3-131091.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$5268 + attribute \src "libresoc.v:130402.7-130402.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:121444.3-121465.6" - wire $1\data_r3__xer_so$next[0:0]$4958 - attribute \src "libresoc.v:120761.7-120761.29" + attribute \src "libresoc.v:131092.3-131113.6" + wire $1\data_r3__xer_so$next[0:0]$5275 + attribute \src "libresoc.v:130406.7-130406.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:121444.3-121465.6" - wire $1\data_r3__xer_so_ok$next[0:0]$4959 - attribute \src "libresoc.v:120765.7-120765.32" + attribute \src "libresoc.v:131092.3-131113.6" + wire $1\data_r3__xer_so_ok$next[0:0]$5276 + attribute \src "libresoc.v:130410.7-130410.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:121514.3-121523.6" + attribute \src "libresoc.v:131162.3-131171.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:121524.3-121533.6" + attribute \src "libresoc.v:131172.3-131181.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:121534.3-121543.6" + attribute \src "libresoc.v:131182.3-131191.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:121544.3-121553.6" + attribute \src "libresoc.v:131192.3-131201.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:121294.3-121302.6" - wire $1\opc_l_r_opc$next[0:0]$4875 - attribute \src "libresoc.v:120785.7-120785.25" + attribute \src "libresoc.v:130942.3-130950.6" + wire $1\opc_l_r_opc$next[0:0]$5192 + attribute \src "libresoc.v:130430.7-130430.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:121285.3-121293.6" - wire $1\opc_l_s_opc$next[0:0]$4872 - attribute \src "libresoc.v:120789.7-120789.25" + attribute \src "libresoc.v:130933.3-130941.6" + wire $1\opc_l_s_opc$next[0:0]$5189 + attribute \src "libresoc.v:130434.7-130434.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:121554.3-121562.6" - wire width 4 $1\prev_wr_go$next[3:0]$4984 - attribute \src "libresoc.v:120920.13-120920.30" + attribute \src "libresoc.v:131202.3-131210.6" + wire width 4 $1\prev_wr_go$next[3:0]$5301 + attribute \src "libresoc.v:130568.13-130568.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:121239.3-121248.6" + attribute \src "libresoc.v:130887.3-130896.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:121330.3-121338.6" - wire width 4 $1\req_l_r_req$next[3:0]$4887 - attribute \src "libresoc.v:120928.13-120928.31" + attribute \src "libresoc.v:130978.3-130986.6" + wire width 4 $1\req_l_r_req$next[3:0]$5204 + attribute \src "libresoc.v:130576.13-130576.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:121321.3-121329.6" - wire width 4 $1\req_l_s_req$next[3:0]$4884 - attribute \src "libresoc.v:120932.13-120932.31" + attribute \src "libresoc.v:130969.3-130977.6" + wire width 4 $1\req_l_s_req$next[3:0]$5201 + attribute \src "libresoc.v:130580.13-130580.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:121258.3-121266.6" - wire $1\rok_l_r_rdok$next[0:0]$4863 - attribute \src "libresoc.v:120944.7-120944.26" + attribute \src "libresoc.v:130906.3-130914.6" + wire $1\rok_l_r_rdok$next[0:0]$5180 + attribute \src "libresoc.v:130592.7-130592.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:121249.3-121257.6" - wire $1\rok_l_s_rdok$next[0:0]$4860 - attribute \src "libresoc.v:120948.7-120948.26" + attribute \src "libresoc.v:130897.3-130905.6" + wire $1\rok_l_s_rdok$next[0:0]$5177 + attribute \src "libresoc.v:130596.7-130596.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:121276.3-121284.6" - wire $1\rst_l_r_rst$next[0:0]$4869 - attribute \src "libresoc.v:120952.7-120952.25" + attribute \src "libresoc.v:130924.3-130932.6" + wire $1\rst_l_r_rst$next[0:0]$5186 + attribute \src "libresoc.v:130600.7-130600.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:121267.3-121275.6" - wire $1\rst_l_s_rst$next[0:0]$4866 - attribute \src "libresoc.v:120956.7-120956.25" + attribute \src "libresoc.v:130915.3-130923.6" + wire $1\rst_l_s_rst$next[0:0]$5183 + attribute \src "libresoc.v:130604.7-130604.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:121312.3-121320.6" - wire width 3 $1\src_l_r_src$next[2:0]$4881 - attribute \src "libresoc.v:120970.13-120970.31" + attribute \src "libresoc.v:130960.3-130968.6" + wire width 3 $1\src_l_r_src$next[2:0]$5198 + attribute \src "libresoc.v:130618.13-130618.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:121303.3-121311.6" - wire width 3 $1\src_l_s_src$next[2:0]$4878 - attribute \src "libresoc.v:120974.13-120974.31" + attribute \src "libresoc.v:130951.3-130959.6" + wire width 3 $1\src_l_s_src$next[2:0]$5195 + attribute \src "libresoc.v:130622.13-130622.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:121466.3-121475.6" - wire width 64 $1\src_r0$next[63:0]$4965 - attribute \src "libresoc.v:120982.14-120982.43" + attribute \src "libresoc.v:131114.3-131123.6" + wire width 64 $1\src_r0$next[63:0]$5282 + attribute \src "libresoc.v:130630.14-130630.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:121476.3-121485.6" - wire width 64 $1\src_r1$next[63:0]$4968 - attribute \src "libresoc.v:120986.14-120986.43" + attribute \src "libresoc.v:131124.3-131133.6" + wire width 64 $1\src_r1$next[63:0]$5285 + attribute \src "libresoc.v:130634.14-130634.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:121486.3-121495.6" - wire $1\src_r2$next[0:0]$4971 - attribute \src "libresoc.v:120990.7-120990.20" + attribute \src "libresoc.v:131134.3-131143.6" + wire $1\src_r2$next[0:0]$5288 + attribute \src "libresoc.v:130638.7-130638.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:121339.3-121377.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4925 - attribute \src "libresoc.v:121339.3-121377.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4926 - attribute \src "libresoc.v:121339.3-121377.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$4927 - attribute \src "libresoc.v:121339.3-121377.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$4928 - attribute \src "libresoc.v:121339.3-121377.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$4929 - attribute \src "libresoc.v:121339.3-121377.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$4930 - attribute \src "libresoc.v:121378.3-121399.6" - wire width 64 $2\data_r0__o$next[63:0]$4936 - attribute \src "libresoc.v:121378.3-121399.6" - wire $2\data_r0__o_ok$next[0:0]$4937 - attribute \src "libresoc.v:121400.3-121421.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$4944 - attribute \src "libresoc.v:121400.3-121421.6" - wire $2\data_r1__cr_a_ok$next[0:0]$4945 - attribute \src "libresoc.v:121422.3-121443.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$4952 - attribute \src "libresoc.v:121422.3-121443.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$4953 - attribute \src "libresoc.v:121444.3-121465.6" - wire $2\data_r3__xer_so$next[0:0]$4960 - attribute \src "libresoc.v:121444.3-121465.6" - wire $2\data_r3__xer_so_ok$next[0:0]$4961 - attribute \src "libresoc.v:121378.3-121399.6" - wire $3\data_r0__o_ok$next[0:0]$4938 - attribute \src "libresoc.v:121400.3-121421.6" - wire $3\data_r1__cr_a_ok$next[0:0]$4946 - attribute \src "libresoc.v:121422.3-121443.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$4954 - attribute \src "libresoc.v:121444.3-121465.6" - wire $3\data_r3__xer_so_ok$next[0:0]$4962 - attribute \src "libresoc.v:121005.19-121005.133" - wire width 3 $and$libresoc.v:121005$4752_Y - attribute \src "libresoc.v:121007.19-121007.115" - wire width 3 $and$libresoc.v:121007$4754_Y - attribute \src "libresoc.v:121008.18-121008.110" - wire $and$libresoc.v:121008$4755_Y - attribute \src "libresoc.v:121009.19-121009.125" - wire $and$libresoc.v:121009$4756_Y - attribute \src "libresoc.v:121010.19-121010.125" - wire $and$libresoc.v:121010$4757_Y - attribute \src "libresoc.v:121011.19-121011.125" - wire $and$libresoc.v:121011$4758_Y - attribute \src "libresoc.v:121012.19-121012.125" - wire $and$libresoc.v:121012$4759_Y - attribute \src "libresoc.v:121013.19-121013.149" - wire width 4 $and$libresoc.v:121013$4760_Y - attribute \src "libresoc.v:121014.19-121014.121" - wire width 4 $and$libresoc.v:121014$4761_Y - attribute \src "libresoc.v:121015.19-121015.127" - wire $and$libresoc.v:121015$4762_Y - attribute \src "libresoc.v:121016.19-121016.127" - wire $and$libresoc.v:121016$4763_Y - attribute \src "libresoc.v:121017.19-121017.127" - wire $and$libresoc.v:121017$4764_Y - attribute \src "libresoc.v:121018.19-121018.127" - wire $and$libresoc.v:121018$4765_Y - attribute \src "libresoc.v:121020.18-121020.98" - wire $and$libresoc.v:121020$4767_Y - attribute \src "libresoc.v:121022.18-121022.100" - wire $and$libresoc.v:121022$4769_Y - attribute \src "libresoc.v:121023.18-121023.160" - wire width 4 $and$libresoc.v:121023$4770_Y - attribute \src "libresoc.v:121025.18-121025.119" - wire width 4 $and$libresoc.v:121025$4772_Y - attribute \src "libresoc.v:121028.17-121028.123" - wire $and$libresoc.v:121028$4775_Y - attribute \src "libresoc.v:121029.18-121029.116" - wire $and$libresoc.v:121029$4776_Y - attribute \src "libresoc.v:121034.18-121034.113" - wire $and$libresoc.v:121034$4781_Y - attribute \src "libresoc.v:121035.18-121035.125" - wire width 4 $and$libresoc.v:121035$4782_Y - attribute \src "libresoc.v:121037.18-121037.112" - wire $and$libresoc.v:121037$4784_Y - attribute \src "libresoc.v:121039.18-121039.126" - wire $and$libresoc.v:121039$4786_Y - attribute \src "libresoc.v:121040.18-121040.126" - wire $and$libresoc.v:121040$4787_Y - attribute \src "libresoc.v:121041.18-121041.117" - wire $and$libresoc.v:121041$4788_Y - attribute \src "libresoc.v:121047.18-121047.130" - wire $and$libresoc.v:121047$4794_Y - attribute \src "libresoc.v:121048.18-121048.124" - wire width 4 $and$libresoc.v:121048$4795_Y - attribute \src "libresoc.v:121050.18-121050.116" - wire $and$libresoc.v:121050$4797_Y - attribute \src "libresoc.v:121051.18-121051.119" - wire $and$libresoc.v:121051$4798_Y - attribute \src "libresoc.v:121052.18-121052.121" - wire $and$libresoc.v:121052$4799_Y - attribute \src "libresoc.v:121053.18-121053.121" - wire $and$libresoc.v:121053$4800_Y - attribute \src "libresoc.v:121063.18-121063.134" - wire $and$libresoc.v:121063$4810_Y - attribute \src "libresoc.v:121064.18-121064.132" - wire $and$libresoc.v:121064$4811_Y - attribute \src "libresoc.v:121065.18-121065.149" - wire width 3 $and$libresoc.v:121065$4812_Y - attribute \src "libresoc.v:121036.18-121036.113" - wire $eq$libresoc.v:121036$4783_Y - attribute \src "libresoc.v:121038.18-121038.119" - wire $eq$libresoc.v:121038$4785_Y - attribute \src "libresoc.v:121003.19-121003.130" - wire $not$libresoc.v:121003$4750_Y - attribute \src "libresoc.v:121004.19-121004.136" - wire $not$libresoc.v:121004$4751_Y - attribute \src "libresoc.v:121006.19-121006.115" - wire width 3 $not$libresoc.v:121006$4753_Y - attribute \src "libresoc.v:121019.18-121019.97" - wire $not$libresoc.v:121019$4766_Y - attribute \src "libresoc.v:121021.18-121021.99" - wire $not$libresoc.v:121021$4768_Y - attribute \src "libresoc.v:121024.18-121024.113" - wire width 4 $not$libresoc.v:121024$4771_Y - attribute \src "libresoc.v:121027.18-121027.106" - wire $not$libresoc.v:121027$4774_Y - attribute \src "libresoc.v:121033.18-121033.120" - wire $not$libresoc.v:121033$4780_Y - attribute \src "libresoc.v:121044.17-121044.113" - wire width 3 $not$libresoc.v:121044$4791_Y - attribute \src "libresoc.v:121032.18-121032.112" - wire $or$libresoc.v:121032$4779_Y - attribute \src "libresoc.v:121042.18-121042.122" - wire $or$libresoc.v:121042$4789_Y - attribute \src "libresoc.v:121043.18-121043.124" - wire $or$libresoc.v:121043$4790_Y - attribute \src "libresoc.v:121045.18-121045.168" - wire width 4 $or$libresoc.v:121045$4792_Y - attribute \src "libresoc.v:121046.18-121046.155" - wire width 3 $or$libresoc.v:121046$4793_Y - attribute \src "libresoc.v:121049.18-121049.120" - wire width 4 $or$libresoc.v:121049$4796_Y - attribute \src "libresoc.v:121055.17-121055.117" - wire width 3 $or$libresoc.v:121055$4802_Y - attribute \src "libresoc.v:121060.17-121060.104" - wire $reduce_and$libresoc.v:121060$4807_Y - attribute \src "libresoc.v:121026.18-121026.106" - wire $reduce_or$libresoc.v:121026$4773_Y - attribute \src "libresoc.v:121030.18-121030.113" - wire $reduce_or$libresoc.v:121030$4777_Y - attribute \src "libresoc.v:121031.18-121031.112" - wire $reduce_or$libresoc.v:121031$4778_Y - attribute \src "libresoc.v:121054.18-121054.158" - wire $ternary$libresoc.v:121054$4801_Y - attribute \src "libresoc.v:121056.18-121056.159" - wire width 64 $ternary$libresoc.v:121056$4803_Y - attribute \src "libresoc.v:121057.18-121057.164" - wire $ternary$libresoc.v:121057$4804_Y - attribute \src "libresoc.v:121058.18-121058.180" - wire width 64 $ternary$libresoc.v:121058$4805_Y - attribute \src "libresoc.v:121059.18-121059.115" - wire width 64 $ternary$libresoc.v:121059$4806_Y - attribute \src "libresoc.v:121061.18-121061.125" - wire width 64 $ternary$libresoc.v:121061$4808_Y - attribute \src "libresoc.v:121062.18-121062.118" - wire $ternary$libresoc.v:121062$4809_Y + attribute \src "libresoc.v:130987.3-131025.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 + attribute \src "libresoc.v:131026.3-131047.6" + wire width 64 $2\data_r0__o$next[63:0]$5253 + attribute \src "libresoc.v:131026.3-131047.6" + wire $2\data_r0__o_ok$next[0:0]$5254 + attribute \src "libresoc.v:131048.3-131069.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$5261 + attribute \src "libresoc.v:131048.3-131069.6" + wire $2\data_r1__cr_a_ok$next[0:0]$5262 + attribute \src "libresoc.v:131070.3-131091.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$5269 + attribute \src "libresoc.v:131070.3-131091.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$5270 + attribute \src "libresoc.v:131092.3-131113.6" + wire $2\data_r3__xer_so$next[0:0]$5277 + attribute \src "libresoc.v:131092.3-131113.6" + wire $2\data_r3__xer_so_ok$next[0:0]$5278 + attribute \src "libresoc.v:131026.3-131047.6" + wire $3\data_r0__o_ok$next[0:0]$5255 + attribute \src "libresoc.v:131048.3-131069.6" + wire $3\data_r1__cr_a_ok$next[0:0]$5263 + attribute \src "libresoc.v:131070.3-131091.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$5271 + attribute \src "libresoc.v:131092.3-131113.6" + wire $3\data_r3__xer_so_ok$next[0:0]$5279 + attribute \src "libresoc.v:130653.19-130653.133" + wire width 3 $and$libresoc.v:130653$5069_Y + attribute \src "libresoc.v:130655.19-130655.115" + wire width 3 $and$libresoc.v:130655$5071_Y + attribute \src "libresoc.v:130656.18-130656.110" + wire $and$libresoc.v:130656$5072_Y + attribute \src "libresoc.v:130657.19-130657.125" + wire $and$libresoc.v:130657$5073_Y + attribute \src "libresoc.v:130658.19-130658.125" + wire $and$libresoc.v:130658$5074_Y + attribute \src "libresoc.v:130659.19-130659.125" + wire $and$libresoc.v:130659$5075_Y + attribute \src "libresoc.v:130660.19-130660.125" + wire $and$libresoc.v:130660$5076_Y + attribute \src "libresoc.v:130661.19-130661.149" + wire width 4 $and$libresoc.v:130661$5077_Y + attribute \src "libresoc.v:130662.19-130662.121" + wire width 4 $and$libresoc.v:130662$5078_Y + attribute \src "libresoc.v:130663.19-130663.127" + wire $and$libresoc.v:130663$5079_Y + attribute \src "libresoc.v:130664.19-130664.127" + wire $and$libresoc.v:130664$5080_Y + attribute \src "libresoc.v:130665.19-130665.127" + wire $and$libresoc.v:130665$5081_Y + attribute \src "libresoc.v:130666.19-130666.127" + wire $and$libresoc.v:130666$5082_Y + attribute \src "libresoc.v:130668.18-130668.98" + wire $and$libresoc.v:130668$5084_Y + attribute \src "libresoc.v:130670.18-130670.100" + wire $and$libresoc.v:130670$5086_Y + attribute \src "libresoc.v:130671.18-130671.160" + wire width 4 $and$libresoc.v:130671$5087_Y + attribute \src "libresoc.v:130673.18-130673.119" + wire width 4 $and$libresoc.v:130673$5089_Y + attribute \src "libresoc.v:130676.17-130676.123" + wire $and$libresoc.v:130676$5092_Y + attribute \src "libresoc.v:130677.18-130677.116" + wire $and$libresoc.v:130677$5093_Y + attribute \src "libresoc.v:130682.18-130682.113" + wire $and$libresoc.v:130682$5098_Y + attribute \src "libresoc.v:130683.18-130683.125" + wire width 4 $and$libresoc.v:130683$5099_Y + attribute \src "libresoc.v:130685.18-130685.112" + wire $and$libresoc.v:130685$5101_Y + attribute \src "libresoc.v:130687.18-130687.126" + wire $and$libresoc.v:130687$5103_Y + attribute \src "libresoc.v:130688.18-130688.126" + wire $and$libresoc.v:130688$5104_Y + attribute \src "libresoc.v:130689.18-130689.117" + wire $and$libresoc.v:130689$5105_Y + attribute \src "libresoc.v:130695.18-130695.130" + wire $and$libresoc.v:130695$5111_Y + attribute \src "libresoc.v:130696.18-130696.124" + wire width 4 $and$libresoc.v:130696$5112_Y + attribute \src "libresoc.v:130698.18-130698.116" + wire $and$libresoc.v:130698$5114_Y + attribute \src "libresoc.v:130699.18-130699.119" + wire $and$libresoc.v:130699$5115_Y + attribute \src "libresoc.v:130700.18-130700.121" + wire $and$libresoc.v:130700$5116_Y + attribute \src "libresoc.v:130701.18-130701.121" + wire $and$libresoc.v:130701$5117_Y + attribute \src "libresoc.v:130711.18-130711.134" + wire $and$libresoc.v:130711$5127_Y + attribute \src "libresoc.v:130712.18-130712.132" + wire $and$libresoc.v:130712$5128_Y + attribute \src "libresoc.v:130713.18-130713.149" + wire width 3 $and$libresoc.v:130713$5129_Y + attribute \src "libresoc.v:130684.18-130684.113" + wire $eq$libresoc.v:130684$5100_Y + attribute \src "libresoc.v:130686.18-130686.119" + wire $eq$libresoc.v:130686$5102_Y + attribute \src "libresoc.v:130651.19-130651.130" + wire $not$libresoc.v:130651$5067_Y + attribute \src "libresoc.v:130652.19-130652.136" + wire $not$libresoc.v:130652$5068_Y + attribute \src "libresoc.v:130654.19-130654.115" + wire width 3 $not$libresoc.v:130654$5070_Y + attribute \src "libresoc.v:130667.18-130667.97" + wire $not$libresoc.v:130667$5083_Y + attribute \src "libresoc.v:130669.18-130669.99" + wire $not$libresoc.v:130669$5085_Y + attribute \src "libresoc.v:130672.18-130672.113" + wire width 4 $not$libresoc.v:130672$5088_Y + attribute \src "libresoc.v:130675.18-130675.106" + wire $not$libresoc.v:130675$5091_Y + attribute \src "libresoc.v:130681.18-130681.120" + wire $not$libresoc.v:130681$5097_Y + attribute \src "libresoc.v:130692.17-130692.113" + wire width 3 $not$libresoc.v:130692$5108_Y + attribute \src "libresoc.v:130680.18-130680.112" + wire $or$libresoc.v:130680$5096_Y + attribute \src "libresoc.v:130690.18-130690.122" + wire $or$libresoc.v:130690$5106_Y + attribute \src "libresoc.v:130691.18-130691.124" + wire $or$libresoc.v:130691$5107_Y + attribute \src "libresoc.v:130693.18-130693.168" + wire width 4 $or$libresoc.v:130693$5109_Y + attribute \src "libresoc.v:130694.18-130694.155" + wire width 3 $or$libresoc.v:130694$5110_Y + attribute \src "libresoc.v:130697.18-130697.120" + wire width 4 $or$libresoc.v:130697$5113_Y + attribute \src "libresoc.v:130703.17-130703.117" + wire width 3 $or$libresoc.v:130703$5119_Y + attribute \src "libresoc.v:130708.17-130708.104" + wire $reduce_and$libresoc.v:130708$5124_Y + attribute \src "libresoc.v:130674.18-130674.106" + wire $reduce_or$libresoc.v:130674$5090_Y + attribute \src "libresoc.v:130678.18-130678.113" + wire $reduce_or$libresoc.v:130678$5094_Y + attribute \src "libresoc.v:130679.18-130679.112" + wire $reduce_or$libresoc.v:130679$5095_Y + attribute \src "libresoc.v:130702.18-130702.158" + wire $ternary$libresoc.v:130702$5118_Y + attribute \src "libresoc.v:130704.18-130704.159" + wire width 64 $ternary$libresoc.v:130704$5120_Y + attribute \src "libresoc.v:130705.18-130705.164" + wire $ternary$libresoc.v:130705$5121_Y + attribute \src "libresoc.v:130706.18-130706.180" + wire width 64 $ternary$libresoc.v:130706$5122_Y + attribute \src "libresoc.v:130707.18-130707.115" + wire width 64 $ternary$libresoc.v:130707$5123_Y + attribute \src "libresoc.v:130709.18-130709.125" + wire width 64 $ternary$libresoc.v:130709$5125_Y + attribute \src "libresoc.v:130710.18-130710.118" + wire $ternary$libresoc.v:130710$5126_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -189400,7 +205096,7 @@ module \div0 wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 4 \$118 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 4 \$120 @@ -189412,11 +205108,11 @@ module \div0 wire \$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$128 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$2 @@ -189492,11 +205188,11 @@ module \div0 wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$88 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$90 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$94 @@ -189506,13 +205202,13 @@ module \div0 wire width 3 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_div0_cr_a @@ -189521,22 +205217,24 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_div0_logical_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_div0_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_div0_logical_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_div0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_div0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_div0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -189631,6 +205329,7 @@ module \div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_div0_logical_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -189679,15 +205378,15 @@ module \div0 wire \alu_div0_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_div0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_div0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_div0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_div0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_div0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_div0_ra @@ -189701,35 +205400,35 @@ module \div0 wire \alu_div0_xer_so$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 4 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -189795,37 +205494,39 @@ module \div0 wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 37 \dest4_o - attribute \src "libresoc.v:120358.7-120358.15" + attribute \src "libresoc.v:130000.7-130000.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_div0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_div0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -189912,6 +205613,7 @@ module \div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -189942,15 +205644,15 @@ module \div0 wire width 4 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -189958,23 +205660,23 @@ module \div0 wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 4 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -189984,31 +205686,31 @@ module \div0 wire width 64 input 26 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel @@ -190021,7 +205723,7 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:121005$4752 + cell $and $and$libresoc.v:130653$5069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -190029,10 +205731,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } - connect \Y $and$libresoc.v:121005$4752_Y + connect \Y $and$libresoc.v:130653$5069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:121007$4754 + cell $and $and$libresoc.v:130655$5071 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -190040,10 +205742,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:121007$4754_Y + connect \Y $and$libresoc.v:130655$5071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:121008$4755 + cell $and $and$libresoc.v:130656$5072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190051,10 +205753,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:121008$4755_Y + connect \Y $and$libresoc.v:130656$5072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:121009$4756 + cell $and $and$libresoc.v:130657$5073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190062,10 +205764,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:121009$4756_Y + connect \Y $and$libresoc.v:130657$5073_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:121010$4757 + cell $and $and$libresoc.v:130658$5074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190073,10 +205775,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:121010$4757_Y + connect \Y $and$libresoc.v:130658$5074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:121011$4758 + cell $and $and$libresoc.v:130659$5075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190084,10 +205786,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:121011$4758_Y + connect \Y $and$libresoc.v:130659$5075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:121012$4759 + cell $and $and$libresoc.v:130660$5076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190095,10 +205797,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:121012$4759_Y + connect \Y $and$libresoc.v:130660$5076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:121013$4760 + cell $and $and$libresoc.v:130661$5077 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190106,10 +205808,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } - connect \Y $and$libresoc.v:121013$4760_Y + connect \Y $and$libresoc.v:130661$5077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:121014$4761 + cell $and $and$libresoc.v:130662$5078 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190117,10 +205819,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:121014$4761_Y + connect \Y $and$libresoc.v:130662$5078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:121015$4762 + cell $and $and$libresoc.v:130663$5079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190128,10 +205830,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:121015$4762_Y + connect \Y $and$libresoc.v:130663$5079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:121016$4763 + cell $and $and$libresoc.v:130664$5080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190139,10 +205841,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:121016$4763_Y + connect \Y $and$libresoc.v:130664$5080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:121017$4764 + cell $and $and$libresoc.v:130665$5081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190150,10 +205852,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:121017$4764_Y + connect \Y $and$libresoc.v:130665$5081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:121018$4765 + cell $and $and$libresoc.v:130666$5082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190161,10 +205863,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:121018$4765_Y + connect \Y $and$libresoc.v:130666$5082_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:121020$4767 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:130668$5084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190172,10 +205874,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:121020$4767_Y + connect \Y $and$libresoc.v:130668$5084_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:121022$4769 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:130670$5086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190183,10 +205885,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:121022$4769_Y + connect \Y $and$libresoc.v:130670$5086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:121023$4770 + cell $and $and$libresoc.v:130671$5087 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190194,10 +205896,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:121023$4770_Y + connect \Y $and$libresoc.v:130671$5087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:121025$4772 + cell $and $and$libresoc.v:130673$5089 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190205,10 +205907,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:121025$4772_Y + connect \Y $and$libresoc.v:130673$5089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:121028$4775 + cell $and $and$libresoc.v:130676$5092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190216,10 +205918,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:121028$4775_Y + connect \Y $and$libresoc.v:130676$5092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:121029$4776 + cell $and $and$libresoc.v:130677$5093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190227,10 +205929,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:121029$4776_Y + connect \Y $and$libresoc.v:130677$5093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:121034$4781 + cell $and $and$libresoc.v:130682$5098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190238,10 +205940,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:121034$4781_Y + connect \Y $and$libresoc.v:130682$5098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:121035$4782 + cell $and $and$libresoc.v:130683$5099 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190249,10 +205951,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:121035$4782_Y + connect \Y $and$libresoc.v:130683$5099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:121037$4784 + cell $and $and$libresoc.v:130685$5101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190260,10 +205962,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:121037$4784_Y + connect \Y $and$libresoc.v:130685$5101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:121039$4786 + cell $and $and$libresoc.v:130687$5103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190271,10 +205973,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i - connect \Y $and$libresoc.v:121039$4786_Y + connect \Y $and$libresoc.v:130687$5103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:121040$4787 + cell $and $and$libresoc.v:130688$5104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190282,10 +205984,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o - connect \Y $and$libresoc.v:121040$4787_Y + connect \Y $and$libresoc.v:130688$5104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:121041$4788 + cell $and $and$libresoc.v:130689$5105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190293,10 +205995,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:121041$4788_Y + connect \Y $and$libresoc.v:130689$5105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:121047$4794 + cell $and $and$libresoc.v:130695$5111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190304,10 +206006,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:121047$4794_Y + connect \Y $and$libresoc.v:130695$5111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:121048$4795 + cell $and $and$libresoc.v:130696$5112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190315,10 +206017,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:121048$4795_Y + connect \Y $and$libresoc.v:130696$5112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:121050$4797 + cell $and $and$libresoc.v:130698$5114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190326,10 +206028,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:121050$4797_Y + connect \Y $and$libresoc.v:130698$5114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:121051$4798 + cell $and $and$libresoc.v:130699$5115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190337,10 +206039,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:121051$4798_Y + connect \Y $and$libresoc.v:130699$5115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:121052$4799 + cell $and $and$libresoc.v:130700$5116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190348,10 +206050,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:121052$4799_Y + connect \Y $and$libresoc.v:130700$5116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:121053$4800 + cell $and $and$libresoc.v:130701$5117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190359,10 +206061,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:121053$4800_Y + connect \Y $and$libresoc.v:130701$5117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:121063$4810 + cell $and $and$libresoc.v:130711$5127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190370,10 +206072,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:121063$4810_Y + connect \Y $and$libresoc.v:130711$5127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:121064$4811 + cell $and $and$libresoc.v:130712$5128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190381,10 +206083,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:121064$4811_Y + connect \Y $and$libresoc.v:130712$5128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:121065$4812 + cell $and $and$libresoc.v:130713$5129 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -190392,10 +206094,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:121065$4812_Y + connect \Y $and$libresoc.v:130713$5129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:121036$4783 + cell $eq $eq$libresoc.v:130684$5100 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190403,10 +206105,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:121036$4783_Y + connect \Y $eq$libresoc.v:130684$5100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:121038$4785 + cell $eq $eq$libresoc.v:130686$5102 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190414,82 +206116,82 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:121038$4785_Y + connect \Y $eq$libresoc.v:130686$5102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:121003$4750 + cell $not $not$libresoc.v:130651$5067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:121003$4750_Y + connect \Y $not$libresoc.v:130651$5067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:121004$4751 + cell $not $not$libresoc.v:130652$5068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:121004$4751_Y + connect \Y $not$libresoc.v:130652$5068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:121006$4753 + cell $not $not$libresoc.v:130654$5070 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:121006$4753_Y + connect \Y $not$libresoc.v:130654$5070_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:121019$4766 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:130667$5083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:121019$4766_Y + connect \Y $not$libresoc.v:130667$5083_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:121021$4768 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:130669$5085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:121021$4768_Y + connect \Y $not$libresoc.v:130669$5085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:121024$4771 + cell $not $not$libresoc.v:130672$5088 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:121024$4771_Y + connect \Y $not$libresoc.v:130672$5088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:121027$4774 + cell $not $not$libresoc.v:130675$5091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:121027$4774_Y + connect \Y $not$libresoc.v:130675$5091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:121033$4780 + cell $not $not$libresoc.v:130681$5097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:121033$4780_Y + connect \Y $not$libresoc.v:130681$5097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:121044$4791 + cell $not $not$libresoc.v:130692$5108 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:121044$4791_Y + connect \Y $not$libresoc.v:130692$5108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:121032$4779 + cell $or $or$libresoc.v:130680$5096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190497,10 +206199,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:121032$4779_Y + connect \Y $or$libresoc.v:130680$5096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:121042$4789 + cell $or $or$libresoc.v:130690$5106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190508,10 +206210,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:121042$4789_Y + connect \Y $or$libresoc.v:130690$5106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:121043$4790 + cell $or $or$libresoc.v:130691$5107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190519,10 +206221,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:121043$4790_Y + connect \Y $or$libresoc.v:130691$5107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:121045$4792 + cell $or $or$libresoc.v:130693$5109 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190530,10 +206232,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:121045$4792_Y + connect \Y $or$libresoc.v:130693$5109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:121046$4793 + cell $or $or$libresoc.v:130694$5110 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -190541,10 +206243,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:121046$4793_Y + connect \Y $or$libresoc.v:130694$5110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:121049$4796 + cell $or $or$libresoc.v:130697$5113 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -190552,10 +206254,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:121049$4796_Y + connect \Y $or$libresoc.v:130697$5113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:121055$4802 + cell $or $or$libresoc.v:130703$5119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -190563,98 +206265,98 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:121055$4802_Y + connect \Y $or$libresoc.v:130703$5119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:121060$4807 + cell $reduce_and $reduce_and$libresoc.v:130708$5124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:121060$4807_Y + connect \Y $reduce_and$libresoc.v:130708$5124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:121026$4773 + cell $reduce_or $reduce_or$libresoc.v:130674$5090 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:121026$4773_Y + connect \Y $reduce_or$libresoc.v:130674$5090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:121030$4777 + cell $reduce_or $reduce_or$libresoc.v:130678$5094 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:121030$4777_Y + connect \Y $reduce_or$libresoc.v:130678$5094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:121031$4778 + cell $reduce_or $reduce_or$libresoc.v:130679$5095 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:121031$4778_Y + connect \Y $reduce_or$libresoc.v:130679$5095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:121054$4801 + cell $mux $ternary$libresoc.v:130702$5118 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:121054$4801_Y + connect \Y $ternary$libresoc.v:130702$5118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:121056$4803 + cell $mux $ternary$libresoc.v:130704$5120 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:121056$4803_Y + connect \Y $ternary$libresoc.v:130704$5120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:121057$4804 + cell $mux $ternary$libresoc.v:130705$5121 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:121057$4804_Y + connect \Y $ternary$libresoc.v:130705$5121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:121058$4805 + cell $mux $ternary$libresoc.v:130706$5122 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:121058$4805_Y + connect \Y $ternary$libresoc.v:130706$5122_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:121059$4806 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:130707$5123 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:121059$4806_Y + connect \Y $ternary$libresoc.v:130707$5123_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:121061$4808 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:130709$5125 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:121061$4808_Y + connect \Y $ternary$libresoc.v:130709$5125_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:121062$4809 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:130710$5126 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:121062$4809_Y + connect \Y $ternary$libresoc.v:130710$5126_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121154.12-121190.4" + attribute \src "libresoc.v:130802.12-130838.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -190693,7 +206395,7 @@ module \div0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:121191.14-121197.4" + attribute \src "libresoc.v:130839.14-130845.4" cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -190702,7 +206404,7 @@ module \div0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:121198.15-121204.4" + attribute \src "libresoc.v:130846.15-130852.4" cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -190711,7 +206413,7 @@ module \div0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:121205.14-121211.4" + attribute \src "libresoc.v:130853.14-130859.4" cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -190720,7 +206422,7 @@ module \div0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:121212.14-121218.4" + attribute \src "libresoc.v:130860.14-130866.4" cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -190729,7 +206431,7 @@ module \div0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:121219.14-121225.4" + attribute \src "libresoc.v:130867.14-130873.4" cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -190738,7 +206440,7 @@ module \div0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:121226.14-121231.4" + attribute \src "libresoc.v:130874.14-130879.4" cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -190746,7 +206448,7 @@ module \div0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:121232.14-121238.4" + attribute \src "libresoc.v:130880.14-130886.4" cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -190754,682 +206456,682 @@ module \div0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:120358.7-120358.20" - process $proc$libresoc.v:120358$4985 + attribute \src "libresoc.v:130000.7-130000.20" + process $proc$libresoc.v:130000$5302 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120488.7-120488.24" - process $proc$libresoc.v:120488$4986 + attribute \src "libresoc.v:130130.7-130130.24" + process $proc$libresoc.v:130130$5303 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:120498.13-120498.49" - process $proc$libresoc.v:120498$4987 + attribute \src "libresoc.v:130140.13-130140.49" + process $proc$libresoc.v:130140$5304 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:120515.14-120515.52" - process $proc$libresoc.v:120515$4988 + attribute \src "libresoc.v:130159.14-130159.53" + process $proc$libresoc.v:130159$5305 assign { } { } - assign $1\alu_div0_logical_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[11:0] + update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:120519.14-120519.72" - process $proc$libresoc.v:120519$4989 + attribute \src "libresoc.v:130163.14-130163.72" + process $proc$libresoc.v:130163$5306 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:120523.7-120523.47" - process $proc$libresoc.v:120523$4990 + attribute \src "libresoc.v:130167.7-130167.47" + process $proc$libresoc.v:130167$5307 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:120531.13-120531.52" - process $proc$libresoc.v:120531$4991 + attribute \src "libresoc.v:130175.13-130175.52" + process $proc$libresoc.v:130175$5308 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:120535.14-120535.47" - process $proc$libresoc.v:120535$4992 + attribute \src "libresoc.v:130179.14-130179.47" + process $proc$libresoc.v:130179$5309 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:120613.13-120613.51" - process $proc$libresoc.v:120613$4993 + attribute \src "libresoc.v:130258.13-130258.51" + process $proc$libresoc.v:130258$5310 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:120617.7-120617.44" - process $proc$libresoc.v:120617$4994 + attribute \src "libresoc.v:130262.7-130262.44" + process $proc$libresoc.v:130262$5311 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:120621.7-120621.45" - process $proc$libresoc.v:120621$4995 + attribute \src "libresoc.v:130266.7-130266.45" + process $proc$libresoc.v:130266$5312 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:120625.7-120625.43" - process $proc$libresoc.v:120625$4996 + attribute \src "libresoc.v:130270.7-130270.43" + process $proc$libresoc.v:130270$5313 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:120629.7-120629.44" - process $proc$libresoc.v:120629$4997 + attribute \src "libresoc.v:130274.7-130274.44" + process $proc$libresoc.v:130274$5314 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:120633.7-120633.41" - process $proc$libresoc.v:120633$4998 + attribute \src "libresoc.v:130278.7-130278.41" + process $proc$libresoc.v:130278$5315 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:120637.7-120637.41" - process $proc$libresoc.v:120637$4999 + attribute \src "libresoc.v:130282.7-130282.41" + process $proc$libresoc.v:130282$5316 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:120641.7-120641.47" - process $proc$libresoc.v:120641$5000 + attribute \src "libresoc.v:130286.7-130286.47" + process $proc$libresoc.v:130286$5317 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:120645.7-120645.41" - process $proc$libresoc.v:120645$5001 + attribute \src "libresoc.v:130290.7-130290.41" + process $proc$libresoc.v:130290$5318 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:120649.7-120649.41" - process $proc$libresoc.v:120649$5002 + attribute \src "libresoc.v:130294.7-130294.41" + process $proc$libresoc.v:130294$5319 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:120653.7-120653.44" - process $proc$libresoc.v:120653$5003 + attribute \src "libresoc.v:130298.7-130298.44" + process $proc$libresoc.v:130298$5320 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:120657.7-120657.41" - process $proc$libresoc.v:120657$5004 + attribute \src "libresoc.v:130302.7-130302.41" + process $proc$libresoc.v:130302$5321 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:120683.7-120683.26" - process $proc$libresoc.v:120683$5005 + attribute \src "libresoc.v:130328.7-130328.26" + process $proc$libresoc.v:130328$5322 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:120691.7-120691.25" - process $proc$libresoc.v:120691$5006 + attribute \src "libresoc.v:130336.7-130336.25" + process $proc$libresoc.v:130336$5323 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:120703.7-120703.27" - process $proc$libresoc.v:120703$5007 + attribute \src "libresoc.v:130348.7-130348.27" + process $proc$libresoc.v:130348$5324 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:120737.14-120737.47" - process $proc$libresoc.v:120737$5008 + attribute \src "libresoc.v:130382.14-130382.47" + process $proc$libresoc.v:130382$5325 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:120741.7-120741.27" - process $proc$libresoc.v:120741$5009 + attribute \src "libresoc.v:130386.7-130386.27" + process $proc$libresoc.v:130386$5326 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:120745.13-120745.33" - process $proc$libresoc.v:120745$5010 + attribute \src "libresoc.v:130390.13-130390.33" + process $proc$libresoc.v:130390$5327 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:120749.7-120749.30" - process $proc$libresoc.v:120749$5011 + attribute \src "libresoc.v:130394.7-130394.30" + process $proc$libresoc.v:130394$5328 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:120753.13-120753.35" - process $proc$libresoc.v:120753$5012 + attribute \src "libresoc.v:130398.13-130398.35" + process $proc$libresoc.v:130398$5329 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:120757.7-120757.32" - process $proc$libresoc.v:120757$5013 + attribute \src "libresoc.v:130402.7-130402.32" + process $proc$libresoc.v:130402$5330 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:120761.7-120761.29" - process $proc$libresoc.v:120761$5014 + attribute \src "libresoc.v:130406.7-130406.29" + process $proc$libresoc.v:130406$5331 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:120765.7-120765.32" - process $proc$libresoc.v:120765$5015 + attribute \src "libresoc.v:130410.7-130410.32" + process $proc$libresoc.v:130410$5332 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:120785.7-120785.25" - process $proc$libresoc.v:120785$5016 + attribute \src "libresoc.v:130430.7-130430.25" + process $proc$libresoc.v:130430$5333 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:120789.7-120789.25" - process $proc$libresoc.v:120789$5017 + attribute \src "libresoc.v:130434.7-130434.25" + process $proc$libresoc.v:130434$5334 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:120920.13-120920.30" - process $proc$libresoc.v:120920$5018 + attribute \src "libresoc.v:130568.13-130568.30" + process $proc$libresoc.v:130568$5335 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:120928.13-120928.31" - process $proc$libresoc.v:120928$5019 + attribute \src "libresoc.v:130576.13-130576.31" + process $proc$libresoc.v:130576$5336 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:120932.13-120932.31" - process $proc$libresoc.v:120932$5020 + attribute \src "libresoc.v:130580.13-130580.31" + process $proc$libresoc.v:130580$5337 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:120944.7-120944.26" - process $proc$libresoc.v:120944$5021 + attribute \src "libresoc.v:130592.7-130592.26" + process $proc$libresoc.v:130592$5338 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:120948.7-120948.26" - process $proc$libresoc.v:120948$5022 + attribute \src "libresoc.v:130596.7-130596.26" + process $proc$libresoc.v:130596$5339 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:120952.7-120952.25" - process $proc$libresoc.v:120952$5023 + attribute \src "libresoc.v:130600.7-130600.25" + process $proc$libresoc.v:130600$5340 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:120956.7-120956.25" - process $proc$libresoc.v:120956$5024 + attribute \src "libresoc.v:130604.7-130604.25" + process $proc$libresoc.v:130604$5341 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:120970.13-120970.31" - process $proc$libresoc.v:120970$5025 + attribute \src "libresoc.v:130618.13-130618.31" + process $proc$libresoc.v:130618$5342 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:120974.13-120974.31" - process $proc$libresoc.v:120974$5026 + attribute \src "libresoc.v:130622.13-130622.31" + process $proc$libresoc.v:130622$5343 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:120982.14-120982.43" - process $proc$libresoc.v:120982$5027 + attribute \src "libresoc.v:130630.14-130630.43" + process $proc$libresoc.v:130630$5344 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:120986.14-120986.43" - process $proc$libresoc.v:120986$5028 + attribute \src "libresoc.v:130634.14-130634.43" + process $proc$libresoc.v:130634$5345 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:120990.7-120990.20" - process $proc$libresoc.v:120990$5029 + attribute \src "libresoc.v:130638.7-130638.20" + process $proc$libresoc.v:130638$5346 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:121066.3-121067.39" - process $proc$libresoc.v:121066$4813 + attribute \src "libresoc.v:130714.3-130715.39" + process $proc$libresoc.v:130714$5130 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:121068.3-121069.43" - process $proc$libresoc.v:121068$4814 + attribute \src "libresoc.v:130716.3-130717.43" + process $proc$libresoc.v:130716$5131 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:121070.3-121071.29" - process $proc$libresoc.v:121070$4815 + attribute \src "libresoc.v:130718.3-130719.29" + process $proc$libresoc.v:130718$5132 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:121072.3-121073.29" - process $proc$libresoc.v:121072$4816 + attribute \src "libresoc.v:130720.3-130721.29" + process $proc$libresoc.v:130720$5133 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:121074.3-121075.29" - process $proc$libresoc.v:121074$4817 + attribute \src "libresoc.v:130722.3-130723.29" + process $proc$libresoc.v:130722$5134 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:121076.3-121077.47" - process $proc$libresoc.v:121076$4818 + attribute \src "libresoc.v:130724.3-130725.47" + process $proc$libresoc.v:130724$5135 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:121078.3-121079.53" - process $proc$libresoc.v:121078$4819 + attribute \src "libresoc.v:130726.3-130727.53" + process $proc$libresoc.v:130726$5136 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:121080.3-121081.47" - process $proc$libresoc.v:121080$4820 + attribute \src "libresoc.v:130728.3-130729.47" + process $proc$libresoc.v:130728$5137 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:121082.3-121083.53" - process $proc$libresoc.v:121082$4821 + attribute \src "libresoc.v:130730.3-130731.53" + process $proc$libresoc.v:130730$5138 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:121084.3-121085.43" - process $proc$libresoc.v:121084$4822 + attribute \src "libresoc.v:130732.3-130733.43" + process $proc$libresoc.v:130732$5139 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:121086.3-121087.49" - process $proc$libresoc.v:121086$4823 + attribute \src "libresoc.v:130734.3-130735.49" + process $proc$libresoc.v:130734$5140 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:121088.3-121089.37" - process $proc$libresoc.v:121088$4824 + attribute \src "libresoc.v:130736.3-130737.37" + process $proc$libresoc.v:130736$5141 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:121090.3-121091.43" - process $proc$libresoc.v:121090$4825 + attribute \src "libresoc.v:130738.3-130739.43" + process $proc$libresoc.v:130738$5142 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:121092.3-121093.77" - process $proc$libresoc.v:121092$4826 + attribute \src "libresoc.v:130740.3-130741.77" + process $proc$libresoc.v:130740$5143 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:121094.3-121095.73" - process $proc$libresoc.v:121094$4827 + attribute \src "libresoc.v:130742.3-130743.73" + process $proc$libresoc.v:130742$5144 assign { } { } - assign $0\alu_div0_logical_op__fn_unit[11:0] \alu_div0_logical_op__fn_unit$next + assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk - update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[11:0] + update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:121096.3-121097.87" - process $proc$libresoc.v:121096$4828 + attribute \src "libresoc.v:130744.3-130745.87" + process $proc$libresoc.v:130744$5145 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:121098.3-121099.83" - process $proc$libresoc.v:121098$4829 + attribute \src "libresoc.v:130746.3-130747.83" + process $proc$libresoc.v:130746$5146 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:121100.3-121101.71" - process $proc$libresoc.v:121100$4830 + attribute \src "libresoc.v:130748.3-130749.71" + process $proc$libresoc.v:130748$5147 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:121102.3-121103.71" - process $proc$libresoc.v:121102$4831 + attribute \src "libresoc.v:130750.3-130751.71" + process $proc$libresoc.v:130750$5148 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:121104.3-121105.71" - process $proc$libresoc.v:121104$4832 + attribute \src "libresoc.v:130752.3-130753.71" + process $proc$libresoc.v:130752$5149 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:121106.3-121107.71" - process $proc$libresoc.v:121106$4833 + attribute \src "libresoc.v:130754.3-130755.71" + process $proc$libresoc.v:130754$5150 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:121108.3-121109.77" - process $proc$libresoc.v:121108$4834 + attribute \src "libresoc.v:130756.3-130757.77" + process $proc$libresoc.v:130756$5151 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:121110.3-121111.71" - process $proc$libresoc.v:121110$4835 + attribute \src "libresoc.v:130758.3-130759.71" + process $proc$libresoc.v:130758$5152 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:121112.3-121113.81" - process $proc$libresoc.v:121112$4836 + attribute \src "libresoc.v:130760.3-130761.81" + process $proc$libresoc.v:130760$5153 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:121114.3-121115.79" - process $proc$libresoc.v:121114$4837 + attribute \src "libresoc.v:130762.3-130763.79" + process $proc$libresoc.v:130762$5154 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:121116.3-121117.77" - process $proc$libresoc.v:121116$4838 + attribute \src "libresoc.v:130764.3-130765.77" + process $proc$libresoc.v:130764$5155 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:121118.3-121119.83" - process $proc$libresoc.v:121118$4839 + attribute \src "libresoc.v:130766.3-130767.83" + process $proc$libresoc.v:130766$5156 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:121120.3-121121.75" - process $proc$libresoc.v:121120$4840 + attribute \src "libresoc.v:130768.3-130769.75" + process $proc$libresoc.v:130768$5157 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:121122.3-121123.77" - process $proc$libresoc.v:121122$4841 + attribute \src "libresoc.v:130770.3-130771.77" + process $proc$libresoc.v:130770$5158 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:121124.3-121125.75" - process $proc$libresoc.v:121124$4842 + attribute \src "libresoc.v:130772.3-130773.75" + process $proc$libresoc.v:130772$5159 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:121126.3-121127.67" - process $proc$libresoc.v:121126$4843 + attribute \src "libresoc.v:130774.3-130775.67" + process $proc$libresoc.v:130774$5160 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:121128.3-121129.39" - process $proc$libresoc.v:121128$4844 + attribute \src "libresoc.v:130776.3-130777.39" + process $proc$libresoc.v:130776$5161 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:121130.3-121131.39" - process $proc$libresoc.v:121130$4845 + attribute \src "libresoc.v:130778.3-130779.39" + process $proc$libresoc.v:130778$5162 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:121132.3-121133.39" - process $proc$libresoc.v:121132$4846 + attribute \src "libresoc.v:130780.3-130781.39" + process $proc$libresoc.v:130780$5163 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:121134.3-121135.39" - process $proc$libresoc.v:121134$4847 + attribute \src "libresoc.v:130782.3-130783.39" + process $proc$libresoc.v:130782$5164 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:121136.3-121137.39" - process $proc$libresoc.v:121136$4848 + attribute \src "libresoc.v:130784.3-130785.39" + process $proc$libresoc.v:130784$5165 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:121138.3-121139.39" - process $proc$libresoc.v:121138$4849 + attribute \src "libresoc.v:130786.3-130787.39" + process $proc$libresoc.v:130786$5166 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:121140.3-121141.39" - process $proc$libresoc.v:121140$4850 + attribute \src "libresoc.v:130788.3-130789.39" + process $proc$libresoc.v:130788$5167 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:121142.3-121143.39" - process $proc$libresoc.v:121142$4851 + attribute \src "libresoc.v:130790.3-130791.39" + process $proc$libresoc.v:130790$5168 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:121144.3-121145.41" - process $proc$libresoc.v:121144$4852 + attribute \src "libresoc.v:130792.3-130793.41" + process $proc$libresoc.v:130792$5169 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:121146.3-121147.41" - process $proc$libresoc.v:121146$4853 + attribute \src "libresoc.v:130794.3-130795.41" + process $proc$libresoc.v:130794$5170 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:121148.3-121149.37" - process $proc$libresoc.v:121148$4854 + attribute \src "libresoc.v:130796.3-130797.37" + process $proc$libresoc.v:130796$5171 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:121150.3-121151.40" - process $proc$libresoc.v:121150$4855 + attribute \src "libresoc.v:130798.3-130799.40" + process $proc$libresoc.v:130798$5172 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:121152.3-121153.25" - process $proc$libresoc.v:121152$4856 + attribute \src "libresoc.v:130800.3-130801.25" + process $proc$libresoc.v:130800$5173 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:121239.3-121248.6" - process $proc$libresoc.v:121239$4857 + attribute \src "libresoc.v:130887.3-130896.6" + process $proc$libresoc.v:130887$5174 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:121240.5-121240.29" + attribute \src "libresoc.v:130888.5-130888.29" switch \initial - attribute \src "libresoc.v:121240.9-121240.17" + attribute \src "libresoc.v:130888.9-130888.17" case 1'1 case end @@ -191445,14 +207147,14 @@ module \div0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:121249.3-121257.6" - process $proc$libresoc.v:121249$4858 + attribute \src "libresoc.v:130897.3-130905.6" + process $proc$libresoc.v:130897$5175 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$4859 $1\rok_l_s_rdok$next[0:0]$4860 - attribute \src "libresoc.v:121250.5-121250.29" + assign $0\rok_l_s_rdok$next[0:0]$5176 $1\rok_l_s_rdok$next[0:0]$5177 + attribute \src "libresoc.v:130898.5-130898.29" switch \initial - attribute \src "libresoc.v:121250.9-121250.17" + attribute \src "libresoc.v:130898.9-130898.17" case 1'1 case end @@ -191461,21 +207163,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$4860 1'0 + assign $1\rok_l_s_rdok$next[0:0]$5177 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$4860 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$5177 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$4859 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5176 end - attribute \src "libresoc.v:121258.3-121266.6" - process $proc$libresoc.v:121258$4861 + attribute \src "libresoc.v:130906.3-130914.6" + process $proc$libresoc.v:130906$5178 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$4862 $1\rok_l_r_rdok$next[0:0]$4863 - attribute \src "libresoc.v:121259.5-121259.29" + assign $0\rok_l_r_rdok$next[0:0]$5179 $1\rok_l_r_rdok$next[0:0]$5180 + attribute \src "libresoc.v:130907.5-130907.29" switch \initial - attribute \src "libresoc.v:121259.9-121259.17" + attribute \src "libresoc.v:130907.9-130907.17" case 1'1 case end @@ -191484,21 +207186,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$4863 1'1 + assign $1\rok_l_r_rdok$next[0:0]$5180 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$4863 \$64 + assign $1\rok_l_r_rdok$next[0:0]$5180 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$4862 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5179 end - attribute \src "libresoc.v:121267.3-121275.6" - process $proc$libresoc.v:121267$4864 + attribute \src "libresoc.v:130915.3-130923.6" + process $proc$libresoc.v:130915$5181 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$4865 $1\rst_l_s_rst$next[0:0]$4866 - attribute \src "libresoc.v:121268.5-121268.29" + assign $0\rst_l_s_rst$next[0:0]$5182 $1\rst_l_s_rst$next[0:0]$5183 + attribute \src "libresoc.v:130916.5-130916.29" switch \initial - attribute \src "libresoc.v:121268.9-121268.17" + attribute \src "libresoc.v:130916.9-130916.17" case 1'1 case end @@ -191507,21 +207209,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$4866 1'0 + assign $1\rst_l_s_rst$next[0:0]$5183 1'0 case - assign $1\rst_l_s_rst$next[0:0]$4866 \all_rd + assign $1\rst_l_s_rst$next[0:0]$5183 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$4865 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5182 end - attribute \src "libresoc.v:121276.3-121284.6" - process $proc$libresoc.v:121276$4867 + attribute \src "libresoc.v:130924.3-130932.6" + process $proc$libresoc.v:130924$5184 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$4868 $1\rst_l_r_rst$next[0:0]$4869 - attribute \src "libresoc.v:121277.5-121277.29" + assign $0\rst_l_r_rst$next[0:0]$5185 $1\rst_l_r_rst$next[0:0]$5186 + attribute \src "libresoc.v:130925.5-130925.29" switch \initial - attribute \src "libresoc.v:121277.9-121277.17" + attribute \src "libresoc.v:130925.9-130925.17" case 1'1 case end @@ -191530,21 +207232,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$4869 1'1 + assign $1\rst_l_r_rst$next[0:0]$5186 1'1 case - assign $1\rst_l_r_rst$next[0:0]$4869 \rst_r + assign $1\rst_l_r_rst$next[0:0]$5186 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$4868 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5185 end - attribute \src "libresoc.v:121285.3-121293.6" - process $proc$libresoc.v:121285$4870 + attribute \src "libresoc.v:130933.3-130941.6" + process $proc$libresoc.v:130933$5187 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$4871 $1\opc_l_s_opc$next[0:0]$4872 - attribute \src "libresoc.v:121286.5-121286.29" + assign $0\opc_l_s_opc$next[0:0]$5188 $1\opc_l_s_opc$next[0:0]$5189 + attribute \src "libresoc.v:130934.5-130934.29" switch \initial - attribute \src "libresoc.v:121286.9-121286.17" + attribute \src "libresoc.v:130934.9-130934.17" case 1'1 case end @@ -191553,21 +207255,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$4872 1'0 + assign $1\opc_l_s_opc$next[0:0]$5189 1'0 case - assign $1\opc_l_s_opc$next[0:0]$4872 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$5189 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$4871 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5188 end - attribute \src "libresoc.v:121294.3-121302.6" - process $proc$libresoc.v:121294$4873 + attribute \src "libresoc.v:130942.3-130950.6" + process $proc$libresoc.v:130942$5190 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$4874 $1\opc_l_r_opc$next[0:0]$4875 - attribute \src "libresoc.v:121295.5-121295.29" + assign $0\opc_l_r_opc$next[0:0]$5191 $1\opc_l_r_opc$next[0:0]$5192 + attribute \src "libresoc.v:130943.5-130943.29" switch \initial - attribute \src "libresoc.v:121295.9-121295.17" + attribute \src "libresoc.v:130943.9-130943.17" case 1'1 case end @@ -191576,21 +207278,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$4875 1'1 + assign $1\opc_l_r_opc$next[0:0]$5192 1'1 case - assign $1\opc_l_r_opc$next[0:0]$4875 \req_done + assign $1\opc_l_r_opc$next[0:0]$5192 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$4874 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5191 end - attribute \src "libresoc.v:121303.3-121311.6" - process $proc$libresoc.v:121303$4876 + attribute \src "libresoc.v:130951.3-130959.6" + process $proc$libresoc.v:130951$5193 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$4877 $1\src_l_s_src$next[2:0]$4878 - attribute \src "libresoc.v:121304.5-121304.29" + assign $0\src_l_s_src$next[2:0]$5194 $1\src_l_s_src$next[2:0]$5195 + attribute \src "libresoc.v:130952.5-130952.29" switch \initial - attribute \src "libresoc.v:121304.9-121304.17" + attribute \src "libresoc.v:130952.9-130952.17" case 1'1 case end @@ -191599,21 +207301,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$4878 3'000 + assign $1\src_l_s_src$next[2:0]$5195 3'000 case - assign $1\src_l_s_src$next[2:0]$4878 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$5195 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$4877 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5194 end - attribute \src "libresoc.v:121312.3-121320.6" - process $proc$libresoc.v:121312$4879 + attribute \src "libresoc.v:130960.3-130968.6" + process $proc$libresoc.v:130960$5196 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$4880 $1\src_l_r_src$next[2:0]$4881 - attribute \src "libresoc.v:121313.5-121313.29" + assign $0\src_l_r_src$next[2:0]$5197 $1\src_l_r_src$next[2:0]$5198 + attribute \src "libresoc.v:130961.5-130961.29" switch \initial - attribute \src "libresoc.v:121313.9-121313.17" + attribute \src "libresoc.v:130961.9-130961.17" case 1'1 case end @@ -191622,21 +207324,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$4881 3'111 + assign $1\src_l_r_src$next[2:0]$5198 3'111 case - assign $1\src_l_r_src$next[2:0]$4881 \reset_r + assign $1\src_l_r_src$next[2:0]$5198 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$4880 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5197 end - attribute \src "libresoc.v:121321.3-121329.6" - process $proc$libresoc.v:121321$4882 + attribute \src "libresoc.v:130969.3-130977.6" + process $proc$libresoc.v:130969$5199 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$4883 $1\req_l_s_req$next[3:0]$4884 - attribute \src "libresoc.v:121322.5-121322.29" + assign $0\req_l_s_req$next[3:0]$5200 $1\req_l_s_req$next[3:0]$5201 + attribute \src "libresoc.v:130970.5-130970.29" switch \initial - attribute \src "libresoc.v:121322.9-121322.17" + attribute \src "libresoc.v:130970.9-130970.17" case 1'1 case end @@ -191645,21 +207347,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$4884 4'0000 + assign $1\req_l_s_req$next[3:0]$5201 4'0000 case - assign $1\req_l_s_req$next[3:0]$4884 \$66 + assign $1\req_l_s_req$next[3:0]$5201 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$4883 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5200 end - attribute \src "libresoc.v:121330.3-121338.6" - process $proc$libresoc.v:121330$4885 + attribute \src "libresoc.v:130978.3-130986.6" + process $proc$libresoc.v:130978$5202 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$4886 $1\req_l_r_req$next[3:0]$4887 - attribute \src "libresoc.v:121331.5-121331.29" + assign $0\req_l_r_req$next[3:0]$5203 $1\req_l_r_req$next[3:0]$5204 + attribute \src "libresoc.v:130979.5-130979.29" switch \initial - attribute \src "libresoc.v:121331.9-121331.17" + attribute \src "libresoc.v:130979.9-130979.17" case 1'1 case end @@ -191668,15 +207370,15 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$4887 4'1111 + assign $1\req_l_r_req$next[3:0]$5204 4'1111 case - assign $1\req_l_r_req$next[3:0]$4887 \$68 + assign $1\req_l_r_req$next[3:0]$5204 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$4886 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5203 end - attribute \src "libresoc.v:121339.3-121377.6" - process $proc$libresoc.v:121339$4888 + attribute \src "libresoc.v:130987.3-131025.6" + process $proc$libresoc.v:130987$5205 assign { } { } assign { } { } assign { } { } @@ -191713,33 +207415,33 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$4889 $1\alu_div0_logical_op__data_len$next[3:0]$4907 - assign $0\alu_div0_logical_op__fn_unit$next[11:0]$4890 $1\alu_div0_logical_op__fn_unit$next[11:0]$4908 + assign $0\alu_div0_logical_op__data_len$next[3:0]$5206 $1\alu_div0_logical_op__data_len$next[3:0]$5224 + assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$4893 $1\alu_div0_logical_op__input_carry$next[1:0]$4911 - assign $0\alu_div0_logical_op__insn$next[31:0]$4894 $1\alu_div0_logical_op__insn$next[31:0]$4912 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$4895 $1\alu_div0_logical_op__insn_type$next[6:0]$4913 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$4896 $1\alu_div0_logical_op__invert_in$next[0:0]$4914 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$4897 $1\alu_div0_logical_op__invert_out$next[0:0]$4915 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$4898 $1\alu_div0_logical_op__is_32bit$next[0:0]$4916 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$4899 $1\alu_div0_logical_op__is_signed$next[0:0]$4917 + assign $0\alu_div0_logical_op__input_carry$next[1:0]$5210 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 + assign $0\alu_div0_logical_op__insn$next[31:0]$5211 $1\alu_div0_logical_op__insn$next[31:0]$5229 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$5212 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$5213 $1\alu_div0_logical_op__invert_in$next[0:0]$5231 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$5214 $1\alu_div0_logical_op__invert_out$next[0:0]$5232 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$5216 $1\alu_div0_logical_op__is_signed$next[0:0]$5234 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$4902 $1\alu_div0_logical_op__output_carry$next[0:0]$4920 + assign $0\alu_div0_logical_op__output_carry$next[0:0]$5219 $1\alu_div0_logical_op__output_carry$next[0:0]$5237 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$4905 $1\alu_div0_logical_op__write_cr0$next[0:0]$4923 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$4906 $1\alu_div0_logical_op__zero_a$next[0:0]$4924 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$4891 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4925 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4892 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4926 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$4900 $2\alu_div0_logical_op__oe__oe$next[0:0]$4927 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$4901 $2\alu_div0_logical_op__oe__ok$next[0:0]$4928 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$4903 $2\alu_div0_logical_op__rc__ok$next[0:0]$4929 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$4904 $2\alu_div0_logical_op__rc__rc$next[0:0]$4930 - attribute \src "libresoc.v:121340.5-121340.29" + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$5223 $1\alu_div0_logical_op__zero_a$next[0:0]$5241 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 + attribute \src "libresoc.v:130988.5-130988.29" switch \initial - attribute \src "libresoc.v:121340.9-121340.17" + attribute \src "libresoc.v:130988.9-130988.17" case 1'1 case end @@ -191765,26 +207467,26 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$4912 $1\alu_div0_logical_op__data_len$next[3:0]$4907 $1\alu_div0_logical_op__is_signed$next[0:0]$4917 $1\alu_div0_logical_op__is_32bit$next[0:0]$4916 $1\alu_div0_logical_op__output_carry$next[0:0]$4920 $1\alu_div0_logical_op__write_cr0$next[0:0]$4923 $1\alu_div0_logical_op__invert_out$next[0:0]$4915 $1\alu_div0_logical_op__input_carry$next[1:0]$4911 $1\alu_div0_logical_op__zero_a$next[0:0]$4924 $1\alu_div0_logical_op__invert_in$next[0:0]$4914 $1\alu_div0_logical_op__oe__ok$next[0:0]$4919 $1\alu_div0_logical_op__oe__oe$next[0:0]$4918 $1\alu_div0_logical_op__rc__ok$next[0:0]$4921 $1\alu_div0_logical_op__rc__rc$next[0:0]$4922 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4910 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4909 $1\alu_div0_logical_op__fn_unit$next[11:0]$4908 $1\alu_div0_logical_op__insn_type$next[6:0]$4913 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + assign { $1\alu_div0_logical_op__insn$next[31:0]$5229 $1\alu_div0_logical_op__data_len$next[3:0]$5224 $1\alu_div0_logical_op__is_signed$next[0:0]$5234 $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 $1\alu_div0_logical_op__output_carry$next[0:0]$5237 $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 $1\alu_div0_logical_op__invert_out$next[0:0]$5232 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 $1\alu_div0_logical_op__zero_a$next[0:0]$5241 $1\alu_div0_logical_op__invert_in$next[0:0]$5231 $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } case - assign $1\alu_div0_logical_op__data_len$next[3:0]$4907 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[11:0]$4908 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$4909 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4910 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$4911 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$4912 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$4913 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$4914 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$4915 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$4916 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$4917 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$4918 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$4919 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$4920 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$4921 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$4922 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$4923 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$4924 \alu_div0_logical_op__zero_a + assign $1\alu_div0_logical_op__data_len$next[3:0]$5224 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$5228 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$5229 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$5230 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$5231 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$5232 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$5234 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$5237 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$5241 \alu_div0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -191796,54 +207498,54 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4925 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4926 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4930 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4929 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4927 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4928 1'0 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 1'0 case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4925 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4909 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4926 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4910 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4927 $1\alu_div0_logical_op__oe__oe$next[0:0]$4918 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4928 $1\alu_div0_logical_op__oe__ok$next[0:0]$4919 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4929 $1\alu_div0_logical_op__rc__ok$next[0:0]$4921 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4930 $1\alu_div0_logical_op__rc__rc$next[0:0]$4922 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 end sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$4889 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[11:0]$4890 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$4891 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4892 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$4893 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$4894 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$4895 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$4896 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$4897 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$4898 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$4899 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$4900 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$4901 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$4902 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$4903 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$4904 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$4905 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$4906 + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5206 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5210 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5211 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5212 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5213 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5214 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5216 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5219 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5223 end - attribute \src "libresoc.v:121378.3-121399.6" - process $proc$libresoc.v:121378$4931 + attribute \src "libresoc.v:131026.3-131047.6" + process $proc$libresoc.v:131026$5248 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$4932 $2\data_r0__o$next[63:0]$4936 + assign $0\data_r0__o$next[63:0]$5249 $2\data_r0__o$next[63:0]$5253 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$4933 $3\data_r0__o_ok$next[0:0]$4938 - attribute \src "libresoc.v:121379.5-121379.29" + assign $0\data_r0__o_ok$next[0:0]$5250 $3\data_r0__o_ok$next[0:0]$5255 + attribute \src "libresoc.v:131027.5-131027.29" switch \initial - attribute \src "libresoc.v:121379.9-121379.17" + attribute \src "libresoc.v:131027.9-131027.17" case 1'1 case end @@ -191853,10 +207555,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$4935 $1\data_r0__o$next[63:0]$4934 } { \o_ok \alu_div0_o } + assign { $1\data_r0__o_ok$next[0:0]$5252 $1\data_r0__o$next[63:0]$5251 } { \o_ok \alu_div0_o } case - assign $1\data_r0__o$next[63:0]$4934 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$4935 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$5251 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5252 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -191864,38 +207566,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$4937 $2\data_r0__o$next[63:0]$4936 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$5254 $2\data_r0__o$next[63:0]$5253 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$4936 $1\data_r0__o$next[63:0]$4934 - assign $2\data_r0__o_ok$next[0:0]$4937 $1\data_r0__o_ok$next[0:0]$4935 + assign $2\data_r0__o$next[63:0]$5253 $1\data_r0__o$next[63:0]$5251 + assign $2\data_r0__o_ok$next[0:0]$5254 $1\data_r0__o_ok$next[0:0]$5252 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$4938 1'0 + assign $3\data_r0__o_ok$next[0:0]$5255 1'0 case - assign $3\data_r0__o_ok$next[0:0]$4938 $2\data_r0__o_ok$next[0:0]$4937 + assign $3\data_r0__o_ok$next[0:0]$5255 $2\data_r0__o_ok$next[0:0]$5254 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$4932 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$4933 + update \data_r0__o$next $0\data_r0__o$next[63:0]$5249 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5250 end - attribute \src "libresoc.v:121400.3-121421.6" - process $proc$libresoc.v:121400$4939 + attribute \src "libresoc.v:131048.3-131069.6" + process $proc$libresoc.v:131048$5256 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$4940 $2\data_r1__cr_a$next[3:0]$4944 + assign $0\data_r1__cr_a$next[3:0]$5257 $2\data_r1__cr_a$next[3:0]$5261 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$4941 $3\data_r1__cr_a_ok$next[0:0]$4946 - attribute \src "libresoc.v:121401.5-121401.29" + assign $0\data_r1__cr_a_ok$next[0:0]$5258 $3\data_r1__cr_a_ok$next[0:0]$5263 + attribute \src "libresoc.v:131049.5-131049.29" switch \initial - attribute \src "libresoc.v:121401.9-121401.17" + attribute \src "libresoc.v:131049.9-131049.17" case 1'1 case end @@ -191905,10 +207607,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$4943 $1\data_r1__cr_a$next[3:0]$4942 } { \cr_a_ok \alu_div0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$5260 $1\data_r1__cr_a$next[3:0]$5259 } { \cr_a_ok \alu_div0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$4942 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$4943 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$5259 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5260 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -191916,38 +207618,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$4945 $2\data_r1__cr_a$next[3:0]$4944 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$5262 $2\data_r1__cr_a$next[3:0]$5261 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$4944 $1\data_r1__cr_a$next[3:0]$4942 - assign $2\data_r1__cr_a_ok$next[0:0]$4945 $1\data_r1__cr_a_ok$next[0:0]$4943 + assign $2\data_r1__cr_a$next[3:0]$5261 $1\data_r1__cr_a$next[3:0]$5259 + assign $2\data_r1__cr_a_ok$next[0:0]$5262 $1\data_r1__cr_a_ok$next[0:0]$5260 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$4946 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$5263 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$4946 $2\data_r1__cr_a_ok$next[0:0]$4945 + assign $3\data_r1__cr_a_ok$next[0:0]$5263 $2\data_r1__cr_a_ok$next[0:0]$5262 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$4940 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$4941 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5257 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5258 end - attribute \src "libresoc.v:121422.3-121443.6" - process $proc$libresoc.v:121422$4947 + attribute \src "libresoc.v:131070.3-131091.6" + process $proc$libresoc.v:131070$5264 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$4948 $2\data_r2__xer_ov$next[1:0]$4952 + assign $0\data_r2__xer_ov$next[1:0]$5265 $2\data_r2__xer_ov$next[1:0]$5269 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$4949 $3\data_r2__xer_ov_ok$next[0:0]$4954 - attribute \src "libresoc.v:121423.5-121423.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$5266 $3\data_r2__xer_ov_ok$next[0:0]$5271 + attribute \src "libresoc.v:131071.5-131071.29" switch \initial - attribute \src "libresoc.v:121423.9-121423.17" + attribute \src "libresoc.v:131071.9-131071.17" case 1'1 case end @@ -191957,10 +207659,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$4951 $1\data_r2__xer_ov$next[1:0]$4950 } { \xer_ov_ok \alu_div0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$5268 $1\data_r2__xer_ov$next[1:0]$5267 } { \xer_ov_ok \alu_div0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$4950 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$4951 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$5267 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$5268 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -191968,38 +207670,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$4953 $2\data_r2__xer_ov$next[1:0]$4952 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$5270 $2\data_r2__xer_ov$next[1:0]$5269 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$4952 $1\data_r2__xer_ov$next[1:0]$4950 - assign $2\data_r2__xer_ov_ok$next[0:0]$4953 $1\data_r2__xer_ov_ok$next[0:0]$4951 + assign $2\data_r2__xer_ov$next[1:0]$5269 $1\data_r2__xer_ov$next[1:0]$5267 + assign $2\data_r2__xer_ov_ok$next[0:0]$5270 $1\data_r2__xer_ov_ok$next[0:0]$5268 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$4954 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$5271 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$4954 $2\data_r2__xer_ov_ok$next[0:0]$4953 + assign $3\data_r2__xer_ov_ok$next[0:0]$5271 $2\data_r2__xer_ov_ok$next[0:0]$5270 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$4948 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$4949 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5265 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5266 end - attribute \src "libresoc.v:121444.3-121465.6" - process $proc$libresoc.v:121444$4955 + attribute \src "libresoc.v:131092.3-131113.6" + process $proc$libresoc.v:131092$5272 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$4956 $2\data_r3__xer_so$next[0:0]$4960 + assign $0\data_r3__xer_so$next[0:0]$5273 $2\data_r3__xer_so$next[0:0]$5277 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$4957 $3\data_r3__xer_so_ok$next[0:0]$4962 - attribute \src "libresoc.v:121445.5-121445.29" + assign $0\data_r3__xer_so_ok$next[0:0]$5274 $3\data_r3__xer_so_ok$next[0:0]$5279 + attribute \src "libresoc.v:131093.5-131093.29" switch \initial - attribute \src "libresoc.v:121445.9-121445.17" + attribute \src "libresoc.v:131093.9-131093.17" case 1'1 case end @@ -192009,10 +207711,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$4959 $1\data_r3__xer_so$next[0:0]$4958 } { \xer_so_ok \alu_div0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$5276 $1\data_r3__xer_so$next[0:0]$5275 } { \xer_so_ok \alu_div0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$4958 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$4959 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$5275 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$5276 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -192020,101 +207722,101 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$4961 $2\data_r3__xer_so$next[0:0]$4960 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$5278 $2\data_r3__xer_so$next[0:0]$5277 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$4960 $1\data_r3__xer_so$next[0:0]$4958 - assign $2\data_r3__xer_so_ok$next[0:0]$4961 $1\data_r3__xer_so_ok$next[0:0]$4959 + assign $2\data_r3__xer_so$next[0:0]$5277 $1\data_r3__xer_so$next[0:0]$5275 + assign $2\data_r3__xer_so_ok$next[0:0]$5278 $1\data_r3__xer_so_ok$next[0:0]$5276 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$4962 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$5279 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$4962 $2\data_r3__xer_so_ok$next[0:0]$4961 + assign $3\data_r3__xer_so_ok$next[0:0]$5279 $2\data_r3__xer_so_ok$next[0:0]$5278 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$4956 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$4957 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5273 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5274 end - attribute \src "libresoc.v:121466.3-121475.6" - process $proc$libresoc.v:121466$4963 + attribute \src "libresoc.v:131114.3-131123.6" + process $proc$libresoc.v:131114$5280 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$4964 $1\src_r0$next[63:0]$4965 - attribute \src "libresoc.v:121467.5-121467.29" + assign $0\src_r0$next[63:0]$5281 $1\src_r0$next[63:0]$5282 + attribute \src "libresoc.v:131115.5-131115.29" switch \initial - attribute \src "libresoc.v:121467.9-121467.17" + attribute \src "libresoc.v:131115.9-131115.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$4965 \src_or_imm + assign $1\src_r0$next[63:0]$5282 \src_or_imm case - assign $1\src_r0$next[63:0]$4965 \src_r0 + assign $1\src_r0$next[63:0]$5282 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$4964 + update \src_r0$next $0\src_r0$next[63:0]$5281 end - attribute \src "libresoc.v:121476.3-121485.6" - process $proc$libresoc.v:121476$4966 + attribute \src "libresoc.v:131124.3-131133.6" + process $proc$libresoc.v:131124$5283 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$4967 $1\src_r1$next[63:0]$4968 - attribute \src "libresoc.v:121477.5-121477.29" + assign $0\src_r1$next[63:0]$5284 $1\src_r1$next[63:0]$5285 + attribute \src "libresoc.v:131125.5-131125.29" switch \initial - attribute \src "libresoc.v:121477.9-121477.17" + attribute \src "libresoc.v:131125.9-131125.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel$82 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$4968 \src_or_imm$85 + assign $1\src_r1$next[63:0]$5285 \src_or_imm$85 case - assign $1\src_r1$next[63:0]$4968 \src_r1 + assign $1\src_r1$next[63:0]$5285 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$4967 + update \src_r1$next $0\src_r1$next[63:0]$5284 end - attribute \src "libresoc.v:121486.3-121495.6" - process $proc$libresoc.v:121486$4969 + attribute \src "libresoc.v:131134.3-131143.6" + process $proc$libresoc.v:131134$5286 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$4970 $1\src_r2$next[0:0]$4971 - attribute \src "libresoc.v:121487.5-121487.29" + assign $0\src_r2$next[0:0]$5287 $1\src_r2$next[0:0]$5288 + attribute \src "libresoc.v:131135.5-131135.29" switch \initial - attribute \src "libresoc.v:121487.9-121487.17" + attribute \src "libresoc.v:131135.9-131135.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$4971 \src3_i + assign $1\src_r2$next[0:0]$5288 \src3_i case - assign $1\src_r2$next[0:0]$4971 \src_r2 + assign $1\src_r2$next[0:0]$5288 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$4970 + update \src_r2$next $0\src_r2$next[0:0]$5287 end - attribute \src "libresoc.v:121496.3-121504.6" - process $proc$libresoc.v:121496$4972 + attribute \src "libresoc.v:131144.3-131152.6" + process $proc$libresoc.v:131144$5289 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$4973 $1\alui_l_r_alui$next[0:0]$4974 - attribute \src "libresoc.v:121497.5-121497.29" + assign $0\alui_l_r_alui$next[0:0]$5290 $1\alui_l_r_alui$next[0:0]$5291 + attribute \src "libresoc.v:131145.5-131145.29" switch \initial - attribute \src "libresoc.v:121497.9-121497.17" + attribute \src "libresoc.v:131145.9-131145.17" case 1'1 case end @@ -192123,21 +207825,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$4974 1'1 + assign $1\alui_l_r_alui$next[0:0]$5291 1'1 case - assign $1\alui_l_r_alui$next[0:0]$4974 \$94 + assign $1\alui_l_r_alui$next[0:0]$5291 \$94 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$4973 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5290 end - attribute \src "libresoc.v:121505.3-121513.6" - process $proc$libresoc.v:121505$4975 + attribute \src "libresoc.v:131153.3-131161.6" + process $proc$libresoc.v:131153$5292 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$4976 $1\alu_l_r_alu$next[0:0]$4977 - attribute \src "libresoc.v:121506.5-121506.29" + assign $0\alu_l_r_alu$next[0:0]$5293 $1\alu_l_r_alu$next[0:0]$5294 + attribute \src "libresoc.v:131154.5-131154.29" switch \initial - attribute \src "libresoc.v:121506.9-121506.17" + attribute \src "libresoc.v:131154.9-131154.17" case 1'1 case end @@ -192146,21 +207848,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$4977 1'1 + assign $1\alu_l_r_alu$next[0:0]$5294 1'1 case - assign $1\alu_l_r_alu$next[0:0]$4977 \$96 + assign $1\alu_l_r_alu$next[0:0]$5294 \$96 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$4976 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5293 end - attribute \src "libresoc.v:121514.3-121523.6" - process $proc$libresoc.v:121514$4978 + attribute \src "libresoc.v:131162.3-131171.6" + process $proc$libresoc.v:131162$5295 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:121515.5-121515.29" + attribute \src "libresoc.v:131163.5-131163.29" switch \initial - attribute \src "libresoc.v:121515.9-121515.17" + attribute \src "libresoc.v:131163.9-131163.17" case 1'1 case end @@ -192176,14 +207878,14 @@ module \div0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:121524.3-121533.6" - process $proc$libresoc.v:121524$4979 + attribute \src "libresoc.v:131172.3-131181.6" + process $proc$libresoc.v:131172$5296 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:121525.5-121525.29" + attribute \src "libresoc.v:131173.5-131173.29" switch \initial - attribute \src "libresoc.v:121525.9-121525.17" + attribute \src "libresoc.v:131173.9-131173.17" case 1'1 case end @@ -192199,14 +207901,14 @@ module \div0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:121534.3-121543.6" - process $proc$libresoc.v:121534$4980 + attribute \src "libresoc.v:131182.3-131191.6" + process $proc$libresoc.v:131182$5297 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:121535.5-121535.29" + attribute \src "libresoc.v:131183.5-131183.29" switch \initial - attribute \src "libresoc.v:121535.9-121535.17" + attribute \src "libresoc.v:131183.9-131183.17" case 1'1 case end @@ -192222,14 +207924,14 @@ module \div0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:121544.3-121553.6" - process $proc$libresoc.v:121544$4981 + attribute \src "libresoc.v:131192.3-131201.6" + process $proc$libresoc.v:131192$5298 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:121545.5-121545.29" + attribute \src "libresoc.v:131193.5-131193.29" switch \initial - attribute \src "libresoc.v:121545.9-121545.17" + attribute \src "libresoc.v:131193.9-131193.17" case 1'1 case end @@ -192245,14 +207947,14 @@ module \div0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:121554.3-121562.6" - process $proc$libresoc.v:121554$4982 + attribute \src "libresoc.v:131202.3-131210.6" + process $proc$libresoc.v:131202$5299 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$4983 $1\prev_wr_go$next[3:0]$4984 - attribute \src "libresoc.v:121555.5-121555.29" + assign $0\prev_wr_go$next[3:0]$5300 $1\prev_wr_go$next[3:0]$5301 + attribute \src "libresoc.v:131203.5-131203.29" switch \initial - attribute \src "libresoc.v:121555.9-121555.17" + attribute \src "libresoc.v:131203.9-131203.17" case 1'1 case end @@ -192261,76 +207963,76 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$4984 4'0000 - case - assign $1\prev_wr_go$next[3:0]$4984 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$4983 - end - connect \$100 $not$libresoc.v:121003$4750_Y - connect \$102 $not$libresoc.v:121004$4751_Y - connect \$104 $and$libresoc.v:121005$4752_Y - connect \$106 $not$libresoc.v:121006$4753_Y - connect \$108 $and$libresoc.v:121007$4754_Y - connect \$10 $and$libresoc.v:121008$4755_Y - connect \$110 $and$libresoc.v:121009$4756_Y - connect \$112 $and$libresoc.v:121010$4757_Y - connect \$114 $and$libresoc.v:121011$4758_Y - connect \$116 $and$libresoc.v:121012$4759_Y - connect \$118 $and$libresoc.v:121013$4760_Y - connect \$120 $and$libresoc.v:121014$4761_Y - connect \$122 $and$libresoc.v:121015$4762_Y - connect \$124 $and$libresoc.v:121016$4763_Y - connect \$126 $and$libresoc.v:121017$4764_Y - connect \$128 $and$libresoc.v:121018$4765_Y - connect \$12 $not$libresoc.v:121019$4766_Y - connect \$14 $and$libresoc.v:121020$4767_Y - connect \$16 $not$libresoc.v:121021$4768_Y - connect \$18 $and$libresoc.v:121022$4769_Y - connect \$20 $and$libresoc.v:121023$4770_Y - connect \$24 $not$libresoc.v:121024$4771_Y - connect \$26 $and$libresoc.v:121025$4772_Y - connect \$23 $reduce_or$libresoc.v:121026$4773_Y - connect \$22 $not$libresoc.v:121027$4774_Y - connect \$2 $and$libresoc.v:121028$4775_Y - connect \$30 $and$libresoc.v:121029$4776_Y - connect \$32 $reduce_or$libresoc.v:121030$4777_Y - connect \$34 $reduce_or$libresoc.v:121031$4778_Y - connect \$36 $or$libresoc.v:121032$4779_Y - connect \$38 $not$libresoc.v:121033$4780_Y - connect \$40 $and$libresoc.v:121034$4781_Y - connect \$42 $and$libresoc.v:121035$4782_Y - connect \$44 $eq$libresoc.v:121036$4783_Y - connect \$46 $and$libresoc.v:121037$4784_Y - connect \$48 $eq$libresoc.v:121038$4785_Y - connect \$50 $and$libresoc.v:121039$4786_Y - connect \$52 $and$libresoc.v:121040$4787_Y - connect \$54 $and$libresoc.v:121041$4788_Y - connect \$56 $or$libresoc.v:121042$4789_Y - connect \$58 $or$libresoc.v:121043$4790_Y - connect \$5 $not$libresoc.v:121044$4791_Y - connect \$60 $or$libresoc.v:121045$4792_Y - connect \$62 $or$libresoc.v:121046$4793_Y - connect \$64 $and$libresoc.v:121047$4794_Y - connect \$66 $and$libresoc.v:121048$4795_Y - connect \$68 $or$libresoc.v:121049$4796_Y - connect \$70 $and$libresoc.v:121050$4797_Y - connect \$72 $and$libresoc.v:121051$4798_Y - connect \$74 $and$libresoc.v:121052$4799_Y - connect \$76 $and$libresoc.v:121053$4800_Y - connect \$78 $ternary$libresoc.v:121054$4801_Y - connect \$7 $or$libresoc.v:121055$4802_Y - connect \$80 $ternary$libresoc.v:121056$4803_Y - connect \$83 $ternary$libresoc.v:121057$4804_Y - connect \$86 $ternary$libresoc.v:121058$4805_Y - connect \$88 $ternary$libresoc.v:121059$4806_Y - connect \$4 $reduce_and$libresoc.v:121060$4807_Y - connect \$90 $ternary$libresoc.v:121061$4808_Y - connect \$92 $ternary$libresoc.v:121062$4809_Y - connect \$94 $and$libresoc.v:121063$4810_Y - connect \$96 $and$libresoc.v:121064$4811_Y - connect \$98 $and$libresoc.v:121065$4812_Y + assign $1\prev_wr_go$next[3:0]$5301 4'0000 + case + assign $1\prev_wr_go$next[3:0]$5301 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5300 + end + connect \$100 $not$libresoc.v:130651$5067_Y + connect \$102 $not$libresoc.v:130652$5068_Y + connect \$104 $and$libresoc.v:130653$5069_Y + connect \$106 $not$libresoc.v:130654$5070_Y + connect \$108 $and$libresoc.v:130655$5071_Y + connect \$10 $and$libresoc.v:130656$5072_Y + connect \$110 $and$libresoc.v:130657$5073_Y + connect \$112 $and$libresoc.v:130658$5074_Y + connect \$114 $and$libresoc.v:130659$5075_Y + connect \$116 $and$libresoc.v:130660$5076_Y + connect \$118 $and$libresoc.v:130661$5077_Y + connect \$120 $and$libresoc.v:130662$5078_Y + connect \$122 $and$libresoc.v:130663$5079_Y + connect \$124 $and$libresoc.v:130664$5080_Y + connect \$126 $and$libresoc.v:130665$5081_Y + connect \$128 $and$libresoc.v:130666$5082_Y + connect \$12 $not$libresoc.v:130667$5083_Y + connect \$14 $and$libresoc.v:130668$5084_Y + connect \$16 $not$libresoc.v:130669$5085_Y + connect \$18 $and$libresoc.v:130670$5086_Y + connect \$20 $and$libresoc.v:130671$5087_Y + connect \$24 $not$libresoc.v:130672$5088_Y + connect \$26 $and$libresoc.v:130673$5089_Y + connect \$23 $reduce_or$libresoc.v:130674$5090_Y + connect \$22 $not$libresoc.v:130675$5091_Y + connect \$2 $and$libresoc.v:130676$5092_Y + connect \$30 $and$libresoc.v:130677$5093_Y + connect \$32 $reduce_or$libresoc.v:130678$5094_Y + connect \$34 $reduce_or$libresoc.v:130679$5095_Y + connect \$36 $or$libresoc.v:130680$5096_Y + connect \$38 $not$libresoc.v:130681$5097_Y + connect \$40 $and$libresoc.v:130682$5098_Y + connect \$42 $and$libresoc.v:130683$5099_Y + connect \$44 $eq$libresoc.v:130684$5100_Y + connect \$46 $and$libresoc.v:130685$5101_Y + connect \$48 $eq$libresoc.v:130686$5102_Y + connect \$50 $and$libresoc.v:130687$5103_Y + connect \$52 $and$libresoc.v:130688$5104_Y + connect \$54 $and$libresoc.v:130689$5105_Y + connect \$56 $or$libresoc.v:130690$5106_Y + connect \$58 $or$libresoc.v:130691$5107_Y + connect \$5 $not$libresoc.v:130692$5108_Y + connect \$60 $or$libresoc.v:130693$5109_Y + connect \$62 $or$libresoc.v:130694$5110_Y + connect \$64 $and$libresoc.v:130695$5111_Y + connect \$66 $and$libresoc.v:130696$5112_Y + connect \$68 $or$libresoc.v:130697$5113_Y + connect \$70 $and$libresoc.v:130698$5114_Y + connect \$72 $and$libresoc.v:130699$5115_Y + connect \$74 $and$libresoc.v:130700$5116_Y + connect \$76 $and$libresoc.v:130701$5117_Y + connect \$78 $ternary$libresoc.v:130702$5118_Y + connect \$7 $or$libresoc.v:130703$5119_Y + connect \$80 $ternary$libresoc.v:130704$5120_Y + connect \$83 $ternary$libresoc.v:130705$5121_Y + connect \$86 $ternary$libresoc.v:130706$5122_Y + connect \$88 $ternary$libresoc.v:130707$5123_Y + connect \$4 $reduce_and$libresoc.v:130708$5124_Y + connect \$90 $ternary$libresoc.v:130709$5125_Y + connect \$92 $ternary$libresoc.v:130710$5126_Y + connect \$94 $and$libresoc.v:130711$5127_Y + connect \$96 $and$libresoc.v:130712$5128_Y + connect \$98 $and$libresoc.v:130713$5129_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 @@ -192364,7 +208066,7 @@ module \div0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:121599.1-121608.10" +attribute \src "libresoc.v:131247.1-131256.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" @@ -192378,37 +208080,37 @@ module \div_state_init connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end -attribute \src "libresoc.v:121612.1-121694.10" +attribute \src "libresoc.v:131260.1-131342.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next - attribute \src "libresoc.v:121613.7-121613.20" + attribute \src "libresoc.v:131261.7-131261.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121678.3-121689.6" + attribute \src "libresoc.v:131326.3-131337.6" wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:121666.3-121677.6" + attribute \src "libresoc.v:131314.3-131325.6" wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:121654.3-121665.6" + attribute \src "libresoc.v:131302.3-131313.6" wire width 128 $0\value[127:0] - attribute \src "libresoc.v:121678.3-121689.6" + attribute \src "libresoc.v:131326.3-131337.6" wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:121666.3-121677.6" + attribute \src "libresoc.v:131314.3-131325.6" wire width 7 $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:121654.3-121665.6" + attribute \src "libresoc.v:131302.3-131313.6" wire width 128 $1\value[127:0] - attribute \src "libresoc.v:121648.18-121648.106" - wire width 8 $add$libresoc.v:121648$5030_Y - attribute \src "libresoc.v:121649.18-121649.109" - wire $ge$libresoc.v:121649$5031_Y - attribute \src "libresoc.v:121653.17-121653.108" - wire $ge$libresoc.v:121653$5035_Y - attribute \src "libresoc.v:121652.17-121652.101" - wire $not$libresoc.v:121652$5034_Y - attribute \src "libresoc.v:121650.17-121650.101" - wire width 127 $sshl$libresoc.v:121650$5032_Y - attribute \src "libresoc.v:121651.17-121651.109" - wire width 129 $sub$libresoc.v:121651$5033_Y + attribute \src "libresoc.v:131296.18-131296.106" + wire width 8 $add$libresoc.v:131296$5347_Y + attribute \src "libresoc.v:131297.18-131297.109" + wire $ge$libresoc.v:131297$5348_Y + attribute \src "libresoc.v:131301.17-131301.108" + wire $ge$libresoc.v:131301$5352_Y + attribute \src "libresoc.v:131300.17-131300.101" + wire $not$libresoc.v:131300$5351_Y + attribute \src "libresoc.v:131298.17-131298.101" + wire width 127 $sshl$libresoc.v:131298$5349_Y + attribute \src "libresoc.v:131299.17-131299.109" + wire width 129 $sub$libresoc.v:131299$5350_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" @@ -192433,7 +208135,7 @@ module \div_state_next wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:121613.7-121613.15" + attribute \src "libresoc.v:131261.7-131261.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit @@ -192444,7 +208146,7 @@ module \div_state_next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:121648$5030 + cell $add $add$libresoc.v:131296$5347 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192452,10 +208154,10 @@ module \div_state_next parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 - connect \Y $add$libresoc.v:121648$5030_Y + connect \Y $add$libresoc.v:131296$5347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:121649$5031 + cell $ge $ge$libresoc.v:131297$5348 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192463,10 +208165,10 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:121649$5031_Y + connect \Y $ge$libresoc.v:131297$5348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:121653$5035 + cell $ge $ge$libresoc.v:131301$5352 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192474,18 +208176,18 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:121653$5035_Y + connect \Y $ge$libresoc.v:131301$5352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:121652$5034 + cell $not $not$libresoc.v:131300$5351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] - connect \Y $not$libresoc.v:121652$5034_Y + connect \Y $not$libresoc.v:131300$5351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:121650$5032 + cell $sshl $sshl$libresoc.v:131298$5349 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -192493,10 +208195,10 @@ module \div_state_next parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 - connect \Y $sshl$libresoc.v:121650$5032_Y + connect \Y $sshl$libresoc.v:131298$5349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:121651$5033 + cell $sub $sub$libresoc.v:131299$5350 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -192504,23 +208206,23 @@ module \div_state_next parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 - connect \Y $sub$libresoc.v:121651$5033_Y + connect \Y $sub$libresoc.v:131299$5350_Y end - attribute \src "libresoc.v:121613.7-121613.20" - process $proc$libresoc.v:121613$5039 + attribute \src "libresoc.v:131261.7-131261.20" + process $proc$libresoc.v:131261$5356 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121654.3-121665.6" - process $proc$libresoc.v:121654$5036 + attribute \src "libresoc.v:131302.3-131313.6" + process $proc$libresoc.v:131302$5353 assign { } { } assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:121655.5-121655.29" + attribute \src "libresoc.v:131303.5-131303.29" switch \initial - attribute \src "libresoc.v:121655.9-121655.17" + attribute \src "libresoc.v:131303.9-131303.17" case 1'1 case end @@ -192538,13 +208240,13 @@ module \div_state_next sync always update \value $0\value[127:0] end - attribute \src "libresoc.v:121666.3-121677.6" - process $proc$libresoc.v:121666$5037 + attribute \src "libresoc.v:131314.3-131325.6" + process $proc$libresoc.v:131314$5354 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:121667.5-121667.29" + attribute \src "libresoc.v:131315.5-131315.29" switch \initial - attribute \src "libresoc.v:121667.9-121667.17" + attribute \src "libresoc.v:131315.9-131315.17" case 1'1 case end @@ -192562,13 +208264,13 @@ module \div_state_next sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end - attribute \src "libresoc.v:121678.3-121689.6" - process $proc$libresoc.v:121678$5038 + attribute \src "libresoc.v:131326.3-131337.6" + process $proc$libresoc.v:131326$5355 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:121679.5-121679.29" + attribute \src "libresoc.v:131327.5-131327.29" switch \initial - attribute \src "libresoc.v:121679.9-121679.17" + attribute \src "libresoc.v:131327.9-131327.17" case 1'1 case end @@ -192586,18 +208288,18 @@ module \div_state_next sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end - connect \$11 $add$libresoc.v:121648$5030_Y - connect \$13 $ge$libresoc.v:121649$5031_Y - connect \$2 $sshl$libresoc.v:121650$5032_Y - connect \$4 $sub$libresoc.v:121651$5033_Y - connect \$6 $not$libresoc.v:121652$5034_Y - connect \$8 $ge$libresoc.v:121653$5035_Y + connect \$11 $add$libresoc.v:131296$5347_Y + connect \$13 $ge$libresoc.v:131297$5348_Y + connect \$2 $sshl$libresoc.v:131298$5349_Y + connect \$4 $sub$libresoc.v:131299$5350_Y + connect \$6 $not$libresoc.v:131300$5351_Y + connect \$8 $ge$libresoc.v:131301$5352_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end -attribute \src "libresoc.v:121698.1-121935.10" +attribute \src "libresoc.v:131346.1-131589.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" @@ -192610,9 +208312,9 @@ module \dummy wire width 64 input 13 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 27 \fast2$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 14 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \ra @@ -192627,35 +208329,39 @@ module \dummy attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \trap_op__cia$6 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 16 \trap_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 16 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -192734,6 +208440,7 @@ module \dummy attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -192810,6 +208517,7 @@ module \dummy attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 15 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -192839,114 +208547,114 @@ module \dummy connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:121939.1-122110.10" +attribute \src "libresoc.v:131593.1-131764.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast - attribute \src "libresoc.v:122034.3-122040.6" - wire width 3 $0$memwr$\memory$libresoc.v:122038$5048_ADDR[2:0]$5056 - attribute \src "libresoc.v:122034.3-122040.6" - wire width 64 $0$memwr$\memory$libresoc.v:122038$5048_DATA[63:0]$5057 - attribute \src "libresoc.v:122034.3-122040.6" - wire width 64 $0$memwr$\memory$libresoc.v:122038$5048_EN[63:0]$5058 - attribute \src "libresoc.v:122034.3-122040.6" - wire width 3 $0$memwr$\memory$libresoc.v:122039$5049_ADDR[2:0]$5059 - attribute \src "libresoc.v:122034.3-122040.6" - wire width 64 $0$memwr$\memory$libresoc.v:122039$5049_DATA[63:0]$5060 - attribute \src "libresoc.v:122034.3-122040.6" - wire width 64 $0$memwr$\memory$libresoc.v:122039$5049_EN[63:0]$5061 - attribute \src "libresoc.v:122034.3-122040.6" + attribute \src "libresoc.v:131688.3-131694.6" + wire width 3 $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 64 $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 64 $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 3 $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 64 $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 64 $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 + attribute \src "libresoc.v:131688.3-131694.6" wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:122034.3-122040.6" + attribute \src "libresoc.v:131688.3-131694.6" wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:122034.3-122040.6" + attribute \src "libresoc.v:131688.3-131694.6" wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:121940.7-121940.20" + attribute \src "libresoc.v:131594.7-131594.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122091.3-122100.6" + attribute \src "libresoc.v:131745.3-131754.6" wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:122063.3-122071.6" - wire $0\ren_delay$10$next[0:0]$5070 - attribute \src "libresoc.v:122016.3-122017.43" - wire $0\ren_delay$10[0:0]$5053 - attribute \src "libresoc.v:121991.7-121991.28" - wire $0\ren_delay$10[0:0]$5090 - attribute \src "libresoc.v:122082.3-122090.6" - wire $0\ren_delay$11$next[0:0]$5074 - attribute \src "libresoc.v:122014.3-122015.43" - wire $0\ren_delay$11[0:0]$5051 - attribute \src "libresoc.v:121995.7-121995.28" - wire $0\ren_delay$11[0:0]$5092 - attribute \src "libresoc.v:122044.3-122052.6" - wire $0\ren_delay$next[0:0]$5066 - attribute \src "libresoc.v:122018.3-122019.35" + attribute \src "libresoc.v:131717.3-131725.6" + wire $0\ren_delay$10$next[0:0]$5387 + attribute \src "libresoc.v:131670.3-131671.43" + wire $0\ren_delay$10[0:0]$5370 + attribute \src "libresoc.v:131645.7-131645.28" + wire $0\ren_delay$10[0:0]$5407 + attribute \src "libresoc.v:131736.3-131744.6" + wire $0\ren_delay$11$next[0:0]$5391 + attribute \src "libresoc.v:131668.3-131669.43" + wire $0\ren_delay$11[0:0]$5368 + attribute \src "libresoc.v:131649.7-131649.28" + wire $0\ren_delay$11[0:0]$5409 + attribute \src "libresoc.v:131698.3-131706.6" + wire $0\ren_delay$next[0:0]$5383 + attribute \src "libresoc.v:131672.3-131673.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:122053.3-122062.6" + attribute \src "libresoc.v:131707.3-131716.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:122072.3-122081.6" + attribute \src "libresoc.v:131726.3-131735.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:122091.3-122100.6" + attribute \src "libresoc.v:131745.3-131754.6" wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:122063.3-122071.6" - wire $1\ren_delay$10$next[0:0]$5071 - attribute \src "libresoc.v:122082.3-122090.6" - wire $1\ren_delay$11$next[0:0]$5075 - attribute \src "libresoc.v:122044.3-122052.6" - wire $1\ren_delay$next[0:0]$5067 - attribute \src "libresoc.v:121989.7-121989.23" + attribute \src "libresoc.v:131717.3-131725.6" + wire $1\ren_delay$10$next[0:0]$5388 + attribute \src "libresoc.v:131736.3-131744.6" + wire $1\ren_delay$11$next[0:0]$5392 + attribute \src "libresoc.v:131698.3-131706.6" + wire $1\ren_delay$next[0:0]$5384 + attribute \src "libresoc.v:131643.7-131643.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:122053.3-122062.6" + attribute \src "libresoc.v:131707.3-131716.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:122072.3-122081.6" + attribute \src "libresoc.v:131726.3-131735.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:122041.26-122041.32" - wire width 64 $memrd$\memory$libresoc.v:122041$5062_DATA - attribute \src "libresoc.v:122042.30-122042.36" - wire width 64 $memrd$\memory$libresoc.v:122042$5063_DATA - attribute \src "libresoc.v:122043.30-122043.36" - wire width 64 $memrd$\memory$libresoc.v:122043$5064_DATA + attribute \src "libresoc.v:131695.26-131695.32" + wire width 64 $memrd$\memory$libresoc.v:131695$5379_DATA + attribute \src "libresoc.v:131696.30-131696.36" + wire width 64 $memrd$\memory$libresoc.v:131696$5380_DATA + attribute \src "libresoc.v:131697.30-131697.36" + wire width 64 $memrd$\memory$libresoc.v:131697$5381_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:122038$5048_ADDR + wire width 3 $memwr$\memory$libresoc.v:131692$5365_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:122038$5048_DATA + wire width 64 $memwr$\memory$libresoc.v:131692$5365_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:122038$5048_EN + wire width 64 $memwr$\memory$libresoc.v:131692$5365_EN attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:122039$5049_ADDR + wire width 3 $memwr$\memory$libresoc.v:131693$5366_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:122039$5049_DATA + wire width 64 $memwr$\memory$libresoc.v:131693$5366_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:122039$5049_EN - attribute \src "libresoc.v:122031.13-122031.16" + wire width 64 $memwr$\memory$libresoc.v:131693$5366_EN + attribute \src "libresoc.v:131685.13-131685.16" wire width 3 \_0_ - attribute \src "libresoc.v:122032.13-122032.16" + attribute \src "libresoc.v:131686.13-131686.16" wire width 3 \_1_ - attribute \src "libresoc.v:122033.13-122033.16" + attribute \src "libresoc.v:131687.13-131687.16" wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 16 \dest1__wen - attribute \src "libresoc.v:121940.7-121940.15" + attribute \src "libresoc.v:131594.7-131594.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 5 \issue__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 4 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 3 \memory_r_addr @@ -192984,102 +208692,102 @@ module \fast wire \ren_delay$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 9 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 8 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 12 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 11 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src2__ren - attribute \src "libresoc.v:122020.14-122020.20" + attribute \src "libresoc.v:131674.14-131674.20" memory width 64 size 8 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5077 + cell $meminit $meminit$\memory$libresoc.v:0$5394 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5077 + parameter \PRIORITY 5394 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5078 + cell $meminit $meminit$\memory$libresoc.v:0$5395 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5078 + parameter \PRIORITY 5395 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5079 + cell $meminit $meminit$\memory$libresoc.v:0$5396 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5079 + parameter \PRIORITY 5396 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5080 + cell $meminit $meminit$\memory$libresoc.v:0$5397 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5080 + parameter \PRIORITY 5397 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5081 + cell $meminit $meminit$\memory$libresoc.v:0$5398 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5081 + parameter \PRIORITY 5398 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5082 + cell $meminit $meminit$\memory$libresoc.v:0$5399 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5082 + parameter \PRIORITY 5399 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5083 + cell $meminit $meminit$\memory$libresoc.v:0$5400 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5083 + parameter \PRIORITY 5400 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5084 + cell $meminit $meminit$\memory$libresoc.v:0$5401 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5084 + parameter \PRIORITY 5401 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:122041.26-122041.32" - cell $memrd $memrd$\memory$libresoc.v:122041$5062 + attribute \src "libresoc.v:131695.26-131695.32" + cell $memrd $memrd$\memory$libresoc.v:131695$5379 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -193088,11 +208796,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:122041$5062_DATA + connect \DATA $memrd$\memory$libresoc.v:131695$5379_DATA connect \EN 1'x end - attribute \src "libresoc.v:122042.30-122042.36" - cell $memrd $memrd$\memory$libresoc.v:122042$5063 + attribute \src "libresoc.v:131696.30-131696.36" + cell $memrd $memrd$\memory$libresoc.v:131696$5380 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -193101,11 +208809,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:122042$5063_DATA + connect \DATA $memrd$\memory$libresoc.v:131696$5380_DATA connect \EN 1'x end - attribute \src "libresoc.v:122043.30-122043.36" - cell $memrd $memrd$\memory$libresoc.v:122043$5064 + attribute \src "libresoc.v:131697.30-131697.36" + cell $memrd $memrd$\memory$libresoc.v:131697$5381 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -193114,95 +208822,95 @@ module \fast parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:122043$5064_DATA + connect \DATA $memrd$\memory$libresoc.v:131697$5381_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5085 + cell $memwr $memwr$\memory$libresoc.v:0$5402 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5085 + parameter \PRIORITY 5402 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:122038$5048_ADDR + connect \ADDR $memwr$\memory$libresoc.v:131692$5365_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:122038$5048_DATA - connect \EN $memwr$\memory$libresoc.v:122038$5048_EN + connect \DATA $memwr$\memory$libresoc.v:131692$5365_DATA + connect \EN $memwr$\memory$libresoc.v:131692$5365_EN end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5086 + cell $memwr $memwr$\memory$libresoc.v:0$5403 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5086 + parameter \PRIORITY 5403 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:122039$5049_ADDR + connect \ADDR $memwr$\memory$libresoc.v:131693$5366_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:122039$5049_DATA - connect \EN $memwr$\memory$libresoc.v:122039$5049_EN + connect \DATA $memwr$\memory$libresoc.v:131693$5366_DATA + connect \EN $memwr$\memory$libresoc.v:131693$5366_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5093 + process $proc$libresoc.v:0$5410 sync always sync init end - attribute \src "libresoc.v:121940.7-121940.20" - process $proc$libresoc.v:121940$5087 + attribute \src "libresoc.v:131594.7-131594.20" + process $proc$libresoc.v:131594$5404 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121989.7-121989.23" - process $proc$libresoc.v:121989$5088 + attribute \src "libresoc.v:131643.7-131643.23" + process $proc$libresoc.v:131643$5405 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:121991.7-121991.28" - process $proc$libresoc.v:121991$5089 + attribute \src "libresoc.v:131645.7-131645.28" + process $proc$libresoc.v:131645$5406 assign { } { } - assign $0\ren_delay$10[0:0]$5090 1'0 + assign $0\ren_delay$10[0:0]$5407 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5090 + update \ren_delay$10 $0\ren_delay$10[0:0]$5407 end - attribute \src "libresoc.v:121995.7-121995.28" - process $proc$libresoc.v:121995$5091 + attribute \src "libresoc.v:131649.7-131649.28" + process $proc$libresoc.v:131649$5408 assign { } { } - assign $0\ren_delay$11[0:0]$5092 1'0 + assign $0\ren_delay$11[0:0]$5409 1'0 sync always sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5092 + update \ren_delay$11 $0\ren_delay$11[0:0]$5409 end - attribute \src "libresoc.v:122014.3-122015.43" - process $proc$libresoc.v:122014$5050 + attribute \src "libresoc.v:131668.3-131669.43" + process $proc$libresoc.v:131668$5367 assign { } { } - assign $0\ren_delay$11[0:0]$5051 \ren_delay$11$next + assign $0\ren_delay$11[0:0]$5368 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5051 + update \ren_delay$11 $0\ren_delay$11[0:0]$5368 end - attribute \src "libresoc.v:122016.3-122017.43" - process $proc$libresoc.v:122016$5052 + attribute \src "libresoc.v:131670.3-131671.43" + process $proc$libresoc.v:131670$5369 assign { } { } - assign $0\ren_delay$10[0:0]$5053 \ren_delay$10$next + assign $0\ren_delay$10[0:0]$5370 \ren_delay$10$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5053 + update \ren_delay$10 $0\ren_delay$10[0:0]$5370 end - attribute \src "libresoc.v:122018.3-122019.35" - process $proc$libresoc.v:122018$5054 + attribute \src "libresoc.v:131672.3-131673.35" + process $proc$libresoc.v:131672$5371 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:122034.3-122040.6" - process $proc$libresoc.v:122034$5055 + attribute \src "libresoc.v:131688.3-131694.6" + process $proc$libresoc.v:131688$5372 assign { } { } assign { } { } assign { } { } @@ -193212,52 +208920,52 @@ module \fast assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:122039$5049_ADDR[2:0]$5059 3'xxx - assign $0$memwr$\memory$libresoc.v:122039$5049_DATA[63:0]$5060 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:122039$5049_EN[63:0]$5061 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:122038$5048_ADDR[2:0]$5056 3'xxx - assign $0$memwr$\memory$libresoc.v:122038$5048_DATA[63:0]$5057 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:122038$5048_EN[63:0]$5058 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 3'xxx + assign $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 3'xxx + assign $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[2:0] \src1__addr assign $0\_1_[2:0] \src2__addr assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:122038.5-122038.62" + attribute \src "libresoc.v:131692.5-131692.62" switch \issue__wen - attribute \src "libresoc.v:122038.9-122038.19" + attribute \src "libresoc.v:131692.9-131692.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:122038$5048_ADDR[2:0]$5056 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:122038$5048_DATA[63:0]$5057 \issue__data_i - assign $0$memwr$\memory$libresoc.v:122038$5048_EN[63:0]$5058 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 \issue__data_i + assign $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 64'1111111111111111111111111111111111111111111111111111111111111111 case end - attribute \src "libresoc.v:122039.5-122039.58" + attribute \src "libresoc.v:131693.5-131693.58" switch \dest1__wen - attribute \src "libresoc.v:122039.9-122039.19" + attribute \src "libresoc.v:131693.9-131693.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:122039$5049_ADDR[2:0]$5059 \dest1__addr - assign $0$memwr$\memory$libresoc.v:122039$5049_DATA[63:0]$5060 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:122039$5049_EN[63:0]$5061 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 \dest1__addr + assign $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:122038$5048_ADDR $0$memwr$\memory$libresoc.v:122038$5048_ADDR[2:0]$5056 - update $memwr$\memory$libresoc.v:122038$5048_DATA $0$memwr$\memory$libresoc.v:122038$5048_DATA[63:0]$5057 - update $memwr$\memory$libresoc.v:122038$5048_EN $0$memwr$\memory$libresoc.v:122038$5048_EN[63:0]$5058 - update $memwr$\memory$libresoc.v:122039$5049_ADDR $0$memwr$\memory$libresoc.v:122039$5049_ADDR[2:0]$5059 - update $memwr$\memory$libresoc.v:122039$5049_DATA $0$memwr$\memory$libresoc.v:122039$5049_DATA[63:0]$5060 - update $memwr$\memory$libresoc.v:122039$5049_EN $0$memwr$\memory$libresoc.v:122039$5049_EN[63:0]$5061 + update $memwr$\memory$libresoc.v:131692$5365_ADDR $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 + update $memwr$\memory$libresoc.v:131692$5365_DATA $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 + update $memwr$\memory$libresoc.v:131692$5365_EN $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 + update $memwr$\memory$libresoc.v:131693$5366_ADDR $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 + update $memwr$\memory$libresoc.v:131693$5366_DATA $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 + update $memwr$\memory$libresoc.v:131693$5366_EN $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 end - attribute \src "libresoc.v:122044.3-122052.6" - process $proc$libresoc.v:122044$5065 + attribute \src "libresoc.v:131698.3-131706.6" + process $proc$libresoc.v:131698$5382 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5066 $1\ren_delay$next[0:0]$5067 - attribute \src "libresoc.v:122045.5-122045.29" + assign $0\ren_delay$next[0:0]$5383 $1\ren_delay$next[0:0]$5384 + attribute \src "libresoc.v:131699.5-131699.29" switch \initial - attribute \src "libresoc.v:122045.9-122045.17" + attribute \src "libresoc.v:131699.9-131699.17" case 1'1 case end @@ -193266,21 +208974,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5067 1'0 + assign $1\ren_delay$next[0:0]$5384 1'0 case - assign $1\ren_delay$next[0:0]$5067 \src1__ren + assign $1\ren_delay$next[0:0]$5384 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5066 + update \ren_delay$next $0\ren_delay$next[0:0]$5383 end - attribute \src "libresoc.v:122053.3-122062.6" - process $proc$libresoc.v:122053$5068 + attribute \src "libresoc.v:131707.3-131716.6" + process $proc$libresoc.v:131707$5385 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:122054.5-122054.29" + attribute \src "libresoc.v:131708.5-131708.29" switch \initial - attribute \src "libresoc.v:122054.9-122054.17" + attribute \src "libresoc.v:131708.9-131708.17" case 1'1 case end @@ -193296,14 +209004,14 @@ module \fast sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:122063.3-122071.6" - process $proc$libresoc.v:122063$5069 + attribute \src "libresoc.v:131717.3-131725.6" + process $proc$libresoc.v:131717$5386 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5070 $1\ren_delay$10$next[0:0]$5071 - attribute \src "libresoc.v:122064.5-122064.29" + assign $0\ren_delay$10$next[0:0]$5387 $1\ren_delay$10$next[0:0]$5388 + attribute \src "libresoc.v:131718.5-131718.29" switch \initial - attribute \src "libresoc.v:122064.9-122064.17" + attribute \src "libresoc.v:131718.9-131718.17" case 1'1 case end @@ -193312,21 +209020,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5071 1'0 + assign $1\ren_delay$10$next[0:0]$5388 1'0 case - assign $1\ren_delay$10$next[0:0]$5071 \src2__ren + assign $1\ren_delay$10$next[0:0]$5388 \src2__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5070 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5387 end - attribute \src "libresoc.v:122072.3-122081.6" - process $proc$libresoc.v:122072$5072 + attribute \src "libresoc.v:131726.3-131735.6" + process $proc$libresoc.v:131726$5389 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:122073.5-122073.29" + attribute \src "libresoc.v:131727.5-131727.29" switch \initial - attribute \src "libresoc.v:122073.9-122073.17" + attribute \src "libresoc.v:131727.9-131727.17" case 1'1 case end @@ -193342,14 +209050,14 @@ module \fast sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:122082.3-122090.6" - process $proc$libresoc.v:122082$5073 + attribute \src "libresoc.v:131736.3-131744.6" + process $proc$libresoc.v:131736$5390 assign { } { } assign { } { } - assign $0\ren_delay$11$next[0:0]$5074 $1\ren_delay$11$next[0:0]$5075 - attribute \src "libresoc.v:122083.5-122083.29" + assign $0\ren_delay$11$next[0:0]$5391 $1\ren_delay$11$next[0:0]$5392 + attribute \src "libresoc.v:131737.5-131737.29" switch \initial - attribute \src "libresoc.v:122083.9-122083.17" + attribute \src "libresoc.v:131737.9-131737.17" case 1'1 case end @@ -193358,21 +209066,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[0:0]$5075 1'0 + assign $1\ren_delay$11$next[0:0]$5392 1'0 case - assign $1\ren_delay$11$next[0:0]$5075 \issue__ren + assign $1\ren_delay$11$next[0:0]$5392 \issue__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5074 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5391 end - attribute \src "libresoc.v:122091.3-122100.6" - process $proc$libresoc.v:122091$5076 + attribute \src "libresoc.v:131745.3-131754.6" + process $proc$libresoc.v:131745$5393 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:122092.5-122092.29" + attribute \src "libresoc.v:131746.5-131746.29" switch \initial - attribute \src "libresoc.v:122092.9-122092.17" + attribute \src "libresoc.v:131746.9-131746.17" case 1'1 case end @@ -193388,9 +209096,9 @@ module \fast sync always update \issue__data_o $0\issue__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:122041$5062_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:122042$5063_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:122043$5064_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:131695$5379_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:131696$5380_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:131697$5381_DATA connect \memory_w_data$9 \issue__data_i connect \memory_w_en$7 \issue__wen connect \memory_w_addr$8 \issue__addr$1 @@ -193401,14 +209109,14 @@ module \fast connect \memory_r_addr$3 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:122114.1-124034.10" +attribute \src "libresoc.v:131768.1-133718.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 257 \cr_a_ok @@ -193719,20 +209427,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 22 \oper_i_alu_alu0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 7 \oper_i_alu_alu0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -193819,6 +209529,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -193846,20 +209557,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 33 \oper_i_alu_branch0__cia attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 35 \oper_i_alu_branch0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 35 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 37 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -193940,6 +209653,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 34 \oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -193947,20 +209661,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 39 \oper_i_alu_branch0__lk attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 28 \oper_i_alu_cr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 28 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 29 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" @@ -194037,25 +209753,28 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 27 \oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 100 \oper_i_alu_div0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 85 \oper_i_alu_div0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 85 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 86 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194142,6 +209861,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 84 \oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194169,20 +209889,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 72 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 57 \oper_i_alu_logical0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 57 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 58 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194269,6 +209991,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 56 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194294,20 +210017,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 65 \oper_i_alu_logical0__zero_a attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 106 \oper_i_alu_mul0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 106 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 107 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194388,6 +210113,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 105 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194405,20 +210131,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 113 \oper_i_alu_mul0__write_cr0 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 121 \oper_i_alu_shift_rot0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 121 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194507,6 +210235,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194530,20 +210259,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 128 \oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 78 \oper_i_alu_spr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 78 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 79 \oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" @@ -194620,6 +210351,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 77 \oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194627,20 +210359,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 48 \oper_i_alu_trap0__cia attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 45 \oper_i_alu_trap0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 45 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 46 \oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" @@ -194717,6 +210451,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 44 \oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194734,20 +210469,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 151 \oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 141 \oper_i_ldst_ldst0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 141 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 142 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194828,6 +210565,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 140 \oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -194958,7 +210696,7 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 - attribute \src "libresoc.v:123666.8-123708.4" + attribute \src "libresoc.v:133350.8-133392.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195003,7 +210741,7 @@ module \fus connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:123709.11-123736.4" + attribute \src "libresoc.v:133393.11-133420.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195033,7 +210771,7 @@ module \fus connect \src3_i \src3_i$71 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123737.7-123762.4" + attribute \src "libresoc.v:133421.7-133446.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195061,7 +210799,7 @@ module \fus connect \src6_i \src6_i$73 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123763.8-123802.4" + attribute \src "libresoc.v:133447.8-133486.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195103,7 +210841,7 @@ module \fus connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123803.9-123857.4" + attribute \src "libresoc.v:133487.9-133541.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195160,7 +210898,7 @@ module \fus connect \src3_i \src3_i$59 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123858.12-123893.4" + attribute \src "libresoc.v:133542.12-133577.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195198,7 +210936,7 @@ module \fus connect \src3_i \src3_i$61 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123894.8-123927.4" + attribute \src "libresoc.v:133578.8-133611.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195234,7 +210972,7 @@ module \fus connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123928.13-123966.4" + attribute \src "libresoc.v:133612.13-133650.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195275,7 +211013,7 @@ module \fus connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123967.8-123999.4" + attribute \src "libresoc.v:133651.8-133683.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195310,7 +211048,7 @@ module \fus connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 - attribute \src "libresoc.v:124000.9-124033.4" + attribute \src "libresoc.v:133684.9-133717.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -195346,75 +211084,75 @@ module \fus connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:124038.1-124096.10" +attribute \src "libresoc.v:133722.1-133780.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l - attribute \src "libresoc.v:124039.7-124039.20" + attribute \src "libresoc.v:133723.7-133723.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124084.3-124092.6" - wire $0\q_int$next[0:0]$5104 - attribute \src "libresoc.v:124082.3-124083.27" + attribute \src "libresoc.v:133768.3-133776.6" + wire $0\q_int$next[0:0]$5421 + attribute \src "libresoc.v:133766.3-133767.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:124084.3-124092.6" - wire $1\q_int$next[0:0]$5105 - attribute \src "libresoc.v:124063.7-124063.19" + attribute \src "libresoc.v:133768.3-133776.6" + wire $1\q_int$next[0:0]$5422 + attribute \src "libresoc.v:133747.7-133747.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:124074.17-124074.96" - wire $and$libresoc.v:124074$5094_Y - attribute \src "libresoc.v:124079.17-124079.96" - wire $and$libresoc.v:124079$5099_Y - attribute \src "libresoc.v:124076.18-124076.95" - wire $not$libresoc.v:124076$5096_Y - attribute \src "libresoc.v:124078.17-124078.94" - wire $not$libresoc.v:124078$5098_Y - attribute \src "libresoc.v:124081.17-124081.94" - wire $not$libresoc.v:124081$5101_Y - attribute \src "libresoc.v:124075.18-124075.100" - wire $or$libresoc.v:124075$5095_Y - attribute \src "libresoc.v:124077.18-124077.101" - wire $or$libresoc.v:124077$5097_Y - attribute \src "libresoc.v:124080.17-124080.99" - wire $or$libresoc.v:124080$5100_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:133758.17-133758.96" + wire $and$libresoc.v:133758$5411_Y + attribute \src "libresoc.v:133763.17-133763.96" + wire $and$libresoc.v:133763$5416_Y + attribute \src "libresoc.v:133760.18-133760.95" + wire $not$libresoc.v:133760$5413_Y + attribute \src "libresoc.v:133762.17-133762.94" + wire $not$libresoc.v:133762$5415_Y + attribute \src "libresoc.v:133765.17-133765.94" + wire $not$libresoc.v:133765$5418_Y + attribute \src "libresoc.v:133759.18-133759.100" + wire $or$libresoc.v:133759$5412_Y + attribute \src "libresoc.v:133761.18-133761.101" + wire $or$libresoc.v:133761$5414_Y + attribute \src "libresoc.v:133764.17-133764.99" + wire $or$libresoc.v:133764$5417_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:124039.7-124039.15" + attribute \src "libresoc.v:133723.7-133723.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:124074$5094 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:133758$5411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195422,10 +211160,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:124074$5094_Y + connect \Y $and$libresoc.v:133758$5411_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:124079$5099 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:133763$5416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195433,34 +211171,34 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:124079$5099_Y + connect \Y $and$libresoc.v:133763$5416_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:124076$5096 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:133760$5413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l - connect \Y $not$libresoc.v:124076$5096_Y + connect \Y $not$libresoc.v:133760$5413_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:124078$5098 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:133762$5415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:124078$5098_Y + connect \Y $not$libresoc.v:133762$5415_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:124081$5101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:133765$5418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:124081$5101_Y + connect \Y $not$libresoc.v:133765$5418_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:124075$5095 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:133759$5412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195468,10 +211206,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l - connect \Y $or$libresoc.v:124075$5095_Y + connect \Y $or$libresoc.v:133759$5412_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:124077$5097 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:133761$5414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195479,10 +211217,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int - connect \Y $or$libresoc.v:124077$5097_Y + connect \Y $or$libresoc.v:133761$5414_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:124080$5100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:133764$5417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195490,39 +211228,39 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l - connect \Y $or$libresoc.v:124080$5100_Y + connect \Y $or$libresoc.v:133764$5417_Y end - attribute \src "libresoc.v:124039.7-124039.20" - process $proc$libresoc.v:124039$5106 + attribute \src "libresoc.v:133723.7-133723.20" + process $proc$libresoc.v:133723$5423 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124063.7-124063.19" - process $proc$libresoc.v:124063$5107 + attribute \src "libresoc.v:133747.7-133747.19" + process $proc$libresoc.v:133747$5424 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:124082.3-124083.27" - process $proc$libresoc.v:124082$5102 + attribute \src "libresoc.v:133766.3-133767.27" + process $proc$libresoc.v:133766$5419 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:124084.3-124092.6" - process $proc$libresoc.v:124084$5103 + attribute \src "libresoc.v:133768.3-133776.6" + process $proc$libresoc.v:133768$5420 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5104 $1\q_int$next[0:0]$5105 - attribute \src "libresoc.v:124085.5-124085.29" + assign $0\q_int$next[0:0]$5421 $1\q_int$next[0:0]$5422 + attribute \src "libresoc.v:133769.5-133769.29" switch \initial - attribute \src "libresoc.v:124085.9-124085.17" + attribute \src "libresoc.v:133769.9-133769.17" case 1'1 case end @@ -195531,192 +211269,192 @@ module \idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5105 1'0 + assign $1\q_int$next[0:0]$5422 1'0 case - assign $1\q_int$next[0:0]$5105 \$5 + assign $1\q_int$next[0:0]$5422 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5104 + update \q_int$next $0\q_int$next[0:0]$5421 end - connect \$9 $and$libresoc.v:124074$5094_Y - connect \$11 $or$libresoc.v:124075$5095_Y - connect \$13 $not$libresoc.v:124076$5096_Y - connect \$15 $or$libresoc.v:124077$5097_Y - connect \$1 $not$libresoc.v:124078$5098_Y - connect \$3 $and$libresoc.v:124079$5099_Y - connect \$5 $or$libresoc.v:124080$5100_Y - connect \$7 $not$libresoc.v:124081$5101_Y + connect \$9 $and$libresoc.v:133758$5411_Y + connect \$11 $or$libresoc.v:133759$5412_Y + connect \$13 $not$libresoc.v:133760$5413_Y + connect \$15 $or$libresoc.v:133761$5414_Y + connect \$1 $not$libresoc.v:133762$5415_Y + connect \$3 $and$libresoc.v:133763$5416_Y + connect \$5 $or$libresoc.v:133764$5417_Y + connect \$7 $not$libresoc.v:133765$5418_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end -attribute \src "libresoc.v:124100.1-124479.10" +attribute \src "libresoc.v:133784.1-134163.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem - attribute \src "libresoc.v:124431.3-124440.6" + attribute \src "libresoc.v:134115.3-134124.6" wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:124411.3-124430.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5176 - attribute \src "libresoc.v:124242.3-124243.39" + attribute \src "libresoc.v:134095.3-134114.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5493 + attribute \src "libresoc.v:133926.3-133927.39" wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:124441.3-124458.6" + attribute \src "libresoc.v:134125.3-134142.6" wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:124388.3-124410.6" - wire $0\f_fetch_err_o$next[0:0]$5171 - attribute \src "libresoc.v:124244.3-124245.43" + attribute \src "libresoc.v:134072.3-134094.6" + wire $0\f_fetch_err_o$next[0:0]$5488 + attribute \src "libresoc.v:133928.3-133929.43" wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:124459.3-124476.6" + attribute \src "libresoc.v:134143.3-134160.6" wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:124365.3-124387.6" - wire width 45 $0\ibus__adr$next[44:0]$5166 - attribute \src "libresoc.v:124246.3-124247.35" + attribute \src "libresoc.v:134049.3-134071.6" + wire width 45 $0\ibus__adr$next[44:0]$5483 + attribute \src "libresoc.v:133930.3-133931.35" wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:124256.3-124283.6" - wire $0\ibus__cyc$next[0:0]$5142 - attribute \src "libresoc.v:124254.3-124255.35" + attribute \src "libresoc.v:133940.3-133967.6" + wire $0\ibus__cyc$next[0:0]$5459 + attribute \src "libresoc.v:133938.3-133939.35" wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:124312.3-124339.6" - wire width 8 $0\ibus__sel$next[7:0]$5154 - attribute \src "libresoc.v:124250.3-124251.35" + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $0\ibus__sel$next[7:0]$5471 + attribute \src "libresoc.v:133934.3-133935.35" wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:124284.3-124311.6" - wire $0\ibus__stb$next[0:0]$5148 - attribute \src "libresoc.v:124252.3-124253.35" + attribute \src "libresoc.v:133968.3-133995.6" + wire $0\ibus__stb$next[0:0]$5465 + attribute \src "libresoc.v:133936.3-133937.35" wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:124340.3-124364.6" - wire width 64 $0\ibus_rdata$next[63:0]$5160 - attribute \src "libresoc.v:124248.3-124249.37" + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $0\ibus_rdata$next[63:0]$5477 + attribute \src "libresoc.v:133932.3-133933.37" wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:124101.7-124101.20" + attribute \src "libresoc.v:133785.7-133785.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124431.3-124440.6" + attribute \src "libresoc.v:134115.3-134124.6" wire $1\a_busy_o[0:0] - attribute \src "libresoc.v:124411.3-124430.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5177 - attribute \src "libresoc.v:124165.14-124165.44" + attribute \src "libresoc.v:134095.3-134114.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5494 + attribute \src "libresoc.v:133849.14-133849.44" wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:124441.3-124458.6" + attribute \src "libresoc.v:134125.3-134142.6" wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:124388.3-124410.6" - wire $1\f_fetch_err_o$next[0:0]$5172 - attribute \src "libresoc.v:124172.7-124172.27" + attribute \src "libresoc.v:134072.3-134094.6" + wire $1\f_fetch_err_o$next[0:0]$5489 + attribute \src "libresoc.v:133856.7-133856.27" wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:124459.3-124476.6" + attribute \src "libresoc.v:134143.3-134160.6" wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:124365.3-124387.6" - wire width 45 $1\ibus__adr$next[44:0]$5167 - attribute \src "libresoc.v:124186.14-124186.42" + attribute \src "libresoc.v:134049.3-134071.6" + wire width 45 $1\ibus__adr$next[44:0]$5484 + attribute \src "libresoc.v:133870.14-133870.42" wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:124256.3-124283.6" - wire $1\ibus__cyc$next[0:0]$5143 - attribute \src "libresoc.v:124191.7-124191.23" + attribute \src "libresoc.v:133940.3-133967.6" + wire $1\ibus__cyc$next[0:0]$5460 + attribute \src "libresoc.v:133875.7-133875.23" wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:124312.3-124339.6" - wire width 8 $1\ibus__sel$next[7:0]$5155 - attribute \src "libresoc.v:124200.13-124200.30" + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $1\ibus__sel$next[7:0]$5472 + attribute \src "libresoc.v:133884.13-133884.30" wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:124284.3-124311.6" - wire $1\ibus__stb$next[0:0]$5149 - attribute \src "libresoc.v:124205.7-124205.23" + attribute \src "libresoc.v:133968.3-133995.6" + wire $1\ibus__stb$next[0:0]$5466 + attribute \src "libresoc.v:133889.7-133889.23" wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:124340.3-124364.6" - wire width 64 $1\ibus_rdata$next[63:0]$5161 - attribute \src "libresoc.v:124209.14-124209.47" + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $1\ibus_rdata$next[63:0]$5478 + attribute \src "libresoc.v:133893.14-133893.47" wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:124411.3-124430.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5178 - attribute \src "libresoc.v:124441.3-124458.6" + attribute \src "libresoc.v:134095.3-134114.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5495 + attribute \src "libresoc.v:134125.3-134142.6" wire $2\f_busy_o[0:0] - attribute \src "libresoc.v:124388.3-124410.6" - wire $2\f_fetch_err_o$next[0:0]$5173 - attribute \src "libresoc.v:124459.3-124476.6" + attribute \src "libresoc.v:134072.3-134094.6" + wire $2\f_fetch_err_o$next[0:0]$5490 + attribute \src "libresoc.v:134143.3-134160.6" wire width 64 $2\f_instr_o[63:0] - attribute \src "libresoc.v:124365.3-124387.6" - wire width 45 $2\ibus__adr$next[44:0]$5168 - attribute \src "libresoc.v:124256.3-124283.6" - wire $2\ibus__cyc$next[0:0]$5144 - attribute \src "libresoc.v:124312.3-124339.6" - wire width 8 $2\ibus__sel$next[7:0]$5156 - attribute \src "libresoc.v:124284.3-124311.6" - wire $2\ibus__stb$next[0:0]$5150 - attribute \src "libresoc.v:124340.3-124364.6" - wire width 64 $2\ibus_rdata$next[63:0]$5162 - attribute \src "libresoc.v:124411.3-124430.6" - wire width 45 $3\f_badaddr_o$next[44:0]$5179 - attribute \src "libresoc.v:124388.3-124410.6" - wire $3\f_fetch_err_o$next[0:0]$5174 - attribute \src "libresoc.v:124365.3-124387.6" - wire width 45 $3\ibus__adr$next[44:0]$5169 - attribute \src "libresoc.v:124256.3-124283.6" - wire $3\ibus__cyc$next[0:0]$5145 - attribute \src "libresoc.v:124312.3-124339.6" - wire width 8 $3\ibus__sel$next[7:0]$5157 - attribute \src "libresoc.v:124284.3-124311.6" - wire $3\ibus__stb$next[0:0]$5151 - attribute \src "libresoc.v:124340.3-124364.6" - wire width 64 $3\ibus_rdata$next[63:0]$5163 - attribute \src "libresoc.v:124256.3-124283.6" - wire $4\ibus__cyc$next[0:0]$5146 - attribute \src "libresoc.v:124312.3-124339.6" - wire width 8 $4\ibus__sel$next[7:0]$5158 - attribute \src "libresoc.v:124284.3-124311.6" - wire $4\ibus__stb$next[0:0]$5152 - attribute \src "libresoc.v:124340.3-124364.6" - wire width 64 $4\ibus_rdata$next[63:0]$5164 - attribute \src "libresoc.v:124218.18-124218.110" - wire $and$libresoc.v:124218$5110_Y - attribute \src "libresoc.v:124224.18-124224.110" - wire $and$libresoc.v:124224$5116_Y - attribute \src "libresoc.v:124229.18-124229.110" - wire $and$libresoc.v:124229$5121_Y - attribute \src "libresoc.v:124232.17-124232.108" - wire $and$libresoc.v:124232$5124_Y - attribute \src "libresoc.v:124235.18-124235.110" - wire $and$libresoc.v:124235$5127_Y - attribute \src "libresoc.v:124236.18-124236.115" - wire $and$libresoc.v:124236$5128_Y - attribute \src "libresoc.v:124238.18-124238.115" - wire $and$libresoc.v:124238$5130_Y - attribute \src "libresoc.v:124217.18-124217.105" - wire $not$libresoc.v:124217$5109_Y - attribute \src "libresoc.v:124220.18-124220.105" - wire $not$libresoc.v:124220$5112_Y - attribute \src "libresoc.v:124221.17-124221.104" - wire $not$libresoc.v:124221$5113_Y - attribute \src "libresoc.v:124223.18-124223.105" - wire $not$libresoc.v:124223$5115_Y - attribute \src "libresoc.v:124226.18-124226.105" - wire $not$libresoc.v:124226$5118_Y - attribute \src "libresoc.v:124228.18-124228.105" - wire $not$libresoc.v:124228$5120_Y - attribute \src "libresoc.v:124231.18-124231.105" - wire $not$libresoc.v:124231$5123_Y - attribute \src "libresoc.v:124234.18-124234.105" - wire $not$libresoc.v:124234$5126_Y - attribute \src "libresoc.v:124237.18-124237.105" - wire $not$libresoc.v:124237$5129_Y - attribute \src "libresoc.v:124239.18-124239.105" - wire $not$libresoc.v:124239$5131_Y - attribute \src "libresoc.v:124241.17-124241.104" - wire $not$libresoc.v:124241$5133_Y - attribute \src "libresoc.v:124216.17-124216.103" - wire $or$libresoc.v:124216$5108_Y - attribute \src "libresoc.v:124219.18-124219.115" - wire $or$libresoc.v:124219$5111_Y - attribute \src "libresoc.v:124222.18-124222.106" - wire $or$libresoc.v:124222$5114_Y - attribute \src "libresoc.v:124225.18-124225.115" - wire $or$libresoc.v:124225$5117_Y - attribute \src "libresoc.v:124227.18-124227.106" - wire $or$libresoc.v:124227$5119_Y - attribute \src "libresoc.v:124230.18-124230.115" - wire $or$libresoc.v:124230$5122_Y - attribute \src "libresoc.v:124233.18-124233.106" - wire $or$libresoc.v:124233$5125_Y - attribute \src "libresoc.v:124240.17-124240.114" - wire $or$libresoc.v:124240$5132_Y + attribute \src "libresoc.v:134049.3-134071.6" + wire width 45 $2\ibus__adr$next[44:0]$5485 + attribute \src "libresoc.v:133940.3-133967.6" + wire $2\ibus__cyc$next[0:0]$5461 + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $2\ibus__sel$next[7:0]$5473 + attribute \src "libresoc.v:133968.3-133995.6" + wire $2\ibus__stb$next[0:0]$5467 + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $2\ibus_rdata$next[63:0]$5479 + attribute \src "libresoc.v:134095.3-134114.6" + wire width 45 $3\f_badaddr_o$next[44:0]$5496 + attribute \src "libresoc.v:134072.3-134094.6" + wire $3\f_fetch_err_o$next[0:0]$5491 + attribute \src "libresoc.v:134049.3-134071.6" + wire width 45 $3\ibus__adr$next[44:0]$5486 + attribute \src "libresoc.v:133940.3-133967.6" + wire $3\ibus__cyc$next[0:0]$5462 + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $3\ibus__sel$next[7:0]$5474 + attribute \src "libresoc.v:133968.3-133995.6" + wire $3\ibus__stb$next[0:0]$5468 + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $3\ibus_rdata$next[63:0]$5480 + attribute \src "libresoc.v:133940.3-133967.6" + wire $4\ibus__cyc$next[0:0]$5463 + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $4\ibus__sel$next[7:0]$5475 + attribute \src "libresoc.v:133968.3-133995.6" + wire $4\ibus__stb$next[0:0]$5469 + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $4\ibus_rdata$next[63:0]$5481 + attribute \src "libresoc.v:133902.18-133902.110" + wire $and$libresoc.v:133902$5427_Y + attribute \src "libresoc.v:133908.18-133908.110" + wire $and$libresoc.v:133908$5433_Y + attribute \src "libresoc.v:133913.18-133913.110" + wire $and$libresoc.v:133913$5438_Y + attribute \src "libresoc.v:133916.17-133916.108" + wire $and$libresoc.v:133916$5441_Y + attribute \src "libresoc.v:133919.18-133919.110" + wire $and$libresoc.v:133919$5444_Y + attribute \src "libresoc.v:133920.18-133920.115" + wire $and$libresoc.v:133920$5445_Y + attribute \src "libresoc.v:133922.18-133922.115" + wire $and$libresoc.v:133922$5447_Y + attribute \src "libresoc.v:133901.18-133901.105" + wire $not$libresoc.v:133901$5426_Y + attribute \src "libresoc.v:133904.18-133904.105" + wire $not$libresoc.v:133904$5429_Y + attribute \src "libresoc.v:133905.17-133905.104" + wire $not$libresoc.v:133905$5430_Y + attribute \src "libresoc.v:133907.18-133907.105" + wire $not$libresoc.v:133907$5432_Y + attribute \src "libresoc.v:133910.18-133910.105" + wire $not$libresoc.v:133910$5435_Y + attribute \src "libresoc.v:133912.18-133912.105" + wire $not$libresoc.v:133912$5437_Y + attribute \src "libresoc.v:133915.18-133915.105" + wire $not$libresoc.v:133915$5440_Y + attribute \src "libresoc.v:133918.18-133918.105" + wire $not$libresoc.v:133918$5443_Y + attribute \src "libresoc.v:133921.18-133921.105" + wire $not$libresoc.v:133921$5446_Y + attribute \src "libresoc.v:133923.18-133923.105" + wire $not$libresoc.v:133923$5448_Y + attribute \src "libresoc.v:133925.17-133925.104" + wire $not$libresoc.v:133925$5450_Y + attribute \src "libresoc.v:133900.17-133900.103" + wire $or$libresoc.v:133900$5425_Y + attribute \src "libresoc.v:133903.18-133903.115" + wire $or$libresoc.v:133903$5428_Y + attribute \src "libresoc.v:133906.18-133906.106" + wire $or$libresoc.v:133906$5431_Y + attribute \src "libresoc.v:133909.18-133909.115" + wire $or$libresoc.v:133909$5434_Y + attribute \src "libresoc.v:133911.18-133911.106" + wire $or$libresoc.v:133911$5436_Y + attribute \src "libresoc.v:133914.18-133914.115" + wire $or$libresoc.v:133914$5439_Y + attribute \src "libresoc.v:133917.18-133917.106" + wire $or$libresoc.v:133917$5442_Y + attribute \src "libresoc.v:133924.17-133924.114" + wire $or$libresoc.v:133924$5449_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" @@ -195777,7 +211515,7 @@ module \imem wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o @@ -195821,14 +211559,14 @@ module \imem wire width 64 \ibus_rdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:124101.7-124101.15" + attribute \src "libresoc.v:133785.7-133785.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire input 7 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124218$5110 + cell $and $and$libresoc.v:133902$5427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195836,10 +211574,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 - connect \Y $and$libresoc.v:124218$5110_Y + connect \Y $and$libresoc.v:133902$5427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124224$5116 + cell $and $and$libresoc.v:133908$5433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195847,10 +211585,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 - connect \Y $and$libresoc.v:124224$5116_Y + connect \Y $and$libresoc.v:133908$5433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124229$5121 + cell $and $and$libresoc.v:133913$5438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195858,10 +211596,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 - connect \Y $and$libresoc.v:124229$5121_Y + connect \Y $and$libresoc.v:133913$5438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124232$5124 + cell $and $and$libresoc.v:133916$5441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195869,10 +211607,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 - connect \Y $and$libresoc.v:124232$5124_Y + connect \Y $and$libresoc.v:133916$5441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124235$5127 + cell $and $and$libresoc.v:133919$5444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195880,10 +211618,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 - connect \Y $and$libresoc.v:124235$5127_Y + connect \Y $and$libresoc.v:133919$5444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:124236$5128 + cell $and $and$libresoc.v:133920$5445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195891,10 +211629,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:124236$5128_Y + connect \Y $and$libresoc.v:133920$5445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:124238$5130 + cell $and $and$libresoc.v:133922$5447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195902,98 +211640,98 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:124238$5130_Y + connect \Y $and$libresoc.v:133922$5447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124217$5109 + cell $not $not$libresoc.v:133901$5426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:124217$5109_Y + connect \Y $not$libresoc.v:133901$5426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:124220$5112 + cell $not $not$libresoc.v:133904$5429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:124220$5112_Y + connect \Y $not$libresoc.v:133904$5429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124221$5113 + cell $not $not$libresoc.v:133905$5430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:124221$5113_Y + connect \Y $not$libresoc.v:133905$5430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124223$5115 + cell $not $not$libresoc.v:133907$5432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:124223$5115_Y + connect \Y $not$libresoc.v:133907$5432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:124226$5118 + cell $not $not$libresoc.v:133910$5435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:124226$5118_Y + connect \Y $not$libresoc.v:133910$5435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124228$5120 + cell $not $not$libresoc.v:133912$5437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:124228$5120_Y + connect \Y $not$libresoc.v:133912$5437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:124231$5123 + cell $not $not$libresoc.v:133915$5440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:124231$5123_Y + connect \Y $not$libresoc.v:133915$5440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124234$5126 + cell $not $not$libresoc.v:133918$5443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:124234$5126_Y + connect \Y $not$libresoc.v:133918$5443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:124237$5129 + cell $not $not$libresoc.v:133921$5446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:124237$5129_Y + connect \Y $not$libresoc.v:133921$5446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:124239$5131 + cell $not $not$libresoc.v:133923$5448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:124239$5131_Y + connect \Y $not$libresoc.v:133923$5448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:124241$5133 + cell $not $not$libresoc.v:133925$5450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:124241$5133_Y + connect \Y $not$libresoc.v:133925$5450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124216$5108 + cell $or $or$libresoc.v:133900$5425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196001,10 +211739,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:124216$5108_Y + connect \Y $or$libresoc.v:133900$5425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124219$5111 + cell $or $or$libresoc.v:133903$5428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196012,10 +211750,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:124219$5111_Y + connect \Y $or$libresoc.v:133903$5428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124222$5114 + cell $or $or$libresoc.v:133906$5431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196023,10 +211761,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:124222$5114_Y + connect \Y $or$libresoc.v:133906$5431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124225$5117 + cell $or $or$libresoc.v:133909$5434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196034,10 +211772,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:124225$5117_Y + connect \Y $or$libresoc.v:133909$5434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124227$5119 + cell $or $or$libresoc.v:133911$5436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196045,10 +211783,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 - connect \Y $or$libresoc.v:124227$5119_Y + connect \Y $or$libresoc.v:133911$5436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124230$5122 + cell $or $or$libresoc.v:133914$5439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196056,10 +211794,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:124230$5122_Y + connect \Y $or$libresoc.v:133914$5439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124233$5125 + cell $or $or$libresoc.v:133917$5442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196067,10 +211805,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 - connect \Y $or$libresoc.v:124233$5125_Y + connect \Y $or$libresoc.v:133917$5442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124240$5132 + cell $or $or$libresoc.v:133924$5449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196078,130 +211816,130 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:124240$5132_Y + connect \Y $or$libresoc.v:133924$5449_Y end - attribute \src "libresoc.v:124101.7-124101.20" - process $proc$libresoc.v:124101$5183 + attribute \src "libresoc.v:133785.7-133785.20" + process $proc$libresoc.v:133785$5500 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124165.14-124165.44" - process $proc$libresoc.v:124165$5184 + attribute \src "libresoc.v:133849.14-133849.44" + process $proc$libresoc.v:133849$5501 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:124172.7-124172.27" - process $proc$libresoc.v:124172$5185 + attribute \src "libresoc.v:133856.7-133856.27" + process $proc$libresoc.v:133856$5502 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:124186.14-124186.42" - process $proc$libresoc.v:124186$5186 + attribute \src "libresoc.v:133870.14-133870.42" + process $proc$libresoc.v:133870$5503 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:124191.7-124191.23" - process $proc$libresoc.v:124191$5187 + attribute \src "libresoc.v:133875.7-133875.23" + process $proc$libresoc.v:133875$5504 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end - attribute \src "libresoc.v:124200.13-124200.30" - process $proc$libresoc.v:124200$5188 + attribute \src "libresoc.v:133884.13-133884.30" + process $proc$libresoc.v:133884$5505 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:124205.7-124205.23" - process $proc$libresoc.v:124205$5189 + attribute \src "libresoc.v:133889.7-133889.23" + process $proc$libresoc.v:133889$5506 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end - attribute \src "libresoc.v:124209.14-124209.47" - process $proc$libresoc.v:124209$5190 + attribute \src "libresoc.v:133893.14-133893.47" + process $proc$libresoc.v:133893$5507 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:124242.3-124243.39" - process $proc$libresoc.v:124242$5134 + attribute \src "libresoc.v:133926.3-133927.39" + process $proc$libresoc.v:133926$5451 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end - attribute \src "libresoc.v:124244.3-124245.43" - process $proc$libresoc.v:124244$5135 + attribute \src "libresoc.v:133928.3-133929.43" + process $proc$libresoc.v:133928$5452 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:124246.3-124247.35" - process $proc$libresoc.v:124246$5136 + attribute \src "libresoc.v:133930.3-133931.35" + process $proc$libresoc.v:133930$5453 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end - attribute \src "libresoc.v:124248.3-124249.37" - process $proc$libresoc.v:124248$5137 + attribute \src "libresoc.v:133932.3-133933.37" + process $proc$libresoc.v:133932$5454 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end - attribute \src "libresoc.v:124250.3-124251.35" - process $proc$libresoc.v:124250$5138 + attribute \src "libresoc.v:133934.3-133935.35" + process $proc$libresoc.v:133934$5455 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end - attribute \src "libresoc.v:124252.3-124253.35" - process $proc$libresoc.v:124252$5139 + attribute \src "libresoc.v:133936.3-133937.35" + process $proc$libresoc.v:133936$5456 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end - attribute \src "libresoc.v:124254.3-124255.35" - process $proc$libresoc.v:124254$5140 + attribute \src "libresoc.v:133938.3-133939.35" + process $proc$libresoc.v:133938$5457 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end - attribute \src "libresoc.v:124256.3-124283.6" - process $proc$libresoc.v:124256$5141 + attribute \src "libresoc.v:133940.3-133967.6" + process $proc$libresoc.v:133940$5458 assign { } { } assign { } { } assign { } { } - assign $0\ibus__cyc$next[0:0]$5142 $4\ibus__cyc$next[0:0]$5146 - attribute \src "libresoc.v:124257.5-124257.29" + assign $0\ibus__cyc$next[0:0]$5459 $4\ibus__cyc$next[0:0]$5463 + attribute \src "libresoc.v:133941.5-133941.29" switch \initial - attribute \src "libresoc.v:124257.9-124257.17" + attribute \src "libresoc.v:133941.9-133941.17" case 1'1 case end @@ -196210,53 +211948,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__cyc$next[0:0]$5143 $2\ibus__cyc$next[0:0]$5144 + assign $1\ibus__cyc$next[0:0]$5460 $2\ibus__cyc$next[0:0]$5461 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$3 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__cyc$next[0:0]$5144 $3\ibus__cyc$next[0:0]$5145 + assign $2\ibus__cyc$next[0:0]$5461 $3\ibus__cyc$next[0:0]$5462 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__cyc$next[0:0]$5145 1'0 + assign $3\ibus__cyc$next[0:0]$5462 1'0 case - assign $3\ibus__cyc$next[0:0]$5145 \ibus__cyc + assign $3\ibus__cyc$next[0:0]$5462 \ibus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__cyc$next[0:0]$5144 1'1 + assign $2\ibus__cyc$next[0:0]$5461 1'1 case - assign $2\ibus__cyc$next[0:0]$5144 \ibus__cyc + assign $2\ibus__cyc$next[0:0]$5461 \ibus__cyc end case - assign $1\ibus__cyc$next[0:0]$5143 \ibus__cyc + assign $1\ibus__cyc$next[0:0]$5460 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__cyc$next[0:0]$5146 1'0 + assign $4\ibus__cyc$next[0:0]$5463 1'0 case - assign $4\ibus__cyc$next[0:0]$5146 $1\ibus__cyc$next[0:0]$5143 + assign $4\ibus__cyc$next[0:0]$5463 $1\ibus__cyc$next[0:0]$5460 end sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5142 + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5459 end - attribute \src "libresoc.v:124284.3-124311.6" - process $proc$libresoc.v:124284$5147 + attribute \src "libresoc.v:133968.3-133995.6" + process $proc$libresoc.v:133968$5464 assign { } { } assign { } { } assign { } { } - assign $0\ibus__stb$next[0:0]$5148 $4\ibus__stb$next[0:0]$5152 - attribute \src "libresoc.v:124285.5-124285.29" + assign $0\ibus__stb$next[0:0]$5465 $4\ibus__stb$next[0:0]$5469 + attribute \src "libresoc.v:133969.5-133969.29" switch \initial - attribute \src "libresoc.v:124285.9-124285.17" + attribute \src "libresoc.v:133969.9-133969.17" case 1'1 case end @@ -196265,53 +212003,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__stb$next[0:0]$5149 $2\ibus__stb$next[0:0]$5150 + assign $1\ibus__stb$next[0:0]$5466 $2\ibus__stb$next[0:0]$5467 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$13 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__stb$next[0:0]$5150 $3\ibus__stb$next[0:0]$5151 + assign $2\ibus__stb$next[0:0]$5467 $3\ibus__stb$next[0:0]$5468 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__stb$next[0:0]$5151 1'0 + assign $3\ibus__stb$next[0:0]$5468 1'0 case - assign $3\ibus__stb$next[0:0]$5151 \ibus__stb + assign $3\ibus__stb$next[0:0]$5468 \ibus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__stb$next[0:0]$5150 1'1 + assign $2\ibus__stb$next[0:0]$5467 1'1 case - assign $2\ibus__stb$next[0:0]$5150 \ibus__stb + assign $2\ibus__stb$next[0:0]$5467 \ibus__stb end case - assign $1\ibus__stb$next[0:0]$5149 \ibus__stb + assign $1\ibus__stb$next[0:0]$5466 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__stb$next[0:0]$5152 1'0 + assign $4\ibus__stb$next[0:0]$5469 1'0 case - assign $4\ibus__stb$next[0:0]$5152 $1\ibus__stb$next[0:0]$5149 + assign $4\ibus__stb$next[0:0]$5469 $1\ibus__stb$next[0:0]$5466 end sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5148 + update \ibus__stb$next $0\ibus__stb$next[0:0]$5465 end - attribute \src "libresoc.v:124312.3-124339.6" - process $proc$libresoc.v:124312$5153 + attribute \src "libresoc.v:133996.3-134023.6" + process $proc$libresoc.v:133996$5470 assign { } { } assign { } { } assign { } { } - assign $0\ibus__sel$next[7:0]$5154 $4\ibus__sel$next[7:0]$5158 - attribute \src "libresoc.v:124313.5-124313.29" + assign $0\ibus__sel$next[7:0]$5471 $4\ibus__sel$next[7:0]$5475 + attribute \src "libresoc.v:133997.5-133997.29" switch \initial - attribute \src "libresoc.v:124313.9-124313.17" + attribute \src "libresoc.v:133997.9-133997.17" case 1'1 case end @@ -196320,53 +212058,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__sel$next[7:0]$5155 $2\ibus__sel$next[7:0]$5156 + assign $1\ibus__sel$next[7:0]$5472 $2\ibus__sel$next[7:0]$5473 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$23 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__sel$next[7:0]$5156 $3\ibus__sel$next[7:0]$5157 + assign $2\ibus__sel$next[7:0]$5473 $3\ibus__sel$next[7:0]$5474 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__sel$next[7:0]$5157 8'00000000 + assign $3\ibus__sel$next[7:0]$5474 8'00000000 case - assign $3\ibus__sel$next[7:0]$5157 \ibus__sel + assign $3\ibus__sel$next[7:0]$5474 \ibus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__sel$next[7:0]$5156 8'11111111 + assign $2\ibus__sel$next[7:0]$5473 8'11111111 case - assign $2\ibus__sel$next[7:0]$5156 \ibus__sel + assign $2\ibus__sel$next[7:0]$5473 \ibus__sel end case - assign $1\ibus__sel$next[7:0]$5155 \ibus__sel + assign $1\ibus__sel$next[7:0]$5472 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__sel$next[7:0]$5158 8'00000000 + assign $4\ibus__sel$next[7:0]$5475 8'00000000 case - assign $4\ibus__sel$next[7:0]$5158 $1\ibus__sel$next[7:0]$5155 + assign $4\ibus__sel$next[7:0]$5475 $1\ibus__sel$next[7:0]$5472 end sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5154 + update \ibus__sel$next $0\ibus__sel$next[7:0]$5471 end - attribute \src "libresoc.v:124340.3-124364.6" - process $proc$libresoc.v:124340$5159 + attribute \src "libresoc.v:134024.3-134048.6" + process $proc$libresoc.v:134024$5476 assign { } { } assign { } { } assign { } { } - assign $0\ibus_rdata$next[63:0]$5160 $4\ibus_rdata$next[63:0]$5164 - attribute \src "libresoc.v:124341.5-124341.29" + assign $0\ibus_rdata$next[63:0]$5477 $4\ibus_rdata$next[63:0]$5481 + attribute \src "libresoc.v:134025.5-134025.29" switch \initial - attribute \src "libresoc.v:124341.9-124341.17" + attribute \src "libresoc.v:134025.9-134025.17" case 1'1 case end @@ -196375,49 +212113,49 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus_rdata$next[63:0]$5161 $2\ibus_rdata$next[63:0]$5162 + assign $1\ibus_rdata$next[63:0]$5478 $2\ibus_rdata$next[63:0]$5479 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$33 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus_rdata$next[63:0]$5162 $3\ibus_rdata$next[63:0]$5163 + assign $2\ibus_rdata$next[63:0]$5479 $3\ibus_rdata$next[63:0]$5480 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus_rdata$next[63:0]$5163 \ibus__dat_r + assign $3\ibus_rdata$next[63:0]$5480 \ibus__dat_r case - assign $3\ibus_rdata$next[63:0]$5163 \ibus_rdata + assign $3\ibus_rdata$next[63:0]$5480 \ibus_rdata end case - assign $2\ibus_rdata$next[63:0]$5162 \ibus_rdata + assign $2\ibus_rdata$next[63:0]$5479 \ibus_rdata end case - assign $1\ibus_rdata$next[63:0]$5161 \ibus_rdata + assign $1\ibus_rdata$next[63:0]$5478 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus_rdata$next[63:0]$5164 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\ibus_rdata$next[63:0]$5481 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\ibus_rdata$next[63:0]$5164 $1\ibus_rdata$next[63:0]$5161 + assign $4\ibus_rdata$next[63:0]$5481 $1\ibus_rdata$next[63:0]$5478 end sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5160 + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5477 end - attribute \src "libresoc.v:124365.3-124387.6" - process $proc$libresoc.v:124365$5165 + attribute \src "libresoc.v:134049.3-134071.6" + process $proc$libresoc.v:134049$5482 assign { } { } assign { } { } assign { } { } - assign $0\ibus__adr$next[44:0]$5166 $3\ibus__adr$next[44:0]$5169 - attribute \src "libresoc.v:124366.5-124366.29" + assign $0\ibus__adr$next[44:0]$5483 $3\ibus__adr$next[44:0]$5486 + attribute \src "libresoc.v:134050.5-134050.29" switch \initial - attribute \src "libresoc.v:124366.9-124366.17" + attribute \src "libresoc.v:134050.9-134050.17" case 1'1 case end @@ -196426,43 +212164,43 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__adr$next[44:0]$5167 $2\ibus__adr$next[44:0]$5168 + assign $1\ibus__adr$next[44:0]$5484 $2\ibus__adr$next[44:0]$5485 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$43 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\ibus__adr$next[44:0]$5168 \ibus__adr + assign $2\ibus__adr$next[44:0]$5485 \ibus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__adr$next[44:0]$5168 \a_pc_i [47:3] + assign $2\ibus__adr$next[44:0]$5485 \a_pc_i [47:3] case - assign $2\ibus__adr$next[44:0]$5168 \ibus__adr + assign $2\ibus__adr$next[44:0]$5485 \ibus__adr end case - assign $1\ibus__adr$next[44:0]$5167 \ibus__adr + assign $1\ibus__adr$next[44:0]$5484 \ibus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__adr$next[44:0]$5169 45'000000000000000000000000000000000000000000000 + assign $3\ibus__adr$next[44:0]$5486 45'000000000000000000000000000000000000000000000 case - assign $3\ibus__adr$next[44:0]$5169 $1\ibus__adr$next[44:0]$5167 + assign $3\ibus__adr$next[44:0]$5486 $1\ibus__adr$next[44:0]$5484 end sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5166 + update \ibus__adr$next $0\ibus__adr$next[44:0]$5483 end - attribute \src "libresoc.v:124388.3-124410.6" - process $proc$libresoc.v:124388$5170 + attribute \src "libresoc.v:134072.3-134094.6" + process $proc$libresoc.v:134072$5487 assign { } { } assign { } { } assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5171 $3\f_fetch_err_o$next[0:0]$5174 - attribute \src "libresoc.v:124389.5-124389.29" + assign $0\f_fetch_err_o$next[0:0]$5488 $3\f_fetch_err_o$next[0:0]$5491 + attribute \src "libresoc.v:134073.5-134073.29" switch \initial - attribute \src "libresoc.v:124389.9-124389.17" + attribute \src "libresoc.v:134073.9-134073.17" case 1'1 case end @@ -196471,44 +212209,44 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5172 $2\f_fetch_err_o$next[0:0]$5173 + assign $1\f_fetch_err_o$next[0:0]$5489 $2\f_fetch_err_o$next[0:0]$5490 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$47 \$45 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5173 1'1 + assign $2\f_fetch_err_o$next[0:0]$5490 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5173 1'0 + assign $2\f_fetch_err_o$next[0:0]$5490 1'0 case - assign $2\f_fetch_err_o$next[0:0]$5173 \f_fetch_err_o + assign $2\f_fetch_err_o$next[0:0]$5490 \f_fetch_err_o end case - assign $1\f_fetch_err_o$next[0:0]$5172 \f_fetch_err_o + assign $1\f_fetch_err_o$next[0:0]$5489 \f_fetch_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_fetch_err_o$next[0:0]$5174 1'0 + assign $3\f_fetch_err_o$next[0:0]$5491 1'0 case - assign $3\f_fetch_err_o$next[0:0]$5174 $1\f_fetch_err_o$next[0:0]$5172 + assign $3\f_fetch_err_o$next[0:0]$5491 $1\f_fetch_err_o$next[0:0]$5489 end sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5171 + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5488 end - attribute \src "libresoc.v:124411.3-124430.6" - process $proc$libresoc.v:124411$5175 + attribute \src "libresoc.v:134095.3-134114.6" + process $proc$libresoc.v:134095$5492 assign { } { } assign { } { } assign { } { } - assign $0\f_badaddr_o$next[44:0]$5176 $3\f_badaddr_o$next[44:0]$5179 - attribute \src "libresoc.v:124412.5-124412.29" + assign $0\f_badaddr_o$next[44:0]$5493 $3\f_badaddr_o$next[44:0]$5496 + attribute \src "libresoc.v:134096.5-134096.29" switch \initial - attribute \src "libresoc.v:124412.9-124412.17" + attribute \src "libresoc.v:134096.9-134096.17" case 1'1 case end @@ -196517,39 +212255,39 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_badaddr_o$next[44:0]$5177 $2\f_badaddr_o$next[44:0]$5178 + assign $1\f_badaddr_o$next[44:0]$5494 $2\f_badaddr_o$next[44:0]$5495 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$51 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_badaddr_o$next[44:0]$5178 \ibus__adr + assign $2\f_badaddr_o$next[44:0]$5495 \ibus__adr case - assign $2\f_badaddr_o$next[44:0]$5178 \f_badaddr_o + assign $2\f_badaddr_o$next[44:0]$5495 \f_badaddr_o end case - assign $1\f_badaddr_o$next[44:0]$5177 \f_badaddr_o + assign $1\f_badaddr_o$next[44:0]$5494 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_badaddr_o$next[44:0]$5179 45'000000000000000000000000000000000000000000000 + assign $3\f_badaddr_o$next[44:0]$5496 45'000000000000000000000000000000000000000000000 case - assign $3\f_badaddr_o$next[44:0]$5179 $1\f_badaddr_o$next[44:0]$5177 + assign $3\f_badaddr_o$next[44:0]$5496 $1\f_badaddr_o$next[44:0]$5494 end sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5176 + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5493 end - attribute \src "libresoc.v:124431.3-124440.6" - process $proc$libresoc.v:124431$5180 + attribute \src "libresoc.v:134115.3-134124.6" + process $proc$libresoc.v:134115$5497 assign { } { } assign { } { } assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:124432.5-124432.29" + attribute \src "libresoc.v:134116.5-134116.29" switch \initial - attribute \src "libresoc.v:124432.9-124432.17" + attribute \src "libresoc.v:134116.9-134116.17" case 1'1 case end @@ -196565,14 +212303,14 @@ module \imem sync always update \a_busy_o $0\a_busy_o[0:0] end - attribute \src "libresoc.v:124441.3-124458.6" - process $proc$libresoc.v:124441$5181 + attribute \src "libresoc.v:134125.3-134142.6" + process $proc$libresoc.v:134125$5498 assign { } { } assign { } { } assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:124442.5-124442.29" + attribute \src "libresoc.v:134126.5-134126.29" switch \initial - attribute \src "libresoc.v:124442.9-124442.17" + attribute \src "libresoc.v:134126.9-134126.17" case 1'1 case end @@ -196599,14 +212337,14 @@ module \imem sync always update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:124459.3-124476.6" - process $proc$libresoc.v:124459$5182 + attribute \src "libresoc.v:134143.3-134160.6" + process $proc$libresoc.v:134143$5499 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:124460.5-124460.29" + attribute \src "libresoc.v:134144.5-134144.29" switch \initial - attribute \src "libresoc.v:124460.9-124460.17" + attribute \src "libresoc.v:134144.9-134144.17" case 1'1 case end @@ -196632,52 +212370,52 @@ module \imem sync always update \f_instr_o $0\f_instr_o[63:0] end - connect \$9 $or$libresoc.v:124216$5108_Y - connect \$11 $not$libresoc.v:124217$5109_Y - connect \$13 $and$libresoc.v:124218$5110_Y - connect \$15 $or$libresoc.v:124219$5111_Y - connect \$17 $not$libresoc.v:124220$5112_Y - connect \$1 $not$libresoc.v:124221$5113_Y - connect \$19 $or$libresoc.v:124222$5114_Y - connect \$21 $not$libresoc.v:124223$5115_Y - connect \$23 $and$libresoc.v:124224$5116_Y - connect \$25 $or$libresoc.v:124225$5117_Y - connect \$27 $not$libresoc.v:124226$5118_Y - connect \$29 $or$libresoc.v:124227$5119_Y - connect \$31 $not$libresoc.v:124228$5120_Y - connect \$33 $and$libresoc.v:124229$5121_Y - connect \$35 $or$libresoc.v:124230$5122_Y - connect \$37 $not$libresoc.v:124231$5123_Y - connect \$3 $and$libresoc.v:124232$5124_Y - connect \$39 $or$libresoc.v:124233$5125_Y - connect \$41 $not$libresoc.v:124234$5126_Y - connect \$43 $and$libresoc.v:124235$5127_Y - connect \$45 $and$libresoc.v:124236$5128_Y - connect \$47 $not$libresoc.v:124237$5129_Y - connect \$49 $and$libresoc.v:124238$5130_Y - connect \$51 $not$libresoc.v:124239$5131_Y - connect \$5 $or$libresoc.v:124240$5132_Y - connect \$7 $not$libresoc.v:124241$5133_Y + connect \$9 $or$libresoc.v:133900$5425_Y + connect \$11 $not$libresoc.v:133901$5426_Y + connect \$13 $and$libresoc.v:133902$5427_Y + connect \$15 $or$libresoc.v:133903$5428_Y + connect \$17 $not$libresoc.v:133904$5429_Y + connect \$1 $not$libresoc.v:133905$5430_Y + connect \$19 $or$libresoc.v:133906$5431_Y + connect \$21 $not$libresoc.v:133907$5432_Y + connect \$23 $and$libresoc.v:133908$5433_Y + connect \$25 $or$libresoc.v:133909$5434_Y + connect \$27 $not$libresoc.v:133910$5435_Y + connect \$29 $or$libresoc.v:133911$5436_Y + connect \$31 $not$libresoc.v:133912$5437_Y + connect \$33 $and$libresoc.v:133913$5438_Y + connect \$35 $or$libresoc.v:133914$5439_Y + connect \$37 $not$libresoc.v:133915$5440_Y + connect \$3 $and$libresoc.v:133916$5441_Y + connect \$39 $or$libresoc.v:133917$5442_Y + connect \$41 $not$libresoc.v:133918$5443_Y + connect \$43 $and$libresoc.v:133919$5444_Y + connect \$45 $and$libresoc.v:133920$5445_Y + connect \$47 $not$libresoc.v:133921$5446_Y + connect \$49 $and$libresoc.v:133922$5447_Y + connect \$51 $not$libresoc.v:133923$5448_Y + connect \$5 $or$libresoc.v:133924$5449_Y + connect \$7 $not$libresoc.v:133925$5450_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 end -attribute \src "libresoc.v:124483.1-124804.10" +attribute \src "libresoc.v:134167.1-134494.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input - attribute \src "libresoc.v:124767.3-124778.6" + attribute \src "libresoc.v:134457.3-134468.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:124484.7-124484.20" + attribute \src "libresoc.v:134168.7-134168.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124779.3-124797.6" - wire width 2 $0\xer_ca$23[1:0]$5194 - attribute \src "libresoc.v:124767.3-124778.6" + attribute \src "libresoc.v:134469.3-134487.6" + wire width 2 $0\xer_ca$23[1:0]$5511 + attribute \src "libresoc.v:134457.3-134468.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:124779.3-124797.6" - wire width 2 $1\xer_ca$23[1:0]$5195 - attribute \src "libresoc.v:124766.18-124766.100" - wire width 64 $not$libresoc.v:124766$5191_Y + attribute \src "libresoc.v:134469.3-134487.6" + wire width 2 $1\xer_ca$23[1:0]$5512 + attribute \src "libresoc.v:134456.18-134456.100" + wire width 64 $not$libresoc.v:134456$5508_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" @@ -196687,35 +212425,39 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \alu_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \alu_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -196814,6 +212556,7 @@ module \input attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -196890,6 +212633,7 @@ module \input attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -196938,11 +212682,11 @@ module \input wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:124484.7-124484.15" + attribute \src "libresoc.v:134168.7-134168.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra @@ -196961,28 +212705,28 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:124766$5191 + cell $not $not$libresoc.v:134456$5508 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:124766$5191_Y + connect \Y $not$libresoc.v:134456$5508_Y end - attribute \src "libresoc.v:124484.7-124484.20" - process $proc$libresoc.v:124484$5196 + attribute \src "libresoc.v:134168.7-134168.20" + process $proc$libresoc.v:134168$5513 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124767.3-124778.6" - process $proc$libresoc.v:124767$5192 + attribute \src "libresoc.v:134457.3-134468.6" + process $proc$libresoc.v:134457$5509 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:124768.5-124768.29" + attribute \src "libresoc.v:134458.5-134458.29" switch \initial - attribute \src "libresoc.v:124768.9-124768.17" + attribute \src "libresoc.v:134458.9-134458.17" case 1'1 case end @@ -197000,14 +212744,14 @@ module \input sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:124779.3-124797.6" - process $proc$libresoc.v:124779$5193 + attribute \src "libresoc.v:134469.3-134487.6" + process $proc$libresoc.v:134469$5510 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5194 $1\xer_ca$23[1:0]$5195 - attribute \src "libresoc.v:124780.5-124780.29" + assign $0\xer_ca$23[1:0]$5511 $1\xer_ca$23[1:0]$5512 + attribute \src "libresoc.v:134470.5-134470.29" switch \initial - attribute \src "libresoc.v:124780.9-124780.17" + attribute \src "libresoc.v:134470.9-134470.17" case 1'1 case end @@ -197016,22 +212760,22 @@ module \input attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5195 2'00 + assign $1\xer_ca$23[1:0]$5512 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5195 2'11 + assign $1\xer_ca$23[1:0]$5512 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5195 \xer_ca + assign $1\xer_ca$23[1:0]$5512 \xer_ca case - assign $1\xer_ca$23[1:0]$5195 2'00 + assign $1\xer_ca$23[1:0]$5512 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5194 + update \xer_ca$23 $0\xer_ca$23[1:0]$5511 end - connect \$24 $not$libresoc.v:124766$5191_Y + connect \$24 $not$libresoc.v:134456$5508_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -197039,34 +212783,34 @@ module \input connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:124808.1-125130.10" +attribute \src "libresoc.v:134498.1-134826.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" module \input$113 - attribute \src "libresoc.v:125092.3-125103.6" + attribute \src "libresoc.v:134788.3-134799.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:124809.7-124809.20" + attribute \src "libresoc.v:134499.7-134499.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125104.3-125122.6" - wire width 2 $0\xer_ca$23[1:0]$5200 - attribute \src "libresoc.v:125092.3-125103.6" + attribute \src "libresoc.v:134800.3-134818.6" + wire width 2 $0\xer_ca$23[1:0]$5517 + attribute \src "libresoc.v:134788.3-134799.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:125104.3-125122.6" - wire width 2 $1\xer_ca$23[1:0]$5201 - attribute \src "libresoc.v:125091.18-125091.100" - wire width 64 $not$libresoc.v:125091$5197_Y + attribute \src "libresoc.v:134800.3-134818.6" + wire width 2 $1\xer_ca$23[1:0]$5518 + attribute \src "libresoc.v:134787.18-134787.100" + wire width 64 $not$libresoc.v:134787$5514_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:124809.7-124809.15" + attribute \src "libresoc.v:134499.7-134499.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 18 \ra @@ -197081,35 +212825,39 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 43 \rc$21 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \sr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -197212,6 +212960,7 @@ module \input$113 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -197288,6 +213037,7 @@ module \input$113 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -197339,28 +213089,28 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:125091$5197 + cell $not $not$libresoc.v:134787$5514 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:125091$5197_Y + connect \Y $not$libresoc.v:134787$5514_Y end - attribute \src "libresoc.v:124809.7-124809.20" - process $proc$libresoc.v:124809$5202 + attribute \src "libresoc.v:134499.7-134499.20" + process $proc$libresoc.v:134499$5519 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125092.3-125103.6" - process $proc$libresoc.v:125092$5198 + attribute \src "libresoc.v:134788.3-134799.6" + process $proc$libresoc.v:134788$5515 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:125093.5-125093.29" + attribute \src "libresoc.v:134789.5-134789.29" switch \initial - attribute \src "libresoc.v:125093.9-125093.17" + attribute \src "libresoc.v:134789.9-134789.17" case 1'1 case end @@ -197378,14 +213128,14 @@ module \input$113 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:125104.3-125122.6" - process $proc$libresoc.v:125104$5199 + attribute \src "libresoc.v:134800.3-134818.6" + process $proc$libresoc.v:134800$5516 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5200 $1\xer_ca$23[1:0]$5201 - attribute \src "libresoc.v:125105.5-125105.29" + assign $0\xer_ca$23[1:0]$5517 $1\xer_ca$23[1:0]$5518 + attribute \src "libresoc.v:134801.5-134801.29" switch \initial - attribute \src "libresoc.v:125105.9-125105.17" + attribute \src "libresoc.v:134801.9-134801.17" case 1'1 case end @@ -197394,22 +213144,22 @@ module \input$113 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5201 2'00 + assign $1\xer_ca$23[1:0]$5518 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5201 2'11 + assign $1\xer_ca$23[1:0]$5518 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5201 \xer_ca + assign $1\xer_ca$23[1:0]$5518 \xer_ca case - assign $1\xer_ca$23[1:0]$5201 2'00 + assign $1\xer_ca$23[1:0]$5518 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5200 + update \xer_ca$23 $0\xer_ca$23[1:0]$5517 end - connect \$24 $not$libresoc.v:125091$5197_Y + connect \$24 $not$libresoc.v:134787$5514_Y connect \rc$21 \rc connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid @@ -197418,61 +213168,65 @@ module \input$113 connect \b \rb connect \ra$19 \a end -attribute \src "libresoc.v:125134.1-125431.10" +attribute \src "libresoc.v:134830.1-135133.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" module \input$50 - attribute \src "libresoc.v:125413.3-125424.6" + attribute \src "libresoc.v:135115.3-135126.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:125135.7-125135.20" + attribute \src "libresoc.v:134831.7-134831.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125413.3-125424.6" + attribute \src "libresoc.v:135115.3-135126.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:125412.18-125412.100" - wire width 64 $not$libresoc.v:125412$5203_Y + attribute \src "libresoc.v:135114.18-135114.100" + wire width 64 $not$libresoc.v:135114$5520_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:125135.7-125135.15" + attribute \src "libresoc.v:134831.7-134831.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -197571,6 +213325,7 @@ module \input$50 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -197647,6 +213402,7 @@ module \input$50 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -197693,9 +213449,9 @@ module \input$50 wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra @@ -197710,28 +213466,28 @@ module \input$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:125412$5203 + cell $not $not$libresoc.v:135114$5520 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $not$libresoc.v:125412$5203_Y + connect \Y $not$libresoc.v:135114$5520_Y end - attribute \src "libresoc.v:125135.7-125135.20" - process $proc$libresoc.v:125135$5205 + attribute \src "libresoc.v:134831.7-134831.20" + process $proc$libresoc.v:134831$5522 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125413.3-125424.6" - process $proc$libresoc.v:125413$5204 + attribute \src "libresoc.v:135115.3-135126.6" + process $proc$libresoc.v:135115$5521 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:125414.5-125414.29" + attribute \src "libresoc.v:135116.5-135116.29" switch \initial - attribute \src "libresoc.v:125414.9-125414.17" + attribute \src "libresoc.v:135116.9-135116.17" case 1'1 case end @@ -197749,7 +213505,7 @@ module \input$50 sync always update \b $0\b[63:0] end - connect \$23 $not$libresoc.v:125412$5203_Y + connect \$23 $not$libresoc.v:135114$5520_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -197757,61 +213513,65 @@ module \input$50 connect \ra$20 \a connect \a \ra end -attribute \src "libresoc.v:125435.1-125732.10" +attribute \src "libresoc.v:135137.1-135440.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" module \input$78 - attribute \src "libresoc.v:125714.3-125725.6" + attribute \src "libresoc.v:135422.3-135433.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:125436.7-125436.20" + attribute \src "libresoc.v:135138.7-135138.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125714.3-125725.6" + attribute \src "libresoc.v:135422.3-135433.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:125713.18-125713.100" - wire width 64 $not$libresoc.v:125713$5206_Y + attribute \src "libresoc.v:135421.18-135421.100" + wire width 64 $not$libresoc.v:135421$5523_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:125436.7-125436.15" + attribute \src "libresoc.v:135138.7-135138.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -197910,6 +213670,7 @@ module \input$78 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -197986,6 +213747,7 @@ module \input$78 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -198032,9 +213794,9 @@ module \input$78 wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra @@ -198049,28 +213811,28 @@ module \input$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:125713$5206 + cell $not $not$libresoc.v:135421$5523 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:125713$5206_Y + connect \Y $not$libresoc.v:135421$5523_Y end - attribute \src "libresoc.v:125436.7-125436.20" - process $proc$libresoc.v:125436$5208 + attribute \src "libresoc.v:135138.7-135138.20" + process $proc$libresoc.v:135138$5525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125714.3-125725.6" - process $proc$libresoc.v:125714$5207 + attribute \src "libresoc.v:135422.3-135433.6" + process $proc$libresoc.v:135422$5524 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:125715.5-125715.29" + attribute \src "libresoc.v:135423.5-135423.29" switch \initial - attribute \src "libresoc.v:125715.9-125715.17" + attribute \src "libresoc.v:135423.9-135423.17" case 1'1 case end @@ -198088,7 +213850,7 @@ module \input$78 sync always update \a $0\a[63:0] end - connect \$23 $not$libresoc.v:125713$5206_Y + connect \$23 $not$libresoc.v:135421$5523_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -198096,7 +213858,7 @@ module \input$78 connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:125736.1-125986.10" +attribute \src "libresoc.v:135444.1-135700.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" @@ -198106,35 +213868,39 @@ module \input$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -198221,6 +213987,7 @@ module \input$95 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -198297,6 +214064,7 @@ module \input$95 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -198327,9 +214095,9 @@ module \input$95 wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 32 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 16 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \ra @@ -198351,114 +214119,114 @@ module \input$95 connect \ra$14 \a connect \a \ra end -attribute \src "libresoc.v:125990.1-126209.10" +attribute \src "libresoc.v:135704.1-135923.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int - attribute \src "libresoc.v:126115.3-126121.6" - wire width 5 $0$memwr$\memory$libresoc.v:126120$5241_ADDR[4:0]$5250 - attribute \src "libresoc.v:126115.3-126121.6" - wire width 64 $0$memwr$\memory$libresoc.v:126120$5241_DATA[63:0]$5251 - attribute \src "libresoc.v:126115.3-126121.6" - wire width 64 $0$memwr$\memory$libresoc.v:126120$5241_EN[63:0]$5252 - attribute \src "libresoc.v:126115.3-126121.6" + attribute \src "libresoc.v:135829.3-135835.6" + wire width 5 $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 + attribute \src "libresoc.v:135829.3-135835.6" + wire width 64 $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 + attribute \src "libresoc.v:135829.3-135835.6" + wire width 64 $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 + attribute \src "libresoc.v:135829.3-135835.6" wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:126115.3-126121.6" + attribute \src "libresoc.v:135829.3-135835.6" wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:126115.3-126121.6" + attribute \src "libresoc.v:135829.3-135835.6" wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:126115.3-126121.6" + attribute \src "libresoc.v:135829.3-135835.6" wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:126144.3-126153.6" + attribute \src "libresoc.v:135858.3-135867.6" wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:125991.7-125991.20" + attribute \src "libresoc.v:135705.7-135705.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126135.3-126143.6" - wire $0\ren_delay$10$next[0:0]$5261 - attribute \src "libresoc.v:126068.3-126069.43" - wire $0\ren_delay$10[0:0]$5243 - attribute \src "libresoc.v:126034.7-126034.28" - wire $0\ren_delay$10[0:0]$5309 - attribute \src "libresoc.v:126164.3-126172.6" - wire $0\ren_delay$8$next[0:0]$5266 - attribute \src "libresoc.v:126072.3-126073.41" - wire $0\ren_delay$8[0:0]$5247 - attribute \src "libresoc.v:126038.7-126038.27" - wire $0\ren_delay$8[0:0]$5311 - attribute \src "libresoc.v:126183.3-126191.6" - wire $0\ren_delay$9$next[0:0]$5270 - attribute \src "libresoc.v:126070.3-126071.41" - wire $0\ren_delay$9[0:0]$5245 - attribute \src "libresoc.v:126042.7-126042.27" - wire $0\ren_delay$9[0:0]$5313 - attribute \src "libresoc.v:126126.3-126134.6" - wire $0\ren_delay$next[0:0]$5258 - attribute \src "libresoc.v:126074.3-126075.35" + attribute \src "libresoc.v:135849.3-135857.6" + wire $0\ren_delay$10$next[0:0]$5578 + attribute \src "libresoc.v:135782.3-135783.43" + wire $0\ren_delay$10[0:0]$5560 + attribute \src "libresoc.v:135748.7-135748.28" + wire $0\ren_delay$10[0:0]$5626 + attribute \src "libresoc.v:135878.3-135886.6" + wire $0\ren_delay$8$next[0:0]$5583 + attribute \src "libresoc.v:135786.3-135787.41" + wire $0\ren_delay$8[0:0]$5564 + attribute \src "libresoc.v:135752.7-135752.27" + wire $0\ren_delay$8[0:0]$5628 + attribute \src "libresoc.v:135897.3-135905.6" + wire $0\ren_delay$9$next[0:0]$5587 + attribute \src "libresoc.v:135784.3-135785.41" + wire $0\ren_delay$9[0:0]$5562 + attribute \src "libresoc.v:135756.7-135756.27" + wire $0\ren_delay$9[0:0]$5630 + attribute \src "libresoc.v:135840.3-135848.6" + wire $0\ren_delay$next[0:0]$5575 + attribute \src "libresoc.v:135788.3-135789.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:126154.3-126163.6" + attribute \src "libresoc.v:135868.3-135877.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:126173.3-126182.6" + attribute \src "libresoc.v:135887.3-135896.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:126192.3-126201.6" + attribute \src "libresoc.v:135906.3-135915.6" wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:126144.3-126153.6" + attribute \src "libresoc.v:135858.3-135867.6" wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:126135.3-126143.6" - wire $1\ren_delay$10$next[0:0]$5262 - attribute \src "libresoc.v:126164.3-126172.6" - wire $1\ren_delay$8$next[0:0]$5267 - attribute \src "libresoc.v:126183.3-126191.6" - wire $1\ren_delay$9$next[0:0]$5271 - attribute \src "libresoc.v:126126.3-126134.6" - wire $1\ren_delay$next[0:0]$5259 - attribute \src "libresoc.v:126032.7-126032.23" + attribute \src "libresoc.v:135849.3-135857.6" + wire $1\ren_delay$10$next[0:0]$5579 + attribute \src "libresoc.v:135878.3-135886.6" + wire $1\ren_delay$8$next[0:0]$5584 + attribute \src "libresoc.v:135897.3-135905.6" + wire $1\ren_delay$9$next[0:0]$5588 + attribute \src "libresoc.v:135840.3-135848.6" + wire $1\ren_delay$next[0:0]$5576 + attribute \src "libresoc.v:135746.7-135746.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:126154.3-126163.6" + attribute \src "libresoc.v:135868.3-135877.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:126173.3-126182.6" + attribute \src "libresoc.v:135887.3-135896.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:126192.3-126201.6" + attribute \src "libresoc.v:135906.3-135915.6" wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:126122.26-126122.32" - wire width 64 $memrd$\memory$libresoc.v:126122$5253_DATA - attribute \src "libresoc.v:126123.30-126123.36" - wire width 64 $memrd$\memory$libresoc.v:126123$5254_DATA - attribute \src "libresoc.v:126124.30-126124.36" - wire width 64 $memrd$\memory$libresoc.v:126124$5255_DATA - attribute \src "libresoc.v:126125.30-126125.36" - wire width 64 $memrd$\memory$libresoc.v:126125$5256_DATA + attribute \src "libresoc.v:135836.26-135836.32" + wire width 64 $memrd$\memory$libresoc.v:135836$5570_DATA + attribute \src "libresoc.v:135837.30-135837.36" + wire width 64 $memrd$\memory$libresoc.v:135837$5571_DATA + attribute \src "libresoc.v:135838.30-135838.36" + wire width 64 $memrd$\memory$libresoc.v:135838$5572_DATA + attribute \src "libresoc.v:135839.30-135839.36" + wire width 64 $memrd$\memory$libresoc.v:135839$5573_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:126120$5241_ADDR + wire width 5 $memwr$\memory$libresoc.v:135834$5558_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:126120$5241_DATA + wire width 64 $memwr$\memory$libresoc.v:135834$5558_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:126120$5241_EN - attribute \src "libresoc.v:126111.13-126111.16" + wire width 64 $memwr$\memory$libresoc.v:135834$5558_EN + attribute \src "libresoc.v:135825.13-135825.16" wire width 5 \_0_ - attribute \src "libresoc.v:126112.13-126112.16" + attribute \src "libresoc.v:135826.13-135826.16" wire width 5 \_1_ - attribute \src "libresoc.v:126113.13-126113.16" + attribute \src "libresoc.v:135827.13-135827.16" wire width 5 \_2_ - attribute \src "libresoc.v:126114.13-126114.16" + attribute \src "libresoc.v:135828.13-135828.16" wire width 5 \_3_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 15 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 16 \dest1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 2 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 4 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \dmi__ren - attribute \src "libresoc.v:125991.7-125991.15" + attribute \src "libresoc.v:135705.7-135705.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr @@ -198498,348 +214266,348 @@ module \int wire \ren_delay$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 6 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 5 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 9 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 8 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 12 \src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 11 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src3__ren - attribute \src "libresoc.v:126076.14-126076.20" + attribute \src "libresoc.v:135790.14-135790.20" memory width 64 size 32 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5273 + cell $meminit $meminit$\memory$libresoc.v:0$5590 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5273 + parameter \PRIORITY 5590 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5274 + cell $meminit $meminit$\memory$libresoc.v:0$5591 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5274 + parameter \PRIORITY 5591 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5275 + cell $meminit $meminit$\memory$libresoc.v:0$5592 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5275 + parameter \PRIORITY 5592 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5276 + cell $meminit $meminit$\memory$libresoc.v:0$5593 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5276 + parameter \PRIORITY 5593 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5277 + cell $meminit $meminit$\memory$libresoc.v:0$5594 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5277 + parameter \PRIORITY 5594 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5278 + cell $meminit $meminit$\memory$libresoc.v:0$5595 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5278 + parameter \PRIORITY 5595 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5279 + cell $meminit $meminit$\memory$libresoc.v:0$5596 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5279 + parameter \PRIORITY 5596 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5280 + cell $meminit $meminit$\memory$libresoc.v:0$5597 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5280 + parameter \PRIORITY 5597 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5281 + cell $meminit $meminit$\memory$libresoc.v:0$5598 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5281 + parameter \PRIORITY 5598 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5282 + cell $meminit $meminit$\memory$libresoc.v:0$5599 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5282 + parameter \PRIORITY 5599 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5283 + cell $meminit $meminit$\memory$libresoc.v:0$5600 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5283 + parameter \PRIORITY 5600 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5284 + cell $meminit $meminit$\memory$libresoc.v:0$5601 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5284 + parameter \PRIORITY 5601 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5285 + cell $meminit $meminit$\memory$libresoc.v:0$5602 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5285 + parameter \PRIORITY 5602 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5286 + cell $meminit $meminit$\memory$libresoc.v:0$5603 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5286 + parameter \PRIORITY 5603 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5287 + cell $meminit $meminit$\memory$libresoc.v:0$5604 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5287 + parameter \PRIORITY 5604 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5288 + cell $meminit $meminit$\memory$libresoc.v:0$5605 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5288 + parameter \PRIORITY 5605 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5289 + cell $meminit $meminit$\memory$libresoc.v:0$5606 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5289 + parameter \PRIORITY 5606 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5290 + cell $meminit $meminit$\memory$libresoc.v:0$5607 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5290 + parameter \PRIORITY 5607 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5291 + cell $meminit $meminit$\memory$libresoc.v:0$5608 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5291 + parameter \PRIORITY 5608 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5292 + cell $meminit $meminit$\memory$libresoc.v:0$5609 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5292 + parameter \PRIORITY 5609 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5293 + cell $meminit $meminit$\memory$libresoc.v:0$5610 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5293 + parameter \PRIORITY 5610 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5294 + cell $meminit $meminit$\memory$libresoc.v:0$5611 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5294 + parameter \PRIORITY 5611 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5295 + cell $meminit $meminit$\memory$libresoc.v:0$5612 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5295 + parameter \PRIORITY 5612 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5296 + cell $meminit $meminit$\memory$libresoc.v:0$5613 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5296 + parameter \PRIORITY 5613 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5297 + cell $meminit $meminit$\memory$libresoc.v:0$5614 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5297 + parameter \PRIORITY 5614 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5298 + cell $meminit $meminit$\memory$libresoc.v:0$5615 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5298 + parameter \PRIORITY 5615 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5299 + cell $meminit $meminit$\memory$libresoc.v:0$5616 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5299 + parameter \PRIORITY 5616 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5300 + cell $meminit $meminit$\memory$libresoc.v:0$5617 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5300 + parameter \PRIORITY 5617 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5301 + cell $meminit $meminit$\memory$libresoc.v:0$5618 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5301 + parameter \PRIORITY 5618 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5302 + cell $meminit $meminit$\memory$libresoc.v:0$5619 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5302 + parameter \PRIORITY 5619 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5303 + cell $meminit $meminit$\memory$libresoc.v:0$5620 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5303 + parameter \PRIORITY 5620 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5304 + cell $meminit $meminit$\memory$libresoc.v:0$5621 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5304 + parameter \PRIORITY 5621 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:126122.26-126122.32" - cell $memrd $memrd$\memory$libresoc.v:126122$5253 + attribute \src "libresoc.v:135836.26-135836.32" + cell $memrd $memrd$\memory$libresoc.v:135836$5570 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -198848,11 +214616,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:126122$5253_DATA + connect \DATA $memrd$\memory$libresoc.v:135836$5570_DATA connect \EN 1'x end - attribute \src "libresoc.v:126123.30-126123.36" - cell $memrd $memrd$\memory$libresoc.v:126123$5254 + attribute \src "libresoc.v:135837.30-135837.36" + cell $memrd $memrd$\memory$libresoc.v:135837$5571 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -198861,11 +214629,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:126123$5254_DATA + connect \DATA $memrd$\memory$libresoc.v:135837$5571_DATA connect \EN 1'x end - attribute \src "libresoc.v:126124.30-126124.36" - cell $memrd $memrd$\memory$libresoc.v:126124$5255 + attribute \src "libresoc.v:135838.30-135838.36" + cell $memrd $memrd$\memory$libresoc.v:135838$5572 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -198874,11 +214642,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:126124$5255_DATA + connect \DATA $memrd$\memory$libresoc.v:135838$5572_DATA connect \EN 1'x end - attribute \src "libresoc.v:126125.30-126125.36" - cell $memrd $memrd$\memory$libresoc.v:126125$5256 + attribute \src "libresoc.v:135839.30-135839.36" + cell $memrd $memrd$\memory$libresoc.v:135839$5573 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -198887,97 +214655,97 @@ module \int parameter \WIDTH 64 connect \ADDR \_3_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:126125$5256_DATA + connect \DATA $memrd$\memory$libresoc.v:135839$5573_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5305 + cell $memwr $memwr$\memory$libresoc.v:0$5622 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5305 + parameter \PRIORITY 5622 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:126120$5241_ADDR + connect \ADDR $memwr$\memory$libresoc.v:135834$5558_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:126120$5241_DATA - connect \EN $memwr$\memory$libresoc.v:126120$5241_EN + connect \DATA $memwr$\memory$libresoc.v:135834$5558_DATA + connect \EN $memwr$\memory$libresoc.v:135834$5558_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5314 + process $proc$libresoc.v:0$5631 sync always sync init end - attribute \src "libresoc.v:125991.7-125991.20" - process $proc$libresoc.v:125991$5306 + attribute \src "libresoc.v:135705.7-135705.20" + process $proc$libresoc.v:135705$5623 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126032.7-126032.23" - process $proc$libresoc.v:126032$5307 + attribute \src "libresoc.v:135746.7-135746.23" + process $proc$libresoc.v:135746$5624 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:126034.7-126034.28" - process $proc$libresoc.v:126034$5308 + attribute \src "libresoc.v:135748.7-135748.28" + process $proc$libresoc.v:135748$5625 assign { } { } - assign $0\ren_delay$10[0:0]$5309 1'0 + assign $0\ren_delay$10[0:0]$5626 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5309 + update \ren_delay$10 $0\ren_delay$10[0:0]$5626 end - attribute \src "libresoc.v:126038.7-126038.27" - process $proc$libresoc.v:126038$5310 + attribute \src "libresoc.v:135752.7-135752.27" + process $proc$libresoc.v:135752$5627 assign { } { } - assign $0\ren_delay$8[0:0]$5311 1'0 + assign $0\ren_delay$8[0:0]$5628 1'0 sync always sync init - update \ren_delay$8 $0\ren_delay$8[0:0]$5311 + update \ren_delay$8 $0\ren_delay$8[0:0]$5628 end - attribute \src "libresoc.v:126042.7-126042.27" - process $proc$libresoc.v:126042$5312 + attribute \src "libresoc.v:135756.7-135756.27" + process $proc$libresoc.v:135756$5629 assign { } { } - assign $0\ren_delay$9[0:0]$5313 1'0 + assign $0\ren_delay$9[0:0]$5630 1'0 sync always sync init - update \ren_delay$9 $0\ren_delay$9[0:0]$5313 + update \ren_delay$9 $0\ren_delay$9[0:0]$5630 end - attribute \src "libresoc.v:126068.3-126069.43" - process $proc$libresoc.v:126068$5242 + attribute \src "libresoc.v:135782.3-135783.43" + process $proc$libresoc.v:135782$5559 assign { } { } - assign $0\ren_delay$10[0:0]$5243 \ren_delay$10$next + assign $0\ren_delay$10[0:0]$5560 \ren_delay$10$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5243 + update \ren_delay$10 $0\ren_delay$10[0:0]$5560 end - attribute \src "libresoc.v:126070.3-126071.41" - process $proc$libresoc.v:126070$5244 + attribute \src "libresoc.v:135784.3-135785.41" + process $proc$libresoc.v:135784$5561 assign { } { } - assign $0\ren_delay$9[0:0]$5245 \ren_delay$9$next + assign $0\ren_delay$9[0:0]$5562 \ren_delay$9$next sync posedge \coresync_clk - update \ren_delay$9 $0\ren_delay$9[0:0]$5245 + update \ren_delay$9 $0\ren_delay$9[0:0]$5562 end - attribute \src "libresoc.v:126072.3-126073.41" - process $proc$libresoc.v:126072$5246 + attribute \src "libresoc.v:135786.3-135787.41" + process $proc$libresoc.v:135786$5563 assign { } { } - assign $0\ren_delay$8[0:0]$5247 \ren_delay$8$next + assign $0\ren_delay$8[0:0]$5564 \ren_delay$8$next sync posedge \coresync_clk - update \ren_delay$8 $0\ren_delay$8[0:0]$5247 + update \ren_delay$8 $0\ren_delay$8[0:0]$5564 end - attribute \src "libresoc.v:126074.3-126075.35" - process $proc$libresoc.v:126074$5248 + attribute \src "libresoc.v:135788.3-135789.35" + process $proc$libresoc.v:135788$5565 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:126115.3-126121.6" - process $proc$libresoc.v:126115$5249 + attribute \src "libresoc.v:135829.3-135835.6" + process $proc$libresoc.v:135829$5566 assign { } { } assign { } { } assign { } { } @@ -198985,20 +214753,20 @@ module \int assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:126120$5241_ADDR[4:0]$5250 5'xxxxx - assign $0$memwr$\memory$libresoc.v:126120$5241_DATA[63:0]$5251 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:126120$5241_EN[63:0]$5252 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 5'xxxxx + assign $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[4:0] \src1__addr assign $0\_1_[4:0] \src2__addr assign $0\_2_[4:0] \src3__addr assign $0\_3_[4:0] \dmi__addr - attribute \src "libresoc.v:126120.5-126120.58" + attribute \src "libresoc.v:135834.5-135834.58" switch \dest1__wen - attribute \src "libresoc.v:126120.9-126120.19" + attribute \src "libresoc.v:135834.9-135834.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:126120$5241_ADDR[4:0]$5250 \dest1__addr - assign $0$memwr$\memory$libresoc.v:126120$5241_DATA[63:0]$5251 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:126120$5241_EN[63:0]$5252 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 \dest1__addr + assign $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk @@ -199006,18 +214774,18 @@ module \int update \_1_ $0\_1_[4:0] update \_2_ $0\_2_[4:0] update \_3_ $0\_3_[4:0] - update $memwr$\memory$libresoc.v:126120$5241_ADDR $0$memwr$\memory$libresoc.v:126120$5241_ADDR[4:0]$5250 - update $memwr$\memory$libresoc.v:126120$5241_DATA $0$memwr$\memory$libresoc.v:126120$5241_DATA[63:0]$5251 - update $memwr$\memory$libresoc.v:126120$5241_EN $0$memwr$\memory$libresoc.v:126120$5241_EN[63:0]$5252 + update $memwr$\memory$libresoc.v:135834$5558_ADDR $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 + update $memwr$\memory$libresoc.v:135834$5558_DATA $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 + update $memwr$\memory$libresoc.v:135834$5558_EN $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 end - attribute \src "libresoc.v:126126.3-126134.6" - process $proc$libresoc.v:126126$5257 + attribute \src "libresoc.v:135840.3-135848.6" + process $proc$libresoc.v:135840$5574 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5258 $1\ren_delay$next[0:0]$5259 - attribute \src "libresoc.v:126127.5-126127.29" + assign $0\ren_delay$next[0:0]$5575 $1\ren_delay$next[0:0]$5576 + attribute \src "libresoc.v:135841.5-135841.29" switch \initial - attribute \src "libresoc.v:126127.9-126127.17" + attribute \src "libresoc.v:135841.9-135841.17" case 1'1 case end @@ -199026,21 +214794,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5259 1'0 + assign $1\ren_delay$next[0:0]$5576 1'0 case - assign $1\ren_delay$next[0:0]$5259 \src1__ren + assign $1\ren_delay$next[0:0]$5576 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5258 + update \ren_delay$next $0\ren_delay$next[0:0]$5575 end - attribute \src "libresoc.v:126135.3-126143.6" - process $proc$libresoc.v:126135$5260 + attribute \src "libresoc.v:135849.3-135857.6" + process $proc$libresoc.v:135849$5577 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5261 $1\ren_delay$10$next[0:0]$5262 - attribute \src "libresoc.v:126136.5-126136.29" + assign $0\ren_delay$10$next[0:0]$5578 $1\ren_delay$10$next[0:0]$5579 + attribute \src "libresoc.v:135850.5-135850.29" switch \initial - attribute \src "libresoc.v:126136.9-126136.17" + attribute \src "libresoc.v:135850.9-135850.17" case 1'1 case end @@ -199049,21 +214817,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5262 1'0 + assign $1\ren_delay$10$next[0:0]$5579 1'0 case - assign $1\ren_delay$10$next[0:0]$5262 \dmi__ren + assign $1\ren_delay$10$next[0:0]$5579 \dmi__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5261 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5578 end - attribute \src "libresoc.v:126144.3-126153.6" - process $proc$libresoc.v:126144$5263 + attribute \src "libresoc.v:135858.3-135867.6" + process $proc$libresoc.v:135858$5580 assign { } { } assign { } { } assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:126145.5-126145.29" + attribute \src "libresoc.v:135859.5-135859.29" switch \initial - attribute \src "libresoc.v:126145.9-126145.17" + attribute \src "libresoc.v:135859.9-135859.17" case 1'1 case end @@ -199079,14 +214847,14 @@ module \int sync always update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:126154.3-126163.6" - process $proc$libresoc.v:126154$5264 + attribute \src "libresoc.v:135868.3-135877.6" + process $proc$libresoc.v:135868$5581 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:126155.5-126155.29" + attribute \src "libresoc.v:135869.5-135869.29" switch \initial - attribute \src "libresoc.v:126155.9-126155.17" + attribute \src "libresoc.v:135869.9-135869.17" case 1'1 case end @@ -199102,14 +214870,14 @@ module \int sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:126164.3-126172.6" - process $proc$libresoc.v:126164$5265 + attribute \src "libresoc.v:135878.3-135886.6" + process $proc$libresoc.v:135878$5582 assign { } { } assign { } { } - assign $0\ren_delay$8$next[0:0]$5266 $1\ren_delay$8$next[0:0]$5267 - attribute \src "libresoc.v:126165.5-126165.29" + assign $0\ren_delay$8$next[0:0]$5583 $1\ren_delay$8$next[0:0]$5584 + attribute \src "libresoc.v:135879.5-135879.29" switch \initial - attribute \src "libresoc.v:126165.9-126165.17" + attribute \src "libresoc.v:135879.9-135879.17" case 1'1 case end @@ -199118,21 +214886,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$8$next[0:0]$5267 1'0 + assign $1\ren_delay$8$next[0:0]$5584 1'0 case - assign $1\ren_delay$8$next[0:0]$5267 \src2__ren + assign $1\ren_delay$8$next[0:0]$5584 \src2__ren end sync always - update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5266 + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5583 end - attribute \src "libresoc.v:126173.3-126182.6" - process $proc$libresoc.v:126173$5268 + attribute \src "libresoc.v:135887.3-135896.6" + process $proc$libresoc.v:135887$5585 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:126174.5-126174.29" + attribute \src "libresoc.v:135888.5-135888.29" switch \initial - attribute \src "libresoc.v:126174.9-126174.17" + attribute \src "libresoc.v:135888.9-135888.17" case 1'1 case end @@ -199148,14 +214916,14 @@ module \int sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:126183.3-126191.6" - process $proc$libresoc.v:126183$5269 + attribute \src "libresoc.v:135897.3-135905.6" + process $proc$libresoc.v:135897$5586 assign { } { } assign { } { } - assign $0\ren_delay$9$next[0:0]$5270 $1\ren_delay$9$next[0:0]$5271 - attribute \src "libresoc.v:126184.5-126184.29" + assign $0\ren_delay$9$next[0:0]$5587 $1\ren_delay$9$next[0:0]$5588 + attribute \src "libresoc.v:135898.5-135898.29" switch \initial - attribute \src "libresoc.v:126184.9-126184.17" + attribute \src "libresoc.v:135898.9-135898.17" case 1'1 case end @@ -199164,21 +214932,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$9$next[0:0]$5271 1'0 + assign $1\ren_delay$9$next[0:0]$5588 1'0 case - assign $1\ren_delay$9$next[0:0]$5271 \src3__ren + assign $1\ren_delay$9$next[0:0]$5588 \src3__ren end sync always - update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5270 + update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5587 end - attribute \src "libresoc.v:126192.3-126201.6" - process $proc$libresoc.v:126192$5272 + attribute \src "libresoc.v:135906.3-135915.6" + process $proc$libresoc.v:135906$5589 assign { } { } assign { } { } assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:126193.5-126193.29" + attribute \src "libresoc.v:135907.5-135907.29" switch \initial - attribute \src "libresoc.v:126193.9-126193.17" + attribute \src "libresoc.v:135907.9-135907.17" case 1'1 case end @@ -199194,10 +214962,10 @@ module \int sync always update \src3__data_o $0\src3__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:126122$5253_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:126123$5254_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:126124$5255_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:126125$5256_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:135836$5570_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:135837$5571_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:135838$5572_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:135839$5573_DATA connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr @@ -199206,915 +214974,925 @@ module \int connect \memory_r_addr$2 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:126213.1-128927.10" +attribute \src "libresoc.v:135927.1-138650.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:128359.3-128385.6" + attribute \src "libresoc.v:138080.3-138106.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:128007.3-128022.6" + attribute \src "libresoc.v:137728.3-137743.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:128520.3-128552.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$5725 - attribute \src "libresoc.v:127910.3-127911.41" + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6043 + attribute \src "libresoc.v:137631.3-137632.41" wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:128606.3-128632.6" - wire width 64 $0\dmi0__din$next[63:0]$5738 - attribute \src "libresoc.v:127906.3-127907.35" + attribute \src "libresoc.v:138327.3-138353.6" + wire width 64 $0\dmi0__din$next[63:0]$6056 + attribute \src "libresoc.v:137627.3-137628.35" wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:128209.3-128225.6" - wire $0\dmi0_addrsr__oe$next[0:0]$5662 - attribute \src "libresoc.v:127938.3-127939.47" + attribute \src "libresoc.v:137930.3-137946.6" + wire $0\dmi0_addrsr__oe$next[0:0]$5980 + attribute \src "libresoc.v:137659.3-137660.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:128226.3-128246.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5666 - attribute \src "libresoc.v:127936.3-127937.47" + attribute \src "libresoc.v:137947.3-137967.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5984 + attribute \src "libresoc.v:137657.3-137658.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:128191.3-128199.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$5656 - attribute \src "libresoc.v:127942.3-127943.63" + attribute \src "libresoc.v:137912.3-137920.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$5974 + attribute \src "libresoc.v:137663.3-137664.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:128200.3-128208.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5659 - attribute \src "libresoc.v:127940.3-127941.73" + attribute \src "libresoc.v:137921.3-137929.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 + attribute \src "libresoc.v:137661.3-137662.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:128633.3-128653.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$5743 - attribute \src "libresoc.v:127904.3-127905.45" + attribute \src "libresoc.v:138354.3-138374.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6061 + attribute \src "libresoc.v:137625.3-137626.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:128265.3-128281.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$5677 - attribute \src "libresoc.v:127930.3-127931.47" + attribute \src "libresoc.v:137986.3-138002.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$5995 + attribute \src "libresoc.v:137651.3-137652.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:128282.3-128302.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$5681 - attribute \src "libresoc.v:127928.3-127929.47" + attribute \src "libresoc.v:138003.3-138023.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$5999 + attribute \src "libresoc.v:137649.3-137650.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:128247.3-128255.6" - wire $0\dmi0_datasr_update_core$next[0:0]$5671 - attribute \src "libresoc.v:127934.3-127935.63" + attribute \src "libresoc.v:137968.3-137976.6" + wire $0\dmi0_datasr_update_core$next[0:0]$5989 + attribute \src "libresoc.v:137655.3-137656.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:128256.3-128264.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$5674 - attribute \src "libresoc.v:127932.3-127933.73" + attribute \src "libresoc.v:137977.3-137985.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$5992 + attribute \src "libresoc.v:137653.3-137654.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:128553.3-128605.6" - wire width 3 $0\fsm_state$503$next[2:0]$5731 - attribute \src "libresoc.v:127908.3-127909.45" - wire width 3 $0\fsm_state$503[2:0]$5577 - attribute \src "libresoc.v:126859.13-126859.35" - wire width 3 $0\fsm_state$503[2:0]$5777 - attribute \src "libresoc.v:128419.3-128471.6" - wire width 3 $0\fsm_state$next[2:0]$5708 - attribute \src "libresoc.v:127916.3-127917.35" + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $0\fsm_state$503$next[2:0]$6049 + attribute \src "libresoc.v:137629.3-137630.45" + wire width 3 $0\fsm_state$503[2:0]$5895 + attribute \src "libresoc.v:136573.13-136573.35" + wire width 3 $0\fsm_state$503[2:0]$6098 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $0\fsm_state$next[2:0]$6026 + attribute \src "libresoc.v:137637.3-137638.35" wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:126214.7-126214.20" + attribute \src "libresoc.v:135928.7-135928.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128701.3-128721.6" - wire width 154 $0\io_bd$next[153:0]$5760 - attribute \src "libresoc.v:127968.3-127969.27" + attribute \src "libresoc.v:138424.3-138444.6" + wire width 154 $0\io_bd$next[153:0]$6081 + attribute \src "libresoc.v:137689.3-137690.27" wire width 154 $0\io_bd[153:0] - attribute \src "libresoc.v:128683.3-128700.6" - wire width 154 $0\io_sr$next[153:0]$5756 - attribute \src "libresoc.v:127970.3-127971.27" + attribute \src "libresoc.v:138406.3-138423.6" + wire width 154 $0\io_sr$next[153:0]$6077 + attribute \src "libresoc.v:137691.3-137692.27" wire width 154 $0\io_sr[153:0] - attribute \src "libresoc.v:128386.3-128418.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$5702 - attribute \src "libresoc.v:127918.3-127919.41" + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6020 + attribute \src "libresoc.v:137639.3-137640.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:128472.3-128498.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$5715 - attribute \src "libresoc.v:127914.3-127915.45" + attribute \src "libresoc.v:138193.3-138219.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6033 + attribute \src "libresoc.v:137635.3-137636.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:128097.3-128113.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5632 - attribute \src "libresoc.v:127954.3-127955.53" + attribute \src "libresoc.v:137818.3-137834.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5950 + attribute \src "libresoc.v:137675.3-137676.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:128114.3-128134.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5636 - attribute \src "libresoc.v:127952.3-127953.53" + attribute \src "libresoc.v:137835.3-137855.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5954 + attribute \src "libresoc.v:137673.3-137674.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:128079.3-128087.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5626 - attribute \src "libresoc.v:127958.3-127959.69" + attribute \src "libresoc.v:137800.3-137808.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5944 + attribute \src "libresoc.v:137679.3-137680.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:128088.3-128096.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5629 - attribute \src "libresoc.v:127956.3-127957.79" + attribute \src "libresoc.v:137809.3-137817.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 + attribute \src "libresoc.v:137677.3-137678.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:128499.3-128519.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$5720 - attribute \src "libresoc.v:127912.3-127913.51" + attribute \src "libresoc.v:138220.3-138240.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6038 + attribute \src "libresoc.v:137633.3-137634.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:128153.3-128169.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5647 - attribute \src "libresoc.v:127946.3-127947.53" + attribute \src "libresoc.v:137874.3-137890.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5965 + attribute \src "libresoc.v:137667.3-137668.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:128170.3-128190.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5651 - attribute \src "libresoc.v:127944.3-127945.53" + attribute \src "libresoc.v:137891.3-137911.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5969 + attribute \src "libresoc.v:137665.3-137666.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:128135.3-128143.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$5641 - attribute \src "libresoc.v:127950.3-127951.69" + attribute \src "libresoc.v:137856.3-137864.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$5959 + attribute \src "libresoc.v:137671.3-137672.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:128144.3-128152.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5644 - attribute \src "libresoc.v:127948.3-127949.79" + attribute \src "libresoc.v:137865.3-137873.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 + attribute \src "libresoc.v:137669.3-137670.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:128041.3-128057.6" - wire $0\sr0__oe$next[0:0]$5617 - attribute \src "libresoc.v:127962.3-127963.31" + attribute \src "libresoc.v:137762.3-137778.6" + wire $0\sr0__oe$next[0:0]$5935 + attribute \src "libresoc.v:137683.3-137684.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:128058.3-128078.6" - wire width 3 $0\sr0_reg$next[2:0]$5621 - attribute \src "libresoc.v:127960.3-127961.31" + attribute \src "libresoc.v:137779.3-137799.6" + wire width 3 $0\sr0_reg$next[2:0]$5939 + attribute \src "libresoc.v:137681.3-137682.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:128023.3-128031.6" - wire $0\sr0_update_core$next[0:0]$5611 - attribute \src "libresoc.v:127966.3-127967.47" + attribute \src "libresoc.v:137744.3-137752.6" + wire $0\sr0_update_core$next[0:0]$5929 + attribute \src "libresoc.v:137687.3-137688.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:128032.3-128040.6" - wire $0\sr0_update_core_prev$next[0:0]$5614 - attribute \src "libresoc.v:127964.3-127965.57" + attribute \src "libresoc.v:137753.3-137761.6" + wire $0\sr0_update_core_prev$next[0:0]$5932 + attribute \src "libresoc.v:137685.3-137686.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:128673.3-128682.6" - wire width 2 $0\sr5__i[1:0] - attribute \src "libresoc.v:128321.3-128337.6" - wire $0\sr5__oe$next[0:0]$5692 - attribute \src "libresoc.v:127922.3-127923.31" + attribute \src "libresoc.v:138396.3-138405.6" + wire width 3 $0\sr5__i[2:0] + attribute \src "libresoc.v:138042.3-138058.6" + wire $0\sr5__oe$next[0:0]$6010 + attribute \src "libresoc.v:137643.3-137644.31" wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:128338.3-128358.6" - wire width 2 $0\sr5_reg$next[1:0]$5696 - attribute \src "libresoc.v:127920.3-127921.31" - wire width 2 $0\sr5_reg[1:0] - attribute \src "libresoc.v:128303.3-128311.6" - wire $0\sr5_update_core$next[0:0]$5686 - attribute \src "libresoc.v:127926.3-127927.47" + attribute \src "libresoc.v:138059.3-138079.6" + wire width 3 $0\sr5_reg$next[2:0]$6014 + attribute \src "libresoc.v:137641.3-137642.31" + wire width 3 $0\sr5_reg[2:0] + attribute \src "libresoc.v:138024.3-138032.6" + wire $0\sr5_update_core$next[0:0]$6004 + attribute \src "libresoc.v:137647.3-137648.47" wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:128312.3-128320.6" - wire $0\sr5_update_core_prev$next[0:0]$5689 - attribute \src "libresoc.v:127924.3-127925.57" + attribute \src "libresoc.v:138033.3-138041.6" + wire $0\sr5_update_core_prev$next[0:0]$6007 + attribute \src "libresoc.v:137645.3-137646.57" wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:128654.3-128672.6" - wire $0\wb_dcache_en$next[0:0]$5748 - attribute \src "libresoc.v:127902.3-127903.41" + attribute \src "libresoc.v:138375.3-138395.6" + wire $0\wb_dcache_en$next[0:0]$6066 + attribute \src "libresoc.v:137621.3-137622.41" wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:128654.3-128672.6" - wire $0\wb_icache_en$next[0:0]$5749 - attribute \src "libresoc.v:127900.3-127901.41" + attribute \src "libresoc.v:138375.3-138395.6" + wire $0\wb_icache_en$next[0:0]$6067 + attribute \src "libresoc.v:137619.3-137620.41" wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:128359.3-128385.6" + attribute \src "libresoc.v:138375.3-138395.6" + wire $0\wb_sram_en$next[0:0]$6068 + attribute \src "libresoc.v:137623.3-137624.37" + wire $0\wb_sram_en[0:0] + attribute \src "libresoc.v:138080.3-138106.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:128007.3-128022.6" + attribute \src "libresoc.v:137728.3-137743.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:128520.3-128552.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$5726 - attribute \src "libresoc.v:126772.13-126772.32" + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6044 + attribute \src "libresoc.v:136486.13-136486.32" wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:128606.3-128632.6" - wire width 64 $1\dmi0__din$next[63:0]$5739 - attribute \src "libresoc.v:126777.14-126777.46" + attribute \src "libresoc.v:138327.3-138353.6" + wire width 64 $1\dmi0__din$next[63:0]$6057 + attribute \src "libresoc.v:136491.14-136491.46" wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:128209.3-128225.6" - wire $1\dmi0_addrsr__oe$next[0:0]$5663 - attribute \src "libresoc.v:126791.7-126791.29" + attribute \src "libresoc.v:137930.3-137946.6" + wire $1\dmi0_addrsr__oe$next[0:0]$5981 + attribute \src "libresoc.v:136505.7-136505.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:128226.3-128246.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5667 - attribute \src "libresoc.v:126799.13-126799.36" + attribute \src "libresoc.v:137947.3-137967.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5985 + attribute \src "libresoc.v:136513.13-136513.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:128191.3-128199.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$5657 - attribute \src "libresoc.v:126807.7-126807.37" + attribute \src "libresoc.v:137912.3-137920.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$5975 + attribute \src "libresoc.v:136521.7-136521.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:128200.3-128208.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5660 - attribute \src "libresoc.v:126811.7-126811.42" + attribute \src "libresoc.v:137921.3-137929.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 + attribute \src "libresoc.v:136525.7-136525.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:128633.3-128653.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$5744 - attribute \src "libresoc.v:126815.14-126815.51" + attribute \src "libresoc.v:138354.3-138374.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6062 + attribute \src "libresoc.v:136529.14-136529.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:128265.3-128281.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$5678 - attribute \src "libresoc.v:126821.13-126821.35" + attribute \src "libresoc.v:137986.3-138002.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$5996 + attribute \src "libresoc.v:136535.13-136535.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:128282.3-128302.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$5682 - attribute \src "libresoc.v:126829.14-126829.52" + attribute \src "libresoc.v:138003.3-138023.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$6000 + attribute \src "libresoc.v:136543.14-136543.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:128247.3-128255.6" - wire $1\dmi0_datasr_update_core$next[0:0]$5672 - attribute \src "libresoc.v:126837.7-126837.37" + attribute \src "libresoc.v:137968.3-137976.6" + wire $1\dmi0_datasr_update_core$next[0:0]$5990 + attribute \src "libresoc.v:136551.7-136551.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:128256.3-128264.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$5675 - attribute \src "libresoc.v:126841.7-126841.42" + attribute \src "libresoc.v:137977.3-137985.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$5993 + attribute \src "libresoc.v:136555.7-136555.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:128553.3-128605.6" - wire width 3 $1\fsm_state$503$next[2:0]$5732 - attribute \src "libresoc.v:128419.3-128471.6" - wire width 3 $1\fsm_state$next[2:0]$5709 - attribute \src "libresoc.v:126857.13-126857.29" + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $1\fsm_state$503$next[2:0]$6050 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $1\fsm_state$next[2:0]$6027 + attribute \src "libresoc.v:136571.13-136571.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:128701.3-128721.6" - wire width 154 $1\io_bd$next[153:0]$5761 - attribute \src "libresoc.v:127057.15-127057.67" + attribute \src "libresoc.v:138424.3-138444.6" + wire width 154 $1\io_bd$next[153:0]$6082 + attribute \src "libresoc.v:136771.15-136771.67" wire width 154 $1\io_bd[153:0] - attribute \src "libresoc.v:128683.3-128700.6" - wire width 154 $1\io_sr$next[153:0]$5757 - attribute \src "libresoc.v:127069.15-127069.67" + attribute \src "libresoc.v:138406.3-138423.6" + wire width 154 $1\io_sr$next[153:0]$6078 + attribute \src "libresoc.v:136783.15-136783.67" wire width 154 $1\io_sr[153:0] - attribute \src "libresoc.v:128386.3-128418.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$5703 - attribute \src "libresoc.v:127078.14-127078.41" + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6021 + attribute \src "libresoc.v:136792.14-136792.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:128472.3-128498.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$5716 - attribute \src "libresoc.v:127087.14-127087.51" + attribute \src "libresoc.v:138193.3-138219.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6034 + attribute \src "libresoc.v:136801.14-136801.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:128097.3-128113.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5633 - attribute \src "libresoc.v:127101.7-127101.32" + attribute \src "libresoc.v:137818.3-137834.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5951 + attribute \src "libresoc.v:136815.7-136815.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:128114.3-128134.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5637 - attribute \src "libresoc.v:127109.14-127109.47" + attribute \src "libresoc.v:137835.3-137855.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5955 + attribute \src "libresoc.v:136823.14-136823.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:128079.3-128087.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5627 - attribute \src "libresoc.v:127117.7-127117.40" + attribute \src "libresoc.v:137800.3-137808.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5945 + attribute \src "libresoc.v:136831.7-136831.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:128088.3-128096.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5630 - attribute \src "libresoc.v:127121.7-127121.45" + attribute \src "libresoc.v:137809.3-137817.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 + attribute \src "libresoc.v:136835.7-136835.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:128499.3-128519.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$5721 - attribute \src "libresoc.v:127125.14-127125.54" + attribute \src "libresoc.v:138220.3-138240.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6039 + attribute \src "libresoc.v:136839.14-136839.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:128153.3-128169.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5648 - attribute \src "libresoc.v:127131.13-127131.38" + attribute \src "libresoc.v:137874.3-137890.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5966 + attribute \src "libresoc.v:136845.13-136845.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:128170.3-128190.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5652 - attribute \src "libresoc.v:127139.14-127139.55" + attribute \src "libresoc.v:137891.3-137911.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5970 + attribute \src "libresoc.v:136853.14-136853.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:128135.3-128143.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$5642 - attribute \src "libresoc.v:127147.7-127147.40" + attribute \src "libresoc.v:137856.3-137864.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$5960 + attribute \src "libresoc.v:136861.7-136861.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:128144.3-128152.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5645 - attribute \src "libresoc.v:127151.7-127151.45" + attribute \src "libresoc.v:137865.3-137873.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 + attribute \src "libresoc.v:136865.7-136865.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:128041.3-128057.6" - wire $1\sr0__oe$next[0:0]$5618 - attribute \src "libresoc.v:127581.7-127581.21" + attribute \src "libresoc.v:137762.3-137778.6" + wire $1\sr0__oe$next[0:0]$5936 + attribute \src "libresoc.v:137295.7-137295.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:128058.3-128078.6" - wire width 3 $1\sr0_reg$next[2:0]$5622 - attribute \src "libresoc.v:127589.13-127589.27" + attribute \src "libresoc.v:137779.3-137799.6" + wire width 3 $1\sr0_reg$next[2:0]$5940 + attribute \src "libresoc.v:137303.13-137303.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:128023.3-128031.6" - wire $1\sr0_update_core$next[0:0]$5612 - attribute \src "libresoc.v:127597.7-127597.29" + attribute \src "libresoc.v:137744.3-137752.6" + wire $1\sr0_update_core$next[0:0]$5930 + attribute \src "libresoc.v:137311.7-137311.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:128032.3-128040.6" - wire $1\sr0_update_core_prev$next[0:0]$5615 - attribute \src "libresoc.v:127601.7-127601.34" + attribute \src "libresoc.v:137753.3-137761.6" + wire $1\sr0_update_core_prev$next[0:0]$5933 + attribute \src "libresoc.v:137315.7-137315.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:128673.3-128682.6" - wire width 2 $1\sr5__i[1:0] - attribute \src "libresoc.v:128321.3-128337.6" - wire $1\sr5__oe$next[0:0]$5693 - attribute \src "libresoc.v:127611.7-127611.21" + attribute \src "libresoc.v:138396.3-138405.6" + wire width 3 $1\sr5__i[2:0] + attribute \src "libresoc.v:138042.3-138058.6" + wire $1\sr5__oe$next[0:0]$6011 + attribute \src "libresoc.v:137325.7-137325.21" wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:128338.3-128358.6" - wire width 2 $1\sr5_reg$next[1:0]$5697 - attribute \src "libresoc.v:127619.13-127619.27" - wire width 2 $1\sr5_reg[1:0] - attribute \src "libresoc.v:128303.3-128311.6" - wire $1\sr5_update_core$next[0:0]$5687 - attribute \src "libresoc.v:127627.7-127627.29" + attribute \src "libresoc.v:138059.3-138079.6" + wire width 3 $1\sr5_reg$next[2:0]$6015 + attribute \src "libresoc.v:137333.13-137333.27" + wire width 3 $1\sr5_reg[2:0] + attribute \src "libresoc.v:138024.3-138032.6" + wire $1\sr5_update_core$next[0:0]$6005 + attribute \src "libresoc.v:137341.7-137341.29" wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:128312.3-128320.6" - wire $1\sr5_update_core_prev$next[0:0]$5690 - attribute \src "libresoc.v:127631.7-127631.34" + attribute \src "libresoc.v:138033.3-138041.6" + wire $1\sr5_update_core_prev$next[0:0]$6008 + attribute \src "libresoc.v:137345.7-137345.34" wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:128654.3-128672.6" - wire $1\wb_dcache_en$next[0:0]$5750 - attribute \src "libresoc.v:127636.7-127636.26" + attribute \src "libresoc.v:138375.3-138395.6" + wire $1\wb_dcache_en$next[0:0]$6069 + attribute \src "libresoc.v:137350.7-137350.26" wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:128654.3-128672.6" - wire $1\wb_icache_en$next[0:0]$5751 - attribute \src "libresoc.v:127641.7-127641.26" + attribute \src "libresoc.v:138375.3-138395.6" + wire $1\wb_icache_en$next[0:0]$6070 + attribute \src "libresoc.v:137355.7-137355.26" wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:128520.3-128552.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$5727 - attribute \src "libresoc.v:128606.3-128632.6" - wire width 64 $2\dmi0__din$next[63:0]$5740 - attribute \src "libresoc.v:128209.3-128225.6" - wire $2\dmi0_addrsr__oe$next[0:0]$5664 - attribute \src "libresoc.v:128226.3-128246.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5668 - attribute \src "libresoc.v:128633.3-128653.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$5745 - attribute \src "libresoc.v:128265.3-128281.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$5679 - attribute \src "libresoc.v:128282.3-128302.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$5683 - attribute \src "libresoc.v:128553.3-128605.6" - wire width 3 $2\fsm_state$503$next[2:0]$5733 - attribute \src "libresoc.v:128419.3-128471.6" - wire width 3 $2\fsm_state$next[2:0]$5710 - attribute \src "libresoc.v:128701.3-128721.6" - wire width 154 $2\io_bd$next[153:0]$5762 - attribute \src "libresoc.v:128683.3-128700.6" - wire width 154 $2\io_sr$next[153:0]$5758 - attribute \src "libresoc.v:128386.3-128418.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$5704 - attribute \src "libresoc.v:128472.3-128498.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$5717 - attribute \src "libresoc.v:128097.3-128113.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$5634 - attribute \src "libresoc.v:128114.3-128134.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5638 - attribute \src "libresoc.v:128499.3-128519.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$5722 - attribute \src "libresoc.v:128153.3-128169.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5649 - attribute \src "libresoc.v:128170.3-128190.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5653 - attribute \src "libresoc.v:128041.3-128057.6" - wire $2\sr0__oe$next[0:0]$5619 - attribute \src "libresoc.v:128058.3-128078.6" - wire width 3 $2\sr0_reg$next[2:0]$5623 - attribute \src "libresoc.v:128321.3-128337.6" - wire $2\sr5__oe$next[0:0]$5694 - attribute \src "libresoc.v:128338.3-128358.6" - wire width 2 $2\sr5_reg$next[1:0]$5698 - attribute \src "libresoc.v:128654.3-128672.6" - wire $2\wb_dcache_en$next[0:0]$5752 - attribute \src "libresoc.v:128654.3-128672.6" - wire $2\wb_icache_en$next[0:0]$5753 - attribute \src "libresoc.v:128520.3-128552.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$5728 - attribute \src "libresoc.v:128606.3-128632.6" - wire width 64 $3\dmi0__din$next[63:0]$5741 - attribute \src "libresoc.v:128226.3-128246.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5669 - attribute \src "libresoc.v:128633.3-128653.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$5746 - attribute \src "libresoc.v:128282.3-128302.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$5684 - attribute \src "libresoc.v:128553.3-128605.6" - wire width 3 $3\fsm_state$503$next[2:0]$5734 - attribute \src "libresoc.v:128419.3-128471.6" - wire width 3 $3\fsm_state$next[2:0]$5711 - attribute \src "libresoc.v:128386.3-128418.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$5705 - attribute \src "libresoc.v:128472.3-128498.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$5718 - attribute \src "libresoc.v:128114.3-128134.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5639 - attribute \src "libresoc.v:128499.3-128519.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$5723 - attribute \src "libresoc.v:128170.3-128190.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5654 - attribute \src "libresoc.v:128058.3-128078.6" - wire width 3 $3\sr0_reg$next[2:0]$5624 - attribute \src "libresoc.v:128338.3-128358.6" - wire width 2 $3\sr5_reg$next[1:0]$5699 - attribute \src "libresoc.v:128520.3-128552.6" - wire width 4 $4\dmi0__addr_i$next[3:0]$5729 - attribute \src "libresoc.v:128553.3-128605.6" - wire width 3 $4\fsm_state$503$next[2:0]$5735 - attribute \src "libresoc.v:128419.3-128471.6" - wire width 3 $4\fsm_state$next[2:0]$5712 - attribute \src "libresoc.v:128386.3-128418.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$5706 - attribute \src "libresoc.v:128553.3-128605.6" - wire width 3 $5\fsm_state$503$next[2:0]$5736 - attribute \src "libresoc.v:128419.3-128471.6" - wire width 3 $5\fsm_state$next[2:0]$5713 - attribute \src "libresoc.v:127864.19-127864.112" - wire width 30 $add$libresoc.v:127864$5535_Y - attribute \src "libresoc.v:127866.19-127866.112" - wire width 30 $add$libresoc.v:127866$5537_Y - attribute \src "libresoc.v:127872.19-127872.112" - wire width 5 $add$libresoc.v:127872$5544_Y - attribute \src "libresoc.v:127873.19-127873.112" - wire width 5 $add$libresoc.v:127873$5545_Y - attribute \src "libresoc.v:127688.18-127688.112" - wire $and$libresoc.v:127688$5359_Y - attribute \src "libresoc.v:127755.18-127755.108" - wire $and$libresoc.v:127755$5426_Y - attribute \src "libresoc.v:127766.18-127766.110" - wire $and$libresoc.v:127766$5437_Y - attribute \src "libresoc.v:127794.19-127794.110" - wire $and$libresoc.v:127794$5465_Y - attribute \src "libresoc.v:127797.19-127797.114" - wire $and$libresoc.v:127797$5468_Y - attribute \src "libresoc.v:127800.19-127800.112" - wire $and$libresoc.v:127800$5471_Y - attribute \src "libresoc.v:127802.19-127802.113" - wire $and$libresoc.v:127802$5473_Y - attribute \src "libresoc.v:127804.19-127804.121" - wire $and$libresoc.v:127804$5475_Y - attribute \src "libresoc.v:127807.19-127807.114" - wire $and$libresoc.v:127807$5478_Y - attribute \src "libresoc.v:127809.19-127809.112" - wire $and$libresoc.v:127809$5480_Y - attribute \src "libresoc.v:127813.19-127813.113" - wire $and$libresoc.v:127813$5484_Y - attribute \src "libresoc.v:127815.19-127815.132" - wire $and$libresoc.v:127815$5486_Y - attribute \src "libresoc.v:127819.19-127819.114" - wire $and$libresoc.v:127819$5490_Y - attribute \src "libresoc.v:127821.19-127821.112" - wire $and$libresoc.v:127821$5492_Y - attribute \src "libresoc.v:127824.19-127824.113" - wire $and$libresoc.v:127824$5495_Y - attribute \src "libresoc.v:127826.19-127826.132" - wire $and$libresoc.v:127826$5497_Y - attribute \src "libresoc.v:127829.19-127829.114" - wire $and$libresoc.v:127829$5500_Y - attribute \src "libresoc.v:127831.19-127831.112" - wire $and$libresoc.v:127831$5502_Y - attribute \src "libresoc.v:127833.18-127833.108" - wire $and$libresoc.v:127833$5504_Y - attribute \src "libresoc.v:127834.19-127834.113" - wire $and$libresoc.v:127834$5505_Y - attribute \src "libresoc.v:127836.19-127836.129" - wire $and$libresoc.v:127836$5507_Y - attribute \src "libresoc.v:127840.19-127840.114" - wire $and$libresoc.v:127840$5511_Y - attribute \src "libresoc.v:127842.19-127842.112" - wire $and$libresoc.v:127842$5513_Y - attribute \src "libresoc.v:127844.18-127844.111" - wire $and$libresoc.v:127844$5515_Y - attribute \src "libresoc.v:127845.19-127845.113" - wire $and$libresoc.v:127845$5516_Y - attribute \src "libresoc.v:127847.19-127847.129" - wire $and$libresoc.v:127847$5518_Y - attribute \src "libresoc.v:127850.19-127850.114" - wire $and$libresoc.v:127850$5521_Y - attribute \src "libresoc.v:127852.19-127852.112" - wire $and$libresoc.v:127852$5523_Y - attribute \src "libresoc.v:127854.19-127854.113" - wire $and$libresoc.v:127854$5525_Y - attribute \src "libresoc.v:127857.19-127857.121" - wire $and$libresoc.v:127857$5528_Y - attribute \src "libresoc.v:127889.17-127889.106" - wire $and$libresoc.v:127889$5561_Y - attribute \src "libresoc.v:127644.17-127644.110" - wire $eq$libresoc.v:127644$5315_Y - attribute \src "libresoc.v:127655.18-127655.111" - wire $eq$libresoc.v:127655$5326_Y - attribute \src "libresoc.v:127666.18-127666.111" - wire $eq$libresoc.v:127666$5337_Y - attribute \src "libresoc.v:127699.17-127699.110" - wire $eq$libresoc.v:127699$5370_Y - attribute \src "libresoc.v:127700.18-127700.111" - wire $eq$libresoc.v:127700$5371_Y - attribute \src "libresoc.v:127711.18-127711.111" - wire $eq$libresoc.v:127711$5382_Y - attribute \src "libresoc.v:127733.18-127733.111" - wire $eq$libresoc.v:127733$5404_Y - attribute \src "libresoc.v:127777.18-127777.111" - wire $eq$libresoc.v:127777$5448_Y - attribute \src "libresoc.v:127788.18-127788.111" - wire $eq$libresoc.v:127788$5459_Y - attribute \src "libresoc.v:127789.19-127789.112" - wire $eq$libresoc.v:127789$5460_Y - attribute \src "libresoc.v:127790.19-127790.112" - wire $eq$libresoc.v:127790$5461_Y - attribute \src "libresoc.v:127792.19-127792.112" - wire $eq$libresoc.v:127792$5463_Y - attribute \src "libresoc.v:127795.19-127795.112" - wire $eq$libresoc.v:127795$5466_Y - attribute \src "libresoc.v:127805.19-127805.112" - wire $eq$libresoc.v:127805$5476_Y - attribute \src "libresoc.v:127810.17-127810.110" - wire $eq$libresoc.v:127810$5481_Y - attribute \src "libresoc.v:127811.18-127811.111" - wire $eq$libresoc.v:127811$5482_Y - attribute \src "libresoc.v:127816.19-127816.112" - wire $eq$libresoc.v:127816$5487_Y - attribute \src "libresoc.v:127817.19-127817.112" - wire $eq$libresoc.v:127817$5488_Y - attribute \src "libresoc.v:127827.19-127827.112" - wire $eq$libresoc.v:127827$5498_Y - attribute \src "libresoc.v:127837.19-127837.112" - wire $eq$libresoc.v:127837$5508_Y - attribute \src "libresoc.v:127838.19-127838.112" - wire $eq$libresoc.v:127838$5509_Y - attribute \src "libresoc.v:127848.19-127848.112" - wire $eq$libresoc.v:127848$5519_Y - attribute \src "libresoc.v:127855.18-127855.111" - wire $eq$libresoc.v:127855$5526_Y - attribute \src "libresoc.v:127858.19-127858.110" - wire $eq$libresoc.v:127858$5529_Y - attribute \src "libresoc.v:127860.19-127860.110" - wire $eq$libresoc.v:127860$5531_Y - attribute \src "libresoc.v:127861.19-127861.110" - wire $eq$libresoc.v:127861$5532_Y - attribute \src "libresoc.v:127863.19-127863.110" - wire $eq$libresoc.v:127863$5534_Y - attribute \src "libresoc.v:127865.18-127865.111" - wire $eq$libresoc.v:127865$5536_Y - attribute \src "libresoc.v:127868.19-127868.116" - wire $eq$libresoc.v:127868$5540_Y - attribute \src "libresoc.v:127869.19-127869.116" - wire $eq$libresoc.v:127869$5541_Y - attribute \src "libresoc.v:127871.19-127871.116" - wire $eq$libresoc.v:127871$5543_Y - attribute \src "libresoc.v:127867.19-127867.106" - wire width 8 $extend$libresoc.v:127867$5538_Y - attribute \src "libresoc.v:127796.19-127796.109" - wire $ne$libresoc.v:127796$5467_Y - attribute \src "libresoc.v:127798.19-127798.109" - wire $ne$libresoc.v:127798$5469_Y - attribute \src "libresoc.v:127801.19-127801.109" - wire $ne$libresoc.v:127801$5472_Y - attribute \src "libresoc.v:127806.19-127806.120" - wire $ne$libresoc.v:127806$5477_Y - attribute \src "libresoc.v:127808.19-127808.120" - wire $ne$libresoc.v:127808$5479_Y - attribute \src "libresoc.v:127812.19-127812.120" - wire $ne$libresoc.v:127812$5483_Y - attribute \src "libresoc.v:127818.19-127818.120" - wire $ne$libresoc.v:127818$5489_Y - attribute \src "libresoc.v:127820.19-127820.120" - wire $ne$libresoc.v:127820$5491_Y - attribute \src "libresoc.v:127823.19-127823.120" - wire $ne$libresoc.v:127823$5494_Y - attribute \src "libresoc.v:127828.19-127828.117" - wire $ne$libresoc.v:127828$5499_Y - attribute \src "libresoc.v:127830.19-127830.117" - wire $ne$libresoc.v:127830$5501_Y - attribute \src "libresoc.v:127832.19-127832.117" - wire $ne$libresoc.v:127832$5503_Y - attribute \src "libresoc.v:127839.19-127839.117" - wire $ne$libresoc.v:127839$5510_Y - attribute \src "libresoc.v:127841.19-127841.117" - wire $ne$libresoc.v:127841$5512_Y - attribute \src "libresoc.v:127843.19-127843.117" - wire $ne$libresoc.v:127843$5514_Y - attribute \src "libresoc.v:127849.19-127849.109" - wire $ne$libresoc.v:127849$5520_Y - attribute \src "libresoc.v:127851.19-127851.109" - wire $ne$libresoc.v:127851$5522_Y - attribute \src "libresoc.v:127853.19-127853.109" - wire $ne$libresoc.v:127853$5524_Y - attribute \src "libresoc.v:127803.19-127803.110" - wire $not$libresoc.v:127803$5474_Y - attribute \src "libresoc.v:127814.19-127814.121" - wire $not$libresoc.v:127814$5485_Y - attribute \src "libresoc.v:127825.19-127825.121" - wire $not$libresoc.v:127825$5496_Y - attribute \src "libresoc.v:127835.19-127835.118" - wire $not$libresoc.v:127835$5506_Y - attribute \src "libresoc.v:127846.19-127846.118" - wire $not$libresoc.v:127846$5517_Y - attribute \src "libresoc.v:127856.19-127856.110" - wire $not$libresoc.v:127856$5527_Y - attribute \src "libresoc.v:127859.19-127859.100" - wire $not$libresoc.v:127859$5530_Y - attribute \src "libresoc.v:127677.18-127677.104" - wire $or$libresoc.v:127677$5348_Y - attribute \src "libresoc.v:127722.18-127722.104" - wire $or$libresoc.v:127722$5393_Y - attribute \src "libresoc.v:127744.18-127744.104" - wire $or$libresoc.v:127744$5415_Y - attribute \src "libresoc.v:127791.19-127791.107" - wire $or$libresoc.v:127791$5462_Y - attribute \src "libresoc.v:127793.19-127793.107" - wire $or$libresoc.v:127793$5464_Y - attribute \src "libresoc.v:127799.18-127799.104" - wire $or$libresoc.v:127799$5470_Y - attribute \src "libresoc.v:127822.18-127822.104" - wire $or$libresoc.v:127822$5493_Y - attribute \src "libresoc.v:127862.19-127862.107" - wire $or$libresoc.v:127862$5533_Y - attribute \src "libresoc.v:127870.19-127870.107" - wire $or$libresoc.v:127870$5542_Y - attribute \src "libresoc.v:127878.17-127878.101" - wire $or$libresoc.v:127878$5550_Y - attribute \src "libresoc.v:127867.19-127867.106" - wire width 8 $pos$libresoc.v:127867$5539_Y - attribute \src "libresoc.v:127645.18-127645.133" - wire $ternary$libresoc.v:127645$5316_Y - attribute \src "libresoc.v:127646.19-127646.133" - wire $ternary$libresoc.v:127646$5317_Y - attribute \src "libresoc.v:127647.19-127647.134" - wire $ternary$libresoc.v:127647$5318_Y - attribute \src "libresoc.v:127648.19-127648.133" - wire $ternary$libresoc.v:127648$5319_Y - attribute \src "libresoc.v:127649.19-127649.132" - wire $ternary$libresoc.v:127649$5320_Y - attribute \src "libresoc.v:127650.19-127650.133" - wire $ternary$libresoc.v:127650$5321_Y - attribute \src "libresoc.v:127651.19-127651.133" - wire $ternary$libresoc.v:127651$5322_Y - attribute \src "libresoc.v:127652.19-127652.132" - wire $ternary$libresoc.v:127652$5323_Y - attribute \src "libresoc.v:127653.19-127653.133" - wire $ternary$libresoc.v:127653$5324_Y - attribute \src "libresoc.v:127654.19-127654.133" - wire $ternary$libresoc.v:127654$5325_Y - attribute \src "libresoc.v:127656.19-127656.132" - wire $ternary$libresoc.v:127656$5327_Y - attribute \src "libresoc.v:127657.19-127657.133" - wire $ternary$libresoc.v:127657$5328_Y - attribute \src "libresoc.v:127658.19-127658.133" - wire $ternary$libresoc.v:127658$5329_Y - attribute \src "libresoc.v:127659.19-127659.132" - wire $ternary$libresoc.v:127659$5330_Y - attribute \src "libresoc.v:127660.19-127660.133" - wire $ternary$libresoc.v:127660$5331_Y - attribute \src "libresoc.v:127661.19-127661.133" - wire $ternary$libresoc.v:127661$5332_Y - attribute \src "libresoc.v:127662.19-127662.132" - wire $ternary$libresoc.v:127662$5333_Y - attribute \src "libresoc.v:127663.19-127663.133" - wire $ternary$libresoc.v:127663$5334_Y - attribute \src "libresoc.v:127664.19-127664.133" - wire $ternary$libresoc.v:127664$5335_Y - attribute \src "libresoc.v:127665.19-127665.132" - wire $ternary$libresoc.v:127665$5336_Y - attribute \src "libresoc.v:127667.19-127667.133" - wire $ternary$libresoc.v:127667$5338_Y - attribute \src "libresoc.v:127668.19-127668.133" - wire $ternary$libresoc.v:127668$5339_Y - attribute \src "libresoc.v:127669.19-127669.132" - wire $ternary$libresoc.v:127669$5340_Y - attribute \src "libresoc.v:127670.19-127670.133" - wire $ternary$libresoc.v:127670$5341_Y - attribute \src "libresoc.v:127671.19-127671.133" - wire $ternary$libresoc.v:127671$5342_Y - attribute \src "libresoc.v:127672.19-127672.132" - wire $ternary$libresoc.v:127672$5343_Y - attribute \src "libresoc.v:127673.19-127673.133" - wire $ternary$libresoc.v:127673$5344_Y - attribute \src "libresoc.v:127674.19-127674.134" - wire $ternary$libresoc.v:127674$5345_Y - attribute \src "libresoc.v:127675.19-127675.135" - wire $ternary$libresoc.v:127675$5346_Y - attribute \src "libresoc.v:127676.19-127676.135" - wire $ternary$libresoc.v:127676$5347_Y - attribute \src "libresoc.v:127678.19-127678.136" - wire $ternary$libresoc.v:127678$5349_Y - attribute \src "libresoc.v:127679.19-127679.134" - wire $ternary$libresoc.v:127679$5350_Y - attribute \src "libresoc.v:127680.19-127680.135" - wire $ternary$libresoc.v:127680$5351_Y - attribute \src "libresoc.v:127681.19-127681.135" - wire $ternary$libresoc.v:127681$5352_Y - attribute \src "libresoc.v:127682.19-127682.136" - wire $ternary$libresoc.v:127682$5353_Y - attribute \src "libresoc.v:127683.19-127683.134" - wire $ternary$libresoc.v:127683$5354_Y - attribute \src "libresoc.v:127684.19-127684.133" - wire $ternary$libresoc.v:127684$5355_Y - attribute \src "libresoc.v:127685.19-127685.134" - wire $ternary$libresoc.v:127685$5356_Y - attribute \src "libresoc.v:127686.19-127686.133" - wire $ternary$libresoc.v:127686$5357_Y - attribute \src "libresoc.v:127687.19-127687.130" - wire $ternary$libresoc.v:127687$5358_Y - attribute \src "libresoc.v:127689.19-127689.130" - wire $ternary$libresoc.v:127689$5360_Y - attribute \src "libresoc.v:127690.19-127690.133" - wire $ternary$libresoc.v:127690$5361_Y - attribute \src "libresoc.v:127691.19-127691.132" - wire $ternary$libresoc.v:127691$5362_Y - attribute \src "libresoc.v:127692.19-127692.133" - wire $ternary$libresoc.v:127692$5363_Y - attribute \src "libresoc.v:127693.19-127693.132" - wire $ternary$libresoc.v:127693$5364_Y - attribute \src "libresoc.v:127694.19-127694.135" - wire $ternary$libresoc.v:127694$5365_Y - attribute \src "libresoc.v:127695.19-127695.134" - wire $ternary$libresoc.v:127695$5366_Y - attribute \src "libresoc.v:127696.19-127696.135" - wire $ternary$libresoc.v:127696$5367_Y - attribute \src "libresoc.v:127697.19-127697.135" - wire $ternary$libresoc.v:127697$5368_Y - attribute \src "libresoc.v:127698.19-127698.134" - wire $ternary$libresoc.v:127698$5369_Y - attribute \src "libresoc.v:127701.19-127701.135" - wire $ternary$libresoc.v:127701$5372_Y - attribute \src "libresoc.v:127702.19-127702.135" - wire $ternary$libresoc.v:127702$5373_Y - attribute \src "libresoc.v:127703.19-127703.134" - wire $ternary$libresoc.v:127703$5374_Y - attribute \src "libresoc.v:127704.19-127704.135" - wire $ternary$libresoc.v:127704$5375_Y - attribute \src "libresoc.v:127705.19-127705.135" - wire $ternary$libresoc.v:127705$5376_Y - attribute \src "libresoc.v:127706.19-127706.134" - wire $ternary$libresoc.v:127706$5377_Y - attribute \src "libresoc.v:127707.19-127707.135" - wire $ternary$libresoc.v:127707$5378_Y - attribute \src "libresoc.v:127708.19-127708.133" - wire $ternary$libresoc.v:127708$5379_Y - attribute \src "libresoc.v:127709.19-127709.134" - wire $ternary$libresoc.v:127709$5380_Y - attribute \src "libresoc.v:127710.19-127710.133" - wire $ternary$libresoc.v:127710$5381_Y - attribute \src "libresoc.v:127712.19-127712.134" - wire $ternary$libresoc.v:127712$5383_Y - attribute \src "libresoc.v:127713.19-127713.134" - wire $ternary$libresoc.v:127713$5384_Y - attribute \src "libresoc.v:127714.19-127714.133" - wire $ternary$libresoc.v:127714$5385_Y - attribute \src "libresoc.v:127715.19-127715.134" - wire $ternary$libresoc.v:127715$5386_Y - attribute \src "libresoc.v:127716.19-127716.134" - wire $ternary$libresoc.v:127716$5387_Y - attribute \src "libresoc.v:127717.19-127717.133" - wire $ternary$libresoc.v:127717$5388_Y - attribute \src "libresoc.v:127718.19-127718.134" - wire $ternary$libresoc.v:127718$5389_Y - attribute \src "libresoc.v:127719.19-127719.134" - wire $ternary$libresoc.v:127719$5390_Y - attribute \src "libresoc.v:127720.19-127720.133" - wire $ternary$libresoc.v:127720$5391_Y - attribute \src "libresoc.v:127721.19-127721.134" - wire $ternary$libresoc.v:127721$5392_Y - attribute \src "libresoc.v:127723.19-127723.134" - wire $ternary$libresoc.v:127723$5394_Y - attribute \src "libresoc.v:127724.19-127724.133" - wire $ternary$libresoc.v:127724$5395_Y - attribute \src "libresoc.v:127725.19-127725.134" - wire $ternary$libresoc.v:127725$5396_Y - attribute \src "libresoc.v:127726.19-127726.134" - wire $ternary$libresoc.v:127726$5397_Y - attribute \src "libresoc.v:127727.19-127727.133" - wire $ternary$libresoc.v:127727$5398_Y - attribute \src "libresoc.v:127728.19-127728.134" - wire $ternary$libresoc.v:127728$5399_Y - attribute \src "libresoc.v:127729.19-127729.135" - wire $ternary$libresoc.v:127729$5400_Y - attribute \src "libresoc.v:127730.19-127730.134" - wire $ternary$libresoc.v:127730$5401_Y - attribute \src "libresoc.v:127731.19-127731.135" - wire $ternary$libresoc.v:127731$5402_Y - attribute \src "libresoc.v:127732.19-127732.135" - wire $ternary$libresoc.v:127732$5403_Y - attribute \src "libresoc.v:127734.19-127734.134" - wire $ternary$libresoc.v:127734$5405_Y - attribute \src "libresoc.v:127735.19-127735.135" - wire $ternary$libresoc.v:127735$5406_Y - attribute \src "libresoc.v:127736.19-127736.133" - wire $ternary$libresoc.v:127736$5407_Y - attribute \src "libresoc.v:127737.19-127737.133" - wire $ternary$libresoc.v:127737$5408_Y - attribute \src "libresoc.v:127738.19-127738.133" - wire $ternary$libresoc.v:127738$5409_Y - attribute \src "libresoc.v:127739.19-127739.133" - wire $ternary$libresoc.v:127739$5410_Y - attribute \src "libresoc.v:127740.19-127740.133" - wire $ternary$libresoc.v:127740$5411_Y - attribute \src "libresoc.v:127741.19-127741.133" - wire $ternary$libresoc.v:127741$5412_Y - attribute \src "libresoc.v:127742.19-127742.133" - wire $ternary$libresoc.v:127742$5413_Y - attribute \src "libresoc.v:127743.19-127743.133" - wire $ternary$libresoc.v:127743$5414_Y - attribute \src "libresoc.v:127745.19-127745.133" - wire $ternary$libresoc.v:127745$5416_Y - attribute \src "libresoc.v:127746.19-127746.133" - wire $ternary$libresoc.v:127746$5417_Y - attribute \src "libresoc.v:127747.19-127747.134" - wire $ternary$libresoc.v:127747$5418_Y - attribute \src "libresoc.v:127748.19-127748.134" - wire $ternary$libresoc.v:127748$5419_Y - attribute \src "libresoc.v:127749.19-127749.135" - wire $ternary$libresoc.v:127749$5420_Y - attribute \src "libresoc.v:127750.19-127750.133" - wire $ternary$libresoc.v:127750$5421_Y - attribute \src "libresoc.v:127751.19-127751.135" - wire $ternary$libresoc.v:127751$5422_Y - attribute \src "libresoc.v:127752.19-127752.135" - wire $ternary$libresoc.v:127752$5423_Y - attribute \src "libresoc.v:127753.19-127753.134" - wire $ternary$libresoc.v:127753$5424_Y - attribute \src "libresoc.v:127754.19-127754.134" - wire $ternary$libresoc.v:127754$5425_Y - attribute \src "libresoc.v:127756.19-127756.134" - wire $ternary$libresoc.v:127756$5427_Y - attribute \src "libresoc.v:127757.19-127757.134" - wire $ternary$libresoc.v:127757$5428_Y - attribute \src "libresoc.v:127758.19-127758.134" - wire $ternary$libresoc.v:127758$5429_Y - attribute \src "libresoc.v:127759.19-127759.135" - wire $ternary$libresoc.v:127759$5430_Y - attribute \src "libresoc.v:127760.19-127760.134" - wire $ternary$libresoc.v:127760$5431_Y - attribute \src "libresoc.v:127761.19-127761.135" - wire $ternary$libresoc.v:127761$5432_Y - attribute \src "libresoc.v:127762.19-127762.135" - wire $ternary$libresoc.v:127762$5433_Y - attribute \src "libresoc.v:127763.19-127763.134" - wire $ternary$libresoc.v:127763$5434_Y - attribute \src "libresoc.v:127764.19-127764.135" - wire $ternary$libresoc.v:127764$5435_Y - attribute \src "libresoc.v:127765.19-127765.135" - wire $ternary$libresoc.v:127765$5436_Y - attribute \src "libresoc.v:127767.19-127767.134" - wire $ternary$libresoc.v:127767$5438_Y - attribute \src "libresoc.v:127768.19-127768.135" - wire $ternary$libresoc.v:127768$5439_Y - attribute \src "libresoc.v:127769.19-127769.136" - wire $ternary$libresoc.v:127769$5440_Y - attribute \src "libresoc.v:127770.19-127770.135" - wire $ternary$libresoc.v:127770$5441_Y - attribute \src "libresoc.v:127771.19-127771.136" - wire $ternary$libresoc.v:127771$5442_Y - attribute \src "libresoc.v:127772.19-127772.136" - wire $ternary$libresoc.v:127772$5443_Y - attribute \src "libresoc.v:127773.19-127773.135" - wire $ternary$libresoc.v:127773$5444_Y - attribute \src "libresoc.v:127774.19-127774.136" - wire $ternary$libresoc.v:127774$5445_Y - attribute \src "libresoc.v:127775.19-127775.136" - wire $ternary$libresoc.v:127775$5446_Y - attribute \src "libresoc.v:127776.19-127776.135" - wire $ternary$libresoc.v:127776$5447_Y - attribute \src "libresoc.v:127778.19-127778.136" - wire $ternary$libresoc.v:127778$5449_Y - attribute \src "libresoc.v:127779.19-127779.136" - wire $ternary$libresoc.v:127779$5450_Y - attribute \src "libresoc.v:127780.19-127780.135" - wire $ternary$libresoc.v:127780$5451_Y - attribute \src "libresoc.v:127781.19-127781.136" - wire $ternary$libresoc.v:127781$5452_Y - attribute \src "libresoc.v:127782.19-127782.136" - wire $ternary$libresoc.v:127782$5453_Y - attribute \src "libresoc.v:127783.19-127783.135" - wire $ternary$libresoc.v:127783$5454_Y - attribute \src "libresoc.v:127784.19-127784.136" - wire $ternary$libresoc.v:127784$5455_Y - attribute \src "libresoc.v:127785.19-127785.136" - wire $ternary$libresoc.v:127785$5456_Y - attribute \src "libresoc.v:127786.19-127786.135" - wire $ternary$libresoc.v:127786$5457_Y - attribute \src "libresoc.v:127787.19-127787.136" - wire $ternary$libresoc.v:127787$5458_Y - attribute \src "libresoc.v:127874.18-127874.130" - wire $ternary$libresoc.v:127874$5546_Y - attribute \src "libresoc.v:127875.18-127875.130" - wire $ternary$libresoc.v:127875$5547_Y - attribute \src "libresoc.v:127876.18-127876.130" - wire $ternary$libresoc.v:127876$5548_Y - attribute \src "libresoc.v:127877.18-127877.131" - wire $ternary$libresoc.v:127877$5549_Y - attribute \src "libresoc.v:127879.18-127879.130" - wire $ternary$libresoc.v:127879$5551_Y - attribute \src "libresoc.v:127880.18-127880.131" - wire $ternary$libresoc.v:127880$5552_Y - attribute \src "libresoc.v:127881.18-127881.131" - wire $ternary$libresoc.v:127881$5553_Y - attribute \src "libresoc.v:127882.18-127882.130" - wire $ternary$libresoc.v:127882$5554_Y - attribute \src "libresoc.v:127883.18-127883.131" - wire $ternary$libresoc.v:127883$5555_Y - attribute \src "libresoc.v:127884.18-127884.132" - wire $ternary$libresoc.v:127884$5556_Y - attribute \src "libresoc.v:127885.18-127885.132" - wire $ternary$libresoc.v:127885$5557_Y - attribute \src "libresoc.v:127886.18-127886.133" - wire $ternary$libresoc.v:127886$5558_Y - attribute \src "libresoc.v:127887.18-127887.133" - wire $ternary$libresoc.v:127887$5559_Y - attribute \src "libresoc.v:127888.18-127888.132" - wire $ternary$libresoc.v:127888$5560_Y - attribute \src "libresoc.v:127890.18-127890.133" - wire $ternary$libresoc.v:127890$5562_Y - attribute \src "libresoc.v:127891.18-127891.133" - wire $ternary$libresoc.v:127891$5563_Y - attribute \src "libresoc.v:127892.18-127892.132" - wire $ternary$libresoc.v:127892$5564_Y - attribute \src "libresoc.v:127893.18-127893.133" - wire $ternary$libresoc.v:127893$5565_Y - attribute \src "libresoc.v:127894.18-127894.133" - wire $ternary$libresoc.v:127894$5566_Y - attribute \src "libresoc.v:127895.18-127895.132" - wire $ternary$libresoc.v:127895$5567_Y - attribute \src "libresoc.v:127896.18-127896.133" - wire $ternary$libresoc.v:127896$5568_Y - attribute \src "libresoc.v:127897.18-127897.133" - wire $ternary$libresoc.v:127897$5569_Y - attribute \src "libresoc.v:127898.18-127898.132" - wire $ternary$libresoc.v:127898$5570_Y - attribute \src "libresoc.v:127899.18-127899.133" - wire $ternary$libresoc.v:127899$5571_Y + attribute \src "libresoc.v:138375.3-138395.6" + wire $1\wb_sram_en$next[0:0]$6071 + attribute \src "libresoc.v:137360.7-137360.24" + wire $1\wb_sram_en[0:0] + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6045 + attribute \src "libresoc.v:138327.3-138353.6" + wire width 64 $2\dmi0__din$next[63:0]$6058 + attribute \src "libresoc.v:137930.3-137946.6" + wire $2\dmi0_addrsr__oe$next[0:0]$5982 + attribute \src "libresoc.v:137947.3-137967.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5986 + attribute \src "libresoc.v:138354.3-138374.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6063 + attribute \src "libresoc.v:137986.3-138002.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$5997 + attribute \src "libresoc.v:138003.3-138023.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$6001 + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $2\fsm_state$503$next[2:0]$6051 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $2\fsm_state$next[2:0]$6028 + attribute \src "libresoc.v:138424.3-138444.6" + wire width 154 $2\io_bd$next[153:0]$6083 + attribute \src "libresoc.v:138406.3-138423.6" + wire width 154 $2\io_sr$next[153:0]$6079 + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6022 + attribute \src "libresoc.v:138193.3-138219.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6035 + attribute \src "libresoc.v:137818.3-137834.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$5952 + attribute \src "libresoc.v:137835.3-137855.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5956 + attribute \src "libresoc.v:138220.3-138240.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6040 + attribute \src "libresoc.v:137874.3-137890.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5967 + attribute \src "libresoc.v:137891.3-137911.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5971 + attribute \src "libresoc.v:137762.3-137778.6" + wire $2\sr0__oe$next[0:0]$5937 + attribute \src "libresoc.v:137779.3-137799.6" + wire width 3 $2\sr0_reg$next[2:0]$5941 + attribute \src "libresoc.v:138042.3-138058.6" + wire $2\sr5__oe$next[0:0]$6012 + attribute \src "libresoc.v:138059.3-138079.6" + wire width 3 $2\sr5_reg$next[2:0]$6016 + attribute \src "libresoc.v:138375.3-138395.6" + wire $2\wb_dcache_en$next[0:0]$6072 + attribute \src "libresoc.v:138375.3-138395.6" + wire $2\wb_icache_en$next[0:0]$6073 + attribute \src "libresoc.v:138375.3-138395.6" + wire $2\wb_sram_en$next[0:0]$6074 + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6046 + attribute \src "libresoc.v:138327.3-138353.6" + wire width 64 $3\dmi0__din$next[63:0]$6059 + attribute \src "libresoc.v:137947.3-137967.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5987 + attribute \src "libresoc.v:138354.3-138374.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6064 + attribute \src "libresoc.v:138003.3-138023.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$6002 + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $3\fsm_state$503$next[2:0]$6052 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $3\fsm_state$next[2:0]$6029 + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$6023 + attribute \src "libresoc.v:138193.3-138219.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$6036 + attribute \src "libresoc.v:137835.3-137855.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5957 + attribute \src "libresoc.v:138220.3-138240.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6041 + attribute \src "libresoc.v:137891.3-137911.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5972 + attribute \src "libresoc.v:137779.3-137799.6" + wire width 3 $3\sr0_reg$next[2:0]$5942 + attribute \src "libresoc.v:138059.3-138079.6" + wire width 3 $3\sr5_reg$next[2:0]$6017 + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$6047 + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $4\fsm_state$503$next[2:0]$6053 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $4\fsm_state$next[2:0]$6030 + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$6024 + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $5\fsm_state$503$next[2:0]$6054 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $5\fsm_state$next[2:0]$6031 + attribute \src "libresoc.v:137583.19-137583.112" + wire width 30 $add$libresoc.v:137583$5852_Y + attribute \src "libresoc.v:137585.19-137585.112" + wire width 30 $add$libresoc.v:137585$5854_Y + attribute \src "libresoc.v:137591.19-137591.112" + wire width 5 $add$libresoc.v:137591$5861_Y + attribute \src "libresoc.v:137592.19-137592.112" + wire width 5 $add$libresoc.v:137592$5862_Y + attribute \src "libresoc.v:137407.18-137407.112" + wire $and$libresoc.v:137407$5676_Y + attribute \src "libresoc.v:137474.18-137474.108" + wire $and$libresoc.v:137474$5743_Y + attribute \src "libresoc.v:137485.18-137485.110" + wire $and$libresoc.v:137485$5754_Y + attribute \src "libresoc.v:137513.19-137513.110" + wire $and$libresoc.v:137513$5782_Y + attribute \src "libresoc.v:137516.19-137516.114" + wire $and$libresoc.v:137516$5785_Y + attribute \src "libresoc.v:137519.19-137519.112" + wire $and$libresoc.v:137519$5788_Y + attribute \src "libresoc.v:137521.19-137521.113" + wire $and$libresoc.v:137521$5790_Y + attribute \src "libresoc.v:137523.19-137523.121" + wire $and$libresoc.v:137523$5792_Y + attribute \src "libresoc.v:137526.19-137526.114" + wire $and$libresoc.v:137526$5795_Y + attribute \src "libresoc.v:137528.19-137528.112" + wire $and$libresoc.v:137528$5797_Y + attribute \src "libresoc.v:137532.19-137532.113" + wire $and$libresoc.v:137532$5801_Y + attribute \src "libresoc.v:137534.19-137534.132" + wire $and$libresoc.v:137534$5803_Y + attribute \src "libresoc.v:137538.19-137538.114" + wire $and$libresoc.v:137538$5807_Y + attribute \src "libresoc.v:137540.19-137540.112" + wire $and$libresoc.v:137540$5809_Y + attribute \src "libresoc.v:137543.19-137543.113" + wire $and$libresoc.v:137543$5812_Y + attribute \src "libresoc.v:137545.19-137545.132" + wire $and$libresoc.v:137545$5814_Y + attribute \src "libresoc.v:137548.19-137548.114" + wire $and$libresoc.v:137548$5817_Y + attribute \src "libresoc.v:137550.19-137550.112" + wire $and$libresoc.v:137550$5819_Y + attribute \src "libresoc.v:137552.18-137552.108" + wire $and$libresoc.v:137552$5821_Y + attribute \src "libresoc.v:137553.19-137553.113" + wire $and$libresoc.v:137553$5822_Y + attribute \src "libresoc.v:137555.19-137555.129" + wire $and$libresoc.v:137555$5824_Y + attribute \src "libresoc.v:137559.19-137559.114" + wire $and$libresoc.v:137559$5828_Y + attribute \src "libresoc.v:137561.19-137561.112" + wire $and$libresoc.v:137561$5830_Y + attribute \src "libresoc.v:137563.18-137563.111" + wire $and$libresoc.v:137563$5832_Y + attribute \src "libresoc.v:137564.19-137564.113" + wire $and$libresoc.v:137564$5833_Y + attribute \src "libresoc.v:137566.19-137566.129" + wire $and$libresoc.v:137566$5835_Y + attribute \src "libresoc.v:137569.19-137569.114" + wire $and$libresoc.v:137569$5838_Y + attribute \src "libresoc.v:137571.19-137571.112" + wire $and$libresoc.v:137571$5840_Y + attribute \src "libresoc.v:137573.19-137573.113" + wire $and$libresoc.v:137573$5842_Y + attribute \src "libresoc.v:137576.19-137576.121" + wire $and$libresoc.v:137576$5845_Y + attribute \src "libresoc.v:137608.17-137608.106" + wire $and$libresoc.v:137608$5878_Y + attribute \src "libresoc.v:137363.17-137363.110" + wire $eq$libresoc.v:137363$5632_Y + attribute \src "libresoc.v:137374.18-137374.111" + wire $eq$libresoc.v:137374$5643_Y + attribute \src "libresoc.v:137385.18-137385.111" + wire $eq$libresoc.v:137385$5654_Y + attribute \src "libresoc.v:137418.17-137418.110" + wire $eq$libresoc.v:137418$5687_Y + attribute \src "libresoc.v:137419.18-137419.111" + wire $eq$libresoc.v:137419$5688_Y + attribute \src "libresoc.v:137430.18-137430.111" + wire $eq$libresoc.v:137430$5699_Y + attribute \src "libresoc.v:137452.18-137452.111" + wire $eq$libresoc.v:137452$5721_Y + attribute \src "libresoc.v:137496.18-137496.111" + wire $eq$libresoc.v:137496$5765_Y + attribute \src "libresoc.v:137507.18-137507.111" + wire $eq$libresoc.v:137507$5776_Y + attribute \src "libresoc.v:137508.19-137508.112" + wire $eq$libresoc.v:137508$5777_Y + attribute \src "libresoc.v:137509.19-137509.112" + wire $eq$libresoc.v:137509$5778_Y + attribute \src "libresoc.v:137511.19-137511.112" + wire $eq$libresoc.v:137511$5780_Y + attribute \src "libresoc.v:137514.19-137514.112" + wire $eq$libresoc.v:137514$5783_Y + attribute \src "libresoc.v:137524.19-137524.112" + wire $eq$libresoc.v:137524$5793_Y + attribute \src "libresoc.v:137529.17-137529.110" + wire $eq$libresoc.v:137529$5798_Y + attribute \src "libresoc.v:137530.18-137530.111" + wire $eq$libresoc.v:137530$5799_Y + attribute \src "libresoc.v:137535.19-137535.112" + wire $eq$libresoc.v:137535$5804_Y + attribute \src "libresoc.v:137536.19-137536.112" + wire $eq$libresoc.v:137536$5805_Y + attribute \src "libresoc.v:137546.19-137546.112" + wire $eq$libresoc.v:137546$5815_Y + attribute \src "libresoc.v:137556.19-137556.112" + wire $eq$libresoc.v:137556$5825_Y + attribute \src "libresoc.v:137557.19-137557.112" + wire $eq$libresoc.v:137557$5826_Y + attribute \src "libresoc.v:137567.19-137567.112" + wire $eq$libresoc.v:137567$5836_Y + attribute \src "libresoc.v:137574.18-137574.111" + wire $eq$libresoc.v:137574$5843_Y + attribute \src "libresoc.v:137577.19-137577.110" + wire $eq$libresoc.v:137577$5846_Y + attribute \src "libresoc.v:137579.19-137579.110" + wire $eq$libresoc.v:137579$5848_Y + attribute \src "libresoc.v:137580.19-137580.110" + wire $eq$libresoc.v:137580$5849_Y + attribute \src "libresoc.v:137582.19-137582.110" + wire $eq$libresoc.v:137582$5851_Y + attribute \src "libresoc.v:137584.18-137584.111" + wire $eq$libresoc.v:137584$5853_Y + attribute \src "libresoc.v:137587.19-137587.116" + wire $eq$libresoc.v:137587$5857_Y + attribute \src "libresoc.v:137588.19-137588.116" + wire $eq$libresoc.v:137588$5858_Y + attribute \src "libresoc.v:137590.19-137590.116" + wire $eq$libresoc.v:137590$5860_Y + attribute \src "libresoc.v:137586.19-137586.106" + wire width 8 $extend$libresoc.v:137586$5855_Y + attribute \src "libresoc.v:137515.19-137515.109" + wire $ne$libresoc.v:137515$5784_Y + attribute \src "libresoc.v:137517.19-137517.109" + wire $ne$libresoc.v:137517$5786_Y + attribute \src "libresoc.v:137520.19-137520.109" + wire $ne$libresoc.v:137520$5789_Y + attribute \src "libresoc.v:137525.19-137525.120" + wire $ne$libresoc.v:137525$5794_Y + attribute \src "libresoc.v:137527.19-137527.120" + wire $ne$libresoc.v:137527$5796_Y + attribute \src "libresoc.v:137531.19-137531.120" + wire $ne$libresoc.v:137531$5800_Y + attribute \src "libresoc.v:137537.19-137537.120" + wire $ne$libresoc.v:137537$5806_Y + attribute \src "libresoc.v:137539.19-137539.120" + wire $ne$libresoc.v:137539$5808_Y + attribute \src "libresoc.v:137542.19-137542.120" + wire $ne$libresoc.v:137542$5811_Y + attribute \src "libresoc.v:137547.19-137547.117" + wire $ne$libresoc.v:137547$5816_Y + attribute \src "libresoc.v:137549.19-137549.117" + wire $ne$libresoc.v:137549$5818_Y + attribute \src "libresoc.v:137551.19-137551.117" + wire $ne$libresoc.v:137551$5820_Y + attribute \src "libresoc.v:137558.19-137558.117" + wire $ne$libresoc.v:137558$5827_Y + attribute \src "libresoc.v:137560.19-137560.117" + wire $ne$libresoc.v:137560$5829_Y + attribute \src "libresoc.v:137562.19-137562.117" + wire $ne$libresoc.v:137562$5831_Y + attribute \src "libresoc.v:137568.19-137568.109" + wire $ne$libresoc.v:137568$5837_Y + attribute \src "libresoc.v:137570.19-137570.109" + wire $ne$libresoc.v:137570$5839_Y + attribute \src "libresoc.v:137572.19-137572.109" + wire $ne$libresoc.v:137572$5841_Y + attribute \src "libresoc.v:137522.19-137522.110" + wire $not$libresoc.v:137522$5791_Y + attribute \src "libresoc.v:137533.19-137533.121" + wire $not$libresoc.v:137533$5802_Y + attribute \src "libresoc.v:137544.19-137544.121" + wire $not$libresoc.v:137544$5813_Y + attribute \src "libresoc.v:137554.19-137554.118" + wire $not$libresoc.v:137554$5823_Y + attribute \src "libresoc.v:137565.19-137565.118" + wire $not$libresoc.v:137565$5834_Y + attribute \src "libresoc.v:137575.19-137575.110" + wire $not$libresoc.v:137575$5844_Y + attribute \src "libresoc.v:137578.19-137578.100" + wire $not$libresoc.v:137578$5847_Y + attribute \src "libresoc.v:137396.18-137396.104" + wire $or$libresoc.v:137396$5665_Y + attribute \src "libresoc.v:137441.18-137441.104" + wire $or$libresoc.v:137441$5710_Y + attribute \src "libresoc.v:137463.18-137463.104" + wire $or$libresoc.v:137463$5732_Y + attribute \src "libresoc.v:137510.19-137510.107" + wire $or$libresoc.v:137510$5779_Y + attribute \src "libresoc.v:137512.19-137512.107" + wire $or$libresoc.v:137512$5781_Y + attribute \src "libresoc.v:137518.18-137518.104" + wire $or$libresoc.v:137518$5787_Y + attribute \src "libresoc.v:137541.18-137541.104" + wire $or$libresoc.v:137541$5810_Y + attribute \src "libresoc.v:137581.19-137581.107" + wire $or$libresoc.v:137581$5850_Y + attribute \src "libresoc.v:137589.19-137589.107" + wire $or$libresoc.v:137589$5859_Y + attribute \src "libresoc.v:137597.17-137597.101" + wire $or$libresoc.v:137597$5867_Y + attribute \src "libresoc.v:137586.19-137586.106" + wire width 8 $pos$libresoc.v:137586$5856_Y + attribute \src "libresoc.v:137364.18-137364.133" + wire $ternary$libresoc.v:137364$5633_Y + attribute \src "libresoc.v:137365.19-137365.133" + wire $ternary$libresoc.v:137365$5634_Y + attribute \src "libresoc.v:137366.19-137366.134" + wire $ternary$libresoc.v:137366$5635_Y + attribute \src "libresoc.v:137367.19-137367.133" + wire $ternary$libresoc.v:137367$5636_Y + attribute \src "libresoc.v:137368.19-137368.132" + wire $ternary$libresoc.v:137368$5637_Y + attribute \src "libresoc.v:137369.19-137369.133" + wire $ternary$libresoc.v:137369$5638_Y + attribute \src "libresoc.v:137370.19-137370.133" + wire $ternary$libresoc.v:137370$5639_Y + attribute \src "libresoc.v:137371.19-137371.132" + wire $ternary$libresoc.v:137371$5640_Y + attribute \src "libresoc.v:137372.19-137372.133" + wire $ternary$libresoc.v:137372$5641_Y + attribute \src "libresoc.v:137373.19-137373.133" + wire $ternary$libresoc.v:137373$5642_Y + attribute \src "libresoc.v:137375.19-137375.132" + wire $ternary$libresoc.v:137375$5644_Y + attribute \src "libresoc.v:137376.19-137376.133" + wire $ternary$libresoc.v:137376$5645_Y + attribute \src "libresoc.v:137377.19-137377.133" + wire $ternary$libresoc.v:137377$5646_Y + attribute \src "libresoc.v:137378.19-137378.132" + wire $ternary$libresoc.v:137378$5647_Y + attribute \src "libresoc.v:137379.19-137379.133" + wire $ternary$libresoc.v:137379$5648_Y + attribute \src "libresoc.v:137380.19-137380.133" + wire $ternary$libresoc.v:137380$5649_Y + attribute \src "libresoc.v:137381.19-137381.132" + wire $ternary$libresoc.v:137381$5650_Y + attribute \src "libresoc.v:137382.19-137382.133" + wire $ternary$libresoc.v:137382$5651_Y + attribute \src "libresoc.v:137383.19-137383.133" + wire $ternary$libresoc.v:137383$5652_Y + attribute \src "libresoc.v:137384.19-137384.132" + wire $ternary$libresoc.v:137384$5653_Y + attribute \src "libresoc.v:137386.19-137386.133" + wire $ternary$libresoc.v:137386$5655_Y + attribute \src "libresoc.v:137387.19-137387.133" + wire $ternary$libresoc.v:137387$5656_Y + attribute \src "libresoc.v:137388.19-137388.132" + wire $ternary$libresoc.v:137388$5657_Y + attribute \src "libresoc.v:137389.19-137389.133" + wire $ternary$libresoc.v:137389$5658_Y + attribute \src "libresoc.v:137390.19-137390.133" + wire $ternary$libresoc.v:137390$5659_Y + attribute \src "libresoc.v:137391.19-137391.132" + wire $ternary$libresoc.v:137391$5660_Y + attribute \src "libresoc.v:137392.19-137392.133" + wire $ternary$libresoc.v:137392$5661_Y + attribute \src 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attribute \src "libresoc.v:137442.19-137442.134" + wire $ternary$libresoc.v:137442$5711_Y + attribute \src "libresoc.v:137443.19-137443.133" + wire $ternary$libresoc.v:137443$5712_Y + attribute \src "libresoc.v:137444.19-137444.134" + wire $ternary$libresoc.v:137444$5713_Y + attribute \src "libresoc.v:137445.19-137445.134" + wire $ternary$libresoc.v:137445$5714_Y + attribute \src "libresoc.v:137446.19-137446.133" + wire $ternary$libresoc.v:137446$5715_Y + attribute \src "libresoc.v:137447.19-137447.134" + wire $ternary$libresoc.v:137447$5716_Y + attribute \src "libresoc.v:137448.19-137448.135" + wire $ternary$libresoc.v:137448$5717_Y + attribute \src "libresoc.v:137449.19-137449.134" + wire $ternary$libresoc.v:137449$5718_Y + attribute \src "libresoc.v:137450.19-137450.135" + wire $ternary$libresoc.v:137450$5719_Y + attribute \src "libresoc.v:137451.19-137451.135" + wire $ternary$libresoc.v:137451$5720_Y + attribute \src "libresoc.v:137453.19-137453.134" + wire $ternary$libresoc.v:137453$5722_Y + attribute \src "libresoc.v:137454.19-137454.135" + wire $ternary$libresoc.v:137454$5723_Y + attribute \src "libresoc.v:137455.19-137455.133" + wire $ternary$libresoc.v:137455$5724_Y + attribute \src "libresoc.v:137456.19-137456.133" + wire $ternary$libresoc.v:137456$5725_Y + attribute \src "libresoc.v:137457.19-137457.133" + wire $ternary$libresoc.v:137457$5726_Y + attribute \src "libresoc.v:137458.19-137458.133" + wire $ternary$libresoc.v:137458$5727_Y + attribute \src "libresoc.v:137459.19-137459.133" + wire $ternary$libresoc.v:137459$5728_Y + attribute \src "libresoc.v:137460.19-137460.133" + wire $ternary$libresoc.v:137460$5729_Y + attribute \src "libresoc.v:137461.19-137461.133" + wire $ternary$libresoc.v:137461$5730_Y + attribute \src "libresoc.v:137462.19-137462.133" + wire $ternary$libresoc.v:137462$5731_Y + attribute \src "libresoc.v:137464.19-137464.133" + wire $ternary$libresoc.v:137464$5733_Y + attribute \src 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attribute \src "libresoc.v:137477.19-137477.134" + wire $ternary$libresoc.v:137477$5746_Y + attribute \src "libresoc.v:137478.19-137478.135" + wire $ternary$libresoc.v:137478$5747_Y + attribute \src "libresoc.v:137479.19-137479.134" + wire $ternary$libresoc.v:137479$5748_Y + attribute \src "libresoc.v:137480.19-137480.135" + wire $ternary$libresoc.v:137480$5749_Y + attribute \src "libresoc.v:137481.19-137481.135" + wire $ternary$libresoc.v:137481$5750_Y + attribute \src "libresoc.v:137482.19-137482.134" + wire $ternary$libresoc.v:137482$5751_Y + attribute \src "libresoc.v:137483.19-137483.135" + wire $ternary$libresoc.v:137483$5752_Y + attribute \src "libresoc.v:137484.19-137484.135" + wire $ternary$libresoc.v:137484$5753_Y + attribute \src "libresoc.v:137486.19-137486.134" + wire $ternary$libresoc.v:137486$5755_Y + attribute \src "libresoc.v:137487.19-137487.135" + wire $ternary$libresoc.v:137487$5756_Y + attribute \src "libresoc.v:137488.19-137488.136" + wire $ternary$libresoc.v:137488$5757_Y + attribute \src "libresoc.v:137489.19-137489.135" + wire $ternary$libresoc.v:137489$5758_Y + attribute \src "libresoc.v:137490.19-137490.136" + wire $ternary$libresoc.v:137490$5759_Y + attribute \src "libresoc.v:137491.19-137491.136" + wire $ternary$libresoc.v:137491$5760_Y + attribute \src "libresoc.v:137492.19-137492.135" + wire $ternary$libresoc.v:137492$5761_Y + attribute \src "libresoc.v:137493.19-137493.136" + wire $ternary$libresoc.v:137493$5762_Y + attribute \src "libresoc.v:137494.19-137494.136" + wire $ternary$libresoc.v:137494$5763_Y + attribute \src "libresoc.v:137495.19-137495.135" + wire $ternary$libresoc.v:137495$5764_Y + attribute \src "libresoc.v:137497.19-137497.136" + wire $ternary$libresoc.v:137497$5766_Y + attribute \src "libresoc.v:137498.19-137498.136" + wire $ternary$libresoc.v:137498$5767_Y + attribute \src "libresoc.v:137499.19-137499.135" + wire $ternary$libresoc.v:137499$5768_Y + attribute \src "libresoc.v:137500.19-137500.136" + wire $ternary$libresoc.v:137500$5769_Y + attribute \src "libresoc.v:137501.19-137501.136" + wire $ternary$libresoc.v:137501$5770_Y + attribute \src "libresoc.v:137502.19-137502.135" + wire $ternary$libresoc.v:137502$5771_Y + attribute \src "libresoc.v:137503.19-137503.136" + wire $ternary$libresoc.v:137503$5772_Y + attribute \src "libresoc.v:137504.19-137504.136" + wire $ternary$libresoc.v:137504$5773_Y + attribute \src "libresoc.v:137505.19-137505.135" + wire $ternary$libresoc.v:137505$5774_Y + attribute \src "libresoc.v:137506.19-137506.136" + wire $ternary$libresoc.v:137506$5775_Y + attribute \src "libresoc.v:137593.18-137593.130" + wire $ternary$libresoc.v:137593$5863_Y + attribute \src "libresoc.v:137594.18-137594.130" + wire $ternary$libresoc.v:137594$5864_Y + attribute \src "libresoc.v:137595.18-137595.130" + wire $ternary$libresoc.v:137595$5865_Y + attribute \src "libresoc.v:137596.18-137596.131" + wire $ternary$libresoc.v:137596$5866_Y + attribute \src "libresoc.v:137598.18-137598.130" + wire $ternary$libresoc.v:137598$5868_Y + attribute \src "libresoc.v:137599.18-137599.131" + wire $ternary$libresoc.v:137599$5869_Y + attribute \src "libresoc.v:137600.18-137600.131" + wire $ternary$libresoc.v:137600$5870_Y + attribute \src "libresoc.v:137601.18-137601.130" + wire $ternary$libresoc.v:137601$5871_Y + attribute \src "libresoc.v:137602.18-137602.131" + wire $ternary$libresoc.v:137602$5872_Y + attribute \src "libresoc.v:137603.18-137603.132" + wire $ternary$libresoc.v:137603$5873_Y + attribute \src "libresoc.v:137604.18-137604.132" + wire $ternary$libresoc.v:137604$5874_Y + attribute \src "libresoc.v:137605.18-137605.133" + wire $ternary$libresoc.v:137605$5875_Y + attribute \src "libresoc.v:137606.18-137606.133" + wire $ternary$libresoc.v:137606$5876_Y + attribute \src "libresoc.v:137607.18-137607.132" + wire $ternary$libresoc.v:137607$5877_Y + attribute \src "libresoc.v:137609.18-137609.133" + wire $ternary$libresoc.v:137609$5879_Y + attribute \src "libresoc.v:137610.18-137610.133" + wire $ternary$libresoc.v:137610$5880_Y + attribute \src "libresoc.v:137611.18-137611.132" + wire $ternary$libresoc.v:137611$5881_Y + attribute \src "libresoc.v:137612.18-137612.133" + wire $ternary$libresoc.v:137612$5882_Y + attribute \src "libresoc.v:137613.18-137613.133" + wire $ternary$libresoc.v:137613$5883_Y + attribute \src "libresoc.v:137614.18-137614.132" + wire $ternary$libresoc.v:137614$5884_Y + attribute \src "libresoc.v:137615.18-137615.133" + wire $ternary$libresoc.v:137615$5885_Y + attribute \src "libresoc.v:137616.18-137616.133" + wire $ternary$libresoc.v:137616$5886_Y + attribute \src "libresoc.v:137617.18-137617.132" + wire $ternary$libresoc.v:137617$5887_Y + attribute \src "libresoc.v:137618.18-137618.133" + wire $ternary$libresoc.v:137618$5888_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" @@ -200636,13 +216414,13 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 328 \TAP_bus__tck + wire input 329 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 164 \TAP_bus__tdi + wire input 165 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 319 \TAP_bus__tdo + wire output 320 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 329 \TAP_bus__tms + wire input 330 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" @@ -200665,8 +216443,8 @@ module \jtag wire width 4 \_irblock_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 330 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 331 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire input 6 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" @@ -200742,17 +216520,17 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \eint_0__core__i + wire output 166 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 10 \eint_0__pad__i + wire input 11 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_1__core__i + wire output 167 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 11 \eint_1__pad__i + wire input 12 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \eint_2__core__i + wire output 168 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 12 \eint_2__pad__i + wire input 13 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" @@ -200762,198 +216540,198 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e10__core__i + wire output 175 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \gpio_e10__core__o + wire input 21 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 21 \gpio_e10__core__oe + wire input 22 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 19 \gpio_e10__pad__i + wire input 20 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__pad__o + wire output 176 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e10__pad__oe + wire output 177 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e11__core__i + wire output 178 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 23 \gpio_e11__core__o + wire input 24 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \gpio_e11__core__oe + wire input 25 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \gpio_e11__pad__i + wire input 23 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__pad__o + wire output 179 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e11__pad__oe + wire output 180 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e12__core__i + wire output 181 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e12__core__o + wire input 27 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e12__core__oe + wire input 28 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \gpio_e12__pad__i + wire input 26 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__pad__o + wire output 182 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e12__pad__oe + wire output 183 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e13__core__i + wire output 184 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e13__core__o + wire input 30 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e13__core__oe + wire input 31 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e13__pad__i + wire input 29 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__pad__o + wire output 185 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e13__pad__oe + wire output 186 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e14__core__i + wire output 187 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e14__core__o + wire input 33 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e14__core__oe + wire input 34 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e14__pad__i + wire input 32 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__pad__o + wire output 188 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e14__pad__oe + wire output 189 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e15__core__i + wire output 190 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e15__core__o + wire input 36 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e15__core__oe + wire input 37 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e15__pad__i + wire input 35 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__pad__o + wire output 191 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e15__pad__oe + wire output 192 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e8__core__i + wire output 169 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 14 \gpio_e8__core__o + wire input 15 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 15 \gpio_e8__core__oe + wire input 16 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 13 \gpio_e8__pad__i + wire input 14 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__pad__o + wire output 170 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e8__pad__oe + wire output 171 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e9__core__i + wire output 172 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 17 \gpio_e9__core__o + wire input 18 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 18 \gpio_e9__core__oe + wire input 19 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 16 \gpio_e9__pad__i + wire input 17 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__pad__o + wire output 173 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e9__pad__oe + wire output 174 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s0__core__i + wire output 193 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_s0__core__o + wire input 39 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_s0__core__oe + wire input 40 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_s0__pad__i + wire input 38 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__pad__o + wire output 194 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s0__pad__oe + wire output 195 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s1__core__i + wire output 196 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_s1__core__o + wire input 42 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_s1__core__oe + wire input 43 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_s1__pad__i + wire input 41 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__pad__o + wire output 197 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s1__pad__oe + wire output 198 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s2__core__i + wire output 199 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_s2__core__o + wire input 45 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_s2__core__oe + wire input 46 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_s2__pad__i + wire input 44 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__pad__o + wire output 200 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s2__pad__oe + wire output 201 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s3__core__i + wire output 202 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_s3__core__o + wire input 48 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_s3__core__oe + wire input 49 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_s3__pad__i + wire input 47 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__pad__o + wire output 203 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s3__pad__oe + wire output 204 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s4__core__i + wire output 205 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_s4__core__o + wire input 51 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s4__core__oe + wire input 52 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_s4__pad__i + wire input 50 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__pad__o + wire output 206 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s4__pad__oe + wire output 207 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s5__core__i + wire output 208 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s5__core__o + wire input 54 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s5__core__oe + wire input 55 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s5__pad__i + wire input 53 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__pad__o + wire output 209 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s5__pad__oe + wire output 210 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s6__core__i + wire output 211 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s6__core__o + wire input 57 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s6__core__oe + wire input 58 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s6__pad__i + wire input 56 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__pad__o + wire output 212 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s6__pad__oe + wire output 213 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s7__core__i + wire output 214 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s7__core__o + wire input 60 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s7__core__oe + wire input 61 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s7__pad__i + wire input 59 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__pad__o + wire output 215 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s7__pad__oe - attribute \src "libresoc.v:126214.7-126214.15" + wire output 216 \gpio_s7__pad__oe + attribute \src "libresoc.v:135928.7-135928.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" wire width 154 \io_bd @@ -200974,25 +216752,25 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 326 \jtag_wb__ack + wire input 327 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 320 \jtag_wb__adr + wire width 29 output 321 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 322 \jtag_wb__cyc + wire output 323 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 327 \jtag_wb__dat_r + wire width 64 input 328 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 325 \jtag_wb__dat_w + wire width 64 output 326 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 321 \jtag_wb__sel + wire output 322 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 323 \jtag_wb__stb + wire output 324 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 324 \jtag_wb__we + wire output 325 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" @@ -201052,53 +216830,53 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \mspi0_clk__core__o + wire input 62 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \mspi0_clk__pad__o + wire output 217 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \mspi0_cs_n__core__o + wire input 63 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_cs_n__pad__o + wire output 218 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi0_miso__core__i + wire output 220 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \mspi0_miso__pad__i + wire input 65 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \mspi0_mosi__core__o + wire input 64 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_mosi__pad__o + wire output 219 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \mspi1_clk__core__o + wire input 66 \mspi1_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi1_clk__pad__o + wire output 221 \mspi1_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi1_cs_n__core__o + wire input 67 \mspi1_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_cs_n__pad__o + wire output 222 \mspi1_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mspi1_miso__core__i + wire output 224 \mspi1_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mspi1_miso__pad__i + wire input 69 \mspi1_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi1_mosi__core__o + wire input 68 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_mosi__pad__o + wire output 223 \mspi1_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \mtwi_scl__core__o + wire input 73 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \mtwi_scl__pad__o + wire output 228 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mtwi_sda__core__i + wire output 225 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mtwi_sda__core__o + wire input 71 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mtwi_sda__core__oe + wire input 72 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mtwi_sda__pad__i + wire input 70 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__pad__o + wire output 226 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_sda__pad__oe + wire output 227 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" @@ -201108,371 +216886,371 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \pwm_0__core__o + wire input 74 \pwm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \pwm_0__pad__o + wire output 229 \pwm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \pwm_1__core__o + wire input 75 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire output 230 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sd0_clk__core__o + wire input 79 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_clk__pad__o + wire output 234 \sd0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sd0_cmd__core__i + wire output 231 \sd0_cmd__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sd0_cmd__core__o + wire input 77 \sd0_cmd__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sd0_cmd__core__oe + wire input 78 \sd0_cmd__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \sd0_cmd__pad__i + wire input 76 \sd0_cmd__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__pad__o + wire output 232 \sd0_cmd__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_cmd__pad__oe + wire output 233 \sd0_cmd__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_data0__core__i + wire output 235 \sd0_data0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_data0__core__o + wire input 81 \sd0_data0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_data0__core__oe + wire input 82 \sd0_data0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sd0_data0__pad__i + wire input 80 \sd0_data0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__pad__o + wire output 236 \sd0_data0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data0__pad__oe + wire output 237 \sd0_data0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data1__core__i + wire output 238 \sd0_data1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_data1__core__o + wire input 84 \sd0_data1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data1__core__oe + wire input 85 \sd0_data1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_data1__pad__i + wire input 83 \sd0_data1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__pad__o + wire output 239 \sd0_data1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data1__pad__oe + wire output 240 \sd0_data1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data2__core__i + wire output 241 \sd0_data2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data2__core__o + wire input 87 \sd0_data2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data2__core__oe + wire input 88 \sd0_data2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data2__pad__i + wire input 86 \sd0_data2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__pad__o + wire output 242 \sd0_data2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data2__pad__oe + wire output 243 \sd0_data2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data3__core__i + wire output 244 \sd0_data3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data3__core__o + wire input 90 \sd0_data3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_data3__core__oe + wire input 91 \sd0_data3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data3__pad__i + wire input 89 \sd0_data3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__pad__o + wire output 245 \sd0_data3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_data3__pad__oe + wire output 246 \sd0_data3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_a_0__core__o + wire input 117 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_a_0__pad__o + wire output 272 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_10__core__o + wire input 135 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_10__pad__o + wire output 290 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_11__core__o + wire input 136 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_11__pad__o + wire output 291 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_12__core__o + wire input 137 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_12__pad__o + wire output 292 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_1__core__o + wire input 118 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_1__pad__o + wire output 273 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_a_2__core__o + wire input 119 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_2__pad__o + wire output 274 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_a_3__core__o + wire input 120 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_3__pad__o + wire output 275 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_a_4__core__o + wire input 121 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_4__pad__o + wire output 276 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_5__core__o + wire input 122 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_5__pad__o + wire output 277 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_6__core__o + wire input 123 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_6__pad__o + wire output 278 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_7__core__o + wire input 124 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_7__pad__o + wire output 279 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_8__core__o + wire input 125 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_8__pad__o + wire output 280 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_a_9__core__o + wire input 126 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_a_9__pad__o + wire output 281 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_ba_0__core__o + wire input 127 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_ba_0__pad__o + wire output 282 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_ba_1__core__o + wire input 128 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_ba_1__pad__o + wire output 283 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_cas_n__core__o + wire input 132 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_cas_n__pad__o + wire output 287 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_cke__core__o + wire input 130 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_cke__pad__o + wire output 285 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_clock__core__o + wire input 129 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_clock__pad__o + wire output 284 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_cs_n__core__o + wire input 134 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_cs_n__pad__o + wire output 289 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sdr_dm_0__core__o + wire input 92 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dm_0__pad__o + wire output 247 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dm_1__core__i + wire output 293 \sdr_dm_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__core__o + wire input 139 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dm_1__core__oe + wire input 140 \sdr_dm_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dm_1__pad__i + wire input 138 \sdr_dm_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dm_1__pad__o + wire output 294 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dm_1__pad__oe + wire output 295 \sdr_dm_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_0__core__i + wire output 248 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_0__core__o + wire input 94 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_0__core__oe + wire input 95 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dq_0__pad__i + wire input 93 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__pad__o + wire output 249 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_0__pad__oe + wire output 250 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_10__core__i + wire output 302 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__core__o + wire input 148 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_10__core__oe + wire input 149 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_10__pad__i + wire input 147 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_10__pad__o + wire output 303 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_10__pad__oe + wire output 304 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_11__core__i + wire output 305 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__core__o + wire input 151 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_11__core__oe + wire input 152 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_11__pad__i + wire input 150 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_11__pad__o + wire output 306 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_11__pad__oe + wire output 307 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__core__i + wire output 308 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__core__o + wire input 154 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_12__core__oe + wire input 155 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_12__pad__i + wire input 153 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__o + wire output 309 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_12__pad__oe + wire output 310 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_13__core__i + wire output 311 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__core__o + wire input 157 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_13__core__oe + wire input 158 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_13__pad__i + wire input 156 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_13__pad__o + wire output 312 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_13__pad__oe + wire output 313 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_14__core__i + wire output 314 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__core__o + wire input 160 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_14__core__oe + wire input 161 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_14__pad__i + wire input 159 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_14__pad__o + wire output 315 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__pad__oe + wire output 316 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_15__core__i + wire output 317 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__core__o + wire input 163 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_15__core__oe + wire input 164 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_15__pad__i + wire input 162 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__pad__o + wire output 318 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_15__pad__oe + wire output 319 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_1__core__i + wire output 251 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_1__core__o + wire input 97 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_1__core__oe + wire input 98 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_1__pad__i + wire input 96 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__pad__o + wire output 252 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_1__pad__oe + wire output 253 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_2__core__i + wire output 254 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_2__core__o + wire input 100 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_2__core__oe + wire input 101 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_2__pad__i + wire input 99 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__pad__o + wire output 255 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_2__pad__oe + wire output 256 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_3__core__i + wire output 257 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_3__core__o + wire input 103 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_3__core__oe + wire input 104 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_3__pad__i + wire input 102 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__pad__o + wire output 258 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_3__pad__oe + wire output 259 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_4__core__i + wire output 260 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_4__core__o + wire input 106 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_4__core__oe + wire input 107 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_4__pad__i + wire input 105 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__pad__o + wire output 261 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_4__pad__oe + wire output 262 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_5__core__i + wire output 263 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_5__core__o + wire input 109 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_5__core__oe + wire input 110 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_5__pad__i + wire input 108 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__pad__o + wire output 264 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_5__pad__oe + wire output 265 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_6__core__i + wire output 266 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_6__core__o + wire input 112 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_6__core__oe + wire input 113 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_6__pad__i + wire input 111 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__pad__o + wire output 267 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_6__pad__oe + wire output 268 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_7__core__i + wire output 269 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_7__core__o + wire input 115 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_7__core__oe + wire input 116 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_7__pad__i + wire input 114 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__pad__o + wire output 270 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_7__pad__oe + wire output 271 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_8__core__i + wire output 296 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__core__o + wire input 142 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_8__core__oe + wire input 143 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_8__pad__i + wire input 141 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_8__pad__o + wire output 297 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_8__pad__oe + wire output 298 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_9__core__i + wire output 299 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__core__o + wire input 145 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_9__core__oe + wire input 146 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_9__pad__i + wire input 144 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_9__pad__o + wire output 300 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_9__pad__oe + wire output 301 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_ras_n__core__o + wire input 131 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_ras_n__pad__o + wire output 286 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_we_n__core__o + wire input 133 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_we_n__pad__o + wire output 288 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" @@ -201501,24 +217279,24 @@ module \jtag wire \sr0_update_core_prev attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr0_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire width 2 \sr5__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire width 3 \sr5__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire \sr5__ie - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire width 2 \sr5__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire width 3 \sr5__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire \sr5__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire \sr5__oe$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \sr5_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire \sr5_isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 2 \sr5_reg + wire width 3 \sr5_reg attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 2 \sr5_reg$next + wire width 3 \sr5_reg$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \sr5_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" @@ -201531,16 +217309,20 @@ module \jtag wire \sr5_update_core_prev attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr5_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire output 9 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire \wb_dcache_en$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire output 8 \wb_dcache_en + wire output 10 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire \wb_dcache_en$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire output 9 \wb_icache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire \wb_icache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire output 8 \wb_sram_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:127864$5535 + cell $add $add$libresoc.v:137583$5852 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -201548,10 +217330,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:127864$5535_Y + connect \Y $add$libresoc.v:137583$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:127866$5537 + cell $add $add$libresoc.v:137585$5854 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -201559,10 +217341,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:127866$5537_Y + connect \Y $add$libresoc.v:137585$5854_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:127872$5544 + cell $add $add$libresoc.v:137591$5861 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201570,10 +217352,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:127872$5544_Y + connect \Y $add$libresoc.v:137591$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:127873$5545 + cell $add $add$libresoc.v:137592$5862 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201581,10 +217363,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:127873$5545_Y + connect \Y $add$libresoc.v:137592$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:127688$5359 + cell $and $and$libresoc.v:137407$5676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201592,10 +217374,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture - connect \Y $and$libresoc.v:127688$5359_Y + connect \Y $and$libresoc.v:137407$5676_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:127755$5426 + cell $and $and$libresoc.v:137474$5743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201603,10 +217385,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 - connect \Y $and$libresoc.v:127755$5426_Y + connect \Y $and$libresoc.v:137474$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:127766$5437 + cell $and $and$libresoc.v:137485$5754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201614,10 +217396,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift - connect \Y $and$libresoc.v:127766$5437_Y + connect \Y $and$libresoc.v:137485$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:127794$5465 + cell $and $and$libresoc.v:137513$5782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201625,10 +217407,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$367 - connect \Y $and$libresoc.v:127794$5465_Y + connect \Y $and$libresoc.v:137513$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:127797$5468 + cell $and $and$libresoc.v:137516$5785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201636,10 +217418,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$373 connect \B \_fsm_capture - connect \Y $and$libresoc.v:127797$5468_Y + connect \Y $and$libresoc.v:137516$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:127800$5471 + cell $and $and$libresoc.v:137519$5788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201647,10 +217429,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$377 connect \B \_fsm_shift - connect \Y $and$libresoc.v:127800$5471_Y + connect \Y $and$libresoc.v:137519$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:127802$5473 + cell $and $and$libresoc.v:137521$5790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201658,10 +217440,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$381 connect \B \_fsm_update - connect \Y $and$libresoc.v:127802$5473_Y + connect \Y $and$libresoc.v:137521$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:127804$5475 + cell $and $and$libresoc.v:137523$5792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201669,10 +217451,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev connect \B \$385 - connect \Y $and$libresoc.v:127804$5475_Y + connect \Y $and$libresoc.v:137523$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:127807$5478 + cell $and $and$libresoc.v:137526$5795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201680,10 +217462,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$391 connect \B \_fsm_capture - connect \Y $and$libresoc.v:127807$5478_Y + connect \Y $and$libresoc.v:137526$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:127809$5480 + cell $and $and$libresoc.v:137528$5797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201691,10 +217473,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$395 connect \B \_fsm_shift - connect \Y $and$libresoc.v:127809$5480_Y + connect \Y $and$libresoc.v:137528$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:127813$5484 + cell $and $and$libresoc.v:137532$5801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201702,10 +217484,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$399 connect \B \_fsm_update - connect \Y $and$libresoc.v:127813$5484_Y + connect \Y $and$libresoc.v:137532$5801_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:127815$5486 + cell $and $and$libresoc.v:137534$5803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201713,10 +217495,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev connect \B \$403 - connect \Y $and$libresoc.v:127815$5486_Y + connect \Y $and$libresoc.v:137534$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:127819$5490 + cell $and $and$libresoc.v:137538$5807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201724,10 +217506,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$411 connect \B \_fsm_capture - connect \Y $and$libresoc.v:127819$5490_Y + connect \Y $and$libresoc.v:137538$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:127821$5492 + cell $and $and$libresoc.v:137540$5809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201735,10 +217517,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$415 connect \B \_fsm_shift - connect \Y $and$libresoc.v:127821$5492_Y + connect \Y $and$libresoc.v:137540$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:127824$5495 + cell $and $and$libresoc.v:137543$5812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201746,10 +217528,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$419 connect \B \_fsm_update - connect \Y $and$libresoc.v:127824$5495_Y + connect \Y $and$libresoc.v:137543$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:127826$5497 + cell $and $and$libresoc.v:137545$5814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201757,10 +217539,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev connect \B \$423 - connect \Y $and$libresoc.v:127826$5497_Y + connect \Y $and$libresoc.v:137545$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:127829$5500 + cell $and $and$libresoc.v:137548$5817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201768,10 +217550,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$429 connect \B \_fsm_capture - connect \Y $and$libresoc.v:127829$5500_Y + connect \Y $and$libresoc.v:137548$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:127831$5502 + cell $and $and$libresoc.v:137550$5819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201779,10 +217561,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$433 connect \B \_fsm_shift - connect \Y $and$libresoc.v:127831$5502_Y + connect \Y $and$libresoc.v:137550$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:127833$5504 + cell $and $and$libresoc.v:137552$5821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201790,10 +217572,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$41 - connect \Y $and$libresoc.v:127833$5504_Y + connect \Y $and$libresoc.v:137552$5821_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:127834$5505 + cell $and $and$libresoc.v:137553$5822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201801,10 +217583,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$437 connect \B \_fsm_update - connect \Y $and$libresoc.v:127834$5505_Y + connect \Y $and$libresoc.v:137553$5822_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:127836$5507 + cell $and $and$libresoc.v:137555$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201812,10 +217594,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev connect \B \$441 - connect \Y $and$libresoc.v:127836$5507_Y + connect \Y $and$libresoc.v:137555$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:127840$5511 + cell $and $and$libresoc.v:137559$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201823,10 +217605,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$449 connect \B \_fsm_capture - connect \Y $and$libresoc.v:127840$5511_Y + connect \Y $and$libresoc.v:137559$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:127842$5513 + cell $and $and$libresoc.v:137561$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201834,10 +217616,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$453 connect \B \_fsm_shift - connect \Y $and$libresoc.v:127842$5513_Y + connect \Y $and$libresoc.v:137561$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:127844$5515 + cell $and $and$libresoc.v:137563$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201845,10 +217627,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$43 connect \B \_fsm_update - connect \Y $and$libresoc.v:127844$5515_Y + connect \Y $and$libresoc.v:137563$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:127845$5516 + cell $and $and$libresoc.v:137564$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201856,10 +217638,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$457 connect \B \_fsm_update - connect \Y $and$libresoc.v:127845$5516_Y + connect \Y $and$libresoc.v:137564$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:127847$5518 + cell $and $and$libresoc.v:137566$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201867,10 +217649,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev connect \B \$461 - connect \Y $and$libresoc.v:127847$5518_Y + connect \Y $and$libresoc.v:137566$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:127850$5521 + cell $and $and$libresoc.v:137569$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201878,10 +217660,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$467 connect \B \_fsm_capture - connect \Y $and$libresoc.v:127850$5521_Y + connect \Y $and$libresoc.v:137569$5838_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:127852$5523 + cell $and $and$libresoc.v:137571$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201889,10 +217671,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$471 connect \B \_fsm_shift - connect \Y $and$libresoc.v:127852$5523_Y + connect \Y $and$libresoc.v:137571$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:127854$5525 + cell $and $and$libresoc.v:137573$5842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201900,10 +217682,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$475 connect \B \_fsm_update - connect \Y $and$libresoc.v:127854$5525_Y + connect \Y $and$libresoc.v:137573$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:127857$5528 + cell $and $and$libresoc.v:137576$5845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201911,10 +217693,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev connect \B \$479 - connect \Y $and$libresoc.v:127857$5528_Y + connect \Y $and$libresoc.v:137576$5845_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:127889$5561 + cell $and $and$libresoc.v:137608$5878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -201922,10 +217704,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 - connect \Y $and$libresoc.v:127889$5561_Y + connect \Y $and$libresoc.v:137608$5878_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:127644$5315 + cell $eq $eq$libresoc.v:137363$5632 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201933,10 +217715,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:127644$5315_Y + connect \Y $eq$libresoc.v:137363$5632_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127655$5326 + cell $eq $eq$libresoc.v:137374$5643 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201944,10 +217726,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:127655$5326_Y + connect \Y $eq$libresoc.v:137374$5643_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127666$5337 + cell $eq $eq$libresoc.v:137385$5654 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201955,10 +217737,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:127666$5337_Y + connect \Y $eq$libresoc.v:137385$5654_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:127699$5370 + cell $eq $eq$libresoc.v:137418$5687 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201966,10 +217748,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:127699$5370_Y + connect \Y $eq$libresoc.v:137418$5687_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127700$5371 + cell $eq $eq$libresoc.v:137419$5688 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201977,10 +217759,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:127700$5371_Y + connect \Y $eq$libresoc.v:137419$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127711$5382 + cell $eq $eq$libresoc.v:137430$5699 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201988,10 +217770,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:127711$5382_Y + connect \Y $eq$libresoc.v:137430$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:127733$5404 + cell $eq $eq$libresoc.v:137452$5721 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -201999,10 +217781,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:127733$5404_Y + connect \Y $eq$libresoc.v:137452$5721_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127777$5448 + cell $eq $eq$libresoc.v:137496$5765 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202010,10 +217792,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:127777$5448_Y + connect \Y $eq$libresoc.v:137496$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127788$5459 + cell $eq $eq$libresoc.v:137507$5776 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202021,10 +217803,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:127788$5459_Y + connect \Y $eq$libresoc.v:137507$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127789$5460 + cell $eq $eq$libresoc.v:137508$5777 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202032,10 +217814,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:127789$5460_Y + connect \Y $eq$libresoc.v:137508$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127790$5461 + cell $eq $eq$libresoc.v:137509$5778 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202043,10 +217825,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:127790$5461_Y + connect \Y $eq$libresoc.v:137509$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:127792$5463 + cell $eq $eq$libresoc.v:137511$5780 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202054,10 +217836,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:127792$5463_Y + connect \Y $eq$libresoc.v:137511$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127795$5466 + cell $eq $eq$libresoc.v:137514$5783 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202065,10 +217847,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:127795$5466_Y + connect \Y $eq$libresoc.v:137514$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127805$5476 + cell $eq $eq$libresoc.v:137524$5793 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202076,10 +217858,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'101 - connect \Y $eq$libresoc.v:127805$5476_Y + connect \Y $eq$libresoc.v:137524$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:127810$5481 + cell $eq $eq$libresoc.v:137529$5798 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202087,10 +217869,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:127810$5481_Y + connect \Y $eq$libresoc.v:137529$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:127811$5482 + cell $eq $eq$libresoc.v:137530$5799 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202098,10 +217880,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:127811$5482_Y + connect \Y $eq$libresoc.v:137530$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127816$5487 + cell $eq $eq$libresoc.v:137535$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202109,10 +217891,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 - connect \Y $eq$libresoc.v:127816$5487_Y + connect \Y $eq$libresoc.v:137535$5804_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127817$5488 + cell $eq $eq$libresoc.v:137536$5805 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202120,10 +217902,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:127817$5488_Y + connect \Y $eq$libresoc.v:137536$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127827$5498 + cell $eq $eq$libresoc.v:137546$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202131,10 +217913,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:127827$5498_Y + connect \Y $eq$libresoc.v:137546$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127837$5508 + cell $eq $eq$libresoc.v:137556$5825 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202142,10 +217924,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:127837$5508_Y + connect \Y $eq$libresoc.v:137556$5825_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127838$5509 + cell $eq $eq$libresoc.v:137557$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202153,10 +217935,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1010 - connect \Y $eq$libresoc.v:127838$5509_Y + connect \Y $eq$libresoc.v:137557$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127848$5519 + cell $eq $eq$libresoc.v:137567$5836 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202164,10 +217946,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1011 - connect \Y $eq$libresoc.v:127848$5519_Y + connect \Y $eq$libresoc.v:137567$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:127855$5526 + cell $eq $eq$libresoc.v:137574$5843 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202175,10 +217957,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:127855$5526_Y + connect \Y $eq$libresoc.v:137574$5843_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:127858$5529 + cell $eq $eq$libresoc.v:137577$5846 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -202186,10 +217968,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:127858$5529_Y + connect \Y $eq$libresoc.v:137577$5846_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:127860$5531 + cell $eq $eq$libresoc.v:137579$5848 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -202197,10 +217979,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:127860$5531_Y + connect \Y $eq$libresoc.v:137579$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:127861$5532 + cell $eq $eq$libresoc.v:137580$5849 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -202208,10 +217990,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:127861$5532_Y + connect \Y $eq$libresoc.v:137580$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:127863$5534 + cell $eq $eq$libresoc.v:137582$5851 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -202219,10 +218001,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:127863$5534_Y + connect \Y $eq$libresoc.v:137582$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:127865$5536 + cell $eq $eq$libresoc.v:137584$5853 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -202230,10 +218012,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:127865$5536_Y + connect \Y $eq$libresoc.v:137584$5853_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:127868$5540 + cell $eq $eq$libresoc.v:137587$5857 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -202241,10 +218023,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$503 connect \B 1'1 - connect \Y $eq$libresoc.v:127868$5540_Y + connect \Y $eq$libresoc.v:137587$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:127869$5541 + cell $eq $eq$libresoc.v:137588$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -202252,10 +218034,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$503 connect \B 2'10 - connect \Y $eq$libresoc.v:127869$5541_Y + connect \Y $eq$libresoc.v:137588$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:127871$5543 + cell $eq $eq$libresoc.v:137590$5860 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -202263,18 +218045,18 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$503 connect \B 2'10 - connect \Y $eq$libresoc.v:127871$5543_Y + connect \Y $eq$libresoc.v:137590$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:127867$5538 + cell $pos $extend$libresoc.v:137586$5855 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:127867$5538_Y + connect \Y $extend$libresoc.v:137586$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:127796$5467 + cell $ne $ne$libresoc.v:137515$5784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202282,10 +218064,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127796$5467_Y + connect \Y $ne$libresoc.v:137515$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:127798$5469 + cell $ne $ne$libresoc.v:137517$5786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202293,10 +218075,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127798$5469_Y + connect \Y $ne$libresoc.v:137517$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:127801$5472 + cell $ne $ne$libresoc.v:137520$5789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202304,10 +218086,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127801$5472_Y + connect \Y $ne$libresoc.v:137520$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:127806$5477 + cell $ne $ne$libresoc.v:137525$5794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202315,10 +218097,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127806$5477_Y + connect \Y $ne$libresoc.v:137525$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:127808$5479 + cell $ne $ne$libresoc.v:137527$5796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202326,10 +218108,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127808$5479_Y + connect \Y $ne$libresoc.v:137527$5796_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:127812$5483 + cell $ne $ne$libresoc.v:137531$5800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202337,10 +218119,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127812$5483_Y + connect \Y $ne$libresoc.v:137531$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:127818$5489 + cell $ne $ne$libresoc.v:137537$5806 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -202348,10 +218130,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127818$5489_Y + connect \Y $ne$libresoc.v:137537$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:127820$5491 + cell $ne $ne$libresoc.v:137539$5808 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -202359,10 +218141,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127820$5491_Y + connect \Y $ne$libresoc.v:137539$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:127823$5494 + cell $ne $ne$libresoc.v:137542$5811 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -202370,10 +218152,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127823$5494_Y + connect \Y $ne$libresoc.v:137542$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:127828$5499 + cell $ne $ne$libresoc.v:137547$5816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202381,10 +218163,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127828$5499_Y + connect \Y $ne$libresoc.v:137547$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:127830$5501 + cell $ne $ne$libresoc.v:137549$5818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202392,10 +218174,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127830$5501_Y + connect \Y $ne$libresoc.v:137549$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:127832$5503 + cell $ne $ne$libresoc.v:137551$5820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202403,10 +218185,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127832$5503_Y + connect \Y $ne$libresoc.v:137551$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:127839$5510 + cell $ne $ne$libresoc.v:137558$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -202414,10 +218196,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127839$5510_Y + connect \Y $ne$libresoc.v:137558$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:127841$5512 + cell $ne $ne$libresoc.v:137560$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -202425,10 +218207,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127841$5512_Y + connect \Y $ne$libresoc.v:137560$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:127843$5514 + cell $ne $ne$libresoc.v:137562$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -202436,10 +218218,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127843$5514_Y + connect \Y $ne$libresoc.v:137562$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:127849$5520 + cell $ne $ne$libresoc.v:137568$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202447,10 +218229,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127849$5520_Y + connect \Y $ne$libresoc.v:137568$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:127851$5522 + cell $ne $ne$libresoc.v:137570$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202458,10 +218240,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127851$5522_Y + connect \Y $ne$libresoc.v:137570$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:127853$5524 + cell $ne $ne$libresoc.v:137572$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202469,66 +218251,66 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:127853$5524_Y + connect \Y $ne$libresoc.v:137572$5841_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:127803$5474 + cell $not $not$libresoc.v:137522$5791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:127803$5474_Y + connect \Y $not$libresoc.v:137522$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:127814$5485 + cell $not $not$libresoc.v:137533$5802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:127814$5485_Y + connect \Y $not$libresoc.v:137533$5802_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:127825$5496 + cell $not $not$libresoc.v:137544$5813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:127825$5496_Y + connect \Y $not$libresoc.v:137544$5813_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:127835$5506 + cell $not $not$libresoc.v:137554$5823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:127835$5506_Y + connect \Y $not$libresoc.v:137554$5823_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:127846$5517 + cell $not $not$libresoc.v:137565$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:127846$5517_Y + connect \Y $not$libresoc.v:137565$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:127856$5527 + cell $not $not$libresoc.v:137575$5844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core - connect \Y $not$libresoc.v:127856$5527_Y + connect \Y $not$libresoc.v:137575$5844_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:127859$5530 + cell $not $not$libresoc.v:137578$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$484 - connect \Y $not$libresoc.v:127859$5530_Y + connect \Y $not$libresoc.v:137578$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:127677$5348 + cell $or $or$libresoc.v:137396$5665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202536,10 +218318,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 - connect \Y $or$libresoc.v:127677$5348_Y + connect \Y $or$libresoc.v:137396$5665_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:127722$5393 + cell $or $or$libresoc.v:137441$5710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202547,10 +218329,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 - connect \Y $or$libresoc.v:127722$5393_Y + connect \Y $or$libresoc.v:137441$5710_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:127744$5415 + cell $or $or$libresoc.v:137463$5732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202558,10 +218340,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:127744$5415_Y + connect \Y $or$libresoc.v:137463$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:127791$5462 + cell $or $or$libresoc.v:137510$5779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202569,10 +218351,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$359 connect \B \$361 - connect \Y $or$libresoc.v:127791$5462_Y + connect \Y $or$libresoc.v:137510$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:127793$5464 + cell $or $or$libresoc.v:137512$5781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202580,10 +218362,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$363 connect \B \$365 - connect \Y $or$libresoc.v:127793$5464_Y + connect \Y $or$libresoc.v:137512$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:127799$5470 + cell $or $or$libresoc.v:137518$5787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202591,10 +218373,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:127799$5470_Y + connect \Y $or$libresoc.v:137518$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:127822$5493 + cell $or $or$libresoc.v:137541$5810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202602,10 +218384,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:127822$5493_Y + connect \Y $or$libresoc.v:137541$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:127862$5533 + cell $or $or$libresoc.v:137581$5850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202613,10 +218395,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$487 connect \B \$489 - connect \Y $or$libresoc.v:127862$5533_Y + connect \Y $or$libresoc.v:137581$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:127870$5542 + cell $or $or$libresoc.v:137589$5859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202624,10 +218406,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$504 connect \B \$506 - connect \Y $or$libresoc.v:127870$5542_Y + connect \Y $or$libresoc.v:137589$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:127878$5550 + cell $or $or$libresoc.v:137597$5867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202635,1250 +218417,1250 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:127878$5550_Y + connect \Y $or$libresoc.v:137597$5867_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:127867$5539 + cell $pos $pos$libresoc.v:137586$5856 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:127867$5538_Y - connect \Y $pos$libresoc.v:127867$5539_Y + connect \A $extend$libresoc.v:137586$5855_Y + connect \Y $pos$libresoc.v:137586$5856_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127645$5316 + cell $mux $ternary$libresoc.v:137364$5633 parameter \WIDTH 1 connect \A \gpio_e15__pad__i connect \B \io_bd [24] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127645$5316_Y + connect \Y $ternary$libresoc.v:137364$5633_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127646$5317 + cell $mux $ternary$libresoc.v:137365$5634 parameter \WIDTH 1 connect \A \gpio_e15__core__o connect \B \io_bd [25] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127646$5317_Y + connect \Y $ternary$libresoc.v:137365$5634_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127647$5318 + cell $mux $ternary$libresoc.v:137366$5635 parameter \WIDTH 1 connect \A \gpio_e15__core__oe connect \B \io_bd [26] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127647$5318_Y + connect \Y $ternary$libresoc.v:137366$5635_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127648$5319 + cell $mux $ternary$libresoc.v:137367$5636 parameter \WIDTH 1 connect \A \gpio_s0__pad__i connect \B \io_bd [27] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127648$5319_Y + connect \Y $ternary$libresoc.v:137367$5636_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127649$5320 + cell $mux $ternary$libresoc.v:137368$5637 parameter \WIDTH 1 connect \A \gpio_s0__core__o connect \B \io_bd [28] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127649$5320_Y + connect \Y $ternary$libresoc.v:137368$5637_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127650$5321 + cell $mux $ternary$libresoc.v:137369$5638 parameter \WIDTH 1 connect \A \gpio_s0__core__oe connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127650$5321_Y + connect \Y $ternary$libresoc.v:137369$5638_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127651$5322 + cell $mux $ternary$libresoc.v:137370$5639 parameter \WIDTH 1 connect \A \gpio_s1__pad__i connect \B \io_bd [30] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127651$5322_Y + connect \Y $ternary$libresoc.v:137370$5639_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127652$5323 + cell $mux $ternary$libresoc.v:137371$5640 parameter \WIDTH 1 connect \A \gpio_s1__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127652$5323_Y + connect \Y $ternary$libresoc.v:137371$5640_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127653$5324 + cell $mux $ternary$libresoc.v:137372$5641 parameter \WIDTH 1 connect \A \gpio_s1__core__oe connect \B \io_bd [32] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127653$5324_Y + connect \Y $ternary$libresoc.v:137372$5641_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127654$5325 + cell $mux $ternary$libresoc.v:137373$5642 parameter \WIDTH 1 connect \A \gpio_s2__pad__i connect \B \io_bd [33] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127654$5325_Y + connect \Y $ternary$libresoc.v:137373$5642_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127656$5327 + cell $mux $ternary$libresoc.v:137375$5644 parameter \WIDTH 1 connect \A \gpio_s2__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127656$5327_Y + connect \Y $ternary$libresoc.v:137375$5644_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127657$5328 + cell $mux $ternary$libresoc.v:137376$5645 parameter \WIDTH 1 connect \A \gpio_s2__core__oe connect \B \io_bd [35] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127657$5328_Y + connect \Y $ternary$libresoc.v:137376$5645_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127658$5329 + cell $mux $ternary$libresoc.v:137377$5646 parameter \WIDTH 1 connect \A \gpio_s3__pad__i connect \B \io_bd [36] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127658$5329_Y + connect \Y $ternary$libresoc.v:137377$5646_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127659$5330 + cell $mux $ternary$libresoc.v:137378$5647 parameter \WIDTH 1 connect \A \gpio_s3__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127659$5330_Y + connect \Y $ternary$libresoc.v:137378$5647_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127660$5331 + cell $mux $ternary$libresoc.v:137379$5648 parameter \WIDTH 1 connect \A \gpio_s3__core__oe connect \B \io_bd [38] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127660$5331_Y + connect \Y $ternary$libresoc.v:137379$5648_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127661$5332 + cell $mux $ternary$libresoc.v:137380$5649 parameter \WIDTH 1 connect \A \gpio_s4__pad__i connect \B \io_bd [39] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127661$5332_Y + connect \Y $ternary$libresoc.v:137380$5649_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127662$5333 + cell $mux $ternary$libresoc.v:137381$5650 parameter \WIDTH 1 connect \A \gpio_s4__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127662$5333_Y + connect \Y $ternary$libresoc.v:137381$5650_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127663$5334 + cell $mux $ternary$libresoc.v:137382$5651 parameter \WIDTH 1 connect \A \gpio_s4__core__oe connect \B \io_bd [41] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127663$5334_Y + connect \Y $ternary$libresoc.v:137382$5651_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127664$5335 + cell $mux $ternary$libresoc.v:137383$5652 parameter \WIDTH 1 connect \A \gpio_s5__pad__i connect \B \io_bd [42] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127664$5335_Y + connect \Y $ternary$libresoc.v:137383$5652_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127665$5336 + cell $mux $ternary$libresoc.v:137384$5653 parameter \WIDTH 1 connect \A \gpio_s5__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127665$5336_Y + connect \Y $ternary$libresoc.v:137384$5653_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127667$5338 + cell $mux $ternary$libresoc.v:137386$5655 parameter \WIDTH 1 connect \A \gpio_s5__core__oe connect \B \io_bd [44] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127667$5338_Y + connect \Y $ternary$libresoc.v:137386$5655_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127668$5339 + cell $mux $ternary$libresoc.v:137387$5656 parameter \WIDTH 1 connect \A \gpio_s6__pad__i connect \B \io_bd [45] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127668$5339_Y + connect \Y $ternary$libresoc.v:137387$5656_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127669$5340 + cell $mux $ternary$libresoc.v:137388$5657 parameter \WIDTH 1 connect \A \gpio_s6__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127669$5340_Y + connect \Y $ternary$libresoc.v:137388$5657_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127670$5341 + cell $mux $ternary$libresoc.v:137389$5658 parameter \WIDTH 1 connect \A \gpio_s6__core__oe connect \B \io_bd [47] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127670$5341_Y + connect \Y $ternary$libresoc.v:137389$5658_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127671$5342 + cell $mux $ternary$libresoc.v:137390$5659 parameter \WIDTH 1 connect \A \gpio_s7__pad__i connect \B \io_bd [48] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127671$5342_Y + connect \Y $ternary$libresoc.v:137390$5659_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127672$5343 + cell $mux $ternary$libresoc.v:137391$5660 parameter \WIDTH 1 connect \A \gpio_s7__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127672$5343_Y + connect \Y $ternary$libresoc.v:137391$5660_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127673$5344 + cell $mux $ternary$libresoc.v:137392$5661 parameter \WIDTH 1 connect \A \gpio_s7__core__oe connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127673$5344_Y + connect \Y $ternary$libresoc.v:137392$5661_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127674$5345 + cell $mux $ternary$libresoc.v:137393$5662 parameter \WIDTH 1 connect \A \mspi0_clk__core__o connect \B \io_bd [51] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127674$5345_Y + connect \Y $ternary$libresoc.v:137393$5662_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127675$5346 + cell $mux $ternary$libresoc.v:137394$5663 parameter \WIDTH 1 connect \A \mspi0_cs_n__core__o connect \B \io_bd [52] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127675$5346_Y + connect \Y $ternary$libresoc.v:137394$5663_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127676$5347 + cell $mux $ternary$libresoc.v:137395$5664 parameter \WIDTH 1 connect \A \mspi0_mosi__core__o connect \B \io_bd [53] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127676$5347_Y + connect \Y $ternary$libresoc.v:137395$5664_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:127678$5349 + cell $mux $ternary$libresoc.v:137397$5666 parameter \WIDTH 1 connect \A \mspi0_miso__pad__i connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127678$5349_Y + connect \Y $ternary$libresoc.v:137397$5666_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127679$5350 + cell $mux $ternary$libresoc.v:137398$5667 parameter \WIDTH 1 connect \A \mspi1_clk__core__o connect \B \io_bd [55] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127679$5350_Y + connect \Y $ternary$libresoc.v:137398$5667_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127680$5351 + cell $mux $ternary$libresoc.v:137399$5668 parameter \WIDTH 1 connect \A \mspi1_cs_n__core__o connect \B \io_bd [56] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127680$5351_Y + connect \Y $ternary$libresoc.v:137399$5668_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127681$5352 + cell $mux $ternary$libresoc.v:137400$5669 parameter \WIDTH 1 connect \A \mspi1_mosi__core__o connect \B \io_bd [57] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127681$5352_Y + connect \Y $ternary$libresoc.v:137400$5669_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:127682$5353 + cell $mux $ternary$libresoc.v:137401$5670 parameter \WIDTH 1 connect \A \mspi1_miso__pad__i connect \B \io_bd [58] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127682$5353_Y + connect \Y $ternary$libresoc.v:137401$5670_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127683$5354 + cell $mux $ternary$libresoc.v:137402$5671 parameter \WIDTH 1 connect \A \mtwi_sda__pad__i connect \B \io_bd [59] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127683$5354_Y + connect \Y $ternary$libresoc.v:137402$5671_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127684$5355 + cell $mux $ternary$libresoc.v:137403$5672 parameter \WIDTH 1 connect \A \mtwi_sda__core__o connect \B \io_bd [60] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127684$5355_Y + connect \Y $ternary$libresoc.v:137403$5672_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127685$5356 + cell $mux $ternary$libresoc.v:137404$5673 parameter \WIDTH 1 connect \A \mtwi_sda__core__oe connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127685$5356_Y + connect \Y $ternary$libresoc.v:137404$5673_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127686$5357 + cell $mux $ternary$libresoc.v:137405$5674 parameter \WIDTH 1 connect \A \mtwi_scl__core__o connect \B \io_bd [62] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127686$5357_Y + connect \Y $ternary$libresoc.v:137405$5674_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127687$5358 + cell $mux $ternary$libresoc.v:137406$5675 parameter \WIDTH 1 connect \A \pwm_0__core__o connect \B \io_bd [63] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127687$5358_Y + connect \Y $ternary$libresoc.v:137406$5675_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127689$5360 + cell $mux $ternary$libresoc.v:137408$5677 parameter \WIDTH 1 connect \A \pwm_1__core__o connect \B \io_bd [64] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127689$5360_Y + connect \Y $ternary$libresoc.v:137408$5677_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127690$5361 + cell $mux $ternary$libresoc.v:137409$5678 parameter \WIDTH 1 connect \A \sd0_cmd__pad__i connect \B \io_bd [65] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127690$5361_Y + connect \Y $ternary$libresoc.v:137409$5678_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127691$5362 + cell $mux $ternary$libresoc.v:137410$5679 parameter \WIDTH 1 connect \A \sd0_cmd__core__o connect \B \io_bd [66] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127691$5362_Y + connect \Y $ternary$libresoc.v:137410$5679_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127692$5363 + cell $mux $ternary$libresoc.v:137411$5680 parameter \WIDTH 1 connect \A \sd0_cmd__core__oe connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127692$5363_Y + connect \Y $ternary$libresoc.v:137411$5680_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127693$5364 + cell $mux $ternary$libresoc.v:137412$5681 parameter \WIDTH 1 connect \A \sd0_clk__core__o connect \B \io_bd [68] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127693$5364_Y + connect \Y $ternary$libresoc.v:137412$5681_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127694$5365 + cell $mux $ternary$libresoc.v:137413$5682 parameter \WIDTH 1 connect \A \sd0_data0__pad__i connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127694$5365_Y + connect \Y $ternary$libresoc.v:137413$5682_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127695$5366 + cell $mux $ternary$libresoc.v:137414$5683 parameter \WIDTH 1 connect \A \sd0_data0__core__o connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127695$5366_Y + connect \Y $ternary$libresoc.v:137414$5683_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127696$5367 + cell $mux $ternary$libresoc.v:137415$5684 parameter \WIDTH 1 connect \A \sd0_data0__core__oe connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127696$5367_Y + connect \Y $ternary$libresoc.v:137415$5684_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127697$5368 + cell $mux $ternary$libresoc.v:137416$5685 parameter \WIDTH 1 connect \A \sd0_data1__pad__i connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127697$5368_Y + connect \Y $ternary$libresoc.v:137416$5685_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127698$5369 + cell $mux $ternary$libresoc.v:137417$5686 parameter \WIDTH 1 connect \A \sd0_data1__core__o connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127698$5369_Y + connect \Y $ternary$libresoc.v:137417$5686_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127701$5372 + cell $mux $ternary$libresoc.v:137420$5689 parameter \WIDTH 1 connect \A \sd0_data1__core__oe connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127701$5372_Y + connect \Y $ternary$libresoc.v:137420$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127702$5373 + cell $mux $ternary$libresoc.v:137421$5690 parameter \WIDTH 1 connect \A \sd0_data2__pad__i connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127702$5373_Y + connect \Y $ternary$libresoc.v:137421$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127703$5374 + cell $mux $ternary$libresoc.v:137422$5691 parameter \WIDTH 1 connect \A \sd0_data2__core__o connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127703$5374_Y + connect \Y $ternary$libresoc.v:137422$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127704$5375 + cell $mux $ternary$libresoc.v:137423$5692 parameter \WIDTH 1 connect \A \sd0_data2__core__oe connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127704$5375_Y + connect \Y $ternary$libresoc.v:137423$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127705$5376 + cell $mux $ternary$libresoc.v:137424$5693 parameter \WIDTH 1 connect \A \sd0_data3__pad__i connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127705$5376_Y + connect \Y $ternary$libresoc.v:137424$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127706$5377 + cell $mux $ternary$libresoc.v:137425$5694 parameter \WIDTH 1 connect \A \sd0_data3__core__o connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127706$5377_Y + connect \Y $ternary$libresoc.v:137425$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127707$5378 + cell $mux $ternary$libresoc.v:137426$5695 parameter \WIDTH 1 connect \A \sd0_data3__core__oe connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127707$5378_Y + connect \Y $ternary$libresoc.v:137426$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127708$5379 + cell $mux $ternary$libresoc.v:137427$5696 parameter \WIDTH 1 connect \A \sdr_dm_0__core__o connect \B \io_bd [81] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127708$5379_Y + connect \Y $ternary$libresoc.v:137427$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127709$5380 + cell $mux $ternary$libresoc.v:137428$5697 parameter \WIDTH 1 connect \A \sdr_dq_0__pad__i connect \B \io_bd [82] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127709$5380_Y + connect \Y $ternary$libresoc.v:137428$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127710$5381 + cell $mux $ternary$libresoc.v:137429$5698 parameter \WIDTH 1 connect \A \sdr_dq_0__core__o connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127710$5381_Y + connect \Y $ternary$libresoc.v:137429$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127712$5383 + cell $mux $ternary$libresoc.v:137431$5700 parameter \WIDTH 1 connect \A \sdr_dq_0__core__oe connect \B \io_bd [84] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127712$5383_Y + connect \Y $ternary$libresoc.v:137431$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127713$5384 + cell $mux $ternary$libresoc.v:137432$5701 parameter \WIDTH 1 connect \A \sdr_dq_1__pad__i connect \B \io_bd [85] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127713$5384_Y + connect \Y $ternary$libresoc.v:137432$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127714$5385 + cell $mux $ternary$libresoc.v:137433$5702 parameter \WIDTH 1 connect \A \sdr_dq_1__core__o connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127714$5385_Y + connect \Y $ternary$libresoc.v:137433$5702_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127715$5386 + cell $mux $ternary$libresoc.v:137434$5703 parameter \WIDTH 1 connect \A \sdr_dq_1__core__oe connect \B \io_bd [87] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127715$5386_Y + connect \Y $ternary$libresoc.v:137434$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127716$5387 + cell $mux $ternary$libresoc.v:137435$5704 parameter \WIDTH 1 connect \A \sdr_dq_2__pad__i connect \B \io_bd [88] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127716$5387_Y + connect \Y $ternary$libresoc.v:137435$5704_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127717$5388 + cell $mux $ternary$libresoc.v:137436$5705 parameter \WIDTH 1 connect \A \sdr_dq_2__core__o connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127717$5388_Y + connect \Y $ternary$libresoc.v:137436$5705_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127718$5389 + cell $mux $ternary$libresoc.v:137437$5706 parameter \WIDTH 1 connect \A \sdr_dq_2__core__oe connect \B \io_bd [90] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127718$5389_Y + connect \Y $ternary$libresoc.v:137437$5706_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127719$5390 + cell $mux $ternary$libresoc.v:137438$5707 parameter \WIDTH 1 connect \A \sdr_dq_3__pad__i connect \B \io_bd [91] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127719$5390_Y + connect \Y $ternary$libresoc.v:137438$5707_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127720$5391 + cell $mux $ternary$libresoc.v:137439$5708 parameter \WIDTH 1 connect \A \sdr_dq_3__core__o connect \B \io_bd [92] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127720$5391_Y + connect \Y $ternary$libresoc.v:137439$5708_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127721$5392 + cell $mux $ternary$libresoc.v:137440$5709 parameter \WIDTH 1 connect \A \sdr_dq_3__core__oe connect \B \io_bd [93] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127721$5392_Y + connect \Y $ternary$libresoc.v:137440$5709_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127723$5394 + cell $mux $ternary$libresoc.v:137442$5711 parameter \WIDTH 1 connect \A \sdr_dq_4__pad__i connect \B \io_bd [94] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127723$5394_Y + connect \Y $ternary$libresoc.v:137442$5711_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127724$5395 + cell $mux $ternary$libresoc.v:137443$5712 parameter \WIDTH 1 connect \A \sdr_dq_4__core__o connect \B \io_bd [95] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127724$5395_Y + connect \Y $ternary$libresoc.v:137443$5712_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127725$5396 + cell $mux $ternary$libresoc.v:137444$5713 parameter \WIDTH 1 connect \A \sdr_dq_4__core__oe connect \B \io_bd [96] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127725$5396_Y + connect \Y $ternary$libresoc.v:137444$5713_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127726$5397 + cell $mux $ternary$libresoc.v:137445$5714 parameter \WIDTH 1 connect \A \sdr_dq_5__pad__i connect \B \io_bd [97] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127726$5397_Y + connect \Y $ternary$libresoc.v:137445$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127727$5398 + cell $mux $ternary$libresoc.v:137446$5715 parameter \WIDTH 1 connect \A \sdr_dq_5__core__o connect \B \io_bd [98] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127727$5398_Y + connect \Y $ternary$libresoc.v:137446$5715_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127728$5399 + cell $mux $ternary$libresoc.v:137447$5716 parameter \WIDTH 1 connect \A \sdr_dq_5__core__oe connect \B \io_bd [99] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127728$5399_Y + connect \Y $ternary$libresoc.v:137447$5716_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127729$5400 + cell $mux $ternary$libresoc.v:137448$5717 parameter \WIDTH 1 connect \A \sdr_dq_6__pad__i connect \B \io_bd [100] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127729$5400_Y + connect \Y $ternary$libresoc.v:137448$5717_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127730$5401 + cell $mux $ternary$libresoc.v:137449$5718 parameter \WIDTH 1 connect \A \sdr_dq_6__core__o connect \B \io_bd [101] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127730$5401_Y + connect \Y $ternary$libresoc.v:137449$5718_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127731$5402 + cell $mux $ternary$libresoc.v:137450$5719 parameter \WIDTH 1 connect \A \sdr_dq_6__core__oe connect \B \io_bd [102] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127731$5402_Y + connect \Y $ternary$libresoc.v:137450$5719_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127732$5403 + cell $mux $ternary$libresoc.v:137451$5720 parameter \WIDTH 1 connect \A \sdr_dq_7__pad__i connect \B \io_bd [103] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127732$5403_Y + connect \Y $ternary$libresoc.v:137451$5720_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127734$5405 + cell $mux $ternary$libresoc.v:137453$5722 parameter \WIDTH 1 connect \A \sdr_dq_7__core__o connect \B \io_bd [104] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127734$5405_Y + connect \Y $ternary$libresoc.v:137453$5722_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127735$5406 + cell $mux $ternary$libresoc.v:137454$5723 parameter \WIDTH 1 connect \A \sdr_dq_7__core__oe connect \B \io_bd [105] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127735$5406_Y + connect \Y $ternary$libresoc.v:137454$5723_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127736$5407 + cell $mux $ternary$libresoc.v:137455$5724 parameter \WIDTH 1 connect \A \sdr_a_0__core__o connect \B \io_bd [106] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127736$5407_Y + connect \Y $ternary$libresoc.v:137455$5724_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127737$5408 + cell $mux $ternary$libresoc.v:137456$5725 parameter \WIDTH 1 connect \A \sdr_a_1__core__o connect \B \io_bd [107] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127737$5408_Y + connect \Y $ternary$libresoc.v:137456$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127738$5409 + cell $mux $ternary$libresoc.v:137457$5726 parameter \WIDTH 1 connect \A \sdr_a_2__core__o connect \B \io_bd [108] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127738$5409_Y + connect \Y $ternary$libresoc.v:137457$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127739$5410 + cell $mux $ternary$libresoc.v:137458$5727 parameter \WIDTH 1 connect \A \sdr_a_3__core__o connect \B \io_bd [109] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127739$5410_Y + connect \Y $ternary$libresoc.v:137458$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127740$5411 + cell $mux $ternary$libresoc.v:137459$5728 parameter \WIDTH 1 connect \A \sdr_a_4__core__o connect \B \io_bd [110] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127740$5411_Y + connect \Y $ternary$libresoc.v:137459$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127741$5412 + cell $mux $ternary$libresoc.v:137460$5729 parameter \WIDTH 1 connect \A \sdr_a_5__core__o connect \B \io_bd [111] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127741$5412_Y + connect \Y $ternary$libresoc.v:137460$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127742$5413 + cell $mux $ternary$libresoc.v:137461$5730 parameter \WIDTH 1 connect \A \sdr_a_6__core__o connect \B \io_bd [112] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127742$5413_Y + connect \Y $ternary$libresoc.v:137461$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127743$5414 + cell $mux $ternary$libresoc.v:137462$5731 parameter \WIDTH 1 connect \A \sdr_a_7__core__o connect \B \io_bd [113] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127743$5414_Y + connect \Y $ternary$libresoc.v:137462$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127745$5416 + cell $mux $ternary$libresoc.v:137464$5733 parameter \WIDTH 1 connect \A \sdr_a_8__core__o connect \B \io_bd [114] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127745$5416_Y + connect \Y $ternary$libresoc.v:137464$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127746$5417 + cell $mux $ternary$libresoc.v:137465$5734 parameter \WIDTH 1 connect \A \sdr_a_9__core__o connect \B \io_bd [115] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127746$5417_Y + connect \Y $ternary$libresoc.v:137465$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127747$5418 + cell $mux $ternary$libresoc.v:137466$5735 parameter \WIDTH 1 connect \A \sdr_ba_0__core__o connect \B \io_bd [116] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127747$5418_Y + connect \Y $ternary$libresoc.v:137466$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127748$5419 + cell $mux $ternary$libresoc.v:137467$5736 parameter \WIDTH 1 connect \A \sdr_ba_1__core__o connect \B \io_bd [117] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127748$5419_Y + connect \Y $ternary$libresoc.v:137467$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127749$5420 + cell $mux $ternary$libresoc.v:137468$5737 parameter \WIDTH 1 connect \A \sdr_clock__core__o connect \B \io_bd [118] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127749$5420_Y + connect \Y $ternary$libresoc.v:137468$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127750$5421 + cell $mux $ternary$libresoc.v:137469$5738 parameter \WIDTH 1 connect \A \sdr_cke__core__o connect \B \io_bd [119] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127750$5421_Y + connect \Y $ternary$libresoc.v:137469$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127751$5422 + cell $mux $ternary$libresoc.v:137470$5739 parameter \WIDTH 1 connect \A \sdr_ras_n__core__o connect \B \io_bd [120] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127751$5422_Y + connect \Y $ternary$libresoc.v:137470$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127752$5423 + cell $mux $ternary$libresoc.v:137471$5740 parameter \WIDTH 1 connect \A \sdr_cas_n__core__o connect \B \io_bd [121] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127752$5423_Y + connect \Y $ternary$libresoc.v:137471$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127753$5424 + cell $mux $ternary$libresoc.v:137472$5741 parameter \WIDTH 1 connect \A \sdr_we_n__core__o connect \B \io_bd [122] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127753$5424_Y + connect \Y $ternary$libresoc.v:137472$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127754$5425 + cell $mux $ternary$libresoc.v:137473$5742 parameter \WIDTH 1 connect \A \sdr_cs_n__core__o connect \B \io_bd [123] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127754$5425_Y + connect \Y $ternary$libresoc.v:137473$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127756$5427 + cell $mux $ternary$libresoc.v:137475$5744 parameter \WIDTH 1 connect \A \sdr_a_10__core__o connect \B \io_bd [124] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127756$5427_Y + connect \Y $ternary$libresoc.v:137475$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127757$5428 + cell $mux $ternary$libresoc.v:137476$5745 parameter \WIDTH 1 connect \A \sdr_a_11__core__o connect \B \io_bd [125] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127757$5428_Y + connect \Y $ternary$libresoc.v:137476$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127758$5429 + cell $mux $ternary$libresoc.v:137477$5746 parameter \WIDTH 1 connect \A \sdr_a_12__core__o connect \B \io_bd [126] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127758$5429_Y + connect \Y $ternary$libresoc.v:137477$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127759$5430 + cell $mux $ternary$libresoc.v:137478$5747 parameter \WIDTH 1 connect \A \sdr_dm_1__pad__i connect \B \io_bd [127] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127759$5430_Y + connect \Y $ternary$libresoc.v:137478$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127760$5431 + cell $mux $ternary$libresoc.v:137479$5748 parameter \WIDTH 1 connect \A \sdr_dm_1__core__o connect \B \io_bd [128] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127760$5431_Y + connect \Y $ternary$libresoc.v:137479$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127761$5432 + cell $mux $ternary$libresoc.v:137480$5749 parameter \WIDTH 1 connect \A \sdr_dm_1__core__oe connect \B \io_bd [129] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127761$5432_Y + connect \Y $ternary$libresoc.v:137480$5749_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127762$5433 + cell $mux $ternary$libresoc.v:137481$5750 parameter \WIDTH 1 connect \A \sdr_dq_8__pad__i connect \B \io_bd [130] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127762$5433_Y + connect \Y $ternary$libresoc.v:137481$5750_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127763$5434 + cell $mux $ternary$libresoc.v:137482$5751 parameter \WIDTH 1 connect \A \sdr_dq_8__core__o connect \B \io_bd [131] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127763$5434_Y + connect \Y $ternary$libresoc.v:137482$5751_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127764$5435 + cell $mux $ternary$libresoc.v:137483$5752 parameter \WIDTH 1 connect \A \sdr_dq_8__core__oe connect \B \io_bd [132] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127764$5435_Y + connect \Y $ternary$libresoc.v:137483$5752_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127765$5436 + cell $mux $ternary$libresoc.v:137484$5753 parameter \WIDTH 1 connect \A \sdr_dq_9__pad__i connect \B \io_bd [133] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127765$5436_Y + connect \Y $ternary$libresoc.v:137484$5753_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127767$5438 + cell $mux $ternary$libresoc.v:137486$5755 parameter \WIDTH 1 connect \A \sdr_dq_9__core__o connect \B \io_bd [134] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127767$5438_Y + connect \Y $ternary$libresoc.v:137486$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127768$5439 + cell $mux $ternary$libresoc.v:137487$5756 parameter \WIDTH 1 connect \A \sdr_dq_9__core__oe connect \B \io_bd [135] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127768$5439_Y + connect \Y $ternary$libresoc.v:137487$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127769$5440 + cell $mux $ternary$libresoc.v:137488$5757 parameter \WIDTH 1 connect \A \sdr_dq_10__pad__i connect \B \io_bd [136] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127769$5440_Y + connect \Y $ternary$libresoc.v:137488$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127770$5441 + cell $mux $ternary$libresoc.v:137489$5758 parameter \WIDTH 1 connect \A \sdr_dq_10__core__o connect \B \io_bd [137] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127770$5441_Y + connect \Y $ternary$libresoc.v:137489$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127771$5442 + cell $mux $ternary$libresoc.v:137490$5759 parameter \WIDTH 1 connect \A \sdr_dq_10__core__oe connect \B \io_bd [138] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127771$5442_Y + connect \Y $ternary$libresoc.v:137490$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127772$5443 + cell $mux $ternary$libresoc.v:137491$5760 parameter \WIDTH 1 connect \A \sdr_dq_11__pad__i connect \B \io_bd [139] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127772$5443_Y + connect \Y $ternary$libresoc.v:137491$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127773$5444 + cell $mux $ternary$libresoc.v:137492$5761 parameter \WIDTH 1 connect \A \sdr_dq_11__core__o connect \B \io_bd [140] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127773$5444_Y + connect \Y $ternary$libresoc.v:137492$5761_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127774$5445 + cell $mux $ternary$libresoc.v:137493$5762 parameter \WIDTH 1 connect \A \sdr_dq_11__core__oe connect \B \io_bd [141] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127774$5445_Y + connect \Y $ternary$libresoc.v:137493$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127775$5446 + cell $mux $ternary$libresoc.v:137494$5763 parameter \WIDTH 1 connect \A \sdr_dq_12__pad__i connect \B \io_bd [142] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127775$5446_Y + connect \Y $ternary$libresoc.v:137494$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127776$5447 + cell $mux $ternary$libresoc.v:137495$5764 parameter \WIDTH 1 connect \A \sdr_dq_12__core__o connect \B \io_bd [143] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127776$5447_Y + connect \Y $ternary$libresoc.v:137495$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127778$5449 + cell $mux $ternary$libresoc.v:137497$5766 parameter \WIDTH 1 connect \A \sdr_dq_12__core__oe connect \B \io_bd [144] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127778$5449_Y + connect \Y $ternary$libresoc.v:137497$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127779$5450 + cell $mux $ternary$libresoc.v:137498$5767 parameter \WIDTH 1 connect \A \sdr_dq_13__pad__i connect \B \io_bd [145] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127779$5450_Y + connect \Y $ternary$libresoc.v:137498$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127780$5451 + cell $mux $ternary$libresoc.v:137499$5768 parameter \WIDTH 1 connect \A \sdr_dq_13__core__o connect \B \io_bd [146] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127780$5451_Y + connect \Y $ternary$libresoc.v:137499$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127781$5452 + cell $mux $ternary$libresoc.v:137500$5769 parameter \WIDTH 1 connect \A \sdr_dq_13__core__oe connect \B \io_bd [147] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127781$5452_Y + connect \Y $ternary$libresoc.v:137500$5769_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127782$5453 + cell $mux $ternary$libresoc.v:137501$5770 parameter \WIDTH 1 connect \A \sdr_dq_14__pad__i connect \B \io_bd [148] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127782$5453_Y + connect \Y $ternary$libresoc.v:137501$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127783$5454 + cell $mux $ternary$libresoc.v:137502$5771 parameter \WIDTH 1 connect \A \sdr_dq_14__core__o connect \B \io_bd [149] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127783$5454_Y + connect \Y $ternary$libresoc.v:137502$5771_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127784$5455 + cell $mux $ternary$libresoc.v:137503$5772 parameter \WIDTH 1 connect \A \sdr_dq_14__core__oe connect \B \io_bd [150] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127784$5455_Y + connect \Y $ternary$libresoc.v:137503$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127785$5456 + cell $mux $ternary$libresoc.v:137504$5773 parameter \WIDTH 1 connect \A \sdr_dq_15__pad__i connect \B \io_bd [151] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127785$5456_Y + connect \Y $ternary$libresoc.v:137504$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127786$5457 + cell $mux $ternary$libresoc.v:137505$5774 parameter \WIDTH 1 connect \A \sdr_dq_15__core__o connect \B \io_bd [152] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127786$5457_Y + connect \Y $ternary$libresoc.v:137505$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127787$5458 + cell $mux $ternary$libresoc.v:137506$5775 parameter \WIDTH 1 connect \A \sdr_dq_15__core__oe connect \B \io_bd [153] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127787$5458_Y + connect \Y $ternary$libresoc.v:137506$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:127874$5546 + cell $mux $ternary$libresoc.v:137593$5863 parameter \WIDTH 1 connect \A \eint_0__pad__i connect \B \io_bd [0] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127874$5546_Y + connect \Y $ternary$libresoc.v:137593$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:127875$5547 + cell $mux $ternary$libresoc.v:137594$5864 parameter \WIDTH 1 connect \A \eint_1__pad__i connect \B \io_bd [1] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127875$5547_Y + connect \Y $ternary$libresoc.v:137594$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:127876$5548 + cell $mux $ternary$libresoc.v:137595$5865 parameter \WIDTH 1 connect \A \eint_2__pad__i connect \B \io_bd [2] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127876$5548_Y + connect \Y $ternary$libresoc.v:137595$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127877$5549 + cell $mux $ternary$libresoc.v:137596$5866 parameter \WIDTH 1 connect \A \gpio_e8__pad__i connect \B \io_bd [3] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127877$5549_Y + connect \Y $ternary$libresoc.v:137596$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127879$5551 + cell $mux $ternary$libresoc.v:137598$5868 parameter \WIDTH 1 connect \A \gpio_e8__core__o connect \B \io_bd [4] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127879$5551_Y + connect \Y $ternary$libresoc.v:137598$5868_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127880$5552 + cell $mux $ternary$libresoc.v:137599$5869 parameter \WIDTH 1 connect \A \gpio_e8__core__oe connect \B \io_bd [5] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127880$5552_Y + connect \Y $ternary$libresoc.v:137599$5869_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127881$5553 + cell $mux $ternary$libresoc.v:137600$5870 parameter \WIDTH 1 connect \A \gpio_e9__pad__i connect \B \io_bd [6] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127881$5553_Y + connect \Y $ternary$libresoc.v:137600$5870_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127882$5554 + cell $mux $ternary$libresoc.v:137601$5871 parameter \WIDTH 1 connect \A \gpio_e9__core__o connect \B \io_bd [7] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127882$5554_Y + connect \Y $ternary$libresoc.v:137601$5871_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127883$5555 + cell $mux $ternary$libresoc.v:137602$5872 parameter \WIDTH 1 connect \A \gpio_e9__core__oe connect \B \io_bd [8] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127883$5555_Y + connect \Y $ternary$libresoc.v:137602$5872_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127884$5556 + cell $mux $ternary$libresoc.v:137603$5873 parameter \WIDTH 1 connect \A \gpio_e10__pad__i connect \B \io_bd [9] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127884$5556_Y + connect \Y $ternary$libresoc.v:137603$5873_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127885$5557 + cell $mux $ternary$libresoc.v:137604$5874 parameter \WIDTH 1 connect \A \gpio_e10__core__o connect \B \io_bd [10] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127885$5557_Y + connect \Y $ternary$libresoc.v:137604$5874_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127886$5558 + cell $mux $ternary$libresoc.v:137605$5875 parameter \WIDTH 1 connect \A \gpio_e10__core__oe connect \B \io_bd [11] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127886$5558_Y + connect \Y $ternary$libresoc.v:137605$5875_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127887$5559 + cell $mux $ternary$libresoc.v:137606$5876 parameter \WIDTH 1 connect \A \gpio_e11__pad__i connect \B \io_bd [12] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127887$5559_Y + connect \Y $ternary$libresoc.v:137606$5876_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127888$5560 + cell $mux $ternary$libresoc.v:137607$5877 parameter \WIDTH 1 connect \A \gpio_e11__core__o connect \B \io_bd [13] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127888$5560_Y + connect \Y $ternary$libresoc.v:137607$5877_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127890$5562 + cell $mux $ternary$libresoc.v:137609$5879 parameter \WIDTH 1 connect \A \gpio_e11__core__oe connect \B \io_bd [14] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127890$5562_Y + connect \Y $ternary$libresoc.v:137609$5879_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127891$5563 + cell $mux $ternary$libresoc.v:137610$5880 parameter \WIDTH 1 connect \A \gpio_e12__pad__i connect \B \io_bd [15] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127891$5563_Y + connect \Y $ternary$libresoc.v:137610$5880_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127892$5564 + cell $mux $ternary$libresoc.v:137611$5881 parameter \WIDTH 1 connect \A \gpio_e12__core__o connect \B \io_bd [16] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127892$5564_Y + connect \Y $ternary$libresoc.v:137611$5881_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127893$5565 + cell $mux $ternary$libresoc.v:137612$5882 parameter \WIDTH 1 connect \A \gpio_e12__core__oe connect \B \io_bd [17] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127893$5565_Y + connect \Y $ternary$libresoc.v:137612$5882_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127894$5566 + cell $mux $ternary$libresoc.v:137613$5883 parameter \WIDTH 1 connect \A \gpio_e13__pad__i connect \B \io_bd [18] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127894$5566_Y + connect \Y $ternary$libresoc.v:137613$5883_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127895$5567 + cell $mux $ternary$libresoc.v:137614$5884 parameter \WIDTH 1 connect \A \gpio_e13__core__o connect \B \io_bd [19] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127895$5567_Y + connect \Y $ternary$libresoc.v:137614$5884_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127896$5568 + cell $mux $ternary$libresoc.v:137615$5885 parameter \WIDTH 1 connect \A \gpio_e13__core__oe connect \B \io_bd [20] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127896$5568_Y + connect \Y $ternary$libresoc.v:137615$5885_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127897$5569 + cell $mux $ternary$libresoc.v:137616$5886 parameter \WIDTH 1 connect \A \gpio_e14__pad__i connect \B \io_bd [21] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127897$5569_Y + connect \Y $ternary$libresoc.v:137616$5886_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127898$5570 + cell $mux $ternary$libresoc.v:137617$5887 parameter \WIDTH 1 connect \A \gpio_e14__core__o connect \B \io_bd [22] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127898$5570_Y + connect \Y $ternary$libresoc.v:137617$5887_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127899$5571 + cell $mux $ternary$libresoc.v:137618$5888 parameter \WIDTH 1 connect \A \gpio_e14__core__oe connect \B \io_bd [23] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127899$5571_Y + connect \Y $ternary$libresoc.v:137618$5888_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:127972.8-127984.4" + attribute \src "libresoc.v:137693.8-137705.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -203893,7 +219675,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:127985.12-127995.4" + attribute \src "libresoc.v:137706.12-137716.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo @@ -203906,7 +219688,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:127996.12-128006.4" + attribute \src "libresoc.v:137717.12-137727.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -203918,562 +219700,577 @@ module \jtag connect \tdo \_irblock_tdo connect \update \_fsm_update end - attribute \src "libresoc.v:126214.7-126214.20" - process $proc$libresoc.v:126214$5763 + attribute \src "libresoc.v:135928.7-135928.20" + process $proc$libresoc.v:135928$6084 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126772.13-126772.32" - process $proc$libresoc.v:126772$5764 + attribute \src "libresoc.v:136486.13-136486.32" + process $proc$libresoc.v:136486$6085 assign { } { } assign $1\dmi0__addr_i[3:0] 4'0000 sync always sync init update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:126777.14-126777.46" - process $proc$libresoc.v:126777$5765 + attribute \src "libresoc.v:136491.14-136491.46" + process $proc$libresoc.v:136491$6086 assign { } { } assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:126791.7-126791.29" - process $proc$libresoc.v:126791$5766 + attribute \src "libresoc.v:136505.7-136505.29" + process $proc$libresoc.v:136505$6087 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:126799.13-126799.36" - process $proc$libresoc.v:126799$5767 + attribute \src "libresoc.v:136513.13-136513.36" + process $proc$libresoc.v:136513$6088 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:126807.7-126807.37" - process $proc$libresoc.v:126807$5768 + attribute \src "libresoc.v:136521.7-136521.37" + process $proc$libresoc.v:136521$6089 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:126811.7-126811.42" - process $proc$libresoc.v:126811$5769 + attribute \src "libresoc.v:136525.7-136525.42" + process $proc$libresoc.v:136525$6090 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:126815.14-126815.51" - process $proc$libresoc.v:126815$5770 + attribute \src "libresoc.v:136529.14-136529.51" + process $proc$libresoc.v:136529$6091 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:126821.13-126821.35" - process $proc$libresoc.v:126821$5771 + attribute \src "libresoc.v:136535.13-136535.35" + process $proc$libresoc.v:136535$6092 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:126829.14-126829.52" - process $proc$libresoc.v:126829$5772 + attribute \src "libresoc.v:136543.14-136543.52" + process $proc$libresoc.v:136543$6093 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:126837.7-126837.37" - process $proc$libresoc.v:126837$5773 + attribute \src "libresoc.v:136551.7-136551.37" + process $proc$libresoc.v:136551$6094 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:126841.7-126841.42" - process $proc$libresoc.v:126841$5774 + attribute \src "libresoc.v:136555.7-136555.42" + process $proc$libresoc.v:136555$6095 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:126857.13-126857.29" - process $proc$libresoc.v:126857$5775 + attribute \src "libresoc.v:136571.13-136571.29" + process $proc$libresoc.v:136571$6096 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:126859.13-126859.35" - process $proc$libresoc.v:126859$5776 + attribute \src "libresoc.v:136573.13-136573.35" + process $proc$libresoc.v:136573$6097 assign { } { } - assign $0\fsm_state$503[2:0]$5777 3'000 + assign $0\fsm_state$503[2:0]$6098 3'000 sync always sync init - update \fsm_state$503 $0\fsm_state$503[2:0]$5777 + update \fsm_state$503 $0\fsm_state$503[2:0]$6098 end - attribute \src "libresoc.v:127057.15-127057.67" - process $proc$libresoc.v:127057$5778 + attribute \src "libresoc.v:136771.15-136771.67" + process $proc$libresoc.v:136771$6099 assign { } { } assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \io_bd $1\io_bd[153:0] end - attribute \src "libresoc.v:127069.15-127069.67" - process $proc$libresoc.v:127069$5779 + attribute \src "libresoc.v:136783.15-136783.67" + process $proc$libresoc.v:136783$6100 assign { } { } assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \io_sr $1\io_sr[153:0] end - attribute \src "libresoc.v:127078.14-127078.41" - process $proc$libresoc.v:127078$5780 + attribute \src "libresoc.v:136792.14-136792.41" + process $proc$libresoc.v:136792$6101 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:127087.14-127087.51" - process $proc$libresoc.v:127087$5781 + attribute \src "libresoc.v:136801.14-136801.51" + process $proc$libresoc.v:136801$6102 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:127101.7-127101.32" - process $proc$libresoc.v:127101$5782 + attribute \src "libresoc.v:136815.7-136815.32" + process $proc$libresoc.v:136815$6103 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:127109.14-127109.47" - process $proc$libresoc.v:127109$5783 + attribute \src "libresoc.v:136823.14-136823.47" + process $proc$libresoc.v:136823$6104 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:127117.7-127117.40" - process $proc$libresoc.v:127117$5784 + attribute \src "libresoc.v:136831.7-136831.40" + process $proc$libresoc.v:136831$6105 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:127121.7-127121.45" - process $proc$libresoc.v:127121$5785 + attribute \src "libresoc.v:136835.7-136835.45" + process $proc$libresoc.v:136835$6106 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:127125.14-127125.54" - process $proc$libresoc.v:127125$5786 + attribute \src "libresoc.v:136839.14-136839.54" + process $proc$libresoc.v:136839$6107 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:127131.13-127131.38" - process $proc$libresoc.v:127131$5787 + attribute \src "libresoc.v:136845.13-136845.38" + process $proc$libresoc.v:136845$6108 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:127139.14-127139.55" - process $proc$libresoc.v:127139$5788 + attribute \src "libresoc.v:136853.14-136853.55" + process $proc$libresoc.v:136853$6109 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:127147.7-127147.40" - process $proc$libresoc.v:127147$5789 + attribute \src "libresoc.v:136861.7-136861.40" + process $proc$libresoc.v:136861$6110 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:127151.7-127151.45" - process $proc$libresoc.v:127151$5790 + attribute \src "libresoc.v:136865.7-136865.45" + process $proc$libresoc.v:136865$6111 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:127581.7-127581.21" - process $proc$libresoc.v:127581$5791 + attribute \src "libresoc.v:137295.7-137295.21" + process $proc$libresoc.v:137295$6112 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "libresoc.v:127589.13-127589.27" - process $proc$libresoc.v:127589$5792 + attribute \src "libresoc.v:137303.13-137303.27" + process $proc$libresoc.v:137303$6113 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:127597.7-127597.29" - process $proc$libresoc.v:127597$5793 + attribute \src "libresoc.v:137311.7-137311.29" + process $proc$libresoc.v:137311$6114 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "libresoc.v:127601.7-127601.34" - process $proc$libresoc.v:127601$5794 + attribute \src "libresoc.v:137315.7-137315.34" + process $proc$libresoc.v:137315$6115 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:127611.7-127611.21" - process $proc$libresoc.v:127611$5795 + attribute \src "libresoc.v:137325.7-137325.21" + process $proc$libresoc.v:137325$6116 assign { } { } assign $1\sr5__oe[0:0] 1'0 sync always sync init update \sr5__oe $1\sr5__oe[0:0] end - attribute \src "libresoc.v:127619.13-127619.27" - process $proc$libresoc.v:127619$5796 + attribute \src "libresoc.v:137333.13-137333.27" + process $proc$libresoc.v:137333$6117 assign { } { } - assign $1\sr5_reg[1:0] 2'00 + assign $1\sr5_reg[2:0] 3'000 sync always sync init - update \sr5_reg $1\sr5_reg[1:0] + update \sr5_reg $1\sr5_reg[2:0] end - attribute \src "libresoc.v:127627.7-127627.29" - process $proc$libresoc.v:127627$5797 + attribute \src "libresoc.v:137341.7-137341.29" + process $proc$libresoc.v:137341$6118 assign { } { } assign $1\sr5_update_core[0:0] 1'0 sync always sync init update \sr5_update_core $1\sr5_update_core[0:0] end - attribute \src "libresoc.v:127631.7-127631.34" - process $proc$libresoc.v:127631$5798 + attribute \src "libresoc.v:137345.7-137345.34" + process $proc$libresoc.v:137345$6119 assign { } { } assign $1\sr5_update_core_prev[0:0] 1'0 sync always sync init update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:127636.7-127636.26" - process $proc$libresoc.v:127636$5799 + attribute \src "libresoc.v:137350.7-137350.26" + process $proc$libresoc.v:137350$6120 assign { } { } assign $1\wb_dcache_en[0:0] 1'1 sync always sync init update \wb_dcache_en $1\wb_dcache_en[0:0] end - attribute \src "libresoc.v:127641.7-127641.26" - process $proc$libresoc.v:127641$5800 + attribute \src "libresoc.v:137355.7-137355.26" + process $proc$libresoc.v:137355$6121 assign { } { } assign $1\wb_icache_en[0:0] 1'1 sync always sync init update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:127900.3-127901.41" - process $proc$libresoc.v:127900$5572 + attribute \src "libresoc.v:137360.7-137360.24" + process $proc$libresoc.v:137360$6122 + assign { } { } + assign $1\wb_sram_en[0:0] 1'1 + sync always + sync init + update \wb_sram_en $1\wb_sram_en[0:0] + end + attribute \src "libresoc.v:137619.3-137620.41" + process $proc$libresoc.v:137619$5889 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "libresoc.v:127902.3-127903.41" - process $proc$libresoc.v:127902$5573 + attribute \src "libresoc.v:137621.3-137622.41" + process $proc$libresoc.v:137621$5890 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:127904.3-127905.45" - process $proc$libresoc.v:127904$5574 + attribute \src "libresoc.v:137623.3-137624.37" + process $proc$libresoc.v:137623$5891 + assign { } { } + assign $0\wb_sram_en[0:0] \wb_sram_en$next + sync posedge \clk + update \wb_sram_en $0\wb_sram_en[0:0] + end + attribute \src "libresoc.v:137625.3-137626.45" + process $proc$libresoc.v:137625$5892 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:127906.3-127907.35" - process $proc$libresoc.v:127906$5575 + attribute \src "libresoc.v:137627.3-137628.35" + process $proc$libresoc.v:137627$5893 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:127908.3-127909.45" - process $proc$libresoc.v:127908$5576 + attribute \src "libresoc.v:137629.3-137630.45" + process $proc$libresoc.v:137629$5894 assign { } { } - assign $0\fsm_state$503[2:0]$5577 \fsm_state$503$next + assign $0\fsm_state$503[2:0]$5895 \fsm_state$503$next sync posedge \clk - update \fsm_state$503 $0\fsm_state$503[2:0]$5577 + update \fsm_state$503 $0\fsm_state$503[2:0]$5895 end - attribute \src "libresoc.v:127910.3-127911.41" - process $proc$libresoc.v:127910$5578 + attribute \src "libresoc.v:137631.3-137632.41" + process $proc$libresoc.v:137631$5896 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:127912.3-127913.51" - process $proc$libresoc.v:127912$5579 + attribute \src "libresoc.v:137633.3-137634.51" + process $proc$libresoc.v:137633$5897 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:127914.3-127915.45" - process $proc$libresoc.v:127914$5580 + attribute \src "libresoc.v:137635.3-137636.45" + process $proc$libresoc.v:137635$5898 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:127916.3-127917.35" - process $proc$libresoc.v:127916$5581 + attribute \src "libresoc.v:137637.3-137638.35" + process $proc$libresoc.v:137637$5899 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:127918.3-127919.41" - process $proc$libresoc.v:127918$5582 + attribute \src "libresoc.v:137639.3-137640.41" + process $proc$libresoc.v:137639$5900 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:127920.3-127921.31" - process $proc$libresoc.v:127920$5583 + attribute \src "libresoc.v:137641.3-137642.31" + process $proc$libresoc.v:137641$5901 assign { } { } - assign $0\sr5_reg[1:0] \sr5_reg$next + assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk - update \sr5_reg $0\sr5_reg[1:0] + update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "libresoc.v:127922.3-127923.31" - process $proc$libresoc.v:127922$5584 + attribute \src "libresoc.v:137643.3-137644.31" + process $proc$libresoc.v:137643$5902 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:127924.3-127925.57" - process $proc$libresoc.v:127924$5585 + attribute \src "libresoc.v:137645.3-137646.57" + process $proc$libresoc.v:137645$5903 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:127926.3-127927.47" - process $proc$libresoc.v:127926$5586 + attribute \src "libresoc.v:137647.3-137648.47" + process $proc$libresoc.v:137647$5904 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:127928.3-127929.47" - process $proc$libresoc.v:127928$5587 + attribute \src "libresoc.v:137649.3-137650.47" + process $proc$libresoc.v:137649$5905 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:127930.3-127931.47" - process $proc$libresoc.v:127930$5588 + attribute \src "libresoc.v:137651.3-137652.47" + process $proc$libresoc.v:137651$5906 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:127932.3-127933.73" - process $proc$libresoc.v:127932$5589 + attribute \src "libresoc.v:137653.3-137654.73" + process $proc$libresoc.v:137653$5907 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:127934.3-127935.63" - process $proc$libresoc.v:127934$5590 + attribute \src "libresoc.v:137655.3-137656.63" + process $proc$libresoc.v:137655$5908 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:127936.3-127937.47" - process $proc$libresoc.v:127936$5591 + attribute \src "libresoc.v:137657.3-137658.47" + process $proc$libresoc.v:137657$5909 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:127938.3-127939.47" - process $proc$libresoc.v:127938$5592 + attribute \src "libresoc.v:137659.3-137660.47" + process $proc$libresoc.v:137659$5910 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:127940.3-127941.73" - process $proc$libresoc.v:127940$5593 + attribute \src "libresoc.v:137661.3-137662.73" + process $proc$libresoc.v:137661$5911 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:127942.3-127943.63" - process $proc$libresoc.v:127942$5594 + attribute \src "libresoc.v:137663.3-137664.63" + process $proc$libresoc.v:137663$5912 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:127944.3-127945.53" - process $proc$libresoc.v:127944$5595 + attribute \src "libresoc.v:137665.3-137666.53" + process $proc$libresoc.v:137665$5913 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:127946.3-127947.53" - process $proc$libresoc.v:127946$5596 + attribute \src "libresoc.v:137667.3-137668.53" + process $proc$libresoc.v:137667$5914 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:127948.3-127949.79" - process $proc$libresoc.v:127948$5597 + attribute \src "libresoc.v:137669.3-137670.79" + process $proc$libresoc.v:137669$5915 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:127950.3-127951.69" - process $proc$libresoc.v:127950$5598 + attribute \src "libresoc.v:137671.3-137672.69" + process $proc$libresoc.v:137671$5916 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:127952.3-127953.53" - process $proc$libresoc.v:127952$5599 + attribute \src "libresoc.v:137673.3-137674.53" + process $proc$libresoc.v:137673$5917 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:127954.3-127955.53" - process $proc$libresoc.v:127954$5600 + attribute \src "libresoc.v:137675.3-137676.53" + process $proc$libresoc.v:137675$5918 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:127956.3-127957.79" - process $proc$libresoc.v:127956$5601 + attribute \src "libresoc.v:137677.3-137678.79" + process $proc$libresoc.v:137677$5919 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:127958.3-127959.69" - process $proc$libresoc.v:127958$5602 + attribute \src "libresoc.v:137679.3-137680.69" + process $proc$libresoc.v:137679$5920 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:127960.3-127961.31" - process $proc$libresoc.v:127960$5603 + attribute \src "libresoc.v:137681.3-137682.31" + process $proc$libresoc.v:137681$5921 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:127962.3-127963.31" - process $proc$libresoc.v:127962$5604 + attribute \src "libresoc.v:137683.3-137684.31" + process $proc$libresoc.v:137683$5922 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:127964.3-127965.57" - process $proc$libresoc.v:127964$5605 + attribute \src "libresoc.v:137685.3-137686.57" + process $proc$libresoc.v:137685$5923 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:127966.3-127967.47" - process $proc$libresoc.v:127966$5606 + attribute \src "libresoc.v:137687.3-137688.47" + process $proc$libresoc.v:137687$5924 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:127968.3-127969.27" - process $proc$libresoc.v:127968$5607 + attribute \src "libresoc.v:137689.3-137690.27" + process $proc$libresoc.v:137689$5925 assign { } { } assign $0\io_bd[153:0] \io_bd$next sync negedge \negjtag_clk update \io_bd $0\io_bd[153:0] end - attribute \src "libresoc.v:127970.3-127971.27" - process $proc$libresoc.v:127970$5608 + attribute \src "libresoc.v:137691.3-137692.27" + process $proc$libresoc.v:137691$5926 assign { } { } assign $0\io_sr[153:0] \io_sr$next sync posedge \posjtag_clk update \io_sr $0\io_sr[153:0] end - attribute \src "libresoc.v:128007.3-128022.6" - process $proc$libresoc.v:128007$5609 + attribute \src "libresoc.v:137728.3-137743.6" + process $proc$libresoc.v:137728$5927 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:128008.5-128008.29" + attribute \src "libresoc.v:137729.5-137729.29" switch \initial - attribute \src "libresoc.v:128008.9-128008.17" + attribute \src "libresoc.v:137729.9-137729.17" case 1'1 case end @@ -204497,14 +220294,14 @@ module \jtag sync always update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:128023.3-128031.6" - process $proc$libresoc.v:128023$5610 + attribute \src "libresoc.v:137744.3-137752.6" + process $proc$libresoc.v:137744$5928 assign { } { } assign { } { } - assign $0\sr0_update_core$next[0:0]$5611 $1\sr0_update_core$next[0:0]$5612 - attribute \src "libresoc.v:128024.5-128024.29" + assign $0\sr0_update_core$next[0:0]$5929 $1\sr0_update_core$next[0:0]$5930 + attribute \src "libresoc.v:137745.5-137745.29" switch \initial - attribute \src "libresoc.v:128024.9-128024.17" + attribute \src "libresoc.v:137745.9-137745.17" case 1'1 case end @@ -204513,21 +220310,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$5612 1'0 + assign $1\sr0_update_core$next[0:0]$5930 1'0 case - assign $1\sr0_update_core$next[0:0]$5612 \sr0_update + assign $1\sr0_update_core$next[0:0]$5930 \sr0_update end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5611 + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5929 end - attribute \src "libresoc.v:128032.3-128040.6" - process $proc$libresoc.v:128032$5613 + attribute \src "libresoc.v:137753.3-137761.6" + process $proc$libresoc.v:137753$5931 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5614 $1\sr0_update_core_prev$next[0:0]$5615 - attribute \src "libresoc.v:128033.5-128033.29" + assign $0\sr0_update_core_prev$next[0:0]$5932 $1\sr0_update_core_prev$next[0:0]$5933 + attribute \src "libresoc.v:137754.5-137754.29" switch \initial - attribute \src "libresoc.v:128033.9-128033.17" + attribute \src "libresoc.v:137754.9-137754.17" case 1'1 case end @@ -204536,21 +220333,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5615 1'0 + assign $1\sr0_update_core_prev$next[0:0]$5933 1'0 case - assign $1\sr0_update_core_prev$next[0:0]$5615 \sr0_update_core + assign $1\sr0_update_core_prev$next[0:0]$5933 \sr0_update_core end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5614 + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5932 end - attribute \src "libresoc.v:128041.3-128057.6" - process $proc$libresoc.v:128041$5616 + attribute \src "libresoc.v:137762.3-137778.6" + process $proc$libresoc.v:137762$5934 assign { } { } assign { } { } - assign $0\sr0__oe$next[0:0]$5617 $2\sr0__oe$next[0:0]$5619 - attribute \src "libresoc.v:128042.5-128042.29" + assign $0\sr0__oe$next[0:0]$5935 $2\sr0__oe$next[0:0]$5937 + attribute \src "libresoc.v:137763.5-137763.29" switch \initial - attribute \src "libresoc.v:128042.9-128042.17" + attribute \src "libresoc.v:137763.9-137763.17" case 1'1 case end @@ -204559,34 +220356,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0__oe$next[0:0]$5618 \sr0_isir + assign $1\sr0__oe$next[0:0]$5936 \sr0_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr0__oe$next[0:0]$5618 1'0 + assign $1\sr0__oe$next[0:0]$5936 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$5619 1'0 + assign $2\sr0__oe$next[0:0]$5937 1'0 case - assign $2\sr0__oe$next[0:0]$5619 $1\sr0__oe$next[0:0]$5618 + assign $2\sr0__oe$next[0:0]$5937 $1\sr0__oe$next[0:0]$5936 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5617 + update \sr0__oe$next $0\sr0__oe$next[0:0]$5935 end - attribute \src "libresoc.v:128058.3-128078.6" - process $proc$libresoc.v:128058$5620 + attribute \src "libresoc.v:137779.3-137799.6" + process $proc$libresoc.v:137779$5938 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr0_reg$next[2:0]$5621 $3\sr0_reg$next[2:0]$5624 - attribute \src "libresoc.v:128059.5-128059.29" + assign $0\sr0_reg$next[2:0]$5939 $3\sr0_reg$next[2:0]$5942 + attribute \src "libresoc.v:137780.5-137780.29" switch \initial - attribute \src "libresoc.v:128059.9-128059.17" + attribute \src "libresoc.v:137780.9-137780.17" case 1'1 case end @@ -204595,39 +220392,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_reg$next[2:0]$5622 { \TAP_bus__tdi \sr0_reg [2:1] } + assign $1\sr0_reg$next[2:0]$5940 { \TAP_bus__tdi \sr0_reg [2:1] } case - assign $1\sr0_reg$next[2:0]$5622 \sr0_reg + assign $1\sr0_reg$next[2:0]$5940 \sr0_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr0_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0_reg$next[2:0]$5623 \sr0__i + assign $2\sr0_reg$next[2:0]$5941 \sr0__i case - assign $2\sr0_reg$next[2:0]$5623 $1\sr0_reg$next[2:0]$5622 + assign $2\sr0_reg$next[2:0]$5941 $1\sr0_reg$next[2:0]$5940 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr0_reg$next[2:0]$5624 3'000 + assign $3\sr0_reg$next[2:0]$5942 3'000 case - assign $3\sr0_reg$next[2:0]$5624 $2\sr0_reg$next[2:0]$5623 + assign $3\sr0_reg$next[2:0]$5942 $2\sr0_reg$next[2:0]$5941 end sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5621 + update \sr0_reg$next $0\sr0_reg$next[2:0]$5939 end - attribute \src "libresoc.v:128079.3-128087.6" - process $proc$libresoc.v:128079$5625 + attribute \src "libresoc.v:137800.3-137808.6" + process $proc$libresoc.v:137800$5943 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5626 $1\jtag_wb_addrsr_update_core$next[0:0]$5627 - attribute \src "libresoc.v:128080.5-128080.29" + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5944 $1\jtag_wb_addrsr_update_core$next[0:0]$5945 + attribute \src "libresoc.v:137801.5-137801.29" switch \initial - attribute \src "libresoc.v:128080.9-128080.17" + attribute \src "libresoc.v:137801.9-137801.17" case 1'1 case end @@ -204636,21 +220433,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5627 1'0 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5945 1'0 case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5627 \jtag_wb_addrsr_update + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5945 \jtag_wb_addrsr_update end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5626 + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5944 end - attribute \src "libresoc.v:128088.3-128096.6" - process $proc$libresoc.v:128088$5628 + attribute \src "libresoc.v:137809.3-137817.6" + process $proc$libresoc.v:137809$5946 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5629 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5630 - attribute \src "libresoc.v:128089.5-128089.29" + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 + attribute \src "libresoc.v:137810.5-137810.29" switch \initial - attribute \src "libresoc.v:128089.9-128089.17" + attribute \src "libresoc.v:137810.9-137810.17" case 1'1 case end @@ -204659,21 +220456,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5630 1'0 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 1'0 case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5630 \jtag_wb_addrsr_update_core + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 \jtag_wb_addrsr_update_core end sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5629 + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 end - attribute \src "libresoc.v:128097.3-128113.6" - process $proc$libresoc.v:128097$5631 + attribute \src "libresoc.v:137818.3-137834.6" + process $proc$libresoc.v:137818$5949 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5632 $2\jtag_wb_addrsr__oe$next[0:0]$5634 - attribute \src "libresoc.v:128098.5-128098.29" + assign $0\jtag_wb_addrsr__oe$next[0:0]$5950 $2\jtag_wb_addrsr__oe$next[0:0]$5952 + attribute \src "libresoc.v:137819.5-137819.29" switch \initial - attribute \src "libresoc.v:128098.9-128098.17" + attribute \src "libresoc.v:137819.9-137819.17" case 1'1 case end @@ -204682,34 +220479,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5633 \jtag_wb_addrsr_isir + assign $1\jtag_wb_addrsr__oe$next[0:0]$5951 \jtag_wb_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5633 1'0 + assign $1\jtag_wb_addrsr__oe$next[0:0]$5951 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$5634 1'0 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5952 1'0 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$5634 $1\jtag_wb_addrsr__oe$next[0:0]$5633 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5952 $1\jtag_wb_addrsr__oe$next[0:0]$5951 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5632 + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5950 end - attribute \src "libresoc.v:128114.3-128134.6" - process $proc$libresoc.v:128114$5635 + attribute \src "libresoc.v:137835.3-137855.6" + process $proc$libresoc.v:137835$5953 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$5636 $3\jtag_wb_addrsr_reg$next[28:0]$5639 - attribute \src "libresoc.v:128115.5-128115.29" + assign $0\jtag_wb_addrsr_reg$next[28:0]$5954 $3\jtag_wb_addrsr_reg$next[28:0]$5957 + attribute \src "libresoc.v:137836.5-137836.29" switch \initial - attribute \src "libresoc.v:128115.9-128115.17" + attribute \src "libresoc.v:137836.9-137836.17" case 1'1 case end @@ -204718,39 +220515,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$5637 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + assign $1\jtag_wb_addrsr_reg$next[28:0]$5955 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } case - assign $1\jtag_wb_addrsr_reg$next[28:0]$5637 \jtag_wb_addrsr_reg + assign $1\jtag_wb_addrsr_reg$next[28:0]$5955 \jtag_wb_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$5638 \jtag_wb_addrsr__i + assign $2\jtag_wb_addrsr_reg$next[28:0]$5956 \jtag_wb_addrsr__i case - assign $2\jtag_wb_addrsr_reg$next[28:0]$5638 $1\jtag_wb_addrsr_reg$next[28:0]$5637 + assign $2\jtag_wb_addrsr_reg$next[28:0]$5956 $1\jtag_wb_addrsr_reg$next[28:0]$5955 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$5639 29'00000000000000000000000000000 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5957 29'00000000000000000000000000000 case - assign $3\jtag_wb_addrsr_reg$next[28:0]$5639 $2\jtag_wb_addrsr_reg$next[28:0]$5638 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5957 $2\jtag_wb_addrsr_reg$next[28:0]$5956 end sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5636 + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5954 end - attribute \src "libresoc.v:128135.3-128143.6" - process $proc$libresoc.v:128135$5640 + attribute \src "libresoc.v:137856.3-137864.6" + process $proc$libresoc.v:137856$5958 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$5641 $1\jtag_wb_datasr_update_core$next[0:0]$5642 - attribute \src "libresoc.v:128136.5-128136.29" + assign $0\jtag_wb_datasr_update_core$next[0:0]$5959 $1\jtag_wb_datasr_update_core$next[0:0]$5960 + attribute \src "libresoc.v:137857.5-137857.29" switch \initial - attribute \src "libresoc.v:128136.9-128136.17" + attribute \src "libresoc.v:137857.9-137857.17" case 1'1 case end @@ -204759,21 +220556,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$5642 1'0 + assign $1\jtag_wb_datasr_update_core$next[0:0]$5960 1'0 case - assign $1\jtag_wb_datasr_update_core$next[0:0]$5642 \jtag_wb_datasr_update + assign $1\jtag_wb_datasr_update_core$next[0:0]$5960 \jtag_wb_datasr_update end sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5641 + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5959 end - attribute \src "libresoc.v:128144.3-128152.6" - process $proc$libresoc.v:128144$5643 + attribute \src "libresoc.v:137865.3-137873.6" + process $proc$libresoc.v:137865$5961 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5644 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5645 - attribute \src "libresoc.v:128145.5-128145.29" + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 + attribute \src "libresoc.v:137866.5-137866.29" switch \initial - attribute \src "libresoc.v:128145.9-128145.17" + attribute \src "libresoc.v:137866.9-137866.17" case 1'1 case end @@ -204782,21 +220579,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5645 1'0 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 1'0 case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5645 \jtag_wb_datasr_update_core + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 \jtag_wb_datasr_update_core end sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5644 + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 end - attribute \src "libresoc.v:128153.3-128169.6" - process $proc$libresoc.v:128153$5646 + attribute \src "libresoc.v:137874.3-137890.6" + process $proc$libresoc.v:137874$5964 assign { } { } assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$5647 $2\jtag_wb_datasr__oe$next[1:0]$5649 - attribute \src "libresoc.v:128154.5-128154.29" + assign $0\jtag_wb_datasr__oe$next[1:0]$5965 $2\jtag_wb_datasr__oe$next[1:0]$5967 + attribute \src "libresoc.v:137875.5-137875.29" switch \initial - attribute \src "libresoc.v:128154.9-128154.17" + attribute \src "libresoc.v:137875.9-137875.17" case 1'1 case end @@ -204805,34 +220602,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5648 \jtag_wb_datasr_isir + assign $1\jtag_wb_datasr__oe$next[1:0]$5966 \jtag_wb_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5648 2'00 + assign $1\jtag_wb_datasr__oe$next[1:0]$5966 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$5649 2'00 + assign $2\jtag_wb_datasr__oe$next[1:0]$5967 2'00 case - assign $2\jtag_wb_datasr__oe$next[1:0]$5649 $1\jtag_wb_datasr__oe$next[1:0]$5648 + assign $2\jtag_wb_datasr__oe$next[1:0]$5967 $1\jtag_wb_datasr__oe$next[1:0]$5966 end sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5647 + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5965 end - attribute \src "libresoc.v:128170.3-128190.6" - process $proc$libresoc.v:128170$5650 + attribute \src "libresoc.v:137891.3-137911.6" + process $proc$libresoc.v:137891$5968 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$5651 $3\jtag_wb_datasr_reg$next[63:0]$5654 - attribute \src "libresoc.v:128171.5-128171.29" + assign $0\jtag_wb_datasr_reg$next[63:0]$5969 $3\jtag_wb_datasr_reg$next[63:0]$5972 + attribute \src "libresoc.v:137892.5-137892.29" switch \initial - attribute \src "libresoc.v:128171.9-128171.17" + attribute \src "libresoc.v:137892.9-137892.17" case 1'1 case end @@ -204841,39 +220638,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$5652 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + assign $1\jtag_wb_datasr_reg$next[63:0]$5970 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case - assign $1\jtag_wb_datasr_reg$next[63:0]$5652 \jtag_wb_datasr_reg + assign $1\jtag_wb_datasr_reg$next[63:0]$5970 \jtag_wb_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$5653 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr_reg$next[63:0]$5971 \jtag_wb_datasr__i case - assign $2\jtag_wb_datasr_reg$next[63:0]$5653 $1\jtag_wb_datasr_reg$next[63:0]$5652 + assign $2\jtag_wb_datasr_reg$next[63:0]$5971 $1\jtag_wb_datasr_reg$next[63:0]$5970 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$5654 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr_reg$next[63:0]$5972 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr_reg$next[63:0]$5654 $2\jtag_wb_datasr_reg$next[63:0]$5653 + assign $3\jtag_wb_datasr_reg$next[63:0]$5972 $2\jtag_wb_datasr_reg$next[63:0]$5971 end sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5651 + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5969 end - attribute \src "libresoc.v:128191.3-128199.6" - process $proc$libresoc.v:128191$5655 + attribute \src "libresoc.v:137912.3-137920.6" + process $proc$libresoc.v:137912$5973 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$5656 $1\dmi0_addrsr_update_core$next[0:0]$5657 - attribute \src "libresoc.v:128192.5-128192.29" + assign $0\dmi0_addrsr_update_core$next[0:0]$5974 $1\dmi0_addrsr_update_core$next[0:0]$5975 + attribute \src "libresoc.v:137913.5-137913.29" switch \initial - attribute \src "libresoc.v:128192.9-128192.17" + attribute \src "libresoc.v:137913.9-137913.17" case 1'1 case end @@ -204882,21 +220679,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$5657 1'0 + assign $1\dmi0_addrsr_update_core$next[0:0]$5975 1'0 case - assign $1\dmi0_addrsr_update_core$next[0:0]$5657 \dmi0_addrsr_update + assign $1\dmi0_addrsr_update_core$next[0:0]$5975 \dmi0_addrsr_update end sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5656 + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5974 end - attribute \src "libresoc.v:128200.3-128208.6" - process $proc$libresoc.v:128200$5658 + attribute \src "libresoc.v:137921.3-137929.6" + process $proc$libresoc.v:137921$5976 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5659 $1\dmi0_addrsr_update_core_prev$next[0:0]$5660 - attribute \src "libresoc.v:128201.5-128201.29" + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 + attribute \src "libresoc.v:137922.5-137922.29" switch \initial - attribute \src "libresoc.v:128201.9-128201.17" + attribute \src "libresoc.v:137922.9-137922.17" case 1'1 case end @@ -204905,21 +220702,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5660 1'0 + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 1'0 case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5660 \dmi0_addrsr_update_core + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 \dmi0_addrsr_update_core end sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5659 + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 end - attribute \src "libresoc.v:128209.3-128225.6" - process $proc$libresoc.v:128209$5661 + attribute \src "libresoc.v:137930.3-137946.6" + process $proc$libresoc.v:137930$5979 assign { } { } assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$5662 $2\dmi0_addrsr__oe$next[0:0]$5664 - attribute \src "libresoc.v:128210.5-128210.29" + assign $0\dmi0_addrsr__oe$next[0:0]$5980 $2\dmi0_addrsr__oe$next[0:0]$5982 + attribute \src "libresoc.v:137931.5-137931.29" switch \initial - attribute \src "libresoc.v:128210.9-128210.17" + attribute \src "libresoc.v:137931.9-137931.17" case 1'1 case end @@ -204928,34 +220725,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5663 \dmi0_addrsr_isir + assign $1\dmi0_addrsr__oe$next[0:0]$5981 \dmi0_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5663 1'0 + assign $1\dmi0_addrsr__oe$next[0:0]$5981 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$5664 1'0 + assign $2\dmi0_addrsr__oe$next[0:0]$5982 1'0 case - assign $2\dmi0_addrsr__oe$next[0:0]$5664 $1\dmi0_addrsr__oe$next[0:0]$5663 + assign $2\dmi0_addrsr__oe$next[0:0]$5982 $1\dmi0_addrsr__oe$next[0:0]$5981 end sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5662 + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5980 end - attribute \src "libresoc.v:128226.3-128246.6" - process $proc$libresoc.v:128226$5665 + attribute \src "libresoc.v:137947.3-137967.6" + process $proc$libresoc.v:137947$5983 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$5666 $3\dmi0_addrsr_reg$next[7:0]$5669 - attribute \src "libresoc.v:128227.5-128227.29" + assign $0\dmi0_addrsr_reg$next[7:0]$5984 $3\dmi0_addrsr_reg$next[7:0]$5987 + attribute \src "libresoc.v:137948.5-137948.29" switch \initial - attribute \src "libresoc.v:128227.9-128227.17" + attribute \src "libresoc.v:137948.9-137948.17" case 1'1 case end @@ -204964,39 +220761,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$5667 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + assign $1\dmi0_addrsr_reg$next[7:0]$5985 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case - assign $1\dmi0_addrsr_reg$next[7:0]$5667 \dmi0_addrsr_reg + assign $1\dmi0_addrsr_reg$next[7:0]$5985 \dmi0_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$5668 \dmi0_addrsr__i + assign $2\dmi0_addrsr_reg$next[7:0]$5986 \dmi0_addrsr__i case - assign $2\dmi0_addrsr_reg$next[7:0]$5668 $1\dmi0_addrsr_reg$next[7:0]$5667 + assign $2\dmi0_addrsr_reg$next[7:0]$5986 $1\dmi0_addrsr_reg$next[7:0]$5985 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$5669 8'00000000 + assign $3\dmi0_addrsr_reg$next[7:0]$5987 8'00000000 case - assign $3\dmi0_addrsr_reg$next[7:0]$5669 $2\dmi0_addrsr_reg$next[7:0]$5668 + assign $3\dmi0_addrsr_reg$next[7:0]$5987 $2\dmi0_addrsr_reg$next[7:0]$5986 end sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5666 + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5984 end - attribute \src "libresoc.v:128247.3-128255.6" - process $proc$libresoc.v:128247$5670 + attribute \src "libresoc.v:137968.3-137976.6" + process $proc$libresoc.v:137968$5988 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$5671 $1\dmi0_datasr_update_core$next[0:0]$5672 - attribute \src "libresoc.v:128248.5-128248.29" + assign $0\dmi0_datasr_update_core$next[0:0]$5989 $1\dmi0_datasr_update_core$next[0:0]$5990 + attribute \src "libresoc.v:137969.5-137969.29" switch \initial - attribute \src "libresoc.v:128248.9-128248.17" + attribute \src "libresoc.v:137969.9-137969.17" case 1'1 case end @@ -205005,21 +220802,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$5672 1'0 + assign $1\dmi0_datasr_update_core$next[0:0]$5990 1'0 case - assign $1\dmi0_datasr_update_core$next[0:0]$5672 \dmi0_datasr_update + assign $1\dmi0_datasr_update_core$next[0:0]$5990 \dmi0_datasr_update end sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5671 + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5989 end - attribute \src "libresoc.v:128256.3-128264.6" - process $proc$libresoc.v:128256$5673 + attribute \src "libresoc.v:137977.3-137985.6" + process $proc$libresoc.v:137977$5991 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$5674 $1\dmi0_datasr_update_core_prev$next[0:0]$5675 - attribute \src "libresoc.v:128257.5-128257.29" + assign $0\dmi0_datasr_update_core_prev$next[0:0]$5992 $1\dmi0_datasr_update_core_prev$next[0:0]$5993 + attribute \src "libresoc.v:137978.5-137978.29" switch \initial - attribute \src "libresoc.v:128257.9-128257.17" + attribute \src "libresoc.v:137978.9-137978.17" case 1'1 case end @@ -205028,21 +220825,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5675 1'0 + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5993 1'0 case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5675 \dmi0_datasr_update_core + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5993 \dmi0_datasr_update_core end sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5674 + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5992 end - attribute \src "libresoc.v:128265.3-128281.6" - process $proc$libresoc.v:128265$5676 + attribute \src "libresoc.v:137986.3-138002.6" + process $proc$libresoc.v:137986$5994 assign { } { } assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$5677 $2\dmi0_datasr__oe$next[1:0]$5679 - attribute \src "libresoc.v:128266.5-128266.29" + assign $0\dmi0_datasr__oe$next[1:0]$5995 $2\dmi0_datasr__oe$next[1:0]$5997 + attribute \src "libresoc.v:137987.5-137987.29" switch \initial - attribute \src "libresoc.v:128266.9-128266.17" + attribute \src "libresoc.v:137987.9-137987.17" case 1'1 case end @@ -205051,34 +220848,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5678 \dmi0_datasr_isir + assign $1\dmi0_datasr__oe$next[1:0]$5996 \dmi0_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5678 2'00 + assign $1\dmi0_datasr__oe$next[1:0]$5996 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$5679 2'00 + assign $2\dmi0_datasr__oe$next[1:0]$5997 2'00 case - assign $2\dmi0_datasr__oe$next[1:0]$5679 $1\dmi0_datasr__oe$next[1:0]$5678 + assign $2\dmi0_datasr__oe$next[1:0]$5997 $1\dmi0_datasr__oe$next[1:0]$5996 end sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5677 + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5995 end - attribute \src "libresoc.v:128282.3-128302.6" - process $proc$libresoc.v:128282$5680 + attribute \src "libresoc.v:138003.3-138023.6" + process $proc$libresoc.v:138003$5998 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$5681 $3\dmi0_datasr_reg$next[63:0]$5684 - attribute \src "libresoc.v:128283.5-128283.29" + assign $0\dmi0_datasr_reg$next[63:0]$5999 $3\dmi0_datasr_reg$next[63:0]$6002 + attribute \src "libresoc.v:138004.5-138004.29" switch \initial - attribute \src "libresoc.v:128283.9-128283.17" + attribute \src "libresoc.v:138004.9-138004.17" case 1'1 case end @@ -205087,39 +220884,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$5682 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + assign $1\dmi0_datasr_reg$next[63:0]$6000 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\dmi0_datasr_reg$next[63:0]$5682 \dmi0_datasr_reg + assign $1\dmi0_datasr_reg$next[63:0]$6000 \dmi0_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$5683 \dmi0_datasr__i + assign $2\dmi0_datasr_reg$next[63:0]$6001 \dmi0_datasr__i case - assign $2\dmi0_datasr_reg$next[63:0]$5683 $1\dmi0_datasr_reg$next[63:0]$5682 + assign $2\dmi0_datasr_reg$next[63:0]$6001 $1\dmi0_datasr_reg$next[63:0]$6000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$5684 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr_reg$next[63:0]$6002 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr_reg$next[63:0]$5684 $2\dmi0_datasr_reg$next[63:0]$5683 + assign $3\dmi0_datasr_reg$next[63:0]$6002 $2\dmi0_datasr_reg$next[63:0]$6001 end sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5681 + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5999 end - attribute \src "libresoc.v:128303.3-128311.6" - process $proc$libresoc.v:128303$5685 + attribute \src "libresoc.v:138024.3-138032.6" + process $proc$libresoc.v:138024$6003 assign { } { } assign { } { } - assign $0\sr5_update_core$next[0:0]$5686 $1\sr5_update_core$next[0:0]$5687 - attribute \src "libresoc.v:128304.5-128304.29" + assign $0\sr5_update_core$next[0:0]$6004 $1\sr5_update_core$next[0:0]$6005 + attribute \src "libresoc.v:138025.5-138025.29" switch \initial - attribute \src "libresoc.v:128304.9-128304.17" + attribute \src "libresoc.v:138025.9-138025.17" case 1'1 case end @@ -205128,21 +220925,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core$next[0:0]$5687 1'0 + assign $1\sr5_update_core$next[0:0]$6005 1'0 case - assign $1\sr5_update_core$next[0:0]$5687 \sr5_update + assign $1\sr5_update_core$next[0:0]$6005 \sr5_update end sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5686 + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6004 end - attribute \src "libresoc.v:128312.3-128320.6" - process $proc$libresoc.v:128312$5688 + attribute \src "libresoc.v:138033.3-138041.6" + process $proc$libresoc.v:138033$6006 assign { } { } assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$5689 $1\sr5_update_core_prev$next[0:0]$5690 - attribute \src "libresoc.v:128313.5-128313.29" + assign $0\sr5_update_core_prev$next[0:0]$6007 $1\sr5_update_core_prev$next[0:0]$6008 + attribute \src "libresoc.v:138034.5-138034.29" switch \initial - attribute \src "libresoc.v:128313.9-128313.17" + attribute \src "libresoc.v:138034.9-138034.17" case 1'1 case end @@ -205151,21 +220948,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$5690 1'0 + assign $1\sr5_update_core_prev$next[0:0]$6008 1'0 case - assign $1\sr5_update_core_prev$next[0:0]$5690 \sr5_update_core + assign $1\sr5_update_core_prev$next[0:0]$6008 \sr5_update_core end sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5689 + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6007 end - attribute \src "libresoc.v:128321.3-128337.6" - process $proc$libresoc.v:128321$5691 + attribute \src "libresoc.v:138042.3-138058.6" + process $proc$libresoc.v:138042$6009 assign { } { } assign { } { } - assign $0\sr5__oe$next[0:0]$5692 $2\sr5__oe$next[0:0]$5694 - attribute \src "libresoc.v:128322.5-128322.29" + assign $0\sr5__oe$next[0:0]$6010 $2\sr5__oe$next[0:0]$6012 + attribute \src "libresoc.v:138043.5-138043.29" switch \initial - attribute \src "libresoc.v:128322.9-128322.17" + attribute \src "libresoc.v:138043.9-138043.17" case 1'1 case end @@ -205174,34 +220971,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__oe$next[0:0]$5693 \sr5_isir + assign $1\sr5__oe$next[0:0]$6011 \sr5_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr5__oe$next[0:0]$5693 1'0 + assign $1\sr5__oe$next[0:0]$6011 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5__oe$next[0:0]$5694 1'0 + assign $2\sr5__oe$next[0:0]$6012 1'0 case - assign $2\sr5__oe$next[0:0]$5694 $1\sr5__oe$next[0:0]$5693 + assign $2\sr5__oe$next[0:0]$6012 $1\sr5__oe$next[0:0]$6011 end sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$5692 + update \sr5__oe$next $0\sr5__oe$next[0:0]$6010 end - attribute \src "libresoc.v:128338.3-128358.6" - process $proc$libresoc.v:128338$5695 + attribute \src "libresoc.v:138059.3-138079.6" + process $proc$libresoc.v:138059$6013 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr5_reg$next[1:0]$5696 $3\sr5_reg$next[1:0]$5699 - attribute \src "libresoc.v:128339.5-128339.29" + assign $0\sr5_reg$next[2:0]$6014 $3\sr5_reg$next[2:0]$6017 + attribute \src "libresoc.v:138060.5-138060.29" switch \initial - attribute \src "libresoc.v:128339.9-128339.17" + attribute \src "libresoc.v:138060.9-138060.17" case 1'1 case end @@ -205210,38 +221007,38 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_reg$next[1:0]$5697 { \TAP_bus__tdi \sr5_reg [1] } + assign $1\sr5_reg$next[2:0]$6015 { \TAP_bus__tdi \sr5_reg [2:1] } case - assign $1\sr5_reg$next[1:0]$5697 \sr5_reg + assign $1\sr5_reg$next[2:0]$6015 \sr5_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr5_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5_reg$next[1:0]$5698 \sr5__i + assign $2\sr5_reg$next[2:0]$6016 \sr5__i case - assign $2\sr5_reg$next[1:0]$5698 $1\sr5_reg$next[1:0]$5697 + assign $2\sr5_reg$next[2:0]$6016 $1\sr5_reg$next[2:0]$6015 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr5_reg$next[1:0]$5699 2'00 + assign $3\sr5_reg$next[2:0]$6017 3'000 case - assign $3\sr5_reg$next[1:0]$5699 $2\sr5_reg$next[1:0]$5698 + assign $3\sr5_reg$next[2:0]$6017 $2\sr5_reg$next[2:0]$6016 end sync always - update \sr5_reg$next $0\sr5_reg$next[1:0]$5696 + update \sr5_reg$next $0\sr5_reg$next[2:0]$6014 end - attribute \src "libresoc.v:128359.3-128385.6" - process $proc$libresoc.v:128359$5700 + attribute \src "libresoc.v:138080.3-138106.6" + process $proc$libresoc.v:138080$6018 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:128360.5-128360.29" + attribute \src "libresoc.v:138081.5-138081.29" switch \initial - attribute \src "libresoc.v:128360.9-128360.17" + attribute \src "libresoc.v:138081.9-138081.17" case 1'1 case end @@ -205279,15 +221076,15 @@ module \jtag sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "libresoc.v:128386.3-128418.6" - process $proc$libresoc.v:128386$5701 + attribute \src "libresoc.v:138107.3-138139.6" + process $proc$libresoc.v:138107$6019 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__adr$next[28:0]$5702 $4\jtag_wb__adr$next[28:0]$5706 - attribute \src "libresoc.v:128387.5-128387.29" + assign $0\jtag_wb__adr$next[28:0]$6020 $4\jtag_wb__adr$next[28:0]$6024 + attribute \src "libresoc.v:138108.5-138108.29" switch \initial - attribute \src "libresoc.v:128387.9-128387.17" + attribute \src "libresoc.v:138108.9-138108.17" case 1'1 case end @@ -205296,57 +221093,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$5703 $2\jtag_wb__adr$next[28:0]$5704 + assign $1\jtag_wb__adr$next[28:0]$6021 $2\jtag_wb__adr$next[28:0]$6022 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\jtag_wb__adr$next[28:0]$5704 \jtag_wb_addrsr__o + assign $2\jtag_wb__adr$next[28:0]$6022 \jtag_wb_addrsr__o attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\jtag_wb__adr$next[28:0]$5704 \$495 [28:0] + assign $2\jtag_wb__adr$next[28:0]$6022 \$495 [28:0] case - assign $2\jtag_wb__adr$next[28:0]$5704 \jtag_wb__adr + assign $2\jtag_wb__adr$next[28:0]$6022 \jtag_wb__adr end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$5703 $3\jtag_wb__adr$next[28:0]$5705 + assign $1\jtag_wb__adr$next[28:0]$6021 $3\jtag_wb__adr$next[28:0]$6023 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__adr$next[28:0]$5705 \$498 [28:0] + assign $3\jtag_wb__adr$next[28:0]$6023 \$498 [28:0] case - assign $3\jtag_wb__adr$next[28:0]$5705 \jtag_wb__adr + assign $3\jtag_wb__adr$next[28:0]$6023 \jtag_wb__adr end case - assign $1\jtag_wb__adr$next[28:0]$5703 \jtag_wb__adr + assign $1\jtag_wb__adr$next[28:0]$6021 \jtag_wb__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\jtag_wb__adr$next[28:0]$5706 29'00000000000000000000000000000 + assign $4\jtag_wb__adr$next[28:0]$6024 29'00000000000000000000000000000 case - assign $4\jtag_wb__adr$next[28:0]$5706 $1\jtag_wb__adr$next[28:0]$5703 + assign $4\jtag_wb__adr$next[28:0]$6024 $1\jtag_wb__adr$next[28:0]$6021 end sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$5702 + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6020 end - attribute \src "libresoc.v:128419.3-128471.6" - process $proc$libresoc.v:128419$5707 + attribute \src "libresoc.v:138140.3-138192.6" + process $proc$libresoc.v:138140$6025 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[2:0]$5708 $5\fsm_state$next[2:0]$5713 - attribute \src "libresoc.v:128420.5-128420.29" + assign $0\fsm_state$next[2:0]$6026 $5\fsm_state$next[2:0]$6031 + attribute \src "libresoc.v:138141.5-138141.29" switch \initial - attribute \src "libresoc.v:128420.9-128420.17" + attribute \src "libresoc.v:138141.9-138141.17" case 1'1 case end @@ -205355,82 +221152,82 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$next[2:0]$5709 $2\fsm_state$next[2:0]$5710 + assign $1\fsm_state$next[2:0]$6027 $2\fsm_state$next[2:0]$6028 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$next[2:0]$5710 3'001 + assign $2\fsm_state$next[2:0]$6028 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$next[2:0]$5710 3'001 + assign $2\fsm_state$next[2:0]$6028 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$next[2:0]$5710 3'010 + assign $2\fsm_state$next[2:0]$6028 3'010 case - assign $2\fsm_state$next[2:0]$5710 \fsm_state + assign $2\fsm_state$next[2:0]$6028 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$next[2:0]$5709 3'011 + assign $1\fsm_state$next[2:0]$6027 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$next[2:0]$5709 $3\fsm_state$next[2:0]$5711 + assign $1\fsm_state$next[2:0]$6027 $3\fsm_state$next[2:0]$6029 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[2:0]$5711 3'000 + assign $3\fsm_state$next[2:0]$6029 3'000 case - assign $3\fsm_state$next[2:0]$5711 \fsm_state + assign $3\fsm_state$next[2:0]$6029 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$next[2:0]$5709 3'100 + assign $1\fsm_state$next[2:0]$6027 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$next[2:0]$5709 $4\fsm_state$next[2:0]$5712 + assign $1\fsm_state$next[2:0]$6027 $4\fsm_state$next[2:0]$6030 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[2:0]$5712 3'001 + assign $4\fsm_state$next[2:0]$6030 3'001 case - assign $4\fsm_state$next[2:0]$5712 \fsm_state + assign $4\fsm_state$next[2:0]$6030 \fsm_state end case - assign $1\fsm_state$next[2:0]$5709 \fsm_state + assign $1\fsm_state$next[2:0]$6027 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$5713 3'000 + assign $5\fsm_state$next[2:0]$6031 3'000 case - assign $5\fsm_state$next[2:0]$5713 $1\fsm_state$next[2:0]$5709 + assign $5\fsm_state$next[2:0]$6031 $1\fsm_state$next[2:0]$6027 end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$5708 + update \fsm_state$next $0\fsm_state$next[2:0]$6026 end - attribute \src "libresoc.v:128472.3-128498.6" - process $proc$libresoc.v:128472$5714 + attribute \src "libresoc.v:138193.3-138219.6" + process $proc$libresoc.v:138193$6032 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$5715 $3\jtag_wb__dat_w$next[63:0]$5718 - attribute \src "libresoc.v:128473.5-128473.29" + assign $0\jtag_wb__dat_w$next[63:0]$6033 $3\jtag_wb__dat_w$next[63:0]$6036 + attribute \src "libresoc.v:138194.5-138194.29" switch \initial - attribute \src "libresoc.v:128473.9-128473.17" + attribute \src "libresoc.v:138194.9-138194.17" case 1'1 case end @@ -205439,46 +221236,46 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$5716 $2\jtag_wb__dat_w$next[63:0]$5717 + assign $1\jtag_wb__dat_w$next[63:0]$6034 $2\jtag_wb__dat_w$next[63:0]$6035 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$5717 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$5717 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$5717 \jtag_wb_datasr__o + assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb_datasr__o case - assign $2\jtag_wb__dat_w$next[63:0]$5717 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w end case - assign $1\jtag_wb__dat_w$next[63:0]$5716 \jtag_wb__dat_w + assign $1\jtag_wb__dat_w$next[63:0]$6034 \jtag_wb__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$5718 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb__dat_w$next[63:0]$6036 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb__dat_w$next[63:0]$5718 $1\jtag_wb__dat_w$next[63:0]$5716 + assign $3\jtag_wb__dat_w$next[63:0]$6036 $1\jtag_wb__dat_w$next[63:0]$6034 end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$5715 + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6033 end - attribute \src "libresoc.v:128499.3-128519.6" - process $proc$libresoc.v:128499$5719 + attribute \src "libresoc.v:138220.3-138240.6" + process $proc$libresoc.v:138220$6037 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$5720 $3\jtag_wb_datasr__i$next[63:0]$5723 - attribute \src "libresoc.v:128500.5-128500.29" + assign $0\jtag_wb_datasr__i$next[63:0]$6038 $3\jtag_wb_datasr__i$next[63:0]$6041 + attribute \src "libresoc.v:138221.5-138221.29" switch \initial - attribute \src "libresoc.v:128500.9-128500.17" + attribute \src "libresoc.v:138221.9-138221.17" case 1'1 case end @@ -205487,40 +221284,40 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$5721 $2\jtag_wb_datasr__i$next[63:0]$5722 + assign $1\jtag_wb_datasr__i$next[63:0]$6039 $2\jtag_wb_datasr__i$next[63:0]$6040 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$5722 \jtag_wb__dat_r + assign $2\jtag_wb_datasr__i$next[63:0]$6040 \jtag_wb__dat_r case - assign $2\jtag_wb_datasr__i$next[63:0]$5722 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr__i$next[63:0]$6040 \jtag_wb_datasr__i end case - assign $1\jtag_wb_datasr__i$next[63:0]$5721 \jtag_wb_datasr__i + assign $1\jtag_wb_datasr__i$next[63:0]$6039 \jtag_wb_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$5723 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr__i$next[63:0]$6041 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr__i$next[63:0]$5723 $1\jtag_wb_datasr__i$next[63:0]$5721 + assign $3\jtag_wb_datasr__i$next[63:0]$6041 $1\jtag_wb_datasr__i$next[63:0]$6039 end sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$5720 + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6038 end - attribute \src "libresoc.v:128520.3-128552.6" - process $proc$libresoc.v:128520$5724 + attribute \src "libresoc.v:138241.3-138273.6" + process $proc$libresoc.v:138241$6042 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__addr_i$next[3:0]$5725 $4\dmi0__addr_i$next[3:0]$5729 - attribute \src "libresoc.v:128521.5-128521.29" + assign $0\dmi0__addr_i$next[3:0]$6043 $4\dmi0__addr_i$next[3:0]$6047 + attribute \src "libresoc.v:138242.5-138242.29" switch \initial - attribute \src "libresoc.v:128521.9-128521.17" + attribute \src "libresoc.v:138242.9-138242.17" case 1'1 case end @@ -205529,57 +221326,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$5726 $2\dmi0__addr_i$next[3:0]$5727 + assign $1\dmi0__addr_i$next[3:0]$6044 $2\dmi0__addr_i$next[3:0]$6045 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\dmi0__addr_i$next[3:0]$5727 \dmi0_addrsr__o [3:0] + assign $2\dmi0__addr_i$next[3:0]$6045 \dmi0_addrsr__o [3:0] attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\dmi0__addr_i$next[3:0]$5727 \$512 [3:0] + assign $2\dmi0__addr_i$next[3:0]$6045 \$512 [3:0] case - assign $2\dmi0__addr_i$next[3:0]$5727 \dmi0__addr_i + assign $2\dmi0__addr_i$next[3:0]$6045 \dmi0__addr_i end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$5726 $3\dmi0__addr_i$next[3:0]$5728 + assign $1\dmi0__addr_i$next[3:0]$6044 $3\dmi0__addr_i$next[3:0]$6046 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__addr_i$next[3:0]$5728 \$515 [3:0] + assign $3\dmi0__addr_i$next[3:0]$6046 \$515 [3:0] case - assign $3\dmi0__addr_i$next[3:0]$5728 \dmi0__addr_i + assign $3\dmi0__addr_i$next[3:0]$6046 \dmi0__addr_i end case - assign $1\dmi0__addr_i$next[3:0]$5726 \dmi0__addr_i + assign $1\dmi0__addr_i$next[3:0]$6044 \dmi0__addr_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dmi0__addr_i$next[3:0]$5729 4'0000 + assign $4\dmi0__addr_i$next[3:0]$6047 4'0000 case - assign $4\dmi0__addr_i$next[3:0]$5729 $1\dmi0__addr_i$next[3:0]$5726 + assign $4\dmi0__addr_i$next[3:0]$6047 $1\dmi0__addr_i$next[3:0]$6044 end sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$5725 + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6043 end - attribute \src "libresoc.v:128553.3-128605.6" - process $proc$libresoc.v:128553$5730 + attribute \src "libresoc.v:138274.3-138326.6" + process $proc$libresoc.v:138274$6048 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$503$next[2:0]$5731 $5\fsm_state$503$next[2:0]$5736 - attribute \src "libresoc.v:128554.5-128554.29" + assign $0\fsm_state$503$next[2:0]$6049 $5\fsm_state$503$next[2:0]$6054 + attribute \src "libresoc.v:138275.5-138275.29" switch \initial - attribute \src "libresoc.v:128554.9-128554.17" + attribute \src "libresoc.v:138275.9-138275.17" case 1'1 case end @@ -205588,82 +221385,82 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$503$next[2:0]$5732 $2\fsm_state$503$next[2:0]$5733 + assign $1\fsm_state$503$next[2:0]$6050 $2\fsm_state$503$next[2:0]$6051 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$503$next[2:0]$5733 3'001 + assign $2\fsm_state$503$next[2:0]$6051 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$503$next[2:0]$5733 3'001 + assign $2\fsm_state$503$next[2:0]$6051 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$503$next[2:0]$5733 3'010 + assign $2\fsm_state$503$next[2:0]$6051 3'010 case - assign $2\fsm_state$503$next[2:0]$5733 \fsm_state$503 + assign $2\fsm_state$503$next[2:0]$6051 \fsm_state$503 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$503$next[2:0]$5732 3'011 + assign $1\fsm_state$503$next[2:0]$6050 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$503$next[2:0]$5732 $3\fsm_state$503$next[2:0]$5734 + assign $1\fsm_state$503$next[2:0]$6050 $3\fsm_state$503$next[2:0]$6052 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$503$next[2:0]$5734 3'000 + assign $3\fsm_state$503$next[2:0]$6052 3'000 case - assign $3\fsm_state$503$next[2:0]$5734 \fsm_state$503 + assign $3\fsm_state$503$next[2:0]$6052 \fsm_state$503 end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$503$next[2:0]$5732 3'100 + assign $1\fsm_state$503$next[2:0]$6050 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$503$next[2:0]$5732 $4\fsm_state$503$next[2:0]$5735 + assign $1\fsm_state$503$next[2:0]$6050 $4\fsm_state$503$next[2:0]$6053 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$503$next[2:0]$5735 3'001 + assign $4\fsm_state$503$next[2:0]$6053 3'001 case - assign $4\fsm_state$503$next[2:0]$5735 \fsm_state$503 + assign $4\fsm_state$503$next[2:0]$6053 \fsm_state$503 end case - assign $1\fsm_state$503$next[2:0]$5732 \fsm_state$503 + assign $1\fsm_state$503$next[2:0]$6050 \fsm_state$503 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$503$next[2:0]$5736 3'000 + assign $5\fsm_state$503$next[2:0]$6054 3'000 case - assign $5\fsm_state$503$next[2:0]$5736 $1\fsm_state$503$next[2:0]$5732 + assign $5\fsm_state$503$next[2:0]$6054 $1\fsm_state$503$next[2:0]$6050 end sync always - update \fsm_state$503$next $0\fsm_state$503$next[2:0]$5731 + update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6049 end - attribute \src "libresoc.v:128606.3-128632.6" - process $proc$libresoc.v:128606$5737 + attribute \src "libresoc.v:138327.3-138353.6" + process $proc$libresoc.v:138327$6055 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__din$next[63:0]$5738 $3\dmi0__din$next[63:0]$5741 - attribute \src "libresoc.v:128607.5-128607.29" + assign $0\dmi0__din$next[63:0]$6056 $3\dmi0__din$next[63:0]$6059 + attribute \src "libresoc.v:138328.5-138328.29" switch \initial - attribute \src "libresoc.v:128607.9-128607.17" + attribute \src "libresoc.v:138328.9-138328.17" case 1'1 case end @@ -205672,46 +221469,46 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__din$next[63:0]$5739 $2\dmi0__din$next[63:0]$5740 + assign $1\dmi0__din$next[63:0]$6057 $2\dmi0__din$next[63:0]$6058 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\dmi0__din$next[63:0]$5740 \dmi0__din + assign $2\dmi0__din$next[63:0]$6058 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\dmi0__din$next[63:0]$5740 \dmi0__din + assign $2\dmi0__din$next[63:0]$6058 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\dmi0__din$next[63:0]$5740 \dmi0_datasr__o + assign $2\dmi0__din$next[63:0]$6058 \dmi0_datasr__o case - assign $2\dmi0__din$next[63:0]$5740 \dmi0__din + assign $2\dmi0__din$next[63:0]$6058 \dmi0__din end case - assign $1\dmi0__din$next[63:0]$5739 \dmi0__din + assign $1\dmi0__din$next[63:0]$6057 \dmi0__din end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__din$next[63:0]$5741 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0__din$next[63:0]$6059 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0__din$next[63:0]$5741 $1\dmi0__din$next[63:0]$5739 + assign $3\dmi0__din$next[63:0]$6059 $1\dmi0__din$next[63:0]$6057 end sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$5738 + update \dmi0__din$next $0\dmi0__din$next[63:0]$6056 end - attribute \src "libresoc.v:128633.3-128653.6" - process $proc$libresoc.v:128633$5742 + attribute \src "libresoc.v:138354.3-138374.6" + process $proc$libresoc.v:138354$6060 assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$5743 $3\dmi0_datasr__i$next[63:0]$5746 - attribute \src "libresoc.v:128634.5-128634.29" + assign $0\dmi0_datasr__i$next[63:0]$6061 $3\dmi0_datasr__i$next[63:0]$6064 + attribute \src "libresoc.v:138355.5-138355.29" switch \initial - attribute \src "libresoc.v:128634.9-128634.17" + attribute \src "libresoc.v:138355.9-138355.17" case 1'1 case end @@ -205720,57 +221517,63 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$5744 $2\dmi0_datasr__i$next[63:0]$5745 + assign $1\dmi0_datasr__i$next[63:0]$6062 $2\dmi0_datasr__i$next[63:0]$6063 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$5745 \dmi0__dout + assign $2\dmi0_datasr__i$next[63:0]$6063 \dmi0__dout case - assign $2\dmi0_datasr__i$next[63:0]$5745 \dmi0_datasr__i + assign $2\dmi0_datasr__i$next[63:0]$6063 \dmi0_datasr__i end case - assign $1\dmi0_datasr__i$next[63:0]$5744 \dmi0_datasr__i + assign $1\dmi0_datasr__i$next[63:0]$6062 \dmi0_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$5746 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr__i$next[63:0]$6064 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr__i$next[63:0]$5746 $1\dmi0_datasr__i$next[63:0]$5744 + assign $3\dmi0_datasr__i$next[63:0]$6064 $1\dmi0_datasr__i$next[63:0]$6062 end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$5743 + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6061 end - attribute \src "libresoc.v:128654.3-128672.6" - process $proc$libresoc.v:128654$5747 + attribute \src "libresoc.v:138375.3-138395.6" + process $proc$libresoc.v:138375$6065 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\wb_dcache_en$next[0:0]$5748 $2\wb_dcache_en$next[0:0]$5752 - assign $0\wb_icache_en$next[0:0]$5749 $2\wb_icache_en$next[0:0]$5753 - attribute \src "libresoc.v:128655.5-128655.29" + assign { } { } + assign { } { } + assign { } { } + assign $0\wb_dcache_en$next[0:0]$6066 $2\wb_dcache_en$next[0:0]$6072 + assign $0\wb_icache_en$next[0:0]$6067 $2\wb_icache_en$next[0:0]$6073 + assign $0\wb_sram_en$next[0:0]$6068 $2\wb_sram_en$next[0:0]$6074 + attribute \src "libresoc.v:138376.5-138376.29" switch \initial - attribute \src "libresoc.v:128655.9-128655.17" + attribute \src "libresoc.v:138376.9-138376.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:106" switch \sr5__oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $1\wb_dcache_en$next[0:0]$5750 $1\wb_icache_en$next[0:0]$5751 } \sr5__o + assign { } { } + assign { $1\wb_sram_en$next[0:0]$6071 $1\wb_dcache_en$next[0:0]$6069 $1\wb_icache_en$next[0:0]$6070 } \sr5__o case - assign $1\wb_dcache_en$next[0:0]$5750 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$5751 \wb_icache_en + assign $1\wb_dcache_en$next[0:0]$6069 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6070 \wb_icache_en + assign $1\wb_sram_en$next[0:0]$6071 \wb_sram_en end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -205778,48 +221581,52 @@ module \jtag case 1'1 assign { } { } assign { } { } - assign $2\wb_icache_en$next[0:0]$5753 1'1 - assign $2\wb_dcache_en$next[0:0]$5752 1'1 + assign { } { } + assign $2\wb_icache_en$next[0:0]$6073 1'1 + assign $2\wb_dcache_en$next[0:0]$6072 1'1 + assign $2\wb_sram_en$next[0:0]$6074 1'1 case - assign $2\wb_dcache_en$next[0:0]$5752 $1\wb_dcache_en$next[0:0]$5750 - assign $2\wb_icache_en$next[0:0]$5753 $1\wb_icache_en$next[0:0]$5751 + assign $2\wb_dcache_en$next[0:0]$6072 $1\wb_dcache_en$next[0:0]$6069 + assign $2\wb_icache_en$next[0:0]$6073 $1\wb_icache_en$next[0:0]$6070 + assign $2\wb_sram_en$next[0:0]$6074 $1\wb_sram_en$next[0:0]$6071 end sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$5748 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$5749 + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6066 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6067 + update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6068 end - attribute \src "libresoc.v:128673.3-128682.6" - process $proc$libresoc.v:128673$5754 + attribute \src "libresoc.v:138396.3-138405.6" + process $proc$libresoc.v:138396$6075 assign { } { } assign { } { } - assign $0\sr5__i[1:0] $1\sr5__i[1:0] - attribute \src "libresoc.v:128674.5-128674.29" + assign $0\sr5__i[2:0] $1\sr5__i[2:0] + attribute \src "libresoc.v:138397.5-138397.29" switch \initial - attribute \src "libresoc.v:128674.9-128674.17" + attribute \src "libresoc.v:138397.9-138397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:109" switch \sr5__ie attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } + assign $1\sr5__i[2:0] { \wb_sram_en \wb_dcache_en \wb_icache_en } case - assign $1\sr5__i[1:0] 2'00 + assign $1\sr5__i[2:0] 3'000 end sync always - update \sr5__i $0\sr5__i[1:0] + update \sr5__i $0\sr5__i[2:0] end - attribute \src "libresoc.v:128683.3-128700.6" - process $proc$libresoc.v:128683$5755 + attribute \src "libresoc.v:138406.3-138423.6" + process $proc$libresoc.v:138406$6076 assign { } { } assign { } { } assign { } { } - assign $0\io_sr$next[153:0]$5756 $2\io_sr$next[153:0]$5758 - attribute \src "libresoc.v:128684.5-128684.29" + assign $0\io_sr$next[153:0]$6077 $2\io_sr$next[153:0]$6079 + attribute \src "libresoc.v:138407.5-138407.29" switch \initial - attribute \src "libresoc.v:128684.9-128684.17" + attribute \src "libresoc.v:138407.9-138407.17" case 1'1 case end @@ -205828,35 +221635,35 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $1\io_sr$next[153:0]$5757 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign $1\io_sr$next[153:0]$6078 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $1\io_sr$next[153:0]$5757 { \io_sr [152:0] \TAP_bus__tdi } + assign $1\io_sr$next[153:0]$6078 { \io_sr [152:0] \TAP_bus__tdi } case - assign $1\io_sr$next[153:0]$5757 \io_sr + assign $1\io_sr$next[153:0]$6078 \io_sr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[153:0]$5758 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\io_sr$next[153:0]$6079 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\io_sr$next[153:0]$5758 $1\io_sr$next[153:0]$5757 + assign $2\io_sr$next[153:0]$6079 $1\io_sr$next[153:0]$6078 end sync always - update \io_sr$next $0\io_sr$next[153:0]$5756 + update \io_sr$next $0\io_sr$next[153:0]$6077 end - attribute \src "libresoc.v:128701.3-128721.6" - process $proc$libresoc.v:128701$5759 + attribute \src "libresoc.v:138424.3-138444.6" + process $proc$libresoc.v:138424$6080 assign { } { } assign { } { } assign { } { } - assign $0\io_bd$next[153:0]$5760 $2\io_bd$next[153:0]$5762 - attribute \src "libresoc.v:128702.5-128702.29" + assign $0\io_bd$next[153:0]$6081 $2\io_bd$next[153:0]$6083 + attribute \src "libresoc.v:138425.5-138425.29" switch \initial - attribute \src "libresoc.v:128702.9-128702.17" + attribute \src "libresoc.v:138425.9-138425.17" case 1'1 case end @@ -205864,285 +221671,285 @@ module \jtag switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $1\io_bd$next[153:0]$5761 \io_bd + assign $1\io_bd$next[153:0]$6082 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $1\io_bd$next[153:0]$5761 \io_bd + assign $1\io_bd$next[153:0]$6082 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\io_bd$next[153:0]$5761 \io_sr + assign $1\io_bd$next[153:0]$6082 \io_sr case - assign $1\io_bd$next[153:0]$5761 \io_bd + assign $1\io_bd$next[153:0]$6082 \io_bd end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \negjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_bd$next[153:0]$5762 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[153:0]$5762 $1\io_bd$next[153:0]$5761 - end - sync always - update \io_bd$next $0\io_bd$next[153:0]$5760 - end - connect \$9 $eq$libresoc.v:127644$5315_Y - connect \$99 $ternary$libresoc.v:127645$5316_Y - connect \$101 $ternary$libresoc.v:127646$5317_Y - connect \$103 $ternary$libresoc.v:127647$5318_Y - connect \$105 $ternary$libresoc.v:127648$5319_Y - connect \$107 $ternary$libresoc.v:127649$5320_Y - connect \$109 $ternary$libresoc.v:127650$5321_Y - connect \$111 $ternary$libresoc.v:127651$5322_Y - connect \$113 $ternary$libresoc.v:127652$5323_Y - connect \$115 $ternary$libresoc.v:127653$5324_Y - connect \$117 $ternary$libresoc.v:127654$5325_Y - connect \$11 $eq$libresoc.v:127655$5326_Y - connect \$119 $ternary$libresoc.v:127656$5327_Y - connect \$121 $ternary$libresoc.v:127657$5328_Y - connect \$123 $ternary$libresoc.v:127658$5329_Y - connect \$125 $ternary$libresoc.v:127659$5330_Y - connect \$127 $ternary$libresoc.v:127660$5331_Y - connect \$129 $ternary$libresoc.v:127661$5332_Y - connect \$131 $ternary$libresoc.v:127662$5333_Y - connect \$133 $ternary$libresoc.v:127663$5334_Y - connect \$135 $ternary$libresoc.v:127664$5335_Y - connect \$137 $ternary$libresoc.v:127665$5336_Y - connect \$13 $eq$libresoc.v:127666$5337_Y - connect \$139 $ternary$libresoc.v:127667$5338_Y - connect \$141 $ternary$libresoc.v:127668$5339_Y - connect \$143 $ternary$libresoc.v:127669$5340_Y - connect \$145 $ternary$libresoc.v:127670$5341_Y - connect \$147 $ternary$libresoc.v:127671$5342_Y - connect \$149 $ternary$libresoc.v:127672$5343_Y - connect \$151 $ternary$libresoc.v:127673$5344_Y - connect \$153 $ternary$libresoc.v:127674$5345_Y - connect \$155 $ternary$libresoc.v:127675$5346_Y - connect \$157 $ternary$libresoc.v:127676$5347_Y - connect \$15 $or$libresoc.v:127677$5348_Y - connect \$159 $ternary$libresoc.v:127678$5349_Y - connect \$161 $ternary$libresoc.v:127679$5350_Y - connect \$163 $ternary$libresoc.v:127680$5351_Y - connect \$165 $ternary$libresoc.v:127681$5352_Y - connect \$167 $ternary$libresoc.v:127682$5353_Y - connect \$169 $ternary$libresoc.v:127683$5354_Y - connect \$171 $ternary$libresoc.v:127684$5355_Y - connect \$173 $ternary$libresoc.v:127685$5356_Y - connect \$175 $ternary$libresoc.v:127686$5357_Y - connect \$177 $ternary$libresoc.v:127687$5358_Y - connect \$17 $and$libresoc.v:127688$5359_Y - connect \$179 $ternary$libresoc.v:127689$5360_Y - connect \$181 $ternary$libresoc.v:127690$5361_Y - connect \$183 $ternary$libresoc.v:127691$5362_Y - connect \$185 $ternary$libresoc.v:127692$5363_Y - connect \$187 $ternary$libresoc.v:127693$5364_Y - connect \$189 $ternary$libresoc.v:127694$5365_Y - connect \$191 $ternary$libresoc.v:127695$5366_Y - connect \$193 $ternary$libresoc.v:127696$5367_Y - connect \$195 $ternary$libresoc.v:127697$5368_Y - connect \$197 $ternary$libresoc.v:127698$5369_Y - connect \$1 $eq$libresoc.v:127699$5370_Y - connect \$19 $eq$libresoc.v:127700$5371_Y - connect \$199 $ternary$libresoc.v:127701$5372_Y - connect \$201 $ternary$libresoc.v:127702$5373_Y - connect \$203 $ternary$libresoc.v:127703$5374_Y - connect \$205 $ternary$libresoc.v:127704$5375_Y - connect \$207 $ternary$libresoc.v:127705$5376_Y - connect \$209 $ternary$libresoc.v:127706$5377_Y - connect \$211 $ternary$libresoc.v:127707$5378_Y - connect \$213 $ternary$libresoc.v:127708$5379_Y - connect \$215 $ternary$libresoc.v:127709$5380_Y - connect \$217 $ternary$libresoc.v:127710$5381_Y - connect \$21 $eq$libresoc.v:127711$5382_Y - connect \$219 $ternary$libresoc.v:127712$5383_Y - connect \$221 $ternary$libresoc.v:127713$5384_Y - connect \$223 $ternary$libresoc.v:127714$5385_Y - connect \$225 $ternary$libresoc.v:127715$5386_Y - connect \$227 $ternary$libresoc.v:127716$5387_Y - connect \$229 $ternary$libresoc.v:127717$5388_Y - connect \$231 $ternary$libresoc.v:127718$5389_Y - connect \$233 $ternary$libresoc.v:127719$5390_Y - connect \$235 $ternary$libresoc.v:127720$5391_Y - connect \$237 $ternary$libresoc.v:127721$5392_Y - connect \$23 $or$libresoc.v:127722$5393_Y - connect \$239 $ternary$libresoc.v:127723$5394_Y - connect \$241 $ternary$libresoc.v:127724$5395_Y - connect \$243 $ternary$libresoc.v:127725$5396_Y - connect \$245 $ternary$libresoc.v:127726$5397_Y - connect \$247 $ternary$libresoc.v:127727$5398_Y - connect \$249 $ternary$libresoc.v:127728$5399_Y - connect \$251 $ternary$libresoc.v:127729$5400_Y - connect \$253 $ternary$libresoc.v:127730$5401_Y - connect \$255 $ternary$libresoc.v:127731$5402_Y - connect \$257 $ternary$libresoc.v:127732$5403_Y - connect \$25 $eq$libresoc.v:127733$5404_Y - connect \$259 $ternary$libresoc.v:127734$5405_Y - connect \$261 $ternary$libresoc.v:127735$5406_Y - connect \$263 $ternary$libresoc.v:127736$5407_Y - connect \$265 $ternary$libresoc.v:127737$5408_Y - connect \$267 $ternary$libresoc.v:127738$5409_Y - connect \$269 $ternary$libresoc.v:127739$5410_Y - connect \$271 $ternary$libresoc.v:127740$5411_Y - connect \$273 $ternary$libresoc.v:127741$5412_Y - connect \$275 $ternary$libresoc.v:127742$5413_Y - connect \$277 $ternary$libresoc.v:127743$5414_Y - connect \$27 $or$libresoc.v:127744$5415_Y - connect \$279 $ternary$libresoc.v:127745$5416_Y - connect \$281 $ternary$libresoc.v:127746$5417_Y - connect \$283 $ternary$libresoc.v:127747$5418_Y - connect \$285 $ternary$libresoc.v:127748$5419_Y - connect \$287 $ternary$libresoc.v:127749$5420_Y - connect \$289 $ternary$libresoc.v:127750$5421_Y - connect \$291 $ternary$libresoc.v:127751$5422_Y - connect \$293 $ternary$libresoc.v:127752$5423_Y - connect \$295 $ternary$libresoc.v:127753$5424_Y - connect \$297 $ternary$libresoc.v:127754$5425_Y - connect \$29 $and$libresoc.v:127755$5426_Y - connect \$299 $ternary$libresoc.v:127756$5427_Y - connect \$301 $ternary$libresoc.v:127757$5428_Y - connect \$303 $ternary$libresoc.v:127758$5429_Y - connect \$305 $ternary$libresoc.v:127759$5430_Y - connect \$307 $ternary$libresoc.v:127760$5431_Y - connect \$309 $ternary$libresoc.v:127761$5432_Y - connect \$311 $ternary$libresoc.v:127762$5433_Y - connect \$313 $ternary$libresoc.v:127763$5434_Y - connect \$315 $ternary$libresoc.v:127764$5435_Y - connect \$317 $ternary$libresoc.v:127765$5436_Y - connect \$31 $and$libresoc.v:127766$5437_Y - connect \$319 $ternary$libresoc.v:127767$5438_Y - connect \$321 $ternary$libresoc.v:127768$5439_Y - connect \$323 $ternary$libresoc.v:127769$5440_Y - connect \$325 $ternary$libresoc.v:127770$5441_Y - connect \$327 $ternary$libresoc.v:127771$5442_Y - connect \$329 $ternary$libresoc.v:127772$5443_Y - connect \$331 $ternary$libresoc.v:127773$5444_Y - connect \$333 $ternary$libresoc.v:127774$5445_Y - connect \$335 $ternary$libresoc.v:127775$5446_Y - connect \$337 $ternary$libresoc.v:127776$5447_Y - connect \$33 $eq$libresoc.v:127777$5448_Y - connect \$339 $ternary$libresoc.v:127778$5449_Y - connect \$341 $ternary$libresoc.v:127779$5450_Y - connect \$343 $ternary$libresoc.v:127780$5451_Y - connect \$345 $ternary$libresoc.v:127781$5452_Y - connect \$347 $ternary$libresoc.v:127782$5453_Y - connect \$349 $ternary$libresoc.v:127783$5454_Y - connect \$351 $ternary$libresoc.v:127784$5455_Y - connect \$353 $ternary$libresoc.v:127785$5456_Y - connect \$355 $ternary$libresoc.v:127786$5457_Y - connect \$357 $ternary$libresoc.v:127787$5458_Y - connect \$35 $eq$libresoc.v:127788$5459_Y - connect \$359 $eq$libresoc.v:127789$5460_Y - connect \$361 $eq$libresoc.v:127790$5461_Y - connect \$363 $or$libresoc.v:127791$5462_Y - connect \$365 $eq$libresoc.v:127792$5463_Y - connect \$367 $or$libresoc.v:127793$5464_Y - connect \$369 $and$libresoc.v:127794$5465_Y - connect \$371 $eq$libresoc.v:127795$5466_Y - connect \$373 $ne$libresoc.v:127796$5467_Y - connect \$375 $and$libresoc.v:127797$5468_Y - connect \$377 $ne$libresoc.v:127798$5469_Y - connect \$37 $or$libresoc.v:127799$5470_Y - connect \$379 $and$libresoc.v:127800$5471_Y - connect \$381 $ne$libresoc.v:127801$5472_Y - connect \$383 $and$libresoc.v:127802$5473_Y - connect \$385 $not$libresoc.v:127803$5474_Y - connect \$387 $and$libresoc.v:127804$5475_Y - connect \$389 $eq$libresoc.v:127805$5476_Y - connect \$391 $ne$libresoc.v:127806$5477_Y - connect \$393 $and$libresoc.v:127807$5478_Y - connect \$395 $ne$libresoc.v:127808$5479_Y - connect \$397 $and$libresoc.v:127809$5480_Y - connect \$3 $eq$libresoc.v:127810$5481_Y - connect \$39 $eq$libresoc.v:127811$5482_Y - connect \$399 $ne$libresoc.v:127812$5483_Y - connect \$401 $and$libresoc.v:127813$5484_Y - connect \$403 $not$libresoc.v:127814$5485_Y - connect \$405 $and$libresoc.v:127815$5486_Y - connect \$407 $eq$libresoc.v:127816$5487_Y - connect \$409 $eq$libresoc.v:127817$5488_Y - connect \$411 $ne$libresoc.v:127818$5489_Y - connect \$413 $and$libresoc.v:127819$5490_Y - connect \$415 $ne$libresoc.v:127820$5491_Y - connect \$417 $and$libresoc.v:127821$5492_Y - connect \$41 $or$libresoc.v:127822$5493_Y - connect \$419 $ne$libresoc.v:127823$5494_Y - connect \$421 $and$libresoc.v:127824$5495_Y - connect \$423 $not$libresoc.v:127825$5496_Y - connect \$425 $and$libresoc.v:127826$5497_Y - connect \$427 $eq$libresoc.v:127827$5498_Y - connect \$429 $ne$libresoc.v:127828$5499_Y - connect \$431 $and$libresoc.v:127829$5500_Y - connect \$433 $ne$libresoc.v:127830$5501_Y - connect \$435 $and$libresoc.v:127831$5502_Y - connect \$437 $ne$libresoc.v:127832$5503_Y - connect \$43 $and$libresoc.v:127833$5504_Y - connect \$439 $and$libresoc.v:127834$5505_Y - connect \$441 $not$libresoc.v:127835$5506_Y - connect \$443 $and$libresoc.v:127836$5507_Y - connect \$445 $eq$libresoc.v:127837$5508_Y - connect \$447 $eq$libresoc.v:127838$5509_Y - connect \$449 $ne$libresoc.v:127839$5510_Y - connect \$451 $and$libresoc.v:127840$5511_Y - connect \$453 $ne$libresoc.v:127841$5512_Y - connect \$455 $and$libresoc.v:127842$5513_Y - connect \$457 $ne$libresoc.v:127843$5514_Y - connect \$45 $and$libresoc.v:127844$5515_Y - connect \$459 $and$libresoc.v:127845$5516_Y - connect \$461 $not$libresoc.v:127846$5517_Y - connect \$463 $and$libresoc.v:127847$5518_Y - connect \$465 $eq$libresoc.v:127848$5519_Y - connect \$467 $ne$libresoc.v:127849$5520_Y - connect \$469 $and$libresoc.v:127850$5521_Y - connect \$471 $ne$libresoc.v:127851$5522_Y - connect \$473 $and$libresoc.v:127852$5523_Y - connect \$475 $ne$libresoc.v:127853$5524_Y - connect \$477 $and$libresoc.v:127854$5525_Y - connect \$47 $eq$libresoc.v:127855$5526_Y - connect \$479 $not$libresoc.v:127856$5527_Y - connect \$481 $and$libresoc.v:127857$5528_Y - connect \$484 $eq$libresoc.v:127858$5529_Y - connect \$483 $not$libresoc.v:127859$5530_Y - connect \$487 $eq$libresoc.v:127860$5531_Y - connect \$489 $eq$libresoc.v:127861$5532_Y - connect \$491 $or$libresoc.v:127862$5533_Y - connect \$493 $eq$libresoc.v:127863$5534_Y - connect \$496 $add$libresoc.v:127864$5535_Y - connect \$49 $eq$libresoc.v:127865$5536_Y - connect \$499 $add$libresoc.v:127866$5537_Y - connect \$501 $pos$libresoc.v:127867$5539_Y - connect \$504 $eq$libresoc.v:127868$5540_Y - connect \$506 $eq$libresoc.v:127869$5541_Y - connect \$508 $or$libresoc.v:127870$5542_Y - connect \$510 $eq$libresoc.v:127871$5543_Y - connect \$513 $add$libresoc.v:127872$5544_Y - connect \$516 $add$libresoc.v:127873$5545_Y - connect \$51 $ternary$libresoc.v:127874$5546_Y - connect \$53 $ternary$libresoc.v:127875$5547_Y - connect \$55 $ternary$libresoc.v:127876$5548_Y - connect \$57 $ternary$libresoc.v:127877$5549_Y - connect \$5 $or$libresoc.v:127878$5550_Y - connect \$59 $ternary$libresoc.v:127879$5551_Y - connect \$61 $ternary$libresoc.v:127880$5552_Y - connect \$63 $ternary$libresoc.v:127881$5553_Y - connect \$65 $ternary$libresoc.v:127882$5554_Y - connect \$67 $ternary$libresoc.v:127883$5555_Y - connect \$69 $ternary$libresoc.v:127884$5556_Y - connect \$71 $ternary$libresoc.v:127885$5557_Y - connect \$73 $ternary$libresoc.v:127886$5558_Y - connect \$75 $ternary$libresoc.v:127887$5559_Y - connect \$77 $ternary$libresoc.v:127888$5560_Y - connect \$7 $and$libresoc.v:127889$5561_Y - connect \$79 $ternary$libresoc.v:127890$5562_Y - connect \$81 $ternary$libresoc.v:127891$5563_Y - connect \$83 $ternary$libresoc.v:127892$5564_Y - connect \$85 $ternary$libresoc.v:127893$5565_Y - connect \$87 $ternary$libresoc.v:127894$5566_Y - connect \$89 $ternary$libresoc.v:127895$5567_Y - connect \$91 $ternary$libresoc.v:127896$5568_Y - connect \$93 $ternary$libresoc.v:127897$5569_Y - connect \$95 $ternary$libresoc.v:127898$5570_Y - connect \$97 $ternary$libresoc.v:127899$5571_Y + assign $2\io_bd$next[153:0]$6083 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[153:0]$6083 $1\io_bd$next[153:0]$6082 + end + sync always + update \io_bd$next $0\io_bd$next[153:0]$6081 + end + connect \$9 $eq$libresoc.v:137363$5632_Y + connect \$99 $ternary$libresoc.v:137364$5633_Y + connect \$101 $ternary$libresoc.v:137365$5634_Y + connect \$103 $ternary$libresoc.v:137366$5635_Y + connect \$105 $ternary$libresoc.v:137367$5636_Y + connect \$107 $ternary$libresoc.v:137368$5637_Y + connect \$109 $ternary$libresoc.v:137369$5638_Y + connect \$111 $ternary$libresoc.v:137370$5639_Y + connect \$113 $ternary$libresoc.v:137371$5640_Y + connect \$115 $ternary$libresoc.v:137372$5641_Y + connect \$117 $ternary$libresoc.v:137373$5642_Y + connect \$11 $eq$libresoc.v:137374$5643_Y + connect \$119 $ternary$libresoc.v:137375$5644_Y + connect \$121 $ternary$libresoc.v:137376$5645_Y + connect \$123 $ternary$libresoc.v:137377$5646_Y + connect \$125 $ternary$libresoc.v:137378$5647_Y + connect \$127 $ternary$libresoc.v:137379$5648_Y + connect \$129 $ternary$libresoc.v:137380$5649_Y + connect \$131 $ternary$libresoc.v:137381$5650_Y + connect \$133 $ternary$libresoc.v:137382$5651_Y + connect \$135 $ternary$libresoc.v:137383$5652_Y + connect \$137 $ternary$libresoc.v:137384$5653_Y + connect \$13 $eq$libresoc.v:137385$5654_Y + connect \$139 $ternary$libresoc.v:137386$5655_Y + connect \$141 $ternary$libresoc.v:137387$5656_Y + connect \$143 $ternary$libresoc.v:137388$5657_Y + connect \$145 $ternary$libresoc.v:137389$5658_Y + connect \$147 $ternary$libresoc.v:137390$5659_Y + connect \$149 $ternary$libresoc.v:137391$5660_Y + connect \$151 $ternary$libresoc.v:137392$5661_Y + connect \$153 $ternary$libresoc.v:137393$5662_Y + connect \$155 $ternary$libresoc.v:137394$5663_Y + connect \$157 $ternary$libresoc.v:137395$5664_Y + connect \$15 $or$libresoc.v:137396$5665_Y + connect \$159 $ternary$libresoc.v:137397$5666_Y + connect \$161 $ternary$libresoc.v:137398$5667_Y + connect \$163 $ternary$libresoc.v:137399$5668_Y + connect \$165 $ternary$libresoc.v:137400$5669_Y + connect \$167 $ternary$libresoc.v:137401$5670_Y + connect \$169 $ternary$libresoc.v:137402$5671_Y + connect \$171 $ternary$libresoc.v:137403$5672_Y + connect \$173 $ternary$libresoc.v:137404$5673_Y + connect \$175 $ternary$libresoc.v:137405$5674_Y + connect \$177 $ternary$libresoc.v:137406$5675_Y + connect \$17 $and$libresoc.v:137407$5676_Y + connect \$179 $ternary$libresoc.v:137408$5677_Y + connect \$181 $ternary$libresoc.v:137409$5678_Y + connect \$183 $ternary$libresoc.v:137410$5679_Y + connect \$185 $ternary$libresoc.v:137411$5680_Y + connect \$187 $ternary$libresoc.v:137412$5681_Y + connect \$189 $ternary$libresoc.v:137413$5682_Y + connect \$191 $ternary$libresoc.v:137414$5683_Y + connect \$193 $ternary$libresoc.v:137415$5684_Y + connect \$195 $ternary$libresoc.v:137416$5685_Y + connect \$197 $ternary$libresoc.v:137417$5686_Y + connect \$1 $eq$libresoc.v:137418$5687_Y + connect \$19 $eq$libresoc.v:137419$5688_Y + connect \$199 $ternary$libresoc.v:137420$5689_Y + connect \$201 $ternary$libresoc.v:137421$5690_Y + connect \$203 $ternary$libresoc.v:137422$5691_Y + connect \$205 $ternary$libresoc.v:137423$5692_Y + connect \$207 $ternary$libresoc.v:137424$5693_Y + connect \$209 $ternary$libresoc.v:137425$5694_Y + connect \$211 $ternary$libresoc.v:137426$5695_Y + connect \$213 $ternary$libresoc.v:137427$5696_Y + connect \$215 $ternary$libresoc.v:137428$5697_Y + connect \$217 $ternary$libresoc.v:137429$5698_Y + connect \$21 $eq$libresoc.v:137430$5699_Y + connect \$219 $ternary$libresoc.v:137431$5700_Y + connect \$221 $ternary$libresoc.v:137432$5701_Y + connect \$223 $ternary$libresoc.v:137433$5702_Y + connect \$225 $ternary$libresoc.v:137434$5703_Y + connect \$227 $ternary$libresoc.v:137435$5704_Y + connect \$229 $ternary$libresoc.v:137436$5705_Y + connect \$231 $ternary$libresoc.v:137437$5706_Y + connect \$233 $ternary$libresoc.v:137438$5707_Y + connect \$235 $ternary$libresoc.v:137439$5708_Y + connect \$237 $ternary$libresoc.v:137440$5709_Y + connect \$23 $or$libresoc.v:137441$5710_Y + connect \$239 $ternary$libresoc.v:137442$5711_Y + connect \$241 $ternary$libresoc.v:137443$5712_Y + connect \$243 $ternary$libresoc.v:137444$5713_Y + connect \$245 $ternary$libresoc.v:137445$5714_Y + connect \$247 $ternary$libresoc.v:137446$5715_Y + connect \$249 $ternary$libresoc.v:137447$5716_Y + connect \$251 $ternary$libresoc.v:137448$5717_Y + connect \$253 $ternary$libresoc.v:137449$5718_Y + connect \$255 $ternary$libresoc.v:137450$5719_Y + connect \$257 $ternary$libresoc.v:137451$5720_Y + connect \$25 $eq$libresoc.v:137452$5721_Y + connect \$259 $ternary$libresoc.v:137453$5722_Y + connect \$261 $ternary$libresoc.v:137454$5723_Y + connect \$263 $ternary$libresoc.v:137455$5724_Y + connect \$265 $ternary$libresoc.v:137456$5725_Y + connect \$267 $ternary$libresoc.v:137457$5726_Y + connect \$269 $ternary$libresoc.v:137458$5727_Y + connect \$271 $ternary$libresoc.v:137459$5728_Y + connect \$273 $ternary$libresoc.v:137460$5729_Y + connect \$275 $ternary$libresoc.v:137461$5730_Y + connect \$277 $ternary$libresoc.v:137462$5731_Y + connect \$27 $or$libresoc.v:137463$5732_Y + connect \$279 $ternary$libresoc.v:137464$5733_Y + connect \$281 $ternary$libresoc.v:137465$5734_Y + connect \$283 $ternary$libresoc.v:137466$5735_Y + connect \$285 $ternary$libresoc.v:137467$5736_Y + connect \$287 $ternary$libresoc.v:137468$5737_Y + connect \$289 $ternary$libresoc.v:137469$5738_Y + connect \$291 $ternary$libresoc.v:137470$5739_Y + connect \$293 $ternary$libresoc.v:137471$5740_Y + connect \$295 $ternary$libresoc.v:137472$5741_Y + connect \$297 $ternary$libresoc.v:137473$5742_Y + connect \$29 $and$libresoc.v:137474$5743_Y + connect \$299 $ternary$libresoc.v:137475$5744_Y + connect \$301 $ternary$libresoc.v:137476$5745_Y + connect \$303 $ternary$libresoc.v:137477$5746_Y + connect \$305 $ternary$libresoc.v:137478$5747_Y + connect \$307 $ternary$libresoc.v:137479$5748_Y + connect \$309 $ternary$libresoc.v:137480$5749_Y + connect \$311 $ternary$libresoc.v:137481$5750_Y + connect \$313 $ternary$libresoc.v:137482$5751_Y + connect \$315 $ternary$libresoc.v:137483$5752_Y + connect \$317 $ternary$libresoc.v:137484$5753_Y + connect \$31 $and$libresoc.v:137485$5754_Y + connect \$319 $ternary$libresoc.v:137486$5755_Y + connect \$321 $ternary$libresoc.v:137487$5756_Y + connect \$323 $ternary$libresoc.v:137488$5757_Y + connect \$325 $ternary$libresoc.v:137489$5758_Y + connect \$327 $ternary$libresoc.v:137490$5759_Y + connect \$329 $ternary$libresoc.v:137491$5760_Y + connect \$331 $ternary$libresoc.v:137492$5761_Y + connect \$333 $ternary$libresoc.v:137493$5762_Y + connect \$335 $ternary$libresoc.v:137494$5763_Y + connect \$337 $ternary$libresoc.v:137495$5764_Y + connect \$33 $eq$libresoc.v:137496$5765_Y + connect \$339 $ternary$libresoc.v:137497$5766_Y + connect \$341 $ternary$libresoc.v:137498$5767_Y + connect \$343 $ternary$libresoc.v:137499$5768_Y + connect \$345 $ternary$libresoc.v:137500$5769_Y + connect \$347 $ternary$libresoc.v:137501$5770_Y + connect \$349 $ternary$libresoc.v:137502$5771_Y + connect \$351 $ternary$libresoc.v:137503$5772_Y + connect \$353 $ternary$libresoc.v:137504$5773_Y + connect \$355 $ternary$libresoc.v:137505$5774_Y + connect \$357 $ternary$libresoc.v:137506$5775_Y + connect \$35 $eq$libresoc.v:137507$5776_Y + connect \$359 $eq$libresoc.v:137508$5777_Y + connect \$361 $eq$libresoc.v:137509$5778_Y + connect \$363 $or$libresoc.v:137510$5779_Y + connect \$365 $eq$libresoc.v:137511$5780_Y + connect \$367 $or$libresoc.v:137512$5781_Y + connect \$369 $and$libresoc.v:137513$5782_Y + connect \$371 $eq$libresoc.v:137514$5783_Y + connect \$373 $ne$libresoc.v:137515$5784_Y + connect \$375 $and$libresoc.v:137516$5785_Y + connect \$377 $ne$libresoc.v:137517$5786_Y + connect \$37 $or$libresoc.v:137518$5787_Y + connect \$379 $and$libresoc.v:137519$5788_Y + connect \$381 $ne$libresoc.v:137520$5789_Y + connect \$383 $and$libresoc.v:137521$5790_Y + connect \$385 $not$libresoc.v:137522$5791_Y + connect \$387 $and$libresoc.v:137523$5792_Y + connect \$389 $eq$libresoc.v:137524$5793_Y + connect \$391 $ne$libresoc.v:137525$5794_Y + connect \$393 $and$libresoc.v:137526$5795_Y + connect \$395 $ne$libresoc.v:137527$5796_Y + connect \$397 $and$libresoc.v:137528$5797_Y + connect \$3 $eq$libresoc.v:137529$5798_Y + connect \$39 $eq$libresoc.v:137530$5799_Y + connect \$399 $ne$libresoc.v:137531$5800_Y + connect \$401 $and$libresoc.v:137532$5801_Y + connect \$403 $not$libresoc.v:137533$5802_Y + connect \$405 $and$libresoc.v:137534$5803_Y + connect \$407 $eq$libresoc.v:137535$5804_Y + connect \$409 $eq$libresoc.v:137536$5805_Y + connect \$411 $ne$libresoc.v:137537$5806_Y + connect \$413 $and$libresoc.v:137538$5807_Y + connect \$415 $ne$libresoc.v:137539$5808_Y + connect \$417 $and$libresoc.v:137540$5809_Y + connect \$41 $or$libresoc.v:137541$5810_Y + connect \$419 $ne$libresoc.v:137542$5811_Y + connect \$421 $and$libresoc.v:137543$5812_Y + connect \$423 $not$libresoc.v:137544$5813_Y + connect \$425 $and$libresoc.v:137545$5814_Y + connect \$427 $eq$libresoc.v:137546$5815_Y + connect \$429 $ne$libresoc.v:137547$5816_Y + connect \$431 $and$libresoc.v:137548$5817_Y + connect \$433 $ne$libresoc.v:137549$5818_Y + connect \$435 $and$libresoc.v:137550$5819_Y + connect \$437 $ne$libresoc.v:137551$5820_Y + connect \$43 $and$libresoc.v:137552$5821_Y + connect \$439 $and$libresoc.v:137553$5822_Y + connect \$441 $not$libresoc.v:137554$5823_Y + connect \$443 $and$libresoc.v:137555$5824_Y + connect \$445 $eq$libresoc.v:137556$5825_Y + connect \$447 $eq$libresoc.v:137557$5826_Y + connect \$449 $ne$libresoc.v:137558$5827_Y + connect \$451 $and$libresoc.v:137559$5828_Y + connect \$453 $ne$libresoc.v:137560$5829_Y + connect \$455 $and$libresoc.v:137561$5830_Y + connect \$457 $ne$libresoc.v:137562$5831_Y + connect \$45 $and$libresoc.v:137563$5832_Y + connect \$459 $and$libresoc.v:137564$5833_Y + connect \$461 $not$libresoc.v:137565$5834_Y + connect \$463 $and$libresoc.v:137566$5835_Y + connect \$465 $eq$libresoc.v:137567$5836_Y + connect \$467 $ne$libresoc.v:137568$5837_Y + connect \$469 $and$libresoc.v:137569$5838_Y + connect \$471 $ne$libresoc.v:137570$5839_Y + connect \$473 $and$libresoc.v:137571$5840_Y + connect \$475 $ne$libresoc.v:137572$5841_Y + connect \$477 $and$libresoc.v:137573$5842_Y + connect \$47 $eq$libresoc.v:137574$5843_Y + connect \$479 $not$libresoc.v:137575$5844_Y + connect \$481 $and$libresoc.v:137576$5845_Y + connect \$484 $eq$libresoc.v:137577$5846_Y + connect \$483 $not$libresoc.v:137578$5847_Y + connect \$487 $eq$libresoc.v:137579$5848_Y + connect \$489 $eq$libresoc.v:137580$5849_Y + connect \$491 $or$libresoc.v:137581$5850_Y + connect \$493 $eq$libresoc.v:137582$5851_Y + connect \$496 $add$libresoc.v:137583$5852_Y + connect \$49 $eq$libresoc.v:137584$5853_Y + connect \$499 $add$libresoc.v:137585$5854_Y + connect \$501 $pos$libresoc.v:137586$5856_Y + connect \$504 $eq$libresoc.v:137587$5857_Y + connect \$506 $eq$libresoc.v:137588$5858_Y + connect \$508 $or$libresoc.v:137589$5859_Y + connect \$510 $eq$libresoc.v:137590$5860_Y + connect \$513 $add$libresoc.v:137591$5861_Y + connect \$516 $add$libresoc.v:137592$5862_Y + connect \$51 $ternary$libresoc.v:137593$5863_Y + connect \$53 $ternary$libresoc.v:137594$5864_Y + connect \$55 $ternary$libresoc.v:137595$5865_Y + connect \$57 $ternary$libresoc.v:137596$5866_Y + connect \$5 $or$libresoc.v:137597$5867_Y + connect \$59 $ternary$libresoc.v:137598$5868_Y + connect \$61 $ternary$libresoc.v:137599$5869_Y + connect \$63 $ternary$libresoc.v:137600$5870_Y + connect \$65 $ternary$libresoc.v:137601$5871_Y + connect \$67 $ternary$libresoc.v:137602$5872_Y + connect \$69 $ternary$libresoc.v:137603$5873_Y + connect \$71 $ternary$libresoc.v:137604$5874_Y + connect \$73 $ternary$libresoc.v:137605$5875_Y + connect \$75 $ternary$libresoc.v:137606$5876_Y + connect \$77 $ternary$libresoc.v:137607$5877_Y + connect \$7 $and$libresoc.v:137608$5878_Y + connect \$79 $ternary$libresoc.v:137609$5879_Y + connect \$81 $ternary$libresoc.v:137610$5880_Y + connect \$83 $ternary$libresoc.v:137611$5881_Y + connect \$85 $ternary$libresoc.v:137612$5882_Y + connect \$87 $ternary$libresoc.v:137613$5883_Y + connect \$89 $ternary$libresoc.v:137614$5884_Y + connect \$91 $ternary$libresoc.v:137615$5885_Y + connect \$93 $ternary$libresoc.v:137616$5886_Y + connect \$95 $ternary$libresoc.v:137617$5887_Y + connect \$97 $ternary$libresoc.v:137618$5888_Y connect \$495 \$496 connect \$498 \$499 connect \$512 \$513 @@ -206349,14 +222156,14 @@ module \jtag connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:128931.1-129120.10" +attribute \src "libresoc.v:138654.1-138843.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 23 \dbus__ack @@ -206456,10 +222263,10 @@ module \l0 wire \pimem_x_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire \pimem_x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:129036.12-129070.4" + attribute \src "libresoc.v:138759.12-138793.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206496,7 +222303,7 @@ module \l0 connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:129071.9-129093.4" + attribute \src "libresoc.v:138794.9-138816.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206521,7 +222328,7 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:129094.9-129118.4" + attribute \src "libresoc.v:138817.9-138841.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206549,150 +222356,150 @@ module \l0 end connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:129124.1-129532.10" +attribute \src "libresoc.v:138847.1-139255.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 - attribute \src "libresoc.v:129387.3-129401.6" - wire $0\idx_l$23$next[0:0]$5840 - attribute \src "libresoc.v:129287.3-129288.35" - wire $0\idx_l$23[0:0]$5807 - attribute \src "libresoc.v:129145.7-129145.24" - wire $0\idx_l$23[0:0]$5862 - attribute \src "libresoc.v:129442.3-129451.6" + attribute \src "libresoc.v:139110.3-139124.6" + wire $0\idx_l$23$next[0:0]$6162 + attribute \src "libresoc.v:139010.3-139011.35" + wire $0\idx_l$23[0:0]$6129 + attribute \src "libresoc.v:138868.7-138868.24" + wire $0\idx_l$23[0:0]$6184 + attribute \src "libresoc.v:139165.3-139174.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:129432.3-129441.6" + attribute \src "libresoc.v:139155.3-139164.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:129125.7-129125.20" + attribute \src "libresoc.v:138848.7-138848.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129308.3-129317.6" - wire width 48 $0\ldst_port0_addr_i$12[47:0]$5809 - attribute \src "libresoc.v:129318.3-129327.6" - wire $0\ldst_port0_addr_i_ok$13[0:0]$5812 - attribute \src "libresoc.v:129360.3-129369.6" + attribute \src "libresoc.v:139031.3-139040.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6131 + attribute \src "libresoc.v:139041.3-139050.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6134 + attribute \src "libresoc.v:139083.3-139092.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:129350.3-129359.6" + attribute \src "libresoc.v:139073.3-139082.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:129422.3-129431.6" + attribute \src "libresoc.v:139145.3-139154.6" wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:129497.3-129506.6" - wire width 4 $0\ldst_port0_data_len$11[3:0]$5857 - attribute \src "libresoc.v:129370.3-129386.6" - wire $0\ldst_port0_exc_$signal$1[0:0]$5824 - attribute \src "libresoc.v:129370.3-129386.6" - wire $0\ldst_port0_exc_$signal$2[0:0]$5825 - attribute \src "libresoc.v:129370.3-129386.6" - wire $0\ldst_port0_exc_$signal$3[0:0]$5826 - attribute \src "libresoc.v:129370.3-129386.6" - wire $0\ldst_port0_exc_$signal$4[0:0]$5827 - attribute \src "libresoc.v:129370.3-129386.6" - wire $0\ldst_port0_exc_$signal$5[0:0]$5828 - attribute \src "libresoc.v:129370.3-129386.6" - wire $0\ldst_port0_exc_$signal$6[0:0]$5829 - attribute \src "libresoc.v:129370.3-129386.6" - wire $0\ldst_port0_exc_$signal$7[0:0]$5830 - attribute \src "libresoc.v:129370.3-129386.6" - wire $0\ldst_port0_exc_$signal[0:0]$5823 - attribute \src "libresoc.v:129507.3-129516.6" + attribute \src "libresoc.v:139220.3-139229.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6179 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6146 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6147 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6148 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6149 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6150 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6151 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6152 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal[0:0]$6145 + attribute \src "libresoc.v:139230.3-139239.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:129477.3-129486.6" - wire $0\ldst_port0_is_ld_i$8[0:0]$5851 - attribute \src "libresoc.v:129487.3-129496.6" - wire $0\ldst_port0_is_st_i$9[0:0]$5854 - attribute \src "libresoc.v:129339.3-129349.6" + attribute \src "libresoc.v:139200.3-139209.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6173 + attribute \src "libresoc.v:139210.3-139219.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6176 + attribute \src "libresoc.v:139062.3-139072.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:129339.3-129349.6" + attribute \src "libresoc.v:139062.3-139072.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:129412.3-129421.6" + attribute \src "libresoc.v:139135.3-139144.6" wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:129402.3-129411.6" + attribute \src "libresoc.v:139125.3-139134.6" wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:129328.3-129338.6" - wire width 64 $0\ldst_port0_st_data_i$18[63:0]$5815 - attribute \src "libresoc.v:129328.3-129338.6" - wire $0\ldst_port0_st_data_i_ok$17[0:0]$5816 - attribute \src "libresoc.v:129285.3-129286.36" + attribute \src "libresoc.v:139051.3-139061.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6137 + attribute \src "libresoc.v:139051.3-139061.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6138 + attribute \src "libresoc.v:139008.3-139009.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:129467.3-129476.6" + attribute \src "libresoc.v:139190.3-139199.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:129452.3-129466.6" + attribute \src "libresoc.v:139175.3-139189.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:129387.3-129401.6" - wire $1\idx_l$23$next[0:0]$5841 - attribute \src "libresoc.v:129442.3-129451.6" + attribute \src "libresoc.v:139110.3-139124.6" + wire $1\idx_l$23$next[0:0]$6163 + attribute \src "libresoc.v:139165.3-139174.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:129432.3-129441.6" + attribute \src "libresoc.v:139155.3-139164.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:129308.3-129317.6" - wire width 48 $1\ldst_port0_addr_i$12[47:0]$5810 - attribute \src "libresoc.v:129318.3-129327.6" - wire $1\ldst_port0_addr_i_ok$13[0:0]$5813 - attribute \src "libresoc.v:129360.3-129369.6" + attribute \src "libresoc.v:139031.3-139040.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6132 + attribute \src "libresoc.v:139041.3-139050.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6135 + attribute \src "libresoc.v:139083.3-139092.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:129350.3-129359.6" + attribute \src "libresoc.v:139073.3-139082.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:129422.3-129431.6" + attribute \src "libresoc.v:139145.3-139154.6" wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:129497.3-129506.6" - wire width 4 $1\ldst_port0_data_len$11[3:0]$5858 - attribute \src "libresoc.v:129370.3-129386.6" - wire $1\ldst_port0_exc_$signal$1[0:0]$5832 - attribute \src "libresoc.v:129370.3-129386.6" - wire $1\ldst_port0_exc_$signal$2[0:0]$5833 - attribute \src "libresoc.v:129370.3-129386.6" - wire $1\ldst_port0_exc_$signal$3[0:0]$5834 - attribute \src "libresoc.v:129370.3-129386.6" - wire $1\ldst_port0_exc_$signal$4[0:0]$5835 - attribute \src "libresoc.v:129370.3-129386.6" - wire $1\ldst_port0_exc_$signal$5[0:0]$5836 - attribute \src "libresoc.v:129370.3-129386.6" - wire $1\ldst_port0_exc_$signal$6[0:0]$5837 - attribute \src "libresoc.v:129370.3-129386.6" - wire $1\ldst_port0_exc_$signal$7[0:0]$5838 - attribute \src "libresoc.v:129370.3-129386.6" - wire $1\ldst_port0_exc_$signal[0:0]$5831 - attribute \src "libresoc.v:129507.3-129516.6" + attribute \src "libresoc.v:139220.3-139229.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6180 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6154 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6155 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6156 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6157 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6158 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6159 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6160 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal[0:0]$6153 + attribute \src "libresoc.v:139230.3-139239.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:129477.3-129486.6" - wire $1\ldst_port0_is_ld_i$8[0:0]$5852 - attribute \src "libresoc.v:129487.3-129496.6" - wire $1\ldst_port0_is_st_i$9[0:0]$5855 - attribute \src "libresoc.v:129339.3-129349.6" + attribute \src "libresoc.v:139200.3-139209.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6174 + attribute \src "libresoc.v:139210.3-139219.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6177 + attribute \src "libresoc.v:139062.3-139072.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:129339.3-129349.6" + attribute \src "libresoc.v:139062.3-139072.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:129412.3-129421.6" + attribute \src "libresoc.v:139135.3-139144.6" wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:129402.3-129411.6" + attribute \src "libresoc.v:139125.3-139134.6" wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:129328.3-129338.6" - wire width 64 $1\ldst_port0_st_data_i$18[63:0]$5817 - attribute \src "libresoc.v:129328.3-129338.6" - wire $1\ldst_port0_st_data_i_ok$17[0:0]$5818 - attribute \src "libresoc.v:129272.7-129272.25" + attribute \src "libresoc.v:139051.3-139061.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6139 + attribute \src "libresoc.v:139051.3-139061.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6140 + attribute \src "libresoc.v:138995.7-138995.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:129467.3-129476.6" + attribute \src "libresoc.v:139190.3-139199.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:129452.3-129466.6" + attribute \src "libresoc.v:139175.3-139189.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:129387.3-129401.6" - wire $2\idx_l$23$next[0:0]$5842 - attribute \src "libresoc.v:129452.3-129466.6" + attribute \src "libresoc.v:139110.3-139124.6" + wire $2\idx_l$23$next[0:0]$6164 + attribute \src "libresoc.v:139175.3-139189.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:129283.18-129283.103" - wire $not$libresoc.v:129283$5803_Y - attribute \src "libresoc.v:129284.18-129284.118" - wire $not$libresoc.v:129284$5804_Y - attribute \src "libresoc.v:129281.18-129281.134" - wire $or$libresoc.v:129281$5801_Y - attribute \src "libresoc.v:129282.18-129282.120" - wire $ternary$libresoc.v:129282$5802_Y + attribute \src "libresoc.v:139006.18-139006.103" + wire $not$libresoc.v:139006$6125_Y + attribute \src "libresoc.v:139007.18-139007.118" + wire $not$libresoc.v:139007$6126_Y + attribute \src "libresoc.v:139004.18-139004.134" + wire $or$libresoc.v:139004$6123_Y + attribute \src "libresoc.v:139005.18-139005.120" + wire $ternary$libresoc.v:139005$6124_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" wire \$26 @@ -206702,21 +222509,21 @@ module \l0$130 wire width 96 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \idx_l_q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \idx_l_r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l - attribute \src "libresoc.v:129125.7-129125.15" + attribute \src "libresoc.v:138848.7-138848.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 input 6 \ldst_port0_addr_i @@ -206820,30 +222627,30 @@ module \l0$130 wire \reset_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" wire \reset_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \reset_l_q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:129283$5803 + cell $not $not$libresoc.v:139006$6125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:129283$5803_Y + connect \Y $not$libresoc.v:139006$6125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:129284$5804 + cell $not $not$libresoc.v:139007$6126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:129284$5804_Y + connect \Y $not$libresoc.v:139007$6126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:129281$5801 + cell $or $or$libresoc.v:139004$6123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206851,18 +222658,18 @@ module \l0$130 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:129281$5801_Y + connect \Y $or$libresoc.v:139004$6123_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:129282$5802 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:139005$6124 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:129282$5802_Y + connect \Y $ternary$libresoc.v:139005$6124_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:129289.9-129295.4" + attribute \src "libresoc.v:139012.9-139018.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206871,14 +222678,14 @@ module \l0$130 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:129296.8-129300.4" + attribute \src "libresoc.v:139019.8-139023.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:129301.17-129307.4" + attribute \src "libresoc.v:139024.17-139030.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206886,52 +222693,52 @@ module \l0$130 connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:129125.7-129125.20" - process $proc$libresoc.v:129125$5860 + attribute \src "libresoc.v:138848.7-138848.20" + process $proc$libresoc.v:138848$6182 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129145.7-129145.24" - process $proc$libresoc.v:129145$5861 + attribute \src "libresoc.v:138868.7-138868.24" + process $proc$libresoc.v:138868$6183 assign { } { } - assign $0\idx_l$23[0:0]$5862 1'0 + assign $0\idx_l$23[0:0]$6184 1'0 sync always sync init - update \idx_l$23 $0\idx_l$23[0:0]$5862 + update \idx_l$23 $0\idx_l$23[0:0]$6184 end - attribute \src "libresoc.v:129272.7-129272.25" - process $proc$libresoc.v:129272$5863 + attribute \src "libresoc.v:138995.7-138995.25" + process $proc$libresoc.v:138995$6185 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:129285.3-129286.36" - process $proc$libresoc.v:129285$5805 + attribute \src "libresoc.v:139008.3-139009.36" + process $proc$libresoc.v:139008$6127 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:129287.3-129288.35" - process $proc$libresoc.v:129287$5806 + attribute \src "libresoc.v:139010.3-139011.35" + process $proc$libresoc.v:139010$6128 assign { } { } - assign $0\idx_l$23[0:0]$5807 \idx_l$23$next + assign $0\idx_l$23[0:0]$6129 \idx_l$23$next sync posedge \coresync_clk - update \idx_l$23 $0\idx_l$23[0:0]$5807 + update \idx_l$23 $0\idx_l$23[0:0]$6129 end - attribute \src "libresoc.v:129308.3-129317.6" - process $proc$libresoc.v:129308$5808 + attribute \src "libresoc.v:139031.3-139040.6" + process $proc$libresoc.v:139031$6130 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i$12[47:0]$5809 $1\ldst_port0_addr_i$12[47:0]$5810 - attribute \src "libresoc.v:129309.5-129309.29" + assign $0\ldst_port0_addr_i$12[47:0]$6131 $1\ldst_port0_addr_i$12[47:0]$6132 + attribute \src "libresoc.v:139032.5-139032.29" switch \initial - attribute \src "libresoc.v:129309.9-129309.17" + attribute \src "libresoc.v:139032.9-139032.17" case 1'1 case end @@ -206940,21 +222747,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i$12[47:0]$5810 \$32 [47:0] + assign $1\ldst_port0_addr_i$12[47:0]$6132 \$32 [47:0] case - assign $1\ldst_port0_addr_i$12[47:0]$5810 48'000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_addr_i$12[47:0]$6132 48'000000000000000000000000000000000000000000000000 end sync always - update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$5809 + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6131 end - attribute \src "libresoc.v:129318.3-129327.6" - process $proc$libresoc.v:129318$5811 + attribute \src "libresoc.v:139041.3-139050.6" + process $proc$libresoc.v:139041$6133 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$13[0:0]$5812 $1\ldst_port0_addr_i_ok$13[0:0]$5813 - attribute \src "libresoc.v:129319.5-129319.29" + assign $0\ldst_port0_addr_i_ok$13[0:0]$6134 $1\ldst_port0_addr_i_ok$13[0:0]$6135 + attribute \src "libresoc.v:139042.5-139042.29" switch \initial - attribute \src "libresoc.v:129319.9-129319.17" + attribute \src "libresoc.v:139042.9-139042.17" case 1'1 case end @@ -206963,24 +222770,24 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$13[0:0]$5813 \ldst_port0_addr_i_ok + assign $1\ldst_port0_addr_i_ok$13[0:0]$6135 \ldst_port0_addr_i_ok case - assign $1\ldst_port0_addr_i_ok$13[0:0]$5813 1'0 + assign $1\ldst_port0_addr_i_ok$13[0:0]$6135 1'0 end sync always - update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$5812 + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6134 end - attribute \src "libresoc.v:129328.3-129338.6" - process $proc$libresoc.v:129328$5814 + attribute \src "libresoc.v:139051.3-139061.6" + process $proc$libresoc.v:139051$6136 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_st_data_i$18[63:0]$5815 $1\ldst_port0_st_data_i$18[63:0]$5817 - assign $0\ldst_port0_st_data_i_ok$17[0:0]$5816 $1\ldst_port0_st_data_i_ok$17[0:0]$5818 - attribute \src "libresoc.v:129329.5-129329.29" + assign $0\ldst_port0_st_data_i$18[63:0]$6137 $1\ldst_port0_st_data_i$18[63:0]$6139 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6138 $1\ldst_port0_st_data_i_ok$17[0:0]$6140 + attribute \src "libresoc.v:139052.5-139052.29" switch \initial - attribute \src "libresoc.v:129329.9-129329.17" + attribute \src "libresoc.v:139052.9-139052.17" case 1'1 case end @@ -206990,26 +222797,26 @@ module \l0$130 case 1'1 assign { } { } assign { } { } - assign { $1\ldst_port0_st_data_i_ok$17[0:0]$5818 $1\ldst_port0_st_data_i$18[63:0]$5817 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6140 $1\ldst_port0_st_data_i$18[63:0]$6139 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case - assign $1\ldst_port0_st_data_i$18[63:0]$5817 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$17[0:0]$5818 1'0 + assign $1\ldst_port0_st_data_i$18[63:0]$6139 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6140 1'0 end sync always - update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$5815 - update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$5816 + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6137 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6138 end - attribute \src "libresoc.v:129339.3-129349.6" - process $proc$libresoc.v:129339$5819 + attribute \src "libresoc.v:139062.3-139072.6" + process $proc$libresoc.v:139062$6141 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:129340.5-129340.29" + attribute \src "libresoc.v:139063.5-139063.29" switch \initial - attribute \src "libresoc.v:129340.9-129340.17" + attribute \src "libresoc.v:139063.9-139063.17" case 1'1 case end @@ -207028,14 +222835,14 @@ module \l0$130 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:129350.3-129359.6" - process $proc$libresoc.v:129350$5820 + attribute \src "libresoc.v:139073.3-139082.6" + process $proc$libresoc.v:139073$6142 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:129351.5-129351.29" + attribute \src "libresoc.v:139074.5-139074.29" switch \initial - attribute \src "libresoc.v:129351.9-129351.17" + attribute \src "libresoc.v:139074.9-139074.17" case 1'1 case end @@ -207051,14 +222858,14 @@ module \l0$130 sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:129360.3-129369.6" - process $proc$libresoc.v:129360$5821 + attribute \src "libresoc.v:139083.3-139092.6" + process $proc$libresoc.v:139083$6143 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:129361.5-129361.29" + attribute \src "libresoc.v:139084.5-139084.29" switch \initial - attribute \src "libresoc.v:129361.9-129361.17" + attribute \src "libresoc.v:139084.9-139084.17" case 1'1 case end @@ -207074,8 +222881,8 @@ module \l0$130 sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:129370.3-129386.6" - process $proc$libresoc.v:129370$5822 + attribute \src "libresoc.v:139093.3-139109.6" + process $proc$libresoc.v:139093$6144 assign { } { } assign { } { } assign { } { } @@ -207092,17 +222899,17 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_exc_$signal[0:0]$5823 $1\ldst_port0_exc_$signal[0:0]$5831 - assign $0\ldst_port0_exc_$signal$1[0:0]$5824 $1\ldst_port0_exc_$signal$1[0:0]$5832 - assign $0\ldst_port0_exc_$signal$2[0:0]$5825 $1\ldst_port0_exc_$signal$2[0:0]$5833 - assign $0\ldst_port0_exc_$signal$3[0:0]$5826 $1\ldst_port0_exc_$signal$3[0:0]$5834 - assign $0\ldst_port0_exc_$signal$4[0:0]$5827 $1\ldst_port0_exc_$signal$4[0:0]$5835 - assign $0\ldst_port0_exc_$signal$5[0:0]$5828 $1\ldst_port0_exc_$signal$5[0:0]$5836 - assign $0\ldst_port0_exc_$signal$6[0:0]$5829 $1\ldst_port0_exc_$signal$6[0:0]$5837 - assign $0\ldst_port0_exc_$signal$7[0:0]$5830 $1\ldst_port0_exc_$signal$7[0:0]$5838 - attribute \src "libresoc.v:129371.5-129371.29" + assign $0\ldst_port0_exc_$signal[0:0]$6145 $1\ldst_port0_exc_$signal[0:0]$6153 + assign $0\ldst_port0_exc_$signal$1[0:0]$6146 $1\ldst_port0_exc_$signal$1[0:0]$6154 + assign $0\ldst_port0_exc_$signal$2[0:0]$6147 $1\ldst_port0_exc_$signal$2[0:0]$6155 + assign $0\ldst_port0_exc_$signal$3[0:0]$6148 $1\ldst_port0_exc_$signal$3[0:0]$6156 + assign $0\ldst_port0_exc_$signal$4[0:0]$6149 $1\ldst_port0_exc_$signal$4[0:0]$6157 + assign $0\ldst_port0_exc_$signal$5[0:0]$6150 $1\ldst_port0_exc_$signal$5[0:0]$6158 + assign $0\ldst_port0_exc_$signal$6[0:0]$6151 $1\ldst_port0_exc_$signal$6[0:0]$6159 + assign $0\ldst_port0_exc_$signal$7[0:0]$6152 $1\ldst_port0_exc_$signal$7[0:0]$6160 + attribute \src "libresoc.v:139094.5-139094.29" switch \initial - attribute \src "libresoc.v:129371.9-129371.17" + attribute \src "libresoc.v:139094.9-139094.17" case 1'1 case end @@ -207118,68 +222925,68 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign { $1\ldst_port0_exc_$signal$7[0:0]$5838 $1\ldst_port0_exc_$signal$6[0:0]$5837 $1\ldst_port0_exc_$signal$5[0:0]$5836 $1\ldst_port0_exc_$signal$4[0:0]$5835 $1\ldst_port0_exc_$signal$3[0:0]$5834 $1\ldst_port0_exc_$signal$2[0:0]$5833 $1\ldst_port0_exc_$signal$1[0:0]$5832 $1\ldst_port0_exc_$signal[0:0]$5831 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6160 $1\ldst_port0_exc_$signal$6[0:0]$6159 $1\ldst_port0_exc_$signal$5[0:0]$6158 $1\ldst_port0_exc_$signal$4[0:0]$6157 $1\ldst_port0_exc_$signal$3[0:0]$6156 $1\ldst_port0_exc_$signal$2[0:0]$6155 $1\ldst_port0_exc_$signal$1[0:0]$6154 $1\ldst_port0_exc_$signal[0:0]$6153 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case - assign $1\ldst_port0_exc_$signal[0:0]$5831 1'0 - assign $1\ldst_port0_exc_$signal$1[0:0]$5832 1'0 - assign $1\ldst_port0_exc_$signal$2[0:0]$5833 1'0 - assign $1\ldst_port0_exc_$signal$3[0:0]$5834 1'0 - assign $1\ldst_port0_exc_$signal$4[0:0]$5835 1'0 - assign $1\ldst_port0_exc_$signal$5[0:0]$5836 1'0 - assign $1\ldst_port0_exc_$signal$6[0:0]$5837 1'0 - assign $1\ldst_port0_exc_$signal$7[0:0]$5838 1'0 + assign $1\ldst_port0_exc_$signal[0:0]$6153 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6154 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6155 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6156 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6157 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6158 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6159 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6160 1'0 end sync always - update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$5823 - update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$5824 - update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$5825 - update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$5826 - update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$5827 - update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$5828 - update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$5829 - update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$5830 + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6145 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6146 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6147 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6148 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6149 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6150 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6151 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6152 end - attribute \src "libresoc.v:129387.3-129401.6" - process $proc$libresoc.v:129387$5839 + attribute \src "libresoc.v:139110.3-139124.6" + process $proc$libresoc.v:139110$6161 assign { } { } assign { } { } assign { } { } - assign $0\idx_l$23$next[0:0]$5840 $2\idx_l$23$next[0:0]$5842 - attribute \src "libresoc.v:129388.5-129388.29" + assign $0\idx_l$23$next[0:0]$6162 $2\idx_l$23$next[0:0]$6164 + attribute \src "libresoc.v:139111.5-139111.29" switch \initial - attribute \src "libresoc.v:129388.9-129388.17" + attribute \src "libresoc.v:139111.9-139111.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l$23$next[0:0]$5841 \pick_o + assign $1\idx_l$23$next[0:0]$6163 \pick_o case - assign $1\idx_l$23$next[0:0]$5841 \idx_l$23 + assign $1\idx_l$23$next[0:0]$6163 \idx_l$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\idx_l$23$next[0:0]$5842 1'0 + assign $2\idx_l$23$next[0:0]$6164 1'0 case - assign $2\idx_l$23$next[0:0]$5842 $1\idx_l$23$next[0:0]$5841 + assign $2\idx_l$23$next[0:0]$6164 $1\idx_l$23$next[0:0]$6163 end sync always - update \idx_l$23$next $0\idx_l$23$next[0:0]$5840 + update \idx_l$23$next $0\idx_l$23$next[0:0]$6162 end - attribute \src "libresoc.v:129402.3-129411.6" - process $proc$libresoc.v:129402$5843 + attribute \src "libresoc.v:139125.3-139134.6" + process $proc$libresoc.v:139125$6165 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:129403.5-129403.29" + attribute \src "libresoc.v:139126.5-139126.29" switch \initial - attribute \src "libresoc.v:129403.9-129403.17" + attribute \src "libresoc.v:139126.9-139126.17" case 1'1 case end @@ -207195,14 +223002,14 @@ module \l0$130 sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:129412.3-129421.6" - process $proc$libresoc.v:129412$5844 + attribute \src "libresoc.v:139135.3-139144.6" + process $proc$libresoc.v:139135$6166 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:129413.5-129413.29" + attribute \src "libresoc.v:139136.5-139136.29" switch \initial - attribute \src "libresoc.v:129413.9-129413.17" + attribute \src "libresoc.v:139136.9-139136.17" case 1'1 case end @@ -207218,14 +223025,14 @@ module \l0$130 sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:129422.3-129431.6" - process $proc$libresoc.v:129422$5845 + attribute \src "libresoc.v:139145.3-139154.6" + process $proc$libresoc.v:139145$6167 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:129423.5-129423.29" + attribute \src "libresoc.v:139146.5-139146.29" switch \initial - attribute \src "libresoc.v:129423.9-129423.17" + attribute \src "libresoc.v:139146.9-139146.17" case 1'1 case end @@ -207241,14 +223048,14 @@ module \l0$130 sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:129432.3-129441.6" - process $proc$libresoc.v:129432$5846 + attribute \src "libresoc.v:139155.3-139164.6" + process $proc$libresoc.v:139155$6168 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:129433.5-129433.29" + attribute \src "libresoc.v:139156.5-139156.29" switch \initial - attribute \src "libresoc.v:129433.9-129433.17" + attribute \src "libresoc.v:139156.9-139156.17" case 1'1 case end @@ -207264,14 +223071,14 @@ module \l0$130 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:129442.3-129451.6" - process $proc$libresoc.v:129442$5847 + attribute \src "libresoc.v:139165.3-139174.6" + process $proc$libresoc.v:139165$6169 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:129443.5-129443.29" + attribute \src "libresoc.v:139166.5-139166.29" switch \initial - attribute \src "libresoc.v:129443.9-129443.17" + attribute \src "libresoc.v:139166.9-139166.17" case 1'1 case end @@ -207287,14 +223094,14 @@ module \l0$130 sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:129452.3-129466.6" - process $proc$libresoc.v:129452$5848 + attribute \src "libresoc.v:139175.3-139189.6" + process $proc$libresoc.v:139175$6170 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:129453.5-129453.29" + attribute \src "libresoc.v:139176.5-139176.29" switch \initial - attribute \src "libresoc.v:129453.9-129453.17" + attribute \src "libresoc.v:139176.9-139176.17" case 1'1 case end @@ -207319,14 +223126,14 @@ module \l0$130 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:129467.3-129476.6" - process $proc$libresoc.v:129467$5849 + attribute \src "libresoc.v:139190.3-139199.6" + process $proc$libresoc.v:139190$6171 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:129468.5-129468.29" + attribute \src "libresoc.v:139191.5-139191.29" switch \initial - attribute \src "libresoc.v:129468.9-129468.17" + attribute \src "libresoc.v:139191.9-139191.17" case 1'1 case end @@ -207342,14 +223149,14 @@ module \l0$130 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:129477.3-129486.6" - process $proc$libresoc.v:129477$5850 + attribute \src "libresoc.v:139200.3-139209.6" + process $proc$libresoc.v:139200$6172 assign { } { } assign { } { } - assign $0\ldst_port0_is_ld_i$8[0:0]$5851 $1\ldst_port0_is_ld_i$8[0:0]$5852 - attribute \src "libresoc.v:129478.5-129478.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$6173 $1\ldst_port0_is_ld_i$8[0:0]$6174 + attribute \src "libresoc.v:139201.5-139201.29" switch \initial - attribute \src "libresoc.v:129478.9-129478.17" + attribute \src "libresoc.v:139201.9-139201.17" case 1'1 case end @@ -207358,21 +223165,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_ld_i$8[0:0]$5852 \ldst_port0_is_ld_i + assign $1\ldst_port0_is_ld_i$8[0:0]$6174 \ldst_port0_is_ld_i case - assign $1\ldst_port0_is_ld_i$8[0:0]$5852 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$6174 1'0 end sync always - update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$5851 + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6173 end - attribute \src "libresoc.v:129487.3-129496.6" - process $proc$libresoc.v:129487$5853 + attribute \src "libresoc.v:139210.3-139219.6" + process $proc$libresoc.v:139210$6175 assign { } { } assign { } { } - assign $0\ldst_port0_is_st_i$9[0:0]$5854 $1\ldst_port0_is_st_i$9[0:0]$5855 - attribute \src "libresoc.v:129488.5-129488.29" + assign $0\ldst_port0_is_st_i$9[0:0]$6176 $1\ldst_port0_is_st_i$9[0:0]$6177 + attribute \src "libresoc.v:139211.5-139211.29" switch \initial - attribute \src "libresoc.v:129488.9-129488.17" + attribute \src "libresoc.v:139211.9-139211.17" case 1'1 case end @@ -207381,21 +223188,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_st_i$9[0:0]$5855 \ldst_port0_is_st_i + assign $1\ldst_port0_is_st_i$9[0:0]$6177 \ldst_port0_is_st_i case - assign $1\ldst_port0_is_st_i$9[0:0]$5855 1'0 + assign $1\ldst_port0_is_st_i$9[0:0]$6177 1'0 end sync always - update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$5854 + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6176 end - attribute \src "libresoc.v:129497.3-129506.6" - process $proc$libresoc.v:129497$5856 + attribute \src "libresoc.v:139220.3-139229.6" + process $proc$libresoc.v:139220$6178 assign { } { } assign { } { } - assign $0\ldst_port0_data_len$11[3:0]$5857 $1\ldst_port0_data_len$11[3:0]$5858 - attribute \src "libresoc.v:129498.5-129498.29" + assign $0\ldst_port0_data_len$11[3:0]$6179 $1\ldst_port0_data_len$11[3:0]$6180 + attribute \src "libresoc.v:139221.5-139221.29" switch \initial - attribute \src "libresoc.v:129498.9-129498.17" + attribute \src "libresoc.v:139221.9-139221.17" case 1'1 case end @@ -207404,21 +223211,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_data_len$11[3:0]$5858 \ldst_port0_data_len + assign $1\ldst_port0_data_len$11[3:0]$6180 \ldst_port0_data_len case - assign $1\ldst_port0_data_len$11[3:0]$5858 4'0000 + assign $1\ldst_port0_data_len$11[3:0]$6180 4'0000 end sync always - update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$5857 + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6179 end - attribute \src "libresoc.v:129507.3-129516.6" - process $proc$libresoc.v:129507$5859 + attribute \src "libresoc.v:139230.3-139239.6" + process $proc$libresoc.v:139230$6181 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:129508.5-129508.29" + attribute \src "libresoc.v:139231.5-139231.29" switch \initial - attribute \src "libresoc.v:129508.9-129508.17" + attribute \src "libresoc.v:139231.9-139231.17" case 1'1 case end @@ -207434,10 +223241,10 @@ module \l0$130 sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$20 $or$libresoc.v:129281$5801_Y - connect \$24 $ternary$libresoc.v:129282$5802_Y - connect \$26 $not$libresoc.v:129283$5803_Y - connect \$28 $not$libresoc.v:129284$5804_Y + connect \$20 $or$libresoc.v:139004$6123_Y + connect \$24 $ternary$libresoc.v:139005$6124_Y + connect \$26 $not$libresoc.v:139006$6125_Y + connect \$28 $not$libresoc.v:139007$6126_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 @@ -207454,75 +223261,75 @@ module \l0$130 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end -attribute \src "libresoc.v:129536.1-129594.10" +attribute \src "libresoc.v:139259.1-139317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:129537.7-129537.20" + attribute \src "libresoc.v:139260.7-139260.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129582.3-129590.6" - wire $0\q_int$next[0:0]$5874 - attribute \src "libresoc.v:129580.3-129581.27" + attribute \src "libresoc.v:139305.3-139313.6" + wire $0\q_int$next[0:0]$6196 + attribute \src "libresoc.v:139303.3-139304.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:129582.3-129590.6" - wire $1\q_int$next[0:0]$5875 - attribute \src "libresoc.v:129559.7-129559.19" + attribute \src "libresoc.v:139305.3-139313.6" + wire $1\q_int$next[0:0]$6197 + attribute \src "libresoc.v:139282.7-139282.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:129572.17-129572.96" - wire $and$libresoc.v:129572$5864_Y - attribute \src "libresoc.v:129577.17-129577.96" - wire $and$libresoc.v:129577$5869_Y - attribute \src "libresoc.v:129574.18-129574.99" - wire $not$libresoc.v:129574$5866_Y - attribute \src "libresoc.v:129576.17-129576.98" - wire $not$libresoc.v:129576$5868_Y - attribute \src "libresoc.v:129579.17-129579.98" - wire $not$libresoc.v:129579$5871_Y - attribute \src "libresoc.v:129573.18-129573.104" - wire $or$libresoc.v:129573$5865_Y - attribute \src "libresoc.v:129575.18-129575.105" - wire $or$libresoc.v:129575$5867_Y - attribute \src "libresoc.v:129578.17-129578.103" - wire $or$libresoc.v:129578$5870_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:139295.17-139295.96" + wire $and$libresoc.v:139295$6186_Y + attribute \src "libresoc.v:139300.17-139300.96" + wire $and$libresoc.v:139300$6191_Y + attribute \src "libresoc.v:139297.18-139297.99" + wire $not$libresoc.v:139297$6188_Y + attribute \src "libresoc.v:139299.17-139299.98" + wire $not$libresoc.v:139299$6190_Y + attribute \src "libresoc.v:139302.17-139302.98" + wire $not$libresoc.v:139302$6193_Y + attribute \src "libresoc.v:139296.18-139296.104" + wire $or$libresoc.v:139296$6187_Y + attribute \src "libresoc.v:139298.18-139298.105" + wire $or$libresoc.v:139298$6189_Y + attribute \src "libresoc.v:139301.17-139301.103" + wire $or$libresoc.v:139301$6192_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:129537.7-129537.15" + attribute \src "libresoc.v:139260.7-139260.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 2 \r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:129572$5864 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:139295$6186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -207530,10 +223337,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:129572$5864_Y + connect \Y $and$libresoc.v:139295$6186_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:129577$5869 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:139300$6191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -207541,34 +223348,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:129577$5869_Y + connect \Y $and$libresoc.v:139300$6191_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:129574$5866 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:139297$6188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:129574$5866_Y + connect \Y $not$libresoc.v:139297$6188_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:129576$5868 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:139299$6190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:129576$5868_Y + connect \Y $not$libresoc.v:139299$6190_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:129579$5871 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:139302$6193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:129579$5871_Y + connect \Y $not$libresoc.v:139302$6193_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:129573$5865 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:139296$6187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -207576,10 +223383,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:129573$5865_Y + connect \Y $or$libresoc.v:139296$6187_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:129575$5867 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:139298$6189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -207587,10 +223394,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:129575$5867_Y + connect \Y $or$libresoc.v:139298$6189_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:129578$5870 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:139301$6192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -207598,39 +223405,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:129578$5870_Y + connect \Y $or$libresoc.v:139301$6192_Y end - attribute \src "libresoc.v:129537.7-129537.20" - process $proc$libresoc.v:129537$5876 + attribute \src "libresoc.v:139260.7-139260.20" + process $proc$libresoc.v:139260$6198 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129559.7-129559.19" - process $proc$libresoc.v:129559$5877 + attribute \src "libresoc.v:139282.7-139282.19" + process $proc$libresoc.v:139282$6199 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:129580.3-129581.27" - process $proc$libresoc.v:129580$5872 + attribute \src "libresoc.v:139303.3-139304.27" + process $proc$libresoc.v:139303$6194 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:129582.3-129590.6" - process $proc$libresoc.v:129582$5873 + attribute \src "libresoc.v:139305.3-139313.6" + process $proc$libresoc.v:139305$6195 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5874 $1\q_int$next[0:0]$5875 - attribute \src "libresoc.v:129583.5-129583.29" + assign $0\q_int$next[0:0]$6196 $1\q_int$next[0:0]$6197 + attribute \src "libresoc.v:139306.5-139306.29" switch \initial - attribute \src "libresoc.v:129583.9-129583.17" + attribute \src "libresoc.v:139306.9-139306.17" case 1'1 case end @@ -207639,572 +223446,572 @@ module \ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5875 1'0 + assign $1\q_int$next[0:0]$6197 1'0 case - assign $1\q_int$next[0:0]$5875 \$5 + assign $1\q_int$next[0:0]$6197 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5874 + update \q_int$next $0\q_int$next[0:0]$6196 end - connect \$9 $and$libresoc.v:129572$5864_Y - connect \$11 $or$libresoc.v:129573$5865_Y - connect \$13 $not$libresoc.v:129574$5866_Y - connect \$15 $or$libresoc.v:129575$5867_Y - connect \$1 $not$libresoc.v:129576$5868_Y - connect \$3 $and$libresoc.v:129577$5869_Y - connect \$5 $or$libresoc.v:129578$5870_Y - connect \$7 $not$libresoc.v:129579$5871_Y + connect \$9 $and$libresoc.v:139295$6186_Y + connect \$11 $or$libresoc.v:139296$6187_Y + connect \$13 $not$libresoc.v:139297$6188_Y + connect \$15 $or$libresoc.v:139298$6189_Y + connect \$1 $not$libresoc.v:139299$6190_Y + connect \$3 $and$libresoc.v:139300$6191_Y + connect \$5 $or$libresoc.v:139301$6192_Y + connect \$7 $not$libresoc.v:139302$6193_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:129598.1-130955.10" +attribute \src "libresoc.v:139321.1-140684.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:130610.3-130618.6" - wire $0\adr_l_r_adr$next[0:0]$6020 - attribute \src "libresoc.v:130492.3-130493.39" + attribute \src "libresoc.v:140339.3-140347.6" + wire $0\adr_l_r_adr$next[0:0]$6342 + attribute \src "libresoc.v:140221.3-140222.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:130438.3-130439.21" + attribute \src "libresoc.v:140167.3-140168.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:130775.3-130784.6" + attribute \src "libresoc.v:140504.3-140513.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:130785.3-130794.6" + attribute \src "libresoc.v:140514.3-140523.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:130765.3-130774.6" - wire width 64 $0\ea_r$next[63:0]$6108 - attribute \src "libresoc.v:130440.3-130441.25" + attribute \src "libresoc.v:140494.3-140503.6" + wire width 64 $0\ea_r$next[63:0]$6430 + attribute \src "libresoc.v:140169.3-140170.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:129599.7-129599.20" + attribute \src "libresoc.v:139322.7-139322.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130840.3-130859.6" + attribute \src "libresoc.v:140569.3-140588.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:130804.3-130827.6" + attribute \src "libresoc.v:140533.3-140556.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:130707.3-130716.6" - wire width 64 $0\ldo_r$next[63:0]$6093 - attribute \src "libresoc.v:130448.3-130449.27" + attribute \src "libresoc.v:140436.3-140445.6" + wire width 64 $0\ldo_r$next[63:0]$6415 + attribute \src "libresoc.v:140177.3-140178.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:130436.3-130437.33" + attribute \src "libresoc.v:140165.3-140166.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:130795.3-130803.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$6113 - attribute \src "libresoc.v:130434.3-130435.57" + attribute \src "libresoc.v:140524.3-140532.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6435 + attribute \src "libresoc.v:140163.3-140164.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:130884.3-130895.6" + attribute \src "libresoc.v:140613.3-140624.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:130655.3-130663.6" - wire $0\lsd_l_r_lsd$next[0:0]$6035 - attribute \src "libresoc.v:130482.3-130483.39" + attribute \src "libresoc.v:140384.3-140392.6" + wire $0\lsd_l_r_lsd$next[0:0]$6357 + attribute \src "libresoc.v:140211.3-140212.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:130583.3-130591.6" - wire $0\opc_l_r_opc$next[0:0]$6011 - attribute \src "libresoc.v:130498.3-130499.39" + attribute \src "libresoc.v:140312.3-140320.6" + wire $0\opc_l_r_opc$next[0:0]$6333 + attribute \src "libresoc.v:140227.3-140228.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130574.3-130582.6" - wire $0\opc_l_s_opc$next[0:0]$6008 - attribute \src "libresoc.v:130500.3-130501.39" + attribute \src "libresoc.v:140303.3-140311.6" + wire $0\opc_l_s_opc$next[0:0]$6330 + attribute \src "libresoc.v:140229.3-140230.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__byte_reverse$next[0:0]$6038 - attribute \src "libresoc.v:130474.3-130475.57" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__byte_reverse$next[0:0]$6360 + attribute \src "libresoc.v:140203.3-140204.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 4 $0\oper_r__data_len$next[3:0]$6039 - attribute \src "libresoc.v:130472.3-130473.49" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6361 + attribute \src "libresoc.v:140201.3-140202.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 12 $0\oper_r__fn_unit$next[11:0]$6040 - attribute \src "libresoc.v:130452.3-130453.47" - wire width 12 $0\oper_r__fn_unit[11:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$6041 - attribute \src "libresoc.v:130454.3-130455.61" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 14 $0\oper_r__fn_unit$next[13:0]$6362 + attribute \src "libresoc.v:140181.3-140182.47" + wire width 14 $0\oper_r__fn_unit[13:0] + attribute \src "libresoc.v:140393.3-140435.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6363 + attribute \src "libresoc.v:140183.3-140184.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__imm_data__ok$next[0:0]$6042 - attribute \src "libresoc.v:130456.3-130457.57" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6364 + attribute \src "libresoc.v:140185.3-140186.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 32 $0\oper_r__insn$next[31:0]$6043 - attribute \src "libresoc.v:130480.3-130481.41" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 32 $0\oper_r__insn$next[31:0]$6365 + attribute \src "libresoc.v:140209.3-140210.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$6044 - attribute \src "libresoc.v:130450.3-130451.51" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6366 + attribute \src "libresoc.v:140179.3-140180.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__is_32bit$next[0:0]$6045 - attribute \src "libresoc.v:130468.3-130469.49" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__is_32bit$next[0:0]$6367 + attribute \src "libresoc.v:140197.3-140198.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__is_signed$next[0:0]$6046 - attribute \src "libresoc.v:130470.3-130471.51" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__is_signed$next[0:0]$6368 + attribute \src "libresoc.v:140199.3-140200.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$6047 - attribute \src "libresoc.v:130478.3-130479.51" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6369 + attribute \src "libresoc.v:140207.3-140208.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__oe__oe$next[0:0]$6048 - attribute \src "libresoc.v:130464.3-130465.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__oe__oe$next[0:0]$6370 + attribute \src "libresoc.v:140193.3-140194.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__oe__ok$next[0:0]$6049 - attribute \src "libresoc.v:130466.3-130467.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__oe__ok$next[0:0]$6371 + attribute \src "libresoc.v:140195.3-140196.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__rc__ok$next[0:0]$6050 - attribute \src "libresoc.v:130462.3-130463.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__rc__ok$next[0:0]$6372 + attribute \src "libresoc.v:140191.3-140192.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__rc__rc$next[0:0]$6051 - attribute \src "libresoc.v:130460.3-130461.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__rc__rc$next[0:0]$6373 + attribute \src "libresoc.v:140189.3-140190.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__sign_extend$next[0:0]$6052 - attribute \src "libresoc.v:130476.3-130477.55" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__sign_extend$next[0:0]$6374 + attribute \src "libresoc.v:140205.3-140206.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $0\oper_r__zero_a$next[0:0]$6053 - attribute \src "libresoc.v:130458.3-130459.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__zero_a$next[0:0]$6375 + attribute \src "libresoc.v:140187.3-140188.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:130502.3-130503.28" + attribute \src "libresoc.v:140231.3-140232.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:130828.3-130839.6" + attribute \src "libresoc.v:140557.3-140568.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:130601.3-130609.6" - wire width 3 $0\src_l_r_src$next[2:0]$6017 - attribute \src "libresoc.v:130494.3-130495.39" + attribute \src "libresoc.v:140330.3-140338.6" + wire width 3 $0\src_l_r_src$next[2:0]$6339 + attribute \src "libresoc.v:140223.3-140224.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:130592.3-130600.6" - wire width 3 $0\src_l_s_src$next[2:0]$6014 - attribute \src "libresoc.v:130496.3-130497.39" + attribute \src "libresoc.v:140321.3-140329.6" + wire width 3 $0\src_l_s_src$next[2:0]$6336 + attribute \src "libresoc.v:140225.3-140226.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:130717.3-130732.6" - wire width 64 $0\src_r0$next[63:0]$6096 - attribute \src "libresoc.v:130446.3-130447.29" + attribute \src "libresoc.v:140446.3-140461.6" + wire width 64 $0\src_r0$next[63:0]$6418 + attribute \src "libresoc.v:140175.3-140176.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:130733.3-130748.6" - wire width 64 $0\src_r1$next[63:0]$6100 - attribute \src "libresoc.v:130444.3-130445.29" + attribute \src "libresoc.v:140462.3-140477.6" + wire width 64 $0\src_r1$next[63:0]$6422 + attribute \src "libresoc.v:140173.3-140174.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:130749.3-130764.6" - wire width 64 $0\src_r2$next[63:0]$6104 - attribute \src "libresoc.v:130442.3-130443.29" + attribute \src "libresoc.v:140478.3-140493.6" + wire width 64 $0\src_r2$next[63:0]$6426 + attribute \src "libresoc.v:140171.3-140172.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:130860.3-130883.6" + attribute \src "libresoc.v:140589.3-140612.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:130646.3-130654.6" - wire $0\sto_l_r_sto$next[0:0]$6032 - attribute \src "libresoc.v:130484.3-130485.39" + attribute \src "libresoc.v:140375.3-140383.6" + wire $0\sto_l_r_sto$next[0:0]$6354 + attribute \src "libresoc.v:140213.3-140214.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:130637.3-130645.6" - wire $0\upd_l_r_upd$next[0:0]$6029 - attribute \src "libresoc.v:130486.3-130487.39" + attribute \src "libresoc.v:140366.3-140374.6" + wire $0\upd_l_r_upd$next[0:0]$6351 + attribute \src "libresoc.v:140215.3-140216.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:130628.3-130636.6" - wire $0\upd_l_s_upd$next[0:0]$6026 - attribute \src "libresoc.v:130488.3-130489.39" + attribute \src "libresoc.v:140357.3-140365.6" + wire $0\upd_l_s_upd$next[0:0]$6348 + attribute \src "libresoc.v:140217.3-140218.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:130619.3-130627.6" - wire $0\wri_l_r_wri$next[0:0]$6023 - attribute \src "libresoc.v:130490.3-130491.39" + attribute \src "libresoc.v:140348.3-140356.6" + wire $0\wri_l_r_wri$next[0:0]$6345 + attribute \src "libresoc.v:140219.3-140220.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:130610.3-130618.6" - wire $1\adr_l_r_adr$next[0:0]$6021 - attribute \src "libresoc.v:129795.7-129795.25" + attribute \src "libresoc.v:140339.3-140347.6" + wire $1\adr_l_r_adr$next[0:0]$6343 + attribute \src "libresoc.v:139518.7-139518.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:129809.7-129809.20" + attribute \src "libresoc.v:139532.7-139532.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:130775.3-130784.6" + attribute \src "libresoc.v:140504.3-140513.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:130785.3-130794.6" + attribute \src "libresoc.v:140514.3-140523.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:130765.3-130774.6" - wire width 64 $1\ea_r$next[63:0]$6109 - attribute \src "libresoc.v:129855.14-129855.41" + attribute \src "libresoc.v:140494.3-140503.6" + wire width 64 $1\ea_r$next[63:0]$6431 + attribute \src "libresoc.v:139578.14-139578.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:130840.3-130859.6" + attribute \src "libresoc.v:140569.3-140588.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:130804.3-130827.6" + attribute \src "libresoc.v:140533.3-140556.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:130707.3-130716.6" - wire width 64 $1\ldo_r$next[63:0]$6094 - attribute \src "libresoc.v:129885.14-129885.42" + attribute \src "libresoc.v:140436.3-140445.6" + wire width 64 $1\ldo_r$next[63:0]$6416 + attribute \src "libresoc.v:139608.14-139608.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:129890.14-129890.62" + attribute \src "libresoc.v:139613.14-139613.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:130795.3-130803.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$6114 - attribute \src "libresoc.v:129895.7-129895.34" + attribute \src "libresoc.v:140524.3-140532.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6436 + attribute \src "libresoc.v:139618.7-139618.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:130884.3-130895.6" + attribute \src "libresoc.v:140613.3-140624.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:130655.3-130663.6" - wire $1\lsd_l_r_lsd$next[0:0]$6036 - attribute \src "libresoc.v:129944.7-129944.25" + attribute \src "libresoc.v:140384.3-140392.6" + wire $1\lsd_l_r_lsd$next[0:0]$6358 + attribute \src "libresoc.v:139667.7-139667.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:130583.3-130591.6" - wire $1\opc_l_r_opc$next[0:0]$6012 - attribute \src "libresoc.v:129958.7-129958.25" + attribute \src "libresoc.v:140312.3-140320.6" + wire $1\opc_l_r_opc$next[0:0]$6334 + attribute \src "libresoc.v:139681.7-139681.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130574.3-130582.6" - wire $1\opc_l_s_opc$next[0:0]$6009 - attribute \src "libresoc.v:129962.7-129962.25" + attribute \src "libresoc.v:140303.3-140311.6" + wire $1\opc_l_s_opc$next[0:0]$6331 + attribute \src "libresoc.v:139685.7-139685.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__byte_reverse$next[0:0]$6054 - attribute \src "libresoc.v:130090.7-130090.34" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__byte_reverse$next[0:0]$6376 + attribute \src "libresoc.v:139816.7-139816.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 4 $1\oper_r__data_len$next[3:0]$6055 - attribute \src "libresoc.v:130094.13-130094.36" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6377 + attribute \src "libresoc.v:139820.13-139820.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 12 $1\oper_r__fn_unit$next[11:0]$6056 - attribute \src "libresoc.v:130111.14-130111.39" - wire width 12 $1\oper_r__fn_unit[11:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$6057 - attribute \src "libresoc.v:130115.14-130115.59" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 14 $1\oper_r__fn_unit$next[13:0]$6378 + attribute \src "libresoc.v:139839.14-139839.40" + wire width 14 $1\oper_r__fn_unit[13:0] + attribute \src "libresoc.v:140393.3-140435.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6379 + attribute \src "libresoc.v:139843.14-139843.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__imm_data__ok$next[0:0]$6058 - attribute \src "libresoc.v:130119.7-130119.34" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6380 + attribute \src "libresoc.v:139847.7-139847.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 32 $1\oper_r__insn$next[31:0]$6059 - attribute \src "libresoc.v:130123.14-130123.34" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 32 $1\oper_r__insn$next[31:0]$6381 + attribute \src "libresoc.v:139851.14-139851.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$6060 - attribute \src "libresoc.v:130201.13-130201.38" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6382 + attribute \src "libresoc.v:139930.13-139930.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__is_32bit$next[0:0]$6061 - attribute \src "libresoc.v:130205.7-130205.30" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__is_32bit$next[0:0]$6383 + attribute \src "libresoc.v:139934.7-139934.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__is_signed$next[0:0]$6062 - attribute \src "libresoc.v:130209.7-130209.31" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__is_signed$next[0:0]$6384 + attribute \src "libresoc.v:139938.7-139938.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$6063 - attribute \src "libresoc.v:130218.13-130218.37" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6385 + attribute \src "libresoc.v:139947.13-139947.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__oe__oe$next[0:0]$6064 - attribute \src "libresoc.v:130222.7-130222.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__oe__oe$next[0:0]$6386 + attribute \src "libresoc.v:139951.7-139951.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__oe__ok$next[0:0]$6065 - attribute \src "libresoc.v:130226.7-130226.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__oe__ok$next[0:0]$6387 + attribute \src "libresoc.v:139955.7-139955.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__rc__ok$next[0:0]$6066 - attribute \src "libresoc.v:130230.7-130230.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__rc__ok$next[0:0]$6388 + attribute \src "libresoc.v:139959.7-139959.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__rc__rc$next[0:0]$6067 - attribute \src "libresoc.v:130234.7-130234.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__rc__rc$next[0:0]$6389 + attribute \src "libresoc.v:139963.7-139963.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__sign_extend$next[0:0]$6068 - attribute \src "libresoc.v:130238.7-130238.33" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__sign_extend$next[0:0]$6390 + attribute \src "libresoc.v:139967.7-139967.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $1\oper_r__zero_a$next[0:0]$6069 - attribute \src "libresoc.v:130242.7-130242.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__zero_a$next[0:0]$6391 + attribute \src "libresoc.v:139971.7-139971.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:130246.7-130246.21" + attribute \src "libresoc.v:139975.7-139975.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:130828.3-130839.6" + attribute \src "libresoc.v:140557.3-140568.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:130601.3-130609.6" - wire width 3 $1\src_l_r_src$next[2:0]$6018 - attribute \src "libresoc.v:130288.13-130288.31" + attribute \src "libresoc.v:140330.3-140338.6" + wire width 3 $1\src_l_r_src$next[2:0]$6340 + attribute \src "libresoc.v:140017.13-140017.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:130592.3-130600.6" - wire width 3 $1\src_l_s_src$next[2:0]$6015 - attribute \src "libresoc.v:130292.13-130292.31" + attribute \src "libresoc.v:140321.3-140329.6" + wire width 3 $1\src_l_s_src$next[2:0]$6337 + attribute \src "libresoc.v:140021.13-140021.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:130717.3-130732.6" - wire width 64 $1\src_r0$next[63:0]$6097 - attribute \src "libresoc.v:130296.14-130296.43" + attribute \src "libresoc.v:140446.3-140461.6" + wire width 64 $1\src_r0$next[63:0]$6419 + attribute \src "libresoc.v:140025.14-140025.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:130733.3-130748.6" - wire width 64 $1\src_r1$next[63:0]$6101 - attribute \src "libresoc.v:130300.14-130300.43" + attribute \src "libresoc.v:140462.3-140477.6" + wire width 64 $1\src_r1$next[63:0]$6423 + attribute \src "libresoc.v:140029.14-140029.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:130749.3-130764.6" - wire width 64 $1\src_r2$next[63:0]$6105 - attribute \src "libresoc.v:130304.14-130304.43" + attribute \src "libresoc.v:140478.3-140493.6" + wire width 64 $1\src_r2$next[63:0]$6427 + attribute \src "libresoc.v:140033.14-140033.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:130860.3-130883.6" + attribute \src "libresoc.v:140589.3-140612.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:130646.3-130654.6" - wire $1\sto_l_r_sto$next[0:0]$6033 - attribute \src "libresoc.v:130314.7-130314.25" + attribute \src "libresoc.v:140375.3-140383.6" + wire $1\sto_l_r_sto$next[0:0]$6355 + attribute \src "libresoc.v:140043.7-140043.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:130637.3-130645.6" - wire $1\upd_l_r_upd$next[0:0]$6030 - attribute \src "libresoc.v:130324.7-130324.25" + attribute \src "libresoc.v:140366.3-140374.6" + wire $1\upd_l_r_upd$next[0:0]$6352 + attribute \src "libresoc.v:140053.7-140053.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:130628.3-130636.6" - wire $1\upd_l_s_upd$next[0:0]$6027 - attribute \src "libresoc.v:130328.7-130328.25" + attribute \src "libresoc.v:140357.3-140365.6" + wire $1\upd_l_s_upd$next[0:0]$6349 + attribute \src "libresoc.v:140057.7-140057.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:130619.3-130627.6" - wire $1\wri_l_r_wri$next[0:0]$6024 - attribute \src "libresoc.v:130338.7-130338.25" + attribute \src "libresoc.v:140348.3-140356.6" + wire $1\wri_l_r_wri$next[0:0]$6346 + attribute \src "libresoc.v:140067.7-140067.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:130840.3-130859.6" + attribute \src "libresoc.v:140569.3-140588.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:130804.3-130827.6" + attribute \src "libresoc.v:140533.3-140556.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__byte_reverse$next[0:0]$6070 - attribute \src "libresoc.v:130664.3-130706.6" - wire width 4 $2\oper_r__data_len$next[3:0]$6071 - attribute \src "libresoc.v:130664.3-130706.6" - wire width 12 $2\oper_r__fn_unit$next[11:0]$6072 - attribute \src "libresoc.v:130664.3-130706.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$6073 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__imm_data__ok$next[0:0]$6074 - attribute \src "libresoc.v:130664.3-130706.6" - wire width 32 $2\oper_r__insn$next[31:0]$6075 - attribute \src "libresoc.v:130664.3-130706.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$6076 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__is_32bit$next[0:0]$6077 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__is_signed$next[0:0]$6078 - attribute \src "libresoc.v:130664.3-130706.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$6079 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__oe__oe$next[0:0]$6080 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__oe__ok$next[0:0]$6081 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__rc__ok$next[0:0]$6082 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__rc__rc$next[0:0]$6083 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__sign_extend$next[0:0]$6084 - attribute \src "libresoc.v:130664.3-130706.6" - wire $2\oper_r__zero_a$next[0:0]$6085 - attribute \src "libresoc.v:130717.3-130732.6" - wire width 64 $2\src_r0$next[63:0]$6098 - attribute \src "libresoc.v:130733.3-130748.6" - wire width 64 $2\src_r1$next[63:0]$6102 - attribute \src "libresoc.v:130749.3-130764.6" - wire width 64 $2\src_r2$next[63:0]$6106 - attribute \src "libresoc.v:130860.3-130883.6" + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__byte_reverse$next[0:0]$6392 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6393 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 14 $2\oper_r__fn_unit$next[13:0]$6394 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6395 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6396 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 32 $2\oper_r__insn$next[31:0]$6397 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6398 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__is_32bit$next[0:0]$6399 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__is_signed$next[0:0]$6400 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6401 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__oe__oe$next[0:0]$6402 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__oe__ok$next[0:0]$6403 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__rc__ok$next[0:0]$6404 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__rc__rc$next[0:0]$6405 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__sign_extend$next[0:0]$6406 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__zero_a$next[0:0]$6407 + attribute \src "libresoc.v:140446.3-140461.6" + wire width 64 $2\src_r0$next[63:0]$6420 + attribute \src "libresoc.v:140462.3-140477.6" + wire width 64 $2\src_r1$next[63:0]$6424 + attribute \src "libresoc.v:140478.3-140493.6" + wire width 64 $2\src_r2$next[63:0]$6428 + attribute \src "libresoc.v:140589.3-140612.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:130664.3-130706.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$6086 - attribute \src "libresoc.v:130664.3-130706.6" - wire $3\oper_r__imm_data__ok$next[0:0]$6087 - attribute \src "libresoc.v:130664.3-130706.6" - wire $3\oper_r__oe__oe$next[0:0]$6088 - attribute \src "libresoc.v:130664.3-130706.6" - wire $3\oper_r__oe__ok$next[0:0]$6089 - attribute \src "libresoc.v:130664.3-130706.6" - wire $3\oper_r__rc__ok$next[0:0]$6090 - attribute \src "libresoc.v:130664.3-130706.6" - wire $3\oper_r__rc__rc$next[0:0]$6091 - attribute \src "libresoc.v:130420.18-130420.124" - wire width 65 $add$libresoc.v:130420$5958_Y - attribute \src "libresoc.v:130343.19-130343.118" - wire $and$libresoc.v:130343$5878_Y - attribute \src "libresoc.v:130344.19-130344.125" - wire $and$libresoc.v:130344$5879_Y - attribute \src "libresoc.v:130345.19-130345.120" - wire $and$libresoc.v:130345$5880_Y - attribute \src "libresoc.v:130346.19-130346.125" - wire $and$libresoc.v:130346$5881_Y - attribute \src "libresoc.v:130347.19-130347.118" - wire $and$libresoc.v:130347$5882_Y - attribute \src "libresoc.v:130349.19-130349.119" - wire $and$libresoc.v:130349$5884_Y - attribute \src "libresoc.v:130350.19-130350.123" - wire $and$libresoc.v:130350$5885_Y - attribute \src "libresoc.v:130351.19-130351.123" - wire $and$libresoc.v:130351$5886_Y - attribute \src "libresoc.v:130352.19-130352.120" - wire $and$libresoc.v:130352$5887_Y - attribute \src "libresoc.v:130353.19-130353.123" - wire $and$libresoc.v:130353$5888_Y - attribute \src "libresoc.v:130354.19-130354.119" - wire $and$libresoc.v:130354$5889_Y - attribute \src "libresoc.v:130355.19-130355.123" - wire $and$libresoc.v:130355$5890_Y - attribute \src "libresoc.v:130356.19-130356.125" - wire $and$libresoc.v:130356$5891_Y - attribute \src "libresoc.v:130358.19-130358.116" - wire $and$libresoc.v:130358$5893_Y - attribute \src "libresoc.v:130360.19-130360.120" - wire $and$libresoc.v:130360$5895_Y - attribute \src "libresoc.v:130361.19-130361.123" - wire $and$libresoc.v:130361$5896_Y - attribute \src "libresoc.v:130365.19-130365.125" - wire $and$libresoc.v:130365$5900_Y - attribute \src "libresoc.v:130366.19-130366.123" - wire $and$libresoc.v:130366$5901_Y - attribute \src "libresoc.v:130371.19-130371.116" - wire $and$libresoc.v:130371$5906_Y - attribute \src "libresoc.v:130373.19-130373.116" - wire $and$libresoc.v:130373$5908_Y - attribute \src "libresoc.v:130376.19-130376.118" - wire $and$libresoc.v:130376$5911_Y - attribute \src "libresoc.v:130378.19-130378.125" - wire $and$libresoc.v:130378$5913_Y - attribute \src "libresoc.v:130381.19-130381.160" - wire width 3 $and$libresoc.v:130381$5916_Y - attribute \src "libresoc.v:130382.19-130382.122" - wire $and$libresoc.v:130382$5917_Y - attribute \src "libresoc.v:130383.19-130383.122" - wire $and$libresoc.v:130383$5918_Y - attribute \src "libresoc.v:130385.19-130385.122" - wire $and$libresoc.v:130385$5921_Y - attribute \src "libresoc.v:130397.18-130397.123" - wire $and$libresoc.v:130397$5935_Y - attribute \src "libresoc.v:130398.18-130398.123" - wire $and$libresoc.v:130398$5936_Y - attribute \src "libresoc.v:130400.18-130400.114" - wire $and$libresoc.v:130400$5938_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" @@ -208295,19 +224102,19 @@ module \ldst0 wire \$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" wire width 3 \$18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$186 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" wire \$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" wire \$20 @@ -208355,9 +224162,9 @@ module \ldst0 wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" wire width 64 \$69 @@ -208397,19 +224204,19 @@ module \ldst0 wire \addr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" wire width 64 \addr_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \adr_l_q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \adr_l_r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \adr_l_r_adr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \adr_l_s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" wire width 64 \alu_o @@ -208419,9 +224226,9 @@ module \ldst0 wire \alu_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i @@ -208459,9 +224266,9 @@ module \ldst0 wire width 64 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 33 \ea - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ea_r$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal @@ -208479,7 +224286,7 @@ module \ldst0 wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 - attribute \src "libresoc.v:129599.7-129599.15" + attribute \src "libresoc.v:139322.7-139322.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o @@ -208489,11 +224296,11 @@ module \ldst0 wire width 64 \ldd_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" wire width 64 \ldd_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" wire width 64 \lddata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ldo_r$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 output 38 \ldst_port0_addr_i @@ -208539,19 +224346,19 @@ module \ldst0 wire output 52 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" wire \load_mem_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \lod_l_qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \lod_l_r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \lod_l_s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \lsd_l_q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \lsd_l_r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \lsd_l_r_lsd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \lsd_l_s_lsd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 32 \o @@ -208559,35 +224366,37 @@ module \ldst0 wire \op_is_ld attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" wire \op_is_st - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \oper_i_ldst_ldst0__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 7 \oper_i_ldst_ldst0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -208668,6 +224477,7 @@ module \ldst0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -208702,22 +224512,24 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \oper_r__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \oper_r__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \oper_r__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \oper_r__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -208804,6 +224616,7 @@ module \ldst0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \oper_r__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -208873,11 +224686,11 @@ module \ldst0 wire \reset_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" wire width 64 \revnorev - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rst_l_q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 27 \src1_i @@ -208889,15 +224702,15 @@ module \ldst0 wire width 64 \src2_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 29 \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r0 @@ -208913,42 +224726,42 @@ module \ldst0 wire width 64 \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" wire \st_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" wire width 64 \stdata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \sto_l_q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \sto_l_r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \sto_l_r_sto$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \sto_l_s_sto attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:115" wire \stwd_mem_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \upd_l_q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \upd_l_r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \upd_l_r_upd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \upd_l_s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \upd_l_s_upd$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" wire \wr_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \wri_l_q_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \wri_l_r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \wri_l_r_wri$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:130420$5958 + cell $add $add$libresoc.v:140149$6280 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -208956,10 +224769,10 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:130420$5958_Y + connect \Y $add$libresoc.v:140149$6280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:130343$5878 + cell $and $and$libresoc.v:140072$6200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208967,10 +224780,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 - connect \Y $and$libresoc.v:130343$5878_Y + connect \Y $and$libresoc.v:140072$6200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:130344$5879 + cell $and $and$libresoc.v:140073$6201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208978,10 +224791,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:130344$5879_Y + connect \Y $and$libresoc.v:140073$6201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:130345$5880 + cell $and $and$libresoc.v:140074$6202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208989,10 +224802,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o - connect \Y $and$libresoc.v:130345$5880_Y + connect \Y $and$libresoc.v:140074$6202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:130346$5881 + cell $and $and$libresoc.v:140075$6203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209000,10 +224813,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:130346$5881_Y + connect \Y $and$libresoc.v:140075$6203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:130347$5882 + cell $and $and$libresoc.v:140076$6204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209011,10 +224824,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:130347$5882_Y + connect \Y $and$libresoc.v:140076$6204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:130349$5884 + cell $and $and$libresoc.v:140078$6206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209022,10 +224835,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:130349$5884_Y + connect \Y $and$libresoc.v:140078$6206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:130350$5885 + cell $and $and$libresoc.v:140079$6207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209033,10 +224846,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130350$5885_Y + connect \Y $and$libresoc.v:140079$6207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:130351$5886 + cell $and $and$libresoc.v:140080$6208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209044,10 +224857,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:130351$5886_Y + connect \Y $and$libresoc.v:140080$6208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:130352$5887 + cell $and $and$libresoc.v:140081$6209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209055,10 +224868,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:130352$5887_Y + connect \Y $and$libresoc.v:140081$6209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:130353$5888 + cell $and $and$libresoc.v:140082$6210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209066,10 +224879,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:130353$5888_Y + connect \Y $and$libresoc.v:140082$6210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:130354$5889 + cell $and $and$libresoc.v:140083$6211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209077,10 +224890,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:130354$5889_Y + connect \Y $and$libresoc.v:140083$6211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:130355$5890 + cell $and $and$libresoc.v:140084$6212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209088,10 +224901,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130355$5890_Y + connect \Y $and$libresoc.v:140084$6212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:130356$5891 + cell $and $and$libresoc.v:140085$6213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209099,10 +224912,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:130356$5891_Y + connect \Y $and$libresoc.v:140085$6213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:130358$5893 + cell $and $and$libresoc.v:140087$6215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209110,10 +224923,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:130358$5893_Y + connect \Y $and$libresoc.v:140087$6215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:130360$5895 + cell $and $and$libresoc.v:140089$6217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209121,10 +224934,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:130360$5895_Y + connect \Y $and$libresoc.v:140089$6217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:130361$5896 + cell $and $and$libresoc.v:140090$6218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209132,10 +224945,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130361$5896_Y + connect \Y $and$libresoc.v:140090$6218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:130365$5900 + cell $and $and$libresoc.v:140094$6222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209143,10 +224956,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:130365$5900_Y + connect \Y $and$libresoc.v:140094$6222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:130366$5901 + cell $and $and$libresoc.v:140095$6223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209154,10 +224967,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130366$5901_Y + connect \Y $and$libresoc.v:140095$6223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:130371$5906 + cell $and $and$libresoc.v:140100$6228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209165,10 +224978,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 - connect \Y $and$libresoc.v:130371$5906_Y + connect \Y $and$libresoc.v:140100$6228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:130373$5908 + cell $and $and$libresoc.v:140102$6230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209176,10 +224989,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 - connect \Y $and$libresoc.v:130373$5908_Y + connect \Y $and$libresoc.v:140102$6230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:130376$5911 + cell $and $and$libresoc.v:140105$6233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209187,10 +225000,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 - connect \Y $and$libresoc.v:130376$5911_Y + connect \Y $and$libresoc.v:140105$6233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:130378$5913 + cell $and $and$libresoc.v:140107$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209198,10 +225011,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:130378$5913_Y + connect \Y $and$libresoc.v:140107$6235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:130381$5916 + cell $and $and$libresoc.v:140110$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209209,10 +225022,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:130381$5916_Y + connect \Y $and$libresoc.v:140110$6238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:130382$5917 + cell $and $and$libresoc.v:140111$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209220,10 +225033,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:130382$5917_Y + connect \Y $and$libresoc.v:140111$6239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:130383$5918 + cell $and $and$libresoc.v:140112$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209231,10 +225044,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:130383$5918_Y + connect \Y $and$libresoc.v:140112$6240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - cell $and $and$libresoc.v:130385$5921 + cell $and $and$libresoc.v:140114$6243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209242,10 +225055,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:130385$5921_Y + connect \Y $and$libresoc.v:140114$6243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:130397$5935 + cell $and $and$libresoc.v:140126$6257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209253,10 +225066,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:130397$5935_Y + connect \Y $and$libresoc.v:140126$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:130398$5936 + cell $and $and$libresoc.v:140127$6258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209264,10 +225077,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:130398$5936_Y + connect \Y $and$libresoc.v:140127$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:130400$5938 + cell $and $and$libresoc.v:140129$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209275,10 +225088,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 - connect \Y $and$libresoc.v:130400$5938_Y + connect \Y $and$libresoc.v:140129$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:130402$5940 + cell $and $and$libresoc.v:140131$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209286,10 +225099,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $and$libresoc.v:130402$5940_Y + connect \Y $and$libresoc.v:140131$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:130405$5943 + cell $and $and$libresoc.v:140134$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209297,10 +225110,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:130405$5943_Y + connect \Y $and$libresoc.v:140134$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:130409$5947 + cell $and $and$libresoc.v:140138$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209308,10 +225121,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 - connect \Y $and$libresoc.v:130409$5947_Y + connect \Y $and$libresoc.v:140138$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:130412$5950 + cell $and $and$libresoc.v:140141$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209319,10 +225132,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:130412$5950_Y + connect \Y $and$libresoc.v:140141$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:130421$5959 + cell $and $and$libresoc.v:140150$6281 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209330,10 +225143,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:130421$5959_Y + connect \Y $and$libresoc.v:140150$6281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:130423$5961 + cell $and $and$libresoc.v:140152$6283 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209341,10 +225154,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:130423$5961_Y + connect \Y $and$libresoc.v:140152$6283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:130425$5963 + cell $and $and$libresoc.v:140154$6285 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209352,10 +225165,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 - connect \Y $and$libresoc.v:130425$5963_Y + connect \Y $and$libresoc.v:140154$6285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:130426$5964 + cell $and $and$libresoc.v:140155$6286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209363,10 +225176,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130426$5964_Y + connect \Y $and$libresoc.v:140155$6286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:130427$5965 + cell $and $and$libresoc.v:140156$6287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209374,10 +225187,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:130427$5965_Y + connect \Y $and$libresoc.v:140156$6287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:130432$5970 + cell $and $and$libresoc.v:140161$6292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209385,10 +225198,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 - connect \Y $and$libresoc.v:130432$5970_Y + connect \Y $and$libresoc.v:140161$6292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:130357$5892 + cell $eq $eq$libresoc.v:140086$6214 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209396,10 +225209,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:130357$5892_Y + connect \Y $eq$libresoc.v:140086$6214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:130377$5912 + cell $eq $eq$libresoc.v:140106$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209407,10 +225220,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:130377$5912_Y + connect \Y $eq$libresoc.v:140106$6234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:130379$5914 + cell $eq $eq$libresoc.v:140108$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209418,10 +225231,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:130379$5914_Y + connect \Y $eq$libresoc.v:140108$6236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:130390$5927 + cell $eq $eq$libresoc.v:140119$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -209429,10 +225242,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:130390$5927_Y + connect \Y $eq$libresoc.v:140119$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:130395$5933 + cell $eq $eq$libresoc.v:140124$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -209440,10 +225253,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $eq$libresoc.v:130395$5933_Y + connect \Y $eq$libresoc.v:140124$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:130396$5934 + cell $eq $eq$libresoc.v:140125$6256 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -209451,10 +225264,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $eq$libresoc.v:130396$5934_Y + connect \Y $eq$libresoc.v:140125$6256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:130404$5942 + cell $eq $eq$libresoc.v:140133$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209462,10 +225275,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:130404$5942_Y + connect \Y $eq$libresoc.v:140133$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:130408$5946 + cell $eq $eq$libresoc.v:140137$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209473,114 +225286,114 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:130408$5946_Y + connect \Y $eq$libresoc.v:140137$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:130384$5919 + cell $pos $extend$libresoc.v:140113$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:130384$5919_Y + connect \Y $extend$libresoc.v:140113$6241_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $extend$libresoc.v:130386$5922 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $extend$libresoc.v:140115$6244 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:130386$5922_Y + connect \Y $extend$libresoc.v:140115$6244_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $extend$libresoc.v:130391$5928 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $extend$libresoc.v:140120$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:130391$5928_Y + connect \Y $extend$libresoc.v:140120$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:130369$5904 + cell $not $not$libresoc.v:140098$6226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 - connect \Y $not$libresoc.v:130369$5904_Y + connect \Y $not$libresoc.v:140098$6226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:130374$5909 + cell $not $not$libresoc.v:140103$6231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:130374$5909_Y + connect \Y $not$libresoc.v:140103$6231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:130399$5937 + cell $not $not$libresoc.v:140128$6259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:130399$5937_Y + connect \Y $not$libresoc.v:140128$6259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:130401$5939 + cell $not $not$libresoc.v:140130$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:130401$5939_Y + connect \Y $not$libresoc.v:140130$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:130403$5941 + cell $not $not$libresoc.v:140132$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:130403$5941_Y + connect \Y $not$libresoc.v:140132$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:130407$5945 + cell $not $not$libresoc.v:140136$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:130407$5945_Y + connect \Y $not$libresoc.v:140136$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:130422$5960 + cell $not $not$libresoc.v:140151$6282 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:130422$5960_Y + connect \Y $not$libresoc.v:140151$6282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:130424$5962 + cell $not $not$libresoc.v:140153$6284 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:130424$5962_Y + connect \Y $not$libresoc.v:140153$6284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:130431$5969 + cell $not $not$libresoc.v:140160$6291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 - connect \Y $not$libresoc.v:130431$5969_Y + connect \Y $not$libresoc.v:140160$6291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:130433$5971 + cell $not $not$libresoc.v:140162$6293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:130433$5971_Y + connect \Y $not$libresoc.v:140162$6293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:130348$5883 + cell $or $or$libresoc.v:140077$6205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209588,10 +225401,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130348$5883_Y + connect \Y $or$libresoc.v:140077$6205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:130359$5894 + cell $or $or$libresoc.v:140088$6216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209599,10 +225412,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130359$5894_Y + connect \Y $or$libresoc.v:140088$6216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:130362$5897 + cell $or $or$libresoc.v:140091$6219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209610,10 +225423,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:130362$5897_Y + connect \Y $or$libresoc.v:140091$6219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:130363$5898 + cell $or $or$libresoc.v:140092$6220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209621,10 +225434,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:130363$5898_Y + connect \Y $or$libresoc.v:140092$6220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:130364$5899 + cell $or $or$libresoc.v:140093$6221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209632,10 +225445,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:130364$5899_Y + connect \Y $or$libresoc.v:140093$6221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:130367$5902 + cell $or $or$libresoc.v:140096$6224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209643,10 +225456,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:130367$5902_Y + connect \Y $or$libresoc.v:140096$6224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:130368$5903 + cell $or $or$libresoc.v:140097$6225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209654,10 +225467,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:130368$5903_Y + connect \Y $or$libresoc.v:140097$6225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:130370$5905 + cell $or $or$libresoc.v:140099$6227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209665,10 +225478,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130370$5905_Y + connect \Y $or$libresoc.v:140099$6227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:130372$5907 + cell $or $or$libresoc.v:140101$6229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209676,10 +225489,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:130372$5907_Y + connect \Y $or$libresoc.v:140101$6229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:130375$5910 + cell $or $or$libresoc.v:140104$6232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209687,10 +225500,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:130375$5910_Y + connect \Y $or$libresoc.v:140104$6232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:130380$5915 + cell $or $or$libresoc.v:140109$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209698,10 +225511,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130380$5915_Y + connect \Y $or$libresoc.v:140109$6237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:130388$5925 + cell $or $or$libresoc.v:140117$6247 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209709,10 +225522,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:130388$5925_Y + connect \Y $or$libresoc.v:140117$6247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:130394$5932 + cell $or $or$libresoc.v:140123$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209720,10 +225533,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130394$5932_Y + connect \Y $or$libresoc.v:140123$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:130406$5944 + cell $or $or$libresoc.v:140135$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209731,10 +225544,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 - connect \Y $or$libresoc.v:130406$5944_Y + connect \Y $or$libresoc.v:140135$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:130410$5948 + cell $or $or$libresoc.v:140139$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209742,10 +225555,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 - connect \Y $or$libresoc.v:130410$5948_Y + connect \Y $or$libresoc.v:140139$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:130411$5949 + cell $or $or$libresoc.v:140140$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209753,10 +225566,10 @@ module \ldst0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:130411$5949_Y + connect \Y $or$libresoc.v:140140$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:130413$5951 + cell $or $or$libresoc.v:140142$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209764,10 +225577,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:130413$5951_Y + connect \Y $or$libresoc.v:140142$6273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:130414$5952 + cell $or $or$libresoc.v:140143$6274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209775,10 +225588,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:130414$5952_Y + connect \Y $or$libresoc.v:140143$6274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:130415$5953 + cell $or $or$libresoc.v:140144$6275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209786,10 +225599,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:130415$5953_Y + connect \Y $or$libresoc.v:140144$6275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:130428$5966 + cell $or $or$libresoc.v:140157$6288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209797,10 +225610,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130428$5966_Y + connect \Y $or$libresoc.v:140157$6288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:130429$5967 + cell $or $or$libresoc.v:140158$6289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209808,10 +225621,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:130429$5967_Y + connect \Y $or$libresoc.v:140158$6289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:130430$5968 + cell $or $or$libresoc.v:140159$6290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209819,98 +225632,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:130430$5968_Y + connect \Y $or$libresoc.v:140159$6290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:130384$5920 + cell $pos $pos$libresoc.v:140113$6242 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:130384$5919_Y - connect \Y $pos$libresoc.v:130384$5920_Y + connect \A $extend$libresoc.v:140113$6241_Y + connect \Y $pos$libresoc.v:140113$6242_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130386$5923 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140115$6245 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:130386$5922_Y - connect \Y $pos$libresoc.v:130386$5923_Y + connect \A $extend$libresoc.v:140115$6244_Y + connect \Y $pos$libresoc.v:140115$6245_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130387$5924 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140116$6246 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:130387$5924_Y + connect \Y $pos$libresoc.v:140116$6246_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130389$5926 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140118$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:130389$5926_Y + connect \Y $pos$libresoc.v:140118$6248_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130391$5929 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140120$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:130391$5928_Y - connect \Y $pos$libresoc.v:130391$5929_Y + connect \A $extend$libresoc.v:140120$6250_Y + connect \Y $pos$libresoc.v:140120$6251_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130392$5930 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140121$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:130392$5930_Y + connect \Y $pos$libresoc.v:140121$6252_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130393$5931 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140122$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:130393$5931_Y + connect \Y $pos$libresoc.v:140122$6253_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:130416$5954 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:140145$6276 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:130416$5954_Y + connect \Y $ternary$libresoc.v:140145$6276_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:130417$5955 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:140146$6277 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:130417$5955_Y + connect \Y $ternary$libresoc.v:140146$6277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:130418$5956 + cell $mux $ternary$libresoc.v:140147$6278 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:130418$5956_Y + connect \Y $ternary$libresoc.v:140147$6278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:130419$5957 + cell $mux $ternary$libresoc.v:140148$6279 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:130419$5957_Y + connect \Y $ternary$libresoc.v:140148$6279_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:130504.9-130510.4" + attribute \src "libresoc.v:140233.9-140239.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209919,7 +225732,7 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:130511.15-130517.4" + attribute \src "libresoc.v:140240.15-140246.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209928,7 +225741,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:130518.9-130524.4" + attribute \src "libresoc.v:140247.9-140253.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209937,7 +225750,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:130525.9-130531.4" + attribute \src "libresoc.v:140254.9-140260.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209946,7 +225759,7 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:130532.15-130538.4" + attribute \src "libresoc.v:140261.15-140267.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209955,7 +225768,7 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:130539.15-130545.4" + attribute \src "libresoc.v:140268.15-140274.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209964,7 +225777,7 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:130546.15-130552.4" + attribute \src "libresoc.v:140275.15-140281.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209973,7 +225786,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:130553.9-130559.4" + attribute \src "libresoc.v:140282.9-140288.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209982,7 +225795,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:130560.9-130566.4" + attribute \src "libresoc.v:140289.9-140295.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209991,7 +225804,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:130567.9-130573.4" + attribute \src "libresoc.v:140296.9-140302.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209999,547 +225812,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:129599.7-129599.20" - process $proc$libresoc.v:129599$6120 + attribute \src "libresoc.v:139322.7-139322.20" + process $proc$libresoc.v:139322$6442 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129795.7-129795.25" - process $proc$libresoc.v:129795$6121 + attribute \src "libresoc.v:139518.7-139518.25" + process $proc$libresoc.v:139518$6443 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:129809.7-129809.20" - process $proc$libresoc.v:129809$6122 + attribute \src "libresoc.v:139532.7-139532.20" + process $proc$libresoc.v:139532$6444 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:129855.14-129855.41" - process $proc$libresoc.v:129855$6123 + attribute \src "libresoc.v:139578.14-139578.41" + process $proc$libresoc.v:139578$6445 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:129885.14-129885.42" - process $proc$libresoc.v:129885$6124 + attribute \src "libresoc.v:139608.14-139608.42" + process $proc$libresoc.v:139608$6446 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:129890.14-129890.62" - process $proc$libresoc.v:129890$6125 + attribute \src "libresoc.v:139613.14-139613.62" + process $proc$libresoc.v:139613$6447 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:129895.7-129895.34" - process $proc$libresoc.v:129895$6126 + attribute \src "libresoc.v:139618.7-139618.34" + process $proc$libresoc.v:139618$6448 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:129944.7-129944.25" - process $proc$libresoc.v:129944$6127 + attribute \src "libresoc.v:139667.7-139667.25" + process $proc$libresoc.v:139667$6449 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:129958.7-129958.25" - process $proc$libresoc.v:129958$6128 + attribute \src "libresoc.v:139681.7-139681.25" + process $proc$libresoc.v:139681$6450 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:129962.7-129962.25" - process $proc$libresoc.v:129962$6129 + attribute \src "libresoc.v:139685.7-139685.25" + process $proc$libresoc.v:139685$6451 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:130090.7-130090.34" - process $proc$libresoc.v:130090$6130 + attribute \src "libresoc.v:139816.7-139816.34" + process $proc$libresoc.v:139816$6452 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:130094.13-130094.36" - process $proc$libresoc.v:130094$6131 + attribute \src "libresoc.v:139820.13-139820.36" + process $proc$libresoc.v:139820$6453 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:130111.14-130111.39" - process $proc$libresoc.v:130111$6132 + attribute \src "libresoc.v:139839.14-139839.40" + process $proc$libresoc.v:139839$6454 assign { } { } - assign $1\oper_r__fn_unit[11:0] 12'000000000000 + assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init - update \oper_r__fn_unit $1\oper_r__fn_unit[11:0] + update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:130115.14-130115.59" - process $proc$libresoc.v:130115$6133 + attribute \src "libresoc.v:139843.14-139843.59" + process $proc$libresoc.v:139843$6455 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:130119.7-130119.34" - process $proc$libresoc.v:130119$6134 + attribute \src "libresoc.v:139847.7-139847.34" + process $proc$libresoc.v:139847$6456 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:130123.14-130123.34" - process $proc$libresoc.v:130123$6135 + attribute \src "libresoc.v:139851.14-139851.34" + process $proc$libresoc.v:139851$6457 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:130201.13-130201.38" - process $proc$libresoc.v:130201$6136 + attribute \src "libresoc.v:139930.13-139930.38" + process $proc$libresoc.v:139930$6458 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:130205.7-130205.30" - process $proc$libresoc.v:130205$6137 + attribute \src "libresoc.v:139934.7-139934.30" + process $proc$libresoc.v:139934$6459 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:130209.7-130209.31" - process $proc$libresoc.v:130209$6138 + attribute \src "libresoc.v:139938.7-139938.31" + process $proc$libresoc.v:139938$6460 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:130218.13-130218.37" - process $proc$libresoc.v:130218$6139 + attribute \src "libresoc.v:139947.13-139947.37" + process $proc$libresoc.v:139947$6461 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:130222.7-130222.28" - process $proc$libresoc.v:130222$6140 + attribute \src "libresoc.v:139951.7-139951.28" + process $proc$libresoc.v:139951$6462 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:130226.7-130226.28" - process $proc$libresoc.v:130226$6141 + attribute \src "libresoc.v:139955.7-139955.28" + process $proc$libresoc.v:139955$6463 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:130230.7-130230.28" - process $proc$libresoc.v:130230$6142 + attribute \src "libresoc.v:139959.7-139959.28" + process $proc$libresoc.v:139959$6464 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:130234.7-130234.28" - process $proc$libresoc.v:130234$6143 + attribute \src "libresoc.v:139963.7-139963.28" + process $proc$libresoc.v:139963$6465 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:130238.7-130238.33" - process $proc$libresoc.v:130238$6144 + attribute \src "libresoc.v:139967.7-139967.33" + process $proc$libresoc.v:139967$6466 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:130242.7-130242.28" - process $proc$libresoc.v:130242$6145 + attribute \src "libresoc.v:139971.7-139971.28" + process $proc$libresoc.v:139971$6467 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:130246.7-130246.21" - process $proc$libresoc.v:130246$6146 + attribute \src "libresoc.v:139975.7-139975.21" + process $proc$libresoc.v:139975$6468 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:130288.13-130288.31" - process $proc$libresoc.v:130288$6147 + attribute \src "libresoc.v:140017.13-140017.31" + process $proc$libresoc.v:140017$6469 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:130292.13-130292.31" - process $proc$libresoc.v:130292$6148 + attribute \src "libresoc.v:140021.13-140021.31" + process $proc$libresoc.v:140021$6470 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:130296.14-130296.43" - process $proc$libresoc.v:130296$6149 + attribute \src "libresoc.v:140025.14-140025.43" + process $proc$libresoc.v:140025$6471 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:130300.14-130300.43" - process $proc$libresoc.v:130300$6150 + attribute \src "libresoc.v:140029.14-140029.43" + process $proc$libresoc.v:140029$6472 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:130304.14-130304.43" - process $proc$libresoc.v:130304$6151 + attribute \src "libresoc.v:140033.14-140033.43" + process $proc$libresoc.v:140033$6473 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:130314.7-130314.25" - process $proc$libresoc.v:130314$6152 + attribute \src "libresoc.v:140043.7-140043.25" + process $proc$libresoc.v:140043$6474 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:130324.7-130324.25" - process $proc$libresoc.v:130324$6153 + attribute \src "libresoc.v:140053.7-140053.25" + process $proc$libresoc.v:140053$6475 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:130328.7-130328.25" - process $proc$libresoc.v:130328$6154 + attribute \src "libresoc.v:140057.7-140057.25" + process $proc$libresoc.v:140057$6476 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:130338.7-130338.25" - process $proc$libresoc.v:130338$6155 + attribute \src "libresoc.v:140067.7-140067.25" + process $proc$libresoc.v:140067$6477 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:130434.3-130435.57" - process $proc$libresoc.v:130434$5972 + attribute \src "libresoc.v:140163.3-140164.57" + process $proc$libresoc.v:140163$6294 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:130436.3-130437.33" - process $proc$libresoc.v:130436$5973 + attribute \src "libresoc.v:140165.3-140166.33" + process $proc$libresoc.v:140165$6295 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:130438.3-130439.21" - process $proc$libresoc.v:130438$5974 + attribute \src "libresoc.v:140167.3-140168.21" + process $proc$libresoc.v:140167$6296 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:130440.3-130441.25" - process $proc$libresoc.v:130440$5975 + attribute \src "libresoc.v:140169.3-140170.25" + process $proc$libresoc.v:140169$6297 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:130442.3-130443.29" - process $proc$libresoc.v:130442$5976 + attribute \src "libresoc.v:140171.3-140172.29" + process $proc$libresoc.v:140171$6298 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:130444.3-130445.29" - process $proc$libresoc.v:130444$5977 + attribute \src "libresoc.v:140173.3-140174.29" + process $proc$libresoc.v:140173$6299 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:130446.3-130447.29" - process $proc$libresoc.v:130446$5978 + attribute \src "libresoc.v:140175.3-140176.29" + process $proc$libresoc.v:140175$6300 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:130448.3-130449.27" - process $proc$libresoc.v:130448$5979 + attribute \src "libresoc.v:140177.3-140178.27" + process $proc$libresoc.v:140177$6301 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:130450.3-130451.51" - process $proc$libresoc.v:130450$5980 + attribute \src "libresoc.v:140179.3-140180.51" + process $proc$libresoc.v:140179$6302 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:130452.3-130453.47" - process $proc$libresoc.v:130452$5981 + attribute \src "libresoc.v:140181.3-140182.47" + process $proc$libresoc.v:140181$6303 assign { } { } - assign $0\oper_r__fn_unit[11:0] \oper_r__fn_unit$next + assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk - update \oper_r__fn_unit $0\oper_r__fn_unit[11:0] + update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:130454.3-130455.61" - process $proc$libresoc.v:130454$5982 + attribute \src "libresoc.v:140183.3-140184.61" + process $proc$libresoc.v:140183$6304 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:130456.3-130457.57" - process $proc$libresoc.v:130456$5983 + attribute \src "libresoc.v:140185.3-140186.57" + process $proc$libresoc.v:140185$6305 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:130458.3-130459.45" - process $proc$libresoc.v:130458$5984 + attribute \src "libresoc.v:140187.3-140188.45" + process $proc$libresoc.v:140187$6306 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:130460.3-130461.45" - process $proc$libresoc.v:130460$5985 + attribute \src "libresoc.v:140189.3-140190.45" + process $proc$libresoc.v:140189$6307 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:130462.3-130463.45" - process $proc$libresoc.v:130462$5986 + attribute \src "libresoc.v:140191.3-140192.45" + process $proc$libresoc.v:140191$6308 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:130464.3-130465.45" - process $proc$libresoc.v:130464$5987 + attribute \src "libresoc.v:140193.3-140194.45" + process $proc$libresoc.v:140193$6309 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:130466.3-130467.45" - process $proc$libresoc.v:130466$5988 + attribute \src "libresoc.v:140195.3-140196.45" + process $proc$libresoc.v:140195$6310 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:130468.3-130469.49" - process $proc$libresoc.v:130468$5989 + attribute \src "libresoc.v:140197.3-140198.49" + process $proc$libresoc.v:140197$6311 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:130470.3-130471.51" - process $proc$libresoc.v:130470$5990 + attribute \src "libresoc.v:140199.3-140200.51" + process $proc$libresoc.v:140199$6312 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:130472.3-130473.49" - process $proc$libresoc.v:130472$5991 + attribute \src "libresoc.v:140201.3-140202.49" + process $proc$libresoc.v:140201$6313 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:130474.3-130475.57" - process $proc$libresoc.v:130474$5992 + attribute \src "libresoc.v:140203.3-140204.57" + process $proc$libresoc.v:140203$6314 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:130476.3-130477.55" - process $proc$libresoc.v:130476$5993 + attribute \src "libresoc.v:140205.3-140206.55" + process $proc$libresoc.v:140205$6315 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:130478.3-130479.51" - process $proc$libresoc.v:130478$5994 + attribute \src "libresoc.v:140207.3-140208.51" + process $proc$libresoc.v:140207$6316 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:130480.3-130481.41" - process $proc$libresoc.v:130480$5995 + attribute \src "libresoc.v:140209.3-140210.41" + process $proc$libresoc.v:140209$6317 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:130482.3-130483.39" - process $proc$libresoc.v:130482$5996 + attribute \src "libresoc.v:140211.3-140212.39" + process $proc$libresoc.v:140211$6318 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:130484.3-130485.39" - process $proc$libresoc.v:130484$5997 + attribute \src "libresoc.v:140213.3-140214.39" + process $proc$libresoc.v:140213$6319 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:130486.3-130487.39" - process $proc$libresoc.v:130486$5998 + attribute \src "libresoc.v:140215.3-140216.39" + process $proc$libresoc.v:140215$6320 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:130488.3-130489.39" - process $proc$libresoc.v:130488$5999 + attribute \src "libresoc.v:140217.3-140218.39" + process $proc$libresoc.v:140217$6321 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:130490.3-130491.39" - process $proc$libresoc.v:130490$6000 + attribute \src "libresoc.v:140219.3-140220.39" + process $proc$libresoc.v:140219$6322 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:130492.3-130493.39" - process $proc$libresoc.v:130492$6001 + attribute \src "libresoc.v:140221.3-140222.39" + process $proc$libresoc.v:140221$6323 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:130494.3-130495.39" - process $proc$libresoc.v:130494$6002 + attribute \src "libresoc.v:140223.3-140224.39" + process $proc$libresoc.v:140223$6324 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:130496.3-130497.39" - process $proc$libresoc.v:130496$6003 + attribute \src "libresoc.v:140225.3-140226.39" + process $proc$libresoc.v:140225$6325 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:130498.3-130499.39" - process $proc$libresoc.v:130498$6004 + attribute \src "libresoc.v:140227.3-140228.39" + process $proc$libresoc.v:140227$6326 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:130500.3-130501.39" - process $proc$libresoc.v:130500$6005 + attribute \src "libresoc.v:140229.3-140230.39" + process $proc$libresoc.v:140229$6327 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:130502.3-130503.28" - process $proc$libresoc.v:130502$6006 + attribute \src "libresoc.v:140231.3-140232.28" + process $proc$libresoc.v:140231$6328 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:130574.3-130582.6" - process $proc$libresoc.v:130574$6007 + attribute \src "libresoc.v:140303.3-140311.6" + process $proc$libresoc.v:140303$6329 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6008 $1\opc_l_s_opc$next[0:0]$6009 - attribute \src "libresoc.v:130575.5-130575.29" + assign $0\opc_l_s_opc$next[0:0]$6330 $1\opc_l_s_opc$next[0:0]$6331 + attribute \src "libresoc.v:140304.5-140304.29" switch \initial - attribute \src "libresoc.v:130575.9-130575.17" + attribute \src "libresoc.v:140304.9-140304.17" case 1'1 case end @@ -210548,21 +226361,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6009 1'0 + assign $1\opc_l_s_opc$next[0:0]$6331 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6009 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6331 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6008 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6330 end - attribute \src "libresoc.v:130583.3-130591.6" - process $proc$libresoc.v:130583$6010 + attribute \src "libresoc.v:140312.3-140320.6" + process $proc$libresoc.v:140312$6332 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6011 $1\opc_l_r_opc$next[0:0]$6012 - attribute \src "libresoc.v:130584.5-130584.29" + assign $0\opc_l_r_opc$next[0:0]$6333 $1\opc_l_r_opc$next[0:0]$6334 + attribute \src "libresoc.v:140313.5-140313.29" switch \initial - attribute \src "libresoc.v:130584.9-130584.17" + attribute \src "libresoc.v:140313.9-140313.17" case 1'1 case end @@ -210571,21 +226384,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6012 1'1 + assign $1\opc_l_r_opc$next[0:0]$6334 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6012 \reset_o + assign $1\opc_l_r_opc$next[0:0]$6334 \reset_o end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6011 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6333 end - attribute \src "libresoc.v:130592.3-130600.6" - process $proc$libresoc.v:130592$6013 + attribute \src "libresoc.v:140321.3-140329.6" + process $proc$libresoc.v:140321$6335 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6014 $1\src_l_s_src$next[2:0]$6015 - attribute \src "libresoc.v:130593.5-130593.29" + assign $0\src_l_s_src$next[2:0]$6336 $1\src_l_s_src$next[2:0]$6337 + attribute \src "libresoc.v:140322.5-140322.29" switch \initial - attribute \src "libresoc.v:130593.9-130593.17" + attribute \src "libresoc.v:140322.9-140322.17" case 1'1 case end @@ -210594,21 +226407,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6015 3'000 + assign $1\src_l_s_src$next[2:0]$6337 3'000 case - assign $1\src_l_s_src$next[2:0]$6015 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6337 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6014 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6336 end - attribute \src "libresoc.v:130601.3-130609.6" - process $proc$libresoc.v:130601$6016 + attribute \src "libresoc.v:140330.3-140338.6" + process $proc$libresoc.v:140330$6338 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6017 $1\src_l_r_src$next[2:0]$6018 - attribute \src "libresoc.v:130602.5-130602.29" + assign $0\src_l_r_src$next[2:0]$6339 $1\src_l_r_src$next[2:0]$6340 + attribute \src "libresoc.v:140331.5-140331.29" switch \initial - attribute \src "libresoc.v:130602.9-130602.17" + attribute \src "libresoc.v:140331.9-140331.17" case 1'1 case end @@ -210617,21 +226430,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6018 3'111 + assign $1\src_l_r_src$next[2:0]$6340 3'111 case - assign $1\src_l_r_src$next[2:0]$6018 \reset_r + assign $1\src_l_r_src$next[2:0]$6340 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6017 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6339 end - attribute \src "libresoc.v:130610.3-130618.6" - process $proc$libresoc.v:130610$6019 + attribute \src "libresoc.v:140339.3-140347.6" + process $proc$libresoc.v:140339$6341 assign { } { } assign { } { } - assign $0\adr_l_r_adr$next[0:0]$6020 $1\adr_l_r_adr$next[0:0]$6021 - attribute \src "libresoc.v:130611.5-130611.29" + assign $0\adr_l_r_adr$next[0:0]$6342 $1\adr_l_r_adr$next[0:0]$6343 + attribute \src "libresoc.v:140340.5-140340.29" switch \initial - attribute \src "libresoc.v:130611.9-130611.17" + attribute \src "libresoc.v:140340.9-140340.17" case 1'1 case end @@ -210640,21 +226453,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adr_l_r_adr$next[0:0]$6021 1'1 + assign $1\adr_l_r_adr$next[0:0]$6343 1'1 case - assign $1\adr_l_r_adr$next[0:0]$6021 \reset_a + assign $1\adr_l_r_adr$next[0:0]$6343 \reset_a end sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6020 + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6342 end - attribute \src "libresoc.v:130619.3-130627.6" - process $proc$libresoc.v:130619$6022 + attribute \src "libresoc.v:140348.3-140356.6" + process $proc$libresoc.v:140348$6344 assign { } { } assign { } { } - assign $0\wri_l_r_wri$next[0:0]$6023 $1\wri_l_r_wri$next[0:0]$6024 - attribute \src "libresoc.v:130620.5-130620.29" + assign $0\wri_l_r_wri$next[0:0]$6345 $1\wri_l_r_wri$next[0:0]$6346 + attribute \src "libresoc.v:140349.5-140349.29" switch \initial - attribute \src "libresoc.v:130620.9-130620.17" + attribute \src "libresoc.v:140349.9-140349.17" case 1'1 case end @@ -210663,21 +226476,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wri_l_r_wri$next[0:0]$6024 1'1 + assign $1\wri_l_r_wri$next[0:0]$6346 1'1 case - assign $1\wri_l_r_wri$next[0:0]$6024 \$38 [0] + assign $1\wri_l_r_wri$next[0:0]$6346 \$38 [0] end sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6023 + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6345 end - attribute \src "libresoc.v:130628.3-130636.6" - process $proc$libresoc.v:130628$6025 + attribute \src "libresoc.v:140357.3-140365.6" + process $proc$libresoc.v:140357$6347 assign { } { } assign { } { } - assign $0\upd_l_s_upd$next[0:0]$6026 $1\upd_l_s_upd$next[0:0]$6027 - attribute \src "libresoc.v:130629.5-130629.29" + assign $0\upd_l_s_upd$next[0:0]$6348 $1\upd_l_s_upd$next[0:0]$6349 + attribute \src "libresoc.v:140358.5-140358.29" switch \initial - attribute \src "libresoc.v:130629.9-130629.17" + attribute \src "libresoc.v:140358.9-140358.17" case 1'1 case end @@ -210686,21 +226499,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_s_upd$next[0:0]$6027 1'0 + assign $1\upd_l_s_upd$next[0:0]$6349 1'0 case - assign $1\upd_l_s_upd$next[0:0]$6027 \reset_i + assign $1\upd_l_s_upd$next[0:0]$6349 \reset_i end sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6026 + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6348 end - attribute \src "libresoc.v:130637.3-130645.6" - process $proc$libresoc.v:130637$6028 + attribute \src "libresoc.v:140366.3-140374.6" + process $proc$libresoc.v:140366$6350 assign { } { } assign { } { } - assign $0\upd_l_r_upd$next[0:0]$6029 $1\upd_l_r_upd$next[0:0]$6030 - attribute \src "libresoc.v:130638.5-130638.29" + assign $0\upd_l_r_upd$next[0:0]$6351 $1\upd_l_r_upd$next[0:0]$6352 + attribute \src "libresoc.v:140367.5-140367.29" switch \initial - attribute \src "libresoc.v:130638.9-130638.17" + attribute \src "libresoc.v:140367.9-140367.17" case 1'1 case end @@ -210709,21 +226522,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_r_upd$next[0:0]$6030 1'1 + assign $1\upd_l_r_upd$next[0:0]$6352 1'1 case - assign $1\upd_l_r_upd$next[0:0]$6030 \reset_u + assign $1\upd_l_r_upd$next[0:0]$6352 \reset_u end sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6029 + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6351 end - attribute \src "libresoc.v:130646.3-130654.6" - process $proc$libresoc.v:130646$6031 + attribute \src "libresoc.v:140375.3-140383.6" + process $proc$libresoc.v:140375$6353 assign { } { } assign { } { } - assign $0\sto_l_r_sto$next[0:0]$6032 $1\sto_l_r_sto$next[0:0]$6033 - attribute \src "libresoc.v:130647.5-130647.29" + assign $0\sto_l_r_sto$next[0:0]$6354 $1\sto_l_r_sto$next[0:0]$6355 + attribute \src "libresoc.v:140376.5-140376.29" switch \initial - attribute \src "libresoc.v:130647.9-130647.17" + attribute \src "libresoc.v:140376.9-140376.17" case 1'1 case end @@ -210732,21 +226545,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sto_l_r_sto$next[0:0]$6033 1'1 + assign $1\sto_l_r_sto$next[0:0]$6355 1'1 case - assign $1\sto_l_r_sto$next[0:0]$6033 \$59 + assign $1\sto_l_r_sto$next[0:0]$6355 \$59 end sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6032 + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6354 end - attribute \src "libresoc.v:130655.3-130663.6" - process $proc$libresoc.v:130655$6034 + attribute \src "libresoc.v:140384.3-140392.6" + process $proc$libresoc.v:140384$6356 assign { } { } assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$6035 $1\lsd_l_r_lsd$next[0:0]$6036 - attribute \src "libresoc.v:130656.5-130656.29" + assign $0\lsd_l_r_lsd$next[0:0]$6357 $1\lsd_l_r_lsd$next[0:0]$6358 + attribute \src "libresoc.v:140385.5-140385.29" switch \initial - attribute \src "libresoc.v:130656.9-130656.17" + attribute \src "libresoc.v:140385.9-140385.17" case 1'1 case end @@ -210755,15 +226568,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$6036 1'1 + assign $1\lsd_l_r_lsd$next[0:0]$6358 1'1 case - assign $1\lsd_l_r_lsd$next[0:0]$6036 \$63 + assign $1\lsd_l_r_lsd$next[0:0]$6358 \$63 end sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6035 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6357 end - attribute \src "libresoc.v:130664.3-130706.6" - process $proc$libresoc.v:130664$6037 + attribute \src "libresoc.v:140393.3-140435.6" + process $proc$libresoc.v:140393$6359 assign { } { } assign { } { } assign { } { } @@ -210812,31 +226625,31 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$6038 $2\oper_r__byte_reverse$next[0:0]$6070 - assign $0\oper_r__data_len$next[3:0]$6039 $2\oper_r__data_len$next[3:0]$6071 - assign $0\oper_r__fn_unit$next[11:0]$6040 $2\oper_r__fn_unit$next[11:0]$6072 + assign $0\oper_r__byte_reverse$next[0:0]$6360 $2\oper_r__byte_reverse$next[0:0]$6392 + assign $0\oper_r__data_len$next[3:0]$6361 $2\oper_r__data_len$next[3:0]$6393 + assign $0\oper_r__fn_unit$next[13:0]$6362 $2\oper_r__fn_unit$next[13:0]$6394 assign { } { } assign { } { } - assign $0\oper_r__insn$next[31:0]$6043 $2\oper_r__insn$next[31:0]$6075 - assign $0\oper_r__insn_type$next[6:0]$6044 $2\oper_r__insn_type$next[6:0]$6076 - assign $0\oper_r__is_32bit$next[0:0]$6045 $2\oper_r__is_32bit$next[0:0]$6077 - assign $0\oper_r__is_signed$next[0:0]$6046 $2\oper_r__is_signed$next[0:0]$6078 - assign $0\oper_r__ldst_mode$next[1:0]$6047 $2\oper_r__ldst_mode$next[1:0]$6079 + assign $0\oper_r__insn$next[31:0]$6365 $2\oper_r__insn$next[31:0]$6397 + assign $0\oper_r__insn_type$next[6:0]$6366 $2\oper_r__insn_type$next[6:0]$6398 + assign $0\oper_r__is_32bit$next[0:0]$6367 $2\oper_r__is_32bit$next[0:0]$6399 + assign $0\oper_r__is_signed$next[0:0]$6368 $2\oper_r__is_signed$next[0:0]$6400 + assign $0\oper_r__ldst_mode$next[1:0]$6369 $2\oper_r__ldst_mode$next[1:0]$6401 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$6052 $2\oper_r__sign_extend$next[0:0]$6084 - assign $0\oper_r__zero_a$next[0:0]$6053 $2\oper_r__zero_a$next[0:0]$6085 - assign $0\oper_r__imm_data__data$next[63:0]$6041 $3\oper_r__imm_data__data$next[63:0]$6086 - assign $0\oper_r__imm_data__ok$next[0:0]$6042 $3\oper_r__imm_data__ok$next[0:0]$6087 - assign $0\oper_r__oe__oe$next[0:0]$6048 $3\oper_r__oe__oe$next[0:0]$6088 - assign $0\oper_r__oe__ok$next[0:0]$6049 $3\oper_r__oe__ok$next[0:0]$6089 - assign $0\oper_r__rc__ok$next[0:0]$6050 $3\oper_r__rc__ok$next[0:0]$6090 - assign $0\oper_r__rc__rc$next[0:0]$6051 $3\oper_r__rc__rc$next[0:0]$6091 - attribute \src "libresoc.v:130665.5-130665.29" + assign $0\oper_r__sign_extend$next[0:0]$6374 $2\oper_r__sign_extend$next[0:0]$6406 + assign $0\oper_r__zero_a$next[0:0]$6375 $2\oper_r__zero_a$next[0:0]$6407 + assign $0\oper_r__imm_data__data$next[63:0]$6363 $3\oper_r__imm_data__data$next[63:0]$6408 + assign $0\oper_r__imm_data__ok$next[0:0]$6364 $3\oper_r__imm_data__ok$next[0:0]$6409 + assign $0\oper_r__oe__oe$next[0:0]$6370 $3\oper_r__oe__oe$next[0:0]$6410 + assign $0\oper_r__oe__ok$next[0:0]$6371 $3\oper_r__oe__ok$next[0:0]$6411 + assign $0\oper_r__rc__ok$next[0:0]$6372 $3\oper_r__rc__ok$next[0:0]$6412 + assign $0\oper_r__rc__rc$next[0:0]$6373 $3\oper_r__rc__rc$next[0:0]$6413 + attribute \src "libresoc.v:140394.5-140394.29" switch \initial - attribute \src "libresoc.v:130665.9-130665.17" + attribute \src "libresoc.v:140394.9-140394.17" case 1'1 case end @@ -210860,24 +226673,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $1\oper_r__insn$next[31:0]$6059 $1\oper_r__ldst_mode$next[1:0]$6063 $1\oper_r__sign_extend$next[0:0]$6068 $1\oper_r__byte_reverse$next[0:0]$6054 $1\oper_r__data_len$next[3:0]$6055 $1\oper_r__is_signed$next[0:0]$6062 $1\oper_r__is_32bit$next[0:0]$6061 $1\oper_r__oe__ok$next[0:0]$6065 $1\oper_r__oe__oe$next[0:0]$6064 $1\oper_r__rc__ok$next[0:0]$6066 $1\oper_r__rc__rc$next[0:0]$6067 $1\oper_r__zero_a$next[0:0]$6069 $1\oper_r__imm_data__ok$next[0:0]$6058 $1\oper_r__imm_data__data$next[63:0]$6057 $1\oper_r__fn_unit$next[11:0]$6056 $1\oper_r__insn_type$next[6:0]$6060 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + assign { $1\oper_r__insn$next[31:0]$6381 $1\oper_r__ldst_mode$next[1:0]$6385 $1\oper_r__sign_extend$next[0:0]$6390 $1\oper_r__byte_reverse$next[0:0]$6376 $1\oper_r__data_len$next[3:0]$6377 $1\oper_r__is_signed$next[0:0]$6384 $1\oper_r__is_32bit$next[0:0]$6383 $1\oper_r__oe__ok$next[0:0]$6387 $1\oper_r__oe__oe$next[0:0]$6386 $1\oper_r__rc__ok$next[0:0]$6388 $1\oper_r__rc__rc$next[0:0]$6389 $1\oper_r__zero_a$next[0:0]$6391 $1\oper_r__imm_data__ok$next[0:0]$6380 $1\oper_r__imm_data__data$next[63:0]$6379 $1\oper_r__fn_unit$next[13:0]$6378 $1\oper_r__insn_type$next[6:0]$6382 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } case - assign $1\oper_r__byte_reverse$next[0:0]$6054 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$6055 \oper_r__data_len - assign $1\oper_r__fn_unit$next[11:0]$6056 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$6057 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$6058 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$6059 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$6060 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$6061 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$6062 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$6063 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$6064 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$6065 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$6066 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$6067 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$6068 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$6069 \oper_r__zero_a + assign $1\oper_r__byte_reverse$next[0:0]$6376 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6377 \oper_r__data_len + assign $1\oper_r__fn_unit$next[13:0]$6378 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6379 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6380 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6381 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6382 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6383 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6384 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6385 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6386 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6387 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6388 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6389 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6390 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6391 \oper_r__zero_a end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" switch \cu_done_o @@ -210899,24 +226712,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $2\oper_r__insn$next[31:0]$6075 $2\oper_r__ldst_mode$next[1:0]$6079 $2\oper_r__sign_extend$next[0:0]$6084 $2\oper_r__byte_reverse$next[0:0]$6070 $2\oper_r__data_len$next[3:0]$6071 $2\oper_r__is_signed$next[0:0]$6078 $2\oper_r__is_32bit$next[0:0]$6077 $2\oper_r__oe__ok$next[0:0]$6081 $2\oper_r__oe__oe$next[0:0]$6080 $2\oper_r__rc__ok$next[0:0]$6082 $2\oper_r__rc__rc$next[0:0]$6083 $2\oper_r__zero_a$next[0:0]$6085 $2\oper_r__imm_data__ok$next[0:0]$6074 $2\oper_r__imm_data__data$next[63:0]$6073 $2\oper_r__fn_unit$next[11:0]$6072 $2\oper_r__insn_type$next[6:0]$6076 } 131'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\oper_r__insn$next[31:0]$6397 $2\oper_r__ldst_mode$next[1:0]$6401 $2\oper_r__sign_extend$next[0:0]$6406 $2\oper_r__byte_reverse$next[0:0]$6392 $2\oper_r__data_len$next[3:0]$6393 $2\oper_r__is_signed$next[0:0]$6400 $2\oper_r__is_32bit$next[0:0]$6399 $2\oper_r__oe__ok$next[0:0]$6403 $2\oper_r__oe__oe$next[0:0]$6402 $2\oper_r__rc__ok$next[0:0]$6404 $2\oper_r__rc__rc$next[0:0]$6405 $2\oper_r__zero_a$next[0:0]$6407 $2\oper_r__imm_data__ok$next[0:0]$6396 $2\oper_r__imm_data__data$next[63:0]$6395 $2\oper_r__fn_unit$next[13:0]$6394 $2\oper_r__insn_type$next[6:0]$6398 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\oper_r__byte_reverse$next[0:0]$6070 $1\oper_r__byte_reverse$next[0:0]$6054 - assign $2\oper_r__data_len$next[3:0]$6071 $1\oper_r__data_len$next[3:0]$6055 - assign $2\oper_r__fn_unit$next[11:0]$6072 $1\oper_r__fn_unit$next[11:0]$6056 - assign $2\oper_r__imm_data__data$next[63:0]$6073 $1\oper_r__imm_data__data$next[63:0]$6057 - assign $2\oper_r__imm_data__ok$next[0:0]$6074 $1\oper_r__imm_data__ok$next[0:0]$6058 - assign $2\oper_r__insn$next[31:0]$6075 $1\oper_r__insn$next[31:0]$6059 - assign $2\oper_r__insn_type$next[6:0]$6076 $1\oper_r__insn_type$next[6:0]$6060 - assign $2\oper_r__is_32bit$next[0:0]$6077 $1\oper_r__is_32bit$next[0:0]$6061 - assign $2\oper_r__is_signed$next[0:0]$6078 $1\oper_r__is_signed$next[0:0]$6062 - assign $2\oper_r__ldst_mode$next[1:0]$6079 $1\oper_r__ldst_mode$next[1:0]$6063 - assign $2\oper_r__oe__oe$next[0:0]$6080 $1\oper_r__oe__oe$next[0:0]$6064 - assign $2\oper_r__oe__ok$next[0:0]$6081 $1\oper_r__oe__ok$next[0:0]$6065 - assign $2\oper_r__rc__ok$next[0:0]$6082 $1\oper_r__rc__ok$next[0:0]$6066 - assign $2\oper_r__rc__rc$next[0:0]$6083 $1\oper_r__rc__rc$next[0:0]$6067 - assign $2\oper_r__sign_extend$next[0:0]$6084 $1\oper_r__sign_extend$next[0:0]$6068 - assign $2\oper_r__zero_a$next[0:0]$6085 $1\oper_r__zero_a$next[0:0]$6069 + assign $2\oper_r__byte_reverse$next[0:0]$6392 $1\oper_r__byte_reverse$next[0:0]$6376 + assign $2\oper_r__data_len$next[3:0]$6393 $1\oper_r__data_len$next[3:0]$6377 + assign $2\oper_r__fn_unit$next[13:0]$6394 $1\oper_r__fn_unit$next[13:0]$6378 + assign $2\oper_r__imm_data__data$next[63:0]$6395 $1\oper_r__imm_data__data$next[63:0]$6379 + assign $2\oper_r__imm_data__ok$next[0:0]$6396 $1\oper_r__imm_data__ok$next[0:0]$6380 + assign $2\oper_r__insn$next[31:0]$6397 $1\oper_r__insn$next[31:0]$6381 + assign $2\oper_r__insn_type$next[6:0]$6398 $1\oper_r__insn_type$next[6:0]$6382 + assign $2\oper_r__is_32bit$next[0:0]$6399 $1\oper_r__is_32bit$next[0:0]$6383 + assign $2\oper_r__is_signed$next[0:0]$6400 $1\oper_r__is_signed$next[0:0]$6384 + assign $2\oper_r__ldst_mode$next[1:0]$6401 $1\oper_r__ldst_mode$next[1:0]$6385 + assign $2\oper_r__oe__oe$next[0:0]$6402 $1\oper_r__oe__oe$next[0:0]$6386 + assign $2\oper_r__oe__ok$next[0:0]$6403 $1\oper_r__oe__ok$next[0:0]$6387 + assign $2\oper_r__rc__ok$next[0:0]$6404 $1\oper_r__rc__ok$next[0:0]$6388 + assign $2\oper_r__rc__rc$next[0:0]$6405 $1\oper_r__rc__rc$next[0:0]$6389 + assign $2\oper_r__sign_extend$next[0:0]$6406 $1\oper_r__sign_extend$next[0:0]$6390 + assign $2\oper_r__zero_a$next[0:0]$6407 $1\oper_r__zero_a$next[0:0]$6391 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -210928,70 +226741,70 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$6086 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$6087 1'0 - assign $3\oper_r__rc__rc$next[0:0]$6091 1'0 - assign $3\oper_r__rc__ok$next[0:0]$6090 1'0 - assign $3\oper_r__oe__oe$next[0:0]$6088 1'0 - assign $3\oper_r__oe__ok$next[0:0]$6089 1'0 + assign $3\oper_r__imm_data__data$next[63:0]$6408 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6409 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6413 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6412 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6410 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6411 1'0 case - assign $3\oper_r__imm_data__data$next[63:0]$6086 $2\oper_r__imm_data__data$next[63:0]$6073 - assign $3\oper_r__imm_data__ok$next[0:0]$6087 $2\oper_r__imm_data__ok$next[0:0]$6074 - assign $3\oper_r__oe__oe$next[0:0]$6088 $2\oper_r__oe__oe$next[0:0]$6080 - assign $3\oper_r__oe__ok$next[0:0]$6089 $2\oper_r__oe__ok$next[0:0]$6081 - assign $3\oper_r__rc__ok$next[0:0]$6090 $2\oper_r__rc__ok$next[0:0]$6082 - assign $3\oper_r__rc__rc$next[0:0]$6091 $2\oper_r__rc__rc$next[0:0]$6083 + assign $3\oper_r__imm_data__data$next[63:0]$6408 $2\oper_r__imm_data__data$next[63:0]$6395 + assign $3\oper_r__imm_data__ok$next[0:0]$6409 $2\oper_r__imm_data__ok$next[0:0]$6396 + assign $3\oper_r__oe__oe$next[0:0]$6410 $2\oper_r__oe__oe$next[0:0]$6402 + assign $3\oper_r__oe__ok$next[0:0]$6411 $2\oper_r__oe__ok$next[0:0]$6403 + assign $3\oper_r__rc__ok$next[0:0]$6412 $2\oper_r__rc__ok$next[0:0]$6404 + assign $3\oper_r__rc__rc$next[0:0]$6413 $2\oper_r__rc__rc$next[0:0]$6405 end sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6038 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6039 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[11:0]$6040 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6041 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6042 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6043 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6044 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6045 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6046 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6047 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6048 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6049 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6050 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6051 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6052 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6053 + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6360 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6361 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6362 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6363 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6364 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6365 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6366 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6367 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6368 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6369 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6370 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6371 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6372 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6373 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6374 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6375 end - attribute \src "libresoc.v:130707.3-130716.6" - process $proc$libresoc.v:130707$6092 + attribute \src "libresoc.v:140436.3-140445.6" + process $proc$libresoc.v:140436$6414 assign { } { } assign { } { } - assign $0\ldo_r$next[63:0]$6093 $1\ldo_r$next[63:0]$6094 - attribute \src "libresoc.v:130708.5-130708.29" + assign $0\ldo_r$next[63:0]$6415 $1\ldo_r$next[63:0]$6416 + attribute \src "libresoc.v:140437.5-140437.29" switch \initial - attribute \src "libresoc.v:130708.9-130708.17" + attribute \src "libresoc.v:140437.9-140437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \ld_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldo_r$next[63:0]$6094 \ldd_o + assign $1\ldo_r$next[63:0]$6416 \ldd_o case - assign $1\ldo_r$next[63:0]$6094 \ldo_r + assign $1\ldo_r$next[63:0]$6416 \ldo_r end sync always - update \ldo_r$next $0\ldo_r$next[63:0]$6093 + update \ldo_r$next $0\ldo_r$next[63:0]$6415 end - attribute \src "libresoc.v:130717.3-130732.6" - process $proc$libresoc.v:130717$6095 + attribute \src "libresoc.v:140446.3-140461.6" + process $proc$libresoc.v:140446$6417 assign { } { } assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6096 $2\src_r0$next[63:0]$6098 - attribute \src "libresoc.v:130718.5-130718.29" + assign $0\src_r0$next[63:0]$6418 $2\src_r0$next[63:0]$6420 + attribute \src "libresoc.v:140447.5-140447.29" switch \initial - attribute \src "libresoc.v:130718.9-130718.17" + attribute \src "libresoc.v:140447.9-140447.17" case 1'1 case end @@ -211000,31 +226813,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6097 \src1_i + assign $1\src_r0$next[63:0]$6419 \src1_i case - assign $1\src_r0$next[63:0]$6097 \src_r0 + assign $1\src_r0$next[63:0]$6419 \src_r0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r0$next[63:0]$6098 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r0$next[63:0]$6420 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r0$next[63:0]$6098 $1\src_r0$next[63:0]$6097 + assign $2\src_r0$next[63:0]$6420 $1\src_r0$next[63:0]$6419 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6096 + update \src_r0$next $0\src_r0$next[63:0]$6418 end - attribute \src "libresoc.v:130733.3-130748.6" - process $proc$libresoc.v:130733$6099 + attribute \src "libresoc.v:140462.3-140477.6" + process $proc$libresoc.v:140462$6421 assign { } { } assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6100 $2\src_r1$next[63:0]$6102 - attribute \src "libresoc.v:130734.5-130734.29" + assign $0\src_r1$next[63:0]$6422 $2\src_r1$next[63:0]$6424 + attribute \src "libresoc.v:140463.5-140463.29" switch \initial - attribute \src "libresoc.v:130734.9-130734.17" + attribute \src "libresoc.v:140463.9-140463.17" case 1'1 case end @@ -211033,31 +226846,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6101 \src2_i + assign $1\src_r1$next[63:0]$6423 \src2_i case - assign $1\src_r1$next[63:0]$6101 \src_r1 + assign $1\src_r1$next[63:0]$6423 \src_r1 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r1$next[63:0]$6102 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r1$next[63:0]$6424 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r1$next[63:0]$6102 $1\src_r1$next[63:0]$6101 + assign $2\src_r1$next[63:0]$6424 $1\src_r1$next[63:0]$6423 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6100 + update \src_r1$next $0\src_r1$next[63:0]$6422 end - attribute \src "libresoc.v:130749.3-130764.6" - process $proc$libresoc.v:130749$6103 + attribute \src "libresoc.v:140478.3-140493.6" + process $proc$libresoc.v:140478$6425 assign { } { } assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$6104 $2\src_r2$next[63:0]$6106 - attribute \src "libresoc.v:130750.5-130750.29" + assign $0\src_r2$next[63:0]$6426 $2\src_r2$next[63:0]$6428 + attribute \src "libresoc.v:140479.5-140479.29" switch \initial - attribute \src "libresoc.v:130750.9-130750.17" + attribute \src "libresoc.v:140479.9-140479.17" case 1'1 case end @@ -211066,53 +226879,53 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$6105 \src3_i + assign $1\src_r2$next[63:0]$6427 \src3_i case - assign $1\src_r2$next[63:0]$6105 \src_r2 + assign $1\src_r2$next[63:0]$6427 \src_r2 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r2$next[63:0]$6106 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r2$next[63:0]$6428 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r2$next[63:0]$6106 $1\src_r2$next[63:0]$6105 + assign $2\src_r2$next[63:0]$6428 $1\src_r2$next[63:0]$6427 end sync always - update \src_r2$next $0\src_r2$next[63:0]$6104 + update \src_r2$next $0\src_r2$next[63:0]$6426 end - attribute \src "libresoc.v:130765.3-130774.6" - process $proc$libresoc.v:130765$6107 + attribute \src "libresoc.v:140494.3-140503.6" + process $proc$libresoc.v:140494$6429 assign { } { } assign { } { } - assign $0\ea_r$next[63:0]$6108 $1\ea_r$next[63:0]$6109 - attribute \src "libresoc.v:130766.5-130766.29" + assign $0\ea_r$next[63:0]$6430 $1\ea_r$next[63:0]$6431 + attribute \src "libresoc.v:140495.5-140495.29" switch \initial - attribute \src "libresoc.v:130766.9-130766.17" + attribute \src "libresoc.v:140495.9-140495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \alu_l_q_alu attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ea_r$next[63:0]$6109 \alu_o + assign $1\ea_r$next[63:0]$6431 \alu_o case - assign $1\ea_r$next[63:0]$6109 \ea_r + assign $1\ea_r$next[63:0]$6431 \ea_r end sync always - update \ea_r$next $0\ea_r$next[63:0]$6108 + update \ea_r$next $0\ea_r$next[63:0]$6430 end - attribute \src "libresoc.v:130775.3-130784.6" - process $proc$libresoc.v:130775$6110 + attribute \src "libresoc.v:140504.3-140513.6" + process $proc$libresoc.v:140504$6432 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:130776.5-130776.29" + attribute \src "libresoc.v:140505.5-140505.29" switch \initial - attribute \src "libresoc.v:130776.9-130776.17" + attribute \src "libresoc.v:140505.9-140505.17" case 1'1 case end @@ -211128,14 +226941,14 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:130785.3-130794.6" - process $proc$libresoc.v:130785$6111 + attribute \src "libresoc.v:140514.3-140523.6" + process $proc$libresoc.v:140514$6433 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:130786.5-130786.29" + attribute \src "libresoc.v:140515.5-140515.29" switch \initial - attribute \src "libresoc.v:130786.9-130786.17" + attribute \src "libresoc.v:140515.9-140515.17" case 1'1 case end @@ -211151,14 +226964,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:130795.3-130803.6" - process $proc$libresoc.v:130795$6112 + attribute \src "libresoc.v:140524.3-140532.6" + process $proc$libresoc.v:140524$6434 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$6113 $1\ldst_port0_addr_i_ok$next[0:0]$6114 - attribute \src "libresoc.v:130796.5-130796.29" + assign $0\ldst_port0_addr_i_ok$next[0:0]$6435 $1\ldst_port0_addr_i_ok$next[0:0]$6436 + attribute \src "libresoc.v:140525.5-140525.29" switch \initial - attribute \src "libresoc.v:130796.9-130796.17" + attribute \src "libresoc.v:140525.9-140525.17" case 1'1 case end @@ -211167,21 +226980,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$6114 1'0 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6436 1'0 case - assign $1\ldst_port0_addr_i_ok$next[0:0]$6114 \$177 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6436 \$177 end sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6113 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6435 end - attribute \src "libresoc.v:130804.3-130827.6" - process $proc$libresoc.v:130804$6115 + attribute \src "libresoc.v:140533.3-140556.6" + process $proc$libresoc.v:140533$6437 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:130805.5-130805.29" + attribute \src "libresoc.v:140534.5-140534.29" switch \initial - attribute \src "libresoc.v:130805.9-130805.17" + attribute \src "libresoc.v:140534.9-140534.17" case 1'1 case end @@ -211191,7 +227004,7 @@ module \ldst0 case 1'1 assign { } { } assign $1\lddata_r[63:0] $2\lddata_r[63:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" switch \oper_r__data_len attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -211218,13 +227031,13 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:130828.3-130839.6" - process $proc$libresoc.v:130828$6116 + attribute \src "libresoc.v:140557.3-140568.6" + process $proc$libresoc.v:140557$6438 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:130829.5-130829.29" + attribute \src "libresoc.v:140558.5-140558.29" switch \initial - attribute \src "libresoc.v:130829.9-130829.17" + attribute \src "libresoc.v:140558.9-140558.17" case 1'1 case end @@ -211242,13 +227055,13 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:130840.3-130859.6" - process $proc$libresoc.v:130840$6117 + attribute \src "libresoc.v:140569.3-140588.6" + process $proc$libresoc.v:140569$6439 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:130841.5-130841.29" + attribute \src "libresoc.v:140570.5-140570.29" switch \initial - attribute \src "libresoc.v:130841.9-130841.17" + attribute \src "libresoc.v:140570.9-140570.17" case 1'1 case end @@ -211277,14 +227090,14 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:130860.3-130883.6" - process $proc$libresoc.v:130860$6118 + attribute \src "libresoc.v:140589.3-140612.6" + process $proc$libresoc.v:140589$6440 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:130861.5-130861.29" + attribute \src "libresoc.v:140590.5-140590.29" switch \initial - attribute \src "libresoc.v:130861.9-130861.17" + attribute \src "libresoc.v:140590.9-140590.17" case 1'1 case end @@ -211294,7 +227107,7 @@ module \ldst0 case 1'1 assign { } { } assign $1\stdata_r[63:0] $2\stdata_r[63:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" switch \oper_r__data_len attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -211321,13 +227134,13 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:130884.3-130895.6" - process $proc$libresoc.v:130884$6119 + attribute \src "libresoc.v:140613.3-140624.6" + process $proc$libresoc.v:140613$6441 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:130885.5-130885.29" + attribute \src "libresoc.v:140614.5-140614.29" switch \initial - attribute \src "libresoc.v:130885.9-130885.17" + attribute \src "libresoc.v:140614.9-140614.17" case 1'1 case end @@ -211345,97 +227158,97 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$100 $and$libresoc.v:130343$5878_Y - connect \$102 $and$libresoc.v:130344$5879_Y - connect \$104 $and$libresoc.v:130345$5880_Y - connect \$106 $and$libresoc.v:130346$5881_Y - connect \$108 $and$libresoc.v:130347$5882_Y - connect \$10 $or$libresoc.v:130348$5883_Y - connect \$110 $and$libresoc.v:130349$5884_Y - connect \$112 $and$libresoc.v:130350$5885_Y - connect \$114 $and$libresoc.v:130351$5886_Y - connect \$116 $and$libresoc.v:130352$5887_Y - connect \$118 $and$libresoc.v:130353$5888_Y - connect \$120 $and$libresoc.v:130354$5889_Y - connect \$122 $and$libresoc.v:130355$5890_Y - connect \$124 $and$libresoc.v:130356$5891_Y - connect \$126 $eq$libresoc.v:130357$5892_Y - connect \$128 $and$libresoc.v:130358$5893_Y - connect \$12 $or$libresoc.v:130359$5894_Y - connect \$130 $and$libresoc.v:130360$5895_Y - connect \$132 $and$libresoc.v:130361$5896_Y - connect \$134 $or$libresoc.v:130362$5897_Y - connect \$136 $or$libresoc.v:130363$5898_Y - connect \$138 $or$libresoc.v:130364$5899_Y - connect \$140 $and$libresoc.v:130365$5900_Y - connect \$142 $and$libresoc.v:130366$5901_Y - connect \$145 $or$libresoc.v:130367$5902_Y - connect \$147 $or$libresoc.v:130368$5903_Y - connect \$144 $not$libresoc.v:130369$5904_Y - connect \$14 $or$libresoc.v:130370$5905_Y - connect \$150 $and$libresoc.v:130371$5906_Y - connect \$152 $or$libresoc.v:130372$5907_Y - connect \$154 $and$libresoc.v:130373$5908_Y - connect \$156 $not$libresoc.v:130374$5909_Y - connect \$158 $or$libresoc.v:130375$5910_Y - connect \$160 $and$libresoc.v:130376$5911_Y - connect \$162 $eq$libresoc.v:130377$5912_Y - connect \$164 $and$libresoc.v:130378$5913_Y - connect \$167 $eq$libresoc.v:130379$5914_Y - connect \$16 $or$libresoc.v:130380$5915_Y - connect \$169 $and$libresoc.v:130381$5916_Y - connect \$171 $and$libresoc.v:130382$5917_Y - connect \$173 $and$libresoc.v:130383$5918_Y - connect \$175 $pos$libresoc.v:130384$5920_Y - connect \$177 $and$libresoc.v:130385$5921_Y - connect \$186 $pos$libresoc.v:130386$5923_Y - connect \$188 $pos$libresoc.v:130387$5924_Y - connect \$18 $or$libresoc.v:130388$5925_Y - connect \$190 $pos$libresoc.v:130389$5926_Y - connect \$192 $eq$libresoc.v:130390$5927_Y - connect \$194 $pos$libresoc.v:130391$5929_Y - connect \$196 $pos$libresoc.v:130392$5930_Y - connect \$198 $pos$libresoc.v:130393$5931_Y - connect \$20 $or$libresoc.v:130394$5932_Y - connect \$22 $eq$libresoc.v:130395$5933_Y - connect \$24 $eq$libresoc.v:130396$5934_Y - connect \$26 $and$libresoc.v:130397$5935_Y - connect \$28 $and$libresoc.v:130398$5936_Y - connect \$30 $not$libresoc.v:130399$5937_Y - connect \$32 $and$libresoc.v:130400$5938_Y - connect \$34 $not$libresoc.v:130401$5939_Y - connect \$36 $and$libresoc.v:130402$5940_Y - connect \$39 $not$libresoc.v:130403$5941_Y - connect \$41 $eq$libresoc.v:130404$5942_Y - connect \$43 $and$libresoc.v:130405$5943_Y - connect \$45 $or$libresoc.v:130406$5944_Y - connect \$47 $not$libresoc.v:130407$5945_Y - connect \$49 $eq$libresoc.v:130408$5946_Y - connect \$51 $and$libresoc.v:130409$5947_Y - connect \$53 $or$libresoc.v:130410$5948_Y - connect \$55 $or$libresoc.v:130411$5949_Y - connect \$57 $and$libresoc.v:130412$5950_Y - connect \$59 $or$libresoc.v:130413$5951_Y - connect \$61 $or$libresoc.v:130414$5952_Y - connect \$63 $or$libresoc.v:130415$5953_Y - connect \$65 $ternary$libresoc.v:130416$5954_Y - connect \$67 $ternary$libresoc.v:130417$5955_Y - connect \$69 $ternary$libresoc.v:130418$5956_Y - connect \$71 $ternary$libresoc.v:130419$5957_Y - connect \$74 $add$libresoc.v:130420$5958_Y - connect \$76 $and$libresoc.v:130421$5959_Y - connect \$78 $not$libresoc.v:130422$5960_Y - connect \$80 $and$libresoc.v:130423$5961_Y - connect \$82 $not$libresoc.v:130424$5962_Y - connect \$84 $and$libresoc.v:130425$5963_Y - connect \$86 $and$libresoc.v:130426$5964_Y - connect \$88 $and$libresoc.v:130427$5965_Y - connect \$8 $or$libresoc.v:130428$5966_Y - connect \$90 $or$libresoc.v:130429$5967_Y - connect \$93 $or$libresoc.v:130430$5968_Y - connect \$92 $not$libresoc.v:130431$5969_Y - connect \$96 $and$libresoc.v:130432$5970_Y - connect \$98 $not$libresoc.v:130433$5971_Y + connect \$100 $and$libresoc.v:140072$6200_Y + connect \$102 $and$libresoc.v:140073$6201_Y + connect \$104 $and$libresoc.v:140074$6202_Y + connect \$106 $and$libresoc.v:140075$6203_Y + connect \$108 $and$libresoc.v:140076$6204_Y + connect \$10 $or$libresoc.v:140077$6205_Y + connect \$110 $and$libresoc.v:140078$6206_Y + connect \$112 $and$libresoc.v:140079$6207_Y + connect \$114 $and$libresoc.v:140080$6208_Y + connect \$116 $and$libresoc.v:140081$6209_Y + connect \$118 $and$libresoc.v:140082$6210_Y + connect \$120 $and$libresoc.v:140083$6211_Y + connect \$122 $and$libresoc.v:140084$6212_Y + connect \$124 $and$libresoc.v:140085$6213_Y + connect \$126 $eq$libresoc.v:140086$6214_Y + connect \$128 $and$libresoc.v:140087$6215_Y + connect \$12 $or$libresoc.v:140088$6216_Y + connect \$130 $and$libresoc.v:140089$6217_Y + connect \$132 $and$libresoc.v:140090$6218_Y + connect \$134 $or$libresoc.v:140091$6219_Y + connect \$136 $or$libresoc.v:140092$6220_Y + connect \$138 $or$libresoc.v:140093$6221_Y + connect \$140 $and$libresoc.v:140094$6222_Y + connect \$142 $and$libresoc.v:140095$6223_Y + connect \$145 $or$libresoc.v:140096$6224_Y + connect \$147 $or$libresoc.v:140097$6225_Y + connect \$144 $not$libresoc.v:140098$6226_Y + connect \$14 $or$libresoc.v:140099$6227_Y + connect \$150 $and$libresoc.v:140100$6228_Y + connect \$152 $or$libresoc.v:140101$6229_Y + connect \$154 $and$libresoc.v:140102$6230_Y + connect \$156 $not$libresoc.v:140103$6231_Y + connect \$158 $or$libresoc.v:140104$6232_Y + connect \$160 $and$libresoc.v:140105$6233_Y + connect \$162 $eq$libresoc.v:140106$6234_Y + connect \$164 $and$libresoc.v:140107$6235_Y + connect \$167 $eq$libresoc.v:140108$6236_Y + connect \$16 $or$libresoc.v:140109$6237_Y + connect \$169 $and$libresoc.v:140110$6238_Y + connect \$171 $and$libresoc.v:140111$6239_Y + connect \$173 $and$libresoc.v:140112$6240_Y + connect \$175 $pos$libresoc.v:140113$6242_Y + connect \$177 $and$libresoc.v:140114$6243_Y + connect \$186 $pos$libresoc.v:140115$6245_Y + connect \$188 $pos$libresoc.v:140116$6246_Y + connect \$18 $or$libresoc.v:140117$6247_Y + connect \$190 $pos$libresoc.v:140118$6248_Y + connect \$192 $eq$libresoc.v:140119$6249_Y + connect \$194 $pos$libresoc.v:140120$6251_Y + connect \$196 $pos$libresoc.v:140121$6252_Y + connect \$198 $pos$libresoc.v:140122$6253_Y + connect \$20 $or$libresoc.v:140123$6254_Y + connect \$22 $eq$libresoc.v:140124$6255_Y + connect \$24 $eq$libresoc.v:140125$6256_Y + connect \$26 $and$libresoc.v:140126$6257_Y + connect \$28 $and$libresoc.v:140127$6258_Y + connect \$30 $not$libresoc.v:140128$6259_Y + connect \$32 $and$libresoc.v:140129$6260_Y + connect \$34 $not$libresoc.v:140130$6261_Y + connect \$36 $and$libresoc.v:140131$6262_Y + connect \$39 $not$libresoc.v:140132$6263_Y + connect \$41 $eq$libresoc.v:140133$6264_Y + connect \$43 $and$libresoc.v:140134$6265_Y + connect \$45 $or$libresoc.v:140135$6266_Y + connect \$47 $not$libresoc.v:140136$6267_Y + connect \$49 $eq$libresoc.v:140137$6268_Y + connect \$51 $and$libresoc.v:140138$6269_Y + connect \$53 $or$libresoc.v:140139$6270_Y + connect \$55 $or$libresoc.v:140140$6271_Y + connect \$57 $and$libresoc.v:140141$6272_Y + connect \$59 $or$libresoc.v:140142$6273_Y + connect \$61 $or$libresoc.v:140143$6274_Y + connect \$63 $or$libresoc.v:140144$6275_Y + connect \$65 $ternary$libresoc.v:140145$6276_Y + connect \$67 $ternary$libresoc.v:140146$6277_Y + connect \$69 $ternary$libresoc.v:140147$6278_Y + connect \$71 $ternary$libresoc.v:140148$6279_Y + connect \$74 $add$libresoc.v:140149$6280_Y + connect \$76 $and$libresoc.v:140150$6281_Y + connect \$78 $not$libresoc.v:140151$6282_Y + connect \$80 $and$libresoc.v:140152$6283_Y + connect \$82 $not$libresoc.v:140153$6284_Y + connect \$84 $and$libresoc.v:140154$6285_Y + connect \$86 $and$libresoc.v:140155$6286_Y + connect \$88 $and$libresoc.v:140156$6287_Y + connect \$8 $or$libresoc.v:140157$6288_Y + connect \$90 $or$libresoc.v:140158$6289_Y + connect \$93 $or$libresoc.v:140159$6290_Y + connect \$92 $not$libresoc.v:140160$6291_Y + connect \$96 $and$libresoc.v:140161$6292_Y + connect \$98 $not$libresoc.v:140162$6293_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 @@ -211496,407 +227309,407 @@ module \ldst0 connect \reset_o \$10 connect \reset_i \$8 end -attribute \src "libresoc.v:130959.1-131546.10" +attribute \src "libresoc.v:140688.1-141275.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:130960.7-130960.20" + attribute \src "libresoc.v:140689.7-140689.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $10\mask[9:9] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $11\mask[10:10] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $12\mask[11:11] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $13\mask[12:12] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $14\mask[13:13] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $15\mask[14:14] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $16\mask[15:15] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $17\mask[16:16] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $18\mask[17:17] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $19\mask[18:18] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $1\mask[0:0] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $20\mask[19:19] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $21\mask[20:20] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $22\mask[21:21] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $23\mask[22:22] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $24\mask[23:23] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $25\mask[24:24] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $26\mask[25:25] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $27\mask[26:26] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $28\mask[27:27] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $29\mask[28:28] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $2\mask[1:1] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $30\mask[29:29] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $31\mask[30:30] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $32\mask[31:31] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $33\mask[32:32] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $34\mask[33:33] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $35\mask[34:34] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $36\mask[35:35] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $37\mask[36:36] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $38\mask[37:37] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $39\mask[38:38] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $3\mask[2:2] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $40\mask[39:39] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $41\mask[40:40] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $42\mask[41:41] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $43\mask[42:42] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $44\mask[43:43] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $45\mask[44:44] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $46\mask[45:45] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $47\mask[46:46] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $48\mask[47:47] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $49\mask[48:48] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $4\mask[3:3] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $50\mask[49:49] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $51\mask[50:50] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $52\mask[51:51] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $53\mask[52:52] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $54\mask[53:53] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $55\mask[54:54] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $56\mask[55:55] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $57\mask[56:56] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $58\mask[57:57] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $59\mask[58:58] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $5\mask[4:4] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $60\mask[59:59] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $61\mask[60:60] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $62\mask[61:61] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $63\mask[62:62] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $64\mask[63:63] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $6\mask[5:5] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $7\mask[6:6] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $8\mask[7:7] - attribute \src "libresoc.v:131158.3-131545.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $9\mask[8:8] - attribute \src "libresoc.v:131094.17-131094.96" - wire $gt$libresoc.v:131094$6156_Y - attribute \src "libresoc.v:131095.18-131095.98" - wire $gt$libresoc.v:131095$6157_Y - attribute \src "libresoc.v:131096.19-131096.99" - wire $gt$libresoc.v:131096$6158_Y - attribute \src "libresoc.v:131097.19-131097.99" - wire $gt$libresoc.v:131097$6159_Y - attribute \src "libresoc.v:131098.19-131098.99" - wire $gt$libresoc.v:131098$6160_Y - attribute \src "libresoc.v:131099.19-131099.99" - wire $gt$libresoc.v:131099$6161_Y - attribute \src "libresoc.v:131100.19-131100.99" - wire $gt$libresoc.v:131100$6162_Y - attribute \src "libresoc.v:131101.19-131101.99" - wire $gt$libresoc.v:131101$6163_Y - attribute \src "libresoc.v:131102.19-131102.99" - wire $gt$libresoc.v:131102$6164_Y - attribute \src "libresoc.v:131103.19-131103.99" - wire $gt$libresoc.v:131103$6165_Y - attribute \src "libresoc.v:131104.19-131104.99" - wire $gt$libresoc.v:131104$6166_Y - attribute \src "libresoc.v:131105.18-131105.97" - wire $gt$libresoc.v:131105$6167_Y - attribute \src "libresoc.v:131106.19-131106.99" - wire $gt$libresoc.v:131106$6168_Y - attribute \src "libresoc.v:131107.19-131107.99" - wire $gt$libresoc.v:131107$6169_Y - attribute \src "libresoc.v:131108.19-131108.99" - wire $gt$libresoc.v:131108$6170_Y - attribute \src "libresoc.v:131109.19-131109.99" - wire $gt$libresoc.v:131109$6171_Y - attribute \src "libresoc.v:131110.19-131110.99" - wire $gt$libresoc.v:131110$6172_Y - attribute \src "libresoc.v:131111.18-131111.97" - wire $gt$libresoc.v:131111$6173_Y - attribute \src "libresoc.v:131112.18-131112.97" - wire $gt$libresoc.v:131112$6174_Y - attribute \src "libresoc.v:131113.18-131113.97" - wire $gt$libresoc.v:131113$6175_Y - attribute \src "libresoc.v:131114.17-131114.96" - wire $gt$libresoc.v:131114$6176_Y - attribute \src "libresoc.v:131115.18-131115.97" - wire $gt$libresoc.v:131115$6177_Y - attribute \src "libresoc.v:131116.18-131116.97" - wire $gt$libresoc.v:131116$6178_Y - attribute \src "libresoc.v:131117.18-131117.97" - wire $gt$libresoc.v:131117$6179_Y - attribute \src "libresoc.v:131118.18-131118.97" - wire $gt$libresoc.v:131118$6180_Y - attribute \src "libresoc.v:131119.18-131119.97" - wire $gt$libresoc.v:131119$6181_Y - attribute \src "libresoc.v:131120.18-131120.97" - wire $gt$libresoc.v:131120$6182_Y - attribute \src "libresoc.v:131121.18-131121.97" - wire $gt$libresoc.v:131121$6183_Y - attribute \src "libresoc.v:131122.18-131122.98" - wire $gt$libresoc.v:131122$6184_Y - attribute \src "libresoc.v:131123.18-131123.98" - wire $gt$libresoc.v:131123$6185_Y - attribute \src "libresoc.v:131124.18-131124.98" - wire $gt$libresoc.v:131124$6186_Y - attribute \src "libresoc.v:131125.17-131125.96" - wire $gt$libresoc.v:131125$6187_Y - attribute \src "libresoc.v:131126.18-131126.98" - wire $gt$libresoc.v:131126$6188_Y - attribute \src "libresoc.v:131127.18-131127.98" - wire $gt$libresoc.v:131127$6189_Y - attribute \src "libresoc.v:131128.18-131128.98" - wire $gt$libresoc.v:131128$6190_Y - attribute \src "libresoc.v:131129.18-131129.98" - wire $gt$libresoc.v:131129$6191_Y - attribute \src "libresoc.v:131130.18-131130.98" - wire $gt$libresoc.v:131130$6192_Y - attribute \src "libresoc.v:131131.18-131131.98" - wire $gt$libresoc.v:131131$6193_Y - attribute \src "libresoc.v:131132.18-131132.98" - wire $gt$libresoc.v:131132$6194_Y - attribute \src "libresoc.v:131133.18-131133.98" - wire $gt$libresoc.v:131133$6195_Y - attribute \src "libresoc.v:131134.18-131134.98" - wire $gt$libresoc.v:131134$6196_Y - attribute \src "libresoc.v:131135.18-131135.98" - wire $gt$libresoc.v:131135$6197_Y - attribute \src "libresoc.v:131136.17-131136.96" - wire $gt$libresoc.v:131136$6198_Y - attribute \src "libresoc.v:131137.18-131137.98" - wire $gt$libresoc.v:131137$6199_Y - attribute \src "libresoc.v:131138.18-131138.98" - wire $gt$libresoc.v:131138$6200_Y - attribute \src "libresoc.v:131139.18-131139.98" - wire $gt$libresoc.v:131139$6201_Y - attribute \src "libresoc.v:131140.18-131140.98" - wire $gt$libresoc.v:131140$6202_Y - attribute \src "libresoc.v:131141.18-131141.98" - wire $gt$libresoc.v:131141$6203_Y - attribute \src "libresoc.v:131142.18-131142.98" - wire $gt$libresoc.v:131142$6204_Y - attribute \src "libresoc.v:131143.18-131143.98" - wire $gt$libresoc.v:131143$6205_Y - attribute \src "libresoc.v:131144.18-131144.98" - wire $gt$libresoc.v:131144$6206_Y - attribute \src "libresoc.v:131145.18-131145.98" - wire $gt$libresoc.v:131145$6207_Y - attribute \src "libresoc.v:131146.18-131146.98" - wire $gt$libresoc.v:131146$6208_Y - attribute \src "libresoc.v:131147.17-131147.96" - wire $gt$libresoc.v:131147$6209_Y - attribute \src "libresoc.v:131148.18-131148.98" - wire $gt$libresoc.v:131148$6210_Y - attribute \src "libresoc.v:131149.18-131149.98" - wire $gt$libresoc.v:131149$6211_Y - attribute \src "libresoc.v:131150.18-131150.98" - wire $gt$libresoc.v:131150$6212_Y - attribute \src "libresoc.v:131151.18-131151.98" - wire $gt$libresoc.v:131151$6213_Y - attribute \src "libresoc.v:131152.18-131152.98" - wire $gt$libresoc.v:131152$6214_Y - attribute \src "libresoc.v:131153.18-131153.98" - wire $gt$libresoc.v:131153$6215_Y - attribute \src "libresoc.v:131154.18-131154.98" - wire $gt$libresoc.v:131154$6216_Y - attribute \src "libresoc.v:131155.18-131155.98" - wire $gt$libresoc.v:131155$6217_Y - attribute \src "libresoc.v:131156.18-131156.98" - wire $gt$libresoc.v:131156$6218_Y - attribute \src "libresoc.v:131157.18-131157.98" - wire $gt$libresoc.v:131157$6219_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "libresoc.v:140823.17-140823.96" + wire $gt$libresoc.v:140823$6478_Y + attribute \src "libresoc.v:140824.18-140824.98" + wire $gt$libresoc.v:140824$6479_Y + attribute \src "libresoc.v:140825.19-140825.99" + wire $gt$libresoc.v:140825$6480_Y + attribute \src "libresoc.v:140826.19-140826.99" + wire $gt$libresoc.v:140826$6481_Y + attribute \src "libresoc.v:140827.19-140827.99" + wire $gt$libresoc.v:140827$6482_Y + attribute \src "libresoc.v:140828.19-140828.99" + wire $gt$libresoc.v:140828$6483_Y + attribute \src "libresoc.v:140829.19-140829.99" + wire $gt$libresoc.v:140829$6484_Y + attribute \src "libresoc.v:140830.19-140830.99" + wire $gt$libresoc.v:140830$6485_Y + attribute \src "libresoc.v:140831.19-140831.99" + wire $gt$libresoc.v:140831$6486_Y + attribute \src "libresoc.v:140832.19-140832.99" + wire $gt$libresoc.v:140832$6487_Y + attribute \src "libresoc.v:140833.19-140833.99" + wire $gt$libresoc.v:140833$6488_Y + attribute \src "libresoc.v:140834.18-140834.97" + wire $gt$libresoc.v:140834$6489_Y + attribute \src "libresoc.v:140835.19-140835.99" + wire $gt$libresoc.v:140835$6490_Y + attribute \src "libresoc.v:140836.19-140836.99" + wire $gt$libresoc.v:140836$6491_Y + attribute \src "libresoc.v:140837.19-140837.99" + wire $gt$libresoc.v:140837$6492_Y + attribute \src "libresoc.v:140838.19-140838.99" + wire $gt$libresoc.v:140838$6493_Y + attribute \src "libresoc.v:140839.19-140839.99" + wire $gt$libresoc.v:140839$6494_Y + attribute \src "libresoc.v:140840.18-140840.97" + wire $gt$libresoc.v:140840$6495_Y + attribute \src "libresoc.v:140841.18-140841.97" + wire $gt$libresoc.v:140841$6496_Y + attribute \src "libresoc.v:140842.18-140842.97" + wire $gt$libresoc.v:140842$6497_Y + attribute \src "libresoc.v:140843.17-140843.96" + wire $gt$libresoc.v:140843$6498_Y + attribute \src "libresoc.v:140844.18-140844.97" + wire $gt$libresoc.v:140844$6499_Y + attribute \src "libresoc.v:140845.18-140845.97" + wire $gt$libresoc.v:140845$6500_Y + attribute \src "libresoc.v:140846.18-140846.97" + wire $gt$libresoc.v:140846$6501_Y + attribute \src "libresoc.v:140847.18-140847.97" + wire $gt$libresoc.v:140847$6502_Y + attribute \src "libresoc.v:140848.18-140848.97" + wire $gt$libresoc.v:140848$6503_Y + attribute \src "libresoc.v:140849.18-140849.97" + wire $gt$libresoc.v:140849$6504_Y + attribute \src "libresoc.v:140850.18-140850.97" + wire $gt$libresoc.v:140850$6505_Y + attribute \src "libresoc.v:140851.18-140851.98" + wire $gt$libresoc.v:140851$6506_Y + attribute \src "libresoc.v:140852.18-140852.98" + wire $gt$libresoc.v:140852$6507_Y + attribute \src "libresoc.v:140853.18-140853.98" + wire $gt$libresoc.v:140853$6508_Y + attribute \src "libresoc.v:140854.17-140854.96" + wire $gt$libresoc.v:140854$6509_Y + attribute \src "libresoc.v:140855.18-140855.98" + wire $gt$libresoc.v:140855$6510_Y + attribute \src "libresoc.v:140856.18-140856.98" + wire $gt$libresoc.v:140856$6511_Y + attribute \src "libresoc.v:140857.18-140857.98" + wire $gt$libresoc.v:140857$6512_Y + attribute \src "libresoc.v:140858.18-140858.98" + wire $gt$libresoc.v:140858$6513_Y + attribute \src "libresoc.v:140859.18-140859.98" + wire $gt$libresoc.v:140859$6514_Y + attribute \src "libresoc.v:140860.18-140860.98" + wire $gt$libresoc.v:140860$6515_Y + attribute \src "libresoc.v:140861.18-140861.98" + wire $gt$libresoc.v:140861$6516_Y + attribute \src "libresoc.v:140862.18-140862.98" + wire $gt$libresoc.v:140862$6517_Y + attribute \src "libresoc.v:140863.18-140863.98" + wire $gt$libresoc.v:140863$6518_Y + attribute \src "libresoc.v:140864.18-140864.98" + wire $gt$libresoc.v:140864$6519_Y + attribute \src "libresoc.v:140865.17-140865.96" + wire $gt$libresoc.v:140865$6520_Y + attribute \src "libresoc.v:140866.18-140866.98" + wire $gt$libresoc.v:140866$6521_Y + attribute \src "libresoc.v:140867.18-140867.98" + wire $gt$libresoc.v:140867$6522_Y + attribute \src "libresoc.v:140868.18-140868.98" + wire $gt$libresoc.v:140868$6523_Y + attribute \src "libresoc.v:140869.18-140869.98" + wire $gt$libresoc.v:140869$6524_Y + attribute \src "libresoc.v:140870.18-140870.98" + wire $gt$libresoc.v:140870$6525_Y + attribute \src "libresoc.v:140871.18-140871.98" + wire $gt$libresoc.v:140871$6526_Y + attribute \src "libresoc.v:140872.18-140872.98" + wire $gt$libresoc.v:140872$6527_Y + attribute \src "libresoc.v:140873.18-140873.98" + wire $gt$libresoc.v:140873$6528_Y + attribute \src "libresoc.v:140874.18-140874.98" + wire $gt$libresoc.v:140874$6529_Y + attribute \src "libresoc.v:140875.18-140875.98" + wire $gt$libresoc.v:140875$6530_Y + attribute \src "libresoc.v:140876.17-140876.96" + wire $gt$libresoc.v:140876$6531_Y + attribute \src "libresoc.v:140877.18-140877.98" + wire $gt$libresoc.v:140877$6532_Y + attribute \src "libresoc.v:140878.18-140878.98" + wire $gt$libresoc.v:140878$6533_Y + attribute \src "libresoc.v:140879.18-140879.98" + wire $gt$libresoc.v:140879$6534_Y + attribute \src "libresoc.v:140880.18-140880.98" + wire $gt$libresoc.v:140880$6535_Y + attribute \src "libresoc.v:140881.18-140881.98" + wire $gt$libresoc.v:140881$6536_Y + attribute \src "libresoc.v:140882.18-140882.98" + wire $gt$libresoc.v:140882$6537_Y + attribute \src "libresoc.v:140883.18-140883.98" + wire $gt$libresoc.v:140883$6538_Y + attribute \src "libresoc.v:140884.18-140884.98" + wire $gt$libresoc.v:140884$6539_Y + attribute \src "libresoc.v:140885.18-140885.98" + wire $gt$libresoc.v:140885$6540_Y + attribute \src "libresoc.v:140886.18-140886.98" + wire $gt$libresoc.v:140886$6541_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:130960.7-130960.15" + attribute \src "libresoc.v:140689.7-140689.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131094$6156 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140823$6478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211904,10 +227717,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:131094$6156_Y + connect \Y $gt$libresoc.v:140823$6478_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131095$6157 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140824$6479 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211915,10 +227728,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:131095$6157_Y + connect \Y $gt$libresoc.v:140824$6479_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131096$6158 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140825$6480 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211926,10 +227739,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:131096$6158_Y + connect \Y $gt$libresoc.v:140825$6480_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131097$6159 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140826$6481 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211937,10 +227750,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:131097$6159_Y + connect \Y $gt$libresoc.v:140826$6481_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131098$6160 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140827$6482 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211948,10 +227761,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:131098$6160_Y + connect \Y $gt$libresoc.v:140827$6482_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131099$6161 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140828$6483 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211959,10 +227772,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:131099$6161_Y + connect \Y $gt$libresoc.v:140828$6483_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131100$6162 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140829$6484 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211970,10 +227783,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:131100$6162_Y + connect \Y $gt$libresoc.v:140829$6484_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131101$6163 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140830$6485 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211981,10 +227794,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:131101$6163_Y + connect \Y $gt$libresoc.v:140830$6485_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131102$6164 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140831$6486 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211992,10 +227805,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:131102$6164_Y + connect \Y $gt$libresoc.v:140831$6486_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131103$6165 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140832$6487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212003,10 +227816,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:131103$6165_Y + connect \Y $gt$libresoc.v:140832$6487_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131104$6166 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140833$6488 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212014,10 +227827,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:131104$6166_Y + connect \Y $gt$libresoc.v:140833$6488_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131105$6167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140834$6489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212025,10 +227838,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:131105$6167_Y + connect \Y $gt$libresoc.v:140834$6489_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131106$6168 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140835$6490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212036,10 +227849,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:131106$6168_Y + connect \Y $gt$libresoc.v:140835$6490_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131107$6169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140836$6491 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212047,10 +227860,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:131107$6169_Y + connect \Y $gt$libresoc.v:140836$6491_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131108$6170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140837$6492 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212058,10 +227871,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:131108$6170_Y + connect \Y $gt$libresoc.v:140837$6492_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131109$6171 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140838$6493 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212069,10 +227882,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:131109$6171_Y + connect \Y $gt$libresoc.v:140838$6493_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131110$6172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140839$6494 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212080,10 +227893,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:131110$6172_Y + connect \Y $gt$libresoc.v:140839$6494_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131111$6173 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140840$6495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212091,10 +227904,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:131111$6173_Y + connect \Y $gt$libresoc.v:140840$6495_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131112$6174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140841$6496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212102,10 +227915,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:131112$6174_Y + connect \Y $gt$libresoc.v:140841$6496_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131113$6175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140842$6497 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212113,10 +227926,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:131113$6175_Y + connect \Y $gt$libresoc.v:140842$6497_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131114$6176 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140843$6498 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212124,10 +227937,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:131114$6176_Y + connect \Y $gt$libresoc.v:140843$6498_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131115$6177 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140844$6499 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212135,10 +227948,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:131115$6177_Y + connect \Y $gt$libresoc.v:140844$6499_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131116$6178 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140845$6500 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212146,10 +227959,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:131116$6178_Y + connect \Y $gt$libresoc.v:140845$6500_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131117$6179 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140846$6501 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212157,10 +227970,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:131117$6179_Y + connect \Y $gt$libresoc.v:140846$6501_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131118$6180 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140847$6502 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212168,10 +227981,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:131118$6180_Y + connect \Y $gt$libresoc.v:140847$6502_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131119$6181 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140848$6503 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212179,10 +227992,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:131119$6181_Y + connect \Y $gt$libresoc.v:140848$6503_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131120$6182 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140849$6504 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212190,10 +228003,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:131120$6182_Y + connect \Y $gt$libresoc.v:140849$6504_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131121$6183 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140850$6505 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212201,10 +228014,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:131121$6183_Y + connect \Y $gt$libresoc.v:140850$6505_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131122$6184 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140851$6506 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212212,10 +228025,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:131122$6184_Y + connect \Y $gt$libresoc.v:140851$6506_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131123$6185 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140852$6507 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212223,10 +228036,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:131123$6185_Y + connect \Y $gt$libresoc.v:140852$6507_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131124$6186 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140853$6508 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212234,10 +228047,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:131124$6186_Y + connect \Y $gt$libresoc.v:140853$6508_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131125$6187 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140854$6509 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212245,10 +228058,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:131125$6187_Y + connect \Y $gt$libresoc.v:140854$6509_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131126$6188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140855$6510 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212256,10 +228069,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:131126$6188_Y + connect \Y $gt$libresoc.v:140855$6510_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131127$6189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140856$6511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212267,10 +228080,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:131127$6189_Y + connect \Y $gt$libresoc.v:140856$6511_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131128$6190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140857$6512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212278,10 +228091,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:131128$6190_Y + connect \Y $gt$libresoc.v:140857$6512_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131129$6191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140858$6513 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212289,10 +228102,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:131129$6191_Y + connect \Y $gt$libresoc.v:140858$6513_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131130$6192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140859$6514 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212300,10 +228113,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:131130$6192_Y + connect \Y $gt$libresoc.v:140859$6514_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131131$6193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140860$6515 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212311,10 +228124,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:131131$6193_Y + connect \Y $gt$libresoc.v:140860$6515_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131132$6194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140861$6516 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212322,10 +228135,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:131132$6194_Y + connect \Y $gt$libresoc.v:140861$6516_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131133$6195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140862$6517 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212333,10 +228146,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:131133$6195_Y + connect \Y $gt$libresoc.v:140862$6517_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131134$6196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140863$6518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212344,10 +228157,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:131134$6196_Y + connect \Y $gt$libresoc.v:140863$6518_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131135$6197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140864$6519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212355,10 +228168,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:131135$6197_Y + connect \Y $gt$libresoc.v:140864$6519_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131136$6198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140865$6520 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212366,10 +228179,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:131136$6198_Y + connect \Y $gt$libresoc.v:140865$6520_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131137$6199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140866$6521 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212377,10 +228190,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:131137$6199_Y + connect \Y $gt$libresoc.v:140866$6521_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131138$6200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140867$6522 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212388,10 +228201,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:131138$6200_Y + connect \Y $gt$libresoc.v:140867$6522_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131139$6201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140868$6523 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212399,10 +228212,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:131139$6201_Y + connect \Y $gt$libresoc.v:140868$6523_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131140$6202 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140869$6524 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212410,10 +228223,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:131140$6202_Y + connect \Y $gt$libresoc.v:140869$6524_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131141$6203 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140870$6525 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212421,10 +228234,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:131141$6203_Y + connect \Y $gt$libresoc.v:140870$6525_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131142$6204 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140871$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212432,10 +228245,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:131142$6204_Y + connect \Y $gt$libresoc.v:140871$6526_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131143$6205 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140872$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212443,10 +228256,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:131143$6205_Y + connect \Y $gt$libresoc.v:140872$6527_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131144$6206 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140873$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212454,10 +228267,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:131144$6206_Y + connect \Y $gt$libresoc.v:140873$6528_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131145$6207 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140874$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212465,10 +228278,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:131145$6207_Y + connect \Y $gt$libresoc.v:140874$6529_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131146$6208 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140875$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212476,10 +228289,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:131146$6208_Y + connect \Y $gt$libresoc.v:140875$6530_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131147$6209 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140876$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212487,10 +228300,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:131147$6209_Y + connect \Y $gt$libresoc.v:140876$6531_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131148$6210 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140877$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212498,10 +228311,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:131148$6210_Y + connect \Y $gt$libresoc.v:140877$6532_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131149$6211 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140878$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212509,10 +228322,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:131149$6211_Y + connect \Y $gt$libresoc.v:140878$6533_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131150$6212 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140879$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212520,10 +228333,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:131150$6212_Y + connect \Y $gt$libresoc.v:140879$6534_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131151$6213 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140880$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212531,10 +228344,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:131151$6213_Y + connect \Y $gt$libresoc.v:140880$6535_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131152$6214 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140881$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212542,10 +228355,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:131152$6214_Y + connect \Y $gt$libresoc.v:140881$6536_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131153$6215 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140882$6537 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212553,10 +228366,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:131153$6215_Y + connect \Y $gt$libresoc.v:140882$6537_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131154$6216 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140883$6538 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212564,10 +228377,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:131154$6216_Y + connect \Y $gt$libresoc.v:140883$6538_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131155$6217 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140884$6539 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212575,10 +228388,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:131155$6217_Y + connect \Y $gt$libresoc.v:140884$6539_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131156$6218 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140885$6540 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212586,10 +228399,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:131156$6218_Y + connect \Y $gt$libresoc.v:140885$6540_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131157$6219 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140886$6541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -212597,18 +228410,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:131157$6219_Y + connect \Y $gt$libresoc.v:140886$6541_Y end - attribute \src "libresoc.v:130960.7-130960.20" - process $proc$libresoc.v:130960$6221 + attribute \src "libresoc.v:140689.7-140689.20" + process $proc$libresoc.v:140689$6543 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131158.3-131545.6" - process $proc$libresoc.v:131158$6220 + attribute \src "libresoc.v:140887.3-141274.6" + process $proc$libresoc.v:140887$6542 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -212675,13 +228488,13 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:131159.5-131159.29" + attribute \src "libresoc.v:140888.5-140888.29" switch \initial - attribute \src "libresoc.v:131159.9-131159.17" + attribute \src "libresoc.v:140888.9-140888.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212690,7 +228503,7 @@ module \left_mask case assign $1\mask[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212699,7 +228512,7 @@ module \left_mask case assign $2\mask[1:1] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212708,7 +228521,7 @@ module \left_mask case assign $3\mask[2:2] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212717,7 +228530,7 @@ module \left_mask case assign $4\mask[3:3] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212726,7 +228539,7 @@ module \left_mask case assign $5\mask[4:4] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212735,7 +228548,7 @@ module \left_mask case assign $6\mask[5:5] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212744,7 +228557,7 @@ module \left_mask case assign $7\mask[6:6] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212753,7 +228566,7 @@ module \left_mask case assign $8\mask[7:7] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212762,7 +228575,7 @@ module \left_mask case assign $9\mask[8:8] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212771,7 +228584,7 @@ module \left_mask case assign $10\mask[9:9] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212780,7 +228593,7 @@ module \left_mask case assign $11\mask[10:10] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212789,7 +228602,7 @@ module \left_mask case assign $12\mask[11:11] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212798,7 +228611,7 @@ module \left_mask case assign $13\mask[12:12] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212807,7 +228620,7 @@ module \left_mask case assign $14\mask[13:13] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212816,7 +228629,7 @@ module \left_mask case assign $15\mask[14:14] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212825,7 +228638,7 @@ module \left_mask case assign $16\mask[15:15] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212834,7 +228647,7 @@ module \left_mask case assign $17\mask[16:16] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$35 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212843,7 +228656,7 @@ module \left_mask case assign $18\mask[17:17] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212852,7 +228665,7 @@ module \left_mask case assign $19\mask[18:18] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212861,7 +228674,7 @@ module \left_mask case assign $20\mask[19:19] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212870,7 +228683,7 @@ module \left_mask case assign $21\mask[20:20] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212879,7 +228692,7 @@ module \left_mask case assign $22\mask[21:21] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212888,7 +228701,7 @@ module \left_mask case assign $23\mask[22:22] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$47 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212897,7 +228710,7 @@ module \left_mask case assign $24\mask[23:23] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212906,7 +228719,7 @@ module \left_mask case assign $25\mask[24:24] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$51 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212915,7 +228728,7 @@ module \left_mask case assign $26\mask[25:25] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$53 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212924,7 +228737,7 @@ module \left_mask case assign $27\mask[26:26] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212933,7 +228746,7 @@ module \left_mask case assign $28\mask[27:27] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212942,7 +228755,7 @@ module \left_mask case assign $29\mask[28:28] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212951,7 +228764,7 @@ module \left_mask case assign $30\mask[29:29] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212960,7 +228773,7 @@ module \left_mask case assign $31\mask[30:30] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212969,7 +228782,7 @@ module \left_mask case assign $32\mask[31:31] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$65 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212978,7 +228791,7 @@ module \left_mask case assign $33\mask[32:32] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212987,7 +228800,7 @@ module \left_mask case assign $34\mask[33:33] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -212996,7 +228809,7 @@ module \left_mask case assign $35\mask[34:34] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213005,7 +228818,7 @@ module \left_mask case assign $36\mask[35:35] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213014,7 +228827,7 @@ module \left_mask case assign $37\mask[36:36] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$75 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213023,7 +228836,7 @@ module \left_mask case assign $38\mask[37:37] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213032,7 +228845,7 @@ module \left_mask case assign $39\mask[38:38] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$79 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213041,7 +228854,7 @@ module \left_mask case assign $40\mask[39:39] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213050,7 +228863,7 @@ module \left_mask case assign $41\mask[40:40] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213059,7 +228872,7 @@ module \left_mask case assign $42\mask[41:41] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213068,7 +228881,7 @@ module \left_mask case assign $43\mask[42:42] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213077,7 +228890,7 @@ module \left_mask case assign $44\mask[43:43] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$89 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213086,7 +228899,7 @@ module \left_mask case assign $45\mask[44:44] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$91 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213095,7 +228908,7 @@ module \left_mask case assign $46\mask[45:45] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213104,7 +228917,7 @@ module \left_mask case assign $47\mask[46:46] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213113,7 +228926,7 @@ module \left_mask case assign $48\mask[47:47] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$97 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213122,7 +228935,7 @@ module \left_mask case assign $49\mask[48:48] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$99 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213131,7 +228944,7 @@ module \left_mask case assign $50\mask[49:49] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213140,7 +228953,7 @@ module \left_mask case assign $51\mask[50:50] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213149,7 +228962,7 @@ module \left_mask case assign $52\mask[51:51] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213158,7 +228971,7 @@ module \left_mask case assign $53\mask[52:52] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$107 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213167,7 +228980,7 @@ module \left_mask case assign $54\mask[53:53] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$109 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213176,7 +228989,7 @@ module \left_mask case assign $55\mask[54:54] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$111 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213185,7 +228998,7 @@ module \left_mask case assign $56\mask[55:55] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213194,7 +229007,7 @@ module \left_mask case assign $57\mask[56:56] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213203,7 +229016,7 @@ module \left_mask case assign $58\mask[57:57] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213212,7 +229025,7 @@ module \left_mask case assign $59\mask[58:58] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213221,7 +229034,7 @@ module \left_mask case assign $60\mask[59:59] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213230,7 +229043,7 @@ module \left_mask case assign $61\mask[60:60] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213239,7 +229052,7 @@ module \left_mask case assign $62\mask[61:61] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$125 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213248,7 +229061,7 @@ module \left_mask case assign $63\mask[62:62] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -213260,86 +229073,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:131094$6156_Y - connect \$99 $gt$libresoc.v:131095$6157_Y - connect \$101 $gt$libresoc.v:131096$6158_Y - connect \$103 $gt$libresoc.v:131097$6159_Y - connect \$105 $gt$libresoc.v:131098$6160_Y - connect \$107 $gt$libresoc.v:131099$6161_Y - connect \$109 $gt$libresoc.v:131100$6162_Y - connect \$111 $gt$libresoc.v:131101$6163_Y - connect \$113 $gt$libresoc.v:131102$6164_Y - connect \$115 $gt$libresoc.v:131103$6165_Y - connect \$117 $gt$libresoc.v:131104$6166_Y - connect \$11 $gt$libresoc.v:131105$6167_Y - connect \$119 $gt$libresoc.v:131106$6168_Y - connect \$121 $gt$libresoc.v:131107$6169_Y - connect \$123 $gt$libresoc.v:131108$6170_Y - connect \$125 $gt$libresoc.v:131109$6171_Y - connect \$127 $gt$libresoc.v:131110$6172_Y - connect \$13 $gt$libresoc.v:131111$6173_Y - connect \$15 $gt$libresoc.v:131112$6174_Y - connect \$17 $gt$libresoc.v:131113$6175_Y - connect \$1 $gt$libresoc.v:131114$6176_Y - connect \$19 $gt$libresoc.v:131115$6177_Y - connect \$21 $gt$libresoc.v:131116$6178_Y - connect \$23 $gt$libresoc.v:131117$6179_Y - connect \$25 $gt$libresoc.v:131118$6180_Y - connect \$27 $gt$libresoc.v:131119$6181_Y - connect \$29 $gt$libresoc.v:131120$6182_Y - connect \$31 $gt$libresoc.v:131121$6183_Y - connect \$33 $gt$libresoc.v:131122$6184_Y - connect \$35 $gt$libresoc.v:131123$6185_Y - connect \$37 $gt$libresoc.v:131124$6186_Y - connect \$3 $gt$libresoc.v:131125$6187_Y - connect \$39 $gt$libresoc.v:131126$6188_Y - connect \$41 $gt$libresoc.v:131127$6189_Y - connect \$43 $gt$libresoc.v:131128$6190_Y - connect \$45 $gt$libresoc.v:131129$6191_Y - connect \$47 $gt$libresoc.v:131130$6192_Y - connect \$49 $gt$libresoc.v:131131$6193_Y - connect \$51 $gt$libresoc.v:131132$6194_Y - connect \$53 $gt$libresoc.v:131133$6195_Y - connect \$55 $gt$libresoc.v:131134$6196_Y - connect \$57 $gt$libresoc.v:131135$6197_Y - connect \$5 $gt$libresoc.v:131136$6198_Y - connect \$59 $gt$libresoc.v:131137$6199_Y - connect \$61 $gt$libresoc.v:131138$6200_Y - connect \$63 $gt$libresoc.v:131139$6201_Y - connect \$65 $gt$libresoc.v:131140$6202_Y - connect \$67 $gt$libresoc.v:131141$6203_Y - connect \$69 $gt$libresoc.v:131142$6204_Y - connect \$71 $gt$libresoc.v:131143$6205_Y - connect \$73 $gt$libresoc.v:131144$6206_Y - connect \$75 $gt$libresoc.v:131145$6207_Y - connect \$77 $gt$libresoc.v:131146$6208_Y - connect \$7 $gt$libresoc.v:131147$6209_Y - connect \$79 $gt$libresoc.v:131148$6210_Y - connect \$81 $gt$libresoc.v:131149$6211_Y - connect \$83 $gt$libresoc.v:131150$6212_Y - connect \$85 $gt$libresoc.v:131151$6213_Y - connect \$87 $gt$libresoc.v:131152$6214_Y - connect \$89 $gt$libresoc.v:131153$6215_Y - connect \$91 $gt$libresoc.v:131154$6216_Y - connect \$93 $gt$libresoc.v:131155$6217_Y - connect \$95 $gt$libresoc.v:131156$6218_Y - connect \$97 $gt$libresoc.v:131157$6219_Y + connect \$9 $gt$libresoc.v:140823$6478_Y + connect \$99 $gt$libresoc.v:140824$6479_Y + connect \$101 $gt$libresoc.v:140825$6480_Y + connect \$103 $gt$libresoc.v:140826$6481_Y + connect \$105 $gt$libresoc.v:140827$6482_Y + connect \$107 $gt$libresoc.v:140828$6483_Y + connect \$109 $gt$libresoc.v:140829$6484_Y + connect \$111 $gt$libresoc.v:140830$6485_Y + connect \$113 $gt$libresoc.v:140831$6486_Y + connect \$115 $gt$libresoc.v:140832$6487_Y + connect \$117 $gt$libresoc.v:140833$6488_Y + connect \$11 $gt$libresoc.v:140834$6489_Y + connect \$119 $gt$libresoc.v:140835$6490_Y + connect \$121 $gt$libresoc.v:140836$6491_Y + connect \$123 $gt$libresoc.v:140837$6492_Y + connect \$125 $gt$libresoc.v:140838$6493_Y + connect \$127 $gt$libresoc.v:140839$6494_Y + connect \$13 $gt$libresoc.v:140840$6495_Y + connect \$15 $gt$libresoc.v:140841$6496_Y + connect \$17 $gt$libresoc.v:140842$6497_Y + connect \$1 $gt$libresoc.v:140843$6498_Y + connect \$19 $gt$libresoc.v:140844$6499_Y + connect \$21 $gt$libresoc.v:140845$6500_Y + connect \$23 $gt$libresoc.v:140846$6501_Y + connect \$25 $gt$libresoc.v:140847$6502_Y + connect \$27 $gt$libresoc.v:140848$6503_Y + connect \$29 $gt$libresoc.v:140849$6504_Y + connect \$31 $gt$libresoc.v:140850$6505_Y + connect \$33 $gt$libresoc.v:140851$6506_Y + connect \$35 $gt$libresoc.v:140852$6507_Y + connect \$37 $gt$libresoc.v:140853$6508_Y + connect \$3 $gt$libresoc.v:140854$6509_Y + connect \$39 $gt$libresoc.v:140855$6510_Y + connect \$41 $gt$libresoc.v:140856$6511_Y + connect \$43 $gt$libresoc.v:140857$6512_Y + connect \$45 $gt$libresoc.v:140858$6513_Y + connect \$47 $gt$libresoc.v:140859$6514_Y + connect \$49 $gt$libresoc.v:140860$6515_Y + connect \$51 $gt$libresoc.v:140861$6516_Y + connect \$53 $gt$libresoc.v:140862$6517_Y + connect \$55 $gt$libresoc.v:140863$6518_Y + connect \$57 $gt$libresoc.v:140864$6519_Y + connect \$5 $gt$libresoc.v:140865$6520_Y + connect \$59 $gt$libresoc.v:140866$6521_Y + connect \$61 $gt$libresoc.v:140867$6522_Y + connect \$63 $gt$libresoc.v:140868$6523_Y + connect \$65 $gt$libresoc.v:140869$6524_Y + connect \$67 $gt$libresoc.v:140870$6525_Y + connect \$69 $gt$libresoc.v:140871$6526_Y + connect \$71 $gt$libresoc.v:140872$6527_Y + connect \$73 $gt$libresoc.v:140873$6528_Y + connect \$75 $gt$libresoc.v:140874$6529_Y + connect \$77 $gt$libresoc.v:140875$6530_Y + connect \$7 $gt$libresoc.v:140876$6531_Y + connect \$79 $gt$libresoc.v:140877$6532_Y + connect \$81 $gt$libresoc.v:140878$6533_Y + connect \$83 $gt$libresoc.v:140879$6534_Y + connect \$85 $gt$libresoc.v:140880$6535_Y + connect \$87 $gt$libresoc.v:140881$6536_Y + connect \$89 $gt$libresoc.v:140882$6537_Y + connect \$91 $gt$libresoc.v:140883$6538_Y + connect \$93 $gt$libresoc.v:140884$6539_Y + connect \$95 $gt$libresoc.v:140885$6540_Y + connect \$97 $gt$libresoc.v:140886$6541_Y end -attribute \src "libresoc.v:131550.1-131579.10" +attribute \src "libresoc.v:141279.1-141308.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:131574.17-131574.101" - wire width 64 $extend$libresoc.v:131574$6225_Y - attribute \src "libresoc.v:131574.17-131574.101" - wire width 64 $pos$libresoc.v:131574$6226_Y - attribute \src "libresoc.v:131571.17-131571.111" - wire width 20 $sshl$libresoc.v:131571$6222_Y - attribute \src "libresoc.v:131573.17-131573.113" - wire width 32 $sshl$libresoc.v:131573$6224_Y - attribute \src "libresoc.v:131572.17-131572.107" - wire width 21 $sub$libresoc.v:131572$6223_Y + attribute \src "libresoc.v:141303.17-141303.101" + wire width 64 $extend$libresoc.v:141303$6547_Y + attribute \src "libresoc.v:141303.17-141303.101" + wire width 64 $pos$libresoc.v:141303$6548_Y + attribute \src "libresoc.v:141300.17-141300.111" + wire width 20 $sshl$libresoc.v:141300$6544_Y + attribute \src "libresoc.v:141302.17-141302.113" + wire width 32 $sshl$libresoc.v:141302$6546_Y + attribute \src "libresoc.v:141301.17-141301.107" + wire width 21 $sub$libresoc.v:141301$6545_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -213361,23 +229174,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:131574$6225 + cell $pos $extend$libresoc.v:141303$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:131574$6225_Y + connect \Y $extend$libresoc.v:141303$6547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:131574$6226 + cell $pos $pos$libresoc.v:141303$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:131574$6225_Y - connect \Y $pos$libresoc.v:131574$6226_Y + connect \A $extend$libresoc.v:141303$6547_Y + connect \Y $pos$libresoc.v:141303$6548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:131571$6222 + cell $sshl $sshl$libresoc.v:141300$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -213385,10 +229198,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:131571$6222_Y + connect \Y $sshl$libresoc.v:141300$6544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:131573$6224 + cell $sshl $sshl$libresoc.v:141302$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -213396,10 +229209,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:131573$6224_Y + connect \Y $sshl$libresoc.v:141302$6546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:131572$6223 + cell $sub $sub$libresoc.v:141301$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -213407,86 +229220,86 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:131572$6223_Y + connect \Y $sub$libresoc.v:141301$6545_Y end - connect \$2 $sshl$libresoc.v:131571$6222_Y - connect \$4 $sub$libresoc.v:131572$6223_Y - connect \$7 $sshl$libresoc.v:131573$6224_Y - connect \$6 $pos$libresoc.v:131574$6226_Y + connect \$2 $sshl$libresoc.v:141300$6544_Y + connect \$4 $sub$libresoc.v:141301$6545_Y + connect \$7 $sshl$libresoc.v:141302$6546_Y + connect \$6 $pos$libresoc.v:141303$6548_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:131583.1-131641.10" +attribute \src "libresoc.v:141312.1-141370.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:131584.7-131584.20" + attribute \src "libresoc.v:141313.7-141313.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131629.3-131637.6" - wire $0\q_int$next[0:0]$6237 - attribute \src "libresoc.v:131627.3-131628.27" + attribute \src "libresoc.v:141358.3-141366.6" + wire $0\q_int$next[0:0]$6559 + attribute \src "libresoc.v:141356.3-141357.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:131629.3-131637.6" - wire $1\q_int$next[0:0]$6238 - attribute \src "libresoc.v:131606.7-131606.19" + attribute \src "libresoc.v:141358.3-141366.6" + wire $1\q_int$next[0:0]$6560 + attribute \src "libresoc.v:141335.7-141335.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:131619.17-131619.96" - wire $and$libresoc.v:131619$6227_Y - attribute \src "libresoc.v:131624.17-131624.96" - wire $and$libresoc.v:131624$6232_Y - attribute \src "libresoc.v:131621.18-131621.93" - wire $not$libresoc.v:131621$6229_Y - attribute \src "libresoc.v:131623.17-131623.92" - wire $not$libresoc.v:131623$6231_Y - attribute \src "libresoc.v:131626.17-131626.92" - wire $not$libresoc.v:131626$6234_Y - attribute \src "libresoc.v:131620.18-131620.98" - wire $or$libresoc.v:131620$6228_Y - attribute \src "libresoc.v:131622.18-131622.99" - wire $or$libresoc.v:131622$6230_Y - attribute \src "libresoc.v:131625.17-131625.97" - wire $or$libresoc.v:131625$6233_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:141348.17-141348.96" + wire $and$libresoc.v:141348$6549_Y + attribute \src "libresoc.v:141353.17-141353.96" + wire $and$libresoc.v:141353$6554_Y + attribute \src "libresoc.v:141350.18-141350.93" + wire $not$libresoc.v:141350$6551_Y + attribute \src "libresoc.v:141352.17-141352.92" + wire $not$libresoc.v:141352$6553_Y + attribute \src "libresoc.v:141355.17-141355.92" + wire $not$libresoc.v:141355$6556_Y + attribute \src "libresoc.v:141349.18-141349.98" + wire $or$libresoc.v:141349$6550_Y + attribute \src "libresoc.v:141351.18-141351.99" + wire $or$libresoc.v:141351$6552_Y + attribute \src "libresoc.v:141354.17-141354.97" + wire $or$libresoc.v:141354$6555_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:131584.7-131584.15" + attribute \src "libresoc.v:141313.7-141313.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire output 4 \qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:131619$6227 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:141348$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213494,10 +229307,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:131619$6227_Y + connect \Y $and$libresoc.v:141348$6549_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:131624$6232 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:141353$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213505,34 +229318,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:131624$6232_Y + connect \Y $and$libresoc.v:141353$6554_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:131621$6229 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:141350$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:131621$6229_Y + connect \Y $not$libresoc.v:141350$6551_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:131623$6231 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:141352$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:131623$6231_Y + connect \Y $not$libresoc.v:141352$6553_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:131626$6234 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:141355$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:131626$6234_Y + connect \Y $not$libresoc.v:141355$6556_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:131620$6228 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:141349$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213540,10 +229353,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:131620$6228_Y + connect \Y $or$libresoc.v:141349$6550_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:131622$6230 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:141351$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213551,10 +229364,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:131622$6230_Y + connect \Y $or$libresoc.v:141351$6552_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:131625$6233 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:141354$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213562,39 +229375,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:131625$6233_Y + connect \Y $or$libresoc.v:141354$6555_Y end - attribute \src "libresoc.v:131584.7-131584.20" - process $proc$libresoc.v:131584$6239 + attribute \src "libresoc.v:141313.7-141313.20" + process $proc$libresoc.v:141313$6561 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131606.7-131606.19" - process $proc$libresoc.v:131606$6240 + attribute \src "libresoc.v:141335.7-141335.19" + process $proc$libresoc.v:141335$6562 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:131627.3-131628.27" - process $proc$libresoc.v:131627$6235 + attribute \src "libresoc.v:141356.3-141357.27" + process $proc$libresoc.v:141356$6557 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:131629.3-131637.6" - process $proc$libresoc.v:131629$6236 + attribute \src "libresoc.v:141358.3-141366.6" + process $proc$libresoc.v:141358$6558 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6237 $1\q_int$next[0:0]$6238 - attribute \src "libresoc.v:131630.5-131630.29" + assign $0\q_int$next[0:0]$6559 $1\q_int$next[0:0]$6560 + attribute \src "libresoc.v:141359.5-141359.29" switch \initial - attribute \src "libresoc.v:131630.9-131630.17" + attribute \src "libresoc.v:141359.9-141359.17" case 1'1 case end @@ -213603,494 +229416,494 @@ module \lod_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6238 1'0 + assign $1\q_int$next[0:0]$6560 1'0 case - assign $1\q_int$next[0:0]$6238 \$5 + assign $1\q_int$next[0:0]$6560 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6237 + update \q_int$next $0\q_int$next[0:0]$6559 end - connect \$9 $and$libresoc.v:131619$6227_Y - connect \$11 $or$libresoc.v:131620$6228_Y - connect \$13 $not$libresoc.v:131621$6229_Y - connect \$15 $or$libresoc.v:131622$6230_Y - connect \$1 $not$libresoc.v:131623$6231_Y - connect \$3 $and$libresoc.v:131624$6232_Y - connect \$5 $or$libresoc.v:131625$6233_Y - connect \$7 $not$libresoc.v:131626$6234_Y + connect \$9 $and$libresoc.v:141348$6549_Y + connect \$11 $or$libresoc.v:141349$6550_Y + connect \$13 $not$libresoc.v:141350$6551_Y + connect \$15 $or$libresoc.v:141351$6552_Y + connect \$1 $not$libresoc.v:141352$6553_Y + connect \$3 $and$libresoc.v:141353$6554_Y + connect \$5 $or$libresoc.v:141354$6555_Y + connect \$7 $not$libresoc.v:141355$6556_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:131645.1-132759.10" +attribute \src "libresoc.v:141374.1-142494.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:132384.3-132385.24" + attribute \src "libresoc.v:142119.3-142120.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:132382.3-132383.44" + attribute \src "libresoc.v:142117.3-142118.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:132689.3-132697.6" - wire $0\alu_l_r_alu$next[0:0]$6441 - attribute \src "libresoc.v:132306.3-132307.39" + attribute \src "libresoc.v:142424.3-142432.6" + wire $0\alu_l_r_alu$next[0:0]$6763 + attribute \src "libresoc.v:142041.3-142042.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6370 - attribute \src "libresoc.v:132356.3-132357.83" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6692 + attribute \src "libresoc.v:142091.3-142092.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 12 $0\alu_logical0_logical_op__fn_unit$next[11:0]$6371 - attribute \src "libresoc.v:132326.3-132327.81" - wire width 12 $0\alu_logical0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6372 - attribute \src "libresoc.v:132328.3-132329.95" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 + attribute \src "libresoc.v:142061.3-142062.81" + wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:142302.3-142340.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 + attribute \src "libresoc.v:142063.3-142064.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6373 - attribute \src "libresoc.v:132330.3-132331.91" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 + attribute \src "libresoc.v:142065.3-142066.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6374 - attribute \src "libresoc.v:132344.3-132345.89" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 + attribute \src "libresoc.v:142079.3-142080.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6375 - attribute \src "libresoc.v:132358.3-132359.75" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6697 + attribute \src "libresoc.v:142093.3-142094.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6376 - attribute \src "libresoc.v:132324.3-132325.85" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 + attribute \src "libresoc.v:142059.3-142060.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6377 - attribute \src "libresoc.v:132340.3-132341.85" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 + attribute \src "libresoc.v:142075.3-142076.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6378 - attribute \src "libresoc.v:132346.3-132347.87" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 + attribute \src "libresoc.v:142081.3-142082.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6379 - attribute \src "libresoc.v:132352.3-132353.83" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 + attribute \src "libresoc.v:142087.3-142088.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6380 - attribute \src "libresoc.v:132354.3-132355.85" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 + attribute \src "libresoc.v:142089.3-142090.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6381 - attribute \src "libresoc.v:132336.3-132337.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 + attribute \src "libresoc.v:142071.3-142072.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6382 - attribute \src "libresoc.v:132338.3-132339.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 + attribute \src "libresoc.v:142073.3-142074.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6383 - attribute \src "libresoc.v:132350.3-132351.91" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 + attribute \src "libresoc.v:142085.3-142086.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6384 - attribute \src "libresoc.v:132334.3-132335.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 + attribute \src "libresoc.v:142069.3-142070.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6385 - attribute \src "libresoc.v:132332.3-132333.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 + attribute \src "libresoc.v:142067.3-142068.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6386 - attribute \src "libresoc.v:132348.3-132349.85" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 + attribute \src "libresoc.v:142083.3-142084.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6387 - attribute \src "libresoc.v:132342.3-132343.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 + attribute \src "libresoc.v:142077.3-142078.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:132680.3-132688.6" - wire $0\alui_l_r_alui$next[0:0]$6438 - attribute \src "libresoc.v:132308.3-132309.43" + attribute \src "libresoc.v:142415.3-142423.6" + wire $0\alui_l_r_alui$next[0:0]$6760 + attribute \src "libresoc.v:142043.3-142044.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:132606.3-132627.6" - wire width 64 $0\data_r0__o$next[63:0]$6413 - attribute \src "libresoc.v:132320.3-132321.37" + attribute \src "libresoc.v:142341.3-142362.6" + wire width 64 $0\data_r0__o$next[63:0]$6735 + attribute \src "libresoc.v:142055.3-142056.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:132606.3-132627.6" - wire $0\data_r0__o_ok$next[0:0]$6414 - attribute \src "libresoc.v:132322.3-132323.43" + attribute \src "libresoc.v:142341.3-142362.6" + wire $0\data_r0__o_ok$next[0:0]$6736 + attribute \src "libresoc.v:142057.3-142058.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:132628.3-132649.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6421 - attribute \src "libresoc.v:132316.3-132317.43" + attribute \src "libresoc.v:142363.3-142384.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6743 + attribute \src "libresoc.v:142051.3-142052.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:132628.3-132649.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6422 - attribute \src "libresoc.v:132318.3-132319.49" + attribute \src "libresoc.v:142363.3-142384.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6744 + attribute \src "libresoc.v:142053.3-142054.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:132698.3-132707.6" + attribute \src "libresoc.v:142433.3-142442.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:132708.3-132717.6" + attribute \src "libresoc.v:142443.3-142452.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:131646.7-131646.20" + attribute \src "libresoc.v:141375.7-141375.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132522.3-132530.6" - wire $0\opc_l_r_opc$next[0:0]$6355 - attribute \src "libresoc.v:132368.3-132369.39" + attribute \src "libresoc.v:142257.3-142265.6" + wire $0\opc_l_r_opc$next[0:0]$6677 + attribute \src "libresoc.v:142103.3-142104.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:132513.3-132521.6" - wire $0\opc_l_s_opc$next[0:0]$6352 - attribute \src "libresoc.v:132370.3-132371.39" + attribute \src "libresoc.v:142248.3-142256.6" + wire $0\opc_l_s_opc$next[0:0]$6674 + attribute \src "libresoc.v:142105.3-142106.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:132718.3-132726.6" - wire width 2 $0\prev_wr_go$next[1:0]$6446 - attribute \src "libresoc.v:132380.3-132381.37" + attribute \src "libresoc.v:142453.3-142461.6" + wire width 2 $0\prev_wr_go$next[1:0]$6768 + attribute \src "libresoc.v:142115.3-142116.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:132467.3-132476.6" + attribute \src "libresoc.v:142202.3-142211.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:132558.3-132566.6" - wire width 2 $0\req_l_r_req$next[1:0]$6367 - attribute \src "libresoc.v:132360.3-132361.39" + attribute \src "libresoc.v:142293.3-142301.6" + wire width 2 $0\req_l_r_req$next[1:0]$6689 + attribute \src "libresoc.v:142095.3-142096.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:132549.3-132557.6" - wire width 2 $0\req_l_s_req$next[1:0]$6364 - attribute \src "libresoc.v:132362.3-132363.39" + attribute \src "libresoc.v:142284.3-142292.6" + wire width 2 $0\req_l_s_req$next[1:0]$6686 + attribute \src "libresoc.v:142097.3-142098.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:132486.3-132494.6" - wire $0\rok_l_r_rdok$next[0:0]$6343 - attribute \src "libresoc.v:132376.3-132377.41" + attribute \src "libresoc.v:142221.3-142229.6" + wire $0\rok_l_r_rdok$next[0:0]$6665 + attribute \src "libresoc.v:142111.3-142112.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:132477.3-132485.6" - wire $0\rok_l_s_rdok$next[0:0]$6340 - attribute \src "libresoc.v:132378.3-132379.41" + attribute \src "libresoc.v:142212.3-142220.6" + wire $0\rok_l_s_rdok$next[0:0]$6662 + attribute \src "libresoc.v:142113.3-142114.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:132504.3-132512.6" - wire $0\rst_l_r_rst$next[0:0]$6349 - attribute \src "libresoc.v:132372.3-132373.39" + attribute \src "libresoc.v:142239.3-142247.6" + wire $0\rst_l_r_rst$next[0:0]$6671 + attribute \src "libresoc.v:142107.3-142108.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:132495.3-132503.6" - wire $0\rst_l_s_rst$next[0:0]$6346 - attribute \src "libresoc.v:132374.3-132375.39" + attribute \src "libresoc.v:142230.3-142238.6" + wire $0\rst_l_s_rst$next[0:0]$6668 + attribute \src "libresoc.v:142109.3-142110.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:132540.3-132548.6" - wire width 3 $0\src_l_r_src$next[2:0]$6361 - attribute \src "libresoc.v:132364.3-132365.39" + attribute \src "libresoc.v:142275.3-142283.6" + wire width 3 $0\src_l_r_src$next[2:0]$6683 + attribute \src "libresoc.v:142099.3-142100.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:132531.3-132539.6" - wire width 3 $0\src_l_s_src$next[2:0]$6358 - attribute \src "libresoc.v:132366.3-132367.39" + attribute \src "libresoc.v:142266.3-142274.6" + wire width 3 $0\src_l_s_src$next[2:0]$6680 + attribute \src "libresoc.v:142101.3-142102.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:132650.3-132659.6" - wire width 64 $0\src_r0$next[63:0]$6429 - attribute \src "libresoc.v:132314.3-132315.29" + attribute \src "libresoc.v:142385.3-142394.6" + wire width 64 $0\src_r0$next[63:0]$6751 + attribute \src "libresoc.v:142049.3-142050.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:132660.3-132669.6" - wire width 64 $0\src_r1$next[63:0]$6432 - attribute \src "libresoc.v:132312.3-132313.29" + attribute \src "libresoc.v:142395.3-142404.6" + wire width 64 $0\src_r1$next[63:0]$6754 + attribute \src "libresoc.v:142047.3-142048.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:132670.3-132679.6" - wire $0\src_r2$next[0:0]$6435 - attribute \src "libresoc.v:132310.3-132311.29" + attribute \src "libresoc.v:142405.3-142414.6" + wire $0\src_r2$next[0:0]$6757 + attribute \src "libresoc.v:142045.3-142046.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:131764.7-131764.24" + attribute \src "libresoc.v:141493.7-141493.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:131774.7-131774.26" + attribute \src "libresoc.v:141503.7-141503.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:132689.3-132697.6" - wire $1\alu_l_r_alu$next[0:0]$6442 - attribute \src "libresoc.v:131782.7-131782.25" + attribute \src "libresoc.v:142424.3-142432.6" + wire $1\alu_l_r_alu$next[0:0]$6764 + attribute \src "libresoc.v:141511.7-141511.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6388 - attribute \src "libresoc.v:131790.13-131790.53" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 + attribute \src "libresoc.v:141519.13-141519.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 12 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6389 - attribute \src "libresoc.v:131807.14-131807.56" - wire width 12 $1\alu_logical0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6390 - attribute \src "libresoc.v:131811.14-131811.76" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 + attribute \src "libresoc.v:141538.14-141538.57" + wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:142302.3-142340.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 + attribute \src "libresoc.v:141542.14-141542.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6391 - attribute \src "libresoc.v:131815.7-131815.51" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 + attribute \src "libresoc.v:141546.7-141546.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6392 - attribute \src "libresoc.v:131823.13-131823.56" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 + attribute \src "libresoc.v:141554.13-141554.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6393 - attribute \src "libresoc.v:131827.14-131827.51" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6715 + attribute \src "libresoc.v:141558.14-141558.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6394 - attribute \src "libresoc.v:131905.13-131905.55" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 + attribute \src "libresoc.v:141637.13-141637.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6395 - attribute \src "libresoc.v:131909.7-131909.48" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 + attribute \src "libresoc.v:141641.7-141641.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6396 - attribute \src "libresoc.v:131913.7-131913.49" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 + attribute \src "libresoc.v:141645.7-141645.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6397 - attribute \src "libresoc.v:131917.7-131917.47" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 + attribute \src "libresoc.v:141649.7-141649.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6398 - attribute \src "libresoc.v:131921.7-131921.48" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 + attribute \src "libresoc.v:141653.7-141653.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6399 - attribute \src "libresoc.v:131925.7-131925.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 + attribute \src "libresoc.v:141657.7-141657.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6400 - attribute \src "libresoc.v:131929.7-131929.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 + attribute \src "libresoc.v:141661.7-141661.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6401 - attribute \src "libresoc.v:131933.7-131933.51" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 + attribute \src "libresoc.v:141665.7-141665.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6402 - attribute \src "libresoc.v:131937.7-131937.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 + attribute \src "libresoc.v:141669.7-141669.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6403 - attribute \src "libresoc.v:131941.7-131941.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 + attribute \src "libresoc.v:141673.7-141673.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6404 - attribute \src "libresoc.v:131945.7-131945.48" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 + attribute \src "libresoc.v:141677.7-141677.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6405 - attribute \src "libresoc.v:131949.7-131949.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 + attribute \src "libresoc.v:141681.7-141681.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:132680.3-132688.6" - wire $1\alui_l_r_alui$next[0:0]$6439 - attribute \src "libresoc.v:131975.7-131975.27" + attribute \src "libresoc.v:142415.3-142423.6" + wire $1\alui_l_r_alui$next[0:0]$6761 + attribute \src "libresoc.v:141707.7-141707.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:132606.3-132627.6" - wire width 64 $1\data_r0__o$next[63:0]$6415 - attribute \src "libresoc.v:132009.14-132009.47" + attribute \src "libresoc.v:142341.3-142362.6" + wire width 64 $1\data_r0__o$next[63:0]$6737 + attribute \src "libresoc.v:141741.14-141741.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:132606.3-132627.6" - wire $1\data_r0__o_ok$next[0:0]$6416 - attribute \src "libresoc.v:132013.7-132013.27" + attribute \src "libresoc.v:142341.3-142362.6" + wire $1\data_r0__o_ok$next[0:0]$6738 + attribute \src "libresoc.v:141745.7-141745.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:132628.3-132649.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6423 - attribute \src "libresoc.v:132017.13-132017.33" + attribute \src "libresoc.v:142363.3-142384.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6745 + attribute \src "libresoc.v:141749.13-141749.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:132628.3-132649.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6424 - attribute \src "libresoc.v:132021.7-132021.30" + attribute \src "libresoc.v:142363.3-142384.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6746 + attribute \src "libresoc.v:141753.7-141753.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:132698.3-132707.6" + attribute \src "libresoc.v:142433.3-142442.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:132708.3-132717.6" + attribute \src "libresoc.v:142443.3-142452.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:132522.3-132530.6" - wire $1\opc_l_r_opc$next[0:0]$6356 - attribute \src "libresoc.v:132035.7-132035.25" + attribute \src "libresoc.v:142257.3-142265.6" + wire $1\opc_l_r_opc$next[0:0]$6678 + attribute \src "libresoc.v:141767.7-141767.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:132513.3-132521.6" - wire $1\opc_l_s_opc$next[0:0]$6353 - attribute \src "libresoc.v:132039.7-132039.25" + attribute \src "libresoc.v:142248.3-142256.6" + wire $1\opc_l_s_opc$next[0:0]$6675 + attribute \src "libresoc.v:141771.7-141771.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:132718.3-132726.6" - wire width 2 $1\prev_wr_go$next[1:0]$6447 - attribute \src "libresoc.v:132170.13-132170.30" + attribute \src "libresoc.v:142453.3-142461.6" + wire width 2 $1\prev_wr_go$next[1:0]$6769 + attribute \src "libresoc.v:141905.13-141905.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:132467.3-132476.6" + attribute \src "libresoc.v:142202.3-142211.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:132558.3-132566.6" - wire width 2 $1\req_l_r_req$next[1:0]$6368 - attribute \src "libresoc.v:132178.13-132178.31" + attribute \src "libresoc.v:142293.3-142301.6" + wire width 2 $1\req_l_r_req$next[1:0]$6690 + attribute \src "libresoc.v:141913.13-141913.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:132549.3-132557.6" - wire width 2 $1\req_l_s_req$next[1:0]$6365 - attribute \src "libresoc.v:132182.13-132182.31" + attribute \src "libresoc.v:142284.3-142292.6" + wire width 2 $1\req_l_s_req$next[1:0]$6687 + attribute \src "libresoc.v:141917.13-141917.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:132486.3-132494.6" - wire $1\rok_l_r_rdok$next[0:0]$6344 - attribute \src "libresoc.v:132194.7-132194.26" + attribute \src "libresoc.v:142221.3-142229.6" + wire $1\rok_l_r_rdok$next[0:0]$6666 + attribute \src "libresoc.v:141929.7-141929.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:132477.3-132485.6" - wire $1\rok_l_s_rdok$next[0:0]$6341 - attribute \src "libresoc.v:132198.7-132198.26" + attribute \src "libresoc.v:142212.3-142220.6" + wire $1\rok_l_s_rdok$next[0:0]$6663 + attribute \src "libresoc.v:141933.7-141933.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:132504.3-132512.6" - wire $1\rst_l_r_rst$next[0:0]$6350 - attribute \src "libresoc.v:132202.7-132202.25" + attribute \src "libresoc.v:142239.3-142247.6" + wire $1\rst_l_r_rst$next[0:0]$6672 + attribute \src "libresoc.v:141937.7-141937.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:132495.3-132503.6" - wire $1\rst_l_s_rst$next[0:0]$6347 - attribute \src "libresoc.v:132206.7-132206.25" + attribute \src "libresoc.v:142230.3-142238.6" + wire $1\rst_l_s_rst$next[0:0]$6669 + attribute \src "libresoc.v:141941.7-141941.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:132540.3-132548.6" - wire width 3 $1\src_l_r_src$next[2:0]$6362 - attribute \src "libresoc.v:132220.13-132220.31" + attribute \src "libresoc.v:142275.3-142283.6" + wire width 3 $1\src_l_r_src$next[2:0]$6684 + attribute \src "libresoc.v:141955.13-141955.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:132531.3-132539.6" - wire width 3 $1\src_l_s_src$next[2:0]$6359 - attribute \src "libresoc.v:132224.13-132224.31" + attribute \src "libresoc.v:142266.3-142274.6" + wire width 3 $1\src_l_s_src$next[2:0]$6681 + attribute \src "libresoc.v:141959.13-141959.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:132650.3-132659.6" - wire width 64 $1\src_r0$next[63:0]$6430 - attribute \src "libresoc.v:132232.14-132232.43" + attribute \src "libresoc.v:142385.3-142394.6" + wire width 64 $1\src_r0$next[63:0]$6752 + attribute \src "libresoc.v:141967.14-141967.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:132660.3-132669.6" - wire width 64 $1\src_r1$next[63:0]$6433 - attribute \src "libresoc.v:132236.14-132236.43" + attribute \src "libresoc.v:142395.3-142404.6" + wire width 64 $1\src_r1$next[63:0]$6755 + attribute \src "libresoc.v:141971.14-141971.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:132670.3-132679.6" - wire $1\src_r2$next[0:0]$6436 - attribute \src "libresoc.v:132240.7-132240.20" + attribute \src "libresoc.v:142405.3-142414.6" + wire $1\src_r2$next[0:0]$6758 + attribute \src "libresoc.v:141975.7-141975.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:132567.3-132605.6" - wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6406 - attribute \src "libresoc.v:132567.3-132605.6" - wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6407 - attribute \src "libresoc.v:132567.3-132605.6" - wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6408 - attribute \src "libresoc.v:132567.3-132605.6" - wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6409 - attribute \src "libresoc.v:132567.3-132605.6" - wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6410 - attribute \src "libresoc.v:132567.3-132605.6" - wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6411 - attribute \src "libresoc.v:132606.3-132627.6" - wire width 64 $2\data_r0__o$next[63:0]$6417 - attribute \src "libresoc.v:132606.3-132627.6" - wire $2\data_r0__o_ok$next[0:0]$6418 - attribute \src "libresoc.v:132628.3-132649.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$6425 - attribute \src "libresoc.v:132628.3-132649.6" - wire $2\data_r1__cr_a_ok$next[0:0]$6426 - attribute \src "libresoc.v:132606.3-132627.6" - wire $3\data_r0__o_ok$next[0:0]$6419 - attribute \src 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attribute \src "libresoc.v:142006.18-142006.112" + wire $reduce_or$libresoc.v:142006$6585_Y + attribute \src "libresoc.v:142028.18-142028.162" + wire $ternary$libresoc.v:142028$6607_Y + attribute \src "libresoc.v:142029.18-142029.163" + wire width 64 $ternary$libresoc.v:142029$6608_Y + attribute \src "libresoc.v:142030.18-142030.168" + wire $ternary$libresoc.v:142030$6609_Y + attribute \src "libresoc.v:142032.18-142032.188" + wire width 64 $ternary$libresoc.v:142032$6611_Y + attribute \src "libresoc.v:142033.18-142033.115" + wire width 64 $ternary$libresoc.v:142033$6612_Y + attribute \src "libresoc.v:142034.18-142034.125" + wire width 64 $ternary$libresoc.v:142034$6613_Y + attribute \src "libresoc.v:142035.18-142035.118" + wire $ternary$libresoc.v:142035$6614_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -214103,7 +229916,7 @@ module \logical0 wire \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 2 \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 2 \$111 @@ -214111,11 +229924,11 @@ module \logical0 wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 2 \$19 @@ -214185,11 +229998,11 @@ module \logical0 wire \$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$89 @@ -214207,29 +230020,29 @@ module \logical0 wire width 3 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_logical0_cr_a @@ -214238,22 +230051,24 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_logical0_logical_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_logical0_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_logical0_logical_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_logical0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_logical0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_logical0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -214348,6 +230163,7 @@ module \logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_logical0_logical_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -214396,15 +230212,15 @@ module \logical0 wire \alu_logical0_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_logical0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_logical0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_logical0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_logical0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_logical0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_logical0_ra @@ -214416,17 +230232,17 @@ module \logical0 wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 2 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -214472,37 +230288,39 @@ module \logical0 wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:131646.7-131646.15" + attribute \src "libresoc.v:141375.7-141375.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_logical0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -214589,6 +230407,7 @@ module \logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -214619,15 +230438,15 @@ module \logical0 wire width 2 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 2 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -214635,23 +230454,23 @@ module \logical0 wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 2 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -214661,31 +230480,31 @@ module \logical0 wire width 64 input 26 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm$80 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel @@ -214694,7 +230513,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:132249$6241 + cell $and $and$libresoc.v:141984$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214702,10 +230521,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:132249$6241_Y + connect \Y $and$libresoc.v:141984$6563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132250$6242 + cell $and $and$libresoc.v:141985$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -214713,10 +230532,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:132250$6242_Y + connect \Y $and$libresoc.v:141985$6564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132252$6244 + cell $and $and$libresoc.v:141987$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -214724,10 +230543,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:132252$6244_Y + connect \Y $and$libresoc.v:141987$6566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132253$6245 + cell $and $and$libresoc.v:141988$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214735,10 +230554,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132253$6245_Y + connect \Y $and$libresoc.v:141988$6567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132254$6246 + cell $and $and$libresoc.v:141989$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214746,10 +230565,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132254$6246_Y + connect \Y $and$libresoc.v:141989$6568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:132255$6247 + cell $and $and$libresoc.v:141990$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -214757,10 +230576,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:132255$6247_Y + connect \Y $and$libresoc.v:141990$6569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:132256$6248 + cell $and $and$libresoc.v:141991$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -214768,10 +230587,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132256$6248_Y + connect \Y $and$libresoc.v:141991$6570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132257$6249 + cell $and $and$libresoc.v:141992$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214779,10 +230598,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132257$6249_Y + connect \Y $and$libresoc.v:141992$6571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132258$6250 + cell $and $and$libresoc.v:141993$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214790,10 +230609,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132258$6250_Y + connect \Y $and$libresoc.v:141993$6572_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:132260$6252 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:141995$6574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214801,10 +230620,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:132260$6252_Y + connect \Y $and$libresoc.v:141995$6574_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:132262$6254 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:141997$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214812,10 +230631,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:132262$6254_Y + connect \Y $and$libresoc.v:141997$6576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:132263$6255 + cell $and $and$libresoc.v:141998$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214823,10 +230642,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:132263$6255_Y + connect \Y $and$libresoc.v:141998$6577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:132264$6256 + cell $and $and$libresoc.v:141999$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -214834,10 +230653,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:132264$6256_Y + connect \Y $and$libresoc.v:141999$6578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:132266$6258 + cell $and $and$libresoc.v:142001$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -214845,10 +230664,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:132266$6258_Y + connect \Y $and$libresoc.v:142001$6580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:132269$6261 + cell $and $and$libresoc.v:142004$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214856,10 +230675,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:132269$6261_Y + connect \Y $and$libresoc.v:142004$6583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:132274$6266 + cell $and $and$libresoc.v:142009$6588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214867,10 +230686,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:132274$6266_Y + connect \Y $and$libresoc.v:142009$6588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:132275$6267 + cell $and $and$libresoc.v:142010$6589 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -214878,10 +230697,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132275$6267_Y + connect \Y $and$libresoc.v:142010$6589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:132277$6269 + cell $and $and$libresoc.v:142012$6591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214889,10 +230708,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:132277$6269_Y + connect \Y $and$libresoc.v:142012$6591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132280$6272 + cell $and $and$libresoc.v:142015$6594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214900,10 +230719,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:132280$6272_Y + connect \Y $and$libresoc.v:142015$6594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132281$6273 + cell $and $and$libresoc.v:142016$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214911,10 +230730,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:132281$6273_Y + connect \Y $and$libresoc.v:142016$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132282$6274 + cell $and $and$libresoc.v:142017$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214922,10 +230741,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:132282$6274_Y + connect \Y $and$libresoc.v:142017$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:132287$6279 + cell $and $and$libresoc.v:142022$6601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214933,10 +230752,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:132287$6279_Y + connect \Y $and$libresoc.v:142022$6601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:132288$6280 + cell $and $and$libresoc.v:142023$6602 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -214944,10 +230763,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132288$6280_Y + connect \Y $and$libresoc.v:142023$6602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132291$6283 + cell $and $and$libresoc.v:142026$6605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214955,10 +230774,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132291$6283_Y + connect \Y $and$libresoc.v:142026$6605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132292$6284 + cell $and $and$libresoc.v:142027$6606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214966,10 +230785,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132292$6284_Y + connect \Y $and$libresoc.v:142027$6606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:132301$6293 + cell $and $and$libresoc.v:142036$6615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214977,10 +230796,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:132301$6293_Y + connect \Y $and$libresoc.v:142036$6615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:132302$6294 + cell $and $and$libresoc.v:142037$6616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214988,10 +230807,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:132302$6294_Y + connect \Y $and$libresoc.v:142037$6616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132303$6295 + cell $and $and$libresoc.v:142038$6617 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -214999,10 +230818,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:132303$6295_Y + connect \Y $and$libresoc.v:142038$6617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:132276$6268 + cell $eq $eq$libresoc.v:142011$6590 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215010,10 +230829,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:132276$6268_Y + connect \Y $eq$libresoc.v:142011$6590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:132278$6270 + cell $eq $eq$libresoc.v:142013$6592 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215021,82 +230840,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:132278$6270_Y + connect \Y $eq$libresoc.v:142013$6592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:132251$6243 + cell $not $not$libresoc.v:141986$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:132251$6243_Y + connect \Y $not$libresoc.v:141986$6565_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:132259$6251 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:141994$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:132259$6251_Y + connect \Y $not$libresoc.v:141994$6573_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:132261$6253 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:141996$6575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:132261$6253_Y + connect \Y $not$libresoc.v:141996$6575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:132265$6257 + cell $not $not$libresoc.v:142000$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:132265$6257_Y + connect \Y $not$libresoc.v:142000$6579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:132268$6260 + cell $not $not$libresoc.v:142003$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:132268$6260_Y + connect \Y $not$libresoc.v:142003$6582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:132273$6265 + cell $not $not$libresoc.v:142008$6587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:132273$6265_Y + connect \Y $not$libresoc.v:142008$6587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:132279$6271 + cell $not $not$libresoc.v:142014$6593 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:132279$6271_Y + connect \Y $not$libresoc.v:142014$6593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:132304$6296 + cell $not $not$libresoc.v:142039$6618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:132304$6296_Y + connect \Y $not$libresoc.v:142039$6618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:132305$6297 + cell $not $not$libresoc.v:142040$6619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:132305$6297_Y + connect \Y $not$libresoc.v:142040$6619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:132272$6264 + cell $or $or$libresoc.v:142007$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215104,10 +230923,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:132272$6264_Y + connect \Y $or$libresoc.v:142007$6586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:132283$6275 + cell $or $or$libresoc.v:142018$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215115,10 +230934,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:132283$6275_Y + connect \Y $or$libresoc.v:142018$6597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:132284$6276 + cell $or $or$libresoc.v:142019$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215126,10 +230945,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:132284$6276_Y + connect \Y $or$libresoc.v:142019$6598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:132285$6277 + cell $or $or$libresoc.v:142020$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215137,10 +230956,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:132285$6277_Y + connect \Y $or$libresoc.v:142020$6599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:132286$6278 + cell $or $or$libresoc.v:142021$6600 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215148,10 +230967,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:132286$6278_Y + connect \Y $or$libresoc.v:142021$6600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:132289$6281 + cell $or $or$libresoc.v:142024$6603 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215159,10 +230978,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:132289$6281_Y + connect \Y $or$libresoc.v:142024$6603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:132290$6282 + cell $or $or$libresoc.v:142025$6604 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215170,98 +230989,98 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:132290$6282_Y + connect \Y $or$libresoc.v:142025$6604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:132296$6288 + cell $reduce_and $reduce_and$libresoc.v:142031$6610 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:132296$6288_Y + connect \Y $reduce_and$libresoc.v:142031$6610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:132267$6259 + cell $reduce_or $reduce_or$libresoc.v:142002$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:132267$6259_Y + connect \Y $reduce_or$libresoc.v:142002$6581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:132270$6262 + cell $reduce_or $reduce_or$libresoc.v:142005$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:132270$6262_Y + connect \Y $reduce_or$libresoc.v:142005$6584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:132271$6263 + cell $reduce_or $reduce_or$libresoc.v:142006$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:132271$6263_Y + connect \Y $reduce_or$libresoc.v:142006$6585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:132293$6285 + cell $mux $ternary$libresoc.v:142028$6607 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:132293$6285_Y + connect \Y $ternary$libresoc.v:142028$6607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:132294$6286 + cell $mux $ternary$libresoc.v:142029$6608 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:132294$6286_Y + connect \Y $ternary$libresoc.v:142029$6608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:132295$6287 + cell $mux $ternary$libresoc.v:142030$6609 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:132295$6287_Y + connect \Y $ternary$libresoc.v:142030$6609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:132297$6289 + cell $mux $ternary$libresoc.v:142032$6611 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:132297$6289_Y + connect \Y $ternary$libresoc.v:142032$6611_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:132298$6290 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:142033$6612 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:132298$6290_Y + connect \Y $ternary$libresoc.v:142033$6612_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:132299$6291 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:142034$6613 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:132299$6291_Y + connect \Y $ternary$libresoc.v:142034$6613_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:132300$6292 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:142035$6614 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:132300$6292_Y + connect \Y $ternary$libresoc.v:142035$6614_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:132386.14-132392.4" + attribute \src "libresoc.v:142121.14-142127.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -215270,7 +231089,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:132393.16-132425.4" + attribute \src "libresoc.v:142128.16-142160.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -215305,7 +231124,7 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:132426.15-132432.4" + attribute \src "libresoc.v:142161.15-142167.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -215314,7 +231133,7 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:132433.14-132439.4" + attribute \src "libresoc.v:142168.14-142174.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -215323,7 +231142,7 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:132440.14-132446.4" + attribute \src "libresoc.v:142175.14-142181.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -215332,7 +231151,7 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:132447.14-132453.4" + attribute \src "libresoc.v:142182.14-142188.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -215341,7 +231160,7 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:132454.14-132459.4" + attribute \src "libresoc.v:142189.14-142194.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -215349,7 +231168,7 @@ module \logical0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:132460.14-132466.4" + attribute \src "libresoc.v:142195.14-142201.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -215357,622 +231176,622 @@ module \logical0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:131646.7-131646.20" - process $proc$libresoc.v:131646$6448 + attribute \src "libresoc.v:141375.7-141375.20" + process $proc$libresoc.v:141375$6770 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131764.7-131764.24" - process $proc$libresoc.v:131764$6449 + attribute \src "libresoc.v:141493.7-141493.24" + process $proc$libresoc.v:141493$6771 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:131774.7-131774.26" - process $proc$libresoc.v:131774$6450 + attribute \src "libresoc.v:141503.7-141503.26" + process $proc$libresoc.v:141503$6772 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:131782.7-131782.25" - process $proc$libresoc.v:131782$6451 + attribute \src "libresoc.v:141511.7-141511.25" + process $proc$libresoc.v:141511$6773 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:131790.13-131790.53" - process $proc$libresoc.v:131790$6452 + attribute \src "libresoc.v:141519.13-141519.53" + process $proc$libresoc.v:141519$6774 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:131807.14-131807.56" - process $proc$libresoc.v:131807$6453 + attribute \src "libresoc.v:141538.14-141538.57" + process $proc$libresoc.v:141538$6775 assign { } { } - assign $1\alu_logical0_logical_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[11:0] + update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:131811.14-131811.76" - process $proc$libresoc.v:131811$6454 + attribute \src "libresoc.v:141542.14-141542.76" + process $proc$libresoc.v:141542$6776 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:131815.7-131815.51" - process $proc$libresoc.v:131815$6455 + attribute \src "libresoc.v:141546.7-141546.51" + process $proc$libresoc.v:141546$6777 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:131823.13-131823.56" - process $proc$libresoc.v:131823$6456 + attribute \src "libresoc.v:141554.13-141554.56" + process $proc$libresoc.v:141554$6778 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:131827.14-131827.51" - process $proc$libresoc.v:131827$6457 + attribute \src "libresoc.v:141558.14-141558.51" + process $proc$libresoc.v:141558$6779 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:131905.13-131905.55" - process $proc$libresoc.v:131905$6458 + attribute \src "libresoc.v:141637.13-141637.55" + process $proc$libresoc.v:141637$6780 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:131909.7-131909.48" - process $proc$libresoc.v:131909$6459 + attribute \src "libresoc.v:141641.7-141641.48" + process $proc$libresoc.v:141641$6781 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:131913.7-131913.49" - process $proc$libresoc.v:131913$6460 + attribute \src "libresoc.v:141645.7-141645.49" + process $proc$libresoc.v:141645$6782 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:131917.7-131917.47" - process $proc$libresoc.v:131917$6461 + attribute \src "libresoc.v:141649.7-141649.47" + process $proc$libresoc.v:141649$6783 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:131921.7-131921.48" - process $proc$libresoc.v:131921$6462 + attribute \src "libresoc.v:141653.7-141653.48" + process $proc$libresoc.v:141653$6784 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:131925.7-131925.45" - process $proc$libresoc.v:131925$6463 + attribute \src "libresoc.v:141657.7-141657.45" + process $proc$libresoc.v:141657$6785 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:131929.7-131929.45" - process $proc$libresoc.v:131929$6464 + attribute \src "libresoc.v:141661.7-141661.45" + process $proc$libresoc.v:141661$6786 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:131933.7-131933.51" - process $proc$libresoc.v:131933$6465 + attribute \src "libresoc.v:141665.7-141665.51" + process $proc$libresoc.v:141665$6787 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:131937.7-131937.45" - process $proc$libresoc.v:131937$6466 + attribute \src "libresoc.v:141669.7-141669.45" + process $proc$libresoc.v:141669$6788 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:131941.7-131941.45" - process $proc$libresoc.v:131941$6467 + attribute \src "libresoc.v:141673.7-141673.45" + process $proc$libresoc.v:141673$6789 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:131945.7-131945.48" - process $proc$libresoc.v:131945$6468 + attribute \src "libresoc.v:141677.7-141677.48" + process $proc$libresoc.v:141677$6790 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:131949.7-131949.45" - process $proc$libresoc.v:131949$6469 + attribute \src "libresoc.v:141681.7-141681.45" + process $proc$libresoc.v:141681$6791 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:131975.7-131975.27" - process $proc$libresoc.v:131975$6470 + attribute \src "libresoc.v:141707.7-141707.27" + process $proc$libresoc.v:141707$6792 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:132009.14-132009.47" - process $proc$libresoc.v:132009$6471 + attribute \src "libresoc.v:141741.14-141741.47" + process $proc$libresoc.v:141741$6793 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:132013.7-132013.27" - process $proc$libresoc.v:132013$6472 + attribute \src "libresoc.v:141745.7-141745.27" + process $proc$libresoc.v:141745$6794 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:132017.13-132017.33" - process $proc$libresoc.v:132017$6473 + attribute \src "libresoc.v:141749.13-141749.33" + process $proc$libresoc.v:141749$6795 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:132021.7-132021.30" - process $proc$libresoc.v:132021$6474 + attribute \src "libresoc.v:141753.7-141753.30" + process $proc$libresoc.v:141753$6796 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:132035.7-132035.25" - process $proc$libresoc.v:132035$6475 + attribute \src "libresoc.v:141767.7-141767.25" + process $proc$libresoc.v:141767$6797 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:132039.7-132039.25" - process $proc$libresoc.v:132039$6476 + attribute \src "libresoc.v:141771.7-141771.25" + process $proc$libresoc.v:141771$6798 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:132170.13-132170.30" - process $proc$libresoc.v:132170$6477 + attribute \src "libresoc.v:141905.13-141905.30" + process $proc$libresoc.v:141905$6799 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:132178.13-132178.31" - process $proc$libresoc.v:132178$6478 + attribute \src "libresoc.v:141913.13-141913.31" + process $proc$libresoc.v:141913$6800 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:132182.13-132182.31" - process $proc$libresoc.v:132182$6479 + attribute \src "libresoc.v:141917.13-141917.31" + process $proc$libresoc.v:141917$6801 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:132194.7-132194.26" - process $proc$libresoc.v:132194$6480 + attribute \src "libresoc.v:141929.7-141929.26" + process $proc$libresoc.v:141929$6802 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:132198.7-132198.26" - process $proc$libresoc.v:132198$6481 + attribute \src "libresoc.v:141933.7-141933.26" + process $proc$libresoc.v:141933$6803 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:132202.7-132202.25" - process $proc$libresoc.v:132202$6482 + attribute \src "libresoc.v:141937.7-141937.25" + process $proc$libresoc.v:141937$6804 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:132206.7-132206.25" - process $proc$libresoc.v:132206$6483 + attribute \src "libresoc.v:141941.7-141941.25" + process $proc$libresoc.v:141941$6805 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:132220.13-132220.31" - process $proc$libresoc.v:132220$6484 + attribute \src "libresoc.v:141955.13-141955.31" + process $proc$libresoc.v:141955$6806 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:132224.13-132224.31" - process $proc$libresoc.v:132224$6485 + attribute \src "libresoc.v:141959.13-141959.31" + process $proc$libresoc.v:141959$6807 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:132232.14-132232.43" - process $proc$libresoc.v:132232$6486 + attribute \src "libresoc.v:141967.14-141967.43" + process $proc$libresoc.v:141967$6808 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:132236.14-132236.43" - process $proc$libresoc.v:132236$6487 + attribute \src "libresoc.v:141971.14-141971.43" + process $proc$libresoc.v:141971$6809 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:132240.7-132240.20" - process $proc$libresoc.v:132240$6488 + attribute \src "libresoc.v:141975.7-141975.20" + process $proc$libresoc.v:141975$6810 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:132306.3-132307.39" - process $proc$libresoc.v:132306$6298 + attribute \src "libresoc.v:142041.3-142042.39" + process $proc$libresoc.v:142041$6620 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:132308.3-132309.43" - process $proc$libresoc.v:132308$6299 + attribute \src "libresoc.v:142043.3-142044.43" + process $proc$libresoc.v:142043$6621 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:132310.3-132311.29" - process $proc$libresoc.v:132310$6300 + attribute \src "libresoc.v:142045.3-142046.29" + process $proc$libresoc.v:142045$6622 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:132312.3-132313.29" - process $proc$libresoc.v:132312$6301 + attribute \src "libresoc.v:142047.3-142048.29" + process $proc$libresoc.v:142047$6623 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:132314.3-132315.29" - process $proc$libresoc.v:132314$6302 + attribute \src "libresoc.v:142049.3-142050.29" + process $proc$libresoc.v:142049$6624 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:132316.3-132317.43" - process $proc$libresoc.v:132316$6303 + attribute \src "libresoc.v:142051.3-142052.43" + process $proc$libresoc.v:142051$6625 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:132318.3-132319.49" - process $proc$libresoc.v:132318$6304 + attribute \src "libresoc.v:142053.3-142054.49" + process $proc$libresoc.v:142053$6626 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:132320.3-132321.37" - process $proc$libresoc.v:132320$6305 + attribute \src "libresoc.v:142055.3-142056.37" + process $proc$libresoc.v:142055$6627 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:132322.3-132323.43" - process $proc$libresoc.v:132322$6306 + attribute \src "libresoc.v:142057.3-142058.43" + process $proc$libresoc.v:142057$6628 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:132324.3-132325.85" - process $proc$libresoc.v:132324$6307 + attribute \src "libresoc.v:142059.3-142060.85" + process $proc$libresoc.v:142059$6629 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:132326.3-132327.81" - process $proc$libresoc.v:132326$6308 + attribute \src "libresoc.v:142061.3-142062.81" + process $proc$libresoc.v:142061$6630 assign { } { } - assign $0\alu_logical0_logical_op__fn_unit[11:0] \alu_logical0_logical_op__fn_unit$next + assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk - update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[11:0] + update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:132328.3-132329.95" - process $proc$libresoc.v:132328$6309 + attribute \src "libresoc.v:142063.3-142064.95" + process $proc$libresoc.v:142063$6631 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:132330.3-132331.91" - process $proc$libresoc.v:132330$6310 + attribute \src "libresoc.v:142065.3-142066.91" + process $proc$libresoc.v:142065$6632 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:132332.3-132333.79" - process $proc$libresoc.v:132332$6311 + attribute \src "libresoc.v:142067.3-142068.79" + process $proc$libresoc.v:142067$6633 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:132334.3-132335.79" - process $proc$libresoc.v:132334$6312 + attribute \src "libresoc.v:142069.3-142070.79" + process $proc$libresoc.v:142069$6634 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:132336.3-132337.79" - process $proc$libresoc.v:132336$6313 + attribute \src "libresoc.v:142071.3-142072.79" + process $proc$libresoc.v:142071$6635 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:132338.3-132339.79" - process $proc$libresoc.v:132338$6314 + attribute \src "libresoc.v:142073.3-142074.79" + process $proc$libresoc.v:142073$6636 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:132340.3-132341.85" - process $proc$libresoc.v:132340$6315 + attribute \src "libresoc.v:142075.3-142076.85" + process $proc$libresoc.v:142075$6637 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:132342.3-132343.79" - process $proc$libresoc.v:132342$6316 + attribute \src "libresoc.v:142077.3-142078.79" + process $proc$libresoc.v:142077$6638 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:132344.3-132345.89" - process $proc$libresoc.v:132344$6317 + attribute \src "libresoc.v:142079.3-142080.89" + process $proc$libresoc.v:142079$6639 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:132346.3-132347.87" - process $proc$libresoc.v:132346$6318 + attribute \src "libresoc.v:142081.3-142082.87" + process $proc$libresoc.v:142081$6640 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:132348.3-132349.85" - process $proc$libresoc.v:132348$6319 + attribute \src "libresoc.v:142083.3-142084.85" + process $proc$libresoc.v:142083$6641 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:132350.3-132351.91" - process $proc$libresoc.v:132350$6320 + attribute \src "libresoc.v:142085.3-142086.91" + process $proc$libresoc.v:142085$6642 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:132352.3-132353.83" - process $proc$libresoc.v:132352$6321 + attribute \src "libresoc.v:142087.3-142088.83" + process $proc$libresoc.v:142087$6643 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:132354.3-132355.85" - process $proc$libresoc.v:132354$6322 + attribute \src "libresoc.v:142089.3-142090.85" + process $proc$libresoc.v:142089$6644 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:132356.3-132357.83" - process $proc$libresoc.v:132356$6323 + attribute \src "libresoc.v:142091.3-142092.83" + process $proc$libresoc.v:142091$6645 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:132358.3-132359.75" - process $proc$libresoc.v:132358$6324 + attribute \src "libresoc.v:142093.3-142094.75" + process $proc$libresoc.v:142093$6646 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:132360.3-132361.39" - process $proc$libresoc.v:132360$6325 + attribute \src "libresoc.v:142095.3-142096.39" + process $proc$libresoc.v:142095$6647 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:132362.3-132363.39" - process $proc$libresoc.v:132362$6326 + attribute \src "libresoc.v:142097.3-142098.39" + process $proc$libresoc.v:142097$6648 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:132364.3-132365.39" - process $proc$libresoc.v:132364$6327 + attribute \src "libresoc.v:142099.3-142100.39" + process $proc$libresoc.v:142099$6649 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:132366.3-132367.39" - process $proc$libresoc.v:132366$6328 + attribute \src "libresoc.v:142101.3-142102.39" + process $proc$libresoc.v:142101$6650 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:132368.3-132369.39" - process $proc$libresoc.v:132368$6329 + attribute \src "libresoc.v:142103.3-142104.39" + process $proc$libresoc.v:142103$6651 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:132370.3-132371.39" - process $proc$libresoc.v:132370$6330 + attribute \src "libresoc.v:142105.3-142106.39" + process $proc$libresoc.v:142105$6652 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:132372.3-132373.39" - process $proc$libresoc.v:132372$6331 + attribute \src "libresoc.v:142107.3-142108.39" + process $proc$libresoc.v:142107$6653 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:132374.3-132375.39" - process $proc$libresoc.v:132374$6332 + attribute \src "libresoc.v:142109.3-142110.39" + process $proc$libresoc.v:142109$6654 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:132376.3-132377.41" - process $proc$libresoc.v:132376$6333 + attribute \src "libresoc.v:142111.3-142112.41" + process $proc$libresoc.v:142111$6655 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:132378.3-132379.41" - process $proc$libresoc.v:132378$6334 + attribute \src "libresoc.v:142113.3-142114.41" + process $proc$libresoc.v:142113$6656 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:132380.3-132381.37" - process $proc$libresoc.v:132380$6335 + attribute \src "libresoc.v:142115.3-142116.37" + process $proc$libresoc.v:142115$6657 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:132382.3-132383.44" - process $proc$libresoc.v:132382$6336 + attribute \src "libresoc.v:142117.3-142118.44" + process $proc$libresoc.v:142117$6658 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:132384.3-132385.24" - process $proc$libresoc.v:132384$6337 + attribute \src "libresoc.v:142119.3-142120.24" + process $proc$libresoc.v:142119$6659 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:132467.3-132476.6" - process $proc$libresoc.v:132467$6338 + attribute \src "libresoc.v:142202.3-142211.6" + process $proc$libresoc.v:142202$6660 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:132468.5-132468.29" + attribute \src "libresoc.v:142203.5-142203.29" switch \initial - attribute \src "libresoc.v:132468.9-132468.17" + attribute \src "libresoc.v:142203.9-142203.17" case 1'1 case end @@ -215988,14 +231807,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:132477.3-132485.6" - process $proc$libresoc.v:132477$6339 + attribute \src "libresoc.v:142212.3-142220.6" + process $proc$libresoc.v:142212$6661 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6340 $1\rok_l_s_rdok$next[0:0]$6341 - attribute \src "libresoc.v:132478.5-132478.29" + assign $0\rok_l_s_rdok$next[0:0]$6662 $1\rok_l_s_rdok$next[0:0]$6663 + attribute \src "libresoc.v:142213.5-142213.29" switch \initial - attribute \src "libresoc.v:132478.9-132478.17" + attribute \src "libresoc.v:142213.9-142213.17" case 1'1 case end @@ -216004,21 +231823,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6341 1'0 + assign $1\rok_l_s_rdok$next[0:0]$6663 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$6341 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$6663 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6340 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6662 end - attribute \src "libresoc.v:132486.3-132494.6" - process $proc$libresoc.v:132486$6342 + attribute \src "libresoc.v:142221.3-142229.6" + process $proc$libresoc.v:142221$6664 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6343 $1\rok_l_r_rdok$next[0:0]$6344 - attribute \src "libresoc.v:132487.5-132487.29" + assign $0\rok_l_r_rdok$next[0:0]$6665 $1\rok_l_r_rdok$next[0:0]$6666 + attribute \src "libresoc.v:142222.5-142222.29" switch \initial - attribute \src "libresoc.v:132487.9-132487.17" + attribute \src "libresoc.v:142222.9-142222.17" case 1'1 case end @@ -216027,21 +231846,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6344 1'1 + assign $1\rok_l_r_rdok$next[0:0]$6666 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$6344 \$63 + assign $1\rok_l_r_rdok$next[0:0]$6666 \$63 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6343 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6665 end - attribute \src "libresoc.v:132495.3-132503.6" - process $proc$libresoc.v:132495$6345 + attribute \src "libresoc.v:142230.3-142238.6" + process $proc$libresoc.v:142230$6667 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6346 $1\rst_l_s_rst$next[0:0]$6347 - attribute \src "libresoc.v:132496.5-132496.29" + assign $0\rst_l_s_rst$next[0:0]$6668 $1\rst_l_s_rst$next[0:0]$6669 + attribute \src "libresoc.v:142231.5-142231.29" switch \initial - attribute \src "libresoc.v:132496.9-132496.17" + attribute \src "libresoc.v:142231.9-142231.17" case 1'1 case end @@ -216050,21 +231869,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6347 1'0 + assign $1\rst_l_s_rst$next[0:0]$6669 1'0 case - assign $1\rst_l_s_rst$next[0:0]$6347 \all_rd + assign $1\rst_l_s_rst$next[0:0]$6669 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6346 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6668 end - attribute \src "libresoc.v:132504.3-132512.6" - process $proc$libresoc.v:132504$6348 + attribute \src "libresoc.v:142239.3-142247.6" + process $proc$libresoc.v:142239$6670 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6349 $1\rst_l_r_rst$next[0:0]$6350 - attribute \src "libresoc.v:132505.5-132505.29" + assign $0\rst_l_r_rst$next[0:0]$6671 $1\rst_l_r_rst$next[0:0]$6672 + attribute \src "libresoc.v:142240.5-142240.29" switch \initial - attribute \src "libresoc.v:132505.9-132505.17" + attribute \src "libresoc.v:142240.9-142240.17" case 1'1 case end @@ -216073,21 +231892,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6350 1'1 + assign $1\rst_l_r_rst$next[0:0]$6672 1'1 case - assign $1\rst_l_r_rst$next[0:0]$6350 \rst_r + assign $1\rst_l_r_rst$next[0:0]$6672 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6349 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6671 end - attribute \src "libresoc.v:132513.3-132521.6" - process $proc$libresoc.v:132513$6351 + attribute \src "libresoc.v:142248.3-142256.6" + process $proc$libresoc.v:142248$6673 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6352 $1\opc_l_s_opc$next[0:0]$6353 - attribute \src "libresoc.v:132514.5-132514.29" + assign $0\opc_l_s_opc$next[0:0]$6674 $1\opc_l_s_opc$next[0:0]$6675 + attribute \src "libresoc.v:142249.5-142249.29" switch \initial - attribute \src "libresoc.v:132514.9-132514.17" + attribute \src "libresoc.v:142249.9-142249.17" case 1'1 case end @@ -216096,21 +231915,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6353 1'0 + assign $1\opc_l_s_opc$next[0:0]$6675 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6353 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6675 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6352 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6674 end - attribute \src "libresoc.v:132522.3-132530.6" - process $proc$libresoc.v:132522$6354 + attribute \src "libresoc.v:142257.3-142265.6" + process $proc$libresoc.v:142257$6676 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6355 $1\opc_l_r_opc$next[0:0]$6356 - attribute \src "libresoc.v:132523.5-132523.29" + assign $0\opc_l_r_opc$next[0:0]$6677 $1\opc_l_r_opc$next[0:0]$6678 + attribute \src "libresoc.v:142258.5-142258.29" switch \initial - attribute \src "libresoc.v:132523.9-132523.17" + attribute \src "libresoc.v:142258.9-142258.17" case 1'1 case end @@ -216119,21 +231938,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6356 1'1 + assign $1\opc_l_r_opc$next[0:0]$6678 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6356 \req_done + assign $1\opc_l_r_opc$next[0:0]$6678 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6355 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6677 end - attribute \src "libresoc.v:132531.3-132539.6" - process $proc$libresoc.v:132531$6357 + attribute \src "libresoc.v:142266.3-142274.6" + process $proc$libresoc.v:142266$6679 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6358 $1\src_l_s_src$next[2:0]$6359 - attribute \src "libresoc.v:132532.5-132532.29" + assign $0\src_l_s_src$next[2:0]$6680 $1\src_l_s_src$next[2:0]$6681 + attribute \src "libresoc.v:142267.5-142267.29" switch \initial - attribute \src "libresoc.v:132532.9-132532.17" + attribute \src "libresoc.v:142267.9-142267.17" case 1'1 case end @@ -216142,21 +231961,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6359 3'000 + assign $1\src_l_s_src$next[2:0]$6681 3'000 case - assign $1\src_l_s_src$next[2:0]$6359 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6681 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6358 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6680 end - attribute \src "libresoc.v:132540.3-132548.6" - process $proc$libresoc.v:132540$6360 + attribute \src "libresoc.v:142275.3-142283.6" + process $proc$libresoc.v:142275$6682 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6361 $1\src_l_r_src$next[2:0]$6362 - attribute \src "libresoc.v:132541.5-132541.29" + assign $0\src_l_r_src$next[2:0]$6683 $1\src_l_r_src$next[2:0]$6684 + attribute \src "libresoc.v:142276.5-142276.29" switch \initial - attribute \src "libresoc.v:132541.9-132541.17" + attribute \src "libresoc.v:142276.9-142276.17" case 1'1 case end @@ -216165,21 +231984,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6362 3'111 + assign $1\src_l_r_src$next[2:0]$6684 3'111 case - assign $1\src_l_r_src$next[2:0]$6362 \reset_r + assign $1\src_l_r_src$next[2:0]$6684 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6361 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6683 end - attribute \src "libresoc.v:132549.3-132557.6" - process $proc$libresoc.v:132549$6363 + attribute \src "libresoc.v:142284.3-142292.6" + process $proc$libresoc.v:142284$6685 assign { } { } assign { } { } - assign $0\req_l_s_req$next[1:0]$6364 $1\req_l_s_req$next[1:0]$6365 - attribute \src "libresoc.v:132550.5-132550.29" + assign $0\req_l_s_req$next[1:0]$6686 $1\req_l_s_req$next[1:0]$6687 + attribute \src "libresoc.v:142285.5-142285.29" switch \initial - attribute \src "libresoc.v:132550.9-132550.17" + attribute \src "libresoc.v:142285.9-142285.17" case 1'1 case end @@ -216188,21 +232007,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[1:0]$6365 2'00 + assign $1\req_l_s_req$next[1:0]$6687 2'00 case - assign $1\req_l_s_req$next[1:0]$6365 \$65 + assign $1\req_l_s_req$next[1:0]$6687 \$65 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6364 + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6686 end - attribute \src "libresoc.v:132558.3-132566.6" - process $proc$libresoc.v:132558$6366 + attribute \src "libresoc.v:142293.3-142301.6" + process $proc$libresoc.v:142293$6688 assign { } { } assign { } { } - assign $0\req_l_r_req$next[1:0]$6367 $1\req_l_r_req$next[1:0]$6368 - attribute \src "libresoc.v:132559.5-132559.29" + assign $0\req_l_r_req$next[1:0]$6689 $1\req_l_r_req$next[1:0]$6690 + attribute \src "libresoc.v:142294.5-142294.29" switch \initial - attribute \src "libresoc.v:132559.9-132559.17" + attribute \src "libresoc.v:142294.9-142294.17" case 1'1 case end @@ -216211,15 +232030,15 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[1:0]$6368 2'11 + assign $1\req_l_r_req$next[1:0]$6690 2'11 case - assign $1\req_l_r_req$next[1:0]$6368 \$67 + assign $1\req_l_r_req$next[1:0]$6690 \$67 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6367 + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6689 end - attribute \src "libresoc.v:132567.3-132605.6" - process $proc$libresoc.v:132567$6369 + attribute \src "libresoc.v:142302.3-142340.6" + process $proc$libresoc.v:142302$6691 assign { } { } assign { } { } assign { } { } @@ -216256,33 +232075,33 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6370 $1\alu_logical0_logical_op__data_len$next[3:0]$6388 - assign $0\alu_logical0_logical_op__fn_unit$next[11:0]$6371 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6389 + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6692 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 + assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6374 $1\alu_logical0_logical_op__input_carry$next[1:0]$6392 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6375 $1\alu_logical0_logical_op__insn$next[31:0]$6393 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6376 $1\alu_logical0_logical_op__insn_type$next[6:0]$6394 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6377 $1\alu_logical0_logical_op__invert_in$next[0:0]$6395 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6378 $1\alu_logical0_logical_op__invert_out$next[0:0]$6396 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6379 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6397 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6380 $1\alu_logical0_logical_op__is_signed$next[0:0]$6398 + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6697 $1\alu_logical0_logical_op__insn$next[31:0]$6715 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6383 $1\alu_logical0_logical_op__output_carry$next[0:0]$6401 + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6386 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6404 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6387 $1\alu_logical0_logical_op__zero_a$next[0:0]$6405 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6372 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6406 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6373 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6407 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6381 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6408 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6382 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6409 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6384 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6410 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6385 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6411 - attribute \src "libresoc.v:132568.5-132568.29" + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 + attribute \src "libresoc.v:142303.5-142303.29" switch \initial - attribute \src "libresoc.v:132568.9-132568.17" + attribute \src "libresoc.v:142303.9-142303.17" case 1'1 case end @@ -216308,26 +232127,26 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6393 $1\alu_logical0_logical_op__data_len$next[3:0]$6388 $1\alu_logical0_logical_op__is_signed$next[0:0]$6398 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6397 $1\alu_logical0_logical_op__output_carry$next[0:0]$6401 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6404 $1\alu_logical0_logical_op__invert_out$next[0:0]$6396 $1\alu_logical0_logical_op__input_carry$next[1:0]$6392 $1\alu_logical0_logical_op__zero_a$next[0:0]$6405 $1\alu_logical0_logical_op__invert_in$next[0:0]$6395 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6400 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6399 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6402 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6403 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6391 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6390 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6389 $1\alu_logical0_logical_op__insn_type$next[6:0]$6394 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6715 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6388 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[11:0]$6389 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6390 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6391 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6392 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6393 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6394 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6395 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6396 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6397 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6398 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6399 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6400 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6401 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6402 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6403 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6404 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6405 \alu_logical0_logical_op__zero_a + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6710 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6715 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -216339,54 +232158,54 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6406 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6407 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6411 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6410 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6408 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6409 1'0 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 1'0 case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6406 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6390 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6407 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6391 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6408 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6399 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6409 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6400 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6410 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6402 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6411 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6403 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 end sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6370 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[11:0]$6371 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6372 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6373 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6374 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6375 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6376 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6377 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6378 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6379 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6380 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6381 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6382 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6383 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6384 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6385 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6386 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6387 + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6692 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6697 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 end - attribute \src "libresoc.v:132606.3-132627.6" - process $proc$libresoc.v:132606$6412 + attribute \src "libresoc.v:142341.3-142362.6" + process $proc$libresoc.v:142341$6734 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$6413 $2\data_r0__o$next[63:0]$6417 + assign $0\data_r0__o$next[63:0]$6735 $2\data_r0__o$next[63:0]$6739 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6414 $3\data_r0__o_ok$next[0:0]$6419 - attribute \src "libresoc.v:132607.5-132607.29" + assign $0\data_r0__o_ok$next[0:0]$6736 $3\data_r0__o_ok$next[0:0]$6741 + attribute \src "libresoc.v:142342.5-142342.29" switch \initial - attribute \src "libresoc.v:132607.9-132607.17" + attribute \src "libresoc.v:142342.9-142342.17" case 1'1 case end @@ -216396,10 +232215,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6416 $1\data_r0__o$next[63:0]$6415 } { \o_ok \alu_logical0_o } + assign { $1\data_r0__o_ok$next[0:0]$6738 $1\data_r0__o$next[63:0]$6737 } { \o_ok \alu_logical0_o } case - assign $1\data_r0__o$next[63:0]$6415 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6416 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$6737 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6738 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -216407,38 +232226,38 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6418 $2\data_r0__o$next[63:0]$6417 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$6740 $2\data_r0__o$next[63:0]$6739 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$6417 $1\data_r0__o$next[63:0]$6415 - assign $2\data_r0__o_ok$next[0:0]$6418 $1\data_r0__o_ok$next[0:0]$6416 + assign $2\data_r0__o$next[63:0]$6739 $1\data_r0__o$next[63:0]$6737 + assign $2\data_r0__o_ok$next[0:0]$6740 $1\data_r0__o_ok$next[0:0]$6738 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6419 1'0 + assign $3\data_r0__o_ok$next[0:0]$6741 1'0 case - assign $3\data_r0__o_ok$next[0:0]$6419 $2\data_r0__o_ok$next[0:0]$6418 + assign $3\data_r0__o_ok$next[0:0]$6741 $2\data_r0__o_ok$next[0:0]$6740 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6413 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6414 + update \data_r0__o$next $0\data_r0__o$next[63:0]$6735 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6736 end - attribute \src "libresoc.v:132628.3-132649.6" - process $proc$libresoc.v:132628$6420 + attribute \src "libresoc.v:142363.3-142384.6" + process $proc$libresoc.v:142363$6742 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6421 $2\data_r1__cr_a$next[3:0]$6425 + assign $0\data_r1__cr_a$next[3:0]$6743 $2\data_r1__cr_a$next[3:0]$6747 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6422 $3\data_r1__cr_a_ok$next[0:0]$6427 - attribute \src "libresoc.v:132629.5-132629.29" + assign $0\data_r1__cr_a_ok$next[0:0]$6744 $3\data_r1__cr_a_ok$next[0:0]$6749 + attribute \src "libresoc.v:142364.5-142364.29" switch \initial - attribute \src "libresoc.v:132629.9-132629.17" + attribute \src "libresoc.v:142364.9-142364.17" case 1'1 case end @@ -216448,10 +232267,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6424 $1\data_r1__cr_a$next[3:0]$6423 } { \cr_a_ok \alu_logical0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$6746 $1\data_r1__cr_a$next[3:0]$6745 } { \cr_a_ok \alu_logical0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$6423 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6424 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$6745 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6746 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -216459,101 +232278,101 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6426 $2\data_r1__cr_a$next[3:0]$6425 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$6748 $2\data_r1__cr_a$next[3:0]$6747 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$6425 $1\data_r1__cr_a$next[3:0]$6423 - assign $2\data_r1__cr_a_ok$next[0:0]$6426 $1\data_r1__cr_a_ok$next[0:0]$6424 + assign $2\data_r1__cr_a$next[3:0]$6747 $1\data_r1__cr_a$next[3:0]$6745 + assign $2\data_r1__cr_a_ok$next[0:0]$6748 $1\data_r1__cr_a_ok$next[0:0]$6746 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6427 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$6749 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$6427 $2\data_r1__cr_a_ok$next[0:0]$6426 + assign $3\data_r1__cr_a_ok$next[0:0]$6749 $2\data_r1__cr_a_ok$next[0:0]$6748 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6421 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6422 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6743 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6744 end - attribute \src "libresoc.v:132650.3-132659.6" - process $proc$libresoc.v:132650$6428 + attribute \src "libresoc.v:142385.3-142394.6" + process $proc$libresoc.v:142385$6750 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6429 $1\src_r0$next[63:0]$6430 - attribute \src "libresoc.v:132651.5-132651.29" + assign $0\src_r0$next[63:0]$6751 $1\src_r0$next[63:0]$6752 + attribute \src "libresoc.v:142386.5-142386.29" switch \initial - attribute \src "libresoc.v:132651.9-132651.17" + attribute \src "libresoc.v:142386.9-142386.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6430 \src_or_imm + assign $1\src_r0$next[63:0]$6752 \src_or_imm case - assign $1\src_r0$next[63:0]$6430 \src_r0 + assign $1\src_r0$next[63:0]$6752 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6429 + update \src_r0$next $0\src_r0$next[63:0]$6751 end - attribute \src "libresoc.v:132660.3-132669.6" - process $proc$libresoc.v:132660$6431 + attribute \src "libresoc.v:142395.3-142404.6" + process $proc$libresoc.v:142395$6753 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6432 $1\src_r1$next[63:0]$6433 - attribute \src "libresoc.v:132661.5-132661.29" + assign $0\src_r1$next[63:0]$6754 $1\src_r1$next[63:0]$6755 + attribute \src "libresoc.v:142396.5-142396.29" switch \initial - attribute \src "libresoc.v:132661.9-132661.17" + attribute \src "libresoc.v:142396.9-142396.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6433 \src_or_imm$80 + assign $1\src_r1$next[63:0]$6755 \src_or_imm$80 case - assign $1\src_r1$next[63:0]$6433 \src_r1 + assign $1\src_r1$next[63:0]$6755 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6432 + update \src_r1$next $0\src_r1$next[63:0]$6754 end - attribute \src "libresoc.v:132670.3-132679.6" - process $proc$libresoc.v:132670$6434 + attribute \src "libresoc.v:142405.3-142414.6" + process $proc$libresoc.v:142405$6756 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$6435 $1\src_r2$next[0:0]$6436 - attribute \src "libresoc.v:132671.5-132671.29" + assign $0\src_r2$next[0:0]$6757 $1\src_r2$next[0:0]$6758 + attribute \src "libresoc.v:142406.5-142406.29" switch \initial - attribute \src "libresoc.v:132671.9-132671.17" + attribute \src "libresoc.v:142406.9-142406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$6436 \src3_i + assign $1\src_r2$next[0:0]$6758 \src3_i case - assign $1\src_r2$next[0:0]$6436 \src_r2 + assign $1\src_r2$next[0:0]$6758 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$6435 + update \src_r2$next $0\src_r2$next[0:0]$6757 end - attribute \src "libresoc.v:132680.3-132688.6" - process $proc$libresoc.v:132680$6437 + attribute \src "libresoc.v:142415.3-142423.6" + process $proc$libresoc.v:142415$6759 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6438 $1\alui_l_r_alui$next[0:0]$6439 - attribute \src "libresoc.v:132681.5-132681.29" + assign $0\alui_l_r_alui$next[0:0]$6760 $1\alui_l_r_alui$next[0:0]$6761 + attribute \src "libresoc.v:142416.5-142416.29" switch \initial - attribute \src "libresoc.v:132681.9-132681.17" + attribute \src "libresoc.v:142416.9-142416.17" case 1'1 case end @@ -216562,21 +232381,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6439 1'1 + assign $1\alui_l_r_alui$next[0:0]$6761 1'1 case - assign $1\alui_l_r_alui$next[0:0]$6439 \$89 + assign $1\alui_l_r_alui$next[0:0]$6761 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6438 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6760 end - attribute \src "libresoc.v:132689.3-132697.6" - process $proc$libresoc.v:132689$6440 + attribute \src "libresoc.v:142424.3-142432.6" + process $proc$libresoc.v:142424$6762 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6441 $1\alu_l_r_alu$next[0:0]$6442 - attribute \src "libresoc.v:132690.5-132690.29" + assign $0\alu_l_r_alu$next[0:0]$6763 $1\alu_l_r_alu$next[0:0]$6764 + attribute \src "libresoc.v:142425.5-142425.29" switch \initial - attribute \src "libresoc.v:132690.9-132690.17" + attribute \src "libresoc.v:142425.9-142425.17" case 1'1 case end @@ -216585,21 +232404,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6442 1'1 + assign $1\alu_l_r_alu$next[0:0]$6764 1'1 case - assign $1\alu_l_r_alu$next[0:0]$6442 \$91 + assign $1\alu_l_r_alu$next[0:0]$6764 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6441 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6763 end - attribute \src "libresoc.v:132698.3-132707.6" - process $proc$libresoc.v:132698$6443 + attribute \src "libresoc.v:142433.3-142442.6" + process $proc$libresoc.v:142433$6765 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:132699.5-132699.29" + attribute \src "libresoc.v:142434.5-142434.29" switch \initial - attribute \src "libresoc.v:132699.9-132699.17" + attribute \src "libresoc.v:142434.9-142434.17" case 1'1 case end @@ -216615,14 +232434,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:132708.3-132717.6" - process $proc$libresoc.v:132708$6444 + attribute \src "libresoc.v:142443.3-142452.6" + process $proc$libresoc.v:142443$6766 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:132709.5-132709.29" + attribute \src "libresoc.v:142444.5-142444.29" switch \initial - attribute \src "libresoc.v:132709.9-132709.17" + attribute \src "libresoc.v:142444.9-142444.17" case 1'1 case end @@ -216638,14 +232457,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:132718.3-132726.6" - process $proc$libresoc.v:132718$6445 + attribute \src "libresoc.v:142453.3-142461.6" + process $proc$libresoc.v:142453$6767 assign { } { } assign { } { } - assign $0\prev_wr_go$next[1:0]$6446 $1\prev_wr_go$next[1:0]$6447 - attribute \src "libresoc.v:132719.5-132719.29" + assign $0\prev_wr_go$next[1:0]$6768 $1\prev_wr_go$next[1:0]$6769 + attribute \src "libresoc.v:142454.5-142454.29" switch \initial - attribute \src "libresoc.v:132719.9-132719.17" + attribute \src "libresoc.v:142454.9-142454.17" case 1'1 case end @@ -216654,70 +232473,70 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[1:0]$6447 2'00 - case - assign $1\prev_wr_go$next[1:0]$6447 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6446 - end - connect \$9 $and$libresoc.v:132249$6241_Y - connect \$99 $and$libresoc.v:132250$6242_Y - connect \$101 $not$libresoc.v:132251$6243_Y - connect \$103 $and$libresoc.v:132252$6244_Y - connect \$105 $and$libresoc.v:132253$6245_Y - connect \$107 $and$libresoc.v:132254$6246_Y - connect \$109 $and$libresoc.v:132255$6247_Y - connect \$111 $and$libresoc.v:132256$6248_Y - connect \$113 $and$libresoc.v:132257$6249_Y - connect \$115 $and$libresoc.v:132258$6250_Y - connect \$11 $not$libresoc.v:132259$6251_Y - connect \$13 $and$libresoc.v:132260$6252_Y - connect \$15 $not$libresoc.v:132261$6253_Y - connect \$17 $and$libresoc.v:132262$6254_Y - connect \$1 $and$libresoc.v:132263$6255_Y - connect \$19 $and$libresoc.v:132264$6256_Y - connect \$23 $not$libresoc.v:132265$6257_Y - connect \$25 $and$libresoc.v:132266$6258_Y - connect \$22 $reduce_or$libresoc.v:132267$6259_Y - connect \$21 $not$libresoc.v:132268$6260_Y - connect \$29 $and$libresoc.v:132269$6261_Y - connect \$31 $reduce_or$libresoc.v:132270$6262_Y - connect \$33 $reduce_or$libresoc.v:132271$6263_Y - connect \$35 $or$libresoc.v:132272$6264_Y - connect \$37 $not$libresoc.v:132273$6265_Y - connect \$39 $and$libresoc.v:132274$6266_Y - connect \$41 $and$libresoc.v:132275$6267_Y - connect \$43 $eq$libresoc.v:132276$6268_Y - connect \$45 $and$libresoc.v:132277$6269_Y - connect \$47 $eq$libresoc.v:132278$6270_Y - connect \$4 $not$libresoc.v:132279$6271_Y - connect \$49 $and$libresoc.v:132280$6272_Y - connect \$51 $and$libresoc.v:132281$6273_Y - connect \$53 $and$libresoc.v:132282$6274_Y - connect \$55 $or$libresoc.v:132283$6275_Y - connect \$57 $or$libresoc.v:132284$6276_Y - connect \$59 $or$libresoc.v:132285$6277_Y - connect \$61 $or$libresoc.v:132286$6278_Y - connect \$63 $and$libresoc.v:132287$6279_Y - connect \$65 $and$libresoc.v:132288$6280_Y - connect \$67 $or$libresoc.v:132289$6281_Y - connect \$6 $or$libresoc.v:132290$6282_Y - connect \$69 $and$libresoc.v:132291$6283_Y - connect \$71 $and$libresoc.v:132292$6284_Y - connect \$73 $ternary$libresoc.v:132293$6285_Y - connect \$75 $ternary$libresoc.v:132294$6286_Y - connect \$78 $ternary$libresoc.v:132295$6287_Y - connect \$3 $reduce_and$libresoc.v:132296$6288_Y - connect \$81 $ternary$libresoc.v:132297$6289_Y - connect \$83 $ternary$libresoc.v:132298$6290_Y - connect \$85 $ternary$libresoc.v:132299$6291_Y - connect \$87 $ternary$libresoc.v:132300$6292_Y - connect \$89 $and$libresoc.v:132301$6293_Y - connect \$91 $and$libresoc.v:132302$6294_Y - connect \$93 $and$libresoc.v:132303$6295_Y - connect \$95 $not$libresoc.v:132304$6296_Y - connect \$97 $not$libresoc.v:132305$6297_Y + assign $1\prev_wr_go$next[1:0]$6769 2'00 + case + assign $1\prev_wr_go$next[1:0]$6769 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6768 + end + connect \$9 $and$libresoc.v:141984$6563_Y + connect \$99 $and$libresoc.v:141985$6564_Y + connect \$101 $not$libresoc.v:141986$6565_Y + connect \$103 $and$libresoc.v:141987$6566_Y + connect \$105 $and$libresoc.v:141988$6567_Y + connect \$107 $and$libresoc.v:141989$6568_Y + connect \$109 $and$libresoc.v:141990$6569_Y + connect \$111 $and$libresoc.v:141991$6570_Y + connect \$113 $and$libresoc.v:141992$6571_Y + connect \$115 $and$libresoc.v:141993$6572_Y + connect \$11 $not$libresoc.v:141994$6573_Y + connect \$13 $and$libresoc.v:141995$6574_Y + connect \$15 $not$libresoc.v:141996$6575_Y + connect \$17 $and$libresoc.v:141997$6576_Y + connect \$1 $and$libresoc.v:141998$6577_Y + connect \$19 $and$libresoc.v:141999$6578_Y + connect \$23 $not$libresoc.v:142000$6579_Y + connect \$25 $and$libresoc.v:142001$6580_Y + connect \$22 $reduce_or$libresoc.v:142002$6581_Y + connect \$21 $not$libresoc.v:142003$6582_Y + connect \$29 $and$libresoc.v:142004$6583_Y + connect \$31 $reduce_or$libresoc.v:142005$6584_Y + connect \$33 $reduce_or$libresoc.v:142006$6585_Y + connect \$35 $or$libresoc.v:142007$6586_Y + connect \$37 $not$libresoc.v:142008$6587_Y + connect \$39 $and$libresoc.v:142009$6588_Y + connect \$41 $and$libresoc.v:142010$6589_Y + connect \$43 $eq$libresoc.v:142011$6590_Y + connect \$45 $and$libresoc.v:142012$6591_Y + connect \$47 $eq$libresoc.v:142013$6592_Y + connect \$4 $not$libresoc.v:142014$6593_Y + connect \$49 $and$libresoc.v:142015$6594_Y + connect \$51 $and$libresoc.v:142016$6595_Y + connect \$53 $and$libresoc.v:142017$6596_Y + connect \$55 $or$libresoc.v:142018$6597_Y + connect \$57 $or$libresoc.v:142019$6598_Y + connect \$59 $or$libresoc.v:142020$6599_Y + connect \$61 $or$libresoc.v:142021$6600_Y + connect \$63 $and$libresoc.v:142022$6601_Y + connect \$65 $and$libresoc.v:142023$6602_Y + connect \$67 $or$libresoc.v:142024$6603_Y + connect \$6 $or$libresoc.v:142025$6604_Y + connect \$69 $and$libresoc.v:142026$6605_Y + connect \$71 $and$libresoc.v:142027$6606_Y + connect \$73 $ternary$libresoc.v:142028$6607_Y + connect \$75 $ternary$libresoc.v:142029$6608_Y + connect \$78 $ternary$libresoc.v:142030$6609_Y + connect \$3 $reduce_and$libresoc.v:142031$6610_Y + connect \$81 $ternary$libresoc.v:142032$6611_Y + connect \$83 $ternary$libresoc.v:142033$6612_Y + connect \$85 $ternary$libresoc.v:142034$6613_Y + connect \$87 $ternary$libresoc.v:142035$6614_Y + connect \$89 $and$libresoc.v:142036$6615_Y + connect \$91 $and$libresoc.v:142037$6616_Y + connect \$93 $and$libresoc.v:142038$6617_Y + connect \$95 $not$libresoc.v:142039$6618_Y + connect \$97 $not$libresoc.v:142040$6619_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -216751,248 +232570,248 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:132763.1-134133.10" +attribute \src "libresoc.v:142498.1-143889.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:134072.3-134090.6" - wire width 4 $0\cr_a$next[3:0]$6573 - attribute \src "libresoc.v:133832.3-133833.25" + attribute \src "libresoc.v:143828.3-143846.6" + wire width 4 $0\cr_a$next[3:0]$6895 + attribute \src "libresoc.v:143588.3-143589.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:134072.3-134090.6" - wire $0\cr_a_ok$next[0:0]$6574 - attribute \src "libresoc.v:133834.3-133835.31" + attribute \src "libresoc.v:143828.3-143846.6" + wire $0\cr_a_ok$next[0:0]$6896 + attribute \src "libresoc.v:143590.3-143591.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:132764.7-132764.20" + attribute \src "libresoc.v:142499.7-142499.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 4 $0\logical_op__data_len$next[3:0]$6524 - attribute \src "libresoc.v:133872.3-133873.57" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6846 + attribute \src "libresoc.v:143628.3-143629.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 12 $0\logical_op__fn_unit$next[11:0]$6525 - attribute \src "libresoc.v:133842.3-133843.55" - wire width 12 $0\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$6526 - attribute \src "libresoc.v:133844.3-133845.69" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$6847 + attribute \src "libresoc.v:143598.3-143599.55" + wire width 14 $0\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:143767.3-143808.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6848 + attribute \src "libresoc.v:143600.3-143601.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__imm_data__ok$next[0:0]$6527 - attribute \src "libresoc.v:133846.3-133847.65" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6849 + attribute \src "libresoc.v:143602.3-143603.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$6528 - attribute \src "libresoc.v:133860.3-133861.63" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6850 + attribute \src "libresoc.v:143616.3-143617.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 32 $0\logical_op__insn$next[31:0]$6529 - attribute \src "libresoc.v:133874.3-133875.49" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 32 $0\logical_op__insn$next[31:0]$6851 + attribute \src "libresoc.v:143630.3-143631.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$6530 - attribute \src "libresoc.v:133840.3-133841.59" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6852 + attribute \src "libresoc.v:143596.3-143597.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__invert_in$next[0:0]$6531 - attribute \src "libresoc.v:133856.3-133857.59" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__invert_in$next[0:0]$6853 + attribute \src "libresoc.v:143612.3-143613.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__invert_out$next[0:0]$6532 - attribute \src "libresoc.v:133862.3-133863.61" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__invert_out$next[0:0]$6854 + attribute \src "libresoc.v:143618.3-143619.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__is_32bit$next[0:0]$6533 - attribute \src "libresoc.v:133868.3-133869.57" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__is_32bit$next[0:0]$6855 + attribute \src "libresoc.v:143624.3-143625.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__is_signed$next[0:0]$6534 - attribute \src "libresoc.v:133870.3-133871.59" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__is_signed$next[0:0]$6856 + attribute \src "libresoc.v:143626.3-143627.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__oe__oe$next[0:0]$6535 - attribute \src "libresoc.v:133852.3-133853.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__oe__oe$next[0:0]$6857 + attribute \src "libresoc.v:143608.3-143609.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__oe__ok$next[0:0]$6536 - attribute \src "libresoc.v:133854.3-133855.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__oe__ok$next[0:0]$6858 + attribute \src "libresoc.v:143610.3-143611.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__output_carry$next[0:0]$6537 - attribute \src "libresoc.v:133866.3-133867.65" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__output_carry$next[0:0]$6859 + attribute \src "libresoc.v:143622.3-143623.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__rc__ok$next[0:0]$6538 - attribute \src "libresoc.v:133850.3-133851.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__rc__ok$next[0:0]$6860 + attribute \src "libresoc.v:143606.3-143607.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__rc__rc$next[0:0]$6539 - attribute \src "libresoc.v:133848.3-133849.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__rc__rc$next[0:0]$6861 + attribute \src "libresoc.v:143604.3-143605.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__write_cr0$next[0:0]$6540 - attribute \src "libresoc.v:133864.3-133865.59" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__write_cr0$next[0:0]$6862 + attribute \src "libresoc.v:143620.3-143621.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $0\logical_op__zero_a$next[0:0]$6541 - attribute \src "libresoc.v:133858.3-133859.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__zero_a$next[0:0]$6863 + attribute \src "libresoc.v:143614.3-143615.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:133998.3-134010.6" - wire width 2 $0\muxid$next[1:0]$6521 - attribute \src "libresoc.v:133876.3-133877.27" + attribute \src "libresoc.v:143754.3-143766.6" + wire width 2 $0\muxid$next[1:0]$6843 + attribute \src "libresoc.v:143632.3-143633.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:134053.3-134071.6" - wire width 64 $0\o$next[63:0]$6567 - attribute \src "libresoc.v:133836.3-133837.19" + attribute \src "libresoc.v:143809.3-143827.6" + wire width 64 $0\o$next[63:0]$6889 + attribute \src "libresoc.v:143592.3-143593.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:134053.3-134071.6" - wire $0\o_ok$next[0:0]$6568 - attribute \src "libresoc.v:133838.3-133839.25" + attribute \src "libresoc.v:143809.3-143827.6" + wire $0\o_ok$next[0:0]$6890 + attribute \src "libresoc.v:143594.3-143595.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:133980.3-133997.6" - wire $0\r_busy$next[0:0]$6517 - attribute \src "libresoc.v:133878.3-133879.29" + attribute \src "libresoc.v:143736.3-143753.6" + wire $0\r_busy$next[0:0]$6839 + attribute \src "libresoc.v:143634.3-143635.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:134091.3-134109.6" - wire $0\xer_so$next[0:0]$6579 - attribute \src "libresoc.v:133828.3-133829.29" + attribute \src "libresoc.v:143847.3-143865.6" + wire $0\xer_so$next[0:0]$6901 + attribute \src "libresoc.v:143584.3-143585.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:134091.3-134109.6" - wire $0\xer_so_ok$next[0:0]$6580 - attribute \src "libresoc.v:133830.3-133831.35" + attribute \src "libresoc.v:143847.3-143865.6" + wire $0\xer_so_ok$next[0:0]$6902 + attribute \src "libresoc.v:143586.3-143587.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:134072.3-134090.6" - wire width 4 $1\cr_a$next[3:0]$6575 - attribute \src "libresoc.v:132773.13-132773.24" + attribute \src "libresoc.v:143828.3-143846.6" + wire width 4 $1\cr_a$next[3:0]$6897 + attribute \src "libresoc.v:142508.13-142508.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:134072.3-134090.6" - wire $1\cr_a_ok$next[0:0]$6576 - attribute \src "libresoc.v:132782.7-132782.21" + attribute \src "libresoc.v:143828.3-143846.6" + wire $1\cr_a_ok$next[0:0]$6898 + attribute \src "libresoc.v:142517.7-142517.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 4 $1\logical_op__data_len$next[3:0]$6542 - attribute \src "libresoc.v:133061.13-133061.40" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6864 + attribute \src "libresoc.v:142802.13-142802.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 12 $1\logical_op__fn_unit$next[11:0]$6543 - attribute \src "libresoc.v:133083.14-133083.43" - wire width 12 $1\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$6544 - attribute \src "libresoc.v:133118.14-133118.63" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$6865 + attribute \src "libresoc.v:142826.14-142826.44" + wire width 14 $1\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:143767.3-143808.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6866 + attribute \src "libresoc.v:142865.14-142865.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__imm_data__ok$next[0:0]$6545 - attribute \src "libresoc.v:133127.7-133127.38" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6867 + attribute \src "libresoc.v:142874.7-142874.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$6546 - attribute \src "libresoc.v:133140.13-133140.43" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6868 + attribute \src "libresoc.v:142887.13-142887.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 32 $1\logical_op__insn$next[31:0]$6547 - attribute \src "libresoc.v:133157.14-133157.38" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 32 $1\logical_op__insn$next[31:0]$6869 + attribute \src "libresoc.v:142904.14-142904.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$6548 - attribute \src "libresoc.v:133240.13-133240.42" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6870 + attribute \src "libresoc.v:142988.13-142988.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__invert_in$next[0:0]$6549 - attribute \src "libresoc.v:133397.7-133397.35" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__invert_in$next[0:0]$6871 + attribute \src "libresoc.v:143147.7-143147.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__invert_out$next[0:0]$6550 - attribute \src "libresoc.v:133406.7-133406.36" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__invert_out$next[0:0]$6872 + attribute \src "libresoc.v:143156.7-143156.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__is_32bit$next[0:0]$6551 - attribute \src "libresoc.v:133415.7-133415.34" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__is_32bit$next[0:0]$6873 + attribute \src "libresoc.v:143165.7-143165.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__is_signed$next[0:0]$6552 - attribute \src "libresoc.v:133424.7-133424.35" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__is_signed$next[0:0]$6874 + attribute \src "libresoc.v:143174.7-143174.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__oe__oe$next[0:0]$6553 - attribute \src "libresoc.v:133433.7-133433.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__oe__oe$next[0:0]$6875 + attribute \src "libresoc.v:143183.7-143183.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__oe__ok$next[0:0]$6554 - attribute \src "libresoc.v:133442.7-133442.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__oe__ok$next[0:0]$6876 + attribute \src "libresoc.v:143192.7-143192.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__output_carry$next[0:0]$6555 - attribute \src "libresoc.v:133451.7-133451.38" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__output_carry$next[0:0]$6877 + attribute \src "libresoc.v:143201.7-143201.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__rc__ok$next[0:0]$6556 - attribute \src "libresoc.v:133460.7-133460.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__rc__ok$next[0:0]$6878 + attribute \src "libresoc.v:143210.7-143210.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__rc__rc$next[0:0]$6557 - attribute \src "libresoc.v:133469.7-133469.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__rc__rc$next[0:0]$6879 + attribute \src "libresoc.v:143219.7-143219.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__write_cr0$next[0:0]$6558 - attribute \src "libresoc.v:133478.7-133478.35" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__write_cr0$next[0:0]$6880 + attribute \src "libresoc.v:143228.7-143228.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:134011.3-134052.6" - wire $1\logical_op__zero_a$next[0:0]$6559 - attribute \src "libresoc.v:133487.7-133487.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__zero_a$next[0:0]$6881 + attribute \src "libresoc.v:143237.7-143237.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:133998.3-134010.6" - wire width 2 $1\muxid$next[1:0]$6522 - attribute \src "libresoc.v:133766.13-133766.25" + attribute \src "libresoc.v:143754.3-143766.6" + wire width 2 $1\muxid$next[1:0]$6844 + attribute \src "libresoc.v:143522.13-143522.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:134053.3-134071.6" - wire width 64 $1\o$next[63:0]$6569 - attribute \src "libresoc.v:133781.14-133781.38" + attribute \src "libresoc.v:143809.3-143827.6" + wire width 64 $1\o$next[63:0]$6891 + attribute \src "libresoc.v:143537.14-143537.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:134053.3-134071.6" - wire $1\o_ok$next[0:0]$6570 - attribute \src "libresoc.v:133788.7-133788.18" + attribute \src "libresoc.v:143809.3-143827.6" + wire $1\o_ok$next[0:0]$6892 + attribute \src "libresoc.v:143544.7-143544.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:133980.3-133997.6" - wire $1\r_busy$next[0:0]$6518 - attribute \src "libresoc.v:133802.7-133802.20" + attribute \src "libresoc.v:143736.3-143753.6" + wire $1\r_busy$next[0:0]$6840 + attribute \src "libresoc.v:143558.7-143558.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:134091.3-134109.6" - wire $1\xer_so$next[0:0]$6581 - attribute \src "libresoc.v:133811.7-133811.20" + attribute \src "libresoc.v:143847.3-143865.6" + wire $1\xer_so$next[0:0]$6903 + attribute \src "libresoc.v:143567.7-143567.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:134091.3-134109.6" - wire $1\xer_so_ok$next[0:0]$6582 - attribute \src "libresoc.v:133820.7-133820.23" + attribute \src "libresoc.v:143847.3-143865.6" + wire $1\xer_so_ok$next[0:0]$6904 + attribute \src "libresoc.v:143576.7-143576.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:134072.3-134090.6" - wire $2\cr_a_ok$next[0:0]$6577 - attribute \src "libresoc.v:134011.3-134052.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$6560 - attribute \src "libresoc.v:134011.3-134052.6" - wire $2\logical_op__imm_data__ok$next[0:0]$6561 - attribute \src "libresoc.v:134011.3-134052.6" - wire $2\logical_op__oe__oe$next[0:0]$6562 - attribute \src "libresoc.v:134011.3-134052.6" - wire $2\logical_op__oe__ok$next[0:0]$6563 - attribute \src "libresoc.v:134011.3-134052.6" - wire $2\logical_op__rc__ok$next[0:0]$6564 - attribute \src "libresoc.v:134011.3-134052.6" - wire $2\logical_op__rc__rc$next[0:0]$6565 - attribute \src "libresoc.v:134053.3-134071.6" - wire $2\o_ok$next[0:0]$6571 - attribute \src "libresoc.v:133980.3-133997.6" - wire $2\r_busy$next[0:0]$6519 - attribute \src "libresoc.v:134091.3-134109.6" - wire $2\xer_so_ok$next[0:0]$6583 - attribute \src "libresoc.v:133827.18-133827.118" - wire $and$libresoc.v:133827$6489_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + attribute \src "libresoc.v:143828.3-143846.6" + wire $2\cr_a_ok$next[0:0]$6899 + attribute \src "libresoc.v:143767.3-143808.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$6882 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__imm_data__ok$next[0:0]$6883 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__oe__oe$next[0:0]$6884 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__oe__ok$next[0:0]$6885 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__rc__ok$next[0:0]$6886 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__rc__rc$next[0:0]$6887 + attribute \src "libresoc.v:143809.3-143827.6" + wire $2\o_ok$next[0:0]$6893 + attribute \src "libresoc.v:143736.3-143753.6" + wire $2\r_busy$next[0:0]$6841 + attribute \src "libresoc.v:143847.3-143865.6" + wire $2\xer_so_ok$next[0:0]$6905 + attribute \src "libresoc.v:143583.18-143583.118" + wire $and$libresoc.v:143583$6811_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -217010,42 +232829,46 @@ module \logical_pipe1 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:132764.7-132764.15" + attribute \src "libresoc.v:142499.7-142499.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len$38 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit$23 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -217144,6 +232967,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -217220,6 +233044,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -217266,9 +233091,9 @@ module \logical_pipe1 wire \input_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__zero_a$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra @@ -217291,52 +233116,58 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 33 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 33 \logical_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -217455,6 +233286,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -217531,6 +233363,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 32 \logical_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -217607,6 +233440,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -217704,35 +233538,39 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \main_logical_op__data_len$60 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_logical_op__fn_unit$45 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_logical_op__fn_unit$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -217831,6 +233669,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -217907,6 +233746,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_logical_op__insn_type$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -217953,9 +233793,9 @@ module \logical_pipe1 wire \main_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__zero_a$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \main_o @@ -217969,19 +233809,19 @@ module \logical_pipe1 wire \main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_xer_so$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 23 \o @@ -217995,17 +233835,17 @@ module \logical_pipe1 wire \o_ok$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 30 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 29 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 50 \ra @@ -218027,8 +233867,8 @@ module \logical_pipe1 wire \xer_so_ok$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:133827$6489 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:143583$6811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218036,10 +233876,10 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:133827$6489_Y + connect \Y $and$libresoc.v:143583$6811_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:133880.14-133925.4" + attribute \src "libresoc.v:143636.14-143681.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 @@ -218087,7 +233927,7 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133926.13-133971.4" + attribute \src "libresoc.v:143682.13-143727.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 @@ -218135,481 +233975,481 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133972.10-133975.4" + attribute \src "libresoc.v:143728.10-143731.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:133976.10-133979.4" + attribute \src "libresoc.v:143732.10-143735.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:132764.7-132764.20" - process $proc$libresoc.v:132764$6584 + attribute \src "libresoc.v:142499.7-142499.20" + process $proc$libresoc.v:142499$6906 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132773.13-132773.24" - process $proc$libresoc.v:132773$6585 + attribute \src "libresoc.v:142508.13-142508.24" + process $proc$libresoc.v:142508$6907 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:132782.7-132782.21" - process $proc$libresoc.v:132782$6586 + attribute \src "libresoc.v:142517.7-142517.21" + process $proc$libresoc.v:142517$6908 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:133061.13-133061.40" - process $proc$libresoc.v:133061$6587 + attribute \src "libresoc.v:142802.13-142802.40" + process $proc$libresoc.v:142802$6909 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:133083.14-133083.43" - process $proc$libresoc.v:133083$6588 + attribute \src "libresoc.v:142826.14-142826.44" + process $proc$libresoc.v:142826$6910 assign { } { } - assign $1\logical_op__fn_unit[11:0] 12'000000000000 + assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] + update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:133118.14-133118.63" - process $proc$libresoc.v:133118$6589 + attribute \src "libresoc.v:142865.14-142865.63" + process $proc$libresoc.v:142865$6911 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:133127.7-133127.38" - process $proc$libresoc.v:133127$6590 + attribute \src "libresoc.v:142874.7-142874.38" + process $proc$libresoc.v:142874$6912 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:133140.13-133140.43" - process $proc$libresoc.v:133140$6591 + attribute \src "libresoc.v:142887.13-142887.43" + process $proc$libresoc.v:142887$6913 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:133157.14-133157.38" - process $proc$libresoc.v:133157$6592 + attribute \src "libresoc.v:142904.14-142904.38" + process $proc$libresoc.v:142904$6914 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:133240.13-133240.42" - process $proc$libresoc.v:133240$6593 + attribute \src "libresoc.v:142988.13-142988.42" + process $proc$libresoc.v:142988$6915 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:133397.7-133397.35" - process $proc$libresoc.v:133397$6594 + attribute \src "libresoc.v:143147.7-143147.35" + process $proc$libresoc.v:143147$6916 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:133406.7-133406.36" - process $proc$libresoc.v:133406$6595 + attribute \src "libresoc.v:143156.7-143156.36" + process $proc$libresoc.v:143156$6917 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:133415.7-133415.34" - process $proc$libresoc.v:133415$6596 + attribute \src "libresoc.v:143165.7-143165.34" + process $proc$libresoc.v:143165$6918 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:133424.7-133424.35" - process $proc$libresoc.v:133424$6597 + attribute \src "libresoc.v:143174.7-143174.35" + process $proc$libresoc.v:143174$6919 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:133433.7-133433.32" - process $proc$libresoc.v:133433$6598 + attribute \src "libresoc.v:143183.7-143183.32" + process $proc$libresoc.v:143183$6920 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:133442.7-133442.32" - process $proc$libresoc.v:133442$6599 + attribute \src "libresoc.v:143192.7-143192.32" + process $proc$libresoc.v:143192$6921 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:133451.7-133451.38" - process $proc$libresoc.v:133451$6600 + attribute \src "libresoc.v:143201.7-143201.38" + process $proc$libresoc.v:143201$6922 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:133460.7-133460.32" - process $proc$libresoc.v:133460$6601 + attribute \src "libresoc.v:143210.7-143210.32" + process $proc$libresoc.v:143210$6923 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:133469.7-133469.32" - process $proc$libresoc.v:133469$6602 + attribute \src "libresoc.v:143219.7-143219.32" + process $proc$libresoc.v:143219$6924 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:133478.7-133478.35" - process $proc$libresoc.v:133478$6603 + attribute \src "libresoc.v:143228.7-143228.35" + process $proc$libresoc.v:143228$6925 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:133487.7-133487.32" - process $proc$libresoc.v:133487$6604 + attribute \src "libresoc.v:143237.7-143237.32" + process $proc$libresoc.v:143237$6926 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:133766.13-133766.25" - process $proc$libresoc.v:133766$6605 + attribute \src "libresoc.v:143522.13-143522.25" + process $proc$libresoc.v:143522$6927 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:133781.14-133781.38" - process $proc$libresoc.v:133781$6606 + attribute \src "libresoc.v:143537.14-143537.38" + process $proc$libresoc.v:143537$6928 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:133788.7-133788.18" - process $proc$libresoc.v:133788$6607 + attribute \src "libresoc.v:143544.7-143544.18" + process $proc$libresoc.v:143544$6929 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:133802.7-133802.20" - process $proc$libresoc.v:133802$6608 + attribute \src "libresoc.v:143558.7-143558.20" + process $proc$libresoc.v:143558$6930 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:133811.7-133811.20" - process $proc$libresoc.v:133811$6609 + attribute \src "libresoc.v:143567.7-143567.20" + process $proc$libresoc.v:143567$6931 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:133820.7-133820.23" - process $proc$libresoc.v:133820$6610 + attribute \src "libresoc.v:143576.7-143576.23" + process $proc$libresoc.v:143576$6932 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:133828.3-133829.29" - process $proc$libresoc.v:133828$6490 + attribute \src "libresoc.v:143584.3-143585.29" + process $proc$libresoc.v:143584$6812 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:133830.3-133831.35" - process $proc$libresoc.v:133830$6491 + attribute \src "libresoc.v:143586.3-143587.35" + process $proc$libresoc.v:143586$6813 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:133832.3-133833.25" - process $proc$libresoc.v:133832$6492 + attribute \src "libresoc.v:143588.3-143589.25" + process $proc$libresoc.v:143588$6814 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:133834.3-133835.31" - process $proc$libresoc.v:133834$6493 + attribute \src "libresoc.v:143590.3-143591.31" + process $proc$libresoc.v:143590$6815 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:133836.3-133837.19" - process $proc$libresoc.v:133836$6494 + attribute \src "libresoc.v:143592.3-143593.19" + process $proc$libresoc.v:143592$6816 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:133838.3-133839.25" - process $proc$libresoc.v:133838$6495 + attribute \src "libresoc.v:143594.3-143595.25" + process $proc$libresoc.v:143594$6817 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:133840.3-133841.59" - process $proc$libresoc.v:133840$6496 + attribute \src "libresoc.v:143596.3-143597.59" + process $proc$libresoc.v:143596$6818 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:133842.3-133843.55" - process $proc$libresoc.v:133842$6497 + attribute \src "libresoc.v:143598.3-143599.55" + process $proc$libresoc.v:143598$6819 assign { } { } - assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next + assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] + update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:133844.3-133845.69" - process $proc$libresoc.v:133844$6498 + attribute \src "libresoc.v:143600.3-143601.69" + process $proc$libresoc.v:143600$6820 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:133846.3-133847.65" - process $proc$libresoc.v:133846$6499 + attribute \src "libresoc.v:143602.3-143603.65" + process $proc$libresoc.v:143602$6821 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:133848.3-133849.53" - process $proc$libresoc.v:133848$6500 + attribute \src "libresoc.v:143604.3-143605.53" + process $proc$libresoc.v:143604$6822 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:133850.3-133851.53" - process $proc$libresoc.v:133850$6501 + attribute \src "libresoc.v:143606.3-143607.53" + process $proc$libresoc.v:143606$6823 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:133852.3-133853.53" - process $proc$libresoc.v:133852$6502 + attribute \src "libresoc.v:143608.3-143609.53" + process $proc$libresoc.v:143608$6824 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:133854.3-133855.53" - process $proc$libresoc.v:133854$6503 + attribute \src "libresoc.v:143610.3-143611.53" + process $proc$libresoc.v:143610$6825 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:133856.3-133857.59" - process $proc$libresoc.v:133856$6504 + attribute \src "libresoc.v:143612.3-143613.59" + process $proc$libresoc.v:143612$6826 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:133858.3-133859.53" - process $proc$libresoc.v:133858$6505 + attribute \src "libresoc.v:143614.3-143615.53" + process $proc$libresoc.v:143614$6827 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:133860.3-133861.63" - process $proc$libresoc.v:133860$6506 + attribute \src "libresoc.v:143616.3-143617.63" + process $proc$libresoc.v:143616$6828 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:133862.3-133863.61" - process $proc$libresoc.v:133862$6507 + attribute \src "libresoc.v:143618.3-143619.61" + process $proc$libresoc.v:143618$6829 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:133864.3-133865.59" - process $proc$libresoc.v:133864$6508 + attribute \src "libresoc.v:143620.3-143621.59" + process $proc$libresoc.v:143620$6830 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:133866.3-133867.65" - process $proc$libresoc.v:133866$6509 + attribute \src "libresoc.v:143622.3-143623.65" + process $proc$libresoc.v:143622$6831 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:133868.3-133869.57" - process $proc$libresoc.v:133868$6510 + attribute \src "libresoc.v:143624.3-143625.57" + process $proc$libresoc.v:143624$6832 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:133870.3-133871.59" - process $proc$libresoc.v:133870$6511 + attribute \src "libresoc.v:143626.3-143627.59" + process $proc$libresoc.v:143626$6833 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:133872.3-133873.57" - process $proc$libresoc.v:133872$6512 + attribute \src "libresoc.v:143628.3-143629.57" + process $proc$libresoc.v:143628$6834 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:133874.3-133875.49" - process $proc$libresoc.v:133874$6513 + attribute \src "libresoc.v:143630.3-143631.49" + process $proc$libresoc.v:143630$6835 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:133876.3-133877.27" - process $proc$libresoc.v:133876$6514 + attribute \src "libresoc.v:143632.3-143633.27" + process $proc$libresoc.v:143632$6836 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:133878.3-133879.29" - process $proc$libresoc.v:133878$6515 + attribute \src "libresoc.v:143634.3-143635.29" + process $proc$libresoc.v:143634$6837 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:133980.3-133997.6" - process $proc$libresoc.v:133980$6516 + attribute \src "libresoc.v:143736.3-143753.6" + process $proc$libresoc.v:143736$6838 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6517 $2\r_busy$next[0:0]$6519 - attribute \src "libresoc.v:133981.5-133981.29" + assign $0\r_busy$next[0:0]$6839 $2\r_busy$next[0:0]$6841 + attribute \src "libresoc.v:143737.5-143737.29" switch \initial - attribute \src "libresoc.v:133981.9-133981.17" + attribute \src "libresoc.v:143737.9-143737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6518 1'1 + assign $1\r_busy$next[0:0]$6840 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6518 1'0 + assign $1\r_busy$next[0:0]$6840 1'0 case - assign $1\r_busy$next[0:0]$6518 \r_busy + assign $1\r_busy$next[0:0]$6840 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6519 1'0 + assign $2\r_busy$next[0:0]$6841 1'0 case - assign $2\r_busy$next[0:0]$6519 $1\r_busy$next[0:0]$6518 + assign $2\r_busy$next[0:0]$6841 $1\r_busy$next[0:0]$6840 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6517 + update \r_busy$next $0\r_busy$next[0:0]$6839 end - attribute \src "libresoc.v:133998.3-134010.6" - process $proc$libresoc.v:133998$6520 + attribute \src "libresoc.v:143754.3-143766.6" + process $proc$libresoc.v:143754$6842 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$6521 $1\muxid$next[1:0]$6522 - attribute \src "libresoc.v:133999.5-133999.29" + assign $0\muxid$next[1:0]$6843 $1\muxid$next[1:0]$6844 + attribute \src "libresoc.v:143755.5-143755.29" switch \initial - attribute \src "libresoc.v:133999.9-133999.17" + attribute \src "libresoc.v:143755.9-143755.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$6522 \muxid$66 + assign $1\muxid$next[1:0]$6844 \muxid$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$6522 \muxid$66 + assign $1\muxid$next[1:0]$6844 \muxid$66 case - assign $1\muxid$next[1:0]$6522 \muxid + assign $1\muxid$next[1:0]$6844 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$6521 + update \muxid$next $0\muxid$next[1:0]$6843 end - attribute \src "libresoc.v:134011.3-134052.6" - process $proc$libresoc.v:134011$6523 + attribute \src "libresoc.v:143767.3-143808.6" + process $proc$libresoc.v:143767$6845 assign { } { } assign { } { } assign { } { } @@ -218646,37 +234486,37 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$6524 $1\logical_op__data_len$next[3:0]$6542 - assign $0\logical_op__fn_unit$next[11:0]$6525 $1\logical_op__fn_unit$next[11:0]$6543 + assign $0\logical_op__data_len$next[3:0]$6846 $1\logical_op__data_len$next[3:0]$6864 + assign $0\logical_op__fn_unit$next[13:0]$6847 $1\logical_op__fn_unit$next[13:0]$6865 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6528 $1\logical_op__input_carry$next[1:0]$6546 - assign $0\logical_op__insn$next[31:0]$6529 $1\logical_op__insn$next[31:0]$6547 - assign $0\logical_op__insn_type$next[6:0]$6530 $1\logical_op__insn_type$next[6:0]$6548 - assign $0\logical_op__invert_in$next[0:0]$6531 $1\logical_op__invert_in$next[0:0]$6549 - assign $0\logical_op__invert_out$next[0:0]$6532 $1\logical_op__invert_out$next[0:0]$6550 - assign $0\logical_op__is_32bit$next[0:0]$6533 $1\logical_op__is_32bit$next[0:0]$6551 - assign $0\logical_op__is_signed$next[0:0]$6534 $1\logical_op__is_signed$next[0:0]$6552 + assign $0\logical_op__input_carry$next[1:0]$6850 $1\logical_op__input_carry$next[1:0]$6868 + assign $0\logical_op__insn$next[31:0]$6851 $1\logical_op__insn$next[31:0]$6869 + assign $0\logical_op__insn_type$next[6:0]$6852 $1\logical_op__insn_type$next[6:0]$6870 + assign $0\logical_op__invert_in$next[0:0]$6853 $1\logical_op__invert_in$next[0:0]$6871 + assign $0\logical_op__invert_out$next[0:0]$6854 $1\logical_op__invert_out$next[0:0]$6872 + assign $0\logical_op__is_32bit$next[0:0]$6855 $1\logical_op__is_32bit$next[0:0]$6873 + assign $0\logical_op__is_signed$next[0:0]$6856 $1\logical_op__is_signed$next[0:0]$6874 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6537 $1\logical_op__output_carry$next[0:0]$6555 + assign $0\logical_op__output_carry$next[0:0]$6859 $1\logical_op__output_carry$next[0:0]$6877 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6540 $1\logical_op__write_cr0$next[0:0]$6558 - assign $0\logical_op__zero_a$next[0:0]$6541 $1\logical_op__zero_a$next[0:0]$6559 - assign $0\logical_op__imm_data__data$next[63:0]$6526 $2\logical_op__imm_data__data$next[63:0]$6560 - assign $0\logical_op__imm_data__ok$next[0:0]$6527 $2\logical_op__imm_data__ok$next[0:0]$6561 - assign $0\logical_op__oe__oe$next[0:0]$6535 $2\logical_op__oe__oe$next[0:0]$6562 - assign $0\logical_op__oe__ok$next[0:0]$6536 $2\logical_op__oe__ok$next[0:0]$6563 - assign $0\logical_op__rc__ok$next[0:0]$6538 $2\logical_op__rc__ok$next[0:0]$6564 - assign $0\logical_op__rc__rc$next[0:0]$6539 $2\logical_op__rc__rc$next[0:0]$6565 - attribute \src "libresoc.v:134012.5-134012.29" + assign $0\logical_op__write_cr0$next[0:0]$6862 $1\logical_op__write_cr0$next[0:0]$6880 + assign $0\logical_op__zero_a$next[0:0]$6863 $1\logical_op__zero_a$next[0:0]$6881 + assign $0\logical_op__imm_data__data$next[63:0]$6848 $2\logical_op__imm_data__data$next[63:0]$6882 + assign $0\logical_op__imm_data__ok$next[0:0]$6849 $2\logical_op__imm_data__ok$next[0:0]$6883 + assign $0\logical_op__oe__oe$next[0:0]$6857 $2\logical_op__oe__oe$next[0:0]$6884 + assign $0\logical_op__oe__ok$next[0:0]$6858 $2\logical_op__oe__ok$next[0:0]$6885 + assign $0\logical_op__rc__ok$next[0:0]$6860 $2\logical_op__rc__ok$next[0:0]$6886 + assign $0\logical_op__rc__rc$next[0:0]$6861 $2\logical_op__rc__rc$next[0:0]$6887 + attribute \src "libresoc.v:143768.5-143768.29" switch \initial - attribute \src "libresoc.v:134012.9-134012.17" + attribute \src "libresoc.v:143768.9-143768.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -218698,7 +234538,7 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6547 $1\logical_op__data_len$next[3:0]$6542 $1\logical_op__is_signed$next[0:0]$6552 $1\logical_op__is_32bit$next[0:0]$6551 $1\logical_op__output_carry$next[0:0]$6555 $1\logical_op__write_cr0$next[0:0]$6558 $1\logical_op__invert_out$next[0:0]$6550 $1\logical_op__input_carry$next[1:0]$6546 $1\logical_op__zero_a$next[0:0]$6559 $1\logical_op__invert_in$next[0:0]$6549 $1\logical_op__oe__ok$next[0:0]$6554 $1\logical_op__oe__oe$next[0:0]$6553 $1\logical_op__rc__ok$next[0:0]$6556 $1\logical_op__rc__rc$next[0:0]$6557 $1\logical_op__imm_data__ok$next[0:0]$6545 $1\logical_op__imm_data__data$next[63:0]$6544 $1\logical_op__fn_unit$next[11:0]$6543 $1\logical_op__insn_type$next[6:0]$6548 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6869 $1\logical_op__data_len$next[3:0]$6864 $1\logical_op__is_signed$next[0:0]$6874 $1\logical_op__is_32bit$next[0:0]$6873 $1\logical_op__output_carry$next[0:0]$6877 $1\logical_op__write_cr0$next[0:0]$6880 $1\logical_op__invert_out$next[0:0]$6872 $1\logical_op__input_carry$next[1:0]$6868 $1\logical_op__zero_a$next[0:0]$6881 $1\logical_op__invert_in$next[0:0]$6871 $1\logical_op__oe__ok$next[0:0]$6876 $1\logical_op__oe__oe$next[0:0]$6875 $1\logical_op__rc__ok$next[0:0]$6878 $1\logical_op__rc__rc$next[0:0]$6879 $1\logical_op__imm_data__ok$next[0:0]$6867 $1\logical_op__imm_data__data$next[63:0]$6866 $1\logical_op__fn_unit$next[13:0]$6865 $1\logical_op__insn_type$next[6:0]$6870 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -218719,26 +234559,26 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6547 $1\logical_op__data_len$next[3:0]$6542 $1\logical_op__is_signed$next[0:0]$6552 $1\logical_op__is_32bit$next[0:0]$6551 $1\logical_op__output_carry$next[0:0]$6555 $1\logical_op__write_cr0$next[0:0]$6558 $1\logical_op__invert_out$next[0:0]$6550 $1\logical_op__input_carry$next[1:0]$6546 $1\logical_op__zero_a$next[0:0]$6559 $1\logical_op__invert_in$next[0:0]$6549 $1\logical_op__oe__ok$next[0:0]$6554 $1\logical_op__oe__oe$next[0:0]$6553 $1\logical_op__rc__ok$next[0:0]$6556 $1\logical_op__rc__rc$next[0:0]$6557 $1\logical_op__imm_data__ok$next[0:0]$6545 $1\logical_op__imm_data__data$next[63:0]$6544 $1\logical_op__fn_unit$next[11:0]$6543 $1\logical_op__insn_type$next[6:0]$6548 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6869 $1\logical_op__data_len$next[3:0]$6864 $1\logical_op__is_signed$next[0:0]$6874 $1\logical_op__is_32bit$next[0:0]$6873 $1\logical_op__output_carry$next[0:0]$6877 $1\logical_op__write_cr0$next[0:0]$6880 $1\logical_op__invert_out$next[0:0]$6872 $1\logical_op__input_carry$next[1:0]$6868 $1\logical_op__zero_a$next[0:0]$6881 $1\logical_op__invert_in$next[0:0]$6871 $1\logical_op__oe__ok$next[0:0]$6876 $1\logical_op__oe__oe$next[0:0]$6875 $1\logical_op__rc__ok$next[0:0]$6878 $1\logical_op__rc__rc$next[0:0]$6879 $1\logical_op__imm_data__ok$next[0:0]$6867 $1\logical_op__imm_data__data$next[63:0]$6866 $1\logical_op__fn_unit$next[13:0]$6865 $1\logical_op__insn_type$next[6:0]$6870 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } case - assign $1\logical_op__data_len$next[3:0]$6542 \logical_op__data_len - assign $1\logical_op__fn_unit$next[11:0]$6543 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6544 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6545 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6546 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6547 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6548 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6549 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6550 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6551 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6552 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6553 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6554 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6555 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6556 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6557 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6558 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6559 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$6864 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$6865 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6866 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6867 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6868 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6869 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6870 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6871 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6872 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6873 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6874 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6875 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6876 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6877 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6878 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6879 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6880 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6881 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -218750,173 +234590,173 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6560 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6561 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6565 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6564 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6562 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6563 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$6882 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6883 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6887 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6886 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6884 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6885 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$6560 $1\logical_op__imm_data__data$next[63:0]$6544 - assign $2\logical_op__imm_data__ok$next[0:0]$6561 $1\logical_op__imm_data__ok$next[0:0]$6545 - assign $2\logical_op__oe__oe$next[0:0]$6562 $1\logical_op__oe__oe$next[0:0]$6553 - assign $2\logical_op__oe__ok$next[0:0]$6563 $1\logical_op__oe__ok$next[0:0]$6554 - assign $2\logical_op__rc__ok$next[0:0]$6564 $1\logical_op__rc__ok$next[0:0]$6556 - assign $2\logical_op__rc__rc$next[0:0]$6565 $1\logical_op__rc__rc$next[0:0]$6557 + assign $2\logical_op__imm_data__data$next[63:0]$6882 $1\logical_op__imm_data__data$next[63:0]$6866 + assign $2\logical_op__imm_data__ok$next[0:0]$6883 $1\logical_op__imm_data__ok$next[0:0]$6867 + assign $2\logical_op__oe__oe$next[0:0]$6884 $1\logical_op__oe__oe$next[0:0]$6875 + assign $2\logical_op__oe__ok$next[0:0]$6885 $1\logical_op__oe__ok$next[0:0]$6876 + assign $2\logical_op__rc__ok$next[0:0]$6886 $1\logical_op__rc__ok$next[0:0]$6878 + assign $2\logical_op__rc__rc$next[0:0]$6887 $1\logical_op__rc__rc$next[0:0]$6879 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6524 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$6525 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6526 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6527 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6528 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6529 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6530 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6531 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6532 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6533 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6534 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6535 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6536 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6537 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6538 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6539 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6540 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6541 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6846 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6847 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6848 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6849 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6850 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6851 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6852 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6853 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6854 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6855 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6856 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6857 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6858 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6859 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6860 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6861 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6862 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6863 end - attribute \src "libresoc.v:134053.3-134071.6" - process $proc$libresoc.v:134053$6566 + attribute \src "libresoc.v:143809.3-143827.6" + process $proc$libresoc.v:143809$6888 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$6567 $1\o$next[63:0]$6569 + assign $0\o$next[63:0]$6889 $1\o$next[63:0]$6891 assign { } { } - assign $0\o_ok$next[0:0]$6568 $2\o_ok$next[0:0]$6571 - attribute \src "libresoc.v:134054.5-134054.29" + assign $0\o_ok$next[0:0]$6890 $2\o_ok$next[0:0]$6893 + attribute \src "libresoc.v:143810.5-143810.29" switch \initial - attribute \src "libresoc.v:134054.9-134054.17" + attribute \src "libresoc.v:143810.9-143810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6570 $1\o$next[63:0]$6569 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6892 $1\o$next[63:0]$6891 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6570 $1\o$next[63:0]$6569 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6892 $1\o$next[63:0]$6891 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$6569 \o - assign $1\o_ok$next[0:0]$6570 \o_ok + assign $1\o$next[63:0]$6891 \o + assign $1\o_ok$next[0:0]$6892 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$6571 1'0 + assign $2\o_ok$next[0:0]$6893 1'0 case - assign $2\o_ok$next[0:0]$6571 $1\o_ok$next[0:0]$6570 + assign $2\o_ok$next[0:0]$6893 $1\o_ok$next[0:0]$6892 end sync always - update \o$next $0\o$next[63:0]$6567 - update \o_ok$next $0\o_ok$next[0:0]$6568 + update \o$next $0\o$next[63:0]$6889 + update \o_ok$next $0\o_ok$next[0:0]$6890 end - attribute \src "libresoc.v:134072.3-134090.6" - process $proc$libresoc.v:134072$6572 + attribute \src "libresoc.v:143828.3-143846.6" + process $proc$libresoc.v:143828$6894 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$6573 $1\cr_a$next[3:0]$6575 + assign $0\cr_a$next[3:0]$6895 $1\cr_a$next[3:0]$6897 assign { } { } - assign $0\cr_a_ok$next[0:0]$6574 $2\cr_a_ok$next[0:0]$6577 - attribute \src "libresoc.v:134073.5-134073.29" + assign $0\cr_a_ok$next[0:0]$6896 $2\cr_a_ok$next[0:0]$6899 + attribute \src "libresoc.v:143829.5-143829.29" switch \initial - attribute \src "libresoc.v:134073.9-134073.17" + attribute \src "libresoc.v:143829.9-143829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6576 $1\cr_a$next[3:0]$6575 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6898 $1\cr_a$next[3:0]$6897 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6576 $1\cr_a$next[3:0]$6575 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6898 $1\cr_a$next[3:0]$6897 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$6575 \cr_a - assign $1\cr_a_ok$next[0:0]$6576 \cr_a_ok + assign $1\cr_a$next[3:0]$6897 \cr_a + assign $1\cr_a_ok$next[0:0]$6898 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$6577 1'0 + assign $2\cr_a_ok$next[0:0]$6899 1'0 case - assign $2\cr_a_ok$next[0:0]$6577 $1\cr_a_ok$next[0:0]$6576 + assign $2\cr_a_ok$next[0:0]$6899 $1\cr_a_ok$next[0:0]$6898 end sync always - update \cr_a$next $0\cr_a$next[3:0]$6573 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6574 + update \cr_a$next $0\cr_a$next[3:0]$6895 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6896 end - attribute \src "libresoc.v:134091.3-134109.6" - process $proc$libresoc.v:134091$6578 + attribute \src "libresoc.v:143847.3-143865.6" + process $proc$libresoc.v:143847$6900 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$6579 $1\xer_so$next[0:0]$6581 + assign $0\xer_so$next[0:0]$6901 $1\xer_so$next[0:0]$6903 assign { } { } - assign $0\xer_so_ok$next[0:0]$6580 $2\xer_so_ok$next[0:0]$6583 - attribute \src "libresoc.v:134092.5-134092.29" + assign $0\xer_so_ok$next[0:0]$6902 $2\xer_so_ok$next[0:0]$6905 + attribute \src "libresoc.v:143848.5-143848.29" switch \initial - attribute \src "libresoc.v:134092.9-134092.17" + attribute \src "libresoc.v:143848.9-143848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6582 $1\xer_so$next[0:0]$6581 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6904 $1\xer_so$next[0:0]$6903 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6582 $1\xer_so$next[0:0]$6581 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6904 $1\xer_so$next[0:0]$6903 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$6581 \xer_so - assign $1\xer_so_ok$next[0:0]$6582 \xer_so_ok + assign $1\xer_so$next[0:0]$6903 \xer_so + assign $1\xer_so_ok$next[0:0]$6904 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$6583 1'0 + assign $2\xer_so_ok$next[0:0]$6905 1'0 case - assign $2\xer_so_ok$next[0:0]$6583 $1\xer_so_ok$next[0:0]$6582 + assign $2\xer_so_ok$next[0:0]$6905 $1\xer_so_ok$next[0:0]$6904 end sync always - update \xer_so$next $0\xer_so$next[0:0]$6579 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6580 + update \xer_so$next $0\xer_so$next[0:0]$6901 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6902 end - connect \$64 $and$libresoc.v:133827$6489_Y + connect \$64 $and$libresoc.v:143583$6811_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -218941,230 +234781,230 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:134137.1-135155.10" +attribute \src "libresoc.v:143893.1-144926.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:135122.3-135140.6" - wire width 4 $0\cr_a$22$next[3:0]$6716 - attribute \src "libresoc.v:134926.3-134927.33" - wire width 4 $0\cr_a$22[3:0]$6613 - attribute \src "libresoc.v:134149.13-134149.29" - wire width 4 $0\cr_a$22[3:0]$6723 - attribute \src "libresoc.v:135122.3-135140.6" - wire $0\cr_a_ok$23$next[0:0]$6717 - attribute \src "libresoc.v:134928.3-134929.39" - wire $0\cr_a_ok$23[0:0]$6615 - attribute \src "libresoc.v:134158.7-134158.26" - wire $0\cr_a_ok$23[0:0]$6725 - attribute \src "libresoc.v:134138.7-134138.20" + attribute \src "libresoc.v:144893.3-144911.6" + wire width 4 $0\cr_a$22$next[3:0]$7038 + attribute \src "libresoc.v:144697.3-144698.33" + wire width 4 $0\cr_a$22[3:0]$6935 + attribute \src "libresoc.v:143905.13-143905.29" + wire width 4 $0\cr_a$22[3:0]$7045 + attribute \src "libresoc.v:144893.3-144911.6" + wire $0\cr_a_ok$23$next[0:0]$7039 + attribute \src "libresoc.v:144699.3-144700.39" + wire $0\cr_a_ok$23[0:0]$6937 + attribute \src "libresoc.v:143914.7-143914.26" + wire $0\cr_a_ok$23[0:0]$7047 + attribute \src "libresoc.v:143894.7-143894.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135061.3-135102.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$6667 - attribute \src "libresoc.v:134966.3-134967.65" - wire width 4 $0\logical_op__data_len$18[3:0]$6653 - attribute \src "libresoc.v:134169.13-134169.45" - wire width 4 $0\logical_op__data_len$18[3:0]$6727 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 12 $0\logical_op__fn_unit$3$next[11:0]$6668 - attribute \src "libresoc.v:134936.3-134937.61" - wire width 12 $0\logical_op__fn_unit$3[11:0]$6623 - attribute \src "libresoc.v:134204.14-134204.47" - wire width 12 $0\logical_op__fn_unit$3[11:0]$6729 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6669 - attribute \src "libresoc.v:134938.3-134939.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6625 - attribute \src "libresoc.v:134226.14-134226.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6731 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$6670 - attribute \src "libresoc.v:134940.3-134941.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6627 - attribute \src "libresoc.v:134235.7-134235.42" - wire $0\logical_op__imm_data__ok$5[0:0]$6733 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$6671 - attribute \src "libresoc.v:134954.3-134955.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$6641 - attribute \src "libresoc.v:134252.13-134252.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$6735 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$6672 - attribute \src "libresoc.v:134968.3-134969.57" - wire width 32 $0\logical_op__insn$19[31:0]$6655 - attribute \src "libresoc.v:134265.14-134265.43" - wire width 32 $0\logical_op__insn$19[31:0]$6737 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$6673 - attribute \src "libresoc.v:134934.3-134935.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6621 - attribute \src "libresoc.v:134422.13-134422.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$6739 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__invert_in$10$next[0:0]$6674 - attribute \src "libresoc.v:134950.3-134951.67" - wire $0\logical_op__invert_in$10[0:0]$6637 - attribute \src "libresoc.v:134505.7-134505.40" - wire $0\logical_op__invert_in$10[0:0]$6741 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__invert_out$13$next[0:0]$6675 - attribute \src "libresoc.v:134956.3-134957.69" - wire $0\logical_op__invert_out$13[0:0]$6643 - attribute \src "libresoc.v:134514.7-134514.41" - wire $0\logical_op__invert_out$13[0:0]$6743 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__is_32bit$16$next[0:0]$6676 - attribute \src "libresoc.v:134962.3-134963.65" - wire $0\logical_op__is_32bit$16[0:0]$6649 - attribute \src "libresoc.v:134523.7-134523.39" - wire $0\logical_op__is_32bit$16[0:0]$6745 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__is_signed$17$next[0:0]$6677 - attribute \src "libresoc.v:134964.3-134965.67" - wire $0\logical_op__is_signed$17[0:0]$6651 - attribute \src "libresoc.v:134532.7-134532.40" - wire $0\logical_op__is_signed$17[0:0]$6747 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__oe__oe$8$next[0:0]$6678 - attribute \src "libresoc.v:134946.3-134947.59" - wire $0\logical_op__oe__oe$8[0:0]$6633 - attribute \src "libresoc.v:134543.7-134543.36" - wire $0\logical_op__oe__oe$8[0:0]$6749 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__oe__ok$9$next[0:0]$6679 - attribute \src "libresoc.v:134948.3-134949.59" - wire $0\logical_op__oe__ok$9[0:0]$6635 - attribute \src "libresoc.v:134552.7-134552.36" - wire $0\logical_op__oe__ok$9[0:0]$6751 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__output_carry$15$next[0:0]$6680 - attribute \src "libresoc.v:134960.3-134961.73" - wire $0\logical_op__output_carry$15[0:0]$6647 - attribute \src "libresoc.v:134559.7-134559.43" - wire $0\logical_op__output_carry$15[0:0]$6753 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__rc__ok$7$next[0:0]$6681 - attribute \src "libresoc.v:134944.3-134945.59" - wire $0\logical_op__rc__ok$7[0:0]$6631 - attribute \src "libresoc.v:134570.7-134570.36" - wire $0\logical_op__rc__ok$7[0:0]$6755 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__rc__rc$6$next[0:0]$6682 - attribute \src "libresoc.v:134942.3-134943.59" - wire $0\logical_op__rc__rc$6[0:0]$6629 - attribute \src "libresoc.v:134579.7-134579.36" - wire $0\logical_op__rc__rc$6[0:0]$6757 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__write_cr0$14$next[0:0]$6683 - attribute \src "libresoc.v:134958.3-134959.67" - wire $0\logical_op__write_cr0$14[0:0]$6645 - attribute \src "libresoc.v:134586.7-134586.40" - wire $0\logical_op__write_cr0$14[0:0]$6759 - attribute \src "libresoc.v:135061.3-135102.6" - wire $0\logical_op__zero_a$11$next[0:0]$6684 - attribute \src "libresoc.v:134952.3-134953.61" - wire $0\logical_op__zero_a$11[0:0]$6639 - attribute \src "libresoc.v:134595.7-134595.37" - wire $0\logical_op__zero_a$11[0:0]$6761 - attribute \src "libresoc.v:135048.3-135060.6" - wire width 2 $0\muxid$1$next[1:0]$6664 - attribute \src "libresoc.v:134970.3-134971.33" - wire width 2 $0\muxid$1[1:0]$6657 - attribute \src "libresoc.v:134604.13-134604.29" - wire width 2 $0\muxid$1[1:0]$6763 - attribute \src "libresoc.v:135103.3-135121.6" - wire width 64 $0\o$20$next[63:0]$6710 - attribute \src "libresoc.v:134930.3-134931.27" - wire width 64 $0\o$20[63:0]$6617 - attribute \src "libresoc.v:134619.14-134619.43" - wire width 64 $0\o$20[63:0]$6765 - attribute \src "libresoc.v:135103.3-135121.6" - wire $0\o_ok$21$next[0:0]$6711 - attribute \src "libresoc.v:134932.3-134933.33" - wire $0\o_ok$21[0:0]$6619 - attribute \src "libresoc.v:134628.7-134628.23" - wire $0\o_ok$21[0:0]$6767 - attribute \src "libresoc.v:135030.3-135047.6" - wire $0\r_busy$next[0:0]$6660 - attribute \src "libresoc.v:134972.3-134973.29" + attribute \src "libresoc.v:144832.3-144873.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$6989 + attribute \src "libresoc.v:144737.3-144738.65" + wire width 4 $0\logical_op__data_len$18[3:0]$6975 + attribute \src "libresoc.v:143925.13-143925.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7049 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$6990 + attribute \src "libresoc.v:144707.3-144708.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$6945 + attribute \src "libresoc.v:143964.14-143964.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$7051 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6991 + attribute \src "libresoc.v:144709.3-144710.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6947 + attribute \src "libresoc.v:143988.14-143988.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7053 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$6992 + attribute \src "libresoc.v:144711.3-144712.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6949 + attribute \src "libresoc.v:143997.7-143997.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7055 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$6993 + attribute \src "libresoc.v:144725.3-144726.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6963 + attribute \src "libresoc.v:144014.13-144014.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7057 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$6994 + attribute \src "libresoc.v:144739.3-144740.57" + wire width 32 $0\logical_op__insn$19[31:0]$6977 + attribute \src "libresoc.v:144027.14-144027.43" + wire width 32 $0\logical_op__insn$19[31:0]$7059 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$6995 + attribute \src "libresoc.v:144705.3-144706.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6943 + attribute \src "libresoc.v:144186.13-144186.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7061 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__invert_in$10$next[0:0]$6996 + attribute \src "libresoc.v:144721.3-144722.67" + wire $0\logical_op__invert_in$10[0:0]$6959 + attribute \src "libresoc.v:144270.7-144270.40" + wire $0\logical_op__invert_in$10[0:0]$7063 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__invert_out$13$next[0:0]$6997 + attribute \src "libresoc.v:144727.3-144728.69" + wire $0\logical_op__invert_out$13[0:0]$6965 + attribute \src "libresoc.v:144279.7-144279.41" + wire $0\logical_op__invert_out$13[0:0]$7065 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__is_32bit$16$next[0:0]$6998 + attribute \src "libresoc.v:144733.3-144734.65" + wire $0\logical_op__is_32bit$16[0:0]$6971 + attribute \src "libresoc.v:144288.7-144288.39" + wire $0\logical_op__is_32bit$16[0:0]$7067 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__is_signed$17$next[0:0]$6999 + attribute \src "libresoc.v:144735.3-144736.67" + wire $0\logical_op__is_signed$17[0:0]$6973 + attribute \src "libresoc.v:144297.7-144297.40" + wire $0\logical_op__is_signed$17[0:0]$7069 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__oe__oe$8$next[0:0]$7000 + attribute \src "libresoc.v:144717.3-144718.59" + wire $0\logical_op__oe__oe$8[0:0]$6955 + attribute \src "libresoc.v:144308.7-144308.36" + wire $0\logical_op__oe__oe$8[0:0]$7071 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__oe__ok$9$next[0:0]$7001 + attribute \src "libresoc.v:144719.3-144720.59" + wire $0\logical_op__oe__ok$9[0:0]$6957 + attribute \src "libresoc.v:144317.7-144317.36" + wire $0\logical_op__oe__ok$9[0:0]$7073 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__output_carry$15$next[0:0]$7002 + attribute \src "libresoc.v:144731.3-144732.73" + wire $0\logical_op__output_carry$15[0:0]$6969 + attribute \src "libresoc.v:144324.7-144324.43" + wire $0\logical_op__output_carry$15[0:0]$7075 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__rc__ok$7$next[0:0]$7003 + attribute \src "libresoc.v:144715.3-144716.59" + wire $0\logical_op__rc__ok$7[0:0]$6953 + attribute \src "libresoc.v:144335.7-144335.36" + wire $0\logical_op__rc__ok$7[0:0]$7077 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__rc__rc$6$next[0:0]$7004 + attribute \src "libresoc.v:144713.3-144714.59" + wire $0\logical_op__rc__rc$6[0:0]$6951 + attribute \src "libresoc.v:144344.7-144344.36" + wire $0\logical_op__rc__rc$6[0:0]$7079 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__write_cr0$14$next[0:0]$7005 + attribute \src "libresoc.v:144729.3-144730.67" + wire $0\logical_op__write_cr0$14[0:0]$6967 + attribute \src "libresoc.v:144351.7-144351.40" + wire $0\logical_op__write_cr0$14[0:0]$7081 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__zero_a$11$next[0:0]$7006 + attribute \src "libresoc.v:144723.3-144724.61" + wire $0\logical_op__zero_a$11[0:0]$6961 + attribute \src "libresoc.v:144360.7-144360.37" + wire $0\logical_op__zero_a$11[0:0]$7083 + attribute \src "libresoc.v:144819.3-144831.6" + wire width 2 $0\muxid$1$next[1:0]$6986 + attribute \src "libresoc.v:144741.3-144742.33" + wire width 2 $0\muxid$1[1:0]$6979 + attribute \src "libresoc.v:144369.13-144369.29" + wire width 2 $0\muxid$1[1:0]$7085 + attribute \src "libresoc.v:144874.3-144892.6" + wire width 64 $0\o$20$next[63:0]$7032 + attribute \src "libresoc.v:144701.3-144702.27" + wire width 64 $0\o$20[63:0]$6939 + attribute \src "libresoc.v:144384.14-144384.43" + wire width 64 $0\o$20[63:0]$7087 + attribute \src "libresoc.v:144874.3-144892.6" + wire $0\o_ok$21$next[0:0]$7033 + attribute \src "libresoc.v:144703.3-144704.33" + wire $0\o_ok$21[0:0]$6941 + attribute \src "libresoc.v:144393.7-144393.23" + wire $0\o_ok$21[0:0]$7089 + attribute \src "libresoc.v:144801.3-144818.6" + wire $0\r_busy$next[0:0]$6982 + attribute \src "libresoc.v:144743.3-144744.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:135122.3-135140.6" - wire width 4 $1\cr_a$22$next[3:0]$6718 - attribute \src "libresoc.v:135122.3-135140.6" - wire $1\cr_a_ok$23$next[0:0]$6719 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$6685 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 12 $1\logical_op__fn_unit$3$next[11:0]$6686 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6687 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$6688 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$6689 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$6690 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$6691 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__invert_in$10$next[0:0]$6692 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__invert_out$13$next[0:0]$6693 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__is_32bit$16$next[0:0]$6694 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__is_signed$17$next[0:0]$6695 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__oe__oe$8$next[0:0]$6696 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__oe__ok$9$next[0:0]$6697 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__output_carry$15$next[0:0]$6698 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__rc__ok$7$next[0:0]$6699 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__rc__rc$6$next[0:0]$6700 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__write_cr0$14$next[0:0]$6701 - attribute \src "libresoc.v:135061.3-135102.6" - wire $1\logical_op__zero_a$11$next[0:0]$6702 - attribute \src "libresoc.v:135048.3-135060.6" - wire width 2 $1\muxid$1$next[1:0]$6665 - attribute \src "libresoc.v:135103.3-135121.6" - wire width 64 $1\o$20$next[63:0]$6712 - attribute \src "libresoc.v:135103.3-135121.6" - wire $1\o_ok$21$next[0:0]$6713 - attribute \src "libresoc.v:135030.3-135047.6" - wire $1\r_busy$next[0:0]$6661 - attribute \src "libresoc.v:134916.7-134916.20" + attribute \src "libresoc.v:144893.3-144911.6" + wire width 4 $1\cr_a$22$next[3:0]$7040 + attribute \src "libresoc.v:144893.3-144911.6" + wire $1\cr_a_ok$23$next[0:0]$7041 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$7007 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7008 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7009 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$7010 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$7011 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$7012 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$7013 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__invert_in$10$next[0:0]$7014 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__invert_out$13$next[0:0]$7015 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__is_32bit$16$next[0:0]$7016 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__is_signed$17$next[0:0]$7017 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__oe__oe$8$next[0:0]$7018 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__oe__ok$9$next[0:0]$7019 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__output_carry$15$next[0:0]$7020 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7021 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7022 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7023 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__zero_a$11$next[0:0]$7024 + attribute \src "libresoc.v:144819.3-144831.6" + wire width 2 $1\muxid$1$next[1:0]$6987 + attribute \src "libresoc.v:144874.3-144892.6" + wire width 64 $1\o$20$next[63:0]$7034 + attribute \src "libresoc.v:144874.3-144892.6" + wire $1\o_ok$21$next[0:0]$7035 + attribute \src "libresoc.v:144801.3-144818.6" + wire $1\r_busy$next[0:0]$6983 + attribute \src "libresoc.v:144687.7-144687.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:135122.3-135140.6" - wire $2\cr_a_ok$23$next[0:0]$6720 - attribute \src "libresoc.v:135061.3-135102.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6703 - attribute \src "libresoc.v:135061.3-135102.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$6704 - attribute \src "libresoc.v:135061.3-135102.6" - wire $2\logical_op__oe__oe$8$next[0:0]$6705 - attribute \src "libresoc.v:135061.3-135102.6" - wire $2\logical_op__oe__ok$9$next[0:0]$6706 - attribute \src "libresoc.v:135061.3-135102.6" - wire $2\logical_op__rc__ok$7$next[0:0]$6707 - attribute \src "libresoc.v:135061.3-135102.6" - wire $2\logical_op__rc__rc$6$next[0:0]$6708 - attribute \src "libresoc.v:135103.3-135121.6" - wire $2\o_ok$21$next[0:0]$6714 - attribute \src "libresoc.v:135030.3-135047.6" - wire $2\r_busy$next[0:0]$6662 - attribute \src "libresoc.v:134925.18-134925.118" - wire $and$libresoc.v:134925$6611_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + attribute \src "libresoc.v:144893.3-144911.6" + wire $2\cr_a_ok$23$next[0:0]$7042 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7025 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7026 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7027 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7028 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7029 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7030 + attribute \src "libresoc.v:144874.3-144892.6" + wire $2\o_ok$21$next[0:0]$7036 + attribute \src "libresoc.v:144801.3-144818.6" + wire $2\r_busy$next[0:0]$6984 + attribute \src "libresoc.v:144696.18-144696.118" + wire $and$libresoc.v:144696$6933_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -219184,7 +235024,7 @@ module \logical_pipe2 wire \cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$73 - attribute \src "libresoc.v:134138.7-134138.15" + attribute \src "libresoc.v:143894.7-143894.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -219195,52 +235035,58 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$68 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 33 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 33 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$53 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -219359,6 +235205,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -219435,6 +235282,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 32 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -219513,6 +235361,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -219603,19 +235452,19 @@ module \logical_pipe2 wire \logical_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 30 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 29 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 23 \o @@ -219644,35 +235493,39 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len$41 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit$26 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -219771,6 +235624,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -219847,6 +235701,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -219893,9 +235748,9 @@ module \logical_pipe2 wire \output_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_o @@ -219907,17 +235762,17 @@ module \logical_pipe2 wire \output_o_ok$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 27 \xer_so @@ -219925,8 +235780,8 @@ module \logical_pipe2 wire input 28 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:134925$6611 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:144696$6933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219934,16 +235789,16 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:134925$6611_Y + connect \Y $and$libresoc.v:144696$6933_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:134974.10-134977.4" + attribute \src "libresoc.v:144745.10-144748.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:134978.15-135025.4" + attribute \src "libresoc.v:144749.15-144796.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 @@ -219993,445 +235848,445 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:135026.10-135029.4" + attribute \src "libresoc.v:144797.10-144800.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:134138.7-134138.20" - process $proc$libresoc.v:134138$6721 + attribute \src "libresoc.v:143894.7-143894.20" + process $proc$libresoc.v:143894$7043 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134149.13-134149.29" - process $proc$libresoc.v:134149$6722 + attribute \src "libresoc.v:143905.13-143905.29" + process $proc$libresoc.v:143905$7044 assign { } { } - assign $0\cr_a$22[3:0]$6723 4'0000 + assign $0\cr_a$22[3:0]$7045 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$6723 + update \cr_a$22 $0\cr_a$22[3:0]$7045 end - attribute \src "libresoc.v:134158.7-134158.26" - process $proc$libresoc.v:134158$6724 + attribute \src "libresoc.v:143914.7-143914.26" + process $proc$libresoc.v:143914$7046 assign { } { } - assign $0\cr_a_ok$23[0:0]$6725 1'0 + assign $0\cr_a_ok$23[0:0]$7047 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6725 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7047 end - attribute \src "libresoc.v:134169.13-134169.45" - process $proc$libresoc.v:134169$6726 + attribute \src "libresoc.v:143925.13-143925.45" + process $proc$libresoc.v:143925$7048 assign { } { } - assign $0\logical_op__data_len$18[3:0]$6727 4'0000 + assign $0\logical_op__data_len$18[3:0]$7049 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6727 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7049 end - attribute \src "libresoc.v:134204.14-134204.47" - process $proc$libresoc.v:134204$6728 + attribute \src "libresoc.v:143964.14-143964.48" + process $proc$libresoc.v:143964$7050 assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$6729 12'000000000000 + assign $0\logical_op__fn_unit$3[13:0]$7051 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6729 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7051 end - attribute \src "libresoc.v:134226.14-134226.67" - process $proc$libresoc.v:134226$6730 + attribute \src "libresoc.v:143988.14-143988.67" + process $proc$libresoc.v:143988$7052 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6731 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$7053 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6731 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7053 end - attribute \src "libresoc.v:134235.7-134235.42" - process $proc$libresoc.v:134235$6732 + attribute \src "libresoc.v:143997.7-143997.42" + process $proc$libresoc.v:143997$7054 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6733 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$7055 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6733 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7055 end - attribute \src "libresoc.v:134252.13-134252.48" - process $proc$libresoc.v:134252$6734 + attribute \src "libresoc.v:144014.13-144014.48" + process $proc$libresoc.v:144014$7056 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6735 2'00 + assign $0\logical_op__input_carry$12[1:0]$7057 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6735 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7057 end - attribute \src "libresoc.v:134265.14-134265.43" - process $proc$libresoc.v:134265$6736 + attribute \src "libresoc.v:144027.14-144027.43" + process $proc$libresoc.v:144027$7058 assign { } { } - assign $0\logical_op__insn$19[31:0]$6737 0 + assign $0\logical_op__insn$19[31:0]$7059 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6737 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7059 end - attribute \src "libresoc.v:134422.13-134422.46" - process $proc$libresoc.v:134422$6738 + attribute \src "libresoc.v:144186.13-144186.46" + process $proc$libresoc.v:144186$7060 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6739 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$7061 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6739 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7061 end - attribute \src "libresoc.v:134505.7-134505.40" - process $proc$libresoc.v:134505$6740 + attribute \src "libresoc.v:144270.7-144270.40" + process $proc$libresoc.v:144270$7062 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6741 1'0 + assign $0\logical_op__invert_in$10[0:0]$7063 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6741 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7063 end - attribute \src "libresoc.v:134514.7-134514.41" - process $proc$libresoc.v:134514$6742 + attribute \src "libresoc.v:144279.7-144279.41" + process $proc$libresoc.v:144279$7064 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6743 1'0 + assign $0\logical_op__invert_out$13[0:0]$7065 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6743 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7065 end - attribute \src "libresoc.v:134523.7-134523.39" - process $proc$libresoc.v:134523$6744 + attribute \src "libresoc.v:144288.7-144288.39" + process $proc$libresoc.v:144288$7066 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6745 1'0 + assign $0\logical_op__is_32bit$16[0:0]$7067 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6745 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7067 end - attribute \src "libresoc.v:134532.7-134532.40" - process $proc$libresoc.v:134532$6746 + attribute \src "libresoc.v:144297.7-144297.40" + process $proc$libresoc.v:144297$7068 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6747 1'0 + assign $0\logical_op__is_signed$17[0:0]$7069 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6747 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7069 end - attribute \src "libresoc.v:134543.7-134543.36" - process $proc$libresoc.v:134543$6748 + attribute \src "libresoc.v:144308.7-144308.36" + process $proc$libresoc.v:144308$7070 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6749 1'0 + assign $0\logical_op__oe__oe$8[0:0]$7071 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6749 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7071 end - attribute \src "libresoc.v:134552.7-134552.36" - process $proc$libresoc.v:134552$6750 + attribute \src "libresoc.v:144317.7-144317.36" + process $proc$libresoc.v:144317$7072 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6751 1'0 + assign $0\logical_op__oe__ok$9[0:0]$7073 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6751 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7073 end - attribute \src "libresoc.v:134559.7-134559.43" - process $proc$libresoc.v:134559$6752 + attribute \src "libresoc.v:144324.7-144324.43" + process $proc$libresoc.v:144324$7074 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6753 1'0 + assign $0\logical_op__output_carry$15[0:0]$7075 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6753 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7075 end - attribute \src "libresoc.v:134570.7-134570.36" - process $proc$libresoc.v:134570$6754 + attribute \src "libresoc.v:144335.7-144335.36" + process $proc$libresoc.v:144335$7076 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6755 1'0 + assign $0\logical_op__rc__ok$7[0:0]$7077 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6755 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7077 end - attribute \src "libresoc.v:134579.7-134579.36" - process $proc$libresoc.v:134579$6756 + attribute \src "libresoc.v:144344.7-144344.36" + process $proc$libresoc.v:144344$7078 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6757 1'0 + assign $0\logical_op__rc__rc$6[0:0]$7079 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6757 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7079 end - attribute \src "libresoc.v:134586.7-134586.40" - process $proc$libresoc.v:134586$6758 + attribute \src "libresoc.v:144351.7-144351.40" + process $proc$libresoc.v:144351$7080 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6759 1'0 + assign $0\logical_op__write_cr0$14[0:0]$7081 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6759 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7081 end - attribute \src "libresoc.v:134595.7-134595.37" - process $proc$libresoc.v:134595$6760 + attribute \src "libresoc.v:144360.7-144360.37" + process $proc$libresoc.v:144360$7082 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6761 1'0 + assign $0\logical_op__zero_a$11[0:0]$7083 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6761 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7083 end - attribute \src "libresoc.v:134604.13-134604.29" - process $proc$libresoc.v:134604$6762 + attribute \src "libresoc.v:144369.13-144369.29" + process $proc$libresoc.v:144369$7084 assign { } { } - assign $0\muxid$1[1:0]$6763 2'00 + assign $0\muxid$1[1:0]$7085 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$6763 + update \muxid$1 $0\muxid$1[1:0]$7085 end - attribute \src "libresoc.v:134619.14-134619.43" - process $proc$libresoc.v:134619$6764 + attribute \src "libresoc.v:144384.14-144384.43" + process $proc$libresoc.v:144384$7086 assign { } { } - assign $0\o$20[63:0]$6765 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$7087 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$6765 + update \o$20 $0\o$20[63:0]$7087 end - attribute \src "libresoc.v:134628.7-134628.23" - process $proc$libresoc.v:134628$6766 + attribute \src "libresoc.v:144393.7-144393.23" + process $proc$libresoc.v:144393$7088 assign { } { } - assign $0\o_ok$21[0:0]$6767 1'0 + assign $0\o_ok$21[0:0]$7089 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$6767 + update \o_ok$21 $0\o_ok$21[0:0]$7089 end - attribute \src "libresoc.v:134916.7-134916.20" - process $proc$libresoc.v:134916$6768 + attribute \src "libresoc.v:144687.7-144687.20" + process $proc$libresoc.v:144687$7090 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:134926.3-134927.33" - process $proc$libresoc.v:134926$6612 + attribute \src "libresoc.v:144697.3-144698.33" + process $proc$libresoc.v:144697$6934 assign { } { } - assign $0\cr_a$22[3:0]$6613 \cr_a$22$next + assign $0\cr_a$22[3:0]$6935 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6613 + update \cr_a$22 $0\cr_a$22[3:0]$6935 end - attribute \src "libresoc.v:134928.3-134929.39" - process $proc$libresoc.v:134928$6614 + attribute \src "libresoc.v:144699.3-144700.39" + process $proc$libresoc.v:144699$6936 assign { } { } - assign $0\cr_a_ok$23[0:0]$6615 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$6937 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6615 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6937 end - attribute \src "libresoc.v:134930.3-134931.27" - process $proc$libresoc.v:134930$6616 + attribute \src "libresoc.v:144701.3-144702.27" + process $proc$libresoc.v:144701$6938 assign { } { } - assign $0\o$20[63:0]$6617 \o$20$next + assign $0\o$20[63:0]$6939 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6617 + update \o$20 $0\o$20[63:0]$6939 end - attribute \src "libresoc.v:134932.3-134933.33" - process $proc$libresoc.v:134932$6618 + attribute \src "libresoc.v:144703.3-144704.33" + process $proc$libresoc.v:144703$6940 assign { } { } - assign $0\o_ok$21[0:0]$6619 \o_ok$21$next + assign $0\o_ok$21[0:0]$6941 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6619 + update \o_ok$21 $0\o_ok$21[0:0]$6941 end - attribute \src "libresoc.v:134934.3-134935.65" - process $proc$libresoc.v:134934$6620 + attribute \src "libresoc.v:144705.3-144706.65" + process $proc$libresoc.v:144705$6942 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6621 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$6943 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6621 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6943 end - attribute \src "libresoc.v:134936.3-134937.61" - process $proc$libresoc.v:134936$6622 + attribute \src "libresoc.v:144707.3-144708.61" + process $proc$libresoc.v:144707$6944 assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$6623 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$6945 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6623 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6945 end - attribute \src "libresoc.v:134938.3-134939.75" - process $proc$libresoc.v:134938$6624 + attribute \src "libresoc.v:144709.3-144710.75" + process $proc$libresoc.v:144709$6946 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6625 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$6947 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6625 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6947 end - attribute \src "libresoc.v:134940.3-134941.71" - process $proc$libresoc.v:134940$6626 + attribute \src "libresoc.v:144711.3-144712.71" + process $proc$libresoc.v:144711$6948 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6627 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$6949 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6627 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6949 end - attribute \src "libresoc.v:134942.3-134943.59" - process $proc$libresoc.v:134942$6628 + attribute \src "libresoc.v:144713.3-144714.59" + process $proc$libresoc.v:144713$6950 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6629 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$6951 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6629 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6951 end - attribute \src "libresoc.v:134944.3-134945.59" - process $proc$libresoc.v:134944$6630 + attribute \src "libresoc.v:144715.3-144716.59" + process $proc$libresoc.v:144715$6952 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6631 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$6953 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6631 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6953 end - attribute \src "libresoc.v:134946.3-134947.59" - process $proc$libresoc.v:134946$6632 + attribute \src "libresoc.v:144717.3-144718.59" + process $proc$libresoc.v:144717$6954 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6633 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$6955 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6633 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6955 end - attribute \src "libresoc.v:134948.3-134949.59" - process $proc$libresoc.v:134948$6634 + attribute \src "libresoc.v:144719.3-144720.59" + process $proc$libresoc.v:144719$6956 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6635 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$6957 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6635 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6957 end - attribute \src "libresoc.v:134950.3-134951.67" - process $proc$libresoc.v:134950$6636 + attribute \src "libresoc.v:144721.3-144722.67" + process $proc$libresoc.v:144721$6958 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6637 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$6959 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6637 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6959 end - attribute \src "libresoc.v:134952.3-134953.61" - process $proc$libresoc.v:134952$6638 + attribute \src "libresoc.v:144723.3-144724.61" + process $proc$libresoc.v:144723$6960 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6639 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$6961 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6639 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6961 end - attribute \src "libresoc.v:134954.3-134955.71" - process $proc$libresoc.v:134954$6640 + attribute \src "libresoc.v:144725.3-144726.71" + process $proc$libresoc.v:144725$6962 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6641 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$6963 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6641 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6963 end - attribute \src "libresoc.v:134956.3-134957.69" - process $proc$libresoc.v:134956$6642 + attribute \src "libresoc.v:144727.3-144728.69" + process $proc$libresoc.v:144727$6964 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6643 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$6965 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6643 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6965 end - attribute \src "libresoc.v:134958.3-134959.67" - process $proc$libresoc.v:134958$6644 + attribute \src "libresoc.v:144729.3-144730.67" + process $proc$libresoc.v:144729$6966 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6645 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$6967 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6645 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6967 end - attribute \src "libresoc.v:134960.3-134961.73" - process $proc$libresoc.v:134960$6646 + attribute \src "libresoc.v:144731.3-144732.73" + process $proc$libresoc.v:144731$6968 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6647 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$6969 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6647 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6969 end - attribute \src "libresoc.v:134962.3-134963.65" - process $proc$libresoc.v:134962$6648 + attribute \src "libresoc.v:144733.3-144734.65" + process $proc$libresoc.v:144733$6970 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6649 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$6971 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6649 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6971 end - attribute \src "libresoc.v:134964.3-134965.67" - process $proc$libresoc.v:134964$6650 + attribute \src "libresoc.v:144735.3-144736.67" + process $proc$libresoc.v:144735$6972 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6651 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$6973 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6651 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6973 end - attribute \src "libresoc.v:134966.3-134967.65" - process $proc$libresoc.v:134966$6652 + attribute \src "libresoc.v:144737.3-144738.65" + process $proc$libresoc.v:144737$6974 assign { } { } - assign $0\logical_op__data_len$18[3:0]$6653 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$6975 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6653 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6975 end - attribute \src "libresoc.v:134968.3-134969.57" - process $proc$libresoc.v:134968$6654 + attribute \src "libresoc.v:144739.3-144740.57" + process $proc$libresoc.v:144739$6976 assign { } { } - assign $0\logical_op__insn$19[31:0]$6655 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$6977 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6655 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6977 end - attribute \src "libresoc.v:134970.3-134971.33" - process $proc$libresoc.v:134970$6656 + attribute \src "libresoc.v:144741.3-144742.33" + process $proc$libresoc.v:144741$6978 assign { } { } - assign $0\muxid$1[1:0]$6657 \muxid$1$next + assign $0\muxid$1[1:0]$6979 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$6657 + update \muxid$1 $0\muxid$1[1:0]$6979 end - attribute \src "libresoc.v:134972.3-134973.29" - process $proc$libresoc.v:134972$6658 + attribute \src "libresoc.v:144743.3-144744.29" + process $proc$libresoc.v:144743$6980 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:135030.3-135047.6" - process $proc$libresoc.v:135030$6659 + attribute \src "libresoc.v:144801.3-144818.6" + process $proc$libresoc.v:144801$6981 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6660 $2\r_busy$next[0:0]$6662 - attribute \src "libresoc.v:135031.5-135031.29" + assign $0\r_busy$next[0:0]$6982 $2\r_busy$next[0:0]$6984 + attribute \src "libresoc.v:144802.5-144802.29" switch \initial - attribute \src "libresoc.v:135031.9-135031.17" + attribute \src "libresoc.v:144802.9-144802.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6661 1'1 + assign $1\r_busy$next[0:0]$6983 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6661 1'0 + assign $1\r_busy$next[0:0]$6983 1'0 case - assign $1\r_busy$next[0:0]$6661 \r_busy + assign $1\r_busy$next[0:0]$6983 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6662 1'0 + assign $2\r_busy$next[0:0]$6984 1'0 case - assign $2\r_busy$next[0:0]$6662 $1\r_busy$next[0:0]$6661 + assign $2\r_busy$next[0:0]$6984 $1\r_busy$next[0:0]$6983 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6660 + update \r_busy$next $0\r_busy$next[0:0]$6982 end - attribute \src "libresoc.v:135048.3-135060.6" - process $proc$libresoc.v:135048$6663 + attribute \src "libresoc.v:144819.3-144831.6" + process $proc$libresoc.v:144819$6985 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$6664 $1\muxid$1$next[1:0]$6665 - attribute \src "libresoc.v:135049.5-135049.29" + assign $0\muxid$1$next[1:0]$6986 $1\muxid$1$next[1:0]$6987 + attribute \src "libresoc.v:144820.5-144820.29" switch \initial - attribute \src "libresoc.v:135049.9-135049.17" + attribute \src "libresoc.v:144820.9-144820.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$6665 \muxid$51 + assign $1\muxid$1$next[1:0]$6987 \muxid$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$6665 \muxid$51 + assign $1\muxid$1$next[1:0]$6987 \muxid$51 case - assign $1\muxid$1$next[1:0]$6665 \muxid$1 + assign $1\muxid$1$next[1:0]$6987 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$6664 + update \muxid$1$next $0\muxid$1$next[1:0]$6986 end - attribute \src "libresoc.v:135061.3-135102.6" - process $proc$libresoc.v:135061$6666 + attribute \src "libresoc.v:144832.3-144873.6" + process $proc$libresoc.v:144832$6988 assign { } { } assign { } { } assign { } { } @@ -220468,37 +236323,37 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$6667 $1\logical_op__data_len$18$next[3:0]$6685 - assign $0\logical_op__fn_unit$3$next[11:0]$6668 $1\logical_op__fn_unit$3$next[11:0]$6686 + assign $0\logical_op__data_len$18$next[3:0]$6989 $1\logical_op__data_len$18$next[3:0]$7007 + assign $0\logical_op__fn_unit$3$next[13:0]$6990 $1\logical_op__fn_unit$3$next[13:0]$7008 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$6671 $1\logical_op__input_carry$12$next[1:0]$6689 - assign $0\logical_op__insn$19$next[31:0]$6672 $1\logical_op__insn$19$next[31:0]$6690 - assign $0\logical_op__insn_type$2$next[6:0]$6673 $1\logical_op__insn_type$2$next[6:0]$6691 - assign $0\logical_op__invert_in$10$next[0:0]$6674 $1\logical_op__invert_in$10$next[0:0]$6692 - assign $0\logical_op__invert_out$13$next[0:0]$6675 $1\logical_op__invert_out$13$next[0:0]$6693 - assign $0\logical_op__is_32bit$16$next[0:0]$6676 $1\logical_op__is_32bit$16$next[0:0]$6694 - assign $0\logical_op__is_signed$17$next[0:0]$6677 $1\logical_op__is_signed$17$next[0:0]$6695 + assign $0\logical_op__input_carry$12$next[1:0]$6993 $1\logical_op__input_carry$12$next[1:0]$7011 + assign $0\logical_op__insn$19$next[31:0]$6994 $1\logical_op__insn$19$next[31:0]$7012 + assign $0\logical_op__insn_type$2$next[6:0]$6995 $1\logical_op__insn_type$2$next[6:0]$7013 + assign $0\logical_op__invert_in$10$next[0:0]$6996 $1\logical_op__invert_in$10$next[0:0]$7014 + assign $0\logical_op__invert_out$13$next[0:0]$6997 $1\logical_op__invert_out$13$next[0:0]$7015 + assign $0\logical_op__is_32bit$16$next[0:0]$6998 $1\logical_op__is_32bit$16$next[0:0]$7016 + assign $0\logical_op__is_signed$17$next[0:0]$6999 $1\logical_op__is_signed$17$next[0:0]$7017 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$6680 $1\logical_op__output_carry$15$next[0:0]$6698 + assign $0\logical_op__output_carry$15$next[0:0]$7002 $1\logical_op__output_carry$15$next[0:0]$7020 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$6683 $1\logical_op__write_cr0$14$next[0:0]$6701 - assign $0\logical_op__zero_a$11$next[0:0]$6684 $1\logical_op__zero_a$11$next[0:0]$6702 - assign $0\logical_op__imm_data__data$4$next[63:0]$6669 $2\logical_op__imm_data__data$4$next[63:0]$6703 - assign $0\logical_op__imm_data__ok$5$next[0:0]$6670 $2\logical_op__imm_data__ok$5$next[0:0]$6704 - assign $0\logical_op__oe__oe$8$next[0:0]$6678 $2\logical_op__oe__oe$8$next[0:0]$6705 - assign $0\logical_op__oe__ok$9$next[0:0]$6679 $2\logical_op__oe__ok$9$next[0:0]$6706 - assign $0\logical_op__rc__ok$7$next[0:0]$6681 $2\logical_op__rc__ok$7$next[0:0]$6707 - assign $0\logical_op__rc__rc$6$next[0:0]$6682 $2\logical_op__rc__rc$6$next[0:0]$6708 - attribute \src "libresoc.v:135062.5-135062.29" + assign $0\logical_op__write_cr0$14$next[0:0]$7005 $1\logical_op__write_cr0$14$next[0:0]$7023 + assign $0\logical_op__zero_a$11$next[0:0]$7006 $1\logical_op__zero_a$11$next[0:0]$7024 + assign $0\logical_op__imm_data__data$4$next[63:0]$6991 $2\logical_op__imm_data__data$4$next[63:0]$7025 + assign $0\logical_op__imm_data__ok$5$next[0:0]$6992 $2\logical_op__imm_data__ok$5$next[0:0]$7026 + assign $0\logical_op__oe__oe$8$next[0:0]$7000 $2\logical_op__oe__oe$8$next[0:0]$7027 + assign $0\logical_op__oe__ok$9$next[0:0]$7001 $2\logical_op__oe__ok$9$next[0:0]$7028 + assign $0\logical_op__rc__ok$7$next[0:0]$7003 $2\logical_op__rc__ok$7$next[0:0]$7029 + assign $0\logical_op__rc__rc$6$next[0:0]$7004 $2\logical_op__rc__rc$6$next[0:0]$7030 + attribute \src "libresoc.v:144833.5-144833.29" switch \initial - attribute \src "libresoc.v:135062.9-135062.17" + attribute \src "libresoc.v:144833.9-144833.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -220520,7 +236375,7 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6690 $1\logical_op__data_len$18$next[3:0]$6685 $1\logical_op__is_signed$17$next[0:0]$6695 $1\logical_op__is_32bit$16$next[0:0]$6694 $1\logical_op__output_carry$15$next[0:0]$6698 $1\logical_op__write_cr0$14$next[0:0]$6701 $1\logical_op__invert_out$13$next[0:0]$6693 $1\logical_op__input_carry$12$next[1:0]$6689 $1\logical_op__zero_a$11$next[0:0]$6702 $1\logical_op__invert_in$10$next[0:0]$6692 $1\logical_op__oe__ok$9$next[0:0]$6697 $1\logical_op__oe__oe$8$next[0:0]$6696 $1\logical_op__rc__ok$7$next[0:0]$6699 $1\logical_op__rc__rc$6$next[0:0]$6700 $1\logical_op__imm_data__ok$5$next[0:0]$6688 $1\logical_op__imm_data__data$4$next[63:0]$6687 $1\logical_op__fn_unit$3$next[11:0]$6686 $1\logical_op__insn_type$2$next[6:0]$6691 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7012 $1\logical_op__data_len$18$next[3:0]$7007 $1\logical_op__is_signed$17$next[0:0]$7017 $1\logical_op__is_32bit$16$next[0:0]$7016 $1\logical_op__output_carry$15$next[0:0]$7020 $1\logical_op__write_cr0$14$next[0:0]$7023 $1\logical_op__invert_out$13$next[0:0]$7015 $1\logical_op__input_carry$12$next[1:0]$7011 $1\logical_op__zero_a$11$next[0:0]$7024 $1\logical_op__invert_in$10$next[0:0]$7014 $1\logical_op__oe__ok$9$next[0:0]$7019 $1\logical_op__oe__oe$8$next[0:0]$7018 $1\logical_op__rc__ok$7$next[0:0]$7021 $1\logical_op__rc__rc$6$next[0:0]$7022 $1\logical_op__imm_data__ok$5$next[0:0]$7010 $1\logical_op__imm_data__data$4$next[63:0]$7009 $1\logical_op__fn_unit$3$next[13:0]$7008 $1\logical_op__insn_type$2$next[6:0]$7013 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -220541,26 +236396,26 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6690 $1\logical_op__data_len$18$next[3:0]$6685 $1\logical_op__is_signed$17$next[0:0]$6695 $1\logical_op__is_32bit$16$next[0:0]$6694 $1\logical_op__output_carry$15$next[0:0]$6698 $1\logical_op__write_cr0$14$next[0:0]$6701 $1\logical_op__invert_out$13$next[0:0]$6693 $1\logical_op__input_carry$12$next[1:0]$6689 $1\logical_op__zero_a$11$next[0:0]$6702 $1\logical_op__invert_in$10$next[0:0]$6692 $1\logical_op__oe__ok$9$next[0:0]$6697 $1\logical_op__oe__oe$8$next[0:0]$6696 $1\logical_op__rc__ok$7$next[0:0]$6699 $1\logical_op__rc__rc$6$next[0:0]$6700 $1\logical_op__imm_data__ok$5$next[0:0]$6688 $1\logical_op__imm_data__data$4$next[63:0]$6687 $1\logical_op__fn_unit$3$next[11:0]$6686 $1\logical_op__insn_type$2$next[6:0]$6691 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7012 $1\logical_op__data_len$18$next[3:0]$7007 $1\logical_op__is_signed$17$next[0:0]$7017 $1\logical_op__is_32bit$16$next[0:0]$7016 $1\logical_op__output_carry$15$next[0:0]$7020 $1\logical_op__write_cr0$14$next[0:0]$7023 $1\logical_op__invert_out$13$next[0:0]$7015 $1\logical_op__input_carry$12$next[1:0]$7011 $1\logical_op__zero_a$11$next[0:0]$7024 $1\logical_op__invert_in$10$next[0:0]$7014 $1\logical_op__oe__ok$9$next[0:0]$7019 $1\logical_op__oe__oe$8$next[0:0]$7018 $1\logical_op__rc__ok$7$next[0:0]$7021 $1\logical_op__rc__rc$6$next[0:0]$7022 $1\logical_op__imm_data__ok$5$next[0:0]$7010 $1\logical_op__imm_data__data$4$next[63:0]$7009 $1\logical_op__fn_unit$3$next[13:0]$7008 $1\logical_op__insn_type$2$next[6:0]$7013 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case - assign $1\logical_op__data_len$18$next[3:0]$6685 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[11:0]$6686 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$6687 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$6688 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$6689 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$6690 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$6691 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$6692 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$6693 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$6694 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$6695 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$6696 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$6697 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$6698 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$6699 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$6700 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$6701 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$6702 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$7007 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$7008 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$7009 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$7010 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$7011 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$7012 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$7013 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$7014 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$7015 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$7016 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$7017 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$7018 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$7019 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7020 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7021 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7022 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7023 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7024 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -220572,129 +236427,129 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$6703 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6704 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$6708 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$6707 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$6705 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$6706 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$7025 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7026 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7030 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7029 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7027 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7028 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$6703 $1\logical_op__imm_data__data$4$next[63:0]$6687 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6704 $1\logical_op__imm_data__ok$5$next[0:0]$6688 - assign $2\logical_op__oe__oe$8$next[0:0]$6705 $1\logical_op__oe__oe$8$next[0:0]$6696 - assign $2\logical_op__oe__ok$9$next[0:0]$6706 $1\logical_op__oe__ok$9$next[0:0]$6697 - assign $2\logical_op__rc__ok$7$next[0:0]$6707 $1\logical_op__rc__ok$7$next[0:0]$6699 - assign $2\logical_op__rc__rc$6$next[0:0]$6708 $1\logical_op__rc__rc$6$next[0:0]$6700 + assign $2\logical_op__imm_data__data$4$next[63:0]$7025 $1\logical_op__imm_data__data$4$next[63:0]$7009 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7026 $1\logical_op__imm_data__ok$5$next[0:0]$7010 + assign $2\logical_op__oe__oe$8$next[0:0]$7027 $1\logical_op__oe__oe$8$next[0:0]$7018 + assign $2\logical_op__oe__ok$9$next[0:0]$7028 $1\logical_op__oe__ok$9$next[0:0]$7019 + assign $2\logical_op__rc__ok$7$next[0:0]$7029 $1\logical_op__rc__ok$7$next[0:0]$7021 + assign $2\logical_op__rc__rc$6$next[0:0]$7030 $1\logical_op__rc__rc$6$next[0:0]$7022 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6667 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$6668 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6669 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6670 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6671 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6672 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6673 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6674 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6675 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6676 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6677 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6678 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6679 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6680 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6681 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6682 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6683 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6684 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6989 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$6990 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6991 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6992 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6993 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6994 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6995 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6996 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6997 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6998 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6999 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7000 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7001 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7002 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7003 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7004 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7005 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7006 end - attribute \src "libresoc.v:135103.3-135121.6" - process $proc$libresoc.v:135103$6709 + attribute \src "libresoc.v:144874.3-144892.6" + process $proc$libresoc.v:144874$7031 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$6710 $1\o$20$next[63:0]$6712 + assign $0\o$20$next[63:0]$7032 $1\o$20$next[63:0]$7034 assign { } { } - assign $0\o_ok$21$next[0:0]$6711 $2\o_ok$21$next[0:0]$6714 - attribute \src "libresoc.v:135104.5-135104.29" + assign $0\o_ok$21$next[0:0]$7033 $2\o_ok$21$next[0:0]$7036 + attribute \src "libresoc.v:144875.5-144875.29" switch \initial - attribute \src "libresoc.v:135104.9-135104.17" + attribute \src "libresoc.v:144875.9-144875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$6713 $1\o$20$next[63:0]$6712 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7035 $1\o$20$next[63:0]$7034 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$6713 $1\o$20$next[63:0]$6712 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7035 $1\o$20$next[63:0]$7034 } { \o_ok$71 \o$70 } case - assign $1\o$20$next[63:0]$6712 \o$20 - assign $1\o_ok$21$next[0:0]$6713 \o_ok$21 + assign $1\o$20$next[63:0]$7034 \o$20 + assign $1\o_ok$21$next[0:0]$7035 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$6714 1'0 + assign $2\o_ok$21$next[0:0]$7036 1'0 case - assign $2\o_ok$21$next[0:0]$6714 $1\o_ok$21$next[0:0]$6713 + assign $2\o_ok$21$next[0:0]$7036 $1\o_ok$21$next[0:0]$7035 end sync always - update \o$20$next $0\o$20$next[63:0]$6710 - update \o_ok$21$next $0\o_ok$21$next[0:0]$6711 + update \o$20$next $0\o$20$next[63:0]$7032 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7033 end - attribute \src "libresoc.v:135122.3-135140.6" - process $proc$libresoc.v:135122$6715 + attribute \src "libresoc.v:144893.3-144911.6" + process $proc$libresoc.v:144893$7037 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$6716 $1\cr_a$22$next[3:0]$6718 + assign $0\cr_a$22$next[3:0]$7038 $1\cr_a$22$next[3:0]$7040 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$6717 $2\cr_a_ok$23$next[0:0]$6720 - attribute \src "libresoc.v:135123.5-135123.29" + assign $0\cr_a_ok$23$next[0:0]$7039 $2\cr_a_ok$23$next[0:0]$7042 + attribute \src "libresoc.v:144894.5-144894.29" switch \initial - attribute \src "libresoc.v:135123.9-135123.17" + attribute \src "libresoc.v:144894.9-144894.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6719 $1\cr_a$22$next[3:0]$6718 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7041 $1\cr_a$22$next[3:0]$7040 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6719 $1\cr_a$22$next[3:0]$6718 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7041 $1\cr_a$22$next[3:0]$7040 } { \cr_a_ok$73 \cr_a$72 } case - assign $1\cr_a$22$next[3:0]$6718 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$6719 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$7040 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7041 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$6720 1'0 + assign $2\cr_a_ok$23$next[0:0]$7042 1'0 case - assign $2\cr_a_ok$23$next[0:0]$6720 $1\cr_a_ok$23$next[0:0]$6719 + assign $2\cr_a_ok$23$next[0:0]$7042 $1\cr_a_ok$23$next[0:0]$7041 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$6716 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6717 + update \cr_a$22$next $0\cr_a$22$next[3:0]$7038 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7039 end - connect \$49 $and$libresoc.v:134925$6611_Y + connect \$49 $and$libresoc.v:144696$6933_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -220710,2600 +236565,2766 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-10732.10" +attribute \src "ls180.v:4.1-11017.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 - attribute \src "ls180.v:10240.1-10244.4" - wire width 3 $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 - attribute \src "ls180.v:10240.1-10244.4" - wire width 25 $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 - attribute \src "ls180.v:10240.1-10244.4" - wire width 25 $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 - attribute \src "ls180.v:10254.1-10258.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 - attribute \src "ls180.v:10254.1-10258.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 - attribute \src "ls180.v:10254.1-10258.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 - attribute \src "ls180.v:10268.1-10272.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 - attribute \src "ls180.v:10268.1-10272.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 - attribute \src "ls180.v:10268.1-10272.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 - attribute \src "ls180.v:10282.1-10286.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 - attribute \src "ls180.v:10282.1-10286.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 - attribute \src "ls180.v:10282.1-10286.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 - attribute \src "ls180.v:10297.1-10301.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 - attribute \src "ls180.v:10297.1-10301.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 - attribute \src "ls180.v:10297.1-10301.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 - attribute \src "ls180.v:10314.1-10318.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 - attribute \src "ls180.v:10314.1-10318.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 - attribute \src "ls180.v:10314.1-10318.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 - attribute \src "ls180.v:10330.1-10334.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 - attribute \src "ls180.v:10330.1-10334.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 - attribute \src "ls180.v:10330.1-10334.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 - attribute \src "ls180.v:10344.1-10348.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 - attribute \src "ls180.v:10344.1-10348.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 - attribute \src "ls180.v:10344.1-10348.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 + attribute \src "ls180.v:10493.1-10497.4" + wire width 3 $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 + attribute \src "ls180.v:10493.1-10497.4" + wire width 25 $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 + attribute \src "ls180.v:10493.1-10497.4" + wire width 25 $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 + attribute \src "ls180.v:10507.1-10511.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 + attribute \src "ls180.v:10507.1-10511.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 + attribute \src "ls180.v:10507.1-10511.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 + attribute \src "ls180.v:10521.1-10525.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 + attribute \src "ls180.v:10521.1-10525.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 + attribute \src "ls180.v:10521.1-10525.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 + attribute \src "ls180.v:10535.1-10539.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 + attribute \src "ls180.v:10535.1-10539.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 + attribute \src "ls180.v:10535.1-10539.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 + attribute \src "ls180.v:10550.1-10554.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 + attribute \src "ls180.v:10550.1-10554.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 + attribute \src "ls180.v:10550.1-10554.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 + attribute \src "ls180.v:10567.1-10571.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 + attribute \src "ls180.v:10567.1-10571.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 + attribute \src "ls180.v:10567.1-10571.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 + attribute \src "ls180.v:10583.1-10587.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 + attribute \src "ls180.v:10583.1-10587.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 + attribute \src "ls180.v:10583.1-10587.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 + attribute \src "ls180.v:10597.1-10601.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 + attribute \src "ls180.v:10597.1-10601.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 + attribute \src "ls180.v:10597.1-10601.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 + attribute \src "ls180.v:3402.1-3495.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6618.1-6634.4" + attribute \src "ls180.v:6791.1-6807.4" wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6839.1-6855.4" + attribute \src "ls180.v:7012.1-7028.4" wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6856.1-6872.4" + attribute \src "ls180.v:7029.1-7045.4" wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6924.1-6931.4" + attribute \src "ls180.v:7097.1-7104.4" wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6932.1-6939.4" + attribute \src "ls180.v:7105.1-7112.4" wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6940.1-6947.4" + attribute \src "ls180.v:7113.1-7120.4" wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6948.1-6955.4" + attribute \src "ls180.v:7121.1-7128.4" wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6956.1-6963.4" + attribute \src "ls180.v:7129.1-7136.4" wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6964.1-6971.4" + attribute \src "ls180.v:7137.1-7144.4" wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6972.1-6979.4" + attribute \src "ls180.v:7145.1-7152.4" wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6980.1-6987.4" + attribute \src "ls180.v:7153.1-7160.4" wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6635.1-6651.4" + attribute \src "ls180.v:6808.1-6824.4" wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6988.1-6995.4" + attribute \src "ls180.v:7161.1-7168.4" wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6996.1-7003.4" + attribute \src "ls180.v:7169.1-7176.4" wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:7004.1-7011.4" + attribute \src "ls180.v:7177.1-7184.4" wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:7012.1-7019.4" + attribute \src "ls180.v:7185.1-7192.4" wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:7020.1-7039.4" + attribute \src "ls180.v:7193.1-7212.4" wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:7040.1-7059.4" - wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:7060.1-7079.4" - wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:7080.1-7099.4" + attribute \src "ls180.v:7213.1-7232.4" + wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:7233.1-7252.4" + wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:7253.1-7272.4" wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:7100.1-7119.4" + attribute \src "ls180.v:7273.1-7292.4" wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7120.1-7139.4" + attribute \src "ls180.v:7293.1-7312.4" wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6652.1-6668.4" + attribute \src "ls180.v:6825.1-6841.4" wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7140.1-7159.4" + attribute \src "ls180.v:7313.1-7332.4" wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7160.1-7179.4" + attribute \src "ls180.v:7333.1-7352.4" wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6669.1-6685.4" + attribute \src "ls180.v:6842.1-6858.4" wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6686.1-6702.4" + attribute \src "ls180.v:6859.1-6875.4" wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6703.1-6719.4" + attribute \src "ls180.v:6876.1-6892.4" wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6771.1-6787.4" + attribute \src "ls180.v:6944.1-6960.4" wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6788.1-6804.4" + attribute \src "ls180.v:6961.1-6977.4" wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6805.1-6821.4" + attribute \src "ls180.v:6978.1-6994.4" wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6822.1-6838.4" + attribute \src "ls180.v:6995.1-7011.4" wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6720.1-6736.4" + attribute \src "ls180.v:6893.1-6909.4" wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6737.1-6753.4" + attribute \src "ls180.v:6910.1-6926.4" wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6754.1-6770.4" + attribute \src "ls180.v:6927.1-6943.4" wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6873.1-6889.4" + attribute \src "ls180.v:7046.1-7062.4" wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6890.1-6906.4" + attribute \src "ls180.v:7063.1-7079.4" wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6907.1-6923.4" + attribute \src "ls180.v:7080.1-7096.4" wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2831.1-2877.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2891.1-2937.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:2951.1-2997.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5858.1-5869.4" + attribute \src "ls180.v:6031.1-6042.4" wire $0\builder_error[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5848.1-5884.4" wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:1993.5-1993.55" + wire $0\builder_libresocsim_converted_interface_ack[0:0] + attribute \src "ls180.v:1989.12-1989.65" + wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] + attribute \src "ls180.v:1997.5-1997.55" + wire $0\builder_libresocsim_converted_interface_err[0:0] + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5848.1-5884.4" wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:1979.12-1979.52" + wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] + attribute \src "ls180.v:1983.5-1983.44" + wire $0\builder_libresocsim_wishbone_cyc[0:0] + attribute \src "ls180.v:5848.1-5884.4" wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1922.5-1922.44" - wire $0\builder_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:1811.5-1811.27" + attribute \src "ls180.v:1980.12-1980.54" + wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] + attribute \src "ls180.v:1982.11-1982.50" + wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] + attribute \src "ls180.v:1984.5-1984.44" + wire $0\builder_libresocsim_wishbone_stb[0:0] + attribute \src "ls180.v:1986.5-1986.43" + wire $0\builder_libresocsim_wishbone_we[0:0] + attribute \src "ls180.v:1878.5-1878.27" wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1812.5-1812.27" + attribute \src "ls180.v:1879.5-1879.27" wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1813.5-1813.27" + attribute \src "ls180.v:1880.5-1880.27" wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1814.5-1814.27" + attribute \src "ls180.v:1881.5-1881.27" wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5848.1-5884.4" wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3203.1-3233.4" + attribute \src "ls180.v:3308.1-3338.4" wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5646.1-5685.4" wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5743.1-5779.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4623.1-4699.4" wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5858.1-5869.4" + attribute \src "ls180.v:6031.1-6042.4" wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5858.1-5869.4" + attribute \src "ls180.v:6031.1-6042.4" wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5781.1-5791.4" - wire width 8 $0\builder_slave_sel[7:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 8 $0\builder_slave_sel_r[7:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:5909.1-5924.4" + wire width 13 $0\builder_slave_sel[12:0] + attribute \src "ls180.v:7705.1-10349.4" + wire width 13 $0\builder_slave_sel_r[12:0] + attribute \src "ls180.v:4420.1-4468.4" wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7299.1-7327.4" + attribute \src "ls180.v:7472.1-7500.4" wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7328.1-7356.4" + attribute \src "ls180.v:7501.1-7529.4" wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7180.1-7196.4" + attribute \src "ls180.v:7353.1-7369.4" wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7197.1-7213.4" + attribute \src "ls180.v:7370.1-7386.4" wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7214.1-7230.4" + attribute \src "ls180.v:7387.1-7403.4" wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7231.1-7247.4" + attribute \src "ls180.v:7404.1-7420.4" wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7248.1-7264.4" + attribute \src "ls180.v:7421.1-7437.4" wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7265.1-7281.4" + attribute \src "ls180.v:7438.1-7454.4" wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7282.1-7298.4" + attribute \src "ls180.v:7455.1-7471.4" wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:4399.1-4403.4" + wire width 16 $0\gpio_o[15:0] + attribute \src "ls180.v:4404.1-4408.4" + wire width 16 $0\gpio_oe[15:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" + wire $0\main_converter0_counter[0:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7705.1-10349.4" + wire width 64 $0\main_converter0_dat_r[63:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_converter0_skip[0:0] + attribute \src "ls180.v:7705.1-10349.4" + wire $0\main_converter1_counter[0:0] + attribute \src "ls180.v:2966.1-3012.4" + wire $0\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2966.1-3012.4" + wire $0\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7705.1-10349.4" + wire width 64 $0\main_converter1_dat_r[63:0] + attribute \src "ls180.v:2966.1-3012.4" + wire $0\main_converter1_skip[0:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 24 $0\main_dummy[23:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_gpio_oe_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 16 $0\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_gpio_out_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 16 $0\main_gpio_out_storage[15:0] - attribute \src "ls180.v:7414.1-7432.4" - wire width 16 $0\main_gpio_status[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:1085.12-1085.53" + wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] + attribute \src "ls180.v:1087.12-1087.54" + wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] + attribute \src "ls180.v:7587.1-7597.4" + wire width 16 $0\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:7705.1-10349.4" + wire $0\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:7705.1-10349.4" + wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:7705.1-10349.4" + wire $0\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:7705.1-10349.4" + wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:7598.1-7608.4" + wire width 16 $0\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7453.1-7455.4" + attribute \src "ls180.v:7629.1-7631.4" wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1599.11-1599.41" + attribute \src "ls180.v:1666.11-1666.41" wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1598.11-1598.41" + attribute \src "ls180.v:1665.11-1665.41" wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:319.5-319.51" + wire $0\main_interface0_converted_interface_err[0:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:255.5-255.39" + attribute \src "ls180.v:259.5-259.39" wire $0\main_interface0_ram_bus_err[0:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5705.1-5742.4" wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1690.11-1690.41" + attribute \src "ls180.v:1757.11-1757.41" wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1689.11-1689.41" + attribute \src "ls180.v:1756.11-1756.41" wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1682.12-1682.45" - wire width 32 $0\main_interface1_bus_dat_w[31:0] - attribute \src "ls180.v:5589.1-5626.4" - wire width 4 $0\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:1749.12-1749.45" + wire width 64 $0\main_interface1_bus_dat_w[63:0] + attribute \src "ls180.v:5705.1-5742.4" + wire width 8 $0\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:2966.1-3012.4" + wire $0\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:334.5-334.51" + wire $0\main_interface1_converted_interface_err[0:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:270.5-270.39" + attribute \src "ls180.v:274.5-274.39" wire $0\main_interface1_ram_bus_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:285.5-285.39" + attribute \src "ls180.v:289.5-289.39" wire $0\main_interface2_ram_bus_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" + wire $0\main_interface3_ram_bus_ack[0:0] + attribute \src "ls180.v:304.5-304.39" + wire $0\main_interface3_ram_bus_err[0:0] + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:167.11-167.69" - wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] - attribute \src "ls180.v:166.11-166.69" - wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:2819.1-2829.4" - wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2831.1-2877.4" - wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:182.11-182.69" - wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] - attribute \src "ls180.v:181.11-181.69" - wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:2879.1-2889.4" - wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2891.1-2937.4" - wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:2951.1-2997.4" - wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:197.11-197.69" - wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] - attribute \src "ls180.v:196.11-196.69" - wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:2939.1-2949.4" - wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2951.1-2997.4" - wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:74.5-74.46" - wire $0\main_libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:83.5-83.46" - wire $0\main_libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:2812.1-2817.4" + attribute \src "ls180.v:182.12-182.74" + wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + attribute \src "ls180.v:179.5-179.69" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + attribute \src "ls180.v:172.5-172.72" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + attribute \src "ls180.v:175.11-175.79" + wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + attribute \src "ls180.v:195.12-195.78" + wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + attribute \src "ls180.v:75.11-75.52" + wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] + attribute \src "ls180.v:74.11-74.52" + wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] + attribute \src "ls180.v:86.11-86.52" + wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] + attribute \src "ls180.v:85.11-85.52" + wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] + attribute \src "ls180.v:2887.1-2892.4" wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:114.5-114.49" - wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:115.11-115.55" + wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + attribute \src "ls180.v:114.11-114.55" + wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + attribute \src "ls180.v:2906.1-2952.4" + wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:2894.1-2904.4" + wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:2906.1-2952.4" + wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:2966.1-3012.4" + wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:2966.1-3012.4" + wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:2954.1-2964.4" + wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:2966.1-3012.4" + wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:2966.1-3012.4" + wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:2966.1-3012.4" + wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:213.5-213.40" + attribute \src "ls180.v:217.5-217.40" wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:3000.1-3006.4" - wire width 4 $0\main_libresocsim_we[3:0] - attribute \src "ls180.v:3012.1-3017.4" + attribute \src "ls180.v:3075.1-3085.4" + wire width 8 $0\main_libresocsim_we[7:0] + attribute \src "ls180.v:3091.1-3096.4" wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4102.1-4112.4" + attribute \src "ls180.v:4207.1-4217.4" wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 2 $0\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" + wire width 3 $0\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" + wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:7705.1-10349.4" + wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1623.5-1623.41" + attribute \src "ls180.v:1690.5-1690.41" wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5497.1-5504.4" + attribute \src "ls180.v:5613.1-5620.4" wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5646.1-5685.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5530.1-5569.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5646.1-5685.4" + wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:5646.1-5685.4" wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5646.1-5685.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5646.1-5685.4" wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5646.1-5685.4" wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5646.1-5685.4" wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1432.5-1432.34" + attribute \src "ls180.v:1499.5-1499.34" wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5185.1-5192.4" + attribute \src "ls180.v:5301.1-5308.4" wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5241.1-5248.4" + attribute \src "ls180.v:5357.1-5364.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5195.1-5202.4" + attribute \src "ls180.v:5311.1-5318.4" wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5251.1-5258.4" + attribute \src "ls180.v:5367.1-5374.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5205.1-5212.4" + attribute \src "ls180.v:5321.1-5328.4" wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5261.1-5268.4" + attribute \src "ls180.v:5377.1-5384.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5215.1-5222.4" + attribute \src "ls180.v:5331.1-5338.4" wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5271.1-5278.4" + attribute \src "ls180.v:5387.1-5394.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5230.1-5237.4" + attribute \src "ls180.v:5346.1-5353.4" wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1538.5-1538.50" + attribute \src "ls180.v:1605.5-1605.50" wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5224.1-5229.4" + attribute \src "ls180.v:5340.1-5345.4" wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5177.1-5182.4" + attribute \src "ls180.v:5293.1-5298.4" wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:5059.1-5066.4" + attribute \src "ls180.v:5175.1-5182.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:5069.1-5076.4" + attribute \src "ls180.v:5185.1-5192.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5079.1-5086.4" + attribute \src "ls180.v:5195.1-5202.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5089.1-5096.4" + attribute \src "ls180.v:5205.1-5212.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1495.5-1495.51" + attribute \src "ls180.v:1562.5-1562.51" wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:5037.1-5044.4" + attribute \src "ls180.v:5153.1-5160.4" wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 2 $0\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:5675.1-5691.4" + attribute \src "ls180.v:7705.1-10349.4" + wire width 3 $0\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:5791.1-5819.4" wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 32 $0\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:5589.1-5626.4" - wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:7705.1-10349.4" + wire width 64 $0\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:5705.1-5742.4" + wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5743.1-5779.4" wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5743.1-5779.4" wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5743.1-5779.4" wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5743.1-5779.4" wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5743.1-5779.4" wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5743.1-5779.4" wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1703.5-1703.45" + attribute \src "ls180.v:1770.5-1770.45" wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5589.1-5626.4" - wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5705.1-5742.4" + wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1759.5-1759.41" + attribute \src "ls180.v:1826.5-1826.41" wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5705.1-5712.4" + attribute \src "ls180.v:5833.1-5840.4" wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4443.1-4471.4" + attribute \src "ls180.v:4559.1-4587.4" wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1224.5-1224.53" + attribute \src "ls180.v:1291.5-1291.53" wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1225.5-1225.52" + attribute \src "ls180.v:1292.5-1292.52" wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1205.5-1205.46" + attribute \src "ls180.v:1272.5-1272.46" wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1178.5-1178.49" + attribute \src "ls180.v:1245.5-1245.49" wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1179.5-1179.48" + attribute \src "ls180.v:1246.5-1246.48" wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1180.5-1180.55" + attribute \src "ls180.v:1247.5-1247.55" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1182.5-1182.57" + attribute \src "ls180.v:1249.5-1249.57" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1183.5-1183.58" + attribute \src "ls180.v:1250.5-1250.58" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1185.11-1185.64" + attribute \src "ls180.v:1252.11-1252.64" wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1186.5-1186.59" + attribute \src "ls180.v:1253.5-1253.59" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1191.11-1191.57" + attribute \src "ls180.v:1258.11-1258.57" wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1192.5-1192.52" + attribute \src "ls180.v:1259.5-1259.52" wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4623.1-4699.4" wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1168.11-1168.57" + attribute \src "ls180.v:1235.11-1235.57" wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1169.5-1169.52" + attribute \src "ls180.v:1236.5-1236.52" wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1380.5-1380.55" + attribute \src "ls180.v:1447.5-1447.55" wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1381.5-1381.54" + attribute \src "ls180.v:1448.5-1448.54" wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1361.5-1361.48" + attribute \src "ls180.v:1428.5-1428.48" wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1332.5-1332.50" + attribute \src "ls180.v:1399.5-1399.50" wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1333.5-1333.49" + attribute \src "ls180.v:1400.5-1400.49" wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1334.5-1334.56" + attribute \src "ls180.v:1401.5-1401.56" wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1336.5-1336.58" + attribute \src "ls180.v:1403.5-1403.58" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1337.5-1337.59" + attribute \src "ls180.v:1404.5-1404.59" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1339.11-1339.65" + attribute \src "ls180.v:1406.11-1406.65" wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1340.5-1340.60" + attribute \src "ls180.v:1407.5-1407.60" wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1343.5-1343.51" + attribute \src "ls180.v:1410.5-1410.51" wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1344.5-1344.52" + attribute \src "ls180.v:1411.5-1411.52" wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1345.11-1345.58" + attribute \src "ls180.v:1412.11-1412.58" wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1346.5-1346.53" + attribute \src "ls180.v:1413.5-1413.53" wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1353.5-1353.41" + attribute \src "ls180.v:1420.5-1420.41" wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1302.5-1302.54" + attribute \src "ls180.v:1369.5-1369.54" wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1303.5-1303.53" + attribute \src "ls180.v:1370.5-1370.53" wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1283.5-1283.47" + attribute \src "ls180.v:1350.5-1350.47" wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1270.5-1270.50" + attribute \src "ls180.v:1337.5-1337.50" wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1271.5-1271.49" + attribute \src "ls180.v:1338.5-1338.49" wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1272.5-1272.56" + attribute \src "ls180.v:1339.5-1339.56" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1273.5-1273.58" + attribute \src "ls180.v:1340.5-1340.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1274.5-1274.58" + attribute \src "ls180.v:1341.5-1341.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1275.5-1275.59" + attribute \src "ls180.v:1342.5-1342.59" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1276.11-1276.65" + attribute \src "ls180.v:1343.11-1343.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1277.11-1277.65" + attribute \src "ls180.v:1344.11-1344.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1278.5-1278.60" + attribute \src "ls180.v:1345.5-1345.60" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1268.5-1268.50" + attribute \src "ls180.v:1335.5-1335.50" wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1257.5-1257.51" + attribute \src "ls180.v:1324.5-1324.51" wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1258.5-1258.52" + attribute \src "ls180.v:1325.5-1325.52" wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4589.1-4622.4" wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1150.5-1150.40" + attribute \src "ls180.v:1217.5-1217.40" wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4589.1-4622.4" wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3259.1-3266.4" + attribute \src "ls180.v:3364.1-3371.4" wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:490.5-490.64" + attribute \src "ls180.v:539.5-539.64" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:473.5-473.67" + attribute \src "ls180.v:522.5-522.67" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:474.5-474.66" + attribute \src "ls180.v:523.5-523.66" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3281.1-3288.4" + attribute \src "ls180.v:3386.1-3393.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3248.1-3255.4" + attribute \src "ls180.v:3353.1-3360.4" wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3946.1-3954.4" + attribute \src "ls180.v:4051.1-4059.4" wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:532.32-532.76" + attribute \src "ls180.v:581.32-581.76" wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:530.32-530.75" + attribute \src "ls180.v:579.32-579.75" wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3416.1-3423.4" + attribute \src "ls180.v:3521.1-3528.4" wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:572.5-572.64" + attribute \src "ls180.v:621.5-621.64" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:555.5-555.67" + attribute \src "ls180.v:604.5-604.67" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:556.5-556.66" + attribute \src "ls180.v:605.5-605.66" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3438.1-3445.4" + attribute \src "ls180.v:3543.1-3550.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3405.1-3412.4" + attribute \src "ls180.v:3510.1-3517.4" wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3955.1-3963.4" + attribute \src "ls180.v:4060.1-4068.4" wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:614.32-614.76" + attribute \src "ls180.v:663.32-663.76" wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:612.32-612.75" + attribute \src "ls180.v:661.32-661.75" wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3573.1-3580.4" + attribute \src "ls180.v:3678.1-3685.4" wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:654.5-654.64" + attribute \src "ls180.v:703.5-703.64" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:637.5-637.67" + attribute \src "ls180.v:686.5-686.67" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:638.5-638.66" + attribute \src "ls180.v:687.5-687.66" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3595.1-3602.4" + attribute \src "ls180.v:3700.1-3707.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3562.1-3569.4" + attribute \src "ls180.v:3667.1-3674.4" wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3964.1-3972.4" + attribute \src "ls180.v:4069.1-4077.4" wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:696.32-696.76" + attribute \src "ls180.v:745.32-745.76" wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:694.32-694.75" + attribute \src "ls180.v:743.32-743.75" wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3730.1-3737.4" + attribute \src "ls180.v:3835.1-3842.4" wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:736.5-736.64" + attribute \src "ls180.v:785.5-785.64" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:719.5-719.67" + attribute \src "ls180.v:768.5-768.67" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:720.5-720.66" + attribute \src "ls180.v:769.5-769.66" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3752.1-3759.4" + attribute \src "ls180.v:3857.1-3864.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3719.1-3726.4" + attribute \src "ls180.v:3824.1-3831.4" wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3973.1-3981.4" + attribute \src "ls180.v:4078.1-4086.4" wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:778.32-778.76" + attribute \src "ls180.v:827.32-827.76" wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:776.32-776.75" + attribute \src "ls180.v:825.32-825.75" wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3895.1-3900.4" + attribute \src "ls180.v:4000.1-4005.4" wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3901.1-3906.4" + attribute \src "ls180.v:4006.1-4011.4" wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3907.1-3912.4" + attribute \src "ls180.v:4012.1-4017.4" wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:786.5-786.43" + attribute \src "ls180.v:835.5-835.43" wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3881.1-3887.4" + attribute \src "ls180.v:3986.1-3992.4" wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:784.5-784.48" + attribute \src "ls180.v:833.5-833.48" wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:783.5-783.43" + attribute \src "ls180.v:832.5-832.43" wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:781.5-781.44" + attribute \src "ls180.v:830.5-830.44" wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:782.5-782.45" + attribute \src "ls180.v:831.5-831.45" wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3928.1-3933.4" + attribute \src "ls180.v:4033.1-4038.4" wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3934.1-3939.4" + attribute \src "ls180.v:4039.1-4044.4" wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3940.1-3945.4" + attribute \src "ls180.v:4045.1-4050.4" wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3914.1-3920.4" + attribute \src "ls180.v:4019.1-4025.4" wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3203.1-3233.4" + attribute \src "ls180.v:3308.1-3338.4" wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:434.5-434.42" + attribute \src "ls180.v:483.5-483.42" wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:435.5-435.43" + attribute \src "ls180.v:484.5-484.43" wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3203.1-3233.4" + attribute \src "ls180.v:3308.1-3338.4" wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:370.5-370.38" + attribute \src "ls180.v:419.5-419.38" wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:419.5-419.35" + attribute \src "ls180.v:468.5-468.35" wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4082.1-4095.4" + attribute \src "ls180.v:4187.1-4200.4" wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4082.1-4095.4" + attribute \src "ls180.v:4187.1-4200.4" wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:320.5-320.36" + attribute \src "ls180.v:369.5-369.36" wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3144.1-3160.4" + attribute \src "ls180.v:3249.1-3265.4" wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3144.1-3160.4" + attribute \src "ls180.v:3249.1-3265.4" wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3144.1-3160.4" + attribute \src "ls180.v:3249.1-3265.4" wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3144.1-3160.4" + attribute \src "ls180.v:3249.1-3265.4" wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:817.12-817.36" + attribute \src "ls180.v:866.12-866.36" wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:818.11-818.35" + attribute \src "ls180.v:867.11-867.35" wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3203.1-3233.4" + attribute \src "ls180.v:3308.1-3338.4" wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:820.5-820.31" + attribute \src "ls180.v:869.5-869.31" wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:821.5-821.31" + attribute \src "ls180.v:870.5-870.31" wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4091.1-4163.4" wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:825.32-825.63" + attribute \src "ls180.v:874.32-874.63" wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:823.32-823.63" + attribute \src "ls180.v:872.32-872.63" wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:3026.1-3072.4" + wire $0\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:921.5-921.54" + wire $0\main_socbushandler_converted_interface_err[0:0] + attribute \src "ls180.v:7705.1-10349.4" + wire $0\main_socbushandler_counter[0:0] + attribute \src "ls180.v:3026.1-3072.4" + wire $0\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:3026.1-3072.4" + wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7705.1-10349.4" + wire width 64 $0\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:3026.1-3072.4" + wire $0\main_socbushandler_skip[0:0] + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4420.1-4468.4" wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1041.12-1041.47" + attribute \src "ls180.v:1108.12-1108.47" wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6383.1-6388.4" + attribute \src "ls180.v:6556.1-6561.4" wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6429.1-6434.4" + attribute \src "ls180.v:6602.1-6607.4" wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:3021.1-3027.4" - wire width 4 $0\main_sram0_we[3:0] - attribute \src "ls180.v:3031.1-3037.4" - wire width 4 $0\main_sram1_we[3:0] - attribute \src "ls180.v:3041.1-3047.4" - wire width 4 $0\main_sram2_we[3:0] - attribute \src "ls180.v:4222.1-4226.4" + attribute \src "ls180.v:3100.1-3110.4" + wire width 8 $0\main_sram0_we[7:0] + attribute \src "ls180.v:3114.1-3124.4" + wire width 8 $0\main_sram1_we[7:0] + attribute \src "ls180.v:3128.1-3138.4" + wire width 8 $0\main_sram2_we[7:0] + attribute \src "ls180.v:3142.1-3152.4" + wire width 8 $0\main_sram3_we[7:0] + attribute \src "ls180.v:4327.1-4331.4" wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4211.1-4215.4" + attribute \src "ls180.v:4316.1-4320.4" wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:896.5-896.38" + attribute \src "ls180.v:957.5-957.38" wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:897.5-897.37" + attribute \src "ls180.v:958.5-958.37" wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:1023.5-1023.27" + attribute \src "ls180.v:1084.5-1084.27" wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4216.1-4221.4" + attribute \src "ls180.v:4321.1-4326.4" wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1005.5-1005.37" + attribute \src "ls180.v:1066.5-1066.37" wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4274.1-4281.4" + attribute \src "ls180.v:4379.1-4386.4" wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4205.1-4210.4" + attribute \src "ls180.v:4310.1-4315.4" wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:968.5-968.37" + attribute \src "ls180.v:1029.5-1029.37" wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:951.5-951.40" + attribute \src "ls180.v:1012.5-1012.40" wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:952.5-952.39" + attribute \src "ls180.v:1013.5-1013.39" wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4244.1-4251.4" + attribute \src "ls180.v:4349.1-4356.4" wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:864.5-864.29" - wire $0\main_wb_sdram_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:3026.1-3072.4" + wire width 30 $0\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:3026.1-3072.4" + wire $0\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:3014.1-3024.4" + wire width 32 $0\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:3026.1-3072.4" + wire width 4 $0\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:3026.1-3072.4" + wire $0\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:3026.1-3072.4" + wire $0\main_wb_sdram_we[0:0] + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0\memadr_1[6:0] - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0\memadr_2[6:0] - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0\memadr_3[6:0] - attribute \src "ls180.v:10240.1-10244.4" + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0\memadr[5:0] + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0\memadr_1[5:0] + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0\memadr_2[5:0] + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0\memadr_3[5:0] + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0\memadr_4[5:0] + attribute \src "ls180.v:10493.1-10497.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10254.1-10258.4" + attribute \src "ls180.v:10507.1-10511.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10268.1-10272.4" + attribute \src "ls180.v:10521.1-10525.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10282.1-10286.4" + attribute \src "ls180.v:10535.1-10539.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10297.1-10301.4" + attribute \src "ls180.v:10550.1-10554.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10303.1-10306.4" + attribute \src "ls180.v:10556.1-10559.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10314.1-10318.4" + attribute \src "ls180.v:10567.1-10571.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10320.1-10323.4" + attribute \src "ls180.v:10573.1-10576.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10330.1-10334.4" + attribute \src "ls180.v:10583.1-10587.4" wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10344.1-10348.4" + attribute \src "ls180.v:10597.1-10601.4" wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\uart_tx[0:0] - attribute \src "ls180.v:1790.11-1790.49" + attribute \src "ls180.v:1857.11-1857.49" wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1789.11-1789.44" + attribute \src "ls180.v:1856.11-1856.44" wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1792.11-1792.49" + attribute \src "ls180.v:1859.11-1859.49" wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1791.11-1791.44" + attribute \src "ls180.v:1858.11-1858.44" wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1794.11-1794.49" + attribute \src "ls180.v:1861.11-1861.49" wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1793.11-1793.44" + attribute \src "ls180.v:1860.11-1860.44" wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1796.11-1796.49" + attribute \src "ls180.v:1863.11-1863.49" wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1795.11-1795.44" + attribute \src "ls180.v:1862.11-1862.44" wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2641.5-2641.41" + attribute \src "ls180.v:2716.5-2716.41" wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2654.5-2654.42" + attribute \src "ls180.v:2729.5-2729.42" wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2655.5-2655.42" + attribute \src "ls180.v:2730.5-2730.42" wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2659.12-2659.50" + attribute \src "ls180.v:2734.12-2734.50" wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2660.5-2660.42" + attribute \src "ls180.v:2735.5-2735.42" wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2661.5-2661.42" + attribute \src "ls180.v:2736.5-2736.42" wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2662.12-2662.50" + attribute \src "ls180.v:2737.12-2737.50" wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2663.5-2663.42" + attribute \src "ls180.v:2738.5-2738.42" wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2664.5-2664.42" + attribute \src "ls180.v:2739.5-2739.42" wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2665.12-2665.50" + attribute \src "ls180.v:2740.12-2740.50" wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2666.5-2666.42" + attribute \src "ls180.v:2741.5-2741.42" wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2642.12-2642.49" + attribute \src "ls180.v:2717.12-2717.49" wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2667.5-2667.42" + attribute \src "ls180.v:2742.5-2742.42" wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2668.12-2668.50" + attribute \src "ls180.v:2743.12-2743.50" wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2669.5-2669.42" + attribute \src "ls180.v:2744.5-2744.42" wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2670.5-2670.42" + attribute \src "ls180.v:2745.5-2745.42" wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2671.12-2671.50" + attribute \src "ls180.v:2746.12-2746.50" wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2672.12-2672.50" - wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:2673.11-2673.48" - wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:2674.5-2674.42" + attribute \src "ls180.v:2747.12-2747.50" + wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:2748.11-2748.48" + wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:2749.5-2749.42" wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2675.5-2675.42" + attribute \src "ls180.v:2750.5-2750.42" wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2676.5-2676.42" + attribute \src "ls180.v:2751.5-2751.42" wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2643.11-2643.47" + attribute \src "ls180.v:2718.11-2718.47" wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2677.11-2677.48" + attribute \src "ls180.v:2752.11-2752.48" wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2678.11-2678.48" + attribute \src "ls180.v:2753.11-2753.48" wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2644.5-2644.41" + attribute \src "ls180.v:2719.5-2719.41" wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2645.5-2645.41" + attribute \src "ls180.v:2720.5-2720.41" wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2646.5-2646.41" + attribute \src "ls180.v:2721.5-2721.41" wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2650.5-2650.41" + attribute \src "ls180.v:2725.5-2725.41" wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2651.12-2651.49" + attribute \src "ls180.v:2726.12-2726.49" wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2652.11-2652.47" + attribute \src "ls180.v:2727.11-2727.47" wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2653.5-2653.41" + attribute \src "ls180.v:2728.5-2728.41" wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2647.5-2647.39" + attribute \src "ls180.v:2722.5-2722.39" wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2648.5-2648.39" + attribute \src "ls180.v:2723.5-2723.39" wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2649.5-2649.39" + attribute \src "ls180.v:2724.5-2724.39" wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2656.5-2656.39" + attribute \src "ls180.v:2731.5-2731.39" wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2657.5-2657.39" + attribute \src "ls180.v:2732.5-2732.39" wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2658.5-2658.39" + attribute \src "ls180.v:2733.5-2733.39" wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1776.5-1776.41" + attribute \src "ls180.v:1843.5-1843.41" wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1775.5-1775.36" + attribute \src "ls180.v:1842.5-1842.36" wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1780.5-1780.41" + attribute \src "ls180.v:1847.5-1847.41" wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1779.5-1779.36" + attribute \src "ls180.v:1846.5-1846.36" wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1784.5-1784.41" + attribute \src "ls180.v:1851.5-1851.41" wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1783.5-1783.36" + attribute \src "ls180.v:1850.5-1850.36" wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1821.5-1821.40" + attribute \src "ls180.v:1888.5-1888.40" wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1820.5-1820.35" + attribute \src "ls180.v:1887.5-1887.35" wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1941.12-1941.39" + attribute \src "ls180.v:2016.12-2016.39" wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1938.5-1938.25" + attribute \src "ls180.v:2013.5-2013.25" wire $1\builder_error[0:0] - attribute \src "ls180.v:1935.11-1935.31" + attribute \src "ls180.v:2010.11-2010.31" wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:1945.11-1945.51" + attribute \src "ls180.v:2020.11-2020.51" wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2447.11-2447.52" + attribute \src "ls180.v:2522.11-2522.52" wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2480.11-2480.52" + attribute \src "ls180.v:2555.11-2555.52" wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2521.11-2521.52" + attribute \src "ls180.v:2596.11-2596.52" wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2586.11-2586.52" + attribute \src "ls180.v:2661.11-2661.52" wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2611.11-2611.52" + attribute \src "ls180.v:2686.11-2686.52" wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1986.11-1986.51" + attribute \src "ls180.v:2061.11-2061.51" wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2015.11-2015.51" + attribute \src "ls180.v:2090.11-2090.51" wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2028.11-2028.51" + attribute \src "ls180.v:2103.11-2103.51" wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2069.11-2069.51" + attribute \src "ls180.v:2144.11-2144.51" wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2110.11-2110.51" + attribute \src "ls180.v:2185.11-2185.51" wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2175.11-2175.51" + attribute \src "ls180.v:2250.11-2250.51" wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2308.11-2308.51" + attribute \src "ls180.v:2383.11-2383.51" wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2389.11-2389.51" + attribute \src "ls180.v:2464.11-2464.51" wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2406.11-2406.51" + attribute \src "ls180.v:2481.11-2481.51" wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1908.12-1908.43" + attribute \src "ls180.v:1975.12-1975.43" wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2637.12-2637.55" + attribute \src "ls180.v:2712.12-2712.55" wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2638.5-2638.50" + attribute \src "ls180.v:2713.5-2713.50" wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1910.11-1910.43" + attribute \src "ls180.v:1977.11-1977.43" wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2635.11-2635.55" + attribute \src "ls180.v:2710.11-2710.55" wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2636.5-2636.52" + attribute \src "ls180.v:2711.5-2711.52" wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1909.5-1909.34" + attribute \src "ls180.v:1976.5-1976.34" wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2639.5-2639.46" + attribute \src "ls180.v:2714.5-2714.46" wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2640.5-2640.49" + attribute \src "ls180.v:2715.5-2715.49" wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1918.5-1918.44" + attribute \src "ls180.v:1985.5-1985.44" wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1914.12-1914.54" + attribute \src "ls180.v:1981.12-1981.54" wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1798.11-1798.48" + attribute \src "ls180.v:1865.11-1865.48" wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1797.11-1797.43" + attribute \src "ls180.v:1864.11-1864.43" wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2744.32-2744.66" + attribute \src "ls180.v:2819.32-2819.66" wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2745.32-2745.66" + attribute \src "ls180.v:2820.32-2820.66" wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2764.32-2764.67" + attribute \src "ls180.v:2839.32-2839.67" wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2765.32-2765.67" + attribute \src "ls180.v:2840.32-2840.67" wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2766.32-2766.67" + attribute \src "ls180.v:2841.32-2841.67" wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2767.32-2767.67" + attribute \src "ls180.v:2842.32-2842.67" wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2768.32-2768.67" + attribute \src "ls180.v:2843.32-2843.67" wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2769.32-2769.67" + attribute \src "ls180.v:2844.32-2844.67" wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2770.32-2770.67" + attribute \src "ls180.v:2845.32-2845.67" wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2771.32-2771.67" + attribute \src "ls180.v:2846.32-2846.67" wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2772.32-2772.67" + attribute \src "ls180.v:2847.32-2847.67" wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2773.32-2773.67" + attribute \src "ls180.v:2848.32-2848.67" wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2774.32-2774.67" + attribute \src "ls180.v:2849.32-2849.67" wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2775.32-2775.67" + attribute \src "ls180.v:2850.32-2850.67" wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2776.32-2776.67" + attribute \src "ls180.v:2851.32-2851.67" wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2777.32-2777.67" + attribute \src "ls180.v:2852.32-2852.67" wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2746.32-2746.66" + attribute \src "ls180.v:2821.32-2821.66" wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2747.32-2747.66" + attribute \src "ls180.v:2822.32-2822.66" wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2748.32-2748.66" + attribute \src "ls180.v:2823.32-2823.66" wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2749.32-2749.66" + attribute \src "ls180.v:2824.32-2824.66" wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2750.32-2750.66" + attribute \src "ls180.v:2825.32-2825.66" wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2751.32-2751.66" + attribute \src "ls180.v:2826.32-2826.66" wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2752.32-2752.66" + attribute \src "ls180.v:2827.32-2827.66" wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2753.32-2753.66" + attribute \src "ls180.v:2828.32-2828.66" wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2754.32-2754.66" + attribute \src "ls180.v:2829.32-2829.66" wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2755.32-2755.66" + attribute \src "ls180.v:2830.32-2830.66" wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2756.32-2756.66" + attribute \src "ls180.v:2831.32-2831.66" wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2757.32-2757.66" + attribute \src "ls180.v:2832.32-2832.66" wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2758.32-2758.66" + attribute \src "ls180.v:2833.32-2833.66" wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2759.32-2759.66" + attribute \src "ls180.v:2834.32-2834.66" wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2760.32-2760.66" + attribute \src "ls180.v:2835.32-2835.66" wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2761.32-2761.66" + attribute \src "ls180.v:2836.32-2836.66" wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2762.32-2762.66" + attribute \src "ls180.v:2837.32-2837.66" wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2763.32-2763.66" + attribute \src "ls180.v:2838.32-2838.66" wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1816.5-1816.43" + attribute \src "ls180.v:1883.5-1883.43" wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1817.5-1817.43" + attribute \src "ls180.v:1884.5-1884.43" wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1818.5-1818.43" + attribute \src "ls180.v:1885.5-1885.43" wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1819.5-1819.43" + attribute \src "ls180.v:1886.5-1886.43" wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1815.5-1815.42" + attribute \src "ls180.v:1882.5-1882.42" wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2634.11-2634.36" + attribute \src "ls180.v:2709.11-2709.36" wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1788.11-1788.46" + attribute \src "ls180.v:1855.11-1855.46" wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1787.11-1787.41" + attribute \src "ls180.v:1854.11-1854.41" wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1897.11-1897.51" + attribute \src "ls180.v:1964.11-1964.51" wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1896.11-1896.46" + attribute \src "ls180.v:1963.11-1963.46" wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1865.5-1865.57" + attribute \src "ls180.v:1932.5-1932.57" wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1864.5-1864.52" + attribute \src "ls180.v:1931.5-1931.52" wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1877.11-1877.47" + attribute \src "ls180.v:1944.11-1944.47" wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1876.11-1876.42" + attribute \src "ls180.v:1943.11-1943.42" wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1901.5-1901.49" + attribute \src "ls180.v:1968.5-1968.49" wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1900.5-1900.44" + attribute \src "ls180.v:1967.5-1967.44" wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1905.11-1905.65" + attribute \src "ls180.v:1972.11-1972.65" wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1904.11-1904.60" + attribute \src "ls180.v:1971.11-1971.60" wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1853.11-1853.46" + attribute \src "ls180.v:1920.11-1920.46" wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1852.11-1852.41" + attribute \src "ls180.v:1919.11-1919.41" wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1841.11-1841.52" + attribute \src "ls180.v:1908.11-1908.52" wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1840.11-1840.47" + attribute \src "ls180.v:1907.11-1907.47" wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1837.11-1837.52" + attribute \src "ls180.v:1904.11-1904.52" wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1836.11-1836.47" + attribute \src "ls180.v:1903.11-1903.47" wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1849.5-1849.46" + attribute \src "ls180.v:1916.5-1916.46" wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1848.5-1848.41" + attribute \src "ls180.v:1915.5-1915.41" wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1857.11-1857.53" + attribute \src "ls180.v:1924.11-1924.53" wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1856.11-1856.48" + attribute \src "ls180.v:1923.11-1923.48" wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1833.5-1833.46" + attribute \src "ls180.v:1900.5-1900.46" wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1832.5-1832.41" + attribute \src "ls180.v:1899.5-1899.41" wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1929.5-1929.30" + attribute \src "ls180.v:2004.5-2004.30" wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1925.12-1925.40" + attribute \src "ls180.v:2000.12-2000.40" wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1936.11-1936.35" - wire width 8 $1\builder_slave_sel[7:0] - attribute \src "ls180.v:1937.11-1937.37" - wire width 8 $1\builder_slave_sel_r[7:0] - attribute \src "ls180.v:1825.11-1825.47" + attribute \src "ls180.v:2011.12-2011.37" + wire width 13 $1\builder_slave_sel[12:0] + attribute \src "ls180.v:2012.12-2012.39" + wire width 13 $1\builder_slave_sel_r[12:0] + attribute \src "ls180.v:1892.11-1892.47" wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1824.11-1824.42" + attribute \src "ls180.v:1891.11-1891.42" wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1829.11-1829.47" + attribute \src "ls180.v:1896.11-1896.47" wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1828.11-1828.42" + attribute \src "ls180.v:1895.11-1895.42" wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2633.11-2633.31" + attribute \src "ls180.v:2708.11-2708.31" wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2686.5-2686.39" + attribute \src "ls180.v:2761.5-2761.39" wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2687.5-2687.39" + attribute \src "ls180.v:2762.5-2762.39" wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2679.11-2679.47" + attribute \src "ls180.v:2754.11-2754.47" wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2680.12-2680.49" + attribute \src "ls180.v:2755.12-2755.49" wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2681.5-2681.41" + attribute \src "ls180.v:2756.5-2756.41" wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2682.5-2682.41" + attribute \src "ls180.v:2757.5-2757.41" wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2683.5-2683.41" + attribute \src "ls180.v:2758.5-2758.41" wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2684.5-2684.41" + attribute \src "ls180.v:2759.5-2759.41" wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2685.5-2685.41" + attribute \src "ls180.v:2760.5-2760.41" wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:877.5-877.29" + attribute \src "ls180.v:938.5-938.29" wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:874.5-874.34" + attribute \src "ls180.v:321.5-321.35" + wire $1\main_converter0_counter[0:0] + attribute \src "ls180.v:1844.5-1844.57" + wire $1\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1845.5-1845.60" + wire $1\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:323.12-323.41" + wire width 64 $1\main_converter0_dat_r[63:0] + attribute \src "ls180.v:320.5-320.32" + wire $1\main_converter0_skip[0:0] + attribute \src "ls180.v:336.5-336.35" + wire $1\main_converter1_counter[0:0] + attribute \src "ls180.v:1848.5-1848.57" + wire $1\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1849.5-1849.60" + wire $1\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:338.12-338.41" + wire width 64 $1\main_converter1_dat_r[63:0] + attribute \src "ls180.v:335.5-335.32" + wire $1\main_converter1_skip[0:0] + attribute \src "ls180.v:935.5-935.34" wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1822.5-1822.55" + attribute \src "ls180.v:1889.5-1889.55" wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1823.5-1823.58" + attribute \src "ls180.v:1890.5-1890.58" wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:876.12-876.40" + attribute \src "ls180.v:937.12-937.40" wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:873.5-873.31" + attribute \src "ls180.v:934.5-934.31" wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:308.12-308.38" + attribute \src "ls180.v:357.12-357.38" wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:309.5-309.36" + attribute \src "ls180.v:358.5-358.36" wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1108.12-1108.30" + attribute \src "ls180.v:1175.12-1175.30" wire width 24 $1\main_dummy[23:0] - attribute \src "ls180.v:1025.5-1025.27" - wire $1\main_gpio_oe_re[0:0] - attribute \src "ls180.v:1024.12-1024.40" - wire width 16 $1\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:1029.5-1029.28" - wire $1\main_gpio_out_re[0:0] - attribute \src "ls180.v:1028.12-1028.41" - wire width 16 $1\main_gpio_out_storage[15:0] - attribute \src "ls180.v:1026.12-1026.36" - wire width 16 $1\main_gpio_status[15:0] - attribute \src "ls180.v:1133.5-1133.23" + attribute \src "ls180.v:1086.12-1086.49" + wire width 16 $1\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:1092.5-1092.40" + wire $1\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:1091.12-1091.53" + wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:1096.5-1096.41" + wire $1\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:1095.12-1095.54" + wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:1093.12-1093.49" + wire width 16 $1\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:1200.5-1200.23" wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1132.11-1132.34" + attribute \src "ls180.v:1199.11-1199.34" wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:293.5-293.24" + attribute \src "ls180.v:342.5-342.24" wire $1\main_int_rst[0:0] - attribute \src "ls180.v:251.5-251.39" + attribute \src "ls180.v:315.5-315.51" + wire $1\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:255.5-255.39" wire $1\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:1681.12-1681.43" + attribute \src "ls180.v:1748.12-1748.43" wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1685.5-1685.35" + attribute \src "ls180.v:1752.5-1752.35" wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1684.11-1684.41" - wire width 4 $1\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:1686.5-1686.35" + attribute \src "ls180.v:1751.11-1751.41" + wire width 8 $1\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:1753.5-1753.35" wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1688.5-1688.34" + attribute \src "ls180.v:1755.5-1755.34" wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:266.5-266.39" + attribute \src "ls180.v:330.5-330.51" + wire $1\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:270.5-270.39" wire $1\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:281.5-281.39" + attribute \src "ls180.v:285.5-285.39" wire $1\main_interface2_ram_bus_ack[0:0] + attribute \src "ls180.v:300.5-300.39" + wire $1\main_interface3_ram_bus_ack[0:0] attribute \src "ls180.v:63.12-63.47" wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:170.5-170.47" - wire $1\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1777.5-1777.69" - wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1778.5-1778.72" - wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:172.12-172.53" - wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:169.5-169.44" - wire $1\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:185.5-185.47" - wire $1\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1781.5-1781.69" - wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1782.5-1782.72" - wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:187.12-187.53" - wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:184.5-184.44" - wire $1\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:200.5-200.47" - wire $1\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1785.5-1785.69" - wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1786.5-1786.72" - wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:202.12-202.53" - wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:199.5-199.44" - wire $1\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:223.5-223.34" + attribute \src "ls180.v:227.5-227.34" wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:222.5-222.39" + attribute \src "ls180.v:226.5-226.39" wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:243.5-243.44" + attribute \src "ls180.v:247.5-247.44" wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:242.5-242.49" + attribute \src "ls180.v:246.5-246.49" wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:158.12-158.71" - wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:162.5-162.63" - wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:159.12-159.73" - wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:161.11-161.69" - wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:163.5-163.63" - wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:165.5-165.62" - wire $1\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:173.12-173.71" - wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:177.5-177.63" - wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:174.12-174.73" - wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:176.11-176.69" - wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:178.5-178.63" - wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:180.5-180.62" - wire $1\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:188.12-188.71" - wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:192.5-192.63" - wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:189.12-189.73" - wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:191.11-191.69" - wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:193.5-193.63" - wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:195.5-195.62" - wire $1\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:72.5-72.46" - wire $1\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:81.5-81.46" - wire $1\main_libresocsim_libresoc_ibus_ack[0:0] attribute \src "ls180.v:65.12-65.55" wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:112.5-112.49" - wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:219.5-219.36" + attribute \src "ls180.v:88.12-88.58" + wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:92.5-92.50" + wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:89.12-89.60" + wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:91.11-91.56" + wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:93.5-93.50" + wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:95.5-95.49" + wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:97.12-97.58" + wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:101.5-101.50" + wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:98.12-98.60" + wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:100.11-100.56" + wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:102.5-102.50" + wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:104.5-104.49" + wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:223.5-223.36" wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:218.12-218.49" + attribute \src "ls180.v:222.12-222.49" wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:209.5-209.40" + attribute \src "ls180.v:213.5-213.40" wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:221.5-221.38" + attribute \src "ls180.v:225.5-225.38" wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:220.12-220.51" + attribute \src "ls180.v:224.12-224.51" wire width 32 $1\main_libresocsim_reload_storage[31:0] attribute \src "ls180.v:56.5-56.37" wire $1\main_libresocsim_reset_re[0:0] @@ -223313,8358 +239334,8756 @@ module \ls180 wire $1\main_libresocsim_scratch_re[0:0] attribute \src "ls180.v:57.12-57.60" wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:225.5-225.44" + attribute \src "ls180.v:229.5-229.44" wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:224.5-224.49" + attribute \src "ls180.v:228.5-228.49" wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:244.12-244.42" + attribute \src "ls180.v:248.12-248.42" wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:226.12-226.49" + attribute \src "ls180.v:230.12-230.49" wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:216.11-216.37" - wire width 4 $1\main_libresocsim_we[3:0] - attribute \src "ls180.v:232.5-232.39" + attribute \src "ls180.v:220.11-220.37" + wire width 8 $1\main_libresocsim_we[7:0] + attribute \src "ls180.v:236.5-236.39" wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:233.5-233.45" + attribute \src "ls180.v:237.5-237.45" wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:230.5-230.41" + attribute \src "ls180.v:234.5-234.41" wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:865.12-865.40" + attribute \src "ls180.v:926.12-926.40" wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:869.5-869.32" + attribute \src "ls180.v:930.5-930.32" wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:866.12-866.42" + attribute \src "ls180.v:927.12-927.42" wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:868.11-868.38" + attribute \src "ls180.v:929.11-929.38" wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:870.5-870.32" + attribute \src "ls180.v:931.5-931.32" wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:872.5-872.31" + attribute \src "ls180.v:933.5-933.31" wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1112.12-1112.37" + attribute \src "ls180.v:1179.12-1179.37" wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1114.5-1114.31" + attribute \src "ls180.v:1181.5-1181.31" wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1113.5-1113.36" + attribute \src "ls180.v:1180.5-1180.36" wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1118.5-1118.31" + attribute \src "ls180.v:1185.5-1185.31" wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1117.12-1117.44" + attribute \src "ls180.v:1184.12-1184.44" wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1116.5-1116.30" + attribute \src "ls180.v:1183.5-1183.30" wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1115.12-1115.43" + attribute \src "ls180.v:1182.12-1182.43" wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1122.12-1122.37" + attribute \src "ls180.v:1189.12-1189.37" wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1124.5-1124.31" + attribute \src "ls180.v:1191.5-1191.31" wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1123.5-1123.36" + attribute \src "ls180.v:1190.5-1190.36" wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1128.5-1128.31" + attribute \src "ls180.v:1195.5-1195.31" wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1127.12-1127.44" + attribute \src "ls180.v:1194.12-1194.44" wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1126.5-1126.30" + attribute \src "ls180.v:1193.5-1193.30" wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1125.12-1125.43" + attribute \src "ls180.v:1192.12-1192.43" wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:310.11-310.32" + attribute \src "ls180.v:359.11-359.32" wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1650.11-1650.50" - wire width 2 $1\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:1646.5-1646.51" + attribute \src "ls180.v:1717.11-1717.50" + wire width 3 $1\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:1713.5-1713.51" wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1647.5-1647.50" + attribute \src "ls180.v:1714.5-1714.50" wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1648.12-1648.66" - wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:1649.11-1649.77" - wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:1652.5-1652.49" + attribute \src "ls180.v:1715.12-1715.66" + wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:1716.11-1716.77" + wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1719.5-1719.49" wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1625.11-1625.47" + attribute \src "ls180.v:1692.11-1692.47" wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1622.11-1622.45" + attribute \src "ls180.v:1689.11-1689.45" wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1624.11-1624.47" + attribute \src "ls180.v:1691.11-1691.47" wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1626.11-1626.50" + attribute \src "ls180.v:1693.11-1693.50" wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1660.12-1660.62" + attribute \src "ls180.v:1727.12-1727.62" wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1661.12-1661.60" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:1658.5-1658.45" + attribute \src "ls180.v:1728.12-1728.60" + wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:1725.5-1725.45" wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1668.5-1668.54" + attribute \src "ls180.v:1735.5-1735.54" wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1667.12-1667.67" + attribute \src "ls180.v:1734.12-1734.67" wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1672.5-1672.56" + attribute \src "ls180.v:1739.5-1739.56" wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1671.5-1671.61" + attribute \src "ls180.v:1738.5-1738.61" wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1670.5-1670.56" + attribute \src "ls180.v:1737.5-1737.56" wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1669.12-1669.69" + attribute \src "ls180.v:1736.12-1736.69" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1676.5-1676.54" + attribute \src "ls180.v:1743.5-1743.54" wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1675.5-1675.59" + attribute \src "ls180.v:1742.5-1742.59" wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1678.12-1678.61" + attribute \src "ls180.v:1745.12-1745.61" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1898.12-1898.87" + attribute \src "ls180.v:1965.12-1965.87" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1899.5-1899.82" + attribute \src "ls180.v:1966.5-1966.82" wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1663.5-1663.57" + attribute \src "ls180.v:1730.5-1730.57" wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1673.5-1673.53" + attribute \src "ls180.v:1740.5-1740.53" wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1442.5-1442.38" + attribute \src "ls180.v:1509.5-1509.38" wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1441.12-1441.51" + attribute \src "ls180.v:1508.12-1508.51" wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1440.5-1440.39" + attribute \src "ls180.v:1507.5-1507.39" wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1439.11-1439.51" + attribute \src "ls180.v:1506.11-1506.51" wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1426.5-1426.39" + attribute \src "ls180.v:1493.5-1493.39" wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1425.12-1425.52" + attribute \src "ls180.v:1492.12-1492.52" wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1428.5-1428.38" + attribute \src "ls180.v:1495.5-1495.38" wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1427.12-1427.51" + attribute \src "ls180.v:1494.12-1494.51" wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1581.11-1581.39" + attribute \src "ls180.v:1648.11-1648.39" wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1882.11-1882.62" + attribute \src "ls180.v:1949.11-1949.62" wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1883.5-1883.59" + attribute \src "ls180.v:1950.5-1950.59" wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1582.5-1582.32" + attribute \src "ls180.v:1649.5-1649.32" wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1878.5-1878.55" + attribute \src "ls180.v:1945.5-1945.55" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1879.5-1879.58" + attribute \src "ls180.v:1946.5-1946.58" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1583.5-1583.33" + attribute \src "ls180.v:1650.5-1650.33" wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1886.5-1886.56" + attribute \src "ls180.v:1953.5-1953.56" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1887.5-1887.59" + attribute \src "ls180.v:1954.5-1954.59" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1433.13-1433.53" + attribute \src "ls180.v:1500.13-1500.53" wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1894.13-1894.76" + attribute \src "ls180.v:1961.13-1961.76" wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1895.5-1895.69" + attribute \src "ls180.v:1962.5-1962.69" wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1584.5-1584.35" + attribute \src "ls180.v:1651.5-1651.35" wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1888.5-1888.58" + attribute \src "ls180.v:1955.5-1955.58" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1889.5-1889.61" + attribute \src "ls180.v:1956.5-1956.61" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1542.11-1542.47" + attribute \src "ls180.v:1609.11-1609.47" wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1548.5-1548.46" + attribute \src "ls180.v:1615.5-1615.46" wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1547.12-1547.54" + attribute \src "ls180.v:1614.12-1614.54" wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1543.12-1543.58" + attribute \src "ls180.v:1610.12-1610.58" wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1555.5-1555.46" + attribute \src "ls180.v:1622.5-1622.46" wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1554.12-1554.54" + attribute \src "ls180.v:1621.12-1621.54" wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1550.12-1550.58" + attribute \src "ls180.v:1617.12-1617.58" wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1562.5-1562.46" + attribute \src "ls180.v:1629.5-1629.46" wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1561.12-1561.54" + attribute \src "ls180.v:1628.12-1628.54" wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1557.12-1557.58" + attribute \src "ls180.v:1624.12-1624.58" wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1569.5-1569.46" + attribute \src "ls180.v:1636.5-1636.46" wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1568.12-1568.54" + attribute \src "ls180.v:1635.12-1635.54" wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1564.12-1564.58" + attribute \src "ls180.v:1631.12-1631.58" wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1571.12-1571.53" + attribute \src "ls180.v:1638.12-1638.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1572.12-1572.53" + attribute \src "ls180.v:1639.12-1639.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1573.12-1573.53" + attribute \src "ls180.v:1640.12-1640.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1574.12-1574.53" + attribute \src "ls180.v:1641.12-1641.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1576.12-1576.51" + attribute \src "ls180.v:1643.12-1643.51" wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1577.12-1577.51" + attribute \src "ls180.v:1644.12-1644.51" wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1578.12-1578.51" + attribute \src "ls180.v:1645.12-1645.51" wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1579.12-1579.51" + attribute \src "ls180.v:1646.12-1646.51" wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1533.5-1533.48" + attribute \src "ls180.v:1600.5-1600.48" wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1534.5-1534.47" + attribute \src "ls180.v:1601.5-1601.47" wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1535.11-1535.61" + attribute \src "ls180.v:1602.11-1602.61" wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1532.5-1532.48" + attribute \src "ls180.v:1599.5-1599.48" wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1531.5-1531.48" + attribute \src "ls180.v:1598.5-1598.48" wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1536.5-1536.50" + attribute \src "ls180.v:1603.5-1603.50" wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1541.11-1541.47" + attribute \src "ls180.v:1608.11-1608.47" wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1575.5-1575.43" + attribute \src "ls180.v:1642.5-1642.43" wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1498.11-1498.48" + attribute \src "ls180.v:1565.11-1565.48" wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1874.11-1874.87" + attribute \src "ls180.v:1941.11-1941.87" wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1875.5-1875.84" + attribute \src "ls180.v:1942.5-1942.84" wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1503.12-1503.55" + attribute \src "ls180.v:1570.12-1570.55" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1499.12-1499.59" + attribute \src "ls180.v:1566.12-1566.59" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1510.12-1510.55" + attribute \src "ls180.v:1577.12-1577.55" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1506.12-1506.59" + attribute \src "ls180.v:1573.12-1573.59" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1517.12-1517.55" + attribute \src "ls180.v:1584.12-1584.55" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1513.12-1513.59" + attribute \src "ls180.v:1580.12-1580.59" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1524.12-1524.55" + attribute \src "ls180.v:1591.12-1591.55" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1520.12-1520.59" + attribute \src "ls180.v:1587.12-1587.59" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1527.12-1527.54" + attribute \src "ls180.v:1594.12-1594.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1866.12-1866.93" + attribute \src "ls180.v:1933.12-1933.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1867.5-1867.88" + attribute \src "ls180.v:1934.5-1934.88" wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1528.12-1528.54" + attribute \src "ls180.v:1595.12-1595.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1868.12-1868.93" + attribute \src "ls180.v:1935.12-1935.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1869.5-1869.88" + attribute \src "ls180.v:1936.5-1936.88" wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1529.12-1529.54" + attribute \src "ls180.v:1596.12-1596.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1870.12-1870.93" + attribute \src "ls180.v:1937.12-1937.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1871.5-1871.88" + attribute \src "ls180.v:1938.5-1938.88" wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1530.12-1530.54" + attribute \src "ls180.v:1597.12-1597.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1872.12-1872.93" + attribute \src "ls180.v:1939.12-1939.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1873.5-1873.88" + attribute \src "ls180.v:1940.5-1940.88" wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1489.5-1489.49" + attribute \src "ls180.v:1556.5-1556.49" wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1496.5-1496.50" + attribute \src "ls180.v:1563.5-1563.50" wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1497.11-1497.64" + attribute \src "ls180.v:1564.11-1564.64" wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1494.5-1494.51" + attribute \src "ls180.v:1561.5-1561.51" wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1493.5-1493.51" + attribute \src "ls180.v:1560.5-1560.51" wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1485.11-1485.47" + attribute \src "ls180.v:1552.11-1552.47" wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1443.11-1443.51" + attribute \src "ls180.v:1510.11-1510.51" wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1586.12-1586.42" + attribute \src "ls180.v:1653.12-1653.42" wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1884.12-1884.65" + attribute \src "ls180.v:1951.12-1951.65" wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1885.5-1885.60" + attribute \src "ls180.v:1952.5-1952.60" wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1587.5-1587.33" + attribute \src "ls180.v:1654.5-1654.33" wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1880.5-1880.56" + attribute \src "ls180.v:1947.5-1947.56" wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1881.5-1881.59" + attribute \src "ls180.v:1948.5-1948.59" wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1588.5-1588.34" + attribute \src "ls180.v:1655.5-1655.34" wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1890.5-1890.57" + attribute \src "ls180.v:1957.5-1957.57" wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1891.5-1891.60" + attribute \src "ls180.v:1958.5-1958.60" wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1589.5-1589.36" + attribute \src "ls180.v:1656.5-1656.36" wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1892.5-1892.59" + attribute \src "ls180.v:1959.5-1959.59" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1893.5-1893.62" + attribute \src "ls180.v:1960.5-1960.62" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1734.11-1734.48" - wire width 2 $1\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:1732.11-1732.64" + attribute \src "ls180.v:1801.11-1801.48" + wire width 3 $1\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:1799.11-1799.64" wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1708.5-1708.40" + attribute \src "ls180.v:1775.5-1775.40" wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1707.12-1707.53" + attribute \src "ls180.v:1774.12-1774.53" wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1706.12-1706.45" - wire width 32 $1\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:1902.12-1902.75" - wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:1903.5-1903.70" + attribute \src "ls180.v:1773.12-1773.45" + wire width 64 $1\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:1969.12-1969.75" + wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:1970.5-1970.70" wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1713.5-1713.44" + attribute \src "ls180.v:1780.5-1780.44" wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1712.5-1712.42" + attribute \src "ls180.v:1779.5-1779.42" wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1711.5-1711.47" + attribute \src "ls180.v:1778.5-1778.47" wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1710.5-1710.42" + attribute \src "ls180.v:1777.5-1777.42" wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1709.12-1709.55" + attribute \src "ls180.v:1776.12-1776.55" wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1716.5-1716.40" + attribute \src "ls180.v:1783.5-1783.40" wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1715.5-1715.45" + attribute \src "ls180.v:1782.5-1782.45" wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1720.12-1720.47" + attribute \src "ls180.v:1787.12-1787.47" wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1906.12-1906.87" + attribute \src "ls180.v:1973.12-1973.87" wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1907.5-1907.82" + attribute \src "ls180.v:1974.5-1974.82" wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1699.5-1699.42" + attribute \src "ls180.v:1766.5-1766.42" wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1700.12-1700.61" + attribute \src "ls180.v:1767.12-1767.61" wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1698.5-1698.43" + attribute \src "ls180.v:1765.5-1765.43" wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1697.5-1697.43" + attribute \src "ls180.v:1764.5-1764.43" wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1704.5-1704.44" + attribute \src "ls180.v:1771.5-1771.44" wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1705.12-1705.60" - wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:1701.5-1701.45" + attribute \src "ls180.v:1772.12-1772.60" + wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:1768.5-1768.45" wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1761.11-1761.47" + attribute \src "ls180.v:1828.11-1828.47" wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1758.11-1758.45" + attribute \src "ls180.v:1825.11-1825.45" wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1760.11-1760.47" + attribute \src "ls180.v:1827.11-1827.47" wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1762.11-1762.50" + attribute \src "ls180.v:1829.11-1829.50" wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1142.5-1142.35" + attribute \src "ls180.v:1209.5-1209.35" wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1145.5-1145.35" + attribute \src "ls180.v:1212.5-1212.35" wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1146.5-1146.36" + attribute \src "ls180.v:1213.5-1213.36" wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1144.11-1144.41" + attribute \src "ls180.v:1211.11-1211.41" wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1140.5-1140.33" + attribute \src "ls180.v:1207.5-1207.33" wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1139.11-1139.46" + attribute \src "ls180.v:1206.11-1206.46" wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1248.5-1248.49" + attribute \src "ls180.v:1315.5-1315.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1249.5-1249.48" + attribute \src "ls180.v:1316.5-1316.48" wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1250.11-1250.62" + attribute \src "ls180.v:1317.11-1317.62" wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1246.5-1246.49" + attribute \src "ls180.v:1313.5-1313.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1233.11-1233.54" + attribute \src "ls180.v:1300.11-1300.54" wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1229.5-1229.55" + attribute \src "ls180.v:1296.5-1296.55" wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1230.5-1230.54" + attribute \src "ls180.v:1297.5-1297.54" wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1231.11-1231.68" + attribute \src "ls180.v:1298.11-1298.68" wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1232.11-1232.81" + attribute \src "ls180.v:1299.11-1299.81" wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1235.5-1235.53" + attribute \src "ls180.v:1302.5-1302.53" wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1251.5-1251.38" + attribute \src "ls180.v:1318.5-1318.38" wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1846.5-1846.66" + attribute \src "ls180.v:1913.5-1913.66" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1847.5-1847.69" + attribute \src "ls180.v:1914.5-1914.69" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1221.5-1221.36" + attribute \src "ls180.v:1288.5-1288.36" wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1216.5-1216.53" + attribute \src "ls180.v:1283.5-1283.53" wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1203.11-1203.39" + attribute \src "ls180.v:1270.11-1270.39" wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1842.11-1842.67" + attribute \src "ls180.v:1909.11-1909.67" wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1843.5-1843.64" + attribute \src "ls180.v:1910.5-1910.64" wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1188.5-1188.48" + attribute \src "ls180.v:1255.5-1255.48" wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1189.5-1189.50" + attribute \src "ls180.v:1256.5-1256.50" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1190.5-1190.51" + attribute \src "ls180.v:1257.5-1257.51" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1195.5-1195.37" + attribute \src "ls180.v:1262.5-1262.37" wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1196.11-1196.53" + attribute \src "ls180.v:1263.11-1263.53" wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1194.5-1194.38" + attribute \src "ls180.v:1261.5-1261.38" wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1193.5-1193.38" + attribute \src "ls180.v:1260.5-1260.38" wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1199.5-1199.39" + attribute \src "ls180.v:1266.5-1266.39" wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1200.11-1200.53" + attribute \src "ls180.v:1267.11-1267.53" wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1201.11-1201.55" + attribute \src "ls180.v:1268.11-1268.55" wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1198.5-1198.40" + attribute \src "ls180.v:1265.5-1265.40" wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1197.5-1197.40" + attribute \src "ls180.v:1264.5-1264.40" wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1202.12-1202.48" + attribute \src "ls180.v:1269.12-1269.48" wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1844.12-1844.71" + attribute \src "ls180.v:1911.12-1911.71" wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1845.5-1845.66" + attribute \src "ls180.v:1912.5-1912.66" wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1175.11-1175.39" + attribute \src "ls180.v:1242.11-1242.39" wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1838.11-1838.66" + attribute \src "ls180.v:1905.11-1905.66" wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1839.5-1839.63" + attribute \src "ls180.v:1906.5-1906.63" wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1174.5-1174.32" + attribute \src "ls180.v:1241.5-1241.32" wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1165.5-1165.48" + attribute \src "ls180.v:1232.5-1232.48" wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1166.5-1166.50" + attribute \src "ls180.v:1233.5-1233.50" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1167.5-1167.51" + attribute \src "ls180.v:1234.5-1234.51" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1172.5-1172.37" + attribute \src "ls180.v:1239.5-1239.37" wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1173.11-1173.51" + attribute \src "ls180.v:1240.11-1240.51" wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1171.5-1171.38" + attribute \src "ls180.v:1238.5-1238.38" wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1170.5-1170.38" + attribute \src "ls180.v:1237.5-1237.38" wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1359.11-1359.41" + attribute \src "ls180.v:1426.11-1426.41" wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1858.11-1858.70" + attribute \src "ls180.v:1925.11-1925.70" wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1859.5-1859.66" + attribute \src "ls180.v:1926.5-1926.66" wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1404.5-1404.51" + attribute \src "ls180.v:1471.5-1471.51" wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1405.5-1405.50" + attribute \src "ls180.v:1472.5-1472.50" wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1406.11-1406.64" + attribute \src "ls180.v:1473.11-1473.64" wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1402.5-1402.51" + attribute \src "ls180.v:1469.5-1469.51" wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1389.5-1389.50" + attribute \src "ls180.v:1456.5-1456.50" wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1385.5-1385.57" + attribute \src "ls180.v:1452.5-1452.57" wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1386.5-1386.56" + attribute \src "ls180.v:1453.5-1453.56" wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1387.11-1387.70" + attribute \src "ls180.v:1454.11-1454.70" wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1388.11-1388.83" + attribute \src "ls180.v:1455.11-1455.83" wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1391.5-1391.55" + attribute \src "ls180.v:1458.5-1458.55" wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1407.5-1407.40" + attribute \src "ls180.v:1474.5-1474.40" wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1862.5-1862.69" + attribute \src "ls180.v:1929.5-1929.69" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1863.5-1863.72" + attribute \src "ls180.v:1930.5-1930.72" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1377.5-1377.38" + attribute \src "ls180.v:1444.5-1444.38" wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1372.5-1372.55" + attribute \src "ls180.v:1439.5-1439.55" wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1342.5-1342.49" + attribute \src "ls180.v:1409.5-1409.49" wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1349.5-1349.38" + attribute \src "ls180.v:1416.5-1416.38" wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1350.11-1350.61" + attribute \src "ls180.v:1417.11-1417.61" wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1348.5-1348.39" + attribute \src "ls180.v:1415.5-1415.39" wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1347.5-1347.39" + attribute \src "ls180.v:1414.5-1414.39" wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1354.5-1354.40" + attribute \src "ls180.v:1421.5-1421.40" wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1355.11-1355.54" + attribute \src "ls180.v:1422.11-1422.54" wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1356.11-1356.56" + attribute \src "ls180.v:1423.11-1423.56" wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1352.5-1352.41" + attribute \src "ls180.v:1419.5-1419.41" wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1351.5-1351.41" + attribute \src "ls180.v:1418.5-1418.41" wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1357.5-1357.33" + attribute \src "ls180.v:1424.5-1424.33" wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1358.12-1358.49" + attribute \src "ls180.v:1425.12-1425.49" wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1860.12-1860.73" + attribute \src "ls180.v:1927.12-1927.73" wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1861.5-1861.68" + attribute \src "ls180.v:1928.5-1928.68" wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1267.11-1267.40" + attribute \src "ls180.v:1334.11-1334.40" wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1854.11-1854.61" + attribute \src "ls180.v:1921.11-1921.61" wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1855.5-1855.58" + attribute \src "ls180.v:1922.5-1922.58" wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1326.5-1326.50" + attribute \src "ls180.v:1393.5-1393.50" wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1327.5-1327.49" + attribute \src "ls180.v:1394.5-1394.49" wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1328.11-1328.63" + attribute \src "ls180.v:1395.11-1395.63" wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1324.5-1324.50" + attribute \src "ls180.v:1391.5-1391.50" wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1311.11-1311.55" + attribute \src "ls180.v:1378.11-1378.55" wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1307.5-1307.56" + attribute \src "ls180.v:1374.5-1374.56" wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1308.5-1308.55" + attribute \src "ls180.v:1375.5-1375.55" wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1309.11-1309.69" + attribute \src "ls180.v:1376.11-1376.69" wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1310.11-1310.82" + attribute \src "ls180.v:1377.11-1377.82" wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1313.5-1313.54" + attribute \src "ls180.v:1380.5-1380.54" wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1329.5-1329.39" + attribute \src "ls180.v:1396.5-1396.39" wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1850.5-1850.66" + attribute \src "ls180.v:1917.5-1917.66" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1851.5-1851.69" + attribute \src "ls180.v:1918.5-1918.69" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1299.5-1299.37" + attribute \src "ls180.v:1366.5-1366.37" wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1294.5-1294.54" + attribute \src "ls180.v:1361.5-1361.54" wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1281.5-1281.34" + attribute \src "ls180.v:1348.5-1348.34" wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1256.5-1256.49" + attribute \src "ls180.v:1323.5-1323.49" wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1259.11-1259.58" + attribute \src "ls180.v:1326.11-1326.58" wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1260.5-1260.53" + attribute \src "ls180.v:1327.5-1327.53" wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1263.5-1263.39" + attribute \src "ls180.v:1330.5-1330.39" wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1264.5-1264.38" + attribute \src "ls180.v:1331.5-1331.38" wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1265.11-1265.52" + attribute \src "ls180.v:1332.11-1332.52" wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1262.5-1262.39" + attribute \src "ls180.v:1329.5-1329.39" wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1261.5-1261.39" + attribute \src "ls180.v:1328.5-1328.39" wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1279.5-1279.34" + attribute \src "ls180.v:1346.5-1346.34" wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1266.5-1266.33" + attribute \src "ls180.v:1333.5-1333.33" wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1280.5-1280.34" + attribute \src "ls180.v:1347.5-1347.34" wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1160.11-1160.39" + attribute \src "ls180.v:1227.11-1227.39" wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1834.11-1834.66" + attribute \src "ls180.v:1901.11-1901.66" wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1835.5-1835.63" + attribute \src "ls180.v:1902.5-1902.63" wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1155.5-1155.48" + attribute \src "ls180.v:1222.5-1222.48" wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1156.5-1156.50" + attribute \src "ls180.v:1223.5-1223.50" wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1157.5-1157.51" + attribute \src "ls180.v:1224.5-1224.51" wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1158.11-1158.57" + attribute \src "ls180.v:1225.11-1225.57" wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1159.5-1159.52" + attribute \src "ls180.v:1226.5-1226.52" wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1409.5-1409.35" + attribute \src "ls180.v:1476.5-1476.35" wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1412.11-1412.42" + attribute \src "ls180.v:1479.11-1479.42" wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:372.5-372.33" + attribute \src "ls180.v:421.5-421.33" wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:371.12-371.46" + attribute \src "ls180.v:420.12-420.46" wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:374.5-374.34" + attribute \src "ls180.v:423.5-423.34" wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:373.11-373.45" + attribute \src "ls180.v:422.11-422.45" wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:470.5-470.50" + attribute \src "ls180.v:519.5-519.50" wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:492.11-492.70" + attribute \src "ls180.v:541.11-541.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:489.11-489.68" + attribute \src "ls180.v:538.11-538.68" wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:491.11-491.70" + attribute \src "ls180.v:540.11-540.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:493.11-493.73" + attribute \src "ls180.v:542.11-542.73" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:516.5-516.59" + attribute \src "ls180.v:565.5-565.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:517.5-517.58" + attribute \src "ls180.v:566.5-566.58" wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:519.12-519.74" + attribute \src "ls180.v:568.12-568.74" wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:518.5-518.64" + attribute \src "ls180.v:567.5-567.64" wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:514.5-514.59" + attribute \src "ls180.v:563.5-563.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:462.12-462.57" + attribute \src "ls180.v:511.12-511.57" wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:464.5-464.51" + attribute \src "ls180.v:513.5-513.51" wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:467.5-467.54" + attribute \src "ls180.v:516.5-516.54" wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:468.5-468.55" + attribute \src "ls180.v:517.5-517.55" wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:469.5-469.56" + attribute \src "ls180.v:518.5-518.56" wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:465.5-465.51" + attribute \src "ls180.v:514.5-514.51" wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:466.5-466.50" + attribute \src "ls180.v:515.5-515.50" wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:461.5-461.45" + attribute \src "ls180.v:510.5-510.45" wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:460.5-460.45" + attribute \src "ls180.v:509.5-509.45" wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:459.5-459.47" + attribute \src "ls180.v:508.5-508.47" wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:457.5-457.51" + attribute \src "ls180.v:506.5-506.51" wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:456.5-456.51" + attribute \src "ls180.v:505.5-505.51" wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:520.12-520.47" + attribute \src "ls180.v:569.12-569.47" wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:524.5-524.45" + attribute \src "ls180.v:573.5-573.45" wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:525.5-525.54" + attribute \src "ls180.v:574.5-574.54" wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:523.5-523.44" + attribute \src "ls180.v:572.5-572.44" wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:521.5-521.46" + attribute \src "ls180.v:570.5-570.46" wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:528.11-528.55" + attribute \src "ls180.v:577.11-577.55" wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:527.32-527.76" + attribute \src "ls180.v:576.32-576.76" wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:552.5-552.50" + attribute \src "ls180.v:601.5-601.50" wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:574.11-574.70" + attribute \src "ls180.v:623.11-623.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:571.11-571.68" + attribute \src "ls180.v:620.11-620.68" wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:573.11-573.70" + attribute \src "ls180.v:622.11-622.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:575.11-575.73" + attribute \src "ls180.v:624.11-624.73" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:598.5-598.59" + attribute \src "ls180.v:647.5-647.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:599.5-599.58" + attribute \src "ls180.v:648.5-648.58" wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:601.12-601.74" + attribute \src "ls180.v:650.12-650.74" wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:600.5-600.64" + attribute \src "ls180.v:649.5-649.64" wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:596.5-596.59" + attribute \src "ls180.v:645.5-645.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:544.12-544.57" + attribute \src "ls180.v:593.12-593.57" wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:546.5-546.51" + attribute \src "ls180.v:595.5-595.51" wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:549.5-549.54" + attribute \src "ls180.v:598.5-598.54" wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:550.5-550.55" + attribute \src "ls180.v:599.5-599.55" wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:551.5-551.56" + attribute \src "ls180.v:600.5-600.56" wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:547.5-547.51" + attribute \src "ls180.v:596.5-596.51" wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:548.5-548.50" + attribute \src "ls180.v:597.5-597.50" wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:543.5-543.45" + attribute \src "ls180.v:592.5-592.45" wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:542.5-542.45" + attribute \src "ls180.v:591.5-591.45" wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:541.5-541.47" + attribute \src "ls180.v:590.5-590.47" wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:539.5-539.51" + attribute \src "ls180.v:588.5-588.51" wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:538.5-538.51" + attribute \src "ls180.v:587.5-587.51" wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:602.12-602.47" + attribute \src "ls180.v:651.12-651.47" wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:606.5-606.45" + attribute \src "ls180.v:655.5-655.45" wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:607.5-607.54" + attribute \src "ls180.v:656.5-656.54" wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:605.5-605.44" + attribute \src "ls180.v:654.5-654.44" wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:603.5-603.46" + attribute \src "ls180.v:652.5-652.46" wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:610.11-610.55" + attribute \src "ls180.v:659.11-659.55" wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:609.32-609.76" + attribute \src "ls180.v:658.32-658.76" wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:634.5-634.50" + attribute \src "ls180.v:683.5-683.50" wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:656.11-656.70" + attribute \src "ls180.v:705.11-705.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:653.11-653.68" + attribute \src "ls180.v:702.11-702.68" wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:655.11-655.70" + attribute \src "ls180.v:704.11-704.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:657.11-657.73" + attribute \src "ls180.v:706.11-706.73" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:680.5-680.59" + attribute \src "ls180.v:729.5-729.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:681.5-681.58" + attribute \src "ls180.v:730.5-730.58" wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:683.12-683.74" + attribute \src "ls180.v:732.12-732.74" wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:682.5-682.64" + attribute \src "ls180.v:731.5-731.64" wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:678.5-678.59" + attribute \src "ls180.v:727.5-727.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:626.12-626.57" + attribute \src "ls180.v:675.12-675.57" wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:628.5-628.51" + attribute \src "ls180.v:677.5-677.51" wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:631.5-631.54" + attribute \src "ls180.v:680.5-680.54" wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:632.5-632.55" + attribute \src "ls180.v:681.5-681.55" wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:633.5-633.56" + attribute \src "ls180.v:682.5-682.56" wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:629.5-629.51" + attribute \src "ls180.v:678.5-678.51" wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:630.5-630.50" + attribute \src "ls180.v:679.5-679.50" wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:625.5-625.45" + attribute \src "ls180.v:674.5-674.45" wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:624.5-624.45" + attribute \src "ls180.v:673.5-673.45" wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:623.5-623.47" + attribute \src "ls180.v:672.5-672.47" wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:621.5-621.51" + attribute \src "ls180.v:670.5-670.51" wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:620.5-620.51" + attribute \src "ls180.v:669.5-669.51" wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:684.12-684.47" + attribute \src "ls180.v:733.12-733.47" wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:688.5-688.45" + attribute \src "ls180.v:737.5-737.45" wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:689.5-689.54" + attribute \src "ls180.v:738.5-738.54" wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:687.5-687.44" + attribute \src "ls180.v:736.5-736.44" wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:685.5-685.46" + attribute \src "ls180.v:734.5-734.46" wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:692.11-692.55" + attribute \src "ls180.v:741.11-741.55" wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:691.32-691.76" + attribute \src "ls180.v:740.32-740.76" wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:716.5-716.50" + attribute \src "ls180.v:765.5-765.50" wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:738.11-738.70" + attribute \src "ls180.v:787.11-787.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:735.11-735.68" + attribute \src "ls180.v:784.11-784.68" wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:737.11-737.70" + attribute \src "ls180.v:786.11-786.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:739.11-739.73" + attribute \src "ls180.v:788.11-788.73" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:762.5-762.59" + attribute \src "ls180.v:811.5-811.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:763.5-763.58" + attribute \src "ls180.v:812.5-812.58" wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:765.12-765.74" + attribute \src "ls180.v:814.12-814.74" wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:764.5-764.64" + attribute \src "ls180.v:813.5-813.64" wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:760.5-760.59" + attribute \src "ls180.v:809.5-809.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:708.12-708.57" + attribute \src "ls180.v:757.12-757.57" wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:710.5-710.51" + attribute \src "ls180.v:759.5-759.51" wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:713.5-713.54" + attribute \src "ls180.v:762.5-762.54" wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:714.5-714.55" + attribute \src "ls180.v:763.5-763.55" wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:715.5-715.56" + attribute \src "ls180.v:764.5-764.56" wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:711.5-711.51" + attribute \src "ls180.v:760.5-760.51" wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:712.5-712.50" + attribute \src "ls180.v:761.5-761.50" wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:707.5-707.45" + attribute \src "ls180.v:756.5-756.45" wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:706.5-706.45" + attribute \src "ls180.v:755.5-755.45" wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:705.5-705.47" + attribute \src "ls180.v:754.5-754.47" wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:703.5-703.51" + attribute \src "ls180.v:752.5-752.51" wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:702.5-702.51" + attribute \src "ls180.v:751.5-751.51" wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:766.12-766.47" + attribute \src "ls180.v:815.12-815.47" wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:770.5-770.45" + attribute \src "ls180.v:819.5-819.45" wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:771.5-771.54" + attribute \src "ls180.v:820.5-820.54" wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:769.5-769.44" + attribute \src "ls180.v:818.5-818.44" wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:767.5-767.46" + attribute \src "ls180.v:816.5-816.46" wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:774.11-774.55" + attribute \src "ls180.v:823.11-823.55" wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:773.32-773.76" + attribute \src "ls180.v:822.32-822.76" wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:789.5-789.49" + attribute \src "ls180.v:838.5-838.49" wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:790.5-790.49" + attribute \src "ls180.v:839.5-839.49" wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:791.5-791.48" + attribute \src "ls180.v:840.5-840.48" wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:797.11-797.45" + attribute \src "ls180.v:846.11-846.45" wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:795.11-795.46" + attribute \src "ls180.v:844.11-844.46" wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:807.5-807.49" + attribute \src "ls180.v:856.5-856.49" wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:808.5-808.49" + attribute \src "ls180.v:857.5-857.49" wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:809.5-809.48" + attribute \src "ls180.v:858.5-858.48" wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:804.5-804.43" + attribute \src "ls180.v:853.5-853.43" wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:815.11-815.45" + attribute \src "ls180.v:864.11-864.45" wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:813.11-813.46" + attribute \src "ls180.v:862.11-862.46" wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:802.5-802.48" + attribute \src "ls180.v:851.5-851.48" wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:799.5-799.44" + attribute \src "ls180.v:848.5-848.44" wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:800.5-800.45" + attribute \src "ls180.v:849.5-849.45" wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:428.5-428.31" + attribute \src "ls180.v:477.5-477.31" wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:429.12-429.44" + attribute \src "ls180.v:478.12-478.44" wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:430.11-430.43" + attribute \src "ls180.v:479.11-479.43" wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:431.5-431.38" + attribute \src "ls180.v:480.5-480.38" wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:432.5-432.38" + attribute \src "ls180.v:481.5-481.38" wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:433.5-433.37" + attribute \src "ls180.v:482.5-482.37" wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:427.5-427.32" + attribute \src "ls180.v:476.5-476.32" wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:426.5-426.32" + attribute \src "ls180.v:475.5-475.32" wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:366.5-366.33" + attribute \src "ls180.v:415.5-415.33" wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:365.11-365.44" + attribute \src "ls180.v:414.11-414.44" wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:410.12-410.45" + attribute \src "ls180.v:459.12-459.45" wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:411.11-411.40" + attribute \src "ls180.v:460.11-460.40" wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:412.5-412.35" + attribute \src "ls180.v:461.5-461.35" wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:413.5-413.34" + attribute \src "ls180.v:462.5-462.34" wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:414.5-414.35" + attribute \src "ls180.v:463.5-463.35" wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:423.5-423.39" + attribute \src "ls180.v:472.5-472.39" wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:415.5-415.34" + attribute \src "ls180.v:464.5-464.34" wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:421.5-421.39" + attribute \src "ls180.v:470.5-470.39" wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:834.5-834.26" + attribute \src "ls180.v:883.5-883.26" wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:837.5-837.26" + attribute \src "ls180.v:886.5-886.26" wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:407.12-407.46" + attribute \src "ls180.v:456.12-456.46" wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:408.11-408.47" + attribute \src "ls180.v:457.11-457.47" wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:313.5-313.36" + attribute \src "ls180.v:362.5-362.36" wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:314.5-314.35" + attribute \src "ls180.v:363.5-363.35" wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:315.5-315.36" + attribute \src "ls180.v:364.5-364.36" wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:325.12-325.45" + attribute \src "ls180.v:374.12-374.45" wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:326.5-326.43" + attribute \src "ls180.v:375.5-375.43" wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:316.5-316.35" + attribute \src "ls180.v:365.5-365.35" wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:352.5-352.38" + attribute \src "ls180.v:401.5-401.38" wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:343.12-343.48" + attribute \src "ls180.v:392.12-392.48" wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:344.11-344.43" + attribute \src "ls180.v:393.11-393.43" wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:345.5-345.38" + attribute \src "ls180.v:394.5-394.38" wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:349.5-349.36" + attribute \src "ls180.v:398.5-398.36" wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:346.5-346.37" + attribute \src "ls180.v:395.5-395.37" wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:350.5-350.36" + attribute \src "ls180.v:399.5-399.36" wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:347.5-347.38" + attribute \src "ls180.v:396.5-396.38" wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:356.5-356.42" + attribute \src "ls180.v:405.5-405.42" wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:351.5-351.40" + attribute \src "ls180.v:400.5-400.40" wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:348.5-348.37" + attribute \src "ls180.v:397.5-397.37" wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:353.12-353.47" + attribute \src "ls180.v:402.12-402.47" wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:354.5-354.42" + attribute \src "ls180.v:403.5-403.42" wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:355.11-355.50" + attribute \src "ls180.v:404.11-404.50" wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:444.5-444.38" + attribute \src "ls180.v:493.5-493.38" wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:443.5-443.38" + attribute \src "ls180.v:492.5-492.38" wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:364.5-364.25" + attribute \src "ls180.v:413.5-413.25" wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:450.5-450.38" + attribute \src "ls180.v:499.5-499.38" wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:449.11-449.46" + attribute \src "ls180.v:498.11-498.46" wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:448.5-448.38" + attribute \src "ls180.v:497.5-497.38" wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:445.5-445.39" + attribute \src "ls180.v:494.5-494.39" wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:341.12-341.46" + attribute \src "ls180.v:390.12-390.46" wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:342.5-342.44" + attribute \src "ls180.v:391.5-391.44" wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:377.12-377.37" + attribute \src "ls180.v:426.12-426.37" wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:819.11-819.40" + attribute \src "ls180.v:868.11-868.40" wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:363.11-363.36" + attribute \src "ls180.v:412.11-412.36" wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:828.5-828.36" + attribute \src "ls180.v:877.5-877.36" wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:827.32-827.63" + attribute \src "ls180.v:876.32-876.63" wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:836.11-836.34" + attribute \src "ls180.v:885.11-885.34" wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:839.11-839.34" + attribute \src "ls180.v:888.11-888.34" wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:441.11-441.44" + attribute \src "ls180.v:490.11-490.44" wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:831.11-831.42" + attribute \src "ls180.v:880.11-880.42" wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:830.32-830.63" + attribute \src "ls180.v:879.32-879.63" wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:376.5-376.32" + attribute \src "ls180.v:425.5-425.32" wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:375.12-375.45" + attribute \src "ls180.v:424.12-424.45" wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:1044.12-1044.44" + attribute \src "ls180.v:917.5-917.54" + wire $1\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:923.5-923.38" + wire $1\main_socbushandler_counter[0:0] + attribute \src "ls180.v:1852.5-1852.60" + wire $1\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1853.5-1853.63" + wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:925.12-925.44" + wire width 64 $1\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:922.5-922.35" + wire $1\main_socbushandler_skip[0:0] + attribute \src "ls180.v:1111.12-1111.44" wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1045.5-1045.31" + attribute \src "ls180.v:1112.5-1112.31" wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1049.11-1049.42" + attribute \src "ls180.v:1116.11-1116.42" wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1050.5-1050.31" + attribute \src "ls180.v:1117.5-1117.31" wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1106.5-1106.30" + attribute \src "ls180.v:1173.5-1173.30" wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1105.12-1105.45" + attribute \src "ls180.v:1172.12-1172.45" wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1054.5-1054.36" + attribute \src "ls180.v:1121.5-1121.36" wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1055.5-1055.31" + attribute \src "ls180.v:1122.5-1122.31" wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1056.5-1056.36" + attribute \src "ls180.v:1123.5-1123.36" wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1057.5-1057.31" + attribute \src "ls180.v:1124.5-1124.31" wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1058.5-1058.39" + attribute \src "ls180.v:1125.5-1125.39" wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1059.5-1059.38" + attribute \src "ls180.v:1126.5-1126.38" wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1060.11-1060.40" + attribute \src "ls180.v:1127.11-1127.40" wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1826.11-1826.62" + attribute \src "ls180.v:1893.11-1893.62" wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1827.5-1827.59" + attribute \src "ls180.v:1894.5-1894.59" wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1061.5-1061.39" + attribute \src "ls180.v:1128.5-1128.39" wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1062.5-1062.39" + attribute \src "ls180.v:1129.5-1129.39" wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:1035.5-1035.32" + attribute \src "ls180.v:1102.5-1102.32" wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1063.12-1063.48" + attribute \src "ls180.v:1130.12-1130.48" wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1066.11-1066.44" + attribute \src "ls180.v:1133.11-1133.44" wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1067.11-1067.43" + attribute \src "ls180.v:1134.11-1134.43" wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1068.11-1068.44" + attribute \src "ls180.v:1135.11-1135.44" wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:1036.5-1036.31" + attribute \src "ls180.v:1103.5-1103.31" wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:1038.11-1038.38" + attribute \src "ls180.v:1105.11-1105.38" wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1042.5-1042.33" + attribute \src "ls180.v:1109.5-1109.33" wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1099.12-1099.47" + attribute \src "ls180.v:1166.12-1166.47" wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1094.5-1094.37" + attribute \src "ls180.v:1161.5-1161.37" wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1081.5-1081.37" + attribute \src "ls180.v:1148.5-1148.37" wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1080.12-1080.50" + attribute \src "ls180.v:1147.12-1147.50" wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1096.11-1096.38" + attribute \src "ls180.v:1163.11-1163.38" wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1830.11-1830.60" + attribute \src "ls180.v:1897.11-1897.60" wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1831.5-1831.57" + attribute \src "ls180.v:1898.5-1898.57" wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1095.5-1095.36" + attribute \src "ls180.v:1162.5-1162.36" wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1091.5-1091.32" + attribute \src "ls180.v:1158.5-1158.32" wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1090.5-1090.37" + attribute \src "ls180.v:1157.5-1157.37" wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1071.5-1071.32" + attribute \src "ls180.v:1138.5-1138.32" wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1072.5-1072.30" + attribute \src "ls180.v:1139.5-1139.30" wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1093.5-1093.38" + attribute \src "ls180.v:1160.5-1160.38" wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1092.5-1092.43" + attribute \src "ls180.v:1159.5-1159.43" wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1074.11-1074.37" + attribute \src "ls180.v:1141.11-1141.37" wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1104.11-1104.42" + attribute \src "ls180.v:1171.11-1171.42" wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1098.5-1098.37" + attribute \src "ls180.v:1165.5-1165.37" wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1102.11-1102.42" + attribute \src "ls180.v:1169.11-1169.42" wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1097.5-1097.37" + attribute \src "ls180.v:1164.5-1164.37" wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1086.5-1086.34" + attribute \src "ls180.v:1153.5-1153.34" wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1103.11-1103.41" + attribute \src "ls180.v:1170.11-1170.41" wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1085.11-1085.45" + attribute \src "ls180.v:1152.11-1152.45" wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1078.5-1078.33" + attribute \src "ls180.v:1145.5-1145.33" wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:258.11-258.31" - wire width 4 $1\main_sram0_we[3:0] - attribute \src "ls180.v:273.11-273.31" - wire width 4 $1\main_sram1_we[3:0] - attribute \src "ls180.v:288.11-288.31" - wire width 4 $1\main_sram2_we[3:0] - attribute \src "ls180.v:932.11-932.50" + attribute \src "ls180.v:262.11-262.31" + wire width 8 $1\main_sram0_we[7:0] + attribute \src "ls180.v:277.11-277.31" + wire width 8 $1\main_sram1_we[7:0] + attribute \src "ls180.v:292.11-292.31" + wire width 8 $1\main_sram2_we[7:0] + attribute \src "ls180.v:307.11-307.31" + wire width 8 $1\main_sram3_we[7:0] + attribute \src "ls180.v:993.11-993.50" wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:934.5-934.37" + attribute \src "ls180.v:995.5-995.37" wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:928.11-928.49" + attribute \src "ls180.v:989.11-989.49" wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:933.11-933.48" + attribute \src "ls180.v:994.11-994.48" wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:900.12-900.54" + attribute \src "ls180.v:961.12-961.54" wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:890.12-890.54" + attribute \src "ls180.v:951.12-951.54" wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:883.5-883.28" + attribute \src "ls180.v:944.5-944.28" wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:904.11-904.43" + attribute \src "ls180.v:965.11-965.43" wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:905.5-905.33" + attribute \src "ls180.v:966.5-966.33" wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:902.5-902.30" + attribute \src "ls180.v:963.5-963.30" wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:903.11-903.38" + attribute \src "ls180.v:964.11-964.38" wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:885.5-885.36" + attribute \src "ls180.v:946.5-946.36" wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:898.11-898.51" + attribute \src "ls180.v:959.11-959.51" wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:894.5-894.38" + attribute \src "ls180.v:955.5-955.38" wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:882.12-882.47" + attribute \src "ls180.v:943.12-943.47" wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:892.11-892.43" + attribute \src "ls180.v:953.11-953.43" wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:893.5-893.33" + attribute \src "ls180.v:954.5-954.33" wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:891.11-891.38" + attribute \src "ls180.v:952.11-952.38" wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:899.5-899.39" + attribute \src "ls180.v:960.5-960.39" wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:889.5-889.39" + attribute \src "ls180.v:950.5-950.39" wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:923.5-923.30" + attribute \src "ls180.v:984.5-984.30" wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:1007.11-1007.43" + attribute \src "ls180.v:1068.11-1068.43" wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:1004.11-1004.42" + attribute \src "ls180.v:1065.11-1065.42" wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:1006.11-1006.43" + attribute \src "ls180.v:1067.11-1067.43" wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:997.5-997.38" + attribute \src "ls180.v:1058.5-1058.38" wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1008.11-1008.46" + attribute \src "ls180.v:1069.11-1069.46" wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:924.5-924.36" + attribute \src "ls180.v:985.5-985.36" wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:921.5-921.32" + attribute \src "ls180.v:982.5-982.32" wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:918.5-918.30" + attribute \src "ls180.v:979.5-979.30" wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:970.11-970.43" + attribute \src "ls180.v:1031.11-1031.43" wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:967.11-967.42" + attribute \src "ls180.v:1028.11-1028.42" wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:969.11-969.43" + attribute \src "ls180.v:1030.11-1030.43" wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:960.5-960.38" + attribute \src "ls180.v:1021.5-1021.38" wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:971.11-971.46" + attribute \src "ls180.v:1032.11-1032.46" wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:919.5-919.36" + attribute \src "ls180.v:980.5-980.36" wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:916.5-916.32" + attribute \src "ls180.v:977.5-977.32" wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:860.5-860.29" + attribute \src "ls180.v:909.5-909.29" wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:878.5-878.31" + attribute \src "ls180.v:903.12-903.37" + wire width 30 $1\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:907.5-907.29" + wire $1\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:904.12-904.39" + wire width 32 $1\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:906.11-906.35" + wire width 4 $1\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:908.5-908.29" + wire $1\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:910.5-910.28" + wire $1\main_wb_sdram_we[0:0] + attribute \src "ls180.v:939.5-939.31" wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2860.68-2860.110" - wire $add$ls180.v:2860$34_Y - attribute \src "ls180.v:2920.68-2920.110" - wire $add$ls180.v:2920$45_Y - attribute \src "ls180.v:2980.68-2980.110" - wire $add$ls180.v:2980$56_Y - attribute \src "ls180.v:4143.54-4143.83" - wire $add$ls180.v:4143$588_Y - attribute \src "ls180.v:4243.36-4243.89" - wire width 5 $add$ls180.v:4243$634_Y - attribute \src "ls180.v:4273.36-4273.89" - wire width 5 $add$ls180.v:4273$645_Y - attribute \src "ls180.v:4328.54-4328.83" - wire width 3 $add$ls180.v:4328$658_Y - attribute \src "ls180.v:4387.52-4387.79" - wire width 3 $add$ls180.v:4387$666_Y - attribute \src "ls180.v:4491.58-4491.86" - wire width 8 $add$ls180.v:4491$694_Y - attribute \src "ls180.v:4548.58-4548.86" - wire width 8 $add$ls180.v:4548$697_Y - attribute \src "ls180.v:4565.58-4565.86" - wire width 8 $add$ls180.v:4565$699_Y - attribute \src "ls180.v:4658.59-4658.87" - wire width 8 $add$ls180.v:4658$716_Y - attribute \src "ls180.v:4683.59-4683.87" - wire width 8 $add$ls180.v:4683$719_Y - attribute \src "ls180.v:4805.53-4805.82" - wire width 8 $add$ls180.v:4805$736_Y - attribute \src "ls180.v:4916.65-4916.114" - wire width 10 $add$ls180.v:4916$750_Y - attribute \src "ls180.v:4921.62-4921.91" - wire width 10 $add$ls180.v:4921$753_Y - attribute \src "ls180.v:4947.61-4947.90" - wire width 10 $add$ls180.v:4947$756_Y - attribute \src "ls180.v:5151.80-5151.117" - wire width 3 $add$ls180.v:5151$941_Y - attribute \src "ls180.v:5345.54-5345.82" - wire width 3 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attribute \src "ls180.v:4083.78-4083.113" + wire $eq$ls180.v:4083$525_Y + attribute \src "ls180.v:4164.42-4164.82" + wire $eq$ls180.v:4164$548_Y + attribute \src "ls180.v:4164.145-4164.178" + wire $eq$ls180.v:4164$549_Y + attribute \src "ls180.v:4164.220-4164.253" + wire $eq$ls180.v:4164$552_Y + attribute \src "ls180.v:4164.295-4164.328" + wire $eq$ls180.v:4164$555_Y + attribute \src "ls180.v:4169.42-4169.82" + wire $eq$ls180.v:4169$564_Y + attribute \src "ls180.v:4169.145-4169.178" + wire $eq$ls180.v:4169$565_Y + attribute \src "ls180.v:4169.220-4169.253" + wire $eq$ls180.v:4169$568_Y + attribute \src "ls180.v:4169.295-4169.328" + wire $eq$ls180.v:4169$571_Y + attribute \src "ls180.v:4174.42-4174.82" + wire $eq$ls180.v:4174$580_Y + attribute \src "ls180.v:4174.145-4174.178" + wire $eq$ls180.v:4174$581_Y + attribute \src "ls180.v:4174.220-4174.253" + wire $eq$ls180.v:4174$584_Y + attribute \src "ls180.v:4174.295-4174.328" + wire $eq$ls180.v:4174$587_Y + attribute \src "ls180.v:4179.42-4179.82" + wire $eq$ls180.v:4179$596_Y + attribute \src "ls180.v:4179.145-4179.178" + wire $eq$ls180.v:4179$597_Y + attribute \src "ls180.v:4179.220-4179.253" + wire $eq$ls180.v:4179$600_Y + attribute \src "ls180.v:4179.295-4179.328" + wire $eq$ls180.v:4179$603_Y + attribute \src "ls180.v:4184.44-4184.77" + wire $eq$ls180.v:4184$612_Y + attribute \src "ls180.v:4184.83-4184.123" + wire $eq$ls180.v:4184$613_Y + attribute \src "ls180.v:4184.186-4184.219" + wire $eq$ls180.v:4184$614_Y + attribute \src "ls180.v:4184.261-4184.294" + wire $eq$ls180.v:4184$617_Y + attribute \src "ls180.v:4184.336-4184.369" + wire $eq$ls180.v:4184$620_Y + attribute \src "ls180.v:4184.418-4184.451" + wire $eq$ls180.v:4184$628_Y + attribute \src "ls180.v:4184.457-4184.497" + wire $eq$ls180.v:4184$629_Y + attribute \src "ls180.v:4184.560-4184.593" + wire $eq$ls180.v:4184$630_Y + attribute \src "ls180.v:4184.635-4184.668" + wire $eq$ls180.v:4184$633_Y + attribute \src "ls180.v:4184.710-4184.743" + wire $eq$ls180.v:4184$636_Y + attribute \src "ls180.v:4184.792-4184.825" + wire $eq$ls180.v:4184$644_Y + attribute \src "ls180.v:4184.831-4184.871" + wire $eq$ls180.v:4184$645_Y + attribute \src "ls180.v:4184.934-4184.967" + wire $eq$ls180.v:4184$646_Y + attribute \src "ls180.v:4184.1009-4184.1042" + wire $eq$ls180.v:4184$649_Y + attribute \src "ls180.v:4184.1084-4184.1117" + wire $eq$ls180.v:4184$652_Y + attribute \src "ls180.v:4184.1166-4184.1199" + wire $eq$ls180.v:4184$660_Y + attribute \src "ls180.v:4184.1205-4184.1245" + wire $eq$ls180.v:4184$661_Y + attribute \src "ls180.v:4184.1308-4184.1341" + wire $eq$ls180.v:4184$662_Y + attribute \src "ls180.v:4184.1383-4184.1416" + wire $eq$ls180.v:4184$665_Y + attribute \src "ls180.v:4184.1458-4184.1491" + wire $eq$ls180.v:4184$668_Y + attribute \src "ls180.v:4243.29-4243.57" + wire $eq$ls180.v:4243$681_Y + attribute \src "ls180.v:4250.11-4250.41" + wire $eq$ls180.v:4250$686_Y + attribute \src "ls180.v:4418.37-4418.111" + wire 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"ls180.v:4838.39-4838.94" + wire $eq$ls180.v:4838$823_Y + attribute \src "ls180.v:4875.32-4875.89" + wire $eq$ls180.v:4875$832_Y + attribute \src "ls180.v:4923.10-4923.40" + wire $eq$ls180.v:4923$836_Y + attribute \src "ls180.v:4972.40-4972.98" + wire $eq$ls180.v:4972$838_Y + attribute \src "ls180.v:5023.9-5023.41" + wire $eq$ls180.v:5023$848_Y + attribute \src "ls180.v:5032.37-5032.123" + wire $eq$ls180.v:5032$851_Y + attribute \src "ls180.v:5055.9-5055.41" + wire $eq$ls180.v:5055$854_Y + attribute \src "ls180.v:5065.10-5065.41" + wire $eq$ls180.v:5065$856_Y + attribute \src "ls180.v:5234.9-5234.47" + wire $eq$ls180.v:5234$1038_Y + attribute \src "ls180.v:5264.10-5264.48" + wire $eq$ls180.v:5264$1039_Y + attribute \src "ls180.v:5295.10-5295.78" + wire $eq$ls180.v:5295$1044_Y + attribute \src "ls180.v:5295.83-5295.151" + wire $eq$ls180.v:5295$1045_Y + attribute \src "ls180.v:5295.157-5295.225" + wire $eq$ls180.v:5295$1047_Y + attribute \src "ls180.v:5295.231-5295.299" + wire $eq$ls180.v:5295$1049_Y + attribute \src "ls180.v:5303.7-5303.44" + wire $eq$ls180.v:5303$1053_Y + attribute \src "ls180.v:5313.7-5313.44" + wire $eq$ls180.v:5313$1056_Y + attribute \src "ls180.v:5323.7-5323.44" + wire $eq$ls180.v:5323$1059_Y + attribute \src "ls180.v:5333.7-5333.44" + wire $eq$ls180.v:5333$1062_Y + attribute \src "ls180.v:5457.36-5457.64" + wire $eq$ls180.v:5457$1113_Y + attribute \src "ls180.v:5463.10-5463.39" + wire $eq$ls180.v:5463$1116_Y + attribute \src "ls180.v:5464.11-5464.39" + wire $eq$ls180.v:5464$1117_Y + attribute \src "ls180.v:5476.34-5476.63" + wire $eq$ls180.v:5476$1118_Y + attribute \src "ls180.v:5477.9-5477.37" + wire $eq$ls180.v:5477$1119_Y + attribute \src "ls180.v:5484.10-5484.55" + wire $eq$ls180.v:5484$1120_Y + attribute \src "ls180.v:5490.12-5490.41" + wire $eq$ls180.v:5490$1121_Y + attribute \src "ls180.v:5493.13-5493.42" + wire $eq$ls180.v:5493$1122_Y + attribute \src "ls180.v:5515.10-5515.76" + wire $eq$ls180.v:5515$1127_Y + attribute \src "ls180.v:5530.35-5530.101" + wire $eq$ls180.v:5530$1130_Y + attribute \src "ls180.v:5532.10-5532.56" + wire $eq$ls180.v:5532$1131_Y + attribute \src "ls180.v:5541.12-5541.78" + wire $eq$ls180.v:5541$1135_Y + attribute \src "ls180.v:5548.11-5548.57" + wire $eq$ls180.v:5548$1136_Y + attribute \src "ls180.v:5665.10-5665.105" + wire $eq$ls180.v:5665$1153_Y + attribute \src "ls180.v:5755.39-5755.106" + wire $eq$ls180.v:5755$1159_Y + attribute \src "ls180.v:5785.44-5785.82" + wire $eq$ls180.v:5785$1162_Y + attribute \src "ls180.v:5786.43-5786.81" + wire $eq$ls180.v:5786$1163_Y + attribute \src "ls180.v:5898.68-5898.89" + wire $eq$ls180.v:5898$1179_Y + attribute \src "ls180.v:5899.68-5899.89" + wire $eq$ls180.v:5899$1181_Y + attribute \src "ls180.v:5900.71-5900.92" + wire $eq$ls180.v:5900$1183_Y + attribute \src "ls180.v:5901.57-5901.78" + wire $eq$ls180.v:5901$1185_Y + attribute \src "ls180.v:5902.57-5902.78" + wire $eq$ls180.v:5902$1187_Y + attribute \src "ls180.v:5903.68-5903.89" + wire $eq$ls180.v:5903$1189_Y + attribute \src "ls180.v:5904.68-5904.89" + wire $eq$ls180.v:5904$1191_Y + attribute \src "ls180.v:5905.71-5905.92" + wire $eq$ls180.v:5905$1193_Y + attribute \src "ls180.v:5906.57-5906.78" + wire $eq$ls180.v:5906$1195_Y + attribute \src "ls180.v:5907.57-5907.78" + wire $eq$ls180.v:5907$1197_Y + attribute \src "ls180.v:5911.27-5911.59" + wire $eq$ls180.v:5911$1200_Y + attribute \src "ls180.v:5912.27-5912.59" + wire $eq$ls180.v:5912$1201_Y + attribute \src "ls180.v:5913.27-5913.59" + wire $eq$ls180.v:5913$1202_Y + attribute \src "ls180.v:5914.27-5914.59" + wire $eq$ls180.v:5914$1203_Y + attribute \src "ls180.v:5915.27-5915.59" + wire $eq$ls180.v:5915$1204_Y + attribute \src "ls180.v:5916.27-5916.68" + wire $eq$ls180.v:5916$1205_Y + attribute \src "ls180.v:5917.27-5917.65" + wire $eq$ls180.v:5917$1206_Y + attribute \src "ls180.v:5918.27-5918.59" + wire $eq$ls180.v:5918$1207_Y + attribute \src "ls180.v:5919.27-5919.59" + wire $eq$ls180.v:5919$1208_Y + attribute \src "ls180.v:5920.27-5920.59" + wire $eq$ls180.v:5920$1209_Y + attribute \src "ls180.v:5921.28-5921.60" + wire $eq$ls180.v:5921$1210_Y + attribute \src "ls180.v:5922.28-5922.62" + wire $eq$ls180.v:5922$1211_Y + attribute \src "ls180.v:5923.28-5923.66" + wire $eq$ls180.v:5923$1212_Y + attribute \src "ls180.v:6043.24-6043.45" + wire $eq$ls180.v:6043$1279_Y + attribute \src "ls180.v:6044.32-6044.77" + wire $eq$ls180.v:6044$1280_Y + attribute \src "ls180.v:6046.97-6046.141" + wire $eq$ls180.v:6046$1282_Y + attribute \src "ls180.v:6047.100-6047.144" + wire $eq$ls180.v:6047$1286_Y + attribute \src "ls180.v:6049.99-6049.143" + wire $eq$ls180.v:6049$1289_Y + attribute \src "ls180.v:6050.102-6050.146" + wire $eq$ls180.v:6050$1293_Y + attribute \src "ls180.v:6052.99-6052.143" + wire $eq$ls180.v:6052$1296_Y + attribute \src "ls180.v:6053.102-6053.146" + wire $eq$ls180.v:6053$1300_Y + attribute \src "ls180.v:6055.99-6055.143" + wire $eq$ls180.v:6055$1303_Y + attribute \src "ls180.v:6056.102-6056.146" + wire $eq$ls180.v:6056$1307_Y + attribute \src "ls180.v:6058.99-6058.143" + wire $eq$ls180.v:6058$1310_Y + attribute \src "ls180.v:6059.102-6059.146" + wire $eq$ls180.v:6059$1314_Y + attribute \src "ls180.v:6061.102-6061.146" + wire $eq$ls180.v:6061$1317_Y + attribute \src "ls180.v:6062.105-6062.149" + wire $eq$ls180.v:6062$1321_Y + attribute \src "ls180.v:6064.102-6064.146" + wire $eq$ls180.v:6064$1324_Y + attribute \src "ls180.v:6065.105-6065.149" + wire $eq$ls180.v:6065$1328_Y + attribute \src "ls180.v:6067.102-6067.146" + wire $eq$ls180.v:6067$1331_Y + attribute \src "ls180.v:6068.105-6068.149" + wire $eq$ls180.v:6068$1335_Y + attribute \src "ls180.v:6070.102-6070.146" + wire $eq$ls180.v:6070$1338_Y + attribute \src "ls180.v:6071.105-6071.149" + wire $eq$ls180.v:6071$1342_Y + attribute \src "ls180.v:6082.32-6082.77" + wire $eq$ls180.v:6082$1344_Y + attribute \src "ls180.v:6084.94-6084.138" + wire $eq$ls180.v:6084$1346_Y + attribute \src "ls180.v:6085.97-6085.141" + wire $eq$ls180.v:6085$1350_Y + attribute \src "ls180.v:6087.94-6087.138" + wire $eq$ls180.v:6087$1353_Y + attribute \src "ls180.v:6088.97-6088.141" + wire $eq$ls180.v:6088$1357_Y + attribute \src "ls180.v:6090.94-6090.138" + wire $eq$ls180.v:6090$1360_Y + attribute \src "ls180.v:6091.97-6091.141" + wire $eq$ls180.v:6091$1364_Y + attribute \src "ls180.v:6093.94-6093.138" + wire $eq$ls180.v:6093$1367_Y + attribute \src "ls180.v:6094.97-6094.141" + wire $eq$ls180.v:6094$1371_Y + attribute \src "ls180.v:6096.95-6096.139" + wire $eq$ls180.v:6096$1374_Y + attribute \src "ls180.v:6097.98-6097.142" + wire $eq$ls180.v:6097$1378_Y + attribute \src "ls180.v:6099.95-6099.139" + wire $eq$ls180.v:6099$1381_Y + attribute \src "ls180.v:6100.98-6100.142" + wire $eq$ls180.v:6100$1385_Y + attribute \src "ls180.v:6108.32-6108.78" + wire $eq$ls180.v:6108$1387_Y + attribute \src "ls180.v:6110.93-6110.135" + wire $eq$ls180.v:6110$1389_Y + attribute \src "ls180.v:6111.96-6111.138" + wire $eq$ls180.v:6111$1393_Y + attribute \src "ls180.v:6113.92-6113.134" + wire $eq$ls180.v:6113$1396_Y + attribute \src "ls180.v:6114.95-6114.137" + wire $eq$ls180.v:6114$1400_Y + attribute \src "ls180.v:6122.32-6122.78" + wire $eq$ls180.v:6122$1402_Y + attribute \src "ls180.v:6124.98-6124.142" + wire $eq$ls180.v:6124$1404_Y + attribute \src "ls180.v:6125.101-6125.145" + wire $eq$ls180.v:6125$1408_Y + attribute \src "ls180.v:6127.97-6127.141" + wire $eq$ls180.v:6127$1411_Y + attribute \src "ls180.v:6128.100-6128.144" + wire $eq$ls180.v:6128$1415_Y + attribute \src "ls180.v:6130.97-6130.141" + wire $eq$ls180.v:6130$1418_Y + attribute \src "ls180.v:6131.100-6131.144" + wire $eq$ls180.v:6131$1422_Y + attribute \src "ls180.v:6133.97-6133.141" + wire $eq$ls180.v:6133$1425_Y + attribute \src "ls180.v:6134.100-6134.144" + wire $eq$ls180.v:6134$1429_Y + attribute \src "ls180.v:6136.97-6136.141" + wire $eq$ls180.v:6136$1432_Y + attribute \src "ls180.v:6137.100-6137.144" + wire $eq$ls180.v:6137$1436_Y + attribute \src "ls180.v:6139.98-6139.142" + wire $eq$ls180.v:6139$1439_Y + attribute \src "ls180.v:6140.101-6140.145" + wire $eq$ls180.v:6140$1443_Y + attribute \src "ls180.v:6142.98-6142.142" + wire $eq$ls180.v:6142$1446_Y + attribute \src "ls180.v:6143.101-6143.145" + wire $eq$ls180.v:6143$1450_Y + attribute \src "ls180.v:6145.98-6145.142" + wire $eq$ls180.v:6145$1453_Y + attribute \src "ls180.v:6146.101-6146.145" + wire $eq$ls180.v:6146$1457_Y + attribute \src "ls180.v:6148.98-6148.142" + wire $eq$ls180.v:6148$1460_Y + attribute \src "ls180.v:6149.101-6149.145" + wire $eq$ls180.v:6149$1464_Y + attribute \src "ls180.v:6159.32-6159.78" + wire $eq$ls180.v:6159$1466_Y + attribute \src "ls180.v:6161.98-6161.142" + wire $eq$ls180.v:6161$1468_Y + attribute \src "ls180.v:6162.101-6162.145" + wire $eq$ls180.v:6162$1472_Y + attribute \src "ls180.v:6164.97-6164.141" + wire $eq$ls180.v:6164$1475_Y + attribute \src "ls180.v:6165.100-6165.144" + wire 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$eq$ls180.v:6185$1524_Y + attribute \src "ls180.v:6186.101-6186.145" + wire $eq$ls180.v:6186$1528_Y + attribute \src "ls180.v:6196.32-6196.78" + wire $eq$ls180.v:6196$1530_Y + attribute \src "ls180.v:6198.100-6198.144" + wire $eq$ls180.v:6198$1532_Y + attribute \src "ls180.v:6199.103-6199.147" + wire $eq$ls180.v:6199$1536_Y + attribute \src "ls180.v:6201.100-6201.144" + wire $eq$ls180.v:6201$1539_Y + attribute \src "ls180.v:6202.103-6202.147" + wire $eq$ls180.v:6202$1543_Y + attribute \src "ls180.v:6204.100-6204.144" + wire $eq$ls180.v:6204$1546_Y + attribute \src "ls180.v:6205.103-6205.147" + wire $eq$ls180.v:6205$1550_Y + attribute \src "ls180.v:6207.100-6207.144" + wire $eq$ls180.v:6207$1553_Y + attribute \src "ls180.v:6208.103-6208.147" + wire $eq$ls180.v:6208$1557_Y + attribute \src "ls180.v:6210.100-6210.144" + wire $eq$ls180.v:6210$1560_Y + attribute \src "ls180.v:6211.103-6211.147" + wire $eq$ls180.v:6211$1564_Y + attribute \src "ls180.v:6213.100-6213.144" + wire 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$eq$ls180.v:6232$1613_Y + attribute \src "ls180.v:6234.102-6234.147" + wire $eq$ls180.v:6234$1616_Y + attribute \src "ls180.v:6235.105-6235.150" + wire $eq$ls180.v:6235$1620_Y + attribute \src "ls180.v:6237.99-6237.144" + wire $eq$ls180.v:6237$1623_Y + attribute \src "ls180.v:6238.102-6238.147" + wire $eq$ls180.v:6238$1627_Y + attribute \src "ls180.v:6240.100-6240.145" + wire $eq$ls180.v:6240$1630_Y + attribute \src "ls180.v:6241.103-6241.148" + wire $eq$ls180.v:6241$1634_Y + attribute \src "ls180.v:6258.32-6258.78" + wire $eq$ls180.v:6258$1636_Y + attribute \src "ls180.v:6260.104-6260.148" + wire $eq$ls180.v:6260$1638_Y + attribute \src "ls180.v:6261.107-6261.151" + wire $eq$ls180.v:6261$1642_Y + attribute \src "ls180.v:6263.104-6263.148" + wire $eq$ls180.v:6263$1645_Y + attribute \src "ls180.v:6264.107-6264.151" + wire $eq$ls180.v:6264$1649_Y + attribute \src "ls180.v:6266.104-6266.148" + wire $eq$ls180.v:6266$1652_Y + attribute \src "ls180.v:6267.107-6267.151" + wire $eq$ls180.v:6267$1656_Y + attribute \src "ls180.v:6269.104-6269.148" + wire $eq$ls180.v:6269$1659_Y + attribute \src "ls180.v:6270.107-6270.151" + wire $eq$ls180.v:6270$1663_Y + attribute \src "ls180.v:6272.103-6272.147" + wire $eq$ls180.v:6272$1666_Y + attribute \src "ls180.v:6273.106-6273.150" + wire $eq$ls180.v:6273$1670_Y + attribute \src "ls180.v:6275.103-6275.147" + wire $eq$ls180.v:6275$1673_Y + attribute \src "ls180.v:6276.106-6276.150" + wire $eq$ls180.v:6276$1677_Y + attribute \src "ls180.v:6278.103-6278.147" + wire $eq$ls180.v:6278$1680_Y + attribute \src "ls180.v:6279.106-6279.150" + wire $eq$ls180.v:6279$1684_Y + attribute \src "ls180.v:6281.103-6281.147" + wire $eq$ls180.v:6281$1687_Y + attribute \src "ls180.v:6282.106-6282.150" + wire $eq$ls180.v:6282$1691_Y + attribute \src "ls180.v:6284.94-6284.138" + wire $eq$ls180.v:6284$1694_Y + attribute \src "ls180.v:6285.97-6285.141" + wire $eq$ls180.v:6285$1698_Y + attribute \src "ls180.v:6287.105-6287.149" + wire $eq$ls180.v:6287$1701_Y + attribute \src "ls180.v:6288.108-6288.152" + wire $eq$ls180.v:6288$1705_Y + attribute \src "ls180.v:6290.105-6290.150" + wire $eq$ls180.v:6290$1708_Y + attribute \src "ls180.v:6291.108-6291.153" + wire $eq$ls180.v:6291$1712_Y + attribute \src "ls180.v:6293.105-6293.150" + wire $eq$ls180.v:6293$1715_Y + attribute \src "ls180.v:6294.108-6294.153" + wire $eq$ls180.v:6294$1719_Y + attribute \src "ls180.v:6296.105-6296.150" + wire $eq$ls180.v:6296$1722_Y + attribute \src "ls180.v:6297.108-6297.153" + wire $eq$ls180.v:6297$1726_Y + attribute \src "ls180.v:6299.105-6299.150" + wire $eq$ls180.v:6299$1729_Y + attribute \src "ls180.v:6300.108-6300.153" + wire $eq$ls180.v:6300$1733_Y + attribute \src "ls180.v:6302.105-6302.150" + wire $eq$ls180.v:6302$1736_Y + attribute \src "ls180.v:6303.108-6303.153" + wire $eq$ls180.v:6303$1740_Y + attribute \src "ls180.v:6305.104-6305.149" + wire $eq$ls180.v:6305$1743_Y + attribute \src "ls180.v:6306.107-6306.152" + wire $eq$ls180.v:6306$1747_Y + attribute \src "ls180.v:6308.104-6308.149" + wire $eq$ls180.v:6308$1750_Y + attribute \src "ls180.v:6309.107-6309.152" + wire $eq$ls180.v:6309$1754_Y + attribute \src "ls180.v:6311.104-6311.149" + wire $eq$ls180.v:6311$1757_Y + attribute \src "ls180.v:6312.107-6312.152" + wire $eq$ls180.v:6312$1761_Y + attribute \src "ls180.v:6314.104-6314.149" + wire $eq$ls180.v:6314$1764_Y + attribute \src "ls180.v:6315.107-6315.152" + wire $eq$ls180.v:6315$1768_Y + attribute \src "ls180.v:6317.104-6317.149" + wire $eq$ls180.v:6317$1771_Y + attribute \src "ls180.v:6318.107-6318.152" + wire $eq$ls180.v:6318$1775_Y + attribute \src "ls180.v:6320.104-6320.149" + wire $eq$ls180.v:6320$1778_Y + attribute \src "ls180.v:6321.107-6321.152" + wire $eq$ls180.v:6321$1782_Y + attribute \src "ls180.v:6323.104-6323.149" + wire $eq$ls180.v:6323$1785_Y + attribute \src "ls180.v:6324.107-6324.152" + wire $eq$ls180.v:6324$1789_Y + attribute \src "ls180.v:6326.104-6326.149" + wire $eq$ls180.v:6326$1792_Y + attribute \src "ls180.v:6327.107-6327.152" + wire $eq$ls180.v:6327$1796_Y + attribute \src "ls180.v:6329.104-6329.149" + wire $eq$ls180.v:6329$1799_Y + attribute \src "ls180.v:6330.107-6330.152" + wire $eq$ls180.v:6330$1803_Y + attribute \src "ls180.v:6332.104-6332.149" + wire $eq$ls180.v:6332$1806_Y + attribute \src "ls180.v:6333.107-6333.152" + wire $eq$ls180.v:6333$1810_Y + attribute \src "ls180.v:6335.100-6335.145" + wire $eq$ls180.v:6335$1813_Y + attribute \src "ls180.v:6336.103-6336.148" + wire $eq$ls180.v:6336$1817_Y + attribute \src "ls180.v:6338.101-6338.146" + wire $eq$ls180.v:6338$1820_Y + attribute \src "ls180.v:6339.104-6339.149" + wire $eq$ls180.v:6339$1824_Y + attribute \src "ls180.v:6341.104-6341.149" + wire $eq$ls180.v:6341$1827_Y + attribute \src "ls180.v:6342.107-6342.152" + wire $eq$ls180.v:6342$1831_Y + attribute \src "ls180.v:6344.104-6344.149" + wire $eq$ls180.v:6344$1834_Y + attribute \src "ls180.v:6345.107-6345.152" + wire $eq$ls180.v:6345$1838_Y + attribute \src "ls180.v:6347.103-6347.148" + wire $eq$ls180.v:6347$1841_Y + attribute \src "ls180.v:6348.106-6348.151" + wire $eq$ls180.v:6348$1845_Y + attribute \src "ls180.v:6350.103-6350.148" + wire $eq$ls180.v:6350$1848_Y + attribute \src "ls180.v:6351.106-6351.151" + wire $eq$ls180.v:6351$1852_Y + attribute \src "ls180.v:6353.103-6353.148" + wire $eq$ls180.v:6353$1855_Y + attribute \src "ls180.v:6354.106-6354.151" + wire $eq$ls180.v:6354$1859_Y + attribute \src "ls180.v:6356.103-6356.148" + wire $eq$ls180.v:6356$1862_Y + attribute \src "ls180.v:6357.106-6357.151" + wire $eq$ls180.v:6357$1866_Y + attribute \src "ls180.v:6393.32-6393.78" + wire $eq$ls180.v:6393$1868_Y + attribute \src "ls180.v:6395.100-6395.144" + wire $eq$ls180.v:6395$1870_Y + attribute \src "ls180.v:6396.103-6396.147" + wire $eq$ls180.v:6396$1874_Y + attribute \src "ls180.v:6398.100-6398.144" + wire $eq$ls180.v:6398$1877_Y + attribute \src "ls180.v:6399.103-6399.147" + wire $eq$ls180.v:6399$1881_Y + attribute \src "ls180.v:6401.100-6401.144" + wire $eq$ls180.v:6401$1884_Y + attribute \src "ls180.v:6402.103-6402.147" + wire $eq$ls180.v:6402$1888_Y + attribute \src "ls180.v:6404.100-6404.144" + wire $eq$ls180.v:6404$1891_Y + attribute \src "ls180.v:6405.103-6405.147" + wire $eq$ls180.v:6405$1895_Y + attribute \src "ls180.v:6407.100-6407.144" + wire $eq$ls180.v:6407$1898_Y + attribute \src "ls180.v:6408.103-6408.147" + wire $eq$ls180.v:6408$1902_Y + attribute \src "ls180.v:6410.100-6410.144" + wire $eq$ls180.v:6410$1905_Y + attribute \src "ls180.v:6411.103-6411.147" + wire $eq$ls180.v:6411$1909_Y + attribute \src "ls180.v:6413.100-6413.144" + wire $eq$ls180.v:6413$1912_Y + attribute \src "ls180.v:6414.103-6414.147" + wire $eq$ls180.v:6414$1916_Y + attribute \src "ls180.v:6416.100-6416.144" + wire $eq$ls180.v:6416$1919_Y + attribute \src "ls180.v:6417.103-6417.147" + wire $eq$ls180.v:6417$1923_Y + attribute \src "ls180.v:6419.102-6419.146" + wire $eq$ls180.v:6419$1926_Y + attribute \src "ls180.v:6420.105-6420.149" + wire $eq$ls180.v:6420$1930_Y + attribute \src "ls180.v:6422.102-6422.146" + wire $eq$ls180.v:6422$1933_Y + attribute \src "ls180.v:6423.105-6423.149" + wire $eq$ls180.v:6423$1937_Y + attribute \src "ls180.v:6425.102-6425.147" + wire $eq$ls180.v:6425$1940_Y + attribute \src "ls180.v:6426.105-6426.150" + wire $eq$ls180.v:6426$1944_Y + attribute \src "ls180.v:6428.102-6428.147" + wire $eq$ls180.v:6428$1947_Y + attribute \src "ls180.v:6429.105-6429.150" + wire $eq$ls180.v:6429$1951_Y + attribute \src "ls180.v:6431.102-6431.147" + wire $eq$ls180.v:6431$1954_Y + attribute \src "ls180.v:6432.105-6432.150" + wire $eq$ls180.v:6432$1958_Y + attribute \src "ls180.v:6434.99-6434.144" + wire $eq$ls180.v:6434$1961_Y + attribute \src "ls180.v:6435.102-6435.147" + wire $eq$ls180.v:6435$1965_Y + attribute \src "ls180.v:6437.100-6437.145" + wire $eq$ls180.v:6437$1968_Y + attribute \src "ls180.v:6438.103-6438.148" + wire $eq$ls180.v:6438$1972_Y + attribute \src "ls180.v:6440.102-6440.147" + wire $eq$ls180.v:6440$1975_Y + attribute \src "ls180.v:6441.105-6441.150" + wire $eq$ls180.v:6441$1979_Y + attribute \src "ls180.v:6443.102-6443.147" + wire $eq$ls180.v:6443$1982_Y + attribute \src "ls180.v:6444.105-6444.150" + wire $eq$ls180.v:6444$1986_Y + attribute \src "ls180.v:6446.102-6446.147" + wire $eq$ls180.v:6446$1989_Y + attribute \src "ls180.v:6447.105-6447.150" + wire $eq$ls180.v:6447$1993_Y + attribute \src "ls180.v:6449.102-6449.147" + wire $eq$ls180.v:6449$1996_Y + attribute \src "ls180.v:6450.105-6450.150" + wire $eq$ls180.v:6450$2000_Y + attribute \src "ls180.v:6472.32-6472.78" + wire $eq$ls180.v:6472$2002_Y + attribute \src "ls180.v:6474.102-6474.146" + wire $eq$ls180.v:6474$2004_Y + attribute \src "ls180.v:6475.105-6475.149" + wire $eq$ls180.v:6475$2008_Y + attribute \src "ls180.v:6477.107-6477.151" + wire $eq$ls180.v:6477$2011_Y + attribute \src "ls180.v:6478.110-6478.154" + wire $eq$ls180.v:6478$2015_Y + attribute \src "ls180.v:6480.107-6480.151" + wire $eq$ls180.v:6480$2018_Y + attribute \src "ls180.v:6481.110-6481.154" + wire $eq$ls180.v:6481$2022_Y + attribute \src "ls180.v:6483.100-6483.144" + wire $eq$ls180.v:6483$2025_Y + attribute \src "ls180.v:6484.103-6484.147" + wire $eq$ls180.v:6484$2029_Y + attribute \src "ls180.v:6489.32-6489.77" + wire $eq$ls180.v:6489$2031_Y + attribute \src "ls180.v:6491.104-6491.148" + wire $eq$ls180.v:6491$2033_Y + attribute \src "ls180.v:6492.107-6492.151" + wire $eq$ls180.v:6492$2037_Y + attribute \src "ls180.v:6494.108-6494.152" + wire $eq$ls180.v:6494$2040_Y + attribute \src "ls180.v:6495.111-6495.155" + wire $eq$ls180.v:6495$2044_Y + attribute \src "ls180.v:6497.98-6497.142" + wire $eq$ls180.v:6497$2047_Y + attribute \src "ls180.v:6498.101-6498.145" + wire $eq$ls180.v:6498$2051_Y + attribute \src "ls180.v:6500.108-6500.152" + wire $eq$ls180.v:6500$2054_Y + attribute \src "ls180.v:6501.111-6501.155" + wire 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$eq$ls180.v:6630$2234_Y + attribute \src "ls180.v:6631.102-6631.147" + wire $eq$ls180.v:6631$2238_Y + attribute \src "ls180.v:6633.99-6633.144" + wire $eq$ls180.v:6633$2241_Y + attribute \src "ls180.v:6634.102-6634.147" + wire $eq$ls180.v:6634$2245_Y + attribute \src "ls180.v:6636.101-6636.146" + wire $eq$ls180.v:6636$2248_Y + attribute \src "ls180.v:6637.104-6637.149" + wire $eq$ls180.v:6637$2252_Y + attribute \src "ls180.v:6639.101-6639.146" + wire $eq$ls180.v:6639$2255_Y + attribute \src "ls180.v:6640.104-6640.149" + wire $eq$ls180.v:6640$2259_Y + attribute \src "ls180.v:6642.101-6642.146" + wire $eq$ls180.v:6642$2262_Y + attribute \src "ls180.v:6643.104-6643.149" + wire $eq$ls180.v:6643$2266_Y + attribute \src "ls180.v:6645.101-6645.146" + wire $eq$ls180.v:6645$2269_Y + attribute \src "ls180.v:6646.104-6646.149" + wire $eq$ls180.v:6646$2273_Y + attribute \src "ls180.v:6648.97-6648.142" + wire $eq$ls180.v:6648$2276_Y + attribute \src "ls180.v:6649.100-6649.145" + wire $eq$ls180.v:6649$2280_Y + attribute \src "ls180.v:6651.107-6651.152" + wire $eq$ls180.v:6651$2283_Y + attribute \src "ls180.v:6652.110-6652.155" + wire $eq$ls180.v:6652$2287_Y + attribute \src "ls180.v:6654.100-6654.146" + wire $eq$ls180.v:6654$2290_Y + attribute \src "ls180.v:6655.103-6655.149" + wire $eq$ls180.v:6655$2294_Y + attribute \src "ls180.v:6657.100-6657.146" + wire $eq$ls180.v:6657$2297_Y + attribute \src "ls180.v:6658.103-6658.149" + wire $eq$ls180.v:6658$2301_Y + attribute \src "ls180.v:6660.100-6660.146" + wire $eq$ls180.v:6660$2304_Y + attribute \src "ls180.v:6661.103-6661.149" + wire $eq$ls180.v:6661$2308_Y + attribute \src "ls180.v:6663.100-6663.146" + wire $eq$ls180.v:6663$2311_Y + attribute \src "ls180.v:6664.103-6664.149" + wire $eq$ls180.v:6664$2315_Y + attribute \src "ls180.v:6666.112-6666.158" + wire $eq$ls180.v:6666$2318_Y + attribute \src "ls180.v:6667.115-6667.161" + wire $eq$ls180.v:6667$2322_Y + attribute \src "ls180.v:6669.113-6669.159" + wire $eq$ls180.v:6669$2325_Y + attribute \src "ls180.v:6670.116-6670.162" + wire $eq$ls180.v:6670$2329_Y + attribute \src "ls180.v:6672.104-6672.150" + wire $eq$ls180.v:6672$2332_Y + attribute \src "ls180.v:6673.107-6673.153" + wire $eq$ls180.v:6673$2336_Y + attribute \src "ls180.v:6690.33-6690.79" + wire $eq$ls180.v:6690$2338_Y + attribute \src "ls180.v:6692.90-6692.135" + wire $eq$ls180.v:6692$2340_Y + attribute \src "ls180.v:6693.93-6693.138" + wire $eq$ls180.v:6693$2344_Y + attribute \src "ls180.v:6695.100-6695.145" + wire $eq$ls180.v:6695$2347_Y + attribute \src "ls180.v:6696.103-6696.148" + wire $eq$ls180.v:6696$2351_Y + attribute \src "ls180.v:6698.101-6698.146" + wire $eq$ls180.v:6698$2354_Y + attribute \src "ls180.v:6699.104-6699.149" + wire $eq$ls180.v:6699$2358_Y + attribute \src "ls180.v:6701.105-6701.150" + wire $eq$ls180.v:6701$2361_Y + attribute \src "ls180.v:6702.108-6702.153" + wire $eq$ls180.v:6702$2365_Y + attribute \src "ls180.v:6704.106-6704.151" + wire $eq$ls180.v:6704$2368_Y + attribute \src "ls180.v:6705.109-6705.154" + wire $eq$ls180.v:6705$2372_Y + attribute \src "ls180.v:6707.104-6707.149" + wire $eq$ls180.v:6707$2375_Y + attribute \src "ls180.v:6708.107-6708.152" + wire $eq$ls180.v:6708$2379_Y + attribute \src "ls180.v:6710.101-6710.146" + wire $eq$ls180.v:6710$2382_Y + attribute \src "ls180.v:6711.104-6711.149" + wire $eq$ls180.v:6711$2386_Y + attribute \src "ls180.v:6713.100-6713.145" + wire $eq$ls180.v:6713$2389_Y + attribute \src "ls180.v:6714.103-6714.148" + wire $eq$ls180.v:6714$2393_Y + attribute \src "ls180.v:6724.33-6724.79" + wire $eq$ls180.v:6724$2395_Y + attribute \src "ls180.v:6726.106-6726.151" + wire $eq$ls180.v:6726$2397_Y + attribute \src "ls180.v:6727.109-6727.154" + wire $eq$ls180.v:6727$2401_Y + attribute \src "ls180.v:6729.106-6729.151" + wire $eq$ls180.v:6729$2404_Y + attribute \src "ls180.v:6730.109-6730.154" + wire $eq$ls180.v:6730$2408_Y + attribute \src "ls180.v:6732.106-6732.151" + wire $eq$ls180.v:6732$2411_Y + attribute \src "ls180.v:6733.109-6733.154" + wire $eq$ls180.v:6733$2415_Y + attribute \src "ls180.v:6735.106-6735.151" + wire $eq$ls180.v:6735$2418_Y + attribute \src "ls180.v:6736.109-6736.154" + wire $eq$ls180.v:6736$2422_Y + attribute \src "ls180.v:7117.41-7117.81" + wire $eq$ls180.v:7117$2459_Y + attribute \src "ls180.v:7117.144-7117.177" + wire $eq$ls180.v:7117$2460_Y + attribute \src "ls180.v:7117.219-7117.252" + wire $eq$ls180.v:7117$2463_Y + attribute \src "ls180.v:7117.294-7117.327" + wire $eq$ls180.v:7117$2466_Y + attribute \src "ls180.v:7141.41-7141.81" + wire $eq$ls180.v:7141$2475_Y + attribute \src "ls180.v:7141.144-7141.177" + wire $eq$ls180.v:7141$2476_Y + attribute \src "ls180.v:7141.219-7141.252" + wire $eq$ls180.v:7141$2479_Y + attribute \src "ls180.v:7141.294-7141.327" + wire $eq$ls180.v:7141$2482_Y + attribute \src "ls180.v:7165.41-7165.81" + wire $eq$ls180.v:7165$2491_Y + attribute \src "ls180.v:7165.144-7165.177" + wire $eq$ls180.v:7165$2492_Y + attribute \src "ls180.v:7165.219-7165.252" + wire $eq$ls180.v:7165$2495_Y + attribute \src "ls180.v:7165.294-7165.327" + wire $eq$ls180.v:7165$2498_Y + attribute \src "ls180.v:7189.41-7189.81" + wire $eq$ls180.v:7189$2507_Y + attribute \src "ls180.v:7189.144-7189.177" + wire $eq$ls180.v:7189$2508_Y + attribute \src "ls180.v:7189.219-7189.252" + wire $eq$ls180.v:7189$2511_Y + attribute \src "ls180.v:7189.294-7189.327" + wire $eq$ls180.v:7189$2514_Y + attribute \src "ls180.v:7773.8-7773.38" + wire $eq$ls180.v:7773$2606_Y + attribute \src "ls180.v:7820.8-7820.42" + wire $eq$ls180.v:7820$2626_Y + attribute \src "ls180.v:7840.38-7840.74" + wire $eq$ls180.v:7840$2629_Y + attribute \src "ls180.v:7847.7-7847.43" + wire $eq$ls180.v:7847$2631_Y + attribute \src "ls180.v:7854.7-7854.43" + wire $eq$ls180.v:7854$2632_Y + attribute \src "ls180.v:7862.7-7862.43" + wire $eq$ls180.v:7862$2633_Y + attribute \src "ls180.v:7914.9-7914.54" + wire $eq$ls180.v:7914$2651_Y + attribute \src "ls180.v:7960.9-7960.54" + wire $eq$ls180.v:7960$2667_Y + attribute \src "ls180.v:8006.9-8006.54" + wire $eq$ls180.v:8006$2683_Y + attribute \src "ls180.v:8052.9-8052.54" + wire $eq$ls180.v:8052$2699_Y + attribute \src "ls180.v:8202.9-8202.41" + wire $eq$ls180.v:8202$2711_Y + attribute \src "ls180.v:8217.9-8217.41" + wire $eq$ls180.v:8217$2714_Y + attribute \src "ls180.v:8223.49-8223.82" + wire $eq$ls180.v:8223$2715_Y + attribute \src "ls180.v:8223.131-8223.164" + wire $eq$ls180.v:8223$2718_Y + attribute \src "ls180.v:8223.213-8223.246" + wire $eq$ls180.v:8223$2721_Y + attribute \src "ls180.v:8223.295-8223.328" + wire $eq$ls180.v:8223$2724_Y + attribute \src "ls180.v:8224.50-8224.83" + wire $eq$ls180.v:8224$2727_Y + attribute \src "ls180.v:8224.132-8224.165" + wire $eq$ls180.v:8224$2730_Y + attribute \src "ls180.v:8224.214-8224.247" + wire $eq$ls180.v:8224$2733_Y + attribute \src "ls180.v:8224.296-8224.329" + wire $eq$ls180.v:8224$2736_Y + attribute \src "ls180.v:8259.9-8259.42" + wire $eq$ls180.v:8259$2748_Y + attribute \src "ls180.v:8262.10-8262.43" + wire $eq$ls180.v:8262$2749_Y + attribute \src "ls180.v:8288.9-8288.42" + wire $eq$ls180.v:8288$2755_Y + attribute \src "ls180.v:8293.10-8293.43" + wire $eq$ls180.v:8293$2756_Y + attribute \src "ls180.v:8500.9-8500.53" + wire $eq$ls180.v:8500$2805_Y + attribute \src "ls180.v:8581.9-8581.54" + wire $eq$ls180.v:8581$2817_Y + attribute \src "ls180.v:8660.9-8660.55" + wire $eq$ls180.v:8660$2829_Y + attribute \src "ls180.v:8883.9-8883.49" + wire $eq$ls180.v:8883$2862_Y + attribute \src "ls180.v:8459.8-8459.54" + wire $ge$ls180.v:8459$2797_Y + attribute \src "ls180.v:8473.8-8473.54" + wire $ge$ls180.v:8473$2801_Y + attribute \src "ls180.v:5342.47-5342.83" + wire $gt$ls180.v:5342$1064_Y + attribute \src "ls180.v:5348.7-5348.43" + wire $lt$ls180.v:5348$1067_Y + attribute \src "ls180.v:8454.8-8454.43" + wire $lt$ls180.v:8454$2795_Y + attribute \src "ls180.v:8468.8-8468.43" + wire $lt$ls180.v:8468$2799_Y + attribute \src "ls180.v:10373.33-10373.36" + wire width 64 $memrd$\mem$ls180.v:10373$2916_DATA + attribute \src "ls180.v:10401.27-10401.32" + wire width 64 $memrd$\mem_1$ls180.v:10401$2942_DATA + attribute \src "ls180.v:10429.27-10429.32" + wire width 64 $memrd$\mem_2$ls180.v:10429$2968_DATA + attribute \src "ls180.v:10457.27-10457.32" + wire width 64 $memrd$\mem_3$ls180.v:10457$2994_DATA + attribute \src "ls180.v:10485.27-10485.32" + wire width 64 $memrd$\mem_4$ls180.v:10485$3020_DATA + attribute \src "ls180.v:10496.12-10496.19" + wire width 25 $memrd$\storage$ls180.v:10496$3025_DATA + attribute \src "ls180.v:10503.68-10503.75" + wire width 25 $memrd$\storage$ls180.v:10503$3027_DATA + attribute \src "ls180.v:10510.14-10510.23" + wire width 25 $memrd$\storage_1$ls180.v:10510$3032_DATA + attribute \src "ls180.v:10517.68-10517.77" + wire width 25 $memrd$\storage_1$ls180.v:10517$3034_DATA + attribute \src "ls180.v:10524.14-10524.23" + wire width 25 $memrd$\storage_2$ls180.v:10524$3039_DATA + attribute \src "ls180.v:10531.68-10531.77" + wire width 25 $memrd$\storage_2$ls180.v:10531$3041_DATA + attribute \src "ls180.v:10538.14-10538.23" + wire width 25 $memrd$\storage_3$ls180.v:10538$3046_DATA + attribute \src "ls180.v:10545.68-10545.77" + wire width 25 $memrd$\storage_3$ls180.v:10545$3048_DATA + attribute \src "ls180.v:10553.14-10553.23" + wire width 10 $memrd$\storage_4$ls180.v:10553$3053_DATA + attribute \src "ls180.v:10558.15-10558.24" + wire width 10 $memrd$\storage_4$ls180.v:10558$3055_DATA + attribute \src "ls180.v:10570.14-10570.23" + wire width 10 $memrd$\storage_5$ls180.v:10570$3060_DATA + attribute \src "ls180.v:10575.15-10575.24" + wire width 10 $memrd$\storage_5$ls180.v:10575$3062_DATA + attribute \src "ls180.v:10586.14-10586.23" + wire width 10 $memrd$\storage_6$ls180.v:10586$3067_DATA + attribute \src "ls180.v:10593.45-10593.54" + wire width 10 $memrd$\storage_6$ls180.v:10593$3069_DATA + attribute \src "ls180.v:10600.14-10600.23" + wire width 10 $memrd$\storage_7$ls180.v:10600$3074_DATA + attribute \src "ls180.v:10607.45-10607.54" + wire width 10 $memrd$\storage_7$ls180.v:10607$3076_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10355$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10355$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10355$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10357$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10357$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10357$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10359$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10359$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10359$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10361$4_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10162$1_ADDR + wire width 64 $memwr$\mem$ls180.v:10361$4_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10162$1_DATA + wire width 64 $memwr$\mem$ls180.v:10361$4_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10162$1_EN + wire width 6 $memwr$\mem$ls180.v:10363$5_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10164$2_ADDR + wire width 64 $memwr$\mem$ls180.v:10363$5_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10164$2_DATA + wire width 64 $memwr$\mem$ls180.v:10363$5_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10164$2_EN + wire width 6 $memwr$\mem$ls180.v:10365$6_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10166$3_ADDR + wire width 64 $memwr$\mem$ls180.v:10365$6_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10166$3_DATA + wire width 64 $memwr$\mem$ls180.v:10365$6_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10166$3_EN + wire width 6 $memwr$\mem$ls180.v:10367$7_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10168$4_ADDR + wire width 64 $memwr$\mem$ls180.v:10367$7_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10168$4_DATA + wire width 64 $memwr$\mem$ls180.v:10367$7_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10168$4_EN + wire width 6 $memwr$\mem$ls180.v:10369$8_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_1$ls180.v:10182$5_ADDR + wire width 64 $memwr$\mem$ls180.v:10369$8_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10182$5_DATA + wire width 64 $memwr$\mem$ls180.v:10369$8_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10182$5_EN + wire width 6 $memwr$\mem_1$ls180.v:10383$9_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_1$ls180.v:10184$6_ADDR + wire width 64 $memwr$\mem_1$ls180.v:10383$9_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10184$6_DATA + wire width 64 $memwr$\mem_1$ls180.v:10383$9_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10184$6_EN + wire width 6 $memwr$\mem_1$ls180.v:10385$10_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_1$ls180.v:10186$7_ADDR + wire width 64 $memwr$\mem_1$ls180.v:10385$10_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10186$7_DATA + wire width 64 $memwr$\mem_1$ls180.v:10385$10_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10186$7_EN + wire width 6 $memwr$\mem_1$ls180.v:10387$11_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_1$ls180.v:10188$8_ADDR + wire width 64 $memwr$\mem_1$ls180.v:10387$11_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10188$8_DATA + wire width 64 $memwr$\mem_1$ls180.v:10387$11_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10188$8_EN + wire width 6 $memwr$\mem_1$ls180.v:10389$12_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_2$ls180.v:10202$9_ADDR + wire width 64 $memwr$\mem_1$ls180.v:10389$12_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10202$9_DATA + wire width 64 $memwr$\mem_1$ls180.v:10389$12_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10202$9_EN + wire width 6 $memwr$\mem_1$ls180.v:10391$13_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_2$ls180.v:10204$10_ADDR + wire width 64 $memwr$\mem_1$ls180.v:10391$13_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10204$10_DATA + wire width 64 $memwr$\mem_1$ls180.v:10391$13_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10204$10_EN + wire width 6 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$memwr$\mem_3$ls180.v:10226$15_EN + wire width 6 $memwr$\mem_2$ls180.v:10415$19_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_3$ls180.v:10228$16_ADDR + wire width 64 $memwr$\mem_2$ls180.v:10415$19_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10228$16_DATA + wire width 64 $memwr$\mem_2$ls180.v:10415$19_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10228$16_EN + wire width 6 $memwr$\mem_2$ls180.v:10417$20_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage$ls180.v:10242$17_ADDR + wire width 64 $memwr$\mem_2$ls180.v:10417$20_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10242$17_DATA + wire width 64 $memwr$\mem_2$ls180.v:10417$20_EN attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10242$17_EN + wire width 6 $memwr$\mem_2$ls180.v:10419$21_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_1$ls180.v:10256$18_ADDR + wire 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$memwr$\mem_2$ls180.v:10423$23_EN attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10284$20_EN + wire width 6 $memwr$\mem_2$ls180.v:10425$24_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_4$ls180.v:10299$21_ADDR + wire width 64 $memwr$\mem_2$ls180.v:10425$24_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10299$21_DATA + wire width 64 $memwr$\mem_2$ls180.v:10425$24_EN attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10299$21_EN + wire width 6 $memwr$\mem_3$ls180.v:10439$25_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_5$ls180.v:10316$22_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10439$25_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10316$22_DATA + wire width 64 $memwr$\mem_3$ls180.v:10439$25_EN attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10316$22_EN + wire width 6 $memwr$\mem_3$ls180.v:10441$26_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_6$ls180.v:10332$23_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10441$26_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10332$23_DATA + wire width 64 $memwr$\mem_3$ls180.v:10441$26_EN attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10332$23_EN + wire width 6 $memwr$\mem_3$ls180.v:10443$27_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_7$ls180.v:10346$24_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10443$27_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10346$24_DATA + wire width 64 $memwr$\mem_3$ls180.v:10443$27_EN attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10346$24_EN - attribute \src "ls180.v:3010.41-3010.71" - wire $ne$ls180.v:3010$72_Y - attribute \src "ls180.v:3201.70-3201.104" - wire $ne$ls180.v:3201$125_Y - attribute \src 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"ls180.v:5034.360-5034.432" - wire $xor$ls180.v:5034$872_Y - attribute \src "ls180.v:5034.205-5034.277" - wire $xor$ls180.v:5034$873_Y - attribute \src "ls180.v:5034.164-5034.278" - wire $xor$ls180.v:5034$874_Y - attribute \src "ls180.v:5035.360-5035.432" - wire $xor$ls180.v:5035$875_Y - attribute \src "ls180.v:5035.205-5035.277" - wire $xor$ls180.v:5035$876_Y - attribute \src "ls180.v:5035.164-5035.278" - wire $xor$ls180.v:5035$877_Y - attribute \src "ls180.v:5036.360-5036.432" - wire $xor$ls180.v:5036$878_Y - attribute \src "ls180.v:5036.205-5036.277" - wire $xor$ls180.v:5036$879_Y - attribute \src "ls180.v:5036.164-5036.278" - wire $xor$ls180.v:5036$880_Y - attribute \src "ls180.v:5057.899-5057.983" - wire $xor$ls180.v:5057$894_Y - attribute \src "ls180.v:5057.634-5057.718" - wire $xor$ls180.v:5057$895_Y - attribute \src "ls180.v:5057.588-5057.719" - wire $xor$ls180.v:5057$896_Y - attribute \src "ls180.v:5057.234-5057.318" - wire $xor$ls180.v:5057$897_Y - attribute \src "ls180.v:5057.187-5057.319" - wire $xor$ls180.v:5057$898_Y - attribute \src "ls180.v:5058.899-5058.983" - wire $xor$ls180.v:5058$899_Y - attribute \src "ls180.v:5058.634-5058.718" - wire $xor$ls180.v:5058$900_Y - attribute \src "ls180.v:5058.588-5058.719" - wire $xor$ls180.v:5058$901_Y - attribute \src "ls180.v:5058.234-5058.318" - wire $xor$ls180.v:5058$902_Y - attribute \src "ls180.v:5058.187-5058.319" - wire $xor$ls180.v:5058$903_Y - attribute \src "ls180.v:5067.899-5067.983" - wire $xor$ls180.v:5067$905_Y - attribute \src "ls180.v:5067.634-5067.718" - wire $xor$ls180.v:5067$906_Y - attribute \src "ls180.v:5067.588-5067.719" - wire $xor$ls180.v:5067$907_Y - attribute \src "ls180.v:5067.234-5067.318" - wire $xor$ls180.v:5067$908_Y - attribute \src "ls180.v:5067.187-5067.319" - wire $xor$ls180.v:5067$909_Y - attribute \src "ls180.v:5068.899-5068.983" - wire $xor$ls180.v:5068$910_Y - attribute \src "ls180.v:5068.634-5068.718" - wire $xor$ls180.v:5068$911_Y - attribute \src "ls180.v:5068.588-5068.719" - wire $xor$ls180.v:5068$912_Y - attribute \src "ls180.v:5068.234-5068.318" - wire $xor$ls180.v:5068$913_Y - attribute \src "ls180.v:5068.187-5068.319" - wire $xor$ls180.v:5068$914_Y - attribute \src "ls180.v:5077.899-5077.983" - wire $xor$ls180.v:5077$916_Y - attribute \src "ls180.v:5077.634-5077.718" - wire $xor$ls180.v:5077$917_Y - attribute \src "ls180.v:5077.588-5077.719" - wire $xor$ls180.v:5077$918_Y - attribute \src "ls180.v:5077.234-5077.318" - wire $xor$ls180.v:5077$919_Y - attribute \src "ls180.v:5077.187-5077.319" - wire $xor$ls180.v:5077$920_Y - attribute \src "ls180.v:5078.899-5078.983" - wire $xor$ls180.v:5078$921_Y - attribute \src "ls180.v:5078.634-5078.718" - wire $xor$ls180.v:5078$922_Y - attribute \src "ls180.v:5078.588-5078.719" - wire $xor$ls180.v:5078$923_Y - attribute \src "ls180.v:5078.234-5078.318" - wire $xor$ls180.v:5078$924_Y - attribute \src "ls180.v:5078.187-5078.319" - wire $xor$ls180.v:5078$925_Y - attribute \src "ls180.v:5087.899-5087.983" - wire $xor$ls180.v:5087$927_Y - attribute \src "ls180.v:5087.634-5087.718" - wire $xor$ls180.v:5087$928_Y - attribute \src "ls180.v:5087.588-5087.719" - wire $xor$ls180.v:5087$929_Y - attribute \src "ls180.v:5087.234-5087.318" - wire $xor$ls180.v:5087$930_Y - attribute \src "ls180.v:5087.187-5087.319" - wire $xor$ls180.v:5087$931_Y - attribute \src "ls180.v:5088.899-5088.983" - wire $xor$ls180.v:5088$932_Y - attribute \src "ls180.v:5088.634-5088.718" - wire $xor$ls180.v:5088$933_Y - attribute \src "ls180.v:5088.588-5088.719" - wire $xor$ls180.v:5088$934_Y - attribute \src "ls180.v:5088.234-5088.318" - wire $xor$ls180.v:5088$935_Y - attribute \src "ls180.v:5088.187-5088.319" - wire $xor$ls180.v:5088$936_Y - attribute \src "ls180.v:5239.879-5239.961" - wire $xor$ls180.v:5239$969_Y - attribute \src "ls180.v:5239.620-5239.702" - wire $xor$ls180.v:5239$970_Y - attribute \src "ls180.v:5239.575-5239.703" - wire $xor$ls180.v:5239$971_Y - attribute \src "ls180.v:5239.229-5239.311" - wire $xor$ls180.v:5239$972_Y - attribute \src "ls180.v:5239.183-5239.312" - wire $xor$ls180.v:5239$973_Y - attribute \src "ls180.v:5240.879-5240.961" - wire $xor$ls180.v:5240$974_Y - attribute \src "ls180.v:5240.620-5240.702" - wire $xor$ls180.v:5240$975_Y - attribute \src "ls180.v:5240.575-5240.703" - wire $xor$ls180.v:5240$976_Y - attribute \src "ls180.v:5240.229-5240.311" - wire $xor$ls180.v:5240$977_Y - attribute \src "ls180.v:5240.183-5240.312" - wire $xor$ls180.v:5240$978_Y - attribute \src "ls180.v:5249.879-5249.961" - wire $xor$ls180.v:5249$980_Y - attribute \src "ls180.v:5249.620-5249.702" - wire $xor$ls180.v:5249$981_Y - attribute \src "ls180.v:5249.575-5249.703" - wire $xor$ls180.v:5249$982_Y - attribute \src "ls180.v:5249.229-5249.311" - wire $xor$ls180.v:5249$983_Y - attribute \src "ls180.v:5249.183-5249.312" - wire $xor$ls180.v:5249$984_Y - attribute \src "ls180.v:5250.879-5250.961" - wire $xor$ls180.v:5250$985_Y - attribute \src "ls180.v:5250.620-5250.702" - wire $xor$ls180.v:5250$986_Y - attribute \src "ls180.v:5250.575-5250.703" - wire $xor$ls180.v:5250$987_Y - attribute \src "ls180.v:5250.229-5250.311" - wire $xor$ls180.v:5250$988_Y - attribute \src "ls180.v:5250.183-5250.312" - wire $xor$ls180.v:5250$989_Y - attribute \src "ls180.v:5259.879-5259.961" - wire $xor$ls180.v:5259$991_Y - attribute \src "ls180.v:5259.620-5259.702" - wire $xor$ls180.v:5259$992_Y - attribute \src "ls180.v:5259.575-5259.703" - wire $xor$ls180.v:5259$993_Y - attribute \src "ls180.v:5259.229-5259.311" - wire $xor$ls180.v:5259$994_Y - attribute \src "ls180.v:5259.183-5259.312" - wire $xor$ls180.v:5259$995_Y - attribute \src "ls180.v:5260.183-5260.312" - wire $xor$ls180.v:5260$1000_Y - attribute \src "ls180.v:5260.879-5260.961" - wire $xor$ls180.v:5260$996_Y - attribute \src "ls180.v:5260.620-5260.702" - wire $xor$ls180.v:5260$997_Y - attribute \src "ls180.v:5260.575-5260.703" - wire $xor$ls180.v:5260$998_Y - attribute \src "ls180.v:5260.229-5260.311" - wire $xor$ls180.v:5260$999_Y - attribute \src "ls180.v:5269.879-5269.961" - wire $xor$ls180.v:5269$1002_Y - attribute \src "ls180.v:5269.620-5269.702" - wire $xor$ls180.v:5269$1003_Y - attribute \src "ls180.v:5269.575-5269.703" - wire $xor$ls180.v:5269$1004_Y - attribute \src "ls180.v:5269.229-5269.311" - wire $xor$ls180.v:5269$1005_Y - attribute \src "ls180.v:5269.183-5269.312" - wire $xor$ls180.v:5269$1006_Y - attribute \src "ls180.v:5270.879-5270.961" - wire $xor$ls180.v:5270$1007_Y - attribute \src "ls180.v:5270.620-5270.702" - wire $xor$ls180.v:5270$1008_Y - attribute \src "ls180.v:5270.575-5270.703" - wire $xor$ls180.v:5270$1009_Y - attribute \src "ls180.v:5270.229-5270.311" - wire $xor$ls180.v:5270$1010_Y - attribute \src "ls180.v:5270.183-5270.312" - wire $xor$ls180.v:5270$1011_Y - attribute \src "ls180.v:1790.11-1790.42" + wire $not$ls180.v:6241$1632_Y + attribute \src "ls180.v:6261.70-6261.101" + wire $not$ls180.v:6261$1640_Y + attribute \src "ls180.v:6264.70-6264.101" + wire $not$ls180.v:6264$1647_Y + attribute \src "ls180.v:6267.70-6267.101" + wire $not$ls180.v:6267$1654_Y + attribute \src "ls180.v:6270.70-6270.101" + wire $not$ls180.v:6270$1661_Y + attribute \src "ls180.v:6273.69-6273.100" + wire $not$ls180.v:6273$1668_Y + attribute \src "ls180.v:6276.69-6276.100" + wire $not$ls180.v:6276$1675_Y + attribute \src "ls180.v:6279.69-6279.100" + wire $not$ls180.v:6279$1682_Y + attribute \src "ls180.v:6282.69-6282.100" + wire $not$ls180.v:6282$1689_Y + attribute \src "ls180.v:6285.60-6285.91" + wire $not$ls180.v:6285$1696_Y + attribute \src "ls180.v:6288.71-6288.102" + wire $not$ls180.v:6288$1703_Y + attribute \src "ls180.v:6291.71-6291.102" + wire $not$ls180.v:6291$1710_Y + attribute \src "ls180.v:6294.71-6294.102" + wire $not$ls180.v:6294$1717_Y + attribute \src "ls180.v:6297.71-6297.102" + wire $not$ls180.v:6297$1724_Y + attribute \src "ls180.v:6300.71-6300.102" + wire $not$ls180.v:6300$1731_Y + attribute \src "ls180.v:6303.71-6303.102" + wire $not$ls180.v:6303$1738_Y + attribute \src "ls180.v:6306.70-6306.101" + wire $not$ls180.v:6306$1745_Y + attribute \src "ls180.v:6309.70-6309.101" + wire $not$ls180.v:6309$1752_Y + attribute \src "ls180.v:6312.70-6312.101" + wire $not$ls180.v:6312$1759_Y + attribute \src "ls180.v:6315.70-6315.101" + wire $not$ls180.v:6315$1766_Y + attribute \src "ls180.v:6318.70-6318.101" + wire $not$ls180.v:6318$1773_Y + attribute \src "ls180.v:6321.70-6321.101" + wire $not$ls180.v:6321$1780_Y + attribute \src "ls180.v:6324.70-6324.101" + wire $not$ls180.v:6324$1787_Y + attribute \src "ls180.v:6327.70-6327.101" + wire $not$ls180.v:6327$1794_Y + attribute \src "ls180.v:6330.70-6330.101" + wire $not$ls180.v:6330$1801_Y + attribute \src "ls180.v:6333.70-6333.101" + wire $not$ls180.v:6333$1808_Y + attribute \src "ls180.v:6336.66-6336.97" + wire $not$ls180.v:6336$1815_Y + attribute \src "ls180.v:6339.67-6339.98" + wire $not$ls180.v:6339$1822_Y + attribute \src "ls180.v:6342.70-6342.101" + wire $not$ls180.v:6342$1829_Y + attribute \src "ls180.v:6345.70-6345.101" + wire $not$ls180.v:6345$1836_Y + attribute \src "ls180.v:6348.69-6348.100" + wire $not$ls180.v:6348$1843_Y + attribute \src "ls180.v:6351.69-6351.100" + wire $not$ls180.v:6351$1850_Y + attribute \src "ls180.v:6354.69-6354.100" + wire $not$ls180.v:6354$1857_Y + attribute \src "ls180.v:6357.69-6357.100" + wire $not$ls180.v:6357$1864_Y + attribute \src "ls180.v:6396.66-6396.97" + wire $not$ls180.v:6396$1872_Y + attribute \src "ls180.v:6399.66-6399.97" + wire $not$ls180.v:6399$1879_Y + attribute \src "ls180.v:6402.66-6402.97" + wire $not$ls180.v:6402$1886_Y + attribute \src "ls180.v:6405.66-6405.97" + wire $not$ls180.v:6405$1893_Y + attribute \src "ls180.v:6408.66-6408.97" + wire $not$ls180.v:6408$1900_Y + attribute \src "ls180.v:6411.66-6411.97" + wire $not$ls180.v:6411$1907_Y + attribute \src "ls180.v:6414.66-6414.97" + wire $not$ls180.v:6414$1914_Y + attribute \src "ls180.v:6417.66-6417.97" + wire $not$ls180.v:6417$1921_Y + attribute \src "ls180.v:6420.68-6420.99" + wire $not$ls180.v:6420$1928_Y + attribute \src "ls180.v:6423.68-6423.99" + wire $not$ls180.v:6423$1935_Y + attribute \src "ls180.v:6426.68-6426.99" + wire $not$ls180.v:6426$1942_Y + attribute \src "ls180.v:6429.68-6429.99" + wire $not$ls180.v:6429$1949_Y + attribute \src "ls180.v:6432.68-6432.99" + wire $not$ls180.v:6432$1956_Y + attribute \src "ls180.v:6435.65-6435.96" + wire $not$ls180.v:6435$1963_Y + attribute \src "ls180.v:6438.66-6438.97" + wire $not$ls180.v:6438$1970_Y + attribute \src "ls180.v:6441.68-6441.99" + wire $not$ls180.v:6441$1977_Y + attribute \src "ls180.v:6444.68-6444.99" + wire $not$ls180.v:6444$1984_Y + attribute \src "ls180.v:6447.68-6447.99" + wire $not$ls180.v:6447$1991_Y + attribute \src "ls180.v:6450.68-6450.99" + wire $not$ls180.v:6450$1998_Y + attribute \src "ls180.v:6475.68-6475.99" + wire $not$ls180.v:6475$2006_Y + attribute \src "ls180.v:6478.73-6478.104" + wire $not$ls180.v:6478$2013_Y + attribute \src "ls180.v:6481.73-6481.104" + wire $not$ls180.v:6481$2020_Y + attribute \src "ls180.v:6484.66-6484.97" + wire $not$ls180.v:6484$2027_Y + attribute \src "ls180.v:6492.70-6492.101" + wire $not$ls180.v:6492$2035_Y + attribute \src "ls180.v:6495.74-6495.105" + wire $not$ls180.v:6495$2042_Y + attribute \src "ls180.v:6498.64-6498.95" + wire $not$ls180.v:6498$2049_Y + attribute \src "ls180.v:6501.74-6501.105" + wire $not$ls180.v:6501$2056_Y + attribute \src "ls180.v:6504.74-6504.105" + wire $not$ls180.v:6504$2063_Y + attribute \src "ls180.v:6507.75-6507.106" + wire $not$ls180.v:6507$2070_Y + attribute \src "ls180.v:6510.73-6510.104" + wire $not$ls180.v:6510$2077_Y + attribute \src "ls180.v:6513.73-6513.104" + wire $not$ls180.v:6513$2084_Y + attribute \src "ls180.v:6516.73-6516.104" + wire $not$ls180.v:6516$2091_Y + attribute \src "ls180.v:6519.73-6519.104" + wire $not$ls180.v:6519$2098_Y + attribute \src "ls180.v:6537.67-6537.99" + wire $not$ls180.v:6537$2106_Y + attribute \src "ls180.v:6540.67-6540.99" + wire $not$ls180.v:6540$2113_Y + attribute \src "ls180.v:6543.65-6543.97" + wire $not$ls180.v:6543$2120_Y + attribute \src "ls180.v:6546.64-6546.96" + wire $not$ls180.v:6546$2127_Y + attribute \src "ls180.v:6549.63-6549.95" + wire $not$ls180.v:6549$2134_Y + attribute \src "ls180.v:6552.62-6552.94" + wire $not$ls180.v:6552$2141_Y + attribute \src "ls180.v:6555.68-6555.100" + wire $not$ls180.v:6555$2148_Y + attribute \src "ls180.v:6577.67-6577.99" + wire $not$ls180.v:6577$2157_Y + attribute \src "ls180.v:6580.67-6580.99" + wire $not$ls180.v:6580$2164_Y + attribute \src "ls180.v:6583.65-6583.97" + wire $not$ls180.v:6583$2171_Y + attribute \src "ls180.v:6586.64-6586.96" + wire $not$ls180.v:6586$2178_Y + attribute \src "ls180.v:6589.63-6589.95" + wire $not$ls180.v:6589$2185_Y + attribute \src "ls180.v:6592.62-6592.94" + wire $not$ls180.v:6592$2192_Y + attribute \src "ls180.v:6595.68-6595.100" + wire $not$ls180.v:6595$2199_Y + attribute \src "ls180.v:6598.71-6598.103" + wire $not$ls180.v:6598$2206_Y + attribute \src "ls180.v:6601.71-6601.103" + wire $not$ls180.v:6601$2213_Y + attribute \src "ls180.v:6625.64-6625.96" + wire $not$ls180.v:6625$2222_Y + attribute \src "ls180.v:6628.64-6628.96" + wire $not$ls180.v:6628$2229_Y + attribute \src "ls180.v:6631.64-6631.96" + wire $not$ls180.v:6631$2236_Y + attribute \src "ls180.v:6634.64-6634.96" + wire $not$ls180.v:6634$2243_Y + attribute \src "ls180.v:6637.66-6637.98" + wire $not$ls180.v:6637$2250_Y + attribute \src "ls180.v:6640.66-6640.98" + wire $not$ls180.v:6640$2257_Y + attribute \src "ls180.v:6643.66-6643.98" + wire $not$ls180.v:6643$2264_Y + attribute \src "ls180.v:6646.66-6646.98" + wire $not$ls180.v:6646$2271_Y + attribute \src "ls180.v:6649.62-6649.94" + wire $not$ls180.v:6649$2278_Y + attribute \src "ls180.v:6652.72-6652.104" + wire $not$ls180.v:6652$2285_Y + attribute \src "ls180.v:6655.65-6655.97" + wire $not$ls180.v:6655$2292_Y + attribute \src "ls180.v:6658.65-6658.97" + wire $not$ls180.v:6658$2299_Y + attribute \src "ls180.v:6661.65-6661.97" + wire $not$ls180.v:6661$2306_Y + attribute \src "ls180.v:6664.65-6664.97" + wire $not$ls180.v:6664$2313_Y + attribute \src "ls180.v:6667.77-6667.109" + wire $not$ls180.v:6667$2320_Y + attribute \src "ls180.v:6670.78-6670.110" + wire $not$ls180.v:6670$2327_Y + attribute \src "ls180.v:6673.69-6673.101" + wire $not$ls180.v:6673$2334_Y + attribute \src "ls180.v:6693.55-6693.87" + wire $not$ls180.v:6693$2342_Y + attribute \src "ls180.v:6696.65-6696.97" + wire $not$ls180.v:6696$2349_Y + attribute \src "ls180.v:6699.66-6699.98" + wire $not$ls180.v:6699$2356_Y + attribute \src "ls180.v:6702.70-6702.102" + wire $not$ls180.v:6702$2363_Y + attribute \src "ls180.v:6705.71-6705.103" + wire $not$ls180.v:6705$2370_Y + attribute \src "ls180.v:6708.69-6708.101" + wire $not$ls180.v:6708$2377_Y + attribute \src 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$xor$ls180.v:5119$880_Y + attribute \src "ls180.v:5120.353-5120.425" + wire $xor$ls180.v:5120$881_Y + attribute \src "ls180.v:5120.200-5120.272" + wire $xor$ls180.v:5120$882_Y + attribute \src "ls180.v:5120.160-5120.273" + wire $xor$ls180.v:5120$883_Y + attribute \src "ls180.v:5121.353-5121.425" + wire $xor$ls180.v:5121$884_Y + attribute \src "ls180.v:5121.200-5121.272" + wire $xor$ls180.v:5121$885_Y + attribute \src "ls180.v:5121.160-5121.273" + wire $xor$ls180.v:5121$886_Y + attribute \src "ls180.v:5122.354-5122.426" + wire $xor$ls180.v:5122$887_Y + attribute \src "ls180.v:5122.201-5122.273" + wire $xor$ls180.v:5122$888_Y + attribute \src "ls180.v:5122.161-5122.274" + wire $xor$ls180.v:5122$889_Y + attribute \src "ls180.v:5123.361-5123.434" + wire $xor$ls180.v:5123$890_Y + attribute \src "ls180.v:5123.205-5123.278" + wire $xor$ls180.v:5123$891_Y + attribute \src "ls180.v:5123.164-5123.279" + wire $xor$ls180.v:5123$892_Y + attribute \src "ls180.v:5124.361-5124.434" + wire $xor$ls180.v:5124$893_Y + attribute \src "ls180.v:5124.205-5124.278" + wire $xor$ls180.v:5124$894_Y + attribute \src "ls180.v:5124.164-5124.279" + wire $xor$ls180.v:5124$895_Y + attribute \src "ls180.v:5125.361-5125.434" + wire $xor$ls180.v:5125$896_Y + attribute \src "ls180.v:5125.205-5125.278" + wire $xor$ls180.v:5125$897_Y + attribute \src "ls180.v:5125.164-5125.279" + wire $xor$ls180.v:5125$898_Y + attribute \src "ls180.v:5126.361-5126.434" + wire $xor$ls180.v:5126$899_Y + attribute \src "ls180.v:5126.205-5126.278" + wire $xor$ls180.v:5126$900_Y + attribute \src "ls180.v:5126.164-5126.279" + wire $xor$ls180.v:5126$901_Y + attribute \src "ls180.v:5127.361-5127.434" + wire $xor$ls180.v:5127$902_Y + attribute \src "ls180.v:5127.205-5127.278" + wire $xor$ls180.v:5127$903_Y + attribute \src "ls180.v:5127.164-5127.279" + wire $xor$ls180.v:5127$904_Y + attribute \src "ls180.v:5128.361-5128.434" + wire $xor$ls180.v:5128$905_Y + attribute \src "ls180.v:5128.205-5128.278" + wire $xor$ls180.v:5128$906_Y + attribute \src "ls180.v:5128.164-5128.279" + wire $xor$ls180.v:5128$907_Y + attribute \src "ls180.v:5129.361-5129.434" + wire $xor$ls180.v:5129$908_Y + attribute \src "ls180.v:5129.205-5129.278" + wire $xor$ls180.v:5129$909_Y + attribute \src "ls180.v:5129.164-5129.279" + wire $xor$ls180.v:5129$910_Y + attribute \src "ls180.v:5130.361-5130.434" + wire $xor$ls180.v:5130$911_Y + attribute \src "ls180.v:5130.205-5130.278" + wire $xor$ls180.v:5130$912_Y + attribute \src "ls180.v:5130.164-5130.279" + wire $xor$ls180.v:5130$913_Y + attribute \src "ls180.v:5131.361-5131.434" + wire $xor$ls180.v:5131$914_Y + attribute \src "ls180.v:5131.205-5131.278" + wire $xor$ls180.v:5131$915_Y + attribute \src "ls180.v:5131.164-5131.279" + wire $xor$ls180.v:5131$916_Y + attribute \src "ls180.v:5132.361-5132.434" + wire $xor$ls180.v:5132$917_Y + attribute \src "ls180.v:5132.205-5132.278" + wire $xor$ls180.v:5132$918_Y + attribute \src "ls180.v:5132.164-5132.279" + wire $xor$ls180.v:5132$919_Y + attribute \src "ls180.v:5133.361-5133.434" + wire $xor$ls180.v:5133$920_Y + attribute \src "ls180.v:5133.205-5133.278" + wire $xor$ls180.v:5133$921_Y + attribute \src "ls180.v:5133.164-5133.279" + wire $xor$ls180.v:5133$922_Y + attribute \src "ls180.v:5134.361-5134.434" + wire $xor$ls180.v:5134$923_Y + attribute \src "ls180.v:5134.205-5134.278" + wire $xor$ls180.v:5134$924_Y + attribute \src "ls180.v:5134.164-5134.279" + wire $xor$ls180.v:5134$925_Y + attribute \src "ls180.v:5135.361-5135.434" + wire $xor$ls180.v:5135$926_Y + attribute \src "ls180.v:5135.205-5135.278" + wire $xor$ls180.v:5135$927_Y + attribute \src "ls180.v:5135.164-5135.279" + wire $xor$ls180.v:5135$928_Y + attribute \src "ls180.v:5136.361-5136.434" + wire $xor$ls180.v:5136$929_Y + attribute \src "ls180.v:5136.205-5136.278" + wire $xor$ls180.v:5136$930_Y + attribute \src "ls180.v:5136.164-5136.279" + wire $xor$ls180.v:5136$931_Y + attribute \src "ls180.v:5137.361-5137.434" + wire $xor$ls180.v:5137$932_Y + attribute \src "ls180.v:5137.205-5137.278" + wire $xor$ls180.v:5137$933_Y + attribute \src "ls180.v:5137.164-5137.279" + wire $xor$ls180.v:5137$934_Y + attribute \src "ls180.v:5138.361-5138.434" + wire $xor$ls180.v:5138$935_Y + attribute \src "ls180.v:5138.205-5138.278" + wire $xor$ls180.v:5138$936_Y + attribute \src "ls180.v:5138.164-5138.279" + wire $xor$ls180.v:5138$937_Y + attribute \src "ls180.v:5139.361-5139.434" + wire $xor$ls180.v:5139$938_Y + attribute \src "ls180.v:5139.205-5139.278" + wire $xor$ls180.v:5139$939_Y + attribute \src "ls180.v:5139.164-5139.279" + wire $xor$ls180.v:5139$940_Y + attribute \src "ls180.v:5140.361-5140.434" + wire $xor$ls180.v:5140$941_Y + attribute \src "ls180.v:5140.205-5140.278" + wire $xor$ls180.v:5140$942_Y + attribute \src "ls180.v:5140.164-5140.279" + wire $xor$ls180.v:5140$943_Y + attribute \src "ls180.v:5141.361-5141.434" + wire $xor$ls180.v:5141$944_Y + attribute \src "ls180.v:5141.205-5141.278" + wire $xor$ls180.v:5141$945_Y + attribute \src "ls180.v:5141.164-5141.279" + wire $xor$ls180.v:5141$946_Y + attribute \src "ls180.v:5142.361-5142.434" + wire $xor$ls180.v:5142$947_Y + attribute \src "ls180.v:5142.205-5142.278" + wire $xor$ls180.v:5142$948_Y + attribute \src "ls180.v:5142.164-5142.279" + wire $xor$ls180.v:5142$949_Y + attribute \src "ls180.v:5143.360-5143.432" + wire $xor$ls180.v:5143$950_Y + attribute \src "ls180.v:5143.205-5143.277" + wire $xor$ls180.v:5143$951_Y + attribute \src "ls180.v:5143.164-5143.278" + wire $xor$ls180.v:5143$952_Y + attribute \src "ls180.v:5144.360-5144.432" + wire $xor$ls180.v:5144$953_Y + attribute \src "ls180.v:5144.205-5144.277" + wire $xor$ls180.v:5144$954_Y + attribute \src "ls180.v:5144.164-5144.278" + wire $xor$ls180.v:5144$955_Y + attribute \src "ls180.v:5145.360-5145.432" + wire $xor$ls180.v:5145$956_Y + attribute \src "ls180.v:5145.205-5145.277" + wire $xor$ls180.v:5145$957_Y + attribute \src "ls180.v:5145.164-5145.278" + wire $xor$ls180.v:5145$958_Y + attribute \src "ls180.v:5146.360-5146.432" + wire $xor$ls180.v:5146$959_Y + attribute \src "ls180.v:5146.205-5146.277" + wire $xor$ls180.v:5146$960_Y + attribute \src "ls180.v:5146.164-5146.278" + wire $xor$ls180.v:5146$961_Y + attribute \src "ls180.v:5147.360-5147.432" + wire $xor$ls180.v:5147$962_Y + attribute \src "ls180.v:5147.205-5147.277" + wire $xor$ls180.v:5147$963_Y + attribute \src "ls180.v:5147.164-5147.278" + wire $xor$ls180.v:5147$964_Y + attribute \src "ls180.v:5148.360-5148.432" + wire $xor$ls180.v:5148$965_Y + attribute \src "ls180.v:5148.205-5148.277" + wire $xor$ls180.v:5148$966_Y + attribute \src "ls180.v:5148.164-5148.278" + wire $xor$ls180.v:5148$967_Y + attribute \src "ls180.v:5149.360-5149.432" + wire $xor$ls180.v:5149$968_Y + attribute \src "ls180.v:5149.205-5149.277" + wire $xor$ls180.v:5149$969_Y + attribute \src "ls180.v:5149.164-5149.278" + wire $xor$ls180.v:5149$970_Y + attribute \src "ls180.v:5150.360-5150.432" + wire $xor$ls180.v:5150$971_Y + attribute \src "ls180.v:5150.205-5150.277" + wire $xor$ls180.v:5150$972_Y + attribute \src "ls180.v:5150.164-5150.278" + wire $xor$ls180.v:5150$973_Y + attribute \src "ls180.v:5151.360-5151.432" + wire $xor$ls180.v:5151$974_Y + attribute \src "ls180.v:5151.205-5151.277" + wire $xor$ls180.v:5151$975_Y + attribute \src "ls180.v:5151.164-5151.278" + wire $xor$ls180.v:5151$976_Y + attribute \src "ls180.v:5152.360-5152.432" + wire $xor$ls180.v:5152$977_Y + attribute \src "ls180.v:5152.205-5152.277" + wire $xor$ls180.v:5152$978_Y + attribute \src "ls180.v:5152.164-5152.278" + wire $xor$ls180.v:5152$979_Y + attribute \src "ls180.v:5173.899-5173.983" + wire $xor$ls180.v:5173$993_Y + attribute \src "ls180.v:5173.634-5173.718" + wire $xor$ls180.v:5173$994_Y + attribute \src "ls180.v:5173.588-5173.719" + wire $xor$ls180.v:5173$995_Y + attribute \src "ls180.v:5173.234-5173.318" + wire $xor$ls180.v:5173$996_Y + attribute \src "ls180.v:5173.187-5173.319" + wire $xor$ls180.v:5173$997_Y + attribute \src "ls180.v:5174.588-5174.719" + wire $xor$ls180.v:5174$1000_Y + attribute \src "ls180.v:5174.234-5174.318" + wire $xor$ls180.v:5174$1001_Y + attribute \src "ls180.v:5174.187-5174.319" + wire $xor$ls180.v:5174$1002_Y + attribute \src "ls180.v:5174.899-5174.983" + wire $xor$ls180.v:5174$998_Y + attribute \src "ls180.v:5174.634-5174.718" + wire $xor$ls180.v:5174$999_Y + attribute \src "ls180.v:5183.899-5183.983" + wire $xor$ls180.v:5183$1004_Y + attribute \src "ls180.v:5183.634-5183.718" + wire $xor$ls180.v:5183$1005_Y + attribute \src "ls180.v:5183.588-5183.719" + wire $xor$ls180.v:5183$1006_Y + attribute \src "ls180.v:5183.234-5183.318" + wire $xor$ls180.v:5183$1007_Y + attribute \src "ls180.v:5183.187-5183.319" + wire $xor$ls180.v:5183$1008_Y + attribute \src "ls180.v:5184.899-5184.983" + wire $xor$ls180.v:5184$1009_Y + attribute \src "ls180.v:5184.634-5184.718" + wire $xor$ls180.v:5184$1010_Y + attribute \src "ls180.v:5184.588-5184.719" + wire $xor$ls180.v:5184$1011_Y + attribute \src "ls180.v:5184.234-5184.318" + wire $xor$ls180.v:5184$1012_Y + attribute \src "ls180.v:5184.187-5184.319" + wire $xor$ls180.v:5184$1013_Y + attribute \src "ls180.v:5193.899-5193.983" + wire $xor$ls180.v:5193$1015_Y + attribute \src "ls180.v:5193.634-5193.718" + wire $xor$ls180.v:5193$1016_Y + attribute \src "ls180.v:5193.588-5193.719" + wire $xor$ls180.v:5193$1017_Y + attribute \src "ls180.v:5193.234-5193.318" + wire $xor$ls180.v:5193$1018_Y + attribute \src "ls180.v:5193.187-5193.319" + wire $xor$ls180.v:5193$1019_Y + attribute \src "ls180.v:5194.899-5194.983" + wire $xor$ls180.v:5194$1020_Y + attribute \src "ls180.v:5194.634-5194.718" + wire $xor$ls180.v:5194$1021_Y + attribute \src "ls180.v:5194.588-5194.719" + wire $xor$ls180.v:5194$1022_Y + attribute \src "ls180.v:5194.234-5194.318" + wire $xor$ls180.v:5194$1023_Y + attribute \src "ls180.v:5194.187-5194.319" + wire $xor$ls180.v:5194$1024_Y + attribute \src "ls180.v:5203.899-5203.983" + wire $xor$ls180.v:5203$1026_Y + attribute \src "ls180.v:5203.634-5203.718" + wire $xor$ls180.v:5203$1027_Y + attribute \src "ls180.v:5203.588-5203.719" + wire $xor$ls180.v:5203$1028_Y + attribute \src "ls180.v:5203.234-5203.318" + wire $xor$ls180.v:5203$1029_Y + attribute \src "ls180.v:5203.187-5203.319" + wire $xor$ls180.v:5203$1030_Y + attribute \src "ls180.v:5204.899-5204.983" + wire $xor$ls180.v:5204$1031_Y + attribute \src "ls180.v:5204.634-5204.718" + wire $xor$ls180.v:5204$1032_Y + attribute \src "ls180.v:5204.588-5204.719" + wire $xor$ls180.v:5204$1033_Y + attribute \src "ls180.v:5204.234-5204.318" + wire $xor$ls180.v:5204$1034_Y + attribute \src "ls180.v:5204.187-5204.319" + wire $xor$ls180.v:5204$1035_Y + attribute \src "ls180.v:5355.879-5355.961" + wire $xor$ls180.v:5355$1068_Y + attribute \src "ls180.v:5355.620-5355.702" + wire $xor$ls180.v:5355$1069_Y + attribute \src "ls180.v:5355.575-5355.703" + wire $xor$ls180.v:5355$1070_Y + attribute \src "ls180.v:5355.229-5355.311" + wire $xor$ls180.v:5355$1071_Y + attribute \src "ls180.v:5355.183-5355.312" + wire $xor$ls180.v:5355$1072_Y + attribute \src "ls180.v:5356.879-5356.961" + wire $xor$ls180.v:5356$1073_Y + attribute \src "ls180.v:5356.620-5356.702" + wire $xor$ls180.v:5356$1074_Y + attribute \src "ls180.v:5356.575-5356.703" + wire $xor$ls180.v:5356$1075_Y + attribute \src "ls180.v:5356.229-5356.311" + wire $xor$ls180.v:5356$1076_Y + attribute \src "ls180.v:5356.183-5356.312" + wire $xor$ls180.v:5356$1077_Y + attribute \src "ls180.v:5365.879-5365.961" + wire $xor$ls180.v:5365$1079_Y + attribute \src "ls180.v:5365.620-5365.702" + wire $xor$ls180.v:5365$1080_Y + attribute \src "ls180.v:5365.575-5365.703" + wire $xor$ls180.v:5365$1081_Y + attribute \src "ls180.v:5365.229-5365.311" + wire $xor$ls180.v:5365$1082_Y + attribute \src "ls180.v:5365.183-5365.312" + wire $xor$ls180.v:5365$1083_Y + attribute \src "ls180.v:5366.879-5366.961" + wire $xor$ls180.v:5366$1084_Y + attribute \src "ls180.v:5366.620-5366.702" + wire $xor$ls180.v:5366$1085_Y + attribute \src "ls180.v:5366.575-5366.703" + wire $xor$ls180.v:5366$1086_Y + attribute \src "ls180.v:5366.229-5366.311" + wire $xor$ls180.v:5366$1087_Y + attribute \src "ls180.v:5366.183-5366.312" + wire $xor$ls180.v:5366$1088_Y + attribute \src "ls180.v:5375.879-5375.961" + wire $xor$ls180.v:5375$1090_Y + attribute \src "ls180.v:5375.620-5375.702" + wire $xor$ls180.v:5375$1091_Y + attribute \src "ls180.v:5375.575-5375.703" + wire $xor$ls180.v:5375$1092_Y + attribute \src "ls180.v:5375.229-5375.311" + wire $xor$ls180.v:5375$1093_Y + attribute \src "ls180.v:5375.183-5375.312" + wire $xor$ls180.v:5375$1094_Y + attribute \src "ls180.v:5376.879-5376.961" + wire $xor$ls180.v:5376$1095_Y + attribute \src "ls180.v:5376.620-5376.702" + wire $xor$ls180.v:5376$1096_Y + attribute \src "ls180.v:5376.575-5376.703" + wire $xor$ls180.v:5376$1097_Y + attribute \src "ls180.v:5376.229-5376.311" + wire $xor$ls180.v:5376$1098_Y + attribute \src "ls180.v:5376.183-5376.312" + wire $xor$ls180.v:5376$1099_Y + attribute \src "ls180.v:5385.879-5385.961" + wire $xor$ls180.v:5385$1101_Y + attribute \src "ls180.v:5385.620-5385.702" + wire $xor$ls180.v:5385$1102_Y + attribute \src "ls180.v:5385.575-5385.703" + wire $xor$ls180.v:5385$1103_Y + attribute \src "ls180.v:5385.229-5385.311" + wire $xor$ls180.v:5385$1104_Y + attribute \src "ls180.v:5385.183-5385.312" + wire $xor$ls180.v:5385$1105_Y + attribute \src "ls180.v:5386.879-5386.961" + wire $xor$ls180.v:5386$1106_Y + attribute \src "ls180.v:5386.620-5386.702" + wire $xor$ls180.v:5386$1107_Y + attribute \src "ls180.v:5386.575-5386.703" + wire $xor$ls180.v:5386$1108_Y + attribute \src "ls180.v:5386.229-5386.311" + wire $xor$ls180.v:5386$1109_Y + attribute \src "ls180.v:5386.183-5386.312" + wire $xor$ls180.v:5386$1110_Y + attribute \src "ls180.v:1857.11-1857.42" wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1789.11-1789.37" + attribute \src "ls180.v:1856.11-1856.37" wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1792.11-1792.42" + attribute \src "ls180.v:1859.11-1859.42" wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1791.11-1791.37" + attribute \src "ls180.v:1858.11-1858.37" wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1794.11-1794.42" + attribute \src "ls180.v:1861.11-1861.42" wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1793.11-1793.37" + attribute \src "ls180.v:1860.11-1860.37" wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1796.11-1796.42" + attribute \src "ls180.v:1863.11-1863.42" wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1795.11-1795.37" + attribute \src "ls180.v:1862.11-1862.37" wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2641.5-2641.34" + attribute \src "ls180.v:2716.5-2716.34" wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2642.12-2642.41" + attribute \src "ls180.v:2717.12-2717.41" wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2654.5-2654.35" + attribute \src "ls180.v:2729.5-2729.35" wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2655.5-2655.35" + attribute \src "ls180.v:2730.5-2730.35" wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2659.12-2659.42" + attribute \src "ls180.v:2734.12-2734.42" wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2660.5-2660.35" + attribute \src "ls180.v:2735.5-2735.35" wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2661.5-2661.35" + attribute \src "ls180.v:2736.5-2736.35" wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2662.12-2662.42" + attribute \src "ls180.v:2737.12-2737.42" wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2663.5-2663.35" + attribute \src "ls180.v:2738.5-2738.35" wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2664.5-2664.35" + attribute \src "ls180.v:2739.5-2739.35" wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2665.12-2665.42" + attribute \src "ls180.v:2740.12-2740.42" wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2666.5-2666.35" + attribute \src "ls180.v:2741.5-2741.35" wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2643.11-2643.40" + attribute \src "ls180.v:2718.11-2718.40" wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2667.5-2667.35" + attribute \src "ls180.v:2742.5-2742.35" wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2668.12-2668.42" + attribute \src "ls180.v:2743.12-2743.42" wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2669.5-2669.35" + attribute \src "ls180.v:2744.5-2744.35" wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2670.5-2670.35" + attribute \src "ls180.v:2745.5-2745.35" wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2671.12-2671.42" + attribute \src "ls180.v:2746.12-2746.42" wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2672.12-2672.42" - wire width 32 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2673.11-2673.41" - wire width 4 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2674.5-2674.35" + attribute \src "ls180.v:2747.12-2747.42" + wire width 64 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2748.11-2748.41" + wire width 8 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2749.5-2749.35" wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2675.5-2675.35" + attribute \src "ls180.v:2750.5-2750.35" wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2676.5-2676.35" + attribute \src "ls180.v:2751.5-2751.35" wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2644.5-2644.34" + attribute \src "ls180.v:2719.5-2719.34" wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2677.11-2677.41" + attribute \src "ls180.v:2752.11-2752.41" wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2678.11-2678.41" + attribute \src "ls180.v:2753.11-2753.41" wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2645.5-2645.34" + attribute \src "ls180.v:2720.5-2720.34" wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2646.5-2646.34" + attribute \src "ls180.v:2721.5-2721.34" wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2650.5-2650.34" + attribute \src "ls180.v:2725.5-2725.34" wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2651.12-2651.41" + attribute \src "ls180.v:2726.12-2726.41" wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2652.11-2652.40" + attribute \src "ls180.v:2727.11-2727.40" wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2653.5-2653.34" + attribute \src "ls180.v:2728.5-2728.34" wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2647.5-2647.32" + attribute \src "ls180.v:2722.5-2722.32" wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2648.5-2648.32" + attribute \src "ls180.v:2723.5-2723.32" wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2649.5-2649.32" + attribute \src "ls180.v:2724.5-2724.32" wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2656.5-2656.32" + attribute \src "ls180.v:2731.5-2731.32" wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2657.5-2657.32" + attribute \src "ls180.v:2732.5-2732.32" wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2658.5-2658.32" + attribute \src "ls180.v:2733.5-2733.32" wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1776.5-1776.34" + attribute \src "ls180.v:1843.5-1843.34" wire \builder_converter0_next_state - attribute \src "ls180.v:1775.5-1775.29" + attribute \src "ls180.v:1842.5-1842.29" wire \builder_converter0_state - attribute \src "ls180.v:1780.5-1780.34" + attribute \src "ls180.v:1847.5-1847.34" wire \builder_converter1_next_state - attribute \src "ls180.v:1779.5-1779.29" + attribute \src "ls180.v:1846.5-1846.29" wire \builder_converter1_state - attribute \src "ls180.v:1784.5-1784.34" + attribute \src "ls180.v:1851.5-1851.34" wire \builder_converter2_next_state - attribute \src "ls180.v:1783.5-1783.29" + attribute \src "ls180.v:1850.5-1850.29" wire \builder_converter2_state - attribute \src "ls180.v:1821.5-1821.33" + attribute \src "ls180.v:1888.5-1888.33" wire \builder_converter_next_state - attribute \src "ls180.v:1820.5-1820.28" + attribute \src "ls180.v:1887.5-1887.28" wire \builder_converter_state - attribute \src "ls180.v:1941.12-1941.25" + attribute \src "ls180.v:2016.12-2016.25" wire width 20 \builder_count - attribute \src "ls180.v:2629.13-2629.41" + attribute \src "ls180.v:2704.13-2704.41" wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2632.12-2632.42" + attribute \src "ls180.v:2707.12-2707.42" wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2631.12-2631.42" + attribute \src "ls180.v:2706.12-2706.42" wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2630.6-2630.33" + attribute \src "ls180.v:2705.6-2705.33" wire \builder_csr_interconnect_we - attribute \src "ls180.v:1979.12-1979.42" + attribute \src "ls180.v:2054.12-2054.42" wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1978.6-1978.37" + attribute \src "ls180.v:2053.6-2053.37" wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1981.12-1981.42" + attribute \src "ls180.v:2056.12-2056.42" wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1980.6-1980.37" + attribute \src "ls180.v:2055.6-2055.37" wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1975.12-1975.42" + attribute \src "ls180.v:2050.12-2050.42" wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1974.6-1974.37" + attribute \src "ls180.v:2049.6-2049.37" wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1977.12-1977.42" + attribute \src "ls180.v:2052.12-2052.42" wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1976.6-1976.37" + attribute \src "ls180.v:2051.6-2051.37" wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1971.12-1971.42" + attribute \src "ls180.v:2046.12-2046.42" wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1970.6-1970.37" + attribute \src "ls180.v:2045.6-2045.37" wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1973.12-1973.42" + attribute \src "ls180.v:2048.12-2048.42" wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1972.6-1972.37" + attribute \src "ls180.v:2047.6-2047.37" wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1967.12-1967.42" + attribute \src "ls180.v:2042.12-2042.42" wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1966.6-1966.37" + attribute \src "ls180.v:2041.6-2041.37" wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1969.12-1969.42" + attribute \src "ls180.v:2044.12-2044.42" wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1968.6-1968.37" + attribute \src "ls180.v:2043.6-2043.37" wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1947.6-1947.31" + attribute \src "ls180.v:2022.6-2022.31" wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1946.6-1946.32" + attribute \src "ls180.v:2021.6-2021.32" wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1949.6-1949.31" + attribute \src "ls180.v:2024.6-2024.31" wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1948.6-1948.32" + attribute \src "ls180.v:2023.6-2023.32" wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1963.12-1963.39" + attribute \src "ls180.v:2038.12-2038.39" wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1962.6-1962.34" + attribute \src "ls180.v:2037.6-2037.34" wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1965.12-1965.39" + attribute \src "ls180.v:2040.12-2040.39" wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1964.6-1964.34" + attribute \src "ls180.v:2039.6-2039.34" wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1959.12-1959.39" + attribute \src "ls180.v:2034.12-2034.39" wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1958.6-1958.34" + attribute \src "ls180.v:2033.6-2033.34" wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1961.12-1961.39" + attribute \src "ls180.v:2036.12-2036.39" wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1960.6-1960.34" + attribute \src "ls180.v:2035.6-2035.34" wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1955.12-1955.39" + attribute \src "ls180.v:2030.12-2030.39" wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1954.6-1954.34" + attribute \src "ls180.v:2029.6-2029.34" wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1957.12-1957.39" + attribute \src "ls180.v:2032.12-2032.39" wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1956.6-1956.34" + attribute \src "ls180.v:2031.6-2031.34" wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1951.12-1951.39" + attribute \src "ls180.v:2026.12-2026.39" wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1950.6-1950.34" + attribute \src "ls180.v:2025.6-2025.34" wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1953.12-1953.39" + attribute \src "ls180.v:2028.12-2028.39" wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1952.6-1952.34" + attribute \src "ls180.v:2027.6-2027.34" wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1982.6-1982.26" + attribute \src "ls180.v:2057.6-2057.26" wire \builder_csrbank0_sel - attribute \src "ls180.v:2453.12-2453.40" + attribute \src "ls180.v:2528.12-2528.40" wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2452.6-2452.35" + attribute \src "ls180.v:2527.6-2527.35" wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2455.12-2455.40" + attribute \src "ls180.v:2530.12-2530.40" wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2454.6-2454.35" + attribute \src "ls180.v:2529.6-2529.35" wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2449.12-2449.40" + attribute \src "ls180.v:2524.12-2524.40" wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2448.6-2448.35" + attribute \src "ls180.v:2523.6-2523.35" wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2451.12-2451.40" + attribute \src "ls180.v:2526.12-2526.40" wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2450.6-2450.35" + attribute \src "ls180.v:2525.6-2525.35" wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2469.6-2469.29" + attribute \src "ls180.v:2544.6-2544.29" wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2468.6-2468.30" + attribute \src "ls180.v:2543.6-2543.30" wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2471.6-2471.29" + attribute \src "ls180.v:2546.6-2546.29" wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2470.6-2470.30" + attribute \src "ls180.v:2545.6-2545.30" wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2473.6-2473.35" + attribute \src "ls180.v:2548.6-2548.35" wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2472.6-2472.36" + attribute \src "ls180.v:2547.6-2547.36" wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2475.6-2475.35" + attribute \src "ls180.v:2550.6-2550.35" wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2474.6-2474.36" + attribute \src "ls180.v:2549.6-2549.36" wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2465.12-2465.36" + attribute \src "ls180.v:2540.12-2540.36" wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2464.6-2464.31" + attribute \src "ls180.v:2539.6-2539.31" wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2467.12-2467.36" + attribute \src "ls180.v:2542.12-2542.36" wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2466.6-2466.31" + attribute \src "ls180.v:2541.6-2541.31" wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2461.12-2461.37" + attribute \src "ls180.v:2536.12-2536.37" wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2460.6-2460.32" + attribute \src "ls180.v:2535.6-2535.32" wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2463.12-2463.37" + attribute \src "ls180.v:2538.12-2538.37" wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2462.6-2462.32" + attribute \src "ls180.v:2537.6-2537.32" wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2476.6-2476.27" + attribute \src "ls180.v:2551.6-2551.27" wire \builder_csrbank10_sel - attribute \src "ls180.v:2457.6-2457.32" + attribute \src "ls180.v:2532.6-2532.32" wire \builder_csrbank10_status_r - attribute \src "ls180.v:2456.6-2456.33" + attribute \src "ls180.v:2531.6-2531.33" wire \builder_csrbank10_status_re - attribute \src "ls180.v:2459.6-2459.32" + attribute \src "ls180.v:2534.6-2534.32" wire \builder_csrbank10_status_w - attribute \src "ls180.v:2458.6-2458.33" + attribute \src "ls180.v:2533.6-2533.33" wire \builder_csrbank10_status_we - attribute \src "ls180.v:2514.12-2514.44" + attribute \src "ls180.v:2589.12-2589.44" wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2513.6-2513.39" + attribute \src "ls180.v:2588.6-2588.39" wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2516.12-2516.44" + attribute \src "ls180.v:2591.12-2591.44" wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2515.6-2515.39" + attribute \src "ls180.v:2590.6-2590.39" wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2510.12-2510.44" + attribute \src "ls180.v:2585.12-2585.44" wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2509.6-2509.39" + attribute \src "ls180.v:2584.6-2584.39" wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2512.12-2512.44" + attribute \src "ls180.v:2587.12-2587.44" wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2511.6-2511.39" + attribute \src "ls180.v:2586.6-2586.39" wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2486.12-2486.40" + attribute \src "ls180.v:2561.12-2561.40" wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2485.6-2485.35" + attribute \src "ls180.v:2560.6-2560.35" wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2488.12-2488.40" + attribute \src "ls180.v:2563.12-2563.40" wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2487.6-2487.35" + attribute \src "ls180.v:2562.6-2562.35" wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2482.12-2482.40" + attribute \src "ls180.v:2557.12-2557.40" wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2481.6-2481.35" + attribute \src "ls180.v:2556.6-2556.35" wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2484.12-2484.40" + attribute \src "ls180.v:2559.12-2559.40" wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2483.6-2483.35" + attribute \src "ls180.v:2558.6-2558.35" wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2502.6-2502.29" + attribute \src "ls180.v:2577.6-2577.29" wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2501.6-2501.30" + attribute \src "ls180.v:2576.6-2576.30" wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2504.6-2504.29" + attribute \src "ls180.v:2579.6-2579.29" wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2503.6-2503.30" + attribute \src "ls180.v:2578.6-2578.30" wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2506.6-2506.35" + attribute \src "ls180.v:2581.6-2581.35" wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2505.6-2505.36" + attribute \src "ls180.v:2580.6-2580.36" wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2508.6-2508.35" + attribute \src "ls180.v:2583.6-2583.35" wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2507.6-2507.36" + attribute \src "ls180.v:2582.6-2582.36" wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2498.12-2498.36" + attribute \src "ls180.v:2573.12-2573.36" wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2497.6-2497.31" + attribute \src "ls180.v:2572.6-2572.31" wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2500.12-2500.36" + attribute \src "ls180.v:2575.12-2575.36" wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2499.6-2499.31" + attribute \src "ls180.v:2574.6-2574.31" wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2494.12-2494.37" + attribute \src "ls180.v:2569.12-2569.37" wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2493.6-2493.32" + attribute \src "ls180.v:2568.6-2568.32" wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2496.12-2496.37" + attribute \src "ls180.v:2571.12-2571.37" wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2495.6-2495.32" + attribute \src "ls180.v:2570.6-2570.32" wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2517.6-2517.27" + attribute \src "ls180.v:2592.6-2592.27" wire \builder_csrbank11_sel - attribute \src "ls180.v:2490.6-2490.32" + attribute \src "ls180.v:2565.6-2565.32" wire \builder_csrbank11_status_r - attribute \src "ls180.v:2489.6-2489.33" + attribute \src "ls180.v:2564.6-2564.33" wire \builder_csrbank11_status_re - attribute \src "ls180.v:2492.6-2492.32" + attribute \src "ls180.v:2567.6-2567.32" wire \builder_csrbank11_status_w - attribute \src "ls180.v:2491.6-2491.33" + attribute \src "ls180.v:2566.6-2566.33" wire \builder_csrbank11_status_we - attribute \src "ls180.v:2555.6-2555.29" + attribute \src "ls180.v:2630.6-2630.29" wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2554.6-2554.30" + attribute \src "ls180.v:2629.6-2629.30" wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2557.6-2557.29" + attribute \src "ls180.v:2632.6-2632.29" wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2556.6-2556.30" + attribute \src "ls180.v:2631.6-2631.30" wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2579.6-2579.36" + attribute \src "ls180.v:2654.6-2654.36" wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2578.6-2578.37" + attribute \src "ls180.v:2653.6-2653.37" wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2581.6-2581.36" + attribute \src "ls180.v:2656.6-2656.36" wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2580.6-2580.37" + attribute \src "ls180.v:2655.6-2655.37" wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2535.12-2535.37" + attribute \src "ls180.v:2610.12-2610.37" wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2534.6-2534.32" + attribute \src "ls180.v:2609.6-2609.32" wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2537.12-2537.37" + attribute \src "ls180.v:2612.12-2612.37" wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2536.6-2536.32" + attribute \src "ls180.v:2611.6-2611.32" wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2531.12-2531.37" + attribute \src "ls180.v:2606.12-2606.37" wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2530.6-2530.32" + attribute \src "ls180.v:2605.6-2605.32" wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2533.12-2533.37" + attribute \src "ls180.v:2608.12-2608.37" wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2532.6-2532.32" + attribute \src "ls180.v:2607.6-2607.32" wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2527.12-2527.37" + attribute \src "ls180.v:2602.12-2602.37" wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2526.6-2526.32" + attribute \src "ls180.v:2601.6-2601.32" wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2529.12-2529.37" + attribute \src "ls180.v:2604.12-2604.37" wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2528.6-2528.32" + attribute \src "ls180.v:2603.6-2603.32" wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2523.12-2523.37" + attribute \src "ls180.v:2598.12-2598.37" wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2522.6-2522.32" + attribute \src "ls180.v:2597.6-2597.32" wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2525.12-2525.37" + attribute \src "ls180.v:2600.12-2600.37" wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2524.6-2524.32" + attribute \src "ls180.v:2599.6-2599.32" wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2551.12-2551.39" + attribute \src "ls180.v:2626.12-2626.39" wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2550.6-2550.34" + attribute \src "ls180.v:2625.6-2625.34" wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2553.12-2553.39" + attribute \src "ls180.v:2628.12-2628.39" wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2552.6-2552.34" + attribute \src "ls180.v:2627.6-2627.34" wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2547.12-2547.39" + attribute \src "ls180.v:2622.12-2622.39" wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2546.6-2546.34" + attribute \src "ls180.v:2621.6-2621.34" wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2549.12-2549.39" + attribute \src "ls180.v:2624.12-2624.39" wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2548.6-2548.34" + attribute \src "ls180.v:2623.6-2623.34" wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2543.12-2543.39" + attribute \src "ls180.v:2618.12-2618.39" wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2542.6-2542.34" + attribute \src "ls180.v:2617.6-2617.34" wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2545.12-2545.39" + attribute \src "ls180.v:2620.12-2620.39" wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2544.6-2544.34" + attribute \src "ls180.v:2619.6-2619.34" wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2539.12-2539.39" + attribute \src "ls180.v:2614.12-2614.39" wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2538.6-2538.34" + attribute \src "ls180.v:2613.6-2613.34" wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2541.12-2541.39" + attribute \src "ls180.v:2616.12-2616.39" wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2540.6-2540.34" + attribute \src "ls180.v:2615.6-2615.34" wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2582.6-2582.27" + attribute \src "ls180.v:2657.6-2657.27" wire \builder_csrbank12_sel - attribute \src "ls180.v:2559.6-2559.39" + attribute \src "ls180.v:2634.6-2634.39" wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2558.6-2558.40" + attribute \src "ls180.v:2633.6-2633.40" wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2561.6-2561.39" + attribute \src "ls180.v:2636.6-2636.39" wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2560.6-2560.40" + attribute \src "ls180.v:2635.6-2635.40" wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2575.12-2575.38" + attribute \src "ls180.v:2650.12-2650.38" wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2574.6-2574.33" + attribute \src "ls180.v:2649.6-2649.33" wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2577.12-2577.38" + attribute \src "ls180.v:2652.12-2652.38" wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2576.6-2576.33" + attribute \src "ls180.v:2651.6-2651.33" wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2571.12-2571.38" + attribute \src "ls180.v:2646.12-2646.38" wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2570.6-2570.33" + attribute \src "ls180.v:2645.6-2645.33" wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2573.12-2573.38" + attribute \src "ls180.v:2648.12-2648.38" wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2572.6-2572.33" + attribute \src "ls180.v:2647.6-2647.33" wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2567.12-2567.38" + attribute \src "ls180.v:2642.12-2642.38" wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2566.6-2566.33" + attribute \src "ls180.v:2641.6-2641.33" wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2569.12-2569.38" + attribute \src "ls180.v:2644.12-2644.38" wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2568.6-2568.33" + attribute \src "ls180.v:2643.6-2643.33" wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2563.12-2563.38" + attribute \src "ls180.v:2638.12-2638.38" wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2562.6-2562.33" + attribute \src "ls180.v:2637.6-2637.33" wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2565.12-2565.38" + attribute \src "ls180.v:2640.12-2640.38" wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2564.6-2564.33" + attribute \src "ls180.v:2639.6-2639.33" wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2596.12-2596.42" + attribute \src "ls180.v:2671.12-2671.42" wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2595.6-2595.37" + attribute \src "ls180.v:2670.6-2670.37" wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2598.12-2598.42" + attribute \src "ls180.v:2673.12-2673.42" wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2597.6-2597.37" + attribute \src "ls180.v:2672.6-2672.37" wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2592.6-2592.33" + attribute \src "ls180.v:2667.6-2667.33" wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2591.6-2591.34" + attribute \src "ls180.v:2666.6-2666.34" wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2594.6-2594.33" + attribute \src "ls180.v:2669.6-2669.33" wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2593.6-2593.34" + attribute \src "ls180.v:2668.6-2668.34" wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2604.6-2604.32" + attribute \src "ls180.v:2679.6-2679.32" wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2603.6-2603.33" + attribute \src "ls180.v:2678.6-2678.33" wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2606.6-2606.32" + attribute \src "ls180.v:2681.6-2681.32" wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2605.6-2605.33" + attribute \src "ls180.v:2680.6-2680.33" wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2607.6-2607.27" + attribute \src "ls180.v:2682.6-2682.27" wire \builder_csrbank13_sel - attribute \src "ls180.v:2600.6-2600.33" + attribute \src "ls180.v:2675.6-2675.33" wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2599.6-2599.34" + attribute \src "ls180.v:2674.6-2674.34" wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2602.6-2602.33" + attribute \src "ls180.v:2677.6-2677.33" wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2601.6-2601.34" + attribute \src "ls180.v:2676.6-2676.34" wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2588.6-2588.32" + attribute \src "ls180.v:2663.6-2663.32" wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2587.6-2587.33" + attribute \src "ls180.v:2662.6-2662.33" wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2590.6-2590.32" + attribute \src "ls180.v:2665.6-2665.32" wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2589.6-2589.33" + attribute \src "ls180.v:2664.6-2664.33" wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2628.6-2628.27" + attribute \src "ls180.v:2703.6-2703.27" wire \builder_csrbank14_sel - attribute \src "ls180.v:2625.12-2625.44" + attribute \src "ls180.v:2700.12-2700.44" wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2624.6-2624.39" + attribute \src "ls180.v:2699.6-2699.39" wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2627.12-2627.44" + attribute \src "ls180.v:2702.12-2702.44" wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2626.6-2626.39" + attribute \src "ls180.v:2701.6-2701.39" wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2621.12-2621.44" + attribute \src "ls180.v:2696.12-2696.44" wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2620.6-2620.39" + attribute \src "ls180.v:2695.6-2695.39" wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2623.12-2623.44" + attribute \src "ls180.v:2698.12-2698.44" wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2622.6-2622.39" + attribute \src "ls180.v:2697.6-2697.39" wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2617.12-2617.44" + attribute \src "ls180.v:2692.12-2692.44" wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2616.6-2616.39" + attribute \src "ls180.v:2691.6-2691.39" wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2619.12-2619.44" + attribute \src "ls180.v:2694.12-2694.44" wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2618.6-2618.39" + attribute \src "ls180.v:2693.6-2693.39" wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2613.12-2613.44" + attribute \src "ls180.v:2688.12-2688.44" wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2612.6-2612.39" + attribute \src "ls180.v:2687.6-2687.39" wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2615.12-2615.44" + attribute \src "ls180.v:2690.12-2690.44" wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2614.6-2614.39" + attribute \src "ls180.v:2689.6-2689.39" wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:2000.12-2000.34" + attribute \src "ls180.v:2075.12-2075.34" wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:1999.6-1999.29" + attribute \src "ls180.v:2074.6-2074.29" wire \builder_csrbank1_in0_re - attribute \src "ls180.v:2002.12-2002.34" + attribute \src "ls180.v:2077.12-2077.34" wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:2001.6-2001.29" + attribute \src "ls180.v:2076.6-2076.29" wire \builder_csrbank1_in0_we - attribute \src "ls180.v:1996.12-1996.34" + attribute \src "ls180.v:2071.12-2071.34" wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:1995.6-1995.29" + attribute \src "ls180.v:2070.6-2070.29" wire \builder_csrbank1_in1_re - attribute \src "ls180.v:1998.12-1998.34" + attribute \src "ls180.v:2073.12-2073.34" wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:1997.6-1997.29" + attribute \src "ls180.v:2072.6-2072.29" wire \builder_csrbank1_in1_we - attribute \src "ls180.v:1992.12-1992.34" + attribute \src "ls180.v:2067.12-2067.34" wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:1991.6-1991.29" + attribute \src "ls180.v:2066.6-2066.29" wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:1994.12-1994.34" + attribute \src "ls180.v:2069.12-2069.34" wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:1993.6-1993.29" + attribute \src "ls180.v:2068.6-2068.29" wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:1988.12-1988.34" + attribute \src "ls180.v:2063.12-2063.34" wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:1987.6-1987.29" + attribute \src "ls180.v:2062.6-2062.29" wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:1990.12-1990.34" + attribute \src "ls180.v:2065.12-2065.34" wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:1989.6-1989.29" + attribute \src "ls180.v:2064.6-2064.29" wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:2008.12-2008.35" + attribute \src "ls180.v:2083.12-2083.35" wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:2007.6-2007.30" + attribute \src "ls180.v:2082.6-2082.30" wire \builder_csrbank1_out0_re - attribute \src "ls180.v:2010.12-2010.35" + attribute \src "ls180.v:2085.12-2085.35" wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:2009.6-2009.30" + attribute \src "ls180.v:2084.6-2084.30" wire \builder_csrbank1_out0_we - attribute \src "ls180.v:2004.12-2004.35" + attribute \src "ls180.v:2079.12-2079.35" wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:2003.6-2003.30" + attribute \src "ls180.v:2078.6-2078.30" wire \builder_csrbank1_out1_re - attribute \src "ls180.v:2006.12-2006.35" + attribute \src "ls180.v:2081.12-2081.35" wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:2005.6-2005.30" + attribute \src "ls180.v:2080.6-2080.30" wire \builder_csrbank1_out1_we - attribute \src "ls180.v:2011.6-2011.26" + attribute \src "ls180.v:2086.6-2086.26" wire \builder_csrbank1_sel - attribute \src "ls180.v:2021.6-2021.26" + attribute \src "ls180.v:2096.6-2096.26" wire \builder_csrbank2_r_r - attribute \src "ls180.v:2020.6-2020.27" + attribute \src "ls180.v:2095.6-2095.27" wire \builder_csrbank2_r_re - attribute \src "ls180.v:2023.6-2023.26" + attribute \src "ls180.v:2098.6-2098.26" wire \builder_csrbank2_r_w - attribute \src "ls180.v:2022.6-2022.27" + attribute \src "ls180.v:2097.6-2097.27" wire \builder_csrbank2_r_we - attribute \src "ls180.v:2024.6-2024.26" + attribute \src "ls180.v:2099.6-2099.26" wire \builder_csrbank2_sel - attribute \src "ls180.v:2017.12-2017.33" + attribute \src "ls180.v:2092.12-2092.33" wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:2016.6-2016.28" + attribute \src "ls180.v:2091.6-2091.28" wire \builder_csrbank2_w0_re - attribute \src "ls180.v:2019.12-2019.33" + attribute \src "ls180.v:2094.12-2094.33" wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:2018.6-2018.28" + attribute \src "ls180.v:2093.6-2093.28" wire \builder_csrbank2_w0_we - attribute \src "ls180.v:2030.6-2030.32" + attribute \src "ls180.v:2105.6-2105.32" wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:2029.6-2029.33" + attribute \src "ls180.v:2104.6-2104.33" wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:2032.6-2032.32" + attribute \src "ls180.v:2107.6-2107.32" wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:2031.6-2031.33" + attribute \src "ls180.v:2106.6-2106.33" wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2062.12-2062.38" + attribute \src "ls180.v:2137.12-2137.38" wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2061.6-2061.33" + attribute \src "ls180.v:2136.6-2136.33" wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2064.12-2064.38" + attribute \src "ls180.v:2139.12-2139.38" wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2063.6-2063.33" + attribute \src "ls180.v:2138.6-2138.33" wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2058.12-2058.38" + attribute \src "ls180.v:2133.12-2133.38" wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2057.6-2057.33" + attribute \src "ls180.v:2132.6-2132.33" wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2060.12-2060.38" + attribute \src "ls180.v:2135.12-2135.38" wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2059.6-2059.33" + attribute \src "ls180.v:2134.6-2134.33" wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2054.12-2054.38" + attribute \src "ls180.v:2129.12-2129.38" wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2053.6-2053.33" + attribute \src "ls180.v:2128.6-2128.33" wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2056.12-2056.38" + attribute \src "ls180.v:2131.12-2131.38" wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2055.6-2055.33" + attribute \src "ls180.v:2130.6-2130.33" wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2050.12-2050.38" + attribute \src "ls180.v:2125.12-2125.38" wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2049.6-2049.33" + attribute \src "ls180.v:2124.6-2124.33" wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2052.12-2052.38" + attribute \src "ls180.v:2127.12-2127.38" wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2051.6-2051.33" + attribute \src "ls180.v:2126.6-2126.33" wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2065.6-2065.26" + attribute \src "ls180.v:2140.6-2140.26" wire \builder_csrbank3_sel - attribute \src "ls180.v:2046.12-2046.37" + attribute \src "ls180.v:2121.12-2121.37" wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2045.6-2045.32" + attribute \src "ls180.v:2120.6-2120.32" wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2048.12-2048.37" + attribute \src "ls180.v:2123.12-2123.37" wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2047.6-2047.32" + attribute \src "ls180.v:2122.6-2122.32" wire \builder_csrbank3_width0_we - attribute \src "ls180.v:2042.12-2042.37" + attribute \src "ls180.v:2117.12-2117.37" wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:2041.6-2041.32" + attribute \src "ls180.v:2116.6-2116.32" wire \builder_csrbank3_width1_re - attribute \src "ls180.v:2044.12-2044.37" + attribute \src "ls180.v:2119.12-2119.37" wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:2043.6-2043.32" + attribute \src "ls180.v:2118.6-2118.32" wire \builder_csrbank3_width1_we - attribute \src "ls180.v:2038.12-2038.37" + attribute \src "ls180.v:2113.12-2113.37" wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:2037.6-2037.32" + attribute \src "ls180.v:2112.6-2112.32" wire \builder_csrbank3_width2_re - attribute \src "ls180.v:2040.12-2040.37" + attribute \src "ls180.v:2115.12-2115.37" wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:2039.6-2039.32" + attribute \src "ls180.v:2114.6-2114.32" wire \builder_csrbank3_width2_we - attribute \src "ls180.v:2034.12-2034.37" + attribute \src "ls180.v:2109.12-2109.37" wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:2033.6-2033.32" + attribute \src "ls180.v:2108.6-2108.32" wire \builder_csrbank3_width3_re - attribute \src "ls180.v:2036.12-2036.37" + attribute \src "ls180.v:2111.12-2111.37" wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:2035.6-2035.32" + attribute \src "ls180.v:2110.6-2110.32" wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2071.6-2071.32" + attribute \src "ls180.v:2146.6-2146.32" wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2070.6-2070.33" + attribute \src "ls180.v:2145.6-2145.33" wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2073.6-2073.32" + attribute \src "ls180.v:2148.6-2148.32" wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2072.6-2072.33" + attribute \src "ls180.v:2147.6-2147.33" wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2103.12-2103.38" + attribute \src "ls180.v:2178.12-2178.38" wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2102.6-2102.33" + attribute \src "ls180.v:2177.6-2177.33" wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2105.12-2105.38" + attribute \src "ls180.v:2180.12-2180.38" wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2104.6-2104.33" + attribute \src "ls180.v:2179.6-2179.33" wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2099.12-2099.38" + attribute \src "ls180.v:2174.12-2174.38" wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2098.6-2098.33" + attribute \src "ls180.v:2173.6-2173.33" wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2101.12-2101.38" + attribute \src "ls180.v:2176.12-2176.38" wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2100.6-2100.33" + attribute \src "ls180.v:2175.6-2175.33" wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2095.12-2095.38" + attribute \src "ls180.v:2170.12-2170.38" wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2094.6-2094.33" + attribute \src "ls180.v:2169.6-2169.33" wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2097.12-2097.38" + attribute \src "ls180.v:2172.12-2172.38" wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2096.6-2096.33" + attribute \src "ls180.v:2171.6-2171.33" wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2091.12-2091.38" + attribute \src "ls180.v:2166.12-2166.38" wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2090.6-2090.33" + attribute \src "ls180.v:2165.6-2165.33" wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2093.12-2093.38" + attribute \src "ls180.v:2168.12-2168.38" wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2092.6-2092.33" + attribute \src "ls180.v:2167.6-2167.33" wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2106.6-2106.26" + attribute \src "ls180.v:2181.6-2181.26" wire \builder_csrbank4_sel - attribute \src "ls180.v:2087.12-2087.37" + attribute \src "ls180.v:2162.12-2162.37" wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2086.6-2086.32" + attribute \src "ls180.v:2161.6-2161.32" wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2089.12-2089.37" + attribute \src "ls180.v:2164.12-2164.37" wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2088.6-2088.32" + attribute \src "ls180.v:2163.6-2163.32" wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2083.12-2083.37" + attribute \src "ls180.v:2158.12-2158.37" wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2082.6-2082.32" + attribute \src "ls180.v:2157.6-2157.32" wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2085.12-2085.37" + attribute \src "ls180.v:2160.12-2160.37" wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2084.6-2084.32" + attribute \src "ls180.v:2159.6-2159.32" wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2079.12-2079.37" + attribute \src "ls180.v:2154.12-2154.37" wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2078.6-2078.32" + attribute \src "ls180.v:2153.6-2153.32" wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2081.12-2081.37" + attribute \src "ls180.v:2156.12-2156.37" wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2080.6-2080.32" + attribute \src "ls180.v:2155.6-2155.32" wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2075.12-2075.37" + attribute \src "ls180.v:2150.12-2150.37" wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2074.6-2074.32" + attribute \src "ls180.v:2149.6-2149.32" wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2077.12-2077.37" + attribute \src "ls180.v:2152.12-2152.37" wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2076.6-2076.32" + attribute \src "ls180.v:2151.6-2151.32" wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2140.12-2140.40" + attribute \src "ls180.v:2215.12-2215.40" wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2139.6-2139.35" + attribute \src "ls180.v:2214.6-2214.35" wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2142.12-2142.40" + attribute \src "ls180.v:2217.12-2217.40" wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2141.6-2141.35" + attribute \src "ls180.v:2216.6-2216.35" wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2136.12-2136.40" + attribute \src "ls180.v:2211.12-2211.40" wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2135.6-2135.35" + attribute \src "ls180.v:2210.6-2210.35" wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2138.12-2138.40" + attribute \src "ls180.v:2213.12-2213.40" wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2137.6-2137.35" + attribute \src "ls180.v:2212.6-2212.35" wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2132.12-2132.40" + attribute \src "ls180.v:2207.12-2207.40" wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2131.6-2131.35" + attribute \src "ls180.v:2206.6-2206.35" wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2134.12-2134.40" + attribute \src "ls180.v:2209.12-2209.40" wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2133.6-2133.35" + attribute \src "ls180.v:2208.6-2208.35" wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2128.12-2128.40" + attribute \src "ls180.v:2203.12-2203.40" wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2127.6-2127.35" + attribute \src "ls180.v:2202.6-2202.35" wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2130.12-2130.40" + attribute \src "ls180.v:2205.12-2205.40" wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2129.6-2129.35" + attribute \src "ls180.v:2204.6-2204.35" wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2124.12-2124.40" + attribute \src "ls180.v:2199.12-2199.40" wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2123.6-2123.35" + attribute \src "ls180.v:2198.6-2198.35" wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2126.12-2126.40" + attribute \src "ls180.v:2201.12-2201.40" wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2125.6-2125.35" + attribute \src "ls180.v:2200.6-2200.35" wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2120.12-2120.40" + attribute \src "ls180.v:2195.12-2195.40" wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2119.6-2119.35" + attribute \src "ls180.v:2194.6-2194.35" wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2122.12-2122.40" + attribute \src "ls180.v:2197.12-2197.40" wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2121.6-2121.35" + attribute \src "ls180.v:2196.6-2196.35" wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2116.12-2116.40" + attribute \src "ls180.v:2191.12-2191.40" wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2115.6-2115.35" + attribute \src "ls180.v:2190.6-2190.35" wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2118.12-2118.40" + attribute \src "ls180.v:2193.12-2193.40" wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2117.6-2117.35" + attribute \src "ls180.v:2192.6-2192.35" wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2112.12-2112.40" + attribute \src "ls180.v:2187.12-2187.40" wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2111.6-2111.35" + attribute \src "ls180.v:2186.6-2186.35" wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2114.12-2114.40" + attribute \src "ls180.v:2189.12-2189.40" wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2113.6-2113.35" + attribute \src "ls180.v:2188.6-2188.35" wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2164.6-2164.33" + attribute \src "ls180.v:2239.6-2239.33" wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2163.6-2163.34" + attribute \src "ls180.v:2238.6-2238.34" wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2166.6-2166.33" + attribute \src "ls180.v:2241.6-2241.33" wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2165.6-2165.34" + attribute \src "ls180.v:2240.6-2240.34" wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2160.6-2160.36" + attribute \src "ls180.v:2235.6-2235.36" wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2159.6-2159.37" + attribute \src "ls180.v:2234.6-2234.37" wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2162.6-2162.36" + attribute \src "ls180.v:2237.6-2237.36" wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2161.6-2161.37" + attribute \src "ls180.v:2236.6-2236.37" wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2156.12-2156.42" + attribute \src "ls180.v:2231.12-2231.42" wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2155.6-2155.37" + attribute \src "ls180.v:2230.6-2230.37" wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2158.12-2158.42" + attribute \src "ls180.v:2233.12-2233.42" wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2157.6-2157.37" + attribute \src "ls180.v:2232.6-2232.37" wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2152.12-2152.42" + attribute \src "ls180.v:2227.12-2227.42" wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2151.6-2151.37" + attribute \src "ls180.v:2226.6-2226.37" wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2154.12-2154.42" + attribute \src "ls180.v:2229.12-2229.42" wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2153.6-2153.37" + attribute \src "ls180.v:2228.6-2228.37" wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2148.12-2148.42" + attribute \src "ls180.v:2223.12-2223.42" wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2147.6-2147.37" + attribute \src "ls180.v:2222.6-2222.37" wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2150.12-2150.42" + attribute \src "ls180.v:2225.12-2225.42" wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2149.6-2149.37" + attribute \src "ls180.v:2224.6-2224.37" wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2144.12-2144.42" + attribute \src "ls180.v:2219.12-2219.42" wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2143.6-2143.37" + attribute \src "ls180.v:2218.6-2218.37" wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2146.12-2146.42" + attribute \src "ls180.v:2221.12-2221.42" wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2145.6-2145.37" + attribute \src "ls180.v:2220.6-2220.37" wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2168.6-2168.34" + attribute \src "ls180.v:2243.6-2243.34" wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2167.6-2167.35" + attribute \src "ls180.v:2242.6-2242.35" wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2170.6-2170.34" + attribute \src "ls180.v:2245.6-2245.34" wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2169.6-2169.35" + attribute \src "ls180.v:2244.6-2244.35" wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2171.6-2171.26" + attribute \src "ls180.v:2246.6-2246.26" wire \builder_csrbank5_sel - attribute \src "ls180.v:2301.12-2301.43" + attribute \src "ls180.v:2376.12-2376.43" wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2300.6-2300.38" + attribute \src "ls180.v:2375.6-2375.38" wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2303.12-2303.43" + attribute \src "ls180.v:2378.12-2378.43" wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2302.6-2302.38" + attribute \src "ls180.v:2377.6-2377.38" wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2297.12-2297.43" + attribute \src "ls180.v:2372.12-2372.43" wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2296.6-2296.38" + attribute \src "ls180.v:2371.6-2371.38" wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2299.12-2299.43" + attribute \src "ls180.v:2374.12-2374.43" wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2298.6-2298.38" + attribute \src "ls180.v:2373.6-2373.38" wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2293.12-2293.43" + attribute \src "ls180.v:2368.12-2368.43" wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2292.6-2292.38" + attribute \src "ls180.v:2367.6-2367.38" wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2295.12-2295.43" + attribute \src "ls180.v:2370.12-2370.43" wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2294.6-2294.38" + attribute \src "ls180.v:2369.6-2369.38" wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2289.12-2289.43" + attribute \src "ls180.v:2364.12-2364.43" wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2288.6-2288.38" + attribute \src "ls180.v:2363.6-2363.38" wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2291.12-2291.43" + attribute \src "ls180.v:2366.12-2366.43" wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2290.6-2290.38" + attribute \src "ls180.v:2365.6-2365.38" wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2285.12-2285.44" + attribute \src "ls180.v:2360.12-2360.44" wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2284.6-2284.39" + attribute \src "ls180.v:2359.6-2359.39" wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2287.12-2287.44" + attribute \src "ls180.v:2362.12-2362.44" wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2286.6-2286.39" + attribute \src "ls180.v:2361.6-2361.39" wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2281.12-2281.44" + attribute \src "ls180.v:2356.12-2356.44" wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2280.6-2280.39" + attribute \src "ls180.v:2355.6-2355.39" wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2283.12-2283.44" + attribute \src "ls180.v:2358.12-2358.44" wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2282.6-2282.39" + attribute \src "ls180.v:2357.6-2357.39" wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2189.12-2189.44" + attribute \src "ls180.v:2264.12-2264.44" wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2188.6-2188.39" + attribute \src "ls180.v:2263.6-2263.39" wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2191.12-2191.44" + attribute \src "ls180.v:2266.12-2266.44" wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2190.6-2190.39" + attribute \src "ls180.v:2265.6-2265.39" wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2185.12-2185.44" + attribute \src "ls180.v:2260.12-2260.44" wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2184.6-2184.39" + attribute \src "ls180.v:2259.6-2259.39" wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2187.12-2187.44" + attribute \src "ls180.v:2262.12-2262.44" wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2186.6-2186.39" + attribute \src "ls180.v:2261.6-2261.39" wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2181.12-2181.44" + attribute \src "ls180.v:2256.12-2256.44" wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2180.6-2180.39" + attribute \src "ls180.v:2255.6-2255.39" wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2183.12-2183.44" + attribute \src "ls180.v:2258.12-2258.44" wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2182.6-2182.39" + attribute \src "ls180.v:2257.6-2257.39" wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2177.12-2177.44" + attribute \src "ls180.v:2252.12-2252.44" wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2176.6-2176.39" + attribute \src "ls180.v:2251.6-2251.39" wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2179.12-2179.44" + attribute \src "ls180.v:2254.12-2254.44" wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2178.6-2178.39" + attribute \src "ls180.v:2253.6-2253.39" wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2205.12-2205.43" + attribute \src "ls180.v:2280.12-2280.43" wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2204.6-2204.38" + attribute \src "ls180.v:2279.6-2279.38" wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2207.12-2207.43" + attribute \src "ls180.v:2282.12-2282.43" wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2206.6-2206.38" + attribute \src "ls180.v:2281.6-2281.38" wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2201.12-2201.43" + attribute \src "ls180.v:2276.12-2276.43" wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2200.6-2200.38" + attribute \src "ls180.v:2275.6-2275.38" wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2203.12-2203.43" + attribute \src "ls180.v:2278.12-2278.43" wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2202.6-2202.38" + attribute \src "ls180.v:2277.6-2277.38" wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2197.12-2197.43" + attribute \src "ls180.v:2272.12-2272.43" wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2196.6-2196.38" + attribute \src "ls180.v:2271.6-2271.38" wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2199.12-2199.43" + attribute \src "ls180.v:2274.12-2274.43" wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2198.6-2198.38" + attribute \src "ls180.v:2273.6-2273.38" wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2193.12-2193.43" + attribute \src "ls180.v:2268.12-2268.43" wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2192.6-2192.38" + attribute \src "ls180.v:2267.6-2267.38" wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2195.12-2195.43" + attribute \src "ls180.v:2270.12-2270.43" wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2194.6-2194.38" + attribute \src "ls180.v:2269.6-2269.38" wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2273.12-2273.40" + attribute \src "ls180.v:2348.12-2348.40" wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2272.6-2272.35" + attribute \src "ls180.v:2347.6-2347.35" wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2275.12-2275.40" + attribute \src "ls180.v:2350.12-2350.40" wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2274.6-2274.35" + attribute \src "ls180.v:2349.6-2349.35" wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2269.12-2269.44" + attribute \src "ls180.v:2344.12-2344.44" wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2268.6-2268.39" + attribute \src "ls180.v:2343.6-2343.39" wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2271.12-2271.44" + attribute \src "ls180.v:2346.12-2346.44" wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2270.6-2270.39" + attribute \src "ls180.v:2345.6-2345.39" wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2229.12-2229.45" + attribute \src "ls180.v:2304.12-2304.45" wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2228.6-2228.40" + attribute \src "ls180.v:2303.6-2303.40" wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2231.12-2231.45" + attribute \src "ls180.v:2306.12-2306.45" wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2230.6-2230.40" + attribute \src "ls180.v:2305.6-2305.40" wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2225.12-2225.45" + attribute \src "ls180.v:2300.12-2300.45" wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2224.6-2224.40" + attribute \src "ls180.v:2299.6-2299.40" wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2227.12-2227.45" + attribute \src "ls180.v:2302.12-2302.45" wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2226.6-2226.40" + attribute \src "ls180.v:2301.6-2301.40" wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2221.12-2221.45" + attribute \src "ls180.v:2296.12-2296.45" wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2220.6-2220.40" + attribute \src "ls180.v:2295.6-2295.40" wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2223.12-2223.45" + attribute \src "ls180.v:2298.12-2298.45" wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2222.6-2222.40" + attribute \src "ls180.v:2297.6-2297.40" wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2217.12-2217.45" + attribute \src "ls180.v:2292.12-2292.45" wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2216.6-2216.40" + attribute \src "ls180.v:2291.6-2291.40" wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2219.12-2219.45" + attribute \src "ls180.v:2294.12-2294.45" wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2218.6-2218.40" + attribute \src "ls180.v:2293.6-2293.40" wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2213.12-2213.45" + attribute \src "ls180.v:2288.12-2288.45" wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2212.6-2212.40" + attribute \src "ls180.v:2287.6-2287.40" wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2215.12-2215.45" + attribute \src "ls180.v:2290.12-2290.45" wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2214.6-2214.40" + attribute \src "ls180.v:2289.6-2289.40" wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2209.12-2209.45" + attribute \src "ls180.v:2284.12-2284.45" wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2208.6-2208.40" + attribute \src "ls180.v:2283.6-2283.40" wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2211.12-2211.45" + attribute \src "ls180.v:2286.12-2286.45" wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2210.6-2210.40" + attribute \src "ls180.v:2285.6-2285.40" wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2265.12-2265.44" + attribute \src "ls180.v:2340.12-2340.44" wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2264.6-2264.39" + attribute \src "ls180.v:2339.6-2339.39" wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2267.12-2267.44" + attribute \src "ls180.v:2342.12-2342.44" wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2266.6-2266.39" + attribute \src "ls180.v:2341.6-2341.39" wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2261.12-2261.44" + attribute \src "ls180.v:2336.12-2336.44" wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2260.6-2260.39" + attribute \src "ls180.v:2335.6-2335.39" wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2263.12-2263.44" + attribute \src "ls180.v:2338.12-2338.44" wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2262.6-2262.39" + attribute \src "ls180.v:2337.6-2337.39" wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2257.12-2257.44" + attribute \src "ls180.v:2332.12-2332.44" wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2256.6-2256.39" + attribute \src "ls180.v:2331.6-2331.39" wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2259.12-2259.44" + attribute \src "ls180.v:2334.12-2334.44" wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2258.6-2258.39" + attribute \src "ls180.v:2333.6-2333.39" wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2253.12-2253.44" + attribute \src "ls180.v:2328.12-2328.44" wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2252.6-2252.39" + attribute \src "ls180.v:2327.6-2327.39" wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2255.12-2255.44" + attribute \src "ls180.v:2330.12-2330.44" wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2254.6-2254.39" + attribute \src "ls180.v:2329.6-2329.39" wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2249.12-2249.44" + attribute \src "ls180.v:2324.12-2324.44" wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2248.6-2248.39" + attribute \src "ls180.v:2323.6-2323.39" wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2251.12-2251.44" + attribute \src "ls180.v:2326.12-2326.44" wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2250.6-2250.39" + attribute \src "ls180.v:2325.6-2325.39" wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2245.12-2245.44" + attribute \src "ls180.v:2320.12-2320.44" wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2244.6-2244.39" + attribute \src "ls180.v:2319.6-2319.39" wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2247.12-2247.44" + attribute \src "ls180.v:2322.12-2322.44" wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2246.6-2246.39" + attribute \src "ls180.v:2321.6-2321.39" wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2241.12-2241.44" + attribute \src "ls180.v:2316.12-2316.44" wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2240.6-2240.39" + attribute \src "ls180.v:2315.6-2315.39" wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2243.12-2243.44" + attribute \src "ls180.v:2318.12-2318.44" wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2242.6-2242.39" + attribute \src "ls180.v:2317.6-2317.39" wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2237.12-2237.44" + attribute \src "ls180.v:2312.12-2312.44" wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2236.6-2236.39" + attribute \src "ls180.v:2311.6-2311.39" wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2239.12-2239.44" + attribute \src "ls180.v:2314.12-2314.44" wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2238.6-2238.39" + attribute \src "ls180.v:2313.6-2313.39" wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2233.12-2233.44" + attribute \src "ls180.v:2308.12-2308.44" wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2232.6-2232.39" + attribute \src "ls180.v:2307.6-2307.39" wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2235.12-2235.44" + attribute \src "ls180.v:2310.12-2310.44" wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2234.6-2234.39" + attribute \src "ls180.v:2309.6-2309.39" wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2277.12-2277.41" + attribute \src "ls180.v:2352.12-2352.41" wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2276.6-2276.36" + attribute \src "ls180.v:2351.6-2351.36" wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2279.12-2279.41" + attribute \src "ls180.v:2354.12-2354.41" wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2278.6-2278.36" + attribute \src "ls180.v:2353.6-2353.36" wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2304.6-2304.26" + attribute \src "ls180.v:2379.6-2379.26" wire \builder_csrbank6_sel - attribute \src "ls180.v:2338.12-2338.40" + attribute \src "ls180.v:2413.12-2413.40" wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2337.6-2337.35" + attribute \src "ls180.v:2412.6-2412.35" wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2340.12-2340.40" + attribute \src "ls180.v:2415.12-2415.40" wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2339.6-2339.35" + attribute \src "ls180.v:2414.6-2414.35" wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2334.12-2334.40" + attribute \src "ls180.v:2409.12-2409.40" wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2333.6-2333.35" + attribute \src "ls180.v:2408.6-2408.35" wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2336.12-2336.40" + attribute \src "ls180.v:2411.12-2411.40" wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2335.6-2335.35" + attribute \src "ls180.v:2410.6-2410.35" wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2330.12-2330.40" + attribute \src "ls180.v:2405.12-2405.40" wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2329.6-2329.35" + attribute \src "ls180.v:2404.6-2404.35" wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2332.12-2332.40" + attribute \src "ls180.v:2407.12-2407.40" wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2331.6-2331.35" + attribute \src "ls180.v:2406.6-2406.35" wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2326.12-2326.40" + attribute \src "ls180.v:2401.12-2401.40" wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2325.6-2325.35" + attribute \src "ls180.v:2400.6-2400.35" wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2328.12-2328.40" + attribute \src "ls180.v:2403.12-2403.40" wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2327.6-2327.35" + attribute \src "ls180.v:2402.6-2402.35" wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2322.12-2322.40" + attribute \src "ls180.v:2397.12-2397.40" wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2321.6-2321.35" + attribute \src "ls180.v:2396.6-2396.35" wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2324.12-2324.40" + attribute \src "ls180.v:2399.12-2399.40" wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2323.6-2323.35" + attribute \src "ls180.v:2398.6-2398.35" wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2318.12-2318.40" + attribute \src "ls180.v:2393.12-2393.40" wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2317.6-2317.35" + attribute \src "ls180.v:2392.6-2392.35" wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2320.12-2320.40" + attribute \src "ls180.v:2395.12-2395.40" wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2319.6-2319.35" + attribute \src "ls180.v:2394.6-2394.35" wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2314.12-2314.40" + attribute \src "ls180.v:2389.12-2389.40" wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2313.6-2313.35" + attribute \src "ls180.v:2388.6-2388.35" wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2316.12-2316.40" + attribute \src "ls180.v:2391.12-2391.40" wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2315.6-2315.35" + attribute \src "ls180.v:2390.6-2390.35" wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2310.12-2310.40" + attribute \src "ls180.v:2385.12-2385.40" wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2309.6-2309.35" + attribute \src "ls180.v:2384.6-2384.35" wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2312.12-2312.40" + attribute \src "ls180.v:2387.12-2387.40" wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2311.6-2311.35" + attribute \src "ls180.v:2386.6-2386.35" wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2362.6-2362.33" + attribute \src "ls180.v:2437.6-2437.33" wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2361.6-2361.34" + attribute \src "ls180.v:2436.6-2436.34" wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2364.6-2364.33" + attribute \src "ls180.v:2439.6-2439.33" wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2363.6-2363.34" + attribute \src "ls180.v:2438.6-2438.34" wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2358.6-2358.36" + attribute \src "ls180.v:2433.6-2433.36" wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2357.6-2357.37" + attribute \src "ls180.v:2432.6-2432.37" wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2360.6-2360.36" + attribute \src "ls180.v:2435.6-2435.36" wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2359.6-2359.37" + attribute \src "ls180.v:2434.6-2434.37" wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2354.12-2354.42" + attribute \src "ls180.v:2429.12-2429.42" wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2353.6-2353.37" + attribute \src "ls180.v:2428.6-2428.37" wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2356.12-2356.42" + attribute \src "ls180.v:2431.12-2431.42" wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2355.6-2355.37" + attribute \src "ls180.v:2430.6-2430.37" wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2350.12-2350.42" + attribute \src "ls180.v:2425.12-2425.42" wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2349.6-2349.37" + attribute \src "ls180.v:2424.6-2424.37" wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2352.12-2352.42" + attribute \src "ls180.v:2427.12-2427.42" wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2351.6-2351.37" + attribute \src "ls180.v:2426.6-2426.37" wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2346.12-2346.42" + attribute \src "ls180.v:2421.12-2421.42" wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2345.6-2345.37" + attribute \src "ls180.v:2420.6-2420.37" wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2348.12-2348.42" + attribute \src "ls180.v:2423.12-2423.42" wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2347.6-2347.37" + attribute \src "ls180.v:2422.6-2422.37" wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2342.12-2342.42" + attribute \src "ls180.v:2417.12-2417.42" wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2341.6-2341.37" + attribute \src "ls180.v:2416.6-2416.37" wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2344.12-2344.42" + attribute \src "ls180.v:2419.12-2419.42" wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2343.6-2343.37" + attribute \src "ls180.v:2418.6-2418.37" wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2366.6-2366.34" + attribute \src "ls180.v:2441.6-2441.34" wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2365.6-2365.35" + attribute \src "ls180.v:2440.6-2440.35" wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2368.6-2368.34" + attribute \src "ls180.v:2443.6-2443.34" wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2367.6-2367.35" + attribute \src "ls180.v:2442.6-2442.35" wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2382.12-2382.42" + attribute \src "ls180.v:2457.12-2457.42" wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2381.6-2381.37" + attribute \src "ls180.v:2456.6-2456.37" wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2384.12-2384.42" + attribute \src "ls180.v:2459.12-2459.42" wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2383.6-2383.37" + attribute \src "ls180.v:2458.6-2458.37" wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2378.12-2378.42" + attribute \src "ls180.v:2453.12-2453.42" wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2377.6-2377.37" + attribute \src "ls180.v:2452.6-2452.37" wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2380.12-2380.42" + attribute \src "ls180.v:2455.12-2455.42" wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2379.6-2379.37" + attribute \src "ls180.v:2454.6-2454.37" wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2374.12-2374.42" + attribute \src "ls180.v:2449.12-2449.42" wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2373.6-2373.37" + attribute \src "ls180.v:2448.6-2448.37" wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2376.12-2376.42" + attribute \src "ls180.v:2451.12-2451.42" wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2375.6-2375.37" + attribute \src "ls180.v:2450.6-2450.37" wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2370.12-2370.42" + attribute \src "ls180.v:2445.12-2445.42" wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2369.6-2369.37" + attribute \src "ls180.v:2444.6-2444.37" wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2372.12-2372.42" + attribute \src "ls180.v:2447.12-2447.42" wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2371.6-2371.37" + attribute \src "ls180.v:2446.6-2446.37" wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2385.6-2385.26" + attribute \src "ls180.v:2460.6-2460.26" wire \builder_csrbank7_sel - attribute \src "ls180.v:2391.6-2391.36" + attribute \src "ls180.v:2466.6-2466.36" wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2390.6-2390.37" + attribute \src "ls180.v:2465.6-2465.37" wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2393.6-2393.36" + attribute \src "ls180.v:2468.6-2468.36" wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2392.6-2392.37" + attribute \src "ls180.v:2467.6-2467.37" wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2399.12-2399.47" + attribute \src "ls180.v:2474.12-2474.47" wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2398.6-2398.42" + attribute \src "ls180.v:2473.6-2473.42" wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2401.12-2401.47" + attribute \src "ls180.v:2476.12-2476.47" wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2400.6-2400.42" + attribute \src "ls180.v:2475.6-2475.42" wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2395.6-2395.41" + attribute \src "ls180.v:2470.6-2470.41" wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2394.6-2394.42" + attribute \src "ls180.v:2469.6-2469.42" wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2397.6-2397.41" + attribute \src "ls180.v:2472.6-2472.41" wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2396.6-2396.42" + attribute \src "ls180.v:2471.6-2471.42" wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2402.6-2402.26" + attribute \src "ls180.v:2477.6-2477.26" wire \builder_csrbank8_sel - attribute \src "ls180.v:2408.12-2408.44" + attribute \src "ls180.v:2483.12-2483.44" wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2407.6-2407.39" + attribute \src "ls180.v:2482.6-2482.39" wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2410.12-2410.44" + attribute \src "ls180.v:2485.12-2485.44" wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2409.6-2409.39" + attribute \src "ls180.v:2484.6-2484.39" wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2420.12-2420.48" + attribute \src "ls180.v:2495.12-2495.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2419.6-2419.43" + attribute \src "ls180.v:2494.6-2494.43" wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2422.12-2422.48" + attribute \src "ls180.v:2497.12-2497.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2421.6-2421.43" + attribute \src "ls180.v:2496.6-2496.43" wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2416.12-2416.48" + attribute \src "ls180.v:2491.12-2491.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2415.6-2415.43" + attribute \src "ls180.v:2490.6-2490.43" wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2418.12-2418.48" + attribute \src "ls180.v:2493.12-2493.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2417.6-2417.43" + attribute \src "ls180.v:2492.6-2492.43" wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2424.12-2424.49" + attribute \src "ls180.v:2499.12-2499.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2423.6-2423.44" + attribute \src "ls180.v:2498.6-2498.44" wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2426.12-2426.49" + attribute \src "ls180.v:2501.12-2501.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2425.6-2425.44" + attribute \src "ls180.v:2500.6-2500.44" wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2412.12-2412.48" + attribute \src "ls180.v:2487.12-2487.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2411.6-2411.43" + attribute \src "ls180.v:2486.6-2486.43" wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2414.12-2414.48" + attribute \src "ls180.v:2489.12-2489.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2413.6-2413.43" + attribute \src "ls180.v:2488.6-2488.43" wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2440.12-2440.47" + attribute \src "ls180.v:2515.12-2515.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2439.6-2439.42" + attribute \src "ls180.v:2514.6-2514.42" wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2442.12-2442.47" + attribute \src "ls180.v:2517.12-2517.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2441.6-2441.42" + attribute \src "ls180.v:2516.6-2516.42" wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2436.12-2436.47" + attribute \src "ls180.v:2511.12-2511.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2435.6-2435.42" + attribute \src "ls180.v:2510.6-2510.42" wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2438.12-2438.47" + attribute \src "ls180.v:2513.12-2513.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2437.6-2437.42" + attribute \src "ls180.v:2512.6-2512.42" wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2432.12-2432.47" + attribute \src "ls180.v:2507.12-2507.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2431.6-2431.42" + attribute \src "ls180.v:2506.6-2506.42" wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2434.12-2434.47" + attribute \src "ls180.v:2509.12-2509.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2433.6-2433.42" + attribute \src "ls180.v:2508.6-2508.42" wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2428.12-2428.47" + attribute \src "ls180.v:2503.12-2503.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2427.6-2427.42" + attribute \src "ls180.v:2502.6-2502.42" wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2430.12-2430.47" + attribute \src "ls180.v:2505.12-2505.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2429.6-2429.42" + attribute \src "ls180.v:2504.6-2504.42" wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2443.6-2443.26" + attribute \src "ls180.v:2518.6-2518.26" wire \builder_csrbank9_sel - attribute \src "ls180.v:1940.6-1940.18" + attribute \src "ls180.v:2015.6-2015.18" wire \builder_done - attribute \src "ls180.v:1938.5-1938.18" + attribute \src "ls180.v:2013.5-2013.18" wire \builder_error - attribute \src "ls180.v:1935.11-1935.24" + attribute \src "ls180.v:2010.11-2010.24" wire width 3 \builder_grant - attribute \src "ls180.v:1942.13-1942.44" + attribute \src "ls180.v:2017.13-2017.44" wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1945.11-1945.44" + attribute \src "ls180.v:2020.11-2020.44" wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1944.12-1944.45" + attribute \src "ls180.v:2019.12-2019.45" wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1943.6-1943.36" + attribute \src "ls180.v:2018.6-2018.36" wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2444.13-2444.45" + attribute \src "ls180.v:2519.13-2519.45" wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2447.11-2447.45" + attribute \src "ls180.v:2522.11-2522.45" wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2446.12-2446.46" + attribute \src "ls180.v:2521.12-2521.46" wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2445.6-2445.37" + attribute \src "ls180.v:2520.6-2520.37" wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2477.13-2477.45" + attribute \src "ls180.v:2552.13-2552.45" wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2480.11-2480.45" + attribute \src "ls180.v:2555.11-2555.45" wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2479.12-2479.46" + attribute \src "ls180.v:2554.12-2554.46" wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2478.6-2478.37" + attribute \src "ls180.v:2553.6-2553.37" wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2518.13-2518.45" + attribute \src "ls180.v:2593.13-2593.45" wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2521.11-2521.45" + attribute \src "ls180.v:2596.11-2596.45" wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2520.12-2520.46" + attribute \src "ls180.v:2595.12-2595.46" wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2519.6-2519.37" + attribute \src "ls180.v:2594.6-2594.37" wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2583.13-2583.45" + attribute \src "ls180.v:2658.13-2658.45" wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2586.11-2586.45" + attribute \src "ls180.v:2661.11-2661.45" wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2585.12-2585.46" + attribute \src "ls180.v:2660.12-2660.46" wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2584.6-2584.37" + attribute \src "ls180.v:2659.6-2659.37" wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2608.13-2608.45" + attribute \src "ls180.v:2683.13-2683.45" wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2611.11-2611.45" + attribute \src "ls180.v:2686.11-2686.45" wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2610.12-2610.46" + attribute \src "ls180.v:2685.12-2685.46" wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2609.6-2609.37" + attribute \src "ls180.v:2684.6-2684.37" wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:1983.13-1983.44" + attribute \src "ls180.v:2058.13-2058.44" wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1986.11-1986.44" + attribute \src "ls180.v:2061.11-2061.44" wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1985.12-1985.45" + attribute \src "ls180.v:2060.12-2060.45" wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1984.6-1984.36" + attribute \src "ls180.v:2059.6-2059.36" wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:2012.13-2012.44" + attribute \src "ls180.v:2087.13-2087.44" wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:2015.11-2015.44" + attribute \src "ls180.v:2090.11-2090.44" wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:2014.12-2014.45" + attribute \src "ls180.v:2089.12-2089.45" wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:2013.6-2013.36" + attribute \src "ls180.v:2088.6-2088.36" wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:2025.13-2025.44" + attribute \src "ls180.v:2100.13-2100.44" wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:2028.11-2028.44" + attribute \src "ls180.v:2103.11-2103.44" wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:2027.12-2027.45" + attribute \src "ls180.v:2102.12-2102.45" wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:2026.6-2026.36" + attribute \src "ls180.v:2101.6-2101.36" wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2066.13-2066.44" + attribute \src "ls180.v:2141.13-2141.44" wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2069.11-2069.44" + attribute \src "ls180.v:2144.11-2144.44" wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2068.12-2068.45" + attribute \src "ls180.v:2143.12-2143.45" wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2067.6-2067.36" + attribute \src "ls180.v:2142.6-2142.36" wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2107.13-2107.44" + attribute \src "ls180.v:2182.13-2182.44" wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2110.11-2110.44" + attribute \src "ls180.v:2185.11-2185.44" wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2109.12-2109.45" + attribute \src "ls180.v:2184.12-2184.45" wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2108.6-2108.36" + attribute \src "ls180.v:2183.6-2183.36" wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2172.13-2172.44" + attribute \src "ls180.v:2247.13-2247.44" wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2175.11-2175.44" + attribute \src "ls180.v:2250.11-2250.44" wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2174.12-2174.45" + attribute \src "ls180.v:2249.12-2249.45" wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2173.6-2173.36" + attribute \src "ls180.v:2248.6-2248.36" wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2305.13-2305.44" + attribute \src "ls180.v:2380.13-2380.44" wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2308.11-2308.44" + attribute \src "ls180.v:2383.11-2383.44" wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2307.12-2307.45" + attribute \src "ls180.v:2382.12-2382.45" wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2306.6-2306.36" + attribute \src "ls180.v:2381.6-2381.36" wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2386.13-2386.44" + attribute \src "ls180.v:2461.13-2461.44" wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2389.11-2389.44" + attribute \src "ls180.v:2464.11-2464.44" wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2388.12-2388.45" + attribute \src "ls180.v:2463.12-2463.45" wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2387.6-2387.36" + attribute \src "ls180.v:2462.6-2462.36" wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2403.13-2403.44" + attribute \src "ls180.v:2478.13-2478.44" wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2406.11-2406.44" + attribute \src "ls180.v:2481.11-2481.44" wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2405.12-2405.45" + attribute \src "ls180.v:2480.12-2480.45" wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2404.6-2404.36" + attribute \src "ls180.v:2479.6-2479.36" wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1908.12-1908.35" + attribute \src "ls180.v:1975.12-1975.35" wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2637.12-2637.47" + attribute \src "ls180.v:2712.12-2712.47" wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2638.5-2638.43" + attribute \src "ls180.v:2713.5-2713.43" wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1911.12-1911.37" + attribute \src "ls180.v:1993.5-1993.48" + wire \builder_libresocsim_converted_interface_ack + attribute \src "ls180.v:1987.13-1987.56" + wire width 30 \builder_libresocsim_converted_interface_adr + attribute \src "ls180.v:1996.12-1996.55" + wire width 2 \builder_libresocsim_converted_interface_bte + attribute \src "ls180.v:1995.12-1995.55" + wire width 3 \builder_libresocsim_converted_interface_cti + attribute \src "ls180.v:1991.6-1991.49" + wire \builder_libresocsim_converted_interface_cyc + attribute \src "ls180.v:1989.12-1989.57" + wire width 64 \builder_libresocsim_converted_interface_dat_r + attribute \src "ls180.v:1988.13-1988.58" + wire width 64 \builder_libresocsim_converted_interface_dat_w + attribute \src "ls180.v:1997.5-1997.48" + wire \builder_libresocsim_converted_interface_err + attribute \src "ls180.v:1990.12-1990.55" + wire width 8 \builder_libresocsim_converted_interface_sel + attribute \src "ls180.v:1992.6-1992.49" + wire \builder_libresocsim_converted_interface_stb + attribute \src "ls180.v:1994.6-1994.48" + wire \builder_libresocsim_converted_interface_we + attribute \src "ls180.v:1978.12-1978.37" wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1910.11-1910.36" + attribute \src "ls180.v:1977.11-1977.36" wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2635.11-2635.48" + attribute \src "ls180.v:2710.11-2710.48" wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2636.5-2636.45" + attribute \src "ls180.v:2711.5-2711.45" wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1909.5-1909.27" + attribute \src "ls180.v:1976.5-1976.27" wire \builder_libresocsim_we - attribute \src "ls180.v:2639.5-2639.39" + attribute \src "ls180.v:2714.5-2714.39" wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2640.5-2640.42" + attribute \src "ls180.v:2715.5-2715.42" wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1918.5-1918.37" + attribute \src "ls180.v:1985.5-1985.37" wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1912.13-1912.45" + attribute \src "ls180.v:1979.12-1979.44" wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1921.12-1921.44" - wire width 2 \builder_libresocsim_wishbone_bte - attribute \src "ls180.v:1920.12-1920.44" - wire width 3 \builder_libresocsim_wishbone_cti - attribute \src "ls180.v:1916.6-1916.38" + attribute \src "ls180.v:1983.5-1983.37" wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1914.12-1914.46" + attribute \src "ls180.v:1981.12-1981.46" wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1913.13-1913.47" + attribute \src "ls180.v:1980.12-1980.46" wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1922.5-1922.37" - wire \builder_libresocsim_wishbone_err - attribute \src "ls180.v:1915.12-1915.44" + attribute \src "ls180.v:1982.11-1982.43" wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1917.6-1917.38" + attribute \src "ls180.v:1984.5-1984.37" wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1919.6-1919.37" + attribute \src "ls180.v:1986.5-1986.36" wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1811.5-1811.20" + attribute \src "ls180.v:1878.5-1878.20" wire \builder_locked0 - attribute \src "ls180.v:1812.5-1812.20" + attribute \src "ls180.v:1879.5-1879.20" wire \builder_locked1 - attribute \src "ls180.v:1813.5-1813.20" + attribute \src "ls180.v:1880.5-1880.20" wire \builder_locked2 - attribute \src "ls180.v:1814.5-1814.20" + attribute \src "ls180.v:1881.5-1881.20" wire \builder_locked3 - attribute \src "ls180.v:1798.11-1798.41" + attribute \src "ls180.v:1865.11-1865.41" wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1797.11-1797.36" + attribute \src "ls180.v:1864.11-1864.36" wire width 3 \builder_multiplexer_state attribute \no_retiming "true" - attribute \src "ls180.v:2744.32-2744.59" + attribute \src "ls180.v:2819.32-2819.59" wire \builder_multiregimpl0_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2745.32-2745.59" + attribute \src "ls180.v:2820.32-2820.59" wire \builder_multiregimpl0_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2764.32-2764.60" + attribute \src "ls180.v:2839.32-2839.60" wire \builder_multiregimpl10_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2765.32-2765.60" + attribute \src "ls180.v:2840.32-2840.60" wire \builder_multiregimpl10_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2766.32-2766.60" + attribute \src "ls180.v:2841.32-2841.60" wire \builder_multiregimpl11_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2767.32-2767.60" + attribute \src "ls180.v:2842.32-2842.60" wire \builder_multiregimpl11_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2768.32-2768.60" + attribute \src "ls180.v:2843.32-2843.60" wire \builder_multiregimpl12_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2769.32-2769.60" + attribute \src "ls180.v:2844.32-2844.60" wire \builder_multiregimpl12_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2770.32-2770.60" + attribute \src "ls180.v:2845.32-2845.60" wire \builder_multiregimpl13_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2771.32-2771.60" + attribute \src "ls180.v:2846.32-2846.60" wire \builder_multiregimpl13_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2772.32-2772.60" + attribute \src "ls180.v:2847.32-2847.60" wire \builder_multiregimpl14_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2773.32-2773.60" + attribute \src "ls180.v:2848.32-2848.60" wire \builder_multiregimpl14_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2774.32-2774.60" + attribute \src "ls180.v:2849.32-2849.60" wire \builder_multiregimpl15_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2775.32-2775.60" + attribute \src "ls180.v:2850.32-2850.60" wire \builder_multiregimpl15_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2776.32-2776.60" + attribute \src "ls180.v:2851.32-2851.60" wire \builder_multiregimpl16_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2777.32-2777.60" + attribute \src "ls180.v:2852.32-2852.60" wire \builder_multiregimpl16_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2746.32-2746.59" + attribute \src "ls180.v:2821.32-2821.59" wire \builder_multiregimpl1_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2747.32-2747.59" + attribute \src "ls180.v:2822.32-2822.59" wire \builder_multiregimpl1_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2748.32-2748.59" + attribute \src "ls180.v:2823.32-2823.59" wire \builder_multiregimpl2_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2749.32-2749.59" + attribute \src "ls180.v:2824.32-2824.59" wire \builder_multiregimpl2_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2750.32-2750.59" + attribute \src "ls180.v:2825.32-2825.59" wire \builder_multiregimpl3_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2751.32-2751.59" + attribute \src "ls180.v:2826.32-2826.59" wire \builder_multiregimpl3_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2752.32-2752.59" + attribute \src "ls180.v:2827.32-2827.59" wire \builder_multiregimpl4_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2753.32-2753.59" + attribute \src "ls180.v:2828.32-2828.59" wire \builder_multiregimpl4_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2754.32-2754.59" + attribute \src "ls180.v:2829.32-2829.59" wire \builder_multiregimpl5_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2755.32-2755.59" + attribute \src "ls180.v:2830.32-2830.59" wire \builder_multiregimpl5_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2756.32-2756.59" + attribute \src "ls180.v:2831.32-2831.59" wire \builder_multiregimpl6_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2757.32-2757.59" + attribute \src "ls180.v:2832.32-2832.59" wire \builder_multiregimpl6_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2758.32-2758.59" + attribute \src "ls180.v:2833.32-2833.59" wire \builder_multiregimpl7_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2759.32-2759.59" + attribute \src "ls180.v:2834.32-2834.59" wire \builder_multiregimpl7_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2760.32-2760.59" + attribute \src "ls180.v:2835.32-2835.59" wire \builder_multiregimpl8_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2761.32-2761.59" + attribute \src "ls180.v:2836.32-2836.59" wire \builder_multiregimpl8_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2762.32-2762.59" + attribute \src "ls180.v:2837.32-2837.59" wire \builder_multiregimpl9_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2763.32-2763.59" + attribute \src "ls180.v:2838.32-2838.59" wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1816.5-1816.36" + attribute \src "ls180.v:1883.5-1883.36" wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1817.5-1817.36" + attribute \src "ls180.v:1884.5-1884.36" wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1818.5-1818.36" + attribute \src "ls180.v:1885.5-1885.36" wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1819.5-1819.36" + attribute \src "ls180.v:1886.5-1886.36" wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1815.5-1815.35" + attribute \src "ls180.v:1882.5-1882.35" wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2634.11-2634.29" + attribute \src "ls180.v:2709.11-2709.29" wire width 2 \builder_next_state - attribute \src "ls180.v:1788.11-1788.39" + attribute \src "ls180.v:1855.11-1855.39" wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1787.11-1787.34" + attribute \src "ls180.v:1854.11-1854.34" wire width 2 \builder_refresher_state - attribute \src "ls180.v:1934.12-1934.27" + attribute \src "ls180.v:2009.12-2009.27" wire width 5 \builder_request - attribute \src "ls180.v:1801.6-1801.28" + attribute \src "ls180.v:1868.6-1868.28" wire \builder_roundrobin0_ce - attribute \src "ls180.v:1800.6-1800.31" + attribute \src "ls180.v:1867.6-1867.31" wire \builder_roundrobin0_grant - attribute \src "ls180.v:1799.6-1799.33" + attribute \src "ls180.v:1866.6-1866.33" wire \builder_roundrobin0_request - attribute \src "ls180.v:1804.6-1804.28" + attribute \src "ls180.v:1871.6-1871.28" wire \builder_roundrobin1_ce - attribute \src "ls180.v:1803.6-1803.31" + attribute \src "ls180.v:1870.6-1870.31" wire \builder_roundrobin1_grant - attribute \src "ls180.v:1802.6-1802.33" + attribute \src "ls180.v:1869.6-1869.33" wire \builder_roundrobin1_request - attribute \src "ls180.v:1807.6-1807.28" + attribute \src "ls180.v:1874.6-1874.28" wire \builder_roundrobin2_ce - attribute \src "ls180.v:1806.6-1806.31" + attribute \src "ls180.v:1873.6-1873.31" wire \builder_roundrobin2_grant - attribute \src "ls180.v:1805.6-1805.33" + attribute \src "ls180.v:1872.6-1872.33" wire \builder_roundrobin2_request - attribute \src "ls180.v:1810.6-1810.28" + attribute \src "ls180.v:1877.6-1877.28" wire \builder_roundrobin3_ce - attribute \src "ls180.v:1809.6-1809.31" + attribute \src "ls180.v:1876.6-1876.31" wire \builder_roundrobin3_grant - attribute \src "ls180.v:1808.6-1808.33" + attribute \src "ls180.v:1875.6-1875.33" wire \builder_roundrobin3_request - attribute \src "ls180.v:1897.11-1897.44" + attribute \src "ls180.v:1964.11-1964.44" wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1896.11-1896.39" + attribute \src "ls180.v:1963.11-1963.39" wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1865.5-1865.50" + attribute \src "ls180.v:1932.5-1932.50" wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1864.5-1864.45" + attribute \src "ls180.v:1931.5-1931.45" wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1877.11-1877.40" + attribute \src "ls180.v:1944.11-1944.40" wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1876.11-1876.35" + attribute \src "ls180.v:1943.11-1943.35" wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1901.5-1901.42" + attribute \src "ls180.v:1968.5-1968.42" wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1900.5-1900.37" + attribute \src "ls180.v:1967.5-1967.37" wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1905.11-1905.58" + attribute \src "ls180.v:1972.11-1972.58" wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1904.11-1904.53" + attribute \src "ls180.v:1971.11-1971.53" wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1853.11-1853.39" + attribute \src "ls180.v:1920.11-1920.39" wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1852.11-1852.34" + attribute \src "ls180.v:1919.11-1919.34" wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1841.11-1841.45" + attribute \src "ls180.v:1908.11-1908.45" wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1840.11-1840.40" + attribute \src "ls180.v:1907.11-1907.40" wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1837.11-1837.45" + attribute \src "ls180.v:1904.11-1904.45" wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1836.11-1836.40" + attribute \src "ls180.v:1903.11-1903.40" wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1849.5-1849.39" + attribute \src "ls180.v:1916.5-1916.39" wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1848.5-1848.34" + attribute \src "ls180.v:1915.5-1915.34" wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1857.11-1857.46" + attribute \src "ls180.v:1924.11-1924.46" wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1856.11-1856.41" + attribute \src "ls180.v:1923.11-1923.41" wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1833.5-1833.39" + attribute \src "ls180.v:1900.5-1900.39" wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1832.5-1832.34" + attribute \src "ls180.v:1899.5-1899.34" wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1929.5-1929.23" + attribute \src "ls180.v:2004.5-2004.23" wire \builder_shared_ack - attribute \src "ls180.v:1923.13-1923.31" + attribute \src "ls180.v:1998.13-1998.31" wire width 30 \builder_shared_adr - attribute \src "ls180.v:1932.12-1932.30" + attribute \src "ls180.v:2007.12-2007.30" wire width 2 \builder_shared_bte - attribute \src "ls180.v:1931.12-1931.30" + attribute \src "ls180.v:2006.12-2006.30" wire width 3 \builder_shared_cti - attribute \src "ls180.v:1927.6-1927.24" + attribute \src "ls180.v:2002.6-2002.24" wire \builder_shared_cyc - attribute \src "ls180.v:1925.12-1925.32" + attribute \src "ls180.v:2000.12-2000.32" wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1924.13-1924.33" + attribute \src "ls180.v:1999.13-1999.33" wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1933.6-1933.24" + attribute \src "ls180.v:2008.6-2008.24" wire \builder_shared_err - attribute \src "ls180.v:1926.12-1926.30" + attribute \src "ls180.v:2001.12-2001.30" wire width 4 \builder_shared_sel - attribute \src "ls180.v:1928.6-1928.24" + attribute \src "ls180.v:2003.6-2003.24" wire \builder_shared_stb - attribute \src "ls180.v:1930.6-1930.23" + attribute \src "ls180.v:2005.6-2005.23" wire \builder_shared_we - attribute \src "ls180.v:1936.11-1936.28" - wire width 8 \builder_slave_sel - attribute \src "ls180.v:1937.11-1937.30" - wire width 8 \builder_slave_sel_r - attribute \src "ls180.v:1825.11-1825.40" + attribute \src "ls180.v:2011.12-2011.29" + wire width 13 \builder_slave_sel + attribute \src "ls180.v:2012.12-2012.31" + wire width 13 \builder_slave_sel_r + attribute \src "ls180.v:1892.11-1892.40" wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1824.11-1824.35" + attribute \src "ls180.v:1891.11-1891.35" wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1829.11-1829.40" + attribute \src "ls180.v:1896.11-1896.40" wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1828.11-1828.35" + attribute \src "ls180.v:1895.11-1895.35" wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2633.11-2633.24" + attribute \src "ls180.v:2708.11-2708.24" wire width 2 \builder_state - attribute \src "ls180.v:2686.5-2686.32" + attribute \src "ls180.v:2761.5-2761.32" wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2687.5-2687.32" + attribute \src "ls180.v:2762.5-2762.32" wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2679.11-2679.40" + attribute \src "ls180.v:2754.11-2754.40" wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2680.12-2680.41" + attribute \src "ls180.v:2755.12-2755.41" wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2681.5-2681.34" + attribute \src "ls180.v:2756.5-2756.34" wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2682.5-2682.34" + attribute \src "ls180.v:2757.5-2757.34" wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2683.5-2683.34" + attribute \src "ls180.v:2758.5-2758.34" wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2684.5-2684.34" + attribute \src "ls180.v:2759.5-2759.34" wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2685.5-2685.34" + attribute \src "ls180.v:2760.5-2760.34" wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1939.6-1939.18" + attribute \src "ls180.v:2014.6-2014.18" wire \builder_wait - attribute \src "ls180.v:19.19-19.23" - wire width 3 input 15 \eint - attribute \src "ls180.v:137.12-137.18" + attribute \src "ls180.v:42.19-42.23" + wire width 3 input 38 \eint + attribute \src "ls180.v:206.12-206.18" wire width 3 \eint_1 - attribute \src "ls180.v:28.20-28.26" - wire width 16 input 24 \gpio_i - attribute \src "ls180.v:29.21-29.27" - wire width 16 output 25 \gpio_o - attribute \src "ls180.v:30.21-30.28" - wire width 16 output 26 \gpio_oe - attribute \src "ls180.v:31.14-31.21" - wire output 27 \i2c_scl - attribute \src "ls180.v:32.13-32.22" - wire input 28 \i2c_sda_i - attribute \src "ls180.v:33.14-33.23" - wire output 29 \i2c_sda_o - attribute \src "ls180.v:34.14-34.24" - wire output 30 \i2c_sda_oe + attribute \src "ls180.v:18.21-18.27" + wire width 16 output 14 \gpio_i + attribute \src "ls180.v:19.20-19.26" + wire width 16 output 15 \gpio_o + attribute \src "ls180.v:20.20-20.27" + wire width 16 output 16 \gpio_oe + attribute \src "ls180.v:14.14-14.21" + wire output 10 \i2c_scl + attribute \src "ls180.v:15.14-15.23" + wire output 11 \i2c_sda_i + attribute \src "ls180.v:16.14-16.23" + wire output 12 \i2c_sda_o + attribute \src "ls180.v:17.14-17.24" + wire output 13 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -231673,208 +248092,310 @@ module \ls180 wire output 47 \jtag_tdo attribute \src "ls180.v:48.13-48.21" wire input 44 \jtag_tms - attribute \src "ls180.v:879.6-879.18" + attribute \src "ls180.v:940.6-940.18" wire \main_ack_cmd - attribute \src "ls180.v:881.6-881.20" + attribute \src "ls180.v:942.6-942.20" wire \main_ack_rdata - attribute \src "ls180.v:880.6-880.20" + attribute \src "ls180.v:941.6-941.20" wire \main_ack_wdata - attribute \src "ls180.v:877.5-877.22" + attribute \src "ls180.v:938.5-938.22" wire \main_cmd_consumed - attribute \src "ls180.v:874.5-874.27" + attribute \src "ls180.v:321.5-321.28" + wire \main_converter0_counter + attribute \src "ls180.v:1844.5-1844.50" + wire \main_converter0_counter_converter0_next_value + attribute \src "ls180.v:1845.5-1845.53" + wire \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:323.12-323.33" + wire width 64 \main_converter0_dat_r + attribute \src "ls180.v:322.6-322.27" + wire \main_converter0_reset + attribute \src "ls180.v:320.5-320.25" + wire \main_converter0_skip + attribute \src "ls180.v:336.5-336.28" + wire \main_converter1_counter + attribute \src "ls180.v:1848.5-1848.50" + wire \main_converter1_counter_converter1_next_value + attribute \src "ls180.v:1849.5-1849.53" + wire \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:338.12-338.33" + wire width 64 \main_converter1_dat_r + attribute \src "ls180.v:337.6-337.27" + wire \main_converter1_reset + attribute \src "ls180.v:335.5-335.25" + wire \main_converter1_skip + attribute \src "ls180.v:935.5-935.27" wire \main_converter_counter - attribute \src "ls180.v:1822.5-1822.48" + attribute \src "ls180.v:1889.5-1889.48" wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1823.5-1823.51" + attribute \src "ls180.v:1890.5-1890.51" wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:876.12-876.32" + attribute \src "ls180.v:937.12-937.32" wire width 32 \main_converter_dat_r - attribute \src "ls180.v:875.6-875.26" + attribute \src "ls180.v:936.6-936.26" wire \main_converter_reset - attribute \src "ls180.v:873.5-873.24" + attribute \src "ls180.v:934.5-934.24" wire \main_converter_skip - attribute \src "ls180.v:303.6-303.23" + attribute \src "ls180.v:352.6-352.23" wire \main_dfi_p0_act_n - attribute \src "ls180.v:294.13-294.32" + attribute \src "ls180.v:343.13-343.32" wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:295.12-295.28" + attribute \src "ls180.v:344.12-344.28" wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:296.6-296.23" + attribute \src "ls180.v:345.6-345.23" wire \main_dfi_p0_cas_n - attribute \src "ls180.v:300.6-300.21" + attribute \src "ls180.v:349.6-349.21" wire \main_dfi_p0_cke - attribute \src "ls180.v:297.6-297.22" + attribute \src "ls180.v:346.6-346.22" wire \main_dfi_p0_cs_n - attribute \src "ls180.v:301.6-301.21" + attribute \src "ls180.v:350.6-350.21" wire \main_dfi_p0_odt - attribute \src "ls180.v:298.6-298.23" + attribute \src "ls180.v:347.6-347.23" wire \main_dfi_p0_ras_n - attribute \src "ls180.v:308.12-308.30" + attribute \src "ls180.v:357.12-357.30" wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:307.6-307.27" + attribute \src "ls180.v:356.6-356.27" wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:309.5-309.29" + attribute \src "ls180.v:358.5-358.29" wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:302.6-302.25" + attribute \src "ls180.v:351.6-351.25" wire \main_dfi_p0_reset_n - attribute \src "ls180.v:299.6-299.22" + attribute \src "ls180.v:348.6-348.22" wire \main_dfi_p0_we_n - attribute \src "ls180.v:304.13-304.31" + attribute \src "ls180.v:353.13-353.31" wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:305.6-305.27" + attribute \src "ls180.v:354.6-354.27" wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:306.12-306.35" + attribute \src "ls180.v:355.12-355.35" wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1108.12-1108.22" + attribute \src "ls180.v:1175.12-1175.22" wire width 24 \main_dummy - attribute \src "ls180.v:1025.5-1025.20" - wire \main_gpio_oe_re - attribute \src "ls180.v:1024.12-1024.32" - wire width 16 \main_gpio_oe_storage - attribute \src "ls180.v:1029.5-1029.21" - wire \main_gpio_out_re - attribute \src "ls180.v:1028.12-1028.33" - wire width 16 \main_gpio_out_storage - attribute \src "ls180.v:1030.13-1030.29" - wire width 16 \main_gpio_pads_i - attribute \src "ls180.v:1031.13-1031.29" - wire width 16 \main_gpio_pads_o - attribute \src "ls180.v:1032.13-1032.30" - wire width 16 \main_gpio_pads_oe - attribute \src "ls180.v:1026.12-1026.28" - wire width 16 \main_gpio_status - attribute \src "ls180.v:1027.6-1027.18" - wire \main_gpio_we - attribute \src "ls180.v:1130.6-1130.17" + attribute \src "ls180.v:1085.12-1085.45" + wire width 16 \main_gpiotristateasic0_oe_storage + attribute \src "ls180.v:1087.12-1087.46" + wire width 16 \main_gpiotristateasic0_out_storage + attribute \src "ls180.v:1088.13-1088.42" + wire width 16 \main_gpiotristateasic0_pads_i + attribute \src "ls180.v:1089.13-1089.42" + wire width 16 \main_gpiotristateasic0_pads_o + attribute \src "ls180.v:1090.13-1090.43" + wire width 16 \main_gpiotristateasic0_pads_oe + attribute \src "ls180.v:1086.12-1086.41" + wire width 16 \main_gpiotristateasic0_status + attribute \src "ls180.v:1092.5-1092.33" + wire \main_gpiotristateasic1_oe_re + attribute \src "ls180.v:1091.12-1091.45" + wire width 16 \main_gpiotristateasic1_oe_storage + attribute \src "ls180.v:1096.5-1096.34" + wire \main_gpiotristateasic1_out_re + attribute \src "ls180.v:1095.12-1095.46" + wire width 16 \main_gpiotristateasic1_out_storage + attribute \src "ls180.v:1097.13-1097.42" + wire width 16 \main_gpiotristateasic1_pads_i + attribute \src "ls180.v:1098.13-1098.42" + wire width 16 \main_gpiotristateasic1_pads_o + attribute \src "ls180.v:1099.13-1099.43" + wire width 16 \main_gpiotristateasic1_pads_oe + attribute \src "ls180.v:1093.12-1093.41" + wire width 16 \main_gpiotristateasic1_status + attribute \src "ls180.v:1094.6-1094.31" + wire \main_gpiotristateasic1_we + attribute \src "ls180.v:1197.6-1197.17" wire \main_i2c_oe - attribute \src "ls180.v:1133.5-1133.16" + attribute \src "ls180.v:1200.5-1200.16" wire \main_i2c_re - attribute \src "ls180.v:1129.6-1129.18" + attribute \src "ls180.v:1196.6-1196.18" wire \main_i2c_scl - attribute \src "ls180.v:1131.6-1131.19" + attribute \src "ls180.v:1198.6-1198.19" wire \main_i2c_sda0 - attribute \src "ls180.v:1134.6-1134.19" + attribute \src "ls180.v:1201.6-1201.19" wire \main_i2c_sda1 - attribute \src "ls180.v:1135.6-1135.21" + attribute \src "ls180.v:1202.6-1202.21" wire \main_i2c_status - attribute \src "ls180.v:1132.11-1132.27" + attribute \src "ls180.v:1199.11-1199.27" wire width 3 \main_i2c_storage - attribute \src "ls180.v:1136.6-1136.17" + attribute \src "ls180.v:1203.6-1203.17" wire \main_i2c_we - attribute \src "ls180.v:293.5-293.17" + attribute \src "ls180.v:342.5-342.17" wire \main_int_rst - attribute \src "ls180.v:1596.6-1596.29" + attribute \src "ls180.v:1663.6-1663.29" wire \main_interface0_bus_ack - attribute \src "ls180.v:1590.13-1590.36" + attribute \src "ls180.v:1657.13-1657.36" wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1599.11-1599.34" + attribute \src "ls180.v:1666.11-1666.34" wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1598.11-1598.34" + attribute \src "ls180.v:1665.11-1665.34" wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1594.6-1594.29" + attribute \src "ls180.v:1661.6-1661.29" wire \main_interface0_bus_cyc - attribute \src "ls180.v:1592.13-1592.38" - wire width 32 \main_interface0_bus_dat_r - attribute \src "ls180.v:1591.13-1591.38" - wire width 32 \main_interface0_bus_dat_w - attribute \src "ls180.v:1600.6-1600.29" + attribute \src "ls180.v:1659.13-1659.38" + wire width 64 \main_interface0_bus_dat_r + attribute \src "ls180.v:1658.13-1658.38" + wire width 64 \main_interface0_bus_dat_w + attribute \src "ls180.v:1667.6-1667.29" wire \main_interface0_bus_err - attribute \src "ls180.v:1593.12-1593.35" - wire width 4 \main_interface0_bus_sel - attribute \src "ls180.v:1595.6-1595.29" + attribute \src "ls180.v:1660.12-1660.35" + wire width 8 \main_interface0_bus_sel + attribute \src "ls180.v:1662.6-1662.29" wire \main_interface0_bus_stb - attribute \src "ls180.v:1597.6-1597.28" + attribute \src "ls180.v:1664.6-1664.28" wire \main_interface0_bus_we - attribute \src "ls180.v:251.5-251.32" + attribute \src "ls180.v:315.5-315.44" + wire \main_interface0_converted_interface_ack + attribute \src "ls180.v:309.13-309.52" + wire width 30 \main_interface0_converted_interface_adr + attribute \src "ls180.v:318.12-318.51" + wire width 2 \main_interface0_converted_interface_bte + attribute \src "ls180.v:317.12-317.51" + wire width 3 \main_interface0_converted_interface_cti + attribute \src "ls180.v:313.6-313.45" + wire \main_interface0_converted_interface_cyc + attribute \src "ls180.v:311.13-311.54" + wire width 64 \main_interface0_converted_interface_dat_r + attribute \src "ls180.v:310.13-310.54" + wire width 64 \main_interface0_converted_interface_dat_w + attribute \src "ls180.v:319.5-319.44" + wire \main_interface0_converted_interface_err + attribute \src "ls180.v:312.12-312.51" + wire width 8 \main_interface0_converted_interface_sel + attribute \src "ls180.v:314.6-314.45" + wire \main_interface0_converted_interface_stb + attribute \src "ls180.v:316.6-316.44" + wire \main_interface0_converted_interface_we + attribute \src "ls180.v:255.5-255.32" wire \main_interface0_ram_bus_ack - attribute \src "ls180.v:245.13-245.40" + attribute \src "ls180.v:249.13-249.40" wire width 30 \main_interface0_ram_bus_adr - attribute \src "ls180.v:254.12-254.39" + attribute \src "ls180.v:258.12-258.39" wire width 2 \main_interface0_ram_bus_bte - attribute \src "ls180.v:253.12-253.39" + attribute \src "ls180.v:257.12-257.39" wire width 3 \main_interface0_ram_bus_cti - attribute \src "ls180.v:249.6-249.33" + attribute \src "ls180.v:253.6-253.33" wire \main_interface0_ram_bus_cyc - attribute \src "ls180.v:247.13-247.42" - wire width 32 \main_interface0_ram_bus_dat_r - attribute \src "ls180.v:246.13-246.42" - wire width 32 \main_interface0_ram_bus_dat_w - attribute \src "ls180.v:255.5-255.32" + attribute \src "ls180.v:251.13-251.42" + wire width 64 \main_interface0_ram_bus_dat_r + attribute \src "ls180.v:250.13-250.42" + wire width 64 \main_interface0_ram_bus_dat_w + attribute \src "ls180.v:259.5-259.32" wire \main_interface0_ram_bus_err - attribute \src "ls180.v:248.12-248.39" - wire width 4 \main_interface0_ram_bus_sel - attribute \src "ls180.v:250.6-250.33" + attribute \src "ls180.v:252.12-252.39" + wire width 8 \main_interface0_ram_bus_sel + attribute \src "ls180.v:254.6-254.33" wire \main_interface0_ram_bus_stb - attribute \src "ls180.v:252.6-252.32" + attribute \src "ls180.v:256.6-256.32" wire \main_interface0_ram_bus_we - attribute \src "ls180.v:1687.6-1687.29" + attribute \src "ls180.v:1754.6-1754.29" wire \main_interface1_bus_ack - attribute \src "ls180.v:1681.12-1681.35" + attribute \src "ls180.v:1748.12-1748.35" wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1690.11-1690.34" + attribute \src "ls180.v:1757.11-1757.34" wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1689.11-1689.34" + attribute \src "ls180.v:1756.11-1756.34" wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1685.5-1685.28" + attribute \src "ls180.v:1752.5-1752.28" wire \main_interface1_bus_cyc - attribute \src "ls180.v:1683.13-1683.38" - wire width 32 \main_interface1_bus_dat_r - attribute \src "ls180.v:1682.12-1682.37" - wire width 32 \main_interface1_bus_dat_w - attribute \src "ls180.v:1691.6-1691.29" + attribute \src "ls180.v:1750.13-1750.38" + wire width 64 \main_interface1_bus_dat_r + attribute \src "ls180.v:1749.12-1749.37" + wire width 64 \main_interface1_bus_dat_w + attribute \src "ls180.v:1758.6-1758.29" wire \main_interface1_bus_err - attribute \src "ls180.v:1684.11-1684.34" - wire width 4 \main_interface1_bus_sel - attribute \src "ls180.v:1686.5-1686.28" + attribute \src "ls180.v:1751.11-1751.34" + wire width 8 \main_interface1_bus_sel + attribute \src "ls180.v:1753.5-1753.28" wire \main_interface1_bus_stb - attribute \src "ls180.v:1688.5-1688.27" + attribute \src "ls180.v:1755.5-1755.27" wire \main_interface1_bus_we - attribute \src "ls180.v:266.5-266.32" + attribute \src "ls180.v:330.5-330.44" + wire \main_interface1_converted_interface_ack + attribute \src "ls180.v:324.13-324.52" + wire width 30 \main_interface1_converted_interface_adr + attribute \src "ls180.v:333.12-333.51" + wire width 2 \main_interface1_converted_interface_bte + attribute \src "ls180.v:332.12-332.51" + wire width 3 \main_interface1_converted_interface_cti + attribute \src "ls180.v:328.6-328.45" + wire \main_interface1_converted_interface_cyc + attribute \src "ls180.v:326.13-326.54" + wire width 64 \main_interface1_converted_interface_dat_r + attribute \src "ls180.v:325.13-325.54" + wire width 64 \main_interface1_converted_interface_dat_w + attribute \src "ls180.v:334.5-334.44" + wire \main_interface1_converted_interface_err + attribute \src "ls180.v:327.12-327.51" + wire width 8 \main_interface1_converted_interface_sel + attribute \src "ls180.v:329.6-329.45" + wire \main_interface1_converted_interface_stb + attribute \src "ls180.v:331.6-331.44" + wire \main_interface1_converted_interface_we + attribute \src "ls180.v:270.5-270.32" wire \main_interface1_ram_bus_ack - attribute \src "ls180.v:260.13-260.40" + attribute \src "ls180.v:264.13-264.40" wire width 30 \main_interface1_ram_bus_adr - attribute \src "ls180.v:269.12-269.39" + attribute \src "ls180.v:273.12-273.39" wire width 2 \main_interface1_ram_bus_bte - attribute \src "ls180.v:268.12-268.39" + attribute \src "ls180.v:272.12-272.39" wire width 3 \main_interface1_ram_bus_cti - attribute \src "ls180.v:264.6-264.33" + attribute \src "ls180.v:268.6-268.33" wire \main_interface1_ram_bus_cyc - attribute \src "ls180.v:262.13-262.42" - wire width 32 \main_interface1_ram_bus_dat_r - attribute \src "ls180.v:261.13-261.42" - wire width 32 \main_interface1_ram_bus_dat_w - attribute \src "ls180.v:270.5-270.32" + attribute \src "ls180.v:266.13-266.42" + wire width 64 \main_interface1_ram_bus_dat_r + attribute \src "ls180.v:265.13-265.42" + wire width 64 \main_interface1_ram_bus_dat_w + attribute \src "ls180.v:274.5-274.32" wire \main_interface1_ram_bus_err - attribute \src "ls180.v:263.12-263.39" - wire width 4 \main_interface1_ram_bus_sel - attribute \src "ls180.v:265.6-265.33" + attribute \src "ls180.v:267.12-267.39" + wire width 8 \main_interface1_ram_bus_sel + attribute \src "ls180.v:269.6-269.33" wire \main_interface1_ram_bus_stb - attribute \src "ls180.v:267.6-267.32" + attribute \src "ls180.v:271.6-271.32" wire \main_interface1_ram_bus_we - attribute \src "ls180.v:281.5-281.32" + attribute \src "ls180.v:285.5-285.32" wire \main_interface2_ram_bus_ack - attribute \src "ls180.v:275.13-275.40" + attribute \src "ls180.v:279.13-279.40" wire width 30 \main_interface2_ram_bus_adr - attribute \src "ls180.v:284.12-284.39" + attribute \src "ls180.v:288.12-288.39" wire width 2 \main_interface2_ram_bus_bte - attribute \src "ls180.v:283.12-283.39" + attribute \src "ls180.v:287.12-287.39" wire width 3 \main_interface2_ram_bus_cti - attribute \src "ls180.v:279.6-279.33" + attribute \src "ls180.v:283.6-283.33" wire \main_interface2_ram_bus_cyc - attribute \src "ls180.v:277.13-277.42" - wire width 32 \main_interface2_ram_bus_dat_r - attribute \src "ls180.v:276.13-276.42" - wire width 32 \main_interface2_ram_bus_dat_w - attribute \src "ls180.v:285.5-285.32" + attribute \src "ls180.v:281.13-281.42" + wire width 64 \main_interface2_ram_bus_dat_r + attribute \src "ls180.v:280.13-280.42" + wire width 64 \main_interface2_ram_bus_dat_w + attribute \src "ls180.v:289.5-289.32" wire \main_interface2_ram_bus_err - attribute \src "ls180.v:278.12-278.39" - wire width 4 \main_interface2_ram_bus_sel - attribute \src "ls180.v:280.6-280.33" + attribute \src "ls180.v:282.12-282.39" + wire width 8 \main_interface2_ram_bus_sel + attribute \src "ls180.v:284.6-284.33" wire \main_interface2_ram_bus_stb - attribute \src "ls180.v:282.6-282.32" + attribute \src "ls180.v:286.6-286.32" wire \main_interface2_ram_bus_we - attribute \src "ls180.v:214.12-214.32" - wire width 7 \main_libresocsim_adr + attribute \src "ls180.v:300.5-300.32" + wire \main_interface3_ram_bus_ack + attribute \src "ls180.v:294.13-294.40" + wire width 30 \main_interface3_ram_bus_adr + attribute \src "ls180.v:303.12-303.39" + wire width 2 \main_interface3_ram_bus_bte + attribute \src "ls180.v:302.12-302.39" + wire width 3 \main_interface3_ram_bus_cti + attribute \src "ls180.v:298.6-298.33" + wire \main_interface3_ram_bus_cyc + attribute \src "ls180.v:296.13-296.42" + wire width 64 \main_interface3_ram_bus_dat_r + attribute \src "ls180.v:295.13-295.42" + wire width 64 \main_interface3_ram_bus_dat_w + attribute \src "ls180.v:304.5-304.32" + wire \main_interface3_ram_bus_err + attribute \src "ls180.v:297.12-297.39" + wire width 8 \main_interface3_ram_bus_sel + attribute \src "ls180.v:299.6-299.33" + wire \main_interface3_ram_bus_stb + attribute \src "ls180.v:301.6-301.32" + wire \main_interface3_ram_bus_we + attribute \src "ls180.v:218.12-218.32" + wire width 6 \main_libresocsim_adr attribute \src "ls180.v:62.6-62.32" wire \main_libresocsim_bus_error attribute \src "ls180.v:63.12-63.39" @@ -231883,217 +248404,125 @@ module \ls180 wire width 32 \main_libresocsim_bus_errors_status attribute \src "ls180.v:60.6-60.36" wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:170.5-170.40" - wire \main_libresocsim_converter0_counter - attribute \src "ls180.v:1777.5-1777.62" - wire \main_libresocsim_converter0_counter_converter0_next_value - attribute \src "ls180.v:1778.5-1778.65" - wire \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:172.12-172.45" - wire width 64 \main_libresocsim_converter0_dat_r - attribute \src "ls180.v:171.6-171.39" - wire \main_libresocsim_converter0_reset - attribute \src "ls180.v:169.5-169.37" - wire \main_libresocsim_converter0_skip - attribute \src "ls180.v:185.5-185.40" - wire \main_libresocsim_converter1_counter - attribute \src "ls180.v:1781.5-1781.62" - wire \main_libresocsim_converter1_counter_converter1_next_value - attribute \src "ls180.v:1782.5-1782.65" - wire \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:187.12-187.45" - wire width 64 \main_libresocsim_converter1_dat_r - attribute \src "ls180.v:186.6-186.39" - wire \main_libresocsim_converter1_reset - attribute \src "ls180.v:184.5-184.37" - wire \main_libresocsim_converter1_skip - attribute \src "ls180.v:200.5-200.40" - wire \main_libresocsim_converter2_counter - attribute \src "ls180.v:1785.5-1785.62" - wire \main_libresocsim_converter2_counter_converter2_next_value - attribute \src "ls180.v:1786.5-1786.65" - wire \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:202.12-202.45" - wire width 64 \main_libresocsim_converter2_dat_r - attribute \src "ls180.v:201.6-201.39" - wire \main_libresocsim_converter2_reset - attribute \src "ls180.v:199.5-199.37" - wire \main_libresocsim_converter2_skip - attribute \src "ls180.v:215.13-215.35" - wire width 32 \main_libresocsim_dat_r - attribute \src "ls180.v:217.13-217.35" - wire width 32 \main_libresocsim_dat_w - attribute \src "ls180.v:223.5-223.27" + attribute \src "ls180.v:219.13-219.35" + wire width 64 \main_libresocsim_dat_r + attribute \src "ls180.v:221.13-221.35" + wire width 64 \main_libresocsim_dat_w + attribute \src "ls180.v:227.5-227.27" wire \main_libresocsim_en_re - attribute \src "ls180.v:222.5-222.32" + attribute \src "ls180.v:226.5-226.32" wire \main_libresocsim_en_storage - attribute \src "ls180.v:239.6-239.45" + attribute \src "ls180.v:243.6-243.45" wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:238.6-238.46" + attribute \src "ls180.v:242.6-242.46" wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:241.6-241.45" + attribute \src "ls180.v:245.6-245.45" wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:240.6-240.46" + attribute \src "ls180.v:244.6-244.46" wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:243.5-243.37" + attribute \src "ls180.v:247.5-247.37" wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:235.6-235.44" + attribute \src "ls180.v:239.6-239.44" wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:234.6-234.45" + attribute \src "ls180.v:238.6-238.45" wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:237.6-237.44" + attribute \src "ls180.v:241.6-241.44" wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:236.6-236.45" + attribute \src "ls180.v:240.6-240.45" wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:242.5-242.42" + attribute \src "ls180.v:246.5-246.42" wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:164.6-164.57" - wire \main_libresocsim_interface0_converted_interface_ack - attribute \src "ls180.v:158.12-158.63" - wire width 30 \main_libresocsim_interface0_converted_interface_adr - attribute \src "ls180.v:167.11-167.62" - wire width 2 \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:166.11-166.62" - wire width 3 \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:162.5-162.56" - wire \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:160.13-160.66" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_r - attribute \src "ls180.v:159.12-159.65" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:168.6-168.57" - wire \main_libresocsim_interface0_converted_interface_err - attribute \src "ls180.v:161.11-161.62" - wire width 4 \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:163.5-163.56" - wire \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:165.5-165.55" - wire \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:179.6-179.57" - wire \main_libresocsim_interface1_converted_interface_ack - attribute \src "ls180.v:173.12-173.63" - wire width 30 \main_libresocsim_interface1_converted_interface_adr - attribute \src "ls180.v:182.11-182.62" - wire width 2 \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:181.11-181.62" - wire width 3 \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:177.5-177.56" - wire \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:175.13-175.66" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_r - attribute \src "ls180.v:174.12-174.65" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:183.6-183.57" - wire \main_libresocsim_interface1_converted_interface_err - attribute \src "ls180.v:176.11-176.62" - wire width 4 \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:178.5-178.56" - wire \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:180.5-180.55" - wire \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:194.6-194.57" - wire \main_libresocsim_interface2_converted_interface_ack - attribute \src "ls180.v:188.12-188.63" - wire width 30 \main_libresocsim_interface2_converted_interface_adr - attribute \src "ls180.v:197.11-197.62" - wire width 2 \main_libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:196.11-196.62" - wire width 3 \main_libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:192.5-192.56" - wire \main_libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:190.13-190.66" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_r - attribute \src "ls180.v:189.12-189.65" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:198.6-198.57" - wire \main_libresocsim_interface2_converted_interface_err - attribute \src "ls180.v:191.11-191.62" - wire width 4 \main_libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:193.5-193.56" - wire \main_libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:195.5-195.55" - wire \main_libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:228.6-228.26" + attribute \src "ls180.v:232.6-232.26" wire \main_libresocsim_irq - attribute \src "ls180.v:119.6-119.32" + attribute \src "ls180.v:165.6-165.32" wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:120.6-120.32" + attribute \src "ls180.v:166.6-166.32" wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:121.13-121.39" + attribute \src "ls180.v:167.13-167.39" wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:123.12-123.45" + attribute \src "ls180.v:169.12-169.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:146.13-146.67" + attribute \src "ls180.v:182.12-182.66" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:147.13-147.67" + attribute \src "ls180.v:183.13-183.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:148.13-148.68" + attribute \src "ls180.v:184.13-184.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:149.6-149.61" + attribute \src "ls180.v:178.6-178.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:150.6-150.63" + attribute \src "ls180.v:179.5-179.62" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:151.6-151.63" + attribute \src "ls180.v:180.6-180.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:152.6-152.64" + attribute \src "ls180.v:181.6-181.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:153.6-153.64" + attribute \src "ls180.v:171.6-171.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:154.6-154.66" + attribute \src "ls180.v:172.5-172.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:155.6-155.66" + attribute \src "ls180.v:173.6-173.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:156.6-156.67" + attribute \src "ls180.v:174.6-174.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:125.13-125.68" + attribute \src "ls180.v:175.11-175.72" + wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i + attribute \src "ls180.v:176.12-176.73" + wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o + attribute \src "ls180.v:177.6-177.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + attribute \src "ls180.v:194.13-194.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:134.12-134.68" + attribute \src "ls180.v:203.12-203.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:131.6-131.65" + attribute \src "ls180.v:200.6-200.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:133.6-133.63" + attribute \src "ls180.v:202.6-202.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:132.6-132.64" + attribute \src "ls180.v:201.6-201.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:135.12-135.68" + attribute \src "ls180.v:204.12-204.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:126.13-126.71" + attribute \src "ls180.v:195.12-195.70" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:127.13-127.71" + attribute \src "ls180.v:196.13-196.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:128.6-128.65" + attribute \src "ls180.v:197.6-197.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:130.6-130.65" + attribute \src "ls180.v:199.6-199.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:129.6-129.64" + attribute \src "ls180.v:198.6-198.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:142.6-142.67" + attribute \src "ls180.v:185.6-185.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:144.6-144.68" + attribute \src "ls180.v:187.6-187.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:145.6-145.68" + attribute \src "ls180.v:188.6-188.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:143.6-143.68" + attribute \src "ls180.v:186.6-186.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:138.6-138.67" + attribute \src "ls180.v:189.6-189.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:140.6-140.68" + attribute \src "ls180.v:191.6-191.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:141.6-141.68" + attribute \src "ls180.v:192.6-192.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:139.6-139.68" + attribute \src "ls180.v:190.6-190.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - attribute \src "ls180.v:72.5-72.39" + attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack attribute \src "ls180.v:66.13-66.47" wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:75.11-75.45" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:74.11-74.45" + wire width 3 \main_libresocsim_libresoc_dbus_cti attribute \src "ls180.v:70.6-70.40" wire \main_libresocsim_libresoc_dbus_cyc attribute \src "ls180.v:68.13-68.49" wire width 64 \main_libresocsim_libresoc_dbus_dat_r attribute \src "ls180.v:67.13-67.49" wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:74.5-74.39" + attribute \src "ls180.v:76.6-76.40" wire \main_libresocsim_libresoc_dbus_err attribute \src "ls180.v:69.12-69.46" wire width 8 \main_libresocsim_libresoc_dbus_sel @@ -232101,45 +248530,141 @@ module \ls180 wire \main_libresocsim_libresoc_dbus_stb attribute \src "ls180.v:73.6-73.39" wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:81.5-81.39" + attribute \src "ls180.v:83.6-83.40" wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:75.13-75.47" + attribute \src "ls180.v:77.13-77.47" wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:79.6-79.40" + attribute \src "ls180.v:86.11-86.45" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:85.11-85.45" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:81.6-81.40" wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:77.13-77.49" + attribute \src "ls180.v:79.13-79.49" wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:76.13-76.49" + attribute \src "ls180.v:78.13-78.49" wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:83.5-83.39" + attribute \src "ls180.v:87.6-87.40" wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:78.12-78.46" + attribute \src "ls180.v:80.12-80.46" wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:80.6-80.40" + attribute \src "ls180.v:82.6-82.40" wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:82.6-82.39" + attribute \src "ls180.v:84.6-84.39" wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:123.6-123.46" + wire \main_libresocsim_libresoc_interface0_ack + attribute \src "ls180.v:117.13-117.53" + wire width 29 \main_libresocsim_libresoc_interface0_adr + attribute \src "ls180.v:126.12-126.52" + wire width 2 \main_libresocsim_libresoc_interface0_bte + attribute \src "ls180.v:125.12-125.52" + wire width 3 \main_libresocsim_libresoc_interface0_cti + attribute \src "ls180.v:121.6-121.46" + wire \main_libresocsim_libresoc_interface0_cyc + attribute \src "ls180.v:119.13-119.55" + wire width 64 \main_libresocsim_libresoc_interface0_dat_r + attribute \src "ls180.v:118.13-118.55" + wire width 64 \main_libresocsim_libresoc_interface0_dat_w + attribute \src "ls180.v:127.6-127.46" + wire \main_libresocsim_libresoc_interface0_err + attribute \src "ls180.v:120.12-120.52" + wire width 8 \main_libresocsim_libresoc_interface0_sel + attribute \src "ls180.v:122.6-122.46" + wire \main_libresocsim_libresoc_interface0_stb + attribute \src "ls180.v:124.6-124.45" + wire \main_libresocsim_libresoc_interface0_we + attribute \src "ls180.v:134.6-134.46" + wire \main_libresocsim_libresoc_interface1_ack + attribute \src "ls180.v:128.13-128.53" + wire width 29 \main_libresocsim_libresoc_interface1_adr + attribute \src "ls180.v:137.12-137.52" + wire width 2 \main_libresocsim_libresoc_interface1_bte + attribute \src "ls180.v:136.12-136.52" + wire width 3 \main_libresocsim_libresoc_interface1_cti + attribute \src "ls180.v:132.6-132.46" + wire \main_libresocsim_libresoc_interface1_cyc + attribute \src "ls180.v:130.13-130.55" + wire width 64 \main_libresocsim_libresoc_interface1_dat_r + attribute \src "ls180.v:129.13-129.55" + wire width 64 \main_libresocsim_libresoc_interface1_dat_w + attribute \src "ls180.v:138.6-138.46" + wire \main_libresocsim_libresoc_interface1_err + attribute \src "ls180.v:131.12-131.52" + wire width 8 \main_libresocsim_libresoc_interface1_sel + attribute \src "ls180.v:133.6-133.46" + wire \main_libresocsim_libresoc_interface1_stb + attribute \src "ls180.v:135.6-135.45" + wire \main_libresocsim_libresoc_interface1_we + attribute \src "ls180.v:145.6-145.46" + wire \main_libresocsim_libresoc_interface2_ack + attribute \src "ls180.v:139.13-139.53" + wire width 29 \main_libresocsim_libresoc_interface2_adr + attribute \src "ls180.v:148.12-148.52" + wire width 2 \main_libresocsim_libresoc_interface2_bte + attribute \src "ls180.v:147.12-147.52" + wire width 3 \main_libresocsim_libresoc_interface2_cti + attribute \src "ls180.v:143.6-143.46" + wire \main_libresocsim_libresoc_interface2_cyc + attribute \src "ls180.v:141.13-141.55" + wire width 64 \main_libresocsim_libresoc_interface2_dat_r + attribute \src "ls180.v:140.13-140.55" + wire width 64 \main_libresocsim_libresoc_interface2_dat_w + attribute \src "ls180.v:149.6-149.46" + wire \main_libresocsim_libresoc_interface2_err + attribute \src "ls180.v:142.12-142.52" + wire width 8 \main_libresocsim_libresoc_interface2_sel + attribute \src "ls180.v:144.6-144.46" + wire \main_libresocsim_libresoc_interface2_stb + attribute \src "ls180.v:146.6-146.45" + wire \main_libresocsim_libresoc_interface2_we + attribute \src "ls180.v:156.6-156.46" + wire \main_libresocsim_libresoc_interface3_ack + attribute \src "ls180.v:150.13-150.53" + wire width 29 \main_libresocsim_libresoc_interface3_adr + attribute \src "ls180.v:159.12-159.52" + wire width 2 \main_libresocsim_libresoc_interface3_bte + attribute \src "ls180.v:158.12-158.52" + wire width 3 \main_libresocsim_libresoc_interface3_cti + attribute \src "ls180.v:154.6-154.46" + wire \main_libresocsim_libresoc_interface3_cyc + attribute \src "ls180.v:152.13-152.55" + wire width 64 \main_libresocsim_libresoc_interface3_dat_r + attribute \src "ls180.v:151.13-151.55" + wire width 64 \main_libresocsim_libresoc_interface3_dat_w + attribute \src "ls180.v:160.6-160.46" + wire \main_libresocsim_libresoc_interface3_err + attribute \src "ls180.v:153.12-153.52" + wire width 8 \main_libresocsim_libresoc_interface3_sel + attribute \src "ls180.v:155.6-155.46" + wire \main_libresocsim_libresoc_interface3_stb + attribute \src "ls180.v:157.6-157.45" + wire \main_libresocsim_libresoc_interface3_we attribute \src "ls180.v:65.12-65.47" wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:115.6-115.40" + attribute \src "ls180.v:161.6-161.40" wire \main_libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:117.6-117.40" + attribute \src "ls180.v:163.6-163.40" wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:118.6-118.40" + attribute \src "ls180.v:164.6-164.40" wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:116.6-116.40" + attribute \src "ls180.v:162.6-162.40" wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:112.5-112.42" + attribute \src "ls180.v:112.6-112.43" wire \main_libresocsim_libresoc_jtag_wb_ack attribute \src "ls180.v:106.13-106.50" wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:115.11-115.48" + wire width 2 \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:114.11-114.48" + wire width 3 \main_libresocsim_libresoc_jtag_wb_cti attribute \src "ls180.v:110.6-110.43" wire \main_libresocsim_libresoc_jtag_wb_cyc attribute \src "ls180.v:108.13-108.52" wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r attribute \src "ls180.v:107.13-107.52" wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:114.5-114.42" + attribute \src "ls180.v:116.6-116.43" wire \main_libresocsim_libresoc_jtag_wb_err attribute \src "ls180.v:109.12-109.49" wire width 8 \main_libresocsim_libresoc_jtag_wb_sel @@ -232147,85 +248672,77 @@ module \ls180 wire \main_libresocsim_libresoc_jtag_wb_stb attribute \src "ls180.v:113.6-113.42" wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:122.6-122.40" + attribute \src "ls180.v:168.6-168.40" wire \main_libresocsim_libresoc_pll_18_o - attribute \src "ls180.v:124.6-124.41" + attribute \src "ls180.v:170.6-170.41" wire \main_libresocsim_libresoc_pll_lck_o attribute \src "ls180.v:64.6-64.37" wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:90.6-90.44" + attribute \src "ls180.v:94.6-94.44" wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:84.13-84.51" + attribute \src "ls180.v:88.12-88.50" wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:93.12-93.50" - wire width 2 \main_libresocsim_libresoc_xics_icp_bte - attribute \src "ls180.v:92.12-92.50" - wire width 3 \main_libresocsim_libresoc_xics_icp_cti - attribute \src "ls180.v:88.6-88.44" + attribute \src "ls180.v:92.5-92.43" wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:86.13-86.53" + attribute \src "ls180.v:90.13-90.53" wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:85.13-85.53" + attribute \src "ls180.v:89.12-89.52" wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:94.6-94.44" + attribute \src "ls180.v:96.6-96.44" wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:87.12-87.50" + attribute \src "ls180.v:91.11-91.49" wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:89.6-89.44" + attribute \src "ls180.v:93.5-93.43" wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:91.6-91.43" + attribute \src "ls180.v:95.5-95.42" wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:101.6-101.44" + attribute \src "ls180.v:103.6-103.44" wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:95.13-95.51" + attribute \src "ls180.v:97.12-97.50" wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:104.12-104.50" - wire width 2 \main_libresocsim_libresoc_xics_ics_bte - attribute \src "ls180.v:103.12-103.50" - wire width 3 \main_libresocsim_libresoc_xics_ics_cti - attribute \src "ls180.v:99.6-99.44" + attribute \src "ls180.v:101.5-101.43" wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:97.13-97.53" + attribute \src "ls180.v:99.13-99.53" wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:96.13-96.53" + attribute \src "ls180.v:98.12-98.52" wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w attribute \src "ls180.v:105.6-105.44" wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:98.12-98.50" + attribute \src "ls180.v:100.11-100.49" wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:100.6-100.44" + attribute \src "ls180.v:102.5-102.43" wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:102.6-102.43" + attribute \src "ls180.v:104.5-104.42" wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:219.5-219.29" + attribute \src "ls180.v:223.5-223.29" wire \main_libresocsim_load_re - attribute \src "ls180.v:218.12-218.41" + attribute \src "ls180.v:222.12-222.41" wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:209.5-209.33" + attribute \src "ls180.v:213.5-213.33" wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:203.13-203.41" + attribute \src "ls180.v:207.13-207.41" wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:212.12-212.40" + attribute \src "ls180.v:216.12-216.40" wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:211.12-211.40" + attribute \src "ls180.v:215.12-215.40" wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:207.6-207.34" + attribute \src "ls180.v:211.6-211.34" wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:205.13-205.43" - wire width 32 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:204.13-204.43" - wire width 32 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:213.5-213.33" + attribute \src "ls180.v:209.13-209.43" + wire width 64 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:208.13-208.43" + wire width 64 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:217.5-217.33" wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:206.12-206.40" - wire width 4 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:208.6-208.34" + attribute \src "ls180.v:210.12-210.40" + wire width 8 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:212.6-212.34" wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:210.6-210.33" + attribute \src "ls180.v:214.6-214.33" wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:221.5-221.31" + attribute \src "ls180.v:225.5-225.31" wire \main_libresocsim_reload_re - attribute \src "ls180.v:220.12-220.43" + attribute \src "ls180.v:224.12-224.43" wire width 32 \main_libresocsim_reload_storage attribute \src "ls180.v:61.6-61.28" wire \main_libresocsim_reset @@ -232237,3251 +248754,3289 @@ module \ls180 wire \main_libresocsim_scratch_re attribute \src "ls180.v:57.12-57.44" wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:225.5-225.37" + attribute \src "ls180.v:229.5-229.37" wire \main_libresocsim_update_value_re - attribute \src "ls180.v:224.5-224.42" + attribute \src "ls180.v:228.5-228.42" wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:244.12-244.34" + attribute \src "ls180.v:248.12-248.34" wire width 32 \main_libresocsim_value - attribute \src "ls180.v:226.12-226.41" + attribute \src "ls180.v:230.12-230.41" wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:227.6-227.31" + attribute \src "ls180.v:231.6-231.31" wire \main_libresocsim_value_we - attribute \src "ls180.v:216.11-216.30" - wire width 4 \main_libresocsim_we - attribute \src "ls180.v:232.5-232.32" + attribute \src "ls180.v:220.11-220.30" + wire width 8 \main_libresocsim_we + attribute \src "ls180.v:236.5-236.32" wire \main_libresocsim_zero_clear - attribute \src "ls180.v:233.5-233.38" + attribute \src "ls180.v:237.5-237.38" wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:230.5-230.34" + attribute \src "ls180.v:234.5-234.34" wire \main_libresocsim_zero_pending - attribute \src "ls180.v:229.6-229.34" + attribute \src "ls180.v:233.6-233.34" wire \main_libresocsim_zero_status - attribute \src "ls180.v:231.6-231.35" + attribute \src "ls180.v:235.6-235.35" wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:871.6-871.26" + attribute \src "ls180.v:932.6-932.26" wire \main_litedram_wb_ack - attribute \src "ls180.v:865.12-865.32" + attribute \src "ls180.v:926.12-926.32" wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:869.5-869.25" + attribute \src "ls180.v:930.5-930.25" wire \main_litedram_wb_cyc - attribute \src "ls180.v:867.13-867.35" + attribute \src "ls180.v:928.13-928.35" wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:866.12-866.34" + attribute \src "ls180.v:927.12-927.34" wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:868.11-868.31" + attribute \src "ls180.v:929.11-929.31" wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:870.5-870.25" + attribute \src "ls180.v:931.5-931.25" wire \main_litedram_wb_stb - attribute \src "ls180.v:872.5-872.24" + attribute \src "ls180.v:933.5-933.24" wire \main_litedram_wb_we - attribute \src "ls180.v:1107.13-1107.20" + attribute \src "ls180.v:1174.13-1174.20" wire width 24 \main_nc - attribute \src "ls180.v:844.6-844.24" + attribute \src "ls180.v:893.6-893.24" wire \main_port_cmd_last - attribute \src "ls180.v:846.13-846.39" + attribute \src "ls180.v:895.13-895.39" wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:845.6-845.30" + attribute \src "ls180.v:894.6-894.30" wire \main_port_cmd_payload_we - attribute \src "ls180.v:843.6-843.25" + attribute \src "ls180.v:892.6-892.25" wire \main_port_cmd_ready - attribute \src "ls180.v:842.6-842.25" + attribute \src "ls180.v:891.6-891.25" wire \main_port_cmd_valid - attribute \src "ls180.v:841.6-841.21" + attribute \src "ls180.v:890.6-890.21" wire \main_port_flush - attribute \src "ls180.v:853.13-853.41" + attribute \src "ls180.v:902.13-902.41" wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:852.6-852.27" + attribute \src "ls180.v:901.6-901.27" wire \main_port_rdata_ready - attribute \src "ls180.v:851.6-851.27" + attribute \src "ls180.v:900.6-900.27" wire \main_port_rdata_valid - attribute \src "ls180.v:849.13-849.41" + attribute \src "ls180.v:898.13-898.41" wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:850.12-850.38" + attribute \src "ls180.v:899.12-899.38" wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:848.6-848.27" + attribute \src "ls180.v:897.6-897.27" wire \main_port_wdata_ready - attribute \src "ls180.v:847.6-847.27" + attribute \src "ls180.v:896.6-896.27" wire \main_port_wdata_valid - attribute \src "ls180.v:1112.12-1112.29" + attribute \src "ls180.v:1179.12-1179.29" wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1109.6-1109.22" + attribute \src "ls180.v:1176.6-1176.22" wire \main_pwm0_enable - attribute \src "ls180.v:1114.5-1114.24" + attribute \src "ls180.v:1181.5-1181.24" wire \main_pwm0_enable_re - attribute \src "ls180.v:1113.5-1113.29" + attribute \src "ls180.v:1180.5-1180.29" wire \main_pwm0_enable_storage - attribute \src "ls180.v:1111.13-1111.29" + attribute \src "ls180.v:1178.13-1178.29" wire width 32 \main_pwm0_period - attribute \src "ls180.v:1118.5-1118.24" + attribute \src "ls180.v:1185.5-1185.24" wire \main_pwm0_period_re - attribute \src "ls180.v:1117.12-1117.36" + attribute \src "ls180.v:1184.12-1184.36" wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1110.13-1110.28" + attribute \src "ls180.v:1177.13-1177.28" wire width 32 \main_pwm0_width - attribute \src "ls180.v:1116.5-1116.23" + attribute \src "ls180.v:1183.5-1183.23" wire \main_pwm0_width_re - attribute \src "ls180.v:1115.12-1115.35" + attribute \src "ls180.v:1182.12-1182.35" wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1122.12-1122.29" + attribute \src "ls180.v:1189.12-1189.29" wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1119.6-1119.22" + attribute \src "ls180.v:1186.6-1186.22" wire \main_pwm1_enable - attribute \src "ls180.v:1124.5-1124.24" + attribute \src "ls180.v:1191.5-1191.24" wire \main_pwm1_enable_re - attribute \src "ls180.v:1123.5-1123.29" + attribute \src "ls180.v:1190.5-1190.29" wire \main_pwm1_enable_storage - attribute \src "ls180.v:1121.13-1121.29" + attribute \src "ls180.v:1188.13-1188.29" wire width 32 \main_pwm1_period - attribute \src "ls180.v:1128.5-1128.24" + attribute \src "ls180.v:1195.5-1195.24" wire \main_pwm1_period_re - attribute \src "ls180.v:1127.12-1127.36" + attribute \src "ls180.v:1194.12-1194.36" wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1120.13-1120.28" + attribute \src "ls180.v:1187.13-1187.28" wire width 32 \main_pwm1_width - attribute \src "ls180.v:1126.5-1126.23" + attribute \src "ls180.v:1193.5-1193.23" wire \main_pwm1_width_re - attribute \src "ls180.v:1125.12-1125.35" + attribute \src "ls180.v:1192.12-1192.35" wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:310.11-310.25" + attribute \src "ls180.v:359.11-359.25" wire width 3 \main_rddata_en - attribute \src "ls180.v:1650.11-1650.43" - wire width 2 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1651.6-1651.42" + attribute \src "ls180.v:1717.11-1717.43" + wire width 3 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1718.6-1718.42" wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1641.6-1641.43" + attribute \src "ls180.v:1708.6-1708.43" wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1642.6-1642.42" + attribute \src "ls180.v:1709.6-1709.42" wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1643.12-1643.56" + attribute \src "ls180.v:1710.12-1710.56" wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1640.6-1640.43" + attribute \src "ls180.v:1707.6-1707.43" wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1639.6-1639.43" + attribute \src "ls180.v:1706.6-1706.43" wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1646.5-1646.44" + attribute \src "ls180.v:1713.5-1713.44" wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1647.5-1647.43" + attribute \src "ls180.v:1714.5-1714.43" wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1648.12-1648.58" - wire width 32 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1649.11-1649.70" - wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1645.6-1645.45" + attribute \src "ls180.v:1715.12-1715.58" + wire width 64 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1716.11-1716.70" + wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1712.6-1712.45" wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1644.6-1644.45" + attribute \src "ls180.v:1711.6-1711.45" wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1652.5-1652.42" + attribute \src "ls180.v:1719.5-1719.42" wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1625.11-1625.40" + attribute \src "ls180.v:1692.11-1692.40" wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1630.6-1630.35" + attribute \src "ls180.v:1697.6-1697.35" wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1634.6-1634.41" + attribute \src "ls180.v:1701.6-1701.41" wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1635.6-1635.40" + attribute \src "ls180.v:1702.6-1702.40" wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1633.12-1633.54" + attribute \src "ls180.v:1700.12-1700.54" wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1637.6-1637.42" + attribute \src "ls180.v:1704.6-1704.42" wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1638.6-1638.41" + attribute \src "ls180.v:1705.6-1705.41" wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1636.12-1636.55" + attribute \src "ls180.v:1703.12-1703.55" wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1622.11-1622.38" + attribute \src "ls180.v:1689.11-1689.38" wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1624.11-1624.40" + attribute \src "ls180.v:1691.11-1691.40" wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1631.12-1631.44" + attribute \src "ls180.v:1698.12-1698.44" wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1632.12-1632.46" + attribute \src "ls180.v:1699.12-1699.46" wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1623.5-1623.34" + attribute \src "ls180.v:1690.5-1690.34" wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1608.6-1608.38" + attribute \src "ls180.v:1675.6-1675.38" wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1609.6-1609.37" + attribute \src "ls180.v:1676.6-1676.37" wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1610.12-1610.51" + attribute \src "ls180.v:1677.12-1677.51" wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1607.6-1607.38" + attribute \src "ls180.v:1674.6-1674.38" wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1606.6-1606.38" + attribute \src "ls180.v:1673.6-1673.38" wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1613.6-1613.40" + attribute \src "ls180.v:1680.6-1680.40" wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1614.6-1614.39" + attribute \src "ls180.v:1681.6-1681.39" wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1615.12-1615.53" + attribute \src "ls180.v:1682.12-1682.53" wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1612.6-1612.40" + attribute \src "ls180.v:1679.6-1679.40" wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1611.6-1611.40" + attribute \src "ls180.v:1678.6-1678.40" wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1620.12-1620.46" + attribute \src "ls180.v:1687.12-1687.46" wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1621.12-1621.47" + attribute \src "ls180.v:1688.12-1688.47" wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1618.6-1618.39" + attribute \src "ls180.v:1685.6-1685.39" wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1619.6-1619.45" + attribute \src "ls180.v:1686.6-1686.45" wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1616.6-1616.39" + attribute \src "ls180.v:1683.6-1683.39" wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1617.6-1617.45" + attribute \src "ls180.v:1684.6-1684.45" wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1626.11-1626.43" + attribute \src "ls180.v:1693.11-1693.43" wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1627.12-1627.46" + attribute \src "ls180.v:1694.12-1694.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1629.12-1629.46" + attribute \src "ls180.v:1696.12-1696.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1628.6-1628.37" + attribute \src "ls180.v:1695.6-1695.37" wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1603.6-1603.38" + attribute \src "ls180.v:1670.6-1670.38" wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1604.6-1604.37" + attribute \src "ls180.v:1671.6-1671.37" wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1660.12-1660.54" + attribute \src "ls180.v:1727.12-1727.54" wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1605.12-1605.52" + attribute \src "ls180.v:1672.12-1672.52" wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1661.12-1661.52" - wire width 32 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1602.6-1602.39" + attribute \src "ls180.v:1728.12-1728.52" + wire width 64 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1669.6-1669.39" wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1659.6-1659.39" + attribute \src "ls180.v:1726.6-1726.39" wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1601.6-1601.39" + attribute \src "ls180.v:1668.6-1668.39" wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1658.5-1658.38" + attribute \src "ls180.v:1725.5-1725.38" wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1655.6-1655.42" + attribute \src "ls180.v:1722.6-1722.42" wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1656.6-1656.41" + attribute \src "ls180.v:1723.6-1723.41" wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1657.13-1657.56" - wire width 32 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1654.6-1654.42" + attribute \src "ls180.v:1724.13-1724.56" + wire width 64 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1721.6-1721.42" wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1653.6-1653.42" + attribute \src "ls180.v:1720.6-1720.42" wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1677.13-1677.52" + attribute \src "ls180.v:1744.13-1744.52" wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1668.5-1668.47" + attribute \src "ls180.v:1735.5-1735.47" wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1667.12-1667.59" + attribute \src "ls180.v:1734.12-1734.59" wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1672.5-1672.49" + attribute \src "ls180.v:1739.5-1739.49" wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1671.5-1671.54" + attribute \src "ls180.v:1738.5-1738.54" wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1679.13-1679.54" + attribute \src "ls180.v:1746.13-1746.54" wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1670.5-1670.49" + attribute \src "ls180.v:1737.5-1737.49" wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1669.12-1669.61" + attribute \src "ls180.v:1736.12-1736.61" wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1676.5-1676.47" + attribute \src "ls180.v:1743.5-1743.47" wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1675.5-1675.52" + attribute \src "ls180.v:1742.5-1742.52" wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1678.12-1678.53" + attribute \src "ls180.v:1745.12-1745.53" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1898.12-1898.79" + attribute \src "ls180.v:1965.12-1965.79" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1899.5-1899.75" + attribute \src "ls180.v:1966.5-1966.75" wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1680.6-1680.46" + attribute \src "ls180.v:1747.6-1747.46" wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1664.6-1664.51" + attribute \src "ls180.v:1731.6-1731.51" wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1665.6-1665.50" + attribute \src "ls180.v:1732.6-1732.50" wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1666.13-1666.65" - wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1663.5-1663.50" + attribute \src "ls180.v:1733.13-1733.65" + wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1730.5-1730.50" wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1662.6-1662.51" + attribute \src "ls180.v:1729.6-1729.51" wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1673.5-1673.46" + attribute \src "ls180.v:1740.5-1740.46" wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1674.6-1674.43" + attribute \src "ls180.v:1741.6-1741.43" wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1442.5-1442.31" + attribute \src "ls180.v:1509.5-1509.31" wire \main_sdcore_block_count_re - attribute \src "ls180.v:1441.12-1441.43" + attribute \src "ls180.v:1508.12-1508.43" wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1440.5-1440.32" + attribute \src "ls180.v:1507.5-1507.32" wire \main_sdcore_block_length_re - attribute \src "ls180.v:1439.11-1439.43" + attribute \src "ls180.v:1506.11-1506.43" wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1426.5-1426.32" + attribute \src "ls180.v:1493.5-1493.32" wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1425.12-1425.44" + attribute \src "ls180.v:1492.12-1492.44" wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1428.5-1428.31" + attribute \src "ls180.v:1495.5-1495.31" wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1427.12-1427.43" + attribute \src "ls180.v:1494.12-1494.43" wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1581.11-1581.32" + attribute \src "ls180.v:1648.11-1648.32" wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1882.11-1882.55" + attribute \src "ls180.v:1949.11-1949.55" wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1883.5-1883.52" + attribute \src "ls180.v:1950.5-1950.52" wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1582.5-1582.25" + attribute \src "ls180.v:1649.5-1649.25" wire \main_sdcore_cmd_done - attribute \src "ls180.v:1878.5-1878.48" + attribute \src "ls180.v:1945.5-1945.48" wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1879.5-1879.51" + attribute \src "ls180.v:1946.5-1946.51" wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1583.5-1583.26" + attribute \src "ls180.v:1650.5-1650.26" wire \main_sdcore_cmd_error - attribute \src "ls180.v:1886.5-1886.49" + attribute \src "ls180.v:1953.5-1953.49" wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1887.5-1887.52" + attribute \src "ls180.v:1954.5-1954.52" wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1435.12-1435.40" + attribute \src "ls180.v:1502.12-1502.40" wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1436.6-1436.30" + attribute \src "ls180.v:1503.6-1503.30" wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1433.13-1433.44" + attribute \src "ls180.v:1500.13-1500.44" wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1894.13-1894.67" + attribute \src "ls180.v:1961.13-1961.67" wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1895.5-1895.62" + attribute \src "ls180.v:1962.5-1962.62" wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1434.6-1434.33" + attribute \src "ls180.v:1501.6-1501.33" wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1430.6-1430.28" + attribute \src "ls180.v:1497.6-1497.28" wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1429.6-1429.29" + attribute \src "ls180.v:1496.6-1496.29" wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1432.5-1432.27" + attribute \src "ls180.v:1499.5-1499.27" wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1431.6-1431.29" + attribute \src "ls180.v:1498.6-1498.29" wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1584.5-1584.28" + attribute \src "ls180.v:1651.5-1651.28" wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1888.5-1888.51" + attribute \src "ls180.v:1955.5-1955.51" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1889.5-1889.54" + attribute \src "ls180.v:1956.5-1956.54" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1580.12-1580.32" + attribute \src "ls180.v:1647.12-1647.32" wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1542.11-1542.40" + attribute \src "ls180.v:1609.11-1609.40" wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1548.5-1548.39" + attribute \src "ls180.v:1615.5-1615.39" wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1547.12-1547.46" + attribute \src "ls180.v:1614.12-1614.46" wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1543.12-1543.50" + attribute \src "ls180.v:1610.12-1610.50" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1544.13-1544.51" + attribute \src "ls180.v:1611.13-1611.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1545.13-1545.51" + attribute \src "ls180.v:1612.13-1612.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1549.6-1549.43" + attribute \src "ls180.v:1616.6-1616.43" wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1546.12-1546.46" + attribute \src "ls180.v:1613.12-1613.46" wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1555.5-1555.39" + attribute \src "ls180.v:1622.5-1622.39" wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1554.12-1554.46" + attribute \src "ls180.v:1621.12-1621.46" wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1550.12-1550.50" + attribute \src "ls180.v:1617.12-1617.50" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1551.13-1551.51" + attribute \src "ls180.v:1618.13-1618.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1552.13-1552.51" + attribute \src "ls180.v:1619.13-1619.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1556.6-1556.43" + attribute \src "ls180.v:1623.6-1623.43" wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1553.12-1553.46" + attribute \src "ls180.v:1620.12-1620.46" wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1562.5-1562.39" + attribute \src "ls180.v:1629.5-1629.39" wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1561.12-1561.46" + attribute \src "ls180.v:1628.12-1628.46" wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1557.12-1557.50" + attribute \src "ls180.v:1624.12-1624.50" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1558.13-1558.51" + attribute \src "ls180.v:1625.13-1625.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1559.13-1559.51" + attribute \src "ls180.v:1626.13-1626.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1563.6-1563.43" + attribute \src "ls180.v:1630.6-1630.43" wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1560.12-1560.46" + attribute \src "ls180.v:1627.12-1627.46" wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1569.5-1569.39" + attribute \src "ls180.v:1636.5-1636.39" wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1568.12-1568.46" + attribute \src "ls180.v:1635.12-1635.46" wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1564.12-1564.50" + attribute \src "ls180.v:1631.12-1631.50" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1565.13-1565.51" + attribute \src "ls180.v:1632.13-1632.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1566.13-1566.51" + attribute \src "ls180.v:1633.13-1633.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1570.6-1570.43" + attribute \src "ls180.v:1637.6-1637.43" wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1567.12-1567.46" + attribute \src "ls180.v:1634.12-1634.46" wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1571.12-1571.45" + attribute \src "ls180.v:1638.12-1638.45" wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1572.12-1572.45" + attribute \src "ls180.v:1639.12-1639.45" wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1573.12-1573.45" + attribute \src "ls180.v:1640.12-1640.45" wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1574.12-1574.45" + attribute \src "ls180.v:1641.12-1641.45" wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1576.12-1576.43" + attribute \src "ls180.v:1643.12-1643.43" wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1577.12-1577.43" + attribute \src "ls180.v:1644.12-1644.43" wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1578.12-1578.43" + attribute \src "ls180.v:1645.12-1645.43" wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1579.12-1579.43" + attribute \src "ls180.v:1646.12-1646.43" wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1533.5-1533.41" + attribute \src "ls180.v:1600.5-1600.41" wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1534.5-1534.40" + attribute \src "ls180.v:1601.5-1601.40" wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1535.11-1535.54" + attribute \src "ls180.v:1602.11-1602.54" wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1532.5-1532.41" + attribute \src "ls180.v:1599.5-1599.41" wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1531.5-1531.41" + attribute \src "ls180.v:1598.5-1598.41" wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1538.5-1538.43" + attribute \src "ls180.v:1605.5-1605.43" wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1539.6-1539.43" + attribute \src "ls180.v:1606.6-1606.43" wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1540.12-1540.57" + attribute \src "ls180.v:1607.12-1607.57" wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1537.6-1537.44" + attribute \src "ls180.v:1604.6-1604.44" wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1536.5-1536.43" + attribute \src "ls180.v:1603.5-1603.43" wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1541.11-1541.40" + attribute \src "ls180.v:1608.11-1608.40" wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1575.5-1575.36" + attribute \src "ls180.v:1642.5-1642.36" wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1498.11-1498.41" + attribute \src "ls180.v:1565.11-1565.41" wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1874.11-1874.80" + attribute \src "ls180.v:1941.11-1941.80" wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1875.5-1875.77" + attribute \src "ls180.v:1942.5-1942.77" wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1504.6-1504.41" + attribute \src "ls180.v:1571.6-1571.41" wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1503.12-1503.47" + attribute \src "ls180.v:1570.12-1570.47" wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1499.12-1499.51" + attribute \src "ls180.v:1566.12-1566.51" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1500.13-1500.52" + attribute \src "ls180.v:1567.13-1567.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1501.13-1501.52" + attribute \src "ls180.v:1568.13-1568.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1505.6-1505.44" + attribute \src "ls180.v:1572.6-1572.44" wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1502.12-1502.47" + attribute \src "ls180.v:1569.12-1569.47" wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1511.6-1511.41" + attribute \src "ls180.v:1578.6-1578.41" wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1510.12-1510.47" + attribute \src "ls180.v:1577.12-1577.47" wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1506.12-1506.51" + attribute \src "ls180.v:1573.12-1573.51" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1507.13-1507.52" + attribute \src "ls180.v:1574.13-1574.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1508.13-1508.52" + attribute \src "ls180.v:1575.13-1575.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1512.6-1512.44" + attribute \src "ls180.v:1579.6-1579.44" wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1509.12-1509.47" + attribute \src "ls180.v:1576.12-1576.47" wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1518.6-1518.41" + attribute \src "ls180.v:1585.6-1585.41" wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1517.12-1517.47" + attribute \src "ls180.v:1584.12-1584.47" wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1513.12-1513.51" + attribute \src "ls180.v:1580.12-1580.51" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1514.13-1514.52" + attribute \src "ls180.v:1581.13-1581.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1515.13-1515.52" + attribute \src "ls180.v:1582.13-1582.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1519.6-1519.44" + attribute \src "ls180.v:1586.6-1586.44" wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1516.12-1516.47" + attribute \src "ls180.v:1583.12-1583.47" wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1525.6-1525.41" + attribute \src "ls180.v:1592.6-1592.41" wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1524.12-1524.47" + attribute \src "ls180.v:1591.12-1591.47" wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1520.12-1520.51" + attribute \src "ls180.v:1587.12-1587.51" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1521.13-1521.52" + attribute \src "ls180.v:1588.13-1588.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1522.13-1522.52" + attribute \src "ls180.v:1589.13-1589.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1526.6-1526.44" + attribute \src "ls180.v:1593.6-1593.44" wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1523.12-1523.47" + attribute \src "ls180.v:1590.12-1590.47" wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1527.12-1527.46" + attribute \src "ls180.v:1594.12-1594.46" wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1866.12-1866.85" + attribute \src "ls180.v:1933.12-1933.85" wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1867.5-1867.81" + attribute \src "ls180.v:1934.5-1934.81" wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1528.12-1528.46" + attribute \src "ls180.v:1595.12-1595.46" wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1868.12-1868.85" + attribute \src "ls180.v:1935.12-1935.85" wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1869.5-1869.81" + attribute \src "ls180.v:1936.5-1936.81" wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1529.12-1529.46" + attribute \src "ls180.v:1596.12-1596.46" wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1870.12-1870.85" + attribute \src "ls180.v:1937.12-1937.85" wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1871.5-1871.81" + attribute \src "ls180.v:1938.5-1938.81" wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1530.12-1530.46" + attribute \src "ls180.v:1597.12-1597.46" wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1872.12-1872.85" + attribute \src "ls180.v:1939.12-1939.85" wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1873.5-1873.81" + attribute \src "ls180.v:1940.5-1940.81" wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1490.6-1490.43" + attribute \src "ls180.v:1557.6-1557.43" wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1491.6-1491.42" + attribute \src "ls180.v:1558.6-1558.42" wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1492.12-1492.56" + attribute \src "ls180.v:1559.12-1559.56" wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1489.5-1489.42" + attribute \src "ls180.v:1556.5-1556.42" wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1488.6-1488.43" + attribute \src "ls180.v:1555.6-1555.43" wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1495.5-1495.44" + attribute \src "ls180.v:1562.5-1562.44" wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1496.5-1496.43" + attribute \src "ls180.v:1563.5-1563.43" wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1497.11-1497.57" + attribute \src "ls180.v:1564.11-1564.57" wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1494.5-1494.44" + attribute \src "ls180.v:1561.5-1561.44" wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1493.5-1493.44" + attribute \src "ls180.v:1560.5-1560.44" wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1486.6-1486.35" + attribute \src "ls180.v:1553.6-1553.35" wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1485.11-1485.40" + attribute \src "ls180.v:1552.11-1552.40" wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1443.11-1443.44" + attribute \src "ls180.v:1510.11-1510.44" wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1444.12-1444.45" + attribute \src "ls180.v:1511.12-1511.45" wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1453.12-1453.46" + attribute \src "ls180.v:1520.12-1520.46" wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1454.12-1454.46" + attribute \src "ls180.v:1521.12-1521.46" wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1455.12-1455.46" + attribute \src "ls180.v:1522.12-1522.46" wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1456.12-1456.46" + attribute \src "ls180.v:1523.12-1523.46" wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1457.12-1457.46" + attribute \src "ls180.v:1524.12-1524.46" wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1458.12-1458.46" + attribute \src "ls180.v:1525.12-1525.46" wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1459.12-1459.46" + attribute \src "ls180.v:1526.12-1526.46" wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1460.12-1460.46" + attribute \src "ls180.v:1527.12-1527.46" wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1461.12-1461.46" + attribute \src "ls180.v:1528.12-1528.46" wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1462.12-1462.46" + attribute \src "ls180.v:1529.12-1529.46" wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1445.12-1445.45" + attribute \src "ls180.v:1512.12-1512.45" wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1463.12-1463.46" + attribute \src "ls180.v:1530.12-1530.46" wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1464.12-1464.46" + attribute \src "ls180.v:1531.12-1531.46" wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1465.12-1465.46" + attribute \src "ls180.v:1532.12-1532.46" wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1466.12-1466.46" + attribute \src "ls180.v:1533.12-1533.46" wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1467.12-1467.46" + attribute \src "ls180.v:1534.12-1534.46" wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1468.12-1468.46" + attribute \src "ls180.v:1535.12-1535.46" wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1469.12-1469.46" + attribute \src "ls180.v:1536.12-1536.46" wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1470.12-1470.46" + attribute \src "ls180.v:1537.12-1537.46" wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1471.12-1471.46" + attribute \src "ls180.v:1538.12-1538.46" wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1472.12-1472.46" + attribute \src "ls180.v:1539.12-1539.46" wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1446.12-1446.45" + attribute \src "ls180.v:1513.12-1513.45" wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1473.12-1473.46" + attribute \src "ls180.v:1540.12-1540.46" wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1474.12-1474.46" + attribute \src "ls180.v:1541.12-1541.46" wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1475.12-1475.46" + attribute \src "ls180.v:1542.12-1542.46" wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1476.12-1476.46" + attribute \src "ls180.v:1543.12-1543.46" wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1477.12-1477.46" + attribute \src "ls180.v:1544.12-1544.46" wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1478.12-1478.46" + attribute \src "ls180.v:1545.12-1545.46" wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1479.12-1479.46" + attribute \src "ls180.v:1546.12-1546.46" wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1480.12-1480.46" + attribute \src "ls180.v:1547.12-1547.46" wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1481.12-1481.46" + attribute \src "ls180.v:1548.12-1548.46" wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1482.12-1482.46" + attribute \src "ls180.v:1549.12-1549.46" wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1447.12-1447.45" + attribute \src "ls180.v:1514.12-1514.45" wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1483.12-1483.46" + attribute \src "ls180.v:1550.12-1550.46" wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1448.12-1448.45" + attribute \src "ls180.v:1515.12-1515.45" wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1449.12-1449.45" + attribute \src "ls180.v:1516.12-1516.45" wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1450.12-1450.45" + attribute \src "ls180.v:1517.12-1517.45" wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1451.12-1451.45" + attribute \src "ls180.v:1518.12-1518.45" wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1452.12-1452.45" + attribute \src "ls180.v:1519.12-1519.45" wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1487.6-1487.38" + attribute \src "ls180.v:1554.6-1554.38" wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1484.13-1484.42" + attribute \src "ls180.v:1551.13-1551.42" wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1586.12-1586.34" + attribute \src "ls180.v:1653.12-1653.34" wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1884.12-1884.57" + attribute \src "ls180.v:1951.12-1951.57" wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1885.5-1885.53" + attribute \src "ls180.v:1952.5-1952.53" wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1587.5-1587.26" + attribute \src "ls180.v:1654.5-1654.26" wire \main_sdcore_data_done - attribute \src "ls180.v:1880.5-1880.49" + attribute \src "ls180.v:1947.5-1947.49" wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1881.5-1881.52" + attribute \src "ls180.v:1948.5-1948.52" wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1588.5-1588.27" + attribute \src "ls180.v:1655.5-1655.27" wire \main_sdcore_data_error - attribute \src "ls180.v:1890.5-1890.50" + attribute \src "ls180.v:1957.5-1957.50" wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1891.5-1891.53" + attribute \src "ls180.v:1958.5-1958.53" wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1437.12-1437.41" + attribute \src "ls180.v:1504.12-1504.41" wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1438.6-1438.31" + attribute \src "ls180.v:1505.6-1505.31" wire \main_sdcore_data_event_we - attribute \src "ls180.v:1589.5-1589.29" + attribute \src "ls180.v:1656.5-1656.29" wire \main_sdcore_data_timeout - attribute \src "ls180.v:1892.5-1892.52" + attribute \src "ls180.v:1959.5-1959.52" wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1893.5-1893.55" + attribute \src "ls180.v:1960.5-1960.55" wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1585.12-1585.33" + attribute \src "ls180.v:1652.12-1652.33" wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1417.6-1417.33" + attribute \src "ls180.v:1484.6-1484.33" wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1418.6-1418.32" + attribute \src "ls180.v:1485.6-1485.32" wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1419.12-1419.46" + attribute \src "ls180.v:1486.12-1486.46" wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1416.6-1416.33" + attribute \src "ls180.v:1483.6-1483.33" wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1415.6-1415.33" + attribute \src "ls180.v:1482.6-1482.33" wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1422.6-1422.37" + attribute \src "ls180.v:1489.6-1489.37" wire \main_sdcore_source_source_first - attribute \src "ls180.v:1423.6-1423.36" + attribute \src "ls180.v:1490.6-1490.36" wire \main_sdcore_source_source_last - attribute \src "ls180.v:1424.12-1424.50" + attribute \src "ls180.v:1491.12-1491.50" wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1421.6-1421.37" + attribute \src "ls180.v:1488.6-1488.37" wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1420.6-1420.37" + attribute \src "ls180.v:1487.6-1487.37" wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1735.6-1735.38" + attribute \src "ls180.v:1802.6-1802.38" wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1736.6-1736.37" + attribute \src "ls180.v:1803.6-1803.37" wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1734.11-1734.41" - wire width 2 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1725.6-1725.43" + attribute \src "ls180.v:1801.11-1801.41" + wire width 3 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1792.6-1792.43" wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1726.6-1726.42" + attribute \src "ls180.v:1793.6-1793.42" wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1727.13-1727.57" - wire width 32 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1724.6-1724.43" + attribute \src "ls180.v:1794.13-1794.57" + wire width 64 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1791.6-1791.43" wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1723.6-1723.43" + attribute \src "ls180.v:1790.6-1790.43" wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1730.6-1730.45" + attribute \src "ls180.v:1797.6-1797.45" wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1731.6-1731.44" + attribute \src "ls180.v:1798.6-1798.44" wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1732.11-1732.57" + attribute \src "ls180.v:1799.11-1799.57" wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1733.6-1733.65" + attribute \src "ls180.v:1800.6-1800.65" wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1729.6-1729.45" + attribute \src "ls180.v:1796.6-1796.45" wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1728.6-1728.45" + attribute \src "ls180.v:1795.6-1795.45" wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1719.13-1719.38" + attribute \src "ls180.v:1786.13-1786.38" wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1708.5-1708.33" + attribute \src "ls180.v:1775.5-1775.33" wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1707.12-1707.45" + attribute \src "ls180.v:1774.12-1774.45" wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1706.12-1706.37" - wire width 32 \main_sdmem2block_dma_data - attribute \src "ls180.v:1902.12-1902.67" - wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1903.5-1903.63" + attribute \src "ls180.v:1773.12-1773.37" + wire width 64 \main_sdmem2block_dma_data + attribute \src "ls180.v:1969.12-1969.67" + wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1970.5-1970.63" wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1713.5-1713.37" + attribute \src "ls180.v:1780.5-1780.37" wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1714.6-1714.34" + attribute \src "ls180.v:1781.6-1781.34" wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1712.5-1712.35" + attribute \src "ls180.v:1779.5-1779.35" wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1711.5-1711.40" + attribute \src "ls180.v:1778.5-1778.40" wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1721.13-1721.40" + attribute \src "ls180.v:1788.13-1788.40" wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1710.5-1710.35" + attribute \src "ls180.v:1777.5-1777.35" wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1709.12-1709.47" + attribute \src "ls180.v:1776.12-1776.47" wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1716.5-1716.33" + attribute \src "ls180.v:1783.5-1783.33" wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1715.5-1715.38" + attribute \src "ls180.v:1782.5-1782.38" wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1720.12-1720.39" + attribute \src "ls180.v:1787.12-1787.39" wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1906.12-1906.79" + attribute \src "ls180.v:1973.12-1973.79" wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1907.5-1907.75" + attribute \src "ls180.v:1974.5-1974.75" wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1717.13-1717.47" + attribute \src "ls180.v:1784.13-1784.47" wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1718.6-1718.36" + attribute \src "ls180.v:1785.6-1785.36" wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1722.6-1722.32" + attribute \src "ls180.v:1789.6-1789.32" wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1699.5-1699.35" + attribute \src "ls180.v:1766.5-1766.35" wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1700.12-1700.53" + attribute \src "ls180.v:1767.12-1767.53" wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1698.5-1698.36" + attribute \src "ls180.v:1765.5-1765.36" wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1697.5-1697.36" + attribute \src "ls180.v:1764.5-1764.36" wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1703.5-1703.38" + attribute \src "ls180.v:1770.5-1770.38" wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1704.5-1704.37" + attribute \src "ls180.v:1771.5-1771.37" wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1705.12-1705.52" - wire width 32 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1702.6-1702.39" + attribute \src "ls180.v:1772.12-1772.52" + wire width 64 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1769.6-1769.39" wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1701.5-1701.38" + attribute \src "ls180.v:1768.5-1768.38" wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1761.11-1761.40" + attribute \src "ls180.v:1828.11-1828.40" wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1766.6-1766.35" + attribute \src "ls180.v:1833.6-1833.35" wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1770.6-1770.41" + attribute \src "ls180.v:1837.6-1837.41" wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1771.6-1771.40" + attribute \src "ls180.v:1838.6-1838.40" wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1769.12-1769.54" + attribute \src "ls180.v:1836.12-1836.54" wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1773.6-1773.42" + attribute \src "ls180.v:1840.6-1840.42" wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1774.6-1774.41" + attribute \src "ls180.v:1841.6-1841.41" wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1772.12-1772.55" + attribute \src "ls180.v:1839.12-1839.55" wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1758.11-1758.38" + attribute \src "ls180.v:1825.11-1825.38" wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1760.11-1760.40" + attribute \src "ls180.v:1827.11-1827.40" wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1767.12-1767.44" + attribute \src "ls180.v:1834.12-1834.44" wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1768.12-1768.46" + attribute \src "ls180.v:1835.12-1835.46" wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1759.5-1759.34" + attribute \src "ls180.v:1826.5-1826.34" wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1744.6-1744.38" + attribute \src "ls180.v:1811.6-1811.38" wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1745.6-1745.37" + attribute \src "ls180.v:1812.6-1812.37" wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1746.12-1746.51" + attribute \src "ls180.v:1813.12-1813.51" wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1743.6-1743.38" + attribute \src "ls180.v:1810.6-1810.38" wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1742.6-1742.38" + attribute \src "ls180.v:1809.6-1809.38" wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1749.6-1749.40" + attribute \src "ls180.v:1816.6-1816.40" wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1750.6-1750.39" + attribute \src "ls180.v:1817.6-1817.39" wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1751.12-1751.53" + attribute \src "ls180.v:1818.12-1818.53" wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1748.6-1748.40" + attribute \src "ls180.v:1815.6-1815.40" wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1747.6-1747.40" + attribute \src "ls180.v:1814.6-1814.40" wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1756.12-1756.46" + attribute \src "ls180.v:1823.12-1823.46" wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1757.12-1757.47" + attribute \src "ls180.v:1824.12-1824.47" wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1754.6-1754.39" + attribute \src "ls180.v:1821.6-1821.39" wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1755.6-1755.45" + attribute \src "ls180.v:1822.6-1822.45" wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1752.6-1752.39" + attribute \src "ls180.v:1819.6-1819.39" wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1753.6-1753.45" + attribute \src "ls180.v:1820.6-1820.45" wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1762.11-1762.43" + attribute \src "ls180.v:1829.11-1829.43" wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1763.12-1763.46" + attribute \src "ls180.v:1830.12-1830.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1765.12-1765.46" + attribute \src "ls180.v:1832.12-1832.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1764.6-1764.37" + attribute \src "ls180.v:1831.6-1831.37" wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1694.6-1694.43" + attribute \src "ls180.v:1761.6-1761.43" wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1739.6-1739.43" + attribute \src "ls180.v:1806.6-1806.43" wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1695.6-1695.42" + attribute \src "ls180.v:1762.6-1762.42" wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1740.6-1740.42" + attribute \src "ls180.v:1807.6-1807.42" wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1696.12-1696.56" + attribute \src "ls180.v:1763.12-1763.56" wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1741.12-1741.56" + attribute \src "ls180.v:1808.12-1808.56" wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1693.6-1693.43" + attribute \src "ls180.v:1760.6-1760.43" wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1738.6-1738.43" + attribute \src "ls180.v:1805.6-1805.43" wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1692.6-1692.43" + attribute \src "ls180.v:1759.6-1759.43" wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1737.6-1737.43" + attribute \src "ls180.v:1804.6-1804.43" wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1143.6-1143.27" + attribute \src "ls180.v:1210.6-1210.27" wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1142.5-1142.28" + attribute \src "ls180.v:1209.5-1209.28" wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1145.5-1145.28" + attribute \src "ls180.v:1212.5-1212.28" wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1146.5-1146.29" + attribute \src "ls180.v:1213.5-1213.29" wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1144.11-1144.34" + attribute \src "ls180.v:1211.11-1211.34" wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1140.5-1140.26" + attribute \src "ls180.v:1207.5-1207.26" wire \main_sdphy_clocker_re - attribute \src "ls180.v:1141.6-1141.29" + attribute \src "ls180.v:1208.6-1208.29" wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1139.11-1139.37" + attribute \src "ls180.v:1206.11-1206.37" wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1243.6-1243.41" + attribute \src "ls180.v:1310.6-1310.41" wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1244.6-1244.40" + attribute \src "ls180.v:1311.6-1311.40" wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1245.12-1245.54" + attribute \src "ls180.v:1312.12-1312.54" wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1242.6-1242.41" + attribute \src "ls180.v:1309.6-1309.41" wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1241.6-1241.41" + attribute \src "ls180.v:1308.6-1308.41" wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1248.5-1248.42" + attribute \src "ls180.v:1315.5-1315.42" wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1249.5-1249.41" + attribute \src "ls180.v:1316.5-1316.41" wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1250.11-1250.55" + attribute \src "ls180.v:1317.11-1317.55" wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1247.6-1247.43" + attribute \src "ls180.v:1314.6-1314.43" wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1246.5-1246.42" + attribute \src "ls180.v:1313.5-1313.42" wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1233.11-1233.47" + attribute \src "ls180.v:1300.11-1300.47" wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1234.6-1234.46" + attribute \src "ls180.v:1301.6-1301.46" wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1224.5-1224.46" + attribute \src "ls180.v:1291.5-1291.46" wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1225.5-1225.45" + attribute \src "ls180.v:1292.5-1292.45" wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1226.6-1226.54" + attribute \src "ls180.v:1293.6-1293.54" wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1223.6-1223.47" + attribute \src "ls180.v:1290.6-1290.47" wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1222.6-1222.47" + attribute \src "ls180.v:1289.6-1289.47" wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1229.5-1229.48" + attribute \src "ls180.v:1296.5-1296.48" wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1230.5-1230.47" + attribute \src "ls180.v:1297.5-1297.47" wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1231.11-1231.61" + attribute \src "ls180.v:1298.11-1298.61" wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1232.11-1232.74" + attribute \src "ls180.v:1299.11-1299.74" wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1228.6-1228.49" + attribute \src "ls180.v:1295.6-1295.49" wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1227.6-1227.49" + attribute \src "ls180.v:1294.6-1294.49" wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1235.5-1235.46" + attribute \src "ls180.v:1302.5-1302.46" wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1206.6-1206.40" + attribute \src "ls180.v:1273.6-1273.40" wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1207.6-1207.39" + attribute \src "ls180.v:1274.6-1274.39" wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1208.6-1208.46" + attribute \src "ls180.v:1275.6-1275.46" wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1209.6-1209.48" + attribute \src "ls180.v:1276.6-1276.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1210.6-1210.48" + attribute \src "ls180.v:1277.6-1277.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1211.6-1211.49" + attribute \src "ls180.v:1278.6-1278.49" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1212.12-1212.55" + attribute \src "ls180.v:1279.12-1279.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1213.12-1213.55" + attribute \src "ls180.v:1280.12-1280.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1214.6-1214.50" + attribute \src "ls180.v:1281.6-1281.50" wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1205.5-1205.39" + attribute \src "ls180.v:1272.5-1272.39" wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1204.6-1204.40" + attribute \src "ls180.v:1271.6-1271.40" wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1251.5-1251.31" + attribute \src "ls180.v:1318.5-1318.31" wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1846.5-1846.59" + attribute \src "ls180.v:1913.5-1913.59" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1847.5-1847.62" + attribute \src "ls180.v:1914.5-1914.62" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1221.5-1221.29" + attribute \src "ls180.v:1288.5-1288.29" wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1217.6-1217.47" + attribute \src "ls180.v:1284.6-1284.47" wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1238.6-1238.47" + attribute \src "ls180.v:1305.6-1305.47" wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1218.6-1218.46" + attribute \src "ls180.v:1285.6-1285.46" wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1239.6-1239.46" + attribute \src "ls180.v:1306.6-1306.46" wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1219.12-1219.60" + attribute \src "ls180.v:1286.12-1286.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1240.12-1240.60" + attribute \src "ls180.v:1307.12-1307.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1216.5-1216.46" + attribute \src "ls180.v:1283.5-1283.46" wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1237.6-1237.47" + attribute \src "ls180.v:1304.6-1304.47" wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1215.6-1215.47" + attribute \src "ls180.v:1282.6-1282.47" wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1236.6-1236.47" + attribute \src "ls180.v:1303.6-1303.47" wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1220.6-1220.32" + attribute \src "ls180.v:1287.6-1287.32" wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1203.11-1203.32" + attribute \src "ls180.v:1270.11-1270.32" wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1842.11-1842.60" + attribute \src "ls180.v:1909.11-1909.60" wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1843.5-1843.57" + attribute \src "ls180.v:1910.5-1910.57" wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1178.5-1178.42" + attribute \src "ls180.v:1245.5-1245.42" wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1179.5-1179.41" + attribute \src "ls180.v:1246.5-1246.41" wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1180.5-1180.48" + attribute \src "ls180.v:1247.5-1247.48" wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1181.6-1181.51" + attribute \src "ls180.v:1248.6-1248.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1182.5-1182.50" + attribute \src "ls180.v:1249.5-1249.50" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1183.5-1183.51" + attribute \src "ls180.v:1250.5-1250.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1184.12-1184.58" + attribute \src "ls180.v:1251.12-1251.58" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1185.11-1185.57" + attribute \src "ls180.v:1252.11-1252.57" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1186.5-1186.52" + attribute \src "ls180.v:1253.5-1253.52" wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1177.6-1177.43" + attribute \src "ls180.v:1244.6-1244.43" wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1176.6-1176.43" + attribute \src "ls180.v:1243.6-1243.43" wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1188.5-1188.41" + attribute \src "ls180.v:1255.5-1255.41" wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1189.5-1189.43" + attribute \src "ls180.v:1256.5-1256.43" wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1190.5-1190.44" + attribute \src "ls180.v:1257.5-1257.44" wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1191.11-1191.50" + attribute \src "ls180.v:1258.11-1258.50" wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1192.5-1192.45" + attribute \src "ls180.v:1259.5-1259.45" wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1187.6-1187.36" + attribute \src "ls180.v:1254.6-1254.36" wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1195.5-1195.30" + attribute \src "ls180.v:1262.5-1262.30" wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1196.11-1196.46" + attribute \src "ls180.v:1263.11-1263.46" wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1194.5-1194.31" + attribute \src "ls180.v:1261.5-1261.31" wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1193.5-1193.31" + attribute \src "ls180.v:1260.5-1260.31" wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1199.5-1199.32" + attribute \src "ls180.v:1266.5-1266.32" wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1200.11-1200.46" + attribute \src "ls180.v:1267.11-1267.46" wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1201.11-1201.48" + attribute \src "ls180.v:1268.11-1268.48" wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1198.5-1198.33" + attribute \src "ls180.v:1265.5-1265.33" wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1197.5-1197.33" + attribute \src "ls180.v:1264.5-1264.33" wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1202.12-1202.35" + attribute \src "ls180.v:1269.12-1269.35" wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1844.12-1844.63" + attribute \src "ls180.v:1911.12-1911.63" wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1845.5-1845.59" + attribute \src "ls180.v:1912.5-1912.59" wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1175.11-1175.32" + attribute \src "ls180.v:1242.11-1242.32" wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1838.11-1838.59" + attribute \src "ls180.v:1905.11-1905.59" wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1839.5-1839.56" + attribute \src "ls180.v:1906.5-1906.56" wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1174.5-1174.25" + attribute \src "ls180.v:1241.5-1241.25" wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1162.6-1162.43" + attribute \src "ls180.v:1229.6-1229.43" wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1163.12-1163.50" + attribute \src "ls180.v:1230.12-1230.50" wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1161.6-1161.35" + attribute \src "ls180.v:1228.6-1228.35" wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1165.5-1165.41" + attribute \src "ls180.v:1232.5-1232.41" wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1166.5-1166.43" + attribute \src "ls180.v:1233.5-1233.43" wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1167.5-1167.44" + attribute \src "ls180.v:1234.5-1234.44" wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1168.11-1168.50" + attribute \src "ls180.v:1235.11-1235.50" wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1169.5-1169.45" + attribute \src "ls180.v:1236.5-1236.45" wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1164.6-1164.36" + attribute \src "ls180.v:1231.6-1231.36" wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1172.5-1172.30" + attribute \src "ls180.v:1239.5-1239.30" wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1173.11-1173.44" + attribute \src "ls180.v:1240.11-1240.44" wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1171.5-1171.31" + attribute \src "ls180.v:1238.5-1238.31" wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1170.5-1170.31" + attribute \src "ls180.v:1237.5-1237.31" wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1359.11-1359.33" + attribute \src "ls180.v:1426.11-1426.33" wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1858.11-1858.62" + attribute \src "ls180.v:1925.11-1925.62" wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1859.5-1859.59" + attribute \src "ls180.v:1926.5-1926.59" wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1399.6-1399.43" + attribute \src "ls180.v:1466.6-1466.43" wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1400.6-1400.42" + attribute \src "ls180.v:1467.6-1467.42" wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1401.12-1401.56" + attribute \src "ls180.v:1468.12-1468.56" wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1398.6-1398.43" + attribute \src "ls180.v:1465.6-1465.43" wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1397.6-1397.43" + attribute \src "ls180.v:1464.6-1464.43" wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1404.5-1404.44" + attribute \src "ls180.v:1471.5-1471.44" wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1405.5-1405.43" + attribute \src "ls180.v:1472.5-1472.43" wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1406.11-1406.57" + attribute \src "ls180.v:1473.11-1473.57" wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1403.6-1403.45" + attribute \src "ls180.v:1470.6-1470.45" wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1402.5-1402.44" + attribute \src "ls180.v:1469.5-1469.44" wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1389.5-1389.43" + attribute \src "ls180.v:1456.5-1456.43" wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1390.6-1390.48" + attribute \src "ls180.v:1457.6-1457.48" wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1380.5-1380.48" + attribute \src "ls180.v:1447.5-1447.48" wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1381.5-1381.47" + attribute \src "ls180.v:1448.5-1448.47" wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1382.12-1382.62" + attribute \src "ls180.v:1449.12-1449.62" wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1379.6-1379.49" + attribute \src "ls180.v:1446.6-1446.49" wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1378.6-1378.49" + attribute \src "ls180.v:1445.6-1445.49" wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1385.5-1385.50" + attribute \src "ls180.v:1452.5-1452.50" wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1386.5-1386.49" + attribute \src "ls180.v:1453.5-1453.49" wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1387.11-1387.63" + attribute \src "ls180.v:1454.11-1454.63" wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1388.11-1388.76" + attribute \src "ls180.v:1455.11-1455.76" wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1384.6-1384.51" + attribute \src "ls180.v:1451.6-1451.51" wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1383.6-1383.51" + attribute \src "ls180.v:1450.6-1450.51" wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1391.5-1391.48" + attribute \src "ls180.v:1458.5-1458.48" wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1362.6-1362.42" + attribute \src "ls180.v:1429.6-1429.42" wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1363.6-1363.41" + attribute \src "ls180.v:1430.6-1430.41" wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1364.6-1364.48" + attribute \src "ls180.v:1431.6-1431.48" wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1365.6-1365.50" + attribute \src "ls180.v:1432.6-1432.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1366.6-1366.50" + attribute \src "ls180.v:1433.6-1433.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1367.6-1367.51" + attribute \src "ls180.v:1434.6-1434.51" wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1368.12-1368.57" + attribute \src "ls180.v:1435.12-1435.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1369.12-1369.57" + attribute \src "ls180.v:1436.12-1436.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1370.6-1370.52" + attribute \src "ls180.v:1437.6-1437.52" wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1361.5-1361.41" + attribute \src "ls180.v:1428.5-1428.41" wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1360.6-1360.42" + attribute \src "ls180.v:1427.6-1427.42" wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1407.5-1407.33" + attribute \src "ls180.v:1474.5-1474.33" wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1862.5-1862.62" + attribute \src "ls180.v:1929.5-1929.62" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1863.5-1863.65" + attribute \src "ls180.v:1930.5-1930.65" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1377.5-1377.31" + attribute \src "ls180.v:1444.5-1444.31" wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1373.6-1373.49" + attribute \src "ls180.v:1440.6-1440.49" wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1394.6-1394.49" + attribute \src "ls180.v:1461.6-1461.49" wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1374.6-1374.48" + attribute \src "ls180.v:1441.6-1441.48" wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1395.6-1395.48" + attribute \src "ls180.v:1462.6-1462.48" wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1375.12-1375.62" + attribute \src "ls180.v:1442.12-1442.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1396.12-1396.62" + attribute \src "ls180.v:1463.12-1463.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1372.5-1372.48" + attribute \src "ls180.v:1439.5-1439.48" wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1393.6-1393.49" + attribute \src "ls180.v:1460.6-1460.49" wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1371.6-1371.49" + attribute \src "ls180.v:1438.6-1438.49" wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1392.6-1392.49" + attribute \src "ls180.v:1459.6-1459.49" wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1376.6-1376.34" + attribute \src "ls180.v:1443.6-1443.34" wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1332.5-1332.43" + attribute \src "ls180.v:1399.5-1399.43" wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1333.5-1333.42" + attribute \src "ls180.v:1400.5-1400.42" wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1334.5-1334.49" + attribute \src "ls180.v:1401.5-1401.49" wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1335.6-1335.52" + attribute \src "ls180.v:1402.6-1402.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1336.5-1336.51" + attribute \src "ls180.v:1403.5-1403.51" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1337.5-1337.52" + attribute \src "ls180.v:1404.5-1404.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1338.12-1338.59" + attribute \src "ls180.v:1405.12-1405.59" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1339.11-1339.58" + attribute \src "ls180.v:1406.11-1406.58" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1340.5-1340.53" + attribute \src "ls180.v:1407.5-1407.53" wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1331.6-1331.44" + attribute \src "ls180.v:1398.6-1398.44" wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1330.6-1330.44" + attribute \src "ls180.v:1397.6-1397.44" wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1342.5-1342.42" + attribute \src "ls180.v:1409.5-1409.42" wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1343.5-1343.44" + attribute \src "ls180.v:1410.5-1410.44" wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1344.5-1344.45" + attribute \src "ls180.v:1411.5-1411.45" wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1345.11-1345.51" + attribute \src "ls180.v:1412.11-1412.51" wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1346.5-1346.46" + attribute \src "ls180.v:1413.5-1413.46" wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1341.6-1341.37" + attribute \src "ls180.v:1408.6-1408.37" wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1349.5-1349.31" + attribute \src "ls180.v:1416.5-1416.31" wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1350.11-1350.53" + attribute \src "ls180.v:1417.11-1417.53" wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1348.5-1348.32" + attribute \src "ls180.v:1415.5-1415.32" wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1347.5-1347.32" + attribute \src "ls180.v:1414.5-1414.32" wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1353.5-1353.34" + attribute \src "ls180.v:1420.5-1420.34" wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1354.5-1354.33" + attribute \src "ls180.v:1421.5-1421.33" wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1355.11-1355.47" + attribute \src "ls180.v:1422.11-1422.47" wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1356.11-1356.49" + attribute \src "ls180.v:1423.11-1423.49" wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1352.5-1352.34" + attribute \src "ls180.v:1419.5-1419.34" wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1351.5-1351.34" + attribute \src "ls180.v:1418.5-1418.34" wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1357.5-1357.26" + attribute \src "ls180.v:1424.5-1424.26" wire \main_sdphy_datar_stop - attribute \src "ls180.v:1358.12-1358.36" + attribute \src "ls180.v:1425.12-1425.36" wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1860.12-1860.65" + attribute \src "ls180.v:1927.12-1927.65" wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1861.5-1861.61" + attribute \src "ls180.v:1928.5-1928.61" wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1267.11-1267.33" + attribute \src "ls180.v:1334.11-1334.33" wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1854.11-1854.54" + attribute \src "ls180.v:1921.11-1921.54" wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1855.5-1855.51" + attribute \src "ls180.v:1922.5-1922.51" wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1321.6-1321.42" + attribute \src "ls180.v:1388.6-1388.42" wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1322.6-1322.41" + attribute \src "ls180.v:1389.6-1389.41" wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1323.12-1323.55" + attribute \src "ls180.v:1390.12-1390.55" wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1320.6-1320.42" + attribute \src "ls180.v:1387.6-1387.42" wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1319.6-1319.42" + attribute \src "ls180.v:1386.6-1386.42" wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1326.5-1326.43" + attribute \src "ls180.v:1393.5-1393.43" wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1327.5-1327.42" + attribute \src "ls180.v:1394.5-1394.42" wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1328.11-1328.56" + attribute \src "ls180.v:1395.11-1395.56" wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1325.6-1325.44" + attribute \src "ls180.v:1392.6-1392.44" wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1324.5-1324.43" + attribute \src "ls180.v:1391.5-1391.43" wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1311.11-1311.48" + attribute \src "ls180.v:1378.11-1378.48" wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1312.6-1312.47" + attribute \src "ls180.v:1379.6-1379.47" wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1302.5-1302.47" + attribute \src "ls180.v:1369.5-1369.47" wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1303.5-1303.46" + attribute \src "ls180.v:1370.5-1370.46" wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1304.6-1304.55" + attribute \src "ls180.v:1371.6-1371.55" wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1301.6-1301.48" + attribute \src "ls180.v:1368.6-1368.48" wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1300.6-1300.48" + attribute \src "ls180.v:1367.6-1367.48" wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1307.5-1307.49" + attribute \src "ls180.v:1374.5-1374.49" wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1308.5-1308.48" + attribute \src "ls180.v:1375.5-1375.48" wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1309.11-1309.62" + attribute \src "ls180.v:1376.11-1376.62" wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1310.11-1310.75" + attribute \src "ls180.v:1377.11-1377.75" wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1306.6-1306.50" + attribute \src "ls180.v:1373.6-1373.50" wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1305.6-1305.50" + attribute \src "ls180.v:1372.6-1372.50" wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1313.5-1313.47" + attribute \src "ls180.v:1380.5-1380.47" wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1284.6-1284.41" + attribute \src "ls180.v:1351.6-1351.41" wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1285.6-1285.40" + attribute \src "ls180.v:1352.6-1352.40" wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1286.6-1286.47" + attribute \src "ls180.v:1353.6-1353.47" wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1287.6-1287.49" + attribute \src "ls180.v:1354.6-1354.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1288.6-1288.49" + attribute \src "ls180.v:1355.6-1355.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1289.6-1289.50" + attribute \src "ls180.v:1356.6-1356.50" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1290.12-1290.56" + attribute \src "ls180.v:1357.12-1357.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1291.12-1291.56" + attribute \src "ls180.v:1358.12-1358.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1292.6-1292.51" + attribute \src "ls180.v:1359.6-1359.51" wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1283.5-1283.40" + attribute \src "ls180.v:1350.5-1350.40" wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1282.6-1282.41" + attribute \src "ls180.v:1349.6-1349.41" wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1329.5-1329.32" + attribute \src "ls180.v:1396.5-1396.32" wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1850.5-1850.59" + attribute \src "ls180.v:1917.5-1917.59" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1851.5-1851.62" + attribute \src "ls180.v:1918.5-1918.62" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1299.5-1299.30" + attribute \src "ls180.v:1366.5-1366.30" wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1295.6-1295.48" + attribute \src "ls180.v:1362.6-1362.48" wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1316.6-1316.48" + attribute \src "ls180.v:1383.6-1383.48" wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1296.6-1296.47" + attribute \src "ls180.v:1363.6-1363.47" wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1317.6-1317.47" + attribute \src "ls180.v:1384.6-1384.47" wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1297.12-1297.61" + attribute \src "ls180.v:1364.12-1364.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1318.12-1318.61" + attribute \src "ls180.v:1385.12-1385.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1294.5-1294.47" + attribute \src "ls180.v:1361.5-1361.47" wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1315.6-1315.48" + attribute \src "ls180.v:1382.6-1382.48" wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1293.6-1293.48" + attribute \src "ls180.v:1360.6-1360.48" wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1314.6-1314.48" + attribute \src "ls180.v:1381.6-1381.48" wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1298.6-1298.33" + attribute \src "ls180.v:1365.6-1365.33" wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1281.5-1281.27" + attribute \src "ls180.v:1348.5-1348.27" wire \main_sdphy_dataw_error - attribute \src "ls180.v:1270.5-1270.43" + attribute \src "ls180.v:1337.5-1337.43" wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1271.5-1271.42" + attribute \src "ls180.v:1338.5-1338.42" wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1272.5-1272.49" + attribute \src "ls180.v:1339.5-1339.49" wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1273.5-1273.51" + attribute \src "ls180.v:1340.5-1340.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1274.5-1274.51" + attribute \src "ls180.v:1341.5-1341.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1275.5-1275.52" + attribute \src "ls180.v:1342.5-1342.52" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1276.11-1276.58" + attribute \src "ls180.v:1343.11-1343.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1277.11-1277.58" + attribute \src "ls180.v:1344.11-1344.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1278.5-1278.53" + attribute \src "ls180.v:1345.5-1345.53" wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1269.6-1269.44" + attribute \src "ls180.v:1336.6-1336.44" wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1268.5-1268.43" + attribute \src "ls180.v:1335.5-1335.43" wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1253.6-1253.44" + attribute \src "ls180.v:1320.6-1320.44" wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1254.12-1254.51" + attribute \src "ls180.v:1321.12-1321.51" wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1252.6-1252.36" + attribute \src "ls180.v:1319.6-1319.36" wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1256.5-1256.42" + attribute \src "ls180.v:1323.5-1323.42" wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1257.5-1257.44" + attribute \src "ls180.v:1324.5-1324.44" wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1258.5-1258.45" + attribute \src "ls180.v:1325.5-1325.45" wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1259.11-1259.51" + attribute \src "ls180.v:1326.11-1326.51" wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1260.5-1260.46" + attribute \src "ls180.v:1327.5-1327.46" wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1255.6-1255.37" + attribute \src "ls180.v:1322.6-1322.37" wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1263.5-1263.32" + attribute \src "ls180.v:1330.5-1330.32" wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1264.5-1264.31" + attribute \src "ls180.v:1331.5-1331.31" wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1265.11-1265.45" + attribute \src "ls180.v:1332.11-1332.45" wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1262.5-1262.32" + attribute \src "ls180.v:1329.5-1329.32" wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1261.5-1261.32" + attribute \src "ls180.v:1328.5-1328.32" wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1279.5-1279.27" + attribute \src "ls180.v:1346.5-1346.27" wire \main_sdphy_dataw_start - attribute \src "ls180.v:1266.5-1266.26" + attribute \src "ls180.v:1333.5-1333.26" wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1280.5-1280.27" + attribute \src "ls180.v:1347.5-1347.27" wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1160.11-1160.32" + attribute \src "ls180.v:1227.11-1227.32" wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1834.11-1834.59" + attribute \src "ls180.v:1901.11-1901.59" wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1835.5-1835.56" + attribute \src "ls180.v:1902.5-1902.56" wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1148.6-1148.34" + attribute \src "ls180.v:1215.6-1215.34" wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1147.6-1147.35" + attribute \src "ls180.v:1214.6-1214.35" wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1150.5-1150.33" + attribute \src "ls180.v:1217.5-1217.33" wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1149.6-1149.35" + attribute \src "ls180.v:1216.6-1216.35" wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1152.6-1152.43" + attribute \src "ls180.v:1219.6-1219.43" wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1153.12-1153.50" + attribute \src "ls180.v:1220.12-1220.50" wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1151.6-1151.35" + attribute \src "ls180.v:1218.6-1218.35" wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1155.5-1155.41" + attribute \src "ls180.v:1222.5-1222.41" wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1156.5-1156.43" + attribute \src "ls180.v:1223.5-1223.43" wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1157.5-1157.44" + attribute \src "ls180.v:1224.5-1224.44" wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1158.11-1158.50" + attribute \src "ls180.v:1225.11-1225.50" wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1159.5-1159.45" + attribute \src "ls180.v:1226.5-1226.45" wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1154.6-1154.36" + attribute \src "ls180.v:1221.6-1221.36" wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1408.6-1408.27" + attribute \src "ls180.v:1475.6-1475.27" wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1409.5-1409.28" + attribute \src "ls180.v:1476.5-1476.28" wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1410.6-1410.29" + attribute \src "ls180.v:1477.6-1477.29" wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1411.6-1411.30" + attribute \src "ls180.v:1478.6-1478.30" wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1412.11-1412.35" + attribute \src "ls180.v:1479.11-1479.35" wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1413.12-1413.36" + attribute \src "ls180.v:1480.12-1480.36" wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1414.6-1414.31" + attribute \src "ls180.v:1481.6-1481.31" wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1137.6-1137.23" + attribute \src "ls180.v:1204.6-1204.23" wire \main_sdphy_status - attribute \src "ls180.v:1138.6-1138.19" + attribute \src "ls180.v:1205.6-1205.19" wire \main_sdphy_we - attribute \src "ls180.v:372.5-372.26" + attribute \src "ls180.v:421.5-421.26" wire \main_sdram_address_re - attribute \src "ls180.v:371.12-371.38" + attribute \src "ls180.v:420.12-420.38" wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:374.5-374.27" + attribute \src "ls180.v:423.5-423.27" wire \main_sdram_baddress_re - attribute \src "ls180.v:373.11-373.38" + attribute \src "ls180.v:422.11-422.38" wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:470.5-470.43" + attribute \src "ls180.v:519.5-519.43" wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:492.11-492.63" + attribute \src "ls180.v:541.11-541.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:497.6-497.58" + attribute \src "ls180.v:546.6-546.58" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:502.6-502.64" + attribute \src "ls180.v:551.6-551.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:503.6-503.63" + attribute \src "ls180.v:552.6-552.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:501.13-501.78" + attribute \src "ls180.v:550.13-550.78" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:500.6-500.69" + attribute \src "ls180.v:549.6-549.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:506.6-506.65" + attribute \src "ls180.v:555.6-555.65" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:507.6-507.64" + attribute \src "ls180.v:556.6-556.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:505.13-505.79" + attribute \src "ls180.v:554.13-554.79" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:504.6-504.70" + attribute \src "ls180.v:553.6-553.70" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:489.11-489.61" + attribute \src "ls180.v:538.11-538.61" wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:491.11-491.63" + attribute \src "ls180.v:540.11-540.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:498.12-498.67" + attribute \src "ls180.v:547.12-547.67" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:499.13-499.70" + attribute \src "ls180.v:548.13-548.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:490.5-490.57" + attribute \src "ls180.v:539.5-539.57" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:473.5-473.60" + attribute \src "ls180.v:522.5-522.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:474.5-474.59" + attribute \src "ls180.v:523.5-523.59" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:476.13-476.75" + attribute \src "ls180.v:525.13-525.75" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:475.6-475.66" + attribute \src "ls180.v:524.6-524.66" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:472.6-472.61" + attribute \src "ls180.v:521.6-521.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:471.6-471.61" + attribute \src "ls180.v:520.6-520.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:479.6-479.63" + attribute \src "ls180.v:528.6-528.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:480.6-480.62" + attribute \src "ls180.v:529.6-529.62" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:482.13-482.77" + attribute \src "ls180.v:531.13-531.77" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:481.6-481.68" + attribute \src "ls180.v:530.6-530.68" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:478.6-478.63" + attribute \src "ls180.v:527.6-527.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:477.6-477.63" + attribute \src "ls180.v:526.6-526.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:487.13-487.71" + attribute \src "ls180.v:536.13-536.71" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:488.13-488.72" + attribute \src "ls180.v:537.13-537.72" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:485.6-485.63" + attribute \src "ls180.v:534.6-534.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:486.6-486.69" + attribute \src "ls180.v:535.6-535.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:483.6-483.63" + attribute \src "ls180.v:532.6-532.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:484.6-484.69" + attribute \src "ls180.v:533.6-533.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:493.11-493.66" + attribute \src "ls180.v:542.11-542.66" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:494.13-494.70" + attribute \src "ls180.v:543.13-543.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:496.13-496.70" + attribute \src "ls180.v:545.13-545.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:495.6-495.60" + attribute \src "ls180.v:544.6-544.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:510.6-510.51" + attribute \src "ls180.v:559.6-559.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:511.6-511.50" + attribute \src "ls180.v:560.6-560.50" wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:513.13-513.65" + attribute \src "ls180.v:562.13-562.65" wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:512.6-512.56" + attribute \src "ls180.v:561.6-561.56" wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:509.6-509.51" + attribute \src "ls180.v:558.6-558.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:508.6-508.51" + attribute \src "ls180.v:557.6-557.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:516.5-516.52" + attribute \src "ls180.v:565.5-565.52" wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:517.5-517.51" + attribute \src "ls180.v:566.5-566.51" wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:519.12-519.66" + attribute \src "ls180.v:568.12-568.66" wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:518.5-518.57" + attribute \src "ls180.v:567.5-567.57" wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:515.6-515.53" + attribute \src "ls180.v:564.6-564.53" wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:514.5-514.52" + attribute \src "ls180.v:563.5-563.52" wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:462.12-462.49" + attribute \src "ls180.v:511.12-511.49" wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:463.12-463.50" + attribute \src "ls180.v:512.12-512.50" wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:464.5-464.44" + attribute \src "ls180.v:513.5-513.44" wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:467.5-467.47" + attribute \src "ls180.v:516.5-516.47" wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:468.5-468.48" + attribute \src "ls180.v:517.5-517.48" wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:469.5-469.49" + attribute \src "ls180.v:518.5-518.49" wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:465.5-465.44" + attribute \src "ls180.v:514.5-514.44" wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:466.5-466.43" + attribute \src "ls180.v:515.5-515.43" wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:461.5-461.38" + attribute \src "ls180.v:510.5-510.38" wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:460.5-460.38" + attribute \src "ls180.v:509.5-509.38" wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:459.5-459.40" + attribute \src "ls180.v:508.5-508.40" wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:458.6-458.41" + attribute \src "ls180.v:507.6-507.41" wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:454.13-454.45" + attribute \src "ls180.v:503.13-503.45" wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:455.6-455.38" + attribute \src "ls180.v:504.6-504.38" wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:457.5-457.44" + attribute \src "ls180.v:506.5-506.44" wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:452.6-452.39" + attribute \src "ls180.v:501.6-501.39" wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:451.6-451.39" + attribute \src "ls180.v:500.6-500.39" wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:456.5-456.44" + attribute \src "ls180.v:505.5-505.44" wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:453.6-453.36" + attribute \src "ls180.v:502.6-502.36" wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:520.12-520.39" + attribute \src "ls180.v:569.12-569.39" wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:524.5-524.38" + attribute \src "ls180.v:573.5-573.38" wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:525.5-525.47" + attribute \src "ls180.v:574.5-574.47" wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:522.6-522.37" + attribute \src "ls180.v:571.6-571.37" wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:523.5-523.37" + attribute \src "ls180.v:572.5-572.37" wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:521.5-521.39" + attribute \src "ls180.v:570.5-570.39" wire \main_sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:532.32-532.69" + attribute \src "ls180.v:581.32-581.69" wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:531.6-531.43" + attribute \src "ls180.v:580.6-580.43" wire \main_sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:530.32-530.68" + attribute \src "ls180.v:579.32-579.68" wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:529.6-529.42" + attribute \src "ls180.v:578.6-578.42" wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:528.11-528.48" + attribute \src "ls180.v:577.11-577.48" wire width 3 \main_sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:527.32-527.69" + attribute \src "ls180.v:576.32-576.69" wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:526.6-526.43" + attribute \src "ls180.v:575.6-575.43" wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:552.5-552.43" + attribute \src "ls180.v:601.5-601.43" wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:574.11-574.63" + attribute \src "ls180.v:623.11-623.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:579.6-579.58" + attribute \src "ls180.v:628.6-628.58" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:584.6-584.64" + attribute \src "ls180.v:633.6-633.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:585.6-585.63" + attribute \src "ls180.v:634.6-634.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:583.13-583.78" + attribute \src "ls180.v:632.13-632.78" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:582.6-582.69" + attribute \src "ls180.v:631.6-631.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:588.6-588.65" + attribute \src "ls180.v:637.6-637.65" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:589.6-589.64" + attribute \src "ls180.v:638.6-638.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:587.13-587.79" + attribute \src "ls180.v:636.13-636.79" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:586.6-586.70" + attribute \src "ls180.v:635.6-635.70" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:571.11-571.61" + attribute \src "ls180.v:620.11-620.61" wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:573.11-573.63" + attribute \src "ls180.v:622.11-622.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:580.12-580.67" + attribute \src "ls180.v:629.12-629.67" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:581.13-581.70" + attribute \src "ls180.v:630.13-630.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:572.5-572.57" + attribute \src "ls180.v:621.5-621.57" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:555.5-555.60" + attribute \src "ls180.v:604.5-604.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:556.5-556.59" + attribute \src "ls180.v:605.5-605.59" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:558.13-558.75" + attribute \src "ls180.v:607.13-607.75" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:557.6-557.66" + attribute \src "ls180.v:606.6-606.66" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:554.6-554.61" + attribute \src "ls180.v:603.6-603.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:553.6-553.61" + attribute \src "ls180.v:602.6-602.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:561.6-561.63" + attribute \src "ls180.v:610.6-610.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:562.6-562.62" + attribute \src "ls180.v:611.6-611.62" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:564.13-564.77" + attribute \src "ls180.v:613.13-613.77" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:563.6-563.68" + attribute \src "ls180.v:612.6-612.68" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:560.6-560.63" + attribute \src "ls180.v:609.6-609.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:559.6-559.63" + attribute \src "ls180.v:608.6-608.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:569.13-569.71" + attribute \src "ls180.v:618.13-618.71" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:570.13-570.72" + attribute \src "ls180.v:619.13-619.72" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:567.6-567.63" + attribute \src "ls180.v:616.6-616.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:568.6-568.69" + attribute \src "ls180.v:617.6-617.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:565.6-565.63" + attribute \src "ls180.v:614.6-614.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:566.6-566.69" + attribute \src "ls180.v:615.6-615.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:575.11-575.66" + attribute \src "ls180.v:624.11-624.66" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:576.13-576.70" + attribute \src "ls180.v:625.13-625.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:578.13-578.70" + attribute \src "ls180.v:627.13-627.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:577.6-577.60" + attribute \src "ls180.v:626.6-626.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:592.6-592.51" + attribute \src "ls180.v:641.6-641.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:593.6-593.50" + attribute \src "ls180.v:642.6-642.50" wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:595.13-595.65" + attribute \src "ls180.v:644.13-644.65" wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:594.6-594.56" + attribute \src "ls180.v:643.6-643.56" wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:591.6-591.51" + attribute \src "ls180.v:640.6-640.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:590.6-590.51" + attribute \src "ls180.v:639.6-639.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:598.5-598.52" + attribute \src "ls180.v:647.5-647.52" wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:599.5-599.51" + attribute \src "ls180.v:648.5-648.51" wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:601.12-601.66" + attribute \src "ls180.v:650.12-650.66" wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:600.5-600.57" + attribute \src "ls180.v:649.5-649.57" wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:597.6-597.53" + attribute \src "ls180.v:646.6-646.53" wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:596.5-596.52" + attribute \src "ls180.v:645.5-645.52" wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:544.12-544.49" + attribute \src "ls180.v:593.12-593.49" wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:545.12-545.50" + attribute \src "ls180.v:594.12-594.50" wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:546.5-546.44" + attribute \src "ls180.v:595.5-595.44" wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:549.5-549.47" + attribute \src "ls180.v:598.5-598.47" wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:550.5-550.48" + attribute \src "ls180.v:599.5-599.48" wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:551.5-551.49" + attribute \src "ls180.v:600.5-600.49" wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:547.5-547.44" + attribute \src "ls180.v:596.5-596.44" wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:548.5-548.43" + attribute \src "ls180.v:597.5-597.43" wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:543.5-543.38" + attribute \src "ls180.v:592.5-592.38" wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:542.5-542.38" + attribute \src "ls180.v:591.5-591.38" wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:541.5-541.40" + attribute \src "ls180.v:590.5-590.40" wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:540.6-540.41" + attribute \src "ls180.v:589.6-589.41" wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:536.13-536.45" + attribute \src "ls180.v:585.13-585.45" wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:537.6-537.38" + attribute \src "ls180.v:586.6-586.38" wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:539.5-539.44" + attribute \src "ls180.v:588.5-588.44" wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:534.6-534.39" + attribute \src "ls180.v:583.6-583.39" wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:533.6-533.39" + attribute \src "ls180.v:582.6-582.39" wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:538.5-538.44" + attribute \src "ls180.v:587.5-587.44" wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:535.6-535.36" + attribute \src "ls180.v:584.6-584.36" wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:602.12-602.39" + attribute \src "ls180.v:651.12-651.39" wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:606.5-606.38" + attribute \src "ls180.v:655.5-655.38" wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:607.5-607.47" + attribute \src "ls180.v:656.5-656.47" wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:604.6-604.37" + attribute \src "ls180.v:653.6-653.37" wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:605.5-605.37" + attribute \src "ls180.v:654.5-654.37" wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:603.5-603.39" + attribute \src "ls180.v:652.5-652.39" wire \main_sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:614.32-614.69" + attribute \src "ls180.v:663.32-663.69" wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:613.6-613.43" + attribute \src "ls180.v:662.6-662.43" wire \main_sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:612.32-612.68" + attribute \src "ls180.v:661.32-661.68" wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:611.6-611.42" + attribute \src "ls180.v:660.6-660.42" wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:610.11-610.48" + attribute \src "ls180.v:659.11-659.48" wire width 3 \main_sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:609.32-609.69" + attribute \src "ls180.v:658.32-658.69" wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:608.6-608.43" + attribute \src "ls180.v:657.6-657.43" wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:634.5-634.43" + attribute \src "ls180.v:683.5-683.43" wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:656.11-656.63" + attribute \src "ls180.v:705.11-705.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:661.6-661.58" + attribute \src "ls180.v:710.6-710.58" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:666.6-666.64" + attribute \src "ls180.v:715.6-715.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:667.6-667.63" + attribute \src "ls180.v:716.6-716.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:665.13-665.78" + attribute \src "ls180.v:714.13-714.78" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:664.6-664.69" + attribute \src "ls180.v:713.6-713.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:670.6-670.65" + attribute \src "ls180.v:719.6-719.65" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:671.6-671.64" + attribute \src "ls180.v:720.6-720.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:669.13-669.79" + attribute \src "ls180.v:718.13-718.79" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:668.6-668.70" + attribute \src "ls180.v:717.6-717.70" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:653.11-653.61" + attribute \src "ls180.v:702.11-702.61" wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:655.11-655.63" + attribute \src "ls180.v:704.11-704.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:662.12-662.67" + attribute \src "ls180.v:711.12-711.67" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:663.13-663.70" + attribute \src "ls180.v:712.13-712.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:654.5-654.57" + attribute \src "ls180.v:703.5-703.57" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:637.5-637.60" + attribute \src "ls180.v:686.5-686.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:638.5-638.59" + attribute \src "ls180.v:687.5-687.59" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:640.13-640.75" + attribute \src "ls180.v:689.13-689.75" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:639.6-639.66" + attribute \src "ls180.v:688.6-688.66" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:636.6-636.61" + attribute \src "ls180.v:685.6-685.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:635.6-635.61" + attribute \src "ls180.v:684.6-684.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:643.6-643.63" + attribute \src "ls180.v:692.6-692.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:644.6-644.62" + attribute \src "ls180.v:693.6-693.62" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:646.13-646.77" + attribute \src "ls180.v:695.13-695.77" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:645.6-645.68" + attribute \src "ls180.v:694.6-694.68" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:642.6-642.63" + attribute \src "ls180.v:691.6-691.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:641.6-641.63" + attribute \src "ls180.v:690.6-690.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:651.13-651.71" + attribute \src "ls180.v:700.13-700.71" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:652.13-652.72" + attribute \src "ls180.v:701.13-701.72" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:649.6-649.63" + attribute \src "ls180.v:698.6-698.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:650.6-650.69" + attribute \src "ls180.v:699.6-699.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:647.6-647.63" + attribute \src "ls180.v:696.6-696.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:648.6-648.69" + attribute \src "ls180.v:697.6-697.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:657.11-657.66" + attribute \src "ls180.v:706.11-706.66" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:658.13-658.70" + attribute \src "ls180.v:707.13-707.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:660.13-660.70" + attribute \src "ls180.v:709.13-709.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:659.6-659.60" + attribute \src "ls180.v:708.6-708.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:674.6-674.51" + attribute \src "ls180.v:723.6-723.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:675.6-675.50" + attribute \src "ls180.v:724.6-724.50" wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:677.13-677.65" + attribute \src "ls180.v:726.13-726.65" wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:676.6-676.56" + attribute \src "ls180.v:725.6-725.56" wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:673.6-673.51" + attribute \src "ls180.v:722.6-722.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:672.6-672.51" + attribute \src "ls180.v:721.6-721.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:680.5-680.52" + attribute \src "ls180.v:729.5-729.52" wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:681.5-681.51" + attribute \src "ls180.v:730.5-730.51" wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:683.12-683.66" + attribute \src "ls180.v:732.12-732.66" wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:682.5-682.57" + attribute \src "ls180.v:731.5-731.57" wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:679.6-679.53" + attribute \src "ls180.v:728.6-728.53" wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:678.5-678.52" + attribute \src "ls180.v:727.5-727.52" wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:626.12-626.49" + attribute \src "ls180.v:675.12-675.49" wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:627.12-627.50" + attribute \src "ls180.v:676.12-676.50" wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:628.5-628.44" + attribute \src "ls180.v:677.5-677.44" wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:631.5-631.47" + attribute \src "ls180.v:680.5-680.47" wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:632.5-632.48" + attribute \src "ls180.v:681.5-681.48" wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:633.5-633.49" + attribute \src "ls180.v:682.5-682.49" wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:629.5-629.44" + attribute \src "ls180.v:678.5-678.44" wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:630.5-630.43" + attribute \src "ls180.v:679.5-679.43" wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:625.5-625.38" + attribute \src "ls180.v:674.5-674.38" wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:624.5-624.38" + attribute \src "ls180.v:673.5-673.38" wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:623.5-623.40" + attribute \src "ls180.v:672.5-672.40" wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:622.6-622.41" + attribute \src "ls180.v:671.6-671.41" wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:618.13-618.45" + attribute \src "ls180.v:667.13-667.45" wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:619.6-619.38" + attribute \src "ls180.v:668.6-668.38" wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:621.5-621.44" + attribute \src "ls180.v:670.5-670.44" wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:616.6-616.39" + attribute \src "ls180.v:665.6-665.39" wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:615.6-615.39" + attribute \src "ls180.v:664.6-664.39" wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:620.5-620.44" + attribute \src "ls180.v:669.5-669.44" wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:617.6-617.36" + attribute \src "ls180.v:666.6-666.36" wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:684.12-684.39" + attribute \src "ls180.v:733.12-733.39" wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:688.5-688.38" + attribute \src "ls180.v:737.5-737.38" wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:689.5-689.47" + attribute \src "ls180.v:738.5-738.47" wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:686.6-686.37" + attribute \src "ls180.v:735.6-735.37" wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:687.5-687.37" + attribute \src "ls180.v:736.5-736.37" wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:685.5-685.39" + attribute \src "ls180.v:734.5-734.39" wire \main_sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:696.32-696.69" + attribute \src "ls180.v:745.32-745.69" wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:695.6-695.43" + attribute \src "ls180.v:744.6-744.43" wire \main_sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:694.32-694.68" + attribute \src "ls180.v:743.32-743.68" wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:693.6-693.42" + attribute \src "ls180.v:742.6-742.42" wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:692.11-692.48" + attribute \src "ls180.v:741.11-741.48" wire width 3 \main_sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:691.32-691.69" + attribute \src "ls180.v:740.32-740.69" wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:690.6-690.43" + attribute \src "ls180.v:739.6-739.43" wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:716.5-716.43" + attribute \src "ls180.v:765.5-765.43" wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:738.11-738.63" + attribute \src "ls180.v:787.11-787.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:743.6-743.58" + attribute \src "ls180.v:792.6-792.58" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:748.6-748.64" + attribute \src "ls180.v:797.6-797.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:749.6-749.63" + attribute \src "ls180.v:798.6-798.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:747.13-747.78" + attribute \src "ls180.v:796.13-796.78" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:746.6-746.69" + attribute \src "ls180.v:795.6-795.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:752.6-752.65" + attribute \src "ls180.v:801.6-801.65" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:753.6-753.64" + attribute \src "ls180.v:802.6-802.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:751.13-751.79" + attribute \src "ls180.v:800.13-800.79" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:750.6-750.70" + attribute \src "ls180.v:799.6-799.70" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:735.11-735.61" + attribute \src "ls180.v:784.11-784.61" wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:737.11-737.63" + attribute \src "ls180.v:786.11-786.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:744.12-744.67" + attribute \src "ls180.v:793.12-793.67" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:745.13-745.70" + attribute \src "ls180.v:794.13-794.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:736.5-736.57" + attribute \src "ls180.v:785.5-785.57" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:719.5-719.60" + attribute \src "ls180.v:768.5-768.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:720.5-720.59" + attribute \src "ls180.v:769.5-769.59" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:722.13-722.75" + attribute \src "ls180.v:771.13-771.75" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:721.6-721.66" + attribute \src "ls180.v:770.6-770.66" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:718.6-718.61" + attribute \src "ls180.v:767.6-767.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:717.6-717.61" + attribute \src "ls180.v:766.6-766.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:725.6-725.63" + attribute \src "ls180.v:774.6-774.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:726.6-726.62" + attribute \src "ls180.v:775.6-775.62" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:728.13-728.77" + attribute \src "ls180.v:777.13-777.77" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:727.6-727.68" + attribute \src "ls180.v:776.6-776.68" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:724.6-724.63" + attribute \src "ls180.v:773.6-773.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:723.6-723.63" + attribute \src "ls180.v:772.6-772.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:733.13-733.71" + attribute \src "ls180.v:782.13-782.71" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:734.13-734.72" + attribute \src "ls180.v:783.13-783.72" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:731.6-731.63" + attribute \src "ls180.v:780.6-780.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:732.6-732.69" + attribute \src "ls180.v:781.6-781.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:729.6-729.63" + attribute \src "ls180.v:778.6-778.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:730.6-730.69" + attribute \src "ls180.v:779.6-779.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:739.11-739.66" + attribute \src "ls180.v:788.11-788.66" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:740.13-740.70" + attribute \src "ls180.v:789.13-789.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:742.13-742.70" + attribute \src "ls180.v:791.13-791.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:741.6-741.60" + attribute \src "ls180.v:790.6-790.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:756.6-756.51" + attribute \src "ls180.v:805.6-805.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:757.6-757.50" + attribute \src "ls180.v:806.6-806.50" wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:759.13-759.65" + attribute \src "ls180.v:808.13-808.65" wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:758.6-758.56" + attribute \src "ls180.v:807.6-807.56" wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:755.6-755.51" + attribute \src "ls180.v:804.6-804.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:754.6-754.51" + attribute \src "ls180.v:803.6-803.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:762.5-762.52" + attribute \src "ls180.v:811.5-811.52" wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:763.5-763.51" + attribute \src "ls180.v:812.5-812.51" wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:765.12-765.66" + attribute \src "ls180.v:814.12-814.66" wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:764.5-764.57" + attribute \src "ls180.v:813.5-813.57" wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:761.6-761.53" + attribute \src "ls180.v:810.6-810.53" wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:760.5-760.52" + attribute \src "ls180.v:809.5-809.52" wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:708.12-708.49" + attribute \src "ls180.v:757.12-757.49" wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:709.12-709.50" + attribute \src "ls180.v:758.12-758.50" wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:710.5-710.44" + attribute \src "ls180.v:759.5-759.44" wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:713.5-713.47" + attribute \src "ls180.v:762.5-762.47" wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:714.5-714.48" + attribute \src "ls180.v:763.5-763.48" wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:715.5-715.49" + attribute \src "ls180.v:764.5-764.49" wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:711.5-711.44" + attribute \src "ls180.v:760.5-760.44" wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:712.5-712.43" + attribute \src "ls180.v:761.5-761.43" wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:707.5-707.38" + attribute \src "ls180.v:756.5-756.38" wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:706.5-706.38" + attribute \src "ls180.v:755.5-755.38" wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:705.5-705.40" + attribute \src "ls180.v:754.5-754.40" wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:704.6-704.41" + attribute \src "ls180.v:753.6-753.41" wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:700.13-700.45" + attribute \src "ls180.v:749.13-749.45" wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:701.6-701.38" + attribute \src "ls180.v:750.6-750.38" wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:703.5-703.44" + attribute \src "ls180.v:752.5-752.44" wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:698.6-698.39" + attribute \src "ls180.v:747.6-747.39" wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:697.6-697.39" + attribute \src "ls180.v:746.6-746.39" wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:702.5-702.44" + attribute \src "ls180.v:751.5-751.44" wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:699.6-699.36" + attribute \src "ls180.v:748.6-748.36" wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:766.12-766.39" + attribute \src "ls180.v:815.12-815.39" wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:770.5-770.38" + attribute \src "ls180.v:819.5-819.38" wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:771.5-771.47" + attribute \src "ls180.v:820.5-820.47" wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:768.6-768.37" + attribute \src "ls180.v:817.6-817.37" wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:769.5-769.37" + attribute \src "ls180.v:818.5-818.37" wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:767.5-767.39" + attribute \src "ls180.v:816.5-816.39" wire \main_sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:778.32-778.69" + attribute \src "ls180.v:827.32-827.69" wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:777.6-777.43" + attribute \src "ls180.v:826.6-826.43" wire \main_sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:776.32-776.68" + attribute \src "ls180.v:825.32-825.68" wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:775.6-775.42" + attribute \src "ls180.v:824.6-824.42" wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:774.11-774.48" + attribute \src "ls180.v:823.11-823.48" wire width 3 \main_sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:773.32-773.69" + attribute \src "ls180.v:822.32-822.69" wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:772.6-772.43" + attribute \src "ls180.v:821.6-821.43" wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:780.6-780.28" + attribute \src "ls180.v:829.6-829.28" wire \main_sdram_cas_allowed - attribute \src "ls180.v:798.6-798.30" + attribute \src "ls180.v:847.6-847.30" wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:787.13-787.48" + attribute \src "ls180.v:836.13-836.48" wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:788.12-788.48" + attribute \src "ls180.v:837.12-837.48" wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:789.5-789.42" + attribute \src "ls180.v:838.5-838.42" wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:792.6-792.46" + attribute \src "ls180.v:841.6-841.46" wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:793.6-793.47" + attribute \src "ls180.v:842.6-842.47" wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:794.6-794.48" + attribute \src "ls180.v:843.6-843.48" wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:790.5-790.42" + attribute \src "ls180.v:839.5-839.42" wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:791.5-791.41" + attribute \src "ls180.v:840.5-840.41" wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:786.5-786.36" + attribute \src "ls180.v:835.5-835.36" wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:785.6-785.37" + attribute \src "ls180.v:834.6-834.37" wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:797.11-797.38" + attribute \src "ls180.v:846.11-846.38" wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:796.12-796.41" + attribute \src "ls180.v:845.12-845.41" wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:795.11-795.39" + attribute \src "ls180.v:844.11-844.39" wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:784.5-784.41" + attribute \src "ls180.v:833.5-833.41" wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:783.5-783.36" + attribute \src "ls180.v:832.5-832.36" wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:781.5-781.37" + attribute \src "ls180.v:830.5-830.37" wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:782.5-782.38" + attribute \src "ls180.v:831.5-831.38" wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:816.6-816.30" + attribute \src "ls180.v:865.6-865.30" wire \main_sdram_choose_req_ce - attribute \src "ls180.v:805.13-805.48" + attribute \src "ls180.v:854.13-854.48" wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:806.12-806.48" + attribute \src "ls180.v:855.12-855.48" wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:807.5-807.42" + attribute \src "ls180.v:856.5-856.42" wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:810.6-810.46" + attribute \src "ls180.v:859.6-859.46" wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:811.6-811.47" + attribute \src "ls180.v:860.6-860.47" wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:812.6-812.48" + attribute \src "ls180.v:861.6-861.48" wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:808.5-808.42" + attribute \src "ls180.v:857.5-857.42" wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:809.5-809.41" + attribute \src "ls180.v:858.5-858.41" wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:804.5-804.36" + attribute \src "ls180.v:853.5-853.36" wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:803.6-803.37" + attribute \src "ls180.v:852.6-852.37" wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:815.11-815.38" + attribute \src "ls180.v:864.11-864.38" wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:814.12-814.41" + attribute \src "ls180.v:863.12-863.41" wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:813.11-813.39" + attribute \src "ls180.v:862.11-862.39" wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:802.5-802.41" + attribute \src "ls180.v:851.5-851.41" wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:801.6-801.37" + attribute \src "ls180.v:850.6-850.37" wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:799.5-799.37" + attribute \src "ls180.v:848.5-848.37" wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:800.5-800.38" + attribute \src "ls180.v:849.5-849.38" wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:360.6-360.20" + attribute \src "ls180.v:409.6-409.20" wire \main_sdram_cke - attribute \src "ls180.v:428.5-428.24" + attribute \src "ls180.v:477.5-477.24" wire \main_sdram_cmd_last - attribute \src "ls180.v:429.12-429.36" + attribute \src "ls180.v:478.12-478.36" wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:430.11-430.36" + attribute \src "ls180.v:479.11-479.36" wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:431.5-431.31" + attribute \src "ls180.v:480.5-480.31" wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:434.5-434.35" + attribute \src "ls180.v:483.5-483.35" wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:435.5-435.36" + attribute \src "ls180.v:484.5-484.36" wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:432.5-432.31" + attribute \src "ls180.v:481.5-481.31" wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:433.5-433.30" + attribute \src "ls180.v:482.5-482.30" wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:427.5-427.25" + attribute \src "ls180.v:476.5-476.25" wire \main_sdram_cmd_ready - attribute \src "ls180.v:426.5-426.25" + attribute \src "ls180.v:475.5-475.25" wire \main_sdram_cmd_valid - attribute \src "ls180.v:368.6-368.32" + attribute \src "ls180.v:417.6-417.32" wire \main_sdram_command_issue_r - attribute \src "ls180.v:367.6-367.33" + attribute \src "ls180.v:416.6-416.33" wire \main_sdram_command_issue_re - attribute \src "ls180.v:370.5-370.31" + attribute \src "ls180.v:419.5-419.31" wire \main_sdram_command_issue_w - attribute \src "ls180.v:369.6-369.33" + attribute \src "ls180.v:418.6-418.33" wire \main_sdram_command_issue_we - attribute \src "ls180.v:366.5-366.26" + attribute \src "ls180.v:415.5-415.26" wire \main_sdram_command_re - attribute \src "ls180.v:365.11-365.37" + attribute \src "ls180.v:414.11-414.37" wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:419.5-419.28" + attribute \src "ls180.v:468.5-468.28" wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:410.12-410.37" + attribute \src "ls180.v:459.12-459.37" wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:411.11-411.33" + attribute \src "ls180.v:460.11-460.33" wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:412.5-412.28" + attribute \src "ls180.v:461.5-461.28" wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:416.6-416.27" + attribute \src "ls180.v:465.6-465.27" wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:413.5-413.27" + attribute \src "ls180.v:462.5-462.27" wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:417.6-417.27" + attribute \src "ls180.v:466.6-466.27" wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:414.5-414.28" + attribute \src "ls180.v:463.5-463.28" wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:424.13-424.37" + attribute \src "ls180.v:473.13-473.37" wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:423.5-423.32" + attribute \src "ls180.v:472.5-472.32" wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:425.6-425.36" + attribute \src "ls180.v:474.6-474.36" wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:418.6-418.31" + attribute \src "ls180.v:467.6-467.31" wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:415.5-415.27" + attribute \src "ls180.v:464.5-464.27" wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:420.13-420.37" + attribute \src "ls180.v:469.13-469.37" wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:421.5-421.32" + attribute \src "ls180.v:470.5-470.32" wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:422.12-422.41" + attribute \src "ls180.v:471.12-471.41" wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:834.5-834.19" + attribute \src "ls180.v:883.5-883.19" wire \main_sdram_en0 - attribute \src "ls180.v:837.5-837.19" + attribute \src "ls180.v:886.5-886.19" wire \main_sdram_en1 - attribute \src "ls180.v:840.6-840.30" + attribute \src "ls180.v:889.6-889.30" wire \main_sdram_go_to_refresh - attribute \src "ls180.v:382.13-382.44" + attribute \src "ls180.v:431.13-431.44" wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:383.6-383.37" + attribute \src "ls180.v:432.6-432.37" wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:385.6-385.44" + attribute \src "ls180.v:434.6-434.44" wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:380.6-380.38" + attribute \src "ls180.v:429.6-429.38" wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:379.6-379.38" + attribute \src "ls180.v:428.6-428.38" wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:384.6-384.44" + attribute \src "ls180.v:433.6-433.44" wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:381.6-381.35" + attribute \src "ls180.v:430.6-430.35" wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:389.13-389.44" + attribute \src "ls180.v:438.13-438.44" wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:390.6-390.37" + attribute \src "ls180.v:439.6-439.37" wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:392.6-392.44" + attribute \src "ls180.v:441.6-441.44" wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:387.6-387.38" + attribute \src "ls180.v:436.6-436.38" wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:386.6-386.38" + attribute \src "ls180.v:435.6-435.38" wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:391.6-391.44" + attribute \src "ls180.v:440.6-440.44" wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:388.6-388.35" + attribute \src "ls180.v:437.6-437.35" wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:396.13-396.44" + attribute \src "ls180.v:445.13-445.44" wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:397.6-397.37" + attribute \src "ls180.v:446.6-446.37" wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:399.6-399.44" + attribute \src "ls180.v:448.6-448.44" wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:394.6-394.38" + attribute \src "ls180.v:443.6-443.38" wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:393.6-393.38" + attribute \src "ls180.v:442.6-442.38" wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:398.6-398.44" + attribute \src "ls180.v:447.6-447.44" wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:395.6-395.35" + attribute \src "ls180.v:444.6-444.35" wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:403.13-403.44" + attribute \src "ls180.v:452.13-452.44" wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:404.6-404.37" + attribute \src "ls180.v:453.6-453.37" wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:406.6-406.44" + attribute \src "ls180.v:455.6-455.44" wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:401.6-401.38" + attribute \src "ls180.v:450.6-450.38" wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:400.6-400.38" + attribute \src "ls180.v:449.6-449.38" wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:405.6-405.44" + attribute \src "ls180.v:454.6-454.44" wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:402.6-402.35" + attribute \src "ls180.v:451.6-451.35" wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:409.13-409.39" + attribute \src "ls180.v:458.13-458.39" wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:407.12-407.38" + attribute \src "ls180.v:456.12-456.38" wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:408.11-408.40" + attribute \src "ls180.v:457.11-457.40" wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:320.5-320.29" + attribute \src "ls180.v:369.5-369.29" wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:311.13-311.39" + attribute \src "ls180.v:360.13-360.39" wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:312.12-312.35" + attribute \src "ls180.v:361.12-361.35" wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:313.5-313.29" + attribute \src "ls180.v:362.5-362.29" wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:317.6-317.28" + attribute \src "ls180.v:366.6-366.28" wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:314.5-314.28" + attribute \src "ls180.v:363.5-363.28" wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:318.6-318.28" + attribute \src "ls180.v:367.6-367.28" wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:315.5-315.29" + attribute \src "ls180.v:364.5-364.29" wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:325.12-325.37" + attribute \src "ls180.v:374.12-374.37" wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:324.6-324.34" + attribute \src "ls180.v:373.6-373.34" wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:326.5-326.36" + attribute \src "ls180.v:375.5-375.36" wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:319.6-319.32" + attribute \src "ls180.v:368.6-368.32" wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:316.5-316.28" + attribute \src "ls180.v:365.5-365.28" wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:321.13-321.38" + attribute \src "ls180.v:370.13-370.38" wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:322.6-322.34" + attribute \src "ls180.v:371.6-371.34" wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:323.12-323.42" + attribute \src "ls180.v:372.12-372.42" wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:352.5-352.31" + attribute \src "ls180.v:401.5-401.31" wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:343.12-343.40" + attribute \src "ls180.v:392.12-392.40" wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:344.11-344.36" + attribute \src "ls180.v:393.11-393.36" wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:345.5-345.31" + attribute \src "ls180.v:394.5-394.31" wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:349.5-349.29" + attribute \src "ls180.v:398.5-398.29" wire \main_sdram_master_p0_cke - attribute \src "ls180.v:346.5-346.30" + attribute \src "ls180.v:395.5-395.30" wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:350.5-350.29" + attribute \src "ls180.v:399.5-399.29" wire \main_sdram_master_p0_odt - attribute \src "ls180.v:347.5-347.31" + attribute \src "ls180.v:396.5-396.31" wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:357.13-357.40" + attribute \src "ls180.v:406.13-406.40" wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:356.5-356.35" + attribute \src "ls180.v:405.5-405.35" wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:358.6-358.39" + attribute \src "ls180.v:407.6-407.39" wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:351.5-351.33" + attribute \src "ls180.v:400.5-400.33" wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:348.5-348.30" + attribute \src "ls180.v:397.5-397.30" wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:353.12-353.39" + attribute \src "ls180.v:402.12-402.39" wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:354.5-354.35" + attribute \src "ls180.v:403.5-403.35" wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:355.11-355.43" + attribute \src "ls180.v:404.11-404.43" wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:835.6-835.26" + attribute \src "ls180.v:884.6-884.26" wire \main_sdram_max_time0 - attribute \src "ls180.v:838.6-838.26" + attribute \src "ls180.v:887.6-887.26" wire \main_sdram_max_time1 - attribute \src "ls180.v:817.12-817.28" + attribute \src "ls180.v:866.12-866.28" wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:818.11-818.28" + attribute \src "ls180.v:867.11-867.28" wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:361.6-361.20" + attribute \src "ls180.v:410.6-410.20" wire \main_sdram_odt - attribute \src "ls180.v:444.5-444.31" + attribute \src "ls180.v:493.5-493.31" wire \main_sdram_postponer_count - attribute \src "ls180.v:442.6-442.32" + attribute \src "ls180.v:491.6-491.32" wire \main_sdram_postponer_req_i - attribute \src "ls180.v:443.5-443.31" + attribute \src "ls180.v:492.5-492.31" wire \main_sdram_postponer_req_o - attribute \src "ls180.v:779.6-779.28" + attribute \src "ls180.v:828.6-828.28" wire \main_sdram_ras_allowed - attribute \src "ls180.v:364.5-364.18" + attribute \src "ls180.v:413.5-413.18" wire \main_sdram_re - attribute \src "ls180.v:832.6-832.31" + attribute \src "ls180.v:881.6-881.31" wire \main_sdram_read_available - attribute \src "ls180.v:362.6-362.24" + attribute \src "ls180.v:411.6-411.24" wire \main_sdram_reset_n - attribute \src "ls180.v:359.6-359.20" + attribute \src "ls180.v:408.6-408.20" wire \main_sdram_sel - attribute \src "ls180.v:450.5-450.31" + attribute \src "ls180.v:499.5-499.31" wire \main_sdram_sequencer_count - attribute \src "ls180.v:449.11-449.39" + attribute \src "ls180.v:498.11-498.39" wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:446.6-446.32" + attribute \src "ls180.v:495.6-495.32" wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:448.5-448.31" + attribute \src "ls180.v:497.5-497.31" wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:445.5-445.32" + attribute \src "ls180.v:494.5-494.32" wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:447.6-447.33" + attribute \src "ls180.v:496.6-496.33" wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:336.6-336.31" + attribute \src "ls180.v:385.6-385.31" wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:327.13-327.40" + attribute \src "ls180.v:376.13-376.40" wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:328.12-328.36" + attribute \src "ls180.v:377.12-377.36" wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:329.6-329.31" + attribute \src "ls180.v:378.6-378.31" wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:333.6-333.29" + attribute \src "ls180.v:382.6-382.29" wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:330.6-330.30" + attribute \src "ls180.v:379.6-379.30" wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:334.6-334.29" + attribute \src "ls180.v:383.6-383.29" wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:331.6-331.31" + attribute \src "ls180.v:380.6-380.31" wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:341.12-341.38" + attribute \src "ls180.v:390.12-390.38" wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:340.6-340.35" + attribute \src "ls180.v:389.6-389.35" wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:342.5-342.37" + attribute \src "ls180.v:391.5-391.37" wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:335.6-335.33" + attribute \src "ls180.v:384.6-384.33" wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:332.6-332.30" + attribute \src "ls180.v:381.6-381.30" wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:337.13-337.39" + attribute \src "ls180.v:386.13-386.39" wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:338.6-338.35" + attribute \src "ls180.v:387.6-387.35" wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:339.12-339.43" + attribute \src "ls180.v:388.12-388.43" wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:377.12-377.29" + attribute \src "ls180.v:426.12-426.29" wire width 16 \main_sdram_status - attribute \src "ls180.v:820.5-820.24" + attribute \src "ls180.v:869.5-869.24" wire \main_sdram_steerer0 - attribute \src "ls180.v:821.5-821.24" + attribute \src "ls180.v:870.5-870.24" wire \main_sdram_steerer1 - attribute \src "ls180.v:819.11-819.33" + attribute \src "ls180.v:868.11-868.33" wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:363.11-363.29" + attribute \src "ls180.v:412.11-412.29" wire width 4 \main_sdram_storage - attribute \src "ls180.v:828.5-828.29" + attribute \src "ls180.v:877.5-877.29" wire \main_sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:827.32-827.56" + attribute \src "ls180.v:876.32-876.56" wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:826.6-826.30" + attribute \src "ls180.v:875.6-875.30" wire \main_sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:825.32-825.56" + attribute \src "ls180.v:874.32-874.56" wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:824.6-824.30" + attribute \src "ls180.v:873.6-873.30" wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:836.11-836.27" + attribute \src "ls180.v:885.11-885.27" wire width 5 \main_sdram_time0 - attribute \src "ls180.v:839.11-839.27" + attribute \src "ls180.v:888.11-888.27" wire width 4 \main_sdram_time1 - attribute \src "ls180.v:439.12-439.35" + attribute \src "ls180.v:488.12-488.35" wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:441.11-441.34" + attribute \src "ls180.v:490.11-490.34" wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:438.6-438.28" + attribute \src "ls180.v:487.6-487.28" wire \main_sdram_timer_done0 - attribute \src "ls180.v:440.6-440.28" + attribute \src "ls180.v:489.6-489.28" wire \main_sdram_timer_done1 - attribute \src "ls180.v:437.6-437.27" + attribute \src "ls180.v:486.6-486.27" wire \main_sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:823.32-823.56" + attribute \src "ls180.v:872.32-872.56" wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:822.6-822.30" + attribute \src "ls180.v:871.6-871.30" wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:831.11-831.35" + attribute \src "ls180.v:880.11-880.35" wire width 3 \main_sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:830.32-830.56" + attribute \src "ls180.v:879.32-879.56" wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:829.6-829.30" + attribute \src "ls180.v:878.6-878.30" wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:436.6-436.30" + attribute \src "ls180.v:485.6-485.30" wire \main_sdram_wants_refresh - attribute \src "ls180.v:378.6-378.19" + attribute \src "ls180.v:427.6-427.19" wire \main_sdram_we - attribute \src "ls180.v:376.5-376.25" + attribute \src "ls180.v:425.5-425.25" wire \main_sdram_wrdata_re - attribute \src "ls180.v:375.12-375.37" + attribute \src "ls180.v:424.12-424.37" wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:833.6-833.32" + attribute \src "ls180.v:882.6-882.32" wire \main_sdram_write_available - attribute \src "ls180.v:1033.6-1033.27" + attribute \src "ls180.v:917.5-917.47" + wire \main_socbushandler_converted_interface_ack + attribute \src "ls180.v:911.13-911.55" + wire width 30 \main_socbushandler_converted_interface_adr + attribute \src "ls180.v:920.12-920.54" + wire width 2 \main_socbushandler_converted_interface_bte + attribute \src "ls180.v:919.12-919.54" + wire width 3 \main_socbushandler_converted_interface_cti + attribute \src "ls180.v:915.6-915.48" + wire \main_socbushandler_converted_interface_cyc + attribute \src "ls180.v:913.13-913.57" + wire width 64 \main_socbushandler_converted_interface_dat_r + attribute \src "ls180.v:912.13-912.57" + wire width 64 \main_socbushandler_converted_interface_dat_w + attribute \src "ls180.v:921.5-921.47" + wire \main_socbushandler_converted_interface_err + attribute \src "ls180.v:914.12-914.54" + wire width 8 \main_socbushandler_converted_interface_sel + attribute \src "ls180.v:916.6-916.48" + wire \main_socbushandler_converted_interface_stb + attribute \src "ls180.v:918.6-918.47" + wire \main_socbushandler_converted_interface_we + attribute \src "ls180.v:923.5-923.31" + wire \main_socbushandler_counter + attribute \src "ls180.v:1852.5-1852.53" + wire \main_socbushandler_counter_converter2_next_value + attribute \src "ls180.v:1853.5-1853.56" + wire \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:925.12-925.36" + wire width 64 \main_socbushandler_dat_r + attribute \src "ls180.v:924.6-924.30" + wire \main_socbushandler_reset + attribute \src "ls180.v:922.5-922.28" + wire \main_socbushandler_skip + attribute \src "ls180.v:1100.6-1100.27" wire \main_spimaster0_start - attribute \src "ls180.v:1043.12-1043.35" + attribute \src "ls180.v:1110.12-1110.35" wire width 8 \main_spimaster10_length - attribute \src "ls180.v:1044.12-1044.36" + attribute \src "ls180.v:1111.12-1111.36" wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1045.5-1045.24" + attribute \src "ls180.v:1112.5-1112.24" wire \main_spimaster12_re - attribute \src "ls180.v:1046.6-1046.27" + attribute \src "ls180.v:1113.6-1113.27" wire \main_spimaster13_done - attribute \src "ls180.v:1047.6-1047.29" + attribute \src "ls180.v:1114.6-1114.29" wire \main_spimaster14_status - attribute \src "ls180.v:1048.6-1048.25" + attribute \src "ls180.v:1115.6-1115.25" wire \main_spimaster15_we - attribute \src "ls180.v:1049.11-1049.35" + attribute \src "ls180.v:1116.11-1116.35" wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1050.5-1050.24" + attribute \src "ls180.v:1117.5-1117.24" wire \main_spimaster17_re - attribute \src "ls180.v:1051.12-1051.35" + attribute \src "ls180.v:1118.12-1118.35" wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1052.6-1052.25" + attribute \src "ls180.v:1119.6-1119.25" wire \main_spimaster19_we - attribute \src "ls180.v:1034.12-1034.34" + attribute \src "ls180.v:1101.12-1101.34" wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1106.5-1106.23" + attribute \src "ls180.v:1173.5-1173.23" wire \main_spimaster1_re - attribute \src "ls180.v:1105.12-1105.35" + attribute \src "ls180.v:1172.12-1172.35" wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1053.6-1053.26" + attribute \src "ls180.v:1120.6-1120.26" wire \main_spimaster20_sel - attribute \src "ls180.v:1054.5-1054.29" + attribute \src "ls180.v:1121.5-1121.29" wire \main_spimaster21_storage - attribute \src "ls180.v:1055.5-1055.24" + attribute \src "ls180.v:1122.5-1122.24" wire \main_spimaster22_re - attribute \src "ls180.v:1056.5-1056.29" + attribute \src "ls180.v:1123.5-1123.29" wire \main_spimaster23_storage - attribute \src "ls180.v:1057.5-1057.24" + attribute \src "ls180.v:1124.5-1124.24" wire \main_spimaster24_re - attribute \src "ls180.v:1058.5-1058.32" + attribute \src "ls180.v:1125.5-1125.32" wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1059.5-1059.31" + attribute \src "ls180.v:1126.5-1126.31" wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1060.11-1060.33" + attribute \src "ls180.v:1127.11-1127.33" wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1826.11-1826.55" + attribute \src "ls180.v:1893.11-1893.55" wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1827.5-1827.52" + attribute \src "ls180.v:1894.5-1894.52" wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1061.5-1061.32" + attribute \src "ls180.v:1128.5-1128.32" wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1062.5-1062.32" + attribute \src "ls180.v:1129.5-1129.32" wire \main_spimaster29_miso_latch - attribute \src "ls180.v:1035.5-1035.25" + attribute \src "ls180.v:1102.5-1102.25" wire \main_spimaster2_done - attribute \src "ls180.v:1063.12-1063.40" + attribute \src "ls180.v:1130.12-1130.40" wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1064.6-1064.31" + attribute \src "ls180.v:1131.6-1131.31" wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1065.6-1065.31" + attribute \src "ls180.v:1132.6-1132.31" wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1066.11-1066.37" + attribute \src "ls180.v:1133.11-1133.37" wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1067.11-1067.36" + attribute \src "ls180.v:1134.11-1134.36" wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1068.11-1068.37" + attribute \src "ls180.v:1135.11-1135.37" wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:1036.5-1036.24" + attribute \src "ls180.v:1103.5-1103.24" wire \main_spimaster3_irq - attribute \src "ls180.v:1037.12-1037.32" + attribute \src "ls180.v:1104.12-1104.32" wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:1038.11-1038.31" + attribute \src "ls180.v:1105.11-1105.31" wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:1039.6-1039.24" + attribute \src "ls180.v:1106.6-1106.24" wire \main_spimaster6_cs - attribute \src "ls180.v:1040.6-1040.30" + attribute \src "ls180.v:1107.6-1107.30" wire \main_spimaster7_loopback - attribute \src "ls180.v:1041.12-1041.39" + attribute \src "ls180.v:1108.12-1108.39" wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:1042.5-1042.26" + attribute \src "ls180.v:1109.5-1109.26" wire \main_spimaster9_start - attribute \src "ls180.v:1077.13-1077.40" + attribute \src "ls180.v:1144.13-1144.40" wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1099.12-1099.39" + attribute \src "ls180.v:1166.12-1166.39" wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1094.5-1094.30" + attribute \src "ls180.v:1161.5-1161.30" wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1101.6-1101.29" + attribute \src "ls180.v:1168.6-1168.29" wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1100.6-1100.29" + attribute \src "ls180.v:1167.6-1167.29" wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1081.5-1081.30" + attribute \src "ls180.v:1148.5-1148.30" wire \main_spisdcard_control_re - attribute \src "ls180.v:1080.12-1080.42" + attribute \src "ls180.v:1147.12-1147.42" wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1096.11-1096.31" + attribute \src "ls180.v:1163.11-1163.31" wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1830.11-1830.53" + attribute \src "ls180.v:1897.11-1897.53" wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1831.5-1831.50" + attribute \src "ls180.v:1898.5-1898.50" wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1075.6-1075.23" + attribute \src "ls180.v:1142.6-1142.23" wire \main_spisdcard_cs - attribute \src "ls180.v:1095.5-1095.29" + attribute \src "ls180.v:1162.5-1162.29" wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1091.5-1091.25" + attribute \src "ls180.v:1158.5-1158.25" wire \main_spisdcard_cs_re - attribute \src "ls180.v:1090.5-1090.30" + attribute \src "ls180.v:1157.5-1157.30" wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1071.5-1071.25" + attribute \src "ls180.v:1138.5-1138.25" wire \main_spisdcard_done0 - attribute \src "ls180.v:1082.6-1082.26" + attribute \src "ls180.v:1149.6-1149.26" wire \main_spisdcard_done1 - attribute \src "ls180.v:1072.5-1072.23" + attribute \src "ls180.v:1139.5-1139.23" wire \main_spisdcard_irq - attribute \src "ls180.v:1070.12-1070.34" + attribute \src "ls180.v:1137.12-1137.34" wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1079.12-1079.34" + attribute \src "ls180.v:1146.12-1146.34" wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1076.6-1076.29" + attribute \src "ls180.v:1143.6-1143.29" wire \main_spisdcard_loopback - attribute \src "ls180.v:1093.5-1093.31" + attribute \src "ls180.v:1160.5-1160.31" wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1092.5-1092.36" + attribute \src "ls180.v:1159.5-1159.36" wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1074.11-1074.30" + attribute \src "ls180.v:1141.11-1141.30" wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1104.11-1104.35" + attribute \src "ls180.v:1171.11-1171.35" wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1098.5-1098.30" + attribute \src "ls180.v:1165.5-1165.30" wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1087.12-1087.38" + attribute \src "ls180.v:1154.12-1154.38" wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1088.6-1088.28" + attribute \src "ls180.v:1155.6-1155.28" wire \main_spisdcard_miso_we - attribute \src "ls180.v:1073.12-1073.31" + attribute \src "ls180.v:1140.12-1140.31" wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1102.11-1102.35" + attribute \src "ls180.v:1169.11-1169.35" wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1097.5-1097.30" + attribute \src "ls180.v:1164.5-1164.30" wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1086.5-1086.27" + attribute \src "ls180.v:1153.5-1153.27" wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1103.11-1103.34" + attribute \src "ls180.v:1170.11-1170.34" wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1085.11-1085.38" + attribute \src "ls180.v:1152.11-1152.38" wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1089.6-1089.24" + attribute \src "ls180.v:1156.6-1156.24" wire \main_spisdcard_sel - attribute \src "ls180.v:1069.6-1069.27" + attribute \src "ls180.v:1136.6-1136.27" wire \main_spisdcard_start0 - attribute \src "ls180.v:1078.5-1078.26" + attribute \src "ls180.v:1145.5-1145.26" wire \main_spisdcard_start1 - attribute \src "ls180.v:1083.6-1083.34" + attribute \src "ls180.v:1150.6-1150.34" wire \main_spisdcard_status_status - attribute \src "ls180.v:1084.6-1084.30" + attribute \src "ls180.v:1151.6-1151.30" wire \main_spisdcard_status_we - attribute \src "ls180.v:256.12-256.26" - wire width 7 \main_sram0_adr - attribute \src "ls180.v:257.13-257.29" - wire width 32 \main_sram0_dat_r - attribute \src "ls180.v:259.13-259.29" - wire width 32 \main_sram0_dat_w - attribute \src "ls180.v:258.11-258.24" - wire width 4 \main_sram0_we - attribute \src "ls180.v:271.12-271.26" - wire width 7 \main_sram1_adr - attribute \src "ls180.v:272.13-272.29" - wire width 32 \main_sram1_dat_r - attribute \src "ls180.v:274.13-274.29" - wire width 32 \main_sram1_dat_w - attribute \src "ls180.v:273.11-273.24" - wire width 4 \main_sram1_we - attribute \src "ls180.v:286.12-286.26" - wire width 7 \main_sram2_adr - attribute \src "ls180.v:287.13-287.29" - wire width 32 \main_sram2_dat_r - attribute \src "ls180.v:289.13-289.29" - wire width 32 \main_sram2_dat_w - attribute \src "ls180.v:288.11-288.24" - wire width 4 \main_sram2_we - attribute \src "ls180.v:930.12-930.44" + attribute \src "ls180.v:260.12-260.26" + wire width 6 \main_sram0_adr + attribute \src "ls180.v:261.13-261.29" + wire width 64 \main_sram0_dat_r + attribute \src "ls180.v:263.13-263.29" + wire width 64 \main_sram0_dat_w + attribute \src "ls180.v:262.11-262.24" + wire width 8 \main_sram0_we + attribute \src "ls180.v:275.12-275.26" + wire width 6 \main_sram1_adr + attribute \src "ls180.v:276.13-276.29" + wire width 64 \main_sram1_dat_r + attribute \src "ls180.v:278.13-278.29" + wire width 64 \main_sram1_dat_w + attribute \src "ls180.v:277.11-277.24" + wire width 8 \main_sram1_we + attribute \src "ls180.v:290.12-290.26" + wire width 6 \main_sram2_adr + attribute \src "ls180.v:291.13-291.29" + wire width 64 \main_sram2_dat_r + attribute \src "ls180.v:293.13-293.29" + wire width 64 \main_sram2_dat_w + attribute \src "ls180.v:292.11-292.24" + wire width 8 \main_sram2_we + attribute \src "ls180.v:305.12-305.26" + wire width 6 \main_sram3_adr + attribute \src "ls180.v:306.13-306.29" + wire width 64 \main_sram3_dat_r + attribute \src "ls180.v:308.13-308.29" + wire width 64 \main_sram3_dat_w + attribute \src "ls180.v:307.11-307.24" + wire width 8 \main_sram3_we + attribute \src "ls180.v:991.12-991.44" wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:929.6-929.39" + attribute \src "ls180.v:990.6-990.39" wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:932.11-932.43" + attribute \src "ls180.v:993.11-993.43" wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:931.6-931.39" + attribute \src "ls180.v:992.6-992.39" wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:934.5-934.30" + attribute \src "ls180.v:995.5-995.30" wire \main_uart_eventmanager_re - attribute \src "ls180.v:926.12-926.43" + attribute \src "ls180.v:987.12-987.43" wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:925.6-925.38" + attribute \src "ls180.v:986.6-986.38" wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:928.11-928.42" + attribute \src "ls180.v:989.11-989.42" wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:927.6-927.38" + attribute \src "ls180.v:988.6-988.38" wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:933.11-933.41" + attribute \src "ls180.v:994.11-994.41" wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:914.6-914.19" + attribute \src "ls180.v:975.6-975.19" wire \main_uart_irq - attribute \src "ls180.v:900.12-900.46" + attribute \src "ls180.v:961.12-961.46" wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:890.12-890.46" + attribute \src "ls180.v:951.12-951.46" wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:883.5-883.21" + attribute \src "ls180.v:944.5-944.21" wire \main_uart_phy_re - attribute \src "ls180.v:901.6-901.22" + attribute \src "ls180.v:962.6-962.22" wire \main_uart_phy_rx - attribute \src "ls180.v:904.11-904.36" + attribute \src "ls180.v:965.11-965.36" wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:905.5-905.26" + attribute \src "ls180.v:966.5-966.26" wire \main_uart_phy_rx_busy - attribute \src "ls180.v:902.5-902.23" + attribute \src "ls180.v:963.5-963.23" wire \main_uart_phy_rx_r - attribute \src "ls180.v:903.11-903.31" + attribute \src "ls180.v:964.11-964.31" wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:886.6-886.30" + attribute \src "ls180.v:947.6-947.30" wire \main_uart_phy_sink_first - attribute \src "ls180.v:887.6-887.29" + attribute \src "ls180.v:948.6-948.29" wire \main_uart_phy_sink_last - attribute \src "ls180.v:888.12-888.43" + attribute \src "ls180.v:949.12-949.43" wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:885.5-885.29" + attribute \src "ls180.v:946.5-946.29" wire \main_uart_phy_sink_ready - attribute \src "ls180.v:884.6-884.30" + attribute \src "ls180.v:945.6-945.30" wire \main_uart_phy_sink_valid - attribute \src "ls180.v:896.5-896.31" + attribute \src "ls180.v:957.5-957.31" wire \main_uart_phy_source_first - attribute \src "ls180.v:897.5-897.30" + attribute \src "ls180.v:958.5-958.30" wire \main_uart_phy_source_last - attribute \src "ls180.v:898.11-898.44" + attribute \src "ls180.v:959.11-959.44" wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:895.6-895.32" + attribute \src "ls180.v:956.6-956.32" wire \main_uart_phy_source_ready - attribute \src "ls180.v:894.5-894.31" + attribute \src "ls180.v:955.5-955.31" wire \main_uart_phy_source_valid - attribute \src "ls180.v:882.12-882.33" + attribute \src "ls180.v:943.12-943.33" wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:892.11-892.36" + attribute \src "ls180.v:953.11-953.36" wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:893.5-893.26" + attribute \src "ls180.v:954.5-954.26" wire \main_uart_phy_tx_busy - attribute \src "ls180.v:891.11-891.31" + attribute \src "ls180.v:952.11-952.31" wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:899.5-899.32" + attribute \src "ls180.v:960.5-960.32" wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:889.5-889.32" + attribute \src "ls180.v:950.5-950.32" wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:1023.5-1023.20" + attribute \src "ls180.v:1084.5-1084.20" wire \main_uart_reset - attribute \src "ls180.v:923.5-923.23" + attribute \src "ls180.v:984.5-984.23" wire \main_uart_rx_clear - attribute \src "ls180.v:1007.11-1007.36" + attribute \src "ls180.v:1068.11-1068.36" wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:1012.6-1012.31" + attribute \src "ls180.v:1073.6-1073.31" wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:1018.6-1018.37" + attribute \src "ls180.v:1079.6-1079.37" wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:1019.6-1019.36" + attribute \src "ls180.v:1080.6-1080.36" wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:1017.12-1017.50" + attribute \src "ls180.v:1078.12-1078.50" wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1021.6-1021.38" + attribute \src "ls180.v:1082.6-1082.38" wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:1022.6-1022.37" + attribute \src "ls180.v:1083.6-1083.37" wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:1020.12-1020.51" + attribute \src "ls180.v:1081.12-1081.51" wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1004.11-1004.35" + attribute \src "ls180.v:1065.11-1065.35" wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:1016.12-1016.36" + attribute \src "ls180.v:1077.12-1077.36" wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:1006.11-1006.36" + attribute \src "ls180.v:1067.11-1067.36" wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:1013.12-1013.40" + attribute \src "ls180.v:1074.12-1074.40" wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:1014.12-1014.42" + attribute \src "ls180.v:1075.12-1075.42" wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:1015.6-1015.33" + attribute \src "ls180.v:1076.6-1076.33" wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:996.6-996.26" + attribute \src "ls180.v:1057.6-1057.26" wire \main_uart_rx_fifo_re - attribute \src "ls180.v:997.5-997.31" + attribute \src "ls180.v:1058.5-1058.31" wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:1005.5-1005.30" + attribute \src "ls180.v:1066.5-1066.30" wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:988.6-988.34" + attribute \src "ls180.v:1049.6-1049.34" wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:989.6-989.33" + attribute \src "ls180.v:1050.6-1050.33" wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:990.12-990.47" + attribute \src "ls180.v:1051.12-1051.47" wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:987.6-987.34" + attribute \src "ls180.v:1048.6-1048.34" wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:986.6-986.34" + attribute \src "ls180.v:1047.6-1047.34" wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:993.6-993.36" + attribute \src "ls180.v:1054.6-1054.36" wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:994.6-994.35" + attribute \src "ls180.v:1055.6-1055.35" wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:995.12-995.49" + attribute \src "ls180.v:1056.12-1056.49" wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:992.6-992.36" + attribute \src "ls180.v:1053.6-1053.36" wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:991.6-991.36" + attribute \src "ls180.v:1052.6-1052.36" wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:1002.12-1002.42" + attribute \src "ls180.v:1063.12-1063.42" wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:1003.12-1003.43" + attribute \src "ls180.v:1064.12-1064.43" wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:1000.6-1000.35" + attribute \src "ls180.v:1061.6-1061.35" wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:1001.6-1001.41" + attribute \src "ls180.v:1062.6-1062.41" wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:998.6-998.35" + attribute \src "ls180.v:1059.6-1059.35" wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:999.6-999.41" + attribute \src "ls180.v:1060.6-1060.41" wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:1008.11-1008.39" + attribute \src "ls180.v:1069.11-1069.39" wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:1009.12-1009.42" + attribute \src "ls180.v:1070.12-1070.42" wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:1011.12-1011.42" + attribute \src "ls180.v:1072.12-1072.42" wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:1010.6-1010.33" + attribute \src "ls180.v:1071.6-1071.33" wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:924.5-924.29" + attribute \src "ls180.v:985.5-985.29" wire \main_uart_rx_old_trigger - attribute \src "ls180.v:921.5-921.25" + attribute \src "ls180.v:982.5-982.25" wire \main_uart_rx_pending - attribute \src "ls180.v:920.6-920.25" + attribute \src "ls180.v:981.6-981.25" wire \main_uart_rx_status - attribute \src "ls180.v:922.6-922.26" + attribute \src "ls180.v:983.6-983.26" wire \main_uart_rx_trigger - attribute \src "ls180.v:912.6-912.30" + attribute \src "ls180.v:973.6-973.30" wire \main_uart_rxempty_status - attribute \src "ls180.v:913.6-913.26" + attribute \src "ls180.v:974.6-974.26" wire \main_uart_rxempty_we - attribute \src "ls180.v:937.6-937.29" + attribute \src "ls180.v:998.6-998.29" wire \main_uart_rxfull_status - attribute \src "ls180.v:938.6-938.25" + attribute \src "ls180.v:999.6-999.25" wire \main_uart_rxfull_we - attribute \src "ls180.v:907.12-907.28" + attribute \src "ls180.v:968.12-968.28" wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:906.6-906.23" + attribute \src "ls180.v:967.6-967.23" wire \main_uart_rxtx_re - attribute \src "ls180.v:909.12-909.28" + attribute \src "ls180.v:970.12-970.28" wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:908.6-908.23" + attribute \src "ls180.v:969.6-969.23" wire \main_uart_rxtx_we - attribute \src "ls180.v:918.5-918.23" + attribute \src "ls180.v:979.5-979.23" wire \main_uart_tx_clear - attribute \src "ls180.v:970.11-970.36" + attribute \src "ls180.v:1031.11-1031.36" wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:975.6-975.31" + attribute \src "ls180.v:1036.6-1036.31" wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:981.6-981.37" + attribute \src "ls180.v:1042.6-1042.37" wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:982.6-982.36" + attribute \src "ls180.v:1043.6-1043.36" wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:980.12-980.50" + attribute \src "ls180.v:1041.12-1041.50" wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:984.6-984.38" + attribute \src "ls180.v:1045.6-1045.38" wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:985.6-985.37" + attribute \src "ls180.v:1046.6-1046.37" wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:983.12-983.51" + attribute \src "ls180.v:1044.12-1044.51" wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:967.11-967.35" + attribute \src "ls180.v:1028.11-1028.35" wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:979.12-979.36" + attribute \src "ls180.v:1040.12-1040.36" wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:969.11-969.36" + attribute \src "ls180.v:1030.11-1030.36" wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:976.12-976.40" + attribute \src "ls180.v:1037.12-1037.40" wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:977.12-977.42" + attribute \src "ls180.v:1038.12-1038.42" wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:978.6-978.33" + attribute \src "ls180.v:1039.6-1039.33" wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:959.6-959.26" + attribute \src "ls180.v:1020.6-1020.26" wire \main_uart_tx_fifo_re - attribute \src "ls180.v:960.5-960.31" + attribute \src "ls180.v:1021.5-1021.31" wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:968.5-968.30" + attribute \src "ls180.v:1029.5-1029.30" wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:951.5-951.33" + attribute \src "ls180.v:1012.5-1012.33" wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:952.5-952.32" + attribute \src "ls180.v:1013.5-1013.32" wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:953.12-953.47" + attribute \src "ls180.v:1014.12-1014.47" wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:950.6-950.34" + attribute \src "ls180.v:1011.6-1011.34" wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:949.6-949.34" + attribute \src "ls180.v:1010.6-1010.34" wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:956.6-956.36" + attribute \src "ls180.v:1017.6-1017.36" wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:957.6-957.35" + attribute \src "ls180.v:1018.6-1018.35" wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:958.12-958.49" + attribute \src "ls180.v:1019.12-1019.49" wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:955.6-955.36" + attribute \src "ls180.v:1016.6-1016.36" wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:954.6-954.36" + attribute \src "ls180.v:1015.6-1015.36" wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:965.12-965.42" + attribute \src "ls180.v:1026.12-1026.42" wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:966.12-966.43" + attribute \src "ls180.v:1027.12-1027.43" wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:963.6-963.35" + attribute \src "ls180.v:1024.6-1024.35" wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:964.6-964.41" + attribute \src "ls180.v:1025.6-1025.41" wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:961.6-961.35" + attribute \src "ls180.v:1022.6-1022.35" wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:962.6-962.41" + attribute \src "ls180.v:1023.6-1023.41" wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:971.11-971.39" + attribute \src "ls180.v:1032.11-1032.39" wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:972.12-972.42" + attribute \src "ls180.v:1033.12-1033.42" wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:974.12-974.42" + attribute \src "ls180.v:1035.12-1035.42" wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:973.6-973.33" + attribute \src "ls180.v:1034.6-1034.33" wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:919.5-919.29" + attribute \src "ls180.v:980.5-980.29" wire \main_uart_tx_old_trigger - attribute \src "ls180.v:916.5-916.25" + attribute \src "ls180.v:977.5-977.25" wire \main_uart_tx_pending - attribute \src "ls180.v:915.6-915.25" + attribute \src "ls180.v:976.6-976.25" wire \main_uart_tx_status - attribute \src "ls180.v:917.6-917.26" + attribute \src "ls180.v:978.6-978.26" wire \main_uart_tx_trigger - attribute \src "ls180.v:935.6-935.30" + attribute \src "ls180.v:996.6-996.30" wire \main_uart_txempty_status - attribute \src "ls180.v:936.6-936.26" + attribute \src "ls180.v:997.6-997.26" wire \main_uart_txempty_we - attribute \src "ls180.v:910.6-910.29" + attribute \src "ls180.v:971.6-971.29" wire \main_uart_txfull_status - attribute \src "ls180.v:911.6-911.25" + attribute \src "ls180.v:972.6-972.25" wire \main_uart_txfull_we - attribute \src "ls180.v:941.6-941.31" + attribute \src "ls180.v:1002.6-1002.31" wire \main_uart_uart_sink_first - attribute \src "ls180.v:942.6-942.30" + attribute \src "ls180.v:1003.6-1003.30" wire \main_uart_uart_sink_last - attribute \src "ls180.v:943.12-943.44" + attribute \src "ls180.v:1004.12-1004.44" wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:940.6-940.31" + attribute \src "ls180.v:1001.6-1001.31" wire \main_uart_uart_sink_ready - attribute \src "ls180.v:939.6-939.31" + attribute \src "ls180.v:1000.6-1000.31" wire \main_uart_uart_sink_valid - attribute \src "ls180.v:946.6-946.33" + attribute \src "ls180.v:1007.6-1007.33" wire \main_uart_uart_source_first - attribute \src "ls180.v:947.6-947.32" + attribute \src "ls180.v:1008.6-1008.32" wire \main_uart_uart_source_last - attribute \src "ls180.v:948.12-948.46" + attribute \src "ls180.v:1009.12-1009.46" wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:945.6-945.33" + attribute \src "ls180.v:1006.6-1006.33" wire \main_uart_uart_source_ready - attribute \src "ls180.v:944.6-944.33" + attribute \src "ls180.v:1005.6-1005.33" wire \main_uart_uart_source_valid - attribute \src "ls180.v:860.5-860.22" + attribute \src "ls180.v:909.5-909.22" wire \main_wb_sdram_ack - attribute \src "ls180.v:854.13-854.30" + attribute \src "ls180.v:903.12-903.29" wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:863.12-863.29" - wire width 2 \main_wb_sdram_bte - attribute \src "ls180.v:862.12-862.29" - wire width 3 \main_wb_sdram_cti - attribute \src "ls180.v:858.6-858.23" + attribute \src "ls180.v:907.5-907.22" wire \main_wb_sdram_cyc - attribute \src "ls180.v:856.13-856.32" + attribute \src "ls180.v:905.13-905.32" wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:855.13-855.32" + attribute \src "ls180.v:904.12-904.31" wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:864.5-864.22" - wire \main_wb_sdram_err - attribute \src "ls180.v:857.12-857.29" + attribute \src "ls180.v:906.11-906.28" wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:859.6-859.23" + attribute \src "ls180.v:908.5-908.22" wire \main_wb_sdram_stb - attribute \src "ls180.v:861.6-861.22" + attribute \src "ls180.v:910.5-910.21" wire \main_wb_sdram_we - attribute \src "ls180.v:878.5-878.24" + attribute \src "ls180.v:939.5-939.24" wire \main_wdata_consumed - attribute \src "ls180.v:10159.11-10159.17" - wire width 7 \memadr - attribute \src "ls180.v:10179.11-10179.19" - wire width 7 \memadr_1 - attribute \src "ls180.v:10199.11-10199.19" - wire width 7 \memadr_2 - attribute \src "ls180.v:10219.11-10219.19" - wire width 7 \memadr_3 - attribute \src "ls180.v:10239.12-10239.18" + attribute \src "ls180.v:10352.11-10352.17" + wire width 6 \memadr + attribute \src "ls180.v:10380.11-10380.19" + wire width 6 \memadr_1 + attribute \src "ls180.v:10408.11-10408.19" + wire width 6 \memadr_2 + attribute \src "ls180.v:10436.11-10436.19" + wire width 6 \memadr_3 + attribute \src "ls180.v:10464.11-10464.19" + wire width 6 \memadr_4 + attribute \src "ls180.v:10492.12-10492.18" wire width 25 \memdat - attribute \src "ls180.v:10253.12-10253.20" + attribute \src "ls180.v:10506.12-10506.20" wire width 25 \memdat_1 - attribute \src "ls180.v:10267.12-10267.20" + attribute \src "ls180.v:10520.12-10520.20" wire width 25 \memdat_2 - attribute \src "ls180.v:10281.12-10281.20" + attribute \src "ls180.v:10534.12-10534.20" wire width 25 \memdat_3 - attribute \src "ls180.v:10295.11-10295.19" + attribute \src "ls180.v:10548.11-10548.19" wire width 10 \memdat_4 - attribute \src "ls180.v:10296.11-10296.19" + attribute \src "ls180.v:10549.11-10549.19" wire width 10 \memdat_5 - attribute \src "ls180.v:10312.11-10312.19" + attribute \src "ls180.v:10565.11-10565.19" wire width 10 \memdat_6 - attribute \src "ls180.v:10313.11-10313.19" + attribute \src "ls180.v:10566.11-10566.19" wire width 10 \memdat_7 - attribute \src "ls180.v:10329.11-10329.19" + attribute \src "ls180.v:10582.11-10582.19" wire width 10 \memdat_8 - attribute \src "ls180.v:10343.11-10343.19" + attribute \src "ls180.v:10596.11-10596.19" wire width 10 \memdat_9 attribute \src "ls180.v:52.20-52.22" wire width 24 input 48 \nc - attribute \src "ls180.v:292.6-292.13" + attribute \src "ls180.v:341.6-341.13" wire \por_clk - attribute \src "ls180.v:42.19-42.22" - wire width 2 output 38 \pwm - attribute \src "ls180.v:157.12-157.17" + attribute \src "ls180.v:29.19-29.22" + wire width 2 output 25 \pwm + attribute \src "ls180.v:193.12-193.17" wire width 2 \pwm_1 - attribute \src "ls180.v:35.13-35.23" - wire output 31 \sdcard_clk - attribute \src "ls180.v:36.13-36.25" - wire input 32 \sdcard_cmd_i - attribute \src "ls180.v:37.13-37.25" - wire output 33 \sdcard_cmd_o - attribute \src "ls180.v:38.13-38.26" - wire output 34 \sdcard_cmd_oe - attribute \src "ls180.v:39.19-39.32" - wire width 4 input 35 \sdcard_data_i - attribute \src "ls180.v:40.19-40.32" - wire width 4 output 36 \sdcard_data_o - attribute \src "ls180.v:41.13-41.27" - wire output 37 \sdcard_data_oe - attribute \src "ls180.v:5.20-5.27" - wire width 13 output 1 \sdram_a - attribute \src "ls180.v:14.19-14.27" - wire width 2 output 10 \sdram_ba - attribute \src "ls180.v:11.13-11.24" - wire output 7 \sdram_cas_n - attribute \src "ls180.v:13.13-13.22" - wire output 9 \sdram_cke - attribute \src "ls180.v:16.13-16.24" - wire output 12 \sdram_clock - attribute \src "ls180.v:136.6-136.19" + attribute \src "ls180.v:5.13-5.23" + wire output 1 \sdcard_clk + attribute \src "ls180.v:6.14-6.26" + wire output 2 \sdcard_cmd_i + attribute \src "ls180.v:7.13-7.25" + wire output 3 \sdcard_cmd_o + attribute \src "ls180.v:8.13-8.26" + wire output 4 \sdcard_cmd_oe + attribute \src "ls180.v:9.20-9.33" + wire width 4 output 5 \sdcard_data_i + attribute \src "ls180.v:10.19-10.32" + wire width 4 output 6 \sdcard_data_o + attribute \src "ls180.v:11.13-11.27" + wire output 7 \sdcard_data_oe + attribute \src "ls180.v:30.20-30.27" + wire width 13 output 26 \sdram_a + attribute \src "ls180.v:39.19-39.27" + wire width 2 output 35 \sdram_ba + attribute \src "ls180.v:36.13-36.24" + wire output 32 \sdram_cas_n + attribute \src "ls180.v:38.13-38.22" + wire output 34 \sdram_cke + attribute \src "ls180.v:41.13-41.24" + wire output 37 \sdram_clock + attribute \src "ls180.v:205.6-205.19" wire \sdram_clock_1 - attribute \src "ls180.v:12.13-12.23" - wire output 8 \sdram_cs_n - attribute \src "ls180.v:15.19-15.27" - wire width 2 output 11 \sdram_dm - attribute \src "ls180.v:6.20-6.30" - wire width 16 input 2 \sdram_dq_i - attribute \src "ls180.v:7.20-7.30" - wire width 16 output 3 \sdram_dq_o - attribute \src "ls180.v:8.13-8.24" - wire output 4 \sdram_dq_oe - attribute \src "ls180.v:10.13-10.24" - wire output 6 \sdram_ras_n - attribute \src "ls180.v:9.13-9.23" - wire output 5 \sdram_we_n - attribute \src "ls180.v:2688.6-2688.15" + attribute \src "ls180.v:37.13-37.23" + wire output 33 \sdram_cs_n + attribute \src "ls180.v:40.19-40.27" + wire width 2 output 36 \sdram_dm + attribute \src "ls180.v:31.21-31.31" + wire width 16 output 27 \sdram_dq_i + attribute \src "ls180.v:32.20-32.30" + wire width 16 output 28 \sdram_dq_o + attribute \src "ls180.v:33.13-33.24" + wire output 29 \sdram_dq_oe + attribute \src "ls180.v:35.13-35.24" + wire output 31 \sdram_ras_n + attribute \src "ls180.v:34.13-34.23" + wire output 30 \sdram_we_n + attribute \src "ls180.v:2763.6-2763.15" wire \sdrio_clk - attribute \src "ls180.v:2689.6-2689.17" + attribute \src "ls180.v:2764.6-2764.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2698.6-2698.18" + attribute \src "ls180.v:2773.6-2773.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2699.6-2699.18" + attribute \src "ls180.v:2774.6-2774.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2700.6-2700.18" + attribute \src "ls180.v:2775.6-2775.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2701.6-2701.18" + attribute \src "ls180.v:2776.6-2776.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2702.6-2702.18" + attribute \src "ls180.v:2777.6-2777.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2703.6-2703.18" + attribute \src "ls180.v:2778.6-2778.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2704.6-2704.18" + attribute \src "ls180.v:2779.6-2779.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2705.6-2705.18" + attribute \src "ls180.v:2780.6-2780.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2706.6-2706.18" + attribute \src "ls180.v:2781.6-2781.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2707.6-2707.18" + attribute \src "ls180.v:2782.6-2782.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2690.6-2690.17" + attribute \src "ls180.v:2765.6-2765.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2708.6-2708.18" + attribute \src "ls180.v:2783.6-2783.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2709.6-2709.18" + attribute \src "ls180.v:2784.6-2784.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2710.6-2710.18" + attribute \src "ls180.v:2785.6-2785.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2711.6-2711.18" + attribute \src "ls180.v:2786.6-2786.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2712.6-2712.18" + attribute \src "ls180.v:2787.6-2787.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2713.6-2713.18" + attribute \src "ls180.v:2788.6-2788.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2714.6-2714.18" + attribute \src "ls180.v:2789.6-2789.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2715.6-2715.18" + attribute \src "ls180.v:2790.6-2790.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2716.6-2716.18" + attribute \src "ls180.v:2791.6-2791.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2717.6-2717.18" + attribute \src "ls180.v:2792.6-2792.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2691.6-2691.17" + attribute \src "ls180.v:2766.6-2766.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2718.6-2718.18" + attribute \src "ls180.v:2793.6-2793.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2719.6-2719.18" + attribute \src "ls180.v:2794.6-2794.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2720.6-2720.18" + attribute \src "ls180.v:2795.6-2795.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2721.6-2721.18" + attribute \src "ls180.v:2796.6-2796.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2722.6-2722.18" + attribute \src "ls180.v:2797.6-2797.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2723.6-2723.18" + attribute \src "ls180.v:2798.6-2798.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2724.6-2724.18" + attribute \src "ls180.v:2799.6-2799.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2725.6-2725.18" + attribute \src "ls180.v:2800.6-2800.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2726.6-2726.18" + attribute \src "ls180.v:2801.6-2801.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2727.6-2727.18" + attribute \src "ls180.v:2802.6-2802.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2692.6-2692.17" + attribute \src "ls180.v:2767.6-2767.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2728.6-2728.18" + attribute \src "ls180.v:2803.6-2803.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2729.6-2729.18" + attribute \src "ls180.v:2804.6-2804.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2730.6-2730.18" + attribute \src "ls180.v:2805.6-2805.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2731.6-2731.18" + attribute \src "ls180.v:2806.6-2806.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2732.6-2732.18" + attribute \src "ls180.v:2807.6-2807.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2733.6-2733.18" + attribute \src "ls180.v:2808.6-2808.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2734.6-2734.18" + attribute \src "ls180.v:2809.6-2809.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2735.6-2735.18" + attribute \src "ls180.v:2810.6-2810.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2736.6-2736.18" + attribute \src "ls180.v:2811.6-2811.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2737.6-2737.18" + attribute \src "ls180.v:2812.6-2812.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2693.6-2693.17" + attribute \src "ls180.v:2768.6-2768.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2738.6-2738.18" + attribute \src "ls180.v:2813.6-2813.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2739.6-2739.18" + attribute \src "ls180.v:2814.6-2814.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2740.6-2740.18" + attribute \src "ls180.v:2815.6-2815.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2741.6-2741.18" + attribute \src "ls180.v:2816.6-2816.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2742.6-2742.18" + attribute \src "ls180.v:2817.6-2817.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2743.6-2743.18" + attribute \src "ls180.v:2818.6-2818.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2778.6-2778.18" + attribute \src "ls180.v:2853.6-2853.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2779.6-2779.18" + attribute \src "ls180.v:2854.6-2854.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2780.6-2780.18" + attribute \src "ls180.v:2855.6-2855.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2781.6-2781.18" + attribute \src "ls180.v:2856.6-2856.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2694.6-2694.17" + attribute \src "ls180.v:2769.6-2769.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2782.6-2782.18" + attribute \src "ls180.v:2857.6-2857.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2783.6-2783.18" + attribute \src "ls180.v:2858.6-2858.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2784.6-2784.18" + attribute \src "ls180.v:2859.6-2859.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2785.6-2785.18" + attribute \src "ls180.v:2860.6-2860.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2786.6-2786.18" + attribute \src "ls180.v:2861.6-2861.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2787.6-2787.18" + attribute \src "ls180.v:2862.6-2862.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2788.6-2788.18" + attribute \src "ls180.v:2863.6-2863.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2789.6-2789.18" + attribute \src "ls180.v:2864.6-2864.18" wire \sdrio_clk_67 - attribute \src "ls180.v:2790.6-2790.18" + attribute \src "ls180.v:2865.6-2865.18" wire \sdrio_clk_68 - attribute \src "ls180.v:2695.6-2695.17" + attribute \src "ls180.v:2770.6-2770.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2696.6-2696.17" + attribute \src "ls180.v:2771.6-2771.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2697.6-2697.17" + attribute \src "ls180.v:2772.6-2772.17" wire \sdrio_clk_9 - attribute \src "ls180.v:24.13-24.26" - wire output 20 \spimaster_clk - attribute \src "ls180.v:26.13-26.27" - wire output 22 \spimaster_cs_n - attribute \src "ls180.v:27.13-27.27" - wire input 23 \spimaster_miso - attribute \src "ls180.v:25.13-25.27" - wire output 21 \spimaster_mosi - attribute \src "ls180.v:20.13-20.26" - wire output 16 \spisdcard_clk - attribute \src "ls180.v:22.13-22.27" - wire output 18 \spisdcard_cs_n + attribute \src "ls180.v:21.13-21.26" + wire output 17 \spimaster_clk attribute \src "ls180.v:23.13-23.27" - wire input 19 \spisdcard_miso - attribute \src "ls180.v:21.13-21.27" - wire output 17 \spisdcard_mosi + wire output 19 \spimaster_cs_n + attribute \src "ls180.v:24.13-24.27" + wire input 20 \spimaster_miso + attribute \src "ls180.v:22.13-22.27" + wire output 18 \spimaster_mosi + attribute \src "ls180.v:25.13-25.26" + wire output 21 \spisdcard_clk + attribute \src "ls180.v:27.13-27.27" + wire output 23 \spisdcard_cs_n + attribute \src "ls180.v:28.13-28.27" + wire input 24 \spisdcard_miso + attribute \src "ls180.v:26.13-26.27" + wire output 22 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk - attribute \src "ls180.v:290.6-290.15" + attribute \src "ls180.v:339.6-339.15" wire \sys_clk_1 attribute \src "ls180.v:45.19-45.31" wire width 2 input 41 \sys_clksel_i @@ -235491,71 +252046,73 @@ module \ls180 wire output 43 \sys_pll_lck_o attribute \src "ls180.v:44.13-44.20" wire input 40 \sys_rst - attribute \src "ls180.v:291.6-291.15" + attribute \src "ls180.v:340.6-340.15" wire \sys_rst_1 - attribute \src "ls180.v:18.13-18.20" - wire input 14 \uart_rx - attribute \src "ls180.v:17.13-17.20" - wire output 13 \uart_tx - attribute \src "ls180.v:10158.12-10158.15" - memory width 32 size 128 \mem - attribute \src "ls180.v:10178.12-10178.17" - memory width 32 size 128 \mem_1 - attribute \src "ls180.v:10198.12-10198.17" - memory width 32 size 128 \mem_2 - attribute \src "ls180.v:10218.12-10218.17" - memory width 32 size 128 \mem_3 - attribute \src "ls180.v:10238.12-10238.19" + attribute \src "ls180.v:13.13-13.20" + wire input 9 \uart_rx + attribute \src "ls180.v:12.13-12.20" + wire output 8 \uart_tx + attribute \src "ls180.v:10351.12-10351.15" + memory width 64 size 64 \mem + attribute \src "ls180.v:10379.12-10379.17" + memory width 64 size 64 \mem_1 + attribute \src "ls180.v:10407.12-10407.17" + memory width 64 size 64 \mem_2 + attribute \src "ls180.v:10435.12-10435.17" + memory width 64 size 64 \mem_3 + attribute \src "ls180.v:10463.12-10463.17" + memory width 64 size 64 \mem_4 + attribute \src "ls180.v:10491.12-10491.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10252.12-10252.21" + attribute \src "ls180.v:10505.12-10505.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10266.12-10266.21" + attribute \src "ls180.v:10519.12-10519.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10280.12-10280.21" + attribute \src "ls180.v:10533.12-10533.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10294.11-10294.20" + attribute \src "ls180.v:10547.11-10547.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10311.11-10311.20" + attribute \src "ls180.v:10564.11-10564.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10328.11-10328.20" + attribute \src "ls180.v:10581.11-10581.20" memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10342.11-10342.20" + attribute \src "ls180.v:10595.11-10595.20" memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2860.68-2860.110" - cell $add $add$ls180.v:2860$34 + attribute \src "ls180.v:2935.56-2935.86" + cell $add $add$ls180.v:2935$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter + connect \A \main_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2860$34_Y + connect \Y $add$ls180.v:2935$58_Y end - attribute \src "ls180.v:2920.68-2920.110" - cell $add $add$ls180.v:2920$45 + attribute \src "ls180.v:2995.56-2995.86" + cell $add $add$ls180.v:2995$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter + connect \A \main_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2920$45_Y + connect \Y $add$ls180.v:2995$69_Y end - attribute \src "ls180.v:2980.68-2980.110" - cell $add $add$ls180.v:2980$56 + attribute \src "ls180.v:3055.59-3055.92" + cell $add $add$ls180.v:3055$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter + connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $add$ls180.v:2980$56_Y + connect \Y $add$ls180.v:3055$80_Y end - attribute \src "ls180.v:4143.54-4143.83" - cell $add $add$ls180.v:4143$588 + attribute \src "ls180.v:4248.54-4248.83" + cell $add $add$ls180.v:4248$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235563,10 +252120,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4143$588_Y + connect \Y $add$ls180.v:4248$685_Y end - attribute \src "ls180.v:4243.36-4243.89" - cell $add $add$ls180.v:4243$634 + attribute \src "ls180.v:4348.36-4348.89" + cell $add $add$ls180.v:4348$731 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235574,10 +252131,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4243$634_Y + connect \Y $add$ls180.v:4348$731_Y end - attribute \src "ls180.v:4273.36-4273.89" - cell $add $add$ls180.v:4273$645 + attribute \src "ls180.v:4378.36-4378.89" + cell $add $add$ls180.v:4378$742 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235585,10 +252142,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4273$645_Y + connect \Y $add$ls180.v:4378$742_Y end - attribute \src "ls180.v:4328.54-4328.83" - cell $add $add$ls180.v:4328$658 + attribute \src "ls180.v:4444.54-4444.83" + cell $add $add$ls180.v:4444$757 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235596,10 +252153,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster27_count connect \B 1'1 - connect \Y $add$ls180.v:4328$658_Y + connect \Y $add$ls180.v:4444$757_Y end - attribute \src "ls180.v:4387.52-4387.79" - cell $add $add$ls180.v:4387$666 + attribute \src "ls180.v:4503.52-4503.79" + cell $add $add$ls180.v:4503$765 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235607,10 +252164,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_count connect \B 1'1 - connect \Y $add$ls180.v:4387$666_Y + connect \Y $add$ls180.v:4503$765_Y end - attribute \src "ls180.v:4491.58-4491.86" - cell $add $add$ls180.v:4491$694 + attribute \src "ls180.v:4607.58-4607.86" + cell $add $add$ls180.v:4607$793 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235618,10 +252175,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_init_count connect \B 1'1 - connect \Y $add$ls180.v:4491$694_Y + connect \Y $add$ls180.v:4607$793_Y end - attribute \src "ls180.v:4548.58-4548.86" - cell $add $add$ls180.v:4548$697 + attribute \src "ls180.v:4664.58-4664.86" + cell $add $add$ls180.v:4664$796 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235629,10 +252186,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4548$697_Y + connect \Y $add$ls180.v:4664$796_Y end - attribute \src "ls180.v:4565.58-4565.86" - cell $add $add$ls180.v:4565$699 + attribute \src "ls180.v:4681.58-4681.86" + cell $add $add$ls180.v:4681$798 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235640,10 +252197,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4565$699_Y + connect \Y $add$ls180.v:4681$798_Y end - attribute \src "ls180.v:4658.59-4658.87" - cell $add $add$ls180.v:4658$716 + attribute \src "ls180.v:4774.59-4774.87" + cell $add $add$ls180.v:4774$815 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235651,10 +252208,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4658$716_Y + connect \Y $add$ls180.v:4774$815_Y end - attribute \src "ls180.v:4683.59-4683.87" - cell $add $add$ls180.v:4683$719 + attribute \src "ls180.v:4799.59-4799.87" + cell $add $add$ls180.v:4799$818 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235662,10 +252219,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4683$719_Y + connect \Y $add$ls180.v:4799$818_Y end - attribute \src "ls180.v:4805.53-4805.82" - cell $add $add$ls180.v:4805$736 + attribute \src "ls180.v:4921.53-4921.82" + cell $add $add$ls180.v:4921$835 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235673,10 +252230,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $add$ls180.v:4805$736_Y + connect \Y $add$ls180.v:4921$835_Y end - attribute \src "ls180.v:4916.65-4916.114" - cell $add $add$ls180.v:4916$750 + attribute \src "ls180.v:5032.65-5032.114" + cell $add $add$ls180.v:5032$849 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235684,10 +252241,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_sink_payload_block_length connect \B 4'1000 - connect \Y $add$ls180.v:4916$750_Y + connect \Y $add$ls180.v:5032$849_Y end - attribute \src "ls180.v:4921.62-4921.91" - cell $add $add$ls180.v:4921$753 + attribute \src "ls180.v:5037.62-5037.91" + cell $add $add$ls180.v:5037$852 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235695,10 +252252,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4921$753_Y + connect \Y $add$ls180.v:5037$852_Y end - attribute \src "ls180.v:4947.61-4947.90" - cell $add $add$ls180.v:4947$756 + attribute \src "ls180.v:5063.61-5063.90" + cell $add $add$ls180.v:5063$855 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235706,10 +252263,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4947$756_Y + connect \Y $add$ls180.v:5063$855_Y end - attribute \src "ls180.v:5151.80-5151.117" - cell $add $add$ls180.v:5151$941 + attribute \src "ls180.v:5267.80-5267.117" + cell $add $add$ls180.v:5267$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235717,10 +252274,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_crc16_inserter_cnt connect \B 1'1 - connect \Y $add$ls180.v:5151$941_Y + connect \Y $add$ls180.v:5267$1040_Y end - attribute \src "ls180.v:5345.54-5345.82" - cell $add $add$ls180.v:5345$1016 + attribute \src "ls180.v:5461.54-5461.82" + cell $add $add$ls180.v:5461$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235728,10 +252285,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_cmd_count connect \B 1'1 - connect \Y $add$ls180.v:5345$1016_Y + connect \Y $add$ls180.v:5461$1115_Y end - attribute \src "ls180.v:5397.55-5397.84" - cell $add $add$ls180.v:5397$1026 + attribute \src "ls180.v:5513.55-5513.84" + cell $add $add$ls180.v:5513$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235739,10 +252296,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5397$1026_Y + connect \Y $add$ls180.v:5513$1125_Y end - attribute \src "ls180.v:5423.57-5423.86" - cell $add $add$ls180.v:5423$1034 + attribute \src "ls180.v:5539.57-5539.86" + cell $add $add$ls180.v:5539$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235750,10 +252307,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5423$1034_Y + connect \Y $add$ls180.v:5539$1133_Y end - attribute \src "ls180.v:5544.51-5544.134" - cell $add $add$ls180.v:5544$1050 + attribute \src "ls180.v:5660.51-5660.134" + cell $add $add$ls180.v:5660$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235761,10 +252318,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_base connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5544$1050_Y + connect \Y $add$ls180.v:5660$1149_Y end - attribute \src "ls180.v:5547.77-5547.125" - cell $add $add$ls180.v:5547$1052 + attribute \src "ls180.v:5663.77-5663.125" + cell $add $add$ls180.v:5663$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235772,10 +252329,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_offset connect \B 1'1 - connect \Y $add$ls180.v:5547$1052_Y + connect \Y $add$ls180.v:5663$1151_Y end - attribute \src "ls180.v:5640.50-5640.105" - cell $add $add$ls180.v:5640$1061 + attribute \src "ls180.v:5756.50-5756.105" + cell $add $add$ls180.v:5756$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235783,10 +252340,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_base connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5640$1061_Y + connect \Y $add$ls180.v:5756$1160_Y end - attribute \src "ls180.v:5642.77-5642.111" - cell $add $add$ls180.v:5642$1062 + attribute \src "ls180.v:5758.77-5758.111" + cell $add $add$ls180.v:5758$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235794,10 +252351,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_offset connect \B 1'1 - connect \Y $add$ls180.v:5642$1062_Y + connect \Y $add$ls180.v:5758$1161_Y end - attribute \src "ls180.v:7589.36-7589.70" - cell $add $add$ls180.v:7589$2472 + attribute \src "ls180.v:7765.36-7765.70" + cell $add $add$ls180.v:7765$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235805,10 +252362,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7589$2472_Y + connect \Y $add$ls180.v:7765$2602_Y end - attribute \src "ls180.v:7686.37-7686.72" - cell $add $add$ls180.v:7686$2502 + attribute \src "ls180.v:7866.37-7866.72" + cell $add $add$ls180.v:7866$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235816,10 +252373,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7686$2502_Y + connect \Y $add$ls180.v:7866$2635_Y end - attribute \src "ls180.v:7703.60-7703.119" - cell $add $add$ls180.v:7703$2506 + attribute \src "ls180.v:7883.60-7883.119" + cell $add $add$ls180.v:7883$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235827,10 +252384,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7703$2506_Y + connect \Y $add$ls180.v:7883$2639_Y end - attribute \src "ls180.v:7706.60-7706.119" - cell $add $add$ls180.v:7706$2507 + attribute \src "ls180.v:7886.60-7886.119" + cell $add $add$ls180.v:7886$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235838,10 +252395,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7706$2507_Y + connect \Y $add$ls180.v:7886$2640_Y end - attribute \src "ls180.v:7710.59-7710.116" - cell $add $add$ls180.v:7710$2512 + attribute \src "ls180.v:7890.59-7890.116" + cell $add $add$ls180.v:7890$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235849,10 +252406,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7710$2512_Y + connect \Y $add$ls180.v:7890$2645_Y end - attribute \src "ls180.v:7749.60-7749.119" - cell $add $add$ls180.v:7749$2522 + attribute \src "ls180.v:7929.60-7929.119" + cell $add $add$ls180.v:7929$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235860,10 +252417,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7749$2522_Y + connect \Y $add$ls180.v:7929$2655_Y end - attribute \src "ls180.v:7752.60-7752.119" - cell $add $add$ls180.v:7752$2523 + attribute \src "ls180.v:7932.60-7932.119" + cell $add $add$ls180.v:7932$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235871,10 +252428,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7752$2523_Y + connect \Y $add$ls180.v:7932$2656_Y end - attribute \src "ls180.v:7756.59-7756.116" - cell $add $add$ls180.v:7756$2528 + attribute \src "ls180.v:7936.59-7936.116" + cell $add $add$ls180.v:7936$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235882,10 +252439,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7756$2528_Y + connect \Y $add$ls180.v:7936$2661_Y end - attribute \src "ls180.v:7795.60-7795.119" - cell $add $add$ls180.v:7795$2538 + attribute \src "ls180.v:7975.60-7975.119" + cell $add $add$ls180.v:7975$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235893,10 +252450,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7795$2538_Y + connect \Y $add$ls180.v:7975$2671_Y end - attribute \src "ls180.v:7798.60-7798.119" - cell $add $add$ls180.v:7798$2539 + attribute \src "ls180.v:7978.60-7978.119" + cell $add $add$ls180.v:7978$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235904,10 +252461,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7798$2539_Y + connect \Y $add$ls180.v:7978$2672_Y end - attribute \src "ls180.v:7802.59-7802.116" - cell $add $add$ls180.v:7802$2544 + attribute \src "ls180.v:7982.59-7982.116" + cell $add $add$ls180.v:7982$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235915,10 +252472,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7802$2544_Y + connect \Y $add$ls180.v:7982$2677_Y end - attribute \src "ls180.v:7841.60-7841.119" - cell $add $add$ls180.v:7841$2554 + attribute \src "ls180.v:8021.60-8021.119" + cell $add $add$ls180.v:8021$2687 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235926,10 +252483,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7841$2554_Y + connect \Y $add$ls180.v:8021$2687_Y end - attribute \src "ls180.v:7844.60-7844.119" - cell $add $add$ls180.v:7844$2555 + attribute \src "ls180.v:8024.60-8024.119" + cell $add $add$ls180.v:8024$2688 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235937,10 +252494,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7844$2555_Y + connect \Y $add$ls180.v:8024$2688_Y end - attribute \src "ls180.v:7848.59-7848.116" - cell $add $add$ls180.v:7848$2560 + attribute \src "ls180.v:8028.59-8028.116" + cell $add $add$ls180.v:8028$2693 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235948,10 +252505,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7848$2560_Y + connect \Y $add$ls180.v:8028$2693_Y end - attribute \src "ls180.v:8078.34-8078.66" - cell $add $add$ls180.v:8078$2614 + attribute \src "ls180.v:8258.34-8258.66" + cell $add $add$ls180.v:8258$2747 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235959,10 +252516,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8078$2614_Y + connect \Y $add$ls180.v:8258$2747_Y end - attribute \src "ls180.v:8094.73-8094.131" - cell $add $add$ls180.v:8094$2617 + attribute \src "ls180.v:8274.73-8274.131" + cell $add $add$ls180.v:8274$2750 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235970,10 +252527,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_tx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8094$2617_Y + connect \Y $add$ls180.v:8274$2750_Y end - attribute \src "ls180.v:8107.34-8107.66" - cell $add $add$ls180.v:8107$2621 + attribute \src "ls180.v:8287.34-8287.66" + cell $add $add$ls180.v:8287$2754 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235981,10 +252538,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8107$2621_Y + connect \Y $add$ls180.v:8287$2754_Y end - attribute \src "ls180.v:8126.73-8126.131" - cell $add $add$ls180.v:8126$2624 + attribute \src "ls180.v:8306.73-8306.131" + cell $add $add$ls180.v:8306$2757 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235992,10 +252549,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_rx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8126$2624_Y + connect \Y $add$ls180.v:8306$2757_Y end - attribute \src "ls180.v:8152.33-8152.65" - cell $add $add$ls180.v:8152$2632 + attribute \src "ls180.v:8332.33-8332.65" + cell $add $add$ls180.v:8332$2765 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236003,10 +252560,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8152$2632_Y + connect \Y $add$ls180.v:8332$2765_Y end - attribute \src "ls180.v:8155.33-8155.65" - cell $add $add$ls180.v:8155$2633 + attribute \src "ls180.v:8335.33-8335.65" + cell $add $add$ls180.v:8335$2766 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236014,10 +252571,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8155$2633_Y + connect \Y $add$ls180.v:8335$2766_Y end - attribute \src "ls180.v:8159.33-8159.64" - cell $add $add$ls180.v:8159$2638 + attribute \src "ls180.v:8339.33-8339.64" + cell $add $add$ls180.v:8339$2771 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236025,10 +252582,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8159$2638_Y + connect \Y $add$ls180.v:8339$2771_Y end - attribute \src "ls180.v:8174.33-8174.65" - cell $add $add$ls180.v:8174$2643 + attribute \src "ls180.v:8354.33-8354.65" + cell $add $add$ls180.v:8354$2776 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236036,10 +252593,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8174$2643_Y + connect \Y $add$ls180.v:8354$2776_Y end - attribute \src "ls180.v:8177.33-8177.65" - cell $add $add$ls180.v:8177$2644 + attribute \src "ls180.v:8357.33-8357.65" + cell $add $add$ls180.v:8357$2777 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236047,10 +252604,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8177$2644_Y + connect \Y $add$ls180.v:8357$2777_Y end - attribute \src "ls180.v:8181.33-8181.64" - cell $add $add$ls180.v:8181$2649 + attribute \src "ls180.v:8361.33-8361.64" + cell $add $add$ls180.v:8361$2782 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236058,10 +252615,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8181$2649_Y + connect \Y $add$ls180.v:8361$2782_Y end - attribute \src "ls180.v:8202.35-8202.70" - cell $add $add$ls180.v:8202$2651 + attribute \src "ls180.v:8382.35-8382.70" + cell $add $add$ls180.v:8382$2784 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -236069,10 +252626,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster30_clk_divider connect \B 1'1 - connect \Y $add$ls180.v:8202$2651_Y + connect \Y $add$ls180.v:8382$2784_Y end - attribute \src "ls180.v:8237.34-8237.68" - cell $add $add$ls180.v:8237$2656 + attribute \src "ls180.v:8417.34-8417.68" + cell $add $add$ls180.v:8417$2789 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -236080,10 +252637,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8237$2656_Y + connect \Y $add$ls180.v:8417$2789_Y end - attribute \src "ls180.v:8273.25-8273.49" - cell $add $add$ls180.v:8273$2661 + attribute \src "ls180.v:8453.25-8453.49" + cell $add $add$ls180.v:8453$2794 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -236091,10 +252648,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8273$2661_Y + connect \Y $add$ls180.v:8453$2794_Y end - attribute \src "ls180.v:8287.25-8287.49" - cell $add $add$ls180.v:8287$2665 + attribute \src "ls180.v:8467.25-8467.49" + cell $add $add$ls180.v:8467$2798 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -236102,10 +252659,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8287$2665_Y + connect \Y $add$ls180.v:8467$2798_Y end - attribute \src "ls180.v:8301.31-8301.61" - cell $add $add$ls180.v:8301$2670 + attribute \src "ls180.v:8481.31-8481.61" + cell $add $add$ls180.v:8481$2803 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -236113,10 +252670,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8301$2670_Y + connect \Y $add$ls180.v:8481$2803_Y end - attribute \src "ls180.v:8324.45-8324.88" - cell $add $add$ls180.v:8324$2674 + attribute \src "ls180.v:8504.45-8504.88" + cell $add $add$ls180.v:8504$2807 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -236124,10 +252681,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8324$2674_Y + connect \Y $add$ls180.v:8504$2807_Y end - attribute \src "ls180.v:8370.71-8370.114" - cell $add $add$ls180.v:8370$2680 + attribute \src "ls180.v:8550.71-8550.114" + cell $add $add$ls180.v:8550$2813 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -236135,10 +252692,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8370$2680_Y + connect \Y $add$ls180.v:8550$2813_Y end - attribute \src "ls180.v:8405.46-8405.90" - cell $add $add$ls180.v:8405$2686 + attribute \src "ls180.v:8585.46-8585.90" + cell $add $add$ls180.v:8585$2819 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -236146,10 +252703,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8405$2686_Y + connect \Y $add$ls180.v:8585$2819_Y end - attribute \src "ls180.v:8451.72-8451.116" - cell $add $add$ls180.v:8451$2692 + attribute \src "ls180.v:8631.72-8631.116" + cell $add $add$ls180.v:8631$2825 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -236157,10 +252714,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8451$2692_Y + connect \Y $add$ls180.v:8631$2825_Y end - attribute \src "ls180.v:8484.47-8484.92" - cell $add $add$ls180.v:8484$2698 + attribute \src "ls180.v:8664.47-8664.92" + cell $add $add$ls180.v:8664$2831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236168,10 +252725,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8484$2698_Y + connect \Y $add$ls180.v:8664$2831_Y end - attribute \src "ls180.v:8512.73-8512.118" - cell $add $add$ls180.v:8512$2704 + attribute \src "ls180.v:8692.73-8692.118" + cell $add $add$ls180.v:8692$2837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236179,10 +252736,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8512$2704_Y + connect \Y $add$ls180.v:8692$2837_Y end - attribute \src "ls180.v:8624.39-8624.75" - cell $add $add$ls180.v:8624$2717 + attribute \src "ls180.v:8804.39-8804.75" + cell $add $add$ls180.v:8804$2850 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236190,10 +252747,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8624$2717_Y + connect \Y $add$ls180.v:8804$2850_Y end - attribute \src "ls180.v:8685.37-8685.73" - cell $add $add$ls180.v:8685$2721 + attribute \src "ls180.v:8865.37-8865.73" + cell $add $add$ls180.v:8865$2854 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236201,10 +252758,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8685$2721_Y + connect \Y $add$ls180.v:8865$2854_Y end - attribute \src "ls180.v:8688.37-8688.73" - cell $add $add$ls180.v:8688$2722 + attribute \src "ls180.v:8868.37-8868.73" + cell $add $add$ls180.v:8868$2855 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236212,10 +252769,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8688$2722_Y + connect \Y $add$ls180.v:8868$2855_Y end - attribute \src "ls180.v:8692.36-8692.70" - cell $add $add$ls180.v:8692$2727 + attribute \src "ls180.v:8872.36-8872.70" + cell $add $add$ls180.v:8872$2860 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -236223,43 +252780,43 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8692$2727_Y + connect \Y $add$ls180.v:8872$2860_Y end - attribute \src "ls180.v:8707.41-8707.80" - cell $add $add$ls180.v:8707$2731 + attribute \src "ls180.v:8887.41-8887.80" + cell $add $add$ls180.v:8887$2864 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 + parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8707$2731_Y + connect \Y $add$ls180.v:8887$2864_Y end - attribute \src "ls180.v:8741.67-8741.106" - cell $add $add$ls180.v:8741$2737 + attribute \src "ls180.v:8933.67-8933.106" + cell $add $add$ls180.v:8933$2870 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 + parameter \Y_WIDTH 4 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8741$2737_Y + connect \Y $add$ls180.v:8933$2870_Y end - attribute \src "ls180.v:8767.39-8767.76" - cell $add $add$ls180.v:8767$2739 + attribute \src "ls180.v:8959.39-8959.76" + cell $add $add$ls180.v:8959$2872 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 + parameter \Y_WIDTH 3 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8767$2739_Y + connect \Y $add$ls180.v:8959$2872_Y end - attribute \src "ls180.v:8771.37-8771.73" - cell $add $add$ls180.v:8771$2743 + attribute \src "ls180.v:8963.37-8963.73" + cell $add $add$ls180.v:8963$2876 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236267,10 +252824,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8771$2743_Y + connect \Y $add$ls180.v:8963$2876_Y end - attribute \src "ls180.v:8774.37-8774.73" - cell $add $add$ls180.v:8774$2744 + attribute \src "ls180.v:8966.37-8966.73" + cell $add $add$ls180.v:8966$2877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236278,10 +252835,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8774$2744_Y + connect \Y $add$ls180.v:8966$2877_Y end - attribute \src "ls180.v:8778.36-8778.70" - cell $add $add$ls180.v:8778$2749 + attribute \src "ls180.v:8970.36-8970.70" + cell $add $add$ls180.v:8970$2882 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -236289,76 +252846,76 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8778$2749_Y + connect \Y $add$ls180.v:8970$2882_Y end - attribute \src "ls180.v:2854.9-2854.80" - cell $and $and$ls180.v:2854$29 + attribute \src "ls180.v:2929.9-2929.90" + cell $and $and$ls180.v:2929$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2854$29_Y + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2929$53_Y end - attribute \src "ls180.v:2872.9-2872.80" - cell $and $and$ls180.v:2872$36 + attribute \src "ls180.v:2947.9-2947.90" + cell $and $and$ls180.v:2947$60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2872$36_Y + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2947$60_Y end - attribute \src "ls180.v:2914.9-2914.80" - cell $and $and$ls180.v:2914$40 + attribute \src "ls180.v:2989.9-2989.90" + cell $and $and$ls180.v:2989$64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2914$40_Y + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2989$64_Y end - attribute \src "ls180.v:2932.9-2932.80" - cell $and $and$ls180.v:2932$47 + attribute \src "ls180.v:3007.9-3007.90" + cell $and $and$ls180.v:3007$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2932$47_Y + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:3007$71_Y end - attribute \src "ls180.v:2974.9-2974.86" - cell $and $and$ls180.v:2974$51 + attribute \src "ls180.v:3049.9-3049.96" + cell $and $and$ls180.v:3049$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2974$51_Y + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3049$75_Y end - attribute \src "ls180.v:2992.9-2992.86" - cell $and $and$ls180.v:2992$58 + attribute \src "ls180.v:3067.9-3067.96" + cell $and $and$ls180.v:3067$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2992$58_Y + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3067$82_Y end - attribute \src "ls180.v:3002.31-3002.90" - cell $and $and$ls180.v:3002$60 + attribute \src "ls180.v:3077.31-3077.90" + cell $and $and$ls180.v:3077$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236366,32 +252923,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3002$60_Y + connect \Y $and$ls180.v:3077$84_Y end - attribute \src "ls180.v:3002.30-3002.121" - cell $and $and$ls180.v:3002$61 + attribute \src "ls180.v:3077.30-3077.121" + cell $and $and$ls180.v:3077$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3002$60_Y + connect \A $and$ls180.v:3077$84_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3002$61_Y + connect \Y $and$ls180.v:3077$85_Y end - attribute \src "ls180.v:3002.29-3002.156" - cell $and $and$ls180.v:3002$62 + attribute \src "ls180.v:3077.29-3077.156" + cell $and $and$ls180.v:3077$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3002$61_Y + connect \A $and$ls180.v:3077$85_Y connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:3002$62_Y + connect \Y $and$ls180.v:3077$86_Y end - attribute \src "ls180.v:3003.31-3003.90" - cell $and $and$ls180.v:3003$63 + attribute \src "ls180.v:3078.31-3078.90" + cell $and $and$ls180.v:3078$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236399,32 +252956,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3003$63_Y + connect \Y $and$ls180.v:3078$87_Y end - attribute \src "ls180.v:3003.30-3003.121" - cell $and $and$ls180.v:3003$64 + attribute \src "ls180.v:3078.30-3078.121" + cell $and $and$ls180.v:3078$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3003$63_Y + connect \A $and$ls180.v:3078$87_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3003$64_Y + connect \Y $and$ls180.v:3078$88_Y end - attribute \src "ls180.v:3003.29-3003.156" - cell $and $and$ls180.v:3003$65 + attribute \src "ls180.v:3078.29-3078.156" + cell $and $and$ls180.v:3078$89 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3003$64_Y + connect \A $and$ls180.v:3078$88_Y connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:3003$65_Y + connect \Y $and$ls180.v:3078$89_Y end - attribute \src "ls180.v:3004.31-3004.90" - cell $and $and$ls180.v:3004$66 + attribute \src "ls180.v:3079.31-3079.90" + cell $and $and$ls180.v:3079$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236432,32 +252989,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3004$66_Y + connect \Y $and$ls180.v:3079$90_Y end - attribute \src "ls180.v:3004.30-3004.121" - cell $and $and$ls180.v:3004$67 + attribute \src "ls180.v:3079.30-3079.121" + cell $and $and$ls180.v:3079$91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3004$66_Y + connect \A $and$ls180.v:3079$90_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3004$67_Y + connect \Y $and$ls180.v:3079$91_Y end - attribute \src "ls180.v:3004.29-3004.156" - cell $and $and$ls180.v:3004$68 + attribute \src "ls180.v:3079.29-3079.156" + cell $and $and$ls180.v:3079$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3004$67_Y + connect \A $and$ls180.v:3079$91_Y connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:3004$68_Y + connect \Y $and$ls180.v:3079$92_Y end - attribute \src "ls180.v:3005.31-3005.90" - cell $and $and$ls180.v:3005$69 + attribute \src "ls180.v:3080.31-3080.90" + cell $and $and$ls180.v:3080$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236465,32 +253022,164 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3005$69_Y + connect \Y $and$ls180.v:3080$93_Y end - attribute \src "ls180.v:3005.30-3005.121" - cell $and $and$ls180.v:3005$70 + attribute \src "ls180.v:3080.30-3080.121" + cell $and $and$ls180.v:3080$94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3005$69_Y + connect \A $and$ls180.v:3080$93_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3005$70_Y + connect \Y $and$ls180.v:3080$94_Y end - attribute \src "ls180.v:3005.29-3005.156" - cell $and $and$ls180.v:3005$71 + attribute \src "ls180.v:3080.29-3080.156" + cell $and $and$ls180.v:3080$95 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3005$70_Y + connect \A $and$ls180.v:3080$94_Y connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:3005$71_Y + connect \Y $and$ls180.v:3080$95_Y + end + attribute \src "ls180.v:3081.31-3081.90" + cell $and $and$ls180.v:3081$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3081$96_Y + end + attribute \src "ls180.v:3081.30-3081.121" + cell $and $and$ls180.v:3081$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3081$96_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3081$97_Y + end + attribute \src "ls180.v:3081.29-3081.156" + cell $and $and$ls180.v:3081$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3081$97_Y + connect \B \main_libresocsim_ram_bus_sel [4] + connect \Y $and$ls180.v:3081$98_Y + end + attribute \src "ls180.v:3082.30-3082.121" + cell $and $and$ls180.v:3082$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3082$99_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3082$100_Y + end + attribute \src "ls180.v:3082.29-3082.156" + cell $and $and$ls180.v:3082$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3082$100_Y + connect \B \main_libresocsim_ram_bus_sel [5] + connect \Y $and$ls180.v:3082$101_Y + end + attribute \src "ls180.v:3082.31-3082.90" + cell $and $and$ls180.v:3082$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3082$99_Y + end + attribute \src "ls180.v:3083.31-3083.90" + cell $and $and$ls180.v:3083$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3083$102_Y + end + attribute \src "ls180.v:3083.30-3083.121" + cell $and $and$ls180.v:3083$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3083$102_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3083$103_Y + end + attribute \src "ls180.v:3083.29-3083.156" + cell $and $and$ls180.v:3083$104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3083$103_Y + connect \B \main_libresocsim_ram_bus_sel [6] + connect \Y $and$ls180.v:3083$104_Y + end + attribute \src "ls180.v:3084.31-3084.90" + cell $and $and$ls180.v:3084$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3084$105_Y + end + attribute \src "ls180.v:3084.30-3084.121" + cell $and $and$ls180.v:3084$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3084$105_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3084$106_Y + end + attribute \src "ls180.v:3084.29-3084.156" + cell $and $and$ls180.v:3084$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3084$106_Y + connect \B \main_libresocsim_ram_bus_sel [7] + connect \Y $and$ls180.v:3084$107_Y end - attribute \src "ls180.v:3014.7-3014.89" - cell $and $and$ls180.v:3014$74 + attribute \src "ls180.v:3093.7-3093.89" + cell $and $and$ls180.v:3093$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236498,10 +253187,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_re connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:3014$74_Y + connect \Y $and$ls180.v:3093$110_Y end - attribute \src "ls180.v:3019.32-3019.111" - cell $and $and$ls180.v:3019$75 + attribute \src "ls180.v:3098.32-3098.111" + cell $and $and$ls180.v:3098$111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236509,10 +253198,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_w connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:3019$75_Y + connect \Y $and$ls180.v:3098$111_Y end - attribute \src "ls180.v:3023.25-3023.82" - cell $and $and$ls180.v:3023$77 + attribute \src "ls180.v:3102.25-3102.82" + cell $and $and$ls180.v:3102$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236520,32 +253209,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3023$77_Y + connect \Y $and$ls180.v:3102$113_Y end - attribute \src "ls180.v:3023.24-3023.112" - cell $and $and$ls180.v:3023$78 + attribute \src "ls180.v:3102.24-3102.112" + cell $and $and$ls180.v:3102$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3023$77_Y + connect \A $and$ls180.v:3102$113_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3023$78_Y + connect \Y $and$ls180.v:3102$114_Y end - attribute \src "ls180.v:3023.23-3023.146" - cell $and $and$ls180.v:3023$79 + attribute \src "ls180.v:3102.23-3102.146" + cell $and $and$ls180.v:3102$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3023$78_Y + connect \A $and$ls180.v:3102$114_Y connect \B \main_interface0_ram_bus_sel [0] - connect \Y $and$ls180.v:3023$79_Y + connect \Y $and$ls180.v:3102$115_Y end - attribute \src "ls180.v:3024.25-3024.82" - cell $and $and$ls180.v:3024$80 + attribute \src "ls180.v:3103.25-3103.82" + cell $and $and$ls180.v:3103$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236553,32 +253242,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3024$80_Y + connect \Y $and$ls180.v:3103$116_Y end - attribute \src "ls180.v:3024.24-3024.112" - cell $and $and$ls180.v:3024$81 + attribute \src "ls180.v:3103.24-3103.112" + cell $and $and$ls180.v:3103$117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3024$80_Y + connect \A $and$ls180.v:3103$116_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3024$81_Y + connect \Y $and$ls180.v:3103$117_Y end - attribute \src "ls180.v:3024.23-3024.146" - cell $and $and$ls180.v:3024$82 + attribute \src "ls180.v:3103.23-3103.146" + cell $and $and$ls180.v:3103$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3024$81_Y + connect \A $and$ls180.v:3103$117_Y connect \B \main_interface0_ram_bus_sel [1] - connect \Y $and$ls180.v:3024$82_Y + connect \Y $and$ls180.v:3103$118_Y end - attribute \src "ls180.v:3025.25-3025.82" - cell $and $and$ls180.v:3025$83 + attribute \src "ls180.v:3104.25-3104.82" + cell $and $and$ls180.v:3104$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236586,32 +253275,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3025$83_Y + connect \Y $and$ls180.v:3104$119_Y end - attribute \src "ls180.v:3025.24-3025.112" - cell $and $and$ls180.v:3025$84 + attribute \src "ls180.v:3104.24-3104.112" + cell $and $and$ls180.v:3104$120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3025$83_Y + connect \A $and$ls180.v:3104$119_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3025$84_Y + connect \Y $and$ls180.v:3104$120_Y end - attribute \src "ls180.v:3025.23-3025.146" - cell $and $and$ls180.v:3025$85 + attribute \src "ls180.v:3104.23-3104.146" + cell $and $and$ls180.v:3104$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3025$84_Y + connect \A $and$ls180.v:3104$120_Y connect \B \main_interface0_ram_bus_sel [2] - connect \Y $and$ls180.v:3025$85_Y + connect \Y $and$ls180.v:3104$121_Y end - attribute \src "ls180.v:3026.25-3026.82" - cell $and $and$ls180.v:3026$86 + attribute \src "ls180.v:3105.25-3105.82" + cell $and $and$ls180.v:3105$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236619,32 +253308,164 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3026$86_Y + connect \Y $and$ls180.v:3105$122_Y end - attribute \src "ls180.v:3026.24-3026.112" - cell $and $and$ls180.v:3026$87 + attribute \src "ls180.v:3105.24-3105.112" + cell $and $and$ls180.v:3105$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3026$86_Y + connect \A $and$ls180.v:3105$122_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3026$87_Y + connect \Y $and$ls180.v:3105$123_Y end - attribute \src "ls180.v:3026.23-3026.146" - cell $and $and$ls180.v:3026$88 + attribute \src "ls180.v:3105.23-3105.146" + cell $and $and$ls180.v:3105$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3026$87_Y + connect \A $and$ls180.v:3105$123_Y connect \B \main_interface0_ram_bus_sel [3] - connect \Y $and$ls180.v:3026$88_Y + connect \Y $and$ls180.v:3105$124_Y + end + attribute \src "ls180.v:3106.25-3106.82" + cell $and $and$ls180.v:3106$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3106$125_Y + end + attribute \src "ls180.v:3106.24-3106.112" + cell $and $and$ls180.v:3106$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3106$125_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3106$126_Y + end + attribute \src "ls180.v:3106.23-3106.146" + cell $and $and$ls180.v:3106$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3106$126_Y + connect \B \main_interface0_ram_bus_sel [4] + connect \Y $and$ls180.v:3106$127_Y + end + attribute \src "ls180.v:3107.25-3107.82" + cell $and $and$ls180.v:3107$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3107$128_Y + end + attribute \src "ls180.v:3107.24-3107.112" + cell $and $and$ls180.v:3107$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3107$128_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3107$129_Y + end + attribute \src "ls180.v:3107.23-3107.146" + cell $and $and$ls180.v:3107$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3107$129_Y + connect \B \main_interface0_ram_bus_sel [5] + connect \Y $and$ls180.v:3107$130_Y + end + attribute \src "ls180.v:3108.25-3108.82" + cell $and $and$ls180.v:3108$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3108$131_Y + end + attribute \src "ls180.v:3108.24-3108.112" + cell $and $and$ls180.v:3108$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3108$131_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3108$132_Y + end + attribute \src "ls180.v:3108.23-3108.146" + cell $and $and$ls180.v:3108$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3108$132_Y + connect \B \main_interface0_ram_bus_sel [6] + connect \Y $and$ls180.v:3108$133_Y + end + attribute \src "ls180.v:3109.25-3109.82" + cell $and $and$ls180.v:3109$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3109$134_Y + end + attribute \src "ls180.v:3109.24-3109.112" + cell $and $and$ls180.v:3109$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3109$134_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3109$135_Y + end + attribute \src "ls180.v:3109.23-3109.146" + cell $and $and$ls180.v:3109$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3109$135_Y + connect \B \main_interface0_ram_bus_sel [7] + connect \Y $and$ls180.v:3109$136_Y end - attribute \src "ls180.v:3033.25-3033.82" - cell $and $and$ls180.v:3033$90 + attribute \src "ls180.v:3116.25-3116.82" + cell $and $and$ls180.v:3116$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236652,32 +253473,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3033$90_Y + connect \Y $and$ls180.v:3116$138_Y end - attribute \src "ls180.v:3033.24-3033.112" - cell $and $and$ls180.v:3033$91 + attribute \src "ls180.v:3116.24-3116.112" + cell $and $and$ls180.v:3116$139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3033$90_Y + connect \A $and$ls180.v:3116$138_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3033$91_Y + connect \Y $and$ls180.v:3116$139_Y end - attribute \src "ls180.v:3033.23-3033.146" - cell $and $and$ls180.v:3033$92 + attribute \src "ls180.v:3116.23-3116.146" + cell $and $and$ls180.v:3116$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3033$91_Y + connect \A $and$ls180.v:3116$139_Y connect \B \main_interface1_ram_bus_sel [0] - connect \Y $and$ls180.v:3033$92_Y + connect \Y $and$ls180.v:3116$140_Y end - attribute \src "ls180.v:3034.25-3034.82" - cell $and $and$ls180.v:3034$93 + attribute \src "ls180.v:3117.25-3117.82" + cell $and $and$ls180.v:3117$141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236685,32 +253506,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3034$93_Y + connect \Y $and$ls180.v:3117$141_Y end - attribute \src "ls180.v:3034.24-3034.112" - cell $and $and$ls180.v:3034$94 + attribute \src "ls180.v:3117.24-3117.112" + cell $and $and$ls180.v:3117$142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3034$93_Y + connect \A $and$ls180.v:3117$141_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3034$94_Y + connect \Y $and$ls180.v:3117$142_Y end - attribute \src "ls180.v:3034.23-3034.146" - cell $and $and$ls180.v:3034$95 + attribute \src "ls180.v:3117.23-3117.146" + cell $and $and$ls180.v:3117$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3034$94_Y + connect \A $and$ls180.v:3117$142_Y connect \B \main_interface1_ram_bus_sel [1] - connect \Y $and$ls180.v:3034$95_Y + connect \Y $and$ls180.v:3117$143_Y end - attribute \src "ls180.v:3035.25-3035.82" - cell $and $and$ls180.v:3035$96 + attribute \src "ls180.v:3118.25-3118.82" + cell $and $and$ls180.v:3118$144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236718,54 +253539,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3035$96_Y + connect \Y $and$ls180.v:3118$144_Y end - attribute \src "ls180.v:3035.24-3035.112" - cell $and $and$ls180.v:3035$97 + attribute \src "ls180.v:3118.24-3118.112" + cell $and $and$ls180.v:3118$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3035$96_Y + connect \A $and$ls180.v:3118$144_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3035$97_Y + connect \Y $and$ls180.v:3118$145_Y end - attribute \src "ls180.v:3035.23-3035.146" - cell $and $and$ls180.v:3035$98 + attribute \src "ls180.v:3118.23-3118.146" + cell $and $and$ls180.v:3118$146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3035$97_Y + connect \A $and$ls180.v:3118$145_Y connect \B \main_interface1_ram_bus_sel [2] - connect \Y $and$ls180.v:3035$98_Y + connect \Y $and$ls180.v:3118$146_Y + end + attribute \src "ls180.v:3119.25-3119.82" + cell $and $and$ls180.v:3119$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3119$147_Y end - attribute \src "ls180.v:3036.24-3036.112" - cell $and $and$ls180.v:3036$100 + attribute \src "ls180.v:3119.24-3119.112" + cell $and $and$ls180.v:3119$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3036$99_Y + connect \A $and$ls180.v:3119$147_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3036$100_Y + connect \Y $and$ls180.v:3119$148_Y end - attribute \src "ls180.v:3036.23-3036.146" - cell $and $and$ls180.v:3036$101 + attribute \src "ls180.v:3119.23-3119.146" + cell $and $and$ls180.v:3119$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3036$100_Y + connect \A $and$ls180.v:3119$148_Y connect \B \main_interface1_ram_bus_sel [3] - connect \Y $and$ls180.v:3036$101_Y + connect \Y $and$ls180.v:3119$149_Y + end + attribute \src "ls180.v:3120.25-3120.82" + cell $and $and$ls180.v:3120$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3120$150_Y + end + attribute \src "ls180.v:3120.24-3120.112" + cell $and $and$ls180.v:3120$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3120$150_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3120$151_Y + end + attribute \src "ls180.v:3120.23-3120.146" + cell $and $and$ls180.v:3120$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3120$151_Y + connect \B \main_interface1_ram_bus_sel [4] + connect \Y $and$ls180.v:3120$152_Y + end + attribute \src "ls180.v:3121.25-3121.82" + cell $and $and$ls180.v:3121$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3121$153_Y + end + attribute \src "ls180.v:3121.24-3121.112" + cell $and $and$ls180.v:3121$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3121$153_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3121$154_Y + end + attribute \src "ls180.v:3121.23-3121.146" + cell $and $and$ls180.v:3121$155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3121$154_Y + connect \B \main_interface1_ram_bus_sel [5] + connect \Y $and$ls180.v:3121$155_Y end - attribute \src "ls180.v:3036.25-3036.82" - cell $and $and$ls180.v:3036$99 + attribute \src "ls180.v:3122.25-3122.82" + cell $and $and$ls180.v:3122$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236773,10 +253671,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3036$99_Y + connect \Y $and$ls180.v:3122$156_Y + end + attribute \src "ls180.v:3122.24-3122.112" + cell $and $and$ls180.v:3122$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3122$156_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3122$157_Y end - attribute \src "ls180.v:3043.25-3043.82" - cell $and $and$ls180.v:3043$103 + attribute \src "ls180.v:3122.23-3122.146" + cell $and $and$ls180.v:3122$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3122$157_Y + connect \B \main_interface1_ram_bus_sel [6] + connect \Y $and$ls180.v:3122$158_Y + end + attribute \src "ls180.v:3123.25-3123.82" + cell $and $and$ls180.v:3123$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3123$159_Y + end + attribute \src "ls180.v:3123.24-3123.112" + cell $and $and$ls180.v:3123$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3123$159_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3123$160_Y + end + attribute \src "ls180.v:3123.23-3123.146" + cell $and $and$ls180.v:3123$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3123$160_Y + connect \B \main_interface1_ram_bus_sel [7] + connect \Y $and$ls180.v:3123$161_Y + end + attribute \src "ls180.v:3130.25-3130.82" + cell $and $and$ls180.v:3130$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236784,32 +253737,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3043$103_Y + connect \Y $and$ls180.v:3130$163_Y end - attribute \src "ls180.v:3043.24-3043.112" - cell $and $and$ls180.v:3043$104 + attribute \src "ls180.v:3130.24-3130.112" + cell $and $and$ls180.v:3130$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3043$103_Y + connect \A $and$ls180.v:3130$163_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3043$104_Y + connect \Y $and$ls180.v:3130$164_Y end - attribute \src "ls180.v:3043.23-3043.146" - cell $and $and$ls180.v:3043$105 + attribute \src "ls180.v:3130.23-3130.146" + cell $and $and$ls180.v:3130$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3043$104_Y + connect \A $and$ls180.v:3130$164_Y connect \B \main_interface2_ram_bus_sel [0] - connect \Y $and$ls180.v:3043$105_Y + connect \Y $and$ls180.v:3130$165_Y end - attribute \src "ls180.v:3044.25-3044.82" - cell $and $and$ls180.v:3044$106 + attribute \src "ls180.v:3131.25-3131.82" + cell $and $and$ls180.v:3131$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236817,32 +253770,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3044$106_Y + connect \Y $and$ls180.v:3131$166_Y end - attribute \src "ls180.v:3044.24-3044.112" - cell $and $and$ls180.v:3044$107 + attribute \src "ls180.v:3131.24-3131.112" + cell $and $and$ls180.v:3131$167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3044$106_Y + connect \A $and$ls180.v:3131$166_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3044$107_Y + connect \Y $and$ls180.v:3131$167_Y end - attribute \src "ls180.v:3044.23-3044.146" - cell $and $and$ls180.v:3044$108 + attribute \src "ls180.v:3131.23-3131.146" + cell $and $and$ls180.v:3131$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3044$107_Y + connect \A $and$ls180.v:3131$167_Y connect \B \main_interface2_ram_bus_sel [1] - connect \Y $and$ls180.v:3044$108_Y + connect \Y $and$ls180.v:3131$168_Y end - attribute \src "ls180.v:3045.25-3045.82" - cell $and $and$ls180.v:3045$109 + attribute \src "ls180.v:3132.25-3132.82" + cell $and $and$ls180.v:3132$169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236850,32 +253803,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3045$109_Y + connect \Y $and$ls180.v:3132$169_Y end - attribute \src "ls180.v:3045.24-3045.112" - cell $and $and$ls180.v:3045$110 + attribute \src "ls180.v:3132.24-3132.112" + cell $and $and$ls180.v:3132$170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3045$109_Y + connect \A $and$ls180.v:3132$169_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3045$110_Y + connect \Y $and$ls180.v:3132$170_Y end - attribute \src "ls180.v:3045.23-3045.146" - cell $and $and$ls180.v:3045$111 + attribute \src "ls180.v:3132.23-3132.146" + cell $and $and$ls180.v:3132$171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3045$110_Y + connect \A $and$ls180.v:3132$170_Y connect \B \main_interface2_ram_bus_sel [2] - connect \Y $and$ls180.v:3045$111_Y + connect \Y $and$ls180.v:3132$171_Y end - attribute \src "ls180.v:3046.25-3046.82" - cell $and $and$ls180.v:3046$112 + attribute \src "ls180.v:3133.25-3133.82" + cell $and $and$ls180.v:3133$172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236883,32 +253836,428 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3046$112_Y + connect \Y $and$ls180.v:3133$172_Y end - attribute \src "ls180.v:3046.24-3046.112" - cell $and $and$ls180.v:3046$113 + attribute \src "ls180.v:3133.24-3133.112" + cell $and $and$ls180.v:3133$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3046$112_Y + connect \A $and$ls180.v:3133$172_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3046$113_Y + connect \Y $and$ls180.v:3133$173_Y end - attribute \src "ls180.v:3046.23-3046.146" - cell $and $and$ls180.v:3046$114 + attribute \src "ls180.v:3133.23-3133.146" + cell $and $and$ls180.v:3133$174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3046$113_Y + connect \A $and$ls180.v:3133$173_Y connect \B \main_interface2_ram_bus_sel [3] - connect \Y $and$ls180.v:3046$114_Y + connect \Y $and$ls180.v:3133$174_Y + end + attribute \src "ls180.v:3134.25-3134.82" + cell $and $and$ls180.v:3134$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3134$175_Y + end + attribute \src "ls180.v:3134.24-3134.112" + cell $and $and$ls180.v:3134$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3134$175_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3134$176_Y + end + attribute \src "ls180.v:3134.23-3134.146" + cell $and $and$ls180.v:3134$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3134$176_Y + connect \B \main_interface2_ram_bus_sel [4] + connect \Y $and$ls180.v:3134$177_Y + end + attribute \src "ls180.v:3135.25-3135.82" + cell $and $and$ls180.v:3135$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3135$178_Y + end + attribute \src "ls180.v:3135.24-3135.112" + cell $and $and$ls180.v:3135$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3135$178_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3135$179_Y + end + attribute \src "ls180.v:3135.23-3135.146" + cell $and $and$ls180.v:3135$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3135$179_Y + connect \B \main_interface2_ram_bus_sel [5] + connect \Y $and$ls180.v:3135$180_Y + end + attribute \src "ls180.v:3136.25-3136.82" + cell $and $and$ls180.v:3136$181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3136$181_Y + end + attribute \src "ls180.v:3136.24-3136.112" + cell $and $and$ls180.v:3136$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3136$181_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3136$182_Y + end + attribute \src "ls180.v:3136.23-3136.146" + cell $and $and$ls180.v:3136$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3136$182_Y + connect \B \main_interface2_ram_bus_sel [6] + connect \Y $and$ls180.v:3136$183_Y + end + attribute \src "ls180.v:3137.25-3137.82" + cell $and $and$ls180.v:3137$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3137$184_Y + end + attribute \src "ls180.v:3137.24-3137.112" + cell $and $and$ls180.v:3137$185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3137$184_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3137$185_Y + end + attribute \src "ls180.v:3137.23-3137.146" + cell $and $and$ls180.v:3137$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3137$185_Y + connect \B \main_interface2_ram_bus_sel [7] + connect \Y $and$ls180.v:3137$186_Y + end + attribute \src "ls180.v:3144.25-3144.82" + cell $and $and$ls180.v:3144$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3144$188_Y + end + attribute \src "ls180.v:3144.24-3144.112" + cell $and $and$ls180.v:3144$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3144$188_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3144$189_Y + end + attribute \src "ls180.v:3144.23-3144.146" + cell $and $and$ls180.v:3144$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3144$189_Y + connect \B \main_interface3_ram_bus_sel [0] + connect \Y $and$ls180.v:3144$190_Y + end + attribute \src "ls180.v:3145.25-3145.82" + cell $and $and$ls180.v:3145$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3145$191_Y + end + attribute \src "ls180.v:3145.24-3145.112" + cell $and $and$ls180.v:3145$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3145$191_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3145$192_Y + end + attribute \src "ls180.v:3145.23-3145.146" + cell $and $and$ls180.v:3145$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3145$192_Y + connect \B \main_interface3_ram_bus_sel [1] + connect \Y $and$ls180.v:3145$193_Y + end + attribute \src "ls180.v:3146.25-3146.82" + cell $and $and$ls180.v:3146$194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3146$194_Y + end + attribute \src "ls180.v:3146.24-3146.112" + cell $and $and$ls180.v:3146$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3146$194_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3146$195_Y + end + attribute \src "ls180.v:3146.23-3146.146" + cell $and $and$ls180.v:3146$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3146$195_Y + connect \B \main_interface3_ram_bus_sel [2] + connect \Y $and$ls180.v:3146$196_Y + end + attribute \src "ls180.v:3147.25-3147.82" + cell $and $and$ls180.v:3147$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3147$197_Y + end + attribute \src "ls180.v:3147.24-3147.112" + cell $and $and$ls180.v:3147$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3147$197_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3147$198_Y + end + attribute \src "ls180.v:3147.23-3147.146" + cell $and $and$ls180.v:3147$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3147$198_Y + connect \B \main_interface3_ram_bus_sel [3] + connect \Y $and$ls180.v:3147$199_Y + end + attribute \src "ls180.v:3148.25-3148.82" + cell $and $and$ls180.v:3148$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3148$200_Y + end + attribute \src "ls180.v:3148.24-3148.112" + cell $and $and$ls180.v:3148$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3148$200_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3148$201_Y + end + attribute \src "ls180.v:3148.23-3148.146" + cell $and $and$ls180.v:3148$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3148$201_Y + connect \B \main_interface3_ram_bus_sel [4] + connect \Y $and$ls180.v:3148$202_Y + end + attribute \src "ls180.v:3149.25-3149.82" + cell $and $and$ls180.v:3149$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3149$203_Y + end + attribute \src "ls180.v:3149.24-3149.112" + cell $and $and$ls180.v:3149$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3149$203_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3149$204_Y + end + attribute \src "ls180.v:3149.23-3149.146" + cell $and $and$ls180.v:3149$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3149$204_Y + connect \B \main_interface3_ram_bus_sel [5] + connect \Y $and$ls180.v:3149$205_Y + end + attribute \src "ls180.v:3150.25-3150.82" + cell $and $and$ls180.v:3150$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3150$206_Y + end + attribute \src "ls180.v:3150.24-3150.112" + cell $and $and$ls180.v:3150$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3150$206_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3150$207_Y + end + attribute \src "ls180.v:3150.23-3150.146" + cell $and $and$ls180.v:3150$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3150$207_Y + connect \B \main_interface3_ram_bus_sel [6] + connect \Y $and$ls180.v:3150$208_Y + end + attribute \src "ls180.v:3151.25-3151.82" + cell $and $and$ls180.v:3151$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3151$209_Y + end + attribute \src "ls180.v:3151.24-3151.112" + cell $and $and$ls180.v:3151$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3151$209_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3151$210_Y + end + attribute \src "ls180.v:3151.23-3151.146" + cell $and $and$ls180.v:3151$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3151$210_Y + connect \B \main_interface3_ram_bus_sel [7] + connect \Y $and$ls180.v:3151$211_Y end - attribute \src "ls180.v:3163.40-3163.99" - cell $and $and$ls180.v:3163$121 + attribute \src "ls180.v:3268.40-3268.99" + cell $and $and$ls180.v:3268$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236916,10 +254265,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3163$121_Y + connect \Y $and$ls180.v:3268$218_Y end - attribute \src "ls180.v:3164.40-3164.99" - cell $and $and$ls180.v:3164$122 + attribute \src "ls180.v:3269.40-3269.99" + cell $and $and$ls180.v:3269$219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236927,21 +254276,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3164$122_Y + connect \Y $and$ls180.v:3269$219_Y end - attribute \src "ls180.v:3202.38-3202.103" - cell $and $and$ls180.v:3202$128 + attribute \src "ls180.v:3307.38-3307.103" + cell $and $and$ls180.v:3307$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3202$127_Y - connect \Y $and$ls180.v:3202$128_Y + connect \B $eq$ls180.v:3307$224_Y + connect \Y $and$ls180.v:3307$225_Y end - attribute \src "ls180.v:3256.50-3256.119" - cell $and $and$ls180.v:3256$136 + attribute \src "ls180.v:3361.50-3361.119" + cell $and $and$ls180.v:3361$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236949,21 +254298,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3256$136_Y + connect \Y $and$ls180.v:3361$233_Y end - attribute \src "ls180.v:3256.49-3256.167" - cell $and $and$ls180.v:3256$137 + attribute \src "ls180.v:3361.49-3361.167" + cell $and $and$ls180.v:3361$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3256$136_Y + connect \A $and$ls180.v:3361$233_Y connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3256$137_Y + connect \Y $and$ls180.v:3361$234_Y end - attribute \src "ls180.v:3257.49-3257.118" - cell $and $and$ls180.v:3257$138 + attribute \src "ls180.v:3362.49-3362.118" + cell $and $and$ls180.v:3362$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236971,21 +254320,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3257$138_Y + connect \Y $and$ls180.v:3362$235_Y end - attribute \src "ls180.v:3257.48-3257.154" - cell $and $and$ls180.v:3257$139 + attribute \src "ls180.v:3362.48-3362.154" + cell $and $and$ls180.v:3362$236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3257$138_Y + connect \A $and$ls180.v:3362$235_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3257$139_Y + connect \Y $and$ls180.v:3362$236_Y end - attribute \src "ls180.v:3258.50-3258.119" - cell $and $and$ls180.v:3258$140 + attribute \src "ls180.v:3363.50-3363.119" + cell $and $and$ls180.v:3363$237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236993,21 +254342,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3258$140_Y + connect \Y $and$ls180.v:3363$237_Y end - attribute \src "ls180.v:3258.49-3258.155" - cell $and $and$ls180.v:3258$141 + attribute \src "ls180.v:3363.49-3363.155" + cell $and $and$ls180.v:3363$238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3258$140_Y + connect \A $and$ls180.v:3363$237_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3258$141_Y + connect \Y $and$ls180.v:3363$238_Y end - attribute \src "ls180.v:3261.7-3261.114" - cell $and $and$ls180.v:3261$143 + attribute \src "ls180.v:3366.7-3366.114" + cell $and $and$ls180.v:3366$240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237015,21 +254364,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3261$143_Y + connect \Y $and$ls180.v:3366$240_Y end - attribute \src "ls180.v:3290.66-3290.246" - cell $and $and$ls180.v:3290$149 + attribute \src "ls180.v:3395.66-3395.246" + cell $and $and$ls180.v:3395$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3290$148_Y - connect \Y $and$ls180.v:3290$149_Y + connect \B $or$ls180.v:3395$245_Y + connect \Y $and$ls180.v:3395$246_Y end - attribute \src "ls180.v:3291.64-3291.187" - cell $and $and$ls180.v:3291$150 + attribute \src "ls180.v:3396.64-3396.187" + cell $and $and$ls180.v:3396$247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237037,10 +254386,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3291$150_Y + connect \Y $and$ls180.v:3396$247_Y end - attribute \src "ls180.v:3315.9-3315.86" - cell $and $and$ls180.v:3315$156 + attribute \src "ls180.v:3420.9-3420.86" + cell $and $and$ls180.v:3420$253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237048,10 +254397,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3315$156_Y + connect \Y $and$ls180.v:3420$253_Y end - attribute \src "ls180.v:3327.9-3327.86" - cell $and $and$ls180.v:3327$157 + attribute \src "ls180.v:3432.9-3432.86" + cell $and $and$ls180.v:3432$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237059,10 +254408,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3327$157_Y + connect \Y $and$ls180.v:3432$254_Y end - attribute \src "ls180.v:3377.13-3377.87" - cell $and $and$ls180.v:3377$159 + attribute \src "ls180.v:3482.13-3482.87" + cell $and $and$ls180.v:3482$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237070,10 +254419,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_ready connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3377$159_Y + connect \Y $and$ls180.v:3482$256_Y end - attribute \src "ls180.v:3413.50-3413.119" - cell $and $and$ls180.v:3413$166 + attribute \src "ls180.v:3518.50-3518.119" + cell $and $and$ls180.v:3518$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237081,21 +254430,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3413$166_Y + connect \Y $and$ls180.v:3518$263_Y end - attribute \src "ls180.v:3413.49-3413.167" - cell $and $and$ls180.v:3413$167 + attribute \src "ls180.v:3518.49-3518.167" + cell $and $and$ls180.v:3518$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3413$166_Y + connect \A $and$ls180.v:3518$263_Y connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3413$167_Y + connect \Y $and$ls180.v:3518$264_Y end - attribute \src "ls180.v:3414.49-3414.118" - cell $and $and$ls180.v:3414$168 + attribute \src "ls180.v:3519.49-3519.118" + cell $and $and$ls180.v:3519$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237103,21 +254452,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3414$168_Y + connect \Y $and$ls180.v:3519$265_Y end - attribute \src "ls180.v:3414.48-3414.154" - cell $and $and$ls180.v:3414$169 + attribute \src "ls180.v:3519.48-3519.154" + cell $and $and$ls180.v:3519$266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3414$168_Y + connect \A $and$ls180.v:3519$265_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3414$169_Y + connect \Y $and$ls180.v:3519$266_Y end - attribute \src "ls180.v:3415.50-3415.119" - cell $and $and$ls180.v:3415$170 + attribute \src "ls180.v:3520.50-3520.119" + cell $and $and$ls180.v:3520$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237125,21 +254474,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3415$170_Y + connect \Y $and$ls180.v:3520$267_Y end - attribute \src "ls180.v:3415.49-3415.155" - cell $and $and$ls180.v:3415$171 + attribute \src "ls180.v:3520.49-3520.155" + cell $and $and$ls180.v:3520$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3415$170_Y + connect \A $and$ls180.v:3520$267_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3415$171_Y + connect \Y $and$ls180.v:3520$268_Y end - attribute \src "ls180.v:3418.7-3418.114" - cell $and $and$ls180.v:3418$173 + attribute \src "ls180.v:3523.7-3523.114" + cell $and $and$ls180.v:3523$270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237147,21 +254496,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3418$173_Y + connect \Y $and$ls180.v:3523$270_Y end - attribute \src "ls180.v:3447.66-3447.246" - cell $and $and$ls180.v:3447$179 + attribute \src "ls180.v:3552.66-3552.246" + cell $and $and$ls180.v:3552$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3447$178_Y - connect \Y $and$ls180.v:3447$179_Y + connect \B $or$ls180.v:3552$275_Y + connect \Y $and$ls180.v:3552$276_Y end - attribute \src "ls180.v:3448.64-3448.187" - cell $and $and$ls180.v:3448$180 + attribute \src "ls180.v:3553.64-3553.187" + cell $and $and$ls180.v:3553$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237169,10 +254518,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3448$180_Y + connect \Y $and$ls180.v:3553$277_Y end - attribute \src "ls180.v:3472.9-3472.86" - cell $and $and$ls180.v:3472$186 + attribute \src "ls180.v:3577.9-3577.86" + cell $and $and$ls180.v:3577$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237180,10 +254529,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3472$186_Y + connect \Y $and$ls180.v:3577$283_Y end - attribute \src "ls180.v:3484.9-3484.86" - cell $and $and$ls180.v:3484$187 + attribute \src "ls180.v:3589.9-3589.86" + cell $and $and$ls180.v:3589$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237191,10 +254540,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3484$187_Y + connect \Y $and$ls180.v:3589$284_Y end - attribute \src "ls180.v:3534.13-3534.87" - cell $and $and$ls180.v:3534$189 + attribute \src "ls180.v:3639.13-3639.87" + cell $and $and$ls180.v:3639$286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237202,10 +254551,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_ready connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3534$189_Y + connect \Y $and$ls180.v:3639$286_Y end - attribute \src "ls180.v:3570.50-3570.119" - cell $and $and$ls180.v:3570$196 + attribute \src "ls180.v:3675.50-3675.119" + cell $and $and$ls180.v:3675$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237213,21 +254562,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3570$196_Y + connect \Y $and$ls180.v:3675$293_Y end - attribute \src "ls180.v:3570.49-3570.167" - cell $and $and$ls180.v:3570$197 + attribute \src "ls180.v:3675.49-3675.167" + cell $and $and$ls180.v:3675$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3570$196_Y + connect \A $and$ls180.v:3675$293_Y connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3570$197_Y + connect \Y $and$ls180.v:3675$294_Y end - attribute \src "ls180.v:3571.49-3571.118" - cell $and $and$ls180.v:3571$198 + attribute \src "ls180.v:3676.49-3676.118" + cell $and $and$ls180.v:3676$295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237235,21 +254584,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3571$198_Y + connect \Y $and$ls180.v:3676$295_Y end - attribute \src "ls180.v:3571.48-3571.154" - cell $and $and$ls180.v:3571$199 + attribute \src "ls180.v:3676.48-3676.154" + cell $and $and$ls180.v:3676$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3571$198_Y + connect \A $and$ls180.v:3676$295_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3571$199_Y + connect \Y $and$ls180.v:3676$296_Y end - attribute \src "ls180.v:3572.50-3572.119" - cell $and $and$ls180.v:3572$200 + attribute \src "ls180.v:3677.50-3677.119" + cell $and $and$ls180.v:3677$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237257,21 +254606,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3572$200_Y + connect \Y $and$ls180.v:3677$297_Y end - attribute \src "ls180.v:3572.49-3572.155" - cell $and $and$ls180.v:3572$201 + attribute \src "ls180.v:3677.49-3677.155" + cell $and $and$ls180.v:3677$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3572$200_Y + connect \A $and$ls180.v:3677$297_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3572$201_Y + connect \Y $and$ls180.v:3677$298_Y end - attribute \src "ls180.v:3575.7-3575.114" - cell $and $and$ls180.v:3575$203 + attribute \src "ls180.v:3680.7-3680.114" + cell $and $and$ls180.v:3680$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237279,21 +254628,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3575$203_Y + connect \Y $and$ls180.v:3680$300_Y end - attribute \src "ls180.v:3604.66-3604.246" - cell $and $and$ls180.v:3604$209 + attribute \src "ls180.v:3709.66-3709.246" + cell $and $and$ls180.v:3709$306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3604$208_Y - connect \Y $and$ls180.v:3604$209_Y + connect \B $or$ls180.v:3709$305_Y + connect \Y $and$ls180.v:3709$306_Y end - attribute \src "ls180.v:3605.64-3605.187" - cell $and $and$ls180.v:3605$210 + attribute \src "ls180.v:3710.64-3710.187" + cell $and $and$ls180.v:3710$307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237301,10 +254650,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3605$210_Y + connect \Y $and$ls180.v:3710$307_Y end - attribute \src "ls180.v:3629.9-3629.86" - cell $and $and$ls180.v:3629$216 + attribute \src "ls180.v:3734.9-3734.86" + cell $and $and$ls180.v:3734$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237312,10 +254661,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3629$216_Y + connect \Y $and$ls180.v:3734$313_Y end - attribute \src "ls180.v:3641.9-3641.86" - cell $and $and$ls180.v:3641$217 + attribute \src "ls180.v:3746.9-3746.86" + cell $and $and$ls180.v:3746$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237323,10 +254672,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3641$217_Y + connect \Y $and$ls180.v:3746$314_Y end - attribute \src "ls180.v:3691.13-3691.87" - cell $and $and$ls180.v:3691$219 + attribute \src "ls180.v:3796.13-3796.87" + cell $and $and$ls180.v:3796$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237334,10 +254683,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_ready connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3691$219_Y + connect \Y $and$ls180.v:3796$316_Y end - attribute \src "ls180.v:3727.50-3727.119" - cell $and $and$ls180.v:3727$226 + attribute \src "ls180.v:3832.50-3832.119" + cell $and $and$ls180.v:3832$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237345,21 +254694,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3727$226_Y + connect \Y $and$ls180.v:3832$323_Y end - attribute \src "ls180.v:3727.49-3727.167" - cell $and $and$ls180.v:3727$227 + attribute \src "ls180.v:3832.49-3832.167" + cell $and $and$ls180.v:3832$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3727$226_Y + connect \A $and$ls180.v:3832$323_Y connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3727$227_Y + connect \Y $and$ls180.v:3832$324_Y end - attribute \src "ls180.v:3728.49-3728.118" - cell $and $and$ls180.v:3728$228 + attribute \src "ls180.v:3833.49-3833.118" + cell $and $and$ls180.v:3833$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237367,21 +254716,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3728$228_Y + connect \Y $and$ls180.v:3833$325_Y end - attribute \src "ls180.v:3728.48-3728.154" - cell $and $and$ls180.v:3728$229 + attribute \src "ls180.v:3833.48-3833.154" + cell $and $and$ls180.v:3833$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3728$228_Y + connect \A $and$ls180.v:3833$325_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3728$229_Y + connect \Y $and$ls180.v:3833$326_Y end - attribute \src "ls180.v:3729.50-3729.119" - cell $and $and$ls180.v:3729$230 + attribute \src "ls180.v:3834.50-3834.119" + cell $and $and$ls180.v:3834$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237389,21 +254738,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3729$230_Y + connect \Y $and$ls180.v:3834$327_Y end - attribute \src "ls180.v:3729.49-3729.155" - cell $and $and$ls180.v:3729$231 + attribute \src "ls180.v:3834.49-3834.155" + cell $and $and$ls180.v:3834$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3729$230_Y + connect \A $and$ls180.v:3834$327_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3729$231_Y + connect \Y $and$ls180.v:3834$328_Y end - attribute \src "ls180.v:3732.7-3732.114" - cell $and $and$ls180.v:3732$233 + attribute \src "ls180.v:3837.7-3837.114" + cell $and $and$ls180.v:3837$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237411,21 +254760,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3732$233_Y + connect \Y $and$ls180.v:3837$330_Y end - attribute \src "ls180.v:3761.66-3761.246" - cell $and $and$ls180.v:3761$239 + attribute \src "ls180.v:3866.66-3866.246" + cell $and $and$ls180.v:3866$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3761$238_Y - connect \Y $and$ls180.v:3761$239_Y + connect \B $or$ls180.v:3866$335_Y + connect \Y $and$ls180.v:3866$336_Y end - attribute \src "ls180.v:3762.64-3762.187" - cell $and $and$ls180.v:3762$240 + attribute \src "ls180.v:3867.64-3867.187" + cell $and $and$ls180.v:3867$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237433,10 +254782,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3762$240_Y + connect \Y $and$ls180.v:3867$337_Y end - attribute \src "ls180.v:3786.9-3786.86" - cell $and $and$ls180.v:3786$246 + attribute \src "ls180.v:3891.9-3891.86" + cell $and $and$ls180.v:3891$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237444,10 +254793,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3786$246_Y + connect \Y $and$ls180.v:3891$343_Y end - attribute \src "ls180.v:3798.9-3798.86" - cell $and $and$ls180.v:3798$247 + attribute \src "ls180.v:3903.9-3903.86" + cell $and $and$ls180.v:3903$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237455,10 +254804,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3798$247_Y + connect \Y $and$ls180.v:3903$344_Y end - attribute \src "ls180.v:3848.13-3848.87" - cell $and $and$ls180.v:3848$249 + attribute \src "ls180.v:3953.13-3953.87" + cell $and $and$ls180.v:3953$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237466,10 +254815,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_ready connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3848$249_Y + connect \Y $and$ls180.v:3953$346_Y end - attribute \src "ls180.v:3863.37-3863.102" - cell $and $and$ls180.v:3863$250 + attribute \src "ls180.v:3968.37-3968.102" + cell $and $and$ls180.v:3968$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237477,43 +254826,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3863$250_Y + connect \Y $and$ls180.v:3968$347_Y end - attribute \src "ls180.v:3863.108-3863.188" - cell $and $and$ls180.v:3863$252 + attribute \src "ls180.v:3968.108-3968.188" + cell $and $and$ls180.v:3968$349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3863$251_Y - connect \Y $and$ls180.v:3863$252_Y + connect \B $not$ls180.v:3968$348_Y + connect \Y $and$ls180.v:3968$349_Y end - attribute \src "ls180.v:3863.107-3863.231" - cell $and $and$ls180.v:3863$254 + attribute \src "ls180.v:3968.107-3968.231" + cell $and $and$ls180.v:3968$351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3863$252_Y - connect \B $not$ls180.v:3863$253_Y - connect \Y $and$ls180.v:3863$254_Y + connect \A $and$ls180.v:3968$349_Y + connect \B $not$ls180.v:3968$350_Y + connect \Y $and$ls180.v:3968$351_Y end - attribute \src "ls180.v:3863.36-3863.232" - cell $and $and$ls180.v:3863$255 + attribute \src "ls180.v:3968.36-3968.232" + cell $and $and$ls180.v:3968$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3863$250_Y - connect \B $and$ls180.v:3863$254_Y - connect \Y $and$ls180.v:3863$255_Y + connect \A $and$ls180.v:3968$347_Y + connect \B $and$ls180.v:3968$351_Y + connect \Y $and$ls180.v:3968$352_Y end - attribute \src "ls180.v:3864.37-3864.102" - cell $and $and$ls180.v:3864$256 + attribute \src "ls180.v:3969.37-3969.102" + cell $and $and$ls180.v:3969$353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237521,43 +254870,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3864$256_Y + connect \Y $and$ls180.v:3969$353_Y end - attribute \src "ls180.v:3864.108-3864.188" - cell $and $and$ls180.v:3864$258 + attribute \src "ls180.v:3969.108-3969.188" + cell $and $and$ls180.v:3969$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3864$257_Y - connect \Y $and$ls180.v:3864$258_Y + connect \B $not$ls180.v:3969$354_Y + connect \Y $and$ls180.v:3969$355_Y end - attribute \src "ls180.v:3864.107-3864.231" - cell $and $and$ls180.v:3864$260 + attribute \src "ls180.v:3969.107-3969.231" + cell $and $and$ls180.v:3969$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3864$258_Y - connect \B $not$ls180.v:3864$259_Y - connect \Y $and$ls180.v:3864$260_Y + connect \A $and$ls180.v:3969$355_Y + connect \B $not$ls180.v:3969$356_Y + connect \Y $and$ls180.v:3969$357_Y end - attribute \src "ls180.v:3864.36-3864.232" - cell $and $and$ls180.v:3864$261 + attribute \src "ls180.v:3969.36-3969.232" + cell $and $and$ls180.v:3969$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3864$256_Y - connect \B $and$ls180.v:3864$260_Y - connect \Y $and$ls180.v:3864$261_Y + connect \A $and$ls180.v:3969$353_Y + connect \B $and$ls180.v:3969$357_Y + connect \Y $and$ls180.v:3969$358_Y end - attribute \src "ls180.v:3865.34-3865.85" - cell $and $and$ls180.v:3865$262 + attribute \src "ls180.v:3970.34-3970.85" + cell $and $and$ls180.v:3970$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237565,10 +254914,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_trrdcon_ready connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3865$262_Y + connect \Y $and$ls180.v:3970$359_Y end - attribute \src "ls180.v:3866.37-3866.102" - cell $and $and$ls180.v:3866$263 + attribute \src "ls180.v:3971.37-3971.102" + cell $and $and$ls180.v:3971$360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237576,21 +254925,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3866$263_Y + connect \Y $and$ls180.v:3971$360_Y end - attribute \src "ls180.v:3866.36-3866.194" - cell $and $and$ls180.v:3866$265 + attribute \src "ls180.v:3971.36-3971.194" + cell $and $and$ls180.v:3971$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3866$263_Y - connect \B $or$ls180.v:3866$264_Y - connect \Y $and$ls180.v:3866$265_Y + connect \A $and$ls180.v:3971$360_Y + connect \B $or$ls180.v:3971$361_Y + connect \Y $and$ls180.v:3971$362_Y end - attribute \src "ls180.v:3868.37-3868.102" - cell $and $and$ls180.v:3868$266 + attribute \src "ls180.v:3973.37-3973.102" + cell $and $and$ls180.v:3973$363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237598,21 +254947,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3868$266_Y + connect \Y $and$ls180.v:3973$363_Y end - attribute \src "ls180.v:3868.36-3868.148" - cell $and $and$ls180.v:3868$267 + attribute \src "ls180.v:3973.36-3973.148" + cell $and $and$ls180.v:3973$364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3868$266_Y + connect \A $and$ls180.v:3973$363_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3868$267_Y + connect \Y $and$ls180.v:3973$364_Y end - attribute \src "ls180.v:3869.40-3869.119" - cell $and $and$ls180.v:3869$268 + attribute \src "ls180.v:3974.40-3974.119" + cell $and $and$ls180.v:3974$365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237620,10 +254969,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3869$268_Y + connect \Y $and$ls180.v:3974$365_Y end - attribute \src "ls180.v:3869.124-3869.203" - cell $and $and$ls180.v:3869$269 + attribute \src "ls180.v:3974.124-3974.203" + cell $and $and$ls180.v:3974$366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237631,10 +254980,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3869$269_Y + connect \Y $and$ls180.v:3974$366_Y end - attribute \src "ls180.v:3869.209-3869.288" - cell $and $and$ls180.v:3869$271 + attribute \src "ls180.v:3974.209-3974.288" + cell $and $and$ls180.v:3974$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237642,10 +254991,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3869$271_Y + connect \Y $and$ls180.v:3974$368_Y end - attribute \src "ls180.v:3869.294-3869.373" - cell $and $and$ls180.v:3869$273 + attribute \src "ls180.v:3974.294-3974.373" + cell $and $and$ls180.v:3974$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237653,10 +255002,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3869$273_Y + connect \Y $and$ls180.v:3974$370_Y end - attribute \src "ls180.v:3870.41-3870.121" - cell $and $and$ls180.v:3870$275 + attribute \src "ls180.v:3975.41-3975.121" + cell $and $and$ls180.v:3975$372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237664,10 +255013,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3870$275_Y + connect \Y $and$ls180.v:3975$372_Y end - attribute \src "ls180.v:3870.126-3870.206" - cell $and $and$ls180.v:3870$276 + attribute \src "ls180.v:3975.126-3975.206" + cell $and $and$ls180.v:3975$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237675,10 +255024,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3870$276_Y + connect \Y $and$ls180.v:3975$373_Y end - attribute \src "ls180.v:3870.212-3870.292" - cell $and $and$ls180.v:3870$278 + attribute \src "ls180.v:3975.212-3975.292" + cell $and $and$ls180.v:3975$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237686,10 +255035,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3870$278_Y + connect \Y $and$ls180.v:3975$375_Y end - attribute \src "ls180.v:3870.298-3870.378" - cell $and $and$ls180.v:3870$280 + attribute \src "ls180.v:3975.298-3975.378" + cell $and $and$ls180.v:3975$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237697,10 +255046,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3870$280_Y + connect \Y $and$ls180.v:3975$377_Y end - attribute \src "ls180.v:3877.38-3877.111" - cell $and $and$ls180.v:3877$284 + attribute \src "ls180.v:3982.38-3982.111" + cell $and $and$ls180.v:3982$381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237708,32 +255057,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_gnt connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3877$284_Y + connect \Y $and$ls180.v:3982$381_Y end - attribute \src "ls180.v:3877.37-3877.150" - cell $and $and$ls180.v:3877$285 + attribute \src "ls180.v:3982.37-3982.150" + cell $and $and$ls180.v:3982$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3877$284_Y + connect \A $and$ls180.v:3982$381_Y connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3877$285_Y + connect \Y $and$ls180.v:3982$382_Y end - attribute \src "ls180.v:3877.36-3877.189" - cell $and $and$ls180.v:3877$286 + attribute \src "ls180.v:3982.36-3982.189" + cell $and $and$ls180.v:3982$383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3877$285_Y + connect \A $and$ls180.v:3982$382_Y connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3877$286_Y + connect \Y $and$ls180.v:3982$383_Y end - attribute \src "ls180.v:3883.77-3883.153" - cell $and $and$ls180.v:3883$289 + attribute \src "ls180.v:3988.77-3988.153" + cell $and $and$ls180.v:3988$386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237741,65 +255090,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3883$289_Y + connect \Y $and$ls180.v:3988$386_Y end - attribute \src "ls180.v:3883.162-3883.246" - cell $and $and$ls180.v:3883$291 + attribute \src "ls180.v:3988.162-3988.246" + cell $and $and$ls180.v:3988$388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3883$290_Y - connect \Y $and$ls180.v:3883$291_Y + connect \B $not$ls180.v:3988$387_Y + connect \Y $and$ls180.v:3988$388_Y end - attribute \src "ls180.v:3883.161-3883.291" - cell $and $and$ls180.v:3883$293 + attribute \src "ls180.v:3988.161-3988.291" + cell $and $and$ls180.v:3988$390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$291_Y - connect \B $not$ls180.v:3883$292_Y - connect \Y $and$ls180.v:3883$293_Y + connect \A $and$ls180.v:3988$388_Y + connect \B $not$ls180.v:3988$389_Y + connect \Y $and$ls180.v:3988$390_Y end - attribute \src "ls180.v:3883.76-3883.333" - cell $and $and$ls180.v:3883$296 + attribute \src "ls180.v:3988.76-3988.333" + cell $and $and$ls180.v:3988$393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$289_Y - connect \B $or$ls180.v:3883$295_Y - connect \Y $and$ls180.v:3883$296_Y + connect \A $and$ls180.v:3988$386_Y + connect \B $or$ls180.v:3988$392_Y + connect \Y $and$ls180.v:3988$393_Y end - attribute \src "ls180.v:3883.338-3883.505" - cell $and $and$ls180.v:3883$299 + attribute \src "ls180.v:3988.338-3988.505" + cell $and $and$ls180.v:3988$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3883$297_Y - connect \B $eq$ls180.v:3883$298_Y - connect \Y $and$ls180.v:3883$299_Y + connect \A $eq$ls180.v:3988$394_Y + connect \B $eq$ls180.v:3988$395_Y + connect \Y $and$ls180.v:3988$396_Y end - attribute \src "ls180.v:3883.38-3883.507" - cell $and $and$ls180.v:3883$301 + attribute \src "ls180.v:3988.38-3988.507" + cell $and $and$ls180.v:3988$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3883$300_Y - connect \Y $and$ls180.v:3883$301_Y + connect \B $or$ls180.v:3988$397_Y + connect \Y $and$ls180.v:3988$398_Y end - attribute \src "ls180.v:3884.77-3884.153" - cell $and $and$ls180.v:3884$302 + attribute \src "ls180.v:3989.77-3989.153" + cell $and $and$ls180.v:3989$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237807,65 +255156,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3884$302_Y + connect \Y $and$ls180.v:3989$399_Y end - attribute \src "ls180.v:3884.162-3884.246" - cell $and $and$ls180.v:3884$304 + attribute \src "ls180.v:3989.162-3989.246" + cell $and $and$ls180.v:3989$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3884$303_Y - connect \Y $and$ls180.v:3884$304_Y + connect \B $not$ls180.v:3989$400_Y + connect \Y $and$ls180.v:3989$401_Y end - attribute \src "ls180.v:3884.161-3884.291" - cell $and $and$ls180.v:3884$306 + attribute \src "ls180.v:3989.161-3989.291" + cell $and $and$ls180.v:3989$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$304_Y - connect \B $not$ls180.v:3884$305_Y - connect \Y $and$ls180.v:3884$306_Y + connect \A $and$ls180.v:3989$401_Y + connect \B $not$ls180.v:3989$402_Y + connect \Y $and$ls180.v:3989$403_Y end - attribute \src "ls180.v:3884.76-3884.333" - cell $and $and$ls180.v:3884$309 + attribute \src "ls180.v:3989.76-3989.333" + cell $and $and$ls180.v:3989$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$302_Y - connect \B $or$ls180.v:3884$308_Y - connect \Y $and$ls180.v:3884$309_Y + connect \A $and$ls180.v:3989$399_Y + connect \B $or$ls180.v:3989$405_Y + connect \Y $and$ls180.v:3989$406_Y end - attribute \src "ls180.v:3884.338-3884.505" - cell $and $and$ls180.v:3884$312 + attribute \src "ls180.v:3989.338-3989.505" + cell $and $and$ls180.v:3989$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3884$310_Y - connect \B $eq$ls180.v:3884$311_Y - connect \Y $and$ls180.v:3884$312_Y + connect \A $eq$ls180.v:3989$407_Y + connect \B $eq$ls180.v:3989$408_Y + connect \Y $and$ls180.v:3989$409_Y end - attribute \src "ls180.v:3884.38-3884.507" - cell $and $and$ls180.v:3884$314 + attribute \src "ls180.v:3989.38-3989.507" + cell $and $and$ls180.v:3989$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3884$313_Y - connect \Y $and$ls180.v:3884$314_Y + connect \B $or$ls180.v:3989$410_Y + connect \Y $and$ls180.v:3989$411_Y end - attribute \src "ls180.v:3885.77-3885.153" - cell $and $and$ls180.v:3885$315 + attribute \src "ls180.v:3990.77-3990.153" + cell $and $and$ls180.v:3990$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237873,65 +255222,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3885$315_Y + connect \Y $and$ls180.v:3990$412_Y end - attribute \src "ls180.v:3885.162-3885.246" - cell $and $and$ls180.v:3885$317 + attribute \src "ls180.v:3990.162-3990.246" + cell $and $and$ls180.v:3990$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3885$316_Y - connect \Y $and$ls180.v:3885$317_Y + connect \B $not$ls180.v:3990$413_Y + connect \Y $and$ls180.v:3990$414_Y end - attribute \src "ls180.v:3885.161-3885.291" - cell $and $and$ls180.v:3885$319 + attribute \src "ls180.v:3990.161-3990.291" + cell $and $and$ls180.v:3990$416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$317_Y - connect \B $not$ls180.v:3885$318_Y - connect \Y $and$ls180.v:3885$319_Y + connect \A $and$ls180.v:3990$414_Y + connect \B $not$ls180.v:3990$415_Y + connect \Y $and$ls180.v:3990$416_Y end - attribute \src "ls180.v:3885.76-3885.333" - cell $and $and$ls180.v:3885$322 + attribute \src "ls180.v:3990.76-3990.333" + cell $and $and$ls180.v:3990$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$315_Y - connect \B $or$ls180.v:3885$321_Y - connect \Y $and$ls180.v:3885$322_Y + connect \A $and$ls180.v:3990$412_Y + connect \B $or$ls180.v:3990$418_Y + connect \Y $and$ls180.v:3990$419_Y end - attribute \src "ls180.v:3885.338-3885.505" - cell $and $and$ls180.v:3885$325 + attribute \src "ls180.v:3990.338-3990.505" + cell $and $and$ls180.v:3990$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$323_Y - connect \B $eq$ls180.v:3885$324_Y - connect \Y $and$ls180.v:3885$325_Y + connect \A $eq$ls180.v:3990$420_Y + connect \B $eq$ls180.v:3990$421_Y + connect \Y $and$ls180.v:3990$422_Y end - attribute \src "ls180.v:3885.38-3885.507" - cell $and $and$ls180.v:3885$327 + attribute \src "ls180.v:3990.38-3990.507" + cell $and $and$ls180.v:3990$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3885$326_Y - connect \Y $and$ls180.v:3885$327_Y + connect \B $or$ls180.v:3990$423_Y + connect \Y $and$ls180.v:3990$424_Y end - attribute \src "ls180.v:3886.77-3886.153" - cell $and $and$ls180.v:3886$328 + attribute \src "ls180.v:3991.77-3991.153" + cell $and $and$ls180.v:3991$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237939,65 +255288,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3886$328_Y + connect \Y $and$ls180.v:3991$425_Y end - attribute \src "ls180.v:3886.162-3886.246" - cell $and $and$ls180.v:3886$330 + attribute \src "ls180.v:3991.162-3991.246" + cell $and $and$ls180.v:3991$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3886$329_Y - connect \Y $and$ls180.v:3886$330_Y + connect \B $not$ls180.v:3991$426_Y + connect \Y $and$ls180.v:3991$427_Y end - attribute \src "ls180.v:3886.161-3886.291" - cell $and $and$ls180.v:3886$332 + attribute \src "ls180.v:3991.161-3991.291" + cell $and $and$ls180.v:3991$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$330_Y - connect \B $not$ls180.v:3886$331_Y - connect \Y $and$ls180.v:3886$332_Y + connect \A $and$ls180.v:3991$427_Y + connect \B $not$ls180.v:3991$428_Y + connect \Y $and$ls180.v:3991$429_Y end - attribute \src "ls180.v:3886.76-3886.333" - cell $and $and$ls180.v:3886$335 + attribute \src "ls180.v:3991.76-3991.333" + cell $and $and$ls180.v:3991$432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$328_Y - connect \B $or$ls180.v:3886$334_Y - connect \Y $and$ls180.v:3886$335_Y + connect \A $and$ls180.v:3991$425_Y + connect \B $or$ls180.v:3991$431_Y + connect \Y $and$ls180.v:3991$432_Y end - attribute \src "ls180.v:3886.338-3886.505" - cell $and $and$ls180.v:3886$338 + attribute \src "ls180.v:3991.338-3991.505" + cell $and $and$ls180.v:3991$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3886$336_Y - connect \B $eq$ls180.v:3886$337_Y - connect \Y $and$ls180.v:3886$338_Y + connect \A $eq$ls180.v:3991$433_Y + connect \B $eq$ls180.v:3991$434_Y + connect \Y $and$ls180.v:3991$435_Y end - attribute \src "ls180.v:3886.38-3886.507" - cell $and $and$ls180.v:3886$340 + attribute \src "ls180.v:3991.38-3991.507" + cell $and $and$ls180.v:3991$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3886$339_Y - connect \Y $and$ls180.v:3886$340_Y + connect \B $or$ls180.v:3991$436_Y + connect \Y $and$ls180.v:3991$437_Y end - attribute \src "ls180.v:3916.77-3916.153" - cell $and $and$ls180.v:3916$347 + attribute \src "ls180.v:4021.77-4021.153" + cell $and $and$ls180.v:4021$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238005,65 +255354,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3916$347_Y + connect \Y $and$ls180.v:4021$444_Y end - attribute \src "ls180.v:3916.162-3916.246" - cell $and $and$ls180.v:3916$349 + attribute \src "ls180.v:4021.162-4021.246" + cell $and $and$ls180.v:4021$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3916$348_Y - connect \Y $and$ls180.v:3916$349_Y + connect \B $not$ls180.v:4021$445_Y + connect \Y $and$ls180.v:4021$446_Y end - attribute \src "ls180.v:3916.161-3916.291" - cell $and $and$ls180.v:3916$351 + attribute \src "ls180.v:4021.161-4021.291" + cell $and $and$ls180.v:4021$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3916$349_Y - connect \B $not$ls180.v:3916$350_Y - connect \Y $and$ls180.v:3916$351_Y + connect \A $and$ls180.v:4021$446_Y + connect \B $not$ls180.v:4021$447_Y + connect \Y $and$ls180.v:4021$448_Y end - attribute \src "ls180.v:3916.76-3916.333" - cell $and $and$ls180.v:3916$354 + attribute \src "ls180.v:4021.76-4021.333" + cell $and $and$ls180.v:4021$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3916$347_Y - connect \B $or$ls180.v:3916$353_Y - connect \Y $and$ls180.v:3916$354_Y + connect \A $and$ls180.v:4021$444_Y + connect \B $or$ls180.v:4021$450_Y + connect \Y $and$ls180.v:4021$451_Y end - attribute \src "ls180.v:3916.338-3916.505" - cell $and $and$ls180.v:3916$357 + attribute \src "ls180.v:4021.338-4021.505" + cell $and $and$ls180.v:4021$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3916$355_Y - connect \B $eq$ls180.v:3916$356_Y - connect \Y $and$ls180.v:3916$357_Y + connect \A $eq$ls180.v:4021$452_Y + connect \B $eq$ls180.v:4021$453_Y + connect \Y $and$ls180.v:4021$454_Y end - attribute \src "ls180.v:3916.38-3916.507" - cell $and $and$ls180.v:3916$359 + attribute \src "ls180.v:4021.38-4021.507" + cell $and $and$ls180.v:4021$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3916$358_Y - connect \Y $and$ls180.v:3916$359_Y + connect \B $or$ls180.v:4021$455_Y + connect \Y $and$ls180.v:4021$456_Y end - attribute \src "ls180.v:3917.77-3917.153" - cell $and $and$ls180.v:3917$360 + attribute \src "ls180.v:4022.77-4022.153" + cell $and $and$ls180.v:4022$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238071,65 +255420,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3917$360_Y + connect \Y $and$ls180.v:4022$457_Y end - attribute \src "ls180.v:3917.162-3917.246" - cell $and $and$ls180.v:3917$362 + attribute \src "ls180.v:4022.162-4022.246" + cell $and $and$ls180.v:4022$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3917$361_Y - connect \Y $and$ls180.v:3917$362_Y + connect \B $not$ls180.v:4022$458_Y + connect \Y $and$ls180.v:4022$459_Y end - attribute \src "ls180.v:3917.161-3917.291" - cell $and $and$ls180.v:3917$364 + attribute \src "ls180.v:4022.161-4022.291" + cell $and $and$ls180.v:4022$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3917$362_Y - connect \B $not$ls180.v:3917$363_Y - connect \Y $and$ls180.v:3917$364_Y + connect \A $and$ls180.v:4022$459_Y + connect \B $not$ls180.v:4022$460_Y + connect \Y $and$ls180.v:4022$461_Y end - attribute \src "ls180.v:3917.76-3917.333" - cell $and $and$ls180.v:3917$367 + attribute \src "ls180.v:4022.76-4022.333" + cell $and $and$ls180.v:4022$464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3917$360_Y - connect \B $or$ls180.v:3917$366_Y - connect \Y $and$ls180.v:3917$367_Y + connect \A $and$ls180.v:4022$457_Y + connect \B $or$ls180.v:4022$463_Y + connect \Y $and$ls180.v:4022$464_Y end - attribute \src "ls180.v:3917.338-3917.505" - cell $and $and$ls180.v:3917$370 + attribute \src "ls180.v:4022.338-4022.505" + cell $and $and$ls180.v:4022$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3917$368_Y - connect \B $eq$ls180.v:3917$369_Y - connect \Y $and$ls180.v:3917$370_Y + connect \A $eq$ls180.v:4022$465_Y + connect \B $eq$ls180.v:4022$466_Y + connect \Y $and$ls180.v:4022$467_Y end - attribute \src "ls180.v:3917.38-3917.507" - cell $and $and$ls180.v:3917$372 + attribute \src "ls180.v:4022.38-4022.507" + cell $and $and$ls180.v:4022$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3917$371_Y - connect \Y $and$ls180.v:3917$372_Y + connect \B $or$ls180.v:4022$468_Y + connect \Y $and$ls180.v:4022$469_Y end - attribute \src "ls180.v:3918.77-3918.153" - cell $and $and$ls180.v:3918$373 + attribute \src "ls180.v:4023.77-4023.153" + cell $and $and$ls180.v:4023$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238137,65 +255486,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3918$373_Y + connect \Y $and$ls180.v:4023$470_Y end - attribute \src "ls180.v:3918.162-3918.246" - cell $and $and$ls180.v:3918$375 + attribute \src "ls180.v:4023.162-4023.246" + cell $and $and$ls180.v:4023$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3918$374_Y - connect \Y $and$ls180.v:3918$375_Y + connect \B $not$ls180.v:4023$471_Y + connect \Y $and$ls180.v:4023$472_Y end - attribute \src "ls180.v:3918.161-3918.291" - cell $and $and$ls180.v:3918$377 + attribute \src "ls180.v:4023.161-4023.291" + cell $and $and$ls180.v:4023$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3918$375_Y - connect \B $not$ls180.v:3918$376_Y - connect \Y $and$ls180.v:3918$377_Y + connect \A $and$ls180.v:4023$472_Y + connect \B $not$ls180.v:4023$473_Y + connect \Y $and$ls180.v:4023$474_Y end - attribute \src "ls180.v:3918.76-3918.333" - cell $and $and$ls180.v:3918$380 + attribute \src "ls180.v:4023.76-4023.333" + cell $and $and$ls180.v:4023$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3918$373_Y - connect \B $or$ls180.v:3918$379_Y - connect \Y $and$ls180.v:3918$380_Y + connect \A $and$ls180.v:4023$470_Y + connect \B $or$ls180.v:4023$476_Y + connect \Y $and$ls180.v:4023$477_Y end - attribute \src "ls180.v:3918.338-3918.505" - cell $and $and$ls180.v:3918$383 + attribute \src "ls180.v:4023.338-4023.505" + cell $and $and$ls180.v:4023$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3918$381_Y - connect \B $eq$ls180.v:3918$382_Y - connect \Y $and$ls180.v:3918$383_Y + connect \A $eq$ls180.v:4023$478_Y + connect \B $eq$ls180.v:4023$479_Y + connect \Y $and$ls180.v:4023$480_Y end - attribute \src "ls180.v:3918.38-3918.507" - cell $and $and$ls180.v:3918$385 + attribute \src "ls180.v:4023.38-4023.507" + cell $and $and$ls180.v:4023$482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3918$384_Y - connect \Y $and$ls180.v:3918$385_Y + connect \B $or$ls180.v:4023$481_Y + connect \Y $and$ls180.v:4023$482_Y end - attribute \src "ls180.v:3919.77-3919.153" - cell $and $and$ls180.v:3919$386 + attribute \src "ls180.v:4024.77-4024.153" + cell $and $and$ls180.v:4024$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238203,65 +255552,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3919$386_Y + connect \Y $and$ls180.v:4024$483_Y end - attribute \src "ls180.v:3919.162-3919.246" - cell $and $and$ls180.v:3919$388 + attribute \src "ls180.v:4024.162-4024.246" + cell $and $and$ls180.v:4024$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3919$387_Y - connect \Y $and$ls180.v:3919$388_Y + connect \B $not$ls180.v:4024$484_Y + connect \Y $and$ls180.v:4024$485_Y end - attribute \src "ls180.v:3919.161-3919.291" - cell $and $and$ls180.v:3919$390 + attribute \src "ls180.v:4024.161-4024.291" + cell $and $and$ls180.v:4024$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$388_Y - connect \B $not$ls180.v:3919$389_Y - connect \Y $and$ls180.v:3919$390_Y + connect \A $and$ls180.v:4024$485_Y + connect \B $not$ls180.v:4024$486_Y + connect \Y $and$ls180.v:4024$487_Y end - attribute \src "ls180.v:3919.76-3919.333" - cell $and $and$ls180.v:3919$393 + attribute \src "ls180.v:4024.76-4024.333" + cell $and $and$ls180.v:4024$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$386_Y - connect \B $or$ls180.v:3919$392_Y - connect \Y $and$ls180.v:3919$393_Y + connect \A $and$ls180.v:4024$483_Y + connect \B $or$ls180.v:4024$489_Y + connect \Y $and$ls180.v:4024$490_Y end - attribute \src "ls180.v:3919.338-3919.505" - cell $and $and$ls180.v:3919$396 + attribute \src "ls180.v:4024.338-4024.505" + cell $and $and$ls180.v:4024$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3919$394_Y - connect \B $eq$ls180.v:3919$395_Y - connect \Y $and$ls180.v:3919$396_Y + connect \A $eq$ls180.v:4024$491_Y + connect \B $eq$ls180.v:4024$492_Y + connect \Y $and$ls180.v:4024$493_Y end - attribute \src "ls180.v:3919.38-3919.507" - cell $and $and$ls180.v:3919$398 + attribute \src "ls180.v:4024.38-4024.507" + cell $and $and$ls180.v:4024$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3919$397_Y - connect \Y $and$ls180.v:3919$398_Y + connect \B $or$ls180.v:4024$494_Y + connect \Y $and$ls180.v:4024$495_Y end - attribute \src "ls180.v:3948.8-3948.73" - cell $and $and$ls180.v:3948$403 + attribute \src "ls180.v:4053.8-4053.73" + cell $and $and$ls180.v:4053$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238269,21 +255618,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3948$403_Y + connect \Y $and$ls180.v:4053$500_Y end - attribute \src "ls180.v:3948.7-3948.114" - cell $and $and$ls180.v:3948$405 + attribute \src "ls180.v:4053.7-4053.114" + cell $and $and$ls180.v:4053$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3948$403_Y - connect \B $eq$ls180.v:3948$404_Y - connect \Y $and$ls180.v:3948$405_Y + connect \A $and$ls180.v:4053$500_Y + connect \B $eq$ls180.v:4053$501_Y + connect \Y $and$ls180.v:4053$502_Y end - attribute \src "ls180.v:3951.8-3951.73" - cell $and $and$ls180.v:3951$406 + attribute \src "ls180.v:4056.8-4056.73" + cell $and $and$ls180.v:4056$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238291,21 +255640,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3951$406_Y + connect \Y $and$ls180.v:4056$503_Y end - attribute \src "ls180.v:3951.7-3951.114" - cell $and $and$ls180.v:3951$408 + attribute \src "ls180.v:4056.7-4056.114" + cell $and $and$ls180.v:4056$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3951$406_Y - connect \B $eq$ls180.v:3951$407_Y - connect \Y $and$ls180.v:3951$408_Y + connect \A $and$ls180.v:4056$503_Y + connect \B $eq$ls180.v:4056$504_Y + connect \Y $and$ls180.v:4056$505_Y end - attribute \src "ls180.v:3957.8-3957.73" - cell $and $and$ls180.v:3957$410 + attribute \src "ls180.v:4062.8-4062.73" + cell $and $and$ls180.v:4062$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238313,21 +255662,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3957$410_Y + connect \Y $and$ls180.v:4062$507_Y end - attribute \src "ls180.v:3957.7-3957.114" - cell $and $and$ls180.v:3957$412 + attribute \src "ls180.v:4062.7-4062.114" + cell $and $and$ls180.v:4062$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3957$410_Y - connect \B $eq$ls180.v:3957$411_Y - connect \Y $and$ls180.v:3957$412_Y + connect \A $and$ls180.v:4062$507_Y + connect \B $eq$ls180.v:4062$508_Y + connect \Y $and$ls180.v:4062$509_Y end - attribute \src "ls180.v:3960.8-3960.73" - cell $and $and$ls180.v:3960$413 + attribute \src "ls180.v:4065.8-4065.73" + cell $and $and$ls180.v:4065$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238335,21 +255684,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3960$413_Y + connect \Y $and$ls180.v:4065$510_Y end - attribute \src "ls180.v:3960.7-3960.114" - cell $and $and$ls180.v:3960$415 + attribute \src "ls180.v:4065.7-4065.114" + cell $and $and$ls180.v:4065$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3960$413_Y - connect \B $eq$ls180.v:3960$414_Y - connect \Y $and$ls180.v:3960$415_Y + connect \A $and$ls180.v:4065$510_Y + connect \B $eq$ls180.v:4065$511_Y + connect \Y $and$ls180.v:4065$512_Y end - attribute \src "ls180.v:3966.8-3966.73" - cell $and $and$ls180.v:3966$417 + attribute \src "ls180.v:4071.8-4071.73" + cell $and $and$ls180.v:4071$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238357,21 +255706,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3966$417_Y + connect \Y $and$ls180.v:4071$514_Y end - attribute \src "ls180.v:3966.7-3966.114" - cell $and $and$ls180.v:3966$419 + attribute \src "ls180.v:4071.7-4071.114" + cell $and $and$ls180.v:4071$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3966$417_Y - connect \B $eq$ls180.v:3966$418_Y - connect \Y $and$ls180.v:3966$419_Y + connect \A $and$ls180.v:4071$514_Y + connect \B $eq$ls180.v:4071$515_Y + connect \Y $and$ls180.v:4071$516_Y end - attribute \src "ls180.v:3969.8-3969.73" - cell $and $and$ls180.v:3969$420 + attribute \src "ls180.v:4074.8-4074.73" + cell $and $and$ls180.v:4074$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238379,21 +255728,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3969$420_Y + connect \Y $and$ls180.v:4074$517_Y end - attribute \src "ls180.v:3969.7-3969.114" - cell $and $and$ls180.v:3969$422 + attribute \src "ls180.v:4074.7-4074.114" + cell $and $and$ls180.v:4074$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3969$420_Y - connect \B $eq$ls180.v:3969$421_Y - connect \Y $and$ls180.v:3969$422_Y + connect \A $and$ls180.v:4074$517_Y + connect \B $eq$ls180.v:4074$518_Y + connect \Y $and$ls180.v:4074$519_Y end - attribute \src "ls180.v:3975.8-3975.73" - cell $and $and$ls180.v:3975$424 + attribute \src "ls180.v:4080.8-4080.73" + cell $and $and$ls180.v:4080$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238401,21 +255750,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3975$424_Y + connect \Y $and$ls180.v:4080$521_Y end - attribute \src "ls180.v:3975.7-3975.114" - cell $and $and$ls180.v:3975$426 + attribute \src "ls180.v:4080.7-4080.114" + cell $and $and$ls180.v:4080$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3975$424_Y - connect \B $eq$ls180.v:3975$425_Y - connect \Y $and$ls180.v:3975$426_Y + connect \A $and$ls180.v:4080$521_Y + connect \B $eq$ls180.v:4080$522_Y + connect \Y $and$ls180.v:4080$523_Y end - attribute \src "ls180.v:3978.8-3978.73" - cell $and $and$ls180.v:3978$427 + attribute \src "ls180.v:4083.8-4083.73" + cell $and $and$ls180.v:4083$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238423,615 +255772,615 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3978$427_Y + connect \Y $and$ls180.v:4083$524_Y end - attribute \src "ls180.v:3978.7-3978.114" - cell $and $and$ls180.v:3978$429 + attribute \src "ls180.v:4083.7-4083.114" + cell $and $and$ls180.v:4083$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3978$427_Y - connect \B $eq$ls180.v:3978$428_Y - connect \Y $and$ls180.v:3978$429_Y + connect \A $and$ls180.v:4083$524_Y + connect \B $eq$ls180.v:4083$525_Y + connect \Y $and$ls180.v:4083$526_Y end - attribute \src "ls180.v:4003.71-4003.151" - cell $and $and$ls180.v:4003$434 + attribute \src "ls180.v:4108.71-4108.151" + cell $and $and$ls180.v:4108$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4003$433_Y - connect \Y $and$ls180.v:4003$434_Y + connect \B $not$ls180.v:4108$530_Y + connect \Y $and$ls180.v:4108$531_Y end - attribute \src "ls180.v:4003.70-4003.194" - cell $and $and$ls180.v:4003$436 + attribute \src "ls180.v:4108.70-4108.194" + cell $and $and$ls180.v:4108$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4003$434_Y - connect \B $not$ls180.v:4003$435_Y - connect \Y $and$ls180.v:4003$436_Y + connect \A $and$ls180.v:4108$531_Y + connect \B $not$ls180.v:4108$532_Y + connect \Y $and$ls180.v:4108$533_Y end - attribute \src "ls180.v:4003.41-4003.222" - cell $and $and$ls180.v:4003$439 + attribute \src "ls180.v:4108.41-4108.222" + cell $and $and$ls180.v:4108$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4003$438_Y - connect \Y $and$ls180.v:4003$439_Y + connect \B $or$ls180.v:4108$535_Y + connect \Y $and$ls180.v:4108$536_Y end - attribute \src "ls180.v:4041.71-4041.151" - cell $and $and$ls180.v:4041$443 + attribute \src "ls180.v:4146.71-4146.151" + cell $and $and$ls180.v:4146$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4041$442_Y - connect \Y $and$ls180.v:4041$443_Y + connect \B $not$ls180.v:4146$539_Y + connect \Y $and$ls180.v:4146$540_Y end - attribute \src "ls180.v:4041.70-4041.194" - cell $and $and$ls180.v:4041$445 + attribute \src "ls180.v:4146.70-4146.194" + cell $and $and$ls180.v:4146$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4041$443_Y - connect \B $not$ls180.v:4041$444_Y - connect \Y $and$ls180.v:4041$445_Y + connect \A $and$ls180.v:4146$540_Y + connect \B $not$ls180.v:4146$541_Y + connect \Y $and$ls180.v:4146$542_Y end - attribute \src "ls180.v:4041.41-4041.222" - cell $and $and$ls180.v:4041$448 + attribute \src "ls180.v:4146.41-4146.222" + cell $and $and$ls180.v:4146$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4041$447_Y - connect \Y $and$ls180.v:4041$448_Y + connect \B $or$ls180.v:4146$544_Y + connect \Y $and$ls180.v:4146$545_Y end - attribute \src "ls180.v:4059.110-4059.179" - cell $and $and$ls180.v:4059$453 + attribute \src "ls180.v:4164.110-4164.179" + cell $and $and$ls180.v:4164$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4059$452_Y - connect \Y $and$ls180.v:4059$453_Y + connect \B $eq$ls180.v:4164$549_Y + connect \Y $and$ls180.v:4164$550_Y end - attribute \src "ls180.v:4059.185-4059.254" - cell $and $and$ls180.v:4059$456 + attribute \src "ls180.v:4164.185-4164.254" + cell $and $and$ls180.v:4164$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4059$455_Y - connect \Y $and$ls180.v:4059$456_Y + connect \B $eq$ls180.v:4164$552_Y + connect \Y $and$ls180.v:4164$553_Y end - attribute \src "ls180.v:4059.260-4059.329" - cell $and $and$ls180.v:4059$459 + attribute \src "ls180.v:4164.260-4164.329" + cell $and $and$ls180.v:4164$556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4059$458_Y - connect \Y $and$ls180.v:4059$459_Y + connect \B $eq$ls180.v:4164$555_Y + connect \Y $and$ls180.v:4164$556_Y end - attribute \src "ls180.v:4059.41-4059.332" - cell $and $and$ls180.v:4059$462 + attribute \src "ls180.v:4164.41-4164.332" + cell $and $and$ls180.v:4164$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4059$451_Y - connect \B $not$ls180.v:4059$461_Y - connect \Y $and$ls180.v:4059$462_Y + connect \A $eq$ls180.v:4164$548_Y + connect \B $not$ls180.v:4164$558_Y + connect \Y $and$ls180.v:4164$559_Y end - attribute \src "ls180.v:4059.40-4059.355" - cell $and $and$ls180.v:4059$463 + attribute \src "ls180.v:4164.40-4164.355" + cell $and $and$ls180.v:4164$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4059$462_Y + connect \A $and$ls180.v:4164$559_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4059$463_Y + connect \Y $and$ls180.v:4164$560_Y end - attribute \src "ls180.v:4060.34-4060.106" - cell $and $and$ls180.v:4060$466 + attribute \src "ls180.v:4165.34-4165.106" + cell $and $and$ls180.v:4165$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4060$464_Y - connect \B $not$ls180.v:4060$465_Y - connect \Y $and$ls180.v:4060$466_Y + connect \A $not$ls180.v:4165$561_Y + connect \B $not$ls180.v:4165$562_Y + connect \Y $and$ls180.v:4165$563_Y end - attribute \src "ls180.v:4064.110-4064.179" - cell $and $and$ls180.v:4064$469 + attribute \src "ls180.v:4169.110-4169.179" + cell $and $and$ls180.v:4169$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4064$468_Y - connect \Y $and$ls180.v:4064$469_Y + connect \B $eq$ls180.v:4169$565_Y + connect \Y $and$ls180.v:4169$566_Y end - attribute \src "ls180.v:4064.185-4064.254" - cell $and $and$ls180.v:4064$472 + attribute \src "ls180.v:4169.185-4169.254" + cell $and $and$ls180.v:4169$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4064$471_Y - connect \Y $and$ls180.v:4064$472_Y + connect \B $eq$ls180.v:4169$568_Y + connect \Y $and$ls180.v:4169$569_Y end - attribute \src "ls180.v:4064.260-4064.329" - cell $and $and$ls180.v:4064$475 + attribute \src "ls180.v:4169.260-4169.329" + cell $and $and$ls180.v:4169$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4064$474_Y - connect \Y $and$ls180.v:4064$475_Y + connect \B $eq$ls180.v:4169$571_Y + connect \Y $and$ls180.v:4169$572_Y end - attribute \src "ls180.v:4064.41-4064.332" - cell $and $and$ls180.v:4064$478 + attribute \src "ls180.v:4169.41-4169.332" + cell $and $and$ls180.v:4169$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4064$467_Y - connect \B $not$ls180.v:4064$477_Y - connect \Y $and$ls180.v:4064$478_Y + connect \A $eq$ls180.v:4169$564_Y + connect \B $not$ls180.v:4169$574_Y + connect \Y $and$ls180.v:4169$575_Y end - attribute \src "ls180.v:4064.40-4064.355" - cell $and $and$ls180.v:4064$479 + attribute \src "ls180.v:4169.40-4169.355" + cell $and $and$ls180.v:4169$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4064$478_Y + connect \A $and$ls180.v:4169$575_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4064$479_Y + connect \Y $and$ls180.v:4169$576_Y end - attribute \src "ls180.v:4065.34-4065.106" - cell $and $and$ls180.v:4065$482 + attribute \src "ls180.v:4170.34-4170.106" + cell $and $and$ls180.v:4170$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4065$480_Y - connect \B $not$ls180.v:4065$481_Y - connect \Y $and$ls180.v:4065$482_Y + connect \A $not$ls180.v:4170$577_Y + connect \B $not$ls180.v:4170$578_Y + connect \Y $and$ls180.v:4170$579_Y end - attribute \src "ls180.v:4069.110-4069.179" - cell $and $and$ls180.v:4069$485 + attribute \src "ls180.v:4174.110-4174.179" + cell $and $and$ls180.v:4174$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4069$484_Y - connect \Y $and$ls180.v:4069$485_Y + connect \B $eq$ls180.v:4174$581_Y + connect \Y $and$ls180.v:4174$582_Y end - attribute \src "ls180.v:4069.185-4069.254" - cell $and $and$ls180.v:4069$488 + attribute \src "ls180.v:4174.185-4174.254" + cell $and $and$ls180.v:4174$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4069$487_Y - connect \Y $and$ls180.v:4069$488_Y + connect \B $eq$ls180.v:4174$584_Y + connect \Y $and$ls180.v:4174$585_Y end - attribute \src "ls180.v:4069.260-4069.329" - cell $and $and$ls180.v:4069$491 + attribute \src "ls180.v:4174.260-4174.329" + cell $and $and$ls180.v:4174$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4069$490_Y - connect \Y $and$ls180.v:4069$491_Y + connect \B $eq$ls180.v:4174$587_Y + connect \Y $and$ls180.v:4174$588_Y end - attribute \src "ls180.v:4069.41-4069.332" - cell $and $and$ls180.v:4069$494 + attribute \src "ls180.v:4174.41-4174.332" + cell $and $and$ls180.v:4174$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4069$483_Y - connect \B $not$ls180.v:4069$493_Y - connect \Y $and$ls180.v:4069$494_Y + connect \A $eq$ls180.v:4174$580_Y + connect \B $not$ls180.v:4174$590_Y + connect \Y $and$ls180.v:4174$591_Y end - attribute \src "ls180.v:4069.40-4069.355" - cell $and $and$ls180.v:4069$495 + attribute \src "ls180.v:4174.40-4174.355" + cell $and $and$ls180.v:4174$592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4069$494_Y + connect \A $and$ls180.v:4174$591_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4069$495_Y + connect \Y $and$ls180.v:4174$592_Y end - attribute \src "ls180.v:4070.34-4070.106" - cell $and $and$ls180.v:4070$498 + attribute \src "ls180.v:4175.34-4175.106" + cell $and $and$ls180.v:4175$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4070$496_Y - connect \B $not$ls180.v:4070$497_Y - connect \Y $and$ls180.v:4070$498_Y + connect \A $not$ls180.v:4175$593_Y + connect \B $not$ls180.v:4175$594_Y + connect \Y $and$ls180.v:4175$595_Y end - attribute \src "ls180.v:4074.110-4074.179" - cell $and $and$ls180.v:4074$501 + attribute \src "ls180.v:4179.110-4179.179" + cell $and $and$ls180.v:4179$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4074$500_Y - connect \Y $and$ls180.v:4074$501_Y + connect \B $eq$ls180.v:4179$597_Y + connect \Y $and$ls180.v:4179$598_Y end - attribute \src "ls180.v:4074.185-4074.254" - cell $and $and$ls180.v:4074$504 + attribute \src "ls180.v:4179.185-4179.254" + cell $and $and$ls180.v:4179$601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4074$503_Y - connect \Y $and$ls180.v:4074$504_Y + connect \B $eq$ls180.v:4179$600_Y + connect \Y $and$ls180.v:4179$601_Y end - attribute \src "ls180.v:4074.260-4074.329" - cell $and $and$ls180.v:4074$507 + attribute \src "ls180.v:4179.260-4179.329" + cell $and $and$ls180.v:4179$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4074$506_Y - connect \Y $and$ls180.v:4074$507_Y + connect \B $eq$ls180.v:4179$603_Y + connect \Y $and$ls180.v:4179$604_Y end - attribute \src "ls180.v:4074.41-4074.332" - cell $and $and$ls180.v:4074$510 + attribute \src "ls180.v:4179.41-4179.332" + cell $and $and$ls180.v:4179$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4074$499_Y - connect \B $not$ls180.v:4074$509_Y - connect \Y $and$ls180.v:4074$510_Y + connect \A $eq$ls180.v:4179$596_Y + connect \B $not$ls180.v:4179$606_Y + connect \Y $and$ls180.v:4179$607_Y end - attribute \src "ls180.v:4074.40-4074.355" - cell $and $and$ls180.v:4074$511 + attribute \src "ls180.v:4179.40-4179.355" + cell $and $and$ls180.v:4179$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4074$510_Y + connect \A $and$ls180.v:4179$607_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4074$511_Y + connect \Y $and$ls180.v:4179$608_Y end - attribute \src "ls180.v:4075.34-4075.106" - cell $and $and$ls180.v:4075$514 + attribute \src "ls180.v:4180.34-4180.106" + cell $and $and$ls180.v:4180$611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4075$512_Y - connect \B $not$ls180.v:4075$513_Y - connect \Y $and$ls180.v:4075$514_Y + connect \A $not$ls180.v:4180$609_Y + connect \B $not$ls180.v:4180$610_Y + connect \Y $and$ls180.v:4180$611_Y end - attribute \src "ls180.v:4079.151-4079.220" - cell $and $and$ls180.v:4079$518 + attribute \src "ls180.v:4184.151-4184.220" + cell $and $and$ls180.v:4184$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4079$517_Y - connect \Y $and$ls180.v:4079$518_Y + connect \B $eq$ls180.v:4184$614_Y + connect \Y $and$ls180.v:4184$615_Y end - attribute \src "ls180.v:4079.226-4079.295" - cell $and $and$ls180.v:4079$521 + attribute \src "ls180.v:4184.226-4184.295" + cell $and $and$ls180.v:4184$618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4079$520_Y - connect \Y $and$ls180.v:4079$521_Y + connect \B $eq$ls180.v:4184$617_Y + connect \Y $and$ls180.v:4184$618_Y end - attribute \src "ls180.v:4079.301-4079.370" - cell $and $and$ls180.v:4079$524 + attribute \src "ls180.v:4184.301-4184.370" + cell $and $and$ls180.v:4184$621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4079$523_Y - connect \Y $and$ls180.v:4079$524_Y + connect \B $eq$ls180.v:4184$620_Y + connect \Y $and$ls180.v:4184$621_Y end - attribute \src "ls180.v:4079.82-4079.373" - cell $and $and$ls180.v:4079$527 + attribute \src "ls180.v:4184.82-4184.373" + cell $and $and$ls180.v:4184$624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$516_Y - connect \B $not$ls180.v:4079$526_Y - connect \Y $and$ls180.v:4079$527_Y + connect \A $eq$ls180.v:4184$613_Y + connect \B $not$ls180.v:4184$623_Y + connect \Y $and$ls180.v:4184$624_Y end - attribute \src "ls180.v:4079.43-4079.374" - cell $and $and$ls180.v:4079$528 + attribute \src "ls180.v:4184.43-4184.374" + cell $and $and$ls180.v:4184$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$515_Y - connect \B $and$ls180.v:4079$527_Y - connect \Y $and$ls180.v:4079$528_Y + connect \A $eq$ls180.v:4184$612_Y + connect \B $and$ls180.v:4184$624_Y + connect \Y $and$ls180.v:4184$625_Y end - attribute \src "ls180.v:4079.42-4079.410" - cell $and $and$ls180.v:4079$529 + attribute \src "ls180.v:4184.42-4184.410" + cell $and $and$ls180.v:4184$626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4079$528_Y + connect \A $and$ls180.v:4184$625_Y connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4079$529_Y + connect \Y $and$ls180.v:4184$626_Y end - attribute \src "ls180.v:4079.525-4079.594" - cell $and $and$ls180.v:4079$534 + attribute \src "ls180.v:4184.525-4184.594" + cell $and $and$ls180.v:4184$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4079$533_Y - connect \Y $and$ls180.v:4079$534_Y + connect \B $eq$ls180.v:4184$630_Y + connect \Y $and$ls180.v:4184$631_Y end - attribute \src "ls180.v:4079.600-4079.669" - cell $and $and$ls180.v:4079$537 + attribute \src "ls180.v:4184.600-4184.669" + cell $and $and$ls180.v:4184$634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4079$536_Y - connect \Y $and$ls180.v:4079$537_Y + connect \B $eq$ls180.v:4184$633_Y + connect \Y $and$ls180.v:4184$634_Y end - attribute \src "ls180.v:4079.675-4079.744" - cell $and $and$ls180.v:4079$540 + attribute \src "ls180.v:4184.675-4184.744" + cell $and $and$ls180.v:4184$637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4079$539_Y - connect \Y $and$ls180.v:4079$540_Y + connect \B $eq$ls180.v:4184$636_Y + connect \Y $and$ls180.v:4184$637_Y end - attribute \src "ls180.v:4079.456-4079.747" - cell $and $and$ls180.v:4079$543 + attribute \src "ls180.v:4184.456-4184.747" + cell $and $and$ls180.v:4184$640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$532_Y - connect \B $not$ls180.v:4079$542_Y - connect \Y $and$ls180.v:4079$543_Y + connect \A $eq$ls180.v:4184$629_Y + connect \B $not$ls180.v:4184$639_Y + connect \Y $and$ls180.v:4184$640_Y end - attribute \src "ls180.v:4079.417-4079.748" - cell $and $and$ls180.v:4079$544 + attribute \src "ls180.v:4184.417-4184.748" + cell $and $and$ls180.v:4184$641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$531_Y - connect \B $and$ls180.v:4079$543_Y - connect \Y $and$ls180.v:4079$544_Y + connect \A $eq$ls180.v:4184$628_Y + connect \B $and$ls180.v:4184$640_Y + connect \Y $and$ls180.v:4184$641_Y end - attribute \src "ls180.v:4079.416-4079.784" - cell $and $and$ls180.v:4079$545 + attribute \src "ls180.v:4184.416-4184.784" + cell $and $and$ls180.v:4184$642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4079$544_Y + connect \A $and$ls180.v:4184$641_Y connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4079$545_Y + connect \Y $and$ls180.v:4184$642_Y end - attribute \src "ls180.v:4079.899-4079.968" - cell $and $and$ls180.v:4079$550 + attribute \src "ls180.v:4184.899-4184.968" + cell $and $and$ls180.v:4184$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4079$549_Y - connect \Y $and$ls180.v:4079$550_Y + connect \B $eq$ls180.v:4184$646_Y + connect \Y $and$ls180.v:4184$647_Y end - attribute \src "ls180.v:4079.974-4079.1043" - cell $and $and$ls180.v:4079$553 + attribute \src "ls180.v:4184.974-4184.1043" + cell $and $and$ls180.v:4184$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4079$552_Y - connect \Y $and$ls180.v:4079$553_Y + connect \B $eq$ls180.v:4184$649_Y + connect \Y $and$ls180.v:4184$650_Y end - attribute \src "ls180.v:4079.1049-4079.1118" - cell $and $and$ls180.v:4079$556 + attribute \src "ls180.v:4184.1049-4184.1118" + cell $and $and$ls180.v:4184$653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4079$555_Y - connect \Y $and$ls180.v:4079$556_Y + connect \B $eq$ls180.v:4184$652_Y + connect \Y $and$ls180.v:4184$653_Y end - attribute \src "ls180.v:4079.830-4079.1121" - cell $and $and$ls180.v:4079$559 + attribute \src "ls180.v:4184.830-4184.1121" + cell $and $and$ls180.v:4184$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$548_Y - connect \B $not$ls180.v:4079$558_Y - connect \Y $and$ls180.v:4079$559_Y + connect \A $eq$ls180.v:4184$645_Y + connect \B $not$ls180.v:4184$655_Y + connect \Y $and$ls180.v:4184$656_Y end - attribute \src "ls180.v:4079.791-4079.1122" - cell $and $and$ls180.v:4079$560 + attribute \src "ls180.v:4184.791-4184.1122" + cell $and $and$ls180.v:4184$657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$547_Y - connect \B $and$ls180.v:4079$559_Y - connect \Y $and$ls180.v:4079$560_Y + connect \A $eq$ls180.v:4184$644_Y + connect \B $and$ls180.v:4184$656_Y + connect \Y $and$ls180.v:4184$657_Y end - attribute \src "ls180.v:4079.790-4079.1158" - cell $and $and$ls180.v:4079$561 + attribute \src "ls180.v:4184.790-4184.1158" + cell $and $and$ls180.v:4184$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4079$560_Y + connect \A $and$ls180.v:4184$657_Y connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4079$561_Y + connect \Y $and$ls180.v:4184$658_Y end - attribute \src "ls180.v:4079.1273-4079.1342" - cell $and $and$ls180.v:4079$566 + attribute \src "ls180.v:4184.1273-4184.1342" + cell $and $and$ls180.v:4184$663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4079$565_Y - connect \Y $and$ls180.v:4079$566_Y + connect \B $eq$ls180.v:4184$662_Y + connect \Y $and$ls180.v:4184$663_Y end - attribute \src "ls180.v:4079.1348-4079.1417" - cell $and $and$ls180.v:4079$569 + attribute \src "ls180.v:4184.1348-4184.1417" + cell $and $and$ls180.v:4184$666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4079$568_Y - connect \Y $and$ls180.v:4079$569_Y + connect \B $eq$ls180.v:4184$665_Y + connect \Y $and$ls180.v:4184$666_Y end - attribute \src "ls180.v:4079.1423-4079.1492" - cell $and $and$ls180.v:4079$572 + attribute \src "ls180.v:4184.1423-4184.1492" + cell $and $and$ls180.v:4184$669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4079$571_Y - connect \Y $and$ls180.v:4079$572_Y + connect \B $eq$ls180.v:4184$668_Y + connect \Y $and$ls180.v:4184$669_Y end - attribute \src "ls180.v:4079.1204-4079.1495" - cell $and $and$ls180.v:4079$575 + attribute \src "ls180.v:4184.1204-4184.1495" + cell $and $and$ls180.v:4184$672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$564_Y - connect \B $not$ls180.v:4079$574_Y - connect \Y $and$ls180.v:4079$575_Y + connect \A $eq$ls180.v:4184$661_Y + connect \B $not$ls180.v:4184$671_Y + connect \Y $and$ls180.v:4184$672_Y end - attribute \src "ls180.v:4079.1165-4079.1496" - cell $and $and$ls180.v:4079$576 + attribute \src "ls180.v:4184.1165-4184.1496" + cell $and $and$ls180.v:4184$673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$563_Y - connect \B $and$ls180.v:4079$575_Y - connect \Y $and$ls180.v:4079$576_Y + connect \A $eq$ls180.v:4184$660_Y + connect \B $and$ls180.v:4184$672_Y + connect \Y $and$ls180.v:4184$673_Y end - attribute \src "ls180.v:4079.1164-4079.1532" - cell $and $and$ls180.v:4079$577 + attribute \src "ls180.v:4184.1164-4184.1532" + cell $and $and$ls180.v:4184$674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4079$576_Y + connect \A $and$ls180.v:4184$673_Y connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4079$577_Y + connect \Y $and$ls180.v:4184$674_Y end - attribute \src "ls180.v:4137.9-4137.46" - cell $and $and$ls180.v:4137$583 + attribute \src "ls180.v:4242.9-4242.46" + cell $and $and$ls180.v:4242$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239039,10 +256388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4137$583_Y + connect \Y $and$ls180.v:4242$680_Y end - attribute \src "ls180.v:4155.9-4155.46" - cell $and $and$ls180.v:4155$590 + attribute \src "ls180.v:4260.9-4260.46" + cell $and $and$ls180.v:4260$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239050,10 +256399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4155$590_Y + connect \Y $and$ls180.v:4260$687_Y end - attribute \src "ls180.v:4168.32-4168.75" - cell $and $and$ls180.v:4168$594 + attribute \src "ls180.v:4273.32-4273.75" + cell $and $and$ls180.v:4273$691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239061,54 +256410,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4168$594_Y + connect \Y $and$ls180.v:4273$691_Y end - attribute \src "ls180.v:4168.31-4168.99" - cell $and $and$ls180.v:4168$596 + attribute \src "ls180.v:4273.31-4273.99" + cell $and $and$ls180.v:4273$693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4168$594_Y - connect \B $not$ls180.v:4168$595_Y - connect \Y $and$ls180.v:4168$596_Y + connect \A $and$ls180.v:4273$691_Y + connect \B $not$ls180.v:4273$692_Y + connect \Y $and$ls180.v:4273$693_Y end - attribute \src "ls180.v:4169.34-4169.102" - cell $and $and$ls180.v:4169$598 + attribute \src "ls180.v:4274.34-4274.102" + cell $and $and$ls180.v:4274$695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4169$597_Y + connect \A $or$ls180.v:4274$694_Y connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4169$598_Y + connect \Y $and$ls180.v:4274$695_Y end - attribute \src "ls180.v:4169.33-4169.128" - cell $and $and$ls180.v:4169$600 + attribute \src "ls180.v:4274.33-4274.128" + cell $and $and$ls180.v:4274$697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4169$598_Y - connect \B $not$ls180.v:4169$599_Y - connect \Y $and$ls180.v:4169$600_Y + connect \A $and$ls180.v:4274$695_Y + connect \B $not$ls180.v:4274$696_Y + connect \Y $and$ls180.v:4274$697_Y end - attribute \src "ls180.v:4170.33-4170.104" - cell $and $and$ls180.v:4170$603 + attribute \src "ls180.v:4275.33-4275.104" + cell $and $and$ls180.v:4275$700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4170$601_Y - connect \B $not$ls180.v:4170$602_Y - connect \Y $and$ls180.v:4170$603_Y + connect \A $or$ls180.v:4275$698_Y + connect \B $not$ls180.v:4275$699_Y + connect \Y $and$ls180.v:4275$700_Y end - attribute \src "ls180.v:4171.49-4171.85" - cell $and $and$ls180.v:4171$604 + attribute \src "ls180.v:4276.49-4276.85" + cell $and $and$ls180.v:4276$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239116,32 +256465,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we connect \B \main_ack_wdata - connect \Y $and$ls180.v:4171$604_Y + connect \Y $and$ls180.v:4276$701_Y end - attribute \src "ls180.v:4171.90-4171.129" - cell $and $and$ls180.v:4171$606 + attribute \src "ls180.v:4276.90-4276.129" + cell $and $and$ls180.v:4276$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4171$605_Y + connect \A $not$ls180.v:4276$702_Y connect \B \main_ack_rdata - connect \Y $and$ls180.v:4171$606_Y + connect \Y $and$ls180.v:4276$703_Y end - attribute \src "ls180.v:4171.32-4171.131" - cell $and $and$ls180.v:4171$608 + attribute \src "ls180.v:4276.32-4276.131" + cell $and $and$ls180.v:4276$705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_ack_cmd - connect \B $or$ls180.v:4171$607_Y - connect \Y $and$ls180.v:4171$608_Y + connect \B $or$ls180.v:4276$704_Y + connect \Y $and$ls180.v:4276$705_Y end - attribute \src "ls180.v:4172.25-4172.66" - cell $and $and$ls180.v:4172$609 + attribute \src "ls180.v:4277.25-4277.66" + cell $and $and$ls180.v:4277$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239149,10 +256498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4172$609_Y + connect \Y $and$ls180.v:4277$706_Y end - attribute \src "ls180.v:4173.27-4173.72" - cell $and $and$ls180.v:4173$611 + attribute \src "ls180.v:4278.27-4278.72" + cell $and $and$ls180.v:4278$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239160,10 +256509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4173$611_Y + connect \Y $and$ls180.v:4278$708_Y end - attribute \src "ls180.v:4174.26-4174.71" - cell $and $and$ls180.v:4174$613 + attribute \src "ls180.v:4279.26-4279.71" + cell $and $and$ls180.v:4279$710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239171,10 +256520,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_rdata_valid connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4174$613_Y + connect \Y $and$ls180.v:4279$710_Y end - attribute \src "ls180.v:4203.64-4203.88" - cell $and $and$ls180.v:4203$619 + attribute \src "ls180.v:4308.64-4308.88" + cell $and $and$ls180.v:4308$716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239182,10 +256531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4203$619_Y + connect \Y $and$ls180.v:4308$716_Y end - attribute \src "ls180.v:4207.7-4207.78" - cell $and $and$ls180.v:4207$623 + attribute \src "ls180.v:4312.7-4312.78" + cell $and $and$ls180.v:4312$720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239193,10 +256542,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4207$623_Y + connect \Y $and$ls180.v:4312$720_Y end - attribute \src "ls180.v:4218.7-4218.78" - cell $and $and$ls180.v:4218$626 + attribute \src "ls180.v:4323.7-4323.78" + cell $and $and$ls180.v:4323$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239204,10 +256553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4218$626_Y + connect \Y $and$ls180.v:4323$723_Y end - attribute \src "ls180.v:4227.26-4227.97" - cell $and $and$ls180.v:4227$628 + attribute \src "ls180.v:4332.26-4332.97" + cell $and $and$ls180.v:4332$725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239215,10 +256564,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [0] connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4227$628_Y + connect \Y $and$ls180.v:4332$725_Y end - attribute \src "ls180.v:4227.102-4227.173" - cell $and $and$ls180.v:4227$629 + attribute \src "ls180.v:4332.102-4332.173" + cell $and $and$ls180.v:4332$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239226,32 +256575,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [1] connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4227$629_Y + connect \Y $and$ls180.v:4332$726_Y end - attribute \src "ls180.v:4242.41-4242.133" - cell $and $and$ls180.v:4242$633 + attribute \src "ls180.v:4347.41-4347.133" + cell $and $and$ls180.v:4347$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4242$632_Y - connect \Y $and$ls180.v:4242$633_Y + connect \B $or$ls180.v:4347$729_Y + connect \Y $and$ls180.v:4347$730_Y end - attribute \src "ls180.v:4253.39-4253.136" - cell $and $and$ls180.v:4253$638 + attribute \src "ls180.v:4358.39-4358.136" + cell $and $and$ls180.v:4358$735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4253$637_Y - connect \Y $and$ls180.v:4253$638_Y + connect \B $or$ls180.v:4358$734_Y + connect \Y $and$ls180.v:4358$735_Y end - attribute \src "ls180.v:4254.37-4254.104" - cell $and $and$ls180.v:4254$639 + attribute \src "ls180.v:4359.37-4359.104" + cell $and $and$ls180.v:4359$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239259,32 +256608,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4254$639_Y + connect \Y $and$ls180.v:4359$736_Y end - attribute \src "ls180.v:4272.41-4272.133" - cell $and $and$ls180.v:4272$644 + attribute \src "ls180.v:4377.41-4377.133" + cell $and $and$ls180.v:4377$741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4272$643_Y - connect \Y $and$ls180.v:4272$644_Y + connect \B $or$ls180.v:4377$740_Y + connect \Y $and$ls180.v:4377$741_Y end - attribute \src "ls180.v:4283.39-4283.136" - cell $and $and$ls180.v:4283$649 + attribute \src "ls180.v:4388.39-4388.136" + cell $and $and$ls180.v:4388$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4283$648_Y - connect \Y $and$ls180.v:4283$649_Y + connect \B $or$ls180.v:4388$745_Y + connect \Y $and$ls180.v:4388$746_Y end - attribute \src "ls180.v:4284.37-4284.104" - cell $and $and$ls180.v:4284$650 + attribute \src "ls180.v:4389.37-4389.104" + cell $and $and$ls180.v:4389$747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239292,21 +256641,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4284$650_Y + connect \Y $and$ls180.v:4389$747_Y end - attribute \src "ls180.v:4472.33-4472.86" - cell $and $and$ls180.v:4472$692 + attribute \src "ls180.v:4588.33-4588.86" + cell $and $and$ls180.v:4588$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4472$691_Y - connect \Y $and$ls180.v:4472$692_Y + connect \B $not$ls180.v:4588$790_Y + connect \Y $and$ls180.v:4588$791_Y end - attribute \src "ls180.v:4576.9-4576.68" - cell $and $and$ls180.v:4576$701 + attribute \src "ls180.v:4692.9-4692.68" + cell $and $and$ls180.v:4692$800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239314,21 +256663,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4576$701_Y + connect \Y $and$ls180.v:4692$800_Y end - attribute \src "ls180.v:4596.53-4596.145" - cell $and $and$ls180.v:4596$704 + attribute \src "ls180.v:4712.53-4712.145" + cell $and $and$ls180.v:4712$803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4596$703_Y - connect \Y $and$ls180.v:4596$704_Y + connect \B $or$ls180.v:4712$802_Y + connect \Y $and$ls180.v:4712$803_Y end - attribute \src "ls180.v:4615.52-4615.137" - cell $and $and$ls180.v:4615$707 + attribute \src "ls180.v:4731.52-4731.137" + cell $and $and$ls180.v:4731$806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239336,10 +256685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4615$707_Y + connect \Y $and$ls180.v:4731$806_Y end - attribute \src "ls180.v:4656.9-4656.68" - cell $and $and$ls180.v:4656$715 + attribute \src "ls180.v:4772.9-4772.68" + cell $and $and$ls180.v:4772$814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239347,10 +256696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4656$715_Y + connect \Y $and$ls180.v:4772$814_Y end - attribute \src "ls180.v:4694.9-4694.68" - cell $and $and$ls180.v:4694$721 + attribute \src "ls180.v:4810.9-4810.68" + cell $and $and$ls180.v:4810$820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239358,10 +256707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4694$721_Y + connect \Y $and$ls180.v:4810$820_Y end - attribute \src "ls180.v:4703.10-4703.69" - cell $and $and$ls180.v:4703$722 + attribute \src "ls180.v:4819.10-4819.69" + cell $and $and$ls180.v:4819$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239369,21 +256718,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_sink_valid connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4703$722_Y + connect \Y $and$ls180.v:4819$821_Y end - attribute \src "ls180.v:4703.9-4703.93" - cell $and $and$ls180.v:4703$723 + attribute \src "ls180.v:4819.9-4819.93" + cell $and $and$ls180.v:4819$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4703$722_Y + connect \A $and$ls180.v:4819$821_Y connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4703$723_Y + connect \Y $and$ls180.v:4819$822_Y end - attribute \src "ls180.v:4723.54-4723.117" - cell $and $and$ls180.v:4723$725 + attribute \src "ls180.v:4839.54-4839.117" + cell $and $and$ls180.v:4839$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239391,10 +256740,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_valid connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4723$725_Y + connect \Y $and$ls180.v:4839$824_Y end - attribute \src "ls180.v:4742.53-4742.140" - cell $and $and$ls180.v:4742$728 + attribute \src "ls180.v:4858.53-4858.140" + cell $and $and$ls180.v:4858$827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239402,10 +256751,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4742$728_Y + connect \Y $and$ls180.v:4858$827_Y end - attribute \src "ls180.v:4839.9-4839.70" - cell $and $and$ls180.v:4839$738 + attribute \src "ls180.v:4955.9-4955.70" + cell $and $and$ls180.v:4955$837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239413,10 +256762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4839$738_Y + connect \Y $and$ls180.v:4955$837_Y end - attribute \src "ls180.v:4857.55-4857.120" - cell $and $and$ls180.v:4857$740 + attribute \src "ls180.v:4973.55-4973.120" + cell $and $and$ls180.v:4973$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239424,10 +256773,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_valid connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4857$740_Y + connect \Y $and$ls180.v:4973$839_Y end - attribute \src "ls180.v:4876.54-4876.143" - cell $and $and$ls180.v:4876$743 + attribute \src "ls180.v:4992.54-4992.143" + cell $and $and$ls180.v:4992$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239435,10 +256784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4876$743_Y + connect \Y $and$ls180.v:4992$842_Y end - attribute \src "ls180.v:4958.9-4958.70" - cell $and $and$ls180.v:4958$758 + attribute \src "ls180.v:5074.9-5074.70" + cell $and $and$ls180.v:5074$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239446,10 +256795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_valid connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:4958$758_Y + connect \Y $and$ls180.v:5074$857_Y end - attribute \src "ls180.v:4965.9-4965.70" - cell $and $and$ls180.v:4965$759 + attribute \src "ls180.v:5081.9-5081.70" + cell $and $and$ls180.v:5081$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239457,10 +256806,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_sink_valid connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:4965$759_Y + connect \Y $and$ls180.v:5081$858_Y end - attribute \src "ls180.v:5046.48-5046.124" - cell $and $and$ls180.v:5046$882 + attribute \src "ls180.v:5162.48-5162.124" + cell $and $and$ls180.v:5162$981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239468,21 +256817,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5046$882_Y + connect \Y $and$ls180.v:5162$981_Y end - attribute \src "ls180.v:5046.47-5046.165" - cell $and $and$ls180.v:5046$883 + attribute \src "ls180.v:5162.47-5162.165" + cell $and $and$ls180.v:5162$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5046$882_Y + connect \A $and$ls180.v:5162$981_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5046$883_Y + connect \Y $and$ls180.v:5162$982_Y end - attribute \src "ls180.v:5047.50-5047.127" - cell $and $and$ls180.v:5047$884 + attribute \src "ls180.v:5163.50-5163.127" + cell $and $and$ls180.v:5163$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239490,10 +256839,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5047$884_Y + connect \Y $and$ls180.v:5163$983_Y end - attribute \src "ls180.v:5049.48-5049.124" - cell $and $and$ls180.v:5049$885 + attribute \src "ls180.v:5165.48-5165.124" + cell $and $and$ls180.v:5165$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239501,21 +256850,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5049$885_Y + connect \Y $and$ls180.v:5165$984_Y end - attribute \src "ls180.v:5049.47-5049.165" - cell $and $and$ls180.v:5049$886 + attribute \src "ls180.v:5165.47-5165.165" + cell $and $and$ls180.v:5165$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5049$885_Y + connect \A $and$ls180.v:5165$984_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5049$886_Y + connect \Y $and$ls180.v:5165$985_Y end - attribute \src "ls180.v:5050.50-5050.127" - cell $and $and$ls180.v:5050$887 + attribute \src "ls180.v:5166.50-5166.127" + cell $and $and$ls180.v:5166$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239523,10 +256872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5050$887_Y + connect \Y $and$ls180.v:5166$986_Y end - attribute \src "ls180.v:5052.48-5052.124" - cell $and $and$ls180.v:5052$888 + attribute \src "ls180.v:5168.48-5168.124" + cell $and $and$ls180.v:5168$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239534,21 +256883,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5052$888_Y + connect \Y $and$ls180.v:5168$987_Y end - attribute \src "ls180.v:5052.47-5052.165" - cell $and $and$ls180.v:5052$889 + attribute \src "ls180.v:5168.47-5168.165" + cell $and $and$ls180.v:5168$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5052$888_Y + connect \A $and$ls180.v:5168$987_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5052$889_Y + connect \Y $and$ls180.v:5168$988_Y end - attribute \src "ls180.v:5053.50-5053.127" - cell $and $and$ls180.v:5053$890 + attribute \src "ls180.v:5169.50-5169.127" + cell $and $and$ls180.v:5169$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239556,10 +256905,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5053$890_Y + connect \Y $and$ls180.v:5169$989_Y end - attribute \src "ls180.v:5055.48-5055.124" - cell $and $and$ls180.v:5055$891 + attribute \src "ls180.v:5171.48-5171.124" + cell $and $and$ls180.v:5171$990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239567,21 +256916,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5055$891_Y + connect \Y $and$ls180.v:5171$990_Y end - attribute \src "ls180.v:5055.47-5055.165" - cell $and $and$ls180.v:5055$892 + attribute \src "ls180.v:5171.47-5171.165" + cell $and $and$ls180.v:5171$991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5055$891_Y + connect \A $and$ls180.v:5171$990_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5055$892_Y + connect \Y $and$ls180.v:5171$991_Y end - attribute \src "ls180.v:5056.50-5056.127" - cell $and $and$ls180.v:5056$893 + attribute \src "ls180.v:5172.50-5172.127" + cell $and $and$ls180.v:5172$992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239589,10 +256938,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5056$893_Y + connect \Y $and$ls180.v:5172$992_Y end - attribute \src "ls180.v:5169.10-5169.86" - cell $and $and$ls180.v:5169$942 + attribute \src "ls180.v:5285.10-5285.86" + cell $and $and$ls180.v:5285$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239600,54 +256949,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5169$942_Y + connect \Y $and$ls180.v:5285$1041_Y end - attribute \src "ls180.v:5169.9-5169.127" - cell $and $and$ls180.v:5169$943 + attribute \src "ls180.v:5285.9-5285.127" + cell $and $and$ls180.v:5285$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5169$942_Y + connect \A $and$ls180.v:5285$1041_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5169$943_Y + connect \Y $and$ls180.v:5285$1042_Y end - attribute \src "ls180.v:5179.9-5179.152" - cell $and $and$ls180.v:5179$947 + attribute \src "ls180.v:5295.9-5295.152" + cell $and $and$ls180.v:5295$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5179$945_Y - connect \B $eq$ls180.v:5179$946_Y - connect \Y $and$ls180.v:5179$947_Y + connect \A $eq$ls180.v:5295$1044_Y + connect \B $eq$ls180.v:5295$1045_Y + connect \Y $and$ls180.v:5295$1046_Y end - attribute \src "ls180.v:5179.8-5179.226" - cell $and $and$ls180.v:5179$949 + attribute \src "ls180.v:5295.8-5295.226" + cell $and $and$ls180.v:5295$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5179$947_Y - connect \B $eq$ls180.v:5179$948_Y - connect \Y $and$ls180.v:5179$949_Y + connect \A $and$ls180.v:5295$1046_Y + connect \B $eq$ls180.v:5295$1047_Y + connect \Y $and$ls180.v:5295$1048_Y end - attribute \src "ls180.v:5179.7-5179.300" - cell $and $and$ls180.v:5179$951 + attribute \src "ls180.v:5295.7-5295.300" + cell $and $and$ls180.v:5295$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5179$949_Y - connect \B $eq$ls180.v:5179$950_Y - connect \Y $and$ls180.v:5179$951_Y + connect \A $and$ls180.v:5295$1048_Y + connect \B $eq$ls180.v:5295$1049_Y + connect \Y $and$ls180.v:5295$1050_Y end - attribute \src "ls180.v:5184.49-5184.124" - cell $and $and$ls180.v:5184$952 + attribute \src "ls180.v:5300.49-5300.124" + cell $and $and$ls180.v:5300$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239655,10 +257004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5184$952_Y + connect \Y $and$ls180.v:5300$1051_Y end - attribute \src "ls180.v:5194.49-5194.124" - cell $and $and$ls180.v:5194$955 + attribute \src "ls180.v:5310.49-5310.124" + cell $and $and$ls180.v:5310$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239666,10 +257015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5194$955_Y + connect \Y $and$ls180.v:5310$1054_Y end - attribute \src "ls180.v:5204.49-5204.124" - cell $and $and$ls180.v:5204$958 + attribute \src "ls180.v:5320.49-5320.124" + cell $and $and$ls180.v:5320$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239677,10 +257026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5204$958_Y + connect \Y $and$ls180.v:5320$1057_Y end - attribute \src "ls180.v:5214.49-5214.124" - cell $and $and$ls180.v:5214$961 + attribute \src "ls180.v:5330.49-5330.124" + cell $and $and$ls180.v:5330$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239688,21 +257037,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5214$961_Y + connect \Y $and$ls180.v:5330$1060_Y end - attribute \src "ls180.v:5226.7-5226.84" - cell $and $and$ls180.v:5226$966 + attribute \src "ls180.v:5342.7-5342.84" + cell $and $and$ls180.v:5342$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5226$965_Y - connect \Y $and$ls180.v:5226$966_Y + connect \B $gt$ls180.v:5342$1064_Y + connect \Y $and$ls180.v:5342$1065_Y end - attribute \src "ls180.v:5344.9-5344.64" - cell $and $and$ls180.v:5344$1015 + attribute \src "ls180.v:5460.9-5460.64" + cell $and $and$ls180.v:5460$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239710,10 +257059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5344$1015_Y + connect \Y $and$ls180.v:5460$1114_Y end - attribute \src "ls180.v:5396.10-5396.66" - cell $and $and$ls180.v:5396$1024 + attribute \src "ls180.v:5512.10-5512.66" + cell $and $and$ls180.v:5512$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239721,21 +257070,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5396$1024_Y + connect \Y $and$ls180.v:5512$1123_Y end - attribute \src "ls180.v:5396.9-5396.97" - cell $and $and$ls180.v:5396$1025 + attribute \src "ls180.v:5512.9-5512.97" + cell $and $and$ls180.v:5512$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5396$1024_Y + connect \A $and$ls180.v:5512$1123_Y connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5396$1025_Y + connect \Y $and$ls180.v:5512$1124_Y end - attribute \src "ls180.v:5422.11-5422.71" - cell $and $and$ls180.v:5422$1033 + attribute \src "ls180.v:5538.11-5538.71" + cell $and $and$ls180.v:5538$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239743,21 +257092,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_last connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5422$1033_Y + connect \Y $and$ls180.v:5538$1132_Y end - attribute \src "ls180.v:5506.43-5506.152" - cell $and $and$ls180.v:5506$1041 + attribute \src "ls180.v:5622.43-5622.152" + cell $and $and$ls180.v:5622$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5506$1040_Y - connect \Y $and$ls180.v:5506$1041_Y + connect \B $or$ls180.v:5622$1139_Y + connect \Y $and$ls180.v:5622$1140_Y end - attribute \src "ls180.v:5507.41-5507.116" - cell $and $and$ls180.v:5507$1042 + attribute \src "ls180.v:5623.41-5623.116" + cell $and $and$ls180.v:5623$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239765,10 +257114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_readable connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5507$1042_Y + connect \Y $and$ls180.v:5623$1141_Y end - attribute \src "ls180.v:5519.48-5519.125" - cell $and $and$ls180.v:5519$1047 + attribute \src "ls180.v:5635.48-5635.125" + cell $and $and$ls180.v:5635$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239776,10 +257125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5519$1047_Y + connect \Y $and$ls180.v:5635$1146_Y end - attribute \src "ls180.v:5546.9-5546.102" - cell $and $and$ls180.v:5546$1051 + attribute \src "ls180.v:5662.9-5662.102" + cell $and $and$ls180.v:5662$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239787,10 +257136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5546$1051_Y + connect \Y $and$ls180.v:5662$1150_Y end - attribute \src "ls180.v:5619.9-5619.58" - cell $and $and$ls180.v:5619$1057 + attribute \src "ls180.v:5735.9-5735.58" + cell $and $and$ls180.v:5735$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239798,10 +257147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_bus_stb connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5619$1057_Y + connect \Y $and$ls180.v:5735$1156_Y end - attribute \src "ls180.v:5672.51-5672.123" - cell $and $and$ls180.v:5672$1065 + attribute \src "ls180.v:5788.51-5788.123" + cell $and $and$ls180.v:5788$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239809,10 +257158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_first connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5672$1065_Y + connect \Y $and$ls180.v:5788$1164_Y end - attribute \src "ls180.v:5673.50-5673.120" - cell $and $and$ls180.v:5673$1066 + attribute \src "ls180.v:5789.50-5789.120" + cell $and $and$ls180.v:5789$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239820,10 +257169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_last connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5673$1066_Y + connect \Y $and$ls180.v:5789$1165_Y end - attribute \src "ls180.v:5674.49-5674.122" - cell $and $and$ls180.v:5674$1067 + attribute \src "ls180.v:5790.49-5790.122" + cell $and $and$ls180.v:5790$1166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239831,21 +257180,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_last connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5674$1067_Y + connect \Y $and$ls180.v:5790$1166_Y end - attribute \src "ls180.v:5714.43-5714.152" - cell $and $and$ls180.v:5714$1072 + attribute \src "ls180.v:5842.43-5842.152" + cell $and $and$ls180.v:5842$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5714$1071_Y - connect \Y $and$ls180.v:5714$1072_Y + connect \B $or$ls180.v:5842$1170_Y + connect \Y $and$ls180.v:5842$1171_Y end - attribute \src "ls180.v:5715.41-5715.116" - cell $and $and$ls180.v:5715$1073 + attribute \src "ls180.v:5843.41-5843.116" + cell $and $and$ls180.v:5843$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239853,10 +257202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_readable connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5715$1073_Y + connect \Y $and$ls180.v:5843$1172_Y end - attribute \src "ls180.v:5747.9-5747.76" - cell $and $and$ls180.v:5747$1077 + attribute \src "ls180.v:5875.9-5875.76" + cell $and $and$ls180.v:5875$1176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239864,131 +257213,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_cyc connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5747$1077_Y + connect \Y $and$ls180.v:5875$1176_Y end - attribute \src "ls180.v:5750.44-5750.120" - cell $and $and$ls180.v:5750$1079 + attribute \src "ls180.v:5878.44-5878.120" + cell $and $and$ls180.v:5878$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5750$1078_Y - connect \Y $and$ls180.v:5750$1079_Y + connect \B $ne$ls180.v:5878$1177_Y + connect \Y $and$ls180.v:5878$1178_Y end - attribute \src "ls180.v:5770.63-5770.107" - cell $and $and$ls180.v:5770$1081 + attribute \src "ls180.v:5898.46-5898.90" + cell $and $and$ls180.v:5898$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5770$1080_Y - connect \Y $and$ls180.v:5770$1081_Y + connect \B $eq$ls180.v:5898$1179_Y + connect \Y $and$ls180.v:5898$1180_Y end - attribute \src "ls180.v:5771.63-5771.107" - cell $and $and$ls180.v:5771$1083 + attribute \src "ls180.v:5899.46-5899.90" + cell $and $and$ls180.v:5899$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5771$1082_Y - connect \Y $and$ls180.v:5771$1083_Y + connect \B $eq$ls180.v:5899$1181_Y + connect \Y $and$ls180.v:5899$1182_Y end - attribute \src "ls180.v:5772.63-5772.107" - cell $and $and$ls180.v:5772$1085 + attribute \src "ls180.v:5900.49-5900.93" + cell $and $and$ls180.v:5900$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5772$1084_Y - connect \Y $and$ls180.v:5772$1085_Y + connect \B $eq$ls180.v:5900$1183_Y + connect \Y $and$ls180.v:5900$1184_Y end - attribute \src "ls180.v:5773.35-5773.79" - cell $and $and$ls180.v:5773$1087 + attribute \src "ls180.v:5901.35-5901.79" + cell $and $and$ls180.v:5901$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5773$1086_Y - connect \Y $and$ls180.v:5773$1087_Y + connect \B $eq$ls180.v:5901$1185_Y + connect \Y $and$ls180.v:5901$1186_Y end - attribute \src "ls180.v:5774.35-5774.79" - cell $and $and$ls180.v:5774$1089 + attribute \src "ls180.v:5902.35-5902.79" + cell $and $and$ls180.v:5902$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5774$1088_Y - connect \Y $and$ls180.v:5774$1089_Y + connect \B $eq$ls180.v:5902$1187_Y + connect \Y $and$ls180.v:5902$1188_Y end - attribute \src "ls180.v:5775.63-5775.107" - cell $and $and$ls180.v:5775$1091 + attribute \src "ls180.v:5903.46-5903.90" + cell $and $and$ls180.v:5903$1190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5775$1090_Y - connect \Y $and$ls180.v:5775$1091_Y + connect \B $eq$ls180.v:5903$1189_Y + connect \Y $and$ls180.v:5903$1190_Y end - attribute \src "ls180.v:5776.63-5776.107" - cell $and $and$ls180.v:5776$1093 + attribute \src "ls180.v:5904.46-5904.90" + cell $and $and$ls180.v:5904$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5776$1092_Y - connect \Y $and$ls180.v:5776$1093_Y + connect \B $eq$ls180.v:5904$1191_Y + connect \Y $and$ls180.v:5904$1192_Y end - attribute \src "ls180.v:5777.63-5777.107" - cell $and $and$ls180.v:5777$1095 + attribute \src "ls180.v:5905.49-5905.93" + cell $and $and$ls180.v:5905$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5777$1094_Y - connect \Y $and$ls180.v:5777$1095_Y + connect \B $eq$ls180.v:5905$1193_Y + connect \Y $and$ls180.v:5905$1194_Y end - attribute \src "ls180.v:5778.35-5778.79" - cell $and $and$ls180.v:5778$1097 + attribute \src "ls180.v:5906.35-5906.79" + cell $and $and$ls180.v:5906$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5778$1096_Y - connect \Y $and$ls180.v:5778$1097_Y + connect \B $eq$ls180.v:5906$1195_Y + connect \Y $and$ls180.v:5906$1196_Y end - attribute \src "ls180.v:5779.35-5779.79" - cell $and $and$ls180.v:5779$1099 + attribute \src "ls180.v:5907.35-5907.79" + cell $and $and$ls180.v:5907$1198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5779$1098_Y - connect \Y $and$ls180.v:5779$1099_Y + connect \B $eq$ls180.v:5907$1197_Y + connect \Y $and$ls180.v:5907$1198_Y end - attribute \src "ls180.v:5848.40-5848.81" - cell $and $and$ls180.v:5848$1109 + attribute \src "ls180.v:6016.40-6016.81" + cell $and $and$ls180.v:6016$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239996,10 +257345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5848$1109_Y + connect \Y $and$ls180.v:6016$1213_Y end - attribute \src "ls180.v:5849.39-5849.80" - cell $and $and$ls180.v:5849$1110 + attribute \src "ls180.v:6017.39-6017.80" + cell $and $and$ls180.v:6017$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240007,10 +257356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5849$1110_Y + connect \Y $and$ls180.v:6017$1214_Y end - attribute \src "ls180.v:5850.39-5850.80" - cell $and $and$ls180.v:5850$1111 + attribute \src "ls180.v:6018.39-6018.80" + cell $and $and$ls180.v:6018$1215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240018,10 +257367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5850$1111_Y + connect \Y $and$ls180.v:6018$1215_Y end - attribute \src "ls180.v:5851.39-5851.80" - cell $and $and$ls180.v:5851$1112 + attribute \src "ls180.v:6019.39-6019.80" + cell $and $and$ls180.v:6019$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240029,10 +257378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5851$1112_Y + connect \Y $and$ls180.v:6019$1216_Y end - attribute \src "ls180.v:5852.50-5852.91" - cell $and $and$ls180.v:5852$1113 + attribute \src "ls180.v:6020.39-6020.80" + cell $and $and$ls180.v:6020$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240040,10 +257389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5852$1113_Y + connect \Y $and$ls180.v:6020$1217_Y end - attribute \src "ls180.v:5853.50-5853.91" - cell $and $and$ls180.v:5853$1114 + attribute \src "ls180.v:6021.51-6021.92" + cell $and $and$ls180.v:6021$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240051,10 +257400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [5] - connect \Y $and$ls180.v:5853$1114_Y + connect \Y $and$ls180.v:6021$1218_Y end - attribute \src "ls180.v:5854.29-5854.70" - cell $and $and$ls180.v:5854$1115 + attribute \src "ls180.v:6022.51-6022.92" + cell $and $and$ls180.v:6022$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240062,10 +257411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [6] - connect \Y $and$ls180.v:5854$1115_Y + connect \Y $and$ls180.v:6022$1219_Y end - attribute \src "ls180.v:5855.44-5855.85" - cell $and $and$ls180.v:5855$1116 + attribute \src "ls180.v:6023.52-6023.93" + cell $and $and$ls180.v:6023$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240073,10 +257422,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [7] - connect \Y $and$ls180.v:5855$1116_Y + connect \Y $and$ls180.v:6023$1220_Y end - attribute \src "ls180.v:5857.25-5857.64" - cell $and $and$ls180.v:5857$1124 + attribute \src "ls180.v:6024.52-6024.93" + cell $and $and$ls180.v:6024$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [8] + connect \Y $and$ls180.v:6024$1221_Y + end + attribute \src "ls180.v:6025.52-6025.93" + cell $and $and$ls180.v:6025$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [9] + connect \Y $and$ls180.v:6025$1222_Y + end + attribute \src "ls180.v:6026.52-6026.94" + cell $and $and$ls180.v:6026$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [10] + connect \Y $and$ls180.v:6026$1223_Y + end + attribute \src "ls180.v:6027.54-6027.96" + cell $and $and$ls180.v:6027$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [11] + connect \Y $and$ls180.v:6027$1224_Y + end + attribute \src "ls180.v:6028.55-6028.97" + cell $and $and$ls180.v:6028$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [12] + connect \Y $and$ls180.v:6028$1225_Y + end + attribute \src "ls180.v:6030.25-6030.64" + cell $and $and$ls180.v:6030$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240084,109 +257488,164 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_stb connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5857$1124_Y + connect \Y $and$ls180.v:6030$1238_Y end - attribute \src "ls180.v:5857.24-5857.89" - cell $and $and$ls180.v:5857$1126 + attribute \src "ls180.v:6030.24-6030.89" + cell $and $and$ls180.v:6030$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5857$1124_Y - connect \B $not$ls180.v:5857$1125_Y - connect \Y $and$ls180.v:5857$1126_Y + connect \A $and$ls180.v:6030$1238_Y + connect \B $not$ls180.v:6030$1239_Y + connect \Y $and$ls180.v:6030$1240_Y end - attribute \src "ls180.v:5863.34-5863.95" - cell $and $and$ls180.v:5863$1135 + attribute \src "ls180.v:6036.39-6036.100" + cell $and $and$ls180.v:6036$1254 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5863$1135_Y + connect \Y $and$ls180.v:6036$1254_Y end - attribute \src "ls180.v:5863.100-5863.160" - cell $and $and$ls180.v:5863$1136 + attribute \src "ls180.v:6036.105-6036.165" + cell $and $and$ls180.v:6036$1255 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } connect \B \main_interface0_ram_bus_dat_r - connect \Y $and$ls180.v:5863$1136_Y + connect \Y $and$ls180.v:6036$1255_Y end - attribute \src "ls180.v:5863.166-5863.226" - cell $and $and$ls180.v:5863$1138 + attribute \src "ls180.v:6036.171-6036.231" + cell $and $and$ls180.v:6036$1257 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } connect \B \main_interface1_ram_bus_dat_r - connect \Y $and$ls180.v:5863$1138_Y + connect \Y $and$ls180.v:6036$1257_Y end - attribute \src "ls180.v:5863.232-5863.292" - cell $and $and$ls180.v:5863$1140 + attribute \src "ls180.v:6036.237-6036.297" + cell $and $and$ls180.v:6036$1259 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } connect \B \main_interface2_ram_bus_dat_r - connect \Y $and$ls180.v:5863$1140_Y + connect \Y $and$ls180.v:6036$1259_Y end - attribute \src "ls180.v:5863.298-5863.369" - cell $and $and$ls180.v:5863$1142 + attribute \src "ls180.v:6036.303-6036.363" + cell $and $and$ls180.v:6036$1261 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \main_libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:5863$1142_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \main_interface3_ram_bus_dat_r + connect \Y $and$ls180.v:6036$1261_Y end - attribute \src "ls180.v:5863.375-5863.446" - cell $and $and$ls180.v:5863$1144 + attribute \src "ls180.v:6036.369-6036.441" + cell $and $and$ls180.v:6036$1263 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } - connect \B \main_libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:5863$1144_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } + connect \B \main_interface0_converted_interface_dat_r + connect \Y $and$ls180.v:6036$1263_Y end - attribute \src "ls180.v:5863.452-5863.502" - cell $and $and$ls180.v:5863$1146 + attribute \src "ls180.v:6036.447-6036.519" + cell $and $and$ls180.v:6036$1265 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } - connect \B \main_wb_sdram_dat_r - connect \Y $and$ls180.v:5863$1146_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } + connect \B \main_interface1_converted_interface_dat_r + connect \Y $and$ls180.v:6036$1265_Y end - attribute \src "ls180.v:5863.508-5863.573" - cell $and $and$ls180.v:5863$1148 + attribute \src "ls180.v:6036.525-6036.598" + cell $and $and$ls180.v:6036$1267 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } - connect \B \builder_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:5863$1148_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } + connect \B \main_libresocsim_libresoc_interface0_dat_r + connect \Y $and$ls180.v:6036$1267_Y + end + attribute \src "ls180.v:6036.604-6036.677" + cell $and $and$ls180.v:6036$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] } + connect \B \main_libresocsim_libresoc_interface1_dat_r + connect \Y $and$ls180.v:6036$1269_Y end - attribute \src "ls180.v:5873.39-5873.92" - cell $and $and$ls180.v:5873$1152 + attribute \src "ls180.v:6036.683-6036.756" + cell $and $and$ls180.v:6036$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] } + connect \B \main_libresocsim_libresoc_interface2_dat_r + connect \Y $and$ls180.v:6036$1271_Y + end + attribute \src "ls180.v:6036.762-6036.836" + cell $and $and$ls180.v:6036$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] } + connect \B \main_libresocsim_libresoc_interface3_dat_r + connect \Y $and$ls180.v:6036$1273_Y + end + attribute \src "ls180.v:6036.842-6036.918" + cell $and $and$ls180.v:6036$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] } + connect \B \main_socbushandler_converted_interface_dat_r + connect \Y $and$ls180.v:6036$1275_Y + end + attribute \src "ls180.v:6036.924-6036.1001" + cell $and $and$ls180.v:6036$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] } + connect \B \builder_libresocsim_converted_interface_dat_r + connect \Y $and$ls180.v:6036$1277_Y + end + attribute \src "ls180.v:6046.39-6046.92" + cell $and $and$ls180.v:6046$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240194,43 +257653,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5873$1152_Y + connect \Y $and$ls180.v:6046$1281_Y end - attribute \src "ls180.v:5873.38-5873.142" - cell $and $and$ls180.v:5873$1154 + attribute \src "ls180.v:6046.38-6046.142" + cell $and $and$ls180.v:6046$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5873$1152_Y - connect \B $eq$ls180.v:5873$1153_Y - connect \Y $and$ls180.v:5873$1154_Y + connect \A $and$ls180.v:6046$1281_Y + connect \B $eq$ls180.v:6046$1282_Y + connect \Y $and$ls180.v:6046$1283_Y end - attribute \src "ls180.v:5874.39-5874.95" - cell $and $and$ls180.v:5874$1156 + attribute \src "ls180.v:6047.39-6047.95" + cell $and $and$ls180.v:6047$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5874$1155_Y - connect \Y $and$ls180.v:5874$1156_Y + connect \B $not$ls180.v:6047$1284_Y + connect \Y $and$ls180.v:6047$1285_Y end - attribute \src "ls180.v:5874.38-5874.145" - cell $and $and$ls180.v:5874$1158 + attribute \src "ls180.v:6047.38-6047.145" + cell $and $and$ls180.v:6047$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1156_Y - connect \B $eq$ls180.v:5874$1157_Y - connect \Y $and$ls180.v:5874$1158_Y + connect \A $and$ls180.v:6047$1285_Y + connect \B $eq$ls180.v:6047$1286_Y + connect \Y $and$ls180.v:6047$1287_Y end - attribute \src "ls180.v:5876.41-5876.94" - cell $and $and$ls180.v:5876$1159 + attribute \src "ls180.v:6049.41-6049.94" + cell $and $and$ls180.v:6049$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240238,43 +257697,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5876$1159_Y + connect \Y $and$ls180.v:6049$1288_Y end - attribute \src "ls180.v:5876.40-5876.144" - cell $and $and$ls180.v:5876$1161 + attribute \src "ls180.v:6049.40-6049.144" + cell $and $and$ls180.v:6049$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5876$1159_Y - connect \B $eq$ls180.v:5876$1160_Y - connect \Y $and$ls180.v:5876$1161_Y + connect \A $and$ls180.v:6049$1288_Y + connect \B $eq$ls180.v:6049$1289_Y + connect \Y $and$ls180.v:6049$1290_Y end - attribute \src "ls180.v:5877.41-5877.97" - cell $and $and$ls180.v:5877$1163 + attribute \src "ls180.v:6050.41-6050.97" + cell $and $and$ls180.v:6050$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5877$1162_Y - connect \Y $and$ls180.v:5877$1163_Y + connect \B $not$ls180.v:6050$1291_Y + connect \Y $and$ls180.v:6050$1292_Y end - attribute \src "ls180.v:5877.40-5877.147" - cell $and $and$ls180.v:5877$1165 + attribute \src "ls180.v:6050.40-6050.147" + cell $and $and$ls180.v:6050$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5877$1163_Y - connect \B $eq$ls180.v:5877$1164_Y - connect \Y $and$ls180.v:5877$1165_Y + connect \A $and$ls180.v:6050$1292_Y + connect \B $eq$ls180.v:6050$1293_Y + connect \Y $and$ls180.v:6050$1294_Y end - attribute \src "ls180.v:5879.41-5879.94" - cell $and $and$ls180.v:5879$1166 + attribute \src "ls180.v:6052.41-6052.94" + cell $and $and$ls180.v:6052$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240282,43 +257741,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5879$1166_Y + connect \Y $and$ls180.v:6052$1295_Y end - attribute \src "ls180.v:5879.40-5879.144" - cell $and $and$ls180.v:5879$1168 + attribute \src "ls180.v:6052.40-6052.144" + cell $and $and$ls180.v:6052$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5879$1166_Y - connect \B $eq$ls180.v:5879$1167_Y - connect \Y $and$ls180.v:5879$1168_Y + connect \A $and$ls180.v:6052$1295_Y + connect \B $eq$ls180.v:6052$1296_Y + connect \Y $and$ls180.v:6052$1297_Y end - attribute \src "ls180.v:5880.41-5880.97" - cell $and $and$ls180.v:5880$1170 + attribute \src "ls180.v:6053.41-6053.97" + cell $and $and$ls180.v:6053$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5880$1169_Y - connect \Y $and$ls180.v:5880$1170_Y + connect \B $not$ls180.v:6053$1298_Y + connect \Y $and$ls180.v:6053$1299_Y end - attribute \src "ls180.v:5880.40-5880.147" - cell $and $and$ls180.v:5880$1172 + attribute \src "ls180.v:6053.40-6053.147" + cell $and $and$ls180.v:6053$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5880$1170_Y - connect \B $eq$ls180.v:5880$1171_Y - connect \Y $and$ls180.v:5880$1172_Y + connect \A $and$ls180.v:6053$1299_Y + connect \B $eq$ls180.v:6053$1300_Y + connect \Y $and$ls180.v:6053$1301_Y end - attribute \src "ls180.v:5882.41-5882.94" - cell $and $and$ls180.v:5882$1173 + attribute \src "ls180.v:6055.41-6055.94" + cell $and $and$ls180.v:6055$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240326,43 +257785,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5882$1173_Y + connect \Y $and$ls180.v:6055$1302_Y end - attribute \src "ls180.v:5882.40-5882.144" - cell $and $and$ls180.v:5882$1175 + attribute \src "ls180.v:6055.40-6055.144" + cell $and $and$ls180.v:6055$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5882$1173_Y - connect \B $eq$ls180.v:5882$1174_Y - connect \Y $and$ls180.v:5882$1175_Y + connect \A $and$ls180.v:6055$1302_Y + connect \B $eq$ls180.v:6055$1303_Y + connect \Y $and$ls180.v:6055$1304_Y end - attribute \src "ls180.v:5883.41-5883.97" - cell $and $and$ls180.v:5883$1177 + attribute \src "ls180.v:6056.41-6056.97" + cell $and $and$ls180.v:6056$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5883$1176_Y - connect \Y $and$ls180.v:5883$1177_Y + connect \B $not$ls180.v:6056$1305_Y + connect \Y $and$ls180.v:6056$1306_Y end - attribute \src "ls180.v:5883.40-5883.147" - cell $and $and$ls180.v:5883$1179 + attribute \src "ls180.v:6056.40-6056.147" + cell $and $and$ls180.v:6056$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5883$1177_Y - connect \B $eq$ls180.v:5883$1178_Y - connect \Y $and$ls180.v:5883$1179_Y + connect \A $and$ls180.v:6056$1306_Y + connect \B $eq$ls180.v:6056$1307_Y + connect \Y $and$ls180.v:6056$1308_Y end - attribute \src "ls180.v:5885.41-5885.94" - cell $and $and$ls180.v:5885$1180 + attribute \src "ls180.v:6058.41-6058.94" + cell $and $and$ls180.v:6058$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240370,43 +257829,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5885$1180_Y + connect \Y $and$ls180.v:6058$1309_Y end - attribute \src "ls180.v:5885.40-5885.144" - cell $and $and$ls180.v:5885$1182 + attribute \src "ls180.v:6058.40-6058.144" + cell $and $and$ls180.v:6058$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5885$1180_Y - connect \B $eq$ls180.v:5885$1181_Y - connect \Y $and$ls180.v:5885$1182_Y + connect \A $and$ls180.v:6058$1309_Y + connect \B $eq$ls180.v:6058$1310_Y + connect \Y $and$ls180.v:6058$1311_Y end - attribute \src "ls180.v:5886.41-5886.97" - cell $and $and$ls180.v:5886$1184 + attribute \src "ls180.v:6059.41-6059.97" + cell $and $and$ls180.v:6059$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5886$1183_Y - connect \Y $and$ls180.v:5886$1184_Y + connect \B $not$ls180.v:6059$1312_Y + connect \Y $and$ls180.v:6059$1313_Y end - attribute \src "ls180.v:5886.40-5886.147" - cell $and $and$ls180.v:5886$1186 + attribute \src "ls180.v:6059.40-6059.147" + cell $and $and$ls180.v:6059$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5886$1184_Y - connect \B $eq$ls180.v:5886$1185_Y - connect \Y $and$ls180.v:5886$1186_Y + connect \A $and$ls180.v:6059$1313_Y + connect \B $eq$ls180.v:6059$1314_Y + connect \Y $and$ls180.v:6059$1315_Y end - attribute \src "ls180.v:5888.44-5888.97" - cell $and $and$ls180.v:5888$1187 + attribute \src "ls180.v:6061.44-6061.97" + cell $and $and$ls180.v:6061$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240414,43 +257873,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5888$1187_Y + connect \Y $and$ls180.v:6061$1316_Y end - attribute \src "ls180.v:5888.43-5888.147" - cell $and $and$ls180.v:5888$1189 + attribute \src "ls180.v:6061.43-6061.147" + cell $and $and$ls180.v:6061$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5888$1187_Y - connect \B $eq$ls180.v:5888$1188_Y - connect \Y $and$ls180.v:5888$1189_Y + connect \A $and$ls180.v:6061$1316_Y + connect \B $eq$ls180.v:6061$1317_Y + connect \Y $and$ls180.v:6061$1318_Y end - attribute \src "ls180.v:5889.44-5889.100" - cell $and $and$ls180.v:5889$1191 + attribute \src "ls180.v:6062.44-6062.100" + cell $and $and$ls180.v:6062$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5889$1190_Y - connect \Y $and$ls180.v:5889$1191_Y + connect \B $not$ls180.v:6062$1319_Y + connect \Y $and$ls180.v:6062$1320_Y end - attribute \src "ls180.v:5889.43-5889.150" - cell $and $and$ls180.v:5889$1193 + attribute \src "ls180.v:6062.43-6062.150" + cell $and $and$ls180.v:6062$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5889$1191_Y - connect \B $eq$ls180.v:5889$1192_Y - connect \Y $and$ls180.v:5889$1193_Y + connect \A $and$ls180.v:6062$1320_Y + connect \B $eq$ls180.v:6062$1321_Y + connect \Y $and$ls180.v:6062$1322_Y end - attribute \src "ls180.v:5891.44-5891.97" - cell $and $and$ls180.v:5891$1194 + attribute \src "ls180.v:6064.44-6064.97" + cell $and $and$ls180.v:6064$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240458,43 +257917,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5891$1194_Y + connect \Y $and$ls180.v:6064$1323_Y end - attribute \src "ls180.v:5891.43-5891.147" - cell $and $and$ls180.v:5891$1196 + attribute \src "ls180.v:6064.43-6064.147" + cell $and $and$ls180.v:6064$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5891$1194_Y - connect \B $eq$ls180.v:5891$1195_Y - connect \Y $and$ls180.v:5891$1196_Y + connect \A $and$ls180.v:6064$1323_Y + connect \B $eq$ls180.v:6064$1324_Y + connect \Y $and$ls180.v:6064$1325_Y end - attribute \src "ls180.v:5892.44-5892.100" - cell $and $and$ls180.v:5892$1198 + attribute \src "ls180.v:6065.44-6065.100" + cell $and $and$ls180.v:6065$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5892$1197_Y - connect \Y $and$ls180.v:5892$1198_Y + connect \B $not$ls180.v:6065$1326_Y + connect \Y $and$ls180.v:6065$1327_Y end - attribute \src "ls180.v:5892.43-5892.150" - cell $and $and$ls180.v:5892$1200 + attribute \src "ls180.v:6065.43-6065.150" + cell $and $and$ls180.v:6065$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5892$1198_Y - connect \B $eq$ls180.v:5892$1199_Y - connect \Y $and$ls180.v:5892$1200_Y + connect \A $and$ls180.v:6065$1327_Y + connect \B $eq$ls180.v:6065$1328_Y + connect \Y $and$ls180.v:6065$1329_Y end - attribute \src "ls180.v:5894.44-5894.97" - cell $and $and$ls180.v:5894$1201 + attribute \src "ls180.v:6067.44-6067.97" + cell $and $and$ls180.v:6067$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240502,43 +257961,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5894$1201_Y + connect \Y $and$ls180.v:6067$1330_Y end - attribute \src "ls180.v:5894.43-5894.147" - cell $and $and$ls180.v:5894$1203 + attribute \src "ls180.v:6067.43-6067.147" + cell $and $and$ls180.v:6067$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5894$1201_Y - connect \B $eq$ls180.v:5894$1202_Y - connect \Y $and$ls180.v:5894$1203_Y + connect \A $and$ls180.v:6067$1330_Y + connect \B $eq$ls180.v:6067$1331_Y + connect \Y $and$ls180.v:6067$1332_Y end - attribute \src "ls180.v:5895.44-5895.100" - cell $and $and$ls180.v:5895$1205 + attribute \src "ls180.v:6068.44-6068.100" + cell $and $and$ls180.v:6068$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5895$1204_Y - connect \Y $and$ls180.v:5895$1205_Y + connect \B $not$ls180.v:6068$1333_Y + connect \Y $and$ls180.v:6068$1334_Y end - attribute \src "ls180.v:5895.43-5895.150" - cell $and $and$ls180.v:5895$1207 + attribute \src "ls180.v:6068.43-6068.150" + cell $and $and$ls180.v:6068$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5895$1205_Y - connect \B $eq$ls180.v:5895$1206_Y - connect \Y $and$ls180.v:5895$1207_Y + connect \A $and$ls180.v:6068$1334_Y + connect \B $eq$ls180.v:6068$1335_Y + connect \Y $and$ls180.v:6068$1336_Y end - attribute \src "ls180.v:5897.44-5897.97" - cell $and $and$ls180.v:5897$1208 + attribute \src "ls180.v:6070.44-6070.97" + cell $and $and$ls180.v:6070$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240546,43 +258005,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5897$1208_Y + connect \Y $and$ls180.v:6070$1337_Y end - attribute \src "ls180.v:5897.43-5897.147" - cell $and $and$ls180.v:5897$1210 + attribute \src "ls180.v:6070.43-6070.147" + cell $and $and$ls180.v:6070$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5897$1208_Y - connect \B $eq$ls180.v:5897$1209_Y - connect \Y $and$ls180.v:5897$1210_Y + connect \A $and$ls180.v:6070$1337_Y + connect \B $eq$ls180.v:6070$1338_Y + connect \Y $and$ls180.v:6070$1339_Y end - attribute \src "ls180.v:5898.44-5898.100" - cell $and $and$ls180.v:5898$1212 + attribute \src "ls180.v:6071.44-6071.100" + cell $and $and$ls180.v:6071$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5898$1211_Y - connect \Y $and$ls180.v:5898$1212_Y + connect \B $not$ls180.v:6071$1340_Y + connect \Y $and$ls180.v:6071$1341_Y end - attribute \src "ls180.v:5898.43-5898.150" - cell $and $and$ls180.v:5898$1214 + attribute \src "ls180.v:6071.43-6071.150" + cell $and $and$ls180.v:6071$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5898$1212_Y - connect \B $eq$ls180.v:5898$1213_Y - connect \Y $and$ls180.v:5898$1214_Y + connect \A $and$ls180.v:6071$1341_Y + connect \B $eq$ls180.v:6071$1342_Y + connect \Y $and$ls180.v:6071$1343_Y end - attribute \src "ls180.v:5911.36-5911.89" - cell $and $and$ls180.v:5911$1216 + attribute \src "ls180.v:6084.36-6084.89" + cell $and $and$ls180.v:6084$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240590,43 +258049,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5911$1216_Y + connect \Y $and$ls180.v:6084$1345_Y end - attribute \src "ls180.v:5911.35-5911.139" - cell $and $and$ls180.v:5911$1218 + attribute \src "ls180.v:6084.35-6084.139" + cell $and $and$ls180.v:6084$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5911$1216_Y - connect \B $eq$ls180.v:5911$1217_Y - connect \Y $and$ls180.v:5911$1218_Y + connect \A $and$ls180.v:6084$1345_Y + connect \B $eq$ls180.v:6084$1346_Y + connect \Y $and$ls180.v:6084$1347_Y end - attribute \src "ls180.v:5912.36-5912.92" - cell $and $and$ls180.v:5912$1220 + attribute \src "ls180.v:6085.36-6085.92" + cell $and $and$ls180.v:6085$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5912$1219_Y - connect \Y $and$ls180.v:5912$1220_Y + connect \B $not$ls180.v:6085$1348_Y + connect \Y $and$ls180.v:6085$1349_Y end - attribute \src "ls180.v:5912.35-5912.142" - cell $and $and$ls180.v:5912$1222 + attribute \src "ls180.v:6085.35-6085.142" + cell $and $and$ls180.v:6085$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5912$1220_Y - connect \B $eq$ls180.v:5912$1221_Y - connect \Y $and$ls180.v:5912$1222_Y + connect \A $and$ls180.v:6085$1349_Y + connect \B $eq$ls180.v:6085$1350_Y + connect \Y $and$ls180.v:6085$1351_Y end - attribute \src "ls180.v:5914.36-5914.89" - cell $and $and$ls180.v:5914$1223 + attribute \src "ls180.v:6087.36-6087.89" + cell $and $and$ls180.v:6087$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240634,43 +258093,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5914$1223_Y + connect \Y $and$ls180.v:6087$1352_Y end - attribute \src "ls180.v:5914.35-5914.139" - cell $and $and$ls180.v:5914$1225 + attribute \src "ls180.v:6087.35-6087.139" + cell $and $and$ls180.v:6087$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5914$1223_Y - connect \B $eq$ls180.v:5914$1224_Y - connect \Y $and$ls180.v:5914$1225_Y + connect \A $and$ls180.v:6087$1352_Y + connect \B $eq$ls180.v:6087$1353_Y + connect \Y $and$ls180.v:6087$1354_Y end - attribute \src "ls180.v:5915.36-5915.92" - cell $and $and$ls180.v:5915$1227 + attribute \src "ls180.v:6088.36-6088.92" + cell $and $and$ls180.v:6088$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5915$1226_Y - connect \Y $and$ls180.v:5915$1227_Y + connect \B $not$ls180.v:6088$1355_Y + connect \Y $and$ls180.v:6088$1356_Y end - attribute \src "ls180.v:5915.35-5915.142" - cell $and $and$ls180.v:5915$1229 + attribute \src "ls180.v:6088.35-6088.142" + cell $and $and$ls180.v:6088$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5915$1227_Y - connect \B $eq$ls180.v:5915$1228_Y - connect \Y $and$ls180.v:5915$1229_Y + connect \A $and$ls180.v:6088$1356_Y + connect \B $eq$ls180.v:6088$1357_Y + connect \Y $and$ls180.v:6088$1358_Y end - attribute \src "ls180.v:5917.36-5917.89" - cell $and $and$ls180.v:5917$1230 + attribute \src "ls180.v:6090.36-6090.89" + cell $and $and$ls180.v:6090$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240678,43 +258137,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5917$1230_Y + connect \Y $and$ls180.v:6090$1359_Y end - attribute \src "ls180.v:5917.35-5917.139" - cell $and $and$ls180.v:5917$1232 + attribute \src "ls180.v:6090.35-6090.139" + cell $and $and$ls180.v:6090$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5917$1230_Y - connect \B $eq$ls180.v:5917$1231_Y - connect \Y $and$ls180.v:5917$1232_Y + connect \A $and$ls180.v:6090$1359_Y + connect \B $eq$ls180.v:6090$1360_Y + connect \Y $and$ls180.v:6090$1361_Y end - attribute \src "ls180.v:5918.36-5918.92" - cell $and $and$ls180.v:5918$1234 + attribute \src "ls180.v:6091.36-6091.92" + cell $and $and$ls180.v:6091$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5918$1233_Y - connect \Y $and$ls180.v:5918$1234_Y + connect \B $not$ls180.v:6091$1362_Y + connect \Y $and$ls180.v:6091$1363_Y end - attribute \src "ls180.v:5918.35-5918.142" - cell $and $and$ls180.v:5918$1236 + attribute \src "ls180.v:6091.35-6091.142" + cell $and $and$ls180.v:6091$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5918$1234_Y - connect \B $eq$ls180.v:5918$1235_Y - connect \Y $and$ls180.v:5918$1236_Y + connect \A $and$ls180.v:6091$1363_Y + connect \B $eq$ls180.v:6091$1364_Y + connect \Y $and$ls180.v:6091$1365_Y end - attribute \src "ls180.v:5920.36-5920.89" - cell $and $and$ls180.v:5920$1237 + attribute \src "ls180.v:6093.36-6093.89" + cell $and $and$ls180.v:6093$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240722,43 +258181,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5920$1237_Y + connect \Y $and$ls180.v:6093$1366_Y end - attribute \src "ls180.v:5920.35-5920.139" - cell $and $and$ls180.v:5920$1239 + attribute \src "ls180.v:6093.35-6093.139" + cell $and $and$ls180.v:6093$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5920$1237_Y - connect \B $eq$ls180.v:5920$1238_Y - connect \Y $and$ls180.v:5920$1239_Y + connect \A $and$ls180.v:6093$1366_Y + connect \B $eq$ls180.v:6093$1367_Y + connect \Y $and$ls180.v:6093$1368_Y end - attribute \src "ls180.v:5921.36-5921.92" - cell $and $and$ls180.v:5921$1241 + attribute \src "ls180.v:6094.36-6094.92" + cell $and $and$ls180.v:6094$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5921$1240_Y - connect \Y $and$ls180.v:5921$1241_Y + connect \B $not$ls180.v:6094$1369_Y + connect \Y $and$ls180.v:6094$1370_Y end - attribute \src "ls180.v:5921.35-5921.142" - cell $and $and$ls180.v:5921$1243 + attribute \src "ls180.v:6094.35-6094.142" + cell $and $and$ls180.v:6094$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5921$1241_Y - connect \B $eq$ls180.v:5921$1242_Y - connect \Y $and$ls180.v:5921$1243_Y + connect \A $and$ls180.v:6094$1370_Y + connect \B $eq$ls180.v:6094$1371_Y + connect \Y $and$ls180.v:6094$1372_Y end - attribute \src "ls180.v:5923.37-5923.90" - cell $and $and$ls180.v:5923$1244 + attribute \src "ls180.v:6096.37-6096.90" + cell $and $and$ls180.v:6096$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240766,43 +258225,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5923$1244_Y + connect \Y $and$ls180.v:6096$1373_Y end - attribute \src "ls180.v:5923.36-5923.140" - cell $and $and$ls180.v:5923$1246 + attribute \src "ls180.v:6096.36-6096.140" + cell $and $and$ls180.v:6096$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5923$1244_Y - connect \B $eq$ls180.v:5923$1245_Y - connect \Y $and$ls180.v:5923$1246_Y + connect \A $and$ls180.v:6096$1373_Y + connect \B $eq$ls180.v:6096$1374_Y + connect \Y $and$ls180.v:6096$1375_Y end - attribute \src "ls180.v:5924.37-5924.93" - cell $and $and$ls180.v:5924$1248 + attribute \src "ls180.v:6097.37-6097.93" + cell $and $and$ls180.v:6097$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5924$1247_Y - connect \Y $and$ls180.v:5924$1248_Y + connect \B $not$ls180.v:6097$1376_Y + connect \Y $and$ls180.v:6097$1377_Y end - attribute \src "ls180.v:5924.36-5924.143" - cell $and $and$ls180.v:5924$1250 + attribute \src "ls180.v:6097.36-6097.143" + cell $and $and$ls180.v:6097$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5924$1248_Y - connect \B $eq$ls180.v:5924$1249_Y - connect \Y $and$ls180.v:5924$1250_Y + connect \A $and$ls180.v:6097$1377_Y + connect \B $eq$ls180.v:6097$1378_Y + connect \Y $and$ls180.v:6097$1379_Y end - attribute \src "ls180.v:5926.37-5926.90" - cell $and $and$ls180.v:5926$1251 + attribute \src "ls180.v:6099.37-6099.90" + cell $and $and$ls180.v:6099$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240810,43 +258269,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5926$1251_Y + connect \Y $and$ls180.v:6099$1380_Y end - attribute \src "ls180.v:5926.36-5926.140" - cell $and $and$ls180.v:5926$1253 + attribute \src "ls180.v:6099.36-6099.140" + cell $and $and$ls180.v:6099$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5926$1251_Y - connect \B $eq$ls180.v:5926$1252_Y - connect \Y $and$ls180.v:5926$1253_Y + connect \A $and$ls180.v:6099$1380_Y + connect \B $eq$ls180.v:6099$1381_Y + connect \Y $and$ls180.v:6099$1382_Y end - attribute \src "ls180.v:5927.37-5927.93" - cell $and $and$ls180.v:5927$1255 + attribute \src "ls180.v:6100.37-6100.93" + cell $and $and$ls180.v:6100$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5927$1254_Y - connect \Y $and$ls180.v:5927$1255_Y + connect \B $not$ls180.v:6100$1383_Y + connect \Y $and$ls180.v:6100$1384_Y end - attribute \src "ls180.v:5927.36-5927.143" - cell $and $and$ls180.v:5927$1257 + attribute \src "ls180.v:6100.36-6100.143" + cell $and $and$ls180.v:6100$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5927$1255_Y - connect \B $eq$ls180.v:5927$1256_Y - connect \Y $and$ls180.v:5927$1257_Y + connect \A $and$ls180.v:6100$1384_Y + connect \B $eq$ls180.v:6100$1385_Y + connect \Y $and$ls180.v:6100$1386_Y end - attribute \src "ls180.v:5937.35-5937.88" - cell $and $and$ls180.v:5937$1259 + attribute \src "ls180.v:6110.35-6110.88" + cell $and $and$ls180.v:6110$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240854,43 +258313,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5937$1259_Y + connect \Y $and$ls180.v:6110$1388_Y end - attribute \src "ls180.v:5937.34-5937.136" - cell $and $and$ls180.v:5937$1261 + attribute \src "ls180.v:6110.34-6110.136" + cell $and $and$ls180.v:6110$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5937$1259_Y - connect \B $eq$ls180.v:5937$1260_Y - connect \Y $and$ls180.v:5937$1261_Y + connect \A $and$ls180.v:6110$1388_Y + connect \B $eq$ls180.v:6110$1389_Y + connect \Y $and$ls180.v:6110$1390_Y end - attribute \src "ls180.v:5938.35-5938.91" - cell $and $and$ls180.v:5938$1263 + attribute \src "ls180.v:6111.35-6111.91" + cell $and $and$ls180.v:6111$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5938$1262_Y - connect \Y $and$ls180.v:5938$1263_Y + connect \B $not$ls180.v:6111$1391_Y + connect \Y $and$ls180.v:6111$1392_Y end - attribute \src "ls180.v:5938.34-5938.139" - cell $and $and$ls180.v:5938$1265 + attribute \src "ls180.v:6111.34-6111.139" + cell $and $and$ls180.v:6111$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5938$1263_Y - connect \B $eq$ls180.v:5938$1264_Y - connect \Y $and$ls180.v:5938$1265_Y + connect \A $and$ls180.v:6111$1392_Y + connect \B $eq$ls180.v:6111$1393_Y + connect \Y $and$ls180.v:6111$1394_Y end - attribute \src "ls180.v:5940.34-5940.87" - cell $and $and$ls180.v:5940$1266 + attribute \src "ls180.v:6113.34-6113.87" + cell $and $and$ls180.v:6113$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240898,43 +258357,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5940$1266_Y + connect \Y $and$ls180.v:6113$1395_Y end - attribute \src "ls180.v:5940.33-5940.135" - cell $and $and$ls180.v:5940$1268 + attribute \src "ls180.v:6113.33-6113.135" + cell $and $and$ls180.v:6113$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5940$1266_Y - connect \B $eq$ls180.v:5940$1267_Y - connect \Y $and$ls180.v:5940$1268_Y + connect \A $and$ls180.v:6113$1395_Y + connect \B $eq$ls180.v:6113$1396_Y + connect \Y $and$ls180.v:6113$1397_Y end - attribute \src "ls180.v:5941.34-5941.90" - cell $and $and$ls180.v:5941$1270 + attribute \src "ls180.v:6114.34-6114.90" + cell $and $and$ls180.v:6114$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5941$1269_Y - connect \Y $and$ls180.v:5941$1270_Y + connect \B $not$ls180.v:6114$1398_Y + connect \Y $and$ls180.v:6114$1399_Y end - attribute \src "ls180.v:5941.33-5941.138" - cell $and $and$ls180.v:5941$1272 + attribute \src "ls180.v:6114.33-6114.138" + cell $and $and$ls180.v:6114$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5941$1270_Y - connect \B $eq$ls180.v:5941$1271_Y - connect \Y $and$ls180.v:5941$1272_Y + connect \A $and$ls180.v:6114$1399_Y + connect \B $eq$ls180.v:6114$1400_Y + connect \Y $and$ls180.v:6114$1401_Y end - attribute \src "ls180.v:5951.40-5951.93" - cell $and $and$ls180.v:5951$1274 + attribute \src "ls180.v:6124.40-6124.93" + cell $and $and$ls180.v:6124$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240942,43 +258401,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5951$1274_Y + connect \Y $and$ls180.v:6124$1403_Y end - attribute \src "ls180.v:5951.39-5951.143" - cell $and $and$ls180.v:5951$1276 + attribute \src "ls180.v:6124.39-6124.143" + cell $and $and$ls180.v:6124$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5951$1274_Y - connect \B $eq$ls180.v:5951$1275_Y - connect \Y $and$ls180.v:5951$1276_Y + connect \A $and$ls180.v:6124$1403_Y + connect \B $eq$ls180.v:6124$1404_Y + connect \Y $and$ls180.v:6124$1405_Y end - attribute \src "ls180.v:5952.40-5952.96" - cell $and $and$ls180.v:5952$1278 + attribute \src "ls180.v:6125.40-6125.96" + cell $and $and$ls180.v:6125$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5952$1277_Y - connect \Y $and$ls180.v:5952$1278_Y + connect \B $not$ls180.v:6125$1406_Y + connect \Y $and$ls180.v:6125$1407_Y end - attribute \src "ls180.v:5952.39-5952.146" - cell $and $and$ls180.v:5952$1280 + attribute \src "ls180.v:6125.39-6125.146" + cell $and $and$ls180.v:6125$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5952$1278_Y - connect \B $eq$ls180.v:5952$1279_Y - connect \Y $and$ls180.v:5952$1280_Y + connect \A $and$ls180.v:6125$1407_Y + connect \B $eq$ls180.v:6125$1408_Y + connect \Y $and$ls180.v:6125$1409_Y end - attribute \src "ls180.v:5954.39-5954.92" - cell $and $and$ls180.v:5954$1281 + attribute \src "ls180.v:6127.39-6127.92" + cell $and $and$ls180.v:6127$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240986,43 +258445,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5954$1281_Y + connect \Y $and$ls180.v:6127$1410_Y end - attribute \src "ls180.v:5954.38-5954.142" - cell $and $and$ls180.v:5954$1283 + attribute \src "ls180.v:6127.38-6127.142" + cell $and $and$ls180.v:6127$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5954$1281_Y - connect \B $eq$ls180.v:5954$1282_Y - connect \Y $and$ls180.v:5954$1283_Y + connect \A $and$ls180.v:6127$1410_Y + connect \B $eq$ls180.v:6127$1411_Y + connect \Y $and$ls180.v:6127$1412_Y end - attribute \src "ls180.v:5955.39-5955.95" - cell $and $and$ls180.v:5955$1285 + attribute \src "ls180.v:6128.39-6128.95" + cell $and $and$ls180.v:6128$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5955$1284_Y - connect \Y $and$ls180.v:5955$1285_Y + connect \B $not$ls180.v:6128$1413_Y + connect \Y $and$ls180.v:6128$1414_Y end - attribute \src "ls180.v:5955.38-5955.145" - cell $and $and$ls180.v:5955$1287 + attribute \src "ls180.v:6128.38-6128.145" + cell $and $and$ls180.v:6128$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5955$1285_Y - connect \B $eq$ls180.v:5955$1286_Y - connect \Y $and$ls180.v:5955$1287_Y + connect \A $and$ls180.v:6128$1414_Y + connect \B $eq$ls180.v:6128$1415_Y + connect \Y $and$ls180.v:6128$1416_Y end - attribute \src "ls180.v:5957.39-5957.92" - cell $and $and$ls180.v:5957$1288 + attribute \src "ls180.v:6130.39-6130.92" + cell $and $and$ls180.v:6130$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241030,43 +258489,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5957$1288_Y + connect \Y $and$ls180.v:6130$1417_Y end - attribute \src "ls180.v:5957.38-5957.142" - cell $and $and$ls180.v:5957$1290 + attribute \src "ls180.v:6130.38-6130.142" + cell $and $and$ls180.v:6130$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5957$1288_Y - connect \B $eq$ls180.v:5957$1289_Y - connect \Y $and$ls180.v:5957$1290_Y + connect \A $and$ls180.v:6130$1417_Y + connect \B $eq$ls180.v:6130$1418_Y + connect \Y $and$ls180.v:6130$1419_Y end - attribute \src "ls180.v:5958.39-5958.95" - cell $and $and$ls180.v:5958$1292 + attribute \src "ls180.v:6131.39-6131.95" + cell $and $and$ls180.v:6131$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5958$1291_Y - connect \Y $and$ls180.v:5958$1292_Y + connect \B $not$ls180.v:6131$1420_Y + connect \Y $and$ls180.v:6131$1421_Y end - attribute \src "ls180.v:5958.38-5958.145" - cell $and $and$ls180.v:5958$1294 + attribute \src "ls180.v:6131.38-6131.145" + cell $and $and$ls180.v:6131$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5958$1292_Y - connect \B $eq$ls180.v:5958$1293_Y - connect \Y $and$ls180.v:5958$1294_Y + connect \A $and$ls180.v:6131$1421_Y + connect \B $eq$ls180.v:6131$1422_Y + connect \Y $and$ls180.v:6131$1423_Y end - attribute \src "ls180.v:5960.39-5960.92" - cell $and $and$ls180.v:5960$1295 + attribute \src "ls180.v:6133.39-6133.92" + cell $and $and$ls180.v:6133$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241074,43 +258533,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5960$1295_Y + connect \Y $and$ls180.v:6133$1424_Y end - attribute \src "ls180.v:5960.38-5960.142" - cell $and $and$ls180.v:5960$1297 + attribute \src "ls180.v:6133.38-6133.142" + cell $and $and$ls180.v:6133$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5960$1295_Y - connect \B $eq$ls180.v:5960$1296_Y - connect \Y $and$ls180.v:5960$1297_Y + connect \A $and$ls180.v:6133$1424_Y + connect \B $eq$ls180.v:6133$1425_Y + connect \Y $and$ls180.v:6133$1426_Y end - attribute \src "ls180.v:5961.39-5961.95" - cell $and $and$ls180.v:5961$1299 + attribute \src "ls180.v:6134.39-6134.95" + cell $and $and$ls180.v:6134$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5961$1298_Y - connect \Y $and$ls180.v:5961$1299_Y + connect \B $not$ls180.v:6134$1427_Y + connect \Y $and$ls180.v:6134$1428_Y end - attribute \src "ls180.v:5961.38-5961.145" - cell $and $and$ls180.v:5961$1301 + attribute \src "ls180.v:6134.38-6134.145" + cell $and $and$ls180.v:6134$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5961$1299_Y - connect \B $eq$ls180.v:5961$1300_Y - connect \Y $and$ls180.v:5961$1301_Y + connect \A $and$ls180.v:6134$1428_Y + connect \B $eq$ls180.v:6134$1429_Y + connect \Y $and$ls180.v:6134$1430_Y end - attribute \src "ls180.v:5963.39-5963.92" - cell $and $and$ls180.v:5963$1302 + attribute \src "ls180.v:6136.39-6136.92" + cell $and $and$ls180.v:6136$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241118,43 +258577,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5963$1302_Y + connect \Y $and$ls180.v:6136$1431_Y end - attribute \src "ls180.v:5963.38-5963.142" - cell $and $and$ls180.v:5963$1304 + attribute \src "ls180.v:6136.38-6136.142" + cell $and $and$ls180.v:6136$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5963$1302_Y - connect \B $eq$ls180.v:5963$1303_Y - connect \Y $and$ls180.v:5963$1304_Y + connect \A $and$ls180.v:6136$1431_Y + connect \B $eq$ls180.v:6136$1432_Y + connect \Y $and$ls180.v:6136$1433_Y end - attribute \src "ls180.v:5964.39-5964.95" - cell $and $and$ls180.v:5964$1306 + attribute \src "ls180.v:6137.39-6137.95" + cell $and $and$ls180.v:6137$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5964$1305_Y - connect \Y $and$ls180.v:5964$1306_Y + connect \B $not$ls180.v:6137$1434_Y + connect \Y $and$ls180.v:6137$1435_Y end - attribute \src "ls180.v:5964.38-5964.145" - cell $and $and$ls180.v:5964$1308 + attribute \src "ls180.v:6137.38-6137.145" + cell $and $and$ls180.v:6137$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5964$1306_Y - connect \B $eq$ls180.v:5964$1307_Y - connect \Y $and$ls180.v:5964$1308_Y + connect \A $and$ls180.v:6137$1435_Y + connect \B $eq$ls180.v:6137$1436_Y + connect \Y $and$ls180.v:6137$1437_Y end - attribute \src "ls180.v:5966.40-5966.93" - cell $and $and$ls180.v:5966$1309 + attribute \src "ls180.v:6139.40-6139.93" + cell $and $and$ls180.v:6139$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241162,43 +258621,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5966$1309_Y + connect \Y $and$ls180.v:6139$1438_Y end - attribute \src "ls180.v:5966.39-5966.143" - cell $and $and$ls180.v:5966$1311 + attribute \src "ls180.v:6139.39-6139.143" + cell $and $and$ls180.v:6139$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5966$1309_Y - connect \B $eq$ls180.v:5966$1310_Y - connect \Y $and$ls180.v:5966$1311_Y + connect \A $and$ls180.v:6139$1438_Y + connect \B $eq$ls180.v:6139$1439_Y + connect \Y $and$ls180.v:6139$1440_Y end - attribute \src "ls180.v:5967.40-5967.96" - cell $and $and$ls180.v:5967$1313 + attribute \src "ls180.v:6140.40-6140.96" + cell $and $and$ls180.v:6140$1442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5967$1312_Y - connect \Y $and$ls180.v:5967$1313_Y + connect \B $not$ls180.v:6140$1441_Y + connect \Y $and$ls180.v:6140$1442_Y end - attribute \src "ls180.v:5967.39-5967.146" - cell $and $and$ls180.v:5967$1315 + attribute \src "ls180.v:6140.39-6140.146" + cell $and $and$ls180.v:6140$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5967$1313_Y - connect \B $eq$ls180.v:5967$1314_Y - connect \Y $and$ls180.v:5967$1315_Y + connect \A $and$ls180.v:6140$1442_Y + connect \B $eq$ls180.v:6140$1443_Y + connect \Y $and$ls180.v:6140$1444_Y end - attribute \src "ls180.v:5969.40-5969.93" - cell $and $and$ls180.v:5969$1316 + attribute \src "ls180.v:6142.40-6142.93" + cell $and $and$ls180.v:6142$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241206,43 +258665,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5969$1316_Y + connect \Y $and$ls180.v:6142$1445_Y end - attribute \src "ls180.v:5969.39-5969.143" - cell $and $and$ls180.v:5969$1318 + attribute \src "ls180.v:6142.39-6142.143" + cell $and $and$ls180.v:6142$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5969$1316_Y - connect \B $eq$ls180.v:5969$1317_Y - connect \Y $and$ls180.v:5969$1318_Y + connect \A $and$ls180.v:6142$1445_Y + connect \B $eq$ls180.v:6142$1446_Y + connect \Y $and$ls180.v:6142$1447_Y end - attribute \src "ls180.v:5970.40-5970.96" - cell $and $and$ls180.v:5970$1320 + attribute \src "ls180.v:6143.40-6143.96" + cell $and $and$ls180.v:6143$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5970$1319_Y - connect \Y $and$ls180.v:5970$1320_Y + connect \B $not$ls180.v:6143$1448_Y + connect \Y $and$ls180.v:6143$1449_Y end - attribute \src "ls180.v:5970.39-5970.146" - cell $and $and$ls180.v:5970$1322 + attribute \src "ls180.v:6143.39-6143.146" + cell $and $and$ls180.v:6143$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5970$1320_Y - connect \B $eq$ls180.v:5970$1321_Y - connect \Y $and$ls180.v:5970$1322_Y + connect \A $and$ls180.v:6143$1449_Y + connect \B $eq$ls180.v:6143$1450_Y + connect \Y $and$ls180.v:6143$1451_Y end - attribute \src "ls180.v:5972.40-5972.93" - cell $and $and$ls180.v:5972$1323 + attribute \src "ls180.v:6145.40-6145.93" + cell $and $and$ls180.v:6145$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241250,43 +258709,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5972$1323_Y + connect \Y $and$ls180.v:6145$1452_Y end - attribute \src "ls180.v:5972.39-5972.143" - cell $and $and$ls180.v:5972$1325 + attribute \src "ls180.v:6145.39-6145.143" + cell $and $and$ls180.v:6145$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5972$1323_Y - connect \B $eq$ls180.v:5972$1324_Y - connect \Y $and$ls180.v:5972$1325_Y + connect \A $and$ls180.v:6145$1452_Y + connect \B $eq$ls180.v:6145$1453_Y + connect \Y $and$ls180.v:6145$1454_Y end - attribute \src "ls180.v:5973.40-5973.96" - cell $and $and$ls180.v:5973$1327 + attribute \src "ls180.v:6146.40-6146.96" + cell $and $and$ls180.v:6146$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5973$1326_Y - connect \Y $and$ls180.v:5973$1327_Y + connect \B $not$ls180.v:6146$1455_Y + connect \Y $and$ls180.v:6146$1456_Y end - attribute \src "ls180.v:5973.39-5973.146" - cell $and $and$ls180.v:5973$1329 + attribute \src "ls180.v:6146.39-6146.146" + cell $and $and$ls180.v:6146$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5973$1327_Y - connect \B $eq$ls180.v:5973$1328_Y - connect \Y $and$ls180.v:5973$1329_Y + connect \A $and$ls180.v:6146$1456_Y + connect \B $eq$ls180.v:6146$1457_Y + connect \Y $and$ls180.v:6146$1458_Y end - attribute \src "ls180.v:5975.40-5975.93" - cell $and $and$ls180.v:5975$1330 + attribute \src "ls180.v:6148.40-6148.93" + cell $and $and$ls180.v:6148$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241294,43 +258753,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5975$1330_Y + connect \Y $and$ls180.v:6148$1459_Y end - attribute \src "ls180.v:5975.39-5975.143" - cell $and $and$ls180.v:5975$1332 + attribute \src "ls180.v:6148.39-6148.143" + cell $and $and$ls180.v:6148$1461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5975$1330_Y - connect \B $eq$ls180.v:5975$1331_Y - connect \Y $and$ls180.v:5975$1332_Y + connect \A $and$ls180.v:6148$1459_Y + connect \B $eq$ls180.v:6148$1460_Y + connect \Y $and$ls180.v:6148$1461_Y end - attribute \src "ls180.v:5976.40-5976.96" - cell $and $and$ls180.v:5976$1334 + attribute \src "ls180.v:6149.40-6149.96" + cell $and $and$ls180.v:6149$1463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5976$1333_Y - connect \Y $and$ls180.v:5976$1334_Y + connect \B $not$ls180.v:6149$1462_Y + connect \Y $and$ls180.v:6149$1463_Y end - attribute \src "ls180.v:5976.39-5976.146" - cell $and $and$ls180.v:5976$1336 + attribute \src "ls180.v:6149.39-6149.146" + cell $and $and$ls180.v:6149$1465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5976$1334_Y - connect \B $eq$ls180.v:5976$1335_Y - connect \Y $and$ls180.v:5976$1336_Y + connect \A $and$ls180.v:6149$1463_Y + connect \B $eq$ls180.v:6149$1464_Y + connect \Y $and$ls180.v:6149$1465_Y end - attribute \src "ls180.v:5988.40-5988.93" - cell $and $and$ls180.v:5988$1338 + attribute \src "ls180.v:6161.40-6161.93" + cell $and $and$ls180.v:6161$1467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241338,43 +258797,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5988$1338_Y + connect \Y $and$ls180.v:6161$1467_Y end - attribute \src "ls180.v:5988.39-5988.143" - cell $and $and$ls180.v:5988$1340 + attribute \src "ls180.v:6161.39-6161.143" + cell $and $and$ls180.v:6161$1469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5988$1338_Y - connect \B $eq$ls180.v:5988$1339_Y - connect \Y $and$ls180.v:5988$1340_Y + connect \A $and$ls180.v:6161$1467_Y + connect \B $eq$ls180.v:6161$1468_Y + connect \Y $and$ls180.v:6161$1469_Y end - attribute \src "ls180.v:5989.40-5989.96" - cell $and $and$ls180.v:5989$1342 + attribute \src "ls180.v:6162.40-6162.96" + cell $and $and$ls180.v:6162$1471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5989$1341_Y - connect \Y $and$ls180.v:5989$1342_Y + connect \B $not$ls180.v:6162$1470_Y + connect \Y $and$ls180.v:6162$1471_Y end - attribute \src "ls180.v:5989.39-5989.146" - cell $and $and$ls180.v:5989$1344 + attribute \src "ls180.v:6162.39-6162.146" + cell $and $and$ls180.v:6162$1473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5989$1342_Y - connect \B $eq$ls180.v:5989$1343_Y - connect \Y $and$ls180.v:5989$1344_Y + connect \A $and$ls180.v:6162$1471_Y + connect \B $eq$ls180.v:6162$1472_Y + connect \Y $and$ls180.v:6162$1473_Y end - attribute \src "ls180.v:5991.39-5991.92" - cell $and $and$ls180.v:5991$1345 + attribute \src "ls180.v:6164.39-6164.92" + cell $and $and$ls180.v:6164$1474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241382,43 +258841,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5991$1345_Y + connect \Y $and$ls180.v:6164$1474_Y end - attribute \src "ls180.v:5991.38-5991.142" - cell $and $and$ls180.v:5991$1347 + attribute \src "ls180.v:6164.38-6164.142" + cell $and $and$ls180.v:6164$1476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5991$1345_Y - connect \B $eq$ls180.v:5991$1346_Y - connect \Y $and$ls180.v:5991$1347_Y + connect \A $and$ls180.v:6164$1474_Y + connect \B $eq$ls180.v:6164$1475_Y + connect \Y $and$ls180.v:6164$1476_Y end - attribute \src "ls180.v:5992.39-5992.95" - cell $and $and$ls180.v:5992$1349 + attribute \src "ls180.v:6165.39-6165.95" + cell $and $and$ls180.v:6165$1478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5992$1348_Y - connect \Y $and$ls180.v:5992$1349_Y + connect \B $not$ls180.v:6165$1477_Y + connect \Y $and$ls180.v:6165$1478_Y end - attribute \src "ls180.v:5992.38-5992.145" - cell $and $and$ls180.v:5992$1351 + attribute \src "ls180.v:6165.38-6165.145" + cell $and $and$ls180.v:6165$1480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5992$1349_Y - connect \B $eq$ls180.v:5992$1350_Y - connect \Y $and$ls180.v:5992$1351_Y + connect \A $and$ls180.v:6165$1478_Y + connect \B $eq$ls180.v:6165$1479_Y + connect \Y $and$ls180.v:6165$1480_Y end - attribute \src "ls180.v:5994.39-5994.92" - cell $and $and$ls180.v:5994$1352 + attribute \src "ls180.v:6167.39-6167.92" + cell $and $and$ls180.v:6167$1481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241426,43 +258885,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5994$1352_Y + connect \Y $and$ls180.v:6167$1481_Y end - attribute \src "ls180.v:5994.38-5994.142" - cell $and $and$ls180.v:5994$1354 + attribute \src "ls180.v:6167.38-6167.142" + cell $and $and$ls180.v:6167$1483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5994$1352_Y - connect \B $eq$ls180.v:5994$1353_Y - connect \Y $and$ls180.v:5994$1354_Y + connect \A $and$ls180.v:6167$1481_Y + connect \B $eq$ls180.v:6167$1482_Y + connect \Y $and$ls180.v:6167$1483_Y end - attribute \src "ls180.v:5995.39-5995.95" - cell $and $and$ls180.v:5995$1356 + attribute \src "ls180.v:6168.39-6168.95" + cell $and $and$ls180.v:6168$1485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5995$1355_Y - connect \Y $and$ls180.v:5995$1356_Y + connect \B $not$ls180.v:6168$1484_Y + connect \Y $and$ls180.v:6168$1485_Y end - attribute \src "ls180.v:5995.38-5995.145" - cell $and $and$ls180.v:5995$1358 + attribute \src "ls180.v:6168.38-6168.145" + cell $and $and$ls180.v:6168$1487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5995$1356_Y - connect \B $eq$ls180.v:5995$1357_Y - connect \Y $and$ls180.v:5995$1358_Y + connect \A $and$ls180.v:6168$1485_Y + connect \B $eq$ls180.v:6168$1486_Y + connect \Y $and$ls180.v:6168$1487_Y end - attribute \src "ls180.v:5997.39-5997.92" - cell $and $and$ls180.v:5997$1359 + attribute \src "ls180.v:6170.39-6170.92" + cell $and $and$ls180.v:6170$1488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241470,43 +258929,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5997$1359_Y + connect \Y $and$ls180.v:6170$1488_Y end - attribute \src "ls180.v:5997.38-5997.142" - cell $and $and$ls180.v:5997$1361 + attribute \src "ls180.v:6170.38-6170.142" + cell $and $and$ls180.v:6170$1490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5997$1359_Y - connect \B $eq$ls180.v:5997$1360_Y - connect \Y $and$ls180.v:5997$1361_Y + connect \A $and$ls180.v:6170$1488_Y + connect \B $eq$ls180.v:6170$1489_Y + connect \Y $and$ls180.v:6170$1490_Y end - attribute \src "ls180.v:5998.39-5998.95" - cell $and $and$ls180.v:5998$1363 + attribute \src "ls180.v:6171.39-6171.95" + cell $and $and$ls180.v:6171$1492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5998$1362_Y - connect \Y $and$ls180.v:5998$1363_Y + connect \B $not$ls180.v:6171$1491_Y + connect \Y $and$ls180.v:6171$1492_Y end - attribute \src "ls180.v:5998.38-5998.145" - cell $and $and$ls180.v:5998$1365 + attribute \src "ls180.v:6171.38-6171.145" + cell $and $and$ls180.v:6171$1494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5998$1363_Y - connect \B $eq$ls180.v:5998$1364_Y - connect \Y $and$ls180.v:5998$1365_Y + connect \A $and$ls180.v:6171$1492_Y + connect \B $eq$ls180.v:6171$1493_Y + connect \Y $and$ls180.v:6171$1494_Y end - attribute \src "ls180.v:6000.39-6000.92" - cell $and $and$ls180.v:6000$1366 + attribute \src "ls180.v:6173.39-6173.92" + cell $and $and$ls180.v:6173$1495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241514,43 +258973,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6000$1366_Y + connect \Y $and$ls180.v:6173$1495_Y end - attribute \src "ls180.v:6000.38-6000.142" - cell $and $and$ls180.v:6000$1368 + attribute \src "ls180.v:6173.38-6173.142" + cell $and $and$ls180.v:6173$1497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6000$1366_Y - connect \B $eq$ls180.v:6000$1367_Y - connect \Y $and$ls180.v:6000$1368_Y + connect \A $and$ls180.v:6173$1495_Y + connect \B $eq$ls180.v:6173$1496_Y + connect \Y $and$ls180.v:6173$1497_Y end - attribute \src "ls180.v:6001.39-6001.95" - cell $and $and$ls180.v:6001$1370 + attribute \src "ls180.v:6174.39-6174.95" + cell $and $and$ls180.v:6174$1499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6001$1369_Y - connect \Y $and$ls180.v:6001$1370_Y + connect \B $not$ls180.v:6174$1498_Y + connect \Y $and$ls180.v:6174$1499_Y end - attribute \src "ls180.v:6001.38-6001.145" - cell $and $and$ls180.v:6001$1372 + attribute \src "ls180.v:6174.38-6174.145" + cell $and $and$ls180.v:6174$1501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6001$1370_Y - connect \B $eq$ls180.v:6001$1371_Y - connect \Y $and$ls180.v:6001$1372_Y + connect \A $and$ls180.v:6174$1499_Y + connect \B $eq$ls180.v:6174$1500_Y + connect \Y $and$ls180.v:6174$1501_Y end - attribute \src "ls180.v:6003.40-6003.93" - cell $and $and$ls180.v:6003$1373 + attribute \src "ls180.v:6176.40-6176.93" + cell $and $and$ls180.v:6176$1502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241558,43 +259017,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6003$1373_Y + connect \Y $and$ls180.v:6176$1502_Y end - attribute \src "ls180.v:6003.39-6003.143" - cell $and $and$ls180.v:6003$1375 + attribute \src "ls180.v:6176.39-6176.143" + cell $and $and$ls180.v:6176$1504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6003$1373_Y - connect \B $eq$ls180.v:6003$1374_Y - connect \Y $and$ls180.v:6003$1375_Y + connect \A $and$ls180.v:6176$1502_Y + connect \B $eq$ls180.v:6176$1503_Y + connect \Y $and$ls180.v:6176$1504_Y end - attribute \src "ls180.v:6004.40-6004.96" - cell $and $and$ls180.v:6004$1377 + attribute \src "ls180.v:6177.40-6177.96" + cell $and $and$ls180.v:6177$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6004$1376_Y - connect \Y $and$ls180.v:6004$1377_Y + connect \B $not$ls180.v:6177$1505_Y + connect \Y $and$ls180.v:6177$1506_Y end - attribute \src "ls180.v:6004.39-6004.146" - cell $and $and$ls180.v:6004$1379 + attribute \src "ls180.v:6177.39-6177.146" + cell $and $and$ls180.v:6177$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6004$1377_Y - connect \B $eq$ls180.v:6004$1378_Y - connect \Y $and$ls180.v:6004$1379_Y + connect \A $and$ls180.v:6177$1506_Y + connect \B $eq$ls180.v:6177$1507_Y + connect \Y $and$ls180.v:6177$1508_Y end - attribute \src "ls180.v:6006.40-6006.93" - cell $and $and$ls180.v:6006$1380 + attribute \src "ls180.v:6179.40-6179.93" + cell $and $and$ls180.v:6179$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241602,43 +259061,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6006$1380_Y + connect \Y $and$ls180.v:6179$1509_Y end - attribute \src "ls180.v:6006.39-6006.143" - cell $and $and$ls180.v:6006$1382 + attribute \src "ls180.v:6179.39-6179.143" + cell $and $and$ls180.v:6179$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6006$1380_Y - connect \B $eq$ls180.v:6006$1381_Y - connect \Y $and$ls180.v:6006$1382_Y + connect \A $and$ls180.v:6179$1509_Y + connect \B $eq$ls180.v:6179$1510_Y + connect \Y $and$ls180.v:6179$1511_Y end - attribute \src "ls180.v:6007.40-6007.96" - cell $and $and$ls180.v:6007$1384 + attribute \src "ls180.v:6180.40-6180.96" + cell $and $and$ls180.v:6180$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6007$1383_Y - connect \Y $and$ls180.v:6007$1384_Y + connect \B $not$ls180.v:6180$1512_Y + connect \Y $and$ls180.v:6180$1513_Y end - attribute \src "ls180.v:6007.39-6007.146" - cell $and $and$ls180.v:6007$1386 + attribute \src "ls180.v:6180.39-6180.146" + cell $and $and$ls180.v:6180$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6007$1384_Y - connect \B $eq$ls180.v:6007$1385_Y - connect \Y $and$ls180.v:6007$1386_Y + connect \A $and$ls180.v:6180$1513_Y + connect \B $eq$ls180.v:6180$1514_Y + connect \Y $and$ls180.v:6180$1515_Y end - attribute \src "ls180.v:6009.40-6009.93" - cell $and $and$ls180.v:6009$1387 + attribute \src "ls180.v:6182.40-6182.93" + cell $and $and$ls180.v:6182$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241646,43 +259105,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6009$1387_Y + connect \Y $and$ls180.v:6182$1516_Y end - attribute \src "ls180.v:6009.39-6009.143" - cell $and $and$ls180.v:6009$1389 + attribute \src "ls180.v:6182.39-6182.143" + cell $and $and$ls180.v:6182$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6009$1387_Y - connect \B $eq$ls180.v:6009$1388_Y - connect \Y $and$ls180.v:6009$1389_Y + connect \A $and$ls180.v:6182$1516_Y + connect \B $eq$ls180.v:6182$1517_Y + connect \Y $and$ls180.v:6182$1518_Y end - attribute \src "ls180.v:6010.40-6010.96" - cell $and $and$ls180.v:6010$1391 + attribute \src "ls180.v:6183.40-6183.96" + cell $and $and$ls180.v:6183$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6010$1390_Y - connect \Y $and$ls180.v:6010$1391_Y + connect \B $not$ls180.v:6183$1519_Y + connect \Y $and$ls180.v:6183$1520_Y end - attribute \src "ls180.v:6010.39-6010.146" - cell $and $and$ls180.v:6010$1393 + attribute \src "ls180.v:6183.39-6183.146" + cell $and $and$ls180.v:6183$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6010$1391_Y - connect \B $eq$ls180.v:6010$1392_Y - connect \Y $and$ls180.v:6010$1393_Y + connect \A $and$ls180.v:6183$1520_Y + connect \B $eq$ls180.v:6183$1521_Y + connect \Y $and$ls180.v:6183$1522_Y end - attribute \src "ls180.v:6012.40-6012.93" - cell $and $and$ls180.v:6012$1394 + attribute \src "ls180.v:6185.40-6185.93" + cell $and $and$ls180.v:6185$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241690,43 +259149,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6012$1394_Y + connect \Y $and$ls180.v:6185$1523_Y end - attribute \src "ls180.v:6012.39-6012.143" - cell $and $and$ls180.v:6012$1396 + attribute \src "ls180.v:6185.39-6185.143" + cell $and $and$ls180.v:6185$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6012$1394_Y - connect \B $eq$ls180.v:6012$1395_Y - connect \Y $and$ls180.v:6012$1396_Y + connect \A $and$ls180.v:6185$1523_Y + connect \B $eq$ls180.v:6185$1524_Y + connect \Y $and$ls180.v:6185$1525_Y end - attribute \src "ls180.v:6013.40-6013.96" - cell $and $and$ls180.v:6013$1398 + attribute \src "ls180.v:6186.40-6186.96" + cell $and $and$ls180.v:6186$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6013$1397_Y - connect \Y $and$ls180.v:6013$1398_Y + connect \B $not$ls180.v:6186$1526_Y + connect \Y $and$ls180.v:6186$1527_Y end - attribute \src "ls180.v:6013.39-6013.146" - cell $and $and$ls180.v:6013$1400 + attribute \src "ls180.v:6186.39-6186.146" + cell $and $and$ls180.v:6186$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6013$1398_Y - connect \B $eq$ls180.v:6013$1399_Y - connect \Y $and$ls180.v:6013$1400_Y + connect \A $and$ls180.v:6186$1527_Y + connect \B $eq$ls180.v:6186$1528_Y + connect \Y $and$ls180.v:6186$1529_Y end - attribute \src "ls180.v:6025.42-6025.95" - cell $and $and$ls180.v:6025$1402 + attribute \src "ls180.v:6198.42-6198.95" + cell $and $and$ls180.v:6198$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241734,43 +259193,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6025$1402_Y + connect \Y $and$ls180.v:6198$1531_Y end - attribute \src "ls180.v:6025.41-6025.145" - cell $and $and$ls180.v:6025$1404 + attribute \src "ls180.v:6198.41-6198.145" + cell $and $and$ls180.v:6198$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6025$1402_Y - connect \B $eq$ls180.v:6025$1403_Y - connect \Y $and$ls180.v:6025$1404_Y + connect \A $and$ls180.v:6198$1531_Y + connect \B $eq$ls180.v:6198$1532_Y + connect \Y $and$ls180.v:6198$1533_Y end - attribute \src "ls180.v:6026.42-6026.98" - cell $and $and$ls180.v:6026$1406 + attribute \src "ls180.v:6199.42-6199.98" + cell $and $and$ls180.v:6199$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6026$1405_Y - connect \Y $and$ls180.v:6026$1406_Y + connect \B $not$ls180.v:6199$1534_Y + connect \Y $and$ls180.v:6199$1535_Y end - attribute \src "ls180.v:6026.41-6026.148" - cell $and $and$ls180.v:6026$1408 + attribute \src "ls180.v:6199.41-6199.148" + cell $and $and$ls180.v:6199$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6026$1406_Y - connect \B $eq$ls180.v:6026$1407_Y - connect \Y $and$ls180.v:6026$1408_Y + connect \A $and$ls180.v:6199$1535_Y + connect \B $eq$ls180.v:6199$1536_Y + connect \Y $and$ls180.v:6199$1537_Y end - attribute \src "ls180.v:6028.42-6028.95" - cell $and $and$ls180.v:6028$1409 + attribute \src "ls180.v:6201.42-6201.95" + cell $and $and$ls180.v:6201$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241778,43 +259237,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6028$1409_Y + connect \Y $and$ls180.v:6201$1538_Y end - attribute \src "ls180.v:6028.41-6028.145" - cell $and $and$ls180.v:6028$1411 + attribute \src "ls180.v:6201.41-6201.145" + cell $and $and$ls180.v:6201$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6028$1409_Y - connect \B $eq$ls180.v:6028$1410_Y - connect \Y $and$ls180.v:6028$1411_Y + connect \A $and$ls180.v:6201$1538_Y + connect \B $eq$ls180.v:6201$1539_Y + connect \Y $and$ls180.v:6201$1540_Y end - attribute \src "ls180.v:6029.42-6029.98" - cell $and $and$ls180.v:6029$1413 + attribute \src "ls180.v:6202.42-6202.98" + cell $and $and$ls180.v:6202$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6029$1412_Y - connect \Y $and$ls180.v:6029$1413_Y + connect \B $not$ls180.v:6202$1541_Y + connect \Y $and$ls180.v:6202$1542_Y end - attribute \src "ls180.v:6029.41-6029.148" - cell $and $and$ls180.v:6029$1415 + attribute \src "ls180.v:6202.41-6202.148" + cell $and $and$ls180.v:6202$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6029$1413_Y - connect \B $eq$ls180.v:6029$1414_Y - connect \Y $and$ls180.v:6029$1415_Y + connect \A $and$ls180.v:6202$1542_Y + connect \B $eq$ls180.v:6202$1543_Y + connect \Y $and$ls180.v:6202$1544_Y end - attribute \src "ls180.v:6031.42-6031.95" - cell $and $and$ls180.v:6031$1416 + attribute \src "ls180.v:6204.42-6204.95" + cell $and $and$ls180.v:6204$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241822,43 +259281,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6031$1416_Y + connect \Y $and$ls180.v:6204$1545_Y end - attribute \src "ls180.v:6031.41-6031.145" - cell $and $and$ls180.v:6031$1418 + attribute \src "ls180.v:6204.41-6204.145" + cell $and $and$ls180.v:6204$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6031$1416_Y - connect \B $eq$ls180.v:6031$1417_Y - connect \Y $and$ls180.v:6031$1418_Y + connect \A $and$ls180.v:6204$1545_Y + connect \B $eq$ls180.v:6204$1546_Y + connect \Y $and$ls180.v:6204$1547_Y end - attribute \src "ls180.v:6032.42-6032.98" - cell $and $and$ls180.v:6032$1420 + attribute \src "ls180.v:6205.42-6205.98" + cell $and $and$ls180.v:6205$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6032$1419_Y - connect \Y $and$ls180.v:6032$1420_Y + connect \B $not$ls180.v:6205$1548_Y + connect \Y $and$ls180.v:6205$1549_Y end - attribute \src "ls180.v:6032.41-6032.148" - cell $and $and$ls180.v:6032$1422 + attribute \src "ls180.v:6205.41-6205.148" + cell $and $and$ls180.v:6205$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6032$1420_Y - connect \B $eq$ls180.v:6032$1421_Y - connect \Y $and$ls180.v:6032$1422_Y + connect \A $and$ls180.v:6205$1549_Y + connect \B $eq$ls180.v:6205$1550_Y + connect \Y $and$ls180.v:6205$1551_Y end - attribute \src "ls180.v:6034.42-6034.95" - cell $and $and$ls180.v:6034$1423 + attribute \src "ls180.v:6207.42-6207.95" + cell $and $and$ls180.v:6207$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241866,43 +259325,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6034$1423_Y + connect \Y $and$ls180.v:6207$1552_Y end - attribute \src "ls180.v:6034.41-6034.145" - cell $and $and$ls180.v:6034$1425 + attribute \src "ls180.v:6207.41-6207.145" + cell $and $and$ls180.v:6207$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6034$1423_Y - connect \B $eq$ls180.v:6034$1424_Y - connect \Y $and$ls180.v:6034$1425_Y + connect \A $and$ls180.v:6207$1552_Y + connect \B $eq$ls180.v:6207$1553_Y + connect \Y $and$ls180.v:6207$1554_Y end - attribute \src "ls180.v:6035.42-6035.98" - cell $and $and$ls180.v:6035$1427 + attribute \src "ls180.v:6208.42-6208.98" + cell $and $and$ls180.v:6208$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6035$1426_Y - connect \Y $and$ls180.v:6035$1427_Y + connect \B $not$ls180.v:6208$1555_Y + connect \Y $and$ls180.v:6208$1556_Y end - attribute \src "ls180.v:6035.41-6035.148" - cell $and $and$ls180.v:6035$1429 + attribute \src "ls180.v:6208.41-6208.148" + cell $and $and$ls180.v:6208$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6035$1427_Y - connect \B $eq$ls180.v:6035$1428_Y - connect \Y $and$ls180.v:6035$1429_Y + connect \A $and$ls180.v:6208$1556_Y + connect \B $eq$ls180.v:6208$1557_Y + connect \Y $and$ls180.v:6208$1558_Y end - attribute \src "ls180.v:6037.42-6037.95" - cell $and $and$ls180.v:6037$1430 + attribute \src "ls180.v:6210.42-6210.95" + cell $and $and$ls180.v:6210$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241910,43 +259369,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6037$1430_Y + connect \Y $and$ls180.v:6210$1559_Y end - attribute \src "ls180.v:6037.41-6037.145" - cell $and $and$ls180.v:6037$1432 + attribute \src "ls180.v:6210.41-6210.145" + cell $and $and$ls180.v:6210$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6037$1430_Y - connect \B $eq$ls180.v:6037$1431_Y - connect \Y $and$ls180.v:6037$1432_Y + connect \A $and$ls180.v:6210$1559_Y + connect \B $eq$ls180.v:6210$1560_Y + connect \Y $and$ls180.v:6210$1561_Y end - attribute \src "ls180.v:6038.42-6038.98" - cell $and $and$ls180.v:6038$1434 + attribute \src "ls180.v:6211.42-6211.98" + cell $and $and$ls180.v:6211$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6038$1433_Y - connect \Y $and$ls180.v:6038$1434_Y + connect \B $not$ls180.v:6211$1562_Y + connect \Y $and$ls180.v:6211$1563_Y end - attribute \src "ls180.v:6038.41-6038.148" - cell $and $and$ls180.v:6038$1436 + attribute \src "ls180.v:6211.41-6211.148" + cell $and $and$ls180.v:6211$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6038$1434_Y - connect \B $eq$ls180.v:6038$1435_Y - connect \Y $and$ls180.v:6038$1436_Y + connect \A $and$ls180.v:6211$1563_Y + connect \B $eq$ls180.v:6211$1564_Y + connect \Y $and$ls180.v:6211$1565_Y end - attribute \src "ls180.v:6040.42-6040.95" - cell $and $and$ls180.v:6040$1437 + attribute \src "ls180.v:6213.42-6213.95" + cell $and $and$ls180.v:6213$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241954,43 +259413,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6040$1437_Y + connect \Y $and$ls180.v:6213$1566_Y end - attribute \src "ls180.v:6040.41-6040.145" - cell $and $and$ls180.v:6040$1439 + attribute \src "ls180.v:6213.41-6213.145" + cell $and $and$ls180.v:6213$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6040$1437_Y - connect \B $eq$ls180.v:6040$1438_Y - connect \Y $and$ls180.v:6040$1439_Y + connect \A $and$ls180.v:6213$1566_Y + connect \B $eq$ls180.v:6213$1567_Y + connect \Y $and$ls180.v:6213$1568_Y end - attribute \src "ls180.v:6041.42-6041.98" - cell $and $and$ls180.v:6041$1441 + attribute \src "ls180.v:6214.42-6214.98" + cell $and $and$ls180.v:6214$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6041$1440_Y - connect \Y $and$ls180.v:6041$1441_Y + connect \B $not$ls180.v:6214$1569_Y + connect \Y $and$ls180.v:6214$1570_Y end - attribute \src "ls180.v:6041.41-6041.148" - cell $and $and$ls180.v:6041$1443 + attribute \src "ls180.v:6214.41-6214.148" + cell $and $and$ls180.v:6214$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6041$1441_Y - connect \B $eq$ls180.v:6041$1442_Y - connect \Y $and$ls180.v:6041$1443_Y + connect \A $and$ls180.v:6214$1570_Y + connect \B $eq$ls180.v:6214$1571_Y + connect \Y $and$ls180.v:6214$1572_Y end - attribute \src "ls180.v:6043.42-6043.95" - cell $and $and$ls180.v:6043$1444 + attribute \src "ls180.v:6216.42-6216.95" + cell $and $and$ls180.v:6216$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241998,43 +259457,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6043$1444_Y + connect \Y $and$ls180.v:6216$1573_Y end - attribute \src "ls180.v:6043.41-6043.145" - cell $and $and$ls180.v:6043$1446 + attribute \src "ls180.v:6216.41-6216.145" + cell $and $and$ls180.v:6216$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6043$1444_Y - connect \B $eq$ls180.v:6043$1445_Y - connect \Y $and$ls180.v:6043$1446_Y + connect \A $and$ls180.v:6216$1573_Y + connect \B $eq$ls180.v:6216$1574_Y + connect \Y $and$ls180.v:6216$1575_Y end - attribute \src "ls180.v:6044.42-6044.98" - cell $and $and$ls180.v:6044$1448 + attribute \src "ls180.v:6217.42-6217.98" + cell $and $and$ls180.v:6217$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6044$1447_Y - connect \Y $and$ls180.v:6044$1448_Y + connect \B $not$ls180.v:6217$1576_Y + connect \Y $and$ls180.v:6217$1577_Y end - attribute \src "ls180.v:6044.41-6044.148" - cell $and $and$ls180.v:6044$1450 + attribute \src "ls180.v:6217.41-6217.148" + cell $and $and$ls180.v:6217$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6044$1448_Y - connect \B $eq$ls180.v:6044$1449_Y - connect \Y $and$ls180.v:6044$1450_Y + connect \A $and$ls180.v:6217$1577_Y + connect \B $eq$ls180.v:6217$1578_Y + connect \Y $and$ls180.v:6217$1579_Y end - attribute \src "ls180.v:6046.42-6046.95" - cell $and $and$ls180.v:6046$1451 + attribute \src "ls180.v:6219.42-6219.95" + cell $and $and$ls180.v:6219$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242042,43 +259501,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6046$1451_Y + connect \Y $and$ls180.v:6219$1580_Y end - attribute \src "ls180.v:6046.41-6046.145" - cell $and $and$ls180.v:6046$1453 + attribute \src "ls180.v:6219.41-6219.145" + cell $and $and$ls180.v:6219$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1451_Y - connect \B $eq$ls180.v:6046$1452_Y - connect \Y $and$ls180.v:6046$1453_Y + connect \A $and$ls180.v:6219$1580_Y + connect \B $eq$ls180.v:6219$1581_Y + connect \Y $and$ls180.v:6219$1582_Y end - attribute \src "ls180.v:6047.42-6047.98" - cell $and $and$ls180.v:6047$1455 + attribute \src "ls180.v:6220.42-6220.98" + cell $and $and$ls180.v:6220$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6047$1454_Y - connect \Y $and$ls180.v:6047$1455_Y + connect \B $not$ls180.v:6220$1583_Y + connect \Y $and$ls180.v:6220$1584_Y end - attribute \src "ls180.v:6047.41-6047.148" - cell $and $and$ls180.v:6047$1457 + attribute \src "ls180.v:6220.41-6220.148" + cell $and $and$ls180.v:6220$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1455_Y - connect \B $eq$ls180.v:6047$1456_Y - connect \Y $and$ls180.v:6047$1457_Y + connect \A $and$ls180.v:6220$1584_Y + connect \B $eq$ls180.v:6220$1585_Y + connect \Y $and$ls180.v:6220$1586_Y end - attribute \src "ls180.v:6049.44-6049.97" - cell $and $and$ls180.v:6049$1458 + attribute \src "ls180.v:6222.44-6222.97" + cell $and $and$ls180.v:6222$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242086,43 +259545,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6049$1458_Y + connect \Y $and$ls180.v:6222$1587_Y end - attribute \src "ls180.v:6049.43-6049.147" - cell $and $and$ls180.v:6049$1460 + attribute \src "ls180.v:6222.43-6222.147" + cell $and $and$ls180.v:6222$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1458_Y - connect \B $eq$ls180.v:6049$1459_Y - connect \Y $and$ls180.v:6049$1460_Y + connect \A $and$ls180.v:6222$1587_Y + connect \B $eq$ls180.v:6222$1588_Y + connect \Y $and$ls180.v:6222$1589_Y end - attribute \src "ls180.v:6050.44-6050.100" - cell $and $and$ls180.v:6050$1462 + attribute \src "ls180.v:6223.44-6223.100" + cell $and $and$ls180.v:6223$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6050$1461_Y - connect \Y $and$ls180.v:6050$1462_Y + connect \B $not$ls180.v:6223$1590_Y + connect \Y $and$ls180.v:6223$1591_Y end - attribute \src "ls180.v:6050.43-6050.150" - cell $and $and$ls180.v:6050$1464 + attribute \src "ls180.v:6223.43-6223.150" + cell $and $and$ls180.v:6223$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1462_Y - connect \B $eq$ls180.v:6050$1463_Y - connect \Y $and$ls180.v:6050$1464_Y + connect \A $and$ls180.v:6223$1591_Y + connect \B $eq$ls180.v:6223$1592_Y + connect \Y $and$ls180.v:6223$1593_Y end - attribute \src "ls180.v:6052.44-6052.97" - cell $and $and$ls180.v:6052$1465 + attribute \src "ls180.v:6225.44-6225.97" + cell $and $and$ls180.v:6225$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242130,43 +259589,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6052$1465_Y + connect \Y $and$ls180.v:6225$1594_Y end - attribute \src "ls180.v:6052.43-6052.147" - cell $and $and$ls180.v:6052$1467 + attribute \src "ls180.v:6225.43-6225.147" + cell $and $and$ls180.v:6225$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6052$1465_Y - connect \B $eq$ls180.v:6052$1466_Y - connect \Y $and$ls180.v:6052$1467_Y + connect \A $and$ls180.v:6225$1594_Y + connect \B $eq$ls180.v:6225$1595_Y + connect \Y $and$ls180.v:6225$1596_Y end - attribute \src "ls180.v:6053.44-6053.100" - cell $and $and$ls180.v:6053$1469 + attribute \src "ls180.v:6226.44-6226.100" + cell $and $and$ls180.v:6226$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6053$1468_Y - connect \Y $and$ls180.v:6053$1469_Y + connect \B $not$ls180.v:6226$1597_Y + connect \Y $and$ls180.v:6226$1598_Y end - attribute \src "ls180.v:6053.43-6053.150" - cell $and $and$ls180.v:6053$1471 + attribute \src "ls180.v:6226.43-6226.150" + cell $and $and$ls180.v:6226$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6053$1469_Y - connect \B $eq$ls180.v:6053$1470_Y - connect \Y $and$ls180.v:6053$1471_Y + connect \A $and$ls180.v:6226$1598_Y + connect \B $eq$ls180.v:6226$1599_Y + connect \Y $and$ls180.v:6226$1600_Y end - attribute \src "ls180.v:6055.44-6055.97" - cell $and $and$ls180.v:6055$1472 + attribute \src "ls180.v:6228.44-6228.97" + cell $and $and$ls180.v:6228$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242174,43 +259633,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6055$1472_Y + connect \Y $and$ls180.v:6228$1601_Y end - attribute \src "ls180.v:6055.43-6055.148" - cell $and $and$ls180.v:6055$1474 + attribute \src "ls180.v:6228.43-6228.148" + cell $and $and$ls180.v:6228$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1472_Y - connect \B $eq$ls180.v:6055$1473_Y - connect \Y $and$ls180.v:6055$1474_Y + connect \A $and$ls180.v:6228$1601_Y + connect \B $eq$ls180.v:6228$1602_Y + connect \Y $and$ls180.v:6228$1603_Y end - attribute \src "ls180.v:6056.44-6056.100" - cell $and $and$ls180.v:6056$1476 + attribute \src "ls180.v:6229.44-6229.100" + cell $and $and$ls180.v:6229$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6056$1475_Y - connect \Y $and$ls180.v:6056$1476_Y + connect \B $not$ls180.v:6229$1604_Y + connect \Y $and$ls180.v:6229$1605_Y end - attribute \src "ls180.v:6056.43-6056.151" - cell $and $and$ls180.v:6056$1478 + attribute \src "ls180.v:6229.43-6229.151" + cell $and $and$ls180.v:6229$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1476_Y - connect \B $eq$ls180.v:6056$1477_Y - connect \Y $and$ls180.v:6056$1478_Y + connect \A $and$ls180.v:6229$1605_Y + connect \B $eq$ls180.v:6229$1606_Y + connect \Y $and$ls180.v:6229$1607_Y end - attribute \src "ls180.v:6058.44-6058.97" - cell $and $and$ls180.v:6058$1479 + attribute \src "ls180.v:6231.44-6231.97" + cell $and $and$ls180.v:6231$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242218,43 +259677,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6058$1479_Y + connect \Y $and$ls180.v:6231$1608_Y end - attribute \src "ls180.v:6058.43-6058.148" - cell $and $and$ls180.v:6058$1481 + attribute \src "ls180.v:6231.43-6231.148" + cell $and $and$ls180.v:6231$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1479_Y - connect \B $eq$ls180.v:6058$1480_Y - connect \Y $and$ls180.v:6058$1481_Y + connect \A $and$ls180.v:6231$1608_Y + connect \B $eq$ls180.v:6231$1609_Y + connect \Y $and$ls180.v:6231$1610_Y end - attribute \src "ls180.v:6059.44-6059.100" - cell $and $and$ls180.v:6059$1483 + attribute \src "ls180.v:6232.44-6232.100" + cell $and $and$ls180.v:6232$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6059$1482_Y - connect \Y $and$ls180.v:6059$1483_Y + connect \B $not$ls180.v:6232$1611_Y + connect \Y $and$ls180.v:6232$1612_Y end - attribute \src "ls180.v:6059.43-6059.151" - cell $and $and$ls180.v:6059$1485 + attribute \src "ls180.v:6232.43-6232.151" + cell $and $and$ls180.v:6232$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1483_Y - connect \B $eq$ls180.v:6059$1484_Y - connect \Y $and$ls180.v:6059$1485_Y + connect \A $and$ls180.v:6232$1612_Y + connect \B $eq$ls180.v:6232$1613_Y + connect \Y $and$ls180.v:6232$1614_Y end - attribute \src "ls180.v:6061.44-6061.97" - cell $and $and$ls180.v:6061$1486 + attribute \src "ls180.v:6234.44-6234.97" + cell $and $and$ls180.v:6234$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242262,43 +259721,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6061$1486_Y + connect \Y $and$ls180.v:6234$1615_Y end - attribute \src "ls180.v:6061.43-6061.148" - cell $and $and$ls180.v:6061$1488 + attribute \src "ls180.v:6234.43-6234.148" + cell $and $and$ls180.v:6234$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1486_Y - connect \B $eq$ls180.v:6061$1487_Y - connect \Y $and$ls180.v:6061$1488_Y + connect \A $and$ls180.v:6234$1615_Y + connect \B $eq$ls180.v:6234$1616_Y + connect \Y $and$ls180.v:6234$1617_Y end - attribute \src "ls180.v:6062.44-6062.100" - cell $and $and$ls180.v:6062$1490 + attribute \src "ls180.v:6235.44-6235.100" + cell $and $and$ls180.v:6235$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6062$1489_Y - connect \Y $and$ls180.v:6062$1490_Y + connect \B $not$ls180.v:6235$1618_Y + connect \Y $and$ls180.v:6235$1619_Y end - attribute \src "ls180.v:6062.43-6062.151" - cell $and $and$ls180.v:6062$1492 + attribute \src "ls180.v:6235.43-6235.151" + cell $and $and$ls180.v:6235$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1490_Y - connect \B $eq$ls180.v:6062$1491_Y - connect \Y $and$ls180.v:6062$1492_Y + connect \A $and$ls180.v:6235$1619_Y + connect \B $eq$ls180.v:6235$1620_Y + connect \Y $and$ls180.v:6235$1621_Y end - attribute \src "ls180.v:6064.41-6064.94" - cell $and $and$ls180.v:6064$1493 + attribute \src "ls180.v:6237.41-6237.94" + cell $and $and$ls180.v:6237$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242306,43 +259765,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6064$1493_Y + connect \Y $and$ls180.v:6237$1622_Y end - attribute \src "ls180.v:6064.40-6064.145" - cell $and $and$ls180.v:6064$1495 + attribute \src "ls180.v:6237.40-6237.145" + cell $and $and$ls180.v:6237$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1493_Y - connect \B $eq$ls180.v:6064$1494_Y - connect \Y $and$ls180.v:6064$1495_Y + connect \A $and$ls180.v:6237$1622_Y + connect \B $eq$ls180.v:6237$1623_Y + connect \Y $and$ls180.v:6237$1624_Y end - attribute \src "ls180.v:6065.41-6065.97" - cell $and $and$ls180.v:6065$1497 + attribute \src "ls180.v:6238.41-6238.97" + cell $and $and$ls180.v:6238$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6065$1496_Y - connect \Y $and$ls180.v:6065$1497_Y + connect \B $not$ls180.v:6238$1625_Y + connect \Y $and$ls180.v:6238$1626_Y end - attribute \src "ls180.v:6065.40-6065.148" - cell $and $and$ls180.v:6065$1499 + attribute \src "ls180.v:6238.40-6238.148" + cell $and $and$ls180.v:6238$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1497_Y - connect \B $eq$ls180.v:6065$1498_Y - connect \Y $and$ls180.v:6065$1499_Y + connect \A $and$ls180.v:6238$1626_Y + connect \B $eq$ls180.v:6238$1627_Y + connect \Y $and$ls180.v:6238$1628_Y end - attribute \src "ls180.v:6067.42-6067.95" - cell $and $and$ls180.v:6067$1500 + attribute \src "ls180.v:6240.42-6240.95" + cell $and $and$ls180.v:6240$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242350,43 +259809,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6067$1500_Y + connect \Y $and$ls180.v:6240$1629_Y end - attribute \src "ls180.v:6067.41-6067.146" - cell $and $and$ls180.v:6067$1502 + attribute \src "ls180.v:6240.41-6240.146" + cell $and $and$ls180.v:6240$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1500_Y - connect \B $eq$ls180.v:6067$1501_Y - connect \Y $and$ls180.v:6067$1502_Y + connect \A $and$ls180.v:6240$1629_Y + connect \B $eq$ls180.v:6240$1630_Y + connect \Y $and$ls180.v:6240$1631_Y end - attribute \src "ls180.v:6068.42-6068.98" - cell $and $and$ls180.v:6068$1504 + attribute \src "ls180.v:6241.42-6241.98" + cell $and $and$ls180.v:6241$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6068$1503_Y - connect \Y $and$ls180.v:6068$1504_Y + connect \B $not$ls180.v:6241$1632_Y + connect \Y $and$ls180.v:6241$1633_Y end - attribute \src "ls180.v:6068.41-6068.149" - cell $and $and$ls180.v:6068$1506 + attribute \src "ls180.v:6241.41-6241.149" + cell $and $and$ls180.v:6241$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1504_Y - connect \B $eq$ls180.v:6068$1505_Y - connect \Y $and$ls180.v:6068$1506_Y + connect \A $and$ls180.v:6241$1633_Y + connect \B $eq$ls180.v:6241$1634_Y + connect \Y $and$ls180.v:6241$1635_Y end - attribute \src "ls180.v:6087.46-6087.99" - cell $and $and$ls180.v:6087$1508 + attribute \src "ls180.v:6260.46-6260.99" + cell $and $and$ls180.v:6260$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242394,43 +259853,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6087$1508_Y + connect \Y $and$ls180.v:6260$1637_Y end - attribute \src "ls180.v:6087.45-6087.149" - cell $and $and$ls180.v:6087$1510 + attribute \src "ls180.v:6260.45-6260.149" + cell $and $and$ls180.v:6260$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1508_Y - connect \B $eq$ls180.v:6087$1509_Y - connect \Y $and$ls180.v:6087$1510_Y + connect \A $and$ls180.v:6260$1637_Y + connect \B $eq$ls180.v:6260$1638_Y + connect \Y $and$ls180.v:6260$1639_Y end - attribute \src "ls180.v:6088.46-6088.102" - cell $and $and$ls180.v:6088$1512 + attribute \src "ls180.v:6261.46-6261.102" + cell $and $and$ls180.v:6261$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6088$1511_Y - connect \Y $and$ls180.v:6088$1512_Y + connect \B $not$ls180.v:6261$1640_Y + connect \Y $and$ls180.v:6261$1641_Y end - attribute \src "ls180.v:6088.45-6088.152" - cell $and $and$ls180.v:6088$1514 + attribute \src "ls180.v:6261.45-6261.152" + cell $and $and$ls180.v:6261$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$1512_Y - connect \B $eq$ls180.v:6088$1513_Y - connect \Y $and$ls180.v:6088$1514_Y + connect \A $and$ls180.v:6261$1641_Y + connect \B $eq$ls180.v:6261$1642_Y + connect \Y $and$ls180.v:6261$1643_Y end - attribute \src "ls180.v:6090.46-6090.99" - cell $and $and$ls180.v:6090$1515 + attribute \src "ls180.v:6263.46-6263.99" + cell $and $and$ls180.v:6263$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242438,43 +259897,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6090$1515_Y + connect \Y $and$ls180.v:6263$1644_Y end - attribute \src "ls180.v:6090.45-6090.149" - cell $and $and$ls180.v:6090$1517 + attribute \src "ls180.v:6263.45-6263.149" + cell $and $and$ls180.v:6263$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$1515_Y - connect \B $eq$ls180.v:6090$1516_Y - connect \Y $and$ls180.v:6090$1517_Y + connect \A $and$ls180.v:6263$1644_Y + connect \B $eq$ls180.v:6263$1645_Y + connect \Y $and$ls180.v:6263$1646_Y end - attribute \src "ls180.v:6091.46-6091.102" - cell $and $and$ls180.v:6091$1519 + attribute \src "ls180.v:6264.46-6264.102" + cell $and $and$ls180.v:6264$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6091$1518_Y - connect \Y $and$ls180.v:6091$1519_Y + connect \B $not$ls180.v:6264$1647_Y + connect \Y $and$ls180.v:6264$1648_Y end - attribute \src "ls180.v:6091.45-6091.152" - cell $and $and$ls180.v:6091$1521 + attribute \src "ls180.v:6264.45-6264.152" + cell $and $and$ls180.v:6264$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$1519_Y - connect \B $eq$ls180.v:6091$1520_Y - connect \Y $and$ls180.v:6091$1521_Y + connect \A $and$ls180.v:6264$1648_Y + connect \B $eq$ls180.v:6264$1649_Y + connect \Y $and$ls180.v:6264$1650_Y end - attribute \src "ls180.v:6093.46-6093.99" - cell $and $and$ls180.v:6093$1522 + attribute \src "ls180.v:6266.46-6266.99" + cell $and $and$ls180.v:6266$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242482,43 +259941,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6093$1522_Y + connect \Y $and$ls180.v:6266$1651_Y end - attribute \src "ls180.v:6093.45-6093.149" - cell $and $and$ls180.v:6093$1524 + attribute \src "ls180.v:6266.45-6266.149" + cell $and $and$ls180.v:6266$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6093$1522_Y - connect \B $eq$ls180.v:6093$1523_Y - connect \Y $and$ls180.v:6093$1524_Y + connect \A $and$ls180.v:6266$1651_Y + connect \B $eq$ls180.v:6266$1652_Y + connect \Y $and$ls180.v:6266$1653_Y end - attribute \src "ls180.v:6094.46-6094.102" - cell $and $and$ls180.v:6094$1526 + attribute \src "ls180.v:6267.46-6267.102" + cell $and $and$ls180.v:6267$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6094$1525_Y - connect \Y $and$ls180.v:6094$1526_Y + connect \B $not$ls180.v:6267$1654_Y + connect \Y $and$ls180.v:6267$1655_Y end - attribute \src "ls180.v:6094.45-6094.152" - cell $and $and$ls180.v:6094$1528 + attribute \src "ls180.v:6267.45-6267.152" + cell $and $and$ls180.v:6267$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6094$1526_Y - connect \B $eq$ls180.v:6094$1527_Y - connect \Y $and$ls180.v:6094$1528_Y + connect \A $and$ls180.v:6267$1655_Y + connect \B $eq$ls180.v:6267$1656_Y + connect \Y $and$ls180.v:6267$1657_Y end - attribute \src "ls180.v:6096.46-6096.99" - cell $and $and$ls180.v:6096$1529 + attribute \src "ls180.v:6269.46-6269.99" + cell $and $and$ls180.v:6269$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242526,43 +259985,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6096$1529_Y + connect \Y $and$ls180.v:6269$1658_Y end - attribute \src "ls180.v:6096.45-6096.149" - cell $and $and$ls180.v:6096$1531 + attribute \src "ls180.v:6269.45-6269.149" + cell $and $and$ls180.v:6269$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6096$1529_Y - connect \B $eq$ls180.v:6096$1530_Y - connect \Y $and$ls180.v:6096$1531_Y + connect \A $and$ls180.v:6269$1658_Y + connect \B $eq$ls180.v:6269$1659_Y + connect \Y $and$ls180.v:6269$1660_Y end - attribute \src "ls180.v:6097.46-6097.102" - cell $and $and$ls180.v:6097$1533 + attribute \src "ls180.v:6270.46-6270.102" + cell $and $and$ls180.v:6270$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6097$1532_Y - connect \Y $and$ls180.v:6097$1533_Y + connect \B $not$ls180.v:6270$1661_Y + connect \Y $and$ls180.v:6270$1662_Y end - attribute \src "ls180.v:6097.45-6097.152" - cell $and $and$ls180.v:6097$1535 + attribute \src "ls180.v:6270.45-6270.152" + cell $and $and$ls180.v:6270$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6097$1533_Y - connect \B $eq$ls180.v:6097$1534_Y - connect \Y $and$ls180.v:6097$1535_Y + connect \A $and$ls180.v:6270$1662_Y + connect \B $eq$ls180.v:6270$1663_Y + connect \Y $and$ls180.v:6270$1664_Y end - attribute \src "ls180.v:6099.45-6099.98" - cell $and $and$ls180.v:6099$1536 + attribute \src "ls180.v:6272.45-6272.98" + cell $and $and$ls180.v:6272$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242570,43 +260029,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6099$1536_Y + connect \Y $and$ls180.v:6272$1665_Y end - attribute \src "ls180.v:6099.44-6099.148" - cell $and $and$ls180.v:6099$1538 + attribute \src "ls180.v:6272.44-6272.148" + cell $and $and$ls180.v:6272$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6099$1536_Y - connect \B $eq$ls180.v:6099$1537_Y - connect \Y $and$ls180.v:6099$1538_Y + connect \A $and$ls180.v:6272$1665_Y + connect \B $eq$ls180.v:6272$1666_Y + connect \Y $and$ls180.v:6272$1667_Y end - attribute \src "ls180.v:6100.45-6100.101" - cell $and $and$ls180.v:6100$1540 + attribute \src "ls180.v:6273.45-6273.101" + cell $and $and$ls180.v:6273$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6100$1539_Y - connect \Y $and$ls180.v:6100$1540_Y + connect \B $not$ls180.v:6273$1668_Y + connect \Y $and$ls180.v:6273$1669_Y end - attribute \src "ls180.v:6100.44-6100.151" - cell $and $and$ls180.v:6100$1542 + attribute \src "ls180.v:6273.44-6273.151" + cell $and $and$ls180.v:6273$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6100$1540_Y - connect \B $eq$ls180.v:6100$1541_Y - connect \Y $and$ls180.v:6100$1542_Y + connect \A $and$ls180.v:6273$1669_Y + connect \B $eq$ls180.v:6273$1670_Y + connect \Y $and$ls180.v:6273$1671_Y end - attribute \src "ls180.v:6102.45-6102.98" - cell $and $and$ls180.v:6102$1543 + attribute \src "ls180.v:6275.45-6275.98" + cell $and $and$ls180.v:6275$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242614,43 +260073,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6102$1543_Y + connect \Y $and$ls180.v:6275$1672_Y end - attribute \src "ls180.v:6102.44-6102.148" - cell $and $and$ls180.v:6102$1545 + attribute \src "ls180.v:6275.44-6275.148" + cell $and $and$ls180.v:6275$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6102$1543_Y - connect \B $eq$ls180.v:6102$1544_Y - connect \Y $and$ls180.v:6102$1545_Y + connect \A $and$ls180.v:6275$1672_Y + connect \B $eq$ls180.v:6275$1673_Y + connect \Y $and$ls180.v:6275$1674_Y end - attribute \src "ls180.v:6103.45-6103.101" - cell $and $and$ls180.v:6103$1547 + attribute \src "ls180.v:6276.45-6276.101" + cell $and $and$ls180.v:6276$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6103$1546_Y - connect \Y $and$ls180.v:6103$1547_Y + connect \B $not$ls180.v:6276$1675_Y + connect \Y $and$ls180.v:6276$1676_Y end - attribute \src "ls180.v:6103.44-6103.151" - cell $and $and$ls180.v:6103$1549 + attribute \src "ls180.v:6276.44-6276.151" + cell $and $and$ls180.v:6276$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6103$1547_Y - connect \B $eq$ls180.v:6103$1548_Y - connect \Y $and$ls180.v:6103$1549_Y + connect \A $and$ls180.v:6276$1676_Y + connect \B $eq$ls180.v:6276$1677_Y + connect \Y $and$ls180.v:6276$1678_Y end - attribute \src "ls180.v:6105.45-6105.98" - cell $and $and$ls180.v:6105$1550 + attribute \src "ls180.v:6278.45-6278.98" + cell $and $and$ls180.v:6278$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242658,43 +260117,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6105$1550_Y + connect \Y $and$ls180.v:6278$1679_Y end - attribute \src "ls180.v:6105.44-6105.148" - cell $and $and$ls180.v:6105$1552 + attribute \src "ls180.v:6278.44-6278.148" + cell $and $and$ls180.v:6278$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6105$1550_Y - connect \B $eq$ls180.v:6105$1551_Y - connect \Y $and$ls180.v:6105$1552_Y + connect \A $and$ls180.v:6278$1679_Y + connect \B $eq$ls180.v:6278$1680_Y + connect \Y $and$ls180.v:6278$1681_Y end - attribute \src "ls180.v:6106.45-6106.101" - cell $and $and$ls180.v:6106$1554 + attribute \src "ls180.v:6279.45-6279.101" + cell $and $and$ls180.v:6279$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6106$1553_Y - connect \Y $and$ls180.v:6106$1554_Y + connect \B $not$ls180.v:6279$1682_Y + connect \Y $and$ls180.v:6279$1683_Y end - attribute \src "ls180.v:6106.44-6106.151" - cell $and $and$ls180.v:6106$1556 + attribute \src "ls180.v:6279.44-6279.151" + cell $and $and$ls180.v:6279$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6106$1554_Y - connect \B $eq$ls180.v:6106$1555_Y - connect \Y $and$ls180.v:6106$1556_Y + connect \A $and$ls180.v:6279$1683_Y + connect \B $eq$ls180.v:6279$1684_Y + connect \Y $and$ls180.v:6279$1685_Y end - attribute \src "ls180.v:6108.45-6108.98" - cell $and $and$ls180.v:6108$1557 + attribute \src "ls180.v:6281.45-6281.98" + cell $and $and$ls180.v:6281$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242702,43 +260161,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6108$1557_Y + connect \Y $and$ls180.v:6281$1686_Y end - attribute \src "ls180.v:6108.44-6108.148" - cell $and $and$ls180.v:6108$1559 + attribute \src "ls180.v:6281.44-6281.148" + cell $and $and$ls180.v:6281$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6108$1557_Y - connect \B $eq$ls180.v:6108$1558_Y - connect \Y $and$ls180.v:6108$1559_Y + connect \A $and$ls180.v:6281$1686_Y + connect \B $eq$ls180.v:6281$1687_Y + connect \Y $and$ls180.v:6281$1688_Y end - attribute \src "ls180.v:6109.45-6109.101" - cell $and $and$ls180.v:6109$1561 + attribute \src "ls180.v:6282.45-6282.101" + cell $and $and$ls180.v:6282$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6109$1560_Y - connect \Y $and$ls180.v:6109$1561_Y + connect \B $not$ls180.v:6282$1689_Y + connect \Y $and$ls180.v:6282$1690_Y end - attribute \src "ls180.v:6109.44-6109.151" - cell $and $and$ls180.v:6109$1563 + attribute \src "ls180.v:6282.44-6282.151" + cell $and $and$ls180.v:6282$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6109$1561_Y - connect \B $eq$ls180.v:6109$1562_Y - connect \Y $and$ls180.v:6109$1563_Y + connect \A $and$ls180.v:6282$1690_Y + connect \B $eq$ls180.v:6282$1691_Y + connect \Y $and$ls180.v:6282$1692_Y end - attribute \src "ls180.v:6111.36-6111.89" - cell $and $and$ls180.v:6111$1564 + attribute \src "ls180.v:6284.36-6284.89" + cell $and $and$ls180.v:6284$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242746,43 +260205,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6111$1564_Y + connect \Y $and$ls180.v:6284$1693_Y end - attribute \src "ls180.v:6111.35-6111.139" - cell $and $and$ls180.v:6111$1566 + attribute \src "ls180.v:6284.35-6284.139" + cell $and $and$ls180.v:6284$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1564_Y - connect \B $eq$ls180.v:6111$1565_Y - connect \Y $and$ls180.v:6111$1566_Y + connect \A $and$ls180.v:6284$1693_Y + connect \B $eq$ls180.v:6284$1694_Y + connect \Y $and$ls180.v:6284$1695_Y end - attribute \src "ls180.v:6112.36-6112.92" - cell $and $and$ls180.v:6112$1568 + attribute \src "ls180.v:6285.36-6285.92" + cell $and $and$ls180.v:6285$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6112$1567_Y - connect \Y $and$ls180.v:6112$1568_Y + connect \B $not$ls180.v:6285$1696_Y + connect \Y $and$ls180.v:6285$1697_Y end - attribute \src "ls180.v:6112.35-6112.142" - cell $and $and$ls180.v:6112$1570 + attribute \src "ls180.v:6285.35-6285.142" + cell $and $and$ls180.v:6285$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6112$1568_Y - connect \B $eq$ls180.v:6112$1569_Y - connect \Y $and$ls180.v:6112$1570_Y + connect \A $and$ls180.v:6285$1697_Y + connect \B $eq$ls180.v:6285$1698_Y + connect \Y $and$ls180.v:6285$1699_Y end - attribute \src "ls180.v:6114.47-6114.100" - cell $and $and$ls180.v:6114$1571 + attribute \src "ls180.v:6287.47-6287.100" + cell $and $and$ls180.v:6287$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242790,43 +260249,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6114$1571_Y + connect \Y $and$ls180.v:6287$1700_Y end - attribute \src "ls180.v:6114.46-6114.150" - cell $and $and$ls180.v:6114$1573 + attribute \src "ls180.v:6287.46-6287.150" + cell $and $and$ls180.v:6287$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6114$1571_Y - connect \B $eq$ls180.v:6114$1572_Y - connect \Y $and$ls180.v:6114$1573_Y + connect \A $and$ls180.v:6287$1700_Y + connect \B $eq$ls180.v:6287$1701_Y + connect \Y $and$ls180.v:6287$1702_Y end - attribute \src "ls180.v:6115.47-6115.103" - cell $and $and$ls180.v:6115$1575 + attribute \src "ls180.v:6288.47-6288.103" + cell $and $and$ls180.v:6288$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6115$1574_Y - connect \Y $and$ls180.v:6115$1575_Y + connect \B $not$ls180.v:6288$1703_Y + connect \Y $and$ls180.v:6288$1704_Y end - attribute \src "ls180.v:6115.46-6115.153" - cell $and $and$ls180.v:6115$1577 + attribute \src "ls180.v:6288.46-6288.153" + cell $and $and$ls180.v:6288$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6115$1575_Y - connect \B $eq$ls180.v:6115$1576_Y - connect \Y $and$ls180.v:6115$1577_Y + connect \A $and$ls180.v:6288$1704_Y + connect \B $eq$ls180.v:6288$1705_Y + connect \Y $and$ls180.v:6288$1706_Y end - attribute \src "ls180.v:6117.47-6117.100" - cell $and $and$ls180.v:6117$1578 + attribute \src "ls180.v:6290.47-6290.100" + cell $and $and$ls180.v:6290$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242834,43 +260293,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6117$1578_Y + connect \Y $and$ls180.v:6290$1707_Y end - attribute \src "ls180.v:6117.46-6117.151" - cell $and $and$ls180.v:6117$1580 + attribute \src "ls180.v:6290.46-6290.151" + cell $and $and$ls180.v:6290$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6117$1578_Y - connect \B $eq$ls180.v:6117$1579_Y - connect \Y $and$ls180.v:6117$1580_Y + connect \A $and$ls180.v:6290$1707_Y + connect \B $eq$ls180.v:6290$1708_Y + connect \Y $and$ls180.v:6290$1709_Y end - attribute \src "ls180.v:6118.47-6118.103" - cell $and $and$ls180.v:6118$1582 + attribute \src "ls180.v:6291.47-6291.103" + cell $and $and$ls180.v:6291$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6118$1581_Y - connect \Y $and$ls180.v:6118$1582_Y + connect \B $not$ls180.v:6291$1710_Y + connect \Y $and$ls180.v:6291$1711_Y end - attribute \src "ls180.v:6118.46-6118.154" - cell $and $and$ls180.v:6118$1584 + attribute \src "ls180.v:6291.46-6291.154" + cell $and $and$ls180.v:6291$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6118$1582_Y - connect \B $eq$ls180.v:6118$1583_Y - connect \Y $and$ls180.v:6118$1584_Y + connect \A $and$ls180.v:6291$1711_Y + connect \B $eq$ls180.v:6291$1712_Y + connect \Y $and$ls180.v:6291$1713_Y end - attribute \src "ls180.v:6120.47-6120.100" - cell $and $and$ls180.v:6120$1585 + attribute \src "ls180.v:6293.47-6293.100" + cell $and $and$ls180.v:6293$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242878,43 +260337,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6120$1585_Y + connect \Y $and$ls180.v:6293$1714_Y end - attribute \src "ls180.v:6120.46-6120.151" - cell $and $and$ls180.v:6120$1587 + attribute \src "ls180.v:6293.46-6293.151" + cell $and $and$ls180.v:6293$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6120$1585_Y - connect \B $eq$ls180.v:6120$1586_Y - connect \Y $and$ls180.v:6120$1587_Y + connect \A $and$ls180.v:6293$1714_Y + connect \B $eq$ls180.v:6293$1715_Y + connect \Y $and$ls180.v:6293$1716_Y end - attribute \src "ls180.v:6121.47-6121.103" - cell $and $and$ls180.v:6121$1589 + attribute \src "ls180.v:6294.47-6294.103" + cell $and $and$ls180.v:6294$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6121$1588_Y - connect \Y $and$ls180.v:6121$1589_Y + connect \B $not$ls180.v:6294$1717_Y + connect \Y $and$ls180.v:6294$1718_Y end - attribute \src "ls180.v:6121.46-6121.154" - cell $and $and$ls180.v:6121$1591 + attribute \src "ls180.v:6294.46-6294.154" + cell $and $and$ls180.v:6294$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6121$1589_Y - connect \B $eq$ls180.v:6121$1590_Y - connect \Y $and$ls180.v:6121$1591_Y + connect \A $and$ls180.v:6294$1718_Y + connect \B $eq$ls180.v:6294$1719_Y + connect \Y $and$ls180.v:6294$1720_Y end - attribute \src "ls180.v:6123.47-6123.100" - cell $and $and$ls180.v:6123$1592 + attribute \src "ls180.v:6296.47-6296.100" + cell $and $and$ls180.v:6296$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242922,43 +260381,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6123$1592_Y + connect \Y $and$ls180.v:6296$1721_Y end - attribute \src "ls180.v:6123.46-6123.151" - cell $and $and$ls180.v:6123$1594 + attribute \src "ls180.v:6296.46-6296.151" + cell $and $and$ls180.v:6296$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6123$1592_Y - connect \B $eq$ls180.v:6123$1593_Y - connect \Y $and$ls180.v:6123$1594_Y + connect \A $and$ls180.v:6296$1721_Y + connect \B $eq$ls180.v:6296$1722_Y + connect \Y $and$ls180.v:6296$1723_Y end - attribute \src "ls180.v:6124.47-6124.103" - cell $and $and$ls180.v:6124$1596 + attribute \src "ls180.v:6297.47-6297.103" + cell $and $and$ls180.v:6297$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6124$1595_Y - connect \Y $and$ls180.v:6124$1596_Y + connect \B $not$ls180.v:6297$1724_Y + connect \Y $and$ls180.v:6297$1725_Y end - attribute \src "ls180.v:6124.46-6124.154" - cell $and $and$ls180.v:6124$1598 + attribute \src "ls180.v:6297.46-6297.154" + cell $and $and$ls180.v:6297$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1596_Y - connect \B $eq$ls180.v:6124$1597_Y - connect \Y $and$ls180.v:6124$1598_Y + connect \A $and$ls180.v:6297$1725_Y + connect \B $eq$ls180.v:6297$1726_Y + connect \Y $and$ls180.v:6297$1727_Y end - attribute \src "ls180.v:6126.47-6126.100" - cell $and $and$ls180.v:6126$1599 + attribute \src "ls180.v:6299.47-6299.100" + cell $and $and$ls180.v:6299$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242966,43 +260425,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6126$1599_Y + connect \Y $and$ls180.v:6299$1728_Y end - attribute \src "ls180.v:6126.46-6126.151" - cell $and $and$ls180.v:6126$1601 + attribute \src "ls180.v:6299.46-6299.151" + cell $and $and$ls180.v:6299$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6126$1599_Y - connect \B $eq$ls180.v:6126$1600_Y - connect \Y $and$ls180.v:6126$1601_Y + connect \A $and$ls180.v:6299$1728_Y + connect \B $eq$ls180.v:6299$1729_Y + connect \Y $and$ls180.v:6299$1730_Y end - attribute \src "ls180.v:6127.47-6127.103" - cell $and $and$ls180.v:6127$1603 + attribute \src "ls180.v:6300.47-6300.103" + cell $and $and$ls180.v:6300$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6127$1602_Y - connect \Y $and$ls180.v:6127$1603_Y + connect \B $not$ls180.v:6300$1731_Y + connect \Y $and$ls180.v:6300$1732_Y end - attribute \src "ls180.v:6127.46-6127.154" - cell $and $and$ls180.v:6127$1605 + attribute \src "ls180.v:6300.46-6300.154" + cell $and $and$ls180.v:6300$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1603_Y - connect \B $eq$ls180.v:6127$1604_Y - connect \Y $and$ls180.v:6127$1605_Y + connect \A $and$ls180.v:6300$1732_Y + connect \B $eq$ls180.v:6300$1733_Y + connect \Y $and$ls180.v:6300$1734_Y end - attribute \src "ls180.v:6129.47-6129.100" - cell $and $and$ls180.v:6129$1606 + attribute \src "ls180.v:6302.47-6302.100" + cell $and $and$ls180.v:6302$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243010,43 +260469,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6129$1606_Y + connect \Y $and$ls180.v:6302$1735_Y end - attribute \src "ls180.v:6129.46-6129.151" - cell $and $and$ls180.v:6129$1608 + attribute \src "ls180.v:6302.46-6302.151" + cell $and $and$ls180.v:6302$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6129$1606_Y - connect \B $eq$ls180.v:6129$1607_Y - connect \Y $and$ls180.v:6129$1608_Y + connect \A $and$ls180.v:6302$1735_Y + connect \B $eq$ls180.v:6302$1736_Y + connect \Y $and$ls180.v:6302$1737_Y end - attribute \src "ls180.v:6130.47-6130.103" - cell $and $and$ls180.v:6130$1610 + attribute \src "ls180.v:6303.47-6303.103" + cell $and $and$ls180.v:6303$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6130$1609_Y - connect \Y $and$ls180.v:6130$1610_Y + connect \B $not$ls180.v:6303$1738_Y + connect \Y $and$ls180.v:6303$1739_Y end - attribute \src "ls180.v:6130.46-6130.154" - cell $and $and$ls180.v:6130$1612 + attribute \src "ls180.v:6303.46-6303.154" + cell $and $and$ls180.v:6303$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1610_Y - connect \B $eq$ls180.v:6130$1611_Y - connect \Y $and$ls180.v:6130$1612_Y + connect \A $and$ls180.v:6303$1739_Y + connect \B $eq$ls180.v:6303$1740_Y + connect \Y $and$ls180.v:6303$1741_Y end - attribute \src "ls180.v:6132.46-6132.99" - cell $and $and$ls180.v:6132$1613 + attribute \src "ls180.v:6305.46-6305.99" + cell $and $and$ls180.v:6305$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243054,43 +260513,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6132$1613_Y + connect \Y $and$ls180.v:6305$1742_Y end - attribute \src "ls180.v:6132.45-6132.150" - cell $and $and$ls180.v:6132$1615 + attribute \src "ls180.v:6305.45-6305.150" + cell $and $and$ls180.v:6305$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6132$1613_Y - connect \B $eq$ls180.v:6132$1614_Y - connect \Y $and$ls180.v:6132$1615_Y + connect \A $and$ls180.v:6305$1742_Y + connect \B $eq$ls180.v:6305$1743_Y + connect \Y $and$ls180.v:6305$1744_Y end - attribute \src "ls180.v:6133.46-6133.102" - cell $and $and$ls180.v:6133$1617 + attribute \src "ls180.v:6306.46-6306.102" + cell $and $and$ls180.v:6306$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6133$1616_Y - connect \Y $and$ls180.v:6133$1617_Y + connect \B $not$ls180.v:6306$1745_Y + connect \Y $and$ls180.v:6306$1746_Y end - attribute \src "ls180.v:6133.45-6133.153" - cell $and $and$ls180.v:6133$1619 + attribute \src "ls180.v:6306.45-6306.153" + cell $and $and$ls180.v:6306$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1617_Y - connect \B $eq$ls180.v:6133$1618_Y - connect \Y $and$ls180.v:6133$1619_Y + connect \A $and$ls180.v:6306$1746_Y + connect \B $eq$ls180.v:6306$1747_Y + connect \Y $and$ls180.v:6306$1748_Y end - attribute \src "ls180.v:6135.46-6135.99" - cell $and $and$ls180.v:6135$1620 + attribute \src "ls180.v:6308.46-6308.99" + cell $and $and$ls180.v:6308$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243098,43 +260557,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6135$1620_Y + connect \Y $and$ls180.v:6308$1749_Y end - attribute \src "ls180.v:6135.45-6135.150" - cell $and $and$ls180.v:6135$1622 + attribute \src "ls180.v:6308.45-6308.150" + cell $and $and$ls180.v:6308$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6135$1620_Y - connect \B $eq$ls180.v:6135$1621_Y - connect \Y $and$ls180.v:6135$1622_Y + connect \A $and$ls180.v:6308$1749_Y + connect \B $eq$ls180.v:6308$1750_Y + connect \Y $and$ls180.v:6308$1751_Y end - attribute \src "ls180.v:6136.46-6136.102" - cell $and $and$ls180.v:6136$1624 + attribute \src "ls180.v:6309.46-6309.102" + cell $and $and$ls180.v:6309$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6136$1623_Y - connect \Y $and$ls180.v:6136$1624_Y + connect \B $not$ls180.v:6309$1752_Y + connect \Y $and$ls180.v:6309$1753_Y end - attribute \src "ls180.v:6136.45-6136.153" - cell $and $and$ls180.v:6136$1626 + attribute \src "ls180.v:6309.45-6309.153" + cell $and $and$ls180.v:6309$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1624_Y - connect \B $eq$ls180.v:6136$1625_Y - connect \Y $and$ls180.v:6136$1626_Y + connect \A $and$ls180.v:6309$1753_Y + connect \B $eq$ls180.v:6309$1754_Y + connect \Y $and$ls180.v:6309$1755_Y end - attribute \src "ls180.v:6138.46-6138.99" - cell $and $and$ls180.v:6138$1627 + attribute \src "ls180.v:6311.46-6311.99" + cell $and $and$ls180.v:6311$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243142,43 +260601,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6138$1627_Y + connect \Y $and$ls180.v:6311$1756_Y end - attribute \src "ls180.v:6138.45-6138.150" - cell $and $and$ls180.v:6138$1629 + attribute \src "ls180.v:6311.45-6311.150" + cell $and $and$ls180.v:6311$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6138$1627_Y - connect \B $eq$ls180.v:6138$1628_Y - connect \Y $and$ls180.v:6138$1629_Y + connect \A $and$ls180.v:6311$1756_Y + connect \B $eq$ls180.v:6311$1757_Y + connect \Y $and$ls180.v:6311$1758_Y end - attribute \src "ls180.v:6139.46-6139.102" - cell $and $and$ls180.v:6139$1631 + attribute \src "ls180.v:6312.46-6312.102" + cell $and $and$ls180.v:6312$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6139$1630_Y - connect \Y $and$ls180.v:6139$1631_Y + connect \B $not$ls180.v:6312$1759_Y + connect \Y $and$ls180.v:6312$1760_Y end - attribute \src "ls180.v:6139.45-6139.153" - cell $and $and$ls180.v:6139$1633 + attribute \src "ls180.v:6312.45-6312.153" + cell $and $and$ls180.v:6312$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1631_Y - connect \B $eq$ls180.v:6139$1632_Y - connect \Y $and$ls180.v:6139$1633_Y + connect \A $and$ls180.v:6312$1760_Y + connect \B $eq$ls180.v:6312$1761_Y + connect \Y $and$ls180.v:6312$1762_Y end - attribute \src "ls180.v:6141.46-6141.99" - cell $and $and$ls180.v:6141$1634 + attribute \src "ls180.v:6314.46-6314.99" + cell $and $and$ls180.v:6314$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243186,43 +260645,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6141$1634_Y + connect \Y $and$ls180.v:6314$1763_Y end - attribute \src "ls180.v:6141.45-6141.150" - cell $and $and$ls180.v:6141$1636 + attribute \src "ls180.v:6314.45-6314.150" + cell $and $and$ls180.v:6314$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6141$1634_Y - connect \B $eq$ls180.v:6141$1635_Y - connect \Y $and$ls180.v:6141$1636_Y + connect \A $and$ls180.v:6314$1763_Y + connect \B $eq$ls180.v:6314$1764_Y + connect \Y $and$ls180.v:6314$1765_Y end - attribute \src "ls180.v:6142.46-6142.102" - cell $and $and$ls180.v:6142$1638 + attribute \src "ls180.v:6315.46-6315.102" + cell $and $and$ls180.v:6315$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6142$1637_Y - connect \Y $and$ls180.v:6142$1638_Y + connect \B $not$ls180.v:6315$1766_Y + connect \Y $and$ls180.v:6315$1767_Y end - attribute \src "ls180.v:6142.45-6142.153" - cell $and $and$ls180.v:6142$1640 + attribute \src "ls180.v:6315.45-6315.153" + cell $and $and$ls180.v:6315$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1638_Y - connect \B $eq$ls180.v:6142$1639_Y - connect \Y $and$ls180.v:6142$1640_Y + connect \A $and$ls180.v:6315$1767_Y + connect \B $eq$ls180.v:6315$1768_Y + connect \Y $and$ls180.v:6315$1769_Y end - attribute \src "ls180.v:6144.46-6144.99" - cell $and $and$ls180.v:6144$1641 + attribute \src "ls180.v:6317.46-6317.99" + cell $and $and$ls180.v:6317$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243230,43 +260689,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6144$1641_Y + connect \Y $and$ls180.v:6317$1770_Y end - attribute \src "ls180.v:6144.45-6144.150" - cell $and $and$ls180.v:6144$1643 + attribute \src "ls180.v:6317.45-6317.150" + cell $and $and$ls180.v:6317$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6144$1641_Y - connect \B $eq$ls180.v:6144$1642_Y - connect \Y $and$ls180.v:6144$1643_Y + connect \A $and$ls180.v:6317$1770_Y + connect \B $eq$ls180.v:6317$1771_Y + connect \Y $and$ls180.v:6317$1772_Y end - attribute \src "ls180.v:6145.46-6145.102" - cell $and $and$ls180.v:6145$1645 + attribute \src "ls180.v:6318.46-6318.102" + cell $and $and$ls180.v:6318$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6145$1644_Y - connect \Y $and$ls180.v:6145$1645_Y + connect \B $not$ls180.v:6318$1773_Y + connect \Y $and$ls180.v:6318$1774_Y end - attribute \src "ls180.v:6145.45-6145.153" - cell $and $and$ls180.v:6145$1647 + attribute \src "ls180.v:6318.45-6318.153" + cell $and $and$ls180.v:6318$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1645_Y - connect \B $eq$ls180.v:6145$1646_Y - connect \Y $and$ls180.v:6145$1647_Y + connect \A $and$ls180.v:6318$1774_Y + connect \B $eq$ls180.v:6318$1775_Y + connect \Y $and$ls180.v:6318$1776_Y end - attribute \src "ls180.v:6147.46-6147.99" - cell $and $and$ls180.v:6147$1648 + attribute \src "ls180.v:6320.46-6320.99" + cell $and $and$ls180.v:6320$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243274,43 +260733,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6147$1648_Y + connect \Y $and$ls180.v:6320$1777_Y end - attribute \src "ls180.v:6147.45-6147.150" - cell $and $and$ls180.v:6147$1650 + attribute \src "ls180.v:6320.45-6320.150" + cell $and $and$ls180.v:6320$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6147$1648_Y - connect \B $eq$ls180.v:6147$1649_Y - connect \Y $and$ls180.v:6147$1650_Y + connect \A $and$ls180.v:6320$1777_Y + connect \B $eq$ls180.v:6320$1778_Y + connect \Y $and$ls180.v:6320$1779_Y end - attribute \src "ls180.v:6148.46-6148.102" - cell $and $and$ls180.v:6148$1652 + attribute \src "ls180.v:6321.46-6321.102" + cell $and $and$ls180.v:6321$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6148$1651_Y - connect \Y $and$ls180.v:6148$1652_Y + connect \B $not$ls180.v:6321$1780_Y + connect \Y $and$ls180.v:6321$1781_Y end - attribute \src "ls180.v:6148.45-6148.153" - cell $and $and$ls180.v:6148$1654 + attribute \src "ls180.v:6321.45-6321.153" + cell $and $and$ls180.v:6321$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6148$1652_Y - connect \B $eq$ls180.v:6148$1653_Y - connect \Y $and$ls180.v:6148$1654_Y + connect \A $and$ls180.v:6321$1781_Y + connect \B $eq$ls180.v:6321$1782_Y + connect \Y $and$ls180.v:6321$1783_Y end - attribute \src "ls180.v:6150.46-6150.99" - cell $and $and$ls180.v:6150$1655 + attribute \src "ls180.v:6323.46-6323.99" + cell $and $and$ls180.v:6323$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243318,43 +260777,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6150$1655_Y + connect \Y $and$ls180.v:6323$1784_Y end - attribute \src "ls180.v:6150.45-6150.150" - cell $and $and$ls180.v:6150$1657 + attribute \src "ls180.v:6323.45-6323.150" + cell $and $and$ls180.v:6323$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6150$1655_Y - connect \B $eq$ls180.v:6150$1656_Y - connect \Y $and$ls180.v:6150$1657_Y + connect \A $and$ls180.v:6323$1784_Y + connect \B $eq$ls180.v:6323$1785_Y + connect \Y $and$ls180.v:6323$1786_Y end - attribute \src "ls180.v:6151.46-6151.102" - cell $and $and$ls180.v:6151$1659 + attribute \src "ls180.v:6324.46-6324.102" + cell $and $and$ls180.v:6324$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6151$1658_Y - connect \Y $and$ls180.v:6151$1659_Y + connect \B $not$ls180.v:6324$1787_Y + connect \Y $and$ls180.v:6324$1788_Y end - attribute \src "ls180.v:6151.45-6151.153" - cell $and $and$ls180.v:6151$1661 + attribute \src "ls180.v:6324.45-6324.153" + cell $and $and$ls180.v:6324$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6151$1659_Y - connect \B $eq$ls180.v:6151$1660_Y - connect \Y $and$ls180.v:6151$1661_Y + connect \A $and$ls180.v:6324$1788_Y + connect \B $eq$ls180.v:6324$1789_Y + connect \Y $and$ls180.v:6324$1790_Y end - attribute \src "ls180.v:6153.46-6153.99" - cell $and $and$ls180.v:6153$1662 + attribute \src "ls180.v:6326.46-6326.99" + cell $and $and$ls180.v:6326$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243362,43 +260821,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6153$1662_Y + connect \Y $and$ls180.v:6326$1791_Y end - attribute \src "ls180.v:6153.45-6153.150" - cell $and $and$ls180.v:6153$1664 + attribute \src "ls180.v:6326.45-6326.150" + cell $and $and$ls180.v:6326$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6153$1662_Y - connect \B $eq$ls180.v:6153$1663_Y - connect \Y $and$ls180.v:6153$1664_Y + connect \A $and$ls180.v:6326$1791_Y + connect \B $eq$ls180.v:6326$1792_Y + connect \Y $and$ls180.v:6326$1793_Y end - attribute \src "ls180.v:6154.46-6154.102" - cell $and $and$ls180.v:6154$1666 + attribute \src "ls180.v:6327.46-6327.102" + cell $and $and$ls180.v:6327$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6154$1665_Y - connect \Y $and$ls180.v:6154$1666_Y + connect \B $not$ls180.v:6327$1794_Y + connect \Y $and$ls180.v:6327$1795_Y end - attribute \src "ls180.v:6154.45-6154.153" - cell $and $and$ls180.v:6154$1668 + attribute \src "ls180.v:6327.45-6327.153" + cell $and $and$ls180.v:6327$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6154$1666_Y - connect \B $eq$ls180.v:6154$1667_Y - connect \Y $and$ls180.v:6154$1668_Y + connect \A $and$ls180.v:6327$1795_Y + connect \B $eq$ls180.v:6327$1796_Y + connect \Y $and$ls180.v:6327$1797_Y end - attribute \src "ls180.v:6156.46-6156.99" - cell $and $and$ls180.v:6156$1669 + attribute \src "ls180.v:6329.46-6329.99" + cell $and $and$ls180.v:6329$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243406,43 +260865,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6156$1669_Y + connect \Y $and$ls180.v:6329$1798_Y end - attribute \src "ls180.v:6156.45-6156.150" - cell $and $and$ls180.v:6156$1671 + attribute \src "ls180.v:6329.45-6329.150" + cell $and $and$ls180.v:6329$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6156$1669_Y - connect \B $eq$ls180.v:6156$1670_Y - connect \Y $and$ls180.v:6156$1671_Y + connect \A $and$ls180.v:6329$1798_Y + connect \B $eq$ls180.v:6329$1799_Y + connect \Y $and$ls180.v:6329$1800_Y end - attribute \src "ls180.v:6157.46-6157.102" - cell $and $and$ls180.v:6157$1673 + attribute \src "ls180.v:6330.46-6330.102" + cell $and $and$ls180.v:6330$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6157$1672_Y - connect \Y $and$ls180.v:6157$1673_Y + connect \B $not$ls180.v:6330$1801_Y + connect \Y $and$ls180.v:6330$1802_Y end - attribute \src "ls180.v:6157.45-6157.153" - cell $and $and$ls180.v:6157$1675 + attribute \src "ls180.v:6330.45-6330.153" + cell $and $and$ls180.v:6330$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6157$1673_Y - connect \B $eq$ls180.v:6157$1674_Y - connect \Y $and$ls180.v:6157$1675_Y + connect \A $and$ls180.v:6330$1802_Y + connect \B $eq$ls180.v:6330$1803_Y + connect \Y $and$ls180.v:6330$1804_Y end - attribute \src "ls180.v:6159.46-6159.99" - cell $and $and$ls180.v:6159$1676 + attribute \src "ls180.v:6332.46-6332.99" + cell $and $and$ls180.v:6332$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243450,43 +260909,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6159$1676_Y + connect \Y $and$ls180.v:6332$1805_Y end - attribute \src "ls180.v:6159.45-6159.150" - cell $and $and$ls180.v:6159$1678 + attribute \src "ls180.v:6332.45-6332.150" + cell $and $and$ls180.v:6332$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6159$1676_Y - connect \B $eq$ls180.v:6159$1677_Y - connect \Y $and$ls180.v:6159$1678_Y + connect \A $and$ls180.v:6332$1805_Y + connect \B $eq$ls180.v:6332$1806_Y + connect \Y $and$ls180.v:6332$1807_Y end - attribute \src "ls180.v:6160.46-6160.102" - cell $and $and$ls180.v:6160$1680 + attribute \src "ls180.v:6333.46-6333.102" + cell $and $and$ls180.v:6333$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6160$1679_Y - connect \Y $and$ls180.v:6160$1680_Y + connect \B $not$ls180.v:6333$1808_Y + connect \Y $and$ls180.v:6333$1809_Y end - attribute \src "ls180.v:6160.45-6160.153" - cell $and $and$ls180.v:6160$1682 + attribute \src "ls180.v:6333.45-6333.153" + cell $and $and$ls180.v:6333$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6160$1680_Y - connect \B $eq$ls180.v:6160$1681_Y - connect \Y $and$ls180.v:6160$1682_Y + connect \A $and$ls180.v:6333$1809_Y + connect \B $eq$ls180.v:6333$1810_Y + connect \Y $and$ls180.v:6333$1811_Y end - attribute \src "ls180.v:6162.42-6162.95" - cell $and $and$ls180.v:6162$1683 + attribute \src "ls180.v:6335.42-6335.95" + cell $and $and$ls180.v:6335$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243494,43 +260953,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6162$1683_Y + connect \Y $and$ls180.v:6335$1812_Y end - attribute \src "ls180.v:6162.41-6162.146" - cell $and $and$ls180.v:6162$1685 + attribute \src "ls180.v:6335.41-6335.146" + cell $and $and$ls180.v:6335$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1683_Y - connect \B $eq$ls180.v:6162$1684_Y - connect \Y $and$ls180.v:6162$1685_Y + connect \A $and$ls180.v:6335$1812_Y + connect \B $eq$ls180.v:6335$1813_Y + connect \Y $and$ls180.v:6335$1814_Y end - attribute \src "ls180.v:6163.42-6163.98" - cell $and $and$ls180.v:6163$1687 + attribute \src "ls180.v:6336.42-6336.98" + cell $and $and$ls180.v:6336$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6163$1686_Y - connect \Y $and$ls180.v:6163$1687_Y + connect \B $not$ls180.v:6336$1815_Y + connect \Y $and$ls180.v:6336$1816_Y end - attribute \src "ls180.v:6163.41-6163.149" - cell $and $and$ls180.v:6163$1689 + attribute \src "ls180.v:6336.41-6336.149" + cell $and $and$ls180.v:6336$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6163$1687_Y - connect \B $eq$ls180.v:6163$1688_Y - connect \Y $and$ls180.v:6163$1689_Y + connect \A $and$ls180.v:6336$1816_Y + connect \B $eq$ls180.v:6336$1817_Y + connect \Y $and$ls180.v:6336$1818_Y end - attribute \src "ls180.v:6165.43-6165.96" - cell $and $and$ls180.v:6165$1690 + attribute \src "ls180.v:6338.43-6338.96" + cell $and $and$ls180.v:6338$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243538,43 +260997,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6165$1690_Y + connect \Y $and$ls180.v:6338$1819_Y end - attribute \src "ls180.v:6165.42-6165.147" - cell $and $and$ls180.v:6165$1692 + attribute \src "ls180.v:6338.42-6338.147" + cell $and $and$ls180.v:6338$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6165$1690_Y - connect \B $eq$ls180.v:6165$1691_Y - connect \Y $and$ls180.v:6165$1692_Y + connect \A $and$ls180.v:6338$1819_Y + connect \B $eq$ls180.v:6338$1820_Y + connect \Y $and$ls180.v:6338$1821_Y end - attribute \src "ls180.v:6166.43-6166.99" - cell $and $and$ls180.v:6166$1694 + attribute \src "ls180.v:6339.43-6339.99" + cell $and $and$ls180.v:6339$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6166$1693_Y - connect \Y $and$ls180.v:6166$1694_Y + connect \B $not$ls180.v:6339$1822_Y + connect \Y $and$ls180.v:6339$1823_Y end - attribute \src "ls180.v:6166.42-6166.150" - cell $and $and$ls180.v:6166$1696 + attribute \src "ls180.v:6339.42-6339.150" + cell $and $and$ls180.v:6339$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6166$1694_Y - connect \B $eq$ls180.v:6166$1695_Y - connect \Y $and$ls180.v:6166$1696_Y + connect \A $and$ls180.v:6339$1823_Y + connect \B $eq$ls180.v:6339$1824_Y + connect \Y $and$ls180.v:6339$1825_Y end - attribute \src "ls180.v:6168.46-6168.99" - cell $and $and$ls180.v:6168$1697 + attribute \src "ls180.v:6341.46-6341.99" + cell $and $and$ls180.v:6341$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243582,43 +261041,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6168$1697_Y + connect \Y $and$ls180.v:6341$1826_Y end - attribute \src "ls180.v:6168.45-6168.150" - cell $and $and$ls180.v:6168$1699 + attribute \src "ls180.v:6341.45-6341.150" + cell $and $and$ls180.v:6341$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6168$1697_Y - connect \B $eq$ls180.v:6168$1698_Y - connect \Y $and$ls180.v:6168$1699_Y + connect \A $and$ls180.v:6341$1826_Y + connect \B $eq$ls180.v:6341$1827_Y + connect \Y $and$ls180.v:6341$1828_Y end - attribute \src "ls180.v:6169.46-6169.102" - cell $and $and$ls180.v:6169$1701 + attribute \src "ls180.v:6342.46-6342.102" + cell $and $and$ls180.v:6342$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6169$1700_Y - connect \Y $and$ls180.v:6169$1701_Y + connect \B $not$ls180.v:6342$1829_Y + connect \Y $and$ls180.v:6342$1830_Y end - attribute \src "ls180.v:6169.45-6169.153" - cell $and $and$ls180.v:6169$1703 + attribute \src "ls180.v:6342.45-6342.153" + cell $and $and$ls180.v:6342$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6169$1701_Y - connect \B $eq$ls180.v:6169$1702_Y - connect \Y $and$ls180.v:6169$1703_Y + connect \A $and$ls180.v:6342$1830_Y + connect \B $eq$ls180.v:6342$1831_Y + connect \Y $and$ls180.v:6342$1832_Y end - attribute \src "ls180.v:6171.46-6171.99" - cell $and $and$ls180.v:6171$1704 + attribute \src "ls180.v:6344.46-6344.99" + cell $and $and$ls180.v:6344$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243626,43 +261085,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6171$1704_Y + connect \Y $and$ls180.v:6344$1833_Y end - attribute \src "ls180.v:6171.45-6171.150" - cell $and $and$ls180.v:6171$1706 + attribute \src "ls180.v:6344.45-6344.150" + cell $and $and$ls180.v:6344$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6171$1704_Y - connect \B $eq$ls180.v:6171$1705_Y - connect \Y $and$ls180.v:6171$1706_Y + connect \A $and$ls180.v:6344$1833_Y + connect \B $eq$ls180.v:6344$1834_Y + connect \Y $and$ls180.v:6344$1835_Y end - attribute \src "ls180.v:6172.46-6172.102" - cell $and $and$ls180.v:6172$1708 + attribute \src "ls180.v:6345.46-6345.102" + cell $and $and$ls180.v:6345$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6172$1707_Y - connect \Y $and$ls180.v:6172$1708_Y + connect \B $not$ls180.v:6345$1836_Y + connect \Y $and$ls180.v:6345$1837_Y end - attribute \src "ls180.v:6172.45-6172.153" - cell $and $and$ls180.v:6172$1710 + attribute \src "ls180.v:6345.45-6345.153" + cell $and $and$ls180.v:6345$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6172$1708_Y - connect \B $eq$ls180.v:6172$1709_Y - connect \Y $and$ls180.v:6172$1710_Y + connect \A $and$ls180.v:6345$1837_Y + connect \B $eq$ls180.v:6345$1838_Y + connect \Y $and$ls180.v:6345$1839_Y end - attribute \src "ls180.v:6174.45-6174.98" - cell $and $and$ls180.v:6174$1711 + attribute \src "ls180.v:6347.45-6347.98" + cell $and $and$ls180.v:6347$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243670,43 +261129,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6174$1711_Y + connect \Y $and$ls180.v:6347$1840_Y end - attribute \src "ls180.v:6174.44-6174.149" - cell $and $and$ls180.v:6174$1713 + attribute \src "ls180.v:6347.44-6347.149" + cell $and $and$ls180.v:6347$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6174$1711_Y - connect \B $eq$ls180.v:6174$1712_Y - connect \Y $and$ls180.v:6174$1713_Y + connect \A $and$ls180.v:6347$1840_Y + connect \B $eq$ls180.v:6347$1841_Y + connect \Y $and$ls180.v:6347$1842_Y end - attribute \src "ls180.v:6175.45-6175.101" - cell $and $and$ls180.v:6175$1715 + attribute \src "ls180.v:6348.45-6348.101" + cell $and $and$ls180.v:6348$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6175$1714_Y - connect \Y $and$ls180.v:6175$1715_Y + connect \B $not$ls180.v:6348$1843_Y + connect \Y $and$ls180.v:6348$1844_Y end - attribute \src "ls180.v:6175.44-6175.152" - cell $and $and$ls180.v:6175$1717 + attribute \src "ls180.v:6348.44-6348.152" + cell $and $and$ls180.v:6348$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6175$1715_Y - connect \B $eq$ls180.v:6175$1716_Y - connect \Y $and$ls180.v:6175$1717_Y + connect \A $and$ls180.v:6348$1844_Y + connect \B $eq$ls180.v:6348$1845_Y + connect \Y $and$ls180.v:6348$1846_Y end - attribute \src "ls180.v:6177.45-6177.98" - cell $and $and$ls180.v:6177$1718 + attribute \src "ls180.v:6350.45-6350.98" + cell $and $and$ls180.v:6350$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243714,43 +261173,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6177$1718_Y + connect \Y $and$ls180.v:6350$1847_Y end - attribute \src "ls180.v:6177.44-6177.149" - cell $and $and$ls180.v:6177$1720 + attribute \src "ls180.v:6350.44-6350.149" + cell $and $and$ls180.v:6350$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6177$1718_Y - connect \B $eq$ls180.v:6177$1719_Y - connect \Y $and$ls180.v:6177$1720_Y + connect \A $and$ls180.v:6350$1847_Y + connect \B $eq$ls180.v:6350$1848_Y + connect \Y $and$ls180.v:6350$1849_Y end - attribute \src "ls180.v:6178.45-6178.101" - cell $and $and$ls180.v:6178$1722 + attribute \src "ls180.v:6351.45-6351.101" + cell $and $and$ls180.v:6351$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6178$1721_Y - connect \Y $and$ls180.v:6178$1722_Y + connect \B $not$ls180.v:6351$1850_Y + connect \Y $and$ls180.v:6351$1851_Y end - attribute \src "ls180.v:6178.44-6178.152" - cell $and $and$ls180.v:6178$1724 + attribute \src "ls180.v:6351.44-6351.152" + cell $and $and$ls180.v:6351$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6178$1722_Y - connect \B $eq$ls180.v:6178$1723_Y - connect \Y $and$ls180.v:6178$1724_Y + connect \A $and$ls180.v:6351$1851_Y + connect \B $eq$ls180.v:6351$1852_Y + connect \Y $and$ls180.v:6351$1853_Y end - attribute \src "ls180.v:6180.45-6180.98" - cell $and $and$ls180.v:6180$1725 + attribute \src "ls180.v:6353.45-6353.98" + cell $and $and$ls180.v:6353$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243758,43 +261217,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6180$1725_Y + connect \Y $and$ls180.v:6353$1854_Y end - attribute \src "ls180.v:6180.44-6180.149" - cell $and $and$ls180.v:6180$1727 + attribute \src "ls180.v:6353.44-6353.149" + cell $and $and$ls180.v:6353$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6180$1725_Y - connect \B $eq$ls180.v:6180$1726_Y - connect \Y $and$ls180.v:6180$1727_Y + connect \A $and$ls180.v:6353$1854_Y + connect \B $eq$ls180.v:6353$1855_Y + connect \Y $and$ls180.v:6353$1856_Y end - attribute \src "ls180.v:6181.45-6181.101" - cell $and $and$ls180.v:6181$1729 + attribute \src "ls180.v:6354.45-6354.101" + cell $and $and$ls180.v:6354$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6181$1728_Y - connect \Y $and$ls180.v:6181$1729_Y + connect \B $not$ls180.v:6354$1857_Y + connect \Y $and$ls180.v:6354$1858_Y end - attribute \src "ls180.v:6181.44-6181.152" - cell $and $and$ls180.v:6181$1731 + attribute \src "ls180.v:6354.44-6354.152" + cell $and $and$ls180.v:6354$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6181$1729_Y - connect \B $eq$ls180.v:6181$1730_Y - connect \Y $and$ls180.v:6181$1731_Y + connect \A $and$ls180.v:6354$1858_Y + connect \B $eq$ls180.v:6354$1859_Y + connect \Y $and$ls180.v:6354$1860_Y end - attribute \src "ls180.v:6183.45-6183.98" - cell $and $and$ls180.v:6183$1732 + attribute \src "ls180.v:6356.45-6356.98" + cell $and $and$ls180.v:6356$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243802,43 +261261,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6183$1732_Y + connect \Y $and$ls180.v:6356$1861_Y end - attribute \src "ls180.v:6183.44-6183.149" - cell $and $and$ls180.v:6183$1734 + attribute \src "ls180.v:6356.44-6356.149" + cell $and $and$ls180.v:6356$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6183$1732_Y - connect \B $eq$ls180.v:6183$1733_Y - connect \Y $and$ls180.v:6183$1734_Y + connect \A $and$ls180.v:6356$1861_Y + connect \B $eq$ls180.v:6356$1862_Y + connect \Y $and$ls180.v:6356$1863_Y end - attribute \src "ls180.v:6184.45-6184.101" - cell $and $and$ls180.v:6184$1736 + attribute \src "ls180.v:6357.45-6357.101" + cell $and $and$ls180.v:6357$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6184$1735_Y - connect \Y $and$ls180.v:6184$1736_Y + connect \B $not$ls180.v:6357$1864_Y + connect \Y $and$ls180.v:6357$1865_Y end - attribute \src "ls180.v:6184.44-6184.152" - cell $and $and$ls180.v:6184$1738 + attribute \src "ls180.v:6357.44-6357.152" + cell $and $and$ls180.v:6357$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6184$1736_Y - connect \B $eq$ls180.v:6184$1737_Y - connect \Y $and$ls180.v:6184$1738_Y + connect \A $and$ls180.v:6357$1865_Y + connect \B $eq$ls180.v:6357$1866_Y + connect \Y $and$ls180.v:6357$1867_Y end - attribute \src "ls180.v:6222.42-6222.95" - cell $and $and$ls180.v:6222$1740 + attribute \src "ls180.v:6395.42-6395.95" + cell $and $and$ls180.v:6395$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243846,43 +261305,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6222$1740_Y + connect \Y $and$ls180.v:6395$1869_Y end - attribute \src "ls180.v:6222.41-6222.145" - cell $and $and$ls180.v:6222$1742 + attribute \src "ls180.v:6395.41-6395.145" + cell $and $and$ls180.v:6395$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1740_Y - connect \B $eq$ls180.v:6222$1741_Y - connect \Y $and$ls180.v:6222$1742_Y + connect \A $and$ls180.v:6395$1869_Y + connect \B $eq$ls180.v:6395$1870_Y + connect \Y $and$ls180.v:6395$1871_Y end - attribute \src "ls180.v:6223.42-6223.98" - cell $and $and$ls180.v:6223$1744 + attribute \src "ls180.v:6396.42-6396.98" + cell $and $and$ls180.v:6396$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6223$1743_Y - connect \Y $and$ls180.v:6223$1744_Y + connect \B $not$ls180.v:6396$1872_Y + connect \Y $and$ls180.v:6396$1873_Y end - attribute \src "ls180.v:6223.41-6223.148" - cell $and $and$ls180.v:6223$1746 + attribute \src "ls180.v:6396.41-6396.148" + cell $and $and$ls180.v:6396$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1744_Y - connect \B $eq$ls180.v:6223$1745_Y - connect \Y $and$ls180.v:6223$1746_Y + connect \A $and$ls180.v:6396$1873_Y + connect \B $eq$ls180.v:6396$1874_Y + connect \Y $and$ls180.v:6396$1875_Y end - attribute \src "ls180.v:6225.42-6225.95" - cell $and $and$ls180.v:6225$1747 + attribute \src "ls180.v:6398.42-6398.95" + cell $and $and$ls180.v:6398$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243890,43 +261349,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6225$1747_Y + connect \Y $and$ls180.v:6398$1876_Y end - attribute \src "ls180.v:6225.41-6225.145" - cell $and $and$ls180.v:6225$1749 + attribute \src "ls180.v:6398.41-6398.145" + cell $and $and$ls180.v:6398$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1747_Y - connect \B $eq$ls180.v:6225$1748_Y - connect \Y $and$ls180.v:6225$1749_Y + connect \A $and$ls180.v:6398$1876_Y + connect \B $eq$ls180.v:6398$1877_Y + connect \Y $and$ls180.v:6398$1878_Y end - attribute \src "ls180.v:6226.42-6226.98" - cell $and $and$ls180.v:6226$1751 + attribute \src "ls180.v:6399.42-6399.98" + cell $and $and$ls180.v:6399$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6226$1750_Y - connect \Y $and$ls180.v:6226$1751_Y + connect \B $not$ls180.v:6399$1879_Y + connect \Y $and$ls180.v:6399$1880_Y end - attribute \src "ls180.v:6226.41-6226.148" - cell $and $and$ls180.v:6226$1753 + attribute \src "ls180.v:6399.41-6399.148" + cell $and $and$ls180.v:6399$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1751_Y - connect \B $eq$ls180.v:6226$1752_Y - connect \Y $and$ls180.v:6226$1753_Y + connect \A $and$ls180.v:6399$1880_Y + connect \B $eq$ls180.v:6399$1881_Y + connect \Y $and$ls180.v:6399$1882_Y end - attribute \src "ls180.v:6228.42-6228.95" - cell $and $and$ls180.v:6228$1754 + attribute \src "ls180.v:6401.42-6401.95" + cell $and $and$ls180.v:6401$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243934,43 +261393,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6228$1754_Y + connect \Y $and$ls180.v:6401$1883_Y end - attribute \src "ls180.v:6228.41-6228.145" - cell $and $and$ls180.v:6228$1756 + attribute \src "ls180.v:6401.41-6401.145" + cell $and $and$ls180.v:6401$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1754_Y - connect \B $eq$ls180.v:6228$1755_Y - connect \Y $and$ls180.v:6228$1756_Y + connect \A $and$ls180.v:6401$1883_Y + connect \B $eq$ls180.v:6401$1884_Y + connect \Y $and$ls180.v:6401$1885_Y end - attribute \src "ls180.v:6229.42-6229.98" - cell $and $and$ls180.v:6229$1758 + attribute \src "ls180.v:6402.42-6402.98" + cell $and $and$ls180.v:6402$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6229$1757_Y - connect \Y $and$ls180.v:6229$1758_Y + connect \B $not$ls180.v:6402$1886_Y + connect \Y $and$ls180.v:6402$1887_Y end - attribute \src "ls180.v:6229.41-6229.148" - cell $and $and$ls180.v:6229$1760 + attribute \src "ls180.v:6402.41-6402.148" + cell $and $and$ls180.v:6402$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1758_Y - connect \B $eq$ls180.v:6229$1759_Y - connect \Y $and$ls180.v:6229$1760_Y + connect \A $and$ls180.v:6402$1887_Y + connect \B $eq$ls180.v:6402$1888_Y + connect \Y $and$ls180.v:6402$1889_Y end - attribute \src "ls180.v:6231.42-6231.95" - cell $and $and$ls180.v:6231$1761 + attribute \src "ls180.v:6404.42-6404.95" + cell $and $and$ls180.v:6404$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243978,43 +261437,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6231$1761_Y + connect \Y $and$ls180.v:6404$1890_Y end - attribute \src "ls180.v:6231.41-6231.145" - cell $and $and$ls180.v:6231$1763 + attribute \src "ls180.v:6404.41-6404.145" + cell $and $and$ls180.v:6404$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6231$1761_Y - connect \B $eq$ls180.v:6231$1762_Y - connect \Y $and$ls180.v:6231$1763_Y + connect \A $and$ls180.v:6404$1890_Y + connect \B $eq$ls180.v:6404$1891_Y + connect \Y $and$ls180.v:6404$1892_Y end - attribute \src "ls180.v:6232.42-6232.98" - cell $and $and$ls180.v:6232$1765 + attribute \src "ls180.v:6405.42-6405.98" + cell $and $and$ls180.v:6405$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6232$1764_Y - connect \Y $and$ls180.v:6232$1765_Y + connect \B $not$ls180.v:6405$1893_Y + connect \Y $and$ls180.v:6405$1894_Y end - attribute \src "ls180.v:6232.41-6232.148" - cell $and $and$ls180.v:6232$1767 + attribute \src "ls180.v:6405.41-6405.148" + cell $and $and$ls180.v:6405$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1765_Y - connect \B $eq$ls180.v:6232$1766_Y - connect \Y $and$ls180.v:6232$1767_Y + connect \A $and$ls180.v:6405$1894_Y + connect \B $eq$ls180.v:6405$1895_Y + connect \Y $and$ls180.v:6405$1896_Y end - attribute \src "ls180.v:6234.42-6234.95" - cell $and $and$ls180.v:6234$1768 + attribute \src "ls180.v:6407.42-6407.95" + cell $and $and$ls180.v:6407$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244022,43 +261481,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6234$1768_Y + connect \Y $and$ls180.v:6407$1897_Y end - attribute \src "ls180.v:6234.41-6234.145" - cell $and $and$ls180.v:6234$1770 + attribute \src "ls180.v:6407.41-6407.145" + cell $and $and$ls180.v:6407$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6234$1768_Y - connect \B $eq$ls180.v:6234$1769_Y - connect \Y $and$ls180.v:6234$1770_Y + connect \A $and$ls180.v:6407$1897_Y + connect \B $eq$ls180.v:6407$1898_Y + connect \Y $and$ls180.v:6407$1899_Y end - attribute \src "ls180.v:6235.42-6235.98" - cell $and $and$ls180.v:6235$1772 + attribute \src "ls180.v:6408.42-6408.98" + cell $and $and$ls180.v:6408$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6235$1771_Y - connect \Y $and$ls180.v:6235$1772_Y + connect \B $not$ls180.v:6408$1900_Y + connect \Y $and$ls180.v:6408$1901_Y end - attribute \src "ls180.v:6235.41-6235.148" - cell $and $and$ls180.v:6235$1774 + attribute \src "ls180.v:6408.41-6408.148" + cell $and $and$ls180.v:6408$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1772_Y - connect \B $eq$ls180.v:6235$1773_Y - connect \Y $and$ls180.v:6235$1774_Y + connect \A $and$ls180.v:6408$1901_Y + connect \B $eq$ls180.v:6408$1902_Y + connect \Y $and$ls180.v:6408$1903_Y end - attribute \src "ls180.v:6237.42-6237.95" - cell $and $and$ls180.v:6237$1775 + attribute \src "ls180.v:6410.42-6410.95" + cell $and $and$ls180.v:6410$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244066,43 +261525,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6237$1775_Y + connect \Y $and$ls180.v:6410$1904_Y end - attribute \src "ls180.v:6237.41-6237.145" - cell $and $and$ls180.v:6237$1777 + attribute \src "ls180.v:6410.41-6410.145" + cell $and $and$ls180.v:6410$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1775_Y - connect \B $eq$ls180.v:6237$1776_Y - connect \Y $and$ls180.v:6237$1777_Y + connect \A $and$ls180.v:6410$1904_Y + connect \B $eq$ls180.v:6410$1905_Y + connect \Y $and$ls180.v:6410$1906_Y end - attribute \src "ls180.v:6238.42-6238.98" - cell $and $and$ls180.v:6238$1779 + attribute \src "ls180.v:6411.42-6411.98" + cell $and $and$ls180.v:6411$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6238$1778_Y - connect \Y $and$ls180.v:6238$1779_Y + connect \B $not$ls180.v:6411$1907_Y + connect \Y $and$ls180.v:6411$1908_Y end - attribute \src "ls180.v:6238.41-6238.148" - cell $and $and$ls180.v:6238$1781 + attribute \src "ls180.v:6411.41-6411.148" + cell $and $and$ls180.v:6411$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1779_Y - connect \B $eq$ls180.v:6238$1780_Y - connect \Y $and$ls180.v:6238$1781_Y + connect \A $and$ls180.v:6411$1908_Y + connect \B $eq$ls180.v:6411$1909_Y + connect \Y $and$ls180.v:6411$1910_Y end - attribute \src "ls180.v:6240.42-6240.95" - cell $and $and$ls180.v:6240$1782 + attribute \src "ls180.v:6413.42-6413.95" + cell $and $and$ls180.v:6413$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244110,43 +261569,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6240$1782_Y + connect \Y $and$ls180.v:6413$1911_Y end - attribute \src "ls180.v:6240.41-6240.145" - cell $and $and$ls180.v:6240$1784 + attribute \src "ls180.v:6413.41-6413.145" + cell $and $and$ls180.v:6413$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6240$1782_Y - connect \B $eq$ls180.v:6240$1783_Y - connect \Y $and$ls180.v:6240$1784_Y + connect \A $and$ls180.v:6413$1911_Y + connect \B $eq$ls180.v:6413$1912_Y + connect \Y $and$ls180.v:6413$1913_Y end - attribute \src "ls180.v:6241.42-6241.98" - cell $and $and$ls180.v:6241$1786 + attribute \src "ls180.v:6414.42-6414.98" + cell $and $and$ls180.v:6414$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6241$1785_Y - connect \Y $and$ls180.v:6241$1786_Y + connect \B $not$ls180.v:6414$1914_Y + connect \Y $and$ls180.v:6414$1915_Y end - attribute \src "ls180.v:6241.41-6241.148" - cell $and $and$ls180.v:6241$1788 + attribute \src "ls180.v:6414.41-6414.148" + cell $and $and$ls180.v:6414$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6241$1786_Y - connect \B $eq$ls180.v:6241$1787_Y - connect \Y $and$ls180.v:6241$1788_Y + connect \A $and$ls180.v:6414$1915_Y + connect \B $eq$ls180.v:6414$1916_Y + connect \Y $and$ls180.v:6414$1917_Y end - attribute \src "ls180.v:6243.42-6243.95" - cell $and $and$ls180.v:6243$1789 + attribute \src "ls180.v:6416.42-6416.95" + cell $and $and$ls180.v:6416$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244154,43 +261613,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6243$1789_Y + connect \Y $and$ls180.v:6416$1918_Y end - attribute \src "ls180.v:6243.41-6243.145" - cell $and $and$ls180.v:6243$1791 + attribute \src "ls180.v:6416.41-6416.145" + cell $and $and$ls180.v:6416$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6243$1789_Y - connect \B $eq$ls180.v:6243$1790_Y - connect \Y $and$ls180.v:6243$1791_Y + connect \A $and$ls180.v:6416$1918_Y + connect \B $eq$ls180.v:6416$1919_Y + connect \Y $and$ls180.v:6416$1920_Y end - attribute \src "ls180.v:6244.42-6244.98" - cell $and $and$ls180.v:6244$1793 + attribute \src "ls180.v:6417.42-6417.98" + cell $and $and$ls180.v:6417$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6244$1792_Y - connect \Y $and$ls180.v:6244$1793_Y + connect \B $not$ls180.v:6417$1921_Y + connect \Y $and$ls180.v:6417$1922_Y end - attribute \src "ls180.v:6244.41-6244.148" - cell $and $and$ls180.v:6244$1795 + attribute \src "ls180.v:6417.41-6417.148" + cell $and $and$ls180.v:6417$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6244$1793_Y - connect \B $eq$ls180.v:6244$1794_Y - connect \Y $and$ls180.v:6244$1795_Y + connect \A $and$ls180.v:6417$1922_Y + connect \B $eq$ls180.v:6417$1923_Y + connect \Y $and$ls180.v:6417$1924_Y end - attribute \src "ls180.v:6246.44-6246.97" - cell $and $and$ls180.v:6246$1796 + attribute \src "ls180.v:6419.44-6419.97" + cell $and $and$ls180.v:6419$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244198,43 +261657,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6246$1796_Y + connect \Y $and$ls180.v:6419$1925_Y end - attribute \src "ls180.v:6246.43-6246.147" - cell $and $and$ls180.v:6246$1798 + attribute \src "ls180.v:6419.43-6419.147" + cell $and $and$ls180.v:6419$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6246$1796_Y - connect \B $eq$ls180.v:6246$1797_Y - connect \Y $and$ls180.v:6246$1798_Y + connect \A $and$ls180.v:6419$1925_Y + connect \B $eq$ls180.v:6419$1926_Y + connect \Y $and$ls180.v:6419$1927_Y end - attribute \src "ls180.v:6247.44-6247.100" - cell $and $and$ls180.v:6247$1800 + attribute \src "ls180.v:6420.44-6420.100" + cell $and $and$ls180.v:6420$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6247$1799_Y - connect \Y $and$ls180.v:6247$1800_Y + connect \B $not$ls180.v:6420$1928_Y + connect \Y $and$ls180.v:6420$1929_Y end - attribute \src "ls180.v:6247.43-6247.150" - cell $and $and$ls180.v:6247$1802 + attribute \src "ls180.v:6420.43-6420.150" + cell $and $and$ls180.v:6420$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6247$1800_Y - connect \B $eq$ls180.v:6247$1801_Y - connect \Y $and$ls180.v:6247$1802_Y + connect \A $and$ls180.v:6420$1929_Y + connect \B $eq$ls180.v:6420$1930_Y + connect \Y $and$ls180.v:6420$1931_Y end - attribute \src "ls180.v:6249.44-6249.97" - cell $and $and$ls180.v:6249$1803 + attribute \src "ls180.v:6422.44-6422.97" + cell $and $and$ls180.v:6422$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244242,43 +261701,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6249$1803_Y + connect \Y $and$ls180.v:6422$1932_Y end - attribute \src "ls180.v:6249.43-6249.147" - cell $and $and$ls180.v:6249$1805 + attribute \src "ls180.v:6422.43-6422.147" + cell $and $and$ls180.v:6422$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6249$1803_Y - connect \B $eq$ls180.v:6249$1804_Y - connect \Y $and$ls180.v:6249$1805_Y + connect \A $and$ls180.v:6422$1932_Y + connect \B $eq$ls180.v:6422$1933_Y + connect \Y $and$ls180.v:6422$1934_Y end - attribute \src "ls180.v:6250.44-6250.100" - cell $and $and$ls180.v:6250$1807 + attribute \src "ls180.v:6423.44-6423.100" + cell $and $and$ls180.v:6423$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6250$1806_Y - connect \Y $and$ls180.v:6250$1807_Y + connect \B $not$ls180.v:6423$1935_Y + connect \Y $and$ls180.v:6423$1936_Y end - attribute \src "ls180.v:6250.43-6250.150" - cell $and $and$ls180.v:6250$1809 + attribute \src "ls180.v:6423.43-6423.150" + cell $and $and$ls180.v:6423$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6250$1807_Y - connect \B $eq$ls180.v:6250$1808_Y - connect \Y $and$ls180.v:6250$1809_Y + connect \A $and$ls180.v:6423$1936_Y + connect \B $eq$ls180.v:6423$1937_Y + connect \Y $and$ls180.v:6423$1938_Y end - attribute \src "ls180.v:6252.44-6252.97" - cell $and $and$ls180.v:6252$1810 + attribute \src "ls180.v:6425.44-6425.97" + cell $and $and$ls180.v:6425$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244286,43 +261745,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6252$1810_Y + connect \Y $and$ls180.v:6425$1939_Y end - attribute \src "ls180.v:6252.43-6252.148" - cell $and $and$ls180.v:6252$1812 + attribute \src "ls180.v:6425.43-6425.148" + cell $and $and$ls180.v:6425$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6252$1810_Y - connect \B $eq$ls180.v:6252$1811_Y - connect \Y $and$ls180.v:6252$1812_Y + connect \A $and$ls180.v:6425$1939_Y + connect \B $eq$ls180.v:6425$1940_Y + connect \Y $and$ls180.v:6425$1941_Y end - attribute \src "ls180.v:6253.44-6253.100" - cell $and $and$ls180.v:6253$1814 + attribute \src "ls180.v:6426.44-6426.100" + cell $and $and$ls180.v:6426$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6253$1813_Y - connect \Y $and$ls180.v:6253$1814_Y + connect \B $not$ls180.v:6426$1942_Y + connect \Y $and$ls180.v:6426$1943_Y end - attribute \src "ls180.v:6253.43-6253.151" - cell $and $and$ls180.v:6253$1816 + attribute \src "ls180.v:6426.43-6426.151" + cell $and $and$ls180.v:6426$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6253$1814_Y - connect \B $eq$ls180.v:6253$1815_Y - connect \Y $and$ls180.v:6253$1816_Y + connect \A $and$ls180.v:6426$1943_Y + connect \B $eq$ls180.v:6426$1944_Y + connect \Y $and$ls180.v:6426$1945_Y end - attribute \src "ls180.v:6255.44-6255.97" - cell $and $and$ls180.v:6255$1817 + attribute \src "ls180.v:6428.44-6428.97" + cell $and $and$ls180.v:6428$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244330,43 +261789,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6255$1817_Y + connect \Y $and$ls180.v:6428$1946_Y end - attribute \src "ls180.v:6255.43-6255.148" - cell $and $and$ls180.v:6255$1819 + attribute \src "ls180.v:6428.43-6428.148" + cell $and $and$ls180.v:6428$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6255$1817_Y - connect \B $eq$ls180.v:6255$1818_Y - connect \Y $and$ls180.v:6255$1819_Y + connect \A $and$ls180.v:6428$1946_Y + connect \B $eq$ls180.v:6428$1947_Y + connect \Y $and$ls180.v:6428$1948_Y end - attribute \src "ls180.v:6256.44-6256.100" - cell $and $and$ls180.v:6256$1821 + attribute \src "ls180.v:6429.44-6429.100" + cell $and $and$ls180.v:6429$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6256$1820_Y - connect \Y $and$ls180.v:6256$1821_Y + connect \B $not$ls180.v:6429$1949_Y + connect \Y $and$ls180.v:6429$1950_Y end - attribute \src "ls180.v:6256.43-6256.151" - cell $and $and$ls180.v:6256$1823 + attribute \src "ls180.v:6429.43-6429.151" + cell $and $and$ls180.v:6429$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6256$1821_Y - connect \B $eq$ls180.v:6256$1822_Y - connect \Y $and$ls180.v:6256$1823_Y + connect \A $and$ls180.v:6429$1950_Y + connect \B $eq$ls180.v:6429$1951_Y + connect \Y $and$ls180.v:6429$1952_Y end - attribute \src "ls180.v:6258.44-6258.97" - cell $and $and$ls180.v:6258$1824 + attribute \src "ls180.v:6431.44-6431.97" + cell $and $and$ls180.v:6431$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244374,43 +261833,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6258$1824_Y + connect \Y $and$ls180.v:6431$1953_Y end - attribute \src "ls180.v:6258.43-6258.148" - cell $and $and$ls180.v:6258$1826 + attribute \src "ls180.v:6431.43-6431.148" + cell $and $and$ls180.v:6431$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6258$1824_Y - connect \B $eq$ls180.v:6258$1825_Y - connect \Y $and$ls180.v:6258$1826_Y + connect \A $and$ls180.v:6431$1953_Y + connect \B $eq$ls180.v:6431$1954_Y + connect \Y $and$ls180.v:6431$1955_Y end - attribute \src "ls180.v:6259.44-6259.100" - cell $and $and$ls180.v:6259$1828 + attribute \src "ls180.v:6432.44-6432.100" + cell $and $and$ls180.v:6432$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6259$1827_Y - connect \Y $and$ls180.v:6259$1828_Y + connect \B $not$ls180.v:6432$1956_Y + connect \Y $and$ls180.v:6432$1957_Y end - attribute \src "ls180.v:6259.43-6259.151" - cell $and $and$ls180.v:6259$1830 + attribute \src "ls180.v:6432.43-6432.151" + cell $and $and$ls180.v:6432$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6259$1828_Y - connect \B $eq$ls180.v:6259$1829_Y - connect \Y $and$ls180.v:6259$1830_Y + connect \A $and$ls180.v:6432$1957_Y + connect \B $eq$ls180.v:6432$1958_Y + connect \Y $and$ls180.v:6432$1959_Y end - attribute \src "ls180.v:6261.41-6261.94" - cell $and $and$ls180.v:6261$1831 + attribute \src "ls180.v:6434.41-6434.94" + cell $and $and$ls180.v:6434$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244418,43 +261877,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6261$1831_Y + connect \Y $and$ls180.v:6434$1960_Y end - attribute \src "ls180.v:6261.40-6261.145" - cell $and $and$ls180.v:6261$1833 + attribute \src "ls180.v:6434.40-6434.145" + cell $and $and$ls180.v:6434$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1831_Y - connect \B $eq$ls180.v:6261$1832_Y - connect \Y $and$ls180.v:6261$1833_Y + connect \A $and$ls180.v:6434$1960_Y + connect \B $eq$ls180.v:6434$1961_Y + connect \Y $and$ls180.v:6434$1962_Y end - attribute \src "ls180.v:6262.41-6262.97" - cell $and $and$ls180.v:6262$1835 + attribute \src "ls180.v:6435.41-6435.97" + cell $and $and$ls180.v:6435$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6262$1834_Y - connect \Y $and$ls180.v:6262$1835_Y + connect \B $not$ls180.v:6435$1963_Y + connect \Y $and$ls180.v:6435$1964_Y end - attribute \src "ls180.v:6262.40-6262.148" - cell $and $and$ls180.v:6262$1837 + attribute \src "ls180.v:6435.40-6435.148" + cell $and $and$ls180.v:6435$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6262$1835_Y - connect \B $eq$ls180.v:6262$1836_Y - connect \Y $and$ls180.v:6262$1837_Y + connect \A $and$ls180.v:6435$1964_Y + connect \B $eq$ls180.v:6435$1965_Y + connect \Y $and$ls180.v:6435$1966_Y end - attribute \src "ls180.v:6264.42-6264.95" - cell $and $and$ls180.v:6264$1838 + attribute \src "ls180.v:6437.42-6437.95" + cell $and $and$ls180.v:6437$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244462,43 +261921,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6264$1838_Y + connect \Y $and$ls180.v:6437$1967_Y end - attribute \src "ls180.v:6264.41-6264.146" - cell $and $and$ls180.v:6264$1840 + attribute \src "ls180.v:6437.41-6437.146" + cell $and $and$ls180.v:6437$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1838_Y - connect \B $eq$ls180.v:6264$1839_Y - connect \Y $and$ls180.v:6264$1840_Y + connect \A $and$ls180.v:6437$1967_Y + connect \B $eq$ls180.v:6437$1968_Y + connect \Y $and$ls180.v:6437$1969_Y end - attribute \src "ls180.v:6265.42-6265.98" - cell $and $and$ls180.v:6265$1842 + attribute \src "ls180.v:6438.42-6438.98" + cell $and $and$ls180.v:6438$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6265$1841_Y - connect \Y $and$ls180.v:6265$1842_Y + connect \B $not$ls180.v:6438$1970_Y + connect \Y $and$ls180.v:6438$1971_Y end - attribute \src "ls180.v:6265.41-6265.149" - cell $and $and$ls180.v:6265$1844 + attribute \src "ls180.v:6438.41-6438.149" + cell $and $and$ls180.v:6438$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6265$1842_Y - connect \B $eq$ls180.v:6265$1843_Y - connect \Y $and$ls180.v:6265$1844_Y + connect \A $and$ls180.v:6438$1971_Y + connect \B $eq$ls180.v:6438$1972_Y + connect \Y $and$ls180.v:6438$1973_Y end - attribute \src "ls180.v:6267.44-6267.97" - cell $and $and$ls180.v:6267$1845 + attribute \src "ls180.v:6440.44-6440.97" + cell $and $and$ls180.v:6440$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244506,43 +261965,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6267$1845_Y + connect \Y $and$ls180.v:6440$1974_Y end - attribute \src "ls180.v:6267.43-6267.148" - cell $and $and$ls180.v:6267$1847 + attribute \src "ls180.v:6440.43-6440.148" + cell $and $and$ls180.v:6440$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6267$1845_Y - connect \B $eq$ls180.v:6267$1846_Y - connect \Y $and$ls180.v:6267$1847_Y + connect \A $and$ls180.v:6440$1974_Y + connect \B $eq$ls180.v:6440$1975_Y + connect \Y $and$ls180.v:6440$1976_Y end - attribute \src "ls180.v:6268.44-6268.100" - cell $and $and$ls180.v:6268$1849 + attribute \src "ls180.v:6441.44-6441.100" + cell $and $and$ls180.v:6441$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6268$1848_Y - connect \Y $and$ls180.v:6268$1849_Y + connect \B $not$ls180.v:6441$1977_Y + connect \Y $and$ls180.v:6441$1978_Y end - attribute \src "ls180.v:6268.43-6268.151" - cell $and $and$ls180.v:6268$1851 + attribute \src "ls180.v:6441.43-6441.151" + cell $and $and$ls180.v:6441$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6268$1849_Y - connect \B $eq$ls180.v:6268$1850_Y - connect \Y $and$ls180.v:6268$1851_Y + connect \A $and$ls180.v:6441$1978_Y + connect \B $eq$ls180.v:6441$1979_Y + connect \Y $and$ls180.v:6441$1980_Y end - attribute \src "ls180.v:6270.44-6270.97" - cell $and $and$ls180.v:6270$1852 + attribute \src "ls180.v:6443.44-6443.97" + cell $and $and$ls180.v:6443$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244550,43 +262009,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6270$1852_Y + connect \Y $and$ls180.v:6443$1981_Y end - attribute \src "ls180.v:6270.43-6270.148" - cell $and $and$ls180.v:6270$1854 + attribute \src "ls180.v:6443.43-6443.148" + cell $and $and$ls180.v:6443$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6270$1852_Y - connect \B $eq$ls180.v:6270$1853_Y - connect \Y $and$ls180.v:6270$1854_Y + connect \A $and$ls180.v:6443$1981_Y + connect \B $eq$ls180.v:6443$1982_Y + connect \Y $and$ls180.v:6443$1983_Y end - attribute \src "ls180.v:6271.44-6271.100" - cell $and $and$ls180.v:6271$1856 + attribute \src "ls180.v:6444.44-6444.100" + cell $and $and$ls180.v:6444$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6271$1855_Y - connect \Y $and$ls180.v:6271$1856_Y + connect \B $not$ls180.v:6444$1984_Y + connect \Y $and$ls180.v:6444$1985_Y end - attribute \src "ls180.v:6271.43-6271.151" - cell $and $and$ls180.v:6271$1858 + attribute \src "ls180.v:6444.43-6444.151" + cell $and $and$ls180.v:6444$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6271$1856_Y - connect \B $eq$ls180.v:6271$1857_Y - connect \Y $and$ls180.v:6271$1858_Y + connect \A $and$ls180.v:6444$1985_Y + connect \B $eq$ls180.v:6444$1986_Y + connect \Y $and$ls180.v:6444$1987_Y end - attribute \src "ls180.v:6273.44-6273.97" - cell $and $and$ls180.v:6273$1859 + attribute \src "ls180.v:6446.44-6446.97" + cell $and $and$ls180.v:6446$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244594,43 +262053,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6273$1859_Y + connect \Y $and$ls180.v:6446$1988_Y end - attribute \src "ls180.v:6273.43-6273.148" - cell $and $and$ls180.v:6273$1861 + attribute \src "ls180.v:6446.43-6446.148" + cell $and $and$ls180.v:6446$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6273$1859_Y - connect \B $eq$ls180.v:6273$1860_Y - connect \Y $and$ls180.v:6273$1861_Y + connect \A $and$ls180.v:6446$1988_Y + connect \B $eq$ls180.v:6446$1989_Y + connect \Y $and$ls180.v:6446$1990_Y end - attribute \src "ls180.v:6274.44-6274.100" - cell $and $and$ls180.v:6274$1863 + attribute \src "ls180.v:6447.44-6447.100" + cell $and $and$ls180.v:6447$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6274$1862_Y - connect \Y $and$ls180.v:6274$1863_Y + connect \B $not$ls180.v:6447$1991_Y + connect \Y $and$ls180.v:6447$1992_Y end - attribute \src "ls180.v:6274.43-6274.151" - cell $and $and$ls180.v:6274$1865 + attribute \src "ls180.v:6447.43-6447.151" + cell $and $and$ls180.v:6447$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6274$1863_Y - connect \B $eq$ls180.v:6274$1864_Y - connect \Y $and$ls180.v:6274$1865_Y + connect \A $and$ls180.v:6447$1992_Y + connect \B $eq$ls180.v:6447$1993_Y + connect \Y $and$ls180.v:6447$1994_Y end - attribute \src "ls180.v:6276.44-6276.97" - cell $and $and$ls180.v:6276$1866 + attribute \src "ls180.v:6449.44-6449.97" + cell $and $and$ls180.v:6449$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244638,43 +262097,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6276$1866_Y + connect \Y $and$ls180.v:6449$1995_Y end - attribute \src "ls180.v:6276.43-6276.148" - cell $and $and$ls180.v:6276$1868 + attribute \src "ls180.v:6449.43-6449.148" + cell $and $and$ls180.v:6449$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6276$1866_Y - connect \B $eq$ls180.v:6276$1867_Y - connect \Y $and$ls180.v:6276$1868_Y + connect \A $and$ls180.v:6449$1995_Y + connect \B $eq$ls180.v:6449$1996_Y + connect \Y $and$ls180.v:6449$1997_Y end - attribute \src "ls180.v:6277.44-6277.100" - cell $and $and$ls180.v:6277$1870 + attribute \src "ls180.v:6450.44-6450.100" + cell $and $and$ls180.v:6450$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6277$1869_Y - connect \Y $and$ls180.v:6277$1870_Y + connect \B $not$ls180.v:6450$1998_Y + connect \Y $and$ls180.v:6450$1999_Y end - attribute \src "ls180.v:6277.43-6277.151" - cell $and $and$ls180.v:6277$1872 + attribute \src "ls180.v:6450.43-6450.151" + cell $and $and$ls180.v:6450$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6277$1870_Y - connect \B $eq$ls180.v:6277$1871_Y - connect \Y $and$ls180.v:6277$1872_Y + connect \A $and$ls180.v:6450$1999_Y + connect \B $eq$ls180.v:6450$2000_Y + connect \Y $and$ls180.v:6450$2001_Y end - attribute \src "ls180.v:6301.44-6301.97" - cell $and $and$ls180.v:6301$1874 + attribute \src "ls180.v:6474.44-6474.97" + cell $and $and$ls180.v:6474$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244682,43 +262141,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6301$1874_Y + connect \Y $and$ls180.v:6474$2003_Y end - attribute \src "ls180.v:6301.43-6301.147" - cell $and $and$ls180.v:6301$1876 + attribute \src "ls180.v:6474.43-6474.147" + cell $and $and$ls180.v:6474$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6301$1874_Y - connect \B $eq$ls180.v:6301$1875_Y - connect \Y $and$ls180.v:6301$1876_Y + connect \A $and$ls180.v:6474$2003_Y + connect \B $eq$ls180.v:6474$2004_Y + connect \Y $and$ls180.v:6474$2005_Y end - attribute \src "ls180.v:6302.44-6302.100" - cell $and $and$ls180.v:6302$1878 + attribute \src "ls180.v:6475.44-6475.100" + cell $and $and$ls180.v:6475$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6302$1877_Y - connect \Y $and$ls180.v:6302$1878_Y + connect \B $not$ls180.v:6475$2006_Y + connect \Y $and$ls180.v:6475$2007_Y end - attribute \src "ls180.v:6302.43-6302.150" - cell $and $and$ls180.v:6302$1880 + attribute \src "ls180.v:6475.43-6475.150" + cell $and $and$ls180.v:6475$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$1878_Y - connect \B $eq$ls180.v:6302$1879_Y - connect \Y $and$ls180.v:6302$1880_Y + connect \A $and$ls180.v:6475$2007_Y + connect \B $eq$ls180.v:6475$2008_Y + connect \Y $and$ls180.v:6475$2009_Y end - attribute \src "ls180.v:6304.49-6304.102" - cell $and $and$ls180.v:6304$1881 + attribute \src "ls180.v:6477.49-6477.102" + cell $and $and$ls180.v:6477$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244726,43 +262185,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6304$1881_Y + connect \Y $and$ls180.v:6477$2010_Y end - attribute \src "ls180.v:6304.48-6304.152" - cell $and $and$ls180.v:6304$1883 + attribute \src "ls180.v:6477.48-6477.152" + cell $and $and$ls180.v:6477$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6304$1881_Y - connect \B $eq$ls180.v:6304$1882_Y - connect \Y $and$ls180.v:6304$1883_Y + connect \A $and$ls180.v:6477$2010_Y + connect \B $eq$ls180.v:6477$2011_Y + connect \Y $and$ls180.v:6477$2012_Y end - attribute \src "ls180.v:6305.49-6305.105" - cell $and $and$ls180.v:6305$1885 + attribute \src "ls180.v:6478.49-6478.105" + cell $and $and$ls180.v:6478$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6305$1884_Y - connect \Y $and$ls180.v:6305$1885_Y + connect \B $not$ls180.v:6478$2013_Y + connect \Y $and$ls180.v:6478$2014_Y end - attribute \src "ls180.v:6305.48-6305.155" - cell $and $and$ls180.v:6305$1887 + attribute \src "ls180.v:6478.48-6478.155" + cell $and $and$ls180.v:6478$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$1885_Y - connect \B $eq$ls180.v:6305$1886_Y - connect \Y $and$ls180.v:6305$1887_Y + connect \A $and$ls180.v:6478$2014_Y + connect \B $eq$ls180.v:6478$2015_Y + connect \Y $and$ls180.v:6478$2016_Y end - attribute \src "ls180.v:6307.49-6307.102" - cell $and $and$ls180.v:6307$1888 + attribute \src "ls180.v:6480.49-6480.102" + cell $and $and$ls180.v:6480$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244770,43 +262229,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6307$1888_Y + connect \Y $and$ls180.v:6480$2017_Y end - attribute \src "ls180.v:6307.48-6307.152" - cell $and $and$ls180.v:6307$1890 + attribute \src "ls180.v:6480.48-6480.152" + cell $and $and$ls180.v:6480$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6307$1888_Y - connect \B $eq$ls180.v:6307$1889_Y - connect \Y $and$ls180.v:6307$1890_Y + connect \A $and$ls180.v:6480$2017_Y + connect \B $eq$ls180.v:6480$2018_Y + connect \Y $and$ls180.v:6480$2019_Y end - attribute \src "ls180.v:6308.49-6308.105" - cell $and $and$ls180.v:6308$1892 + attribute \src "ls180.v:6481.49-6481.105" + cell $and $and$ls180.v:6481$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6308$1891_Y - connect \Y $and$ls180.v:6308$1892_Y + connect \B $not$ls180.v:6481$2020_Y + connect \Y $and$ls180.v:6481$2021_Y end - attribute \src "ls180.v:6308.48-6308.155" - cell $and $and$ls180.v:6308$1894 + attribute \src "ls180.v:6481.48-6481.155" + cell $and $and$ls180.v:6481$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$1892_Y - connect \B $eq$ls180.v:6308$1893_Y - connect \Y $and$ls180.v:6308$1894_Y + connect \A $and$ls180.v:6481$2021_Y + connect \B $eq$ls180.v:6481$2022_Y + connect \Y $and$ls180.v:6481$2023_Y end - attribute \src "ls180.v:6310.42-6310.95" - cell $and $and$ls180.v:6310$1895 + attribute \src "ls180.v:6483.42-6483.95" + cell $and $and$ls180.v:6483$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244814,43 +262273,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6310$1895_Y + connect \Y $and$ls180.v:6483$2024_Y end - attribute \src "ls180.v:6310.41-6310.145" - cell $and $and$ls180.v:6310$1897 + attribute \src "ls180.v:6483.41-6483.145" + cell $and $and$ls180.v:6483$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6310$1895_Y - connect \B $eq$ls180.v:6310$1896_Y - connect \Y $and$ls180.v:6310$1897_Y + connect \A $and$ls180.v:6483$2024_Y + connect \B $eq$ls180.v:6483$2025_Y + connect \Y $and$ls180.v:6483$2026_Y end - attribute \src "ls180.v:6311.42-6311.98" - cell $and $and$ls180.v:6311$1899 + attribute \src "ls180.v:6484.42-6484.98" + cell $and $and$ls180.v:6484$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6311$1898_Y - connect \Y $and$ls180.v:6311$1899_Y + connect \B $not$ls180.v:6484$2027_Y + connect \Y $and$ls180.v:6484$2028_Y end - attribute \src "ls180.v:6311.41-6311.148" - cell $and $and$ls180.v:6311$1901 + attribute \src "ls180.v:6484.41-6484.148" + cell $and $and$ls180.v:6484$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$1899_Y - connect \B $eq$ls180.v:6311$1900_Y - connect \Y $and$ls180.v:6311$1901_Y + connect \A $and$ls180.v:6484$2028_Y + connect \B $eq$ls180.v:6484$2029_Y + connect \Y $and$ls180.v:6484$2030_Y end - attribute \src "ls180.v:6318.46-6318.99" - cell $and $and$ls180.v:6318$1903 + attribute \src "ls180.v:6491.46-6491.99" + cell $and $and$ls180.v:6491$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244858,43 +262317,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6318$1903_Y + connect \Y $and$ls180.v:6491$2032_Y end - attribute \src "ls180.v:6318.45-6318.149" - cell $and $and$ls180.v:6318$1905 + attribute \src "ls180.v:6491.45-6491.149" + cell $and $and$ls180.v:6491$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$1903_Y - connect \B $eq$ls180.v:6318$1904_Y - connect \Y $and$ls180.v:6318$1905_Y + connect \A $and$ls180.v:6491$2032_Y + connect \B $eq$ls180.v:6491$2033_Y + connect \Y $and$ls180.v:6491$2034_Y end - attribute \src "ls180.v:6319.46-6319.102" - cell $and $and$ls180.v:6319$1907 + attribute \src "ls180.v:6492.46-6492.102" + cell $and $and$ls180.v:6492$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6319$1906_Y - connect \Y $and$ls180.v:6319$1907_Y + connect \B $not$ls180.v:6492$2035_Y + connect \Y $and$ls180.v:6492$2036_Y end - attribute \src "ls180.v:6319.45-6319.152" - cell $and $and$ls180.v:6319$1909 + attribute \src "ls180.v:6492.45-6492.152" + cell $and $and$ls180.v:6492$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6319$1907_Y - connect \B $eq$ls180.v:6319$1908_Y - connect \Y $and$ls180.v:6319$1909_Y + connect \A $and$ls180.v:6492$2036_Y + connect \B $eq$ls180.v:6492$2037_Y + connect \Y $and$ls180.v:6492$2038_Y end - attribute \src "ls180.v:6321.50-6321.103" - cell $and $and$ls180.v:6321$1910 + attribute \src "ls180.v:6494.50-6494.103" + cell $and $and$ls180.v:6494$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244902,43 +262361,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6321$1910_Y + connect \Y $and$ls180.v:6494$2039_Y end - attribute \src "ls180.v:6321.49-6321.153" - cell $and $and$ls180.v:6321$1912 + attribute \src "ls180.v:6494.49-6494.153" + cell $and $and$ls180.v:6494$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$1910_Y - connect \B $eq$ls180.v:6321$1911_Y - connect \Y $and$ls180.v:6321$1912_Y + connect \A $and$ls180.v:6494$2039_Y + connect \B $eq$ls180.v:6494$2040_Y + connect \Y $and$ls180.v:6494$2041_Y end - attribute \src "ls180.v:6322.50-6322.106" - cell $and $and$ls180.v:6322$1914 + attribute \src "ls180.v:6495.50-6495.106" + cell $and $and$ls180.v:6495$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6322$1913_Y - connect \Y $and$ls180.v:6322$1914_Y + connect \B $not$ls180.v:6495$2042_Y + connect \Y $and$ls180.v:6495$2043_Y end - attribute \src "ls180.v:6322.49-6322.156" - cell $and $and$ls180.v:6322$1916 + attribute \src "ls180.v:6495.49-6495.156" + cell $and $and$ls180.v:6495$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6322$1914_Y - connect \B $eq$ls180.v:6322$1915_Y - connect \Y $and$ls180.v:6322$1916_Y + connect \A $and$ls180.v:6495$2043_Y + connect \B $eq$ls180.v:6495$2044_Y + connect \Y $and$ls180.v:6495$2045_Y end - attribute \src "ls180.v:6324.40-6324.93" - cell $and $and$ls180.v:6324$1917 + attribute \src "ls180.v:6497.40-6497.93" + cell $and $and$ls180.v:6497$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244946,43 +262405,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6324$1917_Y + connect \Y $and$ls180.v:6497$2046_Y end - attribute \src "ls180.v:6324.39-6324.143" - cell $and $and$ls180.v:6324$1919 + attribute \src "ls180.v:6497.39-6497.143" + cell $and $and$ls180.v:6497$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$1917_Y - connect \B $eq$ls180.v:6324$1918_Y - connect \Y $and$ls180.v:6324$1919_Y + connect \A $and$ls180.v:6497$2046_Y + connect \B $eq$ls180.v:6497$2047_Y + connect \Y $and$ls180.v:6497$2048_Y end - attribute \src "ls180.v:6325.40-6325.96" - cell $and $and$ls180.v:6325$1921 + attribute \src "ls180.v:6498.40-6498.96" + cell $and $and$ls180.v:6498$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6325$1920_Y - connect \Y $and$ls180.v:6325$1921_Y + connect \B $not$ls180.v:6498$2049_Y + connect \Y $and$ls180.v:6498$2050_Y end - attribute \src "ls180.v:6325.39-6325.146" - cell $and $and$ls180.v:6325$1923 + attribute \src "ls180.v:6498.39-6498.146" + cell $and $and$ls180.v:6498$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6325$1921_Y - connect \B $eq$ls180.v:6325$1922_Y - connect \Y $and$ls180.v:6325$1923_Y + connect \A $and$ls180.v:6498$2050_Y + connect \B $eq$ls180.v:6498$2051_Y + connect \Y $and$ls180.v:6498$2052_Y end - attribute \src "ls180.v:6327.50-6327.103" - cell $and $and$ls180.v:6327$1924 + attribute \src "ls180.v:6500.50-6500.103" + cell $and $and$ls180.v:6500$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244990,43 +262449,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6327$1924_Y + connect \Y $and$ls180.v:6500$2053_Y end - attribute \src "ls180.v:6327.49-6327.153" - cell $and $and$ls180.v:6327$1926 + attribute \src "ls180.v:6500.49-6500.153" + cell $and $and$ls180.v:6500$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$1924_Y - connect \B $eq$ls180.v:6327$1925_Y - connect \Y $and$ls180.v:6327$1926_Y + connect \A $and$ls180.v:6500$2053_Y + connect \B $eq$ls180.v:6500$2054_Y + connect \Y $and$ls180.v:6500$2055_Y end - attribute \src "ls180.v:6328.50-6328.106" - cell $and $and$ls180.v:6328$1928 + attribute \src "ls180.v:6501.50-6501.106" + cell $and $and$ls180.v:6501$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6328$1927_Y - connect \Y $and$ls180.v:6328$1928_Y + connect \B $not$ls180.v:6501$2056_Y + connect \Y $and$ls180.v:6501$2057_Y end - attribute \src "ls180.v:6328.49-6328.156" - cell $and $and$ls180.v:6328$1930 + attribute \src "ls180.v:6501.49-6501.156" + cell $and $and$ls180.v:6501$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6328$1928_Y - connect \B $eq$ls180.v:6328$1929_Y - connect \Y $and$ls180.v:6328$1930_Y + connect \A $and$ls180.v:6501$2057_Y + connect \B $eq$ls180.v:6501$2058_Y + connect \Y $and$ls180.v:6501$2059_Y end - attribute \src "ls180.v:6330.50-6330.103" - cell $and $and$ls180.v:6330$1931 + attribute \src "ls180.v:6503.50-6503.103" + cell $and $and$ls180.v:6503$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245034,43 +262493,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6330$1931_Y + connect \Y $and$ls180.v:6503$2060_Y end - attribute \src "ls180.v:6330.49-6330.153" - cell $and $and$ls180.v:6330$1933 + attribute \src "ls180.v:6503.49-6503.153" + cell $and $and$ls180.v:6503$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6330$1931_Y - connect \B $eq$ls180.v:6330$1932_Y - connect \Y $and$ls180.v:6330$1933_Y + connect \A $and$ls180.v:6503$2060_Y + connect \B $eq$ls180.v:6503$2061_Y + connect \Y $and$ls180.v:6503$2062_Y end - attribute \src "ls180.v:6331.50-6331.106" - cell $and $and$ls180.v:6331$1935 + attribute \src "ls180.v:6504.50-6504.106" + cell $and $and$ls180.v:6504$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6331$1934_Y - connect \Y $and$ls180.v:6331$1935_Y + connect \B $not$ls180.v:6504$2063_Y + connect \Y $and$ls180.v:6504$2064_Y end - attribute \src "ls180.v:6331.49-6331.156" - cell $and $and$ls180.v:6331$1937 + attribute \src "ls180.v:6504.49-6504.156" + cell $and $and$ls180.v:6504$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6331$1935_Y - connect \B $eq$ls180.v:6331$1936_Y - connect \Y $and$ls180.v:6331$1937_Y + connect \A $and$ls180.v:6504$2064_Y + connect \B $eq$ls180.v:6504$2065_Y + connect \Y $and$ls180.v:6504$2066_Y end - attribute \src "ls180.v:6333.51-6333.104" - cell $and $and$ls180.v:6333$1938 + attribute \src "ls180.v:6506.51-6506.104" + cell $and $and$ls180.v:6506$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245078,43 +262537,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6333$1938_Y + connect \Y $and$ls180.v:6506$2067_Y end - attribute \src "ls180.v:6333.50-6333.154" - cell $and $and$ls180.v:6333$1940 + attribute \src "ls180.v:6506.50-6506.154" + cell $and $and$ls180.v:6506$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$1938_Y - connect \B $eq$ls180.v:6333$1939_Y - connect \Y $and$ls180.v:6333$1940_Y + connect \A $and$ls180.v:6506$2067_Y + connect \B $eq$ls180.v:6506$2068_Y + connect \Y $and$ls180.v:6506$2069_Y end - attribute \src "ls180.v:6334.51-6334.107" - cell $and $and$ls180.v:6334$1942 + attribute \src "ls180.v:6507.51-6507.107" + cell $and $and$ls180.v:6507$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6334$1941_Y - connect \Y $and$ls180.v:6334$1942_Y + connect \B $not$ls180.v:6507$2070_Y + connect \Y $and$ls180.v:6507$2071_Y end - attribute \src "ls180.v:6334.50-6334.157" - cell $and $and$ls180.v:6334$1944 + attribute \src "ls180.v:6507.50-6507.157" + cell $and $and$ls180.v:6507$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6334$1942_Y - connect \B $eq$ls180.v:6334$1943_Y - connect \Y $and$ls180.v:6334$1944_Y + connect \A $and$ls180.v:6507$2071_Y + connect \B $eq$ls180.v:6507$2072_Y + connect \Y $and$ls180.v:6507$2073_Y end - attribute \src "ls180.v:6336.49-6336.102" - cell $and $and$ls180.v:6336$1945 + attribute \src "ls180.v:6509.49-6509.102" + cell $and $and$ls180.v:6509$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245122,43 +262581,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6336$1945_Y + connect \Y $and$ls180.v:6509$2074_Y end - attribute \src "ls180.v:6336.48-6336.152" - cell $and $and$ls180.v:6336$1947 + attribute \src "ls180.v:6509.48-6509.152" + cell $and $and$ls180.v:6509$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6336$1945_Y - connect \B $eq$ls180.v:6336$1946_Y - connect \Y $and$ls180.v:6336$1947_Y + connect \A $and$ls180.v:6509$2074_Y + connect \B $eq$ls180.v:6509$2075_Y + connect \Y $and$ls180.v:6509$2076_Y end - attribute \src "ls180.v:6337.49-6337.105" - cell $and $and$ls180.v:6337$1949 + attribute \src "ls180.v:6510.49-6510.105" + cell $and $and$ls180.v:6510$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6337$1948_Y - connect \Y $and$ls180.v:6337$1949_Y + connect \B $not$ls180.v:6510$2077_Y + connect \Y $and$ls180.v:6510$2078_Y end - attribute \src "ls180.v:6337.48-6337.155" - cell $and $and$ls180.v:6337$1951 + attribute \src "ls180.v:6510.48-6510.155" + cell $and $and$ls180.v:6510$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6337$1949_Y - connect \B $eq$ls180.v:6337$1950_Y - connect \Y $and$ls180.v:6337$1951_Y + connect \A $and$ls180.v:6510$2078_Y + connect \B $eq$ls180.v:6510$2079_Y + connect \Y $and$ls180.v:6510$2080_Y end - attribute \src "ls180.v:6339.49-6339.102" - cell $and $and$ls180.v:6339$1952 + attribute \src "ls180.v:6512.49-6512.102" + cell $and $and$ls180.v:6512$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245166,43 +262625,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6339$1952_Y + connect \Y $and$ls180.v:6512$2081_Y end - attribute \src "ls180.v:6339.48-6339.152" - cell $and $and$ls180.v:6339$1954 + attribute \src "ls180.v:6512.48-6512.152" + cell $and $and$ls180.v:6512$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6339$1952_Y - connect \B $eq$ls180.v:6339$1953_Y - connect \Y $and$ls180.v:6339$1954_Y + connect \A $and$ls180.v:6512$2081_Y + connect \B $eq$ls180.v:6512$2082_Y + connect \Y $and$ls180.v:6512$2083_Y end - attribute \src "ls180.v:6340.49-6340.105" - cell $and $and$ls180.v:6340$1956 + attribute \src "ls180.v:6513.49-6513.105" + cell $and $and$ls180.v:6513$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6340$1955_Y - connect \Y $and$ls180.v:6340$1956_Y + connect \B $not$ls180.v:6513$2084_Y + connect \Y $and$ls180.v:6513$2085_Y end - attribute \src "ls180.v:6340.48-6340.155" - cell $and $and$ls180.v:6340$1958 + attribute \src "ls180.v:6513.48-6513.155" + cell $and $and$ls180.v:6513$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6340$1956_Y - connect \B $eq$ls180.v:6340$1957_Y - connect \Y $and$ls180.v:6340$1958_Y + connect \A $and$ls180.v:6513$2085_Y + connect \B $eq$ls180.v:6513$2086_Y + connect \Y $and$ls180.v:6513$2087_Y end - attribute \src "ls180.v:6342.49-6342.102" - cell $and $and$ls180.v:6342$1959 + attribute \src "ls180.v:6515.49-6515.102" + cell $and $and$ls180.v:6515$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245210,43 +262669,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6342$1959_Y + connect \Y $and$ls180.v:6515$2088_Y end - attribute \src "ls180.v:6342.48-6342.152" - cell $and $and$ls180.v:6342$1961 + attribute \src "ls180.v:6515.48-6515.152" + cell $and $and$ls180.v:6515$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6342$1959_Y - connect \B $eq$ls180.v:6342$1960_Y - connect \Y $and$ls180.v:6342$1961_Y + connect \A $and$ls180.v:6515$2088_Y + connect \B $eq$ls180.v:6515$2089_Y + connect \Y $and$ls180.v:6515$2090_Y end - attribute \src "ls180.v:6343.49-6343.105" - cell $and $and$ls180.v:6343$1963 + attribute \src "ls180.v:6516.49-6516.105" + cell $and $and$ls180.v:6516$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6343$1962_Y - connect \Y $and$ls180.v:6343$1963_Y + connect \B $not$ls180.v:6516$2091_Y + connect \Y $and$ls180.v:6516$2092_Y end - attribute \src "ls180.v:6343.48-6343.155" - cell $and $and$ls180.v:6343$1965 + attribute \src "ls180.v:6516.48-6516.155" + cell $and $and$ls180.v:6516$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6343$1963_Y - connect \B $eq$ls180.v:6343$1964_Y - connect \Y $and$ls180.v:6343$1965_Y + connect \A $and$ls180.v:6516$2092_Y + connect \B $eq$ls180.v:6516$2093_Y + connect \Y $and$ls180.v:6516$2094_Y end - attribute \src "ls180.v:6345.49-6345.102" - cell $and $and$ls180.v:6345$1966 + attribute \src "ls180.v:6518.49-6518.102" + cell $and $and$ls180.v:6518$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245254,43 +262713,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6345$1966_Y + connect \Y $and$ls180.v:6518$2095_Y end - attribute \src "ls180.v:6345.48-6345.152" - cell $and $and$ls180.v:6345$1968 + attribute \src "ls180.v:6518.48-6518.152" + cell $and $and$ls180.v:6518$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6345$1966_Y - connect \B $eq$ls180.v:6345$1967_Y - connect \Y $and$ls180.v:6345$1968_Y + connect \A $and$ls180.v:6518$2095_Y + connect \B $eq$ls180.v:6518$2096_Y + connect \Y $and$ls180.v:6518$2097_Y end - attribute \src "ls180.v:6346.49-6346.105" - cell $and $and$ls180.v:6346$1970 + attribute \src "ls180.v:6519.49-6519.105" + cell $and $and$ls180.v:6519$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6346$1969_Y - connect \Y $and$ls180.v:6346$1970_Y + connect \B $not$ls180.v:6519$2098_Y + connect \Y $and$ls180.v:6519$2099_Y end - attribute \src "ls180.v:6346.48-6346.155" - cell $and $and$ls180.v:6346$1972 + attribute \src "ls180.v:6519.48-6519.155" + cell $and $and$ls180.v:6519$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6346$1970_Y - connect \B $eq$ls180.v:6346$1971_Y - connect \Y $and$ls180.v:6346$1972_Y + connect \A $and$ls180.v:6519$2099_Y + connect \B $eq$ls180.v:6519$2100_Y + connect \Y $and$ls180.v:6519$2101_Y end - attribute \src "ls180.v:6363.42-6363.97" - cell $and $and$ls180.v:6363$1974 + attribute \src "ls180.v:6536.42-6536.97" + cell $and $and$ls180.v:6536$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245298,43 +262757,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6363$1974_Y + connect \Y $and$ls180.v:6536$2103_Y end - attribute \src "ls180.v:6363.41-6363.148" - cell $and $and$ls180.v:6363$1976 + attribute \src "ls180.v:6536.41-6536.148" + cell $and $and$ls180.v:6536$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6363$1974_Y - connect \B $eq$ls180.v:6363$1975_Y - connect \Y $and$ls180.v:6363$1976_Y + connect \A $and$ls180.v:6536$2103_Y + connect \B $eq$ls180.v:6536$2104_Y + connect \Y $and$ls180.v:6536$2105_Y end - attribute \src "ls180.v:6364.42-6364.100" - cell $and $and$ls180.v:6364$1978 + attribute \src "ls180.v:6537.42-6537.100" + cell $and $and$ls180.v:6537$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6364$1977_Y - connect \Y $and$ls180.v:6364$1978_Y + connect \B $not$ls180.v:6537$2106_Y + connect \Y $and$ls180.v:6537$2107_Y end - attribute \src "ls180.v:6364.41-6364.151" - cell $and $and$ls180.v:6364$1980 + attribute \src "ls180.v:6537.41-6537.151" + cell $and $and$ls180.v:6537$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6364$1978_Y - connect \B $eq$ls180.v:6364$1979_Y - connect \Y $and$ls180.v:6364$1980_Y + connect \A $and$ls180.v:6537$2107_Y + connect \B $eq$ls180.v:6537$2108_Y + connect \Y $and$ls180.v:6537$2109_Y end - attribute \src "ls180.v:6366.42-6366.97" - cell $and $and$ls180.v:6366$1981 + attribute \src "ls180.v:6539.42-6539.97" + cell $and $and$ls180.v:6539$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245342,43 +262801,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6366$1981_Y + connect \Y $and$ls180.v:6539$2110_Y end - attribute \src "ls180.v:6366.41-6366.148" - cell $and $and$ls180.v:6366$1983 + attribute \src "ls180.v:6539.41-6539.148" + cell $and $and$ls180.v:6539$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6366$1981_Y - connect \B $eq$ls180.v:6366$1982_Y - connect \Y $and$ls180.v:6366$1983_Y + connect \A $and$ls180.v:6539$2110_Y + connect \B $eq$ls180.v:6539$2111_Y + connect \Y $and$ls180.v:6539$2112_Y end - attribute \src "ls180.v:6367.42-6367.100" - cell $and $and$ls180.v:6367$1985 + attribute \src "ls180.v:6540.42-6540.100" + cell $and $and$ls180.v:6540$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6367$1984_Y - connect \Y $and$ls180.v:6367$1985_Y + connect \B $not$ls180.v:6540$2113_Y + connect \Y $and$ls180.v:6540$2114_Y end - attribute \src "ls180.v:6367.41-6367.151" - cell $and $and$ls180.v:6367$1987 + attribute \src "ls180.v:6540.41-6540.151" + cell $and $and$ls180.v:6540$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6367$1985_Y - connect \B $eq$ls180.v:6367$1986_Y - connect \Y $and$ls180.v:6367$1987_Y + connect \A $and$ls180.v:6540$2114_Y + connect \B $eq$ls180.v:6540$2115_Y + connect \Y $and$ls180.v:6540$2116_Y end - attribute \src "ls180.v:6369.40-6369.95" - cell $and $and$ls180.v:6369$1988 + attribute \src "ls180.v:6542.40-6542.95" + cell $and $and$ls180.v:6542$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245386,43 +262845,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6369$1988_Y + connect \Y $and$ls180.v:6542$2117_Y end - attribute \src "ls180.v:6369.39-6369.146" - cell $and $and$ls180.v:6369$1990 + attribute \src "ls180.v:6542.39-6542.146" + cell $and $and$ls180.v:6542$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6369$1988_Y - connect \B $eq$ls180.v:6369$1989_Y - connect \Y $and$ls180.v:6369$1990_Y + connect \A $and$ls180.v:6542$2117_Y + connect \B $eq$ls180.v:6542$2118_Y + connect \Y $and$ls180.v:6542$2119_Y end - attribute \src "ls180.v:6370.40-6370.98" - cell $and $and$ls180.v:6370$1992 + attribute \src "ls180.v:6543.40-6543.98" + cell $and $and$ls180.v:6543$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6370$1991_Y - connect \Y $and$ls180.v:6370$1992_Y + connect \B $not$ls180.v:6543$2120_Y + connect \Y $and$ls180.v:6543$2121_Y end - attribute \src "ls180.v:6370.39-6370.149" - cell $and $and$ls180.v:6370$1994 + attribute \src "ls180.v:6543.39-6543.149" + cell $and $and$ls180.v:6543$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6370$1992_Y - connect \B $eq$ls180.v:6370$1993_Y - connect \Y $and$ls180.v:6370$1994_Y + connect \A $and$ls180.v:6543$2121_Y + connect \B $eq$ls180.v:6543$2122_Y + connect \Y $and$ls180.v:6543$2123_Y end - attribute \src "ls180.v:6372.39-6372.94" - cell $and $and$ls180.v:6372$1995 + attribute \src "ls180.v:6545.39-6545.94" + cell $and $and$ls180.v:6545$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245430,43 +262889,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6372$1995_Y + connect \Y $and$ls180.v:6545$2124_Y end - attribute \src "ls180.v:6372.38-6372.145" - cell $and $and$ls180.v:6372$1997 + attribute \src "ls180.v:6545.38-6545.145" + cell $and $and$ls180.v:6545$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6372$1995_Y - connect \B $eq$ls180.v:6372$1996_Y - connect \Y $and$ls180.v:6372$1997_Y + connect \A $and$ls180.v:6545$2124_Y + connect \B $eq$ls180.v:6545$2125_Y + connect \Y $and$ls180.v:6545$2126_Y end - attribute \src "ls180.v:6373.39-6373.97" - cell $and $and$ls180.v:6373$1999 + attribute \src "ls180.v:6546.39-6546.97" + cell $and $and$ls180.v:6546$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6373$1998_Y - connect \Y $and$ls180.v:6373$1999_Y + connect \B $not$ls180.v:6546$2127_Y + connect \Y $and$ls180.v:6546$2128_Y end - attribute \src "ls180.v:6373.38-6373.148" - cell $and $and$ls180.v:6373$2001 + attribute \src "ls180.v:6546.38-6546.148" + cell $and $and$ls180.v:6546$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6373$1999_Y - connect \B $eq$ls180.v:6373$2000_Y - connect \Y $and$ls180.v:6373$2001_Y + connect \A $and$ls180.v:6546$2128_Y + connect \B $eq$ls180.v:6546$2129_Y + connect \Y $and$ls180.v:6546$2130_Y end - attribute \src "ls180.v:6375.38-6375.93" - cell $and $and$ls180.v:6375$2002 + attribute \src "ls180.v:6548.38-6548.93" + cell $and $and$ls180.v:6548$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245474,43 +262933,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6375$2002_Y + connect \Y $and$ls180.v:6548$2131_Y end - attribute \src "ls180.v:6375.37-6375.144" - cell $and $and$ls180.v:6375$2004 + attribute \src "ls180.v:6548.37-6548.144" + cell $and $and$ls180.v:6548$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6375$2002_Y - connect \B $eq$ls180.v:6375$2003_Y - connect \Y $and$ls180.v:6375$2004_Y + connect \A $and$ls180.v:6548$2131_Y + connect \B $eq$ls180.v:6548$2132_Y + connect \Y $and$ls180.v:6548$2133_Y end - attribute \src "ls180.v:6376.38-6376.96" - cell $and $and$ls180.v:6376$2006 + attribute \src "ls180.v:6549.38-6549.96" + cell $and $and$ls180.v:6549$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6376$2005_Y - connect \Y $and$ls180.v:6376$2006_Y + connect \B $not$ls180.v:6549$2134_Y + connect \Y $and$ls180.v:6549$2135_Y end - attribute \src "ls180.v:6376.37-6376.147" - cell $and $and$ls180.v:6376$2008 + attribute \src "ls180.v:6549.37-6549.147" + cell $and $and$ls180.v:6549$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6376$2006_Y - connect \B $eq$ls180.v:6376$2007_Y - connect \Y $and$ls180.v:6376$2008_Y + connect \A $and$ls180.v:6549$2135_Y + connect \B $eq$ls180.v:6549$2136_Y + connect \Y $and$ls180.v:6549$2137_Y end - attribute \src "ls180.v:6378.37-6378.92" - cell $and $and$ls180.v:6378$2009 + attribute \src "ls180.v:6551.37-6551.92" + cell $and $and$ls180.v:6551$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245518,43 +262977,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6378$2009_Y + connect \Y $and$ls180.v:6551$2138_Y end - attribute \src "ls180.v:6378.36-6378.143" - cell $and $and$ls180.v:6378$2011 + attribute \src "ls180.v:6551.36-6551.143" + cell $and $and$ls180.v:6551$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6378$2009_Y - connect \B $eq$ls180.v:6378$2010_Y - connect \Y $and$ls180.v:6378$2011_Y + connect \A $and$ls180.v:6551$2138_Y + connect \B $eq$ls180.v:6551$2139_Y + connect \Y $and$ls180.v:6551$2140_Y end - attribute \src "ls180.v:6379.37-6379.95" - cell $and $and$ls180.v:6379$2013 + attribute \src "ls180.v:6552.37-6552.95" + cell $and $and$ls180.v:6552$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6379$2012_Y - connect \Y $and$ls180.v:6379$2013_Y + connect \B $not$ls180.v:6552$2141_Y + connect \Y $and$ls180.v:6552$2142_Y end - attribute \src "ls180.v:6379.36-6379.146" - cell $and $and$ls180.v:6379$2015 + attribute \src "ls180.v:6552.36-6552.146" + cell $and $and$ls180.v:6552$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6379$2013_Y - connect \B $eq$ls180.v:6379$2014_Y - connect \Y $and$ls180.v:6379$2015_Y + connect \A $and$ls180.v:6552$2142_Y + connect \B $eq$ls180.v:6552$2143_Y + connect \Y $and$ls180.v:6552$2144_Y end - attribute \src "ls180.v:6381.43-6381.98" - cell $and $and$ls180.v:6381$2016 + attribute \src "ls180.v:6554.43-6554.98" + cell $and $and$ls180.v:6554$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245562,43 +263021,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6381$2016_Y + connect \Y $and$ls180.v:6554$2145_Y end - attribute \src "ls180.v:6381.42-6381.149" - cell $and $and$ls180.v:6381$2018 + attribute \src "ls180.v:6554.42-6554.149" + cell $and $and$ls180.v:6554$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6381$2016_Y - connect \B $eq$ls180.v:6381$2017_Y - connect \Y $and$ls180.v:6381$2018_Y + connect \A $and$ls180.v:6554$2145_Y + connect \B $eq$ls180.v:6554$2146_Y + connect \Y $and$ls180.v:6554$2147_Y end - attribute \src "ls180.v:6382.43-6382.101" - cell $and $and$ls180.v:6382$2020 + attribute \src "ls180.v:6555.43-6555.101" + cell $and $and$ls180.v:6555$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6382$2019_Y - connect \Y $and$ls180.v:6382$2020_Y + connect \B $not$ls180.v:6555$2148_Y + connect \Y $and$ls180.v:6555$2149_Y end - attribute \src "ls180.v:6382.42-6382.152" - cell $and $and$ls180.v:6382$2022 + attribute \src "ls180.v:6555.42-6555.152" + cell $and $and$ls180.v:6555$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6382$2020_Y - connect \B $eq$ls180.v:6382$2021_Y - connect \Y $and$ls180.v:6382$2022_Y + connect \A $and$ls180.v:6555$2149_Y + connect \B $eq$ls180.v:6555$2150_Y + connect \Y $and$ls180.v:6555$2151_Y end - attribute \src "ls180.v:6403.42-6403.97" - cell $and $and$ls180.v:6403$2025 + attribute \src "ls180.v:6576.42-6576.97" + cell $and $and$ls180.v:6576$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245606,43 +263065,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6403$2025_Y + connect \Y $and$ls180.v:6576$2154_Y end - attribute \src "ls180.v:6403.41-6403.148" - cell $and $and$ls180.v:6403$2027 + attribute \src "ls180.v:6576.41-6576.148" + cell $and $and$ls180.v:6576$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6403$2025_Y - connect \B $eq$ls180.v:6403$2026_Y - connect \Y $and$ls180.v:6403$2027_Y + connect \A $and$ls180.v:6576$2154_Y + connect \B $eq$ls180.v:6576$2155_Y + connect \Y $and$ls180.v:6576$2156_Y end - attribute \src "ls180.v:6404.42-6404.100" - cell $and $and$ls180.v:6404$2029 + attribute \src "ls180.v:6577.42-6577.100" + cell $and $and$ls180.v:6577$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6404$2028_Y - connect \Y $and$ls180.v:6404$2029_Y + connect \B $not$ls180.v:6577$2157_Y + connect \Y $and$ls180.v:6577$2158_Y end - attribute \src "ls180.v:6404.41-6404.151" - cell $and $and$ls180.v:6404$2031 + attribute \src "ls180.v:6577.41-6577.151" + cell $and $and$ls180.v:6577$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6404$2029_Y - connect \B $eq$ls180.v:6404$2030_Y - connect \Y $and$ls180.v:6404$2031_Y + connect \A $and$ls180.v:6577$2158_Y + connect \B $eq$ls180.v:6577$2159_Y + connect \Y $and$ls180.v:6577$2160_Y end - attribute \src "ls180.v:6406.42-6406.97" - cell $and $and$ls180.v:6406$2032 + attribute \src "ls180.v:6579.42-6579.97" + cell $and $and$ls180.v:6579$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245650,43 +263109,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6406$2032_Y + connect \Y $and$ls180.v:6579$2161_Y end - attribute \src "ls180.v:6406.41-6406.148" - cell $and $and$ls180.v:6406$2034 + attribute \src "ls180.v:6579.41-6579.148" + cell $and $and$ls180.v:6579$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6406$2032_Y - connect \B $eq$ls180.v:6406$2033_Y - connect \Y $and$ls180.v:6406$2034_Y + connect \A $and$ls180.v:6579$2161_Y + connect \B $eq$ls180.v:6579$2162_Y + connect \Y $and$ls180.v:6579$2163_Y end - attribute \src "ls180.v:6407.42-6407.100" - cell $and $and$ls180.v:6407$2036 + attribute \src "ls180.v:6580.42-6580.100" + cell $and $and$ls180.v:6580$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6407$2035_Y - connect \Y $and$ls180.v:6407$2036_Y + connect \B $not$ls180.v:6580$2164_Y + connect \Y $and$ls180.v:6580$2165_Y end - attribute \src "ls180.v:6407.41-6407.151" - cell $and $and$ls180.v:6407$2038 + attribute \src "ls180.v:6580.41-6580.151" + cell $and $and$ls180.v:6580$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6407$2036_Y - connect \B $eq$ls180.v:6407$2037_Y - connect \Y $and$ls180.v:6407$2038_Y + connect \A $and$ls180.v:6580$2165_Y + connect \B $eq$ls180.v:6580$2166_Y + connect \Y $and$ls180.v:6580$2167_Y end - attribute \src "ls180.v:6409.40-6409.95" - cell $and $and$ls180.v:6409$2039 + attribute \src "ls180.v:6582.40-6582.95" + cell $and $and$ls180.v:6582$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245694,43 +263153,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6409$2039_Y + connect \Y $and$ls180.v:6582$2168_Y end - attribute \src "ls180.v:6409.39-6409.146" - cell $and $and$ls180.v:6409$2041 + attribute \src "ls180.v:6582.39-6582.146" + cell $and $and$ls180.v:6582$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6409$2039_Y - connect \B $eq$ls180.v:6409$2040_Y - connect \Y $and$ls180.v:6409$2041_Y + connect \A $and$ls180.v:6582$2168_Y + connect \B $eq$ls180.v:6582$2169_Y + connect \Y $and$ls180.v:6582$2170_Y end - attribute \src "ls180.v:6410.40-6410.98" - cell $and $and$ls180.v:6410$2043 + attribute \src "ls180.v:6583.40-6583.98" + cell $and $and$ls180.v:6583$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6410$2042_Y - connect \Y $and$ls180.v:6410$2043_Y + connect \B $not$ls180.v:6583$2171_Y + connect \Y $and$ls180.v:6583$2172_Y end - attribute \src "ls180.v:6410.39-6410.149" - cell $and $and$ls180.v:6410$2045 + attribute \src "ls180.v:6583.39-6583.149" + cell $and $and$ls180.v:6583$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6410$2043_Y - connect \B $eq$ls180.v:6410$2044_Y - connect \Y $and$ls180.v:6410$2045_Y + connect \A $and$ls180.v:6583$2172_Y + connect \B $eq$ls180.v:6583$2173_Y + connect \Y $and$ls180.v:6583$2174_Y end - attribute \src "ls180.v:6412.39-6412.94" - cell $and $and$ls180.v:6412$2046 + attribute \src "ls180.v:6585.39-6585.94" + cell $and $and$ls180.v:6585$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245738,43 +263197,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6412$2046_Y + connect \Y $and$ls180.v:6585$2175_Y end - attribute \src "ls180.v:6412.38-6412.145" - cell $and $and$ls180.v:6412$2048 + attribute \src "ls180.v:6585.38-6585.145" + cell $and $and$ls180.v:6585$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6412$2046_Y - connect \B $eq$ls180.v:6412$2047_Y - connect \Y $and$ls180.v:6412$2048_Y + connect \A $and$ls180.v:6585$2175_Y + connect \B $eq$ls180.v:6585$2176_Y + connect \Y $and$ls180.v:6585$2177_Y end - attribute \src "ls180.v:6413.39-6413.97" - cell $and $and$ls180.v:6413$2050 + attribute \src "ls180.v:6586.39-6586.97" + cell $and $and$ls180.v:6586$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6413$2049_Y - connect \Y $and$ls180.v:6413$2050_Y + connect \B $not$ls180.v:6586$2178_Y + connect \Y $and$ls180.v:6586$2179_Y end - attribute \src "ls180.v:6413.38-6413.148" - cell $and $and$ls180.v:6413$2052 + attribute \src "ls180.v:6586.38-6586.148" + cell $and $and$ls180.v:6586$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6413$2050_Y - connect \B $eq$ls180.v:6413$2051_Y - connect \Y $and$ls180.v:6413$2052_Y + connect \A $and$ls180.v:6586$2179_Y + connect \B $eq$ls180.v:6586$2180_Y + connect \Y $and$ls180.v:6586$2181_Y end - attribute \src "ls180.v:6415.38-6415.93" - cell $and $and$ls180.v:6415$2053 + attribute \src "ls180.v:6588.38-6588.93" + cell $and $and$ls180.v:6588$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245782,43 +263241,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6415$2053_Y + connect \Y $and$ls180.v:6588$2182_Y end - attribute \src "ls180.v:6415.37-6415.144" - cell $and $and$ls180.v:6415$2055 + attribute \src "ls180.v:6588.37-6588.144" + cell $and $and$ls180.v:6588$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6415$2053_Y - connect \B $eq$ls180.v:6415$2054_Y - connect \Y $and$ls180.v:6415$2055_Y + connect \A $and$ls180.v:6588$2182_Y + connect \B $eq$ls180.v:6588$2183_Y + connect \Y $and$ls180.v:6588$2184_Y end - attribute \src "ls180.v:6416.38-6416.96" - cell $and $and$ls180.v:6416$2057 + attribute \src "ls180.v:6589.38-6589.96" + cell $and $and$ls180.v:6589$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6416$2056_Y - connect \Y $and$ls180.v:6416$2057_Y + connect \B $not$ls180.v:6589$2185_Y + connect \Y $and$ls180.v:6589$2186_Y end - attribute \src "ls180.v:6416.37-6416.147" - cell $and $and$ls180.v:6416$2059 + attribute \src "ls180.v:6589.37-6589.147" + cell $and $and$ls180.v:6589$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6416$2057_Y - connect \B $eq$ls180.v:6416$2058_Y - connect \Y $and$ls180.v:6416$2059_Y + connect \A $and$ls180.v:6589$2186_Y + connect \B $eq$ls180.v:6589$2187_Y + connect \Y $and$ls180.v:6589$2188_Y end - attribute \src "ls180.v:6418.37-6418.92" - cell $and $and$ls180.v:6418$2060 + attribute \src "ls180.v:6591.37-6591.92" + cell $and $and$ls180.v:6591$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245826,43 +263285,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6418$2060_Y + connect \Y $and$ls180.v:6591$2189_Y end - attribute \src "ls180.v:6418.36-6418.143" - cell $and $and$ls180.v:6418$2062 + attribute \src "ls180.v:6591.36-6591.143" + cell $and $and$ls180.v:6591$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6418$2060_Y - connect \B $eq$ls180.v:6418$2061_Y - connect \Y $and$ls180.v:6418$2062_Y + connect \A $and$ls180.v:6591$2189_Y + connect \B $eq$ls180.v:6591$2190_Y + connect \Y $and$ls180.v:6591$2191_Y end - attribute \src "ls180.v:6419.37-6419.95" - cell $and $and$ls180.v:6419$2064 + attribute \src "ls180.v:6592.37-6592.95" + cell $and $and$ls180.v:6592$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6419$2063_Y - connect \Y $and$ls180.v:6419$2064_Y + connect \B $not$ls180.v:6592$2192_Y + connect \Y $and$ls180.v:6592$2193_Y end - attribute \src "ls180.v:6419.36-6419.146" - cell $and $and$ls180.v:6419$2066 + attribute \src "ls180.v:6592.36-6592.146" + cell $and $and$ls180.v:6592$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6419$2064_Y - connect \B $eq$ls180.v:6419$2065_Y - connect \Y $and$ls180.v:6419$2066_Y + connect \A $and$ls180.v:6592$2193_Y + connect \B $eq$ls180.v:6592$2194_Y + connect \Y $and$ls180.v:6592$2195_Y end - attribute \src "ls180.v:6421.43-6421.98" - cell $and $and$ls180.v:6421$2067 + attribute \src "ls180.v:6594.43-6594.98" + cell $and $and$ls180.v:6594$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245870,43 +263329,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6421$2067_Y + connect \Y $and$ls180.v:6594$2196_Y end - attribute \src "ls180.v:6421.42-6421.149" - cell $and $and$ls180.v:6421$2069 + attribute \src "ls180.v:6594.42-6594.149" + cell $and $and$ls180.v:6594$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6421$2067_Y - connect \B $eq$ls180.v:6421$2068_Y - connect \Y $and$ls180.v:6421$2069_Y + connect \A $and$ls180.v:6594$2196_Y + connect \B $eq$ls180.v:6594$2197_Y + connect \Y $and$ls180.v:6594$2198_Y end - attribute \src "ls180.v:6422.43-6422.101" - cell $and $and$ls180.v:6422$2071 + attribute \src "ls180.v:6595.43-6595.101" + cell $and $and$ls180.v:6595$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6422$2070_Y - connect \Y $and$ls180.v:6422$2071_Y + connect \B $not$ls180.v:6595$2199_Y + connect \Y $and$ls180.v:6595$2200_Y end - attribute \src "ls180.v:6422.42-6422.152" - cell $and $and$ls180.v:6422$2073 + attribute \src "ls180.v:6595.42-6595.152" + cell $and $and$ls180.v:6595$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6422$2071_Y - connect \B $eq$ls180.v:6422$2072_Y - connect \Y $and$ls180.v:6422$2073_Y + connect \A $and$ls180.v:6595$2200_Y + connect \B $eq$ls180.v:6595$2201_Y + connect \Y $and$ls180.v:6595$2202_Y end - attribute \src "ls180.v:6424.46-6424.101" - cell $and $and$ls180.v:6424$2074 + attribute \src "ls180.v:6597.46-6597.101" + cell $and $and$ls180.v:6597$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245914,43 +263373,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6424$2074_Y + connect \Y $and$ls180.v:6597$2203_Y end - attribute \src "ls180.v:6424.45-6424.152" - cell $and $and$ls180.v:6424$2076 + attribute \src "ls180.v:6597.45-6597.152" + cell $and $and$ls180.v:6597$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6424$2074_Y - connect \B $eq$ls180.v:6424$2075_Y - connect \Y $and$ls180.v:6424$2076_Y + connect \A $and$ls180.v:6597$2203_Y + connect \B $eq$ls180.v:6597$2204_Y + connect \Y $and$ls180.v:6597$2205_Y end - attribute \src "ls180.v:6425.46-6425.104" - cell $and $and$ls180.v:6425$2078 + attribute \src "ls180.v:6598.46-6598.104" + cell $and $and$ls180.v:6598$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6425$2077_Y - connect \Y $and$ls180.v:6425$2078_Y + connect \B $not$ls180.v:6598$2206_Y + connect \Y $and$ls180.v:6598$2207_Y end - attribute \src "ls180.v:6425.45-6425.155" - cell $and $and$ls180.v:6425$2080 + attribute \src "ls180.v:6598.45-6598.155" + cell $and $and$ls180.v:6598$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6425$2078_Y - connect \B $eq$ls180.v:6425$2079_Y - connect \Y $and$ls180.v:6425$2080_Y + connect \A $and$ls180.v:6598$2207_Y + connect \B $eq$ls180.v:6598$2208_Y + connect \Y $and$ls180.v:6598$2209_Y end - attribute \src "ls180.v:6427.46-6427.101" - cell $and $and$ls180.v:6427$2081 + attribute \src "ls180.v:6600.46-6600.101" + cell $and $and$ls180.v:6600$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245958,43 +263417,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6427$2081_Y + connect \Y $and$ls180.v:6600$2210_Y end - attribute \src "ls180.v:6427.45-6427.152" - cell $and $and$ls180.v:6427$2083 + attribute \src "ls180.v:6600.45-6600.152" + cell $and $and$ls180.v:6600$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6427$2081_Y - connect \B $eq$ls180.v:6427$2082_Y - connect \Y $and$ls180.v:6427$2083_Y + connect \A $and$ls180.v:6600$2210_Y + connect \B $eq$ls180.v:6600$2211_Y + connect \Y $and$ls180.v:6600$2212_Y end - attribute \src "ls180.v:6428.46-6428.104" - cell $and $and$ls180.v:6428$2085 + attribute \src "ls180.v:6601.46-6601.104" + cell $and $and$ls180.v:6601$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6428$2084_Y - connect \Y $and$ls180.v:6428$2085_Y + connect \B $not$ls180.v:6601$2213_Y + connect \Y $and$ls180.v:6601$2214_Y end - attribute \src "ls180.v:6428.45-6428.155" - cell $and $and$ls180.v:6428$2087 + attribute \src "ls180.v:6601.45-6601.155" + cell $and $and$ls180.v:6601$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6428$2085_Y - connect \B $eq$ls180.v:6428$2086_Y - connect \Y $and$ls180.v:6428$2087_Y + connect \A $and$ls180.v:6601$2214_Y + connect \B $eq$ls180.v:6601$2215_Y + connect \Y $and$ls180.v:6601$2216_Y end - attribute \src "ls180.v:6451.39-6451.94" - cell $and $and$ls180.v:6451$2090 + attribute \src "ls180.v:6624.39-6624.94" + cell $and $and$ls180.v:6624$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246002,43 +263461,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6451$2090_Y + connect \Y $and$ls180.v:6624$2219_Y end - attribute \src "ls180.v:6451.38-6451.145" - cell $and $and$ls180.v:6451$2092 + attribute \src "ls180.v:6624.38-6624.145" + cell $and $and$ls180.v:6624$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6451$2090_Y - connect \B $eq$ls180.v:6451$2091_Y - connect \Y $and$ls180.v:6451$2092_Y + connect \A $and$ls180.v:6624$2219_Y + connect \B $eq$ls180.v:6624$2220_Y + connect \Y $and$ls180.v:6624$2221_Y end - attribute \src "ls180.v:6452.39-6452.97" - cell $and $and$ls180.v:6452$2094 + attribute \src "ls180.v:6625.39-6625.97" + cell $and $and$ls180.v:6625$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6452$2093_Y - connect \Y $and$ls180.v:6452$2094_Y + connect \B $not$ls180.v:6625$2222_Y + connect \Y $and$ls180.v:6625$2223_Y end - attribute \src "ls180.v:6452.38-6452.148" - cell $and $and$ls180.v:6452$2096 + attribute \src "ls180.v:6625.38-6625.148" + cell $and $and$ls180.v:6625$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6452$2094_Y - connect \B $eq$ls180.v:6452$2095_Y - connect \Y $and$ls180.v:6452$2096_Y + connect \A $and$ls180.v:6625$2223_Y + connect \B $eq$ls180.v:6625$2224_Y + connect \Y $and$ls180.v:6625$2225_Y end - attribute \src "ls180.v:6454.39-6454.94" - cell $and $and$ls180.v:6454$2097 + attribute \src "ls180.v:6627.39-6627.94" + cell $and $and$ls180.v:6627$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246046,43 +263505,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6454$2097_Y + connect \Y $and$ls180.v:6627$2226_Y end - attribute \src "ls180.v:6454.38-6454.145" - cell $and $and$ls180.v:6454$2099 + attribute \src "ls180.v:6627.38-6627.145" + cell $and $and$ls180.v:6627$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6454$2097_Y - connect \B $eq$ls180.v:6454$2098_Y - connect \Y $and$ls180.v:6454$2099_Y + connect \A $and$ls180.v:6627$2226_Y + connect \B $eq$ls180.v:6627$2227_Y + connect \Y $and$ls180.v:6627$2228_Y end - attribute \src "ls180.v:6455.39-6455.97" - cell $and $and$ls180.v:6455$2101 + attribute \src "ls180.v:6628.39-6628.97" + cell $and $and$ls180.v:6628$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6455$2100_Y - connect \Y $and$ls180.v:6455$2101_Y + connect \B $not$ls180.v:6628$2229_Y + connect \Y $and$ls180.v:6628$2230_Y end - attribute \src "ls180.v:6455.38-6455.148" - cell $and $and$ls180.v:6455$2103 + attribute \src "ls180.v:6628.38-6628.148" + cell $and $and$ls180.v:6628$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6455$2101_Y - connect \B $eq$ls180.v:6455$2102_Y - connect \Y $and$ls180.v:6455$2103_Y + connect \A $and$ls180.v:6628$2230_Y + connect \B $eq$ls180.v:6628$2231_Y + connect \Y $and$ls180.v:6628$2232_Y end - attribute \src "ls180.v:6457.39-6457.94" - cell $and $and$ls180.v:6457$2104 + attribute \src "ls180.v:6630.39-6630.94" + cell $and $and$ls180.v:6630$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246090,43 +263549,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6457$2104_Y + connect \Y $and$ls180.v:6630$2233_Y end - attribute \src "ls180.v:6457.38-6457.145" - cell $and $and$ls180.v:6457$2106 + attribute \src "ls180.v:6630.38-6630.145" + cell $and $and$ls180.v:6630$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6457$2104_Y - connect \B $eq$ls180.v:6457$2105_Y - connect \Y $and$ls180.v:6457$2106_Y + connect \A $and$ls180.v:6630$2233_Y + connect \B $eq$ls180.v:6630$2234_Y + connect \Y $and$ls180.v:6630$2235_Y end - attribute \src "ls180.v:6458.39-6458.97" - cell $and $and$ls180.v:6458$2108 + attribute \src "ls180.v:6631.39-6631.97" + cell $and $and$ls180.v:6631$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6458$2107_Y - connect \Y $and$ls180.v:6458$2108_Y + connect \B $not$ls180.v:6631$2236_Y + connect \Y $and$ls180.v:6631$2237_Y end - attribute \src "ls180.v:6458.38-6458.148" - cell $and $and$ls180.v:6458$2110 + attribute \src "ls180.v:6631.38-6631.148" + cell $and $and$ls180.v:6631$2239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6458$2108_Y - connect \B $eq$ls180.v:6458$2109_Y - connect \Y $and$ls180.v:6458$2110_Y + connect \A $and$ls180.v:6631$2237_Y + connect \B $eq$ls180.v:6631$2238_Y + connect \Y $and$ls180.v:6631$2239_Y end - attribute \src "ls180.v:6460.39-6460.94" - cell $and $and$ls180.v:6460$2111 + attribute \src "ls180.v:6633.39-6633.94" + cell $and $and$ls180.v:6633$2240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246134,43 +263593,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6460$2111_Y + connect \Y $and$ls180.v:6633$2240_Y end - attribute \src "ls180.v:6460.38-6460.145" - cell $and $and$ls180.v:6460$2113 + attribute \src "ls180.v:6633.38-6633.145" + cell $and $and$ls180.v:6633$2242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6460$2111_Y - connect \B $eq$ls180.v:6460$2112_Y - connect \Y $and$ls180.v:6460$2113_Y + connect \A $and$ls180.v:6633$2240_Y + connect \B $eq$ls180.v:6633$2241_Y + connect \Y $and$ls180.v:6633$2242_Y end - attribute \src "ls180.v:6461.39-6461.97" - cell $and $and$ls180.v:6461$2115 + attribute \src "ls180.v:6634.39-6634.97" + cell $and $and$ls180.v:6634$2244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6461$2114_Y - connect \Y $and$ls180.v:6461$2115_Y + connect \B $not$ls180.v:6634$2243_Y + connect \Y $and$ls180.v:6634$2244_Y end - attribute \src "ls180.v:6461.38-6461.148" - cell $and $and$ls180.v:6461$2117 + attribute \src "ls180.v:6634.38-6634.148" + cell $and $and$ls180.v:6634$2246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6461$2115_Y - connect \B $eq$ls180.v:6461$2116_Y - connect \Y $and$ls180.v:6461$2117_Y + connect \A $and$ls180.v:6634$2244_Y + connect \B $eq$ls180.v:6634$2245_Y + connect \Y $and$ls180.v:6634$2246_Y end - attribute \src "ls180.v:6463.41-6463.96" - cell $and $and$ls180.v:6463$2118 + attribute \src "ls180.v:6636.41-6636.96" + cell $and $and$ls180.v:6636$2247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246178,43 +263637,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6463$2118_Y + connect \Y $and$ls180.v:6636$2247_Y end - attribute \src "ls180.v:6463.40-6463.147" - cell $and $and$ls180.v:6463$2120 + attribute \src "ls180.v:6636.40-6636.147" + cell $and $and$ls180.v:6636$2249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6463$2118_Y - connect \B $eq$ls180.v:6463$2119_Y - connect \Y $and$ls180.v:6463$2120_Y + connect \A $and$ls180.v:6636$2247_Y + connect \B $eq$ls180.v:6636$2248_Y + connect \Y $and$ls180.v:6636$2249_Y end - attribute \src "ls180.v:6464.41-6464.99" - cell $and $and$ls180.v:6464$2122 + attribute \src "ls180.v:6637.41-6637.99" + cell $and $and$ls180.v:6637$2251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6464$2121_Y - connect \Y $and$ls180.v:6464$2122_Y + connect \B $not$ls180.v:6637$2250_Y + connect \Y $and$ls180.v:6637$2251_Y end - attribute \src "ls180.v:6464.40-6464.150" - cell $and $and$ls180.v:6464$2124 + attribute \src "ls180.v:6637.40-6637.150" + cell $and $and$ls180.v:6637$2253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6464$2122_Y - connect \B $eq$ls180.v:6464$2123_Y - connect \Y $and$ls180.v:6464$2124_Y + connect \A $and$ls180.v:6637$2251_Y + connect \B $eq$ls180.v:6637$2252_Y + connect \Y $and$ls180.v:6637$2253_Y end - attribute \src "ls180.v:6466.41-6466.96" - cell $and $and$ls180.v:6466$2125 + attribute \src "ls180.v:6639.41-6639.96" + cell $and $and$ls180.v:6639$2254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246222,43 +263681,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6466$2125_Y + connect \Y $and$ls180.v:6639$2254_Y end - attribute \src "ls180.v:6466.40-6466.147" - cell $and $and$ls180.v:6466$2127 + attribute \src "ls180.v:6639.40-6639.147" + cell $and $and$ls180.v:6639$2256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6466$2125_Y - connect \B $eq$ls180.v:6466$2126_Y - connect \Y $and$ls180.v:6466$2127_Y + connect \A $and$ls180.v:6639$2254_Y + connect \B $eq$ls180.v:6639$2255_Y + connect \Y $and$ls180.v:6639$2256_Y end - attribute \src "ls180.v:6467.41-6467.99" - cell $and $and$ls180.v:6467$2129 + attribute \src "ls180.v:6640.41-6640.99" + cell $and $and$ls180.v:6640$2258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6467$2128_Y - connect \Y $and$ls180.v:6467$2129_Y + connect \B $not$ls180.v:6640$2257_Y + connect \Y $and$ls180.v:6640$2258_Y end - attribute \src "ls180.v:6467.40-6467.150" - cell $and $and$ls180.v:6467$2131 + attribute \src "ls180.v:6640.40-6640.150" + cell $and $and$ls180.v:6640$2260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6467$2129_Y - connect \B $eq$ls180.v:6467$2130_Y - connect \Y $and$ls180.v:6467$2131_Y + connect \A $and$ls180.v:6640$2258_Y + connect \B $eq$ls180.v:6640$2259_Y + connect \Y $and$ls180.v:6640$2260_Y end - attribute \src "ls180.v:6469.41-6469.96" - cell $and $and$ls180.v:6469$2132 + attribute \src "ls180.v:6642.41-6642.96" + cell $and $and$ls180.v:6642$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246266,43 +263725,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6469$2132_Y + connect \Y $and$ls180.v:6642$2261_Y end - attribute \src "ls180.v:6469.40-6469.147" - cell $and $and$ls180.v:6469$2134 + attribute \src "ls180.v:6642.40-6642.147" + cell $and $and$ls180.v:6642$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6469$2132_Y - connect \B $eq$ls180.v:6469$2133_Y - connect \Y $and$ls180.v:6469$2134_Y + connect \A $and$ls180.v:6642$2261_Y + connect \B $eq$ls180.v:6642$2262_Y + connect \Y $and$ls180.v:6642$2263_Y end - attribute \src "ls180.v:6470.41-6470.99" - cell $and $and$ls180.v:6470$2136 + attribute \src "ls180.v:6643.41-6643.99" + cell $and $and$ls180.v:6643$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6470$2135_Y - connect \Y $and$ls180.v:6470$2136_Y + connect \B $not$ls180.v:6643$2264_Y + connect \Y $and$ls180.v:6643$2265_Y end - attribute \src "ls180.v:6470.40-6470.150" - cell $and $and$ls180.v:6470$2138 + attribute \src "ls180.v:6643.40-6643.150" + cell $and $and$ls180.v:6643$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6470$2136_Y - connect \B $eq$ls180.v:6470$2137_Y - connect \Y $and$ls180.v:6470$2138_Y + connect \A $and$ls180.v:6643$2265_Y + connect \B $eq$ls180.v:6643$2266_Y + connect \Y $and$ls180.v:6643$2267_Y end - attribute \src "ls180.v:6472.41-6472.96" - cell $and $and$ls180.v:6472$2139 + attribute \src "ls180.v:6645.41-6645.96" + cell $and $and$ls180.v:6645$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246310,43 +263769,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6472$2139_Y + connect \Y $and$ls180.v:6645$2268_Y end - attribute \src "ls180.v:6472.40-6472.147" - cell $and $and$ls180.v:6472$2141 + attribute \src "ls180.v:6645.40-6645.147" + cell $and $and$ls180.v:6645$2270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6472$2139_Y - connect \B $eq$ls180.v:6472$2140_Y - connect \Y $and$ls180.v:6472$2141_Y + connect \A $and$ls180.v:6645$2268_Y + connect \B $eq$ls180.v:6645$2269_Y + connect \Y $and$ls180.v:6645$2270_Y end - attribute \src "ls180.v:6473.41-6473.99" - cell $and $and$ls180.v:6473$2143 + attribute \src "ls180.v:6646.41-6646.99" + cell $and $and$ls180.v:6646$2272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6473$2142_Y - connect \Y $and$ls180.v:6473$2143_Y + connect \B $not$ls180.v:6646$2271_Y + connect \Y $and$ls180.v:6646$2272_Y end - attribute \src "ls180.v:6473.40-6473.150" - cell $and $and$ls180.v:6473$2145 + attribute \src "ls180.v:6646.40-6646.150" + cell $and $and$ls180.v:6646$2274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6473$2143_Y - connect \B $eq$ls180.v:6473$2144_Y - connect \Y $and$ls180.v:6473$2145_Y + connect \A $and$ls180.v:6646$2272_Y + connect \B $eq$ls180.v:6646$2273_Y + connect \Y $and$ls180.v:6646$2274_Y end - attribute \src "ls180.v:6475.37-6475.92" - cell $and $and$ls180.v:6475$2146 + attribute \src "ls180.v:6648.37-6648.92" + cell $and $and$ls180.v:6648$2275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246354,43 +263813,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6475$2146_Y + connect \Y $and$ls180.v:6648$2275_Y end - attribute \src "ls180.v:6475.36-6475.143" - cell $and $and$ls180.v:6475$2148 + attribute \src "ls180.v:6648.36-6648.143" + cell $and $and$ls180.v:6648$2277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6475$2146_Y - connect \B $eq$ls180.v:6475$2147_Y - connect \Y $and$ls180.v:6475$2148_Y + connect \A $and$ls180.v:6648$2275_Y + connect \B $eq$ls180.v:6648$2276_Y + connect \Y $and$ls180.v:6648$2277_Y end - attribute \src "ls180.v:6476.37-6476.95" - cell $and $and$ls180.v:6476$2150 + attribute \src "ls180.v:6649.37-6649.95" + cell $and $and$ls180.v:6649$2279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6476$2149_Y - connect \Y $and$ls180.v:6476$2150_Y + connect \B $not$ls180.v:6649$2278_Y + connect \Y $and$ls180.v:6649$2279_Y end - attribute \src "ls180.v:6476.36-6476.146" - cell $and $and$ls180.v:6476$2152 + attribute \src "ls180.v:6649.36-6649.146" + cell $and $and$ls180.v:6649$2281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6476$2150_Y - connect \B $eq$ls180.v:6476$2151_Y - connect \Y $and$ls180.v:6476$2152_Y + connect \A $and$ls180.v:6649$2279_Y + connect \B $eq$ls180.v:6649$2280_Y + connect \Y $and$ls180.v:6649$2281_Y end - attribute \src "ls180.v:6478.47-6478.102" - cell $and $and$ls180.v:6478$2153 + attribute \src "ls180.v:6651.47-6651.102" + cell $and $and$ls180.v:6651$2282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246398,43 +263857,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6478$2153_Y + connect \Y $and$ls180.v:6651$2282_Y end - attribute \src "ls180.v:6478.46-6478.153" - cell $and $and$ls180.v:6478$2155 + attribute \src "ls180.v:6651.46-6651.153" + cell $and $and$ls180.v:6651$2284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6478$2153_Y - connect \B $eq$ls180.v:6478$2154_Y - connect \Y $and$ls180.v:6478$2155_Y + connect \A $and$ls180.v:6651$2282_Y + connect \B $eq$ls180.v:6651$2283_Y + connect \Y $and$ls180.v:6651$2284_Y end - attribute \src "ls180.v:6479.47-6479.105" - cell $and $and$ls180.v:6479$2157 + attribute \src "ls180.v:6652.47-6652.105" + cell $and $and$ls180.v:6652$2286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6479$2156_Y - connect \Y $and$ls180.v:6479$2157_Y + connect \B $not$ls180.v:6652$2285_Y + connect \Y $and$ls180.v:6652$2286_Y end - attribute \src "ls180.v:6479.46-6479.156" - cell $and $and$ls180.v:6479$2159 + attribute \src "ls180.v:6652.46-6652.156" + cell $and $and$ls180.v:6652$2288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6479$2157_Y - connect \B $eq$ls180.v:6479$2158_Y - connect \Y $and$ls180.v:6479$2159_Y + connect \A $and$ls180.v:6652$2286_Y + connect \B $eq$ls180.v:6652$2287_Y + connect \Y $and$ls180.v:6652$2288_Y end - attribute \src "ls180.v:6481.40-6481.95" - cell $and $and$ls180.v:6481$2160 + attribute \src "ls180.v:6654.40-6654.95" + cell $and $and$ls180.v:6654$2289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246442,43 +263901,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6481$2160_Y + connect \Y $and$ls180.v:6654$2289_Y end - attribute \src "ls180.v:6481.39-6481.147" - cell $and $and$ls180.v:6481$2162 + attribute \src "ls180.v:6654.39-6654.147" + cell $and $and$ls180.v:6654$2291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6481$2160_Y - connect \B $eq$ls180.v:6481$2161_Y - connect \Y $and$ls180.v:6481$2162_Y + connect \A $and$ls180.v:6654$2289_Y + connect \B $eq$ls180.v:6654$2290_Y + connect \Y $and$ls180.v:6654$2291_Y end - attribute \src "ls180.v:6482.40-6482.98" - cell $and $and$ls180.v:6482$2164 + attribute \src "ls180.v:6655.40-6655.98" + cell $and $and$ls180.v:6655$2293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6482$2163_Y - connect \Y $and$ls180.v:6482$2164_Y + connect \B $not$ls180.v:6655$2292_Y + connect \Y $and$ls180.v:6655$2293_Y end - attribute \src "ls180.v:6482.39-6482.150" - cell $and $and$ls180.v:6482$2166 + attribute \src "ls180.v:6655.39-6655.150" + cell $and $and$ls180.v:6655$2295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6482$2164_Y - connect \B $eq$ls180.v:6482$2165_Y - connect \Y $and$ls180.v:6482$2166_Y + connect \A $and$ls180.v:6655$2293_Y + connect \B $eq$ls180.v:6655$2294_Y + connect \Y $and$ls180.v:6655$2295_Y end - attribute \src "ls180.v:6484.40-6484.95" - cell $and $and$ls180.v:6484$2167 + attribute \src "ls180.v:6657.40-6657.95" + cell $and $and$ls180.v:6657$2296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246486,43 +263945,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6484$2167_Y + connect \Y $and$ls180.v:6657$2296_Y end - attribute \src "ls180.v:6484.39-6484.147" - cell $and $and$ls180.v:6484$2169 + attribute \src "ls180.v:6657.39-6657.147" + cell $and $and$ls180.v:6657$2298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6484$2167_Y - connect \B $eq$ls180.v:6484$2168_Y - connect \Y $and$ls180.v:6484$2169_Y + connect \A $and$ls180.v:6657$2296_Y + connect \B $eq$ls180.v:6657$2297_Y + connect \Y $and$ls180.v:6657$2298_Y end - attribute \src "ls180.v:6485.40-6485.98" - cell $and $and$ls180.v:6485$2171 + attribute \src "ls180.v:6658.40-6658.98" + cell $and $and$ls180.v:6658$2300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6485$2170_Y - connect \Y $and$ls180.v:6485$2171_Y + connect \B $not$ls180.v:6658$2299_Y + connect \Y $and$ls180.v:6658$2300_Y end - attribute \src "ls180.v:6485.39-6485.150" - cell $and $and$ls180.v:6485$2173 + attribute \src "ls180.v:6658.39-6658.150" + cell $and $and$ls180.v:6658$2302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6485$2171_Y - connect \B $eq$ls180.v:6485$2172_Y - connect \Y $and$ls180.v:6485$2173_Y + connect \A $and$ls180.v:6658$2300_Y + connect \B $eq$ls180.v:6658$2301_Y + connect \Y $and$ls180.v:6658$2302_Y end - attribute \src "ls180.v:6487.40-6487.95" - cell $and $and$ls180.v:6487$2174 + attribute \src "ls180.v:6660.40-6660.95" + cell $and $and$ls180.v:6660$2303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246530,43 +263989,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6487$2174_Y + connect \Y $and$ls180.v:6660$2303_Y end - attribute \src "ls180.v:6487.39-6487.147" - cell $and $and$ls180.v:6487$2176 + attribute \src "ls180.v:6660.39-6660.147" + cell $and $and$ls180.v:6660$2305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6487$2174_Y - connect \B $eq$ls180.v:6487$2175_Y - connect \Y $and$ls180.v:6487$2176_Y + connect \A $and$ls180.v:6660$2303_Y + connect \B $eq$ls180.v:6660$2304_Y + connect \Y $and$ls180.v:6660$2305_Y end - attribute \src "ls180.v:6488.40-6488.98" - cell $and $and$ls180.v:6488$2178 + attribute \src "ls180.v:6661.40-6661.98" + cell $and $and$ls180.v:6661$2307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6488$2177_Y - connect \Y $and$ls180.v:6488$2178_Y + connect \B $not$ls180.v:6661$2306_Y + connect \Y $and$ls180.v:6661$2307_Y end - attribute \src "ls180.v:6488.39-6488.150" - cell $and $and$ls180.v:6488$2180 + attribute \src "ls180.v:6661.39-6661.150" + cell $and $and$ls180.v:6661$2309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6488$2178_Y - connect \B $eq$ls180.v:6488$2179_Y - connect \Y $and$ls180.v:6488$2180_Y + connect \A $and$ls180.v:6661$2307_Y + connect \B $eq$ls180.v:6661$2308_Y + connect \Y $and$ls180.v:6661$2309_Y end - attribute \src "ls180.v:6490.40-6490.95" - cell $and $and$ls180.v:6490$2181 + attribute \src "ls180.v:6663.40-6663.95" + cell $and $and$ls180.v:6663$2310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246574,43 +264033,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6490$2181_Y + connect \Y $and$ls180.v:6663$2310_Y end - attribute \src "ls180.v:6490.39-6490.147" - cell $and $and$ls180.v:6490$2183 + attribute \src "ls180.v:6663.39-6663.147" + cell $and $and$ls180.v:6663$2312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6490$2181_Y - connect \B $eq$ls180.v:6490$2182_Y - connect \Y $and$ls180.v:6490$2183_Y + connect \A $and$ls180.v:6663$2310_Y + connect \B $eq$ls180.v:6663$2311_Y + connect \Y $and$ls180.v:6663$2312_Y end - attribute \src "ls180.v:6491.40-6491.98" - cell $and $and$ls180.v:6491$2185 + attribute \src "ls180.v:6664.40-6664.98" + cell $and $and$ls180.v:6664$2314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6491$2184_Y - connect \Y $and$ls180.v:6491$2185_Y + connect \B $not$ls180.v:6664$2313_Y + connect \Y $and$ls180.v:6664$2314_Y end - attribute \src "ls180.v:6491.39-6491.150" - cell $and $and$ls180.v:6491$2187 + attribute \src "ls180.v:6664.39-6664.150" + cell $and $and$ls180.v:6664$2316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6491$2185_Y - connect \B $eq$ls180.v:6491$2186_Y - connect \Y $and$ls180.v:6491$2187_Y + connect \A $and$ls180.v:6664$2314_Y + connect \B $eq$ls180.v:6664$2315_Y + connect \Y $and$ls180.v:6664$2316_Y end - attribute \src "ls180.v:6493.52-6493.107" - cell $and $and$ls180.v:6493$2188 + attribute \src "ls180.v:6666.52-6666.107" + cell $and $and$ls180.v:6666$2317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246618,43 +264077,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6493$2188_Y + connect \Y $and$ls180.v:6666$2317_Y end - attribute \src "ls180.v:6493.51-6493.159" - cell $and $and$ls180.v:6493$2190 + attribute \src "ls180.v:6666.51-6666.159" + cell $and $and$ls180.v:6666$2319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6493$2188_Y - connect \B $eq$ls180.v:6493$2189_Y - connect \Y $and$ls180.v:6493$2190_Y + connect \A $and$ls180.v:6666$2317_Y + connect \B $eq$ls180.v:6666$2318_Y + connect \Y $and$ls180.v:6666$2319_Y end - attribute \src "ls180.v:6494.52-6494.110" - cell $and $and$ls180.v:6494$2192 + attribute \src "ls180.v:6667.52-6667.110" + cell $and $and$ls180.v:6667$2321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6494$2191_Y - connect \Y $and$ls180.v:6494$2192_Y + connect \B $not$ls180.v:6667$2320_Y + connect \Y $and$ls180.v:6667$2321_Y end - attribute \src "ls180.v:6494.51-6494.162" - cell $and $and$ls180.v:6494$2194 + attribute \src "ls180.v:6667.51-6667.162" + cell $and $and$ls180.v:6667$2323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6494$2192_Y - connect \B $eq$ls180.v:6494$2193_Y - connect \Y $and$ls180.v:6494$2194_Y + connect \A $and$ls180.v:6667$2321_Y + connect \B $eq$ls180.v:6667$2322_Y + connect \Y $and$ls180.v:6667$2323_Y end - attribute \src "ls180.v:6496.53-6496.108" - cell $and $and$ls180.v:6496$2195 + attribute \src "ls180.v:6669.53-6669.108" + cell $and $and$ls180.v:6669$2324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246662,43 +264121,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6496$2195_Y + connect \Y $and$ls180.v:6669$2324_Y end - attribute \src "ls180.v:6496.52-6496.160" - cell $and $and$ls180.v:6496$2197 + attribute \src "ls180.v:6669.52-6669.160" + cell $and $and$ls180.v:6669$2326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6496$2195_Y - connect \B $eq$ls180.v:6496$2196_Y - connect \Y $and$ls180.v:6496$2197_Y + connect \A $and$ls180.v:6669$2324_Y + connect \B $eq$ls180.v:6669$2325_Y + connect \Y $and$ls180.v:6669$2326_Y end - attribute \src "ls180.v:6497.53-6497.111" - cell $and $and$ls180.v:6497$2199 + attribute \src "ls180.v:6670.53-6670.111" + cell $and $and$ls180.v:6670$2328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6497$2198_Y - connect \Y $and$ls180.v:6497$2199_Y + connect \B $not$ls180.v:6670$2327_Y + connect \Y $and$ls180.v:6670$2328_Y end - attribute \src "ls180.v:6497.52-6497.163" - cell $and $and$ls180.v:6497$2201 + attribute \src "ls180.v:6670.52-6670.163" + cell $and $and$ls180.v:6670$2330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6497$2199_Y - connect \B $eq$ls180.v:6497$2200_Y - connect \Y $and$ls180.v:6497$2201_Y + connect \A $and$ls180.v:6670$2328_Y + connect \B $eq$ls180.v:6670$2329_Y + connect \Y $and$ls180.v:6670$2330_Y end - attribute \src "ls180.v:6499.44-6499.99" - cell $and $and$ls180.v:6499$2202 + attribute \src "ls180.v:6672.44-6672.99" + cell $and $and$ls180.v:6672$2331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246706,43 +264165,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6499$2202_Y + connect \Y $and$ls180.v:6672$2331_Y end - attribute \src "ls180.v:6499.43-6499.151" - cell $and $and$ls180.v:6499$2204 + attribute \src "ls180.v:6672.43-6672.151" + cell $and $and$ls180.v:6672$2333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6499$2202_Y - connect \B $eq$ls180.v:6499$2203_Y - connect \Y $and$ls180.v:6499$2204_Y + connect \A $and$ls180.v:6672$2331_Y + connect \B $eq$ls180.v:6672$2332_Y + connect \Y $and$ls180.v:6672$2333_Y end - attribute \src "ls180.v:6500.44-6500.102" - cell $and $and$ls180.v:6500$2206 + attribute \src "ls180.v:6673.44-6673.102" + cell $and $and$ls180.v:6673$2335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6500$2205_Y - connect \Y $and$ls180.v:6500$2206_Y + connect \B $not$ls180.v:6673$2334_Y + connect \Y $and$ls180.v:6673$2335_Y end - attribute \src "ls180.v:6500.43-6500.154" - cell $and $and$ls180.v:6500$2208 + attribute \src "ls180.v:6673.43-6673.154" + cell $and $and$ls180.v:6673$2337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6500$2206_Y - connect \B $eq$ls180.v:6500$2207_Y - connect \Y $and$ls180.v:6500$2208_Y + connect \A $and$ls180.v:6673$2335_Y + connect \B $eq$ls180.v:6673$2336_Y + connect \Y $and$ls180.v:6673$2337_Y end - attribute \src "ls180.v:6519.30-6519.85" - cell $and $and$ls180.v:6519$2210 + attribute \src "ls180.v:6692.30-6692.85" + cell $and $and$ls180.v:6692$2339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246750,43 +264209,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6519$2210_Y + connect \Y $and$ls180.v:6692$2339_Y end - attribute \src "ls180.v:6519.29-6519.136" - cell $and $and$ls180.v:6519$2212 + attribute \src "ls180.v:6692.29-6692.136" + cell $and $and$ls180.v:6692$2341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6519$2210_Y - connect \B $eq$ls180.v:6519$2211_Y - connect \Y $and$ls180.v:6519$2212_Y + connect \A $and$ls180.v:6692$2339_Y + connect \B $eq$ls180.v:6692$2340_Y + connect \Y $and$ls180.v:6692$2341_Y end - attribute \src "ls180.v:6520.30-6520.88" - cell $and $and$ls180.v:6520$2214 + attribute \src "ls180.v:6693.30-6693.88" + cell $and $and$ls180.v:6693$2343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6520$2213_Y - connect \Y $and$ls180.v:6520$2214_Y + connect \B $not$ls180.v:6693$2342_Y + connect \Y $and$ls180.v:6693$2343_Y end - attribute \src "ls180.v:6520.29-6520.139" - cell $and $and$ls180.v:6520$2216 + attribute \src "ls180.v:6693.29-6693.139" + cell $and $and$ls180.v:6693$2345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6520$2214_Y - connect \B $eq$ls180.v:6520$2215_Y - connect \Y $and$ls180.v:6520$2216_Y + connect \A $and$ls180.v:6693$2343_Y + connect \B $eq$ls180.v:6693$2344_Y + connect \Y $and$ls180.v:6693$2345_Y end - attribute \src "ls180.v:6522.40-6522.95" - cell $and $and$ls180.v:6522$2217 + attribute \src "ls180.v:6695.40-6695.95" + cell $and $and$ls180.v:6695$2346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246794,43 +264253,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6522$2217_Y + connect \Y $and$ls180.v:6695$2346_Y end - attribute \src "ls180.v:6522.39-6522.146" - cell $and $and$ls180.v:6522$2219 + attribute \src "ls180.v:6695.39-6695.146" + cell $and $and$ls180.v:6695$2348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6522$2217_Y - connect \B $eq$ls180.v:6522$2218_Y - connect \Y $and$ls180.v:6522$2219_Y + connect \A $and$ls180.v:6695$2346_Y + connect \B $eq$ls180.v:6695$2347_Y + connect \Y $and$ls180.v:6695$2348_Y end - attribute \src "ls180.v:6523.40-6523.98" - cell $and $and$ls180.v:6523$2221 + attribute \src "ls180.v:6696.40-6696.98" + cell $and $and$ls180.v:6696$2350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6523$2220_Y - connect \Y $and$ls180.v:6523$2221_Y + connect \B $not$ls180.v:6696$2349_Y + connect \Y $and$ls180.v:6696$2350_Y end - attribute \src "ls180.v:6523.39-6523.149" - cell $and $and$ls180.v:6523$2223 + attribute \src "ls180.v:6696.39-6696.149" + cell $and $and$ls180.v:6696$2352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6523$2221_Y - connect \B $eq$ls180.v:6523$2222_Y - connect \Y $and$ls180.v:6523$2223_Y + connect \A $and$ls180.v:6696$2350_Y + connect \B $eq$ls180.v:6696$2351_Y + connect \Y $and$ls180.v:6696$2352_Y end - attribute \src "ls180.v:6525.41-6525.96" - cell $and $and$ls180.v:6525$2224 + attribute \src "ls180.v:6698.41-6698.96" + cell $and $and$ls180.v:6698$2353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246838,43 +264297,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6525$2224_Y + connect \Y $and$ls180.v:6698$2353_Y end - attribute \src "ls180.v:6525.40-6525.147" - cell $and $and$ls180.v:6525$2226 + attribute \src "ls180.v:6698.40-6698.147" + cell $and $and$ls180.v:6698$2355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6525$2224_Y - connect \B $eq$ls180.v:6525$2225_Y - connect \Y $and$ls180.v:6525$2226_Y + connect \A $and$ls180.v:6698$2353_Y + connect \B $eq$ls180.v:6698$2354_Y + connect \Y $and$ls180.v:6698$2355_Y end - attribute \src "ls180.v:6526.41-6526.99" - cell $and $and$ls180.v:6526$2228 + attribute \src "ls180.v:6699.41-6699.99" + cell $and $and$ls180.v:6699$2357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6526$2227_Y - connect \Y $and$ls180.v:6526$2228_Y + connect \B $not$ls180.v:6699$2356_Y + connect \Y $and$ls180.v:6699$2357_Y end - attribute \src "ls180.v:6526.40-6526.150" - cell $and $and$ls180.v:6526$2230 + attribute \src "ls180.v:6699.40-6699.150" + cell $and $and$ls180.v:6699$2359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6526$2228_Y - connect \B $eq$ls180.v:6526$2229_Y - connect \Y $and$ls180.v:6526$2230_Y + connect \A $and$ls180.v:6699$2357_Y + connect \B $eq$ls180.v:6699$2358_Y + connect \Y $and$ls180.v:6699$2359_Y end - attribute \src "ls180.v:6528.45-6528.100" - cell $and $and$ls180.v:6528$2231 + attribute \src "ls180.v:6701.45-6701.100" + cell $and $and$ls180.v:6701$2360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246882,43 +264341,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6528$2231_Y + connect \Y $and$ls180.v:6701$2360_Y end - attribute \src "ls180.v:6528.44-6528.151" - cell $and $and$ls180.v:6528$2233 + attribute \src "ls180.v:6701.44-6701.151" + cell $and $and$ls180.v:6701$2362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6528$2231_Y - connect \B $eq$ls180.v:6528$2232_Y - connect \Y $and$ls180.v:6528$2233_Y + connect \A $and$ls180.v:6701$2360_Y + connect \B $eq$ls180.v:6701$2361_Y + connect \Y $and$ls180.v:6701$2362_Y end - attribute \src "ls180.v:6529.45-6529.103" - cell $and $and$ls180.v:6529$2235 + attribute \src "ls180.v:6702.45-6702.103" + cell $and $and$ls180.v:6702$2364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6529$2234_Y - connect \Y $and$ls180.v:6529$2235_Y + connect \B $not$ls180.v:6702$2363_Y + connect \Y $and$ls180.v:6702$2364_Y end - attribute \src "ls180.v:6529.44-6529.154" - cell $and $and$ls180.v:6529$2237 + attribute \src "ls180.v:6702.44-6702.154" + cell $and $and$ls180.v:6702$2366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6529$2235_Y - connect \B $eq$ls180.v:6529$2236_Y - connect \Y $and$ls180.v:6529$2237_Y + connect \A $and$ls180.v:6702$2364_Y + connect \B $eq$ls180.v:6702$2365_Y + connect \Y $and$ls180.v:6702$2366_Y end - attribute \src "ls180.v:6531.46-6531.101" - cell $and $and$ls180.v:6531$2238 + attribute \src "ls180.v:6704.46-6704.101" + cell $and $and$ls180.v:6704$2367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246926,43 +264385,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6531$2238_Y + connect \Y $and$ls180.v:6704$2367_Y end - attribute \src "ls180.v:6531.45-6531.152" - cell $and $and$ls180.v:6531$2240 + attribute \src "ls180.v:6704.45-6704.152" + cell $and $and$ls180.v:6704$2369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6531$2238_Y - connect \B $eq$ls180.v:6531$2239_Y - connect \Y $and$ls180.v:6531$2240_Y + connect \A $and$ls180.v:6704$2367_Y + connect \B $eq$ls180.v:6704$2368_Y + connect \Y $and$ls180.v:6704$2369_Y end - attribute \src "ls180.v:6532.46-6532.104" - cell $and $and$ls180.v:6532$2242 + attribute \src "ls180.v:6705.46-6705.104" + cell $and $and$ls180.v:6705$2371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6532$2241_Y - connect \Y $and$ls180.v:6532$2242_Y + connect \B $not$ls180.v:6705$2370_Y + connect \Y $and$ls180.v:6705$2371_Y end - attribute \src "ls180.v:6532.45-6532.155" - cell $and $and$ls180.v:6532$2244 + attribute \src "ls180.v:6705.45-6705.155" + cell $and $and$ls180.v:6705$2373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6532$2242_Y - connect \B $eq$ls180.v:6532$2243_Y - connect \Y $and$ls180.v:6532$2244_Y + connect \A $and$ls180.v:6705$2371_Y + connect \B $eq$ls180.v:6705$2372_Y + connect \Y $and$ls180.v:6705$2373_Y end - attribute \src "ls180.v:6534.44-6534.99" - cell $and $and$ls180.v:6534$2245 + attribute \src "ls180.v:6707.44-6707.99" + cell $and $and$ls180.v:6707$2374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246970,43 +264429,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6534$2245_Y + connect \Y $and$ls180.v:6707$2374_Y end - attribute \src "ls180.v:6534.43-6534.150" - cell $and $and$ls180.v:6534$2247 + attribute \src "ls180.v:6707.43-6707.150" + cell $and $and$ls180.v:6707$2376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6534$2245_Y - connect \B $eq$ls180.v:6534$2246_Y - connect \Y $and$ls180.v:6534$2247_Y + connect \A $and$ls180.v:6707$2374_Y + connect \B $eq$ls180.v:6707$2375_Y + connect \Y $and$ls180.v:6707$2376_Y end - attribute \src "ls180.v:6535.44-6535.102" - cell $and $and$ls180.v:6535$2249 + attribute \src "ls180.v:6708.44-6708.102" + cell $and $and$ls180.v:6708$2378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6535$2248_Y - connect \Y $and$ls180.v:6535$2249_Y + connect \B $not$ls180.v:6708$2377_Y + connect \Y $and$ls180.v:6708$2378_Y end - attribute \src "ls180.v:6535.43-6535.153" - cell $and $and$ls180.v:6535$2251 + attribute \src "ls180.v:6708.43-6708.153" + cell $and $and$ls180.v:6708$2380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6535$2249_Y - connect \B $eq$ls180.v:6535$2250_Y - connect \Y $and$ls180.v:6535$2251_Y + connect \A $and$ls180.v:6708$2378_Y + connect \B $eq$ls180.v:6708$2379_Y + connect \Y $and$ls180.v:6708$2380_Y end - attribute \src "ls180.v:6537.41-6537.96" - cell $and $and$ls180.v:6537$2252 + attribute \src "ls180.v:6710.41-6710.96" + cell $and $and$ls180.v:6710$2381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247014,43 +264473,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6537$2252_Y + connect \Y $and$ls180.v:6710$2381_Y end - attribute \src "ls180.v:6537.40-6537.147" - cell $and $and$ls180.v:6537$2254 + attribute \src "ls180.v:6710.40-6710.147" + cell $and $and$ls180.v:6710$2383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6537$2252_Y - connect \B $eq$ls180.v:6537$2253_Y - connect \Y $and$ls180.v:6537$2254_Y + connect \A $and$ls180.v:6710$2381_Y + connect \B $eq$ls180.v:6710$2382_Y + connect \Y $and$ls180.v:6710$2383_Y end - attribute \src "ls180.v:6538.41-6538.99" - cell $and $and$ls180.v:6538$2256 + attribute \src "ls180.v:6711.41-6711.99" + cell $and $and$ls180.v:6711$2385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6538$2255_Y - connect \Y $and$ls180.v:6538$2256_Y + connect \B $not$ls180.v:6711$2384_Y + connect \Y $and$ls180.v:6711$2385_Y end - attribute \src "ls180.v:6538.40-6538.150" - cell $and $and$ls180.v:6538$2258 + attribute \src "ls180.v:6711.40-6711.150" + cell $and $and$ls180.v:6711$2387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6538$2256_Y - connect \B $eq$ls180.v:6538$2257_Y - connect \Y $and$ls180.v:6538$2258_Y + connect \A $and$ls180.v:6711$2385_Y + connect \B $eq$ls180.v:6711$2386_Y + connect \Y $and$ls180.v:6711$2387_Y end - attribute \src "ls180.v:6540.40-6540.95" - cell $and $and$ls180.v:6540$2259 + attribute \src "ls180.v:6713.40-6713.95" + cell $and $and$ls180.v:6713$2388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247058,43 +264517,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6540$2259_Y + connect \Y $and$ls180.v:6713$2388_Y end - attribute \src "ls180.v:6540.39-6540.146" - cell $and $and$ls180.v:6540$2261 + attribute \src "ls180.v:6713.39-6713.146" + cell $and $and$ls180.v:6713$2390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6540$2259_Y - connect \B $eq$ls180.v:6540$2260_Y - connect \Y $and$ls180.v:6540$2261_Y + connect \A $and$ls180.v:6713$2388_Y + connect \B $eq$ls180.v:6713$2389_Y + connect \Y $and$ls180.v:6713$2390_Y end - attribute \src "ls180.v:6541.40-6541.98" - cell $and $and$ls180.v:6541$2263 + attribute \src "ls180.v:6714.40-6714.98" + cell $and $and$ls180.v:6714$2392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6541$2262_Y - connect \Y $and$ls180.v:6541$2263_Y + connect \B $not$ls180.v:6714$2391_Y + connect \Y $and$ls180.v:6714$2392_Y end - attribute \src "ls180.v:6541.39-6541.149" - cell $and $and$ls180.v:6541$2265 + attribute \src "ls180.v:6714.39-6714.149" + cell $and $and$ls180.v:6714$2394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6541$2263_Y - connect \B $eq$ls180.v:6541$2264_Y - connect \Y $and$ls180.v:6541$2265_Y + connect \A $and$ls180.v:6714$2392_Y + connect \B $eq$ls180.v:6714$2393_Y + connect \Y $and$ls180.v:6714$2394_Y end - attribute \src "ls180.v:6553.46-6553.101" - cell $and $and$ls180.v:6553$2267 + attribute \src "ls180.v:6726.46-6726.101" + cell $and $and$ls180.v:6726$2396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247102,43 +264561,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6553$2267_Y + connect \Y $and$ls180.v:6726$2396_Y end - attribute \src "ls180.v:6553.45-6553.152" - cell $and $and$ls180.v:6553$2269 + attribute \src "ls180.v:6726.45-6726.152" + cell $and $and$ls180.v:6726$2398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6553$2267_Y - connect \B $eq$ls180.v:6553$2268_Y - connect \Y $and$ls180.v:6553$2269_Y + connect \A $and$ls180.v:6726$2396_Y + connect \B $eq$ls180.v:6726$2397_Y + connect \Y $and$ls180.v:6726$2398_Y end - attribute \src "ls180.v:6554.46-6554.104" - cell $and $and$ls180.v:6554$2271 + attribute \src "ls180.v:6727.46-6727.104" + cell $and $and$ls180.v:6727$2400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6554$2270_Y - connect \Y $and$ls180.v:6554$2271_Y + connect \B $not$ls180.v:6727$2399_Y + connect \Y $and$ls180.v:6727$2400_Y end - attribute \src "ls180.v:6554.45-6554.155" - cell $and $and$ls180.v:6554$2273 + attribute \src "ls180.v:6727.45-6727.155" + cell $and $and$ls180.v:6727$2402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6554$2271_Y - connect \B $eq$ls180.v:6554$2272_Y - connect \Y $and$ls180.v:6554$2273_Y + connect \A $and$ls180.v:6727$2400_Y + connect \B $eq$ls180.v:6727$2401_Y + connect \Y $and$ls180.v:6727$2402_Y end - attribute \src "ls180.v:6556.46-6556.101" - cell $and $and$ls180.v:6556$2274 + attribute \src "ls180.v:6729.46-6729.101" + cell $and $and$ls180.v:6729$2403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247146,43 +264605,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6556$2274_Y + connect \Y $and$ls180.v:6729$2403_Y end - attribute \src "ls180.v:6556.45-6556.152" - cell $and $and$ls180.v:6556$2276 + attribute \src "ls180.v:6729.45-6729.152" + cell $and $and$ls180.v:6729$2405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6556$2274_Y - connect \B $eq$ls180.v:6556$2275_Y - connect \Y $and$ls180.v:6556$2276_Y + connect \A $and$ls180.v:6729$2403_Y + connect \B $eq$ls180.v:6729$2404_Y + connect \Y $and$ls180.v:6729$2405_Y end - attribute \src "ls180.v:6557.46-6557.104" - cell $and $and$ls180.v:6557$2278 + attribute \src "ls180.v:6730.46-6730.104" + cell $and $and$ls180.v:6730$2407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6557$2277_Y - connect \Y $and$ls180.v:6557$2278_Y + connect \B $not$ls180.v:6730$2406_Y + connect \Y $and$ls180.v:6730$2407_Y end - attribute \src "ls180.v:6557.45-6557.155" - cell $and $and$ls180.v:6557$2280 + attribute \src "ls180.v:6730.45-6730.155" + cell $and $and$ls180.v:6730$2409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6557$2278_Y - connect \B $eq$ls180.v:6557$2279_Y - connect \Y $and$ls180.v:6557$2280_Y + connect \A $and$ls180.v:6730$2407_Y + connect \B $eq$ls180.v:6730$2408_Y + connect \Y $and$ls180.v:6730$2409_Y end - attribute \src "ls180.v:6559.46-6559.101" - cell $and $and$ls180.v:6559$2281 + attribute \src "ls180.v:6732.46-6732.101" + cell $and $and$ls180.v:6732$2410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247190,43 +264649,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6559$2281_Y + connect \Y $and$ls180.v:6732$2410_Y end - attribute \src "ls180.v:6559.45-6559.152" - cell $and $and$ls180.v:6559$2283 + attribute \src "ls180.v:6732.45-6732.152" + cell $and $and$ls180.v:6732$2412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6559$2281_Y - connect \B $eq$ls180.v:6559$2282_Y - connect \Y $and$ls180.v:6559$2283_Y + connect \A $and$ls180.v:6732$2410_Y + connect \B $eq$ls180.v:6732$2411_Y + connect \Y $and$ls180.v:6732$2412_Y end - attribute \src "ls180.v:6560.46-6560.104" - cell $and $and$ls180.v:6560$2285 + attribute \src "ls180.v:6733.46-6733.104" + cell $and $and$ls180.v:6733$2414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6560$2284_Y - connect \Y $and$ls180.v:6560$2285_Y + connect \B $not$ls180.v:6733$2413_Y + connect \Y $and$ls180.v:6733$2414_Y end - attribute \src "ls180.v:6560.45-6560.155" - cell $and $and$ls180.v:6560$2287 + attribute \src "ls180.v:6733.45-6733.155" + cell $and $and$ls180.v:6733$2416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6560$2285_Y - connect \B $eq$ls180.v:6560$2286_Y - connect \Y $and$ls180.v:6560$2287_Y + connect \A $and$ls180.v:6733$2414_Y + connect \B $eq$ls180.v:6733$2415_Y + connect \Y $and$ls180.v:6733$2416_Y end - attribute \src "ls180.v:6562.46-6562.101" - cell $and $and$ls180.v:6562$2288 + attribute \src "ls180.v:6735.46-6735.101" + cell $and $and$ls180.v:6735$2417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247234,263 +264693,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6562$2288_Y + connect \Y $and$ls180.v:6735$2417_Y end - attribute \src "ls180.v:6562.45-6562.152" - cell $and $and$ls180.v:6562$2290 + attribute \src "ls180.v:6735.45-6735.152" + cell $and $and$ls180.v:6735$2419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6562$2288_Y - connect \B $eq$ls180.v:6562$2289_Y - connect \Y $and$ls180.v:6562$2290_Y + connect \A $and$ls180.v:6735$2417_Y + connect \B $eq$ls180.v:6735$2418_Y + connect \Y $and$ls180.v:6735$2419_Y end - attribute \src "ls180.v:6563.46-6563.104" - cell $and $and$ls180.v:6563$2292 + attribute \src "ls180.v:6736.46-6736.104" + cell $and $and$ls180.v:6736$2421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6563$2291_Y - connect \Y $and$ls180.v:6563$2292_Y + connect \B $not$ls180.v:6736$2420_Y + connect \Y $and$ls180.v:6736$2421_Y end - attribute \src "ls180.v:6563.45-6563.155" - cell $and $and$ls180.v:6563$2294 + attribute \src "ls180.v:6736.45-6736.155" + cell $and $and$ls180.v:6736$2423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6563$2292_Y - connect \B $eq$ls180.v:6563$2293_Y - connect \Y $and$ls180.v:6563$2294_Y + connect \A $and$ls180.v:6736$2421_Y + connect \B $eq$ls180.v:6736$2422_Y + connect \Y $and$ls180.v:6736$2423_Y end - attribute \src "ls180.v:6944.109-6944.178" - cell $and $and$ls180.v:6944$2332 + attribute \src "ls180.v:7117.109-7117.178" + cell $and $and$ls180.v:7117$2461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6944$2331_Y - connect \Y $and$ls180.v:6944$2332_Y + connect \B $eq$ls180.v:7117$2460_Y + connect \Y $and$ls180.v:7117$2461_Y end - attribute \src "ls180.v:6944.184-6944.253" - cell $and $and$ls180.v:6944$2335 + attribute \src "ls180.v:7117.184-7117.253" + cell $and $and$ls180.v:7117$2464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6944$2334_Y - connect \Y $and$ls180.v:6944$2335_Y + connect \B $eq$ls180.v:7117$2463_Y + connect \Y $and$ls180.v:7117$2464_Y end - attribute \src "ls180.v:6944.259-6944.328" - cell $and $and$ls180.v:6944$2338 + attribute \src "ls180.v:7117.259-7117.328" + cell $and $and$ls180.v:7117$2467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6944$2337_Y - connect \Y $and$ls180.v:6944$2338_Y + connect \B $eq$ls180.v:7117$2466_Y + connect \Y $and$ls180.v:7117$2467_Y end - attribute \src "ls180.v:6944.40-6944.331" - cell $and $and$ls180.v:6944$2341 + attribute \src "ls180.v:7117.40-7117.331" + cell $and $and$ls180.v:7117$2470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6944$2330_Y - connect \B $not$ls180.v:6944$2340_Y - connect \Y $and$ls180.v:6944$2341_Y + connect \A $eq$ls180.v:7117$2459_Y + connect \B $not$ls180.v:7117$2469_Y + connect \Y $and$ls180.v:7117$2470_Y end - attribute \src "ls180.v:6944.39-6944.354" - cell $and $and$ls180.v:6944$2342 + attribute \src "ls180.v:7117.39-7117.354" + cell $and $and$ls180.v:7117$2471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6944$2341_Y + connect \A $and$ls180.v:7117$2470_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6944$2342_Y + connect \Y $and$ls180.v:7117$2471_Y end - attribute \src "ls180.v:6968.109-6968.178" - cell $and $and$ls180.v:6968$2348 + attribute \src "ls180.v:7141.109-7141.178" + cell $and $and$ls180.v:7141$2477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6968$2347_Y - connect \Y $and$ls180.v:6968$2348_Y + connect \B $eq$ls180.v:7141$2476_Y + connect \Y $and$ls180.v:7141$2477_Y end - attribute \src "ls180.v:6968.184-6968.253" - cell $and $and$ls180.v:6968$2351 + attribute \src "ls180.v:7141.184-7141.253" + cell $and $and$ls180.v:7141$2480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6968$2350_Y - connect \Y $and$ls180.v:6968$2351_Y + connect \B $eq$ls180.v:7141$2479_Y + connect \Y $and$ls180.v:7141$2480_Y end - attribute \src "ls180.v:6968.259-6968.328" - cell $and $and$ls180.v:6968$2354 + attribute \src "ls180.v:7141.259-7141.328" + cell $and $and$ls180.v:7141$2483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6968$2353_Y - connect \Y $and$ls180.v:6968$2354_Y + connect \B $eq$ls180.v:7141$2482_Y + connect \Y $and$ls180.v:7141$2483_Y end - attribute \src "ls180.v:6968.40-6968.331" - cell $and $and$ls180.v:6968$2357 + attribute \src "ls180.v:7141.40-7141.331" + cell $and $and$ls180.v:7141$2486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6968$2346_Y - connect \B $not$ls180.v:6968$2356_Y - connect \Y $and$ls180.v:6968$2357_Y + connect \A $eq$ls180.v:7141$2475_Y + connect \B $not$ls180.v:7141$2485_Y + connect \Y $and$ls180.v:7141$2486_Y end - attribute \src "ls180.v:6968.39-6968.354" - cell $and $and$ls180.v:6968$2358 + attribute \src "ls180.v:7141.39-7141.354" + cell $and $and$ls180.v:7141$2487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6968$2357_Y + connect \A $and$ls180.v:7141$2486_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6968$2358_Y + connect \Y $and$ls180.v:7141$2487_Y end - attribute \src "ls180.v:6992.109-6992.178" - cell $and $and$ls180.v:6992$2364 + attribute \src "ls180.v:7165.109-7165.178" + cell $and $and$ls180.v:7165$2493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6992$2363_Y - connect \Y $and$ls180.v:6992$2364_Y + connect \B $eq$ls180.v:7165$2492_Y + connect \Y $and$ls180.v:7165$2493_Y end - attribute \src "ls180.v:6992.184-6992.253" - cell $and $and$ls180.v:6992$2367 + attribute \src "ls180.v:7165.184-7165.253" + cell $and $and$ls180.v:7165$2496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6992$2366_Y - connect \Y $and$ls180.v:6992$2367_Y + connect \B $eq$ls180.v:7165$2495_Y + connect \Y $and$ls180.v:7165$2496_Y end - attribute \src "ls180.v:6992.259-6992.328" - cell $and $and$ls180.v:6992$2370 + attribute \src "ls180.v:7165.259-7165.328" + cell $and $and$ls180.v:7165$2499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6992$2369_Y - connect \Y $and$ls180.v:6992$2370_Y + connect \B $eq$ls180.v:7165$2498_Y + connect \Y $and$ls180.v:7165$2499_Y end - attribute \src "ls180.v:6992.40-6992.331" - cell $and $and$ls180.v:6992$2373 + attribute \src "ls180.v:7165.40-7165.331" + cell $and $and$ls180.v:7165$2502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6992$2362_Y - connect \B $not$ls180.v:6992$2372_Y - connect \Y $and$ls180.v:6992$2373_Y + connect \A $eq$ls180.v:7165$2491_Y + connect \B $not$ls180.v:7165$2501_Y + connect \Y $and$ls180.v:7165$2502_Y end - attribute \src "ls180.v:6992.39-6992.354" - cell $and $and$ls180.v:6992$2374 + attribute \src "ls180.v:7165.39-7165.354" + cell $and $and$ls180.v:7165$2503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6992$2373_Y + connect \A $and$ls180.v:7165$2502_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6992$2374_Y + connect \Y $and$ls180.v:7165$2503_Y end - attribute \src "ls180.v:7016.109-7016.178" - cell $and $and$ls180.v:7016$2380 + attribute \src "ls180.v:7189.109-7189.178" + cell $and $and$ls180.v:7189$2509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7016$2379_Y - connect \Y $and$ls180.v:7016$2380_Y + connect \B $eq$ls180.v:7189$2508_Y + connect \Y $and$ls180.v:7189$2509_Y end - attribute \src "ls180.v:7016.184-7016.253" - cell $and $and$ls180.v:7016$2383 + attribute \src "ls180.v:7189.184-7189.253" + cell $and $and$ls180.v:7189$2512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7016$2382_Y - connect \Y $and$ls180.v:7016$2383_Y + connect \B $eq$ls180.v:7189$2511_Y + connect \Y $and$ls180.v:7189$2512_Y end - attribute \src "ls180.v:7016.259-7016.328" - cell $and $and$ls180.v:7016$2386 + attribute \src "ls180.v:7189.259-7189.328" + cell $and $and$ls180.v:7189$2515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7016$2385_Y - connect \Y $and$ls180.v:7016$2386_Y + connect \B $eq$ls180.v:7189$2514_Y + connect \Y $and$ls180.v:7189$2515_Y end - attribute \src "ls180.v:7016.40-7016.331" - cell $and $and$ls180.v:7016$2389 + attribute \src "ls180.v:7189.40-7189.331" + cell $and $and$ls180.v:7189$2518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7016$2378_Y - connect \B $not$ls180.v:7016$2388_Y - connect \Y $and$ls180.v:7016$2389_Y + connect \A $eq$ls180.v:7189$2507_Y + connect \B $not$ls180.v:7189$2517_Y + connect \Y $and$ls180.v:7189$2518_Y end - attribute \src "ls180.v:7016.39-7016.354" - cell $and $and$ls180.v:7016$2390 + attribute \src "ls180.v:7189.39-7189.354" + cell $and $and$ls180.v:7189$2519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7016$2389_Y + connect \A $and$ls180.v:7189$2518_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7016$2390_Y + connect \Y $and$ls180.v:7189$2519_Y end - attribute \src "ls180.v:7221.39-7221.104" - cell $and $and$ls180.v:7221$2402 + attribute \src "ls180.v:7394.39-7394.104" + cell $and $and$ls180.v:7394$2531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247498,21 +264957,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7221$2402_Y + connect \Y $and$ls180.v:7394$2531_Y end - attribute \src "ls180.v:7221.38-7221.145" - cell $and $and$ls180.v:7221$2403 + attribute \src "ls180.v:7394.38-7394.145" + cell $and $and$ls180.v:7394$2532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7221$2402_Y + connect \A $and$ls180.v:7394$2531_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7221$2403_Y + connect \Y $and$ls180.v:7394$2532_Y end - attribute \src "ls180.v:7224.39-7224.104" - cell $and $and$ls180.v:7224$2404 + attribute \src "ls180.v:7397.39-7397.104" + cell $and $and$ls180.v:7397$2533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247520,21 +264979,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7224$2404_Y + connect \Y $and$ls180.v:7397$2533_Y end - attribute \src "ls180.v:7224.38-7224.145" - cell $and $and$ls180.v:7224$2405 + attribute \src "ls180.v:7397.38-7397.145" + cell $and $and$ls180.v:7397$2534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7224$2404_Y + connect \A $and$ls180.v:7397$2533_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7224$2405_Y + connect \Y $and$ls180.v:7397$2534_Y end - attribute \src "ls180.v:7227.39-7227.82" - cell $and $and$ls180.v:7227$2406 + attribute \src "ls180.v:7400.39-7400.82" + cell $and $and$ls180.v:7400$2535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247542,21 +265001,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7227$2406_Y + connect \Y $and$ls180.v:7400$2535_Y end - attribute \src "ls180.v:7227.38-7227.112" - cell $and $and$ls180.v:7227$2407 + attribute \src "ls180.v:7400.38-7400.112" + cell $and $and$ls180.v:7400$2536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7227$2406_Y + connect \A $and$ls180.v:7400$2535_Y connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7227$2407_Y + connect \Y $and$ls180.v:7400$2536_Y end - attribute \src "ls180.v:7238.39-7238.104" - cell $and $and$ls180.v:7238$2409 + attribute \src "ls180.v:7411.39-7411.104" + cell $and $and$ls180.v:7411$2538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247564,21 +265023,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7238$2409_Y + connect \Y $and$ls180.v:7411$2538_Y end - attribute \src "ls180.v:7238.38-7238.145" - cell $and $and$ls180.v:7238$2410 + attribute \src "ls180.v:7411.38-7411.145" + cell $and $and$ls180.v:7411$2539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7238$2409_Y + connect \A $and$ls180.v:7411$2538_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7238$2410_Y + connect \Y $and$ls180.v:7411$2539_Y end - attribute \src "ls180.v:7241.39-7241.104" - cell $and $and$ls180.v:7241$2411 + attribute \src "ls180.v:7414.39-7414.104" + cell $and $and$ls180.v:7414$2540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247586,21 +265045,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7241$2411_Y + connect \Y $and$ls180.v:7414$2540_Y end - attribute \src "ls180.v:7241.38-7241.145" - cell $and $and$ls180.v:7241$2412 + attribute \src "ls180.v:7414.38-7414.145" + cell $and $and$ls180.v:7414$2541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7241$2411_Y + connect \A $and$ls180.v:7414$2540_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7241$2412_Y + connect \Y $and$ls180.v:7414$2541_Y end - attribute \src "ls180.v:7244.39-7244.82" - cell $and $and$ls180.v:7244$2413 + attribute \src "ls180.v:7417.39-7417.82" + cell $and $and$ls180.v:7417$2542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247608,21 +265067,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7244$2413_Y + connect \Y $and$ls180.v:7417$2542_Y end - attribute \src "ls180.v:7244.38-7244.112" - cell $and $and$ls180.v:7244$2414 + attribute \src "ls180.v:7417.38-7417.112" + cell $and $and$ls180.v:7417$2543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7244$2413_Y + connect \A $and$ls180.v:7417$2542_Y connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7244$2414_Y + connect \Y $and$ls180.v:7417$2543_Y end - attribute \src "ls180.v:7255.39-7255.104" - cell $and $and$ls180.v:7255$2416 + attribute \src "ls180.v:7428.39-7428.104" + cell $and $and$ls180.v:7428$2545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247630,21 +265089,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7255$2416_Y + connect \Y $and$ls180.v:7428$2545_Y end - attribute \src "ls180.v:7255.38-7255.144" - cell $and $and$ls180.v:7255$2417 + attribute \src "ls180.v:7428.38-7428.144" + cell $and $and$ls180.v:7428$2546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7255$2416_Y + connect \A $and$ls180.v:7428$2545_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7255$2417_Y + connect \Y $and$ls180.v:7428$2546_Y end - attribute \src "ls180.v:7258.39-7258.104" - cell $and $and$ls180.v:7258$2418 + attribute \src "ls180.v:7431.39-7431.104" + cell $and $and$ls180.v:7431$2547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247652,21 +265111,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7258$2418_Y + connect \Y $and$ls180.v:7431$2547_Y end - attribute \src "ls180.v:7258.38-7258.144" - cell $and $and$ls180.v:7258$2419 + attribute \src "ls180.v:7431.38-7431.144" + cell $and $and$ls180.v:7431$2548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7258$2418_Y + connect \A $and$ls180.v:7431$2547_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7258$2419_Y + connect \Y $and$ls180.v:7431$2548_Y end - attribute \src "ls180.v:7261.39-7261.82" - cell $and $and$ls180.v:7261$2420 + attribute \src "ls180.v:7434.39-7434.82" + cell $and $and$ls180.v:7434$2549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247674,21 +265133,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7261$2420_Y + connect \Y $and$ls180.v:7434$2549_Y end - attribute \src "ls180.v:7261.38-7261.111" - cell $and $and$ls180.v:7261$2421 + attribute \src "ls180.v:7434.38-7434.111" + cell $and $and$ls180.v:7434$2550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7261$2420_Y + connect \A $and$ls180.v:7434$2549_Y connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7261$2421_Y + connect \Y $and$ls180.v:7434$2550_Y end - attribute \src "ls180.v:7272.39-7272.104" - cell $and $and$ls180.v:7272$2423 + attribute \src "ls180.v:7445.39-7445.104" + cell $and $and$ls180.v:7445$2552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247696,21 +265155,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7272$2423_Y + connect \Y $and$ls180.v:7445$2552_Y end - attribute \src "ls180.v:7272.38-7272.149" - cell $and $and$ls180.v:7272$2424 + attribute \src "ls180.v:7445.38-7445.149" + cell $and $and$ls180.v:7445$2553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7272$2423_Y + connect \A $and$ls180.v:7445$2552_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7272$2424_Y + connect \Y $and$ls180.v:7445$2553_Y end - attribute \src "ls180.v:7275.39-7275.104" - cell $and $and$ls180.v:7275$2425 + attribute \src "ls180.v:7448.39-7448.104" + cell $and $and$ls180.v:7448$2554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247718,21 +265177,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7275$2425_Y + connect \Y $and$ls180.v:7448$2554_Y end - attribute \src "ls180.v:7275.38-7275.149" - cell $and $and$ls180.v:7275$2426 + attribute \src "ls180.v:7448.38-7448.149" + cell $and $and$ls180.v:7448$2555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7275$2425_Y + connect \A $and$ls180.v:7448$2554_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7275$2426_Y + connect \Y $and$ls180.v:7448$2555_Y end - attribute \src "ls180.v:7278.39-7278.82" - cell $and $and$ls180.v:7278$2427 + attribute \src "ls180.v:7451.39-7451.82" + cell $and $and$ls180.v:7451$2556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247740,21 +265199,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7278$2427_Y + connect \Y $and$ls180.v:7451$2556_Y end - attribute \src "ls180.v:7278.38-7278.116" - cell $and $and$ls180.v:7278$2428 + attribute \src "ls180.v:7451.38-7451.116" + cell $and $and$ls180.v:7451$2557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7278$2427_Y + connect \A $and$ls180.v:7451$2556_Y connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7278$2428_Y + connect \Y $and$ls180.v:7451$2557_Y end - attribute \src "ls180.v:7289.39-7289.104" - cell $and $and$ls180.v:7289$2430 + attribute \src "ls180.v:7462.39-7462.104" + cell $and $and$ls180.v:7462$2559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247762,21 +265221,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7289$2430_Y + connect \Y $and$ls180.v:7462$2559_Y end - attribute \src "ls180.v:7289.38-7289.150" - cell $and $and$ls180.v:7289$2431 + attribute \src "ls180.v:7462.38-7462.150" + cell $and $and$ls180.v:7462$2560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7289$2430_Y + connect \A $and$ls180.v:7462$2559_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7289$2431_Y + connect \Y $and$ls180.v:7462$2560_Y end - attribute \src "ls180.v:7292.39-7292.104" - cell $and $and$ls180.v:7292$2432 + attribute \src "ls180.v:7465.39-7465.104" + cell $and $and$ls180.v:7465$2561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247784,21 +265243,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7292$2432_Y + connect \Y $and$ls180.v:7465$2561_Y end - attribute \src "ls180.v:7292.38-7292.150" - cell $and $and$ls180.v:7292$2433 + attribute \src "ls180.v:7465.38-7465.150" + cell $and $and$ls180.v:7465$2562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7292$2432_Y + connect \A $and$ls180.v:7465$2561_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7292$2433_Y + connect \Y $and$ls180.v:7465$2562_Y end - attribute \src "ls180.v:7295.39-7295.82" - cell $and $and$ls180.v:7295$2434 + attribute \src "ls180.v:7468.39-7468.82" + cell $and $and$ls180.v:7468$2563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247806,32 +265265,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7295$2434_Y + connect \Y $and$ls180.v:7468$2563_Y end - attribute \src "ls180.v:7295.38-7295.117" - cell $and $and$ls180.v:7295$2435 + attribute \src "ls180.v:7468.38-7468.117" + cell $and $and$ls180.v:7468$2564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7295$2434_Y + connect \A $and$ls180.v:7468$2563_Y connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7295$2435_Y + connect \Y $and$ls180.v:7468$2564_Y end - attribute \src "ls180.v:7514.17-7514.67" - cell $and $and$ls180.v:7514$2442 + attribute \src "ls180.v:7690.17-7690.67" + cell $and $and$ls180.v:7690$2572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7514$2441_Y + connect \A $not$ls180.v:7690$2571_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7514$2442_Y + connect \Y $and$ls180.v:7690$2572_Y end - attribute \src "ls180.v:7593.8-7593.67" - cell $and $and$ls180.v:7593$2473 + attribute \src "ls180.v:7769.8-7769.67" + cell $and $and$ls180.v:7769$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247839,32 +265298,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7593$2473_Y + connect \Y $and$ls180.v:7769$2603_Y end - attribute \src "ls180.v:7593.7-7593.102" - cell $and $and$ls180.v:7593$2475 + attribute \src "ls180.v:7769.7-7769.102" + cell $and $and$ls180.v:7769$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7593$2473_Y - connect \B $not$ls180.v:7593$2474_Y - connect \Y $and$ls180.v:7593$2475_Y + connect \A $and$ls180.v:7769$2603_Y + connect \B $not$ls180.v:7769$2604_Y + connect \Y $and$ls180.v:7769$2605_Y end - attribute \src "ls180.v:7612.7-7612.75" - cell $and $and$ls180.v:7612$2479 + attribute \src "ls180.v:7788.7-7788.75" + cell $and $and$ls180.v:7788$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7612$2478_Y + connect \A $not$ls180.v:7788$2608_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7612$2479_Y + connect \Y $and$ls180.v:7788$2609_Y end - attribute \src "ls180.v:7616.8-7616.65" - cell $and $and$ls180.v:7616$2480 + attribute \src "ls180.v:7792.8-7792.65" + cell $and $and$ls180.v:7792$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247872,21 +265331,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:7616$2480_Y + connect \Y $and$ls180.v:7792$2610_Y end - attribute \src "ls180.v:7616.7-7616.99" - cell $and $and$ls180.v:7616$2482 + attribute \src "ls180.v:7792.7-7792.99" + cell $and $and$ls180.v:7792$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7616$2480_Y - connect \B $not$ls180.v:7616$2481_Y - connect \Y $and$ls180.v:7616$2482_Y + connect \A $and$ls180.v:7792$2610_Y + connect \B $not$ls180.v:7792$2611_Y + connect \Y $and$ls180.v:7792$2612_Y end - attribute \src "ls180.v:7620.8-7620.65" - cell $and $and$ls180.v:7620$2483 + attribute \src "ls180.v:7796.8-7796.65" + cell $and $and$ls180.v:7796$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247894,21 +265353,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:7620$2483_Y + connect \Y $and$ls180.v:7796$2613_Y end - attribute \src "ls180.v:7620.7-7620.99" - cell $and $and$ls180.v:7620$2485 + attribute \src "ls180.v:7796.7-7796.99" + cell $and $and$ls180.v:7796$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7620$2483_Y - connect \B $not$ls180.v:7620$2484_Y - connect \Y $and$ls180.v:7620$2485_Y + connect \A $and$ls180.v:7796$2613_Y + connect \B $not$ls180.v:7796$2614_Y + connect \Y $and$ls180.v:7796$2615_Y end - attribute \src "ls180.v:7624.8-7624.65" - cell $and $and$ls180.v:7624$2486 + attribute \src "ls180.v:7800.8-7800.65" + cell $and $and$ls180.v:7800$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247916,43 +265375,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:7624$2486_Y + connect \Y $and$ls180.v:7800$2616_Y + end + attribute \src "ls180.v:7800.7-7800.99" + cell $and $and$ls180.v:7800$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7800$2616_Y + connect \B $not$ls180.v:7800$2617_Y + connect \Y $and$ls180.v:7800$2618_Y end - attribute \src "ls180.v:7624.7-7624.99" - cell $and $and$ls180.v:7624$2488 + attribute \src "ls180.v:7804.8-7804.65" + cell $and $and$ls180.v:7804$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7624$2486_Y - connect \B $not$ls180.v:7624$2487_Y - connect \Y $and$ls180.v:7624$2488_Y + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:7804$2619_Y end - attribute \src "ls180.v:7632.7-7632.56" - cell $and $and$ls180.v:7632$2490 + attribute \src "ls180.v:7804.7-7804.99" + cell $and $and$ls180.v:7804$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7804$2619_Y + connect \B $not$ls180.v:7804$2620_Y + connect \Y $and$ls180.v:7804$2621_Y + end + attribute \src "ls180.v:7812.7-7812.56" + cell $and $and$ls180.v:7812$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7632$2489_Y - connect \Y $and$ls180.v:7632$2490_Y + connect \B $not$ls180.v:7812$2622_Y + connect \Y $and$ls180.v:7812$2623_Y end - attribute \src "ls180.v:7660.7-7660.75" - cell $and $and$ls180.v:7660$2497 + attribute \src "ls180.v:7840.7-7840.75" + cell $and $and$ls180.v:7840$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7660$2496_Y - connect \Y $and$ls180.v:7660$2497_Y + connect \B $eq$ls180.v:7840$2629_Y + connect \Y $and$ls180.v:7840$2630_Y end - attribute \src "ls180.v:7702.8-7702.131" - cell $and $and$ls180.v:7702$2503 + attribute \src "ls180.v:7882.8-7882.131" + cell $and $and$ls180.v:7882$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247960,21 +265441,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7702$2503_Y + connect \Y $and$ls180.v:7882$2636_Y end - attribute \src "ls180.v:7702.7-7702.190" - cell $and $and$ls180.v:7702$2505 + attribute \src "ls180.v:7882.7-7882.190" + cell $and $and$ls180.v:7882$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7702$2503_Y - connect \B $not$ls180.v:7702$2504_Y - connect \Y $and$ls180.v:7702$2505_Y + connect \A $and$ls180.v:7882$2636_Y + connect \B $not$ls180.v:7882$2637_Y + connect \Y $and$ls180.v:7882$2638_Y end - attribute \src "ls180.v:7708.8-7708.131" - cell $and $and$ls180.v:7708$2508 + attribute \src "ls180.v:7888.8-7888.131" + cell $and $and$ls180.v:7888$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247982,21 +265463,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7708$2508_Y + connect \Y $and$ls180.v:7888$2641_Y end - attribute \src "ls180.v:7708.7-7708.190" - cell $and $and$ls180.v:7708$2510 + attribute \src "ls180.v:7888.7-7888.190" + cell $and $and$ls180.v:7888$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7708$2508_Y - connect \B $not$ls180.v:7708$2509_Y - connect \Y $and$ls180.v:7708$2510_Y + connect \A $and$ls180.v:7888$2641_Y + connect \B $not$ls180.v:7888$2642_Y + connect \Y $and$ls180.v:7888$2643_Y end - attribute \src "ls180.v:7748.8-7748.131" - cell $and $and$ls180.v:7748$2519 + attribute \src "ls180.v:7928.8-7928.131" + cell $and $and$ls180.v:7928$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248004,21 +265485,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7748$2519_Y + connect \Y $and$ls180.v:7928$2652_Y end - attribute \src "ls180.v:7748.7-7748.190" - cell $and $and$ls180.v:7748$2521 + attribute \src "ls180.v:7928.7-7928.190" + cell $and $and$ls180.v:7928$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7748$2519_Y - connect \B $not$ls180.v:7748$2520_Y - connect \Y $and$ls180.v:7748$2521_Y + connect \A $and$ls180.v:7928$2652_Y + connect \B $not$ls180.v:7928$2653_Y + connect \Y $and$ls180.v:7928$2654_Y end - attribute \src "ls180.v:7754.8-7754.131" - cell $and $and$ls180.v:7754$2524 + attribute \src "ls180.v:7934.8-7934.131" + cell $and $and$ls180.v:7934$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248026,21 +265507,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7754$2524_Y + connect \Y $and$ls180.v:7934$2657_Y end - attribute \src "ls180.v:7754.7-7754.190" - cell $and $and$ls180.v:7754$2526 + attribute \src "ls180.v:7934.7-7934.190" + cell $and $and$ls180.v:7934$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7754$2524_Y - connect \B $not$ls180.v:7754$2525_Y - connect \Y $and$ls180.v:7754$2526_Y + connect \A $and$ls180.v:7934$2657_Y + connect \B $not$ls180.v:7934$2658_Y + connect \Y $and$ls180.v:7934$2659_Y end - attribute \src "ls180.v:7794.8-7794.131" - cell $and $and$ls180.v:7794$2535 + attribute \src "ls180.v:7974.8-7974.131" + cell $and $and$ls180.v:7974$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248048,21 +265529,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7794$2535_Y + connect \Y $and$ls180.v:7974$2668_Y end - attribute \src "ls180.v:7794.7-7794.190" - cell $and $and$ls180.v:7794$2537 + attribute \src "ls180.v:7974.7-7974.190" + cell $and $and$ls180.v:7974$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7794$2535_Y - connect \B $not$ls180.v:7794$2536_Y - connect \Y $and$ls180.v:7794$2537_Y + connect \A $and$ls180.v:7974$2668_Y + connect \B $not$ls180.v:7974$2669_Y + connect \Y $and$ls180.v:7974$2670_Y end - attribute \src "ls180.v:7800.8-7800.131" - cell $and $and$ls180.v:7800$2540 + attribute \src "ls180.v:7980.8-7980.131" + cell $and $and$ls180.v:7980$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248070,21 +265551,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7800$2540_Y + connect \Y $and$ls180.v:7980$2673_Y end - attribute \src "ls180.v:7800.7-7800.190" - cell $and $and$ls180.v:7800$2542 + attribute \src "ls180.v:7980.7-7980.190" + cell $and $and$ls180.v:7980$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7800$2540_Y - connect \B $not$ls180.v:7800$2541_Y - connect \Y $and$ls180.v:7800$2542_Y + connect \A $and$ls180.v:7980$2673_Y + connect \B $not$ls180.v:7980$2674_Y + connect \Y $and$ls180.v:7980$2675_Y end - attribute \src "ls180.v:7840.8-7840.131" - cell $and $and$ls180.v:7840$2551 + attribute \src "ls180.v:8020.8-8020.131" + cell $and $and$ls180.v:8020$2684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248092,21 +265573,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7840$2551_Y + connect \Y $and$ls180.v:8020$2684_Y end - attribute \src "ls180.v:7840.7-7840.190" - cell $and $and$ls180.v:7840$2553 + attribute \src "ls180.v:8020.7-8020.190" + cell $and $and$ls180.v:8020$2686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7840$2551_Y - connect \B $not$ls180.v:7840$2552_Y - connect \Y $and$ls180.v:7840$2553_Y + connect \A $and$ls180.v:8020$2684_Y + connect \B $not$ls180.v:8020$2685_Y + connect \Y $and$ls180.v:8020$2686_Y end - attribute \src "ls180.v:7846.8-7846.131" - cell $and $and$ls180.v:7846$2556 + attribute \src "ls180.v:8026.8-8026.131" + cell $and $and$ls180.v:8026$2689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248114,109 +265595,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7846$2556_Y + connect \Y $and$ls180.v:8026$2689_Y end - attribute \src "ls180.v:7846.7-7846.190" - cell $and $and$ls180.v:7846$2558 + attribute \src "ls180.v:8026.7-8026.190" + cell $and $and$ls180.v:8026$2691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7846$2556_Y - connect \B $not$ls180.v:7846$2557_Y - connect \Y $and$ls180.v:7846$2558_Y + connect \A $and$ls180.v:8026$2689_Y + connect \B $not$ls180.v:8026$2690_Y + connect \Y $and$ls180.v:8026$2691_Y end - attribute \src "ls180.v:8043.48-8043.124" - cell $and $and$ls180.v:8043$2583 + attribute \src "ls180.v:8223.48-8223.124" + cell $and $and$ls180.v:8223$2716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8043$2582_Y + connect \A $eq$ls180.v:8223$2715_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8043$2583_Y + connect \Y $and$ls180.v:8223$2716_Y end - attribute \src "ls180.v:8043.130-8043.206" - cell $and $and$ls180.v:8043$2586 + attribute \src "ls180.v:8223.130-8223.206" + cell $and $and$ls180.v:8223$2719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8043$2585_Y + connect \A $eq$ls180.v:8223$2718_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8043$2586_Y + connect \Y $and$ls180.v:8223$2719_Y end - attribute \src "ls180.v:8043.212-8043.288" - cell $and $and$ls180.v:8043$2589 + attribute \src "ls180.v:8223.212-8223.288" + cell $and $and$ls180.v:8223$2722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8043$2588_Y + connect \A $eq$ls180.v:8223$2721_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8043$2589_Y + connect \Y $and$ls180.v:8223$2722_Y end - attribute \src "ls180.v:8043.294-8043.370" - cell $and $and$ls180.v:8043$2592 + attribute \src "ls180.v:8223.294-8223.370" + cell $and $and$ls180.v:8223$2725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8043$2591_Y + connect \A $eq$ls180.v:8223$2724_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8043$2592_Y + connect \Y $and$ls180.v:8223$2725_Y end - attribute \src "ls180.v:8044.49-8044.125" - cell $and $and$ls180.v:8044$2595 + attribute \src "ls180.v:8224.49-8224.125" + cell $and $and$ls180.v:8224$2728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8044$2594_Y + connect \A $eq$ls180.v:8224$2727_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8044$2595_Y + connect \Y $and$ls180.v:8224$2728_Y end - attribute \src "ls180.v:8044.131-8044.207" - cell $and $and$ls180.v:8044$2598 + attribute \src "ls180.v:8224.131-8224.207" + cell $and $and$ls180.v:8224$2731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8044$2597_Y + connect \A $eq$ls180.v:8224$2730_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8044$2598_Y + connect \Y $and$ls180.v:8224$2731_Y end - attribute \src "ls180.v:8044.213-8044.289" - cell $and $and$ls180.v:8044$2601 + attribute \src "ls180.v:8224.213-8224.289" + cell $and $and$ls180.v:8224$2734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8044$2600_Y + connect \A $eq$ls180.v:8224$2733_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8044$2601_Y + connect \Y $and$ls180.v:8224$2734_Y end - attribute \src "ls180.v:8044.295-8044.371" - cell $and $and$ls180.v:8044$2604 + attribute \src "ls180.v:8224.295-8224.371" + cell $and $and$ls180.v:8224$2737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8044$2603_Y + connect \A $eq$ls180.v:8224$2736_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8044$2604_Y + connect \Y $and$ls180.v:8224$2737_Y end - attribute \src "ls180.v:8063.8-8063.49" - cell $and $and$ls180.v:8063$2607 + attribute \src "ls180.v:8243.8-8243.49" + cell $and $and$ls180.v:8243$2740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248224,10 +265705,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8063$2607_Y + connect \Y $and$ls180.v:8243$2740_Y end - attribute \src "ls180.v:8066.8-8066.53" - cell $and $and$ls180.v:8066$2608 + attribute \src "ls180.v:8246.8-8246.53" + cell $and $and$ls180.v:8246$2741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248235,32 +265716,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8066$2608_Y + connect \Y $and$ls180.v:8246$2741_Y end - attribute \src "ls180.v:8071.8-8071.59" - cell $and $and$ls180.v:8071$2610 + attribute \src "ls180.v:8251.8-8251.59" + cell $and $and$ls180.v:8251$2743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8071$2609_Y - connect \Y $and$ls180.v:8071$2610_Y + connect \B $not$ls180.v:8251$2742_Y + connect \Y $and$ls180.v:8251$2743_Y end - attribute \src "ls180.v:8071.7-8071.90" - cell $and $and$ls180.v:8071$2612 + attribute \src "ls180.v:8251.7-8251.90" + cell $and $and$ls180.v:8251$2745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8071$2610_Y - connect \B $not$ls180.v:8071$2611_Y - connect \Y $and$ls180.v:8071$2612_Y + connect \A $and$ls180.v:8251$2743_Y + connect \B $not$ls180.v:8251$2744_Y + connect \Y $and$ls180.v:8251$2745_Y end - attribute \src "ls180.v:8077.8-8077.59" - cell $and $and$ls180.v:8077$2613 + attribute \src "ls180.v:8257.8-8257.59" + cell $and $and$ls180.v:8257$2746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248268,43 +265749,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_uart_clk_txen connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8077$2613_Y + connect \Y $and$ls180.v:8257$2746_Y end - attribute \src "ls180.v:8101.8-8101.48" - cell $and $and$ls180.v:8101$2620 + attribute \src "ls180.v:8281.8-8281.48" + cell $and $and$ls180.v:8281$2753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8101$2619_Y + connect \A $not$ls180.v:8281$2752_Y connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8101$2620_Y + connect \Y $and$ls180.v:8281$2753_Y end - attribute \src "ls180.v:8134.7-8134.57" - cell $and $and$ls180.v:8134$2626 + attribute \src "ls180.v:8314.7-8314.57" + cell $and $and$ls180.v:8314$2759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8134$2625_Y + connect \A $not$ls180.v:8314$2758_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8134$2626_Y + connect \Y $and$ls180.v:8314$2759_Y end - attribute \src "ls180.v:8141.7-8141.57" - cell $and $and$ls180.v:8141$2628 + attribute \src "ls180.v:8321.7-8321.57" + cell $and $and$ls180.v:8321$2761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8141$2627_Y + connect \A $not$ls180.v:8321$2760_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8141$2628_Y + connect \Y $and$ls180.v:8321$2761_Y end - attribute \src "ls180.v:8151.8-8151.75" - cell $and $and$ls180.v:8151$2629 + attribute \src "ls180.v:8331.8-8331.75" + cell $and $and$ls180.v:8331$2762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248312,21 +265793,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8151$2629_Y + connect \Y $and$ls180.v:8331$2762_Y end - attribute \src "ls180.v:8151.7-8151.107" - cell $and $and$ls180.v:8151$2631 + attribute \src "ls180.v:8331.7-8331.107" + cell $and $and$ls180.v:8331$2764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8151$2629_Y - connect \B $not$ls180.v:8151$2630_Y - connect \Y $and$ls180.v:8151$2631_Y + connect \A $and$ls180.v:8331$2762_Y + connect \B $not$ls180.v:8331$2763_Y + connect \Y $and$ls180.v:8331$2764_Y end - attribute \src "ls180.v:8157.8-8157.75" - cell $and $and$ls180.v:8157$2634 + attribute \src "ls180.v:8337.8-8337.75" + cell $and $and$ls180.v:8337$2767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248334,21 +265815,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8157$2634_Y + connect \Y $and$ls180.v:8337$2767_Y end - attribute \src "ls180.v:8157.7-8157.107" - cell $and $and$ls180.v:8157$2636 + attribute \src "ls180.v:8337.7-8337.107" + cell $and $and$ls180.v:8337$2769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8157$2634_Y - connect \B $not$ls180.v:8157$2635_Y - connect \Y $and$ls180.v:8157$2636_Y + connect \A $and$ls180.v:8337$2767_Y + connect \B $not$ls180.v:8337$2768_Y + connect \Y $and$ls180.v:8337$2769_Y end - attribute \src "ls180.v:8173.8-8173.75" - cell $and $and$ls180.v:8173$2640 + attribute \src "ls180.v:8353.8-8353.75" + cell $and $and$ls180.v:8353$2773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248356,21 +265837,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8173$2640_Y + connect \Y $and$ls180.v:8353$2773_Y end - attribute \src "ls180.v:8173.7-8173.107" - cell $and $and$ls180.v:8173$2642 + attribute \src "ls180.v:8353.7-8353.107" + cell $and $and$ls180.v:8353$2775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8173$2640_Y - connect \B $not$ls180.v:8173$2641_Y - connect \Y $and$ls180.v:8173$2642_Y + connect \A $and$ls180.v:8353$2773_Y + connect \B $not$ls180.v:8353$2774_Y + connect \Y $and$ls180.v:8353$2775_Y end - attribute \src "ls180.v:8179.8-8179.75" - cell $and $and$ls180.v:8179$2645 + attribute \src "ls180.v:8359.8-8359.75" + cell $and $and$ls180.v:8359$2778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248378,21 +265859,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8179$2645_Y + connect \Y $and$ls180.v:8359$2778_Y end - attribute \src "ls180.v:8179.7-8179.107" - cell $and $and$ls180.v:8179$2647 + attribute \src "ls180.v:8359.7-8359.107" + cell $and $and$ls180.v:8359$2780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8179$2645_Y - connect \B $not$ls180.v:8179$2646_Y - connect \Y $and$ls180.v:8179$2647_Y + connect \A $and$ls180.v:8359$2778_Y + connect \B $not$ls180.v:8359$2779_Y + connect \Y $and$ls180.v:8359$2780_Y end - attribute \src "ls180.v:8327.7-8327.96" - cell $and $and$ls180.v:8327$2675 + attribute \src "ls180.v:8507.7-8507.96" + cell $and $and$ls180.v:8507$2808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248400,10 +265881,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8327$2675_Y + connect \Y $and$ls180.v:8507$2808_Y end - attribute \src "ls180.v:8328.8-8328.93" - cell $and $and$ls180.v:8328$2676 + attribute \src "ls180.v:8508.8-8508.93" + cell $and $and$ls180.v:8508$2809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248411,10 +265892,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8328$2676_Y + connect \Y $and$ls180.v:8508$2809_Y end - attribute \src "ls180.v:8336.8-8336.93" - cell $and $and$ls180.v:8336$2677 + attribute \src "ls180.v:8516.8-8516.93" + cell $and $and$ls180.v:8516$2810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248422,10 +265903,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8336$2677_Y + connect \Y $and$ls180.v:8516$2810_Y end - attribute \src "ls180.v:8408.7-8408.98" - cell $and $and$ls180.v:8408$2687 + attribute \src "ls180.v:8588.7-8588.98" + cell $and $and$ls180.v:8588$2820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248433,10 +265914,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8408$2687_Y + connect \Y $and$ls180.v:8588$2820_Y end - attribute \src "ls180.v:8409.8-8409.95" - cell $and $and$ls180.v:8409$2688 + attribute \src "ls180.v:8589.8-8589.95" + cell $and $and$ls180.v:8589$2821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248444,10 +265925,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8409$2688_Y + connect \Y $and$ls180.v:8589$2821_Y end - attribute \src "ls180.v:8417.8-8417.95" - cell $and $and$ls180.v:8417$2689 + attribute \src "ls180.v:8597.8-8597.95" + cell $and $and$ls180.v:8597$2822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248455,10 +265936,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8417$2689_Y + connect \Y $and$ls180.v:8597$2822_Y end - attribute \src "ls180.v:8487.7-8487.100" - cell $and $and$ls180.v:8487$2699 + attribute \src "ls180.v:8667.7-8667.100" + cell $and $and$ls180.v:8667$2832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248466,10 +265947,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8487$2699_Y + connect \Y $and$ls180.v:8667$2832_Y end - attribute \src "ls180.v:8488.8-8488.97" - cell $and $and$ls180.v:8488$2700 + attribute \src "ls180.v:8668.8-8668.97" + cell $and $and$ls180.v:8668$2833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248477,10 +265958,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8488$2700_Y + connect \Y $and$ls180.v:8668$2833_Y end - attribute \src "ls180.v:8496.8-8496.97" - cell $and $and$ls180.v:8496$2701 + attribute \src "ls180.v:8676.8-8676.97" + cell $and $and$ls180.v:8676$2834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248488,10 +265969,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8496$2701_Y + connect \Y $and$ls180.v:8676$2834_Y end - attribute \src "ls180.v:8587.7-8587.82" - cell $and $and$ls180.v:8587$2707 + attribute \src "ls180.v:8767.7-8767.82" + cell $and $and$ls180.v:8767$2840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248499,10 +265980,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8587$2707_Y + connect \Y $and$ls180.v:8767$2840_Y end - attribute \src "ls180.v:8590.7-8590.82" - cell $and $and$ls180.v:8590$2708 + attribute \src "ls180.v:8770.7-8770.82" + cell $and $and$ls180.v:8770$2841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248510,10 +265991,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8590$2708_Y + connect \Y $and$ls180.v:8770$2841_Y end - attribute \src "ls180.v:8593.7-8593.82" - cell $and $and$ls180.v:8593$2709 + attribute \src "ls180.v:8773.7-8773.82" + cell $and $and$ls180.v:8773$2842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248521,10 +266002,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8593$2709_Y + connect \Y $and$ls180.v:8773$2842_Y end - attribute \src "ls180.v:8596.7-8596.82" - cell $and $and$ls180.v:8596$2710 + attribute \src "ls180.v:8776.7-8776.82" + cell $and $and$ls180.v:8776$2843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248532,10 +266013,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8596$2710_Y + connect \Y $and$ls180.v:8776$2843_Y end - attribute \src "ls180.v:8599.7-8599.82" - cell $and $and$ls180.v:8599$2711 + attribute \src "ls180.v:8779.7-8779.82" + cell $and $and$ls180.v:8779$2844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248543,10 +266024,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8599$2711_Y + connect \Y $and$ls180.v:8779$2844_Y end - attribute \src "ls180.v:8604.7-8604.82" - cell $and $and$ls180.v:8604$2712 + attribute \src "ls180.v:8784.7-8784.82" + cell $and $and$ls180.v:8784$2845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248554,10 +266035,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8604$2712_Y + connect \Y $and$ls180.v:8784$2845_Y end - attribute \src "ls180.v:8609.7-8609.82" - cell $and $and$ls180.v:8609$2713 + attribute \src "ls180.v:8789.7-8789.82" + cell $and $and$ls180.v:8789$2846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248565,10 +266046,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8609$2713_Y + connect \Y $and$ls180.v:8789$2846_Y end - attribute \src "ls180.v:8614.7-8614.82" - cell $and $and$ls180.v:8614$2714 + attribute \src "ls180.v:8794.7-8794.82" + cell $and $and$ls180.v:8794$2847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248576,10 +266057,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8614$2714_Y + connect \Y $and$ls180.v:8794$2847_Y end - attribute \src "ls180.v:8619.7-8619.82" - cell $and $and$ls180.v:8619$2715 + attribute \src "ls180.v:8799.7-8799.82" + cell $and $and$ls180.v:8799$2848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248587,10 +266068,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8619$2715_Y + connect \Y $and$ls180.v:8799$2848_Y end - attribute \src "ls180.v:8684.8-8684.83" - cell $and $and$ls180.v:8684$2718 + attribute \src "ls180.v:8864.8-8864.83" + cell $and $and$ls180.v:8864$2851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248598,21 +266079,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8684$2718_Y + connect \Y $and$ls180.v:8864$2851_Y end - attribute \src "ls180.v:8684.7-8684.119" - cell $and $and$ls180.v:8684$2720 + attribute \src "ls180.v:8864.7-8864.119" + cell $and $and$ls180.v:8864$2853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8684$2718_Y - connect \B $not$ls180.v:8684$2719_Y - connect \Y $and$ls180.v:8684$2720_Y + connect \A $and$ls180.v:8864$2851_Y + connect \B $not$ls180.v:8864$2852_Y + connect \Y $and$ls180.v:8864$2853_Y end - attribute \src "ls180.v:8690.8-8690.83" - cell $and $and$ls180.v:8690$2723 + attribute \src "ls180.v:8870.8-8870.83" + cell $and $and$ls180.v:8870$2856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248620,21 +266101,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8690$2723_Y + connect \Y $and$ls180.v:8870$2856_Y end - attribute \src "ls180.v:8690.7-8690.119" - cell $and $and$ls180.v:8690$2725 + attribute \src "ls180.v:8870.7-8870.119" + cell $and $and$ls180.v:8870$2858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8690$2723_Y - connect \B $not$ls180.v:8690$2724_Y - connect \Y $and$ls180.v:8690$2725_Y + connect \A $and$ls180.v:8870$2856_Y + connect \B $not$ls180.v:8870$2857_Y + connect \Y $and$ls180.v:8870$2858_Y end - attribute \src "ls180.v:8710.7-8710.88" - cell $and $and$ls180.v:8710$2732 + attribute \src "ls180.v:8890.7-8890.88" + cell $and $and$ls180.v:8890$2865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248642,10 +266123,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8710$2732_Y + connect \Y $and$ls180.v:8890$2865_Y end - attribute \src "ls180.v:8711.8-8711.85" - cell $and $and$ls180.v:8711$2733 + attribute \src "ls180.v:8891.8-8891.85" + cell $and $and$ls180.v:8891$2866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248653,10 +266134,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8711$2733_Y + connect \Y $and$ls180.v:8891$2866_Y end - attribute \src "ls180.v:8719.8-8719.85" - cell $and $and$ls180.v:8719$2734 + attribute \src "ls180.v:8899.8-8899.85" + cell $and $and$ls180.v:8899$2867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248664,10 +266145,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8719$2734_Y + connect \Y $and$ls180.v:8899$2867_Y end - attribute \src "ls180.v:8763.7-8763.88" - cell $and $and$ls180.v:8763$2738 + attribute \src "ls180.v:8955.7-8955.88" + cell $and $and$ls180.v:8955$2871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248675,10 +266156,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8763$2738_Y + connect \Y $and$ls180.v:8955$2871_Y end - attribute \src "ls180.v:8770.8-8770.83" - cell $and $and$ls180.v:8770$2740 + attribute \src "ls180.v:8962.8-8962.83" + cell $and $and$ls180.v:8962$2873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248686,21 +266167,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8770$2740_Y + connect \Y $and$ls180.v:8962$2873_Y end - attribute \src "ls180.v:8770.7-8770.119" - cell $and $and$ls180.v:8770$2742 + attribute \src "ls180.v:8962.7-8962.119" + cell $and $and$ls180.v:8962$2875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8770$2740_Y - connect \B $not$ls180.v:8770$2741_Y - connect \Y $and$ls180.v:8770$2742_Y + connect \A $and$ls180.v:8962$2873_Y + connect \B $not$ls180.v:8962$2874_Y + connect \Y $and$ls180.v:8962$2875_Y end - attribute \src "ls180.v:8776.8-8776.83" - cell $and $and$ls180.v:8776$2745 + attribute \src "ls180.v:8968.8-8968.83" + cell $and $and$ls180.v:8968$2878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248708,87 +266189,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8776$2745_Y + connect \Y $and$ls180.v:8968$2878_Y end - attribute \src "ls180.v:8776.7-8776.119" - cell $and $and$ls180.v:8776$2747 + attribute \src "ls180.v:8968.7-8968.119" + cell $and $and$ls180.v:8968$2880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8776$2745_Y - connect \B $not$ls180.v:8776$2746_Y - connect \Y $and$ls180.v:8776$2747_Y + connect \A $and$ls180.v:8968$2878_Y + connect \B $not$ls180.v:8968$2879_Y + connect \Y $and$ls180.v:8968$2880_Y end - attribute \src "ls180.v:2855.42-2855.101" - cell $eq $eq$ls180.v:2855$30 + attribute \src "ls180.v:2930.30-2930.76" + cell $eq $eq$ls180.v:2930$54 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_sel + connect \A \main_libresocsim_libresoc_xics_icp_sel connect \B 1'0 - connect \Y $eq$ls180.v:2855$30_Y + connect \Y $eq$ls180.v:2930$54_Y end - attribute \src "ls180.v:2862.11-2862.54" - cell $eq $eq$ls180.v:2862$35 + attribute \src "ls180.v:2937.11-2937.42" + cell $eq $eq$ls180.v:2937$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter + connect \A \main_converter0_counter connect \B 1'1 - connect \Y $eq$ls180.v:2862$35_Y + connect \Y $eq$ls180.v:2937$59_Y end - attribute \src "ls180.v:2915.42-2915.101" - cell $eq $eq$ls180.v:2915$41 + attribute \src "ls180.v:2990.30-2990.76" + cell $eq $eq$ls180.v:2990$65 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_sel + connect \A \main_libresocsim_libresoc_xics_ics_sel connect \B 1'0 - connect \Y $eq$ls180.v:2915$41_Y + connect \Y $eq$ls180.v:2990$65_Y end - attribute \src "ls180.v:2922.11-2922.54" - cell $eq $eq$ls180.v:2922$46 + attribute \src "ls180.v:2997.11-2997.42" + cell $eq $eq$ls180.v:2997$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter + connect \A \main_converter1_counter connect \B 1'1 - connect \Y $eq$ls180.v:2922$46_Y + connect \Y $eq$ls180.v:2997$70_Y end - attribute \src "ls180.v:2975.42-2975.101" - cell $eq $eq$ls180.v:2975$52 + attribute \src "ls180.v:3050.33-3050.58" + cell $eq $eq$ls180.v:3050$76 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_sel + connect \A \main_wb_sdram_sel connect \B 1'0 - connect \Y $eq$ls180.v:2975$52_Y + connect \Y $eq$ls180.v:3050$76_Y end - attribute \src "ls180.v:2982.11-2982.54" - cell $eq $eq$ls180.v:2982$57 + attribute \src "ls180.v:3057.11-3057.45" + cell $eq $eq$ls180.v:3057$81 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter + connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $eq$ls180.v:2982$57_Y + connect \Y $eq$ls180.v:3057$81_Y end - attribute \src "ls180.v:3198.34-3198.65" - cell $eq $eq$ls180.v:3198$124 + attribute \src "ls180.v:3303.34-3303.65" + cell $eq $eq$ls180.v:3303$221 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -248796,10 +266277,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_count1 connect \B 1'0 - connect \Y $eq$ls180.v:3198$124_Y + connect \Y $eq$ls180.v:3303$221_Y end - attribute \src "ls180.v:3202.68-3202.102" - cell $eq $eq$ls180.v:3202$127 + attribute \src "ls180.v:3307.68-3307.102" + cell $eq $eq$ls180.v:3307$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248807,10 +266288,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $eq$ls180.v:3202$127_Y + connect \Y $eq$ls180.v:3307$224_Y end - attribute \src "ls180.v:3246.43-3246.134" - cell $eq $eq$ls180.v:3246$132 + attribute \src "ls180.v:3351.43-3351.134" + cell $eq $eq$ls180.v:3351$229 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248818,10 +266299,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3246$132_Y + connect \Y $eq$ls180.v:3351$229_Y end - attribute \src "ls180.v:3263.47-3263.88" - cell $eq $eq$ls180.v:3263$145 + attribute \src "ls180.v:3368.47-3368.88" + cell $eq $eq$ls180.v:3368$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248829,10 +266310,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3263$145_Y + connect \Y $eq$ls180.v:3368$242_Y end - attribute \src "ls180.v:3403.43-3403.134" - cell $eq $eq$ls180.v:3403$162 + attribute \src "ls180.v:3508.43-3508.134" + cell $eq $eq$ls180.v:3508$259 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248840,10 +266321,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3403$162_Y + connect \Y $eq$ls180.v:3508$259_Y end - attribute \src "ls180.v:3420.47-3420.88" - cell $eq $eq$ls180.v:3420$175 + attribute \src "ls180.v:3525.47-3525.88" + cell $eq $eq$ls180.v:3525$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248851,10 +266332,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3420$175_Y + connect \Y $eq$ls180.v:3525$272_Y end - attribute \src "ls180.v:3560.43-3560.134" - cell $eq $eq$ls180.v:3560$192 + attribute \src "ls180.v:3665.43-3665.134" + cell $eq $eq$ls180.v:3665$289 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248862,10 +266343,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3560$192_Y + connect \Y $eq$ls180.v:3665$289_Y end - attribute \src "ls180.v:3577.47-3577.88" - cell $eq $eq$ls180.v:3577$205 + attribute \src "ls180.v:3682.47-3682.88" + cell $eq $eq$ls180.v:3682$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248873,10 +266354,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3577$205_Y + connect \Y $eq$ls180.v:3682$302_Y end - attribute \src "ls180.v:3717.43-3717.134" - cell $eq $eq$ls180.v:3717$222 + attribute \src "ls180.v:3822.43-3822.134" + cell $eq $eq$ls180.v:3822$319 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248884,10 +266365,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3717$222_Y + connect \Y $eq$ls180.v:3822$319_Y end - attribute \src "ls180.v:3734.47-3734.88" - cell $eq $eq$ls180.v:3734$235 + attribute \src "ls180.v:3839.47-3839.88" + cell $eq $eq$ls180.v:3839$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248895,10 +266376,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3734$235_Y + connect \Y $eq$ls180.v:3839$332_Y end - attribute \src "ls180.v:3871.32-3871.56" - cell $eq $eq$ls180.v:3871$282 + attribute \src "ls180.v:3976.32-3976.56" + cell $eq $eq$ls180.v:3976$379 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -248906,10 +266387,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time0 connect \B 1'0 - connect \Y $eq$ls180.v:3871$282_Y + connect \Y $eq$ls180.v:3976$379_Y end - attribute \src "ls180.v:3872.32-3872.56" - cell $eq $eq$ls180.v:3872$283 + attribute \src "ls180.v:3977.32-3977.56" + cell $eq $eq$ls180.v:3977$380 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248917,10 +266398,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time1 connect \B 1'0 - connect \Y $eq$ls180.v:3872$283_Y + connect \Y $eq$ls180.v:3977$380_Y end - attribute \src "ls180.v:3883.339-3883.418" - cell $eq $eq$ls180.v:3883$297 + attribute \src "ls180.v:3988.339-3988.418" + cell $eq $eq$ls180.v:3988$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248928,10 +266409,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3883$297_Y + connect \Y $eq$ls180.v:3988$394_Y end - attribute \src "ls180.v:3883.423-3883.504" - cell $eq $eq$ls180.v:3883$298 + attribute \src "ls180.v:3988.423-3988.504" + cell $eq $eq$ls180.v:3988$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248939,10 +266420,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3883$298_Y + connect \Y $eq$ls180.v:3988$395_Y end - attribute \src "ls180.v:3884.339-3884.418" - cell $eq $eq$ls180.v:3884$310 + attribute \src "ls180.v:3989.339-3989.418" + cell $eq $eq$ls180.v:3989$407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248950,10 +266431,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3884$310_Y + connect \Y $eq$ls180.v:3989$407_Y end - attribute \src "ls180.v:3884.423-3884.504" - cell $eq $eq$ls180.v:3884$311 + attribute \src "ls180.v:3989.423-3989.504" + cell $eq $eq$ls180.v:3989$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248961,10 +266442,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3884$311_Y + connect \Y $eq$ls180.v:3989$408_Y end - attribute \src "ls180.v:3885.339-3885.418" - cell $eq $eq$ls180.v:3885$323 + attribute \src "ls180.v:3990.339-3990.418" + cell $eq $eq$ls180.v:3990$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248972,10 +266453,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3885$323_Y + connect \Y $eq$ls180.v:3990$420_Y end - attribute \src "ls180.v:3885.423-3885.504" - cell $eq $eq$ls180.v:3885$324 + attribute \src "ls180.v:3990.423-3990.504" + cell $eq $eq$ls180.v:3990$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248983,10 +266464,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3885$324_Y + connect \Y $eq$ls180.v:3990$421_Y end - attribute \src "ls180.v:3886.339-3886.418" - cell $eq $eq$ls180.v:3886$336 + attribute \src "ls180.v:3991.339-3991.418" + cell $eq $eq$ls180.v:3991$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248994,10 +266475,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3886$336_Y + connect \Y $eq$ls180.v:3991$433_Y end - attribute \src "ls180.v:3886.423-3886.504" - cell $eq $eq$ls180.v:3886$337 + attribute \src "ls180.v:3991.423-3991.504" + cell $eq $eq$ls180.v:3991$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249005,10 +266486,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3886$337_Y + connect \Y $eq$ls180.v:3991$434_Y end - attribute \src "ls180.v:3916.339-3916.418" - cell $eq $eq$ls180.v:3916$355 + attribute \src "ls180.v:4021.339-4021.418" + cell $eq $eq$ls180.v:4021$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249016,10 +266497,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3916$355_Y + connect \Y $eq$ls180.v:4021$452_Y end - attribute \src "ls180.v:3916.423-3916.504" - cell $eq $eq$ls180.v:3916$356 + attribute \src "ls180.v:4021.423-4021.504" + cell $eq $eq$ls180.v:4021$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249027,10 +266508,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3916$356_Y + connect \Y $eq$ls180.v:4021$453_Y end - attribute \src "ls180.v:3917.339-3917.418" - cell $eq $eq$ls180.v:3917$368 + attribute \src "ls180.v:4022.339-4022.418" + cell $eq $eq$ls180.v:4022$465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249038,10 +266519,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3917$368_Y + connect \Y $eq$ls180.v:4022$465_Y end - attribute \src "ls180.v:3917.423-3917.504" - cell $eq $eq$ls180.v:3917$369 + attribute \src "ls180.v:4022.423-4022.504" + cell $eq $eq$ls180.v:4022$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249049,10 +266530,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3917$369_Y + connect \Y $eq$ls180.v:4022$466_Y end - attribute \src "ls180.v:3918.339-3918.418" - cell $eq $eq$ls180.v:3918$381 + attribute \src "ls180.v:4023.339-4023.418" + cell $eq $eq$ls180.v:4023$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249060,10 +266541,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3918$381_Y + connect \Y $eq$ls180.v:4023$478_Y end - attribute \src "ls180.v:3918.423-3918.504" - cell $eq $eq$ls180.v:3918$382 + attribute \src "ls180.v:4023.423-4023.504" + cell $eq $eq$ls180.v:4023$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249071,10 +266552,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3918$382_Y + connect \Y $eq$ls180.v:4023$479_Y end - attribute \src "ls180.v:3919.339-3919.418" - cell $eq $eq$ls180.v:3919$394 + attribute \src "ls180.v:4024.339-4024.418" + cell $eq $eq$ls180.v:4024$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249082,10 +266563,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3919$394_Y + connect \Y $eq$ls180.v:4024$491_Y end - attribute \src "ls180.v:3919.423-3919.504" - cell $eq $eq$ls180.v:3919$395 + attribute \src "ls180.v:4024.423-4024.504" + cell $eq $eq$ls180.v:4024$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249093,10 +266574,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3919$395_Y + connect \Y $eq$ls180.v:4024$492_Y end - attribute \src "ls180.v:3948.78-3948.113" - cell $eq $eq$ls180.v:3948$404 + attribute \src "ls180.v:4053.78-4053.113" + cell $eq $eq$ls180.v:4053$501 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249104,10 +266585,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'0 - connect \Y $eq$ls180.v:3948$404_Y + connect \Y $eq$ls180.v:4053$501_Y end - attribute \src "ls180.v:3951.78-3951.113" - cell $eq $eq$ls180.v:3951$407 + attribute \src "ls180.v:4056.78-4056.113" + cell $eq $eq$ls180.v:4056$504 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249115,10 +266596,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'0 - connect \Y $eq$ls180.v:3951$407_Y + connect \Y $eq$ls180.v:4056$504_Y end - attribute \src "ls180.v:3957.78-3957.113" - cell $eq $eq$ls180.v:3957$411 + attribute \src "ls180.v:4062.78-4062.113" + cell $eq $eq$ls180.v:4062$508 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249126,10 +266607,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'1 - connect \Y $eq$ls180.v:3957$411_Y + connect \Y $eq$ls180.v:4062$508_Y end - attribute \src "ls180.v:3960.78-3960.113" - cell $eq $eq$ls180.v:3960$414 + attribute \src "ls180.v:4065.78-4065.113" + cell $eq $eq$ls180.v:4065$511 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249137,10 +266618,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'1 - connect \Y $eq$ls180.v:3960$414_Y + connect \Y $eq$ls180.v:4065$511_Y end - attribute \src "ls180.v:3966.78-3966.113" - cell $eq $eq$ls180.v:3966$418 + attribute \src "ls180.v:4071.78-4071.113" + cell $eq $eq$ls180.v:4071$515 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249148,10 +266629,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'10 - connect \Y $eq$ls180.v:3966$418_Y + connect \Y $eq$ls180.v:4071$515_Y end - attribute \src "ls180.v:3969.78-3969.113" - cell $eq $eq$ls180.v:3969$421 + attribute \src "ls180.v:4074.78-4074.113" + cell $eq $eq$ls180.v:4074$518 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249159,10 +266640,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'10 - connect \Y $eq$ls180.v:3969$421_Y + connect \Y $eq$ls180.v:4074$518_Y end - attribute \src "ls180.v:3975.78-3975.113" - cell $eq $eq$ls180.v:3975$425 + attribute \src "ls180.v:4080.78-4080.113" + cell $eq $eq$ls180.v:4080$522 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249170,10 +266651,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'11 - connect \Y $eq$ls180.v:3975$425_Y + connect \Y $eq$ls180.v:4080$522_Y end - attribute \src "ls180.v:3978.78-3978.113" - cell $eq $eq$ls180.v:3978$428 + attribute \src "ls180.v:4083.78-4083.113" + cell $eq $eq$ls180.v:4083$525 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249181,10 +266662,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'11 - connect \Y $eq$ls180.v:3978$428_Y + connect \Y $eq$ls180.v:4083$525_Y end - attribute \src "ls180.v:4059.42-4059.82" - cell $eq $eq$ls180.v:4059$451 + attribute \src "ls180.v:4164.42-4164.82" + cell $eq $eq$ls180.v:4164$548 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249192,10 +266673,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4059$451_Y + connect \Y $eq$ls180.v:4164$548_Y end - attribute \src "ls180.v:4059.145-4059.178" - cell $eq $eq$ls180.v:4059$452 + attribute \src "ls180.v:4164.145-4164.178" + cell $eq $eq$ls180.v:4164$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249203,10 +266684,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4059$452_Y + connect \Y $eq$ls180.v:4164$549_Y end - attribute \src "ls180.v:4059.220-4059.253" - cell $eq $eq$ls180.v:4059$455 + attribute \src "ls180.v:4164.220-4164.253" + cell $eq $eq$ls180.v:4164$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249214,10 +266695,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4059$455_Y + connect \Y $eq$ls180.v:4164$552_Y end - attribute \src "ls180.v:4059.295-4059.328" - cell $eq $eq$ls180.v:4059$458 + attribute \src "ls180.v:4164.295-4164.328" + cell $eq $eq$ls180.v:4164$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249225,10 +266706,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4059$458_Y + connect \Y $eq$ls180.v:4164$555_Y end - attribute \src "ls180.v:4064.42-4064.82" - cell $eq $eq$ls180.v:4064$467 + attribute \src "ls180.v:4169.42-4169.82" + cell $eq $eq$ls180.v:4169$564 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249236,10 +266717,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4064$467_Y + connect \Y $eq$ls180.v:4169$564_Y end - attribute \src "ls180.v:4064.145-4064.178" - cell $eq $eq$ls180.v:4064$468 + attribute \src "ls180.v:4169.145-4169.178" + cell $eq $eq$ls180.v:4169$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249247,10 +266728,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4064$468_Y + connect \Y $eq$ls180.v:4169$565_Y end - attribute \src "ls180.v:4064.220-4064.253" - cell $eq $eq$ls180.v:4064$471 + attribute \src "ls180.v:4169.220-4169.253" + cell $eq $eq$ls180.v:4169$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249258,10 +266739,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4064$471_Y + connect \Y $eq$ls180.v:4169$568_Y end - attribute \src "ls180.v:4064.295-4064.328" - cell $eq $eq$ls180.v:4064$474 + attribute \src "ls180.v:4169.295-4169.328" + cell $eq $eq$ls180.v:4169$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249269,10 +266750,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4064$474_Y + connect \Y $eq$ls180.v:4169$571_Y end - attribute \src "ls180.v:4069.42-4069.82" - cell $eq $eq$ls180.v:4069$483 + attribute \src "ls180.v:4174.42-4174.82" + cell $eq $eq$ls180.v:4174$580 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249280,10 +266761,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4069$483_Y + connect \Y $eq$ls180.v:4174$580_Y end - attribute \src "ls180.v:4069.145-4069.178" - cell $eq $eq$ls180.v:4069$484 + attribute \src "ls180.v:4174.145-4174.178" + cell $eq $eq$ls180.v:4174$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249291,10 +266772,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4069$484_Y + connect \Y $eq$ls180.v:4174$581_Y end - attribute \src "ls180.v:4069.220-4069.253" - cell $eq $eq$ls180.v:4069$487 + attribute \src "ls180.v:4174.220-4174.253" + cell $eq $eq$ls180.v:4174$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249302,10 +266783,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4069$487_Y + connect \Y $eq$ls180.v:4174$584_Y end - attribute \src "ls180.v:4069.295-4069.328" - cell $eq $eq$ls180.v:4069$490 + attribute \src "ls180.v:4174.295-4174.328" + cell $eq $eq$ls180.v:4174$587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249313,10 +266794,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4069$490_Y + connect \Y $eq$ls180.v:4174$587_Y end - attribute \src "ls180.v:4074.42-4074.82" - cell $eq $eq$ls180.v:4074$499 + attribute \src "ls180.v:4179.42-4179.82" + cell $eq $eq$ls180.v:4179$596 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249324,10 +266805,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4074$499_Y + connect \Y $eq$ls180.v:4179$596_Y end - attribute \src "ls180.v:4074.145-4074.178" - cell $eq $eq$ls180.v:4074$500 + attribute \src "ls180.v:4179.145-4179.178" + cell $eq $eq$ls180.v:4179$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249335,10 +266816,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4074$500_Y + connect \Y $eq$ls180.v:4179$597_Y end - attribute \src "ls180.v:4074.220-4074.253" - cell $eq $eq$ls180.v:4074$503 + attribute \src "ls180.v:4179.220-4179.253" + cell $eq $eq$ls180.v:4179$600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249346,10 +266827,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4074$503_Y + connect \Y $eq$ls180.v:4179$600_Y end - attribute \src "ls180.v:4074.295-4074.328" - cell $eq $eq$ls180.v:4074$506 + attribute \src "ls180.v:4179.295-4179.328" + cell $eq $eq$ls180.v:4179$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249357,10 +266838,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4074$506_Y + connect \Y $eq$ls180.v:4179$603_Y end - attribute \src "ls180.v:4079.44-4079.77" - cell $eq $eq$ls180.v:4079$515 + attribute \src "ls180.v:4184.44-4184.77" + cell $eq $eq$ls180.v:4184$612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249368,10 +266849,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$515_Y + connect \Y $eq$ls180.v:4184$612_Y end - attribute \src "ls180.v:4079.83-4079.123" - cell $eq $eq$ls180.v:4079$516 + attribute \src "ls180.v:4184.83-4184.123" + cell $eq $eq$ls180.v:4184$613 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249379,10 +266860,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4079$516_Y + connect \Y $eq$ls180.v:4184$613_Y end - attribute \src "ls180.v:4079.186-4079.219" - cell $eq $eq$ls180.v:4079$517 + attribute \src "ls180.v:4184.186-4184.219" + cell $eq $eq$ls180.v:4184$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249390,10 +266871,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$517_Y + connect \Y $eq$ls180.v:4184$614_Y end - attribute \src "ls180.v:4079.261-4079.294" - cell $eq $eq$ls180.v:4079$520 + attribute \src "ls180.v:4184.261-4184.294" + cell $eq $eq$ls180.v:4184$617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249401,10 +266882,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$520_Y + connect \Y $eq$ls180.v:4184$617_Y end - attribute \src "ls180.v:4079.336-4079.369" - cell $eq $eq$ls180.v:4079$523 + attribute \src "ls180.v:4184.336-4184.369" + cell $eq $eq$ls180.v:4184$620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249412,10 +266893,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$523_Y + connect \Y $eq$ls180.v:4184$620_Y end - attribute \src "ls180.v:4079.418-4079.451" - cell $eq $eq$ls180.v:4079$531 + attribute \src "ls180.v:4184.418-4184.451" + cell $eq $eq$ls180.v:4184$628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249423,10 +266904,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$531_Y + connect \Y $eq$ls180.v:4184$628_Y end - attribute \src "ls180.v:4079.457-4079.497" - cell $eq $eq$ls180.v:4079$532 + attribute \src "ls180.v:4184.457-4184.497" + cell $eq $eq$ls180.v:4184$629 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249434,10 +266915,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4079$532_Y + connect \Y $eq$ls180.v:4184$629_Y end - attribute \src "ls180.v:4079.560-4079.593" - cell $eq $eq$ls180.v:4079$533 + attribute \src "ls180.v:4184.560-4184.593" + cell $eq $eq$ls180.v:4184$630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249445,10 +266926,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$533_Y + connect \Y $eq$ls180.v:4184$630_Y end - attribute \src "ls180.v:4079.635-4079.668" - cell $eq $eq$ls180.v:4079$536 + attribute \src "ls180.v:4184.635-4184.668" + cell $eq $eq$ls180.v:4184$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249456,10 +266937,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$536_Y + connect \Y $eq$ls180.v:4184$633_Y end - attribute \src "ls180.v:4079.710-4079.743" - cell $eq $eq$ls180.v:4079$539 + attribute \src "ls180.v:4184.710-4184.743" + cell $eq $eq$ls180.v:4184$636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249467,10 +266948,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$539_Y + connect \Y $eq$ls180.v:4184$636_Y end - attribute \src "ls180.v:4079.792-4079.825" - cell $eq $eq$ls180.v:4079$547 + attribute \src "ls180.v:4184.792-4184.825" + cell $eq $eq$ls180.v:4184$644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249478,10 +266959,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$547_Y + connect \Y $eq$ls180.v:4184$644_Y end - attribute \src "ls180.v:4079.831-4079.871" - cell $eq $eq$ls180.v:4079$548 + attribute \src "ls180.v:4184.831-4184.871" + cell $eq $eq$ls180.v:4184$645 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249489,10 +266970,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4079$548_Y + connect \Y $eq$ls180.v:4184$645_Y end - attribute \src "ls180.v:4079.934-4079.967" - cell $eq $eq$ls180.v:4079$549 + attribute \src "ls180.v:4184.934-4184.967" + cell $eq $eq$ls180.v:4184$646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249500,10 +266981,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$549_Y + connect \Y $eq$ls180.v:4184$646_Y end - attribute \src "ls180.v:4079.1009-4079.1042" - cell $eq $eq$ls180.v:4079$552 + attribute \src "ls180.v:4184.1009-4184.1042" + cell $eq $eq$ls180.v:4184$649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249511,10 +266992,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$552_Y + connect \Y $eq$ls180.v:4184$649_Y end - attribute \src "ls180.v:4079.1084-4079.1117" - cell $eq $eq$ls180.v:4079$555 + attribute \src "ls180.v:4184.1084-4184.1117" + cell $eq $eq$ls180.v:4184$652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249522,10 +267003,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$555_Y + connect \Y $eq$ls180.v:4184$652_Y end - attribute \src "ls180.v:4079.1166-4079.1199" - cell $eq $eq$ls180.v:4079$563 + attribute \src "ls180.v:4184.1166-4184.1199" + cell $eq $eq$ls180.v:4184$660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249533,10 +267014,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$563_Y + connect \Y $eq$ls180.v:4184$660_Y end - attribute \src "ls180.v:4079.1205-4079.1245" - cell $eq $eq$ls180.v:4079$564 + attribute \src "ls180.v:4184.1205-4184.1245" + cell $eq $eq$ls180.v:4184$661 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249544,10 +267025,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4079$564_Y + connect \Y $eq$ls180.v:4184$661_Y end - attribute \src "ls180.v:4079.1308-4079.1341" - cell $eq $eq$ls180.v:4079$565 + attribute \src "ls180.v:4184.1308-4184.1341" + cell $eq $eq$ls180.v:4184$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249555,10 +267036,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$565_Y + connect \Y $eq$ls180.v:4184$662_Y end - attribute \src "ls180.v:4079.1383-4079.1416" - cell $eq $eq$ls180.v:4079$568 + attribute \src "ls180.v:4184.1383-4184.1416" + cell $eq $eq$ls180.v:4184$665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249566,10 +267047,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$568_Y + connect \Y $eq$ls180.v:4184$665_Y end - attribute \src "ls180.v:4079.1458-4079.1491" - cell $eq $eq$ls180.v:4079$571 + attribute \src "ls180.v:4184.1458-4184.1491" + cell $eq $eq$ls180.v:4184$668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249577,10 +267058,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$571_Y + connect \Y $eq$ls180.v:4184$668_Y end - attribute \src "ls180.v:4138.29-4138.57" - cell $eq $eq$ls180.v:4138$584 + attribute \src "ls180.v:4243.29-4243.57" + cell $eq $eq$ls180.v:4243$681 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249588,10 +267069,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_sel connect \B 1'0 - connect \Y $eq$ls180.v:4138$584_Y + connect \Y $eq$ls180.v:4243$681_Y end - attribute \src "ls180.v:4145.11-4145.41" - cell $eq $eq$ls180.v:4145$589 + attribute \src "ls180.v:4250.11-4250.41" + cell $eq $eq$ls180.v:4250$686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249599,76 +267080,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $eq$ls180.v:4145$589_Y + connect \Y $eq$ls180.v:4250$686_Y end - attribute \src "ls180.v:4302.37-4302.111" - cell $eq $eq$ls180.v:4302$654 + attribute \src "ls180.v:4418.37-4418.111" + cell $eq $eq$ls180.v:4418$753 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4302$653_Y - connect \Y $eq$ls180.v:4302$654_Y + connect \B $sub$ls180.v:4418$752_Y + connect \Y $eq$ls180.v:4418$753_Y end - attribute \src "ls180.v:4303.37-4303.105" - cell $eq $eq$ls180.v:4303$656 + attribute \src "ls180.v:4419.37-4419.105" + cell $eq $eq$ls180.v:4419$755 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4303$655_Y - connect \Y $eq$ls180.v:4303$656_Y + connect \B $sub$ls180.v:4419$754_Y + connect \Y $eq$ls180.v:4419$755_Y end - attribute \src "ls180.v:4330.10-4330.67" - cell $eq $eq$ls180.v:4330$660 + attribute \src "ls180.v:4446.10-4446.67" + cell $eq $eq$ls180.v:4446$759 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4330$659_Y - connect \Y $eq$ls180.v:4330$660_Y + connect \B $sub$ls180.v:4446$758_Y + connect \Y $eq$ls180.v:4446$759_Y end - attribute \src "ls180.v:4360.35-4360.108" - cell $eq $eq$ls180.v:4360$662 + attribute \src "ls180.v:4476.35-4476.108" + cell $eq $eq$ls180.v:4476$761 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4360$661_Y - connect \Y $eq$ls180.v:4360$662_Y + connect \B $sub$ls180.v:4476$760_Y + connect \Y $eq$ls180.v:4476$761_Y end - attribute \src "ls180.v:4361.35-4361.102" - cell $eq $eq$ls180.v:4361$664 + attribute \src "ls180.v:4477.35-4477.102" + cell $eq $eq$ls180.v:4477$763 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4361$663_Y - connect \Y $eq$ls180.v:4361$664_Y + connect \B $sub$ls180.v:4477$762_Y + connect \Y $eq$ls180.v:4477$763_Y end - attribute \src "ls180.v:4389.10-4389.65" - cell $eq $eq$ls180.v:4389$668 + attribute \src "ls180.v:4505.10-4505.65" + cell $eq $eq$ls180.v:4505$767 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4389$667_Y - connect \Y $eq$ls180.v:4389$668_Y + connect \B $sub$ls180.v:4505$766_Y + connect \Y $eq$ls180.v:4505$767_Y end - attribute \src "ls180.v:4493.10-4493.40" - cell $eq $eq$ls180.v:4493$695 + attribute \src "ls180.v:4609.10-4609.40" + cell $eq $eq$ls180.v:4609$794 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249676,10 +267157,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_count connect \B 7'1001111 - connect \Y $eq$ls180.v:4493$695_Y + connect \Y $eq$ls180.v:4609$794_Y end - attribute \src "ls180.v:4550.10-4550.39" - cell $eq $eq$ls180.v:4550$698 + attribute \src "ls180.v:4666.10-4666.39" + cell $eq $eq$ls180.v:4666$797 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249687,10 +267168,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4550$698_Y + connect \Y $eq$ls180.v:4666$797_Y end - attribute \src "ls180.v:4567.10-4567.39" - cell $eq $eq$ls180.v:4567$700 + attribute \src "ls180.v:4683.10-4683.39" + cell $eq $eq$ls180.v:4683$799 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249698,10 +267179,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4567$700_Y + connect \Y $eq$ls180.v:4683$799_Y end - attribute \src "ls180.v:4595.38-4595.88" - cell $eq $eq$ls180.v:4595$702 + attribute \src "ls180.v:4711.38-4711.88" + cell $eq $eq$ls180.v:4711$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249709,10 +267190,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \B 1'0 - connect \Y $eq$ls180.v:4595$702_Y + connect \Y $eq$ls180.v:4711$801_Y end - attribute \src "ls180.v:4645.9-4645.40" - cell $eq $eq$ls180.v:4645$712 + attribute \src "ls180.v:4761.9-4761.40" + cell $eq $eq$ls180.v:4761$811 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249720,21 +267201,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4645$712_Y + connect \Y $eq$ls180.v:4761$811_Y end - attribute \src "ls180.v:4654.36-4654.105" - cell $eq $eq$ls180.v:4654$714 + attribute \src "ls180.v:4770.36-4770.105" + cell $eq $eq$ls180.v:4770$813 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4654$713_Y - connect \Y $eq$ls180.v:4654$714_Y + connect \B $sub$ls180.v:4770$812_Y + connect \Y $eq$ls180.v:4770$813_Y end - attribute \src "ls180.v:4673.9-4673.40" - cell $eq $eq$ls180.v:4673$718 + attribute \src "ls180.v:4789.9-4789.40" + cell $eq $eq$ls180.v:4789$817 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249742,10 +267223,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4673$718_Y + connect \Y $eq$ls180.v:4789$817_Y end - attribute \src "ls180.v:4685.10-4685.39" - cell $eq $eq$ls180.v:4685$720 + attribute \src "ls180.v:4801.10-4801.39" + cell $eq $eq$ls180.v:4801$819 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249753,10 +267234,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count connect \B 3'111 - connect \Y $eq$ls180.v:4685$720_Y + connect \Y $eq$ls180.v:4801$819_Y end - attribute \src "ls180.v:4722.39-4722.94" - cell $eq $eq$ls180.v:4722$724 + attribute \src "ls180.v:4838.39-4838.94" + cell $eq $eq$ls180.v:4838$823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249764,10 +267245,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \B 1'0 - connect \Y $eq$ls180.v:4722$724_Y + connect \Y $eq$ls180.v:4838$823_Y end - attribute \src "ls180.v:4759.32-4759.89" - cell $eq $eq$ls180.v:4759$733 + attribute \src "ls180.v:4875.32-4875.89" + cell $eq $eq$ls180.v:4875$832 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249775,10 +267256,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $eq$ls180.v:4759$733_Y + connect \Y $eq$ls180.v:4875$832_Y end - attribute \src "ls180.v:4807.10-4807.40" - cell $eq $eq$ls180.v:4807$737 + attribute \src "ls180.v:4923.10-4923.40" + cell $eq $eq$ls180.v:4923$836 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249786,10 +267267,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $eq$ls180.v:4807$737_Y + connect \Y $eq$ls180.v:4923$836_Y end - attribute \src "ls180.v:4856.40-4856.98" - cell $eq $eq$ls180.v:4856$739 + attribute \src "ls180.v:4972.40-4972.98" + cell $eq $eq$ls180.v:4972$838 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249797,10 +267278,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_payload_data_i connect \B 1'0 - connect \Y $eq$ls180.v:4856$739_Y + connect \Y $eq$ls180.v:4972$838_Y end - attribute \src "ls180.v:4907.9-4907.41" - cell $eq $eq$ls180.v:4907$749 + attribute \src "ls180.v:5023.9-5023.41" + cell $eq $eq$ls180.v:5023$848 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249808,21 +267289,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4907$749_Y + connect \Y $eq$ls180.v:5023$848_Y end - attribute \src "ls180.v:4916.37-4916.123" - cell $eq $eq$ls180.v:4916$752 + attribute \src "ls180.v:5032.37-5032.123" + cell $eq $eq$ls180.v:5032$851 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:4916$751_Y - connect \Y $eq$ls180.v:4916$752_Y + connect \B $sub$ls180.v:5032$850_Y + connect \Y $eq$ls180.v:5032$851_Y end - attribute \src "ls180.v:4939.9-4939.41" - cell $eq $eq$ls180.v:4939$755 + attribute \src "ls180.v:5055.9-5055.41" + cell $eq $eq$ls180.v:5055$854 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249830,10 +267311,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4939$755_Y + connect \Y $eq$ls180.v:5055$854_Y end - attribute \src "ls180.v:4949.10-4949.41" - cell $eq $eq$ls180.v:4949$757 + attribute \src "ls180.v:5065.10-5065.41" + cell $eq $eq$ls180.v:5065$856 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -249841,10 +267322,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count connect \B 6'100111 - connect \Y $eq$ls180.v:4949$757_Y + connect \Y $eq$ls180.v:5065$856_Y end - attribute \src "ls180.v:5118.9-5118.47" - cell $eq $eq$ls180.v:5118$939 + attribute \src "ls180.v:5234.9-5234.47" + cell $eq $eq$ls180.v:5234$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249852,10 +267333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5118$939_Y + connect \Y $eq$ls180.v:5234$1038_Y end - attribute \src "ls180.v:5148.10-5148.48" - cell $eq $eq$ls180.v:5148$940 + attribute \src "ls180.v:5264.10-5264.48" + cell $eq $eq$ls180.v:5264$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249863,10 +267344,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5148$940_Y + connect \Y $eq$ls180.v:5264$1039_Y end - attribute \src "ls180.v:5179.10-5179.78" - cell $eq $eq$ls180.v:5179$945 + attribute \src "ls180.v:5295.10-5295.78" + cell $eq $eq$ls180.v:5295$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -249874,10 +267355,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo0 connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5179$945_Y + connect \Y $eq$ls180.v:5295$1044_Y end - attribute \src "ls180.v:5179.83-5179.151" - cell $eq $eq$ls180.v:5179$946 + attribute \src "ls180.v:5295.83-5295.151" + cell $eq $eq$ls180.v:5295$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -249885,10 +267366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo1 connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5179$946_Y + connect \Y $eq$ls180.v:5295$1045_Y end - attribute \src "ls180.v:5179.157-5179.225" - cell $eq $eq$ls180.v:5179$948 + attribute \src "ls180.v:5295.157-5295.225" + cell $eq $eq$ls180.v:5295$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -249896,10 +267377,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo2 connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5179$948_Y + connect \Y $eq$ls180.v:5295$1047_Y end - attribute \src "ls180.v:5179.231-5179.299" - cell $eq $eq$ls180.v:5179$950 + attribute \src "ls180.v:5295.231-5295.299" + cell $eq $eq$ls180.v:5295$1049 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -249907,10 +267388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo3 connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5179$950_Y + connect \Y $eq$ls180.v:5295$1049_Y end - attribute \src "ls180.v:5187.7-5187.44" - cell $eq $eq$ls180.v:5187$954 + attribute \src "ls180.v:5303.7-5303.44" + cell $eq $eq$ls180.v:5303$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249918,10 +267399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5187$954_Y + connect \Y $eq$ls180.v:5303$1053_Y end - attribute \src "ls180.v:5197.7-5197.44" - cell $eq $eq$ls180.v:5197$957 + attribute \src "ls180.v:5313.7-5313.44" + cell $eq $eq$ls180.v:5313$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249929,10 +267410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5197$957_Y + connect \Y $eq$ls180.v:5313$1056_Y end - attribute \src "ls180.v:5207.7-5207.44" - cell $eq $eq$ls180.v:5207$960 + attribute \src "ls180.v:5323.7-5323.44" + cell $eq $eq$ls180.v:5323$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249940,10 +267421,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5207$960_Y + connect \Y $eq$ls180.v:5323$1059_Y end - attribute \src "ls180.v:5217.7-5217.44" - cell $eq $eq$ls180.v:5217$963 + attribute \src "ls180.v:5333.7-5333.44" + cell $eq $eq$ls180.v:5333$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249951,10 +267432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5217$963_Y + connect \Y $eq$ls180.v:5333$1062_Y end - attribute \src "ls180.v:5341.36-5341.64" - cell $eq $eq$ls180.v:5341$1014 + attribute \src "ls180.v:5457.36-5457.64" + cell $eq $eq$ls180.v:5457$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249962,10 +267443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5341$1014_Y + connect \Y $eq$ls180.v:5457$1113_Y end - attribute \src "ls180.v:5347.10-5347.39" - cell $eq $eq$ls180.v:5347$1017 + attribute \src "ls180.v:5463.10-5463.39" + cell $eq $eq$ls180.v:5463$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249973,10 +267454,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_count connect \B 3'101 - connect \Y $eq$ls180.v:5347$1017_Y + connect \Y $eq$ls180.v:5463$1116_Y end - attribute \src "ls180.v:5348.11-5348.39" - cell $eq $eq$ls180.v:5348$1018 + attribute \src "ls180.v:5464.11-5464.39" + cell $eq $eq$ls180.v:5464$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249984,10 +267465,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5348$1018_Y + connect \Y $eq$ls180.v:5464$1117_Y end - attribute \src "ls180.v:5360.34-5360.63" - cell $eq $eq$ls180.v:5360$1019 + attribute \src "ls180.v:5476.34-5476.63" + cell $eq $eq$ls180.v:5476$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249995,10 +267476,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'0 - connect \Y $eq$ls180.v:5360$1019_Y + connect \Y $eq$ls180.v:5476$1118_Y end - attribute \src "ls180.v:5361.9-5361.37" - cell $eq $eq$ls180.v:5361$1020 + attribute \src "ls180.v:5477.9-5477.37" + cell $eq $eq$ls180.v:5477$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -250006,10 +267487,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 2'10 - connect \Y $eq$ls180.v:5361$1020_Y + connect \Y $eq$ls180.v:5477$1119_Y end - attribute \src "ls180.v:5368.10-5368.55" - cell $eq $eq$ls180.v:5368$1021 + attribute \src "ls180.v:5484.10-5484.55" + cell $eq $eq$ls180.v:5484$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250017,10 +267498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5368$1021_Y + connect \Y $eq$ls180.v:5484$1120_Y end - attribute \src "ls180.v:5374.12-5374.41" - cell $eq $eq$ls180.v:5374$1022 + attribute \src "ls180.v:5490.12-5490.41" + cell $eq $eq$ls180.v:5490$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -250028,10 +267509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 2'10 - connect \Y $eq$ls180.v:5374$1022_Y + connect \Y $eq$ls180.v:5490$1121_Y end - attribute \src "ls180.v:5377.13-5377.42" - cell $eq $eq$ls180.v:5377$1023 + attribute \src "ls180.v:5493.13-5493.42" + cell $eq $eq$ls180.v:5493$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -250039,32 +267520,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'1 - connect \Y $eq$ls180.v:5377$1023_Y + connect \Y $eq$ls180.v:5493$1122_Y end - attribute \src "ls180.v:5399.10-5399.76" - cell $eq $eq$ls180.v:5399$1028 + attribute \src "ls180.v:5515.10-5515.76" + cell $eq $eq$ls180.v:5515$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5399$1027_Y - connect \Y $eq$ls180.v:5399$1028_Y + connect \B $sub$ls180.v:5515$1126_Y + connect \Y $eq$ls180.v:5515$1127_Y end - attribute \src "ls180.v:5414.35-5414.101" - cell $eq $eq$ls180.v:5414$1031 + attribute \src "ls180.v:5530.35-5530.101" + cell $eq $eq$ls180.v:5530$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5414$1030_Y - connect \Y $eq$ls180.v:5414$1031_Y + connect \B $sub$ls180.v:5530$1129_Y + connect \Y $eq$ls180.v:5530$1130_Y end - attribute \src "ls180.v:5416.10-5416.56" - cell $eq $eq$ls180.v:5416$1032 + attribute \src "ls180.v:5532.10-5532.56" + cell $eq $eq$ls180.v:5532$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250072,21 +267553,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'0 - connect \Y $eq$ls180.v:5416$1032_Y + connect \Y $eq$ls180.v:5532$1131_Y end - attribute \src "ls180.v:5425.12-5425.78" - cell $eq $eq$ls180.v:5425$1036 + attribute \src "ls180.v:5541.12-5541.78" + cell $eq $eq$ls180.v:5541$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5425$1035_Y - connect \Y $eq$ls180.v:5425$1036_Y + connect \B $sub$ls180.v:5541$1134_Y + connect \Y $eq$ls180.v:5541$1135_Y end - attribute \src "ls180.v:5432.11-5432.57" - cell $eq $eq$ls180.v:5432$1037 + attribute \src "ls180.v:5548.11-5548.57" + cell $eq $eq$ls180.v:5548$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250094,54 +267575,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5432$1037_Y + connect \Y $eq$ls180.v:5548$1136_Y end - attribute \src "ls180.v:5549.10-5549.105" - cell $eq $eq$ls180.v:5549$1054 + attribute \src "ls180.v:5665.10-5665.105" + cell $eq $eq$ls180.v:5665$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5549$1053_Y - connect \Y $eq$ls180.v:5549$1054_Y + connect \B $sub$ls180.v:5665$1152_Y + connect \Y $eq$ls180.v:5665$1153_Y end - attribute \src "ls180.v:5639.39-5639.106" - cell $eq $eq$ls180.v:5639$1060 + attribute \src "ls180.v:5755.39-5755.106" + cell $eq $eq$ls180.v:5755$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5639$1059_Y - connect \Y $eq$ls180.v:5639$1060_Y + connect \B $sub$ls180.v:5755$1158_Y + connect \Y $eq$ls180.v:5755$1159_Y end - attribute \src "ls180.v:5669.44-5669.82" - cell $eq $eq$ls180.v:5669$1063 + attribute \src "ls180.v:5785.44-5785.82" + cell $eq $eq$ls180.v:5785$1162 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 1'0 - connect \Y $eq$ls180.v:5669$1063_Y + connect \Y $eq$ls180.v:5785$1162_Y end - attribute \src "ls180.v:5670.43-5670.81" - cell $eq $eq$ls180.v:5670$1064 + attribute \src "ls180.v:5786.43-5786.81" + cell $eq $eq$ls180.v:5786$1163 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux - connect \B 2'11 - connect \Y $eq$ls180.v:5670$1064_Y + connect \B 3'111 + connect \Y $eq$ls180.v:5786$1163_Y end - attribute \src "ls180.v:5770.85-5770.106" - cell $eq $eq$ls180.v:5770$1080 + attribute \src "ls180.v:5898.68-5898.89" + cell $eq $eq$ls180.v:5898$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250149,10 +267630,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5770$1080_Y + connect \Y $eq$ls180.v:5898$1179_Y end - attribute \src "ls180.v:5771.85-5771.106" - cell $eq $eq$ls180.v:5771$1082 + attribute \src "ls180.v:5899.68-5899.89" + cell $eq $eq$ls180.v:5899$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250160,10 +267641,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5771$1082_Y + connect \Y $eq$ls180.v:5899$1181_Y end - attribute \src "ls180.v:5772.85-5772.106" - cell $eq $eq$ls180.v:5772$1084 + attribute \src "ls180.v:5900.71-5900.92" + cell $eq $eq$ls180.v:5900$1183 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250171,10 +267652,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5772$1084_Y + connect \Y $eq$ls180.v:5900$1183_Y end - attribute \src "ls180.v:5773.57-5773.78" - cell $eq $eq$ls180.v:5773$1086 + attribute \src "ls180.v:5901.57-5901.78" + cell $eq $eq$ls180.v:5901$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250182,10 +267663,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5773$1086_Y + connect \Y $eq$ls180.v:5901$1185_Y end - attribute \src "ls180.v:5774.57-5774.78" - cell $eq $eq$ls180.v:5774$1088 + attribute \src "ls180.v:5902.57-5902.78" + cell $eq $eq$ls180.v:5902$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250193,10 +267674,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5774$1088_Y + connect \Y $eq$ls180.v:5902$1187_Y end - attribute \src "ls180.v:5775.85-5775.106" - cell $eq $eq$ls180.v:5775$1090 + attribute \src "ls180.v:5903.68-5903.89" + cell $eq $eq$ls180.v:5903$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250204,10 +267685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5775$1090_Y + connect \Y $eq$ls180.v:5903$1189_Y end - attribute \src "ls180.v:5776.85-5776.106" - cell $eq $eq$ls180.v:5776$1092 + attribute \src "ls180.v:5904.68-5904.89" + cell $eq $eq$ls180.v:5904$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250215,10 +267696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5776$1092_Y + connect \Y $eq$ls180.v:5904$1191_Y end - attribute \src "ls180.v:5777.85-5777.106" - cell $eq $eq$ls180.v:5777$1094 + attribute \src "ls180.v:5905.71-5905.92" + cell $eq $eq$ls180.v:5905$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250226,10 +267707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5777$1094_Y + connect \Y $eq$ls180.v:5905$1193_Y end - attribute \src "ls180.v:5778.57-5778.78" - cell $eq $eq$ls180.v:5778$1096 + attribute \src "ls180.v:5906.57-5906.78" + cell $eq $eq$ls180.v:5906$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250237,10 +267718,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5778$1096_Y + connect \Y $eq$ls180.v:5906$1195_Y end - attribute \src "ls180.v:5779.57-5779.78" - cell $eq $eq$ls180.v:5779$1098 + attribute \src "ls180.v:5907.57-5907.78" + cell $eq $eq$ls180.v:5907$1197 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250248,98 +267729,153 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5779$1098_Y + connect \Y $eq$ls180.v:5907$1197_Y end - attribute \src "ls180.v:5783.27-5783.59" - cell $eq $eq$ls180.v:5783$1101 + attribute \src "ls180.v:5911.27-5911.59" + cell $eq $eq$ls180.v:5911$1200 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] + connect \A \builder_shared_adr [29:6] connect \B 1'0 - connect \Y $eq$ls180.v:5783$1101_Y + connect \Y $eq$ls180.v:5911$1200_Y end - attribute \src "ls180.v:5784.27-5784.59" - cell $eq $eq$ls180.v:5784$1102 + attribute \src "ls180.v:5912.27-5912.59" + cell $eq $eq$ls180.v:5912$1201 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] - connect \B 4'1000 - connect \Y $eq$ls180.v:5784$1102_Y + connect \A \builder_shared_adr [29:6] + connect \B 1'1 + connect \Y $eq$ls180.v:5912$1201_Y end - attribute \src "ls180.v:5785.27-5785.60" - cell $eq $eq$ls180.v:5785$1103 + attribute \src "ls180.v:5913.27-5913.59" + cell $eq $eq$ls180.v:5913$1202 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] - connect \B 5'10000 - connect \Y $eq$ls180.v:5785$1103_Y + connect \A \builder_shared_adr [29:6] + connect \B 2'10 + connect \Y $eq$ls180.v:5913$1202_Y end - attribute \src "ls180.v:5786.27-5786.60" - cell $eq $eq$ls180.v:5786$1104 + attribute \src "ls180.v:5914.27-5914.59" + cell $eq $eq$ls180.v:5914$1203 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] - connect \B 5'11000 - connect \Y $eq$ls180.v:5786$1104_Y + connect \A \builder_shared_adr [29:6] + connect \B 2'11 + connect \Y $eq$ls180.v:5914$1203_Y end - attribute \src "ls180.v:5787.27-5787.68" - cell $eq $eq$ls180.v:5787$1105 + attribute \src "ls180.v:5915.27-5915.59" + cell $eq $eq$ls180.v:5915$1204 parameter \A_SIGNED 0 - parameter \A_WIDTH 27 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 3'100 + connect \Y $eq$ls180.v:5915$1204_Y + end + attribute \src "ls180.v:5916.27-5916.68" + cell $eq $eq$ls180.v:5916$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 28 parameter \B_SIGNED 0 parameter \B_WIDTH 27 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:3] + connect \A \builder_shared_adr [29:2] connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5787$1105_Y + connect \Y $eq$ls180.v:5916$1205_Y end - attribute \src "ls180.v:5788.27-5788.66" - cell $eq $eq$ls180.v:5788$1106 + attribute \src "ls180.v:5917.27-5917.65" + cell $eq $eq$ls180.v:5917$1206 parameter \A_SIGNED 0 - parameter \A_WIDTH 20 + parameter \A_WIDTH 21 parameter \B_SIGNED 0 parameter \B_WIDTH 20 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:10] + connect \A \builder_shared_adr [29:9] connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5788$1106_Y + connect \Y $eq$ls180.v:5917$1206_Y end - attribute \src "ls180.v:5789.27-5789.61" - cell $eq $eq$ls180.v:5789$1107 + attribute \src "ls180.v:5918.27-5918.59" + cell $eq $eq$ls180.v:5918$1207 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 1'1 + connect \Y $eq$ls180.v:5918$1207_Y + end + attribute \src "ls180.v:5919.27-5919.59" + cell $eq $eq$ls180.v:5919$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'10 + connect \Y $eq$ls180.v:5919$1208_Y + end + attribute \src "ls180.v:5920.27-5920.59" + cell $eq $eq$ls180.v:5920$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'11 + connect \Y $eq$ls180.v:5920$1209_Y + end + attribute \src "ls180.v:5921.28-5921.60" + cell $eq $eq$ls180.v:5921$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 3'100 + connect \Y $eq$ls180.v:5921$1210_Y + end + attribute \src "ls180.v:5922.28-5922.62" + cell $eq $eq$ls180.v:5922$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:23] + connect \A \builder_shared_adr [29:22] connect \B 7'1001000 - connect \Y $eq$ls180.v:5789$1107_Y + connect \Y $eq$ls180.v:5922$1211_Y end - attribute \src "ls180.v:5790.27-5790.65" - cell $eq $eq$ls180.v:5790$1108 + attribute \src "ls180.v:5923.28-5923.66" + cell $eq $eq$ls180.v:5923$1212 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 17 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:14] + connect \A \builder_shared_adr [29:13] connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5790$1108_Y + connect \Y $eq$ls180.v:5923$1212_Y end - attribute \src "ls180.v:5870.24-5870.45" - cell $eq $eq$ls180.v:5870$1150 + attribute \src "ls180.v:6043.24-6043.45" + cell $eq $eq$ls180.v:6043$1279 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -250347,21 +267883,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_count connect \B 1'0 - connect \Y $eq$ls180.v:5870$1150_Y + connect \Y $eq$ls180.v:6043$1279_Y end - attribute \src "ls180.v:5871.32-5871.77" - cell $eq $eq$ls180.v:5871$1151 + attribute \src "ls180.v:6044.32-6044.77" + cell $eq $eq$ls180.v:6044$1280 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:9] + connect \A \builder_interface0_bank_bus_adr [13:8] connect \B 1'0 - connect \Y $eq$ls180.v:5871$1151_Y + connect \Y $eq$ls180.v:6044$1280_Y end - attribute \src "ls180.v:5873.97-5873.141" - cell $eq $eq$ls180.v:5873$1153 + attribute \src "ls180.v:6046.97-6046.141" + cell $eq $eq$ls180.v:6046$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250369,10 +267905,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5873$1153_Y + connect \Y $eq$ls180.v:6046$1282_Y end - attribute \src "ls180.v:5874.100-5874.144" - cell $eq $eq$ls180.v:5874$1157 + attribute \src "ls180.v:6047.100-6047.144" + cell $eq $eq$ls180.v:6047$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250380,10 +267916,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5874$1157_Y + connect \Y $eq$ls180.v:6047$1286_Y end - attribute \src "ls180.v:5876.99-5876.143" - cell $eq $eq$ls180.v:5876$1160 + attribute \src "ls180.v:6049.99-6049.143" + cell $eq $eq$ls180.v:6049$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250391,10 +267927,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5876$1160_Y + connect \Y $eq$ls180.v:6049$1289_Y end - attribute \src "ls180.v:5877.102-5877.146" - cell $eq $eq$ls180.v:5877$1164 + attribute \src "ls180.v:6050.102-6050.146" + cell $eq $eq$ls180.v:6050$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250402,10 +267938,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5877$1164_Y + connect \Y $eq$ls180.v:6050$1293_Y end - attribute \src "ls180.v:5879.99-5879.143" - cell $eq $eq$ls180.v:5879$1167 + attribute \src "ls180.v:6052.99-6052.143" + cell $eq $eq$ls180.v:6052$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250413,10 +267949,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5879$1167_Y + connect \Y $eq$ls180.v:6052$1296_Y end - attribute \src "ls180.v:5880.102-5880.146" - cell $eq $eq$ls180.v:5880$1171 + attribute \src "ls180.v:6053.102-6053.146" + cell $eq $eq$ls180.v:6053$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250424,10 +267960,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5880$1171_Y + connect \Y $eq$ls180.v:6053$1300_Y end - attribute \src "ls180.v:5882.99-5882.143" - cell $eq $eq$ls180.v:5882$1174 + attribute \src "ls180.v:6055.99-6055.143" + cell $eq $eq$ls180.v:6055$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250435,10 +267971,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5882$1174_Y + connect \Y $eq$ls180.v:6055$1303_Y end - attribute \src "ls180.v:5883.102-5883.146" - cell $eq $eq$ls180.v:5883$1178 + attribute \src "ls180.v:6056.102-6056.146" + cell $eq $eq$ls180.v:6056$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250446,10 +267982,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5883$1178_Y + connect \Y $eq$ls180.v:6056$1307_Y end - attribute \src "ls180.v:5885.99-5885.143" - cell $eq $eq$ls180.v:5885$1181 + attribute \src "ls180.v:6058.99-6058.143" + cell $eq $eq$ls180.v:6058$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250457,10 +267993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5885$1181_Y + connect \Y $eq$ls180.v:6058$1310_Y end - attribute \src "ls180.v:5886.102-5886.146" - cell $eq $eq$ls180.v:5886$1185 + attribute \src "ls180.v:6059.102-6059.146" + cell $eq $eq$ls180.v:6059$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250468,10 +268004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5886$1185_Y + connect \Y $eq$ls180.v:6059$1314_Y end - attribute \src "ls180.v:5888.102-5888.146" - cell $eq $eq$ls180.v:5888$1188 + attribute \src "ls180.v:6061.102-6061.146" + cell $eq $eq$ls180.v:6061$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250479,10 +268015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5888$1188_Y + connect \Y $eq$ls180.v:6061$1317_Y end - attribute \src "ls180.v:5889.105-5889.149" - cell $eq $eq$ls180.v:5889$1192 + attribute \src "ls180.v:6062.105-6062.149" + cell $eq $eq$ls180.v:6062$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250490,10 +268026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5889$1192_Y + connect \Y $eq$ls180.v:6062$1321_Y end - attribute \src "ls180.v:5891.102-5891.146" - cell $eq $eq$ls180.v:5891$1195 + attribute \src "ls180.v:6064.102-6064.146" + cell $eq $eq$ls180.v:6064$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250501,10 +268037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5891$1195_Y + connect \Y $eq$ls180.v:6064$1324_Y end - attribute \src "ls180.v:5892.105-5892.149" - cell $eq $eq$ls180.v:5892$1199 + attribute \src "ls180.v:6065.105-6065.149" + cell $eq $eq$ls180.v:6065$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250512,10 +268048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5892$1199_Y + connect \Y $eq$ls180.v:6065$1328_Y end - attribute \src "ls180.v:5894.102-5894.146" - cell $eq $eq$ls180.v:5894$1202 + attribute \src "ls180.v:6067.102-6067.146" + cell $eq $eq$ls180.v:6067$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250523,10 +268059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5894$1202_Y + connect \Y $eq$ls180.v:6067$1331_Y end - attribute \src "ls180.v:5895.105-5895.149" - cell $eq $eq$ls180.v:5895$1206 + attribute \src "ls180.v:6068.105-6068.149" + cell $eq $eq$ls180.v:6068$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250534,10 +268070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5895$1206_Y + connect \Y $eq$ls180.v:6068$1335_Y end - attribute \src "ls180.v:5897.102-5897.146" - cell $eq $eq$ls180.v:5897$1209 + attribute \src "ls180.v:6070.102-6070.146" + cell $eq $eq$ls180.v:6070$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250545,10 +268081,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5897$1209_Y + connect \Y $eq$ls180.v:6070$1338_Y end - attribute \src "ls180.v:5898.105-5898.149" - cell $eq $eq$ls180.v:5898$1213 + attribute \src "ls180.v:6071.105-6071.149" + cell $eq $eq$ls180.v:6071$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250556,21 +268092,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5898$1213_Y + connect \Y $eq$ls180.v:6071$1342_Y end - attribute \src "ls180.v:5909.32-5909.77" - cell $eq $eq$ls180.v:5909$1215 + attribute \src "ls180.v:6082.32-6082.77" + cell $eq $eq$ls180.v:6082$1344 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:9] + connect \A \builder_interface1_bank_bus_adr [13:8] connect \B 3'110 - connect \Y $eq$ls180.v:5909$1215_Y + connect \Y $eq$ls180.v:6082$1344_Y end - attribute \src "ls180.v:5911.94-5911.138" - cell $eq $eq$ls180.v:5911$1217 + attribute \src "ls180.v:6084.94-6084.138" + cell $eq $eq$ls180.v:6084$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250578,10 +268114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5911$1217_Y + connect \Y $eq$ls180.v:6084$1346_Y end - attribute \src "ls180.v:5912.97-5912.141" - cell $eq $eq$ls180.v:5912$1221 + attribute \src "ls180.v:6085.97-6085.141" + cell $eq $eq$ls180.v:6085$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250589,10 +268125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5912$1221_Y + connect \Y $eq$ls180.v:6085$1350_Y end - attribute \src "ls180.v:5914.94-5914.138" - cell $eq $eq$ls180.v:5914$1224 + attribute \src "ls180.v:6087.94-6087.138" + cell $eq $eq$ls180.v:6087$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250600,10 +268136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5914$1224_Y + connect \Y $eq$ls180.v:6087$1353_Y end - attribute \src "ls180.v:5915.97-5915.141" - cell $eq $eq$ls180.v:5915$1228 + attribute \src "ls180.v:6088.97-6088.141" + cell $eq $eq$ls180.v:6088$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250611,10 +268147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5915$1228_Y + connect \Y $eq$ls180.v:6088$1357_Y end - attribute \src "ls180.v:5917.94-5917.138" - cell $eq $eq$ls180.v:5917$1231 + attribute \src "ls180.v:6090.94-6090.138" + cell $eq $eq$ls180.v:6090$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250622,10 +268158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5917$1231_Y + connect \Y $eq$ls180.v:6090$1360_Y end - attribute \src "ls180.v:5918.97-5918.141" - cell $eq $eq$ls180.v:5918$1235 + attribute \src "ls180.v:6091.97-6091.141" + cell $eq $eq$ls180.v:6091$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250633,10 +268169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5918$1235_Y + connect \Y $eq$ls180.v:6091$1364_Y end - attribute \src "ls180.v:5920.94-5920.138" - cell $eq $eq$ls180.v:5920$1238 + attribute \src "ls180.v:6093.94-6093.138" + cell $eq $eq$ls180.v:6093$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250644,10 +268180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5920$1238_Y + connect \Y $eq$ls180.v:6093$1367_Y end - attribute \src "ls180.v:5921.97-5921.141" - cell $eq $eq$ls180.v:5921$1242 + attribute \src "ls180.v:6094.97-6094.141" + cell $eq $eq$ls180.v:6094$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250655,10 +268191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5921$1242_Y + connect \Y $eq$ls180.v:6094$1371_Y end - attribute \src "ls180.v:5923.95-5923.139" - cell $eq $eq$ls180.v:5923$1245 + attribute \src "ls180.v:6096.95-6096.139" + cell $eq $eq$ls180.v:6096$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250666,10 +268202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5923$1245_Y + connect \Y $eq$ls180.v:6096$1374_Y end - attribute \src "ls180.v:5924.98-5924.142" - cell $eq $eq$ls180.v:5924$1249 + attribute \src "ls180.v:6097.98-6097.142" + cell $eq $eq$ls180.v:6097$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250677,10 +268213,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5924$1249_Y + connect \Y $eq$ls180.v:6097$1378_Y end - attribute \src "ls180.v:5926.95-5926.139" - cell $eq $eq$ls180.v:5926$1252 + attribute \src "ls180.v:6099.95-6099.139" + cell $eq $eq$ls180.v:6099$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250688,10 +268224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5926$1252_Y + connect \Y $eq$ls180.v:6099$1381_Y end - attribute \src "ls180.v:5927.98-5927.142" - cell $eq $eq$ls180.v:5927$1256 + attribute \src "ls180.v:6100.98-6100.142" + cell $eq $eq$ls180.v:6100$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250699,21 +268235,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5927$1256_Y + connect \Y $eq$ls180.v:6100$1385_Y end - attribute \src "ls180.v:5935.32-5935.78" - cell $eq $eq$ls180.v:5935$1258 + attribute \src "ls180.v:6108.32-6108.78" + cell $eq $eq$ls180.v:6108$1387 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:9] - connect \B 4'1011 - connect \Y $eq$ls180.v:5935$1258_Y + connect \A \builder_interface2_bank_bus_adr [13:8] + connect \B 4'1100 + connect \Y $eq$ls180.v:6108$1387_Y end - attribute \src "ls180.v:5937.93-5937.135" - cell $eq $eq$ls180.v:5937$1260 + attribute \src "ls180.v:6110.93-6110.135" + cell $eq $eq$ls180.v:6110$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250721,10 +268257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:5937$1260_Y + connect \Y $eq$ls180.v:6110$1389_Y end - attribute \src "ls180.v:5938.96-5938.138" - cell $eq $eq$ls180.v:5938$1264 + attribute \src "ls180.v:6111.96-6111.138" + cell $eq $eq$ls180.v:6111$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250732,10 +268268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:5938$1264_Y + connect \Y $eq$ls180.v:6111$1393_Y end - attribute \src "ls180.v:5940.92-5940.134" - cell $eq $eq$ls180.v:5940$1267 + attribute \src "ls180.v:6113.92-6113.134" + cell $eq $eq$ls180.v:6113$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250743,10 +268279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:5940$1267_Y + connect \Y $eq$ls180.v:6113$1396_Y end - attribute \src "ls180.v:5941.95-5941.137" - cell $eq $eq$ls180.v:5941$1271 + attribute \src "ls180.v:6114.95-6114.137" + cell $eq $eq$ls180.v:6114$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250754,21 +268290,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:5941$1271_Y + connect \Y $eq$ls180.v:6114$1400_Y end - attribute \src "ls180.v:5949.32-5949.77" - cell $eq $eq$ls180.v:5949$1273 + attribute \src "ls180.v:6122.32-6122.78" + cell $eq $eq$ls180.v:6122$1402 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:9] - connect \B 4'1001 - connect \Y $eq$ls180.v:5949$1273_Y + connect \A \builder_interface3_bank_bus_adr [13:8] + connect \B 4'1010 + connect \Y $eq$ls180.v:6122$1402_Y end - attribute \src "ls180.v:5951.98-5951.142" - cell $eq $eq$ls180.v:5951$1275 + attribute \src "ls180.v:6124.98-6124.142" + cell $eq $eq$ls180.v:6124$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250776,10 +268312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5951$1275_Y + connect \Y $eq$ls180.v:6124$1404_Y end - attribute \src "ls180.v:5952.101-5952.145" - cell $eq $eq$ls180.v:5952$1279 + attribute \src "ls180.v:6125.101-6125.145" + cell $eq $eq$ls180.v:6125$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250787,10 +268323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5952$1279_Y + connect \Y $eq$ls180.v:6125$1408_Y end - attribute \src "ls180.v:5954.97-5954.141" - cell $eq $eq$ls180.v:5954$1282 + attribute \src "ls180.v:6127.97-6127.141" + cell $eq $eq$ls180.v:6127$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250798,10 +268334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5954$1282_Y + connect \Y $eq$ls180.v:6127$1411_Y end - attribute \src "ls180.v:5955.100-5955.144" - cell $eq $eq$ls180.v:5955$1286 + attribute \src "ls180.v:6128.100-6128.144" + cell $eq $eq$ls180.v:6128$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250809,10 +268345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5955$1286_Y + connect \Y $eq$ls180.v:6128$1415_Y end - attribute \src "ls180.v:5957.97-5957.141" - cell $eq $eq$ls180.v:5957$1289 + attribute \src "ls180.v:6130.97-6130.141" + cell $eq $eq$ls180.v:6130$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250820,10 +268356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5957$1289_Y + connect \Y $eq$ls180.v:6130$1418_Y end - attribute \src "ls180.v:5958.100-5958.144" - cell $eq $eq$ls180.v:5958$1293 + attribute \src "ls180.v:6131.100-6131.144" + cell $eq $eq$ls180.v:6131$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250831,10 +268367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5958$1293_Y + connect \Y $eq$ls180.v:6131$1422_Y end - attribute \src "ls180.v:5960.97-5960.141" - cell $eq $eq$ls180.v:5960$1296 + attribute \src "ls180.v:6133.97-6133.141" + cell $eq $eq$ls180.v:6133$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250842,10 +268378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5960$1296_Y + connect \Y $eq$ls180.v:6133$1425_Y end - attribute \src "ls180.v:5961.100-5961.144" - cell $eq $eq$ls180.v:5961$1300 + attribute \src "ls180.v:6134.100-6134.144" + cell $eq $eq$ls180.v:6134$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250853,10 +268389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5961$1300_Y + connect \Y $eq$ls180.v:6134$1429_Y end - attribute \src "ls180.v:5963.97-5963.141" - cell $eq $eq$ls180.v:5963$1303 + attribute \src "ls180.v:6136.97-6136.141" + cell $eq $eq$ls180.v:6136$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250864,10 +268400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5963$1303_Y + connect \Y $eq$ls180.v:6136$1432_Y end - attribute \src "ls180.v:5964.100-5964.144" - cell $eq $eq$ls180.v:5964$1307 + attribute \src "ls180.v:6137.100-6137.144" + cell $eq $eq$ls180.v:6137$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250875,10 +268411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5964$1307_Y + connect \Y $eq$ls180.v:6137$1436_Y end - attribute \src "ls180.v:5966.98-5966.142" - cell $eq $eq$ls180.v:5966$1310 + attribute \src "ls180.v:6139.98-6139.142" + cell $eq $eq$ls180.v:6139$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250886,10 +268422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5966$1310_Y + connect \Y $eq$ls180.v:6139$1439_Y end - attribute \src "ls180.v:5967.101-5967.145" - cell $eq $eq$ls180.v:5967$1314 + attribute \src "ls180.v:6140.101-6140.145" + cell $eq $eq$ls180.v:6140$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250897,10 +268433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5967$1314_Y + connect \Y $eq$ls180.v:6140$1443_Y end - attribute \src "ls180.v:5969.98-5969.142" - cell $eq $eq$ls180.v:5969$1317 + attribute \src "ls180.v:6142.98-6142.142" + cell $eq $eq$ls180.v:6142$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250908,10 +268444,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5969$1317_Y + connect \Y $eq$ls180.v:6142$1446_Y end - attribute \src "ls180.v:5970.101-5970.145" - cell $eq $eq$ls180.v:5970$1321 + attribute \src "ls180.v:6143.101-6143.145" + cell $eq $eq$ls180.v:6143$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250919,10 +268455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5970$1321_Y + connect \Y $eq$ls180.v:6143$1450_Y end - attribute \src "ls180.v:5972.98-5972.142" - cell $eq $eq$ls180.v:5972$1324 + attribute \src "ls180.v:6145.98-6145.142" + cell $eq $eq$ls180.v:6145$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250930,10 +268466,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5972$1324_Y + connect \Y $eq$ls180.v:6145$1453_Y end - attribute \src "ls180.v:5973.101-5973.145" - cell $eq $eq$ls180.v:5973$1328 + attribute \src "ls180.v:6146.101-6146.145" + cell $eq $eq$ls180.v:6146$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250941,10 +268477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5973$1328_Y + connect \Y $eq$ls180.v:6146$1457_Y end - attribute \src "ls180.v:5975.98-5975.142" - cell $eq $eq$ls180.v:5975$1331 + attribute \src "ls180.v:6148.98-6148.142" + cell $eq $eq$ls180.v:6148$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250952,10 +268488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5975$1331_Y + connect \Y $eq$ls180.v:6148$1460_Y end - attribute \src "ls180.v:5976.101-5976.145" - cell $eq $eq$ls180.v:5976$1335 + attribute \src "ls180.v:6149.101-6149.145" + cell $eq $eq$ls180.v:6149$1464 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250963,21 +268499,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5976$1335_Y + connect \Y $eq$ls180.v:6149$1464_Y end - attribute \src "ls180.v:5986.32-5986.78" - cell $eq $eq$ls180.v:5986$1337 + attribute \src "ls180.v:6159.32-6159.78" + cell $eq $eq$ls180.v:6159$1466 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:9] - connect \B 4'1010 - connect \Y $eq$ls180.v:5986$1337_Y + connect \A \builder_interface4_bank_bus_adr [13:8] + connect \B 4'1011 + connect \Y $eq$ls180.v:6159$1466_Y end - attribute \src "ls180.v:5988.98-5988.142" - cell $eq $eq$ls180.v:5988$1339 + attribute \src "ls180.v:6161.98-6161.142" + cell $eq $eq$ls180.v:6161$1468 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250985,10 +268521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5988$1339_Y + connect \Y $eq$ls180.v:6161$1468_Y end - attribute \src "ls180.v:5989.101-5989.145" - cell $eq $eq$ls180.v:5989$1343 + attribute \src "ls180.v:6162.101-6162.145" + cell $eq $eq$ls180.v:6162$1472 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250996,10 +268532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5989$1343_Y + connect \Y $eq$ls180.v:6162$1472_Y end - attribute \src "ls180.v:5991.97-5991.141" - cell $eq $eq$ls180.v:5991$1346 + attribute \src "ls180.v:6164.97-6164.141" + cell $eq $eq$ls180.v:6164$1475 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251007,10 +268543,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5991$1346_Y + connect \Y $eq$ls180.v:6164$1475_Y end - attribute \src "ls180.v:5992.100-5992.144" - cell $eq $eq$ls180.v:5992$1350 + attribute \src "ls180.v:6165.100-6165.144" + cell $eq $eq$ls180.v:6165$1479 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251018,10 +268554,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5992$1350_Y + connect \Y $eq$ls180.v:6165$1479_Y end - attribute \src "ls180.v:5994.97-5994.141" - cell $eq $eq$ls180.v:5994$1353 + attribute \src "ls180.v:6167.97-6167.141" + cell $eq $eq$ls180.v:6167$1482 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251029,10 +268565,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5994$1353_Y + connect \Y $eq$ls180.v:6167$1482_Y end - attribute \src "ls180.v:5995.100-5995.144" - cell $eq $eq$ls180.v:5995$1357 + attribute \src "ls180.v:6168.100-6168.144" + cell $eq $eq$ls180.v:6168$1486 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251040,10 +268576,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5995$1357_Y + connect \Y $eq$ls180.v:6168$1486_Y end - attribute \src "ls180.v:5997.97-5997.141" - cell $eq $eq$ls180.v:5997$1360 + attribute \src "ls180.v:6170.97-6170.141" + cell $eq $eq$ls180.v:6170$1489 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251051,10 +268587,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5997$1360_Y + connect \Y $eq$ls180.v:6170$1489_Y end - attribute \src "ls180.v:5998.100-5998.144" - cell $eq $eq$ls180.v:5998$1364 + attribute \src "ls180.v:6171.100-6171.144" + cell $eq $eq$ls180.v:6171$1493 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251062,10 +268598,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5998$1364_Y + connect \Y $eq$ls180.v:6171$1493_Y end - attribute \src "ls180.v:6000.97-6000.141" - cell $eq $eq$ls180.v:6000$1367 + attribute \src "ls180.v:6173.97-6173.141" + cell $eq $eq$ls180.v:6173$1496 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251073,10 +268609,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6000$1367_Y + connect \Y $eq$ls180.v:6173$1496_Y end - attribute \src "ls180.v:6001.100-6001.144" - cell $eq $eq$ls180.v:6001$1371 + attribute \src "ls180.v:6174.100-6174.144" + cell $eq $eq$ls180.v:6174$1500 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251084,10 +268620,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6001$1371_Y + connect \Y $eq$ls180.v:6174$1500_Y end - attribute \src "ls180.v:6003.98-6003.142" - cell $eq $eq$ls180.v:6003$1374 + attribute \src "ls180.v:6176.98-6176.142" + cell $eq $eq$ls180.v:6176$1503 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251095,10 +268631,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6003$1374_Y + connect \Y $eq$ls180.v:6176$1503_Y end - attribute \src "ls180.v:6004.101-6004.145" - cell $eq $eq$ls180.v:6004$1378 + attribute \src "ls180.v:6177.101-6177.145" + cell $eq $eq$ls180.v:6177$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251106,10 +268642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6004$1378_Y + connect \Y $eq$ls180.v:6177$1507_Y end - attribute \src "ls180.v:6006.98-6006.142" - cell $eq $eq$ls180.v:6006$1381 + attribute \src "ls180.v:6179.98-6179.142" + cell $eq $eq$ls180.v:6179$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251117,10 +268653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6006$1381_Y + connect \Y $eq$ls180.v:6179$1510_Y end - attribute \src "ls180.v:6007.101-6007.145" - cell $eq $eq$ls180.v:6007$1385 + attribute \src "ls180.v:6180.101-6180.145" + cell $eq $eq$ls180.v:6180$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251128,10 +268664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6007$1385_Y + connect \Y $eq$ls180.v:6180$1514_Y end - attribute \src "ls180.v:6009.98-6009.142" - cell $eq $eq$ls180.v:6009$1388 + attribute \src "ls180.v:6182.98-6182.142" + cell $eq $eq$ls180.v:6182$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251139,10 +268675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6009$1388_Y + connect \Y $eq$ls180.v:6182$1517_Y end - attribute \src "ls180.v:6010.101-6010.145" - cell $eq $eq$ls180.v:6010$1392 + attribute \src "ls180.v:6183.101-6183.145" + cell $eq $eq$ls180.v:6183$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251150,10 +268686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6010$1392_Y + connect \Y $eq$ls180.v:6183$1521_Y end - attribute \src "ls180.v:6012.98-6012.142" - cell $eq $eq$ls180.v:6012$1395 + attribute \src "ls180.v:6185.98-6185.142" + cell $eq $eq$ls180.v:6185$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251161,10 +268697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6012$1395_Y + connect \Y $eq$ls180.v:6185$1524_Y end - attribute \src "ls180.v:6013.101-6013.145" - cell $eq $eq$ls180.v:6013$1399 + attribute \src "ls180.v:6186.101-6186.145" + cell $eq $eq$ls180.v:6186$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251172,21 +268708,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6013$1399_Y + connect \Y $eq$ls180.v:6186$1528_Y end - attribute \src "ls180.v:6023.32-6023.78" - cell $eq $eq$ls180.v:6023$1401 + attribute \src "ls180.v:6196.32-6196.78" + cell $eq $eq$ls180.v:6196$1530 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:9] - connect \B 4'1110 - connect \Y $eq$ls180.v:6023$1401_Y + connect \A \builder_interface5_bank_bus_adr [13:8] + connect \B 4'1111 + connect \Y $eq$ls180.v:6196$1530_Y end - attribute \src "ls180.v:6025.100-6025.144" - cell $eq $eq$ls180.v:6025$1403 + attribute \src "ls180.v:6198.100-6198.144" + cell $eq $eq$ls180.v:6198$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251194,10 +268730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6025$1403_Y + connect \Y $eq$ls180.v:6198$1532_Y end - attribute \src "ls180.v:6026.103-6026.147" - cell $eq $eq$ls180.v:6026$1407 + attribute \src "ls180.v:6199.103-6199.147" + cell $eq $eq$ls180.v:6199$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251205,10 +268741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6026$1407_Y + connect \Y $eq$ls180.v:6199$1536_Y end - attribute \src "ls180.v:6028.100-6028.144" - cell $eq $eq$ls180.v:6028$1410 + attribute \src "ls180.v:6201.100-6201.144" + cell $eq $eq$ls180.v:6201$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251216,10 +268752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6028$1410_Y + connect \Y $eq$ls180.v:6201$1539_Y end - attribute \src "ls180.v:6029.103-6029.147" - cell $eq $eq$ls180.v:6029$1414 + attribute \src "ls180.v:6202.103-6202.147" + cell $eq $eq$ls180.v:6202$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251227,10 +268763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6029$1414_Y + connect \Y $eq$ls180.v:6202$1543_Y end - attribute \src "ls180.v:6031.100-6031.144" - cell $eq $eq$ls180.v:6031$1417 + attribute \src "ls180.v:6204.100-6204.144" + cell $eq $eq$ls180.v:6204$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251238,10 +268774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6031$1417_Y + connect \Y $eq$ls180.v:6204$1546_Y end - attribute \src "ls180.v:6032.103-6032.147" - cell $eq $eq$ls180.v:6032$1421 + attribute \src "ls180.v:6205.103-6205.147" + cell $eq $eq$ls180.v:6205$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251249,10 +268785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6032$1421_Y + connect \Y $eq$ls180.v:6205$1550_Y end - attribute \src "ls180.v:6034.100-6034.144" - cell $eq $eq$ls180.v:6034$1424 + attribute \src "ls180.v:6207.100-6207.144" + cell $eq $eq$ls180.v:6207$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251260,10 +268796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6034$1424_Y + connect \Y $eq$ls180.v:6207$1553_Y end - attribute \src "ls180.v:6035.103-6035.147" - cell $eq $eq$ls180.v:6035$1428 + attribute \src "ls180.v:6208.103-6208.147" + cell $eq $eq$ls180.v:6208$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251271,10 +268807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6035$1428_Y + connect \Y $eq$ls180.v:6208$1557_Y end - attribute \src "ls180.v:6037.100-6037.144" - cell $eq $eq$ls180.v:6037$1431 + attribute \src "ls180.v:6210.100-6210.144" + cell $eq $eq$ls180.v:6210$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251282,10 +268818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6037$1431_Y + connect \Y $eq$ls180.v:6210$1560_Y end - attribute \src "ls180.v:6038.103-6038.147" - cell $eq $eq$ls180.v:6038$1435 + attribute \src "ls180.v:6211.103-6211.147" + cell $eq $eq$ls180.v:6211$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251293,10 +268829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6038$1435_Y + connect \Y $eq$ls180.v:6211$1564_Y end - attribute \src "ls180.v:6040.100-6040.144" - cell $eq $eq$ls180.v:6040$1438 + attribute \src "ls180.v:6213.100-6213.144" + cell $eq $eq$ls180.v:6213$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251304,10 +268840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6040$1438_Y + connect \Y $eq$ls180.v:6213$1567_Y end - attribute \src "ls180.v:6041.103-6041.147" - cell $eq $eq$ls180.v:6041$1442 + attribute \src "ls180.v:6214.103-6214.147" + cell $eq $eq$ls180.v:6214$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251315,10 +268851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6041$1442_Y + connect \Y $eq$ls180.v:6214$1571_Y end - attribute \src "ls180.v:6043.100-6043.144" - cell $eq $eq$ls180.v:6043$1445 + attribute \src "ls180.v:6216.100-6216.144" + cell $eq $eq$ls180.v:6216$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251326,10 +268862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6043$1445_Y + connect \Y $eq$ls180.v:6216$1574_Y end - attribute \src "ls180.v:6044.103-6044.147" - cell $eq $eq$ls180.v:6044$1449 + attribute \src "ls180.v:6217.103-6217.147" + cell $eq $eq$ls180.v:6217$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251337,10 +268873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6044$1449_Y + connect \Y $eq$ls180.v:6217$1578_Y end - attribute \src "ls180.v:6046.100-6046.144" - cell $eq $eq$ls180.v:6046$1452 + attribute \src "ls180.v:6219.100-6219.144" + cell $eq $eq$ls180.v:6219$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251348,10 +268884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6046$1452_Y + connect \Y $eq$ls180.v:6219$1581_Y end - attribute \src "ls180.v:6047.103-6047.147" - cell $eq $eq$ls180.v:6047$1456 + attribute \src "ls180.v:6220.103-6220.147" + cell $eq $eq$ls180.v:6220$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251359,10 +268895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6047$1456_Y + connect \Y $eq$ls180.v:6220$1585_Y end - attribute \src "ls180.v:6049.102-6049.146" - cell $eq $eq$ls180.v:6049$1459 + attribute \src "ls180.v:6222.102-6222.146" + cell $eq $eq$ls180.v:6222$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251370,10 +268906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6049$1459_Y + connect \Y $eq$ls180.v:6222$1588_Y end - attribute \src "ls180.v:6050.105-6050.149" - cell $eq $eq$ls180.v:6050$1463 + attribute \src "ls180.v:6223.105-6223.149" + cell $eq $eq$ls180.v:6223$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251381,10 +268917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6050$1463_Y + connect \Y $eq$ls180.v:6223$1592_Y end - attribute \src "ls180.v:6052.102-6052.146" - cell $eq $eq$ls180.v:6052$1466 + attribute \src "ls180.v:6225.102-6225.146" + cell $eq $eq$ls180.v:6225$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251392,10 +268928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6052$1466_Y + connect \Y $eq$ls180.v:6225$1595_Y end - attribute \src "ls180.v:6053.105-6053.149" - cell $eq $eq$ls180.v:6053$1470 + attribute \src "ls180.v:6226.105-6226.149" + cell $eq $eq$ls180.v:6226$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251403,10 +268939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6053$1470_Y + connect \Y $eq$ls180.v:6226$1599_Y end - attribute \src "ls180.v:6055.102-6055.147" - cell $eq $eq$ls180.v:6055$1473 + attribute \src "ls180.v:6228.102-6228.147" + cell $eq $eq$ls180.v:6228$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251414,10 +268950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6055$1473_Y + connect \Y $eq$ls180.v:6228$1602_Y end - attribute \src "ls180.v:6056.105-6056.150" - cell $eq $eq$ls180.v:6056$1477 + attribute \src "ls180.v:6229.105-6229.150" + cell $eq $eq$ls180.v:6229$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251425,10 +268961,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6056$1477_Y + connect \Y $eq$ls180.v:6229$1606_Y end - attribute \src "ls180.v:6058.102-6058.147" - cell $eq $eq$ls180.v:6058$1480 + attribute \src "ls180.v:6231.102-6231.147" + cell $eq $eq$ls180.v:6231$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251436,10 +268972,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6058$1480_Y + connect \Y $eq$ls180.v:6231$1609_Y end - attribute \src "ls180.v:6059.105-6059.150" - cell $eq $eq$ls180.v:6059$1484 + attribute \src "ls180.v:6232.105-6232.150" + cell $eq $eq$ls180.v:6232$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251447,10 +268983,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6059$1484_Y + connect \Y $eq$ls180.v:6232$1613_Y end - attribute \src "ls180.v:6061.102-6061.147" - cell $eq $eq$ls180.v:6061$1487 + attribute \src "ls180.v:6234.102-6234.147" + cell $eq $eq$ls180.v:6234$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251458,10 +268994,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6061$1487_Y + connect \Y $eq$ls180.v:6234$1616_Y end - attribute \src "ls180.v:6062.105-6062.150" - cell $eq $eq$ls180.v:6062$1491 + attribute \src "ls180.v:6235.105-6235.150" + cell $eq $eq$ls180.v:6235$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251469,10 +269005,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6062$1491_Y + connect \Y $eq$ls180.v:6235$1620_Y end - attribute \src "ls180.v:6064.99-6064.144" - cell $eq $eq$ls180.v:6064$1494 + attribute \src "ls180.v:6237.99-6237.144" + cell $eq $eq$ls180.v:6237$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251480,10 +269016,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6064$1494_Y + connect \Y $eq$ls180.v:6237$1623_Y end - attribute \src "ls180.v:6065.102-6065.147" - cell $eq $eq$ls180.v:6065$1498 + attribute \src "ls180.v:6238.102-6238.147" + cell $eq $eq$ls180.v:6238$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251491,10 +269027,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6065$1498_Y + connect \Y $eq$ls180.v:6238$1627_Y end - attribute \src "ls180.v:6067.100-6067.145" - cell $eq $eq$ls180.v:6067$1501 + attribute \src "ls180.v:6240.100-6240.145" + cell $eq $eq$ls180.v:6240$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251502,10 +269038,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6067$1501_Y + connect \Y $eq$ls180.v:6240$1630_Y end - attribute \src "ls180.v:6068.103-6068.148" - cell $eq $eq$ls180.v:6068$1505 + attribute \src "ls180.v:6241.103-6241.148" + cell $eq $eq$ls180.v:6241$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251513,21 +269049,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6068$1505_Y + connect \Y $eq$ls180.v:6241$1634_Y end - attribute \src "ls180.v:6085.32-6085.78" - cell $eq $eq$ls180.v:6085$1507 + attribute \src "ls180.v:6258.32-6258.78" + cell $eq $eq$ls180.v:6258$1636 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:9] - connect \B 4'1101 - connect \Y $eq$ls180.v:6085$1507_Y + connect \A \builder_interface6_bank_bus_adr [13:8] + connect \B 4'1110 + connect \Y $eq$ls180.v:6258$1636_Y end - attribute \src "ls180.v:6087.104-6087.148" - cell $eq $eq$ls180.v:6087$1509 + attribute \src "ls180.v:6260.104-6260.148" + cell $eq $eq$ls180.v:6260$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251535,10 +269071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:6087$1509_Y + connect \Y $eq$ls180.v:6260$1638_Y end - attribute \src "ls180.v:6088.107-6088.151" - cell $eq $eq$ls180.v:6088$1513 + attribute \src "ls180.v:6261.107-6261.151" + cell $eq $eq$ls180.v:6261$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251546,10 +269082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:6088$1513_Y + connect \Y $eq$ls180.v:6261$1642_Y end - attribute \src "ls180.v:6090.104-6090.148" - cell $eq $eq$ls180.v:6090$1516 + attribute \src "ls180.v:6263.104-6263.148" + cell $eq $eq$ls180.v:6263$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251557,10 +269093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:6090$1516_Y + connect \Y $eq$ls180.v:6263$1645_Y end - attribute \src "ls180.v:6091.107-6091.151" - cell $eq $eq$ls180.v:6091$1520 + attribute \src "ls180.v:6264.107-6264.151" + cell $eq $eq$ls180.v:6264$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251568,10 +269104,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:6091$1520_Y + connect \Y $eq$ls180.v:6264$1649_Y end - attribute \src "ls180.v:6093.104-6093.148" - cell $eq $eq$ls180.v:6093$1523 + attribute \src "ls180.v:6266.104-6266.148" + cell $eq $eq$ls180.v:6266$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251579,10 +269115,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:6093$1523_Y + connect \Y $eq$ls180.v:6266$1652_Y end - attribute \src "ls180.v:6094.107-6094.151" - cell $eq $eq$ls180.v:6094$1527 + attribute \src "ls180.v:6267.107-6267.151" + cell $eq $eq$ls180.v:6267$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251590,10 +269126,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:6094$1527_Y + connect \Y $eq$ls180.v:6267$1656_Y end - attribute \src "ls180.v:6096.104-6096.148" - cell $eq $eq$ls180.v:6096$1530 + attribute \src "ls180.v:6269.104-6269.148" + cell $eq $eq$ls180.v:6269$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251601,10 +269137,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:6096$1530_Y + connect \Y $eq$ls180.v:6269$1659_Y end - attribute \src "ls180.v:6097.107-6097.151" - cell $eq $eq$ls180.v:6097$1534 + attribute \src "ls180.v:6270.107-6270.151" + cell $eq $eq$ls180.v:6270$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251612,10 +269148,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:6097$1534_Y + connect \Y $eq$ls180.v:6270$1663_Y end - attribute \src "ls180.v:6099.103-6099.147" - cell $eq $eq$ls180.v:6099$1537 + attribute \src "ls180.v:6272.103-6272.147" + cell $eq $eq$ls180.v:6272$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251623,10 +269159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:6099$1537_Y + connect \Y $eq$ls180.v:6272$1666_Y end - attribute \src "ls180.v:6100.106-6100.150" - cell $eq $eq$ls180.v:6100$1541 + attribute \src "ls180.v:6273.106-6273.150" + cell $eq $eq$ls180.v:6273$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251634,10 +269170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:6100$1541_Y + connect \Y $eq$ls180.v:6273$1670_Y end - attribute \src "ls180.v:6102.103-6102.147" - cell $eq $eq$ls180.v:6102$1544 + attribute \src "ls180.v:6275.103-6275.147" + cell $eq $eq$ls180.v:6275$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251645,10 +269181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6102$1544_Y + connect \Y $eq$ls180.v:6275$1673_Y end - attribute \src "ls180.v:6103.106-6103.150" - cell $eq $eq$ls180.v:6103$1548 + attribute \src "ls180.v:6276.106-6276.150" + cell $eq $eq$ls180.v:6276$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251656,10 +269192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6103$1548_Y + connect \Y $eq$ls180.v:6276$1677_Y end - attribute \src "ls180.v:6105.103-6105.147" - cell $eq $eq$ls180.v:6105$1551 + attribute \src "ls180.v:6278.103-6278.147" + cell $eq $eq$ls180.v:6278$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251667,10 +269203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6105$1551_Y + connect \Y $eq$ls180.v:6278$1680_Y end - attribute \src "ls180.v:6106.106-6106.150" - cell $eq $eq$ls180.v:6106$1555 + attribute \src "ls180.v:6279.106-6279.150" + cell $eq $eq$ls180.v:6279$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251678,10 +269214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6106$1555_Y + connect \Y $eq$ls180.v:6279$1684_Y end - attribute \src "ls180.v:6108.103-6108.147" - cell $eq $eq$ls180.v:6108$1558 + attribute \src "ls180.v:6281.103-6281.147" + cell $eq $eq$ls180.v:6281$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251689,10 +269225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6108$1558_Y + connect \Y $eq$ls180.v:6281$1687_Y end - attribute \src "ls180.v:6109.106-6109.150" - cell $eq $eq$ls180.v:6109$1562 + attribute \src "ls180.v:6282.106-6282.150" + cell $eq $eq$ls180.v:6282$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251700,10 +269236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6109$1562_Y + connect \Y $eq$ls180.v:6282$1691_Y end - attribute \src "ls180.v:6111.94-6111.138" - cell $eq $eq$ls180.v:6111$1565 + attribute \src "ls180.v:6284.94-6284.138" + cell $eq $eq$ls180.v:6284$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251711,10 +269247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6111$1565_Y + connect \Y $eq$ls180.v:6284$1694_Y end - attribute \src "ls180.v:6112.97-6112.141" - cell $eq $eq$ls180.v:6112$1569 + attribute \src "ls180.v:6285.97-6285.141" + cell $eq $eq$ls180.v:6285$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251722,10 +269258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6112$1569_Y + connect \Y $eq$ls180.v:6285$1698_Y end - attribute \src "ls180.v:6114.105-6114.149" - cell $eq $eq$ls180.v:6114$1572 + attribute \src "ls180.v:6287.105-6287.149" + cell $eq $eq$ls180.v:6287$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251733,10 +269269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6114$1572_Y + connect \Y $eq$ls180.v:6287$1701_Y end - attribute \src "ls180.v:6115.108-6115.152" - cell $eq $eq$ls180.v:6115$1576 + attribute \src "ls180.v:6288.108-6288.152" + cell $eq $eq$ls180.v:6288$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251744,10 +269280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6115$1576_Y + connect \Y $eq$ls180.v:6288$1705_Y end - attribute \src "ls180.v:6117.105-6117.150" - cell $eq $eq$ls180.v:6117$1579 + attribute \src "ls180.v:6290.105-6290.150" + cell $eq $eq$ls180.v:6290$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251755,10 +269291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6117$1579_Y + connect \Y $eq$ls180.v:6290$1708_Y end - attribute \src "ls180.v:6118.108-6118.153" - cell $eq $eq$ls180.v:6118$1583 + attribute \src "ls180.v:6291.108-6291.153" + cell $eq $eq$ls180.v:6291$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251766,10 +269302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6118$1583_Y + connect \Y $eq$ls180.v:6291$1712_Y end - attribute \src "ls180.v:6120.105-6120.150" - cell $eq $eq$ls180.v:6120$1586 + attribute \src "ls180.v:6293.105-6293.150" + cell $eq $eq$ls180.v:6293$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251777,10 +269313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6120$1586_Y + connect \Y $eq$ls180.v:6293$1715_Y end - attribute \src "ls180.v:6121.108-6121.153" - cell $eq $eq$ls180.v:6121$1590 + attribute \src "ls180.v:6294.108-6294.153" + cell $eq $eq$ls180.v:6294$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251788,10 +269324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6121$1590_Y + connect \Y $eq$ls180.v:6294$1719_Y end - attribute \src "ls180.v:6123.105-6123.150" - cell $eq $eq$ls180.v:6123$1593 + attribute \src "ls180.v:6296.105-6296.150" + cell $eq $eq$ls180.v:6296$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251799,10 +269335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6123$1593_Y + connect \Y $eq$ls180.v:6296$1722_Y end - attribute \src "ls180.v:6124.108-6124.153" - cell $eq $eq$ls180.v:6124$1597 + attribute \src "ls180.v:6297.108-6297.153" + cell $eq $eq$ls180.v:6297$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251810,10 +269346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6124$1597_Y + connect \Y $eq$ls180.v:6297$1726_Y end - attribute \src "ls180.v:6126.105-6126.150" - cell $eq $eq$ls180.v:6126$1600 + attribute \src "ls180.v:6299.105-6299.150" + cell $eq $eq$ls180.v:6299$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251821,10 +269357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6126$1600_Y + connect \Y $eq$ls180.v:6299$1729_Y end - attribute \src "ls180.v:6127.108-6127.153" - cell $eq $eq$ls180.v:6127$1604 + attribute \src "ls180.v:6300.108-6300.153" + cell $eq $eq$ls180.v:6300$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251832,10 +269368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6127$1604_Y + connect \Y $eq$ls180.v:6300$1733_Y end - attribute \src "ls180.v:6129.105-6129.150" - cell $eq $eq$ls180.v:6129$1607 + attribute \src "ls180.v:6302.105-6302.150" + cell $eq $eq$ls180.v:6302$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251843,10 +269379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6129$1607_Y + connect \Y $eq$ls180.v:6302$1736_Y end - attribute \src "ls180.v:6130.108-6130.153" - cell $eq $eq$ls180.v:6130$1611 + attribute \src "ls180.v:6303.108-6303.153" + cell $eq $eq$ls180.v:6303$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251854,10 +269390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6130$1611_Y + connect \Y $eq$ls180.v:6303$1740_Y end - attribute \src "ls180.v:6132.104-6132.149" - cell $eq $eq$ls180.v:6132$1614 + attribute \src "ls180.v:6305.104-6305.149" + cell $eq $eq$ls180.v:6305$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251865,10 +269401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6132$1614_Y + connect \Y $eq$ls180.v:6305$1743_Y end - attribute \src "ls180.v:6133.107-6133.152" - cell $eq $eq$ls180.v:6133$1618 + attribute \src "ls180.v:6306.107-6306.152" + cell $eq $eq$ls180.v:6306$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251876,10 +269412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6133$1618_Y + connect \Y $eq$ls180.v:6306$1747_Y end - attribute \src "ls180.v:6135.104-6135.149" - cell $eq $eq$ls180.v:6135$1621 + attribute \src "ls180.v:6308.104-6308.149" + cell $eq $eq$ls180.v:6308$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251887,10 +269423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6135$1621_Y + connect \Y $eq$ls180.v:6308$1750_Y end - attribute \src "ls180.v:6136.107-6136.152" - cell $eq $eq$ls180.v:6136$1625 + attribute \src "ls180.v:6309.107-6309.152" + cell $eq $eq$ls180.v:6309$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251898,10 +269434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6136$1625_Y + connect \Y $eq$ls180.v:6309$1754_Y end - attribute \src "ls180.v:6138.104-6138.149" - cell $eq $eq$ls180.v:6138$1628 + attribute \src "ls180.v:6311.104-6311.149" + cell $eq $eq$ls180.v:6311$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251909,10 +269445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6138$1628_Y + connect \Y $eq$ls180.v:6311$1757_Y end - attribute \src "ls180.v:6139.107-6139.152" - cell $eq $eq$ls180.v:6139$1632 + attribute \src "ls180.v:6312.107-6312.152" + cell $eq $eq$ls180.v:6312$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251920,10 +269456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6139$1632_Y + connect \Y $eq$ls180.v:6312$1761_Y end - attribute \src "ls180.v:6141.104-6141.149" - cell $eq $eq$ls180.v:6141$1635 + attribute \src "ls180.v:6314.104-6314.149" + cell $eq $eq$ls180.v:6314$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251931,10 +269467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6141$1635_Y + connect \Y $eq$ls180.v:6314$1764_Y end - attribute \src "ls180.v:6142.107-6142.152" - cell $eq $eq$ls180.v:6142$1639 + attribute \src "ls180.v:6315.107-6315.152" + cell $eq $eq$ls180.v:6315$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251942,10 +269478,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6142$1639_Y + connect \Y $eq$ls180.v:6315$1768_Y end - attribute \src "ls180.v:6144.104-6144.149" - cell $eq $eq$ls180.v:6144$1642 + attribute \src "ls180.v:6317.104-6317.149" + cell $eq $eq$ls180.v:6317$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251953,10 +269489,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6144$1642_Y + connect \Y $eq$ls180.v:6317$1771_Y end - attribute \src "ls180.v:6145.107-6145.152" - cell $eq $eq$ls180.v:6145$1646 + attribute \src "ls180.v:6318.107-6318.152" + cell $eq $eq$ls180.v:6318$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251964,10 +269500,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6145$1646_Y + connect \Y $eq$ls180.v:6318$1775_Y end - attribute \src "ls180.v:6147.104-6147.149" - cell $eq $eq$ls180.v:6147$1649 + attribute \src "ls180.v:6320.104-6320.149" + cell $eq $eq$ls180.v:6320$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251975,10 +269511,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6147$1649_Y + connect \Y $eq$ls180.v:6320$1778_Y end - attribute \src "ls180.v:6148.107-6148.152" - cell $eq $eq$ls180.v:6148$1653 + attribute \src "ls180.v:6321.107-6321.152" + cell $eq $eq$ls180.v:6321$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251986,10 +269522,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6148$1653_Y + connect \Y $eq$ls180.v:6321$1782_Y end - attribute \src "ls180.v:6150.104-6150.149" - cell $eq $eq$ls180.v:6150$1656 + attribute \src "ls180.v:6323.104-6323.149" + cell $eq $eq$ls180.v:6323$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251997,10 +269533,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6150$1656_Y + connect \Y $eq$ls180.v:6323$1785_Y end - attribute \src "ls180.v:6151.107-6151.152" - cell $eq $eq$ls180.v:6151$1660 + attribute \src "ls180.v:6324.107-6324.152" + cell $eq $eq$ls180.v:6324$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252008,10 +269544,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6151$1660_Y + connect \Y $eq$ls180.v:6324$1789_Y end - attribute \src "ls180.v:6153.104-6153.149" - cell $eq $eq$ls180.v:6153$1663 + attribute \src "ls180.v:6326.104-6326.149" + cell $eq $eq$ls180.v:6326$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252019,10 +269555,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6153$1663_Y + connect \Y $eq$ls180.v:6326$1792_Y end - attribute \src "ls180.v:6154.107-6154.152" - cell $eq $eq$ls180.v:6154$1667 + attribute \src "ls180.v:6327.107-6327.152" + cell $eq $eq$ls180.v:6327$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252030,10 +269566,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6154$1667_Y + connect \Y $eq$ls180.v:6327$1796_Y end - attribute \src "ls180.v:6156.104-6156.149" - cell $eq $eq$ls180.v:6156$1670 + attribute \src "ls180.v:6329.104-6329.149" + cell $eq $eq$ls180.v:6329$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252041,10 +269577,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6156$1670_Y + connect \Y $eq$ls180.v:6329$1799_Y end - attribute \src "ls180.v:6157.107-6157.152" - cell $eq $eq$ls180.v:6157$1674 + attribute \src "ls180.v:6330.107-6330.152" + cell $eq $eq$ls180.v:6330$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252052,10 +269588,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6157$1674_Y + connect \Y $eq$ls180.v:6330$1803_Y end - attribute \src "ls180.v:6159.104-6159.149" - cell $eq $eq$ls180.v:6159$1677 + attribute \src "ls180.v:6332.104-6332.149" + cell $eq $eq$ls180.v:6332$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252063,10 +269599,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6159$1677_Y + connect \Y $eq$ls180.v:6332$1806_Y end - attribute \src "ls180.v:6160.107-6160.152" - cell $eq $eq$ls180.v:6160$1681 + attribute \src "ls180.v:6333.107-6333.152" + cell $eq $eq$ls180.v:6333$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252074,10 +269610,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6160$1681_Y + connect \Y $eq$ls180.v:6333$1810_Y end - attribute \src "ls180.v:6162.100-6162.145" - cell $eq $eq$ls180.v:6162$1684 + attribute \src "ls180.v:6335.100-6335.145" + cell $eq $eq$ls180.v:6335$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252085,10 +269621,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6162$1684_Y + connect \Y $eq$ls180.v:6335$1813_Y end - attribute \src "ls180.v:6163.103-6163.148" - cell $eq $eq$ls180.v:6163$1688 + attribute \src "ls180.v:6336.103-6336.148" + cell $eq $eq$ls180.v:6336$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252096,10 +269632,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6163$1688_Y + connect \Y $eq$ls180.v:6336$1817_Y end - attribute \src "ls180.v:6165.101-6165.146" - cell $eq $eq$ls180.v:6165$1691 + attribute \src "ls180.v:6338.101-6338.146" + cell $eq $eq$ls180.v:6338$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252107,10 +269643,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6165$1691_Y + connect \Y $eq$ls180.v:6338$1820_Y end - attribute \src "ls180.v:6166.104-6166.149" - cell $eq $eq$ls180.v:6166$1695 + attribute \src "ls180.v:6339.104-6339.149" + cell $eq $eq$ls180.v:6339$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252118,10 +269654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6166$1695_Y + connect \Y $eq$ls180.v:6339$1824_Y end - attribute \src "ls180.v:6168.104-6168.149" - cell $eq $eq$ls180.v:6168$1698 + attribute \src "ls180.v:6341.104-6341.149" + cell $eq $eq$ls180.v:6341$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252129,10 +269665,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6168$1698_Y + connect \Y $eq$ls180.v:6341$1827_Y end - attribute \src "ls180.v:6169.107-6169.152" - cell $eq $eq$ls180.v:6169$1702 + attribute \src "ls180.v:6342.107-6342.152" + cell $eq $eq$ls180.v:6342$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252140,10 +269676,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6169$1702_Y + connect \Y $eq$ls180.v:6342$1831_Y end - attribute \src "ls180.v:6171.104-6171.149" - cell $eq $eq$ls180.v:6171$1705 + attribute \src "ls180.v:6344.104-6344.149" + cell $eq $eq$ls180.v:6344$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252151,10 +269687,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6171$1705_Y + connect \Y $eq$ls180.v:6344$1834_Y end - attribute \src "ls180.v:6172.107-6172.152" - cell $eq $eq$ls180.v:6172$1709 + attribute \src "ls180.v:6345.107-6345.152" + cell $eq $eq$ls180.v:6345$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252162,10 +269698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6172$1709_Y + connect \Y $eq$ls180.v:6345$1838_Y end - attribute \src "ls180.v:6174.103-6174.148" - cell $eq $eq$ls180.v:6174$1712 + attribute \src "ls180.v:6347.103-6347.148" + cell $eq $eq$ls180.v:6347$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252173,10 +269709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6174$1712_Y + connect \Y $eq$ls180.v:6347$1841_Y end - attribute \src "ls180.v:6175.106-6175.151" - cell $eq $eq$ls180.v:6175$1716 + attribute \src "ls180.v:6348.106-6348.151" + cell $eq $eq$ls180.v:6348$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252184,10 +269720,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6175$1716_Y + connect \Y $eq$ls180.v:6348$1845_Y end - attribute \src "ls180.v:6177.103-6177.148" - cell $eq $eq$ls180.v:6177$1719 + attribute \src "ls180.v:6350.103-6350.148" + cell $eq $eq$ls180.v:6350$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252195,10 +269731,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6177$1719_Y + connect \Y $eq$ls180.v:6350$1848_Y end - attribute \src "ls180.v:6178.106-6178.151" - cell $eq $eq$ls180.v:6178$1723 + attribute \src "ls180.v:6351.106-6351.151" + cell $eq $eq$ls180.v:6351$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252206,10 +269742,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6178$1723_Y + connect \Y $eq$ls180.v:6351$1852_Y end - attribute \src "ls180.v:6180.103-6180.148" - cell $eq $eq$ls180.v:6180$1726 + attribute \src "ls180.v:6353.103-6353.148" + cell $eq $eq$ls180.v:6353$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252217,10 +269753,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6180$1726_Y + connect \Y $eq$ls180.v:6353$1855_Y end - attribute \src "ls180.v:6181.106-6181.151" - cell $eq $eq$ls180.v:6181$1730 + attribute \src "ls180.v:6354.106-6354.151" + cell $eq $eq$ls180.v:6354$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252228,10 +269764,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6181$1730_Y + connect \Y $eq$ls180.v:6354$1859_Y end - attribute \src "ls180.v:6183.103-6183.148" - cell $eq $eq$ls180.v:6183$1733 + attribute \src "ls180.v:6356.103-6356.148" + cell $eq $eq$ls180.v:6356$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252239,10 +269775,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6183$1733_Y + connect \Y $eq$ls180.v:6356$1862_Y end - attribute \src "ls180.v:6184.106-6184.151" - cell $eq $eq$ls180.v:6184$1737 + attribute \src "ls180.v:6357.106-6357.151" + cell $eq $eq$ls180.v:6357$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252250,21 +269786,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6184$1737_Y + connect \Y $eq$ls180.v:6357$1866_Y end - attribute \src "ls180.v:6220.32-6220.78" - cell $eq $eq$ls180.v:6220$1739 + attribute \src "ls180.v:6393.32-6393.78" + cell $eq $eq$ls180.v:6393$1868 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:9] - connect \B 4'1111 - connect \Y $eq$ls180.v:6220$1739_Y + connect \A \builder_interface7_bank_bus_adr [13:8] + connect \B 5'10000 + connect \Y $eq$ls180.v:6393$1868_Y end - attribute \src "ls180.v:6222.100-6222.144" - cell $eq $eq$ls180.v:6222$1741 + attribute \src "ls180.v:6395.100-6395.144" + cell $eq $eq$ls180.v:6395$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252272,10 +269808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6222$1741_Y + connect \Y $eq$ls180.v:6395$1870_Y end - attribute \src "ls180.v:6223.103-6223.147" - cell $eq $eq$ls180.v:6223$1745 + attribute \src "ls180.v:6396.103-6396.147" + cell $eq $eq$ls180.v:6396$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252283,10 +269819,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6223$1745_Y + connect \Y $eq$ls180.v:6396$1874_Y end - attribute \src "ls180.v:6225.100-6225.144" - cell $eq $eq$ls180.v:6225$1748 + attribute \src "ls180.v:6398.100-6398.144" + cell $eq $eq$ls180.v:6398$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252294,10 +269830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6225$1748_Y + connect \Y $eq$ls180.v:6398$1877_Y end - attribute \src "ls180.v:6226.103-6226.147" - cell $eq $eq$ls180.v:6226$1752 + attribute \src "ls180.v:6399.103-6399.147" + cell $eq $eq$ls180.v:6399$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252305,10 +269841,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6226$1752_Y + connect \Y $eq$ls180.v:6399$1881_Y end - attribute \src "ls180.v:6228.100-6228.144" - cell $eq $eq$ls180.v:6228$1755 + attribute \src "ls180.v:6401.100-6401.144" + cell $eq $eq$ls180.v:6401$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252316,10 +269852,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6228$1755_Y + connect \Y $eq$ls180.v:6401$1884_Y end - attribute \src "ls180.v:6229.103-6229.147" - cell $eq $eq$ls180.v:6229$1759 + attribute \src "ls180.v:6402.103-6402.147" + cell $eq $eq$ls180.v:6402$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252327,10 +269863,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6229$1759_Y + connect \Y $eq$ls180.v:6402$1888_Y end - attribute \src "ls180.v:6231.100-6231.144" - cell $eq $eq$ls180.v:6231$1762 + attribute \src "ls180.v:6404.100-6404.144" + cell $eq $eq$ls180.v:6404$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252338,10 +269874,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6231$1762_Y + connect \Y $eq$ls180.v:6404$1891_Y end - attribute \src "ls180.v:6232.103-6232.147" - cell $eq $eq$ls180.v:6232$1766 + attribute \src "ls180.v:6405.103-6405.147" + cell $eq $eq$ls180.v:6405$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252349,10 +269885,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6232$1766_Y + connect \Y $eq$ls180.v:6405$1895_Y end - attribute \src "ls180.v:6234.100-6234.144" - cell $eq $eq$ls180.v:6234$1769 + attribute \src "ls180.v:6407.100-6407.144" + cell $eq $eq$ls180.v:6407$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252360,10 +269896,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6234$1769_Y + connect \Y $eq$ls180.v:6407$1898_Y end - attribute \src "ls180.v:6235.103-6235.147" - cell $eq $eq$ls180.v:6235$1773 + attribute \src "ls180.v:6408.103-6408.147" + cell $eq $eq$ls180.v:6408$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252371,10 +269907,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6235$1773_Y + connect \Y $eq$ls180.v:6408$1902_Y end - attribute \src "ls180.v:6237.100-6237.144" - cell $eq $eq$ls180.v:6237$1776 + attribute \src "ls180.v:6410.100-6410.144" + cell $eq $eq$ls180.v:6410$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252382,10 +269918,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6237$1776_Y + connect \Y $eq$ls180.v:6410$1905_Y end - attribute \src "ls180.v:6238.103-6238.147" - cell $eq $eq$ls180.v:6238$1780 + attribute \src "ls180.v:6411.103-6411.147" + cell $eq $eq$ls180.v:6411$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252393,10 +269929,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6238$1780_Y + connect \Y $eq$ls180.v:6411$1909_Y end - attribute \src "ls180.v:6240.100-6240.144" - cell $eq $eq$ls180.v:6240$1783 + attribute \src "ls180.v:6413.100-6413.144" + cell $eq $eq$ls180.v:6413$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252404,10 +269940,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6240$1783_Y + connect \Y $eq$ls180.v:6413$1912_Y end - attribute \src "ls180.v:6241.103-6241.147" - cell $eq $eq$ls180.v:6241$1787 + attribute \src "ls180.v:6414.103-6414.147" + cell $eq $eq$ls180.v:6414$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252415,10 +269951,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6241$1787_Y + connect \Y $eq$ls180.v:6414$1916_Y end - attribute \src "ls180.v:6243.100-6243.144" - cell $eq $eq$ls180.v:6243$1790 + attribute \src "ls180.v:6416.100-6416.144" + cell $eq $eq$ls180.v:6416$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252426,10 +269962,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6243$1790_Y + connect \Y $eq$ls180.v:6416$1919_Y end - attribute \src "ls180.v:6244.103-6244.147" - cell $eq $eq$ls180.v:6244$1794 + attribute \src "ls180.v:6417.103-6417.147" + cell $eq $eq$ls180.v:6417$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252437,10 +269973,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6244$1794_Y + connect \Y $eq$ls180.v:6417$1923_Y end - attribute \src "ls180.v:6246.102-6246.146" - cell $eq $eq$ls180.v:6246$1797 + attribute \src "ls180.v:6419.102-6419.146" + cell $eq $eq$ls180.v:6419$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252448,10 +269984,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6246$1797_Y + connect \Y $eq$ls180.v:6419$1926_Y end - attribute \src "ls180.v:6247.105-6247.149" - cell $eq $eq$ls180.v:6247$1801 + attribute \src "ls180.v:6420.105-6420.149" + cell $eq $eq$ls180.v:6420$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252459,10 +269995,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6247$1801_Y + connect \Y $eq$ls180.v:6420$1930_Y end - attribute \src "ls180.v:6249.102-6249.146" - cell $eq $eq$ls180.v:6249$1804 + attribute \src "ls180.v:6422.102-6422.146" + cell $eq $eq$ls180.v:6422$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252470,10 +270006,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6249$1804_Y + connect \Y $eq$ls180.v:6422$1933_Y end - attribute \src "ls180.v:6250.105-6250.149" - cell $eq $eq$ls180.v:6250$1808 + attribute \src "ls180.v:6423.105-6423.149" + cell $eq $eq$ls180.v:6423$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252481,10 +270017,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6250$1808_Y + connect \Y $eq$ls180.v:6423$1937_Y end - attribute \src "ls180.v:6252.102-6252.147" - cell $eq $eq$ls180.v:6252$1811 + attribute \src "ls180.v:6425.102-6425.147" + cell $eq $eq$ls180.v:6425$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252492,10 +270028,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6252$1811_Y + connect \Y $eq$ls180.v:6425$1940_Y end - attribute \src "ls180.v:6253.105-6253.150" - cell $eq $eq$ls180.v:6253$1815 + attribute \src "ls180.v:6426.105-6426.150" + cell $eq $eq$ls180.v:6426$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252503,10 +270039,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6253$1815_Y + connect \Y $eq$ls180.v:6426$1944_Y end - attribute \src "ls180.v:6255.102-6255.147" - cell $eq $eq$ls180.v:6255$1818 + attribute \src "ls180.v:6428.102-6428.147" + cell $eq $eq$ls180.v:6428$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252514,10 +270050,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6255$1818_Y + connect \Y $eq$ls180.v:6428$1947_Y end - attribute \src "ls180.v:6256.105-6256.150" - cell $eq $eq$ls180.v:6256$1822 + attribute \src "ls180.v:6429.105-6429.150" + cell $eq $eq$ls180.v:6429$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252525,10 +270061,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6256$1822_Y + connect \Y $eq$ls180.v:6429$1951_Y end - attribute \src "ls180.v:6258.102-6258.147" - cell $eq $eq$ls180.v:6258$1825 + attribute \src "ls180.v:6431.102-6431.147" + cell $eq $eq$ls180.v:6431$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252536,10 +270072,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6258$1825_Y + connect \Y $eq$ls180.v:6431$1954_Y end - attribute \src "ls180.v:6259.105-6259.150" - cell $eq $eq$ls180.v:6259$1829 + attribute \src "ls180.v:6432.105-6432.150" + cell $eq $eq$ls180.v:6432$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252547,10 +270083,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6259$1829_Y + connect \Y $eq$ls180.v:6432$1958_Y end - attribute \src "ls180.v:6261.99-6261.144" - cell $eq $eq$ls180.v:6261$1832 + attribute \src "ls180.v:6434.99-6434.144" + cell $eq $eq$ls180.v:6434$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252558,10 +270094,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6261$1832_Y + connect \Y $eq$ls180.v:6434$1961_Y end - attribute \src "ls180.v:6262.102-6262.147" - cell $eq $eq$ls180.v:6262$1836 + attribute \src "ls180.v:6435.102-6435.147" + cell $eq $eq$ls180.v:6435$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252569,10 +270105,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6262$1836_Y + connect \Y $eq$ls180.v:6435$1965_Y end - attribute \src "ls180.v:6264.100-6264.145" - cell $eq $eq$ls180.v:6264$1839 + attribute \src "ls180.v:6437.100-6437.145" + cell $eq $eq$ls180.v:6437$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252580,10 +270116,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6264$1839_Y + connect \Y $eq$ls180.v:6437$1968_Y end - attribute \src "ls180.v:6265.103-6265.148" - cell $eq $eq$ls180.v:6265$1843 + attribute \src "ls180.v:6438.103-6438.148" + cell $eq $eq$ls180.v:6438$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252591,10 +270127,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6265$1843_Y + connect \Y $eq$ls180.v:6438$1972_Y end - attribute \src "ls180.v:6267.102-6267.147" - cell $eq $eq$ls180.v:6267$1846 + attribute \src "ls180.v:6440.102-6440.147" + cell $eq $eq$ls180.v:6440$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252602,10 +270138,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6267$1846_Y + connect \Y $eq$ls180.v:6440$1975_Y end - attribute \src "ls180.v:6268.105-6268.150" - cell $eq $eq$ls180.v:6268$1850 + attribute \src "ls180.v:6441.105-6441.150" + cell $eq $eq$ls180.v:6441$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252613,10 +270149,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6268$1850_Y + connect \Y $eq$ls180.v:6441$1979_Y end - attribute \src "ls180.v:6270.102-6270.147" - cell $eq $eq$ls180.v:6270$1853 + attribute \src "ls180.v:6443.102-6443.147" + cell $eq $eq$ls180.v:6443$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252624,10 +270160,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6270$1853_Y + connect \Y $eq$ls180.v:6443$1982_Y end - attribute \src "ls180.v:6271.105-6271.150" - cell $eq $eq$ls180.v:6271$1857 + attribute \src "ls180.v:6444.105-6444.150" + cell $eq $eq$ls180.v:6444$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252635,10 +270171,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6271$1857_Y + connect \Y $eq$ls180.v:6444$1986_Y end - attribute \src "ls180.v:6273.102-6273.147" - cell $eq $eq$ls180.v:6273$1860 + attribute \src "ls180.v:6446.102-6446.147" + cell $eq $eq$ls180.v:6446$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252646,10 +270182,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6273$1860_Y + connect \Y $eq$ls180.v:6446$1989_Y end - attribute \src "ls180.v:6274.105-6274.150" - cell $eq $eq$ls180.v:6274$1864 + attribute \src "ls180.v:6447.105-6447.150" + cell $eq $eq$ls180.v:6447$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252657,10 +270193,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6274$1864_Y + connect \Y $eq$ls180.v:6447$1993_Y end - attribute \src "ls180.v:6276.102-6276.147" - cell $eq $eq$ls180.v:6276$1867 + attribute \src "ls180.v:6449.102-6449.147" + cell $eq $eq$ls180.v:6449$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252668,10 +270204,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6276$1867_Y + connect \Y $eq$ls180.v:6449$1996_Y end - attribute \src "ls180.v:6277.105-6277.150" - cell $eq $eq$ls180.v:6277$1871 + attribute \src "ls180.v:6450.105-6450.150" + cell $eq $eq$ls180.v:6450$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252679,21 +270215,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6277$1871_Y + connect \Y $eq$ls180.v:6450$2000_Y end - attribute \src "ls180.v:6299.32-6299.78" - cell $eq $eq$ls180.v:6299$1873 + attribute \src "ls180.v:6472.32-6472.78" + cell $eq $eq$ls180.v:6472$2002 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:9] - connect \B 4'1100 - connect \Y $eq$ls180.v:6299$1873_Y + connect \A \builder_interface8_bank_bus_adr [13:8] + connect \B 4'1101 + connect \Y $eq$ls180.v:6472$2002_Y end - attribute \src "ls180.v:6301.102-6301.146" - cell $eq $eq$ls180.v:6301$1875 + attribute \src "ls180.v:6474.102-6474.146" + cell $eq $eq$ls180.v:6474$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252701,10 +270237,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6301$1875_Y + connect \Y $eq$ls180.v:6474$2004_Y end - attribute \src "ls180.v:6302.105-6302.149" - cell $eq $eq$ls180.v:6302$1879 + attribute \src "ls180.v:6475.105-6475.149" + cell $eq $eq$ls180.v:6475$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252712,10 +270248,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6302$1879_Y + connect \Y $eq$ls180.v:6475$2008_Y end - attribute \src "ls180.v:6304.107-6304.151" - cell $eq $eq$ls180.v:6304$1882 + attribute \src "ls180.v:6477.107-6477.151" + cell $eq $eq$ls180.v:6477$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252723,10 +270259,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6304$1882_Y + connect \Y $eq$ls180.v:6477$2011_Y end - attribute \src "ls180.v:6305.110-6305.154" - cell $eq $eq$ls180.v:6305$1886 + attribute \src "ls180.v:6478.110-6478.154" + cell $eq $eq$ls180.v:6478$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252734,10 +270270,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6305$1886_Y + connect \Y $eq$ls180.v:6478$2015_Y end - attribute \src "ls180.v:6307.107-6307.151" - cell $eq $eq$ls180.v:6307$1889 + attribute \src "ls180.v:6480.107-6480.151" + cell $eq $eq$ls180.v:6480$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252745,10 +270281,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6307$1889_Y + connect \Y $eq$ls180.v:6480$2018_Y end - attribute \src "ls180.v:6308.110-6308.154" - cell $eq $eq$ls180.v:6308$1893 + attribute \src "ls180.v:6481.110-6481.154" + cell $eq $eq$ls180.v:6481$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252756,10 +270292,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6308$1893_Y + connect \Y $eq$ls180.v:6481$2022_Y end - attribute \src "ls180.v:6310.100-6310.144" - cell $eq $eq$ls180.v:6310$1896 + attribute \src "ls180.v:6483.100-6483.144" + cell $eq $eq$ls180.v:6483$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252767,10 +270303,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6310$1896_Y + connect \Y $eq$ls180.v:6483$2025_Y end - attribute \src "ls180.v:6311.103-6311.147" - cell $eq $eq$ls180.v:6311$1900 + attribute \src "ls180.v:6484.103-6484.147" + cell $eq $eq$ls180.v:6484$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252778,21 +270314,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6311$1900_Y + connect \Y $eq$ls180.v:6484$2029_Y end - attribute \src "ls180.v:6316.32-6316.77" - cell $eq $eq$ls180.v:6316$1902 + attribute \src "ls180.v:6489.32-6489.77" + cell $eq $eq$ls180.v:6489$2031 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:9] + connect \A \builder_interface9_bank_bus_adr [13:8] connect \B 2'11 - connect \Y $eq$ls180.v:6316$1902_Y + connect \Y $eq$ls180.v:6489$2031_Y end - attribute \src "ls180.v:6318.104-6318.148" - cell $eq $eq$ls180.v:6318$1904 + attribute \src "ls180.v:6491.104-6491.148" + cell $eq $eq$ls180.v:6491$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252800,10 +270336,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6318$1904_Y + connect \Y $eq$ls180.v:6491$2033_Y end - attribute \src "ls180.v:6319.107-6319.151" - cell $eq $eq$ls180.v:6319$1908 + attribute \src "ls180.v:6492.107-6492.151" + cell $eq $eq$ls180.v:6492$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252811,10 +270347,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6319$1908_Y + connect \Y $eq$ls180.v:6492$2037_Y end - attribute \src "ls180.v:6321.108-6321.152" - cell $eq $eq$ls180.v:6321$1911 + attribute \src "ls180.v:6494.108-6494.152" + cell $eq $eq$ls180.v:6494$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252822,10 +270358,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6321$1911_Y + connect \Y $eq$ls180.v:6494$2040_Y end - attribute \src "ls180.v:6322.111-6322.155" - cell $eq $eq$ls180.v:6322$1915 + attribute \src "ls180.v:6495.111-6495.155" + cell $eq $eq$ls180.v:6495$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252833,10 +270369,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6322$1915_Y + connect \Y $eq$ls180.v:6495$2044_Y end - attribute \src "ls180.v:6324.98-6324.142" - cell $eq $eq$ls180.v:6324$1918 + attribute \src "ls180.v:6497.98-6497.142" + cell $eq $eq$ls180.v:6497$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252844,10 +270380,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6324$1918_Y + connect \Y $eq$ls180.v:6497$2047_Y end - attribute \src "ls180.v:6325.101-6325.145" - cell $eq $eq$ls180.v:6325$1922 + attribute \src "ls180.v:6498.101-6498.145" + cell $eq $eq$ls180.v:6498$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252855,10 +270391,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6325$1922_Y + connect \Y $eq$ls180.v:6498$2051_Y end - attribute \src "ls180.v:6327.108-6327.152" - cell $eq $eq$ls180.v:6327$1925 + attribute \src "ls180.v:6500.108-6500.152" + cell $eq $eq$ls180.v:6500$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252866,10 +270402,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6327$1925_Y + connect \Y $eq$ls180.v:6500$2054_Y end - attribute \src "ls180.v:6328.111-6328.155" - cell $eq $eq$ls180.v:6328$1929 + attribute \src "ls180.v:6501.111-6501.155" + cell $eq $eq$ls180.v:6501$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252877,10 +270413,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6328$1929_Y + connect \Y $eq$ls180.v:6501$2058_Y end - attribute \src "ls180.v:6330.108-6330.152" - cell $eq $eq$ls180.v:6330$1932 + attribute \src "ls180.v:6503.108-6503.152" + cell $eq $eq$ls180.v:6503$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252888,10 +270424,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6330$1932_Y + connect \Y $eq$ls180.v:6503$2061_Y end - attribute \src "ls180.v:6331.111-6331.155" - cell $eq $eq$ls180.v:6331$1936 + attribute \src "ls180.v:6504.111-6504.155" + cell $eq $eq$ls180.v:6504$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252899,10 +270435,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6331$1936_Y + connect \Y $eq$ls180.v:6504$2065_Y end - attribute \src "ls180.v:6333.109-6333.153" - cell $eq $eq$ls180.v:6333$1939 + attribute \src "ls180.v:6506.109-6506.153" + cell $eq $eq$ls180.v:6506$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252910,10 +270446,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6333$1939_Y + connect \Y $eq$ls180.v:6506$2068_Y end - attribute \src "ls180.v:6334.112-6334.156" - cell $eq $eq$ls180.v:6334$1943 + attribute \src "ls180.v:6507.112-6507.156" + cell $eq $eq$ls180.v:6507$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252921,10 +270457,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6334$1943_Y + connect \Y $eq$ls180.v:6507$2072_Y end - attribute \src "ls180.v:6336.107-6336.151" - cell $eq $eq$ls180.v:6336$1946 + attribute \src "ls180.v:6509.107-6509.151" + cell $eq $eq$ls180.v:6509$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252932,10 +270468,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6336$1946_Y + connect \Y $eq$ls180.v:6509$2075_Y end - attribute \src "ls180.v:6337.110-6337.154" - cell $eq $eq$ls180.v:6337$1950 + attribute \src "ls180.v:6510.110-6510.154" + cell $eq $eq$ls180.v:6510$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252943,10 +270479,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6337$1950_Y + connect \Y $eq$ls180.v:6510$2079_Y end - attribute \src "ls180.v:6339.107-6339.151" - cell $eq $eq$ls180.v:6339$1953 + attribute \src "ls180.v:6512.107-6512.151" + cell $eq $eq$ls180.v:6512$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252954,10 +270490,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6339$1953_Y + connect \Y $eq$ls180.v:6512$2082_Y end - attribute \src "ls180.v:6340.110-6340.154" - cell $eq $eq$ls180.v:6340$1957 + attribute \src "ls180.v:6513.110-6513.154" + cell $eq $eq$ls180.v:6513$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252965,10 +270501,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6340$1957_Y + connect \Y $eq$ls180.v:6513$2086_Y end - attribute \src "ls180.v:6342.107-6342.151" - cell $eq $eq$ls180.v:6342$1960 + attribute \src "ls180.v:6515.107-6515.151" + cell $eq $eq$ls180.v:6515$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252976,10 +270512,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6342$1960_Y + connect \Y $eq$ls180.v:6515$2089_Y end - attribute \src "ls180.v:6343.110-6343.154" - cell $eq $eq$ls180.v:6343$1964 + attribute \src "ls180.v:6516.110-6516.154" + cell $eq $eq$ls180.v:6516$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252987,10 +270523,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6343$1964_Y + connect \Y $eq$ls180.v:6516$2093_Y end - attribute \src "ls180.v:6345.107-6345.151" - cell $eq $eq$ls180.v:6345$1967 + attribute \src "ls180.v:6518.107-6518.151" + cell $eq $eq$ls180.v:6518$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252998,10 +270534,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6345$1967_Y + connect \Y $eq$ls180.v:6518$2096_Y end - attribute \src "ls180.v:6346.110-6346.154" - cell $eq $eq$ls180.v:6346$1971 + attribute \src "ls180.v:6519.110-6519.154" + cell $eq $eq$ls180.v:6519$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253009,21 +270545,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6346$1971_Y + connect \Y $eq$ls180.v:6519$2100_Y end - attribute \src "ls180.v:6361.33-6361.79" - cell $eq $eq$ls180.v:6361$1973 + attribute \src "ls180.v:6534.33-6534.79" + cell $eq $eq$ls180.v:6534$2102 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:9] - connect \B 3'111 - connect \Y $eq$ls180.v:6361$1973_Y + connect \A \builder_interface10_bank_bus_adr [13:8] + connect \B 4'1000 + connect \Y $eq$ls180.v:6534$2102_Y end - attribute \src "ls180.v:6363.102-6363.147" - cell $eq $eq$ls180.v:6363$1975 + attribute \src "ls180.v:6536.102-6536.147" + cell $eq $eq$ls180.v:6536$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253031,10 +270567,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6363$1975_Y + connect \Y $eq$ls180.v:6536$2104_Y end - attribute \src "ls180.v:6364.105-6364.150" - cell $eq $eq$ls180.v:6364$1979 + attribute \src "ls180.v:6537.105-6537.150" + cell $eq $eq$ls180.v:6537$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253042,10 +270578,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6364$1979_Y + connect \Y $eq$ls180.v:6537$2108_Y end - attribute \src "ls180.v:6366.102-6366.147" - cell $eq $eq$ls180.v:6366$1982 + attribute \src "ls180.v:6539.102-6539.147" + cell $eq $eq$ls180.v:6539$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253053,10 +270589,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6366$1982_Y + connect \Y $eq$ls180.v:6539$2111_Y end - attribute \src "ls180.v:6367.105-6367.150" - cell $eq $eq$ls180.v:6367$1986 + attribute \src "ls180.v:6540.105-6540.150" + cell $eq $eq$ls180.v:6540$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253064,10 +270600,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6367$1986_Y + connect \Y $eq$ls180.v:6540$2115_Y end - attribute \src "ls180.v:6369.100-6369.145" - cell $eq $eq$ls180.v:6369$1989 + attribute \src "ls180.v:6542.100-6542.145" + cell $eq $eq$ls180.v:6542$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253075,10 +270611,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6369$1989_Y + connect \Y $eq$ls180.v:6542$2118_Y end - attribute \src "ls180.v:6370.103-6370.148" - cell $eq $eq$ls180.v:6370$1993 + attribute \src "ls180.v:6543.103-6543.148" + cell $eq $eq$ls180.v:6543$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253086,10 +270622,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6370$1993_Y + connect \Y $eq$ls180.v:6543$2122_Y end - attribute \src "ls180.v:6372.99-6372.144" - cell $eq $eq$ls180.v:6372$1996 + attribute \src "ls180.v:6545.99-6545.144" + cell $eq $eq$ls180.v:6545$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253097,10 +270633,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6372$1996_Y + connect \Y $eq$ls180.v:6545$2125_Y end - attribute \src "ls180.v:6373.102-6373.147" - cell $eq $eq$ls180.v:6373$2000 + attribute \src "ls180.v:6546.102-6546.147" + cell $eq $eq$ls180.v:6546$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253108,10 +270644,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6373$2000_Y + connect \Y $eq$ls180.v:6546$2129_Y end - attribute \src "ls180.v:6375.98-6375.143" - cell $eq $eq$ls180.v:6375$2003 + attribute \src "ls180.v:6548.98-6548.143" + cell $eq $eq$ls180.v:6548$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253119,10 +270655,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6375$2003_Y + connect \Y $eq$ls180.v:6548$2132_Y end - attribute \src "ls180.v:6376.101-6376.146" - cell $eq $eq$ls180.v:6376$2007 + attribute \src "ls180.v:6549.101-6549.146" + cell $eq $eq$ls180.v:6549$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253130,10 +270666,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6376$2007_Y + connect \Y $eq$ls180.v:6549$2136_Y end - attribute \src "ls180.v:6378.97-6378.142" - cell $eq $eq$ls180.v:6378$2010 + attribute \src "ls180.v:6551.97-6551.142" + cell $eq $eq$ls180.v:6551$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253141,10 +270677,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6378$2010_Y + connect \Y $eq$ls180.v:6551$2139_Y end - attribute \src "ls180.v:6379.100-6379.145" - cell $eq $eq$ls180.v:6379$2014 + attribute \src "ls180.v:6552.100-6552.145" + cell $eq $eq$ls180.v:6552$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253152,10 +270688,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6379$2014_Y + connect \Y $eq$ls180.v:6552$2143_Y end - attribute \src "ls180.v:6381.103-6381.148" - cell $eq $eq$ls180.v:6381$2017 + attribute \src "ls180.v:6554.103-6554.148" + cell $eq $eq$ls180.v:6554$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253163,10 +270699,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6381$2017_Y + connect \Y $eq$ls180.v:6554$2146_Y end - attribute \src "ls180.v:6382.106-6382.151" - cell $eq $eq$ls180.v:6382$2021 + attribute \src "ls180.v:6555.106-6555.151" + cell $eq $eq$ls180.v:6555$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253174,21 +270710,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6382$2021_Y + connect \Y $eq$ls180.v:6555$2150_Y end - attribute \src "ls180.v:6401.33-6401.79" - cell $eq $eq$ls180.v:6401$2024 + attribute \src "ls180.v:6574.33-6574.79" + cell $eq $eq$ls180.v:6574$2153 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:9] - connect \B 4'1000 - connect \Y $eq$ls180.v:6401$2024_Y + connect \A \builder_interface11_bank_bus_adr [13:8] + connect \B 4'1001 + connect \Y $eq$ls180.v:6574$2153_Y end - attribute \src "ls180.v:6403.102-6403.147" - cell $eq $eq$ls180.v:6403$2026 + attribute \src "ls180.v:6576.102-6576.147" + cell $eq $eq$ls180.v:6576$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253196,10 +270732,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6403$2026_Y + connect \Y $eq$ls180.v:6576$2155_Y end - attribute \src "ls180.v:6404.105-6404.150" - cell $eq $eq$ls180.v:6404$2030 + attribute \src "ls180.v:6577.105-6577.150" + cell $eq $eq$ls180.v:6577$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253207,10 +270743,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6404$2030_Y + connect \Y $eq$ls180.v:6577$2159_Y end - attribute \src "ls180.v:6406.102-6406.147" - cell $eq $eq$ls180.v:6406$2033 + attribute \src "ls180.v:6579.102-6579.147" + cell $eq $eq$ls180.v:6579$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253218,10 +270754,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6406$2033_Y + connect \Y $eq$ls180.v:6579$2162_Y end - attribute \src "ls180.v:6407.105-6407.150" - cell $eq $eq$ls180.v:6407$2037 + attribute \src "ls180.v:6580.105-6580.150" + cell $eq $eq$ls180.v:6580$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253229,10 +270765,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6407$2037_Y + connect \Y $eq$ls180.v:6580$2166_Y end - attribute \src "ls180.v:6409.100-6409.145" - cell $eq $eq$ls180.v:6409$2040 + attribute \src "ls180.v:6582.100-6582.145" + cell $eq $eq$ls180.v:6582$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253240,10 +270776,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6409$2040_Y + connect \Y $eq$ls180.v:6582$2169_Y end - attribute \src "ls180.v:6410.103-6410.148" - cell $eq $eq$ls180.v:6410$2044 + attribute \src "ls180.v:6583.103-6583.148" + cell $eq $eq$ls180.v:6583$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253251,10 +270787,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6410$2044_Y + connect \Y $eq$ls180.v:6583$2173_Y end - attribute \src "ls180.v:6412.99-6412.144" - cell $eq $eq$ls180.v:6412$2047 + attribute \src "ls180.v:6585.99-6585.144" + cell $eq $eq$ls180.v:6585$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253262,10 +270798,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6412$2047_Y + connect \Y $eq$ls180.v:6585$2176_Y end - attribute \src "ls180.v:6413.102-6413.147" - cell $eq $eq$ls180.v:6413$2051 + attribute \src "ls180.v:6586.102-6586.147" + cell $eq $eq$ls180.v:6586$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253273,10 +270809,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6413$2051_Y + connect \Y $eq$ls180.v:6586$2180_Y end - attribute \src "ls180.v:6415.98-6415.143" - cell $eq $eq$ls180.v:6415$2054 + attribute \src "ls180.v:6588.98-6588.143" + cell $eq $eq$ls180.v:6588$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253284,10 +270820,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6415$2054_Y + connect \Y $eq$ls180.v:6588$2183_Y end - attribute \src "ls180.v:6416.101-6416.146" - cell $eq $eq$ls180.v:6416$2058 + attribute \src "ls180.v:6589.101-6589.146" + cell $eq $eq$ls180.v:6589$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253295,10 +270831,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6416$2058_Y + connect \Y $eq$ls180.v:6589$2187_Y end - attribute \src "ls180.v:6418.97-6418.142" - cell $eq $eq$ls180.v:6418$2061 + attribute \src "ls180.v:6591.97-6591.142" + cell $eq $eq$ls180.v:6591$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253306,10 +270842,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6418$2061_Y + connect \Y $eq$ls180.v:6591$2190_Y end - attribute \src "ls180.v:6419.100-6419.145" - cell $eq $eq$ls180.v:6419$2065 + attribute \src "ls180.v:6592.100-6592.145" + cell $eq $eq$ls180.v:6592$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253317,10 +270853,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6419$2065_Y + connect \Y $eq$ls180.v:6592$2194_Y end - attribute \src "ls180.v:6421.103-6421.148" - cell $eq $eq$ls180.v:6421$2068 + attribute \src "ls180.v:6594.103-6594.148" + cell $eq $eq$ls180.v:6594$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253328,10 +270864,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6421$2068_Y + connect \Y $eq$ls180.v:6594$2197_Y end - attribute \src "ls180.v:6422.106-6422.151" - cell $eq $eq$ls180.v:6422$2072 + attribute \src "ls180.v:6595.106-6595.151" + cell $eq $eq$ls180.v:6595$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253339,10 +270875,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6422$2072_Y + connect \Y $eq$ls180.v:6595$2201_Y end - attribute \src "ls180.v:6424.106-6424.151" - cell $eq $eq$ls180.v:6424$2075 + attribute \src "ls180.v:6597.106-6597.151" + cell $eq $eq$ls180.v:6597$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253350,10 +270886,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6424$2075_Y + connect \Y $eq$ls180.v:6597$2204_Y end - attribute \src "ls180.v:6425.109-6425.154" - cell $eq $eq$ls180.v:6425$2079 + attribute \src "ls180.v:6598.109-6598.154" + cell $eq $eq$ls180.v:6598$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253361,10 +270897,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6425$2079_Y + connect \Y $eq$ls180.v:6598$2208_Y end - attribute \src "ls180.v:6427.106-6427.151" - cell $eq $eq$ls180.v:6427$2082 + attribute \src "ls180.v:6600.106-6600.151" + cell $eq $eq$ls180.v:6600$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253372,10 +270908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6427$2082_Y + connect \Y $eq$ls180.v:6600$2211_Y end - attribute \src "ls180.v:6428.109-6428.154" - cell $eq $eq$ls180.v:6428$2086 + attribute \src "ls180.v:6601.109-6601.154" + cell $eq $eq$ls180.v:6601$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253383,21 +270919,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6428$2086_Y + connect \Y $eq$ls180.v:6601$2215_Y end - attribute \src "ls180.v:6449.33-6449.79" - cell $eq $eq$ls180.v:6449$2089 + attribute \src "ls180.v:6622.33-6622.79" + cell $eq $eq$ls180.v:6622$2218 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:9] + connect \A \builder_interface12_bank_bus_adr [13:8] connect \B 2'10 - connect \Y $eq$ls180.v:6449$2089_Y + connect \Y $eq$ls180.v:6622$2218_Y end - attribute \src "ls180.v:6451.99-6451.144" - cell $eq $eq$ls180.v:6451$2091 + attribute \src "ls180.v:6624.99-6624.144" + cell $eq $eq$ls180.v:6624$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253405,10 +270941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6451$2091_Y + connect \Y $eq$ls180.v:6624$2220_Y end - attribute \src "ls180.v:6452.102-6452.147" - cell $eq $eq$ls180.v:6452$2095 + attribute \src "ls180.v:6625.102-6625.147" + cell $eq $eq$ls180.v:6625$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253416,10 +270952,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6452$2095_Y + connect \Y $eq$ls180.v:6625$2224_Y end - attribute \src "ls180.v:6454.99-6454.144" - cell $eq $eq$ls180.v:6454$2098 + attribute \src "ls180.v:6627.99-6627.144" + cell $eq $eq$ls180.v:6627$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253427,10 +270963,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6454$2098_Y + connect \Y $eq$ls180.v:6627$2227_Y end - attribute \src "ls180.v:6455.102-6455.147" - cell $eq $eq$ls180.v:6455$2102 + attribute \src "ls180.v:6628.102-6628.147" + cell $eq $eq$ls180.v:6628$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253438,10 +270974,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6455$2102_Y + connect \Y $eq$ls180.v:6628$2231_Y end - attribute \src "ls180.v:6457.99-6457.144" - cell $eq $eq$ls180.v:6457$2105 + attribute \src "ls180.v:6630.99-6630.144" + cell $eq $eq$ls180.v:6630$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253449,10 +270985,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6457$2105_Y + connect \Y $eq$ls180.v:6630$2234_Y end - attribute \src "ls180.v:6458.102-6458.147" - cell $eq $eq$ls180.v:6458$2109 + attribute \src "ls180.v:6631.102-6631.147" + cell $eq $eq$ls180.v:6631$2238 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253460,10 +270996,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6458$2109_Y + connect \Y $eq$ls180.v:6631$2238_Y end - attribute \src "ls180.v:6460.99-6460.144" - cell $eq $eq$ls180.v:6460$2112 + attribute \src "ls180.v:6633.99-6633.144" + cell $eq $eq$ls180.v:6633$2241 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253471,10 +271007,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6460$2112_Y + connect \Y $eq$ls180.v:6633$2241_Y end - attribute \src "ls180.v:6461.102-6461.147" - cell $eq $eq$ls180.v:6461$2116 + attribute \src "ls180.v:6634.102-6634.147" + cell $eq $eq$ls180.v:6634$2245 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253482,10 +271018,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6461$2116_Y + connect \Y $eq$ls180.v:6634$2245_Y end - attribute \src "ls180.v:6463.101-6463.146" - cell $eq $eq$ls180.v:6463$2119 + attribute \src "ls180.v:6636.101-6636.146" + cell $eq $eq$ls180.v:6636$2248 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253493,10 +271029,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6463$2119_Y + connect \Y $eq$ls180.v:6636$2248_Y end - attribute \src "ls180.v:6464.104-6464.149" - cell $eq $eq$ls180.v:6464$2123 + attribute \src "ls180.v:6637.104-6637.149" + cell $eq $eq$ls180.v:6637$2252 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253504,10 +271040,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6464$2123_Y + connect \Y $eq$ls180.v:6637$2252_Y end - attribute \src "ls180.v:6466.101-6466.146" - cell $eq $eq$ls180.v:6466$2126 + attribute \src "ls180.v:6639.101-6639.146" + cell $eq $eq$ls180.v:6639$2255 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253515,10 +271051,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6466$2126_Y + connect \Y $eq$ls180.v:6639$2255_Y end - attribute \src "ls180.v:6467.104-6467.149" - cell $eq $eq$ls180.v:6467$2130 + attribute \src "ls180.v:6640.104-6640.149" + cell $eq $eq$ls180.v:6640$2259 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253526,10 +271062,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6467$2130_Y + connect \Y $eq$ls180.v:6640$2259_Y end - attribute \src "ls180.v:6469.101-6469.146" - cell $eq $eq$ls180.v:6469$2133 + attribute \src "ls180.v:6642.101-6642.146" + cell $eq $eq$ls180.v:6642$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253537,10 +271073,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6469$2133_Y + connect \Y $eq$ls180.v:6642$2262_Y end - attribute \src "ls180.v:6470.104-6470.149" - cell $eq $eq$ls180.v:6470$2137 + attribute \src "ls180.v:6643.104-6643.149" + cell $eq $eq$ls180.v:6643$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253548,10 +271084,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6470$2137_Y + connect \Y $eq$ls180.v:6643$2266_Y end - attribute \src "ls180.v:6472.101-6472.146" - cell $eq $eq$ls180.v:6472$2140 + attribute \src "ls180.v:6645.101-6645.146" + cell $eq $eq$ls180.v:6645$2269 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253559,10 +271095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6472$2140_Y + connect \Y $eq$ls180.v:6645$2269_Y end - attribute \src "ls180.v:6473.104-6473.149" - cell $eq $eq$ls180.v:6473$2144 + attribute \src "ls180.v:6646.104-6646.149" + cell $eq $eq$ls180.v:6646$2273 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253570,10 +271106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6473$2144_Y + connect \Y $eq$ls180.v:6646$2273_Y end - attribute \src "ls180.v:6475.97-6475.142" - cell $eq $eq$ls180.v:6475$2147 + attribute \src "ls180.v:6648.97-6648.142" + cell $eq $eq$ls180.v:6648$2276 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253581,10 +271117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6475$2147_Y + connect \Y $eq$ls180.v:6648$2276_Y end - attribute \src "ls180.v:6476.100-6476.145" - cell $eq $eq$ls180.v:6476$2151 + attribute \src "ls180.v:6649.100-6649.145" + cell $eq $eq$ls180.v:6649$2280 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253592,10 +271128,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6476$2151_Y + connect \Y $eq$ls180.v:6649$2280_Y end - attribute \src "ls180.v:6478.107-6478.152" - cell $eq $eq$ls180.v:6478$2154 + attribute \src "ls180.v:6651.107-6651.152" + cell $eq $eq$ls180.v:6651$2283 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253603,10 +271139,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6478$2154_Y + connect \Y $eq$ls180.v:6651$2283_Y end - attribute \src "ls180.v:6479.110-6479.155" - cell $eq $eq$ls180.v:6479$2158 + attribute \src "ls180.v:6652.110-6652.155" + cell $eq $eq$ls180.v:6652$2287 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253614,10 +271150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6479$2158_Y + connect \Y $eq$ls180.v:6652$2287_Y end - attribute \src "ls180.v:6481.100-6481.146" - cell $eq $eq$ls180.v:6481$2161 + attribute \src "ls180.v:6654.100-6654.146" + cell $eq $eq$ls180.v:6654$2290 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253625,10 +271161,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6481$2161_Y + connect \Y $eq$ls180.v:6654$2290_Y end - attribute \src "ls180.v:6482.103-6482.149" - cell $eq $eq$ls180.v:6482$2165 + attribute \src "ls180.v:6655.103-6655.149" + cell $eq $eq$ls180.v:6655$2294 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253636,10 +271172,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6482$2165_Y + connect \Y $eq$ls180.v:6655$2294_Y end - attribute \src "ls180.v:6484.100-6484.146" - cell $eq $eq$ls180.v:6484$2168 + attribute \src "ls180.v:6657.100-6657.146" + cell $eq $eq$ls180.v:6657$2297 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253647,10 +271183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6484$2168_Y + connect \Y $eq$ls180.v:6657$2297_Y end - attribute \src "ls180.v:6485.103-6485.149" - cell $eq $eq$ls180.v:6485$2172 + attribute \src "ls180.v:6658.103-6658.149" + cell $eq $eq$ls180.v:6658$2301 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253658,10 +271194,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6485$2172_Y + connect \Y $eq$ls180.v:6658$2301_Y end - attribute \src "ls180.v:6487.100-6487.146" - cell $eq $eq$ls180.v:6487$2175 + attribute \src "ls180.v:6660.100-6660.146" + cell $eq $eq$ls180.v:6660$2304 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253669,10 +271205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6487$2175_Y + connect \Y $eq$ls180.v:6660$2304_Y end - attribute \src "ls180.v:6488.103-6488.149" - cell $eq $eq$ls180.v:6488$2179 + attribute \src "ls180.v:6661.103-6661.149" + cell $eq $eq$ls180.v:6661$2308 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253680,10 +271216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6488$2179_Y + connect \Y $eq$ls180.v:6661$2308_Y end - attribute \src "ls180.v:6490.100-6490.146" - cell $eq $eq$ls180.v:6490$2182 + attribute \src "ls180.v:6663.100-6663.146" + cell $eq $eq$ls180.v:6663$2311 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253691,10 +271227,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6490$2182_Y + connect \Y $eq$ls180.v:6663$2311_Y end - attribute \src "ls180.v:6491.103-6491.149" - cell $eq $eq$ls180.v:6491$2186 + attribute \src "ls180.v:6664.103-6664.149" + cell $eq $eq$ls180.v:6664$2315 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253702,10 +271238,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6491$2186_Y + connect \Y $eq$ls180.v:6664$2315_Y end - attribute \src "ls180.v:6493.112-6493.158" - cell $eq $eq$ls180.v:6493$2189 + attribute \src "ls180.v:6666.112-6666.158" + cell $eq $eq$ls180.v:6666$2318 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253713,10 +271249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6493$2189_Y + connect \Y $eq$ls180.v:6666$2318_Y end - attribute \src "ls180.v:6494.115-6494.161" - cell $eq $eq$ls180.v:6494$2193 + attribute \src "ls180.v:6667.115-6667.161" + cell $eq $eq$ls180.v:6667$2322 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253724,10 +271260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6494$2193_Y + connect \Y $eq$ls180.v:6667$2322_Y end - attribute \src "ls180.v:6496.113-6496.159" - cell $eq $eq$ls180.v:6496$2196 + attribute \src "ls180.v:6669.113-6669.159" + cell $eq $eq$ls180.v:6669$2325 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253735,10 +271271,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6496$2196_Y + connect \Y $eq$ls180.v:6669$2325_Y end - attribute \src "ls180.v:6497.116-6497.162" - cell $eq $eq$ls180.v:6497$2200 + attribute \src "ls180.v:6670.116-6670.162" + cell $eq $eq$ls180.v:6670$2329 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253746,10 +271282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6497$2200_Y + connect \Y $eq$ls180.v:6670$2329_Y end - attribute \src "ls180.v:6499.104-6499.150" - cell $eq $eq$ls180.v:6499$2203 + attribute \src "ls180.v:6672.104-6672.150" + cell $eq $eq$ls180.v:6672$2332 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253757,10 +271293,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6499$2203_Y + connect \Y $eq$ls180.v:6672$2332_Y end - attribute \src "ls180.v:6500.107-6500.153" - cell $eq $eq$ls180.v:6500$2207 + attribute \src "ls180.v:6673.107-6673.153" + cell $eq $eq$ls180.v:6673$2336 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253768,21 +271304,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6500$2207_Y + connect \Y $eq$ls180.v:6673$2336_Y end - attribute \src "ls180.v:6517.33-6517.79" - cell $eq $eq$ls180.v:6517$2209 + attribute \src "ls180.v:6690.33-6690.79" + cell $eq $eq$ls180.v:6690$2338 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:9] + connect \A \builder_interface13_bank_bus_adr [13:8] connect \B 3'101 - connect \Y $eq$ls180.v:6517$2209_Y + connect \Y $eq$ls180.v:6690$2338_Y end - attribute \src "ls180.v:6519.90-6519.135" - cell $eq $eq$ls180.v:6519$2211 + attribute \src "ls180.v:6692.90-6692.135" + cell $eq $eq$ls180.v:6692$2340 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253790,10 +271326,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6519$2211_Y + connect \Y $eq$ls180.v:6692$2340_Y end - attribute \src "ls180.v:6520.93-6520.138" - cell $eq $eq$ls180.v:6520$2215 + attribute \src "ls180.v:6693.93-6693.138" + cell $eq $eq$ls180.v:6693$2344 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253801,10 +271337,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6520$2215_Y + connect \Y $eq$ls180.v:6693$2344_Y end - attribute \src "ls180.v:6522.100-6522.145" - cell $eq $eq$ls180.v:6522$2218 + attribute \src "ls180.v:6695.100-6695.145" + cell $eq $eq$ls180.v:6695$2347 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253812,10 +271348,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6522$2218_Y + connect \Y $eq$ls180.v:6695$2347_Y end - attribute \src "ls180.v:6523.103-6523.148" - cell $eq $eq$ls180.v:6523$2222 + attribute \src "ls180.v:6696.103-6696.148" + cell $eq $eq$ls180.v:6696$2351 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253823,10 +271359,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6523$2222_Y + connect \Y $eq$ls180.v:6696$2351_Y end - attribute \src "ls180.v:6525.101-6525.146" - cell $eq $eq$ls180.v:6525$2225 + attribute \src "ls180.v:6698.101-6698.146" + cell $eq $eq$ls180.v:6698$2354 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253834,10 +271370,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6525$2225_Y + connect \Y $eq$ls180.v:6698$2354_Y end - attribute \src "ls180.v:6526.104-6526.149" - cell $eq $eq$ls180.v:6526$2229 + attribute \src "ls180.v:6699.104-6699.149" + cell $eq $eq$ls180.v:6699$2358 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253845,10 +271381,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6526$2229_Y + connect \Y $eq$ls180.v:6699$2358_Y end - attribute \src "ls180.v:6528.105-6528.150" - cell $eq $eq$ls180.v:6528$2232 + attribute \src "ls180.v:6701.105-6701.150" + cell $eq $eq$ls180.v:6701$2361 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253856,10 +271392,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6528$2232_Y + connect \Y $eq$ls180.v:6701$2361_Y end - attribute \src "ls180.v:6529.108-6529.153" - cell $eq $eq$ls180.v:6529$2236 + attribute \src "ls180.v:6702.108-6702.153" + cell $eq $eq$ls180.v:6702$2365 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253867,10 +271403,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6529$2236_Y + connect \Y $eq$ls180.v:6702$2365_Y end - attribute \src "ls180.v:6531.106-6531.151" - cell $eq $eq$ls180.v:6531$2239 + attribute \src "ls180.v:6704.106-6704.151" + cell $eq $eq$ls180.v:6704$2368 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253878,10 +271414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6531$2239_Y + connect \Y $eq$ls180.v:6704$2368_Y end - attribute \src "ls180.v:6532.109-6532.154" - cell $eq $eq$ls180.v:6532$2243 + attribute \src "ls180.v:6705.109-6705.154" + cell $eq $eq$ls180.v:6705$2372 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253889,10 +271425,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6532$2243_Y + connect \Y $eq$ls180.v:6705$2372_Y end - attribute \src "ls180.v:6534.104-6534.149" - cell $eq $eq$ls180.v:6534$2246 + attribute \src "ls180.v:6707.104-6707.149" + cell $eq $eq$ls180.v:6707$2375 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253900,10 +271436,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6534$2246_Y + connect \Y $eq$ls180.v:6707$2375_Y end - attribute \src "ls180.v:6535.107-6535.152" - cell $eq $eq$ls180.v:6535$2250 + attribute \src "ls180.v:6708.107-6708.152" + cell $eq $eq$ls180.v:6708$2379 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253911,10 +271447,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6535$2250_Y + connect \Y $eq$ls180.v:6708$2379_Y end - attribute \src "ls180.v:6537.101-6537.146" - cell $eq $eq$ls180.v:6537$2253 + attribute \src "ls180.v:6710.101-6710.146" + cell $eq $eq$ls180.v:6710$2382 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253922,10 +271458,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6537$2253_Y + connect \Y $eq$ls180.v:6710$2382_Y end - attribute \src "ls180.v:6538.104-6538.149" - cell $eq $eq$ls180.v:6538$2257 + attribute \src "ls180.v:6711.104-6711.149" + cell $eq $eq$ls180.v:6711$2386 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253933,10 +271469,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6538$2257_Y + connect \Y $eq$ls180.v:6711$2386_Y end - attribute \src "ls180.v:6540.100-6540.145" - cell $eq $eq$ls180.v:6540$2260 + attribute \src "ls180.v:6713.100-6713.145" + cell $eq $eq$ls180.v:6713$2389 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253944,10 +271480,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6540$2260_Y + connect \Y $eq$ls180.v:6713$2389_Y end - attribute \src "ls180.v:6541.103-6541.148" - cell $eq $eq$ls180.v:6541$2264 + attribute \src "ls180.v:6714.103-6714.148" + cell $eq $eq$ls180.v:6714$2393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253955,21 +271491,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6541$2264_Y + connect \Y $eq$ls180.v:6714$2393_Y end - attribute \src "ls180.v:6551.33-6551.79" - cell $eq $eq$ls180.v:6551$2266 + attribute \src "ls180.v:6724.33-6724.79" + cell $eq $eq$ls180.v:6724$2395 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [13:9] + connect \A \builder_interface14_bank_bus_adr [13:8] connect \B 3'100 - connect \Y $eq$ls180.v:6551$2266_Y + connect \Y $eq$ls180.v:6724$2395_Y end - attribute \src "ls180.v:6553.106-6553.151" - cell $eq $eq$ls180.v:6553$2268 + attribute \src "ls180.v:6726.106-6726.151" + cell $eq $eq$ls180.v:6726$2397 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253977,10 +271513,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6553$2268_Y + connect \Y $eq$ls180.v:6726$2397_Y end - attribute \src "ls180.v:6554.109-6554.154" - cell $eq $eq$ls180.v:6554$2272 + attribute \src "ls180.v:6727.109-6727.154" + cell $eq $eq$ls180.v:6727$2401 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253988,10 +271524,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6554$2272_Y + connect \Y $eq$ls180.v:6727$2401_Y end - attribute \src "ls180.v:6556.106-6556.151" - cell $eq $eq$ls180.v:6556$2275 + attribute \src "ls180.v:6729.106-6729.151" + cell $eq $eq$ls180.v:6729$2404 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253999,10 +271535,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6556$2275_Y + connect \Y $eq$ls180.v:6729$2404_Y end - attribute \src "ls180.v:6557.109-6557.154" - cell $eq $eq$ls180.v:6557$2279 + attribute \src "ls180.v:6730.109-6730.154" + cell $eq $eq$ls180.v:6730$2408 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254010,10 +271546,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6557$2279_Y + connect \Y $eq$ls180.v:6730$2408_Y end - attribute \src "ls180.v:6559.106-6559.151" - cell $eq $eq$ls180.v:6559$2282 + attribute \src "ls180.v:6732.106-6732.151" + cell $eq $eq$ls180.v:6732$2411 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254021,10 +271557,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6559$2282_Y + connect \Y $eq$ls180.v:6732$2411_Y end - attribute \src "ls180.v:6560.109-6560.154" - cell $eq $eq$ls180.v:6560$2286 + attribute \src "ls180.v:6733.109-6733.154" + cell $eq $eq$ls180.v:6733$2415 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254032,10 +271568,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6560$2286_Y + connect \Y $eq$ls180.v:6733$2415_Y end - attribute \src "ls180.v:6562.106-6562.151" - cell $eq $eq$ls180.v:6562$2289 + attribute \src "ls180.v:6735.106-6735.151" + cell $eq $eq$ls180.v:6735$2418 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254043,10 +271579,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6562$2289_Y + connect \Y $eq$ls180.v:6735$2418_Y end - attribute \src "ls180.v:6563.109-6563.154" - cell $eq $eq$ls180.v:6563$2293 + attribute \src "ls180.v:6736.109-6736.154" + cell $eq $eq$ls180.v:6736$2422 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254054,10 +271590,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6563$2293_Y + connect \Y $eq$ls180.v:6736$2422_Y end - attribute \src "ls180.v:6944.41-6944.81" - cell $eq $eq$ls180.v:6944$2330 + attribute \src "ls180.v:7117.41-7117.81" + cell $eq $eq$ls180.v:7117$2459 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254065,10 +271601,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:6944$2330_Y + connect \Y $eq$ls180.v:7117$2459_Y end - attribute \src "ls180.v:6944.144-6944.177" - cell $eq $eq$ls180.v:6944$2331 + attribute \src "ls180.v:7117.144-7117.177" + cell $eq $eq$ls180.v:7117$2460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254076,10 +271612,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6944$2331_Y + connect \Y $eq$ls180.v:7117$2460_Y end - attribute \src "ls180.v:6944.219-6944.252" - cell $eq $eq$ls180.v:6944$2334 + attribute \src "ls180.v:7117.219-7117.252" + cell $eq $eq$ls180.v:7117$2463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254087,10 +271623,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6944$2334_Y + connect \Y $eq$ls180.v:7117$2463_Y end - attribute \src "ls180.v:6944.294-6944.327" - cell $eq $eq$ls180.v:6944$2337 + attribute \src "ls180.v:7117.294-7117.327" + cell $eq $eq$ls180.v:7117$2466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254098,10 +271634,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6944$2337_Y + connect \Y $eq$ls180.v:7117$2466_Y end - attribute \src "ls180.v:6968.41-6968.81" - cell $eq $eq$ls180.v:6968$2346 + attribute \src "ls180.v:7141.41-7141.81" + cell $eq $eq$ls180.v:7141$2475 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254109,10 +271645,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:6968$2346_Y + connect \Y $eq$ls180.v:7141$2475_Y end - attribute \src "ls180.v:6968.144-6968.177" - cell $eq $eq$ls180.v:6968$2347 + attribute \src "ls180.v:7141.144-7141.177" + cell $eq $eq$ls180.v:7141$2476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254120,10 +271656,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6968$2347_Y + connect \Y $eq$ls180.v:7141$2476_Y end - attribute \src "ls180.v:6968.219-6968.252" - cell $eq $eq$ls180.v:6968$2350 + attribute \src "ls180.v:7141.219-7141.252" + cell $eq $eq$ls180.v:7141$2479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254131,10 +271667,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6968$2350_Y + connect \Y $eq$ls180.v:7141$2479_Y end - attribute \src "ls180.v:6968.294-6968.327" - cell $eq $eq$ls180.v:6968$2353 + attribute \src "ls180.v:7141.294-7141.327" + cell $eq $eq$ls180.v:7141$2482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254142,10 +271678,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6968$2353_Y + connect \Y $eq$ls180.v:7141$2482_Y end - attribute \src "ls180.v:6992.41-6992.81" - cell $eq $eq$ls180.v:6992$2362 + attribute \src "ls180.v:7165.41-7165.81" + cell $eq $eq$ls180.v:7165$2491 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254153,10 +271689,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:6992$2362_Y + connect \Y $eq$ls180.v:7165$2491_Y end - attribute \src "ls180.v:6992.144-6992.177" - cell $eq $eq$ls180.v:6992$2363 + attribute \src "ls180.v:7165.144-7165.177" + cell $eq $eq$ls180.v:7165$2492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254164,10 +271700,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6992$2363_Y + connect \Y $eq$ls180.v:7165$2492_Y end - attribute \src "ls180.v:6992.219-6992.252" - cell $eq $eq$ls180.v:6992$2366 + attribute \src "ls180.v:7165.219-7165.252" + cell $eq $eq$ls180.v:7165$2495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254175,10 +271711,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6992$2366_Y + connect \Y $eq$ls180.v:7165$2495_Y end - attribute \src "ls180.v:6992.294-6992.327" - cell $eq $eq$ls180.v:6992$2369 + attribute \src "ls180.v:7165.294-7165.327" + cell $eq $eq$ls180.v:7165$2498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254186,10 +271722,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6992$2369_Y + connect \Y $eq$ls180.v:7165$2498_Y end - attribute \src "ls180.v:7016.41-7016.81" - cell $eq $eq$ls180.v:7016$2378 + attribute \src "ls180.v:7189.41-7189.81" + cell $eq $eq$ls180.v:7189$2507 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254197,10 +271733,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:7016$2378_Y + connect \Y $eq$ls180.v:7189$2507_Y end - attribute \src "ls180.v:7016.144-7016.177" - cell $eq $eq$ls180.v:7016$2379 + attribute \src "ls180.v:7189.144-7189.177" + cell $eq $eq$ls180.v:7189$2508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254208,10 +271744,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7016$2379_Y + connect \Y $eq$ls180.v:7189$2508_Y end - attribute \src "ls180.v:7016.219-7016.252" - cell $eq $eq$ls180.v:7016$2382 + attribute \src "ls180.v:7189.219-7189.252" + cell $eq $eq$ls180.v:7189$2511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254219,10 +271755,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7016$2382_Y + connect \Y $eq$ls180.v:7189$2511_Y end - attribute \src "ls180.v:7016.294-7016.327" - cell $eq $eq$ls180.v:7016$2385 + attribute \src "ls180.v:7189.294-7189.327" + cell $eq $eq$ls180.v:7189$2514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254230,10 +271766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7016$2385_Y + connect \Y $eq$ls180.v:7189$2514_Y end - attribute \src "ls180.v:7597.8-7597.38" - cell $eq $eq$ls180.v:7597$2476 + attribute \src "ls180.v:7773.8-7773.38" + cell $eq $eq$ls180.v:7773$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254241,10 +271777,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7597$2476_Y + connect \Y $eq$ls180.v:7773$2606_Y end - attribute \src "ls180.v:7640.8-7640.42" - cell $eq $eq$ls180.v:7640$2493 + attribute \src "ls180.v:7820.8-7820.42" + cell $eq $eq$ls180.v:7820$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254252,10 +271788,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7640$2493_Y + connect \Y $eq$ls180.v:7820$2626_Y end - attribute \src "ls180.v:7660.38-7660.74" - cell $eq $eq$ls180.v:7660$2496 + attribute \src "ls180.v:7840.38-7840.74" + cell $eq $eq$ls180.v:7840$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254263,10 +271799,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7660$2496_Y + connect \Y $eq$ls180.v:7840$2629_Y end - attribute \src "ls180.v:7667.7-7667.43" - cell $eq $eq$ls180.v:7667$2498 + attribute \src "ls180.v:7847.7-7847.43" + cell $eq $eq$ls180.v:7847$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254274,10 +271810,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7667$2498_Y + connect \Y $eq$ls180.v:7847$2631_Y end - attribute \src "ls180.v:7674.7-7674.43" - cell $eq $eq$ls180.v:7674$2499 + attribute \src "ls180.v:7854.7-7854.43" + cell $eq $eq$ls180.v:7854$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254285,10 +271821,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7674$2499_Y + connect \Y $eq$ls180.v:7854$2632_Y end - attribute \src "ls180.v:7682.7-7682.43" - cell $eq $eq$ls180.v:7682$2500 + attribute \src "ls180.v:7862.7-7862.43" + cell $eq $eq$ls180.v:7862$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254296,10 +271832,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7682$2500_Y + connect \Y $eq$ls180.v:7862$2633_Y end - attribute \src "ls180.v:7734.9-7734.54" - cell $eq $eq$ls180.v:7734$2518 + attribute \src "ls180.v:7914.9-7914.54" + cell $eq $eq$ls180.v:7914$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254307,10 +271843,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7734$2518_Y + connect \Y $eq$ls180.v:7914$2651_Y end - attribute \src "ls180.v:7780.9-7780.54" - cell $eq $eq$ls180.v:7780$2534 + attribute \src "ls180.v:7960.9-7960.54" + cell $eq $eq$ls180.v:7960$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254318,10 +271854,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7780$2534_Y + connect \Y $eq$ls180.v:7960$2667_Y end - attribute \src "ls180.v:7826.9-7826.54" - cell $eq $eq$ls180.v:7826$2550 + attribute \src "ls180.v:8006.9-8006.54" + cell $eq $eq$ls180.v:8006$2683 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254329,10 +271865,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7826$2550_Y + connect \Y $eq$ls180.v:8006$2683_Y end - attribute \src "ls180.v:7872.9-7872.54" - cell $eq $eq$ls180.v:7872$2566 + attribute \src "ls180.v:8052.9-8052.54" + cell $eq $eq$ls180.v:8052$2699 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254340,10 +271876,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7872$2566_Y + connect \Y $eq$ls180.v:8052$2699_Y end - attribute \src "ls180.v:8022.9-8022.41" - cell $eq $eq$ls180.v:8022$2578 + attribute \src "ls180.v:8202.9-8202.41" + cell $eq $eq$ls180.v:8202$2711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254351,10 +271887,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8022$2578_Y + connect \Y $eq$ls180.v:8202$2711_Y end - attribute \src "ls180.v:8037.9-8037.41" - cell $eq $eq$ls180.v:8037$2581 + attribute \src "ls180.v:8217.9-8217.41" + cell $eq $eq$ls180.v:8217$2714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254362,10 +271898,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8037$2581_Y + connect \Y $eq$ls180.v:8217$2714_Y end - attribute \src "ls180.v:8043.49-8043.82" - cell $eq $eq$ls180.v:8043$2582 + attribute \src "ls180.v:8223.49-8223.82" + cell $eq $eq$ls180.v:8223$2715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254373,10 +271909,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8043$2582_Y + connect \Y $eq$ls180.v:8223$2715_Y end - attribute \src "ls180.v:8043.131-8043.164" - cell $eq $eq$ls180.v:8043$2585 + attribute \src "ls180.v:8223.131-8223.164" + cell $eq $eq$ls180.v:8223$2718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254384,10 +271920,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8043$2585_Y + connect \Y $eq$ls180.v:8223$2718_Y end - attribute \src "ls180.v:8043.213-8043.246" - cell $eq $eq$ls180.v:8043$2588 + attribute \src "ls180.v:8223.213-8223.246" + cell $eq $eq$ls180.v:8223$2721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254395,10 +271931,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8043$2588_Y + connect \Y $eq$ls180.v:8223$2721_Y end - attribute \src "ls180.v:8043.295-8043.328" - cell $eq $eq$ls180.v:8043$2591 + attribute \src "ls180.v:8223.295-8223.328" + cell $eq $eq$ls180.v:8223$2724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254406,10 +271942,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8043$2591_Y + connect \Y $eq$ls180.v:8223$2724_Y end - attribute \src "ls180.v:8044.50-8044.83" - cell $eq $eq$ls180.v:8044$2594 + attribute \src "ls180.v:8224.50-8224.83" + cell $eq $eq$ls180.v:8224$2727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254417,10 +271953,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8044$2594_Y + connect \Y $eq$ls180.v:8224$2727_Y end - attribute \src "ls180.v:8044.132-8044.165" - cell $eq $eq$ls180.v:8044$2597 + attribute \src "ls180.v:8224.132-8224.165" + cell $eq $eq$ls180.v:8224$2730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254428,10 +271964,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8044$2597_Y + connect \Y $eq$ls180.v:8224$2730_Y end - attribute \src "ls180.v:8044.214-8044.247" - cell $eq $eq$ls180.v:8044$2600 + attribute \src "ls180.v:8224.214-8224.247" + cell $eq $eq$ls180.v:8224$2733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254439,10 +271975,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8044$2600_Y + connect \Y $eq$ls180.v:8224$2733_Y end - attribute \src "ls180.v:8044.296-8044.329" - cell $eq $eq$ls180.v:8044$2603 + attribute \src "ls180.v:8224.296-8224.329" + cell $eq $eq$ls180.v:8224$2736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254450,10 +271986,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8044$2603_Y + connect \Y $eq$ls180.v:8224$2736_Y end - attribute \src "ls180.v:8079.9-8079.42" - cell $eq $eq$ls180.v:8079$2615 + attribute \src "ls180.v:8259.9-8259.42" + cell $eq $eq$ls180.v:8259$2748 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254461,10 +271997,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:8079$2615_Y + connect \Y $eq$ls180.v:8259$2748_Y end - attribute \src "ls180.v:8082.10-8082.43" - cell $eq $eq$ls180.v:8082$2616 + attribute \src "ls180.v:8262.10-8262.43" + cell $eq $eq$ls180.v:8262$2749 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254472,10 +272008,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8082$2616_Y + connect \Y $eq$ls180.v:8262$2749_Y end - attribute \src "ls180.v:8108.9-8108.42" - cell $eq $eq$ls180.v:8108$2622 + attribute \src "ls180.v:8288.9-8288.42" + cell $eq $eq$ls180.v:8288$2755 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254483,10 +272019,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:8108$2622_Y + connect \Y $eq$ls180.v:8288$2755_Y end - attribute \src "ls180.v:8113.10-8113.43" - cell $eq $eq$ls180.v:8113$2623 + attribute \src "ls180.v:8293.10-8293.43" + cell $eq $eq$ls180.v:8293$2756 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254494,10 +272030,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8113$2623_Y + connect \Y $eq$ls180.v:8293$2756_Y end - attribute \src "ls180.v:8320.9-8320.53" - cell $eq $eq$ls180.v:8320$2672 + attribute \src "ls180.v:8500.9-8500.53" + cell $eq $eq$ls180.v:8500$2805 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254505,10 +272041,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8320$2672_Y + connect \Y $eq$ls180.v:8500$2805_Y end - attribute \src "ls180.v:8401.9-8401.54" - cell $eq $eq$ls180.v:8401$2684 + attribute \src "ls180.v:8581.9-8581.54" + cell $eq $eq$ls180.v:8581$2817 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254516,10 +272052,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8401$2684_Y + connect \Y $eq$ls180.v:8581$2817_Y end - attribute \src "ls180.v:8480.9-8480.55" - cell $eq $eq$ls180.v:8480$2696 + attribute \src "ls180.v:8660.9-8660.55" + cell $eq $eq$ls180.v:8660$2829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254527,43 +272063,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8480$2696_Y + connect \Y $eq$ls180.v:8660$2829_Y end - attribute \src "ls180.v:8703.9-8703.49" - cell $eq $eq$ls180.v:8703$2729 + attribute \src "ls180.v:8883.9-8883.49" + cell $eq $eq$ls180.v:8883$2862 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux - connect \B 2'11 - connect \Y $eq$ls180.v:8703$2729_Y + connect \B 3'111 + connect \Y $eq$ls180.v:8883$2862_Y end - attribute \src "ls180.v:8279.8-8279.54" - cell $ge $ge$ls180.v:8279$2664 + attribute \src "ls180.v:8459.8-8459.54" + cell $ge $ge$ls180.v:8459$2797 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8279$2663_Y - connect \Y $ge$ls180.v:8279$2664_Y + connect \B $sub$ls180.v:8459$2796_Y + connect \Y $ge$ls180.v:8459$2797_Y end - attribute \src "ls180.v:8293.8-8293.54" - cell $ge $ge$ls180.v:8293$2668 + attribute \src "ls180.v:8473.8-8473.54" + cell $ge $ge$ls180.v:8473$2801 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8293$2667_Y - connect \Y $ge$ls180.v:8293$2668_Y + connect \B $sub$ls180.v:8473$2800_Y + connect \Y $ge$ls180.v:8473$2801_Y end - attribute \src "ls180.v:5226.47-5226.83" - cell $gt $gt$ls180.v:5226$965 + attribute \src "ls180.v:5342.47-5342.83" + cell $gt $gt$ls180.v:5342$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254571,10 +272107,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $gt$ls180.v:5226$965_Y + connect \Y $gt$ls180.v:5342$1064_Y end - attribute \src "ls180.v:5232.7-5232.43" - cell $lt $lt$ls180.v:5232$968 + attribute \src "ls180.v:5348.7-5348.43" + cell $lt $lt$ls180.v:5348$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254582,10 +272118,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1000 - connect \Y $lt$ls180.v:5232$968_Y + connect \Y $lt$ls180.v:5348$1067_Y end - attribute \src "ls180.v:8274.8-8274.43" - cell $lt $lt$ls180.v:8274$2662 + attribute \src "ls180.v:8454.8-8454.43" + cell $lt $lt$ls180.v:8454$2795 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254593,10 +272129,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8274$2662_Y + connect \Y $lt$ls180.v:8454$2795_Y end - attribute \src "ls180.v:8288.8-8288.43" - cell $lt $lt$ls180.v:8288$2666 + attribute \src "ls180.v:8468.8-8468.43" + cell $lt $lt$ls180.v:8468$2799 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254604,62 +272140,75 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8288$2666_Y + connect \Y $lt$ls180.v:8468$2799_Y end - attribute \src "ls180.v:10172.33-10172.36" - cell $memrd $memrd$\mem$ls180.v:10172$2771 - parameter \ABITS 7 + attribute \src "ls180.v:10373.33-10373.36" + cell $memrd $memrd$\mem$ls180.v:10373$2916 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10172$2771_DATA + connect \DATA $memrd$\mem$ls180.v:10373$2916_DATA connect \EN 1'x end - attribute \src "ls180.v:10192.27-10192.32" - cell $memrd $memrd$\mem_1$ls180.v:10192$2785 - parameter \ABITS 7 + attribute \src "ls180.v:10401.27-10401.32" + cell $memrd $memrd$\mem_1$ls180.v:10401$2942 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr_1 connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10192$2785_DATA + connect \DATA $memrd$\mem_1$ls180.v:10401$2942_DATA connect \EN 1'x end - attribute \src "ls180.v:10212.27-10212.32" - cell $memrd $memrd$\mem_2$ls180.v:10212$2799 - parameter \ABITS 7 + attribute \src "ls180.v:10429.27-10429.32" + cell $memrd $memrd$\mem_2$ls180.v:10429$2968 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr_2 connect \CLK 1'x - connect \DATA $memrd$\mem_2$ls180.v:10212$2799_DATA + connect \DATA $memrd$\mem_2$ls180.v:10429$2968_DATA connect \EN 1'x end - attribute \src "ls180.v:10232.27-10232.32" - cell $memrd $memrd$\mem_3$ls180.v:10232$2813 - parameter \ABITS 7 + attribute \src "ls180.v:10457.27-10457.32" + cell $memrd $memrd$\mem_3$ls180.v:10457$2994 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr_3 connect \CLK 1'x - connect \DATA $memrd$\mem_3$ls180.v:10232$2813_DATA + connect \DATA $memrd$\mem_3$ls180.v:10457$2994_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10485.27-10485.32" + cell $memrd $memrd$\mem_4$ls180.v:10485$3020 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_4 + connect \CLK 1'x + connect \DATA $memrd$\mem_4$ls180.v:10485$3020_DATA connect \EN 1'x end - attribute \src "ls180.v:10243.12-10243.19" - cell $memrd $memrd$\storage$ls180.v:10243$2818 + attribute \src "ls180.v:10496.12-10496.19" + cell $memrd $memrd$\storage$ls180.v:10496$3025 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254668,11 +272217,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10243$2818_DATA + connect \DATA $memrd$\storage$ls180.v:10496$3025_DATA connect \EN 1'x end - attribute \src "ls180.v:10250.68-10250.75" - cell $memrd $memrd$\storage$ls180.v:10250$2820 + attribute \src "ls180.v:10503.68-10503.75" + cell $memrd $memrd$\storage$ls180.v:10503$3027 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254681,11 +272230,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10250$2820_DATA + connect \DATA $memrd$\storage$ls180.v:10503$3027_DATA connect \EN 1'x end - attribute \src "ls180.v:10257.14-10257.23" - cell $memrd $memrd$\storage_1$ls180.v:10257$2825 + attribute \src "ls180.v:10510.14-10510.23" + cell $memrd $memrd$\storage_1$ls180.v:10510$3032 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254694,11 +272243,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10257$2825_DATA + connect \DATA $memrd$\storage_1$ls180.v:10510$3032_DATA connect \EN 1'x end - attribute \src "ls180.v:10264.68-10264.77" - cell $memrd $memrd$\storage_1$ls180.v:10264$2827 + attribute \src "ls180.v:10517.68-10517.77" + cell $memrd $memrd$\storage_1$ls180.v:10517$3034 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254707,11 +272256,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10264$2827_DATA + connect \DATA $memrd$\storage_1$ls180.v:10517$3034_DATA connect \EN 1'x end - attribute \src "ls180.v:10271.14-10271.23" - cell $memrd $memrd$\storage_2$ls180.v:10271$2832 + attribute \src "ls180.v:10524.14-10524.23" + cell $memrd $memrd$\storage_2$ls180.v:10524$3039 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254720,11 +272269,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10271$2832_DATA + connect \DATA $memrd$\storage_2$ls180.v:10524$3039_DATA connect \EN 1'x end - attribute \src "ls180.v:10278.68-10278.77" - cell $memrd $memrd$\storage_2$ls180.v:10278$2834 + attribute \src "ls180.v:10531.68-10531.77" + cell $memrd $memrd$\storage_2$ls180.v:10531$3041 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254733,11 +272282,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10278$2834_DATA + connect \DATA $memrd$\storage_2$ls180.v:10531$3041_DATA connect \EN 1'x end - attribute \src "ls180.v:10285.14-10285.23" - cell $memrd $memrd$\storage_3$ls180.v:10285$2839 + attribute \src "ls180.v:10538.14-10538.23" + cell $memrd $memrd$\storage_3$ls180.v:10538$3046 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254746,11 +272295,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10285$2839_DATA + connect \DATA $memrd$\storage_3$ls180.v:10538$3046_DATA connect \EN 1'x end - attribute \src "ls180.v:10292.68-10292.77" - cell $memrd $memrd$\storage_3$ls180.v:10292$2841 + attribute \src "ls180.v:10545.68-10545.77" + cell $memrd $memrd$\storage_3$ls180.v:10545$3048 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254759,11 +272308,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10292$2841_DATA + connect \DATA $memrd$\storage_3$ls180.v:10545$3048_DATA connect \EN 1'x end - attribute \src "ls180.v:10300.14-10300.23" - cell $memrd $memrd$\storage_4$ls180.v:10300$2846 + attribute \src "ls180.v:10553.14-10553.23" + cell $memrd $memrd$\storage_4$ls180.v:10553$3053 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254772,11 +272321,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10300$2846_DATA + connect \DATA $memrd$\storage_4$ls180.v:10553$3053_DATA connect \EN 1'x end - attribute \src "ls180.v:10305.15-10305.24" - cell $memrd $memrd$\storage_4$ls180.v:10305$2848 + attribute \src "ls180.v:10558.15-10558.24" + cell $memrd $memrd$\storage_4$ls180.v:10558$3055 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254785,11 +272334,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10305$2848_DATA + connect \DATA $memrd$\storage_4$ls180.v:10558$3055_DATA connect \EN 1'x end - attribute \src "ls180.v:10317.14-10317.23" - cell $memrd $memrd$\storage_5$ls180.v:10317$2853 + attribute \src "ls180.v:10570.14-10570.23" + cell $memrd $memrd$\storage_5$ls180.v:10570$3060 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254798,11 +272347,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10317$2853_DATA + connect \DATA $memrd$\storage_5$ls180.v:10570$3060_DATA connect \EN 1'x end - attribute \src "ls180.v:10322.15-10322.24" - cell $memrd $memrd$\storage_5$ls180.v:10322$2855 + attribute \src "ls180.v:10575.15-10575.24" + cell $memrd $memrd$\storage_5$ls180.v:10575$3062 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254811,11 +272360,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10322$2855_DATA + connect \DATA $memrd$\storage_5$ls180.v:10575$3062_DATA connect \EN 1'x end - attribute \src "ls180.v:10333.14-10333.23" - cell $memrd $memrd$\storage_6$ls180.v:10333$2860 + attribute \src "ls180.v:10586.14-10586.23" + cell $memrd $memrd$\storage_6$ls180.v:10586$3067 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254824,11 +272373,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10333$2860_DATA + connect \DATA $memrd$\storage_6$ls180.v:10586$3067_DATA connect \EN 1'x end - attribute \src "ls180.v:10340.45-10340.54" - cell $memrd $memrd$\storage_6$ls180.v:10340$2862 + attribute \src "ls180.v:10593.45-10593.54" + cell $memrd $memrd$\storage_6$ls180.v:10593$3069 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254837,11 +272386,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10340$2862_DATA + connect \DATA $memrd$\storage_6$ls180.v:10593$3069_DATA connect \EN 1'x end - attribute \src "ls180.v:10347.14-10347.23" - cell $memrd $memrd$\storage_7$ls180.v:10347$2867 + attribute \src "ls180.v:10600.14-10600.23" + cell $memrd $memrd$\storage_7$ls180.v:10600$3074 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254850,11 +272399,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10347$2867_DATA + connect \DATA $memrd$\storage_7$ls180.v:10600$3074_DATA connect \EN 1'x end - attribute \src "ls180.v:10354.45-10354.54" - cell $memrd $memrd$\storage_7$ls180.v:10354$2869 + attribute \src "ls180.v:10607.45-10607.54" + cell $memrd $memrd$\storage_7$ls180.v:10607$3076 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254863,323 +272412,635 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10354$2869_DATA + connect \DATA $memrd$\storage_7$ls180.v:10607$3076_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2871 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$3078 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2871 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10162$1_ADDR + parameter \PRIORITY 3078 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10355$1_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10162$1_DATA - connect \EN $memwr$\mem$ls180.v:10162$1_EN + connect \DATA $memwr$\mem$ls180.v:10355$1_DATA + connect \EN $memwr$\mem$ls180.v:10355$1_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2872 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$3079 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2872 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10164$2_ADDR + parameter \PRIORITY 3079 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10357$2_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10164$2_DATA - connect \EN $memwr$\mem$ls180.v:10164$2_EN + connect \DATA $memwr$\mem$ls180.v:10357$2_DATA + connect \EN $memwr$\mem$ls180.v:10357$2_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2873 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$3080 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2873 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10166$3_ADDR + parameter \PRIORITY 3080 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10359$3_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10166$3_DATA - connect \EN $memwr$\mem$ls180.v:10166$3_EN + connect \DATA $memwr$\mem$ls180.v:10359$3_DATA + connect \EN $memwr$\mem$ls180.v:10359$3_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2874 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$3081 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2874 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10168$4_ADDR + parameter \PRIORITY 3081 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10361$4_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10168$4_DATA - connect \EN $memwr$\mem$ls180.v:10168$4_EN + connect \DATA $memwr$\mem$ls180.v:10361$4_DATA + connect \EN $memwr$\mem$ls180.v:10361$4_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2875 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$3082 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3082 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10363$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10363$5_DATA + connect \EN $memwr$\mem$ls180.v:10363$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3083 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3083 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10365$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10365$6_DATA + connect \EN $memwr$\mem$ls180.v:10365$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3084 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3084 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10367$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10367$7_DATA + connect \EN $memwr$\mem$ls180.v:10367$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3085 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3085 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10369$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10369$8_DATA + connect \EN $memwr$\mem$ls180.v:10369$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3086 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 2875 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_1$ls180.v:10182$5_ADDR + parameter \PRIORITY 3086 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10383$9_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10182$5_DATA - connect \EN $memwr$\mem_1$ls180.v:10182$5_EN + connect \DATA $memwr$\mem_1$ls180.v:10383$9_DATA + connect \EN $memwr$\mem_1$ls180.v:10383$9_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2876 - parameter \ABITS 7 + cell $memwr $memwr$\mem_1$ls180.v:0$3087 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 2876 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_1$ls180.v:10184$6_ADDR + parameter \PRIORITY 3087 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10385$10_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10184$6_DATA - connect \EN $memwr$\mem_1$ls180.v:10184$6_EN + connect \DATA $memwr$\mem_1$ls180.v:10385$10_DATA + connect \EN $memwr$\mem_1$ls180.v:10385$10_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2877 - parameter \ABITS 7 + cell $memwr $memwr$\mem_1$ls180.v:0$3088 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 2877 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_1$ls180.v:10186$7_ADDR + parameter \PRIORITY 3088 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10387$11_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10186$7_DATA - connect \EN $memwr$\mem_1$ls180.v:10186$7_EN + connect \DATA $memwr$\mem_1$ls180.v:10387$11_DATA + connect \EN $memwr$\mem_1$ls180.v:10387$11_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2878 - parameter \ABITS 7 + cell $memwr $memwr$\mem_1$ls180.v:0$3089 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 2878 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_1$ls180.v:10188$8_ADDR + parameter \PRIORITY 3089 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10389$12_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10188$8_DATA - connect \EN $memwr$\mem_1$ls180.v:10188$8_EN + connect \DATA $memwr$\mem_1$ls180.v:10389$12_DATA + connect \EN $memwr$\mem_1$ls180.v:10389$12_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$2879 - parameter \ABITS 7 + cell $memwr $memwr$\mem_1$ls180.v:0$3090 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3090 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10391$13_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10391$13_DATA + connect \EN $memwr$\mem_1$ls180.v:10391$13_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3091 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3091 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10393$14_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10393$14_DATA + connect \EN $memwr$\mem_1$ls180.v:10393$14_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3092 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3092 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10395$15_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10395$15_DATA + connect \EN $memwr$\mem_1$ls180.v:10395$15_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3093 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3093 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10397$16_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10397$16_DATA + connect \EN $memwr$\mem_1$ls180.v:10397$16_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3094 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 2879 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_2$ls180.v:10202$9_ADDR + parameter \PRIORITY 3094 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10411$17_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10202$9_DATA - connect \EN $memwr$\mem_2$ls180.v:10202$9_EN + connect \DATA $memwr$\mem_2$ls180.v:10411$17_DATA + connect \EN $memwr$\mem_2$ls180.v:10411$17_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$2880 - parameter \ABITS 7 + cell $memwr $memwr$\mem_2$ls180.v:0$3095 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 2880 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_2$ls180.v:10204$10_ADDR + parameter \PRIORITY 3095 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10413$18_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10204$10_DATA - connect \EN $memwr$\mem_2$ls180.v:10204$10_EN + connect \DATA $memwr$\mem_2$ls180.v:10413$18_DATA + connect \EN $memwr$\mem_2$ls180.v:10413$18_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$2881 - parameter \ABITS 7 + cell $memwr $memwr$\mem_2$ls180.v:0$3096 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 2881 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_2$ls180.v:10206$11_ADDR + parameter \PRIORITY 3096 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10415$19_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10206$11_DATA - connect \EN $memwr$\mem_2$ls180.v:10206$11_EN + connect \DATA $memwr$\mem_2$ls180.v:10415$19_DATA + connect \EN $memwr$\mem_2$ls180.v:10415$19_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$2882 - parameter \ABITS 7 + cell $memwr $memwr$\mem_2$ls180.v:0$3097 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 2882 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_2$ls180.v:10208$12_ADDR + parameter \PRIORITY 3097 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10417$20_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10208$12_DATA - connect \EN $memwr$\mem_2$ls180.v:10208$12_EN + connect \DATA $memwr$\mem_2$ls180.v:10417$20_DATA + connect \EN $memwr$\mem_2$ls180.v:10417$20_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$2883 - parameter \ABITS 7 + cell $memwr $memwr$\mem_2$ls180.v:0$3098 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3098 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10419$21_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10419$21_DATA + connect \EN $memwr$\mem_2$ls180.v:10419$21_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3099 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3099 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10421$22_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10421$22_DATA + connect \EN $memwr$\mem_2$ls180.v:10421$22_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3100 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3100 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10423$23_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10423$23_DATA + connect \EN $memwr$\mem_2$ls180.v:10423$23_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3101 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3101 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10425$24_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10425$24_DATA + connect \EN $memwr$\mem_2$ls180.v:10425$24_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3102 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 2883 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_3$ls180.v:10222$13_ADDR + parameter \PRIORITY 3102 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10439$25_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10222$13_DATA - connect \EN $memwr$\mem_3$ls180.v:10222$13_EN + connect \DATA $memwr$\mem_3$ls180.v:10439$25_DATA + connect \EN $memwr$\mem_3$ls180.v:10439$25_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$2884 - parameter \ABITS 7 + cell $memwr $memwr$\mem_3$ls180.v:0$3103 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 2884 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_3$ls180.v:10224$14_ADDR + parameter \PRIORITY 3103 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10441$26_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10224$14_DATA - connect \EN $memwr$\mem_3$ls180.v:10224$14_EN + connect \DATA $memwr$\mem_3$ls180.v:10441$26_DATA + connect \EN $memwr$\mem_3$ls180.v:10441$26_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$2885 - parameter \ABITS 7 + cell $memwr $memwr$\mem_3$ls180.v:0$3104 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 2885 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_3$ls180.v:10226$15_ADDR + parameter \PRIORITY 3104 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10443$27_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10226$15_DATA - connect \EN $memwr$\mem_3$ls180.v:10226$15_EN + connect \DATA $memwr$\mem_3$ls180.v:10443$27_DATA + connect \EN $memwr$\mem_3$ls180.v:10443$27_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$2886 - parameter \ABITS 7 + cell $memwr $memwr$\mem_3$ls180.v:0$3105 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 2886 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_3$ls180.v:10228$16_ADDR + parameter \PRIORITY 3105 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10445$28_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10445$28_DATA + connect \EN $memwr$\mem_3$ls180.v:10445$28_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3106 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3106 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10447$29_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10447$29_DATA + connect \EN $memwr$\mem_3$ls180.v:10447$29_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3107 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3107 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10449$30_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10449$30_DATA + connect \EN $memwr$\mem_3$ls180.v:10449$30_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3108 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3108 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10451$31_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10451$31_DATA + connect \EN $memwr$\mem_3$ls180.v:10451$31_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3109 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3109 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10453$32_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10453$32_DATA + connect \EN $memwr$\mem_3$ls180.v:10453$32_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3110 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3110 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10467$33_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10467$33_DATA + connect \EN $memwr$\mem_4$ls180.v:10467$33_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3111 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3111 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10469$34_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10469$34_DATA + connect \EN $memwr$\mem_4$ls180.v:10469$34_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3112 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3112 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10471$35_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10471$35_DATA + connect \EN $memwr$\mem_4$ls180.v:10471$35_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3113 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3113 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10473$36_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10228$16_DATA - connect \EN $memwr$\mem_3$ls180.v:10228$16_EN + connect \DATA $memwr$\mem_4$ls180.v:10473$36_DATA + connect \EN $memwr$\mem_4$ls180.v:10473$36_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2887 + cell $memwr $memwr$\mem_4$ls180.v:0$3114 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3114 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10475$37_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10475$37_DATA + connect \EN $memwr$\mem_4$ls180.v:10475$37_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3115 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3115 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10477$38_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10477$38_DATA + connect \EN $memwr$\mem_4$ls180.v:10477$38_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3116 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3116 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10479$39_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10479$39_DATA + connect \EN $memwr$\mem_4$ls180.v:10479$39_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3117 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3117 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10481$40_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10481$40_DATA + connect \EN $memwr$\mem_4$ls180.v:10481$40_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$3118 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" - parameter \PRIORITY 2887 + parameter \PRIORITY 3118 parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10242$17_ADDR + connect \ADDR $memwr$\storage$ls180.v:10495$41_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10242$17_DATA - connect \EN $memwr$\storage$ls180.v:10242$17_EN + connect \DATA $memwr$\storage$ls180.v:10495$41_DATA + connect \EN $memwr$\storage$ls180.v:10495$41_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2888 + cell $memwr $memwr$\storage_1$ls180.v:0$3119 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" - parameter \PRIORITY 2888 + parameter \PRIORITY 3119 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10256$18_ADDR + connect \ADDR $memwr$\storage_1$ls180.v:10509$42_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10256$18_DATA - connect \EN $memwr$\storage_1$ls180.v:10256$18_EN + connect \DATA $memwr$\storage_1$ls180.v:10509$42_DATA + connect \EN $memwr$\storage_1$ls180.v:10509$42_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2889 + cell $memwr $memwr$\storage_2$ls180.v:0$3120 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" - parameter \PRIORITY 2889 + parameter \PRIORITY 3120 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10270$19_ADDR + connect \ADDR $memwr$\storage_2$ls180.v:10523$43_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10270$19_DATA - connect \EN $memwr$\storage_2$ls180.v:10270$19_EN + connect \DATA $memwr$\storage_2$ls180.v:10523$43_DATA + connect \EN $memwr$\storage_2$ls180.v:10523$43_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2890 + cell $memwr $memwr$\storage_3$ls180.v:0$3121 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" - parameter \PRIORITY 2890 + parameter \PRIORITY 3121 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10284$20_ADDR + connect \ADDR $memwr$\storage_3$ls180.v:10537$44_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10284$20_DATA - connect \EN $memwr$\storage_3$ls180.v:10284$20_EN + connect \DATA $memwr$\storage_3$ls180.v:10537$44_DATA + connect \EN $memwr$\storage_3$ls180.v:10537$44_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2891 + cell $memwr $memwr$\storage_4$ls180.v:0$3122 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" - parameter \PRIORITY 2891 + parameter \PRIORITY 3122 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10299$21_ADDR + connect \ADDR $memwr$\storage_4$ls180.v:10552$45_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10299$21_DATA - connect \EN $memwr$\storage_4$ls180.v:10299$21_EN + connect \DATA $memwr$\storage_4$ls180.v:10552$45_DATA + connect \EN $memwr$\storage_4$ls180.v:10552$45_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2892 + cell $memwr $memwr$\storage_5$ls180.v:0$3123 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" - parameter \PRIORITY 2892 + parameter \PRIORITY 3123 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10316$22_ADDR + connect \ADDR $memwr$\storage_5$ls180.v:10569$46_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10316$22_DATA - connect \EN $memwr$\storage_5$ls180.v:10316$22_EN + connect \DATA $memwr$\storage_5$ls180.v:10569$46_DATA + connect \EN $memwr$\storage_5$ls180.v:10569$46_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2893 + cell $memwr $memwr$\storage_6$ls180.v:0$3124 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_6" - parameter \PRIORITY 2893 + parameter \PRIORITY 3124 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10332$23_ADDR + connect \ADDR $memwr$\storage_6$ls180.v:10585$47_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10332$23_DATA - connect \EN $memwr$\storage_6$ls180.v:10332$23_EN + connect \DATA $memwr$\storage_6$ls180.v:10585$47_DATA + connect \EN $memwr$\storage_6$ls180.v:10585$47_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2894 + cell $memwr $memwr$\storage_7$ls180.v:0$3125 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_7" - parameter \PRIORITY 2894 + parameter \PRIORITY 3125 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10346$24_ADDR + connect \ADDR $memwr$\storage_7$ls180.v:10599$48_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10346$24_DATA - connect \EN $memwr$\storage_7$ls180.v:10346$24_EN + connect \DATA $memwr$\storage_7$ls180.v:10599$48_DATA + connect \EN $memwr$\storage_7$ls180.v:10599$48_EN end - attribute \src "ls180.v:3010.41-3010.71" - cell $ne $ne$ls180.v:3010$72 + attribute \src "ls180.v:3089.41-3089.71" + cell $ne $ne$ls180.v:3089$108 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255187,10 +273048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $ne$ls180.v:3010$72_Y + connect \Y $ne$ls180.v:3089$108_Y end - attribute \src "ls180.v:3201.70-3201.104" - cell $ne $ne$ls180.v:3201$125 + attribute \src "ls180.v:3306.70-3306.104" + cell $ne $ne$ls180.v:3306$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255198,10 +273059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:3201$125_Y + connect \Y $ne$ls180.v:3306$222_Y end - attribute \src "ls180.v:3262.8-3262.142" - cell $ne $ne$ls180.v:3262$144 + attribute \src "ls180.v:3367.8-3367.142" + cell $ne $ne$ls180.v:3367$241 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -255209,10 +273070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3262$144_Y + connect \Y $ne$ls180.v:3367$241_Y end - attribute \src "ls180.v:3294.75-3294.133" - cell $ne $ne$ls180.v:3294$151 + attribute \src "ls180.v:3399.75-3399.133" + cell $ne $ne$ls180.v:3399$248 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255220,10 +273081,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3294$151_Y + connect \Y $ne$ls180.v:3399$248_Y end - attribute \src "ls180.v:3295.75-3295.133" - cell $ne $ne$ls180.v:3295$152 + attribute \src "ls180.v:3400.75-3400.133" + cell $ne $ne$ls180.v:3400$249 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255231,10 +273092,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3295$152_Y + connect \Y $ne$ls180.v:3400$249_Y end - attribute \src "ls180.v:3419.8-3419.142" - cell $ne $ne$ls180.v:3419$174 + attribute \src "ls180.v:3524.8-3524.142" + cell $ne $ne$ls180.v:3524$271 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -255242,10 +273103,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3419$174_Y + connect \Y $ne$ls180.v:3524$271_Y end - attribute \src "ls180.v:3451.75-3451.133" - cell $ne $ne$ls180.v:3451$181 + attribute \src "ls180.v:3556.75-3556.133" + cell $ne $ne$ls180.v:3556$278 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255253,10 +273114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3451$181_Y + connect \Y $ne$ls180.v:3556$278_Y end - attribute \src "ls180.v:3452.75-3452.133" - cell $ne $ne$ls180.v:3452$182 + attribute \src "ls180.v:3557.75-3557.133" + cell $ne $ne$ls180.v:3557$279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255264,10 +273125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3452$182_Y + connect \Y $ne$ls180.v:3557$279_Y end - attribute \src "ls180.v:3576.8-3576.142" - cell $ne $ne$ls180.v:3576$204 + attribute \src "ls180.v:3681.8-3681.142" + cell $ne $ne$ls180.v:3681$301 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -255275,10 +273136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3576$204_Y + connect \Y $ne$ls180.v:3681$301_Y end - attribute \src "ls180.v:3608.75-3608.133" - cell $ne $ne$ls180.v:3608$211 + attribute \src "ls180.v:3713.75-3713.133" + cell $ne $ne$ls180.v:3713$308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255286,10 +273147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3608$211_Y + connect \Y $ne$ls180.v:3713$308_Y end - attribute \src "ls180.v:3609.75-3609.133" - cell $ne $ne$ls180.v:3609$212 + attribute \src "ls180.v:3714.75-3714.133" + cell $ne $ne$ls180.v:3714$309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255297,10 +273158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3609$212_Y + connect \Y $ne$ls180.v:3714$309_Y end - attribute \src "ls180.v:3733.8-3733.142" - cell $ne $ne$ls180.v:3733$234 + attribute \src "ls180.v:3838.8-3838.142" + cell $ne $ne$ls180.v:3838$331 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -255308,10 +273169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3733$234_Y + connect \Y $ne$ls180.v:3838$331_Y end - attribute \src "ls180.v:3765.75-3765.133" - cell $ne $ne$ls180.v:3765$241 + attribute \src "ls180.v:3870.75-3870.133" + cell $ne $ne$ls180.v:3870$338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255319,10 +273180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3765$241_Y + connect \Y $ne$ls180.v:3870$338_Y end - attribute \src "ls180.v:3766.75-3766.133" - cell $ne $ne$ls180.v:3766$242 + attribute \src "ls180.v:3871.75-3871.133" + cell $ne $ne$ls180.v:3871$339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255330,10 +273191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3766$242_Y + connect \Y $ne$ls180.v:3871$339_Y end - attribute \src "ls180.v:4258.47-4258.80" - cell $ne $ne$ls180.v:4258$640 + attribute \src "ls180.v:4363.47-4363.80" + cell $ne $ne$ls180.v:4363$737 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255341,10 +273202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4258$640_Y + connect \Y $ne$ls180.v:4363$737_Y end - attribute \src "ls180.v:4259.47-4259.79" - cell $ne $ne$ls180.v:4259$641 + attribute \src "ls180.v:4364.47-4364.79" + cell $ne $ne$ls180.v:4364$738 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255352,10 +273213,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4259$641_Y + connect \Y $ne$ls180.v:4364$738_Y end - attribute \src "ls180.v:4288.47-4288.80" - cell $ne $ne$ls180.v:4288$651 + attribute \src "ls180.v:4393.47-4393.80" + cell $ne $ne$ls180.v:4393$748 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255363,10 +273224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4288$651_Y + connect \Y $ne$ls180.v:4393$748_Y end - attribute \src "ls180.v:4289.47-4289.79" - cell $ne $ne$ls180.v:4289$652 + attribute \src "ls180.v:4394.47-4394.79" + cell $ne $ne$ls180.v:4394$749 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255374,10 +273235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4289$652_Y + connect \Y $ne$ls180.v:4394$749_Y end - attribute \src "ls180.v:4758.32-4758.89" - cell $ne $ne$ls180.v:4758$732 + attribute \src "ls180.v:4874.32-4874.89" + cell $ne $ne$ls180.v:4874$831 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -255385,10 +273246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $ne$ls180.v:4758$732_Y + connect \Y $ne$ls180.v:4874$831_Y end - attribute \src "ls180.v:5405.10-5405.56" - cell $ne $ne$ls180.v:5405$1029 + attribute \src "ls180.v:5521.10-5521.56" + cell $ne $ne$ls180.v:5521$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255396,10 +273257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 2'10 - connect \Y $ne$ls180.v:5405$1029_Y + connect \Y $ne$ls180.v:5521$1128_Y end - attribute \src "ls180.v:5510.51-5510.87" - cell $ne $ne$ls180.v:5510$1043 + attribute \src "ls180.v:5626.51-5626.87" + cell $ne $ne$ls180.v:5626$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255407,10 +273268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5510$1043_Y + connect \Y $ne$ls180.v:5626$1142_Y end - attribute \src "ls180.v:5511.51-5511.86" - cell $ne $ne$ls180.v:5511$1044 + attribute \src "ls180.v:5627.51-5627.86" + cell $ne $ne$ls180.v:5627$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255418,10 +273279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5511$1044_Y + connect \Y $ne$ls180.v:5627$1143_Y end - attribute \src "ls180.v:5718.51-5718.87" - cell $ne $ne$ls180.v:5718$1074 + attribute \src "ls180.v:5846.51-5846.87" + cell $ne $ne$ls180.v:5846$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255429,10 +273290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5718$1074_Y + connect \Y $ne$ls180.v:5846$1173_Y end - attribute \src "ls180.v:5719.51-5719.86" - cell $ne $ne$ls180.v:5719$1075 + attribute \src "ls180.v:5847.51-5847.86" + cell $ne $ne$ls180.v:5847$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255440,10 +273301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5719$1075_Y + connect \Y $ne$ls180.v:5847$1174_Y end - attribute \src "ls180.v:5750.79-5750.119" - cell $ne $ne$ls180.v:5750$1078 + attribute \src "ls180.v:5878.79-5878.119" + cell $ne $ne$ls180.v:5878$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255451,10 +273312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_sel connect \B 1'0 - connect \Y $ne$ls180.v:5750$1078_Y + connect \Y $ne$ls180.v:5878$1177_Y end - attribute \src "ls180.v:7587.7-7587.52" - cell $ne $ne$ls180.v:7587$2471 + attribute \src "ls180.v:7763.7-7763.52" + cell $ne $ne$ls180.v:7763$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255462,10 +273323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7587$2471_Y + connect \Y $ne$ls180.v:7763$2601_Y end - attribute \src "ls180.v:7649.9-7649.43" - cell $ne $ne$ls180.v:7649$2494 + attribute \src "ls180.v:7829.9-7829.43" + cell $ne $ne$ls180.v:7829$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255473,10 +273334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7649$2494_Y + connect \Y $ne$ls180.v:7829$2627_Y end - attribute \src "ls180.v:7685.8-7685.44" - cell $ne $ne$ls180.v:7685$2501 + attribute \src "ls180.v:7865.8-7865.44" + cell $ne $ne$ls180.v:7865$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255484,10 +273345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7685$2501_Y + connect \Y $ne$ls180.v:7865$2634_Y end - attribute \src "ls180.v:8623.9-8623.47" - cell $ne $ne$ls180.v:8623$2716 + attribute \src "ls180.v:8803.9-8803.47" + cell $ne $ne$ls180.v:8803$2849 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255495,2730 +273356,2738 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8623$2716_Y + connect \Y $ne$ls180.v:8803$2849_Y end - attribute \src "ls180.v:2818.45-2818.80" - cell $not $not$ls180.v:2818$26 + attribute \src "ls180.v:2893.33-2893.73" + cell $not $not$ls180.v:2893$50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:2818$26_Y + connect \A \main_interface0_converted_interface_cyc + connect \Y $not$ls180.v:2893$50_Y end - attribute \src "ls180.v:2857.61-2857.94" - cell $not $not$ls180.v:2857$31 + attribute \src "ls180.v:2932.48-2932.69" + cell $not $not$ls180.v:2932$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2857$31_Y + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2932$55_Y end - attribute \src "ls180.v:2858.61-2858.94" - cell $not $not$ls180.v:2858$32 + attribute \src "ls180.v:2933.48-2933.69" + cell $not $not$ls180.v:2933$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2858$32_Y + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2933$56_Y end - attribute \src "ls180.v:2878.45-2878.80" - cell $not $not$ls180.v:2878$37 + attribute \src "ls180.v:2953.33-2953.73" + cell $not $not$ls180.v:2953$61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:2878$37_Y + connect \A \main_interface1_converted_interface_cyc + connect \Y $not$ls180.v:2953$61_Y end - attribute \src "ls180.v:2917.61-2917.94" - cell $not $not$ls180.v:2917$42 + attribute \src "ls180.v:2992.48-2992.69" + cell $not $not$ls180.v:2992$66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2917$42_Y + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2992$66_Y end - attribute \src "ls180.v:2918.61-2918.94" - cell $not $not$ls180.v:2918$43 + attribute \src "ls180.v:2993.48-2993.69" + cell $not $not$ls180.v:2993$67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2918$43_Y + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2993$67_Y end - attribute \src "ls180.v:2938.45-2938.83" - cell $not $not$ls180.v:2938$48 + attribute \src "ls180.v:3013.36-3013.79" + cell $not $not$ls180.v:3013$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $not$ls180.v:2938$48_Y + connect \A \main_socbushandler_converted_interface_cyc + connect \Y $not$ls180.v:3013$72_Y end - attribute \src "ls180.v:2977.61-2977.94" - cell $not $not$ls180.v:2977$53 + attribute \src "ls180.v:3052.27-3052.51" + cell $not $not$ls180.v:3052$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2977$53_Y + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:3052$77_Y end - attribute \src "ls180.v:2978.61-2978.94" - cell $not $not$ls180.v:2978$54 + attribute \src "ls180.v:3053.27-3053.51" + cell $not $not$ls180.v:3053$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2978$54_Y + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:3053$78_Y end - attribute \src "ls180.v:3150.34-3150.64" - cell $not $not$ls180.v:3150$117 + attribute \src "ls180.v:3255.34-3255.64" + cell $not $not$ls180.v:3255$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3150$117_Y + connect \Y $not$ls180.v:3255$214_Y end - attribute \src "ls180.v:3151.31-3151.61" - cell $not $not$ls180.v:3151$118 + attribute \src "ls180.v:3256.31-3256.61" + cell $not $not$ls180.v:3256$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3151$118_Y + connect \Y $not$ls180.v:3256$215_Y end - attribute \src "ls180.v:3152.32-3152.62" - cell $not $not$ls180.v:3152$119 + attribute \src "ls180.v:3257.32-3257.62" + cell $not $not$ls180.v:3257$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3152$119_Y + connect \Y $not$ls180.v:3257$216_Y end - attribute \src "ls180.v:3153.32-3153.62" - cell $not $not$ls180.v:3153$120 + attribute \src "ls180.v:3258.32-3258.62" + cell $not $not$ls180.v:3258$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3153$120_Y + connect \Y $not$ls180.v:3258$217_Y end - attribute \src "ls180.v:3195.33-3195.56" - cell $not $not$ls180.v:3195$123 + attribute \src "ls180.v:3300.33-3300.56" + cell $not $not$ls180.v:3300$220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3195$123_Y + connect \Y $not$ls180.v:3300$220_Y end - attribute \src "ls180.v:3296.58-3296.106" - cell $not $not$ls180.v:3296$153 + attribute \src "ls180.v:3401.58-3401.106" + cell $not $not$ls180.v:3401$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3296$153_Y + connect \Y $not$ls180.v:3401$250_Y end - attribute \src "ls180.v:3350.9-3350.45" - cell $not $not$ls180.v:3350$158 + attribute \src "ls180.v:3455.9-3455.45" + cell $not $not$ls180.v:3455$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3350$158_Y + connect \Y $not$ls180.v:3455$255_Y end - attribute \src "ls180.v:3453.58-3453.106" - cell $not $not$ls180.v:3453$183 + attribute \src "ls180.v:3558.58-3558.106" + cell $not $not$ls180.v:3558$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3453$183_Y + connect \Y $not$ls180.v:3558$280_Y end - attribute \src "ls180.v:3507.9-3507.45" - cell $not $not$ls180.v:3507$188 + attribute \src "ls180.v:3612.9-3612.45" + cell $not $not$ls180.v:3612$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3507$188_Y + connect \Y $not$ls180.v:3612$285_Y end - attribute \src "ls180.v:3610.58-3610.106" - cell $not $not$ls180.v:3610$213 + attribute \src "ls180.v:3715.58-3715.106" + cell $not $not$ls180.v:3715$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3610$213_Y + connect \Y $not$ls180.v:3715$310_Y end - attribute \src "ls180.v:3664.9-3664.45" - cell $not $not$ls180.v:3664$218 + attribute \src "ls180.v:3769.9-3769.45" + cell $not $not$ls180.v:3769$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3664$218_Y + connect \Y $not$ls180.v:3769$315_Y end - attribute \src "ls180.v:3767.58-3767.106" - cell $not $not$ls180.v:3767$243 + attribute \src "ls180.v:3872.58-3872.106" + cell $not $not$ls180.v:3872$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3767$243_Y + connect \Y $not$ls180.v:3872$340_Y end - attribute \src "ls180.v:3821.9-3821.45" - cell $not $not$ls180.v:3821$248 + attribute \src "ls180.v:3926.9-3926.45" + cell $not $not$ls180.v:3926$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3821$248_Y + connect \Y $not$ls180.v:3926$345_Y end - attribute \src "ls180.v:3863.149-3863.187" - cell $not $not$ls180.v:3863$251 + attribute \src "ls180.v:3968.149-3968.187" + cell $not $not$ls180.v:3968$348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3863$251_Y + connect \Y $not$ls180.v:3968$348_Y end - attribute \src "ls180.v:3863.193-3863.230" - cell $not $not$ls180.v:3863$253 + attribute \src "ls180.v:3968.193-3968.230" + cell $not $not$ls180.v:3968$350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3863$253_Y + connect \Y $not$ls180.v:3968$350_Y end - attribute \src "ls180.v:3864.149-3864.187" - cell $not $not$ls180.v:3864$257 + attribute \src "ls180.v:3969.149-3969.187" + cell $not $not$ls180.v:3969$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3864$257_Y + connect \Y $not$ls180.v:3969$354_Y end - attribute \src "ls180.v:3864.193-3864.230" - cell $not $not$ls180.v:3864$259 + attribute \src "ls180.v:3969.193-3969.230" + cell $not $not$ls180.v:3969$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3864$259_Y + connect \Y $not$ls180.v:3969$356_Y end - attribute \src "ls180.v:3880.43-3880.73" - cell $not $not$ls180.v:3880$287 + attribute \src "ls180.v:3985.43-3985.73" + cell $not $not$ls180.v:3985$384 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3880$287_Y + connect \Y $not$ls180.v:3985$384_Y end - attribute \src "ls180.v:3883.205-3883.245" - cell $not $not$ls180.v:3883$290 + attribute \src "ls180.v:3988.205-3988.245" + cell $not $not$ls180.v:3988$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3883$290_Y + connect \Y $not$ls180.v:3988$387_Y end - attribute \src "ls180.v:3883.251-3883.290" - cell $not $not$ls180.v:3883$292 + attribute \src "ls180.v:3988.251-3988.290" + cell $not $not$ls180.v:3988$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3883$292_Y + connect \Y $not$ls180.v:3988$389_Y end - attribute \src "ls180.v:3883.159-3883.292" - cell $not $not$ls180.v:3883$294 + attribute \src "ls180.v:3988.159-3988.292" + cell $not $not$ls180.v:3988$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$293_Y - connect \Y $not$ls180.v:3883$294_Y + connect \A $and$ls180.v:3988$390_Y + connect \Y $not$ls180.v:3988$391_Y end - attribute \src "ls180.v:3884.205-3884.245" - cell $not $not$ls180.v:3884$303 + attribute \src "ls180.v:3989.205-3989.245" + cell $not $not$ls180.v:3989$400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3884$303_Y + connect \Y $not$ls180.v:3989$400_Y end - attribute \src "ls180.v:3884.251-3884.290" - cell $not $not$ls180.v:3884$305 + attribute \src "ls180.v:3989.251-3989.290" + cell $not $not$ls180.v:3989$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3884$305_Y + connect \Y $not$ls180.v:3989$402_Y end - attribute \src "ls180.v:3884.159-3884.292" - cell $not $not$ls180.v:3884$307 + attribute \src "ls180.v:3989.159-3989.292" + cell $not $not$ls180.v:3989$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$306_Y - connect \Y $not$ls180.v:3884$307_Y + connect \A $and$ls180.v:3989$403_Y + connect \Y $not$ls180.v:3989$404_Y end - attribute \src "ls180.v:3885.205-3885.245" - cell $not $not$ls180.v:3885$316 + attribute \src "ls180.v:3990.205-3990.245" + cell $not $not$ls180.v:3990$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3885$316_Y + connect \Y $not$ls180.v:3990$413_Y end - attribute \src "ls180.v:3885.251-3885.290" - cell $not $not$ls180.v:3885$318 + attribute \src "ls180.v:3990.251-3990.290" + cell $not $not$ls180.v:3990$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3885$318_Y + connect \Y $not$ls180.v:3990$415_Y end - attribute \src "ls180.v:3885.159-3885.292" - cell $not $not$ls180.v:3885$320 + attribute \src "ls180.v:3990.159-3990.292" + cell $not $not$ls180.v:3990$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$319_Y - connect \Y $not$ls180.v:3885$320_Y + connect \A $and$ls180.v:3990$416_Y + connect \Y $not$ls180.v:3990$417_Y end - attribute \src "ls180.v:3886.205-3886.245" - cell $not $not$ls180.v:3886$329 + attribute \src "ls180.v:3991.205-3991.245" + cell $not $not$ls180.v:3991$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3886$329_Y + connect \Y $not$ls180.v:3991$426_Y end - attribute \src "ls180.v:3886.251-3886.290" - cell $not $not$ls180.v:3886$331 + attribute \src "ls180.v:3991.251-3991.290" + cell $not $not$ls180.v:3991$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3886$331_Y + connect \Y $not$ls180.v:3991$428_Y end - attribute \src "ls180.v:3886.159-3886.292" - cell $not $not$ls180.v:3886$333 + attribute \src "ls180.v:3991.159-3991.292" + cell $not $not$ls180.v:3991$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$332_Y - connect \Y $not$ls180.v:3886$333_Y + connect \A $and$ls180.v:3991$429_Y + connect \Y $not$ls180.v:3991$430_Y end - attribute \src "ls180.v:3913.71-3913.103" - cell $not $not$ls180.v:3913$344 + attribute \src "ls180.v:4018.71-4018.103" + cell $not $not$ls180.v:4018$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3913$344_Y + connect \Y $not$ls180.v:4018$441_Y end - attribute \src "ls180.v:3916.205-3916.245" - cell $not $not$ls180.v:3916$348 + attribute \src "ls180.v:4021.205-4021.245" + cell $not $not$ls180.v:4021$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3916$348_Y + connect \Y $not$ls180.v:4021$445_Y end - attribute \src "ls180.v:3916.251-3916.290" - cell $not $not$ls180.v:3916$350 + attribute \src "ls180.v:4021.251-4021.290" + cell $not $not$ls180.v:4021$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3916$350_Y + connect \Y $not$ls180.v:4021$447_Y end - attribute \src "ls180.v:3916.159-3916.292" - cell $not $not$ls180.v:3916$352 + attribute \src "ls180.v:4021.159-4021.292" + cell $not $not$ls180.v:4021$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3916$351_Y - connect \Y $not$ls180.v:3916$352_Y + connect \A $and$ls180.v:4021$448_Y + connect \Y $not$ls180.v:4021$449_Y end - attribute \src "ls180.v:3917.205-3917.245" - cell $not $not$ls180.v:3917$361 + attribute \src "ls180.v:4022.205-4022.245" + cell $not $not$ls180.v:4022$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3917$361_Y + connect \Y $not$ls180.v:4022$458_Y end - attribute \src "ls180.v:3917.251-3917.290" - cell $not $not$ls180.v:3917$363 + attribute \src "ls180.v:4022.251-4022.290" + cell $not $not$ls180.v:4022$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3917$363_Y + connect \Y $not$ls180.v:4022$460_Y end - attribute \src "ls180.v:3917.159-3917.292" - cell $not $not$ls180.v:3917$365 + attribute \src "ls180.v:4022.159-4022.292" + cell $not $not$ls180.v:4022$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3917$364_Y - connect \Y $not$ls180.v:3917$365_Y + connect \A $and$ls180.v:4022$461_Y + connect \Y $not$ls180.v:4022$462_Y end - attribute \src "ls180.v:3918.205-3918.245" - cell $not $not$ls180.v:3918$374 + attribute \src "ls180.v:4023.205-4023.245" + cell $not $not$ls180.v:4023$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3918$374_Y + connect \Y $not$ls180.v:4023$471_Y end - attribute \src "ls180.v:3918.251-3918.290" - cell $not $not$ls180.v:3918$376 + attribute \src "ls180.v:4023.251-4023.290" + cell $not $not$ls180.v:4023$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3918$376_Y + connect \Y $not$ls180.v:4023$473_Y end - attribute \src "ls180.v:3918.159-3918.292" - cell $not $not$ls180.v:3918$378 + attribute \src "ls180.v:4023.159-4023.292" + cell $not $not$ls180.v:4023$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3918$377_Y - connect \Y $not$ls180.v:3918$378_Y + connect \A $and$ls180.v:4023$474_Y + connect \Y $not$ls180.v:4023$475_Y end - attribute \src "ls180.v:3919.205-3919.245" - cell $not $not$ls180.v:3919$387 + attribute \src "ls180.v:4024.205-4024.245" + cell $not $not$ls180.v:4024$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3919$387_Y + connect \Y $not$ls180.v:4024$484_Y end - attribute \src "ls180.v:3919.251-3919.290" - cell $not $not$ls180.v:3919$389 + attribute \src "ls180.v:4024.251-4024.290" + cell $not $not$ls180.v:4024$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3919$389_Y + connect \Y $not$ls180.v:4024$486_Y end - attribute \src "ls180.v:3919.159-3919.292" - cell $not $not$ls180.v:3919$391 + attribute \src "ls180.v:4024.159-4024.292" + cell $not $not$ls180.v:4024$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$390_Y - connect \Y $not$ls180.v:3919$391_Y + connect \A $and$ls180.v:4024$487_Y + connect \Y $not$ls180.v:4024$488_Y end - attribute \src "ls180.v:3982.71-3982.103" - cell $not $not$ls180.v:3982$430 + attribute \src "ls180.v:4087.71-4087.103" + cell $not $not$ls180.v:4087$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3982$430_Y + connect \Y $not$ls180.v:4087$527_Y end - attribute \src "ls180.v:4003.112-4003.150" - cell $not $not$ls180.v:4003$433 + attribute \src "ls180.v:4108.112-4108.150" + cell $not $not$ls180.v:4108$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4003$433_Y + connect \Y $not$ls180.v:4108$530_Y end - attribute \src "ls180.v:4003.156-4003.193" - cell $not $not$ls180.v:4003$435 + attribute \src "ls180.v:4108.156-4108.193" + cell $not $not$ls180.v:4108$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4003$435_Y + connect \Y $not$ls180.v:4108$532_Y end - attribute \src "ls180.v:4003.68-4003.195" - cell $not $not$ls180.v:4003$437 + attribute \src "ls180.v:4108.68-4108.195" + cell $not $not$ls180.v:4108$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4003$436_Y - connect \Y $not$ls180.v:4003$437_Y + connect \A $and$ls180.v:4108$533_Y + connect \Y $not$ls180.v:4108$534_Y end - attribute \src "ls180.v:4011.11-4011.38" - cell $not $not$ls180.v:4011$440 + attribute \src "ls180.v:4116.11-4116.38" + cell $not $not$ls180.v:4116$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_write_available - connect \Y $not$ls180.v:4011$440_Y + connect \Y $not$ls180.v:4116$537_Y end - attribute \src "ls180.v:4041.112-4041.150" - cell $not $not$ls180.v:4041$442 + attribute \src "ls180.v:4146.112-4146.150" + cell $not $not$ls180.v:4146$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4041$442_Y + connect \Y $not$ls180.v:4146$539_Y end - attribute \src "ls180.v:4041.156-4041.193" - cell $not $not$ls180.v:4041$444 + attribute \src "ls180.v:4146.156-4146.193" + cell $not $not$ls180.v:4146$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4041$444_Y + connect \Y $not$ls180.v:4146$541_Y end - attribute \src "ls180.v:4041.68-4041.195" - cell $not $not$ls180.v:4041$446 + attribute \src "ls180.v:4146.68-4146.195" + cell $not $not$ls180.v:4146$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4041$445_Y - connect \Y $not$ls180.v:4041$446_Y + connect \A $and$ls180.v:4146$542_Y + connect \Y $not$ls180.v:4146$543_Y end - attribute \src "ls180.v:4049.11-4049.37" - cell $not $not$ls180.v:4049$449 + attribute \src "ls180.v:4154.11-4154.37" + cell $not $not$ls180.v:4154$546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_read_available - connect \Y $not$ls180.v:4049$449_Y + connect \Y $not$ls180.v:4154$546_Y end - attribute \src "ls180.v:4059.87-4059.331" - cell $not $not$ls180.v:4059$461 + attribute \src "ls180.v:4164.87-4164.331" + cell $not $not$ls180.v:4164$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4059$460_Y - connect \Y $not$ls180.v:4059$461_Y + connect \A $or$ls180.v:4164$557_Y + connect \Y $not$ls180.v:4164$558_Y end - attribute \src "ls180.v:4060.35-4060.68" - cell $not $not$ls180.v:4060$464 + attribute \src "ls180.v:4165.35-4165.68" + cell $not $not$ls180.v:4165$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:4060$464_Y + connect \Y $not$ls180.v:4165$561_Y end - attribute \src "ls180.v:4060.73-4060.105" - cell $not $not$ls180.v:4060$465 + attribute \src "ls180.v:4165.73-4165.105" + cell $not $not$ls180.v:4165$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:4060$465_Y + connect \Y $not$ls180.v:4165$562_Y end - attribute \src "ls180.v:4064.87-4064.331" - cell $not $not$ls180.v:4064$477 + attribute \src "ls180.v:4169.87-4169.331" + cell $not $not$ls180.v:4169$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4064$476_Y - connect \Y $not$ls180.v:4064$477_Y + connect \A $or$ls180.v:4169$573_Y + connect \Y $not$ls180.v:4169$574_Y end - attribute \src "ls180.v:4065.35-4065.68" - cell $not $not$ls180.v:4065$480 + attribute \src "ls180.v:4170.35-4170.68" + cell $not $not$ls180.v:4170$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:4065$480_Y + connect \Y $not$ls180.v:4170$577_Y end - attribute \src "ls180.v:4065.73-4065.105" - cell $not $not$ls180.v:4065$481 + attribute \src "ls180.v:4170.73-4170.105" + cell $not $not$ls180.v:4170$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:4065$481_Y + connect \Y $not$ls180.v:4170$578_Y end - attribute \src "ls180.v:4069.87-4069.331" - cell $not $not$ls180.v:4069$493 + attribute \src "ls180.v:4174.87-4174.331" + cell $not $not$ls180.v:4174$590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4069$492_Y - connect \Y $not$ls180.v:4069$493_Y + connect \A $or$ls180.v:4174$589_Y + connect \Y $not$ls180.v:4174$590_Y end - attribute \src "ls180.v:4070.35-4070.68" - cell $not $not$ls180.v:4070$496 + attribute \src "ls180.v:4175.35-4175.68" + cell $not $not$ls180.v:4175$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:4070$496_Y + connect \Y $not$ls180.v:4175$593_Y end - attribute \src "ls180.v:4070.73-4070.105" - cell $not $not$ls180.v:4070$497 + attribute \src "ls180.v:4175.73-4175.105" + cell $not $not$ls180.v:4175$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:4070$497_Y + connect \Y $not$ls180.v:4175$594_Y end - attribute \src "ls180.v:4074.87-4074.331" - cell $not $not$ls180.v:4074$509 + attribute \src "ls180.v:4179.87-4179.331" + cell $not $not$ls180.v:4179$606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4074$508_Y - connect \Y $not$ls180.v:4074$509_Y + connect \A $or$ls180.v:4179$605_Y + connect \Y $not$ls180.v:4179$606_Y end - attribute \src "ls180.v:4075.35-4075.68" - cell $not $not$ls180.v:4075$512 + attribute \src "ls180.v:4180.35-4180.68" + cell $not $not$ls180.v:4180$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4075$512_Y + connect \Y $not$ls180.v:4180$609_Y end - attribute \src "ls180.v:4075.73-4075.105" - cell $not $not$ls180.v:4075$513 + attribute \src "ls180.v:4180.73-4180.105" + cell $not $not$ls180.v:4180$610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4075$513_Y + connect \Y $not$ls180.v:4180$610_Y end - attribute \src "ls180.v:4079.128-4079.372" - cell $not $not$ls180.v:4079$526 + attribute \src "ls180.v:4184.128-4184.372" + cell $not $not$ls180.v:4184$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$525_Y - connect \Y $not$ls180.v:4079$526_Y + connect \A $or$ls180.v:4184$622_Y + connect \Y $not$ls180.v:4184$623_Y end - attribute \src "ls180.v:4079.502-4079.746" - cell $not $not$ls180.v:4079$542 + attribute \src "ls180.v:4184.502-4184.746" + cell $not $not$ls180.v:4184$639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$541_Y - connect \Y $not$ls180.v:4079$542_Y + connect \A $or$ls180.v:4184$638_Y + connect \Y $not$ls180.v:4184$639_Y end - attribute \src "ls180.v:4079.876-4079.1120" - cell $not $not$ls180.v:4079$558 + attribute \src "ls180.v:4184.876-4184.1120" + cell $not $not$ls180.v:4184$655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$557_Y - connect \Y $not$ls180.v:4079$558_Y + connect \A $or$ls180.v:4184$654_Y + connect \Y $not$ls180.v:4184$655_Y end - attribute \src "ls180.v:4079.1250-4079.1494" - cell $not $not$ls180.v:4079$574 + attribute \src "ls180.v:4184.1250-4184.1494" + cell $not $not$ls180.v:4184$671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$573_Y - connect \Y $not$ls180.v:4079$574_Y + connect \A $or$ls180.v:4184$670_Y + connect \Y $not$ls180.v:4184$671_Y end - attribute \src "ls180.v:4101.32-4101.50" - cell $not $not$ls180.v:4101$580 + attribute \src "ls180.v:4206.32-4206.50" + cell $not $not$ls180.v:4206$677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4101$580_Y + connect \Y $not$ls180.v:4206$677_Y end - attribute \src "ls180.v:4140.30-4140.50" - cell $not $not$ls180.v:4140$585 + attribute \src "ls180.v:4245.30-4245.50" + cell $not $not$ls180.v:4245$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4140$585_Y + connect \Y $not$ls180.v:4245$682_Y end - attribute \src "ls180.v:4141.30-4141.50" - cell $not $not$ls180.v:4141$586 + attribute \src "ls180.v:4246.30-4246.50" + cell $not $not$ls180.v:4246$683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4141$586_Y + connect \Y $not$ls180.v:4246$683_Y end - attribute \src "ls180.v:4166.27-4166.48" - cell $not $not$ls180.v:4166$592 + attribute \src "ls180.v:4271.27-4271.48" + cell $not $not$ls180.v:4271$689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4166$592_Y + connect \Y $not$ls180.v:4271$689_Y end - attribute \src "ls180.v:4167.30-4167.50" - cell $not $not$ls180.v:4167$593 + attribute \src "ls180.v:4272.30-4272.50" + cell $not $not$ls180.v:4272$690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4167$593_Y + connect \Y $not$ls180.v:4272$690_Y end - attribute \src "ls180.v:4168.80-4168.98" - cell $not $not$ls180.v:4168$595 + attribute \src "ls180.v:4273.80-4273.98" + cell $not $not$ls180.v:4273$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4168$595_Y + connect \Y $not$ls180.v:4273$692_Y end - attribute \src "ls180.v:4169.107-4169.127" - cell $not $not$ls180.v:4169$599 + attribute \src "ls180.v:4274.107-4274.127" + cell $not $not$ls180.v:4274$696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4169$599_Y + connect \Y $not$ls180.v:4274$696_Y end - attribute \src "ls180.v:4170.78-4170.103" - cell $not $not$ls180.v:4170$602 + attribute \src "ls180.v:4275.78-4275.103" + cell $not $not$ls180.v:4275$699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4170$602_Y + connect \Y $not$ls180.v:4275$699_Y end - attribute \src "ls180.v:4171.91-4171.111" - cell $not $not$ls180.v:4171$605 + attribute \src "ls180.v:4276.91-4276.111" + cell $not $not$ls180.v:4276$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4171$605_Y + connect \Y $not$ls180.v:4276$702_Y end - attribute \src "ls180.v:4187.35-4187.64" - cell $not $not$ls180.v:4187$614 + attribute \src "ls180.v:4292.35-4292.64" + cell $not $not$ls180.v:4292$711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4187$614_Y + connect \Y $not$ls180.v:4292$711_Y end - attribute \src "ls180.v:4188.36-4188.67" - cell $not $not$ls180.v:4188$615 + attribute \src "ls180.v:4293.36-4293.67" + cell $not $not$ls180.v:4293$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4188$615_Y + connect \Y $not$ls180.v:4293$712_Y end - attribute \src "ls180.v:4194.32-4194.61" - cell $not $not$ls180.v:4194$616 + attribute \src "ls180.v:4299.32-4299.61" + cell $not $not$ls180.v:4299$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4194$616_Y + connect \Y $not$ls180.v:4299$713_Y end - attribute \src "ls180.v:4200.36-4200.67" - cell $not $not$ls180.v:4200$617 + attribute \src "ls180.v:4305.36-4305.67" + cell $not $not$ls180.v:4305$714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4200$617_Y + connect \Y $not$ls180.v:4305$714_Y end - attribute \src "ls180.v:4201.35-4201.64" - cell $not $not$ls180.v:4201$618 + attribute \src "ls180.v:4306.35-4306.64" + cell $not $not$ls180.v:4306$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4201$618_Y + connect \Y $not$ls180.v:4306$715_Y end - attribute \src "ls180.v:4204.32-4204.63" - cell $not $not$ls180.v:4204$621 + attribute \src "ls180.v:4309.32-4309.63" + cell $not $not$ls180.v:4309$718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4204$621_Y + connect \Y $not$ls180.v:4309$718_Y end - attribute \src "ls180.v:4242.81-4242.108" - cell $not $not$ls180.v:4242$631 + attribute \src "ls180.v:4347.81-4347.108" + cell $not $not$ls180.v:4347$728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4242$631_Y + connect \Y $not$ls180.v:4347$728_Y end - attribute \src "ls180.v:4272.81-4272.108" - cell $not $not$ls180.v:4272$642 + attribute \src "ls180.v:4377.81-4377.108" + cell $not $not$ls180.v:4377$739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4272$642_Y + connect \Y $not$ls180.v:4377$739_Y end - attribute \src "ls180.v:4472.60-4472.85" - cell $not $not$ls180.v:4472$691 + attribute \src "ls180.v:4588.60-4588.85" + cell $not $not$ls180.v:4588$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4472$691_Y + connect \Y $not$ls180.v:4588$790_Y end - attribute \src "ls180.v:4613.54-4613.96" - cell $not $not$ls180.v:4613$705 + attribute \src "ls180.v:4729.54-4729.96" + cell $not $not$ls180.v:4729$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4613$705_Y + connect \Y $not$ls180.v:4729$804_Y end - attribute \src "ls180.v:4616.48-4616.86" - cell $not $not$ls180.v:4616$708 + attribute \src "ls180.v:4732.48-4732.86" + cell $not $not$ls180.v:4732$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4616$708_Y + connect \Y $not$ls180.v:4732$807_Y end - attribute \src "ls180.v:4740.55-4740.98" - cell $not $not$ls180.v:4740$726 + attribute \src "ls180.v:4856.55-4856.98" + cell $not $not$ls180.v:4856$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4740$726_Y + connect \Y $not$ls180.v:4856$825_Y end - attribute \src "ls180.v:4743.49-4743.88" - cell $not $not$ls180.v:4743$729 + attribute \src "ls180.v:4859.49-4859.88" + cell $not $not$ls180.v:4859$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4743$729_Y + connect \Y $not$ls180.v:4859$828_Y end - attribute \src "ls180.v:4793.30-4793.58" - cell $not $not$ls180.v:4793$735 + attribute \src "ls180.v:4909.30-4909.58" + cell $not $not$ls180.v:4909$834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4793$735_Y + connect \Y $not$ls180.v:4909$834_Y end - attribute \src "ls180.v:4874.56-4874.100" - cell $not $not$ls180.v:4874$741 + attribute \src "ls180.v:4990.56-4990.100" + cell $not $not$ls180.v:4990$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4874$741_Y + connect \Y $not$ls180.v:4990$840_Y end - attribute \src "ls180.v:4877.50-4877.90" - cell $not $not$ls180.v:4877$744 + attribute \src "ls180.v:4993.50-4993.90" + cell $not $not$ls180.v:4993$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4877$744_Y + connect \Y $not$ls180.v:4993$843_Y end - attribute \src "ls180.v:4993.42-4993.74" - cell $not $not$ls180.v:4993$760 + attribute \src "ls180.v:5109.42-5109.74" + cell $not $not$ls180.v:5109$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4993$760_Y + connect \Y $not$ls180.v:5109$859_Y end - attribute \src "ls180.v:5517.50-5517.88" - cell $not $not$ls180.v:5517$1045 + attribute \src "ls180.v:5633.50-5633.88" + cell $not $not$ls180.v:5633$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5517$1045_Y + connect \Y $not$ls180.v:5633$1144_Y end - attribute \src "ls180.v:5529.52-5529.102" - cell $not $not$ls180.v:5529$1048 + attribute \src "ls180.v:5645.52-5645.102" + cell $not $not$ls180.v:5645$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5529$1048_Y + connect \Y $not$ls180.v:5645$1147_Y end - attribute \src "ls180.v:5588.38-5588.74" - cell $not $not$ls180.v:5588$1055 + attribute \src "ls180.v:5704.38-5704.74" + cell $not $not$ls180.v:5704$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5588$1055_Y + connect \Y $not$ls180.v:5704$1154_Y end - attribute \src "ls180.v:5857.69-5857.88" - cell $not $not$ls180.v:5857$1125 + attribute \src "ls180.v:6030.69-6030.88" + cell $not $not$ls180.v:6030$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \Y $not$ls180.v:5857$1125_Y + connect \Y $not$ls180.v:6030$1239_Y end - attribute \src "ls180.v:5874.63-5874.94" - cell $not $not$ls180.v:5874$1155 + attribute \src "ls180.v:6047.63-6047.94" + cell $not $not$ls180.v:6047$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5874$1155_Y + connect \Y $not$ls180.v:6047$1284_Y end - attribute \src "ls180.v:5877.65-5877.96" - cell $not $not$ls180.v:5877$1162 + attribute \src "ls180.v:6050.65-6050.96" + cell $not $not$ls180.v:6050$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5877$1162_Y + connect \Y $not$ls180.v:6050$1291_Y end - attribute \src "ls180.v:5880.65-5880.96" - cell $not $not$ls180.v:5880$1169 + attribute \src "ls180.v:6053.65-6053.96" + cell $not $not$ls180.v:6053$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5880$1169_Y + connect \Y $not$ls180.v:6053$1298_Y end - attribute \src "ls180.v:5883.65-5883.96" - cell $not $not$ls180.v:5883$1176 + attribute \src "ls180.v:6056.65-6056.96" + cell $not $not$ls180.v:6056$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5883$1176_Y + connect \Y $not$ls180.v:6056$1305_Y end - attribute \src "ls180.v:5886.65-5886.96" - cell $not $not$ls180.v:5886$1183 + attribute \src "ls180.v:6059.65-6059.96" + cell $not $not$ls180.v:6059$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5886$1183_Y + connect \Y $not$ls180.v:6059$1312_Y end - attribute \src "ls180.v:5889.68-5889.99" - cell $not $not$ls180.v:5889$1190 + attribute \src "ls180.v:6062.68-6062.99" + cell $not $not$ls180.v:6062$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5889$1190_Y + connect \Y $not$ls180.v:6062$1319_Y end - attribute \src "ls180.v:5892.68-5892.99" - cell $not $not$ls180.v:5892$1197 + attribute \src "ls180.v:6065.68-6065.99" + cell $not $not$ls180.v:6065$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5892$1197_Y + connect \Y $not$ls180.v:6065$1326_Y end - attribute \src "ls180.v:5895.68-5895.99" - cell $not $not$ls180.v:5895$1204 + attribute \src "ls180.v:6068.68-6068.99" + cell $not $not$ls180.v:6068$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5895$1204_Y + connect \Y $not$ls180.v:6068$1333_Y end - attribute \src "ls180.v:5898.68-5898.99" - cell $not $not$ls180.v:5898$1211 + attribute \src "ls180.v:6071.68-6071.99" + cell $not $not$ls180.v:6071$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5898$1211_Y + connect \Y $not$ls180.v:6071$1340_Y end - attribute \src "ls180.v:5912.60-5912.91" - cell $not $not$ls180.v:5912$1219 + attribute \src "ls180.v:6085.60-6085.91" + cell $not $not$ls180.v:6085$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5912$1219_Y + connect \Y $not$ls180.v:6085$1348_Y end - attribute \src "ls180.v:5915.60-5915.91" - cell $not $not$ls180.v:5915$1226 + attribute \src "ls180.v:6088.60-6088.91" + cell $not $not$ls180.v:6088$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5915$1226_Y + connect \Y $not$ls180.v:6088$1355_Y end - attribute \src "ls180.v:5918.60-5918.91" - cell $not $not$ls180.v:5918$1233 + attribute \src "ls180.v:6091.60-6091.91" + cell $not $not$ls180.v:6091$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5918$1233_Y + connect \Y $not$ls180.v:6091$1362_Y end - attribute \src "ls180.v:5921.60-5921.91" - cell $not $not$ls180.v:5921$1240 + attribute \src "ls180.v:6094.60-6094.91" + cell $not $not$ls180.v:6094$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5921$1240_Y + connect \Y $not$ls180.v:6094$1369_Y end - attribute \src "ls180.v:5924.61-5924.92" - cell $not $not$ls180.v:5924$1247 + attribute \src "ls180.v:6097.61-6097.92" + cell $not $not$ls180.v:6097$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5924$1247_Y + connect \Y $not$ls180.v:6097$1376_Y end - attribute \src "ls180.v:5927.61-5927.92" - cell $not $not$ls180.v:5927$1254 + attribute \src "ls180.v:6100.61-6100.92" + cell $not $not$ls180.v:6100$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5927$1254_Y + connect \Y $not$ls180.v:6100$1383_Y end - attribute \src "ls180.v:5938.59-5938.90" - cell $not $not$ls180.v:5938$1262 + attribute \src "ls180.v:6111.59-6111.90" + cell $not $not$ls180.v:6111$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5938$1262_Y + connect \Y $not$ls180.v:6111$1391_Y end - attribute \src "ls180.v:5941.58-5941.89" - cell $not $not$ls180.v:5941$1269 + attribute \src "ls180.v:6114.58-6114.89" + cell $not $not$ls180.v:6114$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5941$1269_Y + connect \Y $not$ls180.v:6114$1398_Y end - attribute \src "ls180.v:5952.64-5952.95" - cell $not $not$ls180.v:5952$1277 + attribute \src "ls180.v:6125.64-6125.95" + cell $not $not$ls180.v:6125$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5952$1277_Y + connect \Y $not$ls180.v:6125$1406_Y end - attribute \src "ls180.v:5955.63-5955.94" - cell $not $not$ls180.v:5955$1284 + attribute \src "ls180.v:6128.63-6128.94" + cell $not $not$ls180.v:6128$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5955$1284_Y + connect \Y $not$ls180.v:6128$1413_Y end - attribute \src "ls180.v:5958.63-5958.94" - cell $not $not$ls180.v:5958$1291 + attribute \src "ls180.v:6131.63-6131.94" + cell $not $not$ls180.v:6131$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5958$1291_Y + connect \Y $not$ls180.v:6131$1420_Y end - attribute \src "ls180.v:5961.63-5961.94" - cell $not $not$ls180.v:5961$1298 + attribute \src "ls180.v:6134.63-6134.94" + cell $not $not$ls180.v:6134$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5961$1298_Y + connect \Y $not$ls180.v:6134$1427_Y end - attribute \src "ls180.v:5964.63-5964.94" - cell $not $not$ls180.v:5964$1305 + attribute \src "ls180.v:6137.63-6137.94" + cell $not $not$ls180.v:6137$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5964$1305_Y + connect \Y $not$ls180.v:6137$1434_Y end - attribute \src "ls180.v:5967.64-5967.95" - cell $not $not$ls180.v:5967$1312 + attribute \src "ls180.v:6140.64-6140.95" + cell $not $not$ls180.v:6140$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5967$1312_Y + connect \Y $not$ls180.v:6140$1441_Y end - attribute \src "ls180.v:5970.64-5970.95" - cell $not $not$ls180.v:5970$1319 + attribute \src "ls180.v:6143.64-6143.95" + cell $not $not$ls180.v:6143$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5970$1319_Y + connect \Y $not$ls180.v:6143$1448_Y end - attribute \src "ls180.v:5973.64-5973.95" - cell $not $not$ls180.v:5973$1326 + attribute \src "ls180.v:6146.64-6146.95" + cell $not $not$ls180.v:6146$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5973$1326_Y + connect \Y $not$ls180.v:6146$1455_Y end - attribute \src "ls180.v:5976.64-5976.95" - cell $not $not$ls180.v:5976$1333 + attribute \src "ls180.v:6149.64-6149.95" + cell $not $not$ls180.v:6149$1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5976$1333_Y + connect \Y $not$ls180.v:6149$1462_Y end - attribute \src "ls180.v:5989.64-5989.95" - cell $not $not$ls180.v:5989$1341 + attribute \src "ls180.v:6162.64-6162.95" + cell $not $not$ls180.v:6162$1470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5989$1341_Y + connect \Y $not$ls180.v:6162$1470_Y end - attribute \src "ls180.v:5992.63-5992.94" - cell $not $not$ls180.v:5992$1348 + attribute \src "ls180.v:6165.63-6165.94" + cell $not $not$ls180.v:6165$1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5992$1348_Y + connect \Y $not$ls180.v:6165$1477_Y end - attribute \src "ls180.v:5995.63-5995.94" - cell $not $not$ls180.v:5995$1355 + attribute \src "ls180.v:6168.63-6168.94" + cell $not $not$ls180.v:6168$1484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5995$1355_Y + connect \Y $not$ls180.v:6168$1484_Y end - attribute \src "ls180.v:5998.63-5998.94" - cell $not $not$ls180.v:5998$1362 + attribute \src "ls180.v:6171.63-6171.94" + cell $not $not$ls180.v:6171$1491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5998$1362_Y + connect \Y $not$ls180.v:6171$1491_Y end - attribute \src "ls180.v:6001.63-6001.94" - cell $not $not$ls180.v:6001$1369 + attribute \src "ls180.v:6174.63-6174.94" + cell $not $not$ls180.v:6174$1498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6001$1369_Y + connect \Y $not$ls180.v:6174$1498_Y end - attribute \src "ls180.v:6004.64-6004.95" - cell $not $not$ls180.v:6004$1376 + attribute \src "ls180.v:6177.64-6177.95" + cell $not $not$ls180.v:6177$1505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6004$1376_Y + connect \Y $not$ls180.v:6177$1505_Y end - attribute \src "ls180.v:6007.64-6007.95" - cell $not $not$ls180.v:6007$1383 + attribute \src "ls180.v:6180.64-6180.95" + cell $not $not$ls180.v:6180$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6007$1383_Y + connect \Y $not$ls180.v:6180$1512_Y end - attribute \src "ls180.v:6010.64-6010.95" - cell $not $not$ls180.v:6010$1390 + attribute \src "ls180.v:6183.64-6183.95" + cell $not $not$ls180.v:6183$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6010$1390_Y + connect \Y $not$ls180.v:6183$1519_Y end - attribute \src "ls180.v:6013.64-6013.95" - cell $not $not$ls180.v:6013$1397 + attribute \src "ls180.v:6186.64-6186.95" + cell $not $not$ls180.v:6186$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6013$1397_Y + connect \Y $not$ls180.v:6186$1526_Y end - attribute \src "ls180.v:6026.66-6026.97" - cell $not $not$ls180.v:6026$1405 + attribute \src "ls180.v:6199.66-6199.97" + cell $not $not$ls180.v:6199$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6026$1405_Y + connect \Y $not$ls180.v:6199$1534_Y end - attribute \src "ls180.v:6029.66-6029.97" - cell $not $not$ls180.v:6029$1412 + attribute \src "ls180.v:6202.66-6202.97" + cell $not $not$ls180.v:6202$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6029$1412_Y + connect \Y $not$ls180.v:6202$1541_Y end - attribute \src "ls180.v:6032.66-6032.97" - cell $not $not$ls180.v:6032$1419 + attribute \src "ls180.v:6205.66-6205.97" + cell $not $not$ls180.v:6205$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6032$1419_Y + connect \Y $not$ls180.v:6205$1548_Y end - attribute \src "ls180.v:6035.66-6035.97" - cell $not $not$ls180.v:6035$1426 + attribute \src "ls180.v:6208.66-6208.97" + cell $not $not$ls180.v:6208$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6035$1426_Y + connect \Y $not$ls180.v:6208$1555_Y end - attribute \src "ls180.v:6038.66-6038.97" - cell $not $not$ls180.v:6038$1433 + attribute \src "ls180.v:6211.66-6211.97" + cell $not $not$ls180.v:6211$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6038$1433_Y + connect \Y $not$ls180.v:6211$1562_Y end - attribute \src "ls180.v:6041.66-6041.97" - cell $not $not$ls180.v:6041$1440 + attribute \src "ls180.v:6214.66-6214.97" + cell $not $not$ls180.v:6214$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6041$1440_Y + connect \Y $not$ls180.v:6214$1569_Y end - attribute \src "ls180.v:6044.66-6044.97" - cell $not $not$ls180.v:6044$1447 + attribute \src "ls180.v:6217.66-6217.97" + cell $not $not$ls180.v:6217$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6044$1447_Y + connect \Y $not$ls180.v:6217$1576_Y end - attribute \src "ls180.v:6047.66-6047.97" - cell $not $not$ls180.v:6047$1454 + attribute \src "ls180.v:6220.66-6220.97" + cell $not $not$ls180.v:6220$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6047$1454_Y + connect \Y $not$ls180.v:6220$1583_Y end - attribute \src "ls180.v:6050.68-6050.99" - cell $not $not$ls180.v:6050$1461 + attribute \src "ls180.v:6223.68-6223.99" + cell $not $not$ls180.v:6223$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6050$1461_Y + connect \Y $not$ls180.v:6223$1590_Y end - attribute \src "ls180.v:6053.68-6053.99" - cell $not $not$ls180.v:6053$1468 + attribute \src "ls180.v:6226.68-6226.99" + cell $not $not$ls180.v:6226$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6053$1468_Y + connect \Y $not$ls180.v:6226$1597_Y end - attribute \src "ls180.v:6056.68-6056.99" - cell $not $not$ls180.v:6056$1475 + attribute \src "ls180.v:6229.68-6229.99" + cell $not $not$ls180.v:6229$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6056$1475_Y + connect \Y $not$ls180.v:6229$1604_Y end - attribute \src "ls180.v:6059.68-6059.99" - cell $not $not$ls180.v:6059$1482 + attribute \src "ls180.v:6232.68-6232.99" + cell $not $not$ls180.v:6232$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6059$1482_Y + connect \Y $not$ls180.v:6232$1611_Y end - attribute \src "ls180.v:6062.68-6062.99" - cell $not $not$ls180.v:6062$1489 + attribute \src "ls180.v:6235.68-6235.99" + cell $not $not$ls180.v:6235$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6062$1489_Y + connect \Y $not$ls180.v:6235$1618_Y end - attribute \src "ls180.v:6065.65-6065.96" - cell $not $not$ls180.v:6065$1496 + attribute \src "ls180.v:6238.65-6238.96" + cell $not $not$ls180.v:6238$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6065$1496_Y + connect \Y $not$ls180.v:6238$1625_Y end - attribute \src "ls180.v:6068.66-6068.97" - cell $not $not$ls180.v:6068$1503 + attribute \src "ls180.v:6241.66-6241.97" + cell $not $not$ls180.v:6241$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6068$1503_Y + connect \Y $not$ls180.v:6241$1632_Y end - attribute \src "ls180.v:6088.70-6088.101" - cell $not $not$ls180.v:6088$1511 + attribute \src "ls180.v:6261.70-6261.101" + cell $not $not$ls180.v:6261$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6088$1511_Y + connect \Y $not$ls180.v:6261$1640_Y end - attribute \src "ls180.v:6091.70-6091.101" - cell $not $not$ls180.v:6091$1518 + attribute \src "ls180.v:6264.70-6264.101" + cell $not $not$ls180.v:6264$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6091$1518_Y + connect \Y $not$ls180.v:6264$1647_Y end - attribute \src "ls180.v:6094.70-6094.101" - cell $not $not$ls180.v:6094$1525 + attribute \src "ls180.v:6267.70-6267.101" + cell $not $not$ls180.v:6267$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6094$1525_Y + connect \Y $not$ls180.v:6267$1654_Y end - attribute \src "ls180.v:6097.70-6097.101" - cell $not $not$ls180.v:6097$1532 + attribute \src "ls180.v:6270.70-6270.101" + cell $not $not$ls180.v:6270$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6097$1532_Y + connect \Y $not$ls180.v:6270$1661_Y end - attribute \src "ls180.v:6100.69-6100.100" - cell $not $not$ls180.v:6100$1539 + attribute \src "ls180.v:6273.69-6273.100" + cell $not $not$ls180.v:6273$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6100$1539_Y + connect \Y $not$ls180.v:6273$1668_Y end - attribute \src "ls180.v:6103.69-6103.100" - cell $not $not$ls180.v:6103$1546 + attribute \src "ls180.v:6276.69-6276.100" + cell $not $not$ls180.v:6276$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6103$1546_Y + connect \Y $not$ls180.v:6276$1675_Y end - attribute \src "ls180.v:6106.69-6106.100" - cell $not $not$ls180.v:6106$1553 + attribute \src "ls180.v:6279.69-6279.100" + cell $not $not$ls180.v:6279$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6106$1553_Y + connect \Y $not$ls180.v:6279$1682_Y end - attribute \src "ls180.v:6109.69-6109.100" - cell $not $not$ls180.v:6109$1560 + attribute \src "ls180.v:6282.69-6282.100" + cell $not $not$ls180.v:6282$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6109$1560_Y + connect \Y $not$ls180.v:6282$1689_Y end - attribute \src "ls180.v:6112.60-6112.91" - cell $not $not$ls180.v:6112$1567 + attribute \src "ls180.v:6285.60-6285.91" + cell $not $not$ls180.v:6285$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6112$1567_Y + connect \Y $not$ls180.v:6285$1696_Y end - attribute \src "ls180.v:6115.71-6115.102" - cell $not $not$ls180.v:6115$1574 + attribute \src "ls180.v:6288.71-6288.102" + cell $not $not$ls180.v:6288$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6115$1574_Y + connect \Y $not$ls180.v:6288$1703_Y end - attribute \src "ls180.v:6118.71-6118.102" - cell $not $not$ls180.v:6118$1581 + attribute \src "ls180.v:6291.71-6291.102" + cell $not $not$ls180.v:6291$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6118$1581_Y + connect \Y $not$ls180.v:6291$1710_Y end - attribute \src "ls180.v:6121.71-6121.102" - cell $not $not$ls180.v:6121$1588 + attribute \src "ls180.v:6294.71-6294.102" + cell $not $not$ls180.v:6294$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6121$1588_Y + connect \Y $not$ls180.v:6294$1717_Y end - attribute \src "ls180.v:6124.71-6124.102" - cell $not $not$ls180.v:6124$1595 + attribute \src "ls180.v:6297.71-6297.102" + cell $not $not$ls180.v:6297$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6124$1595_Y + connect \Y $not$ls180.v:6297$1724_Y end - attribute \src "ls180.v:6127.71-6127.102" - cell $not $not$ls180.v:6127$1602 + attribute \src "ls180.v:6300.71-6300.102" + cell $not $not$ls180.v:6300$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6127$1602_Y + connect \Y $not$ls180.v:6300$1731_Y end - attribute \src "ls180.v:6130.71-6130.102" - cell $not $not$ls180.v:6130$1609 + attribute \src "ls180.v:6303.71-6303.102" + cell $not $not$ls180.v:6303$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6130$1609_Y + connect \Y $not$ls180.v:6303$1738_Y end - attribute \src "ls180.v:6133.70-6133.101" - cell $not $not$ls180.v:6133$1616 + attribute \src "ls180.v:6306.70-6306.101" + cell $not $not$ls180.v:6306$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6133$1616_Y + connect \Y $not$ls180.v:6306$1745_Y end - attribute \src "ls180.v:6136.70-6136.101" - cell $not $not$ls180.v:6136$1623 + attribute \src "ls180.v:6309.70-6309.101" + cell $not $not$ls180.v:6309$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6136$1623_Y + connect \Y $not$ls180.v:6309$1752_Y end - attribute \src "ls180.v:6139.70-6139.101" - cell $not $not$ls180.v:6139$1630 + attribute \src "ls180.v:6312.70-6312.101" + cell $not $not$ls180.v:6312$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6139$1630_Y + connect \Y $not$ls180.v:6312$1759_Y end - attribute \src "ls180.v:6142.70-6142.101" - cell $not $not$ls180.v:6142$1637 + attribute \src "ls180.v:6315.70-6315.101" + cell $not $not$ls180.v:6315$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6142$1637_Y + connect \Y $not$ls180.v:6315$1766_Y end - attribute \src "ls180.v:6145.70-6145.101" - cell $not $not$ls180.v:6145$1644 + attribute \src "ls180.v:6318.70-6318.101" + cell $not $not$ls180.v:6318$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6145$1644_Y + connect \Y $not$ls180.v:6318$1773_Y end - attribute \src "ls180.v:6148.70-6148.101" - cell $not $not$ls180.v:6148$1651 + attribute \src "ls180.v:6321.70-6321.101" + cell $not $not$ls180.v:6321$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6148$1651_Y + connect \Y $not$ls180.v:6321$1780_Y end - attribute \src "ls180.v:6151.70-6151.101" - cell $not $not$ls180.v:6151$1658 + attribute \src "ls180.v:6324.70-6324.101" + cell $not $not$ls180.v:6324$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6151$1658_Y + connect \Y $not$ls180.v:6324$1787_Y end - attribute \src "ls180.v:6154.70-6154.101" - cell $not $not$ls180.v:6154$1665 + attribute \src "ls180.v:6327.70-6327.101" + cell $not $not$ls180.v:6327$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6154$1665_Y + connect \Y $not$ls180.v:6327$1794_Y end - attribute \src "ls180.v:6157.70-6157.101" - cell $not $not$ls180.v:6157$1672 + attribute \src "ls180.v:6330.70-6330.101" + cell $not $not$ls180.v:6330$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6157$1672_Y + connect \Y $not$ls180.v:6330$1801_Y end - attribute \src "ls180.v:6160.70-6160.101" - cell $not $not$ls180.v:6160$1679 + attribute \src "ls180.v:6333.70-6333.101" + cell $not $not$ls180.v:6333$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6160$1679_Y + connect \Y $not$ls180.v:6333$1808_Y end - attribute \src "ls180.v:6163.66-6163.97" - cell $not $not$ls180.v:6163$1686 + attribute \src "ls180.v:6336.66-6336.97" + cell $not $not$ls180.v:6336$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6163$1686_Y + connect \Y $not$ls180.v:6336$1815_Y end - attribute \src "ls180.v:6166.67-6166.98" - cell $not $not$ls180.v:6166$1693 + attribute \src "ls180.v:6339.67-6339.98" + cell $not $not$ls180.v:6339$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6166$1693_Y + connect \Y $not$ls180.v:6339$1822_Y end - attribute \src "ls180.v:6169.70-6169.101" - cell $not $not$ls180.v:6169$1700 + attribute \src "ls180.v:6342.70-6342.101" + cell $not $not$ls180.v:6342$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6169$1700_Y + connect \Y $not$ls180.v:6342$1829_Y end - attribute \src "ls180.v:6172.70-6172.101" - cell $not $not$ls180.v:6172$1707 + attribute \src "ls180.v:6345.70-6345.101" + cell $not $not$ls180.v:6345$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6172$1707_Y + connect \Y $not$ls180.v:6345$1836_Y end - attribute \src "ls180.v:6175.69-6175.100" - cell $not $not$ls180.v:6175$1714 + attribute \src "ls180.v:6348.69-6348.100" + cell $not $not$ls180.v:6348$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6175$1714_Y + connect \Y $not$ls180.v:6348$1843_Y end - attribute \src "ls180.v:6178.69-6178.100" - cell $not $not$ls180.v:6178$1721 + attribute \src "ls180.v:6351.69-6351.100" + cell $not $not$ls180.v:6351$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6178$1721_Y + connect \Y $not$ls180.v:6351$1850_Y end - attribute \src "ls180.v:6181.69-6181.100" - cell $not $not$ls180.v:6181$1728 + attribute \src "ls180.v:6354.69-6354.100" + cell $not $not$ls180.v:6354$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6181$1728_Y + connect \Y $not$ls180.v:6354$1857_Y end - attribute \src "ls180.v:6184.69-6184.100" - cell $not $not$ls180.v:6184$1735 + attribute \src "ls180.v:6357.69-6357.100" + cell $not $not$ls180.v:6357$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6184$1735_Y + connect \Y $not$ls180.v:6357$1864_Y end - attribute \src "ls180.v:6223.66-6223.97" - cell $not $not$ls180.v:6223$1743 + attribute \src "ls180.v:6396.66-6396.97" + cell $not $not$ls180.v:6396$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6223$1743_Y + connect \Y $not$ls180.v:6396$1872_Y end - attribute \src "ls180.v:6226.66-6226.97" - cell $not $not$ls180.v:6226$1750 + attribute \src "ls180.v:6399.66-6399.97" + cell $not $not$ls180.v:6399$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6226$1750_Y + connect \Y $not$ls180.v:6399$1879_Y end - attribute \src "ls180.v:6229.66-6229.97" - cell $not $not$ls180.v:6229$1757 + attribute \src "ls180.v:6402.66-6402.97" + cell $not $not$ls180.v:6402$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6229$1757_Y + connect \Y $not$ls180.v:6402$1886_Y end - attribute \src "ls180.v:6232.66-6232.97" - cell $not $not$ls180.v:6232$1764 + attribute \src "ls180.v:6405.66-6405.97" + cell $not $not$ls180.v:6405$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6232$1764_Y + connect \Y $not$ls180.v:6405$1893_Y end - attribute \src "ls180.v:6235.66-6235.97" - cell $not $not$ls180.v:6235$1771 + attribute \src "ls180.v:6408.66-6408.97" + cell $not $not$ls180.v:6408$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6235$1771_Y + connect \Y $not$ls180.v:6408$1900_Y end - attribute \src "ls180.v:6238.66-6238.97" - cell $not $not$ls180.v:6238$1778 + attribute \src "ls180.v:6411.66-6411.97" + cell $not $not$ls180.v:6411$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6238$1778_Y + connect \Y $not$ls180.v:6411$1907_Y end - attribute \src "ls180.v:6241.66-6241.97" - cell $not $not$ls180.v:6241$1785 + attribute \src "ls180.v:6414.66-6414.97" + cell $not $not$ls180.v:6414$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6241$1785_Y + connect \Y $not$ls180.v:6414$1914_Y end - attribute \src "ls180.v:6244.66-6244.97" - cell $not $not$ls180.v:6244$1792 + attribute \src "ls180.v:6417.66-6417.97" + cell $not $not$ls180.v:6417$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6244$1792_Y + connect \Y $not$ls180.v:6417$1921_Y end - attribute \src "ls180.v:6247.68-6247.99" - cell $not $not$ls180.v:6247$1799 + attribute \src "ls180.v:6420.68-6420.99" + cell $not $not$ls180.v:6420$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6247$1799_Y + connect \Y $not$ls180.v:6420$1928_Y end - attribute \src "ls180.v:6250.68-6250.99" - cell $not $not$ls180.v:6250$1806 + attribute \src "ls180.v:6423.68-6423.99" + cell $not $not$ls180.v:6423$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6250$1806_Y + connect \Y $not$ls180.v:6423$1935_Y end - attribute \src "ls180.v:6253.68-6253.99" - cell $not $not$ls180.v:6253$1813 + attribute \src "ls180.v:6426.68-6426.99" + cell $not $not$ls180.v:6426$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6253$1813_Y + connect \Y $not$ls180.v:6426$1942_Y end - attribute \src "ls180.v:6256.68-6256.99" - cell $not $not$ls180.v:6256$1820 + attribute \src "ls180.v:6429.68-6429.99" + cell $not $not$ls180.v:6429$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6256$1820_Y + connect \Y $not$ls180.v:6429$1949_Y end - attribute \src "ls180.v:6259.68-6259.99" - cell $not $not$ls180.v:6259$1827 + attribute \src "ls180.v:6432.68-6432.99" + cell $not $not$ls180.v:6432$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6259$1827_Y + connect \Y $not$ls180.v:6432$1956_Y end - attribute \src "ls180.v:6262.65-6262.96" - cell $not $not$ls180.v:6262$1834 + attribute \src "ls180.v:6435.65-6435.96" + cell $not $not$ls180.v:6435$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6262$1834_Y + connect \Y $not$ls180.v:6435$1963_Y end - attribute \src "ls180.v:6265.66-6265.97" - cell $not $not$ls180.v:6265$1841 + attribute \src "ls180.v:6438.66-6438.97" + cell $not $not$ls180.v:6438$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6265$1841_Y + connect \Y $not$ls180.v:6438$1970_Y end - attribute \src "ls180.v:6268.68-6268.99" - cell $not $not$ls180.v:6268$1848 + attribute \src "ls180.v:6441.68-6441.99" + cell $not $not$ls180.v:6441$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6268$1848_Y + connect \Y $not$ls180.v:6441$1977_Y end - attribute \src "ls180.v:6271.68-6271.99" - cell $not $not$ls180.v:6271$1855 + attribute \src "ls180.v:6444.68-6444.99" + cell $not $not$ls180.v:6444$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6271$1855_Y + connect \Y $not$ls180.v:6444$1984_Y end - attribute \src "ls180.v:6274.68-6274.99" - cell $not $not$ls180.v:6274$1862 + attribute \src "ls180.v:6447.68-6447.99" + cell $not $not$ls180.v:6447$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6274$1862_Y + connect \Y $not$ls180.v:6447$1991_Y end - attribute \src "ls180.v:6277.68-6277.99" - cell $not $not$ls180.v:6277$1869 + attribute \src "ls180.v:6450.68-6450.99" + cell $not $not$ls180.v:6450$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6277$1869_Y + connect \Y $not$ls180.v:6450$1998_Y end - attribute \src "ls180.v:6302.68-6302.99" - cell $not $not$ls180.v:6302$1877 + attribute \src "ls180.v:6475.68-6475.99" + cell $not $not$ls180.v:6475$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6302$1877_Y + connect \Y $not$ls180.v:6475$2006_Y end - attribute \src "ls180.v:6305.73-6305.104" - cell $not $not$ls180.v:6305$1884 + attribute \src "ls180.v:6478.73-6478.104" + cell $not $not$ls180.v:6478$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6305$1884_Y + connect \Y $not$ls180.v:6478$2013_Y end - attribute \src "ls180.v:6308.73-6308.104" - cell $not $not$ls180.v:6308$1891 + attribute \src "ls180.v:6481.73-6481.104" + cell $not $not$ls180.v:6481$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6308$1891_Y + connect \Y $not$ls180.v:6481$2020_Y end - attribute \src "ls180.v:6311.66-6311.97" - cell $not $not$ls180.v:6311$1898 + attribute \src "ls180.v:6484.66-6484.97" + cell $not $not$ls180.v:6484$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6311$1898_Y + connect \Y $not$ls180.v:6484$2027_Y end - attribute \src "ls180.v:6319.70-6319.101" - cell $not $not$ls180.v:6319$1906 + attribute \src "ls180.v:6492.70-6492.101" + cell $not $not$ls180.v:6492$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6319$1906_Y + connect \Y $not$ls180.v:6492$2035_Y end - attribute \src "ls180.v:6322.74-6322.105" - cell $not $not$ls180.v:6322$1913 + attribute \src "ls180.v:6495.74-6495.105" + cell $not $not$ls180.v:6495$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6322$1913_Y + connect \Y $not$ls180.v:6495$2042_Y end - attribute \src "ls180.v:6325.64-6325.95" - cell $not $not$ls180.v:6325$1920 + attribute \src "ls180.v:6498.64-6498.95" + cell $not $not$ls180.v:6498$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6325$1920_Y + connect \Y $not$ls180.v:6498$2049_Y end - attribute \src "ls180.v:6328.74-6328.105" - cell $not $not$ls180.v:6328$1927 + attribute \src "ls180.v:6501.74-6501.105" + cell $not $not$ls180.v:6501$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6328$1927_Y + connect \Y $not$ls180.v:6501$2056_Y end - attribute \src "ls180.v:6331.74-6331.105" - cell $not $not$ls180.v:6331$1934 + attribute \src "ls180.v:6504.74-6504.105" + cell $not $not$ls180.v:6504$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6331$1934_Y + connect \Y $not$ls180.v:6504$2063_Y end - attribute \src "ls180.v:6334.75-6334.106" - cell $not $not$ls180.v:6334$1941 + attribute \src "ls180.v:6507.75-6507.106" + cell $not $not$ls180.v:6507$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6334$1941_Y + connect \Y $not$ls180.v:6507$2070_Y end - attribute \src "ls180.v:6337.73-6337.104" - cell $not $not$ls180.v:6337$1948 + attribute \src "ls180.v:6510.73-6510.104" + cell $not $not$ls180.v:6510$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6337$1948_Y + connect \Y $not$ls180.v:6510$2077_Y end - attribute \src "ls180.v:6340.73-6340.104" - cell $not $not$ls180.v:6340$1955 + attribute \src "ls180.v:6513.73-6513.104" + cell $not $not$ls180.v:6513$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6340$1955_Y + connect \Y $not$ls180.v:6513$2084_Y end - attribute \src "ls180.v:6343.73-6343.104" - cell $not $not$ls180.v:6343$1962 + attribute \src "ls180.v:6516.73-6516.104" + cell $not $not$ls180.v:6516$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6343$1962_Y + connect \Y $not$ls180.v:6516$2091_Y end - attribute \src "ls180.v:6346.73-6346.104" - cell $not $not$ls180.v:6346$1969 + attribute \src "ls180.v:6519.73-6519.104" + cell $not $not$ls180.v:6519$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6346$1969_Y + connect \Y $not$ls180.v:6519$2098_Y end - attribute \src "ls180.v:6364.67-6364.99" - cell $not $not$ls180.v:6364$1977 + attribute \src "ls180.v:6537.67-6537.99" + cell $not $not$ls180.v:6537$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6364$1977_Y + connect \Y $not$ls180.v:6537$2106_Y end - attribute \src "ls180.v:6367.67-6367.99" - cell $not $not$ls180.v:6367$1984 + attribute \src "ls180.v:6540.67-6540.99" + cell $not $not$ls180.v:6540$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6367$1984_Y + connect \Y $not$ls180.v:6540$2113_Y end - attribute \src "ls180.v:6370.65-6370.97" - cell $not $not$ls180.v:6370$1991 + attribute \src "ls180.v:6543.65-6543.97" + cell $not $not$ls180.v:6543$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6370$1991_Y + connect \Y $not$ls180.v:6543$2120_Y end - attribute \src "ls180.v:6373.64-6373.96" - cell $not $not$ls180.v:6373$1998 + attribute \src "ls180.v:6546.64-6546.96" + cell $not $not$ls180.v:6546$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6373$1998_Y + connect \Y $not$ls180.v:6546$2127_Y end - attribute \src "ls180.v:6376.63-6376.95" - cell $not $not$ls180.v:6376$2005 + attribute \src "ls180.v:6549.63-6549.95" + cell $not $not$ls180.v:6549$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6376$2005_Y + connect \Y $not$ls180.v:6549$2134_Y end - attribute \src "ls180.v:6379.62-6379.94" - cell $not $not$ls180.v:6379$2012 + attribute \src "ls180.v:6552.62-6552.94" + cell $not $not$ls180.v:6552$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6379$2012_Y + connect \Y $not$ls180.v:6552$2141_Y end - attribute \src "ls180.v:6382.68-6382.100" - cell $not $not$ls180.v:6382$2019 + attribute \src "ls180.v:6555.68-6555.100" + cell $not $not$ls180.v:6555$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6382$2019_Y + connect \Y $not$ls180.v:6555$2148_Y end - attribute \src "ls180.v:6404.67-6404.99" - cell $not $not$ls180.v:6404$2028 + attribute \src "ls180.v:6577.67-6577.99" + cell $not $not$ls180.v:6577$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6404$2028_Y + connect \Y $not$ls180.v:6577$2157_Y end - attribute \src "ls180.v:6407.67-6407.99" - cell $not $not$ls180.v:6407$2035 + attribute \src "ls180.v:6580.67-6580.99" + cell $not $not$ls180.v:6580$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6407$2035_Y + connect \Y $not$ls180.v:6580$2164_Y end - attribute \src "ls180.v:6410.65-6410.97" - cell $not $not$ls180.v:6410$2042 + attribute \src "ls180.v:6583.65-6583.97" + cell $not $not$ls180.v:6583$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6410$2042_Y + connect \Y $not$ls180.v:6583$2171_Y end - attribute \src "ls180.v:6413.64-6413.96" - cell $not $not$ls180.v:6413$2049 + attribute \src "ls180.v:6586.64-6586.96" + cell $not $not$ls180.v:6586$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6413$2049_Y + connect \Y $not$ls180.v:6586$2178_Y end - attribute \src "ls180.v:6416.63-6416.95" - cell $not $not$ls180.v:6416$2056 + attribute \src "ls180.v:6589.63-6589.95" + cell $not $not$ls180.v:6589$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6416$2056_Y + connect \Y $not$ls180.v:6589$2185_Y end - attribute \src "ls180.v:6419.62-6419.94" - cell $not $not$ls180.v:6419$2063 + attribute \src "ls180.v:6592.62-6592.94" + cell $not $not$ls180.v:6592$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6419$2063_Y + connect \Y $not$ls180.v:6592$2192_Y end - attribute \src "ls180.v:6422.68-6422.100" - cell $not $not$ls180.v:6422$2070 + attribute \src "ls180.v:6595.68-6595.100" + cell $not $not$ls180.v:6595$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6422$2070_Y + connect \Y $not$ls180.v:6595$2199_Y end - attribute \src "ls180.v:6425.71-6425.103" - cell $not $not$ls180.v:6425$2077 + attribute \src "ls180.v:6598.71-6598.103" + cell $not $not$ls180.v:6598$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6425$2077_Y + connect \Y $not$ls180.v:6598$2206_Y end - attribute \src "ls180.v:6428.71-6428.103" - cell $not $not$ls180.v:6428$2084 + attribute \src "ls180.v:6601.71-6601.103" + cell $not $not$ls180.v:6601$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6428$2084_Y + connect \Y $not$ls180.v:6601$2213_Y end - attribute \src "ls180.v:6452.64-6452.96" - cell $not $not$ls180.v:6452$2093 + attribute \src "ls180.v:6625.64-6625.96" + cell $not $not$ls180.v:6625$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6452$2093_Y + connect \Y $not$ls180.v:6625$2222_Y end - attribute \src "ls180.v:6455.64-6455.96" - cell $not $not$ls180.v:6455$2100 + attribute \src "ls180.v:6628.64-6628.96" + cell $not $not$ls180.v:6628$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6455$2100_Y + connect \Y $not$ls180.v:6628$2229_Y end - attribute \src "ls180.v:6458.64-6458.96" - cell $not $not$ls180.v:6458$2107 + attribute \src "ls180.v:6631.64-6631.96" + cell $not $not$ls180.v:6631$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6458$2107_Y + connect \Y $not$ls180.v:6631$2236_Y end - attribute \src "ls180.v:6461.64-6461.96" - cell $not $not$ls180.v:6461$2114 + attribute \src "ls180.v:6634.64-6634.96" + cell $not $not$ls180.v:6634$2243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6461$2114_Y + connect \Y $not$ls180.v:6634$2243_Y end - attribute \src "ls180.v:6464.66-6464.98" - cell $not $not$ls180.v:6464$2121 + attribute \src "ls180.v:6637.66-6637.98" + cell $not $not$ls180.v:6637$2250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6464$2121_Y + connect \Y $not$ls180.v:6637$2250_Y end - attribute \src "ls180.v:6467.66-6467.98" - cell $not $not$ls180.v:6467$2128 + attribute \src "ls180.v:6640.66-6640.98" + cell $not $not$ls180.v:6640$2257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6467$2128_Y + connect \Y $not$ls180.v:6640$2257_Y end - attribute \src "ls180.v:6470.66-6470.98" - cell $not $not$ls180.v:6470$2135 + attribute \src "ls180.v:6643.66-6643.98" + cell $not $not$ls180.v:6643$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6470$2135_Y + connect \Y $not$ls180.v:6643$2264_Y end - attribute \src "ls180.v:6473.66-6473.98" - cell $not $not$ls180.v:6473$2142 + attribute \src "ls180.v:6646.66-6646.98" + cell $not $not$ls180.v:6646$2271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6473$2142_Y + connect \Y $not$ls180.v:6646$2271_Y end - attribute \src "ls180.v:6476.62-6476.94" - cell $not $not$ls180.v:6476$2149 + attribute \src "ls180.v:6649.62-6649.94" + cell $not $not$ls180.v:6649$2278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6476$2149_Y + connect \Y $not$ls180.v:6649$2278_Y end - attribute \src "ls180.v:6479.72-6479.104" - cell $not $not$ls180.v:6479$2156 + attribute \src "ls180.v:6652.72-6652.104" + cell $not $not$ls180.v:6652$2285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6479$2156_Y + connect \Y $not$ls180.v:6652$2285_Y end - attribute \src "ls180.v:6482.65-6482.97" - cell $not $not$ls180.v:6482$2163 + attribute \src "ls180.v:6655.65-6655.97" + cell $not $not$ls180.v:6655$2292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6482$2163_Y + connect \Y $not$ls180.v:6655$2292_Y end - attribute \src "ls180.v:6485.65-6485.97" - cell $not $not$ls180.v:6485$2170 + attribute \src "ls180.v:6658.65-6658.97" + cell $not $not$ls180.v:6658$2299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6485$2170_Y + connect \Y $not$ls180.v:6658$2299_Y end - attribute \src "ls180.v:6488.65-6488.97" - cell $not $not$ls180.v:6488$2177 + attribute \src "ls180.v:6661.65-6661.97" + cell $not $not$ls180.v:6661$2306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6488$2177_Y + connect \Y $not$ls180.v:6661$2306_Y end - attribute \src "ls180.v:6491.65-6491.97" - cell $not $not$ls180.v:6491$2184 + attribute \src "ls180.v:6664.65-6664.97" + cell $not $not$ls180.v:6664$2313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6491$2184_Y + connect \Y $not$ls180.v:6664$2313_Y end - attribute \src "ls180.v:6494.77-6494.109" - cell $not $not$ls180.v:6494$2191 + attribute \src "ls180.v:6667.77-6667.109" + cell $not $not$ls180.v:6667$2320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6494$2191_Y + connect \Y $not$ls180.v:6667$2320_Y end - attribute \src "ls180.v:6497.78-6497.110" - cell $not $not$ls180.v:6497$2198 + attribute \src "ls180.v:6670.78-6670.110" + cell $not $not$ls180.v:6670$2327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6497$2198_Y + connect \Y $not$ls180.v:6670$2327_Y end - attribute \src "ls180.v:6500.69-6500.101" - cell $not $not$ls180.v:6500$2205 + attribute \src "ls180.v:6673.69-6673.101" + cell $not $not$ls180.v:6673$2334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6500$2205_Y + connect \Y $not$ls180.v:6673$2334_Y end - attribute \src "ls180.v:6520.55-6520.87" - cell $not $not$ls180.v:6520$2213 + attribute \src "ls180.v:6693.55-6693.87" + cell $not $not$ls180.v:6693$2342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6520$2213_Y + connect \Y $not$ls180.v:6693$2342_Y end - attribute \src "ls180.v:6523.65-6523.97" - cell $not $not$ls180.v:6523$2220 + attribute \src "ls180.v:6696.65-6696.97" + cell $not $not$ls180.v:6696$2349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6523$2220_Y + connect \Y $not$ls180.v:6696$2349_Y end - attribute \src "ls180.v:6526.66-6526.98" - cell $not $not$ls180.v:6526$2227 + attribute \src "ls180.v:6699.66-6699.98" + cell $not $not$ls180.v:6699$2356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6526$2227_Y + connect \Y $not$ls180.v:6699$2356_Y end - attribute \src "ls180.v:6529.70-6529.102" - cell $not $not$ls180.v:6529$2234 + attribute \src "ls180.v:6702.70-6702.102" + cell $not $not$ls180.v:6702$2363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6529$2234_Y + connect \Y $not$ls180.v:6702$2363_Y end - attribute \src "ls180.v:6532.71-6532.103" - cell $not $not$ls180.v:6532$2241 + attribute \src "ls180.v:6705.71-6705.103" + cell $not $not$ls180.v:6705$2370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6532$2241_Y + connect \Y $not$ls180.v:6705$2370_Y end - attribute \src "ls180.v:6535.69-6535.101" - cell $not $not$ls180.v:6535$2248 + attribute \src "ls180.v:6708.69-6708.101" + cell $not $not$ls180.v:6708$2377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6535$2248_Y + connect \Y $not$ls180.v:6708$2377_Y end - attribute \src "ls180.v:6538.66-6538.98" - cell $not $not$ls180.v:6538$2255 + attribute \src "ls180.v:6711.66-6711.98" + cell $not $not$ls180.v:6711$2384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6538$2255_Y + connect \Y $not$ls180.v:6711$2384_Y end - attribute \src "ls180.v:6541.65-6541.97" - cell $not $not$ls180.v:6541$2262 + attribute \src "ls180.v:6714.65-6714.97" + cell $not $not$ls180.v:6714$2391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6541$2262_Y + connect \Y $not$ls180.v:6714$2391_Y end - attribute \src "ls180.v:6554.71-6554.103" - cell $not $not$ls180.v:6554$2270 + attribute \src "ls180.v:6727.71-6727.103" + cell $not $not$ls180.v:6727$2399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6554$2270_Y + connect \Y $not$ls180.v:6727$2399_Y end - attribute \src "ls180.v:6557.71-6557.103" - cell $not $not$ls180.v:6557$2277 + attribute \src "ls180.v:6730.71-6730.103" + cell $not $not$ls180.v:6730$2406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6557$2277_Y + connect \Y $not$ls180.v:6730$2406_Y end - attribute \src "ls180.v:6560.71-6560.103" - cell $not $not$ls180.v:6560$2284 + attribute \src "ls180.v:6733.71-6733.103" + cell $not $not$ls180.v:6733$2413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6560$2284_Y + connect \Y $not$ls180.v:6733$2413_Y end - attribute \src "ls180.v:6563.71-6563.103" - cell $not $not$ls180.v:6563$2291 + attribute \src "ls180.v:6736.71-6736.103" + cell $not $not$ls180.v:6736$2420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6563$2291_Y + connect \Y $not$ls180.v:6736$2420_Y end - attribute \src "ls180.v:6944.86-6944.330" - cell $not $not$ls180.v:6944$2340 + attribute \src "ls180.v:7117.86-7117.330" + cell $not $not$ls180.v:7117$2469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6944$2339_Y - connect \Y $not$ls180.v:6944$2340_Y + connect \A $or$ls180.v:7117$2468_Y + connect \Y $not$ls180.v:7117$2469_Y end - attribute \src "ls180.v:6968.86-6968.330" - cell $not $not$ls180.v:6968$2356 + attribute \src "ls180.v:7141.86-7141.330" + cell $not $not$ls180.v:7141$2485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6968$2355_Y - connect \Y $not$ls180.v:6968$2356_Y + connect \A $or$ls180.v:7141$2484_Y + connect \Y $not$ls180.v:7141$2485_Y end - attribute \src "ls180.v:6992.86-6992.330" - cell $not $not$ls180.v:6992$2372 + attribute \src "ls180.v:7165.86-7165.330" + cell $not $not$ls180.v:7165$2501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6992$2371_Y - connect \Y $not$ls180.v:6992$2372_Y + connect \A $or$ls180.v:7165$2500_Y + connect \Y $not$ls180.v:7165$2501_Y end - attribute \src "ls180.v:7016.86-7016.330" - cell $not $not$ls180.v:7016$2388 + attribute \src "ls180.v:7189.86-7189.330" + cell $not $not$ls180.v:7189$2517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7016$2387_Y - connect \Y $not$ls180.v:7016$2388_Y + connect \A $or$ls180.v:7189$2516_Y + connect \Y $not$ls180.v:7189$2517_Y end - attribute \src "ls180.v:7514.18-7514.42" - cell $not $not$ls180.v:7514$2441 + attribute \src "ls180.v:7690.18-7690.42" + cell $not $not$ls180.v:7690$2571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7514$2441_Y + connect \Y $not$ls180.v:7690$2571_Y end - attribute \src "ls180.v:7593.72-7593.101" - cell $not $not$ls180.v:7593$2474 + attribute \src "ls180.v:7769.72-7769.101" + cell $not $not$ls180.v:7769$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7593$2474_Y + connect \Y $not$ls180.v:7769$2604_Y end - attribute \src "ls180.v:7612.8-7612.38" - cell $not $not$ls180.v:7612$2478 + attribute \src "ls180.v:7788.8-7788.38" + cell $not $not$ls180.v:7788$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7612$2478_Y + connect \Y $not$ls180.v:7788$2608_Y end - attribute \src "ls180.v:7616.70-7616.98" - cell $not $not$ls180.v:7616$2481 + attribute \src "ls180.v:7792.70-7792.98" + cell $not $not$ls180.v:7792$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_ack - connect \Y $not$ls180.v:7616$2481_Y + connect \Y $not$ls180.v:7792$2611_Y end - attribute \src "ls180.v:7620.70-7620.98" - cell $not $not$ls180.v:7620$2484 + attribute \src "ls180.v:7796.70-7796.98" + cell $not $not$ls180.v:7796$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_ack - connect \Y $not$ls180.v:7620$2484_Y + connect \Y $not$ls180.v:7796$2614_Y end - attribute \src "ls180.v:7624.70-7624.98" - cell $not $not$ls180.v:7624$2487 + attribute \src "ls180.v:7800.70-7800.98" + cell $not $not$ls180.v:7800$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_ack - connect \Y $not$ls180.v:7624$2487_Y + connect \Y $not$ls180.v:7800$2617_Y + end + attribute \src "ls180.v:7804.70-7804.98" + cell $not $not$ls180.v:7804$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_ack + connect \Y $not$ls180.v:7804$2620_Y end - attribute \src "ls180.v:7632.32-7632.55" - cell $not $not$ls180.v:7632$2489 + attribute \src "ls180.v:7812.32-7812.55" + cell $not $not$ls180.v:7812$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7632$2489_Y + connect \Y $not$ls180.v:7812$2622_Y end - attribute \src "ls180.v:7702.136-7702.189" - cell $not $not$ls180.v:7702$2504 + attribute \src "ls180.v:7882.136-7882.189" + cell $not $not$ls180.v:7882$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7702$2504_Y + connect \Y $not$ls180.v:7882$2637_Y end - attribute \src "ls180.v:7708.136-7708.189" - cell $not $not$ls180.v:7708$2509 + attribute \src "ls180.v:7888.136-7888.189" + cell $not $not$ls180.v:7888$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7708$2509_Y + connect \Y $not$ls180.v:7888$2642_Y end - attribute \src "ls180.v:7709.8-7709.61" - cell $not $not$ls180.v:7709$2511 + attribute \src "ls180.v:7889.8-7889.61" + cell $not $not$ls180.v:7889$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7709$2511_Y + connect \Y $not$ls180.v:7889$2644_Y end - attribute \src "ls180.v:7717.8-7717.56" - cell $not $not$ls180.v:7717$2514 + attribute \src "ls180.v:7897.8-7897.56" + cell $not $not$ls180.v:7897$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7717$2514_Y + connect \Y $not$ls180.v:7897$2647_Y end - attribute \src "ls180.v:7732.8-7732.46" - cell $not $not$ls180.v:7732$2516 + attribute \src "ls180.v:7912.8-7912.46" + cell $not $not$ls180.v:7912$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7732$2516_Y + connect \Y $not$ls180.v:7912$2649_Y end - attribute \src "ls180.v:7748.136-7748.189" - cell $not $not$ls180.v:7748$2520 + attribute \src "ls180.v:7928.136-7928.189" + cell $not $not$ls180.v:7928$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7748$2520_Y + connect \Y $not$ls180.v:7928$2653_Y end - attribute \src "ls180.v:7754.136-7754.189" - cell $not $not$ls180.v:7754$2525 + attribute \src "ls180.v:7934.136-7934.189" + cell $not $not$ls180.v:7934$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7754$2525_Y + connect \Y $not$ls180.v:7934$2658_Y end - attribute \src "ls180.v:7755.8-7755.61" - cell $not $not$ls180.v:7755$2527 + attribute \src "ls180.v:7935.8-7935.61" + cell $not $not$ls180.v:7935$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7755$2527_Y + connect \Y $not$ls180.v:7935$2660_Y end - attribute \src "ls180.v:7763.8-7763.56" - cell $not $not$ls180.v:7763$2530 + attribute \src "ls180.v:7943.8-7943.56" + cell $not $not$ls180.v:7943$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7763$2530_Y + connect \Y $not$ls180.v:7943$2663_Y end - attribute \src "ls180.v:7778.8-7778.46" - cell $not $not$ls180.v:7778$2532 + attribute \src "ls180.v:7958.8-7958.46" + cell $not $not$ls180.v:7958$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7778$2532_Y + connect \Y $not$ls180.v:7958$2665_Y end - attribute \src "ls180.v:7794.136-7794.189" - cell $not $not$ls180.v:7794$2536 + attribute \src "ls180.v:7974.136-7974.189" + cell $not $not$ls180.v:7974$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7794$2536_Y + connect \Y $not$ls180.v:7974$2669_Y end - attribute \src "ls180.v:7800.136-7800.189" - cell $not $not$ls180.v:7800$2541 + attribute \src "ls180.v:7980.136-7980.189" + cell $not $not$ls180.v:7980$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7800$2541_Y + connect \Y $not$ls180.v:7980$2674_Y end - attribute \src "ls180.v:7801.8-7801.61" - cell $not $not$ls180.v:7801$2543 + attribute \src "ls180.v:7981.8-7981.61" + cell $not $not$ls180.v:7981$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7801$2543_Y + connect \Y $not$ls180.v:7981$2676_Y end - attribute \src "ls180.v:7809.8-7809.56" - cell $not $not$ls180.v:7809$2546 + attribute \src "ls180.v:7989.8-7989.56" + cell $not $not$ls180.v:7989$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7809$2546_Y + connect \Y $not$ls180.v:7989$2679_Y end - attribute \src "ls180.v:7824.8-7824.46" - cell $not $not$ls180.v:7824$2548 + attribute \src "ls180.v:8004.8-8004.46" + cell $not $not$ls180.v:8004$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7824$2548_Y + connect \Y $not$ls180.v:8004$2681_Y end - attribute \src "ls180.v:7840.136-7840.189" - cell $not $not$ls180.v:7840$2552 + attribute \src "ls180.v:8020.136-8020.189" + cell $not $not$ls180.v:8020$2685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7840$2552_Y + connect \Y $not$ls180.v:8020$2685_Y end - attribute \src "ls180.v:7846.136-7846.189" - cell $not $not$ls180.v:7846$2557 + attribute \src "ls180.v:8026.136-8026.189" + cell $not $not$ls180.v:8026$2690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7846$2557_Y + connect \Y $not$ls180.v:8026$2690_Y end - attribute \src "ls180.v:7847.8-7847.61" - cell $not $not$ls180.v:7847$2559 + attribute \src "ls180.v:8027.8-8027.61" + cell $not $not$ls180.v:8027$2692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7847$2559_Y + connect \Y $not$ls180.v:8027$2692_Y end - attribute \src "ls180.v:7855.8-7855.56" - cell $not $not$ls180.v:7855$2562 + attribute \src "ls180.v:8035.8-8035.56" + cell $not $not$ls180.v:8035$2695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7855$2562_Y + connect \Y $not$ls180.v:8035$2695_Y end - attribute \src "ls180.v:7870.8-7870.46" - cell $not $not$ls180.v:7870$2564 + attribute \src "ls180.v:8050.8-8050.46" + cell $not $not$ls180.v:8050$2697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7870$2564_Y + connect \Y $not$ls180.v:8050$2697_Y end - attribute \src "ls180.v:7878.7-7878.22" - cell $not $not$ls180.v:7878$2567 + attribute \src "ls180.v:8058.7-8058.22" + cell $not $not$ls180.v:8058$2700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7878$2567_Y + connect \Y $not$ls180.v:8058$2700_Y end - attribute \src "ls180.v:7881.8-7881.29" - cell $not $not$ls180.v:7881$2568 + attribute \src "ls180.v:8061.8-8061.29" + cell $not $not$ls180.v:8061$2701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7881$2568_Y + connect \Y $not$ls180.v:8061$2701_Y end - attribute \src "ls180.v:7885.7-7885.22" - cell $not $not$ls180.v:7885$2570 + attribute \src "ls180.v:8065.7-8065.22" + cell $not $not$ls180.v:8065$2703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7885$2570_Y + connect \Y $not$ls180.v:8065$2703_Y end - attribute \src "ls180.v:7888.8-7888.29" - cell $not $not$ls180.v:7888$2571 + attribute \src "ls180.v:8068.8-8068.29" + cell $not $not$ls180.v:8068$2704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7888$2571_Y + connect \Y $not$ls180.v:8068$2704_Y end - attribute \src "ls180.v:8007.30-8007.60" - cell $not $not$ls180.v:8007$2573 + attribute \src "ls180.v:8187.30-8187.60" + cell $not $not$ls180.v:8187$2706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:8007$2573_Y + connect \Y $not$ls180.v:8187$2706_Y end - attribute \src "ls180.v:8008.30-8008.60" - cell $not $not$ls180.v:8008$2574 + attribute \src "ls180.v:8188.30-8188.60" + cell $not $not$ls180.v:8188$2707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:8008$2574_Y + connect \Y $not$ls180.v:8188$2707_Y end - attribute \src "ls180.v:8009.29-8009.59" - cell $not $not$ls180.v:8009$2575 + attribute \src "ls180.v:8189.29-8189.59" + cell $not $not$ls180.v:8189$2708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:8009$2575_Y + connect \Y $not$ls180.v:8189$2708_Y end - attribute \src "ls180.v:8020.8-8020.33" - cell $not $not$ls180.v:8020$2576 + attribute \src "ls180.v:8200.8-8200.33" + cell $not $not$ls180.v:8200$2709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:8020$2576_Y + connect \Y $not$ls180.v:8200$2709_Y end - attribute \src "ls180.v:8035.8-8035.33" - cell $not $not$ls180.v:8035$2579 + attribute \src "ls180.v:8215.8-8215.33" + cell $not $not$ls180.v:8215$2712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8035$2579_Y + connect \Y $not$ls180.v:8215$2712_Y end - attribute \src "ls180.v:8071.36-8071.58" - cell $not $not$ls180.v:8071$2609 + attribute \src "ls180.v:8251.36-8251.58" + cell $not $not$ls180.v:8251$2742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8071$2609_Y + connect \Y $not$ls180.v:8251$2742_Y end - attribute \src "ls180.v:8071.64-8071.89" - cell $not $not$ls180.v:8071$2611 + attribute \src "ls180.v:8251.64-8251.89" + cell $not $not$ls180.v:8251$2744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8071$2611_Y + connect \Y $not$ls180.v:8251$2744_Y end - attribute \src "ls180.v:8100.7-8100.29" - cell $not $not$ls180.v:8100$2618 + attribute \src "ls180.v:8280.7-8280.29" + cell $not $not$ls180.v:8280$2751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8100$2618_Y + connect \Y $not$ls180.v:8280$2751_Y end - attribute \src "ls180.v:8101.9-8101.26" - cell $not $not$ls180.v:8101$2619 + attribute \src "ls180.v:8281.9-8281.26" + cell $not $not$ls180.v:8281$2752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8101$2619_Y + connect \Y $not$ls180.v:8281$2752_Y end - attribute \src "ls180.v:8134.8-8134.29" - cell $not $not$ls180.v:8134$2625 + attribute \src "ls180.v:8314.8-8314.29" + cell $not $not$ls180.v:8314$2758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8134$2625_Y + connect \Y $not$ls180.v:8314$2758_Y end - attribute \src "ls180.v:8141.8-8141.29" - cell $not $not$ls180.v:8141$2627 + attribute \src "ls180.v:8321.8-8321.29" + cell $not $not$ls180.v:8321$2760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8141$2627_Y + connect \Y $not$ls180.v:8321$2760_Y end - attribute \src "ls180.v:8151.80-8151.106" - cell $not $not$ls180.v:8151$2630 + attribute \src "ls180.v:8331.80-8331.106" + cell $not $not$ls180.v:8331$2763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8151$2630_Y + connect \Y $not$ls180.v:8331$2763_Y end - attribute \src "ls180.v:8157.80-8157.106" - cell $not $not$ls180.v:8157$2635 + attribute \src "ls180.v:8337.80-8337.106" + cell $not $not$ls180.v:8337$2768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8157$2635_Y + connect \Y $not$ls180.v:8337$2768_Y end - attribute \src "ls180.v:8158.8-8158.34" - cell $not $not$ls180.v:8158$2637 + attribute \src "ls180.v:8338.8-8338.34" + cell $not $not$ls180.v:8338$2770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8158$2637_Y + connect \Y $not$ls180.v:8338$2770_Y end - attribute \src "ls180.v:8173.80-8173.106" - cell $not $not$ls180.v:8173$2641 + attribute \src "ls180.v:8353.80-8353.106" + cell $not $not$ls180.v:8353$2774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8173$2641_Y + connect \Y $not$ls180.v:8353$2774_Y end - attribute \src "ls180.v:8179.80-8179.106" - cell $not $not$ls180.v:8179$2646 + attribute \src "ls180.v:8359.80-8359.106" + cell $not $not$ls180.v:8359$2779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8179$2646_Y + connect \Y $not$ls180.v:8359$2779_Y end - attribute \src "ls180.v:8180.8-8180.34" - cell $not $not$ls180.v:8180$2648 + attribute \src "ls180.v:8360.8-8360.34" + cell $not $not$ls180.v:8360$2781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8180$2648_Y + connect \Y $not$ls180.v:8360$2781_Y end - attribute \src "ls180.v:8211.22-8211.41" - cell $not $not$ls180.v:8211$2652 + attribute \src "ls180.v:8391.22-8391.41" + cell $not $not$ls180.v:8391$2785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8211$2652_Y + connect \Y $not$ls180.v:8391$2785_Y end - attribute \src "ls180.v:8211.46-8211.73" - cell $not $not$ls180.v:8211$2653 + attribute \src "ls180.v:8391.46-8391.73" + cell $not $not$ls180.v:8391$2786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8211$2653_Y + connect \Y $not$ls180.v:8391$2786_Y end - attribute \src "ls180.v:8246.22-8246.40" - cell $not $not$ls180.v:8246$2657 + attribute \src "ls180.v:8426.22-8426.40" + cell $not $not$ls180.v:8426$2790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8246$2657_Y + connect \Y $not$ls180.v:8426$2790_Y end - attribute \src "ls180.v:8246.45-8246.70" - cell $not $not$ls180.v:8246$2658 + attribute \src "ls180.v:8426.45-8426.70" + cell $not $not$ls180.v:8426$2791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8246$2658_Y + connect \Y $not$ls180.v:8426$2791_Y end - attribute \src "ls180.v:8300.7-8300.31" - cell $not $not$ls180.v:8300$2669 + attribute \src "ls180.v:8480.7-8480.31" + cell $not $not$ls180.v:8480$2802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8300$2669_Y + connect \Y $not$ls180.v:8480$2802_Y end - attribute \src "ls180.v:8372.8-8372.46" - cell $not $not$ls180.v:8372$2681 + attribute \src "ls180.v:8552.8-8552.46" + cell $not $not$ls180.v:8552$2814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8372$2681_Y + connect \Y $not$ls180.v:8552$2814_Y end - attribute \src "ls180.v:8453.8-8453.47" - cell $not $not$ls180.v:8453$2693 + attribute \src "ls180.v:8633.8-8633.47" + cell $not $not$ls180.v:8633$2826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8453$2693_Y + connect \Y $not$ls180.v:8633$2826_Y end - attribute \src "ls180.v:8514.8-8514.48" - cell $not $not$ls180.v:8514$2705 + attribute \src "ls180.v:8694.8-8694.48" + cell $not $not$ls180.v:8694$2838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8514$2705_Y + connect \Y $not$ls180.v:8694$2838_Y end - attribute \src "ls180.v:8684.88-8684.118" - cell $not $not$ls180.v:8684$2719 + attribute \src "ls180.v:8864.88-8864.118" + cell $not $not$ls180.v:8864$2852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8684$2719_Y + connect \Y $not$ls180.v:8864$2852_Y end - attribute \src "ls180.v:8690.88-8690.118" - cell $not $not$ls180.v:8690$2724 + attribute \src "ls180.v:8870.88-8870.118" + cell $not $not$ls180.v:8870$2857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8690$2724_Y + connect \Y $not$ls180.v:8870$2857_Y end - attribute \src "ls180.v:8691.8-8691.38" - cell $not $not$ls180.v:8691$2726 + attribute \src "ls180.v:8871.8-8871.38" + cell $not $not$ls180.v:8871$2859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8691$2726_Y + connect \Y $not$ls180.v:8871$2859_Y end - attribute \src "ls180.v:8770.88-8770.118" - cell $not $not$ls180.v:8770$2741 + attribute \src "ls180.v:8962.88-8962.118" + cell $not $not$ls180.v:8962$2874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8770$2741_Y + connect \Y $not$ls180.v:8962$2874_Y end - attribute \src "ls180.v:8776.88-8776.118" - cell $not $not$ls180.v:8776$2746 + attribute \src "ls180.v:8968.88-8968.118" + cell $not $not$ls180.v:8968$2879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8776$2746_Y + connect \Y $not$ls180.v:8968$2879_Y end - attribute \src "ls180.v:8777.8-8777.38" - cell $not $not$ls180.v:8777$2748 + attribute \src "ls180.v:8969.8-8969.38" + cell $not $not$ls180.v:8969$2881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8777$2748_Y + connect \Y $not$ls180.v:8969$2881_Y end - attribute \src "ls180.v:8797.9-8797.28" - cell $not $not$ls180.v:8797$2751 + attribute \src "ls180.v:8989.9-8989.28" + cell $not $not$ls180.v:8989$2884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8797$2751_Y + connect \Y $not$ls180.v:8989$2884_Y end - attribute \src "ls180.v:8816.9-8816.28" - cell $not $not$ls180.v:8816$2752 + attribute \src "ls180.v:9008.9-9008.28" + cell $not $not$ls180.v:9008$2885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:8816$2752_Y + connect \Y $not$ls180.v:9008$2885_Y end - attribute \src "ls180.v:8835.9-8835.28" - cell $not $not$ls180.v:8835$2753 + attribute \src "ls180.v:9027.9-9027.28" + cell $not $not$ls180.v:9027$2886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:8835$2753_Y + connect \Y $not$ls180.v:9027$2886_Y end - attribute \src "ls180.v:8854.9-8854.28" - cell $not $not$ls180.v:8854$2754 + attribute \src "ls180.v:9046.9-9046.28" + cell $not $not$ls180.v:9046$2887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:8854$2754_Y + connect \Y $not$ls180.v:9046$2887_Y end - attribute \src "ls180.v:8873.9-8873.28" - cell $not $not$ls180.v:8873$2755 + attribute \src "ls180.v:9065.9-9065.28" + cell $not $not$ls180.v:9065$2888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:8873$2755_Y + connect \Y $not$ls180.v:9065$2888_Y end - attribute \src "ls180.v:8894.8-8894.21" - cell $not $not$ls180.v:8894$2756 + attribute \src "ls180.v:9086.8-9086.21" + cell $not $not$ls180.v:9086$2889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:8894$2756_Y + connect \Y $not$ls180.v:9086$2889_Y end - attribute \src "ls180.v:10456.8-10456.51" - cell $or $or$ls180.v:10456$2870 + attribute \src "ls180.v:10709.8-10709.51" + cell $or $or$ls180.v:10709$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258226,54 +276095,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10456$2870_Y + connect \Y $or$ls180.v:10709$3077_Y end - attribute \src "ls180.v:2859.10-2859.96" - cell $or $or$ls180.v:2859$33 + attribute \src "ls180.v:2934.10-2934.71" + cell $or $or$ls180.v:2934$57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:2859$33_Y + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:2934$57_Y end - attribute \src "ls180.v:2919.10-2919.96" - cell $or $or$ls180.v:2919$44 + attribute \src "ls180.v:2994.10-2994.71" + cell $or $or$ls180.v:2994$68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:2919$44_Y + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:2994$68_Y end - attribute \src "ls180.v:2979.10-2979.96" - cell $or $or$ls180.v:2979$55 + attribute \src "ls180.v:3054.10-3054.53" + cell $or $or$ls180.v:3054$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:2979$55_Y + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:3054$79_Y end - attribute \src "ls180.v:3201.39-3201.105" - cell $or $or$ls180.v:3201$126 + attribute \src "ls180.v:3306.39-3306.105" + cell $or $or$ls180.v:3306$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3201$125_Y - connect \Y $or$ls180.v:3201$126_Y + connect \B $ne$ls180.v:3306$222_Y + connect \Y $or$ls180.v:3306$223_Y end - attribute \src "ls180.v:3244.59-3244.140" - cell $or $or$ls180.v:3244$130 + attribute \src "ls180.v:3349.59-3349.140" + cell $or $or$ls180.v:3349$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258281,10 +276150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_req_wdata_ready connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3244$130_Y + connect \Y $or$ls180.v:3349$227_Y end - attribute \src "ls180.v:3245.44-3245.151" - cell $or $or$ls180.v:3245$131 + attribute \src "ls180.v:3350.44-3350.151" + cell $or $or$ls180.v:3350$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258292,21 +276161,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3245$131_Y + connect \Y $or$ls180.v:3350$228_Y end - attribute \src "ls180.v:3253.45-3253.170" - cell $or $or$ls180.v:3253$135 + attribute \src "ls180.v:3358.45-3358.170" + cell $or $or$ls180.v:3358$232 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3253$134_Y + connect \A $sshl$ls180.v:3358$231_Y connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3253$135_Y + connect \Y $or$ls180.v:3358$232_Y end - attribute \src "ls180.v:3290.127-3290.245" - cell $or $or$ls180.v:3290$148 + attribute \src "ls180.v:3395.127-3395.245" + cell $or $or$ls180.v:3395$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258314,21 +276183,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3290$148_Y + connect \Y $or$ls180.v:3395$245_Y end - attribute \src "ls180.v:3296.57-3296.157" - cell $or $or$ls180.v:3296$154 + attribute \src "ls180.v:3401.57-3401.157" + cell $or $or$ls180.v:3401$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3296$153_Y + connect \A $not$ls180.v:3401$250_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3296$154_Y + connect \Y $or$ls180.v:3401$251_Y end - attribute \src "ls180.v:3401.59-3401.140" - cell $or $or$ls180.v:3401$160 + attribute \src "ls180.v:3506.59-3506.140" + cell $or $or$ls180.v:3506$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258336,10 +276205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_req_wdata_ready connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3401$160_Y + connect \Y $or$ls180.v:3506$257_Y end - attribute \src "ls180.v:3402.44-3402.151" - cell $or $or$ls180.v:3402$161 + attribute \src "ls180.v:3507.44-3507.151" + cell $or $or$ls180.v:3507$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258347,21 +276216,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3402$161_Y + connect \Y $or$ls180.v:3507$258_Y end - attribute \src "ls180.v:3410.45-3410.170" - cell $or $or$ls180.v:3410$165 + attribute \src "ls180.v:3515.45-3515.170" + cell $or $or$ls180.v:3515$262 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3410$164_Y + connect \A $sshl$ls180.v:3515$261_Y connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3410$165_Y + connect \Y $or$ls180.v:3515$262_Y end - attribute \src "ls180.v:3447.127-3447.245" - cell $or $or$ls180.v:3447$178 + attribute \src "ls180.v:3552.127-3552.245" + cell $or $or$ls180.v:3552$275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258369,21 +276238,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3447$178_Y + connect \Y $or$ls180.v:3552$275_Y end - attribute \src "ls180.v:3453.57-3453.157" - cell $or $or$ls180.v:3453$184 + attribute \src "ls180.v:3558.57-3558.157" + cell $or $or$ls180.v:3558$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3453$183_Y + connect \A $not$ls180.v:3558$280_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3453$184_Y + connect \Y $or$ls180.v:3558$281_Y end - attribute \src "ls180.v:3558.59-3558.140" - cell $or $or$ls180.v:3558$190 + attribute \src "ls180.v:3663.59-3663.140" + cell $or $or$ls180.v:3663$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258391,10 +276260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_req_wdata_ready connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3558$190_Y + connect \Y $or$ls180.v:3663$287_Y end - attribute \src "ls180.v:3559.44-3559.151" - cell $or $or$ls180.v:3559$191 + attribute \src "ls180.v:3664.44-3664.151" + cell $or $or$ls180.v:3664$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258402,21 +276271,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3559$191_Y + connect \Y $or$ls180.v:3664$288_Y end - attribute \src "ls180.v:3567.45-3567.170" - cell $or $or$ls180.v:3567$195 + attribute \src "ls180.v:3672.45-3672.170" + cell $or $or$ls180.v:3672$292 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3567$194_Y + connect \A $sshl$ls180.v:3672$291_Y connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3567$195_Y + connect \Y $or$ls180.v:3672$292_Y end - attribute \src "ls180.v:3604.127-3604.245" - cell $or $or$ls180.v:3604$208 + attribute \src "ls180.v:3709.127-3709.245" + cell $or $or$ls180.v:3709$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258424,21 +276293,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3604$208_Y + connect \Y $or$ls180.v:3709$305_Y end - attribute \src "ls180.v:3610.57-3610.157" - cell $or $or$ls180.v:3610$214 + attribute \src "ls180.v:3715.57-3715.157" + cell $or $or$ls180.v:3715$311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3610$213_Y + connect \A $not$ls180.v:3715$310_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3610$214_Y + connect \Y $or$ls180.v:3715$311_Y end - attribute \src "ls180.v:3715.59-3715.140" - cell $or $or$ls180.v:3715$220 + attribute \src "ls180.v:3820.59-3820.140" + cell $or $or$ls180.v:3820$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258446,10 +276315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_req_wdata_ready connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3715$220_Y + connect \Y $or$ls180.v:3820$317_Y end - attribute \src "ls180.v:3716.44-3716.151" - cell $or $or$ls180.v:3716$221 + attribute \src "ls180.v:3821.44-3821.151" + cell $or $or$ls180.v:3821$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258457,21 +276326,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3716$221_Y + connect \Y $or$ls180.v:3821$318_Y end - attribute \src "ls180.v:3724.45-3724.170" - cell $or $or$ls180.v:3724$225 + attribute \src "ls180.v:3829.45-3829.170" + cell $or $or$ls180.v:3829$322 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3724$224_Y + connect \A $sshl$ls180.v:3829$321_Y connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3724$225_Y + connect \Y $or$ls180.v:3829$322_Y end - attribute \src "ls180.v:3761.127-3761.245" - cell $or $or$ls180.v:3761$238 + attribute \src "ls180.v:3866.127-3866.245" + cell $or $or$ls180.v:3866$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258479,21 +276348,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3761$238_Y + connect \Y $or$ls180.v:3866$335_Y end - attribute \src "ls180.v:3767.57-3767.157" - cell $or $or$ls180.v:3767$244 + attribute \src "ls180.v:3872.57-3872.157" + cell $or $or$ls180.v:3872$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3767$243_Y + connect \A $not$ls180.v:3872$340_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3767$244_Y + connect \Y $or$ls180.v:3872$341_Y end - attribute \src "ls180.v:3866.107-3866.193" - cell $or $or$ls180.v:3866$264 + attribute \src "ls180.v:3971.107-3971.193" + cell $or $or$ls180.v:3971$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258501,626 +276370,626 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_is_write connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3866$264_Y + connect \Y $or$ls180.v:3971$361_Y end - attribute \src "ls180.v:3869.39-3869.204" - cell $or $or$ls180.v:3869$270 + attribute \src "ls180.v:3974.39-3974.204" + cell $or $or$ls180.v:3974$367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3869$268_Y - connect \B $and$ls180.v:3869$269_Y - connect \Y $or$ls180.v:3869$270_Y + connect \A $and$ls180.v:3974$365_Y + connect \B $and$ls180.v:3974$366_Y + connect \Y $or$ls180.v:3974$367_Y end - attribute \src "ls180.v:3869.38-3869.289" - cell $or $or$ls180.v:3869$272 + attribute \src "ls180.v:3974.38-3974.289" + cell $or $or$ls180.v:3974$369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3869$270_Y - connect \B $and$ls180.v:3869$271_Y - connect \Y $or$ls180.v:3869$272_Y + connect \A $or$ls180.v:3974$367_Y + connect \B $and$ls180.v:3974$368_Y + connect \Y $or$ls180.v:3974$369_Y end - attribute \src "ls180.v:3869.37-3869.374" - cell $or $or$ls180.v:3869$274 + attribute \src "ls180.v:3974.37-3974.374" + cell $or $or$ls180.v:3974$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3869$272_Y - connect \B $and$ls180.v:3869$273_Y - connect \Y $or$ls180.v:3869$274_Y + connect \A $or$ls180.v:3974$369_Y + connect \B $and$ls180.v:3974$370_Y + connect \Y $or$ls180.v:3974$371_Y end - attribute \src "ls180.v:3870.40-3870.207" - cell $or $or$ls180.v:3870$277 + attribute \src "ls180.v:3975.40-3975.207" + cell $or $or$ls180.v:3975$374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3870$275_Y - connect \B $and$ls180.v:3870$276_Y - connect \Y $or$ls180.v:3870$277_Y + connect \A $and$ls180.v:3975$372_Y + connect \B $and$ls180.v:3975$373_Y + connect \Y $or$ls180.v:3975$374_Y end - attribute \src "ls180.v:3870.39-3870.293" - cell $or $or$ls180.v:3870$279 + attribute \src "ls180.v:3975.39-3975.293" + cell $or $or$ls180.v:3975$376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3870$277_Y - connect \B $and$ls180.v:3870$278_Y - connect \Y $or$ls180.v:3870$279_Y + connect \A $or$ls180.v:3975$374_Y + connect \B $and$ls180.v:3975$375_Y + connect \Y $or$ls180.v:3975$376_Y end - attribute \src "ls180.v:3870.38-3870.379" - cell $or $or$ls180.v:3870$281 + attribute \src "ls180.v:3975.38-3975.379" + cell $or $or$ls180.v:3975$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3870$279_Y - connect \B $and$ls180.v:3870$280_Y - connect \Y $or$ls180.v:3870$281_Y + connect \A $or$ls180.v:3975$376_Y + connect \B $and$ls180.v:3975$377_Y + connect \Y $or$ls180.v:3975$378_Y end - attribute \src "ls180.v:3883.158-3883.332" - cell $or $or$ls180.v:3883$295 + attribute \src "ls180.v:3988.158-3988.332" + cell $or $or$ls180.v:3988$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3883$294_Y + connect \A $not$ls180.v:3988$391_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3883$295_Y + connect \Y $or$ls180.v:3988$392_Y end - attribute \src "ls180.v:3883.75-3883.506" - cell $or $or$ls180.v:3883$300 + attribute \src "ls180.v:3988.75-3988.506" + cell $or $or$ls180.v:3988$397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$296_Y - connect \B $and$ls180.v:3883$299_Y - connect \Y $or$ls180.v:3883$300_Y + connect \A $and$ls180.v:3988$393_Y + connect \B $and$ls180.v:3988$396_Y + connect \Y $or$ls180.v:3988$397_Y end - attribute \src "ls180.v:3884.158-3884.332" - cell $or $or$ls180.v:3884$308 + attribute \src "ls180.v:3989.158-3989.332" + cell $or $or$ls180.v:3989$405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3884$307_Y + connect \A $not$ls180.v:3989$404_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3884$308_Y + connect \Y $or$ls180.v:3989$405_Y end - attribute \src "ls180.v:3884.75-3884.506" - cell $or $or$ls180.v:3884$313 + attribute \src "ls180.v:3989.75-3989.506" + cell $or $or$ls180.v:3989$410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$309_Y - connect \B $and$ls180.v:3884$312_Y - connect \Y $or$ls180.v:3884$313_Y + connect \A $and$ls180.v:3989$406_Y + connect \B $and$ls180.v:3989$409_Y + connect \Y $or$ls180.v:3989$410_Y end - attribute \src "ls180.v:3885.158-3885.332" - cell $or $or$ls180.v:3885$321 + attribute \src "ls180.v:3990.158-3990.332" + cell $or $or$ls180.v:3990$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3885$320_Y + connect \A $not$ls180.v:3990$417_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3885$321_Y + connect \Y $or$ls180.v:3990$418_Y end - attribute \src "ls180.v:3885.75-3885.506" - cell $or $or$ls180.v:3885$326 + attribute \src "ls180.v:3990.75-3990.506" + cell $or $or$ls180.v:3990$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$322_Y - connect \B $and$ls180.v:3885$325_Y - connect \Y $or$ls180.v:3885$326_Y + connect \A $and$ls180.v:3990$419_Y + connect \B $and$ls180.v:3990$422_Y + connect \Y $or$ls180.v:3990$423_Y end - attribute \src "ls180.v:3886.158-3886.332" - cell $or $or$ls180.v:3886$334 + attribute \src "ls180.v:3991.158-3991.332" + cell $or $or$ls180.v:3991$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3886$333_Y + connect \A $not$ls180.v:3991$430_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3886$334_Y + connect \Y $or$ls180.v:3991$431_Y end - attribute \src "ls180.v:3886.75-3886.506" - cell $or $or$ls180.v:3886$339 + attribute \src "ls180.v:3991.75-3991.506" + cell $or $or$ls180.v:3991$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$335_Y - connect \B $and$ls180.v:3886$338_Y - connect \Y $or$ls180.v:3886$339_Y + connect \A $and$ls180.v:3991$432_Y + connect \B $and$ls180.v:3991$435_Y + connect \Y $or$ls180.v:3991$436_Y end - attribute \src "ls180.v:3913.36-3913.104" - cell $or $or$ls180.v:3913$345 + attribute \src "ls180.v:4018.36-4018.104" + cell $or $or$ls180.v:4018$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3913$344_Y - connect \Y $or$ls180.v:3913$345_Y + connect \B $not$ls180.v:4018$441_Y + connect \Y $or$ls180.v:4018$442_Y end - attribute \src "ls180.v:3916.158-3916.332" - cell $or $or$ls180.v:3916$353 + attribute \src "ls180.v:4021.158-4021.332" + cell $or $or$ls180.v:4021$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3916$352_Y + connect \A $not$ls180.v:4021$449_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3916$353_Y + connect \Y $or$ls180.v:4021$450_Y end - attribute \src "ls180.v:3916.75-3916.506" - cell $or $or$ls180.v:3916$358 + attribute \src "ls180.v:4021.75-4021.506" + cell $or $or$ls180.v:4021$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3916$354_Y - connect \B $and$ls180.v:3916$357_Y - connect \Y $or$ls180.v:3916$358_Y + connect \A $and$ls180.v:4021$451_Y + connect \B $and$ls180.v:4021$454_Y + connect \Y $or$ls180.v:4021$455_Y end - attribute \src "ls180.v:3917.158-3917.332" - cell $or $or$ls180.v:3917$366 + attribute \src "ls180.v:4022.158-4022.332" + cell $or $or$ls180.v:4022$463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3917$365_Y + connect \A $not$ls180.v:4022$462_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3917$366_Y + connect \Y $or$ls180.v:4022$463_Y end - attribute \src "ls180.v:3917.75-3917.506" - cell $or $or$ls180.v:3917$371 + attribute \src "ls180.v:4022.75-4022.506" + cell $or $or$ls180.v:4022$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3917$367_Y - connect \B $and$ls180.v:3917$370_Y - connect \Y $or$ls180.v:3917$371_Y + connect \A $and$ls180.v:4022$464_Y + connect \B $and$ls180.v:4022$467_Y + connect \Y $or$ls180.v:4022$468_Y end - attribute \src "ls180.v:3918.158-3918.332" - cell $or $or$ls180.v:3918$379 + attribute \src "ls180.v:4023.158-4023.332" + cell $or $or$ls180.v:4023$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3918$378_Y + connect \A $not$ls180.v:4023$475_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3918$379_Y + connect \Y $or$ls180.v:4023$476_Y end - attribute \src "ls180.v:3918.75-3918.506" - cell $or $or$ls180.v:3918$384 + attribute \src "ls180.v:4023.75-4023.506" + cell $or $or$ls180.v:4023$481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3918$380_Y - connect \B $and$ls180.v:3918$383_Y - connect \Y $or$ls180.v:3918$384_Y + connect \A $and$ls180.v:4023$477_Y + connect \B $and$ls180.v:4023$480_Y + connect \Y $or$ls180.v:4023$481_Y end - attribute \src "ls180.v:3919.158-3919.332" - cell $or $or$ls180.v:3919$392 + attribute \src "ls180.v:4024.158-4024.332" + cell $or $or$ls180.v:4024$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3919$391_Y + connect \A $not$ls180.v:4024$488_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3919$392_Y + connect \Y $or$ls180.v:4024$489_Y end - attribute \src "ls180.v:3919.75-3919.506" - cell $or $or$ls180.v:3919$397 + attribute \src "ls180.v:4024.75-4024.506" + cell $or $or$ls180.v:4024$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$393_Y - connect \B $and$ls180.v:3919$396_Y - connect \Y $or$ls180.v:3919$397_Y + connect \A $and$ls180.v:4024$490_Y + connect \B $and$ls180.v:4024$493_Y + connect \Y $or$ls180.v:4024$494_Y end - attribute \src "ls180.v:3982.36-3982.104" - cell $or $or$ls180.v:3982$431 + attribute \src "ls180.v:4087.36-4087.104" + cell $or $or$ls180.v:4087$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3982$430_Y - connect \Y $or$ls180.v:3982$431_Y + connect \B $not$ls180.v:4087$527_Y + connect \Y $or$ls180.v:4087$528_Y end - attribute \src "ls180.v:4003.67-4003.221" - cell $or $or$ls180.v:4003$438 + attribute \src "ls180.v:4108.67-4108.221" + cell $or $or$ls180.v:4108$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4003$437_Y + connect \A $not$ls180.v:4108$534_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4003$438_Y + connect \Y $or$ls180.v:4108$535_Y end - attribute \src "ls180.v:4011.10-4011.62" - cell $or $or$ls180.v:4011$441 + attribute \src "ls180.v:4116.10-4116.62" + cell $or $or$ls180.v:4116$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4011$440_Y + connect \A $not$ls180.v:4116$537_Y connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:4011$441_Y + connect \Y $or$ls180.v:4116$538_Y end - attribute \src "ls180.v:4041.67-4041.221" - cell $or $or$ls180.v:4041$447 + attribute \src "ls180.v:4146.67-4146.221" + cell $or $or$ls180.v:4146$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4041$446_Y + connect \A $not$ls180.v:4146$543_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4041$447_Y + connect \Y $or$ls180.v:4146$544_Y end - attribute \src "ls180.v:4049.10-4049.61" - cell $or $or$ls180.v:4049$450 + attribute \src "ls180.v:4154.10-4154.61" + cell $or $or$ls180.v:4154$547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4049$449_Y + connect \A $not$ls180.v:4154$546_Y connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:4049$450_Y + connect \Y $or$ls180.v:4154$547_Y end - attribute \src "ls180.v:4059.91-4059.180" - cell $or $or$ls180.v:4059$454 + attribute \src "ls180.v:4164.91-4164.180" + cell $or $or$ls180.v:4164$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4059$453_Y - connect \Y $or$ls180.v:4059$454_Y + connect \B $and$ls180.v:4164$550_Y + connect \Y $or$ls180.v:4164$551_Y end - attribute \src "ls180.v:4059.90-4059.255" - cell $or $or$ls180.v:4059$457 + attribute \src "ls180.v:4164.90-4164.255" + cell $or $or$ls180.v:4164$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4059$454_Y - connect \B $and$ls180.v:4059$456_Y - connect \Y $or$ls180.v:4059$457_Y + connect \A $or$ls180.v:4164$551_Y + connect \B $and$ls180.v:4164$553_Y + connect \Y $or$ls180.v:4164$554_Y end - attribute \src "ls180.v:4059.89-4059.330" - cell $or $or$ls180.v:4059$460 + attribute \src "ls180.v:4164.89-4164.330" + cell $or $or$ls180.v:4164$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4059$457_Y - connect \B $and$ls180.v:4059$459_Y - connect \Y $or$ls180.v:4059$460_Y + connect \A $or$ls180.v:4164$554_Y + connect \B $and$ls180.v:4164$556_Y + connect \Y $or$ls180.v:4164$557_Y end - attribute \src "ls180.v:4064.91-4064.180" - cell $or $or$ls180.v:4064$470 + attribute \src "ls180.v:4169.91-4169.180" + cell $or $or$ls180.v:4169$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4064$469_Y - connect \Y $or$ls180.v:4064$470_Y + connect \B $and$ls180.v:4169$566_Y + connect \Y $or$ls180.v:4169$567_Y end - attribute \src "ls180.v:4064.90-4064.255" - cell $or $or$ls180.v:4064$473 + attribute \src "ls180.v:4169.90-4169.255" + cell $or $or$ls180.v:4169$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4064$470_Y - connect \B $and$ls180.v:4064$472_Y - connect \Y $or$ls180.v:4064$473_Y + connect \A $or$ls180.v:4169$567_Y + connect \B $and$ls180.v:4169$569_Y + connect \Y $or$ls180.v:4169$570_Y end - attribute \src "ls180.v:4064.89-4064.330" - cell $or $or$ls180.v:4064$476 + attribute \src "ls180.v:4169.89-4169.330" + cell $or $or$ls180.v:4169$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4064$473_Y - connect \B $and$ls180.v:4064$475_Y - connect \Y $or$ls180.v:4064$476_Y + connect \A $or$ls180.v:4169$570_Y + connect \B $and$ls180.v:4169$572_Y + connect \Y $or$ls180.v:4169$573_Y end - attribute \src "ls180.v:4069.91-4069.180" - cell $or $or$ls180.v:4069$486 + attribute \src "ls180.v:4174.91-4174.180" + cell $or $or$ls180.v:4174$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4069$485_Y - connect \Y $or$ls180.v:4069$486_Y + connect \B $and$ls180.v:4174$582_Y + connect \Y $or$ls180.v:4174$583_Y end - attribute \src "ls180.v:4069.90-4069.255" - cell $or $or$ls180.v:4069$489 + attribute \src "ls180.v:4174.90-4174.255" + cell $or $or$ls180.v:4174$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4069$486_Y - connect \B $and$ls180.v:4069$488_Y - connect \Y $or$ls180.v:4069$489_Y + connect \A $or$ls180.v:4174$583_Y + connect \B $and$ls180.v:4174$585_Y + connect \Y $or$ls180.v:4174$586_Y end - attribute \src "ls180.v:4069.89-4069.330" - cell $or $or$ls180.v:4069$492 + attribute \src "ls180.v:4174.89-4174.330" + cell $or $or$ls180.v:4174$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4069$489_Y - connect \B $and$ls180.v:4069$491_Y - connect \Y $or$ls180.v:4069$492_Y + connect \A $or$ls180.v:4174$586_Y + connect \B $and$ls180.v:4174$588_Y + connect \Y $or$ls180.v:4174$589_Y end - attribute \src "ls180.v:4074.91-4074.180" - cell $or $or$ls180.v:4074$502 + attribute \src "ls180.v:4179.91-4179.180" + cell $or $or$ls180.v:4179$599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4074$501_Y - connect \Y $or$ls180.v:4074$502_Y + connect \B $and$ls180.v:4179$598_Y + connect \Y $or$ls180.v:4179$599_Y end - attribute \src "ls180.v:4074.90-4074.255" - cell $or $or$ls180.v:4074$505 + attribute \src "ls180.v:4179.90-4179.255" + cell $or $or$ls180.v:4179$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4074$502_Y - connect \B $and$ls180.v:4074$504_Y - connect \Y $or$ls180.v:4074$505_Y + connect \A $or$ls180.v:4179$599_Y + connect \B $and$ls180.v:4179$601_Y + connect \Y $or$ls180.v:4179$602_Y end - attribute \src "ls180.v:4074.89-4074.330" - cell $or $or$ls180.v:4074$508 + attribute \src "ls180.v:4179.89-4179.330" + cell $or $or$ls180.v:4179$605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4074$505_Y - connect \B $and$ls180.v:4074$507_Y - connect \Y $or$ls180.v:4074$508_Y + connect \A $or$ls180.v:4179$602_Y + connect \B $and$ls180.v:4179$604_Y + connect \Y $or$ls180.v:4179$605_Y end - attribute \src "ls180.v:4079.132-4079.221" - cell $or $or$ls180.v:4079$519 + attribute \src "ls180.v:4184.132-4184.221" + cell $or $or$ls180.v:4184$616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4079$518_Y - connect \Y $or$ls180.v:4079$519_Y + connect \B $and$ls180.v:4184$615_Y + connect \Y $or$ls180.v:4184$616_Y end - attribute \src "ls180.v:4079.131-4079.296" - cell $or $or$ls180.v:4079$522 + attribute \src "ls180.v:4184.131-4184.296" + cell $or $or$ls180.v:4184$619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$519_Y - connect \B $and$ls180.v:4079$521_Y - connect \Y $or$ls180.v:4079$522_Y + connect \A $or$ls180.v:4184$616_Y + connect \B $and$ls180.v:4184$618_Y + connect \Y $or$ls180.v:4184$619_Y end - attribute \src "ls180.v:4079.130-4079.371" - cell $or $or$ls180.v:4079$525 + attribute \src "ls180.v:4184.130-4184.371" + cell $or $or$ls180.v:4184$622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$522_Y - connect \B $and$ls180.v:4079$524_Y - connect \Y $or$ls180.v:4079$525_Y + connect \A $or$ls180.v:4184$619_Y + connect \B $and$ls180.v:4184$621_Y + connect \Y $or$ls180.v:4184$622_Y end - attribute \src "ls180.v:4079.34-4079.411" - cell $or $or$ls180.v:4079$530 + attribute \src "ls180.v:4184.34-4184.411" + cell $or $or$ls180.v:4184$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:4079$529_Y - connect \Y $or$ls180.v:4079$530_Y + connect \B $and$ls180.v:4184$626_Y + connect \Y $or$ls180.v:4184$627_Y end - attribute \src "ls180.v:4079.506-4079.595" - cell $or $or$ls180.v:4079$535 + attribute \src "ls180.v:4184.506-4184.595" + cell $or $or$ls180.v:4184$632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4079$534_Y - connect \Y $or$ls180.v:4079$535_Y + connect \B $and$ls180.v:4184$631_Y + connect \Y $or$ls180.v:4184$632_Y end - attribute \src "ls180.v:4079.505-4079.670" - cell $or $or$ls180.v:4079$538 + attribute \src "ls180.v:4184.505-4184.670" + cell $or $or$ls180.v:4184$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$535_Y - connect \B $and$ls180.v:4079$537_Y - connect \Y $or$ls180.v:4079$538_Y + connect \A $or$ls180.v:4184$632_Y + connect \B $and$ls180.v:4184$634_Y + connect \Y $or$ls180.v:4184$635_Y end - attribute \src "ls180.v:4079.504-4079.745" - cell $or $or$ls180.v:4079$541 + attribute \src "ls180.v:4184.504-4184.745" + cell $or $or$ls180.v:4184$638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$538_Y - connect \B $and$ls180.v:4079$540_Y - connect \Y $or$ls180.v:4079$541_Y + connect \A $or$ls180.v:4184$635_Y + connect \B $and$ls180.v:4184$637_Y + connect \Y $or$ls180.v:4184$638_Y end - attribute \src "ls180.v:4079.33-4079.785" - cell $or $or$ls180.v:4079$546 + attribute \src "ls180.v:4184.33-4184.785" + cell $or $or$ls180.v:4184$643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$530_Y - connect \B $and$ls180.v:4079$545_Y - connect \Y $or$ls180.v:4079$546_Y + connect \A $or$ls180.v:4184$627_Y + connect \B $and$ls180.v:4184$642_Y + connect \Y $or$ls180.v:4184$643_Y end - attribute \src "ls180.v:4079.880-4079.969" - cell $or $or$ls180.v:4079$551 + attribute \src "ls180.v:4184.880-4184.969" + cell $or $or$ls180.v:4184$648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4079$550_Y - connect \Y $or$ls180.v:4079$551_Y + connect \B $and$ls180.v:4184$647_Y + connect \Y $or$ls180.v:4184$648_Y end - attribute \src "ls180.v:4079.879-4079.1044" - cell $or $or$ls180.v:4079$554 + attribute \src "ls180.v:4184.879-4184.1044" + cell $or $or$ls180.v:4184$651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$551_Y - connect \B $and$ls180.v:4079$553_Y - connect \Y $or$ls180.v:4079$554_Y + connect \A $or$ls180.v:4184$648_Y + connect \B $and$ls180.v:4184$650_Y + connect \Y $or$ls180.v:4184$651_Y end - attribute \src "ls180.v:4079.878-4079.1119" - cell $or $or$ls180.v:4079$557 + attribute \src "ls180.v:4184.878-4184.1119" + cell $or $or$ls180.v:4184$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$554_Y - connect \B $and$ls180.v:4079$556_Y - connect \Y $or$ls180.v:4079$557_Y + connect \A $or$ls180.v:4184$651_Y + connect \B $and$ls180.v:4184$653_Y + connect \Y $or$ls180.v:4184$654_Y end - attribute \src "ls180.v:4079.32-4079.1159" - cell $or $or$ls180.v:4079$562 + attribute \src "ls180.v:4184.32-4184.1159" + cell $or $or$ls180.v:4184$659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$546_Y - connect \B $and$ls180.v:4079$561_Y - connect \Y $or$ls180.v:4079$562_Y + connect \A $or$ls180.v:4184$643_Y + connect \B $and$ls180.v:4184$658_Y + connect \Y $or$ls180.v:4184$659_Y end - attribute \src "ls180.v:4079.1254-4079.1343" - cell $or $or$ls180.v:4079$567 + attribute \src "ls180.v:4184.1254-4184.1343" + cell $or $or$ls180.v:4184$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4079$566_Y - connect \Y $or$ls180.v:4079$567_Y + connect \B $and$ls180.v:4184$663_Y + connect \Y $or$ls180.v:4184$664_Y end - attribute \src "ls180.v:4079.1253-4079.1418" - cell $or $or$ls180.v:4079$570 + attribute \src "ls180.v:4184.1253-4184.1418" + cell $or $or$ls180.v:4184$667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$567_Y - connect \B $and$ls180.v:4079$569_Y - connect \Y $or$ls180.v:4079$570_Y + connect \A $or$ls180.v:4184$664_Y + connect \B $and$ls180.v:4184$666_Y + connect \Y $or$ls180.v:4184$667_Y end - attribute \src "ls180.v:4079.1252-4079.1493" - cell $or $or$ls180.v:4079$573 + attribute \src "ls180.v:4184.1252-4184.1493" + cell $or $or$ls180.v:4184$670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$570_Y - connect \B $and$ls180.v:4079$572_Y - connect \Y $or$ls180.v:4079$573_Y + connect \A $or$ls180.v:4184$667_Y + connect \B $and$ls180.v:4184$669_Y + connect \Y $or$ls180.v:4184$670_Y end - attribute \src "ls180.v:4079.31-4079.1533" - cell $or $or$ls180.v:4079$578 + attribute \src "ls180.v:4184.31-4184.1533" + cell $or $or$ls180.v:4184$675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$562_Y - connect \B $and$ls180.v:4079$577_Y - connect \Y $or$ls180.v:4079$578_Y + connect \A $or$ls180.v:4184$659_Y + connect \B $and$ls180.v:4184$674_Y + connect \Y $or$ls180.v:4184$675_Y end - attribute \src "ls180.v:4142.10-4142.52" - cell $or $or$ls180.v:4142$587 + attribute \src "ls180.v:4247.10-4247.52" + cell $or $or$ls180.v:4247$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259128,10 +276997,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:4142$587_Y + connect \Y $or$ls180.v:4247$684_Y end - attribute \src "ls180.v:4169.35-4169.74" - cell $or $or$ls180.v:4169$597 + attribute \src "ls180.v:4274.35-4274.74" + cell $or $or$ls180.v:4274$694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259139,10 +277008,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4169$597_Y + connect \Y $or$ls180.v:4274$694_Y end - attribute \src "ls180.v:4170.34-4170.73" - cell $or $or$ls180.v:4170$601 + attribute \src "ls180.v:4275.34-4275.73" + cell $or $or$ls180.v:4275$698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259150,76 +277019,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4170$601_Y + connect \Y $or$ls180.v:4275$698_Y end - attribute \src "ls180.v:4171.48-4171.130" - cell $or $or$ls180.v:4171$607 + attribute \src "ls180.v:4276.48-4276.130" + cell $or $or$ls180.v:4276$704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4171$604_Y - connect \B $and$ls180.v:4171$606_Y - connect \Y $or$ls180.v:4171$607_Y + connect \A $and$ls180.v:4276$701_Y + connect \B $and$ls180.v:4276$703_Y + connect \Y $or$ls180.v:4276$704_Y end - attribute \src "ls180.v:4172.24-4172.87" - cell $or $or$ls180.v:4172$610 + attribute \src "ls180.v:4277.24-4277.87" + cell $or $or$ls180.v:4277$707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4172$609_Y + connect \A $and$ls180.v:4277$706_Y connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4172$610_Y + connect \Y $or$ls180.v:4277$707_Y end - attribute \src "ls180.v:4173.26-4173.95" - cell $or $or$ls180.v:4173$612 + attribute \src "ls180.v:4278.26-4278.95" + cell $or $or$ls180.v:4278$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4173$611_Y + connect \A $and$ls180.v:4278$708_Y connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4173$612_Y + connect \Y $or$ls180.v:4278$709_Y end - attribute \src "ls180.v:4203.42-4203.89" - cell $or $or$ls180.v:4203$620 + attribute \src "ls180.v:4308.42-4308.89" + cell $or $or$ls180.v:4308$717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4203$619_Y - connect \Y $or$ls180.v:4203$620_Y + connect \B $and$ls180.v:4308$716_Y + connect \Y $or$ls180.v:4308$717_Y end - attribute \src "ls180.v:4227.25-4227.174" - cell $or $or$ls180.v:4227$630 + attribute \src "ls180.v:4332.25-4332.174" + cell $or $or$ls180.v:4332$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4227$628_Y - connect \B $and$ls180.v:4227$629_Y - connect \Y $or$ls180.v:4227$630_Y + connect \A $and$ls180.v:4332$725_Y + connect \B $and$ls180.v:4332$726_Y + connect \Y $or$ls180.v:4332$727_Y end - attribute \src "ls180.v:4242.80-4242.132" - cell $or $or$ls180.v:4242$632 + attribute \src "ls180.v:4347.80-4347.132" + cell $or $or$ls180.v:4347$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4242$631_Y + connect \A $not$ls180.v:4347$728_Y connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4242$632_Y + connect \Y $or$ls180.v:4347$729_Y end - attribute \src "ls180.v:4253.72-4253.135" - cell $or $or$ls180.v:4253$637 + attribute \src "ls180.v:4358.72-4358.135" + cell $or $or$ls180.v:4358$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259227,21 +277096,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_writable connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4253$637_Y + connect \Y $or$ls180.v:4358$734_Y end - attribute \src "ls180.v:4272.80-4272.132" - cell $or $or$ls180.v:4272$643 + attribute \src "ls180.v:4377.80-4377.132" + cell $or $or$ls180.v:4377$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4272$642_Y + connect \A $not$ls180.v:4377$739_Y connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4272$643_Y + connect \Y $or$ls180.v:4377$740_Y end - attribute \src "ls180.v:4283.72-4283.135" - cell $or $or$ls180.v:4283$648 + attribute \src "ls180.v:4388.72-4388.135" + cell $or $or$ls180.v:4388$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259249,10 +277118,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_writable connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4283$648_Y + connect \Y $or$ls180.v:4388$745_Y end - attribute \src "ls180.v:4417.36-4417.111" - cell $or $or$ls180.v:4417$669 + attribute \src "ls180.v:4533.36-4533.111" + cell $or $or$ls180.v:4533$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259260,43 +277129,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_clk connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4417$669_Y + connect \Y $or$ls180.v:4533$768_Y end - attribute \src "ls180.v:4417.35-4417.151" - cell $or $or$ls180.v:4417$670 + attribute \src "ls180.v:4533.35-4533.151" + cell $or $or$ls180.v:4533$769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4417$669_Y + connect \A $or$ls180.v:4533$768_Y connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4417$670_Y + connect \Y $or$ls180.v:4533$769_Y end - attribute \src "ls180.v:4417.34-4417.192" - cell $or $or$ls180.v:4417$671 + attribute \src "ls180.v:4533.34-4533.192" + cell $or $or$ls180.v:4533$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4417$670_Y + connect \A $or$ls180.v:4533$769_Y connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4417$671_Y + connect \Y $or$ls180.v:4533$770_Y end - attribute \src "ls180.v:4417.33-4417.233" - cell $or $or$ls180.v:4417$672 + attribute \src "ls180.v:4533.33-4533.233" + cell $or $or$ls180.v:4533$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4417$671_Y + connect \A $or$ls180.v:4533$770_Y connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4417$672_Y + connect \Y $or$ls180.v:4533$771_Y end - attribute \src "ls180.v:4418.39-4418.120" - cell $or $or$ls180.v:4418$673 + attribute \src "ls180.v:4534.39-4534.120" + cell $or $or$ls180.v:4534$772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259304,43 +277173,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_oe connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4418$673_Y + connect \Y $or$ls180.v:4534$772_Y end - attribute \src "ls180.v:4418.38-4418.163" - cell $or $or$ls180.v:4418$674 + attribute \src "ls180.v:4534.38-4534.163" + cell $or $or$ls180.v:4534$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4418$673_Y + connect \A $or$ls180.v:4534$772_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4418$674_Y + connect \Y $or$ls180.v:4534$773_Y end - attribute \src "ls180.v:4418.37-4418.207" - cell $or $or$ls180.v:4418$675 + attribute \src "ls180.v:4534.37-4534.207" + cell $or $or$ls180.v:4534$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4418$674_Y + connect \A $or$ls180.v:4534$773_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4418$675_Y + connect \Y $or$ls180.v:4534$774_Y end - attribute \src "ls180.v:4418.36-4418.251" - cell $or $or$ls180.v:4418$676 + attribute \src "ls180.v:4534.36-4534.251" + cell $or $or$ls180.v:4534$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4418$675_Y + connect \A $or$ls180.v:4534$774_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4418$676_Y + connect \Y $or$ls180.v:4534$775_Y end - attribute \src "ls180.v:4419.38-4419.117" - cell $or $or$ls180.v:4419$677 + attribute \src "ls180.v:4535.38-4535.117" + cell $or $or$ls180.v:4535$776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259348,43 +277217,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_o connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4419$677_Y + connect \Y $or$ls180.v:4535$776_Y end - attribute \src "ls180.v:4419.37-4419.159" - cell $or $or$ls180.v:4419$678 + attribute \src "ls180.v:4535.37-4535.159" + cell $or $or$ls180.v:4535$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4419$677_Y + connect \A $or$ls180.v:4535$776_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4419$678_Y + connect \Y $or$ls180.v:4535$777_Y end - attribute \src "ls180.v:4419.36-4419.202" - cell $or $or$ls180.v:4419$679 + attribute \src "ls180.v:4535.36-4535.202" + cell $or $or$ls180.v:4535$778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4419$678_Y + connect \A $or$ls180.v:4535$777_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4419$679_Y + connect \Y $or$ls180.v:4535$778_Y end - attribute \src "ls180.v:4419.35-4419.245" - cell $or $or$ls180.v:4419$680 + attribute \src "ls180.v:4535.35-4535.245" + cell $or $or$ls180.v:4535$779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4419$679_Y + connect \A $or$ls180.v:4535$778_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4419$680_Y + connect \Y $or$ls180.v:4535$779_Y end - attribute \src "ls180.v:4420.40-4420.123" - cell $or $or$ls180.v:4420$681 + attribute \src "ls180.v:4536.40-4536.123" + cell $or $or$ls180.v:4536$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259392,43 +277261,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_data_oe connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4420$681_Y + connect \Y $or$ls180.v:4536$780_Y end - attribute \src "ls180.v:4420.39-4420.167" - cell $or $or$ls180.v:4420$682 + attribute \src "ls180.v:4536.39-4536.167" + cell $or $or$ls180.v:4536$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4420$681_Y + connect \A $or$ls180.v:4536$780_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4420$682_Y + connect \Y $or$ls180.v:4536$781_Y end - attribute \src "ls180.v:4420.38-4420.212" - cell $or $or$ls180.v:4420$683 + attribute \src "ls180.v:4536.38-4536.212" + cell $or $or$ls180.v:4536$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4420$682_Y + connect \A $or$ls180.v:4536$781_Y connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4420$683_Y + connect \Y $or$ls180.v:4536$782_Y end - attribute \src "ls180.v:4420.37-4420.257" - cell $or $or$ls180.v:4420$684 + attribute \src "ls180.v:4536.37-4536.257" + cell $or $or$ls180.v:4536$783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4420$683_Y + connect \A $or$ls180.v:4536$782_Y connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4420$684_Y + connect \Y $or$ls180.v:4536$783_Y end - attribute \src "ls180.v:4421.39-4421.120" - cell $or $or$ls180.v:4421$685 + attribute \src "ls180.v:4537.39-4537.120" + cell $or $or$ls180.v:4537$784 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259436,43 +277305,43 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_init_pads_out_payload_data_o connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4421$685_Y + connect \Y $or$ls180.v:4537$784_Y end - attribute \src "ls180.v:4421.38-4421.163" - cell $or $or$ls180.v:4421$686 + attribute \src "ls180.v:4537.38-4537.163" + cell $or $or$ls180.v:4537$785 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4421$685_Y + connect \A $or$ls180.v:4537$784_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4421$686_Y + connect \Y $or$ls180.v:4537$785_Y end - attribute \src "ls180.v:4421.37-4421.207" - cell $or $or$ls180.v:4421$687 + attribute \src "ls180.v:4537.37-4537.207" + cell $or $or$ls180.v:4537$786 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4421$686_Y + connect \A $or$ls180.v:4537$785_Y connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4421$687_Y + connect \Y $or$ls180.v:4537$786_Y end - attribute \src "ls180.v:4421.36-4421.251" - cell $or $or$ls180.v:4421$688 + attribute \src "ls180.v:4537.36-4537.251" + cell $or $or$ls180.v:4537$787 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4421$687_Y + connect \A $or$ls180.v:4537$786_Y connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4421$688_Y + connect \Y $or$ls180.v:4537$787_Y end - attribute \src "ls180.v:4442.35-4442.80" - cell $or $or$ls180.v:4442$689 + attribute \src "ls180.v:4558.35-4558.80" + cell $or $or$ls180.v:4558$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259480,10 +277349,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_stop connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4442$689_Y + connect \Y $or$ls180.v:4558$788_Y end - attribute \src "ls180.v:4596.91-4596.144" - cell $or $or$ls180.v:4596$703 + attribute \src "ls180.v:4712.91-4712.144" + cell $or $or$ls180.v:4712$802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259491,76 +277360,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4596$703_Y + connect \Y $or$ls180.v:4712$802_Y end - attribute \src "ls180.v:4613.53-4613.143" - cell $or $or$ls180.v:4613$706 + attribute \src "ls180.v:4729.53-4729.143" + cell $or $or$ls180.v:4729$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4613$705_Y + connect \A $not$ls180.v:4729$804_Y connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4613$706_Y + connect \Y $or$ls180.v:4729$805_Y end - attribute \src "ls180.v:4616.47-4616.127" - cell $or $or$ls180.v:4616$709 + attribute \src "ls180.v:4732.47-4732.127" + cell $or $or$ls180.v:4732$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4616$708_Y + connect \A $not$ls180.v:4732$807_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4616$709_Y + connect \Y $or$ls180.v:4732$808_Y end - attribute \src "ls180.v:4740.54-4740.146" - cell $or $or$ls180.v:4740$727 + attribute \src "ls180.v:4856.54-4856.146" + cell $or $or$ls180.v:4856$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4740$726_Y + connect \A $not$ls180.v:4856$825_Y connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4740$727_Y + connect \Y $or$ls180.v:4856$826_Y end - attribute \src "ls180.v:4743.48-4743.130" - cell $or $or$ls180.v:4743$730 + attribute \src "ls180.v:4859.48-4859.130" + cell $or $or$ls180.v:4859$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4743$729_Y + connect \A $not$ls180.v:4859$828_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4743$730_Y + connect \Y $or$ls180.v:4859$829_Y end - attribute \src "ls180.v:4874.55-4874.149" - cell $or $or$ls180.v:4874$742 + attribute \src "ls180.v:4990.55-4990.149" + cell $or $or$ls180.v:4990$841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4874$741_Y + connect \A $not$ls180.v:4990$840_Y connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4874$742_Y + connect \Y $or$ls180.v:4990$841_Y end - attribute \src "ls180.v:4877.49-4877.133" - cell $or $or$ls180.v:4877$745 + attribute \src "ls180.v:4993.49-4993.133" + cell $or $or$ls180.v:4993$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4877$744_Y + connect \A $not$ls180.v:4993$843_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4877$745_Y + connect \Y $or$ls180.v:4993$844_Y end - attribute \src "ls180.v:5506.80-5506.151" - cell $or $or$ls180.v:5506$1040 + attribute \src "ls180.v:5622.80-5622.151" + cell $or $or$ls180.v:5622$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259568,21 +277437,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_writable connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5506$1040_Y + connect \Y $or$ls180.v:5622$1139_Y end - attribute \src "ls180.v:5517.49-5517.131" - cell $or $or$ls180.v:5517$1046 + attribute \src "ls180.v:5633.49-5633.131" + cell $or $or$ls180.v:5633$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5517$1045_Y + connect \A $not$ls180.v:5633$1144_Y connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5517$1046_Y + connect \Y $or$ls180.v:5633$1145_Y end - attribute \src "ls180.v:5714.80-5714.151" - cell $or $or$ls180.v:5714$1071 + attribute \src "ls180.v:5842.80-5842.151" + cell $or $or$ls180.v:5842$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259590,10 +277459,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_writable connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5714$1071_Y + connect \Y $or$ls180.v:5842$1170_Y end - attribute \src "ls180.v:5856.36-5856.94" - cell $or $or$ls180.v:5856$1117 + attribute \src "ls180.v:6029.41-6029.99" + cell $or $or$ls180.v:6029$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259601,76 +277470,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_err connect \B \main_interface0_ram_bus_err - connect \Y $or$ls180.v:5856$1117_Y + connect \Y $or$ls180.v:6029$1226_Y end - attribute \src "ls180.v:5856.35-5856.125" - cell $or $or$ls180.v:5856$1118 + attribute \src "ls180.v:6029.40-6029.130" + cell $or $or$ls180.v:6029$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1117_Y + connect \A $or$ls180.v:6029$1226_Y connect \B \main_interface1_ram_bus_err - connect \Y $or$ls180.v:5856$1118_Y + connect \Y $or$ls180.v:6029$1227_Y end - attribute \src "ls180.v:5856.34-5856.156" - cell $or $or$ls180.v:5856$1119 + attribute \src "ls180.v:6029.39-6029.161" + cell $or $or$ls180.v:6029$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1118_Y + connect \A $or$ls180.v:6029$1227_Y connect \B \main_interface2_ram_bus_err - connect \Y $or$ls180.v:5856$1119_Y + connect \Y $or$ls180.v:6029$1228_Y + end + attribute \src "ls180.v:6029.38-6029.192" + cell $or $or$ls180.v:6029$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6029$1228_Y + connect \B \main_interface3_ram_bus_err + connect \Y $or$ls180.v:6029$1229_Y + end + attribute \src "ls180.v:6029.37-6029.235" + cell $or $or$ls180.v:6029$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6029$1229_Y + connect \B \main_interface0_converted_interface_err + connect \Y $or$ls180.v:6029$1230_Y + end + attribute \src "ls180.v:6029.36-6029.278" + cell $or $or$ls180.v:6029$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6029$1230_Y + connect \B \main_interface1_converted_interface_err + connect \Y $or$ls180.v:6029$1231_Y + end + attribute \src "ls180.v:6029.35-6029.322" + cell $or $or$ls180.v:6029$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6029$1231_Y + connect \B \main_libresocsim_libresoc_interface0_err + connect \Y $or$ls180.v:6029$1232_Y end - attribute \src "ls180.v:5856.33-5856.198" - cell $or $or$ls180.v:5856$1120 + attribute \src "ls180.v:6029.34-6029.366" + cell $or $or$ls180.v:6029$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1119_Y - connect \B \main_libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:5856$1120_Y + connect \A $or$ls180.v:6029$1232_Y + connect \B \main_libresocsim_libresoc_interface1_err + connect \Y $or$ls180.v:6029$1233_Y end - attribute \src "ls180.v:5856.32-5856.240" - cell $or $or$ls180.v:5856$1121 + attribute \src "ls180.v:6029.33-6029.410" + cell $or $or$ls180.v:6029$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1120_Y - connect \B \main_libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:5856$1121_Y + connect \A $or$ls180.v:6029$1233_Y + connect \B \main_libresocsim_libresoc_interface2_err + connect \Y $or$ls180.v:6029$1234_Y end - attribute \src "ls180.v:5856.31-5856.261" - cell $or $or$ls180.v:5856$1122 + attribute \src "ls180.v:6029.32-6029.454" + cell $or $or$ls180.v:6029$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1121_Y - connect \B \main_wb_sdram_err - connect \Y $or$ls180.v:5856$1122_Y + connect \A $or$ls180.v:6029$1234_Y + connect \B \main_libresocsim_libresoc_interface3_err + connect \Y $or$ls180.v:6029$1235_Y end - attribute \src "ls180.v:5856.30-5856.297" - cell $or $or$ls180.v:5856$1123 + attribute \src "ls180.v:6029.31-6029.500" + cell $or $or$ls180.v:6029$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1122_Y - connect \B \builder_libresocsim_wishbone_err - connect \Y $or$ls180.v:5856$1123_Y + connect \A $or$ls180.v:6029$1235_Y + connect \B \main_socbushandler_converted_interface_err + connect \Y $or$ls180.v:6029$1236_Y end - attribute \src "ls180.v:5862.31-5862.89" - cell $or $or$ls180.v:5862$1128 + attribute \src "ls180.v:6029.30-6029.547" + cell $or $or$ls180.v:6029$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6029$1236_Y + connect \B \builder_libresocsim_converted_interface_err + connect \Y $or$ls180.v:6029$1237_Y + end + attribute \src "ls180.v:6035.36-6035.94" + cell $or $or$ls180.v:6035$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259678,153 +277602,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack connect \B \main_interface0_ram_bus_ack - connect \Y $or$ls180.v:5862$1128_Y + connect \Y $or$ls180.v:6035$1242_Y end - attribute \src "ls180.v:5862.30-5862.120" - cell $or $or$ls180.v:5862$1129 + attribute \src "ls180.v:6035.35-6035.125" + cell $or $or$ls180.v:6035$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1128_Y + connect \A $or$ls180.v:6035$1242_Y connect \B \main_interface1_ram_bus_ack - connect \Y $or$ls180.v:5862$1129_Y + connect \Y $or$ls180.v:6035$1243_Y end - attribute \src "ls180.v:5862.29-5862.151" - cell $or $or$ls180.v:5862$1130 + attribute \src "ls180.v:6035.34-6035.156" + cell $or $or$ls180.v:6035$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1129_Y + connect \A $or$ls180.v:6035$1243_Y connect \B \main_interface2_ram_bus_ack - connect \Y $or$ls180.v:5862$1130_Y + connect \Y $or$ls180.v:6035$1244_Y end - attribute \src "ls180.v:5862.28-5862.193" - cell $or $or$ls180.v:5862$1131 + attribute \src "ls180.v:6035.33-6035.187" + cell $or $or$ls180.v:6035$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1130_Y - connect \B \main_libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:5862$1131_Y + connect \A $or$ls180.v:6035$1244_Y + connect \B \main_interface3_ram_bus_ack + connect \Y $or$ls180.v:6035$1245_Y end - attribute \src "ls180.v:5862.27-5862.235" - cell $or $or$ls180.v:5862$1132 + attribute \src "ls180.v:6035.32-6035.230" + cell $or $or$ls180.v:6035$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1131_Y - connect \B \main_libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:5862$1132_Y + connect \A $or$ls180.v:6035$1245_Y + connect \B \main_interface0_converted_interface_ack + connect \Y $or$ls180.v:6035$1246_Y end - attribute \src "ls180.v:5862.26-5862.256" - cell $or $or$ls180.v:5862$1133 + attribute \src "ls180.v:6035.31-6035.273" + cell $or $or$ls180.v:6035$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1132_Y - connect \B \main_wb_sdram_ack - connect \Y $or$ls180.v:5862$1133_Y + connect \A $or$ls180.v:6035$1246_Y + connect \B \main_interface1_converted_interface_ack + connect \Y $or$ls180.v:6035$1247_Y end - attribute \src "ls180.v:5862.25-5862.292" - cell $or $or$ls180.v:5862$1134 + attribute \src "ls180.v:6035.30-6035.317" + cell $or $or$ls180.v:6035$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1133_Y - connect \B \builder_libresocsim_wishbone_ack - connect \Y $or$ls180.v:5862$1134_Y + connect \A $or$ls180.v:6035$1247_Y + connect \B \main_libresocsim_libresoc_interface0_ack + connect \Y $or$ls180.v:6035$1248_Y end - attribute \src "ls180.v:5863.33-5863.161" - cell $or $or$ls180.v:5863$1137 + attribute \src "ls180.v:6035.29-6035.361" + cell $or $or$ls180.v:6035$1249 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $and$ls180.v:5863$1135_Y - connect \B $and$ls180.v:5863$1136_Y - connect \Y $or$ls180.v:5863$1137_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6035$1248_Y + connect \B \main_libresocsim_libresoc_interface1_ack + connect \Y $or$ls180.v:6035$1249_Y end - attribute \src "ls180.v:5863.32-5863.227" - cell $or $or$ls180.v:5863$1139 + attribute \src "ls180.v:6035.28-6035.405" + cell $or $or$ls180.v:6035$1250 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1137_Y - connect \B $and$ls180.v:5863$1138_Y - connect \Y $or$ls180.v:5863$1139_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6035$1249_Y + connect \B \main_libresocsim_libresoc_interface2_ack + connect \Y $or$ls180.v:6035$1250_Y end - attribute \src "ls180.v:5863.31-5863.293" - cell $or $or$ls180.v:5863$1141 + attribute \src "ls180.v:6035.27-6035.449" + cell $or $or$ls180.v:6035$1251 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1139_Y - connect \B $and$ls180.v:5863$1140_Y - connect \Y $or$ls180.v:5863$1141_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6035$1250_Y + connect \B \main_libresocsim_libresoc_interface3_ack + connect \Y $or$ls180.v:6035$1251_Y end - attribute \src "ls180.v:5863.30-5863.370" - cell $or $or$ls180.v:5863$1143 + attribute \src "ls180.v:6035.26-6035.495" + cell $or $or$ls180.v:6035$1252 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1141_Y - connect \B $and$ls180.v:5863$1142_Y - connect \Y $or$ls180.v:5863$1143_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6035$1251_Y + connect \B \main_socbushandler_converted_interface_ack + connect \Y $or$ls180.v:6035$1252_Y end - attribute \src "ls180.v:5863.29-5863.447" - cell $or $or$ls180.v:5863$1145 + attribute \src "ls180.v:6035.25-6035.542" + cell $or $or$ls180.v:6035$1253 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1143_Y - connect \B $and$ls180.v:5863$1144_Y - connect \Y $or$ls180.v:5863$1145_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6035$1252_Y + connect \B \builder_libresocsim_converted_interface_ack + connect \Y $or$ls180.v:6035$1253_Y end - attribute \src "ls180.v:5863.28-5863.503" - cell $or $or$ls180.v:5863$1147 + attribute \src "ls180.v:6036.38-6036.166" + cell $or $or$ls180.v:6036$1256 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1145_Y - connect \B $and$ls180.v:5863$1146_Y - connect \Y $or$ls180.v:5863$1147_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $and$ls180.v:6036$1254_Y + connect \B $and$ls180.v:6036$1255_Y + connect \Y $or$ls180.v:6036$1256_Y end - attribute \src "ls180.v:5863.27-5863.574" - cell $or $or$ls180.v:5863$1149 + attribute \src "ls180.v:6036.37-6036.232" + cell $or $or$ls180.v:6036$1258 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1147_Y - connect \B $and$ls180.v:5863$1148_Y - connect \Y $or$ls180.v:5863$1149_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1256_Y + connect \B $and$ls180.v:6036$1257_Y + connect \Y $or$ls180.v:6036$1258_Y + end + attribute \src "ls180.v:6036.36-6036.298" + cell $or $or$ls180.v:6036$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1258_Y + connect \B $and$ls180.v:6036$1259_Y + connect \Y $or$ls180.v:6036$1260_Y + end + attribute \src "ls180.v:6036.35-6036.364" + cell $or $or$ls180.v:6036$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1260_Y + connect \B $and$ls180.v:6036$1261_Y + connect \Y $or$ls180.v:6036$1262_Y + end + attribute \src "ls180.v:6036.34-6036.442" + cell $or $or$ls180.v:6036$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1262_Y + connect \B $and$ls180.v:6036$1263_Y + connect \Y $or$ls180.v:6036$1264_Y + end + attribute \src "ls180.v:6036.33-6036.520" + cell $or $or$ls180.v:6036$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1264_Y + connect \B $and$ls180.v:6036$1265_Y + connect \Y $or$ls180.v:6036$1266_Y + end + attribute \src "ls180.v:6036.32-6036.599" + cell $or $or$ls180.v:6036$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1266_Y + connect \B $and$ls180.v:6036$1267_Y + connect \Y $or$ls180.v:6036$1268_Y + end + attribute \src "ls180.v:6036.31-6036.678" + cell $or $or$ls180.v:6036$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1268_Y + connect \B $and$ls180.v:6036$1269_Y + connect \Y $or$ls180.v:6036$1270_Y + end + attribute \src "ls180.v:6036.30-6036.757" + cell $or $or$ls180.v:6036$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1270_Y + connect \B $and$ls180.v:6036$1271_Y + connect \Y $or$ls180.v:6036$1272_Y + end + attribute \src "ls180.v:6036.29-6036.837" + cell $or $or$ls180.v:6036$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1272_Y + connect \B $and$ls180.v:6036$1273_Y + connect \Y $or$ls180.v:6036$1274_Y + end + attribute \src "ls180.v:6036.28-6036.919" + cell $or $or$ls180.v:6036$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1274_Y + connect \B $and$ls180.v:6036$1275_Y + connect \Y $or$ls180.v:6036$1276_Y + end + attribute \src "ls180.v:6036.27-6036.1002" + cell $or $or$ls180.v:6036$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6036$1276_Y + connect \B $and$ls180.v:6036$1277_Y + connect \Y $or$ls180.v:6036$1278_Y end - attribute \src "ls180.v:6617.55-6617.124" - cell $or $or$ls180.v:6617$2295 + attribute \src "ls180.v:6790.55-6790.124" + cell $or $or$ls180.v:6790$2424 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -259832,285 +277866,285 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \builder_interface0_bank_bus_dat_r connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2295_Y + connect \Y $or$ls180.v:6790$2424_Y end - attribute \src "ls180.v:6617.54-6617.161" - cell $or $or$ls180.v:6617$2296 + attribute \src "ls180.v:6790.54-6790.161" + cell $or $or$ls180.v:6790$2425 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2295_Y + connect \A $or$ls180.v:6790$2424_Y connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2296_Y + connect \Y $or$ls180.v:6790$2425_Y end - attribute \src "ls180.v:6617.53-6617.198" - cell $or $or$ls180.v:6617$2297 + attribute \src "ls180.v:6790.53-6790.198" + cell $or $or$ls180.v:6790$2426 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2296_Y + connect \A $or$ls180.v:6790$2425_Y connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2297_Y + connect \Y $or$ls180.v:6790$2426_Y end - attribute \src "ls180.v:6617.52-6617.235" - cell $or $or$ls180.v:6617$2298 + attribute \src "ls180.v:6790.52-6790.235" + cell $or $or$ls180.v:6790$2427 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2297_Y + connect \A $or$ls180.v:6790$2426_Y connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2298_Y + connect \Y $or$ls180.v:6790$2427_Y end - attribute \src "ls180.v:6617.51-6617.272" - cell $or $or$ls180.v:6617$2299 + attribute \src "ls180.v:6790.51-6790.272" + cell $or $or$ls180.v:6790$2428 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2298_Y + connect \A $or$ls180.v:6790$2427_Y connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2299_Y + connect \Y $or$ls180.v:6790$2428_Y end - attribute \src "ls180.v:6617.50-6617.309" - cell $or $or$ls180.v:6617$2300 + attribute \src "ls180.v:6790.50-6790.309" + cell $or $or$ls180.v:6790$2429 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2299_Y + connect \A $or$ls180.v:6790$2428_Y connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2300_Y + connect \Y $or$ls180.v:6790$2429_Y end - attribute \src "ls180.v:6617.49-6617.346" - cell $or $or$ls180.v:6617$2301 + attribute \src "ls180.v:6790.49-6790.346" + cell $or $or$ls180.v:6790$2430 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2300_Y + connect \A $or$ls180.v:6790$2429_Y connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2301_Y + connect \Y $or$ls180.v:6790$2430_Y end - attribute \src "ls180.v:6617.48-6617.383" - cell $or $or$ls180.v:6617$2302 + attribute \src "ls180.v:6790.48-6790.383" + cell $or $or$ls180.v:6790$2431 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2301_Y + connect \A $or$ls180.v:6790$2430_Y connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2302_Y + connect \Y $or$ls180.v:6790$2431_Y end - attribute \src "ls180.v:6617.47-6617.420" - cell $or $or$ls180.v:6617$2303 + attribute \src "ls180.v:6790.47-6790.420" + cell $or $or$ls180.v:6790$2432 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2302_Y + connect \A $or$ls180.v:6790$2431_Y connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2303_Y + connect \Y $or$ls180.v:6790$2432_Y end - attribute \src "ls180.v:6617.46-6617.458" - cell $or $or$ls180.v:6617$2304 + attribute \src "ls180.v:6790.46-6790.458" + cell $or $or$ls180.v:6790$2433 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2303_Y + connect \A $or$ls180.v:6790$2432_Y connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2304_Y + connect \Y $or$ls180.v:6790$2433_Y end - attribute \src "ls180.v:6617.45-6617.496" - cell $or $or$ls180.v:6617$2305 + attribute \src "ls180.v:6790.45-6790.496" + cell $or $or$ls180.v:6790$2434 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2304_Y + connect \A $or$ls180.v:6790$2433_Y connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2305_Y + connect \Y $or$ls180.v:6790$2434_Y end - attribute \src "ls180.v:6617.44-6617.534" - cell $or $or$ls180.v:6617$2306 + attribute \src "ls180.v:6790.44-6790.534" + cell $or $or$ls180.v:6790$2435 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2305_Y + connect \A $or$ls180.v:6790$2434_Y connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2306_Y + connect \Y $or$ls180.v:6790$2435_Y end - attribute \src "ls180.v:6617.43-6617.572" - cell $or $or$ls180.v:6617$2307 + attribute \src "ls180.v:6790.43-6790.572" + cell $or $or$ls180.v:6790$2436 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2306_Y + connect \A $or$ls180.v:6790$2435_Y connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2307_Y + connect \Y $or$ls180.v:6790$2436_Y end - attribute \src "ls180.v:6617.42-6617.610" - cell $or $or$ls180.v:6617$2308 + attribute \src "ls180.v:6790.42-6790.610" + cell $or $or$ls180.v:6790$2437 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2307_Y + connect \A $or$ls180.v:6790$2436_Y connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2308_Y + connect \Y $or$ls180.v:6790$2437_Y end - attribute \src "ls180.v:6944.90-6944.179" - cell $or $or$ls180.v:6944$2333 + attribute \src "ls180.v:7117.90-7117.179" + cell $or $or$ls180.v:7117$2462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:6944$2332_Y - connect \Y $or$ls180.v:6944$2333_Y + connect \B $and$ls180.v:7117$2461_Y + connect \Y $or$ls180.v:7117$2462_Y end - attribute \src "ls180.v:6944.89-6944.254" - cell $or $or$ls180.v:6944$2336 + attribute \src "ls180.v:7117.89-7117.254" + cell $or $or$ls180.v:7117$2465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6944$2333_Y - connect \B $and$ls180.v:6944$2335_Y - connect \Y $or$ls180.v:6944$2336_Y + connect \A $or$ls180.v:7117$2462_Y + connect \B $and$ls180.v:7117$2464_Y + connect \Y $or$ls180.v:7117$2465_Y end - attribute \src "ls180.v:6944.88-6944.329" - cell $or $or$ls180.v:6944$2339 + attribute \src "ls180.v:7117.88-7117.329" + cell $or $or$ls180.v:7117$2468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6944$2336_Y - connect \B $and$ls180.v:6944$2338_Y - connect \Y $or$ls180.v:6944$2339_Y + connect \A $or$ls180.v:7117$2465_Y + connect \B $and$ls180.v:7117$2467_Y + connect \Y $or$ls180.v:7117$2468_Y end - attribute \src "ls180.v:6968.90-6968.179" - cell $or $or$ls180.v:6968$2349 + attribute \src "ls180.v:7141.90-7141.179" + cell $or $or$ls180.v:7141$2478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:6968$2348_Y - connect \Y $or$ls180.v:6968$2349_Y + connect \B $and$ls180.v:7141$2477_Y + connect \Y $or$ls180.v:7141$2478_Y end - attribute \src "ls180.v:6968.89-6968.254" - cell $or $or$ls180.v:6968$2352 + attribute \src "ls180.v:7141.89-7141.254" + cell $or $or$ls180.v:7141$2481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6968$2349_Y - connect \B $and$ls180.v:6968$2351_Y - connect \Y $or$ls180.v:6968$2352_Y + connect \A $or$ls180.v:7141$2478_Y + connect \B $and$ls180.v:7141$2480_Y + connect \Y $or$ls180.v:7141$2481_Y end - attribute \src "ls180.v:6968.88-6968.329" - cell $or $or$ls180.v:6968$2355 + attribute \src "ls180.v:7141.88-7141.329" + cell $or $or$ls180.v:7141$2484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6968$2352_Y - connect \B $and$ls180.v:6968$2354_Y - connect \Y $or$ls180.v:6968$2355_Y + connect \A $or$ls180.v:7141$2481_Y + connect \B $and$ls180.v:7141$2483_Y + connect \Y $or$ls180.v:7141$2484_Y end - attribute \src "ls180.v:6992.90-6992.179" - cell $or $or$ls180.v:6992$2365 + attribute \src "ls180.v:7165.90-7165.179" + cell $or $or$ls180.v:7165$2494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:6992$2364_Y - connect \Y $or$ls180.v:6992$2365_Y + connect \B $and$ls180.v:7165$2493_Y + connect \Y $or$ls180.v:7165$2494_Y end - attribute \src "ls180.v:6992.89-6992.254" - cell $or $or$ls180.v:6992$2368 + attribute \src "ls180.v:7165.89-7165.254" + cell $or $or$ls180.v:7165$2497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6992$2365_Y - connect \B $and$ls180.v:6992$2367_Y - connect \Y $or$ls180.v:6992$2368_Y + connect \A $or$ls180.v:7165$2494_Y + connect \B $and$ls180.v:7165$2496_Y + connect \Y $or$ls180.v:7165$2497_Y end - attribute \src "ls180.v:6992.88-6992.329" - cell $or $or$ls180.v:6992$2371 + attribute \src "ls180.v:7165.88-7165.329" + cell $or $or$ls180.v:7165$2500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6992$2368_Y - connect \B $and$ls180.v:6992$2370_Y - connect \Y $or$ls180.v:6992$2371_Y + connect \A $or$ls180.v:7165$2497_Y + connect \B $and$ls180.v:7165$2499_Y + connect \Y $or$ls180.v:7165$2500_Y end - attribute \src "ls180.v:7016.90-7016.179" - cell $or $or$ls180.v:7016$2381 + attribute \src "ls180.v:7189.90-7189.179" + cell $or $or$ls180.v:7189$2510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:7016$2380_Y - connect \Y $or$ls180.v:7016$2381_Y + connect \B $and$ls180.v:7189$2509_Y + connect \Y $or$ls180.v:7189$2510_Y end - attribute \src "ls180.v:7016.89-7016.254" - cell $or $or$ls180.v:7016$2384 + attribute \src "ls180.v:7189.89-7189.254" + cell $or $or$ls180.v:7189$2513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7016$2381_Y - connect \B $and$ls180.v:7016$2383_Y - connect \Y $or$ls180.v:7016$2384_Y + connect \A $or$ls180.v:7189$2510_Y + connect \B $and$ls180.v:7189$2512_Y + connect \Y $or$ls180.v:7189$2513_Y end - attribute \src "ls180.v:7016.88-7016.329" - cell $or $or$ls180.v:7016$2387 + attribute \src "ls180.v:7189.88-7189.329" + cell $or $or$ls180.v:7189$2516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7016$2384_Y - connect \B $and$ls180.v:7016$2386_Y - connect \Y $or$ls180.v:7016$2387_Y + connect \A $or$ls180.v:7189$2513_Y + connect \B $and$ls180.v:7189$2515_Y + connect \Y $or$ls180.v:7189$2516_Y end - attribute \src "ls180.v:7530.20-7530.71" - cell $or $or$ls180.v:7530$2444 + attribute \src "ls180.v:7706.20-7706.71" + cell $or $or$ls180.v:7706$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260118,10 +278152,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7530$2444_Y + connect \Y $or$ls180.v:7706$2574_Y end - attribute \src "ls180.v:7531.20-7531.71" - cell $or $or$ls180.v:7531$2445 + attribute \src "ls180.v:7707.20-7707.71" + cell $or $or$ls180.v:7707$2575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260129,10 +278163,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7531$2445_Y + connect \Y $or$ls180.v:7707$2575_Y end - attribute \src "ls180.v:7532.20-7532.71" - cell $or $or$ls180.v:7532$2446 + attribute \src "ls180.v:7708.20-7708.71" + cell $or $or$ls180.v:7708$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260140,10 +278174,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7532$2446_Y + connect \Y $or$ls180.v:7708$2576_Y end - attribute \src "ls180.v:7533.20-7533.71" - cell $or $or$ls180.v:7533$2447 + attribute \src "ls180.v:7709.20-7709.71" + cell $or $or$ls180.v:7709$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260151,10 +278185,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7533$2447_Y + connect \Y $or$ls180.v:7709$2577_Y end - attribute \src "ls180.v:7534.20-7534.71" - cell $or $or$ls180.v:7534$2448 + attribute \src "ls180.v:7710.20-7710.71" + cell $or $or$ls180.v:7710$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260162,10 +278196,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7534$2448_Y + connect \Y $or$ls180.v:7710$2578_Y end - attribute \src "ls180.v:7535.20-7535.71" - cell $or $or$ls180.v:7535$2449 + attribute \src "ls180.v:7711.20-7711.71" + cell $or $or$ls180.v:7711$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260173,10 +278207,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7535$2449_Y + connect \Y $or$ls180.v:7711$2579_Y end - attribute \src "ls180.v:7536.20-7536.71" - cell $or $or$ls180.v:7536$2450 + attribute \src "ls180.v:7712.20-7712.71" + cell $or $or$ls180.v:7712$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260184,10 +278218,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7536$2450_Y + connect \Y $or$ls180.v:7712$2580_Y end - attribute \src "ls180.v:7537.20-7537.71" - cell $or $or$ls180.v:7537$2451 + attribute \src "ls180.v:7713.20-7713.71" + cell $or $or$ls180.v:7713$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260195,10 +278229,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7537$2451_Y + connect \Y $or$ls180.v:7713$2581_Y end - attribute \src "ls180.v:7538.20-7538.71" - cell $or $or$ls180.v:7538$2452 + attribute \src "ls180.v:7714.20-7714.71" + cell $or $or$ls180.v:7714$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260206,10 +278240,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7538$2452_Y + connect \Y $or$ls180.v:7714$2582_Y end - attribute \src "ls180.v:7539.20-7539.71" - cell $or $or$ls180.v:7539$2453 + attribute \src "ls180.v:7715.20-7715.71" + cell $or $or$ls180.v:7715$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260217,10 +278251,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7539$2453_Y + connect \Y $or$ls180.v:7715$2583_Y end - attribute \src "ls180.v:7540.21-7540.73" - cell $or $or$ls180.v:7540$2454 + attribute \src "ls180.v:7716.21-7716.73" + cell $or $or$ls180.v:7716$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260228,10 +278262,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7540$2454_Y + connect \Y $or$ls180.v:7716$2584_Y end - attribute \src "ls180.v:7541.21-7541.73" - cell $or $or$ls180.v:7541$2455 + attribute \src "ls180.v:7717.21-7717.73" + cell $or $or$ls180.v:7717$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260239,10 +278273,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7541$2455_Y + connect \Y $or$ls180.v:7717$2585_Y end - attribute \src "ls180.v:7542.21-7542.73" - cell $or $or$ls180.v:7542$2456 + attribute \src "ls180.v:7718.21-7718.73" + cell $or $or$ls180.v:7718$2586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260250,10 +278284,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7542$2456_Y + connect \Y $or$ls180.v:7718$2586_Y end - attribute \src "ls180.v:7543.21-7543.73" - cell $or $or$ls180.v:7543$2457 + attribute \src "ls180.v:7719.21-7719.73" + cell $or $or$ls180.v:7719$2587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260261,10 +278295,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7543$2457_Y + connect \Y $or$ls180.v:7719$2587_Y end - attribute \src "ls180.v:7544.21-7544.73" - cell $or $or$ls180.v:7544$2458 + attribute \src "ls180.v:7720.21-7720.73" + cell $or $or$ls180.v:7720$2588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260272,10 +278306,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7544$2458_Y + connect \Y $or$ls180.v:7720$2588_Y end - attribute \src "ls180.v:7545.21-7545.73" - cell $or $or$ls180.v:7545$2459 + attribute \src "ls180.v:7721.21-7721.73" + cell $or $or$ls180.v:7721$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260283,10 +278317,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7545$2459_Y + connect \Y $or$ls180.v:7721$2589_Y end - attribute \src "ls180.v:7546.21-7546.73" - cell $or $or$ls180.v:7546$2460 + attribute \src "ls180.v:7722.21-7722.73" + cell $or $or$ls180.v:7722$2590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260294,10 +278328,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7546$2460_Y + connect \Y $or$ls180.v:7722$2590_Y end - attribute \src "ls180.v:7547.21-7547.73" - cell $or $or$ls180.v:7547$2461 + attribute \src "ls180.v:7723.21-7723.73" + cell $or $or$ls180.v:7723$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260305,10 +278339,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7547$2461_Y + connect \Y $or$ls180.v:7723$2591_Y end - attribute \src "ls180.v:7548.21-7548.73" - cell $or $or$ls180.v:7548$2462 + attribute \src "ls180.v:7724.21-7724.73" + cell $or $or$ls180.v:7724$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260316,10 +278350,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7548$2462_Y + connect \Y $or$ls180.v:7724$2592_Y end - attribute \src "ls180.v:7549.21-7549.73" - cell $or $or$ls180.v:7549$2463 + attribute \src "ls180.v:7725.21-7725.73" + cell $or $or$ls180.v:7725$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260327,10 +278361,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7549$2463_Y + connect \Y $or$ls180.v:7725$2593_Y end - attribute \src "ls180.v:7550.21-7550.73" - cell $or $or$ls180.v:7550$2464 + attribute \src "ls180.v:7726.21-7726.73" + cell $or $or$ls180.v:7726$2594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260338,10 +278372,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7550$2464_Y + connect \Y $or$ls180.v:7726$2594_Y end - attribute \src "ls180.v:7551.21-7551.73" - cell $or $or$ls180.v:7551$2465 + attribute \src "ls180.v:7727.21-7727.73" + cell $or $or$ls180.v:7727$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260349,10 +278383,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7551$2465_Y + connect \Y $or$ls180.v:7727$2595_Y end - attribute \src "ls180.v:7552.21-7552.73" - cell $or $or$ls180.v:7552$2466 + attribute \src "ls180.v:7728.21-7728.73" + cell $or $or$ls180.v:7728$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260360,10 +278394,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7552$2466_Y + connect \Y $or$ls180.v:7728$2596_Y end - attribute \src "ls180.v:7553.21-7553.73" - cell $or $or$ls180.v:7553$2467 + attribute \src "ls180.v:7729.21-7729.73" + cell $or $or$ls180.v:7729$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260371,175 +278405,175 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7553$2467_Y + connect \Y $or$ls180.v:7729$2597_Y end - attribute \src "ls180.v:7554.7-7554.93" - cell $or $or$ls180.v:7554$2468 + attribute \src "ls180.v:7730.7-7730.68" + cell $or $or$ls180.v:7730$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:7554$2468_Y + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:7730$2598_Y end - attribute \src "ls180.v:7565.7-7565.93" - cell $or $or$ls180.v:7565$2469 + attribute \src "ls180.v:7741.7-7741.68" + cell $or $or$ls180.v:7741$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:7565$2469_Y + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:7741$2599_Y end - attribute \src "ls180.v:7576.7-7576.93" - cell $or $or$ls180.v:7576$2470 + attribute \src "ls180.v:7752.7-7752.50" + cell $or $or$ls180.v:7752$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:7576$2470_Y + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:7752$2600_Y end - attribute \src "ls180.v:7717.7-7717.107" - cell $or $or$ls180.v:7717$2515 + attribute \src "ls180.v:7897.7-7897.107" + cell $or $or$ls180.v:7897$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7717$2514_Y + connect \A $not$ls180.v:7897$2647_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7717$2515_Y + connect \Y $or$ls180.v:7897$2648_Y end - attribute \src "ls180.v:7763.7-7763.107" - cell $or $or$ls180.v:7763$2531 + attribute \src "ls180.v:7943.7-7943.107" + cell $or $or$ls180.v:7943$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7763$2530_Y + connect \A $not$ls180.v:7943$2663_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7763$2531_Y + connect \Y $or$ls180.v:7943$2664_Y end - attribute \src "ls180.v:7809.7-7809.107" - cell $or $or$ls180.v:7809$2547 + attribute \src "ls180.v:7989.7-7989.107" + cell $or $or$ls180.v:7989$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7809$2546_Y + connect \A $not$ls180.v:7989$2679_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7809$2547_Y + connect \Y $or$ls180.v:7989$2680_Y end - attribute \src "ls180.v:7855.7-7855.107" - cell $or $or$ls180.v:7855$2563 + attribute \src "ls180.v:8035.7-8035.107" + cell $or $or$ls180.v:8035$2696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7855$2562_Y + connect \A $not$ls180.v:8035$2695_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7855$2563_Y + connect \Y $or$ls180.v:8035$2696_Y end - attribute \src "ls180.v:8043.40-8043.125" - cell $or $or$ls180.v:8043$2584 + attribute \src "ls180.v:8223.40-8223.125" + cell $or $or$ls180.v:8223$2717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8043$2583_Y - connect \Y $or$ls180.v:8043$2584_Y + connect \B $and$ls180.v:8223$2716_Y + connect \Y $or$ls180.v:8223$2717_Y end - attribute \src "ls180.v:8043.39-8043.207" - cell $or $or$ls180.v:8043$2587 + attribute \src "ls180.v:8223.39-8223.207" + cell $or $or$ls180.v:8223$2720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8043$2584_Y - connect \B $and$ls180.v:8043$2586_Y - connect \Y $or$ls180.v:8043$2587_Y + connect \A $or$ls180.v:8223$2717_Y + connect \B $and$ls180.v:8223$2719_Y + connect \Y $or$ls180.v:8223$2720_Y end - attribute \src "ls180.v:8043.38-8043.289" - cell $or $or$ls180.v:8043$2590 + attribute \src "ls180.v:8223.38-8223.289" + cell $or $or$ls180.v:8223$2723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8043$2587_Y - connect \B $and$ls180.v:8043$2589_Y - connect \Y $or$ls180.v:8043$2590_Y + connect \A $or$ls180.v:8223$2720_Y + connect \B $and$ls180.v:8223$2722_Y + connect \Y $or$ls180.v:8223$2723_Y end - attribute \src "ls180.v:8043.37-8043.371" - cell $or $or$ls180.v:8043$2593 + attribute \src "ls180.v:8223.37-8223.371" + cell $or $or$ls180.v:8223$2726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8043$2590_Y - connect \B $and$ls180.v:8043$2592_Y - connect \Y $or$ls180.v:8043$2593_Y + connect \A $or$ls180.v:8223$2723_Y + connect \B $and$ls180.v:8223$2725_Y + connect \Y $or$ls180.v:8223$2726_Y end - attribute \src "ls180.v:8044.41-8044.126" - cell $or $or$ls180.v:8044$2596 + attribute \src "ls180.v:8224.41-8224.126" + cell $or $or$ls180.v:8224$2729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8044$2595_Y - connect \Y $or$ls180.v:8044$2596_Y + connect \B $and$ls180.v:8224$2728_Y + connect \Y $or$ls180.v:8224$2729_Y end - attribute \src "ls180.v:8044.40-8044.208" - cell $or $or$ls180.v:8044$2599 + attribute \src "ls180.v:8224.40-8224.208" + cell $or $or$ls180.v:8224$2732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8044$2596_Y - connect \B $and$ls180.v:8044$2598_Y - connect \Y $or$ls180.v:8044$2599_Y + connect \A $or$ls180.v:8224$2729_Y + connect \B $and$ls180.v:8224$2731_Y + connect \Y $or$ls180.v:8224$2732_Y end - attribute \src "ls180.v:8044.39-8044.290" - cell $or $or$ls180.v:8044$2602 + attribute \src "ls180.v:8224.39-8224.290" + cell $or $or$ls180.v:8224$2735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8044$2599_Y - connect \B $and$ls180.v:8044$2601_Y - connect \Y $or$ls180.v:8044$2602_Y + connect \A $or$ls180.v:8224$2732_Y + connect \B $and$ls180.v:8224$2734_Y + connect \Y $or$ls180.v:8224$2735_Y end - attribute \src "ls180.v:8044.38-8044.372" - cell $or $or$ls180.v:8044$2605 + attribute \src "ls180.v:8224.38-8224.372" + cell $or $or$ls180.v:8224$2738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8044$2602_Y - connect \B $and$ls180.v:8044$2604_Y - connect \Y $or$ls180.v:8044$2605_Y + connect \A $or$ls180.v:8224$2735_Y + connect \B $and$ls180.v:8224$2737_Y + connect \Y $or$ls180.v:8224$2738_Y end - attribute \src "ls180.v:8048.7-8048.49" - cell $or $or$ls180.v:8048$2606 + attribute \src "ls180.v:8228.7-8228.49" + cell $or $or$ls180.v:8228$2739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260547,32 +278581,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:8048$2606_Y + connect \Y $or$ls180.v:8228$2739_Y end - attribute \src "ls180.v:8211.21-8211.74" - cell $or $or$ls180.v:8211$2654 + attribute \src "ls180.v:8391.21-8391.74" + cell $or $or$ls180.v:8391$2787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8211$2652_Y - connect \B $not$ls180.v:8211$2653_Y - connect \Y $or$ls180.v:8211$2654_Y + connect \A $not$ls180.v:8391$2785_Y + connect \B $not$ls180.v:8391$2786_Y + connect \Y $or$ls180.v:8391$2787_Y end - attribute \src "ls180.v:8246.21-8246.71" - cell $or $or$ls180.v:8246$2659 + attribute \src "ls180.v:8426.21-8426.71" + cell $or $or$ls180.v:8426$2792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8246$2657_Y - connect \B $not$ls180.v:8246$2658_Y - connect \Y $or$ls180.v:8246$2659_Y + connect \A $not$ls180.v:8426$2790_Y + connect \B $not$ls180.v:8426$2791_Y + connect \Y $or$ls180.v:8426$2792_Y end - attribute \src "ls180.v:8314.32-8314.85" - cell $or $or$ls180.v:8314$2671 + attribute \src "ls180.v:8494.32-8494.85" + cell $or $or$ls180.v:8494$2804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260580,21 +278614,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8314$2671_Y + connect \Y $or$ls180.v:8494$2804_Y end - attribute \src "ls180.v:8320.8-8320.97" - cell $or $or$ls180.v:8320$2673 + attribute \src "ls180.v:8500.8-8500.97" + cell $or $or$ls180.v:8500$2806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8320$2672_Y + connect \A $eq$ls180.v:8500$2805_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8320$2673_Y + connect \Y $or$ls180.v:8500$2806_Y end - attribute \src "ls180.v:8337.52-8337.139" - cell $or $or$ls180.v:8337$2678 + attribute \src "ls180.v:8517.52-8517.139" + cell $or $or$ls180.v:8517$2811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260602,10 +278636,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8337$2678_Y + connect \Y $or$ls180.v:8517$2811_Y end - attribute \src "ls180.v:8338.51-8338.136" - cell $or $or$ls180.v:8338$2679 + attribute \src "ls180.v:8518.51-8518.136" + cell $or $or$ls180.v:8518$2812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260613,21 +278647,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8338$2679_Y + connect \Y $or$ls180.v:8518$2812_Y end - attribute \src "ls180.v:8372.7-8372.87" - cell $or $or$ls180.v:8372$2682 + attribute \src "ls180.v:8552.7-8552.87" + cell $or $or$ls180.v:8552$2815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8372$2681_Y + connect \A $not$ls180.v:8552$2814_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8372$2682_Y + connect \Y $or$ls180.v:8552$2815_Y end - attribute \src "ls180.v:8395.33-8395.88" - cell $or $or$ls180.v:8395$2683 + attribute \src "ls180.v:8575.33-8575.88" + cell $or $or$ls180.v:8575$2816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260635,21 +278669,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8395$2683_Y + connect \Y $or$ls180.v:8575$2816_Y end - attribute \src "ls180.v:8401.8-8401.99" - cell $or $or$ls180.v:8401$2685 + attribute \src "ls180.v:8581.8-8581.99" + cell $or $or$ls180.v:8581$2818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8401$2684_Y + connect \A $eq$ls180.v:8581$2817_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8401$2685_Y + connect \Y $or$ls180.v:8581$2818_Y end - attribute \src "ls180.v:8418.53-8418.142" - cell $or $or$ls180.v:8418$2690 + attribute \src "ls180.v:8598.53-8598.142" + cell $or $or$ls180.v:8598$2823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260657,10 +278691,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8418$2690_Y + connect \Y $or$ls180.v:8598$2823_Y end - attribute \src "ls180.v:8419.52-8419.139" - cell $or $or$ls180.v:8419$2691 + attribute \src "ls180.v:8599.52-8599.139" + cell $or $or$ls180.v:8599$2824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260668,21 +278702,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8419$2691_Y + connect \Y $or$ls180.v:8599$2824_Y end - attribute \src "ls180.v:8453.7-8453.89" - cell $or $or$ls180.v:8453$2694 + attribute \src "ls180.v:8633.7-8633.89" + cell $or $or$ls180.v:8633$2827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8453$2693_Y + connect \A $not$ls180.v:8633$2826_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8453$2694_Y + connect \Y $or$ls180.v:8633$2827_Y end - attribute \src "ls180.v:8474.34-8474.91" - cell $or $or$ls180.v:8474$2695 + attribute \src "ls180.v:8654.34-8654.91" + cell $or $or$ls180.v:8654$2828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260690,21 +278724,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8474$2695_Y + connect \Y $or$ls180.v:8654$2828_Y end - attribute \src "ls180.v:8480.8-8480.101" - cell $or $or$ls180.v:8480$2697 + attribute \src "ls180.v:8660.8-8660.101" + cell $or $or$ls180.v:8660$2830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8480$2696_Y + connect \A $eq$ls180.v:8660$2829_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8480$2697_Y + connect \Y $or$ls180.v:8660$2830_Y end - attribute \src "ls180.v:8497.54-8497.145" - cell $or $or$ls180.v:8497$2702 + attribute \src "ls180.v:8677.54-8677.145" + cell $or $or$ls180.v:8677$2835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260712,10 +278746,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8497$2702_Y + connect \Y $or$ls180.v:8677$2835_Y end - attribute \src "ls180.v:8498.53-8498.142" - cell $or $or$ls180.v:8498$2703 + attribute \src "ls180.v:8678.53-8678.142" + cell $or $or$ls180.v:8678$2836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260723,32 +278757,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8498$2703_Y + connect \Y $or$ls180.v:8678$2836_Y end - attribute \src "ls180.v:8514.7-8514.91" - cell $or $or$ls180.v:8514$2706 + attribute \src "ls180.v:8694.7-8694.91" + cell $or $or$ls180.v:8694$2839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8514$2705_Y + connect \A $not$ls180.v:8694$2838_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8514$2706_Y + connect \Y $or$ls180.v:8694$2839_Y end - attribute \src "ls180.v:8703.8-8703.89" - cell $or $or$ls180.v:8703$2730 + attribute \src "ls180.v:8883.8-8883.89" + cell $or $or$ls180.v:8883$2863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8703$2729_Y + connect \A $eq$ls180.v:8883$2862_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8703$2730_Y + connect \Y $or$ls180.v:8883$2863_Y end - attribute \src "ls180.v:8720.48-8720.127" - cell $or $or$ls180.v:8720$2735 + attribute \src "ls180.v:8900.48-8900.127" + cell $or $or$ls180.v:8900$2868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260756,10 +278790,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8720$2735_Y + connect \Y $or$ls180.v:8900$2868_Y end - attribute \src "ls180.v:8721.47-8721.124" - cell $or $or$ls180.v:8721$2736 + attribute \src "ls180.v:8901.47-8901.124" + cell $or $or$ls180.v:8901$2869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260767,10 +278801,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8721$2736_Y + connect \Y $or$ls180.v:8901$2869_Y end - attribute \src "ls180.v:3253.46-3253.94" - cell $sshl $sshl$ls180.v:3253$134 + attribute \src "ls180.v:3358.46-3358.94" + cell $sshl $sshl$ls180.v:3358$231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260778,10 +278812,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine0_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3253$134_Y + connect \Y $sshl$ls180.v:3358$231_Y end - attribute \src "ls180.v:3410.46-3410.94" - cell $sshl $sshl$ls180.v:3410$164 + attribute \src "ls180.v:3515.46-3515.94" + cell $sshl $sshl$ls180.v:3515$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260789,10 +278823,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine1_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3410$164_Y + connect \Y $sshl$ls180.v:3515$261_Y end - attribute \src "ls180.v:3567.46-3567.94" - cell $sshl $sshl$ls180.v:3567$194 + attribute \src "ls180.v:3672.46-3672.94" + cell $sshl $sshl$ls180.v:3672$291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260800,10 +278834,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine2_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3567$194_Y + connect \Y $sshl$ls180.v:3672$291_Y end - attribute \src "ls180.v:3724.46-3724.94" - cell $sshl $sshl$ls180.v:3724$224 + attribute \src "ls180.v:3829.46-3829.94" + cell $sshl $sshl$ls180.v:3829$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260811,10 +278845,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine3_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3724$224_Y + connect \Y $sshl$ls180.v:3829$321_Y end - attribute \src "ls180.v:3284.63-3284.122" - cell $sub $sub$ls180.v:3284$147 + attribute \src "ls180.v:3389.63-3389.122" + cell $sub $sub$ls180.v:3389$244 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260822,10 +278856,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3284$147_Y + connect \Y $sub$ls180.v:3389$244_Y end - attribute \src "ls180.v:3441.63-3441.122" - cell $sub $sub$ls180.v:3441$177 + attribute \src "ls180.v:3546.63-3546.122" + cell $sub $sub$ls180.v:3546$274 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260833,10 +278867,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3441$177_Y + connect \Y $sub$ls180.v:3546$274_Y end - attribute \src "ls180.v:3598.63-3598.122" - cell $sub $sub$ls180.v:3598$207 + attribute \src "ls180.v:3703.63-3703.122" + cell $sub $sub$ls180.v:3703$304 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260844,10 +278878,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3598$207_Y + connect \Y $sub$ls180.v:3703$304_Y end - attribute \src "ls180.v:3755.63-3755.122" - cell $sub $sub$ls180.v:3755$237 + attribute \src "ls180.v:3860.63-3860.122" + cell $sub $sub$ls180.v:3860$334 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260855,10 +278889,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3755$237_Y + connect \Y $sub$ls180.v:3860$334_Y end - attribute \src "ls180.v:4161.38-4161.75" - cell $sub $sub$ls180.v:4161$591 + attribute \src "ls180.v:4266.38-4266.75" + cell $sub $sub$ls180.v:4266$688 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 @@ -260866,10 +278900,10 @@ module \ls180 parameter \Y_WIDTH 31 connect \A \main_litedram_wb_adr connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4161$591_Y + connect \Y $sub$ls180.v:4266$688_Y end - attribute \src "ls180.v:4247.36-4247.68" - cell $sub $sub$ls180.v:4247$636 + attribute \src "ls180.v:4352.36-4352.68" + cell $sub $sub$ls180.v:4352$733 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260877,10 +278911,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4247$636_Y + connect \Y $sub$ls180.v:4352$733_Y end - attribute \src "ls180.v:4277.36-4277.68" - cell $sub $sub$ls180.v:4277$647 + attribute \src "ls180.v:4382.36-4382.68" + cell $sub $sub$ls180.v:4382$744 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260888,10 +278922,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4277$647_Y + connect \Y $sub$ls180.v:4382$744_Y end - attribute \src "ls180.v:4302.70-4302.110" - cell $sub $sub$ls180.v:4302$653 + attribute \src "ls180.v:4418.70-4418.110" + cell $sub $sub$ls180.v:4418$752 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -260899,10 +278933,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4302$653_Y + connect \Y $sub$ls180.v:4418$752_Y end - attribute \src "ls180.v:4303.70-4303.104" - cell $sub $sub$ls180.v:4303$655 + attribute \src "ls180.v:4419.70-4419.104" + cell $sub $sub$ls180.v:4419$754 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -260910,10 +278944,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider connect \B 1'1 - connect \Y $sub$ls180.v:4303$655_Y + connect \Y $sub$ls180.v:4419$754_Y end - attribute \src "ls180.v:4330.37-4330.66" - cell $sub $sub$ls180.v:4330$659 + attribute \src "ls180.v:4446.37-4446.66" + cell $sub $sub$ls180.v:4446$758 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -260921,10 +278955,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spimaster1_length connect \B 1'1 - connect \Y $sub$ls180.v:4330$659_Y + connect \Y $sub$ls180.v:4446$758_Y end - attribute \src "ls180.v:4360.67-4360.107" - cell $sub $sub$ls180.v:4360$661 + attribute \src "ls180.v:4476.67-4476.107" + cell $sub $sub$ls180.v:4476$760 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -260932,10 +278966,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4360$661_Y + connect \Y $sub$ls180.v:4476$760_Y end - attribute \src "ls180.v:4361.67-4361.101" - cell $sub $sub$ls180.v:4361$663 + attribute \src "ls180.v:4477.67-4477.101" + cell $sub $sub$ls180.v:4477$762 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -260943,10 +278977,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 connect \B 1'1 - connect \Y $sub$ls180.v:4361$663_Y + connect \Y $sub$ls180.v:4477$762_Y end - attribute \src "ls180.v:4389.35-4389.64" - cell $sub $sub$ls180.v:4389$667 + attribute \src "ls180.v:4505.35-4505.64" + cell $sub $sub$ls180.v:4505$766 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -260954,10 +278988,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spisdcard_length0 connect \B 1'1 - connect \Y $sub$ls180.v:4389$667_Y + connect \Y $sub$ls180.v:4505$766_Y end - attribute \src "ls180.v:4643.60-4643.90" - cell $sub $sub$ls180.v:4643$711 + attribute \src "ls180.v:4759.60-4759.90" + cell $sub $sub$ls180.v:4759$810 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260965,10 +278999,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4643$711_Y + connect \Y $sub$ls180.v:4759$810_Y end - attribute \src "ls180.v:4654.62-4654.104" - cell $sub $sub$ls180.v:4654$713 + attribute \src "ls180.v:4770.62-4770.104" + cell $sub $sub$ls180.v:4770$812 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -260976,10 +279010,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_sink_payload_length connect \B 1'1 - connect \Y $sub$ls180.v:4654$713_Y + connect \Y $sub$ls180.v:4770$812_Y end - attribute \src "ls180.v:4671.60-4671.90" - cell $sub $sub$ls180.v:4671$717 + attribute \src "ls180.v:4787.60-4787.90" + cell $sub $sub$ls180.v:4787$816 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260987,10 +279021,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4671$717_Y + connect \Y $sub$ls180.v:4787$816_Y end - attribute \src "ls180.v:4900.62-4900.93" - cell $sub $sub$ls180.v:4900$747 + attribute \src "ls180.v:5016.62-5016.93" + cell $sub $sub$ls180.v:5016$846 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260998,10 +279032,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4900$747_Y + connect \Y $sub$ls180.v:5016$846_Y end - attribute \src "ls180.v:4905.62-4905.93" - cell $sub $sub$ls180.v:4905$748 + attribute \src "ls180.v:5021.62-5021.93" + cell $sub $sub$ls180.v:5021$847 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261009,21 +279043,21 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4905$748_Y + connect \Y $sub$ls180.v:5021$847_Y end - attribute \src "ls180.v:4916.64-4916.122" - cell $sub $sub$ls180.v:4916$751 + attribute \src "ls180.v:5032.64-5032.122" + cell $sub $sub$ls180.v:5032$850 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4916$750_Y + connect \A $add$ls180.v:5032$849_Y connect \B 1'1 - connect \Y $sub$ls180.v:4916$751_Y + connect \Y $sub$ls180.v:5032$850_Y end - attribute \src "ls180.v:4937.62-4937.93" - cell $sub $sub$ls180.v:4937$754 + attribute \src "ls180.v:5053.62-5053.93" + cell $sub $sub$ls180.v:5053$853 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261031,10 +279065,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4937$754_Y + connect \Y $sub$ls180.v:5053$853_Y end - attribute \src "ls180.v:5399.37-5399.75" - cell $sub $sub$ls180.v:5399$1027 + attribute \src "ls180.v:5515.37-5515.75" + cell $sub $sub$ls180.v:5515$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261042,10 +279076,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5399$1027_Y + connect \Y $sub$ls180.v:5515$1126_Y end - attribute \src "ls180.v:5414.62-5414.100" - cell $sub $sub$ls180.v:5414$1030 + attribute \src "ls180.v:5530.62-5530.100" + cell $sub $sub$ls180.v:5530$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261053,10 +279087,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5414$1030_Y + connect \Y $sub$ls180.v:5530$1129_Y end - attribute \src "ls180.v:5425.39-5425.77" - cell $sub $sub$ls180.v:5425$1035 + attribute \src "ls180.v:5541.39-5541.77" + cell $sub $sub$ls180.v:5541$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261064,10 +279098,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5425$1035_Y + connect \Y $sub$ls180.v:5541$1134_Y end - attribute \src "ls180.v:5500.40-5500.76" - cell $sub $sub$ls180.v:5500$1039 + attribute \src "ls180.v:5616.40-5616.76" + cell $sub $sub$ls180.v:5616$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261075,10 +279109,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5500$1039_Y + connect \Y $sub$ls180.v:5616$1138_Y end - attribute \src "ls180.v:5549.56-5549.104" - cell $sub $sub$ls180.v:5549$1053 + attribute \src "ls180.v:5665.56-5665.104" + cell $sub $sub$ls180.v:5665$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261086,10 +279120,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_length connect \B 1'1 - connect \Y $sub$ls180.v:5549$1053_Y + connect \Y $sub$ls180.v:5665$1152_Y end - attribute \src "ls180.v:5639.71-5639.105" - cell $sub $sub$ls180.v:5639$1059 + attribute \src "ls180.v:5755.71-5755.105" + cell $sub $sub$ls180.v:5755$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261097,10 +279131,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_length connect \B 1'1 - connect \Y $sub$ls180.v:5639$1059_Y + connect \Y $sub$ls180.v:5755$1158_Y end - attribute \src "ls180.v:5708.40-5708.76" - cell $sub $sub$ls180.v:5708$1070 + attribute \src "ls180.v:5836.40-5836.76" + cell $sub $sub$ls180.v:5836$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261108,10 +279142,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5708$1070_Y + connect \Y $sub$ls180.v:5836$1169_Y end - attribute \src "ls180.v:7600.31-7600.60" - cell $sub $sub$ls180.v:7600$2477 + attribute \src "ls180.v:7776.31-7776.60" + cell $sub $sub$ls180.v:7776$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261119,10 +279153,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7600$2477_Y + connect \Y $sub$ls180.v:7776$2607_Y end - attribute \src "ls180.v:7633.31-7633.61" - cell $sub $sub$ls180.v:7633$2491 + attribute \src "ls180.v:7813.31-7813.61" + cell $sub $sub$ls180.v:7813$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -261130,10 +279164,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7633$2491_Y + connect \Y $sub$ls180.v:7813$2624_Y end - attribute \src "ls180.v:7639.34-7639.67" - cell $sub $sub$ls180.v:7639$2492 + attribute \src "ls180.v:7819.34-7819.67" + cell $sub $sub$ls180.v:7819$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261141,10 +279175,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7639$2492_Y + connect \Y $sub$ls180.v:7819$2625_Y end - attribute \src "ls180.v:7650.36-7650.69" - cell $sub $sub$ls180.v:7650$2495 + attribute \src "ls180.v:7830.36-7830.69" + cell $sub $sub$ls180.v:7830$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261152,10 +279186,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7650$2495_Y + connect \Y $sub$ls180.v:7830$2628_Y end - attribute \src "ls180.v:7714.59-7714.116" - cell $sub $sub$ls180.v:7714$2513 + attribute \src "ls180.v:7894.59-7894.116" + cell $sub $sub$ls180.v:7894$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261163,10 +279197,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7714$2513_Y + connect \Y $sub$ls180.v:7894$2646_Y end - attribute \src "ls180.v:7733.46-7733.90" - cell $sub $sub$ls180.v:7733$2517 + attribute \src "ls180.v:7913.46-7913.90" + cell $sub $sub$ls180.v:7913$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261174,10 +279208,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7733$2517_Y + connect \Y $sub$ls180.v:7913$2650_Y end - attribute \src "ls180.v:7760.59-7760.116" - cell $sub $sub$ls180.v:7760$2529 + attribute \src "ls180.v:7940.59-7940.116" + cell $sub $sub$ls180.v:7940$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261185,10 +279219,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7760$2529_Y + connect \Y $sub$ls180.v:7940$2662_Y end - attribute \src "ls180.v:7779.46-7779.90" - cell $sub $sub$ls180.v:7779$2533 + attribute \src "ls180.v:7959.46-7959.90" + cell $sub $sub$ls180.v:7959$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261196,10 +279230,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7779$2533_Y + connect \Y $sub$ls180.v:7959$2666_Y end - attribute \src "ls180.v:7806.59-7806.116" - cell $sub $sub$ls180.v:7806$2545 + attribute \src "ls180.v:7986.59-7986.116" + cell $sub $sub$ls180.v:7986$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261207,10 +279241,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7806$2545_Y + connect \Y $sub$ls180.v:7986$2678_Y end - attribute \src "ls180.v:7825.46-7825.90" - cell $sub $sub$ls180.v:7825$2549 + attribute \src "ls180.v:8005.46-8005.90" + cell $sub $sub$ls180.v:8005$2682 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261218,10 +279252,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7825$2549_Y + connect \Y $sub$ls180.v:8005$2682_Y end - attribute \src "ls180.v:7852.59-7852.116" - cell $sub $sub$ls180.v:7852$2561 + attribute \src "ls180.v:8032.59-8032.116" + cell $sub $sub$ls180.v:8032$2694 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261229,10 +279263,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7852$2561_Y + connect \Y $sub$ls180.v:8032$2694_Y end - attribute \src "ls180.v:7871.46-7871.90" - cell $sub $sub$ls180.v:7871$2565 + attribute \src "ls180.v:8051.46-8051.90" + cell $sub $sub$ls180.v:8051$2698 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261240,10 +279274,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7871$2565_Y + connect \Y $sub$ls180.v:8051$2698_Y end - attribute \src "ls180.v:7882.25-7882.48" - cell $sub $sub$ls180.v:7882$2569 + attribute \src "ls180.v:8062.25-8062.48" + cell $sub $sub$ls180.v:8062$2702 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261251,10 +279285,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:7882$2569_Y + connect \Y $sub$ls180.v:8062$2702_Y end - attribute \src "ls180.v:7889.25-7889.48" - cell $sub $sub$ls180.v:7889$2572 + attribute \src "ls180.v:8069.25-8069.48" + cell $sub $sub$ls180.v:8069$2705 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261262,10 +279296,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:7889$2572_Y + connect \Y $sub$ls180.v:8069$2705_Y end - attribute \src "ls180.v:8021.33-8021.64" - cell $sub $sub$ls180.v:8021$2577 + attribute \src "ls180.v:8201.33-8201.64" + cell $sub $sub$ls180.v:8201$2710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261273,10 +279307,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8021$2577_Y + connect \Y $sub$ls180.v:8201$2710_Y end - attribute \src "ls180.v:8036.33-8036.64" - cell $sub $sub$ls180.v:8036$2580 + attribute \src "ls180.v:8216.33-8216.64" + cell $sub $sub$ls180.v:8216$2713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261284,10 +279318,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8036$2580_Y + connect \Y $sub$ls180.v:8216$2713_Y end - attribute \src "ls180.v:8163.33-8163.64" - cell $sub $sub$ls180.v:8163$2639 + attribute \src "ls180.v:8343.33-8343.64" + cell $sub $sub$ls180.v:8343$2772 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261295,10 +279329,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8163$2639_Y + connect \Y $sub$ls180.v:8343$2772_Y end - attribute \src "ls180.v:8185.33-8185.64" - cell $sub $sub$ls180.v:8185$2650 + attribute \src "ls180.v:8365.33-8365.64" + cell $sub $sub$ls180.v:8365$2783 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261306,10 +279340,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8185$2650_Y + connect \Y $sub$ls180.v:8365$2783_Y end - attribute \src "ls180.v:8220.34-8220.66" - cell $sub $sub$ls180.v:8220$2655 + attribute \src "ls180.v:8400.34-8400.66" + cell $sub $sub$ls180.v:8400$2788 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261317,10 +279351,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster34_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8220$2655_Y + connect \Y $sub$ls180.v:8400$2788_Y end - attribute \src "ls180.v:8255.32-8255.62" - cell $sub $sub$ls180.v:8255$2660 + attribute \src "ls180.v:8435.32-8435.62" + cell $sub $sub$ls180.v:8435$2793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261328,10 +279362,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8255$2660_Y + connect \Y $sub$ls180.v:8435$2793_Y end - attribute \src "ls180.v:8279.30-8279.53" - cell $sub $sub$ls180.v:8279$2663 + attribute \src "ls180.v:8459.30-8459.53" + cell $sub $sub$ls180.v:8459$2796 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261339,10 +279373,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8279$2663_Y + connect \Y $sub$ls180.v:8459$2796_Y end - attribute \src "ls180.v:8293.30-8293.53" - cell $sub $sub$ls180.v:8293$2667 + attribute \src "ls180.v:8473.30-8473.53" + cell $sub $sub$ls180.v:8473$2800 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261350,10 +279384,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8293$2667_Y + connect \Y $sub$ls180.v:8473$2800_Y end - attribute \src "ls180.v:8696.36-8696.70" - cell $sub $sub$ls180.v:8696$2728 + attribute \src "ls180.v:8876.36-8876.70" + cell $sub $sub$ls180.v:8876$2861 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -261361,10 +279395,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8696$2728_Y + connect \Y $sub$ls180.v:8876$2861_Y end - attribute \src "ls180.v:8782.36-8782.70" - cell $sub $sub$ls180.v:8782$2750 + attribute \src "ls180.v:8974.36-8974.70" + cell $sub $sub$ls180.v:8974$2883 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -261372,10 +279406,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8782$2750_Y + connect \Y $sub$ls180.v:8974$2883_Y end - attribute \src "ls180.v:8895.22-8895.42" - cell $sub $sub$ls180.v:8895$2757 + attribute \src "ls180.v:9087.22-9087.42" + cell $sub $sub$ls180.v:9087$2890 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -261383,10 +279417,10 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:8895$2757_Y + connect \Y $sub$ls180.v:9087$2890_Y end - attribute \src "ls180.v:4997.353-4997.425" - cell $xor $xor$ls180.v:4997$761 + attribute \src "ls180.v:5113.353-5113.425" + cell $xor $xor$ls180.v:5113$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261394,10 +279428,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4997$761_Y + connect \Y $xor$ls180.v:5113$860_Y end - attribute \src "ls180.v:4997.200-4997.272" - cell $xor $xor$ls180.v:4997$762 + attribute \src "ls180.v:5113.200-5113.272" + cell $xor $xor$ls180.v:5113$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261405,21 +279439,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4997$762_Y + connect \Y $xor$ls180.v:5113$861_Y end - attribute \src "ls180.v:4997.160-4997.273" - cell $xor $xor$ls180.v:4997$763 + attribute \src "ls180.v:5113.160-5113.273" + cell $xor $xor$ls180.v:5113$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4997$762_Y - connect \Y $xor$ls180.v:4997$763_Y + connect \B $xor$ls180.v:5113$861_Y + connect \Y $xor$ls180.v:5113$862_Y end - attribute \src "ls180.v:4998.353-4998.425" - cell $xor $xor$ls180.v:4998$764 + attribute \src "ls180.v:5114.353-5114.425" + cell $xor $xor$ls180.v:5114$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261427,10 +279461,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4998$764_Y + connect \Y $xor$ls180.v:5114$863_Y end - attribute \src "ls180.v:4998.200-4998.272" - cell $xor $xor$ls180.v:4998$765 + attribute \src "ls180.v:5114.200-5114.272" + cell $xor $xor$ls180.v:5114$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261438,21 +279472,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4998$765_Y + connect \Y $xor$ls180.v:5114$864_Y end - attribute \src "ls180.v:4998.160-4998.273" - cell $xor $xor$ls180.v:4998$766 + attribute \src "ls180.v:5114.160-5114.273" + cell $xor $xor$ls180.v:5114$865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4998$765_Y - connect \Y $xor$ls180.v:4998$766_Y + connect \B $xor$ls180.v:5114$864_Y + connect \Y $xor$ls180.v:5114$865_Y end - attribute \src "ls180.v:4999.353-4999.425" - cell $xor $xor$ls180.v:4999$767 + attribute \src "ls180.v:5115.353-5115.425" + cell $xor $xor$ls180.v:5115$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261460,10 +279494,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4999$767_Y + connect \Y $xor$ls180.v:5115$866_Y end - attribute \src "ls180.v:4999.200-4999.272" - cell $xor $xor$ls180.v:4999$768 + attribute \src "ls180.v:5115.200-5115.272" + cell $xor $xor$ls180.v:5115$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261471,21 +279505,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4999$768_Y + connect \Y $xor$ls180.v:5115$867_Y end - attribute \src "ls180.v:4999.160-4999.273" - cell $xor $xor$ls180.v:4999$769 + attribute \src "ls180.v:5115.160-5115.273" + cell $xor $xor$ls180.v:5115$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4999$768_Y - connect \Y $xor$ls180.v:4999$769_Y + connect \B $xor$ls180.v:5115$867_Y + connect \Y $xor$ls180.v:5115$868_Y end - attribute \src "ls180.v:5000.353-5000.425" - cell $xor $xor$ls180.v:5000$770 + attribute \src "ls180.v:5116.353-5116.425" + cell $xor $xor$ls180.v:5116$869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261493,10 +279527,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5000$770_Y + connect \Y $xor$ls180.v:5116$869_Y end - attribute \src "ls180.v:5000.200-5000.272" - cell $xor $xor$ls180.v:5000$771 + attribute \src "ls180.v:5116.200-5116.272" + cell $xor $xor$ls180.v:5116$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261504,21 +279538,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5000$771_Y + connect \Y $xor$ls180.v:5116$870_Y end - attribute \src "ls180.v:5000.160-5000.273" - cell $xor $xor$ls180.v:5000$772 + attribute \src "ls180.v:5116.160-5116.273" + cell $xor $xor$ls180.v:5116$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:5000$771_Y - connect \Y $xor$ls180.v:5000$772_Y + connect \B $xor$ls180.v:5116$870_Y + connect \Y $xor$ls180.v:5116$871_Y end - attribute \src "ls180.v:5001.353-5001.425" - cell $xor $xor$ls180.v:5001$773 + attribute \src "ls180.v:5117.353-5117.425" + cell $xor $xor$ls180.v:5117$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261526,10 +279560,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5001$773_Y + connect \Y $xor$ls180.v:5117$872_Y end - attribute \src "ls180.v:5001.200-5001.272" - cell $xor $xor$ls180.v:5001$774 + attribute \src "ls180.v:5117.200-5117.272" + cell $xor $xor$ls180.v:5117$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261537,21 +279571,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5001$774_Y + connect \Y $xor$ls180.v:5117$873_Y end - attribute \src "ls180.v:5001.160-5001.273" - cell $xor $xor$ls180.v:5001$775 + attribute \src "ls180.v:5117.160-5117.273" + cell $xor $xor$ls180.v:5117$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:5001$774_Y - connect \Y $xor$ls180.v:5001$775_Y + connect \B $xor$ls180.v:5117$873_Y + connect \Y $xor$ls180.v:5117$874_Y end - attribute \src "ls180.v:5002.353-5002.425" - cell $xor $xor$ls180.v:5002$776 + attribute \src "ls180.v:5118.353-5118.425" + cell $xor $xor$ls180.v:5118$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261559,10 +279593,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5002$776_Y + connect \Y $xor$ls180.v:5118$875_Y end - attribute \src "ls180.v:5002.200-5002.272" - cell $xor $xor$ls180.v:5002$777 + attribute \src "ls180.v:5118.200-5118.272" + cell $xor $xor$ls180.v:5118$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261570,21 +279604,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5002$777_Y + connect \Y $xor$ls180.v:5118$876_Y end - attribute \src "ls180.v:5002.160-5002.273" - cell $xor $xor$ls180.v:5002$778 + attribute \src "ls180.v:5118.160-5118.273" + cell $xor $xor$ls180.v:5118$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:5002$777_Y - connect \Y $xor$ls180.v:5002$778_Y + connect \B $xor$ls180.v:5118$876_Y + connect \Y $xor$ls180.v:5118$877_Y end - attribute \src "ls180.v:5003.353-5003.425" - cell $xor $xor$ls180.v:5003$779 + attribute \src "ls180.v:5119.353-5119.425" + cell $xor $xor$ls180.v:5119$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261592,10 +279626,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5003$779_Y + connect \Y $xor$ls180.v:5119$878_Y end - attribute \src "ls180.v:5003.200-5003.272" - cell $xor $xor$ls180.v:5003$780 + attribute \src "ls180.v:5119.200-5119.272" + cell $xor $xor$ls180.v:5119$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261603,21 +279637,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5003$780_Y + connect \Y $xor$ls180.v:5119$879_Y end - attribute \src "ls180.v:5003.160-5003.273" - cell $xor $xor$ls180.v:5003$781 + attribute \src "ls180.v:5119.160-5119.273" + cell $xor $xor$ls180.v:5119$880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:5003$780_Y - connect \Y $xor$ls180.v:5003$781_Y + connect \B $xor$ls180.v:5119$879_Y + connect \Y $xor$ls180.v:5119$880_Y end - attribute \src "ls180.v:5004.353-5004.425" - cell $xor $xor$ls180.v:5004$782 + attribute \src "ls180.v:5120.353-5120.425" + cell $xor $xor$ls180.v:5120$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261625,10 +279659,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5004$782_Y + connect \Y $xor$ls180.v:5120$881_Y end - attribute \src "ls180.v:5004.200-5004.272" - cell $xor $xor$ls180.v:5004$783 + attribute \src "ls180.v:5120.200-5120.272" + cell $xor $xor$ls180.v:5120$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261636,21 +279670,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5004$783_Y + connect \Y $xor$ls180.v:5120$882_Y end - attribute \src "ls180.v:5004.160-5004.273" - cell $xor $xor$ls180.v:5004$784 + attribute \src "ls180.v:5120.160-5120.273" + cell $xor $xor$ls180.v:5120$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:5004$783_Y - connect \Y $xor$ls180.v:5004$784_Y + connect \B $xor$ls180.v:5120$882_Y + connect \Y $xor$ls180.v:5120$883_Y end - attribute \src "ls180.v:5005.353-5005.425" - cell $xor $xor$ls180.v:5005$785 + attribute \src "ls180.v:5121.353-5121.425" + cell $xor $xor$ls180.v:5121$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261658,10 +279692,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5005$785_Y + connect \Y $xor$ls180.v:5121$884_Y end - attribute \src "ls180.v:5005.200-5005.272" - cell $xor $xor$ls180.v:5005$786 + attribute \src "ls180.v:5121.200-5121.272" + cell $xor $xor$ls180.v:5121$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261669,21 +279703,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5005$786_Y + connect \Y $xor$ls180.v:5121$885_Y end - attribute \src "ls180.v:5005.160-5005.273" - cell $xor $xor$ls180.v:5005$787 + attribute \src "ls180.v:5121.160-5121.273" + cell $xor $xor$ls180.v:5121$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:5005$786_Y - connect \Y $xor$ls180.v:5005$787_Y + connect \B $xor$ls180.v:5121$885_Y + connect \Y $xor$ls180.v:5121$886_Y end - attribute \src "ls180.v:5006.354-5006.426" - cell $xor $xor$ls180.v:5006$788 + attribute \src "ls180.v:5122.354-5122.426" + cell $xor $xor$ls180.v:5122$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261691,10 +279725,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5006$788_Y + connect \Y $xor$ls180.v:5122$887_Y end - attribute \src "ls180.v:5006.201-5006.273" - cell $xor $xor$ls180.v:5006$789 + attribute \src "ls180.v:5122.201-5122.273" + cell $xor $xor$ls180.v:5122$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261702,21 +279736,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5006$789_Y + connect \Y $xor$ls180.v:5122$888_Y end - attribute \src "ls180.v:5006.161-5006.274" - cell $xor $xor$ls180.v:5006$790 + attribute \src "ls180.v:5122.161-5122.274" + cell $xor $xor$ls180.v:5122$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:5006$789_Y - connect \Y $xor$ls180.v:5006$790_Y + connect \B $xor$ls180.v:5122$888_Y + connect \Y $xor$ls180.v:5122$889_Y end - attribute \src "ls180.v:5007.361-5007.434" - cell $xor $xor$ls180.v:5007$791 + attribute \src "ls180.v:5123.361-5123.434" + cell $xor $xor$ls180.v:5123$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261724,10 +279758,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5007$791_Y + connect \Y $xor$ls180.v:5123$890_Y end - attribute \src "ls180.v:5007.205-5007.278" - cell $xor $xor$ls180.v:5007$792 + attribute \src "ls180.v:5123.205-5123.278" + cell $xor $xor$ls180.v:5123$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261735,21 +279769,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5007$792_Y + connect \Y $xor$ls180.v:5123$891_Y end - attribute \src "ls180.v:5007.164-5007.279" - cell $xor $xor$ls180.v:5007$793 + attribute \src "ls180.v:5123.164-5123.279" + cell $xor $xor$ls180.v:5123$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:5007$792_Y - connect \Y $xor$ls180.v:5007$793_Y + connect \B $xor$ls180.v:5123$891_Y + connect \Y $xor$ls180.v:5123$892_Y end - attribute \src "ls180.v:5008.361-5008.434" - cell $xor $xor$ls180.v:5008$794 + attribute \src "ls180.v:5124.361-5124.434" + cell $xor $xor$ls180.v:5124$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261757,10 +279791,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5008$794_Y + connect \Y $xor$ls180.v:5124$893_Y end - attribute \src "ls180.v:5008.205-5008.278" - cell $xor $xor$ls180.v:5008$795 + attribute \src "ls180.v:5124.205-5124.278" + cell $xor $xor$ls180.v:5124$894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261768,21 +279802,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5008$795_Y + connect \Y $xor$ls180.v:5124$894_Y end - attribute \src "ls180.v:5008.164-5008.279" - cell $xor $xor$ls180.v:5008$796 + attribute \src "ls180.v:5124.164-5124.279" + cell $xor $xor$ls180.v:5124$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:5008$795_Y - connect \Y $xor$ls180.v:5008$796_Y + connect \B $xor$ls180.v:5124$894_Y + connect \Y $xor$ls180.v:5124$895_Y end - attribute \src "ls180.v:5009.361-5009.434" - cell $xor $xor$ls180.v:5009$797 + attribute \src "ls180.v:5125.361-5125.434" + cell $xor $xor$ls180.v:5125$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261790,10 +279824,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5009$797_Y + connect \Y $xor$ls180.v:5125$896_Y end - attribute \src "ls180.v:5009.205-5009.278" - cell $xor $xor$ls180.v:5009$798 + attribute \src "ls180.v:5125.205-5125.278" + cell $xor $xor$ls180.v:5125$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261801,21 +279835,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5009$798_Y + connect \Y $xor$ls180.v:5125$897_Y end - attribute \src "ls180.v:5009.164-5009.279" - cell $xor $xor$ls180.v:5009$799 + attribute \src "ls180.v:5125.164-5125.279" + cell $xor $xor$ls180.v:5125$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:5009$798_Y - connect \Y $xor$ls180.v:5009$799_Y + connect \B $xor$ls180.v:5125$897_Y + connect \Y $xor$ls180.v:5125$898_Y end - attribute \src "ls180.v:5010.361-5010.434" - cell $xor $xor$ls180.v:5010$800 + attribute \src "ls180.v:5126.361-5126.434" + cell $xor $xor$ls180.v:5126$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261823,10 +279857,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5010$800_Y + connect \Y $xor$ls180.v:5126$899_Y end - attribute \src "ls180.v:5010.205-5010.278" - cell $xor $xor$ls180.v:5010$801 + attribute \src "ls180.v:5126.205-5126.278" + cell $xor $xor$ls180.v:5126$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261834,21 +279868,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5010$801_Y + connect \Y $xor$ls180.v:5126$900_Y end - attribute \src "ls180.v:5010.164-5010.279" - cell $xor $xor$ls180.v:5010$802 + attribute \src "ls180.v:5126.164-5126.279" + cell $xor $xor$ls180.v:5126$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:5010$801_Y - connect \Y $xor$ls180.v:5010$802_Y + connect \B $xor$ls180.v:5126$900_Y + connect \Y $xor$ls180.v:5126$901_Y end - attribute \src "ls180.v:5011.361-5011.434" - cell $xor $xor$ls180.v:5011$803 + attribute \src "ls180.v:5127.361-5127.434" + cell $xor $xor$ls180.v:5127$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261856,10 +279890,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5011$803_Y + connect \Y $xor$ls180.v:5127$902_Y end - attribute \src "ls180.v:5011.205-5011.278" - cell $xor $xor$ls180.v:5011$804 + attribute \src "ls180.v:5127.205-5127.278" + cell $xor $xor$ls180.v:5127$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261867,21 +279901,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5011$804_Y + connect \Y $xor$ls180.v:5127$903_Y end - attribute \src "ls180.v:5011.164-5011.279" - cell $xor $xor$ls180.v:5011$805 + attribute \src "ls180.v:5127.164-5127.279" + cell $xor $xor$ls180.v:5127$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:5011$804_Y - connect \Y $xor$ls180.v:5011$805_Y + connect \B $xor$ls180.v:5127$903_Y + connect \Y $xor$ls180.v:5127$904_Y end - attribute \src "ls180.v:5012.361-5012.434" - cell $xor $xor$ls180.v:5012$806 + attribute \src "ls180.v:5128.361-5128.434" + cell $xor $xor$ls180.v:5128$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261889,10 +279923,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5012$806_Y + connect \Y $xor$ls180.v:5128$905_Y end - attribute \src "ls180.v:5012.205-5012.278" - cell $xor $xor$ls180.v:5012$807 + attribute \src "ls180.v:5128.205-5128.278" + cell $xor $xor$ls180.v:5128$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261900,21 +279934,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5012$807_Y + connect \Y $xor$ls180.v:5128$906_Y end - attribute \src "ls180.v:5012.164-5012.279" - cell $xor $xor$ls180.v:5012$808 + attribute \src "ls180.v:5128.164-5128.279" + cell $xor $xor$ls180.v:5128$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:5012$807_Y - connect \Y $xor$ls180.v:5012$808_Y + connect \B $xor$ls180.v:5128$906_Y + connect \Y $xor$ls180.v:5128$907_Y end - attribute \src "ls180.v:5013.361-5013.434" - cell $xor $xor$ls180.v:5013$809 + attribute \src "ls180.v:5129.361-5129.434" + cell $xor $xor$ls180.v:5129$908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261922,10 +279956,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5013$809_Y + connect \Y $xor$ls180.v:5129$908_Y end - attribute \src "ls180.v:5013.205-5013.278" - cell $xor $xor$ls180.v:5013$810 + attribute \src "ls180.v:5129.205-5129.278" + cell $xor $xor$ls180.v:5129$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261933,21 +279967,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5013$810_Y + connect \Y $xor$ls180.v:5129$909_Y end - attribute \src "ls180.v:5013.164-5013.279" - cell $xor $xor$ls180.v:5013$811 + attribute \src "ls180.v:5129.164-5129.279" + cell $xor $xor$ls180.v:5129$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:5013$810_Y - connect \Y $xor$ls180.v:5013$811_Y + connect \B $xor$ls180.v:5129$909_Y + connect \Y $xor$ls180.v:5129$910_Y end - attribute \src "ls180.v:5014.361-5014.434" - cell $xor $xor$ls180.v:5014$812 + attribute \src "ls180.v:5130.361-5130.434" + cell $xor $xor$ls180.v:5130$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261955,10 +279989,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5014$812_Y + connect \Y $xor$ls180.v:5130$911_Y end - attribute \src "ls180.v:5014.205-5014.278" - cell $xor $xor$ls180.v:5014$813 + attribute \src "ls180.v:5130.205-5130.278" + cell $xor $xor$ls180.v:5130$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261966,21 +280000,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5014$813_Y + connect \Y $xor$ls180.v:5130$912_Y end - attribute \src "ls180.v:5014.164-5014.279" - cell $xor $xor$ls180.v:5014$814 + attribute \src "ls180.v:5130.164-5130.279" + cell $xor $xor$ls180.v:5130$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:5014$813_Y - connect \Y $xor$ls180.v:5014$814_Y + connect \B $xor$ls180.v:5130$912_Y + connect \Y $xor$ls180.v:5130$913_Y end - attribute \src "ls180.v:5015.361-5015.434" - cell $xor $xor$ls180.v:5015$815 + attribute \src "ls180.v:5131.361-5131.434" + cell $xor $xor$ls180.v:5131$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261988,10 +280022,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5015$815_Y + connect \Y $xor$ls180.v:5131$914_Y end - attribute \src "ls180.v:5015.205-5015.278" - cell $xor $xor$ls180.v:5015$816 + attribute \src "ls180.v:5131.205-5131.278" + cell $xor $xor$ls180.v:5131$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261999,21 +280033,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5015$816_Y + connect \Y $xor$ls180.v:5131$915_Y end - attribute \src "ls180.v:5015.164-5015.279" - cell $xor $xor$ls180.v:5015$817 + attribute \src "ls180.v:5131.164-5131.279" + cell $xor $xor$ls180.v:5131$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:5015$816_Y - connect \Y $xor$ls180.v:5015$817_Y + connect \B $xor$ls180.v:5131$915_Y + connect \Y $xor$ls180.v:5131$916_Y end - attribute \src "ls180.v:5016.361-5016.434" - cell $xor $xor$ls180.v:5016$818 + attribute \src "ls180.v:5132.361-5132.434" + cell $xor $xor$ls180.v:5132$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262021,10 +280055,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5016$818_Y + connect \Y $xor$ls180.v:5132$917_Y end - attribute \src "ls180.v:5016.205-5016.278" - cell $xor $xor$ls180.v:5016$819 + attribute \src "ls180.v:5132.205-5132.278" + cell $xor $xor$ls180.v:5132$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262032,21 +280066,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5016$819_Y + connect \Y $xor$ls180.v:5132$918_Y end - attribute \src "ls180.v:5016.164-5016.279" - cell $xor $xor$ls180.v:5016$820 + attribute \src "ls180.v:5132.164-5132.279" + cell $xor $xor$ls180.v:5132$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:5016$819_Y - connect \Y $xor$ls180.v:5016$820_Y + connect \B $xor$ls180.v:5132$918_Y + connect \Y $xor$ls180.v:5132$919_Y end - attribute \src "ls180.v:5017.361-5017.434" - cell $xor $xor$ls180.v:5017$821 + attribute \src "ls180.v:5133.361-5133.434" + cell $xor $xor$ls180.v:5133$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262054,10 +280088,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5017$821_Y + connect \Y $xor$ls180.v:5133$920_Y end - attribute \src "ls180.v:5017.205-5017.278" - cell $xor $xor$ls180.v:5017$822 + attribute \src "ls180.v:5133.205-5133.278" + cell $xor $xor$ls180.v:5133$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262065,21 +280099,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5017$822_Y + connect \Y $xor$ls180.v:5133$921_Y end - attribute \src "ls180.v:5017.164-5017.279" - cell $xor $xor$ls180.v:5017$823 + attribute \src "ls180.v:5133.164-5133.279" + cell $xor $xor$ls180.v:5133$922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:5017$822_Y - connect \Y $xor$ls180.v:5017$823_Y + connect \B $xor$ls180.v:5133$921_Y + connect \Y $xor$ls180.v:5133$922_Y end - attribute \src "ls180.v:5018.361-5018.434" - cell $xor $xor$ls180.v:5018$824 + attribute \src "ls180.v:5134.361-5134.434" + cell $xor $xor$ls180.v:5134$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262087,10 +280121,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5018$824_Y + connect \Y $xor$ls180.v:5134$923_Y end - attribute \src "ls180.v:5018.205-5018.278" - cell $xor $xor$ls180.v:5018$825 + attribute \src "ls180.v:5134.205-5134.278" + cell $xor $xor$ls180.v:5134$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262098,21 +280132,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5018$825_Y + connect \Y $xor$ls180.v:5134$924_Y end - attribute \src "ls180.v:5018.164-5018.279" - cell $xor $xor$ls180.v:5018$826 + attribute \src "ls180.v:5134.164-5134.279" + cell $xor $xor$ls180.v:5134$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:5018$825_Y - connect \Y $xor$ls180.v:5018$826_Y + connect \B $xor$ls180.v:5134$924_Y + connect \Y $xor$ls180.v:5134$925_Y end - attribute \src "ls180.v:5019.361-5019.434" - cell $xor $xor$ls180.v:5019$827 + attribute \src "ls180.v:5135.361-5135.434" + cell $xor $xor$ls180.v:5135$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262120,10 +280154,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5019$827_Y + connect \Y $xor$ls180.v:5135$926_Y end - attribute \src "ls180.v:5019.205-5019.278" - cell $xor $xor$ls180.v:5019$828 + attribute \src "ls180.v:5135.205-5135.278" + cell $xor $xor$ls180.v:5135$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262131,21 +280165,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5019$828_Y + connect \Y $xor$ls180.v:5135$927_Y end - attribute \src "ls180.v:5019.164-5019.279" - cell $xor $xor$ls180.v:5019$829 + attribute \src "ls180.v:5135.164-5135.279" + cell $xor $xor$ls180.v:5135$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:5019$828_Y - connect \Y $xor$ls180.v:5019$829_Y + connect \B $xor$ls180.v:5135$927_Y + connect \Y $xor$ls180.v:5135$928_Y end - attribute \src "ls180.v:5020.361-5020.434" - cell $xor $xor$ls180.v:5020$830 + attribute \src "ls180.v:5136.361-5136.434" + cell $xor $xor$ls180.v:5136$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262153,10 +280187,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5020$830_Y + connect \Y $xor$ls180.v:5136$929_Y end - attribute \src "ls180.v:5020.205-5020.278" - cell $xor $xor$ls180.v:5020$831 + attribute \src "ls180.v:5136.205-5136.278" + cell $xor $xor$ls180.v:5136$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262164,21 +280198,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5020$831_Y + connect \Y $xor$ls180.v:5136$930_Y end - attribute \src "ls180.v:5020.164-5020.279" - cell $xor $xor$ls180.v:5020$832 + attribute \src "ls180.v:5136.164-5136.279" + cell $xor $xor$ls180.v:5136$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:5020$831_Y - connect \Y $xor$ls180.v:5020$832_Y + connect \B $xor$ls180.v:5136$930_Y + connect \Y $xor$ls180.v:5136$931_Y end - attribute \src "ls180.v:5021.361-5021.434" - cell $xor $xor$ls180.v:5021$833 + attribute \src "ls180.v:5137.361-5137.434" + cell $xor $xor$ls180.v:5137$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262186,10 +280220,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5021$833_Y + connect \Y $xor$ls180.v:5137$932_Y end - attribute \src "ls180.v:5021.205-5021.278" - cell $xor $xor$ls180.v:5021$834 + attribute \src "ls180.v:5137.205-5137.278" + cell $xor $xor$ls180.v:5137$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262197,21 +280231,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5021$834_Y + connect \Y $xor$ls180.v:5137$933_Y end - attribute \src "ls180.v:5021.164-5021.279" - cell $xor $xor$ls180.v:5021$835 + attribute \src "ls180.v:5137.164-5137.279" + cell $xor $xor$ls180.v:5137$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:5021$834_Y - connect \Y $xor$ls180.v:5021$835_Y + connect \B $xor$ls180.v:5137$933_Y + connect \Y $xor$ls180.v:5137$934_Y end - attribute \src "ls180.v:5022.361-5022.434" - cell $xor $xor$ls180.v:5022$836 + attribute \src "ls180.v:5138.361-5138.434" + cell $xor $xor$ls180.v:5138$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262219,10 +280253,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5022$836_Y + connect \Y $xor$ls180.v:5138$935_Y end - attribute \src "ls180.v:5022.205-5022.278" - cell $xor $xor$ls180.v:5022$837 + attribute \src "ls180.v:5138.205-5138.278" + cell $xor $xor$ls180.v:5138$936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262230,21 +280264,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5022$837_Y + connect \Y $xor$ls180.v:5138$936_Y end - attribute \src "ls180.v:5022.164-5022.279" - cell $xor $xor$ls180.v:5022$838 + attribute \src "ls180.v:5138.164-5138.279" + cell $xor $xor$ls180.v:5138$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:5022$837_Y - connect \Y $xor$ls180.v:5022$838_Y + connect \B $xor$ls180.v:5138$936_Y + connect \Y $xor$ls180.v:5138$937_Y end - attribute \src "ls180.v:5023.361-5023.434" - cell $xor $xor$ls180.v:5023$839 + attribute \src "ls180.v:5139.361-5139.434" + cell $xor $xor$ls180.v:5139$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262252,10 +280286,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5023$839_Y + connect \Y $xor$ls180.v:5139$938_Y end - attribute \src "ls180.v:5023.205-5023.278" - cell $xor $xor$ls180.v:5023$840 + attribute \src "ls180.v:5139.205-5139.278" + cell $xor $xor$ls180.v:5139$939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262263,21 +280297,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5023$840_Y + connect \Y $xor$ls180.v:5139$939_Y end - attribute \src "ls180.v:5023.164-5023.279" - cell $xor $xor$ls180.v:5023$841 + attribute \src "ls180.v:5139.164-5139.279" + cell $xor $xor$ls180.v:5139$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:5023$840_Y - connect \Y $xor$ls180.v:5023$841_Y + connect \B $xor$ls180.v:5139$939_Y + connect \Y $xor$ls180.v:5139$940_Y end - attribute \src "ls180.v:5024.361-5024.434" - cell $xor $xor$ls180.v:5024$842 + attribute \src "ls180.v:5140.361-5140.434" + cell $xor $xor$ls180.v:5140$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262285,10 +280319,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5024$842_Y + connect \Y $xor$ls180.v:5140$941_Y end - attribute \src "ls180.v:5024.205-5024.278" - cell $xor $xor$ls180.v:5024$843 + attribute \src "ls180.v:5140.205-5140.278" + cell $xor $xor$ls180.v:5140$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262296,21 +280330,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5024$843_Y + connect \Y $xor$ls180.v:5140$942_Y end - attribute \src "ls180.v:5024.164-5024.279" - cell $xor $xor$ls180.v:5024$844 + attribute \src "ls180.v:5140.164-5140.279" + cell $xor $xor$ls180.v:5140$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:5024$843_Y - connect \Y $xor$ls180.v:5024$844_Y + connect \B $xor$ls180.v:5140$942_Y + connect \Y $xor$ls180.v:5140$943_Y end - attribute \src "ls180.v:5025.361-5025.434" - cell $xor $xor$ls180.v:5025$845 + attribute \src "ls180.v:5141.361-5141.434" + cell $xor $xor$ls180.v:5141$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262318,10 +280352,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5025$845_Y + connect \Y $xor$ls180.v:5141$944_Y end - attribute \src "ls180.v:5025.205-5025.278" - cell $xor $xor$ls180.v:5025$846 + attribute \src "ls180.v:5141.205-5141.278" + cell $xor $xor$ls180.v:5141$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262329,21 +280363,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5025$846_Y + connect \Y $xor$ls180.v:5141$945_Y end - attribute \src "ls180.v:5025.164-5025.279" - cell $xor $xor$ls180.v:5025$847 + attribute \src "ls180.v:5141.164-5141.279" + cell $xor $xor$ls180.v:5141$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:5025$846_Y - connect \Y $xor$ls180.v:5025$847_Y + connect \B $xor$ls180.v:5141$945_Y + connect \Y $xor$ls180.v:5141$946_Y end - attribute \src "ls180.v:5026.361-5026.434" - cell $xor $xor$ls180.v:5026$848 + attribute \src "ls180.v:5142.361-5142.434" + cell $xor $xor$ls180.v:5142$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262351,10 +280385,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5026$848_Y + connect \Y $xor$ls180.v:5142$947_Y end - attribute \src "ls180.v:5026.205-5026.278" - cell $xor $xor$ls180.v:5026$849 + attribute \src "ls180.v:5142.205-5142.278" + cell $xor $xor$ls180.v:5142$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262362,21 +280396,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5026$849_Y + connect \Y $xor$ls180.v:5142$948_Y end - attribute \src "ls180.v:5026.164-5026.279" - cell $xor $xor$ls180.v:5026$850 + attribute \src "ls180.v:5142.164-5142.279" + cell $xor $xor$ls180.v:5142$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:5026$849_Y - connect \Y $xor$ls180.v:5026$850_Y + connect \B $xor$ls180.v:5142$948_Y + connect \Y $xor$ls180.v:5142$949_Y end - attribute \src "ls180.v:5027.360-5027.432" - cell $xor $xor$ls180.v:5027$851 + attribute \src "ls180.v:5143.360-5143.432" + cell $xor $xor$ls180.v:5143$950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262384,10 +280418,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5027$851_Y + connect \Y $xor$ls180.v:5143$950_Y end - attribute \src "ls180.v:5027.205-5027.277" - cell $xor $xor$ls180.v:5027$852 + attribute \src "ls180.v:5143.205-5143.277" + cell $xor $xor$ls180.v:5143$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262395,21 +280429,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5027$852_Y + connect \Y $xor$ls180.v:5143$951_Y end - attribute \src "ls180.v:5027.164-5027.278" - cell $xor $xor$ls180.v:5027$853 + attribute \src "ls180.v:5143.164-5143.278" + cell $xor $xor$ls180.v:5143$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:5027$852_Y - connect \Y $xor$ls180.v:5027$853_Y + connect \B $xor$ls180.v:5143$951_Y + connect \Y $xor$ls180.v:5143$952_Y end - attribute \src "ls180.v:5028.360-5028.432" - cell $xor $xor$ls180.v:5028$854 + attribute \src "ls180.v:5144.360-5144.432" + cell $xor $xor$ls180.v:5144$953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262417,10 +280451,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5028$854_Y + connect \Y $xor$ls180.v:5144$953_Y end - attribute \src "ls180.v:5028.205-5028.277" - cell $xor $xor$ls180.v:5028$855 + attribute \src "ls180.v:5144.205-5144.277" + cell $xor $xor$ls180.v:5144$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262428,21 +280462,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5028$855_Y + connect \Y $xor$ls180.v:5144$954_Y end - attribute \src "ls180.v:5028.164-5028.278" - cell $xor $xor$ls180.v:5028$856 + attribute \src "ls180.v:5144.164-5144.278" + cell $xor $xor$ls180.v:5144$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:5028$855_Y - connect \Y $xor$ls180.v:5028$856_Y + connect \B $xor$ls180.v:5144$954_Y + connect \Y $xor$ls180.v:5144$955_Y end - attribute \src "ls180.v:5029.360-5029.432" - cell $xor $xor$ls180.v:5029$857 + attribute \src "ls180.v:5145.360-5145.432" + cell $xor $xor$ls180.v:5145$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262450,10 +280484,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5029$857_Y + connect \Y $xor$ls180.v:5145$956_Y end - attribute \src "ls180.v:5029.205-5029.277" - cell $xor $xor$ls180.v:5029$858 + attribute \src "ls180.v:5145.205-5145.277" + cell $xor $xor$ls180.v:5145$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262461,21 +280495,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5029$858_Y + connect \Y $xor$ls180.v:5145$957_Y end - attribute \src "ls180.v:5029.164-5029.278" - cell $xor $xor$ls180.v:5029$859 + attribute \src "ls180.v:5145.164-5145.278" + cell $xor $xor$ls180.v:5145$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:5029$858_Y - connect \Y $xor$ls180.v:5029$859_Y + connect \B $xor$ls180.v:5145$957_Y + connect \Y $xor$ls180.v:5145$958_Y end - attribute \src "ls180.v:5030.360-5030.432" - cell $xor $xor$ls180.v:5030$860 + attribute \src "ls180.v:5146.360-5146.432" + cell $xor $xor$ls180.v:5146$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262483,10 +280517,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5030$860_Y + connect \Y $xor$ls180.v:5146$959_Y end - attribute \src "ls180.v:5030.205-5030.277" - cell $xor $xor$ls180.v:5030$861 + attribute \src "ls180.v:5146.205-5146.277" + cell $xor $xor$ls180.v:5146$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262494,21 +280528,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5030$861_Y + connect \Y $xor$ls180.v:5146$960_Y end - attribute \src "ls180.v:5030.164-5030.278" - cell $xor $xor$ls180.v:5030$862 + attribute \src "ls180.v:5146.164-5146.278" + cell $xor $xor$ls180.v:5146$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:5030$861_Y - connect \Y $xor$ls180.v:5030$862_Y + connect \B $xor$ls180.v:5146$960_Y + connect \Y $xor$ls180.v:5146$961_Y end - attribute \src "ls180.v:5031.360-5031.432" - cell $xor $xor$ls180.v:5031$863 + attribute \src "ls180.v:5147.360-5147.432" + cell $xor $xor$ls180.v:5147$962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262516,10 +280550,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5031$863_Y + connect \Y $xor$ls180.v:5147$962_Y end - attribute \src "ls180.v:5031.205-5031.277" - cell $xor $xor$ls180.v:5031$864 + attribute \src "ls180.v:5147.205-5147.277" + cell $xor $xor$ls180.v:5147$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262527,21 +280561,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5031$864_Y + connect \Y $xor$ls180.v:5147$963_Y end - attribute \src "ls180.v:5031.164-5031.278" - cell $xor $xor$ls180.v:5031$865 + attribute \src "ls180.v:5147.164-5147.278" + cell $xor $xor$ls180.v:5147$964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:5031$864_Y - connect \Y $xor$ls180.v:5031$865_Y + connect \B $xor$ls180.v:5147$963_Y + connect \Y $xor$ls180.v:5147$964_Y end - attribute \src "ls180.v:5032.360-5032.432" - cell $xor $xor$ls180.v:5032$866 + attribute \src "ls180.v:5148.360-5148.432" + cell $xor $xor$ls180.v:5148$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262549,10 +280583,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5032$866_Y + connect \Y $xor$ls180.v:5148$965_Y end - attribute \src "ls180.v:5032.205-5032.277" - cell $xor $xor$ls180.v:5032$867 + attribute \src "ls180.v:5148.205-5148.277" + cell $xor $xor$ls180.v:5148$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262560,21 +280594,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5032$867_Y + connect \Y $xor$ls180.v:5148$966_Y end - attribute \src "ls180.v:5032.164-5032.278" - cell $xor $xor$ls180.v:5032$868 + attribute \src "ls180.v:5148.164-5148.278" + cell $xor $xor$ls180.v:5148$967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:5032$867_Y - connect \Y $xor$ls180.v:5032$868_Y + connect \B $xor$ls180.v:5148$966_Y + connect \Y $xor$ls180.v:5148$967_Y end - attribute \src "ls180.v:5033.360-5033.432" - cell $xor $xor$ls180.v:5033$869 + attribute \src "ls180.v:5149.360-5149.432" + cell $xor $xor$ls180.v:5149$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262582,10 +280616,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5033$869_Y + connect \Y $xor$ls180.v:5149$968_Y end - attribute \src "ls180.v:5033.205-5033.277" - cell $xor $xor$ls180.v:5033$870 + attribute \src "ls180.v:5149.205-5149.277" + cell $xor $xor$ls180.v:5149$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262593,21 +280627,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5033$870_Y + connect \Y $xor$ls180.v:5149$969_Y end - attribute \src "ls180.v:5033.164-5033.278" - cell $xor $xor$ls180.v:5033$871 + attribute \src "ls180.v:5149.164-5149.278" + cell $xor $xor$ls180.v:5149$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:5033$870_Y - connect \Y $xor$ls180.v:5033$871_Y + connect \B $xor$ls180.v:5149$969_Y + connect \Y $xor$ls180.v:5149$970_Y end - attribute \src "ls180.v:5034.360-5034.432" - cell $xor $xor$ls180.v:5034$872 + attribute \src "ls180.v:5150.360-5150.432" + cell $xor $xor$ls180.v:5150$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262615,10 +280649,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5034$872_Y + connect \Y $xor$ls180.v:5150$971_Y end - attribute \src "ls180.v:5034.205-5034.277" - cell $xor $xor$ls180.v:5034$873 + attribute \src "ls180.v:5150.205-5150.277" + cell $xor $xor$ls180.v:5150$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262626,21 +280660,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5034$873_Y + connect \Y $xor$ls180.v:5150$972_Y end - attribute \src "ls180.v:5034.164-5034.278" - cell $xor $xor$ls180.v:5034$874 + attribute \src "ls180.v:5150.164-5150.278" + cell $xor $xor$ls180.v:5150$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:5034$873_Y - connect \Y $xor$ls180.v:5034$874_Y + connect \B $xor$ls180.v:5150$972_Y + connect \Y $xor$ls180.v:5150$973_Y end - attribute \src "ls180.v:5035.360-5035.432" - cell $xor $xor$ls180.v:5035$875 + attribute \src "ls180.v:5151.360-5151.432" + cell $xor $xor$ls180.v:5151$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262648,10 +280682,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5035$875_Y + connect \Y $xor$ls180.v:5151$974_Y end - attribute \src "ls180.v:5035.205-5035.277" - cell $xor $xor$ls180.v:5035$876 + attribute \src "ls180.v:5151.205-5151.277" + cell $xor $xor$ls180.v:5151$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262659,21 +280693,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5035$876_Y + connect \Y $xor$ls180.v:5151$975_Y end - attribute \src "ls180.v:5035.164-5035.278" - cell $xor $xor$ls180.v:5035$877 + attribute \src "ls180.v:5151.164-5151.278" + cell $xor $xor$ls180.v:5151$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:5035$876_Y - connect \Y $xor$ls180.v:5035$877_Y + connect \B $xor$ls180.v:5151$975_Y + connect \Y $xor$ls180.v:5151$976_Y end - attribute \src "ls180.v:5036.360-5036.432" - cell $xor $xor$ls180.v:5036$878 + attribute \src "ls180.v:5152.360-5152.432" + cell $xor $xor$ls180.v:5152$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262681,10 +280715,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5036$878_Y + connect \Y $xor$ls180.v:5152$977_Y end - attribute \src "ls180.v:5036.205-5036.277" - cell $xor $xor$ls180.v:5036$879 + attribute \src "ls180.v:5152.205-5152.277" + cell $xor $xor$ls180.v:5152$978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262692,21 +280726,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5036$879_Y + connect \Y $xor$ls180.v:5152$978_Y end - attribute \src "ls180.v:5036.164-5036.278" - cell $xor $xor$ls180.v:5036$880 + attribute \src "ls180.v:5152.164-5152.278" + cell $xor $xor$ls180.v:5152$979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:5036$879_Y - connect \Y $xor$ls180.v:5036$880_Y + connect \B $xor$ls180.v:5152$978_Y + connect \Y $xor$ls180.v:5152$979_Y end - attribute \src "ls180.v:5057.899-5057.983" - cell $xor $xor$ls180.v:5057$894 + attribute \src "ls180.v:5173.899-5173.983" + cell $xor $xor$ls180.v:5173$993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262714,10 +280748,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5057$894_Y + connect \Y $xor$ls180.v:5173$993_Y end - attribute \src "ls180.v:5057.634-5057.718" - cell $xor $xor$ls180.v:5057$895 + attribute \src "ls180.v:5173.634-5173.718" + cell $xor $xor$ls180.v:5173$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262725,21 +280759,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5057$895_Y + connect \Y $xor$ls180.v:5173$994_Y end - attribute \src "ls180.v:5057.588-5057.719" - cell $xor $xor$ls180.v:5057$896 + attribute \src "ls180.v:5173.588-5173.719" + cell $xor $xor$ls180.v:5173$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5057$895_Y - connect \Y $xor$ls180.v:5057$896_Y + connect \B $xor$ls180.v:5173$994_Y + connect \Y $xor$ls180.v:5173$995_Y end - attribute \src "ls180.v:5057.234-5057.318" - cell $xor $xor$ls180.v:5057$897 + attribute \src "ls180.v:5173.234-5173.318" + cell $xor $xor$ls180.v:5173$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262747,32 +280781,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5057$897_Y + connect \Y $xor$ls180.v:5173$996_Y end - attribute \src "ls180.v:5057.187-5057.319" - cell $xor $xor$ls180.v:5057$898 + attribute \src "ls180.v:5173.187-5173.319" + cell $xor $xor$ls180.v:5173$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5057$897_Y - connect \Y $xor$ls180.v:5057$898_Y + connect \B $xor$ls180.v:5173$996_Y + connect \Y $xor$ls180.v:5173$997_Y end - attribute \src "ls180.v:5058.899-5058.983" - cell $xor $xor$ls180.v:5058$899 + attribute \src "ls180.v:5174.588-5174.719" + cell $xor $xor$ls180.v:5174$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5058$899_Y + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5174$999_Y + connect \Y $xor$ls180.v:5174$1000_Y end - attribute \src "ls180.v:5058.634-5058.718" - cell $xor $xor$ls180.v:5058$900 + attribute \src "ls180.v:5174.234-5174.318" + cell $xor $xor$ls180.v:5174$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262780,21 +280814,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5058$900_Y + connect \Y $xor$ls180.v:5174$1001_Y end - attribute \src "ls180.v:5058.588-5058.719" - cell $xor $xor$ls180.v:5058$901 + attribute \src "ls180.v:5174.187-5174.319" + cell $xor $xor$ls180.v:5174$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5058$900_Y - connect \Y $xor$ls180.v:5058$901_Y + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5174$1001_Y + connect \Y $xor$ls180.v:5174$1002_Y end - attribute \src "ls180.v:5058.234-5058.318" - cell $xor $xor$ls180.v:5058$902 + attribute \src "ls180.v:5174.899-5174.983" + cell $xor $xor$ls180.v:5174$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262802,21 +280836,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5058$902_Y + connect \Y $xor$ls180.v:5174$998_Y end - attribute \src "ls180.v:5058.187-5058.319" - cell $xor $xor$ls180.v:5058$903 + attribute \src "ls180.v:5174.634-5174.718" + cell $xor $xor$ls180.v:5174$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5058$902_Y - connect \Y $xor$ls180.v:5058$903_Y + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5174$999_Y end - attribute \src "ls180.v:5067.899-5067.983" - cell $xor $xor$ls180.v:5067$905 + attribute \src "ls180.v:5183.899-5183.983" + cell $xor $xor$ls180.v:5183$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262824,10 +280858,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5067$905_Y + connect \Y $xor$ls180.v:5183$1004_Y end - attribute \src "ls180.v:5067.634-5067.718" - cell $xor $xor$ls180.v:5067$906 + attribute \src "ls180.v:5183.634-5183.718" + cell $xor $xor$ls180.v:5183$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262835,21 +280869,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5067$906_Y + connect \Y $xor$ls180.v:5183$1005_Y end - attribute \src "ls180.v:5067.588-5067.719" - cell $xor $xor$ls180.v:5067$907 + attribute \src "ls180.v:5183.588-5183.719" + cell $xor $xor$ls180.v:5183$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5067$906_Y - connect \Y $xor$ls180.v:5067$907_Y + connect \B $xor$ls180.v:5183$1005_Y + connect \Y $xor$ls180.v:5183$1006_Y end - attribute \src "ls180.v:5067.234-5067.318" - cell $xor $xor$ls180.v:5067$908 + attribute \src "ls180.v:5183.234-5183.318" + cell $xor $xor$ls180.v:5183$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262857,21 +280891,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5067$908_Y + connect \Y $xor$ls180.v:5183$1007_Y end - attribute \src "ls180.v:5067.187-5067.319" - cell $xor $xor$ls180.v:5067$909 + attribute \src "ls180.v:5183.187-5183.319" + cell $xor $xor$ls180.v:5183$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5067$908_Y - connect \Y $xor$ls180.v:5067$909_Y + connect \B $xor$ls180.v:5183$1007_Y + connect \Y $xor$ls180.v:5183$1008_Y end - attribute \src "ls180.v:5068.899-5068.983" - cell $xor $xor$ls180.v:5068$910 + attribute \src "ls180.v:5184.899-5184.983" + cell $xor $xor$ls180.v:5184$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262879,10 +280913,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5068$910_Y + connect \Y $xor$ls180.v:5184$1009_Y end - attribute \src "ls180.v:5068.634-5068.718" - cell $xor $xor$ls180.v:5068$911 + attribute \src "ls180.v:5184.634-5184.718" + cell $xor $xor$ls180.v:5184$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262890,21 +280924,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5068$911_Y + connect \Y $xor$ls180.v:5184$1010_Y end - attribute \src "ls180.v:5068.588-5068.719" - cell $xor $xor$ls180.v:5068$912 + attribute \src "ls180.v:5184.588-5184.719" + cell $xor $xor$ls180.v:5184$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5068$911_Y - connect \Y $xor$ls180.v:5068$912_Y + connect \B $xor$ls180.v:5184$1010_Y + connect \Y $xor$ls180.v:5184$1011_Y end - attribute \src "ls180.v:5068.234-5068.318" - cell $xor $xor$ls180.v:5068$913 + attribute \src "ls180.v:5184.234-5184.318" + cell $xor $xor$ls180.v:5184$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262912,21 +280946,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5068$913_Y + connect \Y $xor$ls180.v:5184$1012_Y end - attribute \src "ls180.v:5068.187-5068.319" - cell $xor $xor$ls180.v:5068$914 + attribute \src "ls180.v:5184.187-5184.319" + cell $xor $xor$ls180.v:5184$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5068$913_Y - connect \Y $xor$ls180.v:5068$914_Y + connect \B $xor$ls180.v:5184$1012_Y + connect \Y $xor$ls180.v:5184$1013_Y end - attribute \src "ls180.v:5077.899-5077.983" - cell $xor $xor$ls180.v:5077$916 + attribute \src "ls180.v:5193.899-5193.983" + cell $xor $xor$ls180.v:5193$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262934,10 +280968,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5077$916_Y + connect \Y $xor$ls180.v:5193$1015_Y end - attribute \src "ls180.v:5077.634-5077.718" - cell $xor $xor$ls180.v:5077$917 + attribute \src "ls180.v:5193.634-5193.718" + cell $xor $xor$ls180.v:5193$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262945,21 +280979,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5077$917_Y + connect \Y $xor$ls180.v:5193$1016_Y end - attribute \src "ls180.v:5077.588-5077.719" - cell $xor $xor$ls180.v:5077$918 + attribute \src "ls180.v:5193.588-5193.719" + cell $xor $xor$ls180.v:5193$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5077$917_Y - connect \Y $xor$ls180.v:5077$918_Y + connect \B $xor$ls180.v:5193$1016_Y + connect \Y $xor$ls180.v:5193$1017_Y end - attribute \src "ls180.v:5077.234-5077.318" - cell $xor $xor$ls180.v:5077$919 + attribute \src "ls180.v:5193.234-5193.318" + cell $xor $xor$ls180.v:5193$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262967,21 +281001,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5077$919_Y + connect \Y $xor$ls180.v:5193$1018_Y end - attribute \src "ls180.v:5077.187-5077.319" - cell $xor $xor$ls180.v:5077$920 + attribute \src "ls180.v:5193.187-5193.319" + cell $xor $xor$ls180.v:5193$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5077$919_Y - connect \Y $xor$ls180.v:5077$920_Y + connect \B $xor$ls180.v:5193$1018_Y + connect \Y $xor$ls180.v:5193$1019_Y end - attribute \src "ls180.v:5078.899-5078.983" - cell $xor $xor$ls180.v:5078$921 + attribute \src "ls180.v:5194.899-5194.983" + cell $xor $xor$ls180.v:5194$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262989,10 +281023,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5078$921_Y + connect \Y $xor$ls180.v:5194$1020_Y end - attribute \src "ls180.v:5078.634-5078.718" - cell $xor $xor$ls180.v:5078$922 + attribute \src "ls180.v:5194.634-5194.718" + cell $xor $xor$ls180.v:5194$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263000,21 +281034,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5078$922_Y + connect \Y $xor$ls180.v:5194$1021_Y end - attribute \src "ls180.v:5078.588-5078.719" - cell $xor $xor$ls180.v:5078$923 + attribute \src "ls180.v:5194.588-5194.719" + cell $xor $xor$ls180.v:5194$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5078$922_Y - connect \Y $xor$ls180.v:5078$923_Y + connect \B $xor$ls180.v:5194$1021_Y + connect \Y $xor$ls180.v:5194$1022_Y end - attribute \src "ls180.v:5078.234-5078.318" - cell $xor $xor$ls180.v:5078$924 + attribute \src "ls180.v:5194.234-5194.318" + cell $xor $xor$ls180.v:5194$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263022,21 +281056,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5078$924_Y + connect \Y $xor$ls180.v:5194$1023_Y end - attribute \src "ls180.v:5078.187-5078.319" - cell $xor $xor$ls180.v:5078$925 + attribute \src "ls180.v:5194.187-5194.319" + cell $xor $xor$ls180.v:5194$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5078$924_Y - connect \Y $xor$ls180.v:5078$925_Y + connect \B $xor$ls180.v:5194$1023_Y + connect \Y $xor$ls180.v:5194$1024_Y end - attribute \src "ls180.v:5087.899-5087.983" - cell $xor $xor$ls180.v:5087$927 + attribute \src "ls180.v:5203.899-5203.983" + cell $xor $xor$ls180.v:5203$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263044,10 +281078,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5087$927_Y + connect \Y $xor$ls180.v:5203$1026_Y end - attribute \src "ls180.v:5087.634-5087.718" - cell $xor $xor$ls180.v:5087$928 + attribute \src "ls180.v:5203.634-5203.718" + cell $xor $xor$ls180.v:5203$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263055,21 +281089,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5087$928_Y + connect \Y $xor$ls180.v:5203$1027_Y end - attribute \src "ls180.v:5087.588-5087.719" - cell $xor $xor$ls180.v:5087$929 + attribute \src "ls180.v:5203.588-5203.719" + cell $xor $xor$ls180.v:5203$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5087$928_Y - connect \Y $xor$ls180.v:5087$929_Y + connect \B $xor$ls180.v:5203$1027_Y + connect \Y $xor$ls180.v:5203$1028_Y end - attribute \src "ls180.v:5087.234-5087.318" - cell $xor $xor$ls180.v:5087$930 + attribute \src "ls180.v:5203.234-5203.318" + cell $xor $xor$ls180.v:5203$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263077,21 +281111,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5087$930_Y + connect \Y $xor$ls180.v:5203$1029_Y end - attribute \src "ls180.v:5087.187-5087.319" - cell $xor $xor$ls180.v:5087$931 + attribute \src "ls180.v:5203.187-5203.319" + cell $xor $xor$ls180.v:5203$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5087$930_Y - connect \Y $xor$ls180.v:5087$931_Y + connect \B $xor$ls180.v:5203$1029_Y + connect \Y $xor$ls180.v:5203$1030_Y end - attribute \src "ls180.v:5088.899-5088.983" - cell $xor $xor$ls180.v:5088$932 + attribute \src "ls180.v:5204.899-5204.983" + cell $xor $xor$ls180.v:5204$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263099,10 +281133,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5088$932_Y + connect \Y $xor$ls180.v:5204$1031_Y end - attribute \src "ls180.v:5088.634-5088.718" - cell $xor $xor$ls180.v:5088$933 + attribute \src "ls180.v:5204.634-5204.718" + cell $xor $xor$ls180.v:5204$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263110,21 +281144,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5088$933_Y + connect \Y $xor$ls180.v:5204$1032_Y end - attribute \src "ls180.v:5088.588-5088.719" - cell $xor $xor$ls180.v:5088$934 + attribute \src "ls180.v:5204.588-5204.719" + cell $xor $xor$ls180.v:5204$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5088$933_Y - connect \Y $xor$ls180.v:5088$934_Y + connect \B $xor$ls180.v:5204$1032_Y + connect \Y $xor$ls180.v:5204$1033_Y end - attribute \src "ls180.v:5088.234-5088.318" - cell $xor $xor$ls180.v:5088$935 + attribute \src "ls180.v:5204.234-5204.318" + cell $xor $xor$ls180.v:5204$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263132,21 +281166,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5088$935_Y + connect \Y $xor$ls180.v:5204$1034_Y end - attribute \src "ls180.v:5088.187-5088.319" - cell $xor $xor$ls180.v:5088$936 + attribute \src "ls180.v:5204.187-5204.319" + cell $xor $xor$ls180.v:5204$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5088$935_Y - connect \Y $xor$ls180.v:5088$936_Y + connect \B $xor$ls180.v:5204$1034_Y + connect \Y $xor$ls180.v:5204$1035_Y end - attribute \src "ls180.v:5239.879-5239.961" - cell $xor $xor$ls180.v:5239$969 + attribute \src "ls180.v:5355.879-5355.961" + cell $xor $xor$ls180.v:5355$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263154,10 +281188,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5239$969_Y + connect \Y $xor$ls180.v:5355$1068_Y end - attribute \src "ls180.v:5239.620-5239.702" - cell $xor $xor$ls180.v:5239$970 + attribute \src "ls180.v:5355.620-5355.702" + cell $xor $xor$ls180.v:5355$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263165,21 +281199,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5239$970_Y + connect \Y $xor$ls180.v:5355$1069_Y end - attribute \src "ls180.v:5239.575-5239.703" - cell $xor $xor$ls180.v:5239$971 + attribute \src "ls180.v:5355.575-5355.703" + cell $xor $xor$ls180.v:5355$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5239$970_Y - connect \Y $xor$ls180.v:5239$971_Y + connect \B $xor$ls180.v:5355$1069_Y + connect \Y $xor$ls180.v:5355$1070_Y end - attribute \src "ls180.v:5239.229-5239.311" - cell $xor $xor$ls180.v:5239$972 + attribute \src "ls180.v:5355.229-5355.311" + cell $xor $xor$ls180.v:5355$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263187,21 +281221,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5239$972_Y + connect \Y $xor$ls180.v:5355$1071_Y end - attribute \src "ls180.v:5239.183-5239.312" - cell $xor $xor$ls180.v:5239$973 + attribute \src "ls180.v:5355.183-5355.312" + cell $xor $xor$ls180.v:5355$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5239$972_Y - connect \Y $xor$ls180.v:5239$973_Y + connect \B $xor$ls180.v:5355$1071_Y + connect \Y $xor$ls180.v:5355$1072_Y end - attribute \src "ls180.v:5240.879-5240.961" - cell $xor $xor$ls180.v:5240$974 + attribute \src "ls180.v:5356.879-5356.961" + cell $xor $xor$ls180.v:5356$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263209,10 +281243,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5240$974_Y + connect \Y $xor$ls180.v:5356$1073_Y end - attribute \src "ls180.v:5240.620-5240.702" - cell $xor $xor$ls180.v:5240$975 + attribute \src "ls180.v:5356.620-5356.702" + cell $xor $xor$ls180.v:5356$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263220,21 +281254,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5240$975_Y + connect \Y $xor$ls180.v:5356$1074_Y end - attribute \src "ls180.v:5240.575-5240.703" - cell $xor $xor$ls180.v:5240$976 + attribute \src "ls180.v:5356.575-5356.703" + cell $xor $xor$ls180.v:5356$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5240$975_Y - connect \Y $xor$ls180.v:5240$976_Y + connect \B $xor$ls180.v:5356$1074_Y + connect \Y $xor$ls180.v:5356$1075_Y end - attribute \src "ls180.v:5240.229-5240.311" - cell $xor $xor$ls180.v:5240$977 + attribute \src "ls180.v:5356.229-5356.311" + cell $xor $xor$ls180.v:5356$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263242,21 +281276,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5240$977_Y + connect \Y $xor$ls180.v:5356$1076_Y end - attribute \src "ls180.v:5240.183-5240.312" - cell $xor $xor$ls180.v:5240$978 + attribute \src "ls180.v:5356.183-5356.312" + cell $xor $xor$ls180.v:5356$1077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5240$977_Y - connect \Y $xor$ls180.v:5240$978_Y + connect \B $xor$ls180.v:5356$1076_Y + connect \Y $xor$ls180.v:5356$1077_Y end - attribute \src "ls180.v:5249.879-5249.961" - cell $xor $xor$ls180.v:5249$980 + attribute \src "ls180.v:5365.879-5365.961" + cell $xor $xor$ls180.v:5365$1079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263264,10 +281298,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5249$980_Y + connect \Y $xor$ls180.v:5365$1079_Y end - attribute \src "ls180.v:5249.620-5249.702" - cell $xor $xor$ls180.v:5249$981 + attribute \src "ls180.v:5365.620-5365.702" + cell $xor $xor$ls180.v:5365$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263275,21 +281309,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5249$981_Y + connect \Y $xor$ls180.v:5365$1080_Y end - attribute \src "ls180.v:5249.575-5249.703" - cell $xor $xor$ls180.v:5249$982 + attribute \src "ls180.v:5365.575-5365.703" + cell $xor $xor$ls180.v:5365$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5249$981_Y - connect \Y $xor$ls180.v:5249$982_Y + connect \B $xor$ls180.v:5365$1080_Y + connect \Y $xor$ls180.v:5365$1081_Y end - attribute \src "ls180.v:5249.229-5249.311" - cell $xor $xor$ls180.v:5249$983 + attribute \src "ls180.v:5365.229-5365.311" + cell $xor $xor$ls180.v:5365$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263297,21 +281331,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5249$983_Y + connect \Y $xor$ls180.v:5365$1082_Y end - attribute \src "ls180.v:5249.183-5249.312" - cell $xor $xor$ls180.v:5249$984 + attribute \src "ls180.v:5365.183-5365.312" + cell $xor $xor$ls180.v:5365$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5249$983_Y - connect \Y $xor$ls180.v:5249$984_Y + connect \B $xor$ls180.v:5365$1082_Y + connect \Y $xor$ls180.v:5365$1083_Y end - attribute \src "ls180.v:5250.879-5250.961" - cell $xor $xor$ls180.v:5250$985 + attribute \src "ls180.v:5366.879-5366.961" + cell $xor $xor$ls180.v:5366$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263319,10 +281353,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5250$985_Y + connect \Y $xor$ls180.v:5366$1084_Y end - attribute \src "ls180.v:5250.620-5250.702" - cell $xor $xor$ls180.v:5250$986 + attribute \src "ls180.v:5366.620-5366.702" + cell $xor $xor$ls180.v:5366$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263330,21 +281364,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5250$986_Y + connect \Y $xor$ls180.v:5366$1085_Y end - attribute \src "ls180.v:5250.575-5250.703" - cell $xor $xor$ls180.v:5250$987 + attribute \src "ls180.v:5366.575-5366.703" + cell $xor $xor$ls180.v:5366$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5250$986_Y - connect \Y $xor$ls180.v:5250$987_Y + connect \B $xor$ls180.v:5366$1085_Y + connect \Y $xor$ls180.v:5366$1086_Y end - attribute \src "ls180.v:5250.229-5250.311" - cell $xor $xor$ls180.v:5250$988 + attribute \src "ls180.v:5366.229-5366.311" + cell $xor $xor$ls180.v:5366$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263352,21 +281386,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5250$988_Y + connect \Y $xor$ls180.v:5366$1087_Y end - attribute \src "ls180.v:5250.183-5250.312" - cell $xor $xor$ls180.v:5250$989 + attribute \src "ls180.v:5366.183-5366.312" + cell $xor $xor$ls180.v:5366$1088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5250$988_Y - connect \Y $xor$ls180.v:5250$989_Y + connect \B $xor$ls180.v:5366$1087_Y + connect \Y $xor$ls180.v:5366$1088_Y end - attribute \src "ls180.v:5259.879-5259.961" - cell $xor $xor$ls180.v:5259$991 + attribute \src "ls180.v:5375.879-5375.961" + cell $xor $xor$ls180.v:5375$1090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263374,10 +281408,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5259$991_Y + connect \Y $xor$ls180.v:5375$1090_Y end - attribute \src "ls180.v:5259.620-5259.702" - cell $xor $xor$ls180.v:5259$992 + attribute \src "ls180.v:5375.620-5375.702" + cell $xor $xor$ls180.v:5375$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263385,21 +281419,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5259$992_Y + connect \Y $xor$ls180.v:5375$1091_Y end - attribute \src "ls180.v:5259.575-5259.703" - cell $xor $xor$ls180.v:5259$993 + attribute \src "ls180.v:5375.575-5375.703" + cell $xor $xor$ls180.v:5375$1092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5259$992_Y - connect \Y $xor$ls180.v:5259$993_Y + connect \B $xor$ls180.v:5375$1091_Y + connect \Y $xor$ls180.v:5375$1092_Y end - attribute \src "ls180.v:5259.229-5259.311" - cell $xor $xor$ls180.v:5259$994 + attribute \src "ls180.v:5375.229-5375.311" + cell $xor $xor$ls180.v:5375$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263407,32 +281441,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5259$994_Y + connect \Y $xor$ls180.v:5375$1093_Y end - attribute \src "ls180.v:5259.183-5259.312" - cell $xor $xor$ls180.v:5259$995 + attribute \src "ls180.v:5375.183-5375.312" + cell $xor $xor$ls180.v:5375$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5259$994_Y - connect \Y $xor$ls180.v:5259$995_Y + connect \B $xor$ls180.v:5375$1093_Y + connect \Y $xor$ls180.v:5375$1094_Y end - attribute \src "ls180.v:5260.183-5260.312" - cell $xor $xor$ls180.v:5260$1000 + attribute \src "ls180.v:5376.879-5376.961" + cell $xor $xor$ls180.v:5376$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5260$999_Y - connect \Y $xor$ls180.v:5260$1000_Y + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5376$1095_Y end - attribute \src "ls180.v:5260.879-5260.961" - cell $xor $xor$ls180.v:5260$996 + attribute \src "ls180.v:5376.620-5376.702" + cell $xor $xor$ls180.v:5376$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263440,43 +281474,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5260$996_Y + connect \Y $xor$ls180.v:5376$1096_Y end - attribute \src "ls180.v:5260.620-5260.702" - cell $xor $xor$ls180.v:5260$997 + attribute \src "ls180.v:5376.575-5376.703" + cell $xor $xor$ls180.v:5376$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5260$997_Y + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5376$1096_Y + connect \Y $xor$ls180.v:5376$1097_Y end - attribute \src "ls180.v:5260.575-5260.703" - cell $xor $xor$ls180.v:5260$998 + attribute \src "ls180.v:5376.229-5376.311" + cell $xor $xor$ls180.v:5376$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5260$997_Y - connect \Y $xor$ls180.v:5260$998_Y + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5376$1098_Y end - attribute \src "ls180.v:5260.229-5260.311" - cell $xor $xor$ls180.v:5260$999 + attribute \src "ls180.v:5376.183-5376.312" + cell $xor $xor$ls180.v:5376$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5260$999_Y + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5376$1098_Y + connect \Y $xor$ls180.v:5376$1099_Y end - attribute \src "ls180.v:5269.879-5269.961" - cell $xor $xor$ls180.v:5269$1002 + attribute \src "ls180.v:5385.879-5385.961" + cell $xor $xor$ls180.v:5385$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263484,10 +281518,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5269$1002_Y + connect \Y $xor$ls180.v:5385$1101_Y end - attribute \src "ls180.v:5269.620-5269.702" - cell $xor $xor$ls180.v:5269$1003 + attribute \src "ls180.v:5385.620-5385.702" + cell $xor $xor$ls180.v:5385$1102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263495,21 +281529,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5269$1003_Y + connect \Y $xor$ls180.v:5385$1102_Y end - attribute \src "ls180.v:5269.575-5269.703" - cell $xor $xor$ls180.v:5269$1004 + attribute \src "ls180.v:5385.575-5385.703" + cell $xor $xor$ls180.v:5385$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5269$1003_Y - connect \Y $xor$ls180.v:5269$1004_Y + connect \B $xor$ls180.v:5385$1102_Y + connect \Y $xor$ls180.v:5385$1103_Y end - attribute \src "ls180.v:5269.229-5269.311" - cell $xor $xor$ls180.v:5269$1005 + attribute \src "ls180.v:5385.229-5385.311" + cell $xor $xor$ls180.v:5385$1104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263517,21 +281551,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5269$1005_Y + connect \Y $xor$ls180.v:5385$1104_Y end - attribute \src "ls180.v:5269.183-5269.312" - cell $xor $xor$ls180.v:5269$1006 + attribute \src "ls180.v:5385.183-5385.312" + cell $xor $xor$ls180.v:5385$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5269$1005_Y - connect \Y $xor$ls180.v:5269$1006_Y + connect \B $xor$ls180.v:5385$1104_Y + connect \Y $xor$ls180.v:5385$1105_Y end - attribute \src "ls180.v:5270.879-5270.961" - cell $xor $xor$ls180.v:5270$1007 + attribute \src "ls180.v:5386.879-5386.961" + cell $xor $xor$ls180.v:5386$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263539,10 +281573,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5270$1007_Y + connect \Y $xor$ls180.v:5386$1106_Y end - attribute \src "ls180.v:5270.620-5270.702" - cell $xor $xor$ls180.v:5270$1008 + attribute \src "ls180.v:5386.620-5386.702" + cell $xor $xor$ls180.v:5386$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263550,21 +281584,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5270$1008_Y + connect \Y $xor$ls180.v:5386$1107_Y end - attribute \src "ls180.v:5270.575-5270.703" - cell $xor $xor$ls180.v:5270$1009 + attribute \src "ls180.v:5386.575-5386.703" + cell $xor $xor$ls180.v:5386$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5270$1008_Y - connect \Y $xor$ls180.v:5270$1009_Y + connect \B $xor$ls180.v:5386$1107_Y + connect \Y $xor$ls180.v:5386$1108_Y end - attribute \src "ls180.v:5270.229-5270.311" - cell $xor $xor$ls180.v:5270$1010 + attribute \src "ls180.v:5386.229-5386.311" + cell $xor $xor$ls180.v:5386$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263572,21 +281606,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5270$1010_Y + connect \Y $xor$ls180.v:5386$1109_Y end - attribute \src "ls180.v:5270.183-5270.312" - cell $xor $xor$ls180.v:5270$1011 + attribute \src "ls180.v:5386.183-5386.312" + cell $xor $xor$ls180.v:5386$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5270$1010_Y - connect \Y $xor$ls180.v:5270$1011_Y + connect \B $xor$ls180.v:5386$1109_Y + connect \Y $xor$ls180.v:5386$1110_Y end attribute \module_not_derived 1 - attribute \src "ls180.v:10356.13-10730.2" + attribute \src "ls180.v:10609.13-11015.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi @@ -263782,7 +281816,7 @@ module \ls180 connect \pwm_0__pad__o \pwm_1 [0] connect \pwm_1__core__o \pwm [1] connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10456$2870_Y + connect \rst $or$ls180.v:10709$3077_Y connect \sd0_clk__core__o \sdcard_clk connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk connect \sd0_cmd__core__i \sdcard_cmd_i @@ -263791,30 +281825,30 @@ module \ls180 connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data0__core__i \sdcard_cmd_i - connect \sd0_data0__core__o \sdcard_cmd_o - connect \sd0_data0__core__oe \sdcard_cmd_oe - connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data1__core__i \sdcard_cmd_i - connect \sd0_data1__core__o \sdcard_cmd_o - connect \sd0_data1__core__oe \sdcard_cmd_oe - connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data2__core__i \sdcard_cmd_i - connect \sd0_data2__core__o \sdcard_cmd_o - connect \sd0_data2__core__oe \sdcard_cmd_oe - connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data3__core__i \sdcard_cmd_i - connect \sd0_data3__core__o \sdcard_cmd_o - connect \sd0_data3__core__oe \sdcard_cmd_oe - connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data0__core__i \sdcard_data_i [0] + connect \sd0_data0__core__o \sdcard_data_o [0] + connect \sd0_data0__core__oe \sdcard_data_oe + connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [0] + connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [0] + connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data1__core__i \sdcard_data_i [1] + connect \sd0_data1__core__o \sdcard_data_o [1] + connect \sd0_data1__core__oe \sdcard_data_oe + connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [1] + connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [1] + connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data2__core__i \sdcard_data_i [2] + connect \sd0_data2__core__o \sdcard_data_o [2] + connect \sd0_data2__core__oe \sdcard_data_oe + connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [2] + connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [2] + connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data3__core__i \sdcard_data_i [3] + connect \sd0_data3__core__o \sdcard_data_o [3] + connect \sd0_data3__core__oe \sdcard_data_oe + connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [3] + connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [3] + connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe connect \sdr_a_0__core__o \sdram_a [0] connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] connect \sdr_a_10__core__o \sdram_a [10] @@ -263855,12 +281889,8 @@ module \ls180 connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n connect \sdr_dm_0__core__o \sdram_dm [0] connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] - connect \sdr_dm_1__core__i \sdram_dq_i [1] - connect \sdr_dm_1__core__o \sdram_dq_o [1] - connect \sdr_dm_1__core__oe \sdram_dq_oe - connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] - connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] - connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dm_1__core__o \sdram_dm [1] + connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [1] connect \sdr_dq_0__core__i \sdram_dq_i [0] connect \sdr_dq_0__core__o \sdram_dq_o [0] connect \sdr_dq_0__core__oe \sdram_dq_oe @@ -263961,69 +281991,164 @@ module \ls180 connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n connect \sdr_we_n__core__o \sdram_we_n connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + connect \sram4k_0_wb__ack \main_libresocsim_libresoc_interface0_ack + connect \sram4k_0_wb__adr \main_libresocsim_libresoc_interface0_adr + connect \sram4k_0_wb__cyc \main_libresocsim_libresoc_interface0_cyc + connect \sram4k_0_wb__dat_r \main_libresocsim_libresoc_interface0_dat_r + connect \sram4k_0_wb__dat_w \main_libresocsim_libresoc_interface0_dat_w + connect \sram4k_0_wb__err \main_libresocsim_libresoc_interface0_err + connect \sram4k_0_wb__sel \main_libresocsim_libresoc_interface0_sel + connect \sram4k_0_wb__stb \main_libresocsim_libresoc_interface0_stb + connect \sram4k_0_wb__we \main_libresocsim_libresoc_interface0_we + connect \sram4k_1_wb__ack \main_libresocsim_libresoc_interface1_ack + connect \sram4k_1_wb__adr \main_libresocsim_libresoc_interface1_adr + connect \sram4k_1_wb__cyc \main_libresocsim_libresoc_interface1_cyc + connect \sram4k_1_wb__dat_r \main_libresocsim_libresoc_interface1_dat_r + connect \sram4k_1_wb__dat_w \main_libresocsim_libresoc_interface1_dat_w + connect \sram4k_1_wb__err \main_libresocsim_libresoc_interface1_err + connect \sram4k_1_wb__sel \main_libresocsim_libresoc_interface1_sel + connect \sram4k_1_wb__stb \main_libresocsim_libresoc_interface1_stb + connect \sram4k_1_wb__we \main_libresocsim_libresoc_interface1_we + connect \sram4k_2_wb__ack \main_libresocsim_libresoc_interface2_ack + connect \sram4k_2_wb__adr \main_libresocsim_libresoc_interface2_adr + connect \sram4k_2_wb__cyc \main_libresocsim_libresoc_interface2_cyc + connect \sram4k_2_wb__dat_r \main_libresocsim_libresoc_interface2_dat_r + connect \sram4k_2_wb__dat_w \main_libresocsim_libresoc_interface2_dat_w + connect \sram4k_2_wb__err \main_libresocsim_libresoc_interface2_err + connect \sram4k_2_wb__sel \main_libresocsim_libresoc_interface2_sel + connect \sram4k_2_wb__stb \main_libresocsim_libresoc_interface2_stb + connect \sram4k_2_wb__we \main_libresocsim_libresoc_interface2_we + connect \sram4k_3_wb__ack \main_libresocsim_libresoc_interface3_ack + connect \sram4k_3_wb__adr \main_libresocsim_libresoc_interface3_adr + connect \sram4k_3_wb__cyc \main_libresocsim_libresoc_interface3_cyc + connect \sram4k_3_wb__dat_r \main_libresocsim_libresoc_interface3_dat_r + connect \sram4k_3_wb__dat_w \main_libresocsim_libresoc_interface3_dat_w + connect \sram4k_3_wb__err \main_libresocsim_libresoc_interface3_err + connect \sram4k_3_wb__sel \main_libresocsim_libresoc_interface3_sel + connect \sram4k_3_wb__stb \main_libresocsim_libresoc_interface3_stb + connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3842 + process $proc$ls180.v:0$4091 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3843 + process $proc$ls180.v:0$4092 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3844 + process $proc$ls180.v:0$4093 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3845 + process $proc$ls180.v:0$4094 sync always sync init end - attribute \src "ls180.v:1004.11-1004.42" - process $proc$ls180.v:1004$3254 + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4095 + sync always + sync init + end + attribute \src "ls180.v:100.11-100.56" + process $proc$ls180.v:100$3144 assign { } { } - assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 sync always sync init - update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] end - attribute \src "ls180.v:1005.5-1005.37" - process $proc$ls180.v:1005$3255 + attribute \src "ls180.v:101.5-101.50" + process $proc$ls180.v:101$3145 assign { } { } - assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 sync always - update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] sync init + update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] end - attribute \src "ls180.v:1006.11-1006.43" - process $proc$ls180.v:1006$3256 + attribute \src "ls180.v:1012.5-1012.40" + process $proc$ls180.v:1012$3483 assign { } { } - assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init - update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end - attribute \src "ls180.v:1007.11-1007.43" - process $proc$ls180.v:1007$3257 + attribute \src "ls180.v:1013.5-1013.39" + process $proc$ls180.v:1013$3484 assign { } { } - assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init - update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end - attribute \src "ls180.v:1008.11-1008.46" - process $proc$ls180.v:1008$3258 + attribute \src "ls180.v:102.5-102.50" + process $proc$ls180.v:102$3146 assign { } { } - assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 sync always sync init - update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] end - attribute \src "ls180.v:10160.1-10170.4" - process $proc$ls180.v:10160$2758 + attribute \src "ls180.v:1021.5-1021.38" + process $proc$ls180.v:1021$3485 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:1028.11-1028.42" + process $proc$ls180.v:1028$3486 + assign { } { } + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + end + attribute \src "ls180.v:1029.5-1029.37" + process $proc$ls180.v:1029$3487 + assign { } { } + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1030.11-1030.43" + process $proc$ls180.v:1030$3488 + assign { } { } + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + end + attribute \src "ls180.v:1031.11-1031.43" + process $proc$ls180.v:1031$3489 + assign { } { } + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + end + attribute \src "ls180.v:1032.11-1032.46" + process $proc$ls180.v:1032$3490 + assign { } { } + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:10353.1-10371.4" + process $proc$ls180.v:10353$2891 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -264037,72 +282162,139 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 0 - assign $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 0 - assign $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 0 - assign $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 0 - assign $0\memadr[6:0] \main_libresocsim_adr - attribute \src "ls180.v:10161.2-10162.65" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr[5:0] \main_libresocsim_adr + attribute \src "ls180.v:10354.2-10355.65" switch \main_libresocsim_we [0] - attribute \src "ls180.v:10161.6-10161.28" + attribute \src "ls180.v:10354.6-10354.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 255 + assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10163.2-10164.67" + attribute \src "ls180.v:10356.2-10357.67" switch \main_libresocsim_we [1] - attribute \src "ls180.v:10163.6-10163.28" + attribute \src "ls180.v:10356.6-10356.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 65280 + assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10165.2-10166.69" + attribute \src "ls180.v:10358.2-10359.69" switch \main_libresocsim_we [2] - attribute \src "ls180.v:10165.6-10165.28" + attribute \src "ls180.v:10358.6-10358.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 16711680 + assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10167.2-10168.69" + attribute \src "ls180.v:10360.2-10361.69" switch \main_libresocsim_we [3] - attribute \src "ls180.v:10167.6-10167.28" + attribute \src "ls180.v:10360.6-10360.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 32'11111111000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10362.2-10363.69" + switch \main_libresocsim_we [4] + attribute \src "ls180.v:10362.6-10362.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10364.2-10365.69" + switch \main_libresocsim_we [5] + attribute \src "ls180.v:10364.6-10364.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10366.2-10367.69" + switch \main_libresocsim_we [6] + attribute \src "ls180.v:10366.6-10366.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10368.2-10369.69" + switch \main_libresocsim_we [7] + attribute \src "ls180.v:10368.6-10368.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:10162$1_ADDR $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 - update $memwr$\mem$ls180.v:10162$1_DATA $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 - update $memwr$\mem$ls180.v:10162$1_EN $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 - update $memwr$\mem$ls180.v:10164$2_ADDR $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 - update $memwr$\mem$ls180.v:10164$2_DATA $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 - update $memwr$\mem$ls180.v:10164$2_EN $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 - update $memwr$\mem$ls180.v:10166$3_ADDR $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 - update $memwr$\mem$ls180.v:10166$3_DATA $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 - update $memwr$\mem$ls180.v:10166$3_EN $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 - update $memwr$\mem$ls180.v:10168$4_ADDR $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 - update $memwr$\mem$ls180.v:10168$4_DATA $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 - update $memwr$\mem$ls180.v:10168$4_EN $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 + update \memadr $0\memadr[5:0] + update $memwr$\mem$ls180.v:10355$1_ADDR $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 + update $memwr$\mem$ls180.v:10355$1_DATA $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 + update $memwr$\mem$ls180.v:10355$1_EN $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 + update $memwr$\mem$ls180.v:10357$2_ADDR $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 + update $memwr$\mem$ls180.v:10357$2_DATA $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 + update $memwr$\mem$ls180.v:10357$2_EN $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 + update $memwr$\mem$ls180.v:10359$3_ADDR $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 + update $memwr$\mem$ls180.v:10359$3_DATA $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 + update $memwr$\mem$ls180.v:10359$3_EN $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 + update $memwr$\mem$ls180.v:10361$4_ADDR $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 + update $memwr$\mem$ls180.v:10361$4_DATA $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 + update $memwr$\mem$ls180.v:10361$4_EN $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 + update $memwr$\mem$ls180.v:10363$5_ADDR $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 + update $memwr$\mem$ls180.v:10363$5_DATA $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 + update $memwr$\mem$ls180.v:10363$5_EN $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 + update $memwr$\mem$ls180.v:10365$6_ADDR $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 + update $memwr$\mem$ls180.v:10365$6_DATA $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 + update $memwr$\mem$ls180.v:10365$6_EN $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 + update $memwr$\mem$ls180.v:10367$7_ADDR $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 + update $memwr$\mem$ls180.v:10367$7_DATA $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 + update $memwr$\mem$ls180.v:10367$7_EN $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 + update $memwr$\mem$ls180.v:10369$8_ADDR $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 + update $memwr$\mem$ls180.v:10369$8_DATA $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 + update $memwr$\mem$ls180.v:10369$8_EN $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 end - attribute \src "ls180.v:10180.1-10190.4" - process $proc$ls180.v:10180$2772 + attribute \src "ls180.v:10381.1-10399.4" + process $proc$ls180.v:10381$2917 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -264116,72 +282308,163 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 7'xxxxxxx - assign $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 0 - assign $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 7'xxxxxxx - assign $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 0 - assign $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 7'xxxxxxx - assign $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 0 - assign $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 7'xxxxxxx - assign $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 0 - assign $0\memadr_1[6:0] \main_sram0_adr - attribute \src "ls180.v:10181.2-10182.55" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_1[5:0] \main_sram0_adr + attribute \src "ls180.v:10382.2-10383.55" switch \main_sram0_we [0] - attribute \src "ls180.v:10181.6-10181.22" + attribute \src "ls180.v:10382.6-10382.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 { 24'000000000000000000000000 \main_sram0_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 255 + assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10183.2-10184.57" + attribute \src "ls180.v:10384.2-10385.57" switch \main_sram0_we [1] - attribute \src "ls180.v:10183.6-10183.22" + attribute \src "ls180.v:10384.6-10384.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 { 16'0000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 65280 + assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10185.2-10186.59" + attribute \src "ls180.v:10386.2-10387.59" switch \main_sram0_we [2] - attribute \src "ls180.v:10185.6-10185.22" + attribute \src "ls180.v:10386.6-10386.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 { 8'00000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 16711680 + assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10187.2-10188.59" + attribute \src "ls180.v:10388.2-10389.59" switch \main_sram0_we [3] - attribute \src "ls180.v:10187.6-10187.22" + attribute \src "ls180.v:10388.6-10388.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10390.2-10391.59" + switch \main_sram0_we [4] + attribute \src "ls180.v:10390.6-10390.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10392.2-10393.59" + switch \main_sram0_we [5] + attribute \src "ls180.v:10392.6-10392.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10394.2-10395.59" + switch \main_sram0_we [6] + attribute \src "ls180.v:10394.6-10394.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 { \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 32'11111111000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10396.2-10397.59" + switch \main_sram0_we [7] + attribute \src "ls180.v:10396.6-10396.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr_1 $0\memadr_1[6:0] - update $memwr$\mem_1$ls180.v:10182$5_ADDR $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 - update $memwr$\mem_1$ls180.v:10182$5_DATA $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 - update $memwr$\mem_1$ls180.v:10182$5_EN $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 - update $memwr$\mem_1$ls180.v:10184$6_ADDR $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 - update $memwr$\mem_1$ls180.v:10184$6_DATA $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 - update $memwr$\mem_1$ls180.v:10184$6_EN $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 - update $memwr$\mem_1$ls180.v:10186$7_ADDR $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 - update $memwr$\mem_1$ls180.v:10186$7_DATA $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 - update $memwr$\mem_1$ls180.v:10186$7_EN $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 - update $memwr$\mem_1$ls180.v:10188$8_ADDR $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 - update $memwr$\mem_1$ls180.v:10188$8_DATA $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 - update $memwr$\mem_1$ls180.v:10188$8_EN $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 + update \memadr_1 $0\memadr_1[5:0] + update $memwr$\mem_1$ls180.v:10383$9_ADDR $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 + update $memwr$\mem_1$ls180.v:10383$9_DATA $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 + update $memwr$\mem_1$ls180.v:10383$9_EN $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 + update $memwr$\mem_1$ls180.v:10385$10_ADDR $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 + update $memwr$\mem_1$ls180.v:10385$10_DATA $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 + update $memwr$\mem_1$ls180.v:10385$10_EN $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 + update $memwr$\mem_1$ls180.v:10387$11_ADDR $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 + update $memwr$\mem_1$ls180.v:10387$11_DATA $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 + update $memwr$\mem_1$ls180.v:10387$11_EN $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 + update $memwr$\mem_1$ls180.v:10389$12_ADDR $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 + update $memwr$\mem_1$ls180.v:10389$12_DATA $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 + update $memwr$\mem_1$ls180.v:10389$12_EN $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 + update $memwr$\mem_1$ls180.v:10391$13_ADDR $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 + update $memwr$\mem_1$ls180.v:10391$13_DATA $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 + update $memwr$\mem_1$ls180.v:10391$13_EN $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 + update $memwr$\mem_1$ls180.v:10393$14_ADDR $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 + update $memwr$\mem_1$ls180.v:10393$14_DATA $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 + update $memwr$\mem_1$ls180.v:10393$14_EN $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 + update $memwr$\mem_1$ls180.v:10395$15_ADDR $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 + update $memwr$\mem_1$ls180.v:10395$15_DATA $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 + update $memwr$\mem_1$ls180.v:10395$15_EN $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 + update $memwr$\mem_1$ls180.v:10397$16_ADDR $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 + update $memwr$\mem_1$ls180.v:10397$16_DATA $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 + update $memwr$\mem_1$ls180.v:10397$16_EN $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 + end + attribute \src "ls180.v:104.5-104.49" + process $proc$ls180.v:104$3147 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] end - attribute \src "ls180.v:10200.1-10210.4" - process $proc$ls180.v:10200$2786 + attribute \src "ls180.v:10409.1-10427.4" + process $proc$ls180.v:10409$2943 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -264195,72 +282478,140 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 7'xxxxxxx - assign $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 0 - assign $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 7'xxxxxxx - assign $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 0 - assign $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 7'xxxxxxx - assign $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 0 - assign $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 7'xxxxxxx - assign $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 0 - assign $0\memadr_2[6:0] \main_sram1_adr - attribute \src "ls180.v:10201.2-10202.55" + assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_2[5:0] \main_sram1_adr + attribute \src "ls180.v:10410.2-10411.55" switch \main_sram1_we [0] - attribute \src "ls180.v:10201.6-10201.22" + attribute \src "ls180.v:10410.6-10410.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 { 24'000000000000000000000000 \main_sram1_dat_w [7:0] } - assign $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 255 + assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } + assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10203.2-10204.57" + attribute \src "ls180.v:10412.2-10413.57" switch \main_sram1_we [1] - attribute \src "ls180.v:10203.6-10203.22" + attribute \src "ls180.v:10412.6-10412.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 { 16'0000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 65280 + assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10205.2-10206.59" + attribute \src "ls180.v:10414.2-10415.59" switch \main_sram1_we [2] - attribute \src "ls180.v:10205.6-10205.22" + attribute \src "ls180.v:10414.6-10414.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 { 8'00000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 16711680 + assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10207.2-10208.59" + attribute \src "ls180.v:10416.2-10417.59" switch \main_sram1_we [3] - attribute \src "ls180.v:10207.6-10207.22" + attribute \src "ls180.v:10416.6-10416.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 { \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 32'11111111000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10418.2-10419.59" + switch \main_sram1_we [4] + attribute \src "ls180.v:10418.6-10418.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10420.2-10421.59" + switch \main_sram1_we [5] + attribute \src "ls180.v:10420.6-10420.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10422.2-10423.59" + switch \main_sram1_we [6] + attribute \src "ls180.v:10422.6-10422.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10424.2-10425.59" + switch \main_sram1_we [7] + attribute \src "ls180.v:10424.6-10424.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr_2 $0\memadr_2[6:0] - update $memwr$\mem_2$ls180.v:10202$9_ADDR $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 - update $memwr$\mem_2$ls180.v:10202$9_DATA $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 - update $memwr$\mem_2$ls180.v:10202$9_EN $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 - update $memwr$\mem_2$ls180.v:10204$10_ADDR $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 - update $memwr$\mem_2$ls180.v:10204$10_DATA $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 - update $memwr$\mem_2$ls180.v:10204$10_EN $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 - update $memwr$\mem_2$ls180.v:10206$11_ADDR $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 - update $memwr$\mem_2$ls180.v:10206$11_DATA $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 - update $memwr$\mem_2$ls180.v:10206$11_EN $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 - update $memwr$\mem_2$ls180.v:10208$12_ADDR $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 - update $memwr$\mem_2$ls180.v:10208$12_DATA $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 - update $memwr$\mem_2$ls180.v:10208$12_EN $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 + update \memadr_2 $0\memadr_2[5:0] + update $memwr$\mem_2$ls180.v:10411$17_ADDR $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 + update $memwr$\mem_2$ls180.v:10411$17_DATA $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 + update $memwr$\mem_2$ls180.v:10411$17_EN $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 + update $memwr$\mem_2$ls180.v:10413$18_ADDR $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 + update $memwr$\mem_2$ls180.v:10413$18_DATA $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 + update $memwr$\mem_2$ls180.v:10413$18_EN $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 + update $memwr$\mem_2$ls180.v:10415$19_ADDR $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 + update $memwr$\mem_2$ls180.v:10415$19_DATA $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 + update $memwr$\mem_2$ls180.v:10415$19_EN $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 + update $memwr$\mem_2$ls180.v:10417$20_ADDR $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 + update $memwr$\mem_2$ls180.v:10417$20_DATA $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 + update $memwr$\mem_2$ls180.v:10417$20_EN $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 + update $memwr$\mem_2$ls180.v:10419$21_ADDR $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 + update $memwr$\mem_2$ls180.v:10419$21_DATA $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 + update $memwr$\mem_2$ls180.v:10419$21_EN $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 + update $memwr$\mem_2$ls180.v:10421$22_ADDR $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 + update $memwr$\mem_2$ls180.v:10421$22_DATA $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 + update $memwr$\mem_2$ls180.v:10421$22_EN $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 + update $memwr$\mem_2$ls180.v:10423$23_ADDR $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 + update $memwr$\mem_2$ls180.v:10423$23_DATA $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 + update $memwr$\mem_2$ls180.v:10423$23_EN $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 + update $memwr$\mem_2$ls180.v:10425$24_ADDR $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 + update $memwr$\mem_2$ls180.v:10425$24_DATA $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 + update $memwr$\mem_2$ls180.v:10425$24_EN $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 end - attribute \src "ls180.v:10220.1-10230.4" - process $proc$ls180.v:10220$2800 + attribute \src "ls180.v:10437.1-10455.4" + process $proc$ls180.v:10437$2969 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -264274,5466 +282625,5593 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 7'xxxxxxx - assign $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 0 - assign $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 7'xxxxxxx - assign $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 0 - assign $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 7'xxxxxxx - assign $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 0 - assign $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 7'xxxxxxx - assign $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 0 - assign $0\memadr_3[6:0] \main_sram2_adr - attribute \src "ls180.v:10221.2-10222.55" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_3[5:0] \main_sram2_adr + attribute \src "ls180.v:10438.2-10439.55" switch \main_sram2_we [0] - attribute \src "ls180.v:10221.6-10221.22" + attribute \src "ls180.v:10438.6-10438.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 { 24'000000000000000000000000 \main_sram2_dat_w [7:0] } - assign $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 255 + assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } + assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10223.2-10224.57" + attribute \src "ls180.v:10440.2-10441.57" switch \main_sram2_we [1] - attribute \src "ls180.v:10223.6-10223.22" + attribute \src "ls180.v:10440.6-10440.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 { 16'0000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 65280 + assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10225.2-10226.59" + attribute \src "ls180.v:10442.2-10443.59" switch \main_sram2_we [2] - attribute \src "ls180.v:10225.6-10225.22" + attribute \src "ls180.v:10442.6-10442.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 { 8'00000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 16711680 + assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10227.2-10228.59" + attribute \src "ls180.v:10444.2-10445.59" switch \main_sram2_we [3] - attribute \src "ls180.v:10227.6-10227.22" + attribute \src "ls180.v:10444.6-10444.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10446.2-10447.59" + switch \main_sram2_we [4] + attribute \src "ls180.v:10446.6-10446.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10448.2-10449.59" + switch \main_sram2_we [5] + attribute \src "ls180.v:10448.6-10448.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 { \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 32'11111111000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10450.2-10451.59" + switch \main_sram2_we [6] + attribute \src "ls180.v:10450.6-10450.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10452.2-10453.59" + switch \main_sram2_we [7] + attribute \src "ls180.v:10452.6-10452.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr_3 $0\memadr_3[6:0] - update $memwr$\mem_3$ls180.v:10222$13_ADDR $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 - update $memwr$\mem_3$ls180.v:10222$13_DATA $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 - update $memwr$\mem_3$ls180.v:10222$13_EN $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 - update $memwr$\mem_3$ls180.v:10224$14_ADDR $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 - update $memwr$\mem_3$ls180.v:10224$14_DATA $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 - update $memwr$\mem_3$ls180.v:10224$14_EN $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 - update $memwr$\mem_3$ls180.v:10226$15_ADDR $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 - update $memwr$\mem_3$ls180.v:10226$15_DATA $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 - update $memwr$\mem_3$ls180.v:10226$15_EN $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 - update $memwr$\mem_3$ls180.v:10228$16_ADDR $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 - update $memwr$\mem_3$ls180.v:10228$16_DATA $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 - update $memwr$\mem_3$ls180.v:10228$16_EN $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 - end - attribute \src "ls180.v:1023.5-1023.27" - process $proc$ls180.v:1023$3259 - assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init + update \memadr_3 $0\memadr_3[5:0] + update $memwr$\mem_3$ls180.v:10439$25_ADDR $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 + update $memwr$\mem_3$ls180.v:10439$25_DATA $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 + update $memwr$\mem_3$ls180.v:10439$25_EN $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 + update $memwr$\mem_3$ls180.v:10441$26_ADDR $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 + update $memwr$\mem_3$ls180.v:10441$26_DATA $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 + update $memwr$\mem_3$ls180.v:10441$26_EN $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 + update $memwr$\mem_3$ls180.v:10443$27_ADDR $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 + update $memwr$\mem_3$ls180.v:10443$27_DATA $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 + update $memwr$\mem_3$ls180.v:10443$27_EN $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 + update $memwr$\mem_3$ls180.v:10445$28_ADDR $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 + update $memwr$\mem_3$ls180.v:10445$28_DATA $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 + update $memwr$\mem_3$ls180.v:10445$28_EN $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 + update $memwr$\mem_3$ls180.v:10447$29_ADDR $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 + update $memwr$\mem_3$ls180.v:10447$29_DATA $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 + update $memwr$\mem_3$ls180.v:10447$29_EN $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 + update $memwr$\mem_3$ls180.v:10449$30_ADDR $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 + update $memwr$\mem_3$ls180.v:10449$30_DATA $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 + update $memwr$\mem_3$ls180.v:10449$30_EN $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 + update $memwr$\mem_3$ls180.v:10451$31_ADDR $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 + update $memwr$\mem_3$ls180.v:10451$31_DATA $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 + update $memwr$\mem_3$ls180.v:10451$31_EN $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 + update $memwr$\mem_3$ls180.v:10453$32_ADDR $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 + update $memwr$\mem_3$ls180.v:10453$32_DATA $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 + update $memwr$\mem_3$ls180.v:10453$32_EN $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 end - attribute \src "ls180.v:1024.12-1024.40" - process $proc$ls180.v:1024$3260 + attribute \src "ls180.v:10465.1-10483.4" + process $proc$ls180.v:10465$2995 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } - assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] - end - attribute \src "ls180.v:10240.1-10244.4" - process $proc$ls180.v:10240$2814 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 3'xxx - assign $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10243$2818_DATA - attribute \src "ls180.v:10241.2-10242.129" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_4[5:0] \main_sram3_adr + attribute \src "ls180.v:10466.2-10467.55" + switch \main_sram3_we [0] + attribute \src "ls180.v:10466.6-10466.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } + assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10468.2-10469.57" + switch \main_sram3_we [1] + attribute \src "ls180.v:10468.6-10468.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10470.2-10471.59" + switch \main_sram3_we [2] + attribute \src "ls180.v:10470.6-10470.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10472.2-10473.59" + switch \main_sram3_we [3] + attribute \src "ls180.v:10472.6-10472.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10474.2-10475.59" + switch \main_sram3_we [4] + attribute \src "ls180.v:10474.6-10474.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10476.2-10477.59" + switch \main_sram3_we [5] + attribute \src "ls180.v:10476.6-10476.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10478.2-10479.59" + switch \main_sram3_we [6] + attribute \src "ls180.v:10478.6-10478.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10480.2-10481.59" + switch \main_sram3_we [7] + attribute \src "ls180.v:10480.6-10480.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_4 $0\memadr_4[5:0] + update $memwr$\mem_4$ls180.v:10467$33_ADDR $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 + update $memwr$\mem_4$ls180.v:10467$33_DATA $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 + update $memwr$\mem_4$ls180.v:10467$33_EN $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 + update $memwr$\mem_4$ls180.v:10469$34_ADDR $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 + update $memwr$\mem_4$ls180.v:10469$34_DATA $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 + update $memwr$\mem_4$ls180.v:10469$34_EN $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 + update $memwr$\mem_4$ls180.v:10471$35_ADDR $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 + update $memwr$\mem_4$ls180.v:10471$35_DATA $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 + update $memwr$\mem_4$ls180.v:10471$35_EN $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 + update $memwr$\mem_4$ls180.v:10473$36_ADDR $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 + update $memwr$\mem_4$ls180.v:10473$36_DATA $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 + update $memwr$\mem_4$ls180.v:10473$36_EN $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 + update $memwr$\mem_4$ls180.v:10475$37_ADDR $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 + update $memwr$\mem_4$ls180.v:10475$37_DATA $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 + update $memwr$\mem_4$ls180.v:10475$37_EN $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 + update $memwr$\mem_4$ls180.v:10477$38_ADDR $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 + update $memwr$\mem_4$ls180.v:10477$38_DATA $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 + update $memwr$\mem_4$ls180.v:10477$38_EN $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 + update $memwr$\mem_4$ls180.v:10479$39_ADDR $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 + update $memwr$\mem_4$ls180.v:10479$39_DATA $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 + update $memwr$\mem_4$ls180.v:10479$39_EN $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 + update $memwr$\mem_4$ls180.v:10481$40_ADDR $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 + update $memwr$\mem_4$ls180.v:10481$40_DATA $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 + update $memwr$\mem_4$ls180.v:10481$40_EN $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 + end + attribute \src "ls180.v:10493.1-10497.4" + process $proc$ls180.v:10493$3021 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 3'xxx + assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10496$3025_DATA + attribute \src "ls180.v:10494.2-10495.129" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10241.6-10241.60" + attribute \src "ls180.v:10494.6-10494.60" case 1'1 - assign $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 25'1111111111111111111111111 + assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10242$17_ADDR $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 - update $memwr$\storage$ls180.v:10242$17_DATA $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 - update $memwr$\storage$ls180.v:10242$17_EN $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 + update $memwr$\storage$ls180.v:10495$41_ADDR $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 + update $memwr$\storage$ls180.v:10495$41_DATA $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 + update $memwr$\storage$ls180.v:10495$41_EN $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 end - attribute \src "ls180.v:10246.1-10247.4" - process $proc$ls180.v:10246$2819 + attribute \src "ls180.v:10499.1-10500.4" + process $proc$ls180.v:10499$3026 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1025.5-1025.27" - process $proc$ls180.v:1025$3261 - assign { } { } - assign $1\main_gpio_oe_re[0:0] 1'0 - sync always - sync init - update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] - end - attribute \src "ls180.v:10254.1-10258.4" - process $proc$ls180.v:10254$2821 + attribute \src "ls180.v:10507.1-10511.4" + process $proc$ls180.v:10507$3028 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 3'xxx - assign $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10257$2825_DATA - attribute \src "ls180.v:10255.2-10256.131" + assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 3'xxx + assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10510$3032_DATA + attribute \src "ls180.v:10508.2-10509.131" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10255.6-10255.60" + attribute \src "ls180.v:10508.6-10508.60" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 25'1111111111111111111111111 + assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10256$18_ADDR $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 - update $memwr$\storage_1$ls180.v:10256$18_DATA $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 - update $memwr$\storage_1$ls180.v:10256$18_EN $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 + update $memwr$\storage_1$ls180.v:10509$42_ADDR $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 + update $memwr$\storage_1$ls180.v:10509$42_DATA $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 + update $memwr$\storage_1$ls180.v:10509$42_EN $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 end - attribute \src "ls180.v:1026.12-1026.36" - process $proc$ls180.v:1026$3262 - assign { } { } - assign $1\main_gpio_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_status $1\main_gpio_status[15:0] - end - attribute \src "ls180.v:10260.1-10261.4" - process $proc$ls180.v:10260$2826 + attribute \src "ls180.v:10513.1-10514.4" + process $proc$ls180.v:10513$3033 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10268.1-10272.4" - process $proc$ls180.v:10268$2828 + attribute \src "ls180.v:10521.1-10525.4" + process $proc$ls180.v:10521$3035 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 3'xxx - assign $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10271$2832_DATA - attribute \src "ls180.v:10269.2-10270.131" + assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 3'xxx + assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10524$3039_DATA + attribute \src "ls180.v:10522.2-10523.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10269.6-10269.60" + attribute \src "ls180.v:10522.6-10522.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10270$19_ADDR $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 - update $memwr$\storage_2$ls180.v:10270$19_DATA $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 - update $memwr$\storage_2$ls180.v:10270$19_EN $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 + update $memwr$\storage_2$ls180.v:10523$43_ADDR $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 + update $memwr$\storage_2$ls180.v:10523$43_DATA $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 + update $memwr$\storage_2$ls180.v:10523$43_EN $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 end - attribute \src "ls180.v:10274.1-10275.4" - process $proc$ls180.v:10274$2833 + attribute \src "ls180.v:10527.1-10528.4" + process $proc$ls180.v:10527$3040 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1028.12-1028.41" - process $proc$ls180.v:1028$3263 - assign { } { } - assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] - end - attribute \src "ls180.v:10282.1-10286.4" - process $proc$ls180.v:10282$2835 + attribute \src "ls180.v:10535.1-10539.4" + process $proc$ls180.v:10535$3042 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 3'xxx - assign $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10285$2839_DATA - attribute \src "ls180.v:10283.2-10284.131" + assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 3'xxx + assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10538$3046_DATA + attribute \src "ls180.v:10536.2-10537.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10283.6-10283.60" + attribute \src "ls180.v:10536.6-10536.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10284$20_ADDR $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 - update $memwr$\storage_3$ls180.v:10284$20_DATA $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 - update $memwr$\storage_3$ls180.v:10284$20_EN $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 + update $memwr$\storage_3$ls180.v:10537$44_ADDR $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 + update $memwr$\storage_3$ls180.v:10537$44_DATA $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 + update $memwr$\storage_3$ls180.v:10537$44_EN $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 end - attribute \src "ls180.v:10288.1-10289.4" - process $proc$ls180.v:10288$2840 + attribute \src "ls180.v:10541.1-10542.4" + process $proc$ls180.v:10541$3047 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1029.5-1029.28" - process $proc$ls180.v:1029$3264 - assign { } { } - assign $1\main_gpio_out_re[0:0] 1'0 - sync always - sync init - update \main_gpio_out_re $1\main_gpio_out_re[0:0] - end - attribute \src "ls180.v:10297.1-10301.4" - process $proc$ls180.v:10297$2842 + attribute \src "ls180.v:10550.1-10554.4" + process $proc$ls180.v:10550$3049 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10300$2846_DATA - attribute \src "ls180.v:10298.2-10299.77" + assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10553$3053_DATA + attribute \src "ls180.v:10551.2-10552.77" switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10298.6-10298.33" + attribute \src "ls180.v:10551.6-10551.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10299$21_ADDR $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 - update $memwr$\storage_4$ls180.v:10299$21_DATA $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 - update $memwr$\storage_4$ls180.v:10299$21_EN $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 + update $memwr$\storage_4$ls180.v:10552$45_ADDR $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 + update $memwr$\storage_4$ls180.v:10552$45_DATA $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 + update $memwr$\storage_4$ls180.v:10552$45_EN $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 end - attribute \src "ls180.v:10303.1-10306.4" - process $proc$ls180.v:10303$2847 + attribute \src "ls180.v:10556.1-10559.4" + process $proc$ls180.v:10556$3054 assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10304.2-10305.55" + attribute \src "ls180.v:10557.2-10558.55" switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10304.6-10304.33" + attribute \src "ls180.v:10557.6-10557.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10305$2848_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10558$3055_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end - attribute \src "ls180.v:10314.1-10318.4" - process $proc$ls180.v:10314$2849 + attribute \src "ls180.v:10567.1-10571.4" + process $proc$ls180.v:10567$3056 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10317$2853_DATA - attribute \src "ls180.v:10315.2-10316.77" + assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10570$3060_DATA + attribute \src "ls180.v:10568.2-10569.77" switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10315.6-10315.33" + attribute \src "ls180.v:10568.6-10568.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10316$22_ADDR $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 - update $memwr$\storage_5$ls180.v:10316$22_DATA $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 - update $memwr$\storage_5$ls180.v:10316$22_EN $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 + update $memwr$\storage_5$ls180.v:10569$46_ADDR $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 + update $memwr$\storage_5$ls180.v:10569$46_DATA $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 + update $memwr$\storage_5$ls180.v:10569$46_EN $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 end - attribute \src "ls180.v:10320.1-10323.4" - process $proc$ls180.v:10320$2854 + attribute \src "ls180.v:10573.1-10576.4" + process $proc$ls180.v:10573$3061 assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10321.2-10322.55" + attribute \src "ls180.v:10574.2-10575.55" switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10321.6-10321.33" + attribute \src "ls180.v:10574.6-10574.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10322$2855_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10575$3062_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end - attribute \src "ls180.v:10330.1-10334.4" - process $proc$ls180.v:10330$2856 + attribute \src "ls180.v:1058.5-1058.38" + process $proc$ls180.v:1058$3491 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:10583.1-10587.4" + process $proc$ls180.v:10583$3063 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10333$2860_DATA - attribute \src "ls180.v:10331.2-10332.85" + assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10586$3067_DATA + attribute \src "ls180.v:10584.2-10585.85" switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10331.6-10331.37" + attribute \src "ls180.v:10584.6-10584.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10332$23_ADDR $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 - update $memwr$\storage_6$ls180.v:10332$23_DATA $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 - update $memwr$\storage_6$ls180.v:10332$23_EN $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 + update $memwr$\storage_6$ls180.v:10585$47_ADDR $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 + update $memwr$\storage_6$ls180.v:10585$47_DATA $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 + update $memwr$\storage_6$ls180.v:10585$47_EN $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 end - attribute \src "ls180.v:10336.1-10337.4" - process $proc$ls180.v:10336$2861 + attribute \src "ls180.v:10589.1-10590.4" + process $proc$ls180.v:10589$3068 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10344.1-10348.4" - process $proc$ls180.v:10344$2863 + attribute \src "ls180.v:10597.1-10601.4" + process $proc$ls180.v:10597$3070 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10347$2867_DATA - attribute \src "ls180.v:10345.2-10346.85" + assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10600$3074_DATA + attribute \src "ls180.v:10598.2-10599.85" switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10345.6-10345.37" + attribute \src "ls180.v:10598.6-10598.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10346$24_ADDR $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 - update $memwr$\storage_7$ls180.v:10346$24_DATA $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 - update $memwr$\storage_7$ls180.v:10346$24_EN $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 + update $memwr$\storage_7$ls180.v:10599$48_ADDR $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 + update $memwr$\storage_7$ls180.v:10599$48_DATA $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 + update $memwr$\storage_7$ls180.v:10599$48_EN $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 + end + attribute \src "ls180.v:10603.1-10604.4" + process $proc$ls180.v:10603$3075 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1065.11-1065.42" + process $proc$ls180.v:1065$3492 + assign { } { } + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:1066.5-1066.37" + process $proc$ls180.v:1066$3493 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1067.11-1067.43" + process $proc$ls180.v:1067$3494 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + end + attribute \src "ls180.v:1068.11-1068.43" + process $proc$ls180.v:1068$3495 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:1069.11-1069.46" + process $proc$ls180.v:1069$3496 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:1084.5-1084.27" + process $proc$ls180.v:1084$3497 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:1085.12-1085.53" + process $proc$ls180.v:1085$3498 + assign { } { } + assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] + sync init + end + attribute \src "ls180.v:1086.12-1086.49" + process $proc$ls180.v:1086$3499 + assign { } { } + assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:1087.12-1087.54" + process $proc$ls180.v:1087$3500 + assign { } { } + assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] + sync init + end + attribute \src "ls180.v:1091.12-1091.53" + process $proc$ls180.v:1091$3501 + assign { } { } + assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] end - attribute \src "ls180.v:1035.5-1035.32" - process $proc$ls180.v:1035$3265 + attribute \src "ls180.v:1092.5-1092.40" + process $proc$ls180.v:1092$3502 + assign { } { } + assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] + end + attribute \src "ls180.v:1093.12-1093.49" + process $proc$ls180.v:1093$3503 + assign { } { } + assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] + end + attribute \src "ls180.v:1095.12-1095.54" + process $proc$ls180.v:1095$3504 + assign { } { } + assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] + end + attribute \src "ls180.v:1096.5-1096.41" + process $proc$ls180.v:1096$3505 + assign { } { } + assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] + end + attribute \src "ls180.v:1102.5-1102.32" + process $proc$ls180.v:1102$3506 assign { } { } assign $1\main_spimaster2_done[0:0] 1'0 sync always sync init update \main_spimaster2_done $1\main_spimaster2_done[0:0] end - attribute \src "ls180.v:10350.1-10351.4" - process $proc$ls180.v:10350$2868 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1036.5-1036.31" - process $proc$ls180.v:1036$3266 + attribute \src "ls180.v:1103.5-1103.31" + process $proc$ls180.v:1103$3507 assign { } { } assign $1\main_spimaster3_irq[0:0] 1'0 sync always sync init update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] end - attribute \src "ls180.v:1038.11-1038.38" - process $proc$ls180.v:1038$3267 + attribute \src "ls180.v:1105.11-1105.38" + process $proc$ls180.v:1105$3508 assign { } { } assign $1\main_spimaster5_miso[7:0] 8'00000000 sync always sync init update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] end - attribute \src "ls180.v:1041.12-1041.47" - process $proc$ls180.v:1041$3268 + attribute \src "ls180.v:1108.12-1108.47" + process $proc$ls180.v:1108$3509 assign { } { } assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 sync always update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] sync init end - attribute \src "ls180.v:1042.5-1042.33" - process $proc$ls180.v:1042$3269 + attribute \src "ls180.v:1109.5-1109.33" + process $proc$ls180.v:1109$3510 assign { } { } assign $1\main_spimaster9_start[0:0] 1'0 sync always sync init update \main_spimaster9_start $1\main_spimaster9_start[0:0] end - attribute \src "ls180.v:1044.12-1044.44" - process $proc$ls180.v:1044$3270 + attribute \src "ls180.v:1111.12-1111.44" + process $proc$ls180.v:1111$3511 assign { } { } assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 sync always sync init update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] end - attribute \src "ls180.v:1045.5-1045.31" - process $proc$ls180.v:1045$3271 + attribute \src "ls180.v:1112.5-1112.31" + process $proc$ls180.v:1112$3512 assign { } { } assign $1\main_spimaster12_re[0:0] 1'0 sync always sync init update \main_spimaster12_re $1\main_spimaster12_re[0:0] end - attribute \src "ls180.v:1049.11-1049.42" - process $proc$ls180.v:1049$3272 + attribute \src "ls180.v:1116.11-1116.42" + process $proc$ls180.v:1116$3513 assign { } { } assign $1\main_spimaster16_storage[7:0] 8'00000000 sync always sync init update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] end - attribute \src "ls180.v:1050.5-1050.31" - process $proc$ls180.v:1050$3273 + attribute \src "ls180.v:1117.5-1117.31" + process $proc$ls180.v:1117$3514 assign { } { } assign $1\main_spimaster17_re[0:0] 1'0 sync always sync init update \main_spimaster17_re $1\main_spimaster17_re[0:0] end - attribute \src "ls180.v:1054.5-1054.36" - process $proc$ls180.v:1054$3274 + attribute \src "ls180.v:1121.5-1121.36" + process $proc$ls180.v:1121$3515 assign { } { } assign $1\main_spimaster21_storage[0:0] 1'1 sync always sync init update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] end - attribute \src "ls180.v:1055.5-1055.31" - process $proc$ls180.v:1055$3275 + attribute \src "ls180.v:1122.5-1122.31" + process $proc$ls180.v:1122$3516 assign { } { } assign $1\main_spimaster22_re[0:0] 1'0 sync always sync init update \main_spimaster22_re $1\main_spimaster22_re[0:0] end - attribute \src "ls180.v:1056.5-1056.36" - process $proc$ls180.v:1056$3276 + attribute \src "ls180.v:1123.5-1123.36" + process $proc$ls180.v:1123$3517 assign { } { } assign $1\main_spimaster23_storage[0:0] 1'0 sync always sync init update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] end - attribute \src "ls180.v:1057.5-1057.31" - process $proc$ls180.v:1057$3277 + attribute \src "ls180.v:1124.5-1124.31" + process $proc$ls180.v:1124$3518 assign { } { } assign $1\main_spimaster24_re[0:0] 1'0 sync always sync init update \main_spimaster24_re $1\main_spimaster24_re[0:0] end - attribute \src "ls180.v:1058.5-1058.39" - process $proc$ls180.v:1058$3278 + attribute \src "ls180.v:1125.5-1125.39" + process $proc$ls180.v:1125$3519 assign { } { } assign $1\main_spimaster25_clk_enable[0:0] 1'0 sync always sync init update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] end - attribute \src "ls180.v:1059.5-1059.38" - process $proc$ls180.v:1059$3279 + attribute \src "ls180.v:1126.5-1126.38" + process $proc$ls180.v:1126$3520 assign { } { } assign $1\main_spimaster26_cs_enable[0:0] 1'0 sync always sync init update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] end - attribute \src "ls180.v:1060.11-1060.40" - process $proc$ls180.v:1060$3280 + attribute \src "ls180.v:1127.11-1127.40" + process $proc$ls180.v:1127$3521 assign { } { } assign $1\main_spimaster27_count[2:0] 3'000 sync always sync init update \main_spimaster27_count $1\main_spimaster27_count[2:0] end - attribute \src "ls180.v:1061.5-1061.39" - process $proc$ls180.v:1061$3281 + attribute \src "ls180.v:1128.5-1128.39" + process $proc$ls180.v:1128$3522 assign { } { } assign $1\main_spimaster28_mosi_latch[0:0] 1'0 sync always sync init update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] end - attribute \src "ls180.v:1062.5-1062.39" - process $proc$ls180.v:1062$3282 + attribute \src "ls180.v:1129.5-1129.39" + process $proc$ls180.v:1129$3523 assign { } { } assign $1\main_spimaster29_miso_latch[0:0] 1'0 sync always sync init update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] end - attribute \src "ls180.v:1063.12-1063.48" - process $proc$ls180.v:1063$3283 + attribute \src "ls180.v:1130.12-1130.48" + process $proc$ls180.v:1130$3524 assign { } { } assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 sync always sync init update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] end - attribute \src "ls180.v:1066.11-1066.44" - process $proc$ls180.v:1066$3284 + attribute \src "ls180.v:1133.11-1133.44" + process $proc$ls180.v:1133$3525 assign { } { } assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 sync always sync init update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] end - attribute \src "ls180.v:1067.11-1067.43" - process $proc$ls180.v:1067$3285 + attribute \src "ls180.v:1134.11-1134.43" + process $proc$ls180.v:1134$3526 assign { } { } assign $1\main_spimaster34_mosi_sel[2:0] 3'000 sync always sync init update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] end - attribute \src "ls180.v:1068.11-1068.44" - process $proc$ls180.v:1068$3286 + attribute \src "ls180.v:1135.11-1135.44" + process $proc$ls180.v:1135$3527 assign { } { } assign $1\main_spimaster35_miso_data[7:0] 8'00000000 sync always sync init update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] end - attribute \src "ls180.v:1071.5-1071.32" - process $proc$ls180.v:1071$3287 + attribute \src "ls180.v:1138.5-1138.32" + process $proc$ls180.v:1138$3528 assign { } { } assign $1\main_spisdcard_done0[0:0] 1'0 sync always sync init update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] end - attribute \src "ls180.v:1072.5-1072.30" - process $proc$ls180.v:1072$3288 + attribute \src "ls180.v:1139.5-1139.30" + process $proc$ls180.v:1139$3529 assign { } { } assign $1\main_spisdcard_irq[0:0] 1'0 sync always sync init update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] end - attribute \src "ls180.v:1074.11-1074.37" - process $proc$ls180.v:1074$3289 + attribute \src "ls180.v:114.11-114.55" + process $proc$ls180.v:114$3148 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + sync init + end + attribute \src "ls180.v:1141.11-1141.37" + process $proc$ls180.v:1141$3530 assign { } { } assign $1\main_spisdcard_miso[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] end - attribute \src "ls180.v:1078.5-1078.33" - process $proc$ls180.v:1078$3290 + attribute \src "ls180.v:1145.5-1145.33" + process $proc$ls180.v:1145$3531 assign { } { } assign $1\main_spisdcard_start1[0:0] 1'0 sync always sync init update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] end - attribute \src "ls180.v:1080.12-1080.50" - process $proc$ls180.v:1080$3291 + attribute \src "ls180.v:1147.12-1147.50" + process $proc$ls180.v:1147$3532 assign { } { } assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] end - attribute \src "ls180.v:1081.5-1081.37" - process $proc$ls180.v:1081$3292 + attribute \src "ls180.v:1148.5-1148.37" + process $proc$ls180.v:1148$3533 assign { } { } assign $1\main_spisdcard_control_re[0:0] 1'0 sync always sync init update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] end - attribute \src "ls180.v:1085.11-1085.45" - process $proc$ls180.v:1085$3293 + attribute \src "ls180.v:115.11-115.55" + process $proc$ls180.v:115$3149 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + sync init + end + attribute \src "ls180.v:1152.11-1152.45" + process $proc$ls180.v:1152$3534 assign { } { } assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] end - attribute \src "ls180.v:1086.5-1086.34" - process $proc$ls180.v:1086$3294 + attribute \src "ls180.v:1153.5-1153.34" + process $proc$ls180.v:1153$3535 assign { } { } assign $1\main_spisdcard_mosi_re[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] end - attribute \src "ls180.v:1090.5-1090.37" - process $proc$ls180.v:1090$3295 + attribute \src "ls180.v:1157.5-1157.37" + process $proc$ls180.v:1157$3536 assign { } { } assign $1\main_spisdcard_cs_storage[0:0] 1'1 sync always sync init update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] end - attribute \src "ls180.v:1091.5-1091.32" - process $proc$ls180.v:1091$3296 + attribute \src "ls180.v:1158.5-1158.32" + process $proc$ls180.v:1158$3537 assign { } { } assign $1\main_spisdcard_cs_re[0:0] 1'0 sync always sync init update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] end - attribute \src "ls180.v:1092.5-1092.43" - process $proc$ls180.v:1092$3297 + attribute \src "ls180.v:1159.5-1159.43" + process $proc$ls180.v:1159$3538 assign { } { } assign $1\main_spisdcard_loopback_storage[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] end - attribute \src "ls180.v:1093.5-1093.38" - process $proc$ls180.v:1093$3298 + attribute \src "ls180.v:1160.5-1160.38" + process $proc$ls180.v:1160$3539 assign { } { } assign $1\main_spisdcard_loopback_re[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] end - attribute \src "ls180.v:1094.5-1094.37" - process $proc$ls180.v:1094$3299 + attribute \src "ls180.v:1161.5-1161.37" + process $proc$ls180.v:1161$3540 assign { } { } assign $1\main_spisdcard_clk_enable[0:0] 1'0 sync always sync init update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] end - attribute \src "ls180.v:1095.5-1095.36" - process $proc$ls180.v:1095$3300 + attribute \src "ls180.v:1162.5-1162.36" + process $proc$ls180.v:1162$3541 assign { } { } assign $1\main_spisdcard_cs_enable[0:0] 1'0 sync always sync init update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] end - attribute \src "ls180.v:1096.11-1096.38" - process $proc$ls180.v:1096$3301 + attribute \src "ls180.v:1163.11-1163.38" + process $proc$ls180.v:1163$3542 assign { } { } assign $1\main_spisdcard_count[2:0] 3'000 sync always sync init update \main_spisdcard_count $1\main_spisdcard_count[2:0] end - attribute \src "ls180.v:1097.5-1097.37" - process $proc$ls180.v:1097$3302 + attribute \src "ls180.v:1164.5-1164.37" + process $proc$ls180.v:1164$3543 assign { } { } assign $1\main_spisdcard_mosi_latch[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] end - attribute \src "ls180.v:1098.5-1098.37" - process $proc$ls180.v:1098$3303 + attribute \src "ls180.v:1165.5-1165.37" + process $proc$ls180.v:1165$3544 assign { } { } assign $1\main_spisdcard_miso_latch[0:0] 1'0 sync always sync init update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] end - attribute \src "ls180.v:1099.12-1099.47" - process $proc$ls180.v:1099$3304 + attribute \src "ls180.v:1166.12-1166.47" + process $proc$ls180.v:1166$3545 assign { } { } assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] end - attribute \src "ls180.v:1102.11-1102.42" - process $proc$ls180.v:1102$3305 + attribute \src "ls180.v:1169.11-1169.42" + process $proc$ls180.v:1169$3546 assign { } { } assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] end - attribute \src "ls180.v:1103.11-1103.41" - process $proc$ls180.v:1103$3306 + attribute \src "ls180.v:1170.11-1170.41" + process $proc$ls180.v:1170$3547 assign { } { } assign $1\main_spisdcard_mosi_sel[2:0] 3'000 sync always sync init update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] end - attribute \src "ls180.v:1104.11-1104.42" - process $proc$ls180.v:1104$3307 + attribute \src "ls180.v:1171.11-1171.42" + process $proc$ls180.v:1171$3548 assign { } { } assign $1\main_spisdcard_miso_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] end - attribute \src "ls180.v:1105.12-1105.45" - process $proc$ls180.v:1105$3308 + attribute \src "ls180.v:1172.12-1172.45" + process $proc$ls180.v:1172$3549 assign { } { } assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 sync always sync init update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] end - attribute \src "ls180.v:1106.5-1106.30" - process $proc$ls180.v:1106$3309 + attribute \src "ls180.v:1173.5-1173.30" + process $proc$ls180.v:1173$3550 assign { } { } assign $1\main_spimaster1_re[0:0] 1'0 sync always sync init update \main_spimaster1_re $1\main_spimaster1_re[0:0] end - attribute \src "ls180.v:1108.12-1108.30" - process $proc$ls180.v:1108$3310 + attribute \src "ls180.v:1175.12-1175.30" + process $proc$ls180.v:1175$3551 assign { } { } assign $1\main_dummy[23:0] 24'000000000000000000000000 sync always sync init update \main_dummy $1\main_dummy[23:0] end - attribute \src "ls180.v:1112.12-1112.37" - process $proc$ls180.v:1112$3311 + attribute \src "ls180.v:1179.12-1179.37" + process $proc$ls180.v:1179$3552 assign { } { } assign $1\main_pwm0_counter[31:0] 0 sync always sync init update \main_pwm0_counter $1\main_pwm0_counter[31:0] end - attribute \src "ls180.v:1113.5-1113.36" - process $proc$ls180.v:1113$3312 + attribute \src "ls180.v:1180.5-1180.36" + process $proc$ls180.v:1180$3553 assign { } { } assign $1\main_pwm0_enable_storage[0:0] 1'0 sync always sync init update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] end - attribute \src "ls180.v:1114.5-1114.31" - process $proc$ls180.v:1114$3313 + attribute \src "ls180.v:1181.5-1181.31" + process $proc$ls180.v:1181$3554 assign { } { } assign $1\main_pwm0_enable_re[0:0] 1'0 sync always sync init update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] end - attribute \src "ls180.v:1115.12-1115.43" - process $proc$ls180.v:1115$3314 + attribute \src "ls180.v:1182.12-1182.43" + process $proc$ls180.v:1182$3555 assign { } { } assign $1\main_pwm0_width_storage[31:0] 0 sync always sync init update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] end - attribute \src "ls180.v:1116.5-1116.30" - process $proc$ls180.v:1116$3315 + attribute \src "ls180.v:1183.5-1183.30" + process $proc$ls180.v:1183$3556 assign { } { } assign $1\main_pwm0_width_re[0:0] 1'0 sync always sync init update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] end - attribute \src "ls180.v:1117.12-1117.44" - process $proc$ls180.v:1117$3316 + attribute \src "ls180.v:1184.12-1184.44" + process $proc$ls180.v:1184$3557 assign { } { } assign $1\main_pwm0_period_storage[31:0] 0 sync always sync init update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] end - attribute \src "ls180.v:1118.5-1118.31" - process $proc$ls180.v:1118$3317 + attribute \src "ls180.v:1185.5-1185.31" + process $proc$ls180.v:1185$3558 assign { } { } assign $1\main_pwm0_period_re[0:0] 1'0 sync always sync init update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] end - attribute \src "ls180.v:112.5-112.49" - process $proc$ls180.v:112$2905 - assign { } { } - assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - end - attribute \src "ls180.v:1122.12-1122.37" - process $proc$ls180.v:1122$3318 + attribute \src "ls180.v:1189.12-1189.37" + process $proc$ls180.v:1189$3559 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always sync init update \main_pwm1_counter $1\main_pwm1_counter[31:0] end - attribute \src "ls180.v:1123.5-1123.36" - process $proc$ls180.v:1123$3319 + attribute \src "ls180.v:1190.5-1190.36" + process $proc$ls180.v:1190$3560 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always sync init update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end - attribute \src "ls180.v:1124.5-1124.31" - process $proc$ls180.v:1124$3320 + attribute \src "ls180.v:1191.5-1191.31" + process $proc$ls180.v:1191$3561 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always sync init update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end - attribute \src "ls180.v:1125.12-1125.43" - process $proc$ls180.v:1125$3321 + attribute \src "ls180.v:1192.12-1192.43" + process $proc$ls180.v:1192$3562 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always sync init update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end - attribute \src "ls180.v:1126.5-1126.30" - process $proc$ls180.v:1126$3322 + attribute \src "ls180.v:1193.5-1193.30" + process $proc$ls180.v:1193$3563 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always sync init update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end - attribute \src "ls180.v:1127.12-1127.44" - process $proc$ls180.v:1127$3323 + attribute \src "ls180.v:1194.12-1194.44" + process $proc$ls180.v:1194$3564 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always sync init update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end - attribute \src "ls180.v:1128.5-1128.31" - process $proc$ls180.v:1128$3324 + attribute \src "ls180.v:1195.5-1195.31" + process $proc$ls180.v:1195$3565 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always sync init update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end - attribute \src "ls180.v:1132.11-1132.34" - process $proc$ls180.v:1132$3325 + attribute \src "ls180.v:1199.11-1199.34" + process $proc$ls180.v:1199$3566 assign { } { } assign $1\main_i2c_storage[2:0] 3'000 sync always sync init update \main_i2c_storage $1\main_i2c_storage[2:0] end - attribute \src "ls180.v:1133.5-1133.23" - process $proc$ls180.v:1133$3326 + attribute \src "ls180.v:1200.5-1200.23" + process $proc$ls180.v:1200$3567 assign { } { } assign $1\main_i2c_re[0:0] 1'0 sync always sync init update \main_i2c_re $1\main_i2c_re[0:0] end - attribute \src "ls180.v:1139.11-1139.46" - process $proc$ls180.v:1139$3327 + attribute \src "ls180.v:1206.11-1206.46" + process $proc$ls180.v:1206$3568 assign { } { } assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always sync init update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end - attribute \src "ls180.v:114.5-114.49" - process $proc$ls180.v:114$2906 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - sync init - end - attribute \src "ls180.v:1140.5-1140.33" - process $proc$ls180.v:1140$3328 + attribute \src "ls180.v:1207.5-1207.33" + process $proc$ls180.v:1207$3569 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always sync init update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end - attribute \src "ls180.v:1142.5-1142.35" - process $proc$ls180.v:1142$3329 + attribute \src "ls180.v:1209.5-1209.35" + process $proc$ls180.v:1209$3570 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end - attribute \src "ls180.v:1144.11-1144.41" - process $proc$ls180.v:1144$3330 + attribute \src "ls180.v:1211.11-1211.41" + process $proc$ls180.v:1211$3571 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always sync init update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end - attribute \src "ls180.v:1145.5-1145.35" - process $proc$ls180.v:1145$3331 + attribute \src "ls180.v:1212.5-1212.35" + process $proc$ls180.v:1212$3572 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:1146.5-1146.36" - process $proc$ls180.v:1146$3332 + attribute \src "ls180.v:1213.5-1213.36" + process $proc$ls180.v:1213$3573 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end - attribute \src "ls180.v:1150.5-1150.40" - process $proc$ls180.v:1150$3333 + attribute \src "ls180.v:1217.5-1217.40" + process $proc$ls180.v:1217$3574 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] sync init end - attribute \src "ls180.v:1155.5-1155.48" - process $proc$ls180.v:1155$3334 + attribute \src "ls180.v:1222.5-1222.48" + process $proc$ls180.v:1222$3575 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1156.5-1156.50" - process $proc$ls180.v:1156$3335 + attribute \src "ls180.v:1223.5-1223.50" + process $proc$ls180.v:1223$3576 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1157.5-1157.51" - process $proc$ls180.v:1157$3336 + attribute \src "ls180.v:1224.5-1224.51" + process $proc$ls180.v:1224$3577 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1158.11-1158.57" - process $proc$ls180.v:1158$3337 + attribute \src "ls180.v:1225.11-1225.57" + process $proc$ls180.v:1225$3578 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1159.5-1159.52" - process $proc$ls180.v:1159$3338 + attribute \src "ls180.v:1226.5-1226.52" + process $proc$ls180.v:1226$3579 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1160.11-1160.39" - process $proc$ls180.v:1160$3339 + attribute \src "ls180.v:1227.11-1227.39" + process $proc$ls180.v:1227$3580 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end - attribute \src "ls180.v:1165.5-1165.48" - process $proc$ls180.v:1165$3340 + attribute \src "ls180.v:1232.5-1232.48" + process $proc$ls180.v:1232$3581 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1166.5-1166.50" - process $proc$ls180.v:1166$3341 + attribute \src "ls180.v:1233.5-1233.50" + process $proc$ls180.v:1233$3582 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1167.5-1167.51" - process $proc$ls180.v:1167$3342 + attribute \src "ls180.v:1234.5-1234.51" + process $proc$ls180.v:1234$3583 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1168.11-1168.57" - process $proc$ls180.v:1168$3343 + attribute \src "ls180.v:1235.11-1235.57" + process $proc$ls180.v:1235$3584 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1169.5-1169.52" - process $proc$ls180.v:1169$3344 + attribute \src "ls180.v:1236.5-1236.52" + process $proc$ls180.v:1236$3585 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1170.5-1170.38" - process $proc$ls180.v:1170$3345 + attribute \src "ls180.v:1237.5-1237.38" + process $proc$ls180.v:1237$3586 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end - attribute \src "ls180.v:1171.5-1171.38" - process $proc$ls180.v:1171$3346 + attribute \src "ls180.v:1238.5-1238.38" + process $proc$ls180.v:1238$3587 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end - attribute \src "ls180.v:1172.5-1172.37" - process $proc$ls180.v:1172$3347 + attribute \src "ls180.v:1239.5-1239.37" + process $proc$ls180.v:1239$3588 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end - attribute \src "ls180.v:1173.11-1173.51" - process $proc$ls180.v:1173$3348 + attribute \src "ls180.v:1240.11-1240.51" + process $proc$ls180.v:1240$3589 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end - attribute \src "ls180.v:1174.5-1174.32" - process $proc$ls180.v:1174$3349 + attribute \src "ls180.v:1241.5-1241.32" + process $proc$ls180.v:1241$3590 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end - attribute \src "ls180.v:1175.11-1175.39" - process $proc$ls180.v:1175$3350 + attribute \src "ls180.v:1242.11-1242.39" + process $proc$ls180.v:1242$3591 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end - attribute \src "ls180.v:1178.5-1178.49" - process $proc$ls180.v:1178$3351 + attribute \src "ls180.v:1245.5-1245.49" + process $proc$ls180.v:1245$3592 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1179.5-1179.48" - process $proc$ls180.v:1179$3352 + attribute \src "ls180.v:1246.5-1246.48" + process $proc$ls180.v:1246$3593 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1180.5-1180.55" - process $proc$ls180.v:1180$3353 + attribute \src "ls180.v:1247.5-1247.55" + process $proc$ls180.v:1247$3594 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1182.5-1182.57" - process $proc$ls180.v:1182$3354 + attribute \src "ls180.v:1249.5-1249.57" + process $proc$ls180.v:1249$3595 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1183.5-1183.58" - process $proc$ls180.v:1183$3355 + attribute \src "ls180.v:1250.5-1250.58" + process $proc$ls180.v:1250$3596 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1185.11-1185.64" - process $proc$ls180.v:1185$3356 + attribute \src "ls180.v:1252.11-1252.64" + process $proc$ls180.v:1252$3597 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1186.5-1186.59" - process $proc$ls180.v:1186$3357 + attribute \src "ls180.v:1253.5-1253.59" + process $proc$ls180.v:1253$3598 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1188.5-1188.48" - process $proc$ls180.v:1188$3358 + attribute \src "ls180.v:1255.5-1255.48" + process $proc$ls180.v:1255$3599 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1189.5-1189.50" - process $proc$ls180.v:1189$3359 + attribute \src "ls180.v:1256.5-1256.50" + process $proc$ls180.v:1256$3600 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1190.5-1190.51" - process $proc$ls180.v:1190$3360 + attribute \src "ls180.v:1257.5-1257.51" + process $proc$ls180.v:1257$3601 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1191.11-1191.57" - process $proc$ls180.v:1191$3361 + attribute \src "ls180.v:1258.11-1258.57" + process $proc$ls180.v:1258$3602 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1192.5-1192.52" - process $proc$ls180.v:1192$3362 + attribute \src "ls180.v:1259.5-1259.52" + process $proc$ls180.v:1259$3603 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1193.5-1193.38" - process $proc$ls180.v:1193$3363 + attribute \src "ls180.v:1260.5-1260.38" + process $proc$ls180.v:1260$3604 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end - attribute \src "ls180.v:1194.5-1194.38" - process $proc$ls180.v:1194$3364 + attribute \src "ls180.v:1261.5-1261.38" + process $proc$ls180.v:1261$3605 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end - attribute \src "ls180.v:1195.5-1195.37" - process $proc$ls180.v:1195$3365 + attribute \src "ls180.v:1262.5-1262.37" + process $proc$ls180.v:1262$3606 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end - attribute \src "ls180.v:1196.11-1196.53" - process $proc$ls180.v:1196$3366 + attribute \src "ls180.v:1263.11-1263.53" + process $proc$ls180.v:1263$3607 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end - attribute \src "ls180.v:1197.5-1197.40" - process $proc$ls180.v:1197$3367 + attribute \src "ls180.v:1264.5-1264.40" + process $proc$ls180.v:1264$3608 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end - attribute \src "ls180.v:1198.5-1198.40" - process $proc$ls180.v:1198$3368 + attribute \src "ls180.v:1265.5-1265.40" + process $proc$ls180.v:1265$3609 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end - attribute \src "ls180.v:1199.5-1199.39" - process $proc$ls180.v:1199$3369 + attribute \src "ls180.v:1266.5-1266.39" + process $proc$ls180.v:1266$3610 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end - attribute \src "ls180.v:1200.11-1200.53" - process $proc$ls180.v:1200$3370 + attribute \src "ls180.v:1267.11-1267.53" + process $proc$ls180.v:1267$3611 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end - attribute \src "ls180.v:1201.11-1201.55" - process $proc$ls180.v:1201$3371 + attribute \src "ls180.v:1268.11-1268.55" + process $proc$ls180.v:1268$3612 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end - attribute \src "ls180.v:1202.12-1202.48" - process $proc$ls180.v:1202$3372 + attribute \src "ls180.v:1269.12-1269.48" + process $proc$ls180.v:1269$3613 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always sync init update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end - attribute \src "ls180.v:1203.11-1203.39" - process $proc$ls180.v:1203$3373 + attribute \src "ls180.v:1270.11-1270.39" + process $proc$ls180.v:1270$3614 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end - attribute \src "ls180.v:1205.5-1205.46" - process $proc$ls180.v:1205$3374 + attribute \src "ls180.v:1272.5-1272.46" + process $proc$ls180.v:1272$3615 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1216.5-1216.53" - process $proc$ls180.v:1216$3375 + attribute \src "ls180.v:1283.5-1283.53" + process $proc$ls180.v:1283$3616 assign { } { } assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end - attribute \src "ls180.v:1221.5-1221.36" - process $proc$ls180.v:1221$3376 + attribute \src "ls180.v:1288.5-1288.36" + process $proc$ls180.v:1288$3617 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end - attribute \src "ls180.v:1224.5-1224.53" - process $proc$ls180.v:1224$3377 + attribute \src "ls180.v:1291.5-1291.53" + process $proc$ls180.v:1291$3618 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1225.5-1225.52" - process $proc$ls180.v:1225$3378 + attribute \src "ls180.v:1292.5-1292.52" + process $proc$ls180.v:1292$3619 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1229.5-1229.55" - process $proc$ls180.v:1229$3379 + attribute \src "ls180.v:1296.5-1296.55" + process $proc$ls180.v:1296$3620 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end - attribute \src "ls180.v:1230.5-1230.54" - process $proc$ls180.v:1230$3380 + attribute \src "ls180.v:1297.5-1297.54" + process $proc$ls180.v:1297$3621 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end - attribute \src "ls180.v:1231.11-1231.68" - process $proc$ls180.v:1231$3381 + attribute \src "ls180.v:1298.11-1298.68" + process $proc$ls180.v:1298$3622 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1232.11-1232.81" - process $proc$ls180.v:1232$3382 + attribute \src "ls180.v:1299.11-1299.81" + process $proc$ls180.v:1299$3623 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1233.11-1233.54" - process $proc$ls180.v:1233$3383 + attribute \src "ls180.v:1300.11-1300.54" + process $proc$ls180.v:1300$3624 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end - attribute \src "ls180.v:1235.5-1235.53" - process $proc$ls180.v:1235$3384 + attribute \src "ls180.v:1302.5-1302.53" + process $proc$ls180.v:1302$3625 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1246.5-1246.49" - process $proc$ls180.v:1246$3385 + attribute \src "ls180.v:1313.5-1313.49" + process $proc$ls180.v:1313$3626 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end - attribute \src "ls180.v:1248.5-1248.49" - process $proc$ls180.v:1248$3386 + attribute \src "ls180.v:1315.5-1315.49" + process $proc$ls180.v:1315$3627 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end - attribute \src "ls180.v:1249.5-1249.48" - process $proc$ls180.v:1249$3387 + attribute \src "ls180.v:1316.5-1316.48" + process $proc$ls180.v:1316$3628 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end - attribute \src "ls180.v:1250.11-1250.62" - process $proc$ls180.v:1250$3388 + attribute \src "ls180.v:1317.11-1317.62" + process $proc$ls180.v:1317$3629 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1251.5-1251.38" - process $proc$ls180.v:1251$3389 + attribute \src "ls180.v:1318.5-1318.38" + process $proc$ls180.v:1318$3630 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end - attribute \src "ls180.v:1256.5-1256.49" - process $proc$ls180.v:1256$3390 + attribute \src "ls180.v:1323.5-1323.49" + process $proc$ls180.v:1323$3631 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1257.5-1257.51" - process $proc$ls180.v:1257$3391 + attribute \src "ls180.v:1324.5-1324.51" + process $proc$ls180.v:1324$3632 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1258.5-1258.52" - process $proc$ls180.v:1258$3392 + attribute \src "ls180.v:1325.5-1325.52" + process $proc$ls180.v:1325$3633 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1259.11-1259.58" - process $proc$ls180.v:1259$3393 + attribute \src "ls180.v:1326.11-1326.58" + process $proc$ls180.v:1326$3634 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1260.5-1260.53" - process $proc$ls180.v:1260$3394 + attribute \src "ls180.v:1327.5-1327.53" + process $proc$ls180.v:1327$3635 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1261.5-1261.39" - process $proc$ls180.v:1261$3395 + attribute \src "ls180.v:1328.5-1328.39" + process $proc$ls180.v:1328$3636 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end - attribute \src "ls180.v:1262.5-1262.39" - process $proc$ls180.v:1262$3396 + attribute \src "ls180.v:1329.5-1329.39" + process $proc$ls180.v:1329$3637 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end - attribute \src "ls180.v:1263.5-1263.39" - process $proc$ls180.v:1263$3397 + attribute \src "ls180.v:1330.5-1330.39" + process $proc$ls180.v:1330$3638 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end - attribute \src "ls180.v:1264.5-1264.38" - process $proc$ls180.v:1264$3398 + attribute \src "ls180.v:1331.5-1331.38" + process $proc$ls180.v:1331$3639 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end - attribute \src "ls180.v:1265.11-1265.52" - process $proc$ls180.v:1265$3399 + attribute \src "ls180.v:1332.11-1332.52" + process $proc$ls180.v:1332$3640 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end - attribute \src "ls180.v:1266.5-1266.33" - process $proc$ls180.v:1266$3400 + attribute \src "ls180.v:1333.5-1333.33" + process $proc$ls180.v:1333$3641 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always sync init update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end - attribute \src "ls180.v:1267.11-1267.40" - process $proc$ls180.v:1267$3401 + attribute \src "ls180.v:1334.11-1334.40" + process $proc$ls180.v:1334$3642 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end - attribute \src "ls180.v:1268.5-1268.50" - process $proc$ls180.v:1268$3402 + attribute \src "ls180.v:1335.5-1335.50" + process $proc$ls180.v:1335$3643 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] sync init end - attribute \src "ls180.v:1270.5-1270.50" - process $proc$ls180.v:1270$3403 + attribute \src "ls180.v:1337.5-1337.50" + process $proc$ls180.v:1337$3644 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1271.5-1271.49" - process $proc$ls180.v:1271$3404 + attribute \src "ls180.v:1338.5-1338.49" + process $proc$ls180.v:1338$3645 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1272.5-1272.56" - process $proc$ls180.v:1272$3405 + attribute \src "ls180.v:1339.5-1339.56" + process $proc$ls180.v:1339$3646 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1273.5-1273.58" - process $proc$ls180.v:1273$3406 + attribute \src "ls180.v:1340.5-1340.58" + process $proc$ls180.v:1340$3647 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] sync init end - attribute \src "ls180.v:1274.5-1274.58" - process $proc$ls180.v:1274$3407 + attribute \src "ls180.v:1341.5-1341.58" + process $proc$ls180.v:1341$3648 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1275.5-1275.59" - process $proc$ls180.v:1275$3408 + attribute \src "ls180.v:1342.5-1342.59" + process $proc$ls180.v:1342$3649 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1276.11-1276.65" - process $proc$ls180.v:1276$3409 + attribute \src "ls180.v:1343.11-1343.65" + process $proc$ls180.v:1343$3650 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] sync init end - attribute \src "ls180.v:1277.11-1277.65" - process $proc$ls180.v:1277$3410 + attribute \src "ls180.v:1344.11-1344.65" + process $proc$ls180.v:1344$3651 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1278.5-1278.60" - process $proc$ls180.v:1278$3411 + attribute \src "ls180.v:1345.5-1345.60" + process $proc$ls180.v:1345$3652 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1279.5-1279.34" - process $proc$ls180.v:1279$3412 + attribute \src "ls180.v:1346.5-1346.34" + process $proc$ls180.v:1346$3653 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always sync init update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end - attribute \src "ls180.v:1280.5-1280.34" - process $proc$ls180.v:1280$3413 + attribute \src "ls180.v:1347.5-1347.34" + process $proc$ls180.v:1347$3654 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end - attribute \src "ls180.v:1281.5-1281.34" - process $proc$ls180.v:1281$3414 + attribute \src "ls180.v:1348.5-1348.34" + process $proc$ls180.v:1348$3655 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always sync init update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end - attribute \src "ls180.v:1283.5-1283.47" - process $proc$ls180.v:1283$3415 + attribute \src "ls180.v:1350.5-1350.47" + process $proc$ls180.v:1350$3656 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1294.5-1294.54" - process $proc$ls180.v:1294$3416 + attribute \src "ls180.v:1361.5-1361.54" + process $proc$ls180.v:1361$3657 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end - attribute \src "ls180.v:1299.5-1299.37" - process $proc$ls180.v:1299$3417 + attribute \src "ls180.v:1366.5-1366.37" + process $proc$ls180.v:1366$3658 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end - attribute \src "ls180.v:1302.5-1302.54" - process $proc$ls180.v:1302$3418 + attribute \src "ls180.v:1369.5-1369.54" + process $proc$ls180.v:1369$3659 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1303.5-1303.53" - process $proc$ls180.v:1303$3419 + attribute \src "ls180.v:1370.5-1370.53" + process $proc$ls180.v:1370$3660 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1307.5-1307.56" - process $proc$ls180.v:1307$3420 + attribute \src "ls180.v:1374.5-1374.56" + process $proc$ls180.v:1374$3661 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end - attribute \src "ls180.v:1308.5-1308.55" - process $proc$ls180.v:1308$3421 + attribute \src "ls180.v:1375.5-1375.55" + process $proc$ls180.v:1375$3662 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end - attribute \src "ls180.v:1309.11-1309.69" - process $proc$ls180.v:1309$3422 + attribute \src "ls180.v:1376.11-1376.69" + process $proc$ls180.v:1376$3663 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1310.11-1310.82" - process $proc$ls180.v:1310$3423 + attribute \src "ls180.v:1377.11-1377.82" + process $proc$ls180.v:1377$3664 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1311.11-1311.55" - process $proc$ls180.v:1311$3424 + attribute \src "ls180.v:1378.11-1378.55" + process $proc$ls180.v:1378$3665 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end - attribute \src "ls180.v:1313.5-1313.54" - process $proc$ls180.v:1313$3425 + attribute \src "ls180.v:1380.5-1380.54" + process $proc$ls180.v:1380$3666 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1324.5-1324.50" - process $proc$ls180.v:1324$3426 + attribute \src "ls180.v:1391.5-1391.50" + process $proc$ls180.v:1391$3667 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end - attribute \src "ls180.v:1326.5-1326.50" - process $proc$ls180.v:1326$3427 + attribute \src "ls180.v:1393.5-1393.50" + process $proc$ls180.v:1393$3668 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end - attribute \src "ls180.v:1327.5-1327.49" - process $proc$ls180.v:1327$3428 + attribute \src "ls180.v:1394.5-1394.49" + process $proc$ls180.v:1394$3669 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end - attribute \src "ls180.v:1328.11-1328.63" - process $proc$ls180.v:1328$3429 + attribute \src "ls180.v:1395.11-1395.63" + process $proc$ls180.v:1395$3670 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1329.5-1329.39" - process $proc$ls180.v:1329$3430 + attribute \src "ls180.v:1396.5-1396.39" + process $proc$ls180.v:1396$3671 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end - attribute \src "ls180.v:1332.5-1332.50" - process $proc$ls180.v:1332$3431 + attribute \src "ls180.v:1399.5-1399.50" + process $proc$ls180.v:1399$3672 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1333.5-1333.49" - process $proc$ls180.v:1333$3432 + attribute \src "ls180.v:1400.5-1400.49" + process $proc$ls180.v:1400$3673 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1334.5-1334.56" - process $proc$ls180.v:1334$3433 + attribute \src "ls180.v:1401.5-1401.56" + process $proc$ls180.v:1401$3674 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1336.5-1336.58" - process $proc$ls180.v:1336$3434 + attribute \src "ls180.v:1403.5-1403.58" + process $proc$ls180.v:1403$3675 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1337.5-1337.59" - process $proc$ls180.v:1337$3435 + attribute \src "ls180.v:1404.5-1404.59" + process $proc$ls180.v:1404$3676 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1339.11-1339.65" - process $proc$ls180.v:1339$3436 + attribute \src "ls180.v:1406.11-1406.65" + process $proc$ls180.v:1406$3677 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1340.5-1340.60" - process $proc$ls180.v:1340$3437 + attribute \src "ls180.v:1407.5-1407.60" + process $proc$ls180.v:1407$3678 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1342.5-1342.49" - process $proc$ls180.v:1342$3438 + attribute \src "ls180.v:1409.5-1409.49" + process $proc$ls180.v:1409$3679 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1343.5-1343.51" - process $proc$ls180.v:1343$3439 + attribute \src "ls180.v:1410.5-1410.51" + process $proc$ls180.v:1410$3680 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1344.5-1344.52" - process $proc$ls180.v:1344$3440 + attribute \src "ls180.v:1411.5-1411.52" + process $proc$ls180.v:1411$3681 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1345.11-1345.58" - process $proc$ls180.v:1345$3441 + attribute \src "ls180.v:1412.11-1412.58" + process $proc$ls180.v:1412$3682 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1346.5-1346.53" - process $proc$ls180.v:1346$3442 + attribute \src "ls180.v:1413.5-1413.53" + process $proc$ls180.v:1413$3683 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1347.5-1347.39" - process $proc$ls180.v:1347$3443 + attribute \src "ls180.v:1414.5-1414.39" + process $proc$ls180.v:1414$3684 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end - attribute \src "ls180.v:1348.5-1348.39" - process $proc$ls180.v:1348$3444 + attribute \src "ls180.v:1415.5-1415.39" + process $proc$ls180.v:1415$3685 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end - attribute \src "ls180.v:1349.5-1349.38" - process $proc$ls180.v:1349$3445 + attribute \src "ls180.v:1416.5-1416.38" + process $proc$ls180.v:1416$3686 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end - attribute \src "ls180.v:1350.11-1350.61" - process $proc$ls180.v:1350$3446 + attribute \src "ls180.v:1417.11-1417.61" + process $proc$ls180.v:1417$3687 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end - attribute \src "ls180.v:1351.5-1351.41" - process $proc$ls180.v:1351$3447 + attribute \src "ls180.v:1418.5-1418.41" + process $proc$ls180.v:1418$3688 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end - attribute \src "ls180.v:1352.5-1352.41" - process $proc$ls180.v:1352$3448 + attribute \src "ls180.v:1419.5-1419.41" + process $proc$ls180.v:1419$3689 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end - attribute \src "ls180.v:1353.5-1353.41" - process $proc$ls180.v:1353$3449 + attribute \src "ls180.v:1420.5-1420.41" + process $proc$ls180.v:1420$3690 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] sync init end - attribute \src "ls180.v:1354.5-1354.40" - process $proc$ls180.v:1354$3450 + attribute \src "ls180.v:1421.5-1421.40" + process $proc$ls180.v:1421$3691 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end - attribute \src "ls180.v:1355.11-1355.54" - process $proc$ls180.v:1355$3451 + attribute \src "ls180.v:1422.11-1422.54" + process $proc$ls180.v:1422$3692 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end - attribute \src "ls180.v:1356.11-1356.56" - process $proc$ls180.v:1356$3452 + attribute \src "ls180.v:1423.11-1423.56" + process $proc$ls180.v:1423$3693 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end - attribute \src "ls180.v:1357.5-1357.33" - process $proc$ls180.v:1357$3453 + attribute \src "ls180.v:1424.5-1424.33" + process $proc$ls180.v:1424$3694 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always sync init update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end - attribute \src "ls180.v:1358.12-1358.49" - process $proc$ls180.v:1358$3454 + attribute \src "ls180.v:1425.12-1425.49" + process $proc$ls180.v:1425$3695 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always sync init update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end - attribute \src "ls180.v:1359.11-1359.41" - process $proc$ls180.v:1359$3455 + attribute \src "ls180.v:1426.11-1426.41" + process $proc$ls180.v:1426$3696 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end - attribute \src "ls180.v:1361.5-1361.48" - process $proc$ls180.v:1361$3456 + attribute \src "ls180.v:1428.5-1428.48" + process $proc$ls180.v:1428$3697 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1372.5-1372.55" - process $proc$ls180.v:1372$3457 + attribute \src "ls180.v:1439.5-1439.55" + process $proc$ls180.v:1439$3698 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end - attribute \src "ls180.v:1377.5-1377.38" - process $proc$ls180.v:1377$3458 + attribute \src "ls180.v:1444.5-1444.38" + process $proc$ls180.v:1444$3699 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end - attribute \src "ls180.v:1380.5-1380.55" - process $proc$ls180.v:1380$3459 + attribute \src "ls180.v:1447.5-1447.55" + process $proc$ls180.v:1447$3700 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1381.5-1381.54" - process $proc$ls180.v:1381$3460 + attribute \src "ls180.v:1448.5-1448.54" + process $proc$ls180.v:1448$3701 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1385.5-1385.57" - process $proc$ls180.v:1385$3461 + attribute \src "ls180.v:1452.5-1452.57" + process $proc$ls180.v:1452$3702 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end - attribute \src "ls180.v:1386.5-1386.56" - process $proc$ls180.v:1386$3462 + attribute \src "ls180.v:1453.5-1453.56" + process $proc$ls180.v:1453$3703 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end - attribute \src "ls180.v:1387.11-1387.70" - process $proc$ls180.v:1387$3463 + attribute \src "ls180.v:1454.11-1454.70" + process $proc$ls180.v:1454$3704 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1388.11-1388.83" - process $proc$ls180.v:1388$3464 + attribute \src "ls180.v:1455.11-1455.83" + process $proc$ls180.v:1455$3705 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end - attribute \src "ls180.v:1389.5-1389.50" - process $proc$ls180.v:1389$3465 + attribute \src "ls180.v:1456.5-1456.50" + process $proc$ls180.v:1456$3706 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end - attribute \src "ls180.v:1391.5-1391.55" - process $proc$ls180.v:1391$3466 + attribute \src "ls180.v:1458.5-1458.55" + process $proc$ls180.v:1458$3707 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end - attribute \src "ls180.v:1402.5-1402.51" - process $proc$ls180.v:1402$3467 + attribute \src "ls180.v:1469.5-1469.51" + process $proc$ls180.v:1469$3708 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end - attribute \src "ls180.v:1404.5-1404.51" - process $proc$ls180.v:1404$3468 + attribute \src "ls180.v:1471.5-1471.51" + process $proc$ls180.v:1471$3709 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end - attribute \src "ls180.v:1405.5-1405.50" - process $proc$ls180.v:1405$3469 + attribute \src "ls180.v:1472.5-1472.50" + process $proc$ls180.v:1472$3710 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end - attribute \src "ls180.v:1406.11-1406.64" - process $proc$ls180.v:1406$3470 + attribute \src "ls180.v:1473.11-1473.64" + process $proc$ls180.v:1473$3711 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1407.5-1407.40" - process $proc$ls180.v:1407$3471 + attribute \src "ls180.v:1474.5-1474.40" + process $proc$ls180.v:1474$3712 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end - attribute \src "ls180.v:1409.5-1409.35" - process $proc$ls180.v:1409$3472 + attribute \src "ls180.v:1476.5-1476.35" + process $proc$ls180.v:1476$3713 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always sync init update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end - attribute \src "ls180.v:1412.11-1412.42" - process $proc$ls180.v:1412$3473 + attribute \src "ls180.v:1479.11-1479.42" + process $proc$ls180.v:1479$3714 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always sync init update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:1425.12-1425.52" - process $proc$ls180.v:1425$3474 + attribute \src "ls180.v:1492.12-1492.52" + process $proc$ls180.v:1492$3715 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end - attribute \src "ls180.v:1426.5-1426.39" - process $proc$ls180.v:1426$3475 + attribute \src "ls180.v:1493.5-1493.39" + process $proc$ls180.v:1493$3716 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end - attribute \src "ls180.v:1427.12-1427.51" - process $proc$ls180.v:1427$3476 + attribute \src "ls180.v:1494.12-1494.51" + process $proc$ls180.v:1494$3717 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end - attribute \src "ls180.v:1428.5-1428.38" - process $proc$ls180.v:1428$3477 + attribute \src "ls180.v:1495.5-1495.38" + process $proc$ls180.v:1495$3718 assign { } { } assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end - attribute \src "ls180.v:1432.5-1432.34" - process $proc$ls180.v:1432$3478 + attribute \src "ls180.v:1499.5-1499.34" + process $proc$ls180.v:1499$3719 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] sync init end - attribute \src "ls180.v:1433.13-1433.53" - process $proc$ls180.v:1433$3479 + attribute \src "ls180.v:1500.13-1500.53" + process $proc$ls180.v:1500$3720 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end - attribute \src "ls180.v:1439.11-1439.51" - process $proc$ls180.v:1439$3480 + attribute \src "ls180.v:1506.11-1506.51" + process $proc$ls180.v:1506$3721 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always sync init update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end - attribute \src "ls180.v:1440.5-1440.39" - process $proc$ls180.v:1440$3481 + attribute \src "ls180.v:1507.5-1507.39" + process $proc$ls180.v:1507$3722 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always sync init update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end - attribute \src "ls180.v:1441.12-1441.51" - process $proc$ls180.v:1441$3482 + attribute \src "ls180.v:1508.12-1508.51" + process $proc$ls180.v:1508$3723 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always sync init update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end - attribute \src "ls180.v:1442.5-1442.38" - process $proc$ls180.v:1442$3483 + attribute \src "ls180.v:1509.5-1509.38" + process $proc$ls180.v:1509$3724 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always sync init update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end - attribute \src "ls180.v:1443.11-1443.51" - process $proc$ls180.v:1443$3484 + attribute \src "ls180.v:1510.11-1510.51" + process $proc$ls180.v:1510$3725 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end - attribute \src "ls180.v:1485.11-1485.47" - process $proc$ls180.v:1485$3485 + attribute \src "ls180.v:1552.11-1552.47" + process $proc$ls180.v:1552$3726 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:1489.5-1489.49" - process $proc$ls180.v:1489$3486 + attribute \src "ls180.v:1556.5-1556.49" + process $proc$ls180.v:1556$3727 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end - attribute \src "ls180.v:1493.5-1493.51" - process $proc$ls180.v:1493$3487 + attribute \src "ls180.v:1560.5-1560.51" + process $proc$ls180.v:1560$3728 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end - attribute \src "ls180.v:1494.5-1494.51" - process $proc$ls180.v:1494$3488 + attribute \src "ls180.v:1561.5-1561.51" + process $proc$ls180.v:1561$3729 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end - attribute \src "ls180.v:1495.5-1495.51" - process $proc$ls180.v:1495$3489 + attribute \src "ls180.v:1562.5-1562.51" + process $proc$ls180.v:1562$3730 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] sync init end - attribute \src "ls180.v:1496.5-1496.50" - process $proc$ls180.v:1496$3490 + attribute \src "ls180.v:1563.5-1563.50" + process $proc$ls180.v:1563$3731 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end - attribute \src "ls180.v:1497.11-1497.64" - process $proc$ls180.v:1497$3491 + attribute \src "ls180.v:1564.11-1564.64" + process $proc$ls180.v:1564$3732 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end - attribute \src "ls180.v:1498.11-1498.48" - process $proc$ls180.v:1498$3492 + attribute \src "ls180.v:1565.11-1565.48" + process $proc$ls180.v:1565$3733 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end - attribute \src "ls180.v:1499.12-1499.59" - process $proc$ls180.v:1499$3493 + attribute \src "ls180.v:1566.12-1566.59" + process $proc$ls180.v:1566$3734 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1503.12-1503.55" - process $proc$ls180.v:1503$3494 + attribute \src "ls180.v:1570.12-1570.55" + process $proc$ls180.v:1570$3735 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:1506.12-1506.59" - process $proc$ls180.v:1506$3495 + attribute \src "ls180.v:1573.12-1573.59" + process $proc$ls180.v:1573$3736 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1510.12-1510.55" - process $proc$ls180.v:1510$3496 + attribute \src "ls180.v:1577.12-1577.55" + process $proc$ls180.v:1577$3737 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:1513.12-1513.59" - process $proc$ls180.v:1513$3497 + attribute \src "ls180.v:1580.12-1580.59" + process $proc$ls180.v:1580$3738 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1517.12-1517.55" - process $proc$ls180.v:1517$3498 + attribute \src "ls180.v:1584.12-1584.55" + process $proc$ls180.v:1584$3739 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:1520.12-1520.59" - process $proc$ls180.v:1520$3499 + attribute \src "ls180.v:1587.12-1587.59" + process $proc$ls180.v:1587$3740 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1524.12-1524.55" - process $proc$ls180.v:1524$3500 + attribute \src "ls180.v:1591.12-1591.55" + process $proc$ls180.v:1591$3741 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:1527.12-1527.54" - process $proc$ls180.v:1527$3501 + attribute \src "ls180.v:1594.12-1594.54" + process $proc$ls180.v:1594$3742 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end - attribute \src "ls180.v:1528.12-1528.54" - process $proc$ls180.v:1528$3502 + attribute \src "ls180.v:1595.12-1595.54" + process $proc$ls180.v:1595$3743 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end - attribute \src "ls180.v:1529.12-1529.54" - process $proc$ls180.v:1529$3503 + attribute \src "ls180.v:1596.12-1596.54" + process $proc$ls180.v:1596$3744 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end - attribute \src "ls180.v:1530.12-1530.54" - process $proc$ls180.v:1530$3504 + attribute \src "ls180.v:1597.12-1597.54" + process $proc$ls180.v:1597$3745 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end - attribute \src "ls180.v:1531.5-1531.48" - process $proc$ls180.v:1531$3505 + attribute \src "ls180.v:1598.5-1598.48" + process $proc$ls180.v:1598$3746 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end - attribute \src "ls180.v:1532.5-1532.48" - process $proc$ls180.v:1532$3506 + attribute \src "ls180.v:1599.5-1599.48" + process $proc$ls180.v:1599$3747 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:1533.5-1533.48" - process $proc$ls180.v:1533$3507 + attribute \src "ls180.v:1600.5-1600.48" + process $proc$ls180.v:1600$3748 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end - attribute \src "ls180.v:1534.5-1534.47" - process $proc$ls180.v:1534$3508 + attribute \src "ls180.v:1601.5-1601.47" + process $proc$ls180.v:1601$3749 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end - attribute \src "ls180.v:1535.11-1535.61" - process $proc$ls180.v:1535$3509 + attribute \src "ls180.v:1602.11-1602.61" + process $proc$ls180.v:1602$3750 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end - attribute \src "ls180.v:1536.5-1536.50" - process $proc$ls180.v:1536$3510 + attribute \src "ls180.v:1603.5-1603.50" + process $proc$ls180.v:1603$3751 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:1538.5-1538.50" - process $proc$ls180.v:1538$3511 + attribute \src "ls180.v:1605.5-1605.50" + process $proc$ls180.v:1605$3752 assign { } { } assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] sync init end - attribute \src "ls180.v:1541.11-1541.47" - process $proc$ls180.v:1541$3512 + attribute \src "ls180.v:1608.11-1608.47" + process $proc$ls180.v:1608$3753 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end - attribute \src "ls180.v:1542.11-1542.47" - process $proc$ls180.v:1542$3513 + attribute \src "ls180.v:1609.11-1609.47" + process $proc$ls180.v:1609$3754 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always sync init update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end - attribute \src "ls180.v:1543.12-1543.58" - process $proc$ls180.v:1543$3514 + attribute \src "ls180.v:1610.12-1610.58" + process $proc$ls180.v:1610$3755 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1547.12-1547.54" - process $proc$ls180.v:1547$3515 + attribute \src "ls180.v:1614.12-1614.54" + process $proc$ls180.v:1614$3756 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:1548.5-1548.46" - process $proc$ls180.v:1548$3516 + attribute \src "ls180.v:1615.5-1615.46" + process $proc$ls180.v:1615$3757 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:1550.12-1550.58" - process $proc$ls180.v:1550$3517 + attribute \src "ls180.v:1617.12-1617.58" + process $proc$ls180.v:1617$3758 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1554.12-1554.54" - process $proc$ls180.v:1554$3518 + attribute \src "ls180.v:1621.12-1621.54" + process $proc$ls180.v:1621$3759 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:1555.5-1555.46" - process $proc$ls180.v:1555$3519 + attribute \src "ls180.v:1622.5-1622.46" + process $proc$ls180.v:1622$3760 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:1557.12-1557.58" - process $proc$ls180.v:1557$3520 + attribute \src "ls180.v:1624.12-1624.58" + process $proc$ls180.v:1624$3761 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1561.12-1561.54" - process $proc$ls180.v:1561$3521 + attribute \src "ls180.v:1628.12-1628.54" + process $proc$ls180.v:1628$3762 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:1562.5-1562.46" - process $proc$ls180.v:1562$3522 + attribute \src "ls180.v:1629.5-1629.46" + process $proc$ls180.v:1629$3763 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:1564.12-1564.58" - process $proc$ls180.v:1564$3523 + attribute \src "ls180.v:1631.12-1631.58" + process $proc$ls180.v:1631$3764 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1568.12-1568.54" - process $proc$ls180.v:1568$3524 + attribute \src "ls180.v:1635.12-1635.54" + process $proc$ls180.v:1635$3765 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:1569.5-1569.46" - process $proc$ls180.v:1569$3525 + attribute \src "ls180.v:1636.5-1636.46" + process $proc$ls180.v:1636$3766 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:1571.12-1571.53" - process $proc$ls180.v:1571$3526 + attribute \src "ls180.v:1638.12-1638.53" + process $proc$ls180.v:1638$3767 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end - attribute \src "ls180.v:1572.12-1572.53" - process $proc$ls180.v:1572$3527 + attribute \src "ls180.v:1639.12-1639.53" + process $proc$ls180.v:1639$3768 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end - attribute \src "ls180.v:1573.12-1573.53" - process $proc$ls180.v:1573$3528 + attribute \src "ls180.v:1640.12-1640.53" + process $proc$ls180.v:1640$3769 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end - attribute \src "ls180.v:1574.12-1574.53" - process $proc$ls180.v:1574$3529 + attribute \src "ls180.v:1641.12-1641.53" + process $proc$ls180.v:1641$3770 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end - attribute \src "ls180.v:1575.5-1575.43" - process $proc$ls180.v:1575$3530 + attribute \src "ls180.v:1642.5-1642.43" + process $proc$ls180.v:1642$3771 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:1576.12-1576.51" - process $proc$ls180.v:1576$3531 + attribute \src "ls180.v:1643.12-1643.51" + process $proc$ls180.v:1643$3772 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end - attribute \src "ls180.v:1577.12-1577.51" - process $proc$ls180.v:1577$3532 + attribute \src "ls180.v:1644.12-1644.51" + process $proc$ls180.v:1644$3773 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end - attribute \src "ls180.v:1578.12-1578.51" - process $proc$ls180.v:1578$3533 + attribute \src "ls180.v:1645.12-1645.51" + process $proc$ls180.v:1645$3774 assign { } { } assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end - attribute \src "ls180.v:1579.12-1579.51" - process $proc$ls180.v:1579$3534 + attribute \src "ls180.v:1646.12-1646.51" + process $proc$ls180.v:1646$3775 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end - attribute \src "ls180.v:158.12-158.71" - process $proc$ls180.v:158$2907 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1581.11-1581.39" - process $proc$ls180.v:1581$3535 + attribute \src "ls180.v:1648.11-1648.39" + process $proc$ls180.v:1648$3776 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end - attribute \src "ls180.v:1582.5-1582.32" - process $proc$ls180.v:1582$3536 + attribute \src "ls180.v:1649.5-1649.32" + process $proc$ls180.v:1649$3777 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end - attribute \src "ls180.v:1583.5-1583.33" - process $proc$ls180.v:1583$3537 + attribute \src "ls180.v:1650.5-1650.33" + process $proc$ls180.v:1650$3778 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end - attribute \src "ls180.v:1584.5-1584.35" - process $proc$ls180.v:1584$3538 + attribute \src "ls180.v:1651.5-1651.35" + process $proc$ls180.v:1651$3779 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end - attribute \src "ls180.v:1586.12-1586.42" - process $proc$ls180.v:1586$3539 + attribute \src "ls180.v:1653.12-1653.42" + process $proc$ls180.v:1653$3780 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always sync init update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end - attribute \src "ls180.v:1587.5-1587.33" - process $proc$ls180.v:1587$3540 + attribute \src "ls180.v:1654.5-1654.33" + process $proc$ls180.v:1654$3781 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always sync init update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end - attribute \src "ls180.v:1588.5-1588.34" - process $proc$ls180.v:1588$3541 + attribute \src "ls180.v:1655.5-1655.34" + process $proc$ls180.v:1655$3782 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always sync init update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end - attribute \src "ls180.v:1589.5-1589.36" - process $proc$ls180.v:1589$3542 + attribute \src "ls180.v:1656.5-1656.36" + process $proc$ls180.v:1656$3783 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end - attribute \src "ls180.v:159.12-159.73" - process $proc$ls180.v:159$2908 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1598.11-1598.41" - process $proc$ls180.v:1598$3543 + attribute \src "ls180.v:1665.11-1665.41" + process $proc$ls180.v:1665$3784 assign { } { } assign $0\main_interface0_bus_cti[2:0] 3'000 sync always update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] sync init end - attribute \src "ls180.v:1599.11-1599.41" - process $proc$ls180.v:1599$3544 + attribute \src "ls180.v:1666.11-1666.41" + process $proc$ls180.v:1666$3785 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] sync init end - attribute \src "ls180.v:161.11-161.69" - process $proc$ls180.v:161$2909 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] - end - attribute \src "ls180.v:162.5-162.63" - process $proc$ls180.v:162$2910 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1622.11-1622.45" - process $proc$ls180.v:1622$3545 + attribute \src "ls180.v:1689.11-1689.45" + process $proc$ls180.v:1689$3786 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always sync init update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end - attribute \src "ls180.v:1623.5-1623.41" - process $proc$ls180.v:1623$3546 + attribute \src "ls180.v:1690.5-1690.41" + process $proc$ls180.v:1690$3787 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1624.11-1624.47" - process $proc$ls180.v:1624$3547 + attribute \src "ls180.v:1691.11-1691.47" + process $proc$ls180.v:1691$3788 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end - attribute \src "ls180.v:1625.11-1625.47" - process $proc$ls180.v:1625$3548 + attribute \src "ls180.v:1692.11-1692.47" + process $proc$ls180.v:1692$3789 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end - attribute \src "ls180.v:1626.11-1626.50" - process $proc$ls180.v:1626$3549 + attribute \src "ls180.v:1693.11-1693.50" + process $proc$ls180.v:1693$3790 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:163.5-163.63" - process $proc$ls180.v:163$2911 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1646.5-1646.51" - process $proc$ls180.v:1646$3550 + attribute \src "ls180.v:1713.5-1713.51" + process $proc$ls180.v:1713$3791 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end - attribute \src "ls180.v:1647.5-1647.50" - process $proc$ls180.v:1647$3551 + attribute \src "ls180.v:1714.5-1714.50" + process $proc$ls180.v:1714$3792 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end - attribute \src "ls180.v:1648.12-1648.66" - process $proc$ls180.v:1648$3552 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] - end - attribute \src "ls180.v:1649.11-1649.77" - process $proc$ls180.v:1649$3553 + attribute \src "ls180.v:1715.12-1715.66" + process $proc$ls180.v:1715$3793 assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] end - attribute \src "ls180.v:165.5-165.62" - process $proc$ls180.v:165$2912 + attribute \src "ls180.v:1716.11-1716.77" + process $proc$ls180.v:1716$3794 assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init - update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1650.11-1650.50" - process $proc$ls180.v:1650$3554 + attribute \src "ls180.v:1717.11-1717.50" + process $proc$ls180.v:1717$3795 assign { } { } - assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 sync always sync init - update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] end - attribute \src "ls180.v:1652.5-1652.49" - process $proc$ls180.v:1652$3555 + attribute \src "ls180.v:1719.5-1719.49" + process $proc$ls180.v:1719$3796 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:1658.5-1658.45" - process $proc$ls180.v:1658$3556 + attribute \src "ls180.v:172.5-172.72" + process $proc$ls180.v:172$3150 assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:166.11-166.69" - process $proc$ls180.v:166$2913 + attribute \src "ls180.v:1725.5-1725.45" + process $proc$ls180.v:1725$3797 assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always - update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:1660.12-1660.62" - process $proc$ls180.v:1660$3557 + attribute \src "ls180.v:1727.12-1727.62" + process $proc$ls180.v:1727$3798 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end - attribute \src "ls180.v:1661.12-1661.60" - process $proc$ls180.v:1661$3558 + attribute \src "ls180.v:1728.12-1728.60" + process $proc$ls180.v:1728$3799 assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] end - attribute \src "ls180.v:1663.5-1663.57" - process $proc$ls180.v:1663$3559 + attribute \src "ls180.v:1730.5-1730.57" + process $proc$ls180.v:1730$3800 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end - attribute \src "ls180.v:1667.12-1667.67" - process $proc$ls180.v:1667$3560 + attribute \src "ls180.v:1734.12-1734.67" + process $proc$ls180.v:1734$3801 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end - attribute \src "ls180.v:1668.5-1668.54" - process $proc$ls180.v:1668$3561 + attribute \src "ls180.v:1735.5-1735.54" + process $proc$ls180.v:1735$3802 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end - attribute \src "ls180.v:1669.12-1669.69" - process $proc$ls180.v:1669$3562 + attribute \src "ls180.v:1736.12-1736.69" + process $proc$ls180.v:1736$3803 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end - attribute \src "ls180.v:167.11-167.69" - process $proc$ls180.v:167$2914 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1670.5-1670.56" - process $proc$ls180.v:1670$3563 + attribute \src "ls180.v:1737.5-1737.56" + process $proc$ls180.v:1737$3804 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end - attribute \src "ls180.v:1671.5-1671.61" - process $proc$ls180.v:1671$3564 + attribute \src "ls180.v:1738.5-1738.61" + process $proc$ls180.v:1738$3805 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end - attribute \src "ls180.v:1672.5-1672.56" - process $proc$ls180.v:1672$3565 + attribute \src "ls180.v:1739.5-1739.56" + process $proc$ls180.v:1739$3806 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end - attribute \src "ls180.v:1673.5-1673.53" - process $proc$ls180.v:1673$3566 + attribute \src "ls180.v:1740.5-1740.53" + process $proc$ls180.v:1740$3807 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end - attribute \src "ls180.v:1675.5-1675.59" - process $proc$ls180.v:1675$3567 + attribute \src "ls180.v:1742.5-1742.59" + process $proc$ls180.v:1742$3808 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end - attribute \src "ls180.v:1676.5-1676.54" - process $proc$ls180.v:1676$3568 + attribute \src "ls180.v:1743.5-1743.54" + process $proc$ls180.v:1743$3809 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end - attribute \src "ls180.v:1678.12-1678.61" - process $proc$ls180.v:1678$3569 + attribute \src "ls180.v:1745.12-1745.61" + process $proc$ls180.v:1745$3810 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end - attribute \src "ls180.v:1681.12-1681.43" - process $proc$ls180.v:1681$3570 + attribute \src "ls180.v:1748.12-1748.43" + process $proc$ls180.v:1748$3811 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always sync init update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end - attribute \src "ls180.v:1682.12-1682.45" - process $proc$ls180.v:1682$3571 + attribute \src "ls180.v:1749.12-1749.45" + process $proc$ls180.v:1749$3812 + assign { } { } + assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] + sync init + end + attribute \src "ls180.v:175.11-175.79" + process $proc$ls180.v:175$3151 assign { } { } - assign $0\main_interface1_bus_dat_w[31:0] 0 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 sync always - update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] sync init end - attribute \src "ls180.v:1684.11-1684.41" - process $proc$ls180.v:1684$3572 + attribute \src "ls180.v:1751.11-1751.41" + process $proc$ls180.v:1751$3813 assign { } { } - assign $1\main_interface1_bus_sel[3:0] 4'0000 + assign $1\main_interface1_bus_sel[7:0] 8'00000000 sync always sync init - update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] + update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] end - attribute \src "ls180.v:1685.5-1685.35" - process $proc$ls180.v:1685$3573 + attribute \src "ls180.v:1752.5-1752.35" + process $proc$ls180.v:1752$3814 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always sync init update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end - attribute \src "ls180.v:1686.5-1686.35" - process $proc$ls180.v:1686$3574 + attribute \src "ls180.v:1753.5-1753.35" + process $proc$ls180.v:1753$3815 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always sync init update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end - attribute \src "ls180.v:1688.5-1688.34" - process $proc$ls180.v:1688$3575 + attribute \src "ls180.v:1755.5-1755.34" + process $proc$ls180.v:1755$3816 assign { } { } assign $1\main_interface1_bus_we[0:0] 1'0 sync always sync init update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end - attribute \src "ls180.v:1689.11-1689.41" - process $proc$ls180.v:1689$3576 + attribute \src "ls180.v:1756.11-1756.41" + process $proc$ls180.v:1756$3817 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] sync init end - attribute \src "ls180.v:169.5-169.44" - process $proc$ls180.v:169$2915 - assign { } { } - assign $1\main_libresocsim_converter0_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] - end - attribute \src "ls180.v:1690.11-1690.41" - process $proc$ls180.v:1690$3577 + attribute \src "ls180.v:1757.11-1757.41" + process $proc$ls180.v:1757$3818 assign { } { } assign $0\main_interface1_bus_bte[1:0] 2'00 sync always update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end - attribute \src "ls180.v:1697.5-1697.43" - process $proc$ls180.v:1697$3578 + attribute \src "ls180.v:1764.5-1764.43" + process $proc$ls180.v:1764$3819 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end - attribute \src "ls180.v:1698.5-1698.43" - process $proc$ls180.v:1698$3579 + attribute \src "ls180.v:1765.5-1765.43" + process $proc$ls180.v:1765$3820 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end - attribute \src "ls180.v:1699.5-1699.42" - process $proc$ls180.v:1699$3580 + attribute \src "ls180.v:1766.5-1766.42" + process $proc$ls180.v:1766$3821 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end - attribute \src "ls180.v:170.5-170.47" - process $proc$ls180.v:170$2916 - assign { } { } - assign $1\main_libresocsim_converter0_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] - end - attribute \src "ls180.v:1700.12-1700.61" - process $proc$ls180.v:1700$3581 + attribute \src "ls180.v:1767.12-1767.61" + process $proc$ls180.v:1767$3822 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always sync init update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end - attribute \src "ls180.v:1701.5-1701.45" - process $proc$ls180.v:1701$3582 + attribute \src "ls180.v:1768.5-1768.45" + process $proc$ls180.v:1768$3823 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end - attribute \src "ls180.v:1703.5-1703.45" - process $proc$ls180.v:1703$3583 + attribute \src "ls180.v:1770.5-1770.45" + process $proc$ls180.v:1770$3824 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] sync init end - attribute \src "ls180.v:1704.5-1704.44" - process $proc$ls180.v:1704$3584 + attribute \src "ls180.v:1771.5-1771.44" + process $proc$ls180.v:1771$3825 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end - attribute \src "ls180.v:1705.12-1705.60" - process $proc$ls180.v:1705$3585 + attribute \src "ls180.v:1772.12-1772.60" + process $proc$ls180.v:1772$3826 assign { } { } - assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] end - attribute \src "ls180.v:1706.12-1706.45" - process $proc$ls180.v:1706$3586 + attribute \src "ls180.v:1773.12-1773.45" + process $proc$ls180.v:1773$3827 assign { } { } - assign $1\main_sdmem2block_dma_data[31:0] 0 + assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] end - attribute \src "ls180.v:1707.12-1707.53" - process $proc$ls180.v:1707$3587 + attribute \src "ls180.v:1774.12-1774.53" + process $proc$ls180.v:1774$3828 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end - attribute \src "ls180.v:1708.5-1708.40" - process $proc$ls180.v:1708$3588 + attribute \src "ls180.v:1775.5-1775.40" + process $proc$ls180.v:1775$3829 assign { } { } assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end - attribute \src "ls180.v:1709.12-1709.55" - process $proc$ls180.v:1709$3589 + attribute \src "ls180.v:1776.12-1776.55" + process $proc$ls180.v:1776$3830 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always sync init update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end - attribute \src "ls180.v:1710.5-1710.42" - process $proc$ls180.v:1710$3590 + attribute \src "ls180.v:1777.5-1777.42" + process $proc$ls180.v:1777$3831 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end - attribute \src "ls180.v:1711.5-1711.47" - process $proc$ls180.v:1711$3591 + attribute \src "ls180.v:1778.5-1778.47" + process $proc$ls180.v:1778$3832 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end - attribute \src "ls180.v:1712.5-1712.42" - process $proc$ls180.v:1712$3592 + attribute \src "ls180.v:1779.5-1779.42" + process $proc$ls180.v:1779$3833 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end - attribute \src "ls180.v:1713.5-1713.44" - process $proc$ls180.v:1713$3593 + attribute \src "ls180.v:1780.5-1780.44" + process $proc$ls180.v:1780$3834 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end - attribute \src "ls180.v:1715.5-1715.45" - process $proc$ls180.v:1715$3594 + attribute \src "ls180.v:1782.5-1782.45" + process $proc$ls180.v:1782$3835 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end - attribute \src "ls180.v:1716.5-1716.40" - process $proc$ls180.v:1716$3595 + attribute \src "ls180.v:1783.5-1783.40" + process $proc$ls180.v:1783$3836 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end - attribute \src "ls180.v:172.12-172.53" - process $proc$ls180.v:172$2917 - assign { } { } - assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] - end - attribute \src "ls180.v:1720.12-1720.47" - process $proc$ls180.v:1720$3596 + attribute \src "ls180.v:1787.12-1787.47" + process $proc$ls180.v:1787$3837 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end - attribute \src "ls180.v:173.12-173.71" - process $proc$ls180.v:173$2918 + attribute \src "ls180.v:179.5-179.69" + process $proc$ls180.v:179$3152 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] sync init - update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] end - attribute \src "ls180.v:1732.11-1732.64" - process $proc$ls180.v:1732$3597 + attribute \src "ls180.v:1799.11-1799.64" + process $proc$ls180.v:1799$3838 assign { } { } assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1734.11-1734.48" - process $proc$ls180.v:1734$3598 + attribute \src "ls180.v:1801.11-1801.48" + process $proc$ls180.v:1801$3839 assign { } { } - assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + assign $1\main_sdmem2block_converter_mux[2:0] 3'000 sync always sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:174.12-174.73" - process $proc$ls180.v:174$2919 + attribute \src "ls180.v:182.12-182.74" + process $proc$ls180.v:182$3153 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] sync init - update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1758.11-1758.45" - process $proc$ls180.v:1758$3599 + attribute \src "ls180.v:1825.11-1825.45" + process $proc$ls180.v:1825$3840 assign { } { } assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always sync init update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end - attribute \src "ls180.v:1759.5-1759.41" - process $proc$ls180.v:1759$3600 + attribute \src "ls180.v:1826.5-1826.41" + process $proc$ls180.v:1826$3841 assign { } { } assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] sync init end - attribute \src "ls180.v:176.11-176.69" - process $proc$ls180.v:176$2920 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1760.11-1760.47" - process $proc$ls180.v:1760$3601 + attribute \src "ls180.v:1827.11-1827.47" + process $proc$ls180.v:1827$3842 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end - attribute \src "ls180.v:1761.11-1761.47" - process $proc$ls180.v:1761$3602 + attribute \src "ls180.v:1828.11-1828.47" + process $proc$ls180.v:1828$3843 assign { } { } assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end - attribute \src "ls180.v:1762.11-1762.50" - process $proc$ls180.v:1762$3603 + attribute \src "ls180.v:1829.11-1829.50" + process $proc$ls180.v:1829$3844 assign { } { } assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:177.5-177.63" - process $proc$ls180.v:177$2921 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1775.5-1775.36" - process $proc$ls180.v:1775$3604 + attribute \src "ls180.v:1842.5-1842.36" + process $proc$ls180.v:1842$3845 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always sync init update \builder_converter0_state $1\builder_converter0_state[0:0] end - attribute \src "ls180.v:1776.5-1776.41" - process $proc$ls180.v:1776$3605 + attribute \src "ls180.v:1843.5-1843.41" + process $proc$ls180.v:1843$3846 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always sync init update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end - attribute \src "ls180.v:1777.5-1777.69" - process $proc$ls180.v:1777$3606 + attribute \src "ls180.v:1844.5-1844.57" + process $proc$ls180.v:1844$3847 assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] end - attribute \src "ls180.v:1778.5-1778.72" - process $proc$ls180.v:1778$3607 + attribute \src "ls180.v:1845.5-1845.60" + process $proc$ls180.v:1845$3848 assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always sync init - update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:1779.5-1779.36" - process $proc$ls180.v:1779$3608 + attribute \src "ls180.v:1846.5-1846.36" + process $proc$ls180.v:1846$3849 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always sync init update \builder_converter1_state $1\builder_converter1_state[0:0] end - attribute \src "ls180.v:178.5-178.63" - process $proc$ls180.v:178$2922 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1780.5-1780.41" - process $proc$ls180.v:1780$3609 + attribute \src "ls180.v:1847.5-1847.41" + process $proc$ls180.v:1847$3850 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always sync init update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end - attribute \src "ls180.v:1781.5-1781.69" - process $proc$ls180.v:1781$3610 + attribute \src "ls180.v:1848.5-1848.57" + process $proc$ls180.v:1848$3851 assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] end - attribute \src "ls180.v:1782.5-1782.72" - process $proc$ls180.v:1782$3611 + attribute \src "ls180.v:1849.5-1849.60" + process $proc$ls180.v:1849$3852 assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always sync init - update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:1783.5-1783.36" - process $proc$ls180.v:1783$3612 + attribute \src "ls180.v:1850.5-1850.36" + process $proc$ls180.v:1850$3853 assign { } { } assign $1\builder_converter2_state[0:0] 1'0 sync always sync init update \builder_converter2_state $1\builder_converter2_state[0:0] end - attribute \src "ls180.v:1784.5-1784.41" - process $proc$ls180.v:1784$3613 + attribute \src "ls180.v:1851.5-1851.41" + process $proc$ls180.v:1851$3854 assign { } { } assign $1\builder_converter2_next_state[0:0] 1'0 sync always sync init update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end - attribute \src "ls180.v:1785.5-1785.69" - process $proc$ls180.v:1785$3614 + attribute \src "ls180.v:1852.5-1852.60" + process $proc$ls180.v:1852$3855 assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] end - attribute \src "ls180.v:1786.5-1786.72" - process $proc$ls180.v:1786$3615 + attribute \src "ls180.v:1853.5-1853.63" + process $proc$ls180.v:1853$3856 assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 sync always sync init - update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:1787.11-1787.41" - process $proc$ls180.v:1787$3616 + attribute \src "ls180.v:1854.11-1854.41" + process $proc$ls180.v:1854$3857 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always sync init update \builder_refresher_state $1\builder_refresher_state[1:0] end - attribute \src "ls180.v:1788.11-1788.46" - process $proc$ls180.v:1788$3617 + attribute \src "ls180.v:1855.11-1855.46" + process $proc$ls180.v:1855$3858 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always sync init update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:1789.11-1789.44" - process $proc$ls180.v:1789$3618 + attribute \src "ls180.v:1856.11-1856.44" + process $proc$ls180.v:1856$3859 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end - attribute \src "ls180.v:1790.11-1790.49" - process $proc$ls180.v:1790$3619 + attribute \src "ls180.v:1857.11-1857.49" + process $proc$ls180.v:1857$3860 assign { } { } assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:1791.11-1791.44" - process $proc$ls180.v:1791$3620 + attribute \src "ls180.v:1858.11-1858.44" + process $proc$ls180.v:1858$3861 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end - attribute \src "ls180.v:1792.11-1792.49" - process $proc$ls180.v:1792$3621 + attribute \src "ls180.v:1859.11-1859.49" + process $proc$ls180.v:1859$3862 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:1793.11-1793.44" - process $proc$ls180.v:1793$3622 + attribute \src "ls180.v:1860.11-1860.44" + process $proc$ls180.v:1860$3863 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end - attribute \src "ls180.v:1794.11-1794.49" - process $proc$ls180.v:1794$3623 + attribute \src "ls180.v:1861.11-1861.49" + process $proc$ls180.v:1861$3864 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:1795.11-1795.44" - process $proc$ls180.v:1795$3624 + attribute \src "ls180.v:1862.11-1862.44" + process $proc$ls180.v:1862$3865 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end - attribute \src "ls180.v:1796.11-1796.49" - process $proc$ls180.v:1796$3625 + attribute \src "ls180.v:1863.11-1863.49" + process $proc$ls180.v:1863$3866 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:1797.11-1797.43" - process $proc$ls180.v:1797$3626 + attribute \src "ls180.v:1864.11-1864.43" + process $proc$ls180.v:1864$3867 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always sync init update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end - attribute \src "ls180.v:1798.11-1798.48" - process $proc$ls180.v:1798$3627 + attribute \src "ls180.v:1865.11-1865.48" + process $proc$ls180.v:1865$3868 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always sync init update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:180.5-180.62" - process $proc$ls180.v:180$2923 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] - end - attribute \src "ls180.v:181.11-181.69" - process $proc$ls180.v:181$2924 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1811.5-1811.27" - process $proc$ls180.v:1811$3628 + attribute \src "ls180.v:1878.5-1878.27" + process $proc$ls180.v:1878$3869 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always update \builder_locked0 $0\builder_locked0[0:0] sync init end - attribute \src "ls180.v:1812.5-1812.27" - process $proc$ls180.v:1812$3629 + attribute \src "ls180.v:1879.5-1879.27" + process $proc$ls180.v:1879$3870 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:1813.5-1813.27" - process $proc$ls180.v:1813$3630 + attribute \src "ls180.v:1880.5-1880.27" + process $proc$ls180.v:1880$3871 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always update \builder_locked2 $0\builder_locked2[0:0] sync init end - attribute \src "ls180.v:1814.5-1814.27" - process $proc$ls180.v:1814$3631 + attribute \src "ls180.v:1881.5-1881.27" + process $proc$ls180.v:1881$3872 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always update \builder_locked3 $0\builder_locked3[0:0] sync init end - attribute \src "ls180.v:1815.5-1815.42" - process $proc$ls180.v:1815$3632 + attribute \src "ls180.v:1882.5-1882.42" + process $proc$ls180.v:1882$3873 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always sync init update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:1816.5-1816.43" - process $proc$ls180.v:1816$3633 + attribute \src "ls180.v:1883.5-1883.43" + process $proc$ls180.v:1883$3874 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:1817.5-1817.43" - process $proc$ls180.v:1817$3634 + attribute \src "ls180.v:1884.5-1884.43" + process $proc$ls180.v:1884$3875 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:1818.5-1818.43" - process $proc$ls180.v:1818$3635 + attribute \src "ls180.v:1885.5-1885.43" + process $proc$ls180.v:1885$3876 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:1819.5-1819.43" - process $proc$ls180.v:1819$3636 + attribute \src "ls180.v:1886.5-1886.43" + process $proc$ls180.v:1886$3877 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:182.11-182.69" - process $proc$ls180.v:182$2925 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1820.5-1820.35" - process $proc$ls180.v:1820$3637 + attribute \src "ls180.v:1887.5-1887.35" + process $proc$ls180.v:1887$3878 assign { } { } assign $1\builder_converter_state[0:0] 1'0 sync always sync init update \builder_converter_state $1\builder_converter_state[0:0] end - attribute \src "ls180.v:1821.5-1821.40" - process $proc$ls180.v:1821$3638 + attribute \src "ls180.v:1888.5-1888.40" + process $proc$ls180.v:1888$3879 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always sync init update \builder_converter_next_state $1\builder_converter_next_state[0:0] end - attribute \src "ls180.v:1822.5-1822.55" - process $proc$ls180.v:1822$3639 + attribute \src "ls180.v:1889.5-1889.55" + process $proc$ls180.v:1889$3880 assign { } { } assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end - attribute \src "ls180.v:1823.5-1823.58" - process $proc$ls180.v:1823$3640 + attribute \src "ls180.v:1890.5-1890.58" + process $proc$ls180.v:1890$3881 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:1824.11-1824.42" - process $proc$ls180.v:1824$3641 + attribute \src "ls180.v:1891.11-1891.42" + process $proc$ls180.v:1891$3882 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always sync init update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end - attribute \src "ls180.v:1825.11-1825.47" - process $proc$ls180.v:1825$3642 + attribute \src "ls180.v:1892.11-1892.47" + process $proc$ls180.v:1892$3883 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always sync init update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end - attribute \src "ls180.v:1826.11-1826.62" - process $proc$ls180.v:1826$3643 + attribute \src "ls180.v:1893.11-1893.62" + process $proc$ls180.v:1893$3884 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 sync always sync init update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] end - attribute \src "ls180.v:1827.5-1827.59" - process $proc$ls180.v:1827$3644 + attribute \src "ls180.v:1894.5-1894.59" + process $proc$ls180.v:1894$3885 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 sync always sync init update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:1828.11-1828.42" - process $proc$ls180.v:1828$3645 + attribute \src "ls180.v:1895.11-1895.42" + process $proc$ls180.v:1895$3886 assign { } { } assign $1\builder_spimaster1_state[1:0] 2'00 sync always sync init update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] end - attribute \src "ls180.v:1829.11-1829.47" - process $proc$ls180.v:1829$3646 + attribute \src "ls180.v:1896.11-1896.47" + process $proc$ls180.v:1896$3887 assign { } { } assign $1\builder_spimaster1_next_state[1:0] 2'00 sync always sync init update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] end - attribute \src "ls180.v:1830.11-1830.60" - process $proc$ls180.v:1830$3647 + attribute \src "ls180.v:1897.11-1897.60" + process $proc$ls180.v:1897$3888 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 sync always sync init update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] end - attribute \src "ls180.v:1831.5-1831.57" - process $proc$ls180.v:1831$3648 + attribute \src "ls180.v:1898.5-1898.57" + process $proc$ls180.v:1898$3889 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 sync always sync init update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:1832.5-1832.41" - process $proc$ls180.v:1832$3649 + attribute \src "ls180.v:1899.5-1899.41" + process $proc$ls180.v:1899$3890 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end - attribute \src "ls180.v:1833.5-1833.46" - process $proc$ls180.v:1833$3650 + attribute \src "ls180.v:1900.5-1900.46" + process $proc$ls180.v:1900$3891 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end - attribute \src "ls180.v:1834.11-1834.66" - process $proc$ls180.v:1834$3651 + attribute \src "ls180.v:1901.11-1901.66" + process $proc$ls180.v:1901$3892 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end - attribute \src "ls180.v:1835.5-1835.63" - process $proc$ls180.v:1835$3652 + attribute \src "ls180.v:1902.5-1902.63" + process $proc$ls180.v:1902$3893 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:1836.11-1836.47" - process $proc$ls180.v:1836$3653 + attribute \src "ls180.v:1903.11-1903.47" + process $proc$ls180.v:1903$3894 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end - attribute \src "ls180.v:1837.11-1837.52" - process $proc$ls180.v:1837$3654 + attribute \src "ls180.v:1904.11-1904.52" + process $proc$ls180.v:1904$3895 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end - attribute \src "ls180.v:1838.11-1838.66" - process $proc$ls180.v:1838$3655 + attribute \src "ls180.v:1905.11-1905.66" + process $proc$ls180.v:1905$3896 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end - attribute \src "ls180.v:1839.5-1839.63" - process $proc$ls180.v:1839$3656 + attribute \src "ls180.v:1906.5-1906.63" + process $proc$ls180.v:1906$3897 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:184.5-184.44" - process $proc$ls180.v:184$2926 - assign { } { } - assign $1\main_libresocsim_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] - end - attribute \src "ls180.v:1840.11-1840.47" - process $proc$ls180.v:1840$3657 + attribute \src "ls180.v:1907.11-1907.47" + process $proc$ls180.v:1907$3898 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end - attribute \src "ls180.v:1841.11-1841.52" - process $proc$ls180.v:1841$3658 + attribute \src "ls180.v:1908.11-1908.52" + process $proc$ls180.v:1908$3899 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end - attribute \src "ls180.v:1842.11-1842.67" - process $proc$ls180.v:1842$3659 + attribute \src "ls180.v:1909.11-1909.67" + process $proc$ls180.v:1909$3900 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end - attribute \src "ls180.v:1843.5-1843.64" - process $proc$ls180.v:1843$3660 + attribute \src "ls180.v:1910.5-1910.64" + process $proc$ls180.v:1910$3901 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end - attribute \src "ls180.v:1844.12-1844.71" - process $proc$ls180.v:1844$3661 + attribute \src "ls180.v:1911.12-1911.71" + process $proc$ls180.v:1911$3902 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end - attribute \src "ls180.v:1845.5-1845.66" - process $proc$ls180.v:1845$3662 + attribute \src "ls180.v:1912.5-1912.66" + process $proc$ls180.v:1912$3903 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end - attribute \src "ls180.v:1846.5-1846.66" - process $proc$ls180.v:1846$3663 + attribute \src "ls180.v:1913.5-1913.66" + process $proc$ls180.v:1913$3904 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end - attribute \src "ls180.v:1847.5-1847.69" - process $proc$ls180.v:1847$3664 + attribute \src "ls180.v:1914.5-1914.69" + process $proc$ls180.v:1914$3905 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:1848.5-1848.41" - process $proc$ls180.v:1848$3665 + attribute \src "ls180.v:1915.5-1915.41" + process $proc$ls180.v:1915$3906 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end - attribute \src "ls180.v:1849.5-1849.46" - process $proc$ls180.v:1849$3666 + attribute \src "ls180.v:1916.5-1916.46" + process $proc$ls180.v:1916$3907 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end - attribute \src "ls180.v:185.5-185.47" - process $proc$ls180.v:185$2927 - assign { } { } - assign $1\main_libresocsim_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] - end - attribute \src "ls180.v:1850.5-1850.66" - process $proc$ls180.v:1850$3667 + attribute \src "ls180.v:1917.5-1917.66" + process $proc$ls180.v:1917$3908 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end - attribute \src "ls180.v:1851.5-1851.69" - process $proc$ls180.v:1851$3668 + attribute \src "ls180.v:1918.5-1918.69" + process $proc$ls180.v:1918$3909 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:1852.11-1852.41" - process $proc$ls180.v:1852$3669 + attribute \src "ls180.v:1919.11-1919.41" + process $proc$ls180.v:1919$3910 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end - attribute \src "ls180.v:1853.11-1853.46" - process $proc$ls180.v:1853$3670 + attribute \src "ls180.v:1920.11-1920.46" + process $proc$ls180.v:1920$3911 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end - attribute \src "ls180.v:1854.11-1854.61" - process $proc$ls180.v:1854$3671 + attribute \src "ls180.v:1921.11-1921.61" + process $proc$ls180.v:1921$3912 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end - attribute \src "ls180.v:1855.5-1855.58" - process $proc$ls180.v:1855$3672 + attribute \src "ls180.v:1922.5-1922.58" + process $proc$ls180.v:1922$3913 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1856.11-1856.48" - process $proc$ls180.v:1856$3673 + attribute \src "ls180.v:1923.11-1923.48" + process $proc$ls180.v:1923$3914 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end - attribute \src "ls180.v:1857.11-1857.53" - process $proc$ls180.v:1857$3674 + attribute \src "ls180.v:1924.11-1924.53" + process $proc$ls180.v:1924$3915 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end - attribute \src "ls180.v:1858.11-1858.70" - process $proc$ls180.v:1858$3675 + attribute \src "ls180.v:1925.11-1925.70" + process $proc$ls180.v:1925$3916 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end - attribute \src "ls180.v:1859.5-1859.66" - process $proc$ls180.v:1859$3676 + attribute \src "ls180.v:1926.5-1926.66" + process $proc$ls180.v:1926$3917 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end - attribute \src "ls180.v:1860.12-1860.73" - process $proc$ls180.v:1860$3677 + attribute \src "ls180.v:1927.12-1927.73" + process $proc$ls180.v:1927$3918 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end - attribute \src "ls180.v:1861.5-1861.68" - process $proc$ls180.v:1861$3678 + attribute \src "ls180.v:1928.5-1928.68" + process $proc$ls180.v:1928$3919 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end - attribute \src "ls180.v:1862.5-1862.69" - process $proc$ls180.v:1862$3679 + attribute \src "ls180.v:1929.5-1929.69" + process $proc$ls180.v:1929$3920 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end - attribute \src "ls180.v:1863.5-1863.72" - process $proc$ls180.v:1863$3680 + attribute \src "ls180.v:1930.5-1930.72" + process $proc$ls180.v:1930$3921 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:1864.5-1864.52" - process $proc$ls180.v:1864$3681 + attribute \src "ls180.v:1931.5-1931.52" + process $proc$ls180.v:1931$3922 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end - attribute \src "ls180.v:1865.5-1865.57" - process $proc$ls180.v:1865$3682 + attribute \src "ls180.v:1932.5-1932.57" + process $proc$ls180.v:1932$3923 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end - attribute \src "ls180.v:1866.12-1866.93" - process $proc$ls180.v:1866$3683 + attribute \src "ls180.v:1933.12-1933.93" + process $proc$ls180.v:1933$3924 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end - attribute \src "ls180.v:1867.5-1867.88" - process $proc$ls180.v:1867$3684 + attribute \src "ls180.v:1934.5-1934.88" + process $proc$ls180.v:1934$3925 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end - attribute \src "ls180.v:1868.12-1868.93" - process $proc$ls180.v:1868$3685 + attribute \src "ls180.v:1935.12-1935.93" + process $proc$ls180.v:1935$3926 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end - attribute \src "ls180.v:1869.5-1869.88" - process $proc$ls180.v:1869$3686 + attribute \src "ls180.v:1936.5-1936.88" + process $proc$ls180.v:1936$3927 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end - attribute \src "ls180.v:187.12-187.53" - process $proc$ls180.v:187$2928 - assign { } { } - assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] - end - attribute \src "ls180.v:1870.12-1870.93" - process $proc$ls180.v:1870$3687 + attribute \src "ls180.v:1937.12-1937.93" + process $proc$ls180.v:1937$3928 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end - attribute \src "ls180.v:1871.5-1871.88" - process $proc$ls180.v:1871$3688 + attribute \src "ls180.v:1938.5-1938.88" + process $proc$ls180.v:1938$3929 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end - attribute \src "ls180.v:1872.12-1872.93" - process $proc$ls180.v:1872$3689 + attribute \src "ls180.v:1939.12-1939.93" + process $proc$ls180.v:1939$3930 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end - attribute \src "ls180.v:1873.5-1873.88" - process $proc$ls180.v:1873$3690 + attribute \src "ls180.v:1940.5-1940.88" + process $proc$ls180.v:1940$3931 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end - attribute \src "ls180.v:1874.11-1874.87" - process $proc$ls180.v:1874$3691 + attribute \src "ls180.v:1941.11-1941.87" + process $proc$ls180.v:1941$3932 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end - attribute \src "ls180.v:1875.5-1875.84" - process $proc$ls180.v:1875$3692 + attribute \src "ls180.v:1942.5-1942.84" + process $proc$ls180.v:1942$3933 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:1876.11-1876.42" - process $proc$ls180.v:1876$3693 + attribute \src "ls180.v:1943.11-1943.42" + process $proc$ls180.v:1943$3934 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end - attribute \src "ls180.v:1877.11-1877.47" - process $proc$ls180.v:1877$3694 + attribute \src "ls180.v:1944.11-1944.47" + process $proc$ls180.v:1944$3935 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end - attribute \src "ls180.v:1878.5-1878.55" - process $proc$ls180.v:1878$3695 + attribute \src "ls180.v:1945.5-1945.55" + process $proc$ls180.v:1945$3936 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end - attribute \src "ls180.v:1879.5-1879.58" - process $proc$ls180.v:1879$3696 + attribute \src "ls180.v:1946.5-1946.58" + process $proc$ls180.v:1946$3937 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end - attribute \src "ls180.v:188.12-188.71" - process $proc$ls180.v:188$2929 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1880.5-1880.56" - process $proc$ls180.v:1880$3697 + attribute \src "ls180.v:1947.5-1947.56" + process $proc$ls180.v:1947$3938 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end - attribute \src "ls180.v:1881.5-1881.59" - process $proc$ls180.v:1881$3698 + attribute \src "ls180.v:1948.5-1948.59" + process $proc$ls180.v:1948$3939 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end - attribute \src "ls180.v:1882.11-1882.62" - process $proc$ls180.v:1882$3699 + attribute \src "ls180.v:1949.11-1949.62" + process $proc$ls180.v:1949$3940 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:1883.5-1883.59" - process $proc$ls180.v:1883$3700 + attribute \src "ls180.v:195.12-195.78" + process $proc$ls180.v:195$3154 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end + attribute \src "ls180.v:1950.5-1950.59" + process $proc$ls180.v:1950$3941 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end - attribute \src "ls180.v:1884.12-1884.65" - process $proc$ls180.v:1884$3701 + attribute \src "ls180.v:1951.12-1951.65" + process $proc$ls180.v:1951$3942 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end - attribute \src "ls180.v:1885.5-1885.60" - process $proc$ls180.v:1885$3702 + attribute \src "ls180.v:1952.5-1952.60" + process $proc$ls180.v:1952$3943 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end - attribute \src "ls180.v:1886.5-1886.56" - process $proc$ls180.v:1886$3703 + attribute \src "ls180.v:1953.5-1953.56" + process $proc$ls180.v:1953$3944 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end - attribute \src "ls180.v:1887.5-1887.59" - process $proc$ls180.v:1887$3704 + attribute \src "ls180.v:1954.5-1954.59" + process $proc$ls180.v:1954$3945 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end - attribute \src "ls180.v:1888.5-1888.58" - process $proc$ls180.v:1888$3705 + attribute \src "ls180.v:1955.5-1955.58" + process $proc$ls180.v:1955$3946 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end - attribute \src "ls180.v:1889.5-1889.61" - process $proc$ls180.v:1889$3706 + attribute \src "ls180.v:1956.5-1956.61" + process $proc$ls180.v:1956$3947 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end - attribute \src "ls180.v:189.12-189.73" - process $proc$ls180.v:189$2930 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1890.5-1890.57" - process $proc$ls180.v:1890$3707 + attribute \src "ls180.v:1957.5-1957.57" + process $proc$ls180.v:1957$3948 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end - attribute \src "ls180.v:1891.5-1891.60" - process $proc$ls180.v:1891$3708 + attribute \src "ls180.v:1958.5-1958.60" + process $proc$ls180.v:1958$3949 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end - attribute \src "ls180.v:1892.5-1892.59" - process $proc$ls180.v:1892$3709 + attribute \src "ls180.v:1959.5-1959.59" + process $proc$ls180.v:1959$3950 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end - attribute \src "ls180.v:1893.5-1893.62" - process $proc$ls180.v:1893$3710 + attribute \src "ls180.v:1960.5-1960.62" + process $proc$ls180.v:1960$3951 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end - attribute \src "ls180.v:1894.13-1894.76" - process $proc$ls180.v:1894$3711 + attribute \src "ls180.v:1961.13-1961.76" + process $proc$ls180.v:1961$3952 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end - attribute \src "ls180.v:1895.5-1895.69" - process $proc$ls180.v:1895$3712 + attribute \src "ls180.v:1962.5-1962.69" + process $proc$ls180.v:1962$3953 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:1896.11-1896.46" - process $proc$ls180.v:1896$3713 + attribute \src "ls180.v:1963.11-1963.46" + process $proc$ls180.v:1963$3954 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end - attribute \src "ls180.v:1897.11-1897.51" - process $proc$ls180.v:1897$3714 + attribute \src "ls180.v:1964.11-1964.51" + process $proc$ls180.v:1964$3955 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end - attribute \src "ls180.v:1898.12-1898.87" - process $proc$ls180.v:1898$3715 + attribute \src "ls180.v:1965.12-1965.87" + process $proc$ls180.v:1965$3956 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end - attribute \src "ls180.v:1899.5-1899.82" - process $proc$ls180.v:1899$3716 + attribute \src "ls180.v:1966.5-1966.82" + process $proc$ls180.v:1966$3957 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:1900.5-1900.44" - process $proc$ls180.v:1900$3717 + attribute \src "ls180.v:1967.5-1967.44" + process $proc$ls180.v:1967$3958 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end - attribute \src "ls180.v:1901.5-1901.49" - process $proc$ls180.v:1901$3718 + attribute \src "ls180.v:1968.5-1968.49" + process $proc$ls180.v:1968$3959 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end - attribute \src "ls180.v:1902.12-1902.75" - process $proc$ls180.v:1902$3719 + attribute \src "ls180.v:1969.12-1969.75" + process $proc$ls180.v:1969$3960 assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] end - attribute \src "ls180.v:1903.5-1903.70" - process $proc$ls180.v:1903$3720 + attribute \src "ls180.v:1970.5-1970.70" + process $proc$ls180.v:1970$3961 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1904.11-1904.60" - process $proc$ls180.v:1904$3721 + attribute \src "ls180.v:1971.11-1971.60" + process $proc$ls180.v:1971$3962 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end - attribute \src "ls180.v:1905.11-1905.65" - process $proc$ls180.v:1905$3722 + attribute \src "ls180.v:1972.11-1972.65" + process $proc$ls180.v:1972$3963 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end - attribute \src "ls180.v:1906.12-1906.87" - process $proc$ls180.v:1906$3723 + attribute \src "ls180.v:1973.12-1973.87" + process $proc$ls180.v:1973$3964 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end - attribute \src "ls180.v:1907.5-1907.82" - process $proc$ls180.v:1907$3724 + attribute \src "ls180.v:1974.5-1974.82" + process $proc$ls180.v:1974$3965 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:1908.12-1908.43" - process $proc$ls180.v:1908$3725 + attribute \src "ls180.v:1975.12-1975.43" + process $proc$ls180.v:1975$3966 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end - attribute \src "ls180.v:1909.5-1909.34" - process $proc$ls180.v:1909$3726 + attribute \src "ls180.v:1976.5-1976.34" + process $proc$ls180.v:1976$3967 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always sync init update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end - attribute \src "ls180.v:191.11-191.69" - process $proc$ls180.v:191$2931 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1910.11-1910.43" - process $proc$ls180.v:1910$3727 + attribute \src "ls180.v:1977.11-1977.43" + process $proc$ls180.v:1977$3968 assign { } { } assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1914.12-1914.54" - process $proc$ls180.v:1914$3728 + attribute \src "ls180.v:1979.12-1979.52" + process $proc$ls180.v:1979$3969 assign { } { } - assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 sync always + update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] sync init - update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1918.5-1918.44" - process $proc$ls180.v:1918$3729 + attribute \src "ls180.v:1980.12-1980.54" + process $proc$ls180.v:1980$3970 assign { } { } - assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 sync always + update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] sync init - update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:192.5-192.63" - process $proc$ls180.v:192$2932 + attribute \src "ls180.v:1981.12-1981.54" + process $proc$ls180.v:1981$3971 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init - update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1922.5-1922.44" - process $proc$ls180.v:1922$3730 + attribute \src "ls180.v:1982.11-1982.50" + process $proc$ls180.v:1982$3972 assign { } { } - assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 sync always - update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] sync init end - attribute \src "ls180.v:1925.12-1925.40" - process $proc$ls180.v:1925$3731 + attribute \src "ls180.v:1983.5-1983.44" + process $proc$ls180.v:1983$3973 assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 sync always + update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:1929.5-1929.30" - process $proc$ls180.v:1929$3732 + attribute \src "ls180.v:1984.5-1984.44" + process $proc$ls180.v:1984$3974 assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 sync always + update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "ls180.v:193.5-193.63" - process $proc$ls180.v:193$2933 + attribute \src "ls180.v:1985.5-1985.44" + process $proc$ls180.v:1985$3975 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:1935.11-1935.31" - process $proc$ls180.v:1935$3733 + attribute \src "ls180.v:1986.5-1986.43" + process $proc$ls180.v:1986$3976 assign { } { } - assign $1\builder_grant[2:0] 3'000 + assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 sync always + update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] sync init - update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:1936.11-1936.35" - process $proc$ls180.v:1936$3734 + attribute \src "ls180.v:1989.12-1989.65" + process $proc$ls180.v:1989$3977 assign { } { } - assign $1\builder_slave_sel[7:0] 8'00000000 + assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always + update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] sync init - update \builder_slave_sel $1\builder_slave_sel[7:0] end - attribute \src "ls180.v:1937.11-1937.37" - process $proc$ls180.v:1937$3735 + attribute \src "ls180.v:1993.5-1993.55" + process $proc$ls180.v:1993$3978 assign { } { } - assign $1\builder_slave_sel_r[7:0] 8'00000000 + assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 sync always + update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[7:0] end - attribute \src "ls180.v:1938.5-1938.25" - process $proc$ls180.v:1938$3736 + attribute \src "ls180.v:1997.5-1997.55" + process $proc$ls180.v:1997$3979 assign { } { } - assign $1\builder_error[0:0] 1'0 + assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 sync always + update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] sync init - update \builder_error $1\builder_error[0:0] end - attribute \src "ls180.v:1941.12-1941.39" - process $proc$ls180.v:1941$3737 + attribute \src "ls180.v:2000.12-2000.40" + process $proc$ls180.v:2000$3980 assign { } { } - assign $1\builder_count[19:0] 20'11110100001001000000 + assign $1\builder_shared_dat_r[31:0] 0 sync always sync init - update \builder_count $1\builder_count[19:0] + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:1945.11-1945.51" - process $proc$ls180.v:1945$3738 + attribute \src "ls180.v:2004.5-2004.30" + process $proc$ls180.v:2004$3981 assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_shared_ack[0:0] 1'0 sync always sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "ls180.v:195.5-195.62" - process $proc$ls180.v:195$2934 + attribute \src "ls180.v:2010.11-2010.31" + process $proc$ls180.v:2010$3982 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $1\builder_grant[2:0] 3'000 sync always sync init - update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] + update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:196.11-196.69" - process $proc$ls180.v:196$2935 + attribute \src "ls180.v:2011.12-2011.37" + process $proc$ls180.v:2011$3983 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 + assign $1\builder_slave_sel[12:0] 13'0000000000000 sync always - update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] sync init + update \builder_slave_sel $1\builder_slave_sel[12:0] end - attribute \src "ls180.v:197.11-197.69" - process $proc$ls180.v:197$2936 + attribute \src "ls180.v:2012.12-2012.39" + process $proc$ls180.v:2012$3984 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + assign $1\builder_slave_sel_r[12:0] 13'0000000000000 sync always - update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] end - attribute \src "ls180.v:1986.11-1986.51" - process $proc$ls180.v:1986$3739 + attribute \src "ls180.v:2013.5-2013.25" + process $proc$ls180.v:2013$3985 assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_error[0:0] 1'0 sync always sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + update \builder_error $1\builder_error[0:0] end - attribute \src "ls180.v:199.5-199.44" - process $proc$ls180.v:199$2937 + attribute \src "ls180.v:2016.12-2016.39" + process $proc$ls180.v:2016$3986 assign { } { } - assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + assign $1\builder_count[19:0] 20'11110100001001000000 sync always sync init - update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + update \builder_count $1\builder_count[19:0] end - attribute \src "ls180.v:200.5-200.47" - process $proc$ls180.v:200$2938 + attribute \src "ls180.v:2020.11-2020.51" + process $proc$ls180.v:2020$3987 assign { } { } - assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2015.11-2015.51" - process $proc$ls180.v:2015$3740 + attribute \src "ls180.v:2061.11-2061.51" + process $proc$ls180.v:2061$3988 assign { } { } - assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:202.12-202.53" - process $proc$ls180.v:202$2939 + attribute \src "ls180.v:2090.11-2090.51" + process $proc$ls180.v:2090$3989 assign { } { } - assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2028.11-2028.51" - process $proc$ls180.v:2028$3741 + attribute \src "ls180.v:2103.11-2103.51" + process $proc$ls180.v:2103$3990 assign { } { } assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2069.11-2069.51" - process $proc$ls180.v:2069$3742 - assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:209.5-209.40" - process $proc$ls180.v:209$2940 + attribute \src "ls180.v:213.5-213.40" + process $proc$ls180.v:213$3155 assign { } { } assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 sync always sync init update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:2110.11-2110.51" - process $proc$ls180.v:2110$3743 + attribute \src "ls180.v:2144.11-2144.51" + process $proc$ls180.v:2144$3991 assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:213.5-213.40" - process $proc$ls180.v:213$2941 + attribute \src "ls180.v:217.5-217.40" + process $proc$ls180.v:217$3156 assign { } { } assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 sync always update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init end - attribute \src "ls180.v:216.11-216.37" - process $proc$ls180.v:216$2942 + attribute \src "ls180.v:2185.11-2185.51" + process $proc$ls180.v:2185$3992 assign { } { } - assign $1\main_libresocsim_we[3:0] 4'0000 + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_we $1\main_libresocsim_we[3:0] + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2175.11-2175.51" - process $proc$ls180.v:2175$3744 + attribute \src "ls180.v:220.11-220.37" + process $proc$ls180.v:220$3157 assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_we[7:0] 8'00000000 sync always sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + update \main_libresocsim_we $1\main_libresocsim_we[7:0] end - attribute \src "ls180.v:218.12-218.49" - process $proc$ls180.v:218$2943 + attribute \src "ls180.v:222.12-222.49" + process $proc$ls180.v:222$3158 assign { } { } assign $1\main_libresocsim_load_storage[31:0] 0 sync always sync init update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] end - attribute \src "ls180.v:219.5-219.36" - process $proc$ls180.v:219$2944 + attribute \src "ls180.v:223.5-223.36" + process $proc$ls180.v:223$3159 assign { } { } assign $1\main_libresocsim_load_re[0:0] 1'0 sync always sync init update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end - attribute \src "ls180.v:220.12-220.51" - process $proc$ls180.v:220$2945 + attribute \src "ls180.v:224.12-224.51" + process $proc$ls180.v:224$3160 assign { } { } assign $1\main_libresocsim_reload_storage[31:0] 0 sync always sync init update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:221.5-221.38" - process $proc$ls180.v:221$2946 + attribute \src "ls180.v:225.5-225.38" + process $proc$ls180.v:225$3161 assign { } { } assign $1\main_libresocsim_reload_re[0:0] 1'0 sync always sync init update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] end - attribute \src "ls180.v:222.5-222.39" - process $proc$ls180.v:222$2947 + attribute \src "ls180.v:2250.11-2250.51" + process $proc$ls180.v:2250$3993 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:226.5-226.39" + process $proc$ls180.v:226$3162 assign { } { } assign $1\main_libresocsim_en_storage[0:0] 1'0 sync always sync init update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] end - attribute \src "ls180.v:223.5-223.34" - process $proc$ls180.v:223$2948 + attribute \src "ls180.v:227.5-227.34" + process $proc$ls180.v:227$3163 assign { } { } assign $1\main_libresocsim_en_re[0:0] 1'0 sync always sync init update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] end - attribute \src "ls180.v:224.5-224.49" - process $proc$ls180.v:224$2949 + attribute \src "ls180.v:228.5-228.49" + process $proc$ls180.v:228$3164 assign { } { } assign $1\main_libresocsim_update_value_storage[0:0] 1'0 sync always sync init update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end - attribute \src "ls180.v:225.5-225.44" - process $proc$ls180.v:225$2950 + attribute \src "ls180.v:229.5-229.44" + process $proc$ls180.v:229$3165 assign { } { } assign $1\main_libresocsim_update_value_re[0:0] 1'0 sync always sync init update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] end - attribute \src "ls180.v:226.12-226.49" - process $proc$ls180.v:226$2951 + attribute \src "ls180.v:230.12-230.49" + process $proc$ls180.v:230$3166 assign { } { } assign $1\main_libresocsim_value_status[31:0] 0 sync always sync init update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] end - attribute \src "ls180.v:230.5-230.41" - process $proc$ls180.v:230$2952 + attribute \src "ls180.v:234.5-234.41" + process $proc$ls180.v:234$3167 assign { } { } assign $1\main_libresocsim_zero_pending[0:0] 1'0 sync always sync init update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] end - attribute \src "ls180.v:2308.11-2308.51" - process $proc$ls180.v:2308$3745 - assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:232.5-232.39" - process $proc$ls180.v:232$2953 + attribute \src "ls180.v:236.5-236.39" + process $proc$ls180.v:236$3168 assign { } { } assign $1\main_libresocsim_zero_clear[0:0] 1'0 sync always sync init update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:233.5-233.45" - process $proc$ls180.v:233$2954 + attribute \src "ls180.v:237.5-237.45" + process $proc$ls180.v:237$3169 assign { } { } assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 sync always sync init update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] end - attribute \src "ls180.v:2389.11-2389.51" - process $proc$ls180.v:2389$3746 + attribute \src "ls180.v:2383.11-2383.51" + process $proc$ls180.v:2383$3994 assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2406.11-2406.51" - process $proc$ls180.v:2406$3747 + attribute \src "ls180.v:246.5-246.49" + process $proc$ls180.v:246$3170 assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:242.5-242.49" - process $proc$ls180.v:242$2955 + attribute \src "ls180.v:2464.11-2464.51" + process $proc$ls180.v:2464$3995 assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:243.5-243.44" - process $proc$ls180.v:243$2956 + attribute \src "ls180.v:247.5-247.44" + process $proc$ls180.v:247$3171 assign { } { } assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 sync always sync init update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end - attribute \src "ls180.v:244.12-244.42" - process $proc$ls180.v:244$2957 + attribute \src "ls180.v:248.12-248.42" + process $proc$ls180.v:248$3172 assign { } { } assign $1\main_libresocsim_value[31:0] 0 sync always sync init update \main_libresocsim_value $1\main_libresocsim_value[31:0] end - attribute \src "ls180.v:2447.11-2447.52" - process $proc$ls180.v:2447$3748 + attribute \src "ls180.v:2481.11-2481.51" + process $proc$ls180.v:2481$3996 assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2480.11-2480.52" - process $proc$ls180.v:2480$3749 + attribute \src "ls180.v:2522.11-2522.52" + process $proc$ls180.v:2522$3997 assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:251.5-251.39" - process $proc$ls180.v:251$2958 + attribute \src "ls180.v:255.5-255.39" + process $proc$ls180.v:255$3173 assign { } { } assign $1\main_interface0_ram_bus_ack[0:0] 1'0 sync always sync init update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] end - attribute \src "ls180.v:2521.11-2521.52" - process $proc$ls180.v:2521$3750 + attribute \src "ls180.v:2555.11-2555.52" + process $proc$ls180.v:2555$3998 assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:255.5-255.39" - process $proc$ls180.v:255$2959 + attribute \src "ls180.v:259.5-259.39" + process $proc$ls180.v:259$3174 assign { } { } assign $0\main_interface0_ram_bus_err[0:0] 1'0 sync always update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] sync init end - attribute \src "ls180.v:258.11-258.31" - process $proc$ls180.v:258$2960 + attribute \src "ls180.v:2596.11-2596.52" + process $proc$ls180.v:2596$3999 assign { } { } - assign $1\main_sram0_we[3:0] 4'0000 + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_sram0_we $1\main_sram0_we[3:0] + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2586.11-2586.52" - process $proc$ls180.v:2586$3751 + attribute \src "ls180.v:262.11-262.31" + process $proc$ls180.v:262$3175 + assign { } { } + assign $1\main_sram0_we[7:0] 8'00000000 + sync always + sync init + update \main_sram0_we $1\main_sram0_we[7:0] + end + attribute \src "ls180.v:2661.11-2661.52" + process $proc$ls180.v:2661$4000 assign { } { } assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2611.11-2611.52" - process $proc$ls180.v:2611$3752 + attribute \src "ls180.v:2686.11-2686.52" + process $proc$ls180.v:2686$4001 assign { } { } assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2633.11-2633.31" - process $proc$ls180.v:2633$3753 + attribute \src "ls180.v:270.5-270.39" + process $proc$ls180.v:270$3176 + assign { } { } + assign $1\main_interface1_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2708.11-2708.31" + process $proc$ls180.v:2708$4002 assign { } { } assign $1\builder_state[1:0] 2'00 sync always sync init update \builder_state $1\builder_state[1:0] end - attribute \src "ls180.v:2634.11-2634.36" - process $proc$ls180.v:2634$3754 + attribute \src "ls180.v:2709.11-2709.36" + process $proc$ls180.v:2709$4003 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always sync init update \builder_next_state $1\builder_next_state[1:0] end - attribute \src "ls180.v:2635.11-2635.55" - process $proc$ls180.v:2635$3755 + attribute \src "ls180.v:2710.11-2710.55" + process $proc$ls180.v:2710$4004 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end - attribute \src "ls180.v:2636.5-2636.52" - process $proc$ls180.v:2636$3756 + attribute \src "ls180.v:2711.5-2711.52" + process $proc$ls180.v:2711$4005 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always sync init update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end - attribute \src "ls180.v:2637.12-2637.55" - process $proc$ls180.v:2637$3757 + attribute \src "ls180.v:2712.12-2712.55" + process $proc$ls180.v:2712$4006 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end - attribute \src "ls180.v:2638.5-2638.50" - process $proc$ls180.v:2638$3758 + attribute \src "ls180.v:2713.5-2713.50" + process $proc$ls180.v:2713$4007 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always sync init update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end - attribute \src "ls180.v:2639.5-2639.46" - process $proc$ls180.v:2639$3759 + attribute \src "ls180.v:2714.5-2714.46" + process $proc$ls180.v:2714$4008 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end - attribute \src "ls180.v:2640.5-2640.49" - process $proc$ls180.v:2640$3760 + attribute \src "ls180.v:2715.5-2715.49" + process $proc$ls180.v:2715$4009 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:2641.5-2641.41" - process $proc$ls180.v:2641$3761 + attribute \src "ls180.v:2716.5-2716.41" + process $proc$ls180.v:2716$4010 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2642.12-2642.49" - process $proc$ls180.v:2642$3762 + attribute \src "ls180.v:2717.12-2717.49" + process $proc$ls180.v:2717$4011 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2643.11-2643.47" - process $proc$ls180.v:2643$3763 + attribute \src "ls180.v:2718.11-2718.47" + process $proc$ls180.v:2718$4012 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2644.5-2644.41" - process $proc$ls180.v:2644$3764 + attribute \src "ls180.v:2719.5-2719.41" + process $proc$ls180.v:2719$4013 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2645.5-2645.41" - process $proc$ls180.v:2645$3765 + attribute \src "ls180.v:2720.5-2720.41" + process $proc$ls180.v:2720$4014 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2646.5-2646.41" - process $proc$ls180.v:2646$3766 + attribute \src "ls180.v:2721.5-2721.41" + process $proc$ls180.v:2721$4015 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2647.5-2647.39" - process $proc$ls180.v:2647$3767 + attribute \src "ls180.v:2722.5-2722.39" + process $proc$ls180.v:2722$4016 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:2648.5-2648.39" - process $proc$ls180.v:2648$3768 + attribute \src "ls180.v:2723.5-2723.39" + process $proc$ls180.v:2723$4017 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:2649.5-2649.39" - process $proc$ls180.v:2649$3769 + attribute \src "ls180.v:2724.5-2724.39" + process $proc$ls180.v:2724$4018 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:2650.5-2650.41" - process $proc$ls180.v:2650$3770 + attribute \src "ls180.v:2725.5-2725.41" + process $proc$ls180.v:2725$4019 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2651.12-2651.49" - process $proc$ls180.v:2651$3771 + attribute \src "ls180.v:2726.12-2726.49" + process $proc$ls180.v:2726$4020 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2652.11-2652.47" - process $proc$ls180.v:2652$3772 + attribute \src "ls180.v:2727.11-2727.47" + process $proc$ls180.v:2727$4021 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2653.5-2653.41" - process $proc$ls180.v:2653$3773 + attribute \src "ls180.v:2728.5-2728.41" + process $proc$ls180.v:2728$4022 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2654.5-2654.42" - process $proc$ls180.v:2654$3774 + attribute \src "ls180.v:2729.5-2729.42" + process $proc$ls180.v:2729$4023 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2655.5-2655.42" - process $proc$ls180.v:2655$3775 + attribute \src "ls180.v:2730.5-2730.42" + process $proc$ls180.v:2730$4024 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2656.5-2656.39" - process $proc$ls180.v:2656$3776 + attribute \src "ls180.v:2731.5-2731.39" + process $proc$ls180.v:2731$4025 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:2657.5-2657.39" - process $proc$ls180.v:2657$3777 + attribute \src "ls180.v:2732.5-2732.39" + process $proc$ls180.v:2732$4026 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:2658.5-2658.39" - process $proc$ls180.v:2658$3778 + attribute \src "ls180.v:2733.5-2733.39" + process $proc$ls180.v:2733$4027 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:2659.12-2659.50" - process $proc$ls180.v:2659$3779 + attribute \src "ls180.v:2734.12-2734.50" + process $proc$ls180.v:2734$4028 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:266.5-266.39" - process $proc$ls180.v:266$2961 - assign { } { } - assign $1\main_interface1_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2660.5-2660.42" - process $proc$ls180.v:2660$3780 + attribute \src "ls180.v:2735.5-2735.42" + process $proc$ls180.v:2735$4029 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:2661.5-2661.42" - process $proc$ls180.v:2661$3781 + attribute \src "ls180.v:2736.5-2736.42" + process $proc$ls180.v:2736$4030 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2662.12-2662.50" - process $proc$ls180.v:2662$3782 + attribute \src "ls180.v:2737.12-2737.50" + process $proc$ls180.v:2737$4031 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2663.5-2663.42" - process $proc$ls180.v:2663$3783 + attribute \src "ls180.v:2738.5-2738.42" + process $proc$ls180.v:2738$4032 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2664.5-2664.42" - process $proc$ls180.v:2664$3784 + attribute \src "ls180.v:2739.5-2739.42" + process $proc$ls180.v:2739$4033 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:2665.12-2665.50" - process $proc$ls180.v:2665$3785 + attribute \src "ls180.v:274.5-274.39" + process $proc$ls180.v:274$3177 + assign { } { } + assign $0\main_interface1_ram_bus_err[0:0] 1'0 + sync always + update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2740.12-2740.50" + process $proc$ls180.v:2740$4034 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2666.5-2666.42" - process $proc$ls180.v:2666$3786 + attribute \src "ls180.v:2741.5-2741.42" + process $proc$ls180.v:2741$4035 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2667.5-2667.42" - process $proc$ls180.v:2667$3787 + attribute \src "ls180.v:2742.5-2742.42" + process $proc$ls180.v:2742$4036 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:2668.12-2668.50" - process $proc$ls180.v:2668$3788 + attribute \src "ls180.v:2743.12-2743.50" + process $proc$ls180.v:2743$4037 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2669.5-2669.42" - process $proc$ls180.v:2669$3789 + attribute \src "ls180.v:2744.5-2744.42" + process $proc$ls180.v:2744$4038 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:2670.5-2670.42" - process $proc$ls180.v:2670$3790 + attribute \src "ls180.v:2745.5-2745.42" + process $proc$ls180.v:2745$4039 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2671.12-2671.50" - process $proc$ls180.v:2671$3791 + attribute \src "ls180.v:2746.12-2746.50" + process $proc$ls180.v:2746$4040 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:2672.12-2672.50" - process $proc$ls180.v:2672$3792 + attribute \src "ls180.v:2747.12-2747.50" + process $proc$ls180.v:2747$4041 assign { } { } - assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:2673.11-2673.48" - process $proc$ls180.v:2673$3793 + attribute \src "ls180.v:2748.11-2748.48" + process $proc$ls180.v:2748$4042 assign { } { } - assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:2674.5-2674.42" - process $proc$ls180.v:2674$3794 + attribute \src "ls180.v:2749.5-2749.42" + process $proc$ls180.v:2749$4043 assign { } { } assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2675.5-2675.42" - process $proc$ls180.v:2675$3795 + attribute \src "ls180.v:2750.5-2750.42" + process $proc$ls180.v:2750$4044 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2676.5-2676.42" - process $proc$ls180.v:2676$3796 + attribute \src "ls180.v:2751.5-2751.42" + process $proc$ls180.v:2751$4045 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2677.11-2677.48" - process $proc$ls180.v:2677$3797 + attribute \src "ls180.v:2752.11-2752.48" + process $proc$ls180.v:2752$4046 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always sync init update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2678.11-2678.48" - process $proc$ls180.v:2678$3798 + attribute \src "ls180.v:2753.11-2753.48" + process $proc$ls180.v:2753$4047 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2679.11-2679.47" - process $proc$ls180.v:2679$3799 + attribute \src "ls180.v:2754.11-2754.47" + process $proc$ls180.v:2754$4048 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always sync init update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:2680.12-2680.49" - process $proc$ls180.v:2680$3800 + attribute \src "ls180.v:2755.12-2755.49" + process $proc$ls180.v:2755$4049 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2681.5-2681.41" - process $proc$ls180.v:2681$3801 + attribute \src "ls180.v:2756.5-2756.41" + process $proc$ls180.v:2756$4050 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:2682.5-2682.41" - process $proc$ls180.v:2682$3802 + attribute \src "ls180.v:2757.5-2757.41" + process $proc$ls180.v:2757$4051 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2683.5-2683.41" - process $proc$ls180.v:2683$3803 + attribute \src "ls180.v:2758.5-2758.41" + process $proc$ls180.v:2758$4052 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2684.5-2684.41" - process $proc$ls180.v:2684$3804 + attribute \src "ls180.v:2759.5-2759.41" + process $proc$ls180.v:2759$4053 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2685.5-2685.41" - process $proc$ls180.v:2685$3805 + attribute \src "ls180.v:2760.5-2760.41" + process $proc$ls180.v:2760$4054 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2686.5-2686.39" - process $proc$ls180.v:2686$3806 + attribute \src "ls180.v:2761.5-2761.39" + process $proc$ls180.v:2761$4055 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:2687.5-2687.39" - process $proc$ls180.v:2687$3807 + attribute \src "ls180.v:2762.5-2762.39" + process $proc$ls180.v:2762$4056 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:270.5-270.39" - process $proc$ls180.v:270$2962 - assign { } { } - assign $0\main_interface1_ram_bus_err[0:0] 1'0 - sync always - update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:273.11-273.31" - process $proc$ls180.v:273$2963 + attribute \src "ls180.v:277.11-277.31" + process $proc$ls180.v:277$3178 assign { } { } - assign $1\main_sram1_we[3:0] 4'0000 + assign $1\main_sram1_we[7:0] 8'00000000 sync always sync init - update \main_sram1_we $1\main_sram1_we[3:0] + update \main_sram1_we $1\main_sram1_we[7:0] end - attribute \src "ls180.v:2744.32-2744.66" - process $proc$ls180.v:2744$3808 + attribute \src "ls180.v:2819.32-2819.66" + process $proc$ls180.v:2819$4057 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end - attribute \src "ls180.v:2745.32-2745.66" - process $proc$ls180.v:2745$3809 + attribute \src "ls180.v:2820.32-2820.66" + process $proc$ls180.v:2820$4058 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end - attribute \src "ls180.v:2746.32-2746.66" - process $proc$ls180.v:2746$3810 + attribute \src "ls180.v:2821.32-2821.66" + process $proc$ls180.v:2821$4059 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end - attribute \src "ls180.v:2747.32-2747.66" - process $proc$ls180.v:2747$3811 + attribute \src "ls180.v:2822.32-2822.66" + process $proc$ls180.v:2822$4060 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end - attribute \src "ls180.v:2748.32-2748.66" - process $proc$ls180.v:2748$3812 + attribute \src "ls180.v:2823.32-2823.66" + process $proc$ls180.v:2823$4061 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end - attribute \src "ls180.v:2749.32-2749.66" - process $proc$ls180.v:2749$3813 + attribute \src "ls180.v:2824.32-2824.66" + process $proc$ls180.v:2824$4062 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end - attribute \src "ls180.v:2750.32-2750.66" - process $proc$ls180.v:2750$3814 + attribute \src "ls180.v:2825.32-2825.66" + process $proc$ls180.v:2825$4063 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end - attribute \src "ls180.v:2751.32-2751.66" - process $proc$ls180.v:2751$3815 + attribute \src "ls180.v:2826.32-2826.66" + process $proc$ls180.v:2826$4064 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end - attribute \src "ls180.v:2752.32-2752.66" - process $proc$ls180.v:2752$3816 + attribute \src "ls180.v:2827.32-2827.66" + process $proc$ls180.v:2827$4065 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end - attribute \src "ls180.v:2753.32-2753.66" - process $proc$ls180.v:2753$3817 + attribute \src "ls180.v:2828.32-2828.66" + process $proc$ls180.v:2828$4066 assign { } { } assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end - attribute \src "ls180.v:2754.32-2754.66" - process $proc$ls180.v:2754$3818 + attribute \src "ls180.v:2829.32-2829.66" + process $proc$ls180.v:2829$4067 assign { } { } assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end - attribute \src "ls180.v:2755.32-2755.66" - process $proc$ls180.v:2755$3819 + attribute \src "ls180.v:2830.32-2830.66" + process $proc$ls180.v:2830$4068 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end - attribute \src "ls180.v:2756.32-2756.66" - process $proc$ls180.v:2756$3820 + attribute \src "ls180.v:2831.32-2831.66" + process $proc$ls180.v:2831$4069 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end - attribute \src "ls180.v:2757.32-2757.66" - process $proc$ls180.v:2757$3821 + attribute \src "ls180.v:2832.32-2832.66" + process $proc$ls180.v:2832$4070 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end - attribute \src "ls180.v:2758.32-2758.66" - process $proc$ls180.v:2758$3822 + attribute \src "ls180.v:2833.32-2833.66" + process $proc$ls180.v:2833$4071 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end - attribute \src "ls180.v:2759.32-2759.66" - process $proc$ls180.v:2759$3823 + attribute \src "ls180.v:2834.32-2834.66" + process $proc$ls180.v:2834$4072 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end - attribute \src "ls180.v:2760.32-2760.66" - process $proc$ls180.v:2760$3824 + attribute \src "ls180.v:2835.32-2835.66" + process $proc$ls180.v:2835$4073 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end - attribute \src "ls180.v:2761.32-2761.66" - process $proc$ls180.v:2761$3825 + attribute \src "ls180.v:2836.32-2836.66" + process $proc$ls180.v:2836$4074 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end - attribute \src "ls180.v:2762.32-2762.66" - process $proc$ls180.v:2762$3826 + attribute \src "ls180.v:2837.32-2837.66" + process $proc$ls180.v:2837$4075 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end - attribute \src "ls180.v:2763.32-2763.66" - process $proc$ls180.v:2763$3827 + attribute \src "ls180.v:2838.32-2838.66" + process $proc$ls180.v:2838$4076 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end - attribute \src "ls180.v:2764.32-2764.67" - process $proc$ls180.v:2764$3828 + attribute \src "ls180.v:2839.32-2839.67" + process $proc$ls180.v:2839$4077 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end - attribute \src "ls180.v:2765.32-2765.67" - process $proc$ls180.v:2765$3829 + attribute \src "ls180.v:2840.32-2840.67" + process $proc$ls180.v:2840$4078 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end - attribute \src "ls180.v:2766.32-2766.67" - process $proc$ls180.v:2766$3830 + attribute \src "ls180.v:2841.32-2841.67" + process $proc$ls180.v:2841$4079 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end - attribute \src "ls180.v:2767.32-2767.67" - process $proc$ls180.v:2767$3831 + attribute \src "ls180.v:2842.32-2842.67" + process $proc$ls180.v:2842$4080 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end - attribute \src "ls180.v:2768.32-2768.67" - process $proc$ls180.v:2768$3832 + attribute \src "ls180.v:2843.32-2843.67" + process $proc$ls180.v:2843$4081 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end - attribute \src "ls180.v:2769.32-2769.67" - process $proc$ls180.v:2769$3833 + attribute \src "ls180.v:2844.32-2844.67" + process $proc$ls180.v:2844$4082 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end - attribute \src "ls180.v:2770.32-2770.67" - process $proc$ls180.v:2770$3834 + attribute \src "ls180.v:2845.32-2845.67" + process $proc$ls180.v:2845$4083 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end - attribute \src "ls180.v:2771.32-2771.67" - process $proc$ls180.v:2771$3835 + attribute \src "ls180.v:2846.32-2846.67" + process $proc$ls180.v:2846$4084 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end - attribute \src "ls180.v:2772.32-2772.67" - process $proc$ls180.v:2772$3836 + attribute \src "ls180.v:2847.32-2847.67" + process $proc$ls180.v:2847$4085 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end - attribute \src "ls180.v:2773.32-2773.67" - process $proc$ls180.v:2773$3837 + attribute \src "ls180.v:2848.32-2848.67" + process $proc$ls180.v:2848$4086 assign { } { } assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end - attribute \src "ls180.v:2774.32-2774.67" - process $proc$ls180.v:2774$3838 + attribute \src "ls180.v:2849.32-2849.67" + process $proc$ls180.v:2849$4087 assign { } { } assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end - attribute \src "ls180.v:2775.32-2775.67" - process $proc$ls180.v:2775$3839 + attribute \src "ls180.v:285.5-285.39" + process $proc$ls180.v:285$3179 + assign { } { } + assign $1\main_interface2_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2850.32-2850.67" + process $proc$ls180.v:2850$4088 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end - attribute \src "ls180.v:2776.32-2776.67" - process $proc$ls180.v:2776$3840 + attribute \src "ls180.v:2851.32-2851.67" + process $proc$ls180.v:2851$4089 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end - attribute \src "ls180.v:2777.32-2777.67" - process $proc$ls180.v:2777$3841 + attribute \src "ls180.v:2852.32-2852.67" + process $proc$ls180.v:2852$4090 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:281.5-281.39" - process $proc$ls180.v:281$2964 - assign { } { } - assign $1\main_interface2_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2812.1-2817.4" - process $proc$ls180.v:2812$25 + attribute \src "ls180.v:2887.1-2892.4" + process $proc$ls180.v:2887$49 assign { } { } assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } @@ -269742,25 +288220,33 @@ module \ls180 sync always update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:2819.1-2829.4" - process $proc$ls180.v:2819$27 + attribute \src "ls180.v:289.5-289.39" + process $proc$ls180.v:289$3180 + assign { } { } + assign $0\main_interface2_ram_bus_err[0:0] 1'0 + sync always + update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2894.1-2904.4" + process $proc$ls180.v:2894$51 assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2821.2-2828.9" - switch \main_libresocsim_converter0_counter + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + attribute \src "ls180.v:2896.2-2903.9" + switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:2831.1-2877.4" - process $proc$ls180.v:2831$28 + attribute \src "ls180.v:2906.1-2952.4" + process $proc$ls180.v:2906$52 assign { } { } assign { } { } assign { } { } @@ -269772,50 +288258,50 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_converter0_skip[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_interface0_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $0\main_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2843.2-2876.9" + attribute \src "ls180.v:2918.2-2951.9" switch \builder_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } - attribute \src "ls180.v:2846.4-2853.11" - switch \main_libresocsim_converter0_counter + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } + attribute \src "ls180.v:2921.4-2928.11" + switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2854.4-2867.7" - switch $and$ls180.v:2854$29_Y - attribute \src "ls180.v:2854.8-2854.81" + attribute \src "ls180.v:2929.4-2942.7" + switch $and$ls180.v:2929$53_Y + attribute \src "ls180.v:2929.8-2929.91" case 1'1 - assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2855$30_Y - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2857$31_Y - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2858$32_Y - attribute \src "ls180.v:2859.5-2866.8" - switch $or$ls180.v:2859$33_Y - attribute \src "ls180.v:2859.9-2859.97" + assign $0\main_converter0_skip[0:0] $eq$ls180.v:2930$54_Y + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2932$55_Y + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2933$56_Y + attribute \src "ls180.v:2934.5-2941.8" + switch $or$ls180.v:2934$57_Y + attribute \src "ls180.v:2934.9-2934.72" case 1'1 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2860$34_Y - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2862.6-2865.9" - switch $eq$ls180.v:2862$35_Y - attribute \src "ls180.v:2862.10-2862.55" + assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2935$58_Y + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2937.6-2940.9" + switch $eq$ls180.v:2937$59_Y + attribute \src "ls180.v:2937.10-2937.43" case 1'1 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\main_interface0_converted_interface_ack[0:0] 1'1 assign $0\builder_converter0_next_state[0:0] 1'0 case end @@ -269825,63 +288311,55 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2872.4-2874.7" - switch $and$ls180.v:2872$36_Y - attribute \src "ls180.v:2872.8-2872.81" + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2947.4-2949.7" + switch $and$ls180.v:2947$60_Y + attribute \src "ls180.v:2947.8-2947.91" case 1'1 assign $0\builder_converter0_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] - update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] - update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] - update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] - update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] - update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] + update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] + update \main_converter0_skip $0\main_converter0_skip[0:0] update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:285.5-285.39" - process $proc$ls180.v:285$2965 + attribute \src "ls180.v:292.11-292.31" + process $proc$ls180.v:292$3181 assign { } { } - assign $0\main_interface2_ram_bus_err[0:0] 1'0 + assign $1\main_sram2_we[7:0] 8'00000000 sync always - update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] sync init + update \main_sram2_we $1\main_sram2_we[7:0] end - attribute \src "ls180.v:2879.1-2889.4" - process $proc$ls180.v:2879$38 + attribute \src "ls180.v:2954.1-2964.4" + process $proc$ls180.v:2954$62 assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2881.2-2888.9" - switch \main_libresocsim_converter1_counter + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + attribute \src "ls180.v:2956.2-2963.9" + switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:288.11-288.31" - process $proc$ls180.v:288$2966 - assign { } { } - assign $1\main_sram2_we[3:0] 4'0000 - sync always - sync init - update \main_sram2_we $1\main_sram2_we[3:0] - end - attribute \src "ls180.v:2891.1-2937.4" - process $proc$ls180.v:2891$39 + attribute \src "ls180.v:2966.1-3012.4" + process $proc$ls180.v:2966$63 assign { } { } assign { } { } assign { } { } @@ -269892,51 +288370,51 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_converter1_skip[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + assign $0\main_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 assign { } { } - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2903.2-2936.9" + attribute \src "ls180.v:2978.2-3011.9" switch \builder_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } - attribute \src "ls180.v:2906.4-2913.11" - switch \main_libresocsim_converter1_counter + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } + attribute \src "ls180.v:2981.4-2988.11" + switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2914.4-2927.7" - switch $and$ls180.v:2914$40_Y - attribute \src "ls180.v:2914.8-2914.81" + attribute \src "ls180.v:2989.4-3002.7" + switch $and$ls180.v:2989$64_Y + attribute \src "ls180.v:2989.8-2989.91" case 1'1 - assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2915$41_Y - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2917$42_Y - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2918$43_Y - attribute \src "ls180.v:2919.5-2926.8" - switch $or$ls180.v:2919$44_Y - attribute \src "ls180.v:2919.9-2919.97" + assign $0\main_converter1_skip[0:0] $eq$ls180.v:2990$65_Y + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2992$66_Y + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2993$67_Y + attribute \src "ls180.v:2994.5-3001.8" + switch $or$ls180.v:2994$68_Y + attribute \src "ls180.v:2994.9-2994.72" case 1'1 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2920$45_Y - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2922.6-2925.9" - switch $eq$ls180.v:2922$46_Y - attribute \src "ls180.v:2922.10-2922.55" + assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2995$69_Y + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2997.6-3000.9" + switch $eq$ls180.v:2997$70_Y + attribute \src "ls180.v:2997.10-2997.43" case 1'1 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\main_interface1_converted_interface_ack[0:0] 1'1 assign $0\builder_converter1_next_state[0:0] 1'0 case end @@ -269946,55 +288424,55 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2932.4-2934.7" - switch $and$ls180.v:2932$47_Y - attribute \src "ls180.v:2932.8-2932.81" + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3007.4-3009.7" + switch $and$ls180.v:3007$71_Y + attribute \src "ls180.v:3007.8-3007.91" case 1'1 assign $0\builder_converter1_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] - update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] - update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] - update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] - update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] - update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] + update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] + update \main_converter1_skip $0\main_converter1_skip[0:0] update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] + update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:293.5-293.24" - process $proc$ls180.v:293$2967 + attribute \src "ls180.v:300.5-300.39" + process $proc$ls180.v:300$3182 assign { } { } - assign $1\main_int_rst[0:0] 1'1 + assign $1\main_interface3_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_int_rst $1\main_int_rst[0:0] + update \main_interface3_ram_bus_ack $1\main_interface3_ram_bus_ack[0:0] end - attribute \src "ls180.v:2939.1-2949.4" - process $proc$ls180.v:2939$49 + attribute \src "ls180.v:3014.1-3024.4" + process $proc$ls180.v:3014$73 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2941.2-2948.9" - switch \main_libresocsim_converter2_counter + assign $0\main_wb_sdram_dat_w[31:0] 0 + attribute \src "ls180.v:3016.2-3023.9" + switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] end - attribute \src "ls180.v:2951.1-2997.4" - process $proc$ls180.v:2951$50 + attribute \src "ls180.v:3026.1-3072.4" + process $proc$ls180.v:3026$74 assign { } { } assign { } { } assign { } { } @@ -270005,51 +288483,51 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 + assign $0\main_wb_sdram_sel[3:0] 4'0000 + assign $0\main_wb_sdram_cyc[0:0] 1'0 + assign $0\main_wb_sdram_stb[0:0] 1'0 + assign $0\main_socbushandler_skip[0:0] 1'0 assign { } { } - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:2963.2-2996.9" + attribute \src "ls180.v:3038.2-3071.9" switch \builder_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } - attribute \src "ls180.v:2966.4-2973.11" - switch \main_libresocsim_converter2_counter + assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } + attribute \src "ls180.v:3041.4-3048.11" + switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2974.4-2987.7" - switch $and$ls180.v:2974$51_Y - attribute \src "ls180.v:2974.8-2974.87" + attribute \src "ls180.v:3049.4-3062.7" + switch $and$ls180.v:3049$75_Y + attribute \src "ls180.v:3049.8-3049.97" case 1'1 - assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2975$52_Y - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2977$53_Y - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2978$54_Y - attribute \src "ls180.v:2979.5-2986.8" - switch $or$ls180.v:2979$55_Y - attribute \src "ls180.v:2979.9-2979.97" + assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3050$76_Y + assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we + assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3052$77_Y + assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3053$78_Y + attribute \src "ls180.v:3054.5-3061.8" + switch $or$ls180.v:3054$79_Y + attribute \src "ls180.v:3054.9-3054.54" case 1'1 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2980$56_Y - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2982.6-2985.9" - switch $eq$ls180.v:2982$57_Y - attribute \src "ls180.v:2982.10-2982.55" + assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3055$80_Y + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3057.6-3060.9" + switch $eq$ls180.v:3057$81_Y + attribute \src "ls180.v:3057.10-3057.46" case 1'1 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 assign $0\builder_converter2_next_state[0:0] 1'0 case end @@ -270059,46 +288537,66 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2992.4-2994.7" - switch $and$ls180.v:2992$58_Y - attribute \src "ls180.v:2992.8-2992.87" + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3067.4-3069.7" + switch $and$ls180.v:3067$82_Y + attribute \src "ls180.v:3067.8-3067.97" case 1'1 assign $0\builder_converter2_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] - update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] - update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] - update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] - update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] + update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] + update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] + update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] + update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] + update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] + update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] + update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:304.5-304.39" + process $proc$ls180.v:304$3183 + assign { } { } + assign $0\main_interface3_ram_bus_err[0:0] 1'0 + sync always + update \main_interface3_ram_bus_err $0\main_interface3_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:307.11-307.31" + process $proc$ls180.v:307$3184 + assign { } { } + assign $1\main_sram3_we[7:0] 8'00000000 + sync always + sync init + update \main_sram3_we $1\main_sram3_we[7:0] end - attribute \src "ls180.v:3000.1-3006.4" - process $proc$ls180.v:3000$59 + attribute \src "ls180.v:3075.1-3085.4" + process $proc$ls180.v:3075$83 assign { } { } assign { } { } - assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:3002$62_Y - assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:3003$65_Y - assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:3004$68_Y - assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:3005$71_Y + assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3077$86_Y + assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3078$89_Y + assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3079$92_Y + assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3080$95_Y + assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3081$98_Y + assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3082$101_Y + assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3083$104_Y + assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3084$107_Y sync always - update \main_libresocsim_we $0\main_libresocsim_we[3:0] + update \main_libresocsim_we $0\main_libresocsim_we[7:0] end - attribute \src "ls180.v:3012.1-3017.4" - process $proc$ls180.v:3012$73 + attribute \src "ls180.v:3091.1-3096.4" + process $proc$ls180.v:3091$109 assign { } { } assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:3014.2-3016.5" - switch $and$ls180.v:3014$74_Y - attribute \src "ls180.v:3014.6-3014.90" + attribute \src "ls180.v:3093.2-3095.5" + switch $and$ls180.v:3093$110_Y + attribute \src "ls180.v:3093.6-3093.90" case 1'1 assign $0\main_libresocsim_zero_clear[0:0] 1'1 case @@ -270106,49 +288604,84 @@ module \ls180 sync always update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:3021.1-3027.4" - process $proc$ls180.v:3021$76 + attribute \src "ls180.v:3100.1-3110.4" + process $proc$ls180.v:3100$112 assign { } { } assign { } { } - assign $0\main_sram0_we[3:0] [0] $and$ls180.v:3023$79_Y - assign $0\main_sram0_we[3:0] [1] $and$ls180.v:3024$82_Y - assign $0\main_sram0_we[3:0] [2] $and$ls180.v:3025$85_Y - assign $0\main_sram0_we[3:0] [3] $and$ls180.v:3026$88_Y + assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3102$115_Y + assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3103$118_Y + assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3104$121_Y + assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3105$124_Y + assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3106$127_Y + assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3107$130_Y + assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3108$133_Y + assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3109$136_Y sync always - update \main_sram0_we $0\main_sram0_we[3:0] + update \main_sram0_we $0\main_sram0_we[7:0] end - attribute \src "ls180.v:3031.1-3037.4" - process $proc$ls180.v:3031$89 + attribute \src "ls180.v:3114.1-3124.4" + process $proc$ls180.v:3114$137 assign { } { } assign { } { } - assign $0\main_sram1_we[3:0] [0] $and$ls180.v:3033$92_Y - assign $0\main_sram1_we[3:0] [1] $and$ls180.v:3034$95_Y - assign $0\main_sram1_we[3:0] [2] $and$ls180.v:3035$98_Y - assign $0\main_sram1_we[3:0] [3] $and$ls180.v:3036$101_Y + assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3116$140_Y + assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3117$143_Y + assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3118$146_Y + assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3119$149_Y + assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3120$152_Y + assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3121$155_Y + assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3122$158_Y + assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3123$161_Y sync always - update \main_sram1_we $0\main_sram1_we[3:0] + update \main_sram1_we $0\main_sram1_we[7:0] end - attribute \src "ls180.v:3041.1-3047.4" - process $proc$ls180.v:3041$102 + attribute \src "ls180.v:3128.1-3138.4" + process $proc$ls180.v:3128$162 assign { } { } assign { } { } - assign $0\main_sram2_we[3:0] [0] $and$ls180.v:3043$105_Y - assign $0\main_sram2_we[3:0] [1] $and$ls180.v:3044$108_Y - assign $0\main_sram2_we[3:0] [2] $and$ls180.v:3045$111_Y - assign $0\main_sram2_we[3:0] [3] $and$ls180.v:3046$114_Y + assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3130$165_Y + assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3131$168_Y + assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3132$171_Y + assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3133$174_Y + assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3134$177_Y + assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3135$180_Y + assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3136$183_Y + assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3137$186_Y sync always - update \main_sram2_we $0\main_sram2_we[3:0] + update \main_sram2_we $0\main_sram2_we[7:0] end - attribute \src "ls180.v:308.12-308.38" - process $proc$ls180.v:308$2968 + attribute \src "ls180.v:3142.1-3152.4" + process $proc$ls180.v:3142$187 assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + assign { } { } + assign $0\main_sram3_we[7:0] [0] $and$ls180.v:3144$190_Y + assign $0\main_sram3_we[7:0] [1] $and$ls180.v:3145$193_Y + assign $0\main_sram3_we[7:0] [2] $and$ls180.v:3146$196_Y + assign $0\main_sram3_we[7:0] [3] $and$ls180.v:3147$199_Y + assign $0\main_sram3_we[7:0] [4] $and$ls180.v:3148$202_Y + assign $0\main_sram3_we[7:0] [5] $and$ls180.v:3149$205_Y + assign $0\main_sram3_we[7:0] [6] $and$ls180.v:3150$208_Y + assign $0\main_sram3_we[7:0] [7] $and$ls180.v:3151$211_Y + sync always + update \main_sram3_we $0\main_sram3_we[7:0] + end + attribute \src "ls180.v:315.5-315.51" + process $proc$ls180.v:315$3185 + assign { } { } + assign $1\main_interface0_converted_interface_ack[0:0] 1'0 sync always sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] + end + attribute \src "ls180.v:319.5-319.51" + process $proc$ls180.v:319$3186 + assign { } { } + assign $0\main_interface0_converted_interface_err[0:0] 1'0 + sync always + update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] + sync init end - attribute \src "ls180.v:3086.1-3140.4" - process $proc$ls180.v:3086$115 + attribute \src "ls180.v:3191.1-3245.4" + process $proc$ls180.v:3191$212 assign { } { } assign { } { } assign { } { } @@ -270185,9 +288718,9 @@ module \ls180 assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - attribute \src "ls180.v:3105.2-3139.5" + attribute \src "ls180.v:3210.2-3244.5" switch \main_sdram_sel - attribute \src "ls180.v:3105.6-3105.20" + attribute \src "ls180.v:3210.6-3210.20" case 1'1 assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank @@ -270205,7 +288738,7 @@ module \ls180 assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3122.6-3122.10" + attribute \src "ls180.v:3227.6-3227.10" case assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank @@ -270244,57 +288777,49 @@ module \ls180 update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:309.5-309.36" - process $proc$ls180.v:309$2969 + attribute \src "ls180.v:320.5-320.32" + process $proc$ls180.v:320$3187 assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $1\main_converter0_skip[0:0] 1'0 sync always sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + update \main_converter0_skip $1\main_converter0_skip[0:0] end - attribute \src "ls180.v:310.11-310.32" - process $proc$ls180.v:310$2970 + attribute \src "ls180.v:321.5-321.35" + process $proc$ls180.v:321$3188 assign { } { } - assign $1\main_rddata_en[2:0] 3'000 + assign $1\main_converter0_counter[0:0] 1'0 sync always sync init - update \main_rddata_en $1\main_rddata_en[2:0] + update \main_converter0_counter $1\main_converter0_counter[0:0] end - attribute \src "ls180.v:313.5-313.36" - process $proc$ls180.v:313$2971 + attribute \src "ls180.v:323.12-323.41" + process $proc$ls180.v:323$3189 assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] end - attribute \src "ls180.v:314.5-314.35" - process $proc$ls180.v:314$2972 - assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] - end - attribute \src "ls180.v:3144.1-3160.4" - process $proc$ls180.v:3144$116 + attribute \src "ls180.v:3249.1-3265.4" + process $proc$ls180.v:3249$213 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - attribute \src "ls180.v:3149.2-3159.5" + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + attribute \src "ls180.v:3254.2-3264.5" switch \main_sdram_command_issue_re - attribute \src "ls180.v:3149.6-3149.33" + attribute \src "ls180.v:3254.6-3254.33" case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3150$117_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3151$118_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3152$119_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3153$120_Y - attribute \src "ls180.v:3154.6-3154.10" + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3255$214_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3256$215_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3257$216_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3258$217_Y + attribute \src "ls180.v:3259.6-3259.10" case assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 @@ -270307,49 +288832,33 @@ module \ls180 update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:315.5-315.36" - process $proc$ls180.v:315$2973 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:316.5-316.35" - process $proc$ls180.v:316$2974 + attribute \src "ls180.v:330.5-330.51" + process $proc$ls180.v:330$3190 assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:320.5-320.36" - process $proc$ls180.v:320$2975 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + assign $1\main_interface1_converted_interface_ack[0:0] 1'0 sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init + update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] end - attribute \src "ls180.v:3203.1-3233.4" - process $proc$ls180.v:3203$129 + attribute \src "ls180.v:3308.1-3338.4" + process $proc$ls180.v:3308$226 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign { } { } assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign { } { } assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3209.2-3232.9" + attribute \src "ls180.v:3314.2-3337.9" switch \builder_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3212.4-3215.7" + attribute \src "ls180.v:3317.4-3320.7" switch \main_sdram_cmd_ready - attribute \src "ls180.v:3212.8-3212.28" + attribute \src "ls180.v:3317.8-3317.28" case 1'1 assign $0\main_sdram_sequencer_start0[0:0] 1'1 assign $0\builder_refresher_next_state[1:0] 2'10 @@ -270358,9 +288867,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3219.4-3223.7" + attribute \src "ls180.v:3324.4-3328.7" switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3219.8-3219.34" + attribute \src "ls180.v:3324.8-3324.34" case 1'1 assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\main_sdram_cmd_last[0:0] 1'1 @@ -270369,13 +288878,13 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3226.4-3230.7" + attribute \src "ls180.v:3331.4-3335.7" switch 1'1 - attribute \src "ls180.v:3226.8-3226.12" + attribute \src "ls180.v:3331.8-3331.12" case 1'1 - attribute \src "ls180.v:3227.5-3229.8" + attribute \src "ls180.v:3332.5-3334.8" switch \main_sdram_wants_refresh - attribute \src "ls180.v:3227.9-3227.33" + attribute \src "ls180.v:3332.9-3332.33" case 1'1 assign $0\builder_refresher_next_state[1:0] 2'01 case @@ -270389,43 +288898,59 @@ module \ls180 update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:3248.1-3255.4" - process $proc$ls180.v:3248$133 + attribute \src "ls180.v:334.5-334.51" + process $proc$ls180.v:334$3191 + assign { } { } + assign $0\main_interface1_converted_interface_err[0:0] 1'0 + sync always + update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:335.5-335.32" + process $proc$ls180.v:335$3192 + assign { } { } + assign $1\main_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_converter1_skip $1\main_converter1_skip[0:0] + end + attribute \src "ls180.v:3353.1-3360.4" + process $proc$ls180.v:3353$230 assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3250.2-3254.5" + attribute \src "ls180.v:3355.2-3359.5" switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3250.6-3250.48" + attribute \src "ls180.v:3355.6-3355.48" case 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3252.6-3252.10" + attribute \src "ls180.v:3357.6-3357.10" case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3253$135_Y + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3358$232_Y end sync always update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:325.12-325.45" - process $proc$ls180.v:325$2976 + attribute \src "ls180.v:336.5-336.35" + process $proc$ls180.v:336$3193 assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $1\main_converter1_counter[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + update \main_converter1_counter $1\main_converter1_counter[0:0] end - attribute \src "ls180.v:3259.1-3266.4" - process $proc$ls180.v:3259$142 + attribute \src "ls180.v:3364.1-3371.4" + process $proc$ls180.v:3364$239 assign { } { } assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3261.2-3265.5" - switch $and$ls180.v:3261$143_Y - attribute \src "ls180.v:3261.6-3261.115" + attribute \src "ls180.v:3366.2-3370.5" + switch $and$ls180.v:3366$240_Y + attribute \src "ls180.v:3366.6-3366.115" case 1'1 - attribute \src "ls180.v:3262.3-3264.6" - switch $ne$ls180.v:3262$144_Y - attribute \src "ls180.v:3262.7-3262.143" + attribute \src "ls180.v:3367.3-3369.6" + switch $ne$ls180.v:3367$241_Y + attribute \src "ls180.v:3367.7-3367.143" case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3263$145_Y + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3368$242_Y case end case @@ -270433,32 +288958,32 @@ module \ls180 sync always update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:326.5-326.43" - process $proc$ls180.v:326$2977 + attribute \src "ls180.v:338.12-338.41" + process $proc$ls180.v:338$3194 assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] end - attribute \src "ls180.v:3281.1-3288.4" - process $proc$ls180.v:3281$146 + attribute \src "ls180.v:3386.1-3393.4" + process $proc$ls180.v:3386$243 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3283.2-3287.5" + attribute \src "ls180.v:3388.2-3392.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3283.6-3283.58" + attribute \src "ls180.v:3388.6-3388.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3284$147_Y - attribute \src "ls180.v:3285.6-3285.10" + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3389$244_Y + attribute \src "ls180.v:3390.6-3390.10" case assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3297.1-3390.4" - process $proc$ls180.v:3297$155 + attribute \src "ls180.v:3402.1-3495.4" + process $proc$ls180.v:3402$252 assign { } { } assign { } { } assign { } { } @@ -270473,37 +288998,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3313.2-3389.9" + attribute \src "ls180.v:3418.2-3494.9" switch \builder_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3315.4-3323.7" - switch $and$ls180.v:3315$156_Y - attribute \src "ls180.v:3315.8-3315.87" + attribute \src "ls180.v:3420.4-3428.7" + switch $and$ls180.v:3420$253_Y + attribute \src "ls180.v:3420.8-3420.87" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3317.5-3319.8" + attribute \src "ls180.v:3422.5-3424.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3317.9-3317.42" + attribute \src "ls180.v:3422.9-3422.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case @@ -270513,27 +289038,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3327.4-3329.7" - switch $and$ls180.v:3327$157_Y - attribute \src "ls180.v:3327.8-3327.87" + attribute \src "ls180.v:3432.4-3434.7" + switch $and$ls180.v:3432$254_Y + attribute \src "ls180.v:3432.8-3432.87" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3333.4-3342.7" + attribute \src "ls180.v:3438.4-3447.7" switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3333.8-3333.44" + attribute \src "ls180.v:3438.8-3438.44" case 1'1 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3338.5-3340.8" + attribute \src "ls180.v:3443.5-3445.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3338.9-3338.42" + attribute \src "ls180.v:3443.9-3443.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'110 case @@ -270544,16 +289069,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3345.4-3347.7" + attribute \src "ls180.v:3450.4-3452.7" switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3345.8-3345.45" + attribute \src "ls180.v:3450.8-3450.45" case 1'1 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3350.4-3352.7" - switch $not$ls180.v:3350$158_Y - attribute \src "ls180.v:3350.8-3350.46" + attribute \src "ls180.v:3455.4-3457.7" + switch $not$ls180.v:3455$255_Y + attribute \src "ls180.v:3455.8-3455.46" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'000 case @@ -270566,51 +289091,51 @@ module \ls180 assign $0\builder_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3361.4-3387.7" + attribute \src "ls180.v:3466.4-3492.7" switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3361.8-3361.43" + attribute \src "ls180.v:3466.8-3466.43" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3363.8-3363.12" + attribute \src "ls180.v:3468.8-3468.12" case - attribute \src "ls180.v:3364.5-3386.8" + attribute \src "ls180.v:3469.5-3491.8" switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3364.9-3364.56" + attribute \src "ls180.v:3469.9-3469.56" case 1'1 - attribute \src "ls180.v:3365.6-3385.9" + attribute \src "ls180.v:3470.6-3490.9" switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3365.10-3365.44" + attribute \src "ls180.v:3470.10-3470.44" case 1'1 - attribute \src "ls180.v:3366.7-3382.10" + attribute \src "ls180.v:3471.7-3487.10" switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3366.11-3366.42" + attribute \src "ls180.v:3471.11-3471.42" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3368.8-3375.11" + attribute \src "ls180.v:3473.8-3480.11" switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3368.12-3368.64" + attribute \src "ls180.v:3473.12-3473.64" case 1'1 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3372.12-3372.16" + attribute \src "ls180.v:3477.12-3477.16" case assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3377.8-3379.11" - switch $and$ls180.v:3377$159_Y - attribute \src "ls180.v:3377.12-3377.88" + attribute \src "ls180.v:3482.8-3484.11" + switch $and$ls180.v:3482$256_Y + attribute \src "ls180.v:3482.12-3482.88" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3380.11-3380.15" + attribute \src "ls180.v:3485.11-3485.15" case assign $0\builder_bankmachine0_next_state[2:0] 3'001 end - attribute \src "ls180.v:3383.10-3383.14" + attribute \src "ls180.v:3488.10-3488.14" case assign $0\builder_bankmachine0_next_state[2:0] 3'011 end @@ -270634,43 +289159,43 @@ module \ls180 update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:3405.1-3412.4" - process $proc$ls180.v:3405$163 + attribute \src "ls180.v:342.5-342.24" + process $proc$ls180.v:342$3195 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:3510.1-3517.4" + process $proc$ls180.v:3510$260 assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3407.2-3411.5" + attribute \src "ls180.v:3512.2-3516.5" switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3407.6-3407.48" + attribute \src "ls180.v:3512.6-3512.48" case 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3409.6-3409.10" + attribute \src "ls180.v:3514.6-3514.10" case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3410$165_Y + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3515$262_Y end sync always update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:341.12-341.46" - process $proc$ls180.v:341$2978 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:3416.1-3423.4" - process $proc$ls180.v:3416$172 + attribute \src "ls180.v:3521.1-3528.4" + process $proc$ls180.v:3521$269 assign { } { } assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3418.2-3422.5" - switch $and$ls180.v:3418$173_Y - attribute \src "ls180.v:3418.6-3418.115" + attribute \src "ls180.v:3523.2-3527.5" + switch $and$ls180.v:3523$270_Y + attribute \src "ls180.v:3523.6-3523.115" case 1'1 - attribute \src "ls180.v:3419.3-3421.6" - switch $ne$ls180.v:3419$174_Y - attribute \src "ls180.v:3419.7-3419.143" + attribute \src "ls180.v:3524.3-3526.6" + switch $ne$ls180.v:3524$271_Y + attribute \src "ls180.v:3524.7-3524.143" case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3420$175_Y + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3525$272_Y case end case @@ -270678,57 +289203,24 @@ module \ls180 sync always update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:342.5-342.44" - process $proc$ls180.v:342$2979 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:343.12-343.48" - process $proc$ls180.v:343$2980 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:3438.1-3445.4" - process $proc$ls180.v:3438$176 + attribute \src "ls180.v:3543.1-3550.4" + process $proc$ls180.v:3543$273 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3440.2-3444.5" + attribute \src "ls180.v:3545.2-3549.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3440.6-3440.58" + attribute \src "ls180.v:3545.6-3545.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3441$177_Y - attribute \src "ls180.v:3442.6-3442.10" + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3546$274_Y + attribute \src "ls180.v:3547.6-3547.10" case assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:344.11-344.43" - process $proc$ls180.v:344$2981 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:345.5-345.38" - process $proc$ls180.v:345$2982 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:3454.1-3547.4" - process $proc$ls180.v:3454$185 - assign { } { } + attribute \src "ls180.v:3559.1-3652.4" + process $proc$ls180.v:3559$282 assign { } { } assign { } { } assign { } { } @@ -270742,10 +289234,9 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 @@ -270756,23 +289247,25 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3470.2-3546.9" + attribute \src "ls180.v:3575.2-3651.9" switch \builder_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3472.4-3480.7" - switch $and$ls180.v:3472$186_Y - attribute \src "ls180.v:3472.8-3472.87" + attribute \src "ls180.v:3577.4-3585.7" + switch $and$ls180.v:3577$283_Y + attribute \src "ls180.v:3577.8-3577.87" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3474.5-3476.8" + attribute \src "ls180.v:3579.5-3581.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3474.9-3474.42" + attribute \src "ls180.v:3579.9-3579.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case @@ -270782,27 +289275,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3484.4-3486.7" - switch $and$ls180.v:3484$187_Y - attribute \src "ls180.v:3484.8-3484.87" + attribute \src "ls180.v:3589.4-3591.7" + switch $and$ls180.v:3589$284_Y + attribute \src "ls180.v:3589.8-3589.87" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3490.4-3499.7" + attribute \src "ls180.v:3595.4-3604.7" switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3490.8-3490.44" + attribute \src "ls180.v:3595.8-3595.44" case 1'1 assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3495.5-3497.8" + attribute \src "ls180.v:3600.5-3602.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3495.9-3495.42" + attribute \src "ls180.v:3600.9-3600.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'110 case @@ -270813,16 +289306,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3502.4-3504.7" + attribute \src "ls180.v:3607.4-3609.7" switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3502.8-3502.45" + attribute \src "ls180.v:3607.8-3607.45" case 1'1 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3507.4-3509.7" - switch $not$ls180.v:3507$188_Y - attribute \src "ls180.v:3507.8-3507.46" + attribute \src "ls180.v:3612.4-3614.7" + switch $not$ls180.v:3612$285_Y + attribute \src "ls180.v:3612.8-3612.46" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'000 case @@ -270835,51 +289328,51 @@ module \ls180 assign $0\builder_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3518.4-3544.7" + attribute \src "ls180.v:3623.4-3649.7" switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3518.8-3518.43" + attribute \src "ls180.v:3623.8-3623.43" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3520.8-3520.12" + attribute \src "ls180.v:3625.8-3625.12" case - attribute \src "ls180.v:3521.5-3543.8" + attribute \src "ls180.v:3626.5-3648.8" switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3521.9-3521.56" + attribute \src "ls180.v:3626.9-3626.56" case 1'1 - attribute \src "ls180.v:3522.6-3542.9" + attribute \src "ls180.v:3627.6-3647.9" switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3522.10-3522.44" + attribute \src "ls180.v:3627.10-3627.44" case 1'1 - attribute \src "ls180.v:3523.7-3539.10" + attribute \src "ls180.v:3628.7-3644.10" switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3523.11-3523.42" + attribute \src "ls180.v:3628.11-3628.42" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3525.8-3532.11" + attribute \src "ls180.v:3630.8-3637.11" switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3525.12-3525.64" + attribute \src "ls180.v:3630.12-3630.64" case 1'1 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3529.12-3529.16" + attribute \src "ls180.v:3634.12-3634.16" case assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3534.8-3536.11" - switch $and$ls180.v:3534$189_Y - attribute \src "ls180.v:3534.12-3534.88" + attribute \src "ls180.v:3639.8-3641.11" + switch $and$ls180.v:3639$286_Y + attribute \src "ls180.v:3639.12-3639.88" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3537.11-3537.15" + attribute \src "ls180.v:3642.11-3642.15" case assign $0\builder_bankmachine1_next_state[2:0] 3'001 end - attribute \src "ls180.v:3540.10-3540.14" + attribute \src "ls180.v:3645.10-3645.14" case assign $0\builder_bankmachine1_next_state[2:0] 3'011 end @@ -270903,123 +289396,91 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:346.5-346.37" - process $proc$ls180.v:346$2983 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:347.5-347.38" - process $proc$ls180.v:347$2984 + attribute \src "ls180.v:357.12-357.38" + process $proc$ls180.v:357$3196 assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:348.5-348.37" - process $proc$ls180.v:348$2985 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:349.5-349.36" - process $proc$ls180.v:349$2986 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:350.5-350.36" - process $proc$ls180.v:350$2987 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] end - attribute \src "ls180.v:351.5-351.40" - process $proc$ls180.v:351$2988 + attribute \src "ls180.v:358.5-358.36" + process $proc$ls180.v:358$3197 assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] end - attribute \src "ls180.v:352.5-352.38" - process $proc$ls180.v:352$2989 + attribute \src "ls180.v:359.11-359.32" + process $proc$ls180.v:359$3198 assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + assign $1\main_rddata_en[2:0] 3'000 sync always sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + update \main_rddata_en $1\main_rddata_en[2:0] end - attribute \src "ls180.v:353.12-353.47" - process $proc$ls180.v:353$2990 + attribute \src "ls180.v:362.5-362.36" + process $proc$ls180.v:362$3199 assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] end - attribute \src "ls180.v:354.5-354.42" - process $proc$ls180.v:354$2991 + attribute \src "ls180.v:363.5-363.35" + process $proc$ls180.v:363$3200 assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 sync always sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] end - attribute \src "ls180.v:355.11-355.50" - process $proc$ls180.v:355$2992 + attribute \src "ls180.v:364.5-364.36" + process $proc$ls180.v:364$3201 assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:356.5-356.42" - process $proc$ls180.v:356$2993 + attribute \src "ls180.v:365.5-365.35" + process $proc$ls180.v:365$3202 assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:3562.1-3569.4" - process $proc$ls180.v:3562$193 + attribute \src "ls180.v:3667.1-3674.4" + process $proc$ls180.v:3667$290 assign { } { } assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3564.2-3568.5" + attribute \src "ls180.v:3669.2-3673.5" switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3564.6-3564.48" + attribute \src "ls180.v:3669.6-3669.48" case 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3566.6-3566.10" + attribute \src "ls180.v:3671.6-3671.10" case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3567$195_Y + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3672$292_Y end sync always update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:3573.1-3580.4" - process $proc$ls180.v:3573$202 + attribute \src "ls180.v:3678.1-3685.4" + process $proc$ls180.v:3678$299 assign { } { } assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3575.2-3579.5" - switch $and$ls180.v:3575$203_Y - attribute \src "ls180.v:3575.6-3575.115" + attribute \src "ls180.v:3680.2-3684.5" + switch $and$ls180.v:3680$300_Y + attribute \src "ls180.v:3680.6-3680.115" case 1'1 - attribute \src "ls180.v:3576.3-3578.6" - switch $ne$ls180.v:3576$204_Y - attribute \src "ls180.v:3576.7-3576.143" + attribute \src "ls180.v:3681.3-3683.6" + switch $ne$ls180.v:3681$301_Y + attribute \src "ls180.v:3681.7-3681.143" case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3577$205_Y + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3682$302_Y case end case @@ -271027,24 +289488,32 @@ module \ls180 sync always update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:3595.1-3602.4" - process $proc$ls180.v:3595$206 + attribute \src "ls180.v:369.5-369.36" + process $proc$ls180.v:369$3203 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:3700.1-3707.4" + process $proc$ls180.v:3700$303 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3597.2-3601.5" + attribute \src "ls180.v:3702.2-3706.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3597.6-3597.58" + attribute \src "ls180.v:3702.6-3702.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3598$207_Y - attribute \src "ls180.v:3599.6-3599.10" + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3703$304_Y + attribute \src "ls180.v:3704.6-3704.10" case assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3611.1-3704.4" - process $proc$ls180.v:3611$215 + attribute \src "ls180.v:3716.1-3809.4" + process $proc$ls180.v:3716$312 assign { } { } assign { } { } assign { } { } @@ -271059,37 +289528,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - assign { } { } assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3627.2-3703.9" + attribute \src "ls180.v:3732.2-3808.9" switch \builder_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3629.4-3637.7" - switch $and$ls180.v:3629$216_Y - attribute \src "ls180.v:3629.8-3629.87" + attribute \src "ls180.v:3734.4-3742.7" + switch $and$ls180.v:3734$313_Y + attribute \src "ls180.v:3734.8-3734.87" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3631.5-3633.8" + attribute \src "ls180.v:3736.5-3738.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3631.9-3631.42" + attribute \src "ls180.v:3736.9-3736.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case @@ -271099,27 +289568,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3641.4-3643.7" - switch $and$ls180.v:3641$217_Y - attribute \src "ls180.v:3641.8-3641.87" + attribute \src "ls180.v:3746.4-3748.7" + switch $and$ls180.v:3746$314_Y + attribute \src "ls180.v:3746.8-3746.87" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3647.4-3656.7" + attribute \src "ls180.v:3752.4-3761.7" switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3647.8-3647.44" + attribute \src "ls180.v:3752.8-3752.44" case 1'1 assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3652.5-3654.8" + attribute \src "ls180.v:3757.5-3759.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3652.9-3652.42" + attribute \src "ls180.v:3757.9-3757.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'110 case @@ -271130,16 +289599,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3659.4-3661.7" + attribute \src "ls180.v:3764.4-3766.7" switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3659.8-3659.45" + attribute \src "ls180.v:3764.8-3764.45" case 1'1 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3664.4-3666.7" - switch $not$ls180.v:3664$218_Y - attribute \src "ls180.v:3664.8-3664.46" + attribute \src "ls180.v:3769.4-3771.7" + switch $not$ls180.v:3769$315_Y + attribute \src "ls180.v:3769.8-3769.46" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'000 case @@ -271152,51 +289621,51 @@ module \ls180 assign $0\builder_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3675.4-3701.7" + attribute \src "ls180.v:3780.4-3806.7" switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3675.8-3675.43" + attribute \src "ls180.v:3780.8-3780.43" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3677.8-3677.12" + attribute \src "ls180.v:3782.8-3782.12" case - attribute \src "ls180.v:3678.5-3700.8" + attribute \src "ls180.v:3783.5-3805.8" switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3678.9-3678.56" + attribute \src "ls180.v:3783.9-3783.56" case 1'1 - attribute \src "ls180.v:3679.6-3699.9" + attribute \src "ls180.v:3784.6-3804.9" switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3679.10-3679.44" + attribute \src "ls180.v:3784.10-3784.44" case 1'1 - attribute \src "ls180.v:3680.7-3696.10" + attribute \src "ls180.v:3785.7-3801.10" switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3680.11-3680.42" + attribute \src "ls180.v:3785.11-3785.42" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3682.8-3689.11" + attribute \src "ls180.v:3787.8-3794.11" switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3682.12-3682.64" + attribute \src "ls180.v:3787.12-3787.64" case 1'1 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3686.12-3686.16" + attribute \src "ls180.v:3791.12-3791.16" case assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3691.8-3693.11" - switch $and$ls180.v:3691$219_Y - attribute \src "ls180.v:3691.12-3691.88" + attribute \src "ls180.v:3796.8-3798.11" + switch $and$ls180.v:3796$316_Y + attribute \src "ls180.v:3796.12-3796.88" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3694.11-3694.15" + attribute \src "ls180.v:3799.11-3799.15" case assign $0\builder_bankmachine2_next_state[2:0] 3'001 end - attribute \src "ls180.v:3697.10-3697.14" + attribute \src "ls180.v:3802.10-3802.14" case assign $0\builder_bankmachine2_next_state[2:0] 3'011 end @@ -271220,99 +289689,51 @@ module \ls180 update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:363.11-363.36" - process $proc$ls180.v:363$2994 + attribute \src "ls180.v:374.12-374.45" + process $proc$ls180.v:374$3204 assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 - sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] - end - attribute \src "ls180.v:364.5-364.25" - process $proc$ls180.v:364$2995 - assign { } { } - assign $1\main_sdram_re[0:0] 1'0 - sync always - sync init - update \main_sdram_re $1\main_sdram_re[0:0] - end - attribute \src "ls180.v:365.11-365.44" - process $proc$ls180.v:365$2996 - assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] - end - attribute \src "ls180.v:366.5-366.33" - process $proc$ls180.v:366$2997 - assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 - sync always - sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] - end - attribute \src "ls180.v:370.5-370.38" - process $proc$ls180.v:370$2998 - assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] end - attribute \src "ls180.v:371.12-371.46" - process $proc$ls180.v:371$2999 + attribute \src "ls180.v:375.5-375.43" + process $proc$ls180.v:375$3205 assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:3719.1-3726.4" - process $proc$ls180.v:3719$223 + attribute \src "ls180.v:3824.1-3831.4" + process $proc$ls180.v:3824$320 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3721.2-3725.5" + attribute \src "ls180.v:3826.2-3830.5" switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3721.6-3721.48" + attribute \src "ls180.v:3826.6-3826.48" case 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3723.6-3723.10" + attribute \src "ls180.v:3828.6-3828.10" case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3724$225_Y + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3829$322_Y end sync always update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:372.5-372.33" - process $proc$ls180.v:372$3000 - assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 - sync always - sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] - end - attribute \src "ls180.v:373.11-373.45" - process $proc$ls180.v:373$3001 - assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] - end - attribute \src "ls180.v:3730.1-3737.4" - process $proc$ls180.v:3730$232 + attribute \src "ls180.v:3835.1-3842.4" + process $proc$ls180.v:3835$329 assign { } { } assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3732.2-3736.5" - switch $and$ls180.v:3732$233_Y - attribute \src "ls180.v:3732.6-3732.115" + attribute \src "ls180.v:3837.2-3841.5" + switch $and$ls180.v:3837$330_Y + attribute \src "ls180.v:3837.6-3837.115" case 1'1 - attribute \src "ls180.v:3733.3-3735.6" - switch $ne$ls180.v:3733$234_Y - attribute \src "ls180.v:3733.7-3733.143" + attribute \src "ls180.v:3838.3-3840.6" + switch $ne$ls180.v:3838$331_Y + attribute \src "ls180.v:3838.7-3838.143" case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3734$235_Y + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3839$332_Y case end case @@ -271320,48 +289741,24 @@ module \ls180 sync always update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:374.5-374.34" - process $proc$ls180.v:374$3002 - assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 - sync always - sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] - end - attribute \src "ls180.v:375.12-375.45" - process $proc$ls180.v:375$3003 - assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] - end - attribute \src "ls180.v:3752.1-3759.4" - process $proc$ls180.v:3752$236 + attribute \src "ls180.v:3857.1-3864.4" + process $proc$ls180.v:3857$333 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3754.2-3758.5" + attribute \src "ls180.v:3859.2-3863.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3754.6-3754.58" + attribute \src "ls180.v:3859.6-3859.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3755$237_Y - attribute \src "ls180.v:3756.6-3756.10" + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3860$334_Y + attribute \src "ls180.v:3861.6-3861.10" case assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:376.5-376.32" - process $proc$ls180.v:376$3004 - assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 - sync always - sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] - end - attribute \src "ls180.v:3768.1-3861.4" - process $proc$ls180.v:3768$245 + attribute \src "ls180.v:3873.1-3966.4" + process $proc$ls180.v:3873$342 assign { } { } assign { } { } assign { } { } @@ -271376,37 +289773,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3784.2-3860.9" + attribute \src "ls180.v:3889.2-3965.9" switch \builder_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3786.4-3794.7" - switch $and$ls180.v:3786$246_Y - attribute \src "ls180.v:3786.8-3786.87" + attribute \src "ls180.v:3891.4-3899.7" + switch $and$ls180.v:3891$343_Y + attribute \src "ls180.v:3891.8-3891.87" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3788.5-3790.8" + attribute \src "ls180.v:3893.5-3895.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3788.9-3788.42" + attribute \src "ls180.v:3893.9-3893.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case @@ -271416,27 +289813,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3798.4-3800.7" - switch $and$ls180.v:3798$247_Y - attribute \src "ls180.v:3798.8-3798.87" + attribute \src "ls180.v:3903.4-3905.7" + switch $and$ls180.v:3903$344_Y + attribute \src "ls180.v:3903.8-3903.87" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3804.4-3813.7" + attribute \src "ls180.v:3909.4-3918.7" switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3804.8-3804.44" + attribute \src "ls180.v:3909.8-3909.44" case 1'1 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3809.5-3811.8" + attribute \src "ls180.v:3914.5-3916.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3809.9-3809.42" + attribute \src "ls180.v:3914.9-3914.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'110 case @@ -271447,16 +289844,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3816.4-3818.7" + attribute \src "ls180.v:3921.4-3923.7" switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3816.8-3816.45" + attribute \src "ls180.v:3921.8-3921.45" case 1'1 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3821.4-3823.7" - switch $not$ls180.v:3821$248_Y - attribute \src "ls180.v:3821.8-3821.46" + attribute \src "ls180.v:3926.4-3928.7" + switch $not$ls180.v:3926$345_Y + attribute \src "ls180.v:3926.8-3926.46" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'000 case @@ -271469,51 +289866,51 @@ module \ls180 assign $0\builder_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3832.4-3858.7" + attribute \src "ls180.v:3937.4-3963.7" switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3832.8-3832.43" + attribute \src "ls180.v:3937.8-3937.43" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3834.8-3834.12" + attribute \src "ls180.v:3939.8-3939.12" case - attribute \src "ls180.v:3835.5-3857.8" + attribute \src "ls180.v:3940.5-3962.8" switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3835.9-3835.56" + attribute \src "ls180.v:3940.9-3940.56" case 1'1 - attribute \src "ls180.v:3836.6-3856.9" + attribute \src "ls180.v:3941.6-3961.9" switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3836.10-3836.44" + attribute \src "ls180.v:3941.10-3941.44" case 1'1 - attribute \src "ls180.v:3837.7-3853.10" + attribute \src "ls180.v:3942.7-3958.10" switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3837.11-3837.42" + attribute \src "ls180.v:3942.11-3942.42" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3839.8-3846.11" + attribute \src "ls180.v:3944.8-3951.11" switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3839.12-3839.64" + attribute \src "ls180.v:3944.12-3944.64" case 1'1 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3843.12-3843.16" + attribute \src "ls180.v:3948.12-3948.16" case assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3848.8-3850.11" - switch $and$ls180.v:3848$249_Y - attribute \src "ls180.v:3848.12-3848.88" + attribute \src "ls180.v:3953.8-3955.11" + switch $and$ls180.v:3953$346_Y + attribute \src "ls180.v:3953.12-3953.88" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3851.11-3851.15" + attribute \src "ls180.v:3956.11-3956.15" case assign $0\builder_bankmachine3_next_state[2:0] 3'001 end - attribute \src "ls180.v:3854.10-3854.14" + attribute \src "ls180.v:3959.10-3959.14" case assign $0\builder_bankmachine3_next_state[2:0] 3'011 end @@ -271537,32 +289934,112 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:377.12-377.37" - process $proc$ls180.v:377$3005 + attribute \src "ls180.v:390.12-390.46" + process $proc$ls180.v:390$3206 assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_status $1\main_sdram_status[15:0] + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:391.5-391.44" + process $proc$ls180.v:391$3207 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:392.12-392.48" + process $proc$ls180.v:392$3208 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:393.11-393.43" + process $proc$ls180.v:393$3209 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] end - attribute \src "ls180.v:3881.1-3887.4" - process $proc$ls180.v:3881$288 + attribute \src "ls180.v:394.5-394.38" + process $proc$ls180.v:394$3210 assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:395.5-395.37" + process $proc$ls180.v:395$3211 assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3883$301_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3884$314_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3885$327_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3886$340_Y + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:396.5-396.38" + process $proc$ls180.v:396$3212 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:397.5-397.37" + process $proc$ls180.v:397$3213 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:398.5-398.36" + process $proc$ls180.v:398$3214 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:3986.1-3992.4" + process $proc$ls180.v:3986$385 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3988$398_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3989$411_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3990$424_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3991$437_Y sync always update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:3895.1-3900.4" - process $proc$ls180.v:3895$341 + attribute \src "ls180.v:399.5-399.36" + process $proc$ls180.v:399$3215 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:400.5-400.40" + process $proc$ls180.v:400$3216 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:4000.1-4005.4" + process $proc$ls180.v:4000$438 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3897.2-3899.5" + attribute \src "ls180.v:4002.2-4004.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3897.6-3897.37" + attribute \src "ls180.v:4002.6-4002.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 case @@ -271570,13 +290047,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3901.1-3906.4" - process $proc$ls180.v:3901$342 + attribute \src "ls180.v:4006.1-4011.4" + process $proc$ls180.v:4006$439 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3903.2-3905.5" + attribute \src "ls180.v:4008.2-4010.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3903.6-3903.37" + attribute \src "ls180.v:4008.6-4008.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 case @@ -271584,13 +290061,21 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3907.1-3912.4" - process $proc$ls180.v:3907$343 + attribute \src "ls180.v:401.5-401.38" + process $proc$ls180.v:401$3217 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:4012.1-4017.4" + process $proc$ls180.v:4012$440 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3909.2-3911.5" + attribute \src "ls180.v:4014.2-4016.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3909.6-3909.37" + attribute \src "ls180.v:4014.6-4014.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 case @@ -271598,24 +290083,40 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:3914.1-3920.4" - process $proc$ls180.v:3914$346 + attribute \src "ls180.v:4019.1-4025.4" + process $proc$ls180.v:4019$443 assign { } { } assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3916$359_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3917$372_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3918$385_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3919$398_Y + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:4021$456_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:4022$469_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:4023$482_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:4024$495_Y sync always update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:3928.1-3933.4" - process $proc$ls180.v:3928$399 + attribute \src "ls180.v:402.12-402.47" + process $proc$ls180.v:402$3218 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:403.5-403.42" + process $proc$ls180.v:403$3219 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:4033.1-4038.4" + process $proc$ls180.v:4033$496 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3930.2-3932.5" + attribute \src "ls180.v:4035.2-4037.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3930.6-3930.37" + attribute \src "ls180.v:4035.6-4035.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 case @@ -271623,13 +290124,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3934.1-3939.4" - process $proc$ls180.v:3934$400 + attribute \src "ls180.v:4039.1-4044.4" + process $proc$ls180.v:4039$497 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3936.2-3938.5" + attribute \src "ls180.v:4041.2-4043.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3936.6-3936.37" + attribute \src "ls180.v:4041.6-4041.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 case @@ -271637,13 +290138,21 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3940.1-3945.4" - process $proc$ls180.v:3940$401 + attribute \src "ls180.v:404.11-404.50" + process $proc$ls180.v:404$3220 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:4045.1-4050.4" + process $proc$ls180.v:4045$498 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3942.2-3944.5" + attribute \src "ls180.v:4047.2-4049.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3942.6-3942.37" + attribute \src "ls180.v:4047.6-4047.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 case @@ -271651,20 +290160,28 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:3946.1-3954.4" - process $proc$ls180.v:3946$402 + attribute \src "ls180.v:405.5-405.42" + process $proc$ls180.v:405$3221 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:4051.1-4059.4" + process $proc$ls180.v:4051$499 assign { } { } assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3948.2-3950.5" - switch $and$ls180.v:3948$405_Y - attribute \src "ls180.v:3948.6-3948.115" + attribute \src "ls180.v:4053.2-4055.5" + switch $and$ls180.v:4053$502_Y + attribute \src "ls180.v:4053.6-4053.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3951.2-3953.5" - switch $and$ls180.v:3951$408_Y - attribute \src "ls180.v:3951.6-3951.115" + attribute \src "ls180.v:4056.2-4058.5" + switch $and$ls180.v:4056$505_Y + attribute \src "ls180.v:4056.6-4056.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case @@ -271672,20 +290189,20 @@ module \ls180 sync always update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:3955.1-3963.4" - process $proc$ls180.v:3955$409 + attribute \src "ls180.v:4060.1-4068.4" + process $proc$ls180.v:4060$506 assign { } { } assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3957.2-3959.5" - switch $and$ls180.v:3957$412_Y - attribute \src "ls180.v:3957.6-3957.115" + attribute \src "ls180.v:4062.2-4064.5" + switch $and$ls180.v:4062$509_Y + attribute \src "ls180.v:4062.6-4062.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3960.2-3962.5" - switch $and$ls180.v:3960$415_Y - attribute \src "ls180.v:3960.6-3960.115" + attribute \src "ls180.v:4065.2-4067.5" + switch $and$ls180.v:4065$512_Y + attribute \src "ls180.v:4065.6-4065.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case @@ -271693,20 +290210,20 @@ module \ls180 sync always update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:3964.1-3972.4" - process $proc$ls180.v:3964$416 + attribute \src "ls180.v:4069.1-4077.4" + process $proc$ls180.v:4069$513 assign { } { } assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3966.2-3968.5" - switch $and$ls180.v:3966$419_Y - attribute \src "ls180.v:3966.6-3966.115" + attribute \src "ls180.v:4071.2-4073.5" + switch $and$ls180.v:4071$516_Y + attribute \src "ls180.v:4071.6-4071.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3969.2-3971.5" - switch $and$ls180.v:3969$422_Y - attribute \src "ls180.v:3969.6-3969.115" + attribute \src "ls180.v:4074.2-4076.5" + switch $and$ls180.v:4074$519_Y + attribute \src "ls180.v:4074.6-4074.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case @@ -271714,20 +290231,20 @@ module \ls180 sync always update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:3973.1-3981.4" - process $proc$ls180.v:3973$423 + attribute \src "ls180.v:4078.1-4086.4" + process $proc$ls180.v:4078$520 assign { } { } assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3975.2-3977.5" - switch $and$ls180.v:3975$426_Y - attribute \src "ls180.v:3975.6-3975.115" + attribute \src "ls180.v:4080.2-4082.5" + switch $and$ls180.v:4080$523_Y + attribute \src "ls180.v:4080.6-4080.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3978.2-3980.5" - switch $and$ls180.v:3978$429_Y - attribute \src "ls180.v:3978.6-3978.115" + attribute \src "ls180.v:4083.2-4085.5" + switch $and$ls180.v:4083$526_Y + attribute \src "ls180.v:4083.6-4083.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case @@ -271735,8 +290252,8 @@ module \ls180 sync always update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:3986.1-4058.4" - process $proc$ls180.v:3986$432 + attribute \src "ls180.v:4091.1-4163.4" + process $proc$ls180.v:4091$529 assign { } { } assign { } { } assign { } { } @@ -271751,42 +290268,42 @@ module \ls180 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 assign $0\main_sdram_cmd_ready[0:0] 1'0 assign { } { } - assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign { } { } + assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3998.2-4057.9" + attribute \src "ls180.v:4103.2-4162.9" switch \builder_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_en1[0:0] 1'1 assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4002.4-4008.7" + attribute \src "ls180.v:4107.4-4113.7" switch 1'1 - attribute \src "ls180.v:4002.8-4002.12" + attribute \src "ls180.v:4107.8-4107.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4003$439_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4108$536_Y case end - attribute \src "ls180.v:4010.4-4014.7" + attribute \src "ls180.v:4115.4-4119.7" switch \main_sdram_read_available - attribute \src "ls180.v:4010.8-4010.33" + attribute \src "ls180.v:4115.8-4115.33" case 1'1 - attribute \src "ls180.v:4011.5-4013.8" - switch $or$ls180.v:4011$441_Y - attribute \src "ls180.v:4011.9-4011.63" + attribute \src "ls180.v:4116.5-4118.8" + switch $or$ls180.v:4116$538_Y + attribute \src "ls180.v:4116.9-4116.63" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:4015.4-4017.7" + attribute \src "ls180.v:4120.4-4122.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4015.8-4015.32" + attribute \src "ls180.v:4120.8-4120.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -271795,18 +290312,18 @@ module \ls180 case 3'010 assign $0\main_sdram_steerer_sel[1:0] 2'11 assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:4022.4-4024.7" + attribute \src "ls180.v:4127.4-4129.7" switch \main_sdram_cmd_last - attribute \src "ls180.v:4022.8-4022.27" + attribute \src "ls180.v:4127.8-4127.27" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:4027.4-4029.7" + attribute \src "ls180.v:4132.4-4134.7" switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:4027.8-4027.32" + attribute \src "ls180.v:4132.8-4132.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case @@ -271822,29 +290339,29 @@ module \ls180 assign $0\main_sdram_en0[0:0] 1'1 assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4040.4-4046.7" + attribute \src "ls180.v:4145.4-4151.7" switch 1'1 - attribute \src "ls180.v:4040.8-4040.12" + attribute \src "ls180.v:4145.8-4145.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4041$448_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4146$545_Y case end - attribute \src "ls180.v:4048.4-4052.7" + attribute \src "ls180.v:4153.4-4157.7" switch \main_sdram_write_available - attribute \src "ls180.v:4048.8-4048.34" + attribute \src "ls180.v:4153.8-4153.34" case 1'1 - attribute \src "ls180.v:4049.5-4051.8" - switch $or$ls180.v:4049$450_Y - attribute \src "ls180.v:4049.9-4049.62" + attribute \src "ls180.v:4154.5-4156.8" + switch $or$ls180.v:4154$547_Y + attribute \src "ls180.v:4154.9-4154.62" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'100 case end case end - attribute \src "ls180.v:4053.4-4055.7" + attribute \src "ls180.v:4158.4-4160.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4053.8-4053.32" + attribute \src "ls180.v:4158.8-4158.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -271861,29 +290378,45 @@ module \ls180 update \main_sdram_en1 $0\main_sdram_en1[0:0] update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:407.12-407.46" - process $proc$ls180.v:407$3006 + attribute \src "ls180.v:412.11-412.36" + process $proc$ls180.v:412$3222 assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $1\main_sdram_storage[3:0] 4'0001 sync always sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + update \main_sdram_storage $1\main_sdram_storage[3:0] end - attribute \src "ls180.v:408.11-408.47" - process $proc$ls180.v:408$3007 + attribute \src "ls180.v:413.5-413.25" + process $proc$ls180.v:413$3223 assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + assign $1\main_sdram_re[0:0] 1'0 sync always sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + update \main_sdram_re $1\main_sdram_re[0:0] end - attribute \src "ls180.v:4082.1-4095.4" - process $proc$ls180.v:4082$579 + attribute \src "ls180.v:414.11-414.44" + process $proc$ls180.v:414$3224 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:415.5-415.33" + process $proc$ls180.v:415$3225 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:4187.1-4200.4" + process $proc$ls180.v:4187$676 assign { } { } assign { } { } - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:4085.2-4094.9" + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + attribute \src "ls180.v:4190.2-4199.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -271898,19 +290431,27 @@ module \ls180 update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:410.12-410.45" - process $proc$ls180.v:410$3008 + attribute \src "ls180.v:419.5-419.38" + process $proc$ls180.v:419$3226 assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_command_issue_w[0:0] 1'0 sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end - attribute \src "ls180.v:4102.1-4112.4" - process $proc$ls180.v:4102$581 + attribute \src "ls180.v:420.12-420.46" + process $proc$ls180.v:420$3227 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:4207.1-4217.4" + process $proc$ls180.v:4207$678 assign { } { } assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4104.2-4111.9" + attribute \src "ls180.v:4209.2-4216.9" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -271923,16 +290464,16 @@ module \ls180 sync always update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:411.11-411.40" - process $proc$ls180.v:411$3009 + attribute \src "ls180.v:421.5-421.33" + process $proc$ls180.v:421$3228 assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $1\main_sdram_address_re[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_address_re $1\main_sdram_address_re[0:0] end - attribute \src "ls180.v:4114.1-4160.4" - process $proc$ls180.v:4114$582 + attribute \src "ls180.v:4219.1-4265.4" + process $proc$ls180.v:4219$679 assign { } { } assign { } { } assign { } { } @@ -271943,23 +290484,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_litedram_wb_cyc[0:0] 1'0 assign { } { } + assign $0\main_litedram_wb_stb[0:0] 1'0 assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 - assign $0\main_litedram_wb_sel[1:0] 2'00 - assign $0\main_litedram_wb_cyc[0:0] 1'0 - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 assign $0\main_litedram_wb_we[0:0] 1'0 assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4126.2-4159.9" + attribute \src "ls180.v:4231.2-4264.9" switch \builder_converter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4129.4-4136.11" + attribute \src "ls180.v:4234.4-4241.11" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -271969,23 +290510,23 @@ module \ls180 assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] case end - attribute \src "ls180.v:4137.4-4150.7" - switch $and$ls180.v:4137$583_Y - attribute \src "ls180.v:4137.8-4137.47" + attribute \src "ls180.v:4242.4-4255.7" + switch $and$ls180.v:4242$680_Y + attribute \src "ls180.v:4242.8-4242.47" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4138$584_Y + assign $0\main_converter_skip[0:0] $eq$ls180.v:4243$681_Y assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4140$585_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4141$586_Y - attribute \src "ls180.v:4142.5-4149.8" - switch $or$ls180.v:4142$587_Y - attribute \src "ls180.v:4142.9-4142.53" + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4245$682_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4246$683_Y + attribute \src "ls180.v:4247.5-4254.8" + switch $or$ls180.v:4247$684_Y + attribute \src "ls180.v:4247.9-4247.53" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4143$588_Y + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4248$685_Y assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4145.6-4148.9" - switch $eq$ls180.v:4145$589_Y - attribute \src "ls180.v:4145.10-4145.42" + attribute \src "ls180.v:4250.6-4253.9" + switch $eq$ls180.v:4250$686_Y + attribute \src "ls180.v:4250.10-4250.42" case 1'1 assign $0\main_wb_sdram_ack[0:0] 1'1 assign $0\builder_converter_next_state[0:0] 1'0 @@ -271999,9 +290540,9 @@ module \ls180 case assign $0\main_converter_counter_converter_next_value[0:0] 1'0 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4155.4-4157.7" - switch $and$ls180.v:4155$590_Y - attribute \src "ls180.v:4155.8-4155.47" + attribute \src "ls180.v:4260.4-4262.7" + switch $and$ls180.v:4260$687_Y + attribute \src "ls180.v:4260.8-4260.47" case 1'1 assign $0\builder_converter_next_state[0:0] 1'1 case @@ -272019,53 +290560,53 @@ module \ls180 update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:412.5-412.35" - process $proc$ls180.v:412$3010 + attribute \src "ls180.v:422.11-422.45" + process $proc$ls180.v:422$3229 assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $1\main_sdram_baddress_storage[1:0] 2'00 sync always sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] end - attribute \src "ls180.v:413.5-413.34" - process $proc$ls180.v:413$3011 + attribute \src "ls180.v:423.5-423.34" + process $proc$ls180.v:423$3230 assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $1\main_sdram_baddress_re[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] end - attribute \src "ls180.v:414.5-414.35" - process $proc$ls180.v:414$3012 + attribute \src "ls180.v:424.12-424.45" + process $proc$ls180.v:424$3231 assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] end - attribute \src "ls180.v:415.5-415.34" - process $proc$ls180.v:415$3013 + attribute \src "ls180.v:425.5-425.32" + process $proc$ls180.v:425$3232 assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $1\main_sdram_wrdata_re[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] end - attribute \src "ls180.v:419.5-419.35" - process $proc$ls180.v:419$3014 + attribute \src "ls180.v:426.12-426.37" + process $proc$ls180.v:426$3233 assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + assign $1\main_sdram_status[15:0] 16'0000000000000000 sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init + update \main_sdram_status $1\main_sdram_status[15:0] end - attribute \src "ls180.v:4205.1-4210.4" - process $proc$ls180.v:4205$622 + attribute \src "ls180.v:4310.1-4315.4" + process $proc$ls180.v:4310$719 assign { } { } assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4207.2-4209.5" - switch $and$ls180.v:4207$623_Y - attribute \src "ls180.v:4207.6-4207.79" + attribute \src "ls180.v:4312.2-4314.5" + switch $and$ls180.v:4312$720_Y + attribute \src "ls180.v:4312.6-4312.79" case 1'1 assign $0\main_uart_tx_clear[0:0] 1'1 case @@ -272073,16 +290614,8 @@ module \ls180 sync always update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:421.5-421.39" - process $proc$ls180.v:421$3015 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:4211.1-4215.4" - process $proc$ls180.v:4211$624 + attribute \src "ls180.v:4316.1-4320.4" + process $proc$ls180.v:4316$721 assign { } { } assign { } { } assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status @@ -272090,13 +290623,13 @@ module \ls180 sync always update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:4216.1-4221.4" - process $proc$ls180.v:4216$625 + attribute \src "ls180.v:4321.1-4326.4" + process $proc$ls180.v:4321$722 assign { } { } assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4218.2-4220.5" - switch $and$ls180.v:4218$626_Y - attribute \src "ls180.v:4218.6-4218.79" + attribute \src "ls180.v:4323.2-4325.5" + switch $and$ls180.v:4323$723_Y + attribute \src "ls180.v:4323.6-4323.79" case 1'1 assign $0\main_uart_rx_clear[0:0] 1'1 case @@ -272104,8 +290637,8 @@ module \ls180 sync always update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:4222.1-4226.4" - process $proc$ls180.v:4222$627 + attribute \src "ls180.v:4327.1-4331.4" + process $proc$ls180.v:4327$724 assign { } { } assign { } { } assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending @@ -272113,88 +290646,58 @@ module \ls180 sync always update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:423.5-423.39" - process $proc$ls180.v:423$3016 - assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:4244.1-4251.4" - process $proc$ls180.v:4244$635 + attribute \src "ls180.v:4349.1-4356.4" + process $proc$ls180.v:4349$732 assign { } { } assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4246.2-4250.5" + attribute \src "ls180.v:4351.2-4355.5" switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4246.6-4246.31" + attribute \src "ls180.v:4351.6-4351.31" case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4247$636_Y - attribute \src "ls180.v:4248.6-4248.10" + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4352$733_Y + attribute \src "ls180.v:4353.6-4353.10" case assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce end sync always update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:426.5-426.32" - process $proc$ls180.v:426$3017 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:427.5-427.32" - process $proc$ls180.v:427$3018 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:4274.1-4281.4" - process $proc$ls180.v:4274$646 + attribute \src "ls180.v:4379.1-4386.4" + process $proc$ls180.v:4379$743 assign { } { } assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4276.2-4280.5" + attribute \src "ls180.v:4381.2-4385.5" switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4276.6-4276.31" + attribute \src "ls180.v:4381.6-4381.31" case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4277$647_Y - attribute \src "ls180.v:4278.6-4278.10" + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4382$744_Y + attribute \src "ls180.v:4383.6-4383.10" case assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce end sync always update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:428.5-428.31" - process $proc$ls180.v:428$3019 + attribute \src "ls180.v:4399.1-4403.4" + process $proc$ls180.v:4399$750 assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:429.12-429.44" - process $proc$ls180.v:429$3020 assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign { } { } + assign $0\gpio_o[15:0] \main_gpiotristateasic1_pads_o sync always - sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + update \gpio_o $0\gpio_o[15:0] end - attribute \src "ls180.v:430.11-430.43" - process $proc$ls180.v:430$3021 + attribute \src "ls180.v:4404.1-4408.4" + process $proc$ls180.v:4404$751 assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + assign { } { } + assign { } { } + assign $0\gpio_oe[15:0] \main_gpiotristateasic1_pads_oe sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + update \gpio_oe $0\gpio_oe[15:0] end - attribute \src "ls180.v:4304.1-4352.4" - process $proc$ls180.v:4304$657 + attribute \src "ls180.v:4420.1-4468.4" + process $proc$ls180.v:4420$756 assign { } { } assign { } { } assign { } { } @@ -272204,25 +290707,25 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_spimaster28_mosi_latch[0:0] 1'0 assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - assign $0\main_spimaster29_miso_latch[0:0] 1'0 - assign $0\main_spimaster3_irq[0:0] 1'0 assign $0\main_spimaster25_clk_enable[0:0] 1'0 assign $0\main_spimaster26_cs_enable[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'0 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster29_miso_latch[0:0] 1'0 + assign $0\main_spimaster3_irq[0:0] 1'0 assign { } { } assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4315.2-4351.9" + attribute \src "ls180.v:4431.2-4467.9" switch \builder_spimaster0_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4319.4-4322.7" + attribute \src "ls180.v:4435.4-4438.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4319.8-4319.33" + attribute \src "ls180.v:4435.8-4435.33" case 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'10 @@ -272232,15 +290735,15 @@ module \ls180 case 2'10 assign $0\main_spimaster25_clk_enable[0:0] 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4327.4-4333.7" + attribute \src "ls180.v:4443.4-4449.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4327.8-4327.33" + attribute \src "ls180.v:4443.8-4443.33" case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4328$658_Y + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4444$757_Y assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4330.5-4332.8" - switch $eq$ls180.v:4330$660_Y - attribute \src "ls180.v:4330.9-4330.68" + attribute \src "ls180.v:4446.5-4448.8" + switch $eq$ls180.v:4446$759_Y + attribute \src "ls180.v:4446.9-4446.68" case 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'11 case @@ -272250,9 +290753,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4337.4-4341.7" + attribute \src "ls180.v:4453.4-4457.7" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4337.8-4337.33" + attribute \src "ls180.v:4453.8-4453.33" case 1'1 assign $0\main_spimaster29_miso_latch[0:0] 1'1 assign $0\main_spimaster3_irq[0:0] 1'1 @@ -272262,9 +290765,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4345.4-4349.7" + attribute \src "ls180.v:4461.4-4465.7" switch \main_spimaster0_start - attribute \src "ls180.v:4345.8-4345.29" + attribute \src "ls180.v:4461.8-4461.29" case 1'1 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster28_mosi_latch[0:0] 1'1 @@ -272283,48 +290786,8 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:431.5-431.38" - process $proc$ls180.v:431$3022 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:432.5-432.38" - process $proc$ls180.v:432$3023 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:433.5-433.37" - process $proc$ls180.v:433$3024 - assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] - end - attribute \src "ls180.v:434.5-434.42" - process $proc$ls180.v:434$3025 - assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:435.5-435.43" - process $proc$ls180.v:435$3026 - assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] - sync init - end - attribute \src "ls180.v:4363.1-4411.4" - process $proc$ls180.v:4363$665 + attribute \src "ls180.v:4479.1-4527.4" + process $proc$ls180.v:4479$764 assign { } { } assign { } { } assign { } { } @@ -272334,25 +290797,25 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_spisdcard_clk_enable[0:0] 1'0 + assign $0\main_spisdcard_cs_enable[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'0 assign $0\main_spisdcard_done0[0:0] 1'0 assign $0\main_spisdcard_miso_latch[0:0] 1'0 assign $0\main_spisdcard_irq[0:0] 1'0 - assign $0\main_spisdcard_clk_enable[0:0] 1'0 assign { } { } assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\main_spisdcard_cs_enable[0:0] 1'0 assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4374.2-4410.9" + attribute \src "ls180.v:4490.2-4526.9" switch \builder_spimaster1_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4378.4-4381.7" + attribute \src "ls180.v:4494.4-4497.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4378.8-4378.31" + attribute \src "ls180.v:4494.8-4494.31" case 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'10 @@ -272362,15 +290825,15 @@ module \ls180 case 2'10 assign $0\main_spisdcard_clk_enable[0:0] 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4386.4-4392.7" + attribute \src "ls180.v:4502.4-4508.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4386.8-4386.31" + attribute \src "ls180.v:4502.8-4502.31" case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4387$666_Y + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4503$765_Y assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4389.5-4391.8" - switch $eq$ls180.v:4389$668_Y - attribute \src "ls180.v:4389.9-4389.66" + attribute \src "ls180.v:4505.5-4507.8" + switch $eq$ls180.v:4505$767_Y + attribute \src "ls180.v:4505.9-4505.66" case 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'11 case @@ -272380,9 +290843,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4396.4-4400.7" + attribute \src "ls180.v:4512.4-4516.7" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4396.8-4396.31" + attribute \src "ls180.v:4512.8-4512.31" case 1'1 assign $0\main_spisdcard_miso_latch[0:0] 1'1 assign $0\main_spisdcard_irq[0:0] 1'1 @@ -272392,9 +290855,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4404.4-4408.7" + attribute \src "ls180.v:4520.4-4524.7" switch \main_spisdcard_start0 - attribute \src "ls180.v:4404.8-4404.29" + attribute \src "ls180.v:4520.8-4520.29" case 1'1 assign $0\main_spisdcard_done0[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'1 @@ -272413,35 +290876,11 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:441.11-441.44" - process $proc$ls180.v:441$3027 - assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 - sync always - sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] - end - attribute \src "ls180.v:443.5-443.38" - process $proc$ls180.v:443$3028 - assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] - end - attribute \src "ls180.v:444.5-444.38" - process $proc$ls180.v:444$3029 - assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] - end - attribute \src "ls180.v:4443.1-4471.4" - process $proc$ls180.v:4443$690 + attribute \src "ls180.v:4559.1-4587.4" + process $proc$ls180.v:4559$789 assign { } { } assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4445.2-4470.9" + attribute \src "ls180.v:4561.2-4586.9" switch \main_sdphy_clocker_storage attribute \src "ls180.v:0.0-0.0" case 9'000000100 @@ -272471,16 +290910,24 @@ module \ls180 sync always update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:445.5-445.39" - process $proc$ls180.v:445$3030 + attribute \src "ls180.v:456.12-456.46" + process $proc$ls180.v:456$3234 assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:457.11-457.47" + process $proc$ls180.v:457$3235 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:4473.1-4506.4" - process $proc$ls180.v:4473$693 + attribute \src "ls180.v:4589.1-4622.4" + process $proc$ls180.v:4589$792 assign { } { } assign { } { } assign { } { } @@ -272489,16 +290936,16 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4483.2-4505.9" + attribute \src "ls180.v:4599.2-4621.9" switch \builder_sdphy_sdphyinit_state attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -272507,15 +290954,15 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4490.4-4496.7" + attribute \src "ls180.v:4606.4-4612.7" switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4490.8-4490.38" + attribute \src "ls180.v:4606.8-4606.38" case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4491$694_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4607$793_Y assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4493.5-4495.8" - switch $eq$ls180.v:4493$695_Y - attribute \src "ls180.v:4493.9-4493.41" + attribute \src "ls180.v:4609.5-4611.8" + switch $eq$ls180.v:4609$794_Y + attribute \src "ls180.v:4609.9-4609.41" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 case @@ -272526,9 +290973,9 @@ module \ls180 case assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4501.4-4503.7" + attribute \src "ls180.v:4617.4-4619.7" switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4501.8-4501.37" + attribute \src "ls180.v:4617.8-4617.37" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 case @@ -272544,33 +290991,40 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:448.5-448.38" - process $proc$ls180.v:448$3031 + attribute \src "ls180.v:459.12-459.45" + process $proc$ls180.v:459$3236 assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 sync always sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end - attribute \src "ls180.v:449.11-449.46" - process $proc$ls180.v:449$3032 + attribute \src "ls180.v:460.11-460.40" + process $proc$ls180.v:460$3237 assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 sync always sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] end - attribute \src "ls180.v:450.5-450.38" - process $proc$ls180.v:450$3033 + attribute \src "ls180.v:461.5-461.35" + process $proc$ls180.v:461$3238 assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] end - attribute \src "ls180.v:4507.1-4583.4" - process $proc$ls180.v:4507$696 + attribute \src "ls180.v:462.5-462.34" + process $proc$ls180.v:462$3239 assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:4623.1-4699.4" + process $proc$ls180.v:4623$795 assign { } { } assign { } { } assign { } { } @@ -272579,21 +291033,22 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4517.2-4582.9" + attribute \src "ls180.v:4633.2-4698.9" switch \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4521.4-4546.11" + attribute \src "ls180.v:4637.4-4662.11" switch \main_sdphy_cmdw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -272621,22 +291076,22 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] case end - attribute \src "ls180.v:4547.4-4558.7" + attribute \src "ls180.v:4663.4-4674.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4547.8-4547.38" + attribute \src "ls180.v:4663.8-4663.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4548$697_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4664$796_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4550.5-4557.8" - switch $eq$ls180.v:4550$698_Y - attribute \src "ls180.v:4550.9-4550.40" + attribute \src "ls180.v:4666.5-4673.8" + switch $eq$ls180.v:4666$797_Y + attribute \src "ls180.v:4666.9-4666.40" case 1'1 - attribute \src "ls180.v:4551.6-4556.9" + attribute \src "ls180.v:4667.6-4672.9" switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4551.10-4551.35" + attribute \src "ls180.v:4667.10-4667.35" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4553.10-4553.14" + attribute \src "ls180.v:4669.10-4669.14" case assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -272650,15 +291105,15 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4564.4-4571.7" + attribute \src "ls180.v:4680.4-4687.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4564.8-4564.38" + attribute \src "ls180.v:4680.8-4680.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4565$699_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4681$798_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4567.5-4570.8" - switch $eq$ls180.v:4567$700_Y - attribute \src "ls180.v:4567.9-4567.40" + attribute \src "ls180.v:4683.5-4686.8" + switch $eq$ls180.v:4683$799_Y + attribute \src "ls180.v:4683.9-4683.40" case 1'1 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -272670,12 +291125,12 @@ module \ls180 case assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4576.4-4580.7" - switch $and$ls180.v:4576$701_Y - attribute \src "ls180.v:4576.8-4576.69" + attribute \src "ls180.v:4692.4-4696.7" + switch $and$ls180.v:4692$800_Y + attribute \src "ls180.v:4692.8-4692.69" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4578.8-4578.12" + attribute \src "ls180.v:4694.8-4694.12" case assign $0\main_sdphy_cmdw_done[0:0] 1'1 end @@ -272690,48 +291145,48 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:456.5-456.51" - process $proc$ls180.v:456$3034 + attribute \src "ls180.v:463.5-463.35" + process $proc$ls180.v:463$3240 assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] end - attribute \src "ls180.v:457.5-457.51" - process $proc$ls180.v:457$3035 + attribute \src "ls180.v:464.5-464.34" + process $proc$ls180.v:464$3241 assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:459.5-459.47" - process $proc$ls180.v:459$3036 + attribute \src "ls180.v:468.5-468.35" + process $proc$ls180.v:468$3242 assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] end - attribute \src "ls180.v:460.5-460.45" - process $proc$ls180.v:460$3037 + attribute \src "ls180.v:470.5-470.39" + process $proc$ls180.v:470$3243 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "ls180.v:461.5-461.45" - process $proc$ls180.v:461$3038 + attribute \src "ls180.v:472.5-472.39" + process $proc$ls180.v:472$3244 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:4617.1-4710.4" - process $proc$ls180.v:4617$710 + attribute \src "ls180.v:4733.1-4826.4" + process $proc$ls180.v:4733$809 assign { } { } assign { } { } assign { } { } @@ -272748,42 +291203,42 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 assign { } { } assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4635.2-4709.9" + attribute \src "ls180.v:4751.2-4825.9" switch \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4643$711_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4759$810_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4640.4-4642.7" + attribute \src "ls180.v:4756.4-4758.7" switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4640.8-4640.49" + attribute \src "ls180.v:4756.8-4756.49" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4645.4-4648.7" - switch $eq$ls180.v:4645$712_Y - attribute \src "ls180.v:4645.8-4645.41" + attribute \src "ls180.v:4761.4-4764.7" + switch $eq$ls180.v:4761$811_Y + attribute \src "ls180.v:4761.8-4761.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -272794,30 +291249,30 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4654$714_Y + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4770$813_Y assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4671$717_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4787$816_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4656.4-4670.7" - switch $and$ls180.v:4656$715_Y - attribute \src "ls180.v:4656.8-4656.69" + attribute \src "ls180.v:4772.4-4786.7" + switch $and$ls180.v:4772$814_Y + attribute \src "ls180.v:4772.8-4772.69" case 1'1 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4658$716_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4774$815_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4660.5-4669.8" + attribute \src "ls180.v:4776.5-4785.8" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4660.9-4660.36" + attribute \src "ls180.v:4776.9-4776.36" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4662.6-4668.9" + attribute \src "ls180.v:4778.6-4784.9" switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4662.10-4662.35" + attribute \src "ls180.v:4778.10-4778.35" case 1'1 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4666.10-4666.14" + attribute \src "ls180.v:4782.10-4782.14" case assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 end @@ -272825,9 +291280,9 @@ module \ls180 end case end - attribute \src "ls180.v:4673.4-4676.7" - switch $eq$ls180.v:4673$718_Y - attribute \src "ls180.v:4673.8-4673.41" + attribute \src "ls180.v:4789.4-4792.7" + switch $eq$ls180.v:4789$817_Y + attribute \src "ls180.v:4789.8-4789.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -272838,15 +291293,15 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4682.4-4688.7" + attribute \src "ls180.v:4798.4-4804.7" switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4682.8-4682.38" + attribute \src "ls180.v:4798.8-4798.38" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4683$719_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4799$818_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4685.5-4687.8" - switch $eq$ls180.v:4685$720_Y - attribute \src "ls180.v:4685.9-4685.40" + attribute \src "ls180.v:4801.5-4803.8" + switch $eq$ls180.v:4801$819_Y + attribute \src "ls180.v:4801.9-4801.40" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -272858,9 +291313,9 @@ module \ls180 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4694.4-4696.7" - switch $and$ls180.v:4694$721_Y - attribute \src "ls180.v:4694.8-4694.69" + attribute \src "ls180.v:4810.4-4812.7" + switch $and$ls180.v:4810$820_Y + attribute \src "ls180.v:4810.8-4810.69" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -272871,9 +291326,9 @@ module \ls180 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4703.4-4707.7" - switch $and$ls180.v:4703$723_Y - attribute \src "ls180.v:4703.8-4703.94" + attribute \src "ls180.v:4819.4-4823.7" + switch $and$ls180.v:4819$822_Y + attribute \src "ls180.v:4819.8-4819.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 @@ -272899,122 +291354,122 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:462.12-462.57" - process $proc$ls180.v:462$3039 + attribute \src "ls180.v:475.5-475.32" + process $proc$ls180.v:475$3245 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end - attribute \src "ls180.v:464.5-464.51" - process $proc$ls180.v:464$3040 + attribute \src "ls180.v:476.5-476.32" + process $proc$ls180.v:476$3246 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] end - attribute \src "ls180.v:465.5-465.51" - process $proc$ls180.v:465$3041 + attribute \src "ls180.v:477.5-477.31" + process $proc$ls180.v:477$3247 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_cmd_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end - attribute \src "ls180.v:466.5-466.50" - process $proc$ls180.v:466$3042 + attribute \src "ls180.v:478.12-478.44" + process $proc$ls180.v:478$3248 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:467.5-467.54" - process $proc$ls180.v:467$3043 + attribute \src "ls180.v:479.11-479.43" + process $proc$ls180.v:479$3249 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end - attribute \src "ls180.v:468.5-468.55" - process $proc$ls180.v:468$3044 + attribute \src "ls180.v:480.5-480.38" + process $proc$ls180.v:480$3250 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:469.5-469.56" - process $proc$ls180.v:469$3045 + attribute \src "ls180.v:481.5-481.38" + process $proc$ls180.v:481$3251 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] end - attribute \src "ls180.v:470.5-470.50" - process $proc$ls180.v:470$3046 + attribute \src "ls180.v:482.5-482.37" + process $proc$ls180.v:482$3252 assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] end - attribute \src "ls180.v:473.5-473.67" - process $proc$ls180.v:473$3047 + attribute \src "ls180.v:483.5-483.42" + process $proc$ls180.v:483$3253 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] sync init end - attribute \src "ls180.v:474.5-474.66" - process $proc$ls180.v:474$3048 + attribute \src "ls180.v:484.5-484.43" + process $proc$ls180.v:484$3254 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init end - attribute \src "ls180.v:4744.1-4771.4" - process $proc$ls180.v:4744$731 - assign { } { } + attribute \src "ls180.v:4860.1-4887.4" + process $proc$ls180.v:4860$830 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign { } { } assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4752.2-4770.9" + attribute \src "ls180.v:4868.2-4886.9" switch \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4757.4-4761.7" + attribute \src "ls180.v:4873.4-4877.7" switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4757.8-4757.50" + attribute \src "ls180.v:4873.8-4873.50" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4758$732_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4759$733_Y + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4874$831_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4875$832_Y assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 case end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4764.4-4768.7" + attribute \src "ls180.v:4880.4-4884.7" switch \main_sdphy_dataw_start - attribute \src "ls180.v:4764.8-4764.30" + attribute \src "ls180.v:4880.8-4880.30" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 @@ -273030,8 +291485,8 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:4772.1-4844.4" - process $proc$ls180.v:4772$734 + attribute \src "ls180.v:4888.1-4960.4" + process $proc$ls180.v:4888$833 assign { } { } assign { } { } assign { } { } @@ -273041,36 +291496,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign { } { } + assign $0\main_sdphy_dataw_start[0:0] 1'0 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4783.2-4843.9" + attribute \src "ls180.v:4899.2-4959.9" switch \builder_sdphy_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4788.4-4790.7" + attribute \src "ls180.v:4904.4-4906.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4788.8-4788.39" + attribute \src "ls180.v:4904.8-4904.39" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4793$735_Y + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4909$834_Y assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4796.4-4803.11" + attribute \src "ls180.v:4912.4-4919.11" switch \main_sdphy_dataw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -273080,24 +291535,24 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] case end - attribute \src "ls180.v:4804.4-4816.7" + attribute \src "ls180.v:4920.4-4932.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4804.8-4804.39" + attribute \src "ls180.v:4920.8-4920.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4805$736_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4921$835_Y assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4807.5-4815.8" - switch $eq$ls180.v:4807$737_Y - attribute \src "ls180.v:4807.9-4807.41" + attribute \src "ls180.v:4923.5-4931.8" + switch $eq$ls180.v:4923$836_Y + attribute \src "ls180.v:4923.9-4923.41" case 1'1 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4810.6-4814.9" + attribute \src "ls180.v:4926.6-4930.9" switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4810.10-4810.36" + attribute \src "ls180.v:4926.10-4926.36" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4812.10-4812.14" + attribute \src "ls180.v:4928.10-4928.14" case assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 end @@ -273110,9 +291565,9 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4822.4-4825.7" + attribute \src "ls180.v:4938.4-4941.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4822.8-4822.39" + attribute \src "ls180.v:4938.8-4938.39" case 1'1 assign $0\main_sdphy_dataw_start[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 @@ -273121,13 +291576,13 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4829.4-4834.7" + attribute \src "ls180.v:4945.4-4950.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4829.8-4829.39" + attribute \src "ls180.v:4945.8-4945.39" case 1'1 - attribute \src "ls180.v:4830.5-4833.8" + attribute \src "ls180.v:4946.5-4949.8" switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4830.9-4830.51" + attribute \src "ls180.v:4946.9-4946.51" case 1'1 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 @@ -273139,9 +291594,9 @@ module \ls180 case assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4839.4-4841.7" - switch $and$ls180.v:4839$738_Y - attribute \src "ls180.v:4839.8-4839.71" + attribute \src "ls180.v:4955.4-4957.7" + switch $and$ls180.v:4955$837_Y + attribute \src "ls180.v:4955.8-4955.71" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 case @@ -273158,9 +291613,64 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:4878.1-4979.4" - process $proc$ls180.v:4878$746 + attribute \src "ls180.v:490.11-490.44" + process $proc$ls180.v:490$3255 assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:492.5-492.38" + process $proc$ls180.v:492$3256 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:493.5-493.38" + process $proc$ls180.v:493$3257 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:494.5-494.39" + process $proc$ls180.v:494$3258 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:497.5-497.38" + process $proc$ls180.v:497$3259 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "ls180.v:498.11-498.46" + process $proc$ls180.v:498$3260 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:499.5-499.38" + process $proc$ls180.v:499$3261 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:4994.1-5095.4" + process $proc$ls180.v:4994$845 assign { } { } assign { } { } assign { } { } @@ -273175,23 +291685,24 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } + assign $0\main_sdphy_datar_stop[0:0] 1'0 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 assign { } { } assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4895.2-4978.9" + attribute \src "ls180.v:5011.2-5094.9" switch \builder_sdphy_sdphydatar_state attribute \src "ls180.v:0.0-0.0" case 3'001 @@ -273200,18 +291711,18 @@ module \ls180 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 assign { } { } assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4905$748_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5021$847_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4902.4-4904.7" + attribute \src "ls180.v:5018.4-5020.7" switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:4902.8-4902.51" + attribute \src "ls180.v:5018.8-5018.51" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4907.4-4910.7" - switch $eq$ls180.v:4907$749_Y - attribute \src "ls180.v:4907.8-4907.42" + attribute \src "ls180.v:5023.4-5026.7" + switch $eq$ls180.v:5023$848_Y + attribute \src "ls180.v:5023.8-5023.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -273222,48 +291733,48 @@ module \ls180 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4916$752_Y + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:5032$851_Y assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4937$754_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5053$853_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4918.4-4936.7" + attribute \src "ls180.v:5034.4-5052.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:4918.8-4918.37" + attribute \src "ls180.v:5034.8-5034.37" case 1'1 - attribute \src "ls180.v:4919.5-4935.8" + attribute \src "ls180.v:5035.5-5051.8" switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:4919.9-4919.38" + attribute \src "ls180.v:5035.9-5035.38" case 1'1 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4921$753_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5037$852_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4923.6-4932.9" + attribute \src "ls180.v:5039.6-5048.9" switch \main_sdphy_datar_source_last - attribute \src "ls180.v:4923.10-4923.38" + attribute \src "ls180.v:5039.10-5039.38" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4925.7-4931.10" + attribute \src "ls180.v:5041.7-5047.10" switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:4925.11-4925.37" + attribute \src "ls180.v:5041.11-5041.37" case 1'1 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4929.11-4929.15" + attribute \src "ls180.v:5045.11-5045.15" case assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 end case end - attribute \src "ls180.v:4933.9-4933.13" + attribute \src "ls180.v:5049.9-5049.13" case assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:4939.4-4942.7" - switch $eq$ls180.v:4939$755_Y - attribute \src "ls180.v:4939.8-4939.42" + attribute \src "ls180.v:5055.4-5058.7" + switch $eq$ls180.v:5055$854_Y + attribute \src "ls180.v:5055.8-5055.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -273272,15 +291783,15 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4946.4-4952.7" + attribute \src "ls180.v:5062.4-5068.7" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4946.8-4946.39" + attribute \src "ls180.v:5062.8-5062.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4947$756_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5063$855_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4949.5-4951.8" - switch $eq$ls180.v:4949$757_Y - attribute \src "ls180.v:4949.9-4949.42" + attribute \src "ls180.v:5065.5-5067.8" + switch $eq$ls180.v:5065$856_Y + attribute \src "ls180.v:5065.9-5065.42" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -273292,9 +291803,9 @@ module \ls180 assign $0\main_sdphy_datar_source_valid[0:0] 1'1 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4958.4-4960.7" - switch $and$ls180.v:4958$758_Y - attribute \src "ls180.v:4958.8-4958.71" + attribute \src "ls180.v:5074.4-5076.7" + switch $and$ls180.v:5074$857_Y + attribute \src "ls180.v:5074.8-5074.71" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -273303,14 +291814,14 @@ module \ls180 case assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4965.4-4976.7" - switch $and$ls180.v:4965$759_Y - attribute \src "ls180.v:4965.8-4965.71" + attribute \src "ls180.v:5081.4-5092.7" + switch $and$ls180.v:5081$858_Y + attribute \src "ls180.v:5081.8-5081.71" case 1'1 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4967.5-4975.8" + attribute \src "ls180.v:5083.5-5091.8" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4967.9-4967.40" + attribute \src "ls180.v:5083.9-5083.40" case 1'1 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 @@ -273341,128 +291852,192 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:489.11-489.68" - process $proc$ls180.v:489$3049 + attribute \src "ls180.v:505.5-505.51" + process $proc$ls180.v:505$3262 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] end - attribute \src "ls180.v:490.5-490.64" - process $proc$ls180.v:490$3050 + attribute \src "ls180.v:506.5-506.51" + process $proc$ls180.v:506$3263 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "ls180.v:491.11-491.70" - process $proc$ls180.v:491$3051 + attribute \src "ls180.v:508.5-508.47" + process $proc$ls180.v:508$3264 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] end - attribute \src "ls180.v:492.11-492.70" - process $proc$ls180.v:492$3052 + attribute \src "ls180.v:509.5-509.45" + process $proc$ls180.v:509$3265 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] end - attribute \src "ls180.v:493.11-493.73" - process $proc$ls180.v:493$3053 + attribute \src "ls180.v:510.5-510.45" + process $proc$ls180.v:510$3266 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:511.12-511.57" + process $proc$ls180.v:511$3267 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:513.5-513.51" + process $proc$ls180.v:513$3268 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] end - attribute \src "ls180.v:5037.1-5044.4" - process $proc$ls180.v:5037$881 + attribute \src "ls180.v:514.5-514.51" + process $proc$ls180.v:514$3269 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:515.5-515.50" + process $proc$ls180.v:515$3270 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:5153.1-5160.4" + process $proc$ls180.v:5153$980 assign { } { } assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:5039.2-5043.5" + attribute \src "ls180.v:5155.2-5159.5" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:5039.6-5039.38" + attribute \src "ls180.v:5155.6-5155.38" case 1'1 assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:5041.6-5041.10" + attribute \src "ls180.v:5157.6-5157.10" case assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 end sync always update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:5059.1-5066.4" - process $proc$ls180.v:5059$904 + attribute \src "ls180.v:516.5-516.54" + process $proc$ls180.v:516$3271 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:517.5-517.55" + process $proc$ls180.v:517$3272 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:5175.1-5182.4" + process $proc$ls180.v:5175$1003 assign { } { } assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5061.2-5065.5" + attribute \src "ls180.v:5177.2-5181.5" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:5061.6-5061.44" + attribute \src "ls180.v:5177.6-5177.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:5063.6-5063.10" + attribute \src "ls180.v:5179.6-5179.10" case assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:5069.1-5076.4" - process $proc$ls180.v:5069$915 + attribute \src "ls180.v:518.5-518.56" + process $proc$ls180.v:518$3273 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:5185.1-5192.4" + process $proc$ls180.v:5185$1014 assign { } { } assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5071.2-5075.5" + attribute \src "ls180.v:5187.2-5191.5" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:5071.6-5071.44" + attribute \src "ls180.v:5187.6-5187.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:5073.6-5073.10" + attribute \src "ls180.v:5189.6-5189.10" case assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:5079.1-5086.4" - process $proc$ls180.v:5079$926 + attribute \src "ls180.v:519.5-519.50" + process $proc$ls180.v:519$3274 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:5195.1-5202.4" + process $proc$ls180.v:5195$1025 assign { } { } assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5081.2-5085.5" + attribute \src "ls180.v:5197.2-5201.5" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5081.6-5081.44" + attribute \src "ls180.v:5197.6-5197.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5083.6-5083.10" + attribute \src "ls180.v:5199.6-5199.10" case assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:5089.1-5096.4" - process $proc$ls180.v:5089$937 + attribute \src "ls180.v:5205.1-5212.4" + process $proc$ls180.v:5205$1036 assign { } { } assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5091.2-5095.5" + attribute \src "ls180.v:5207.2-5211.5" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5091.6-5091.44" + attribute \src "ls180.v:5207.6-5207.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5093.6-5093.10" + attribute \src "ls180.v:5209.6-5209.10" case assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:5097.1-5176.4" - process $proc$ls180.v:5097$938 + attribute \src "ls180.v:5213.1-5292.4" + process $proc$ls180.v:5213$1037 assign { } { } assign { } { } assign { } { } @@ -273478,36 +292053,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign { } { } assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5114.2-5175.9" + attribute \src "ls180.v:5230.2-5291.9" switch \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5118.4-5120.7" - switch $eq$ls180.v:5118$939_Y - attribute \src "ls180.v:5118.8-5118.48" + attribute \src "ls180.v:5234.4-5236.7" + switch $eq$ls180.v:5234$1038_Y + attribute \src "ls180.v:5234.8-5234.48" case 1'1 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 case end - attribute \src "ls180.v:5121.4-5146.11" + attribute \src "ls180.v:5237.4-5262.11" switch \main_sdcore_crc16_inserter_cnt attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -273535,18 +292110,18 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } case end - attribute \src "ls180.v:5147.4-5154.7" + attribute \src "ls180.v:5263.4-5270.7" switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5147.8-5147.47" + attribute \src "ls180.v:5263.8-5263.47" case 1'1 - attribute \src "ls180.v:5148.5-5153.8" - switch $eq$ls180.v:5148$940_Y - attribute \src "ls180.v:5148.9-5148.49" + attribute \src "ls180.v:5264.5-5269.8" + switch $eq$ls180.v:5264$1039_Y + attribute \src "ls180.v:5264.9-5264.49" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5150.9-5150.13" + attribute \src "ls180.v:5266.9-5266.13" case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5151$941_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5267$1040_Y assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case @@ -273565,9 +292140,9 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5169.4-5173.7" - switch $and$ls180.v:5169$943_Y - attribute \src "ls180.v:5169.8-5169.128" + attribute \src "ls180.v:5285.4-5289.7" + switch $and$ls180.v:5285$1042_Y + attribute \src "ls180.v:5285.8-5285.128" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 @@ -273592,37 +292167,29 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:514.5-514.59" - process $proc$ls180.v:514$3054 + attribute \src "ls180.v:522.5-522.67" + process $proc$ls180.v:522$3275 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:516.5-516.59" - process $proc$ls180.v:516$3055 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:517.5-517.58" - process $proc$ls180.v:517$3056 + attribute \src "ls180.v:523.5-523.66" + process $proc$ls180.v:523$3276 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:5177.1-5182.4" - process $proc$ls180.v:5177$944 + attribute \src "ls180.v:5293.1-5298.4" + process $proc$ls180.v:5293$1043 assign { } { } assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5179.2-5181.5" - switch $and$ls180.v:5179$951_Y - attribute \src "ls180.v:5179.6-5179.301" + attribute \src "ls180.v:5295.2-5297.5" + switch $and$ls180.v:5295$1050_Y + attribute \src "ls180.v:5295.6-5295.301" case 1'1 assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 case @@ -273630,109 +292197,77 @@ module \ls180 sync always update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:518.5-518.64" - process $proc$ls180.v:518$3057 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:5185.1-5192.4" - process $proc$ls180.v:5185$953 + attribute \src "ls180.v:5301.1-5308.4" + process $proc$ls180.v:5301$1052 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5187.2-5191.5" - switch $eq$ls180.v:5187$954_Y - attribute \src "ls180.v:5187.6-5187.45" + attribute \src "ls180.v:5303.2-5307.5" + switch $eq$ls180.v:5303$1053_Y + attribute \src "ls180.v:5303.6-5303.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5189.6-5189.10" + attribute \src "ls180.v:5305.6-5305.10" case assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:519.12-519.74" - process $proc$ls180.v:519$3058 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:5195.1-5202.4" - process $proc$ls180.v:5195$956 + attribute \src "ls180.v:5311.1-5318.4" + process $proc$ls180.v:5311$1055 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5197.2-5201.5" - switch $eq$ls180.v:5197$957_Y - attribute \src "ls180.v:5197.6-5197.45" + attribute \src "ls180.v:5313.2-5317.5" + switch $eq$ls180.v:5313$1056_Y + attribute \src "ls180.v:5313.6-5313.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5199.6-5199.10" + attribute \src "ls180.v:5315.6-5315.10" case assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:520.12-520.47" - process $proc$ls180.v:520$3059 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:5205.1-5212.4" - process $proc$ls180.v:5205$959 + attribute \src "ls180.v:5321.1-5328.4" + process $proc$ls180.v:5321$1058 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5207.2-5211.5" - switch $eq$ls180.v:5207$960_Y - attribute \src "ls180.v:5207.6-5207.45" + attribute \src "ls180.v:5323.2-5327.5" + switch $eq$ls180.v:5323$1059_Y + attribute \src "ls180.v:5323.6-5323.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5209.6-5209.10" + attribute \src "ls180.v:5325.6-5325.10" case assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:521.5-521.46" - process $proc$ls180.v:521$3060 - assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] - end - attribute \src "ls180.v:5215.1-5222.4" - process $proc$ls180.v:5215$962 + attribute \src "ls180.v:5331.1-5338.4" + process $proc$ls180.v:5331$1061 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5217.2-5221.5" - switch $eq$ls180.v:5217$963_Y - attribute \src "ls180.v:5217.6-5217.45" + attribute \src "ls180.v:5333.2-5337.5" + switch $eq$ls180.v:5333$1062_Y + attribute \src "ls180.v:5333.6-5333.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5219.6-5219.10" + attribute \src "ls180.v:5335.6-5335.10" case assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:5224.1-5229.4" - process $proc$ls180.v:5224$964 + attribute \src "ls180.v:5340.1-5345.4" + process $proc$ls180.v:5340$1063 assign { } { } assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5226.2-5228.5" - switch $and$ls180.v:5226$966_Y - attribute \src "ls180.v:5226.6-5226.85" + attribute \src "ls180.v:5342.2-5344.5" + switch $and$ls180.v:5342$1065_Y + attribute \src "ls180.v:5342.6-5342.85" case 1'1 assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 case @@ -273740,121 +292275,104 @@ module \ls180 sync always update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:523.5-523.44" - process $proc$ls180.v:523$3061 - assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:5230.1-5237.4" - process $proc$ls180.v:5230$967 + attribute \src "ls180.v:5346.1-5353.4" + process $proc$ls180.v:5346$1066 assign { } { } assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5232.2-5236.5" - switch $lt$ls180.v:5232$968_Y - attribute \src "ls180.v:5232.6-5232.44" + attribute \src "ls180.v:5348.2-5352.5" + switch $lt$ls180.v:5348$1067_Y + attribute \src "ls180.v:5348.6-5348.44" case 1'1 assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5234.6-5234.10" + attribute \src "ls180.v:5350.6-5350.10" case assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:524.5-524.45" - process $proc$ls180.v:524$3062 - assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] - end - attribute \src "ls180.v:5241.1-5248.4" - process $proc$ls180.v:5241$979 + attribute \src "ls180.v:5357.1-5364.4" + process $proc$ls180.v:5357$1078 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5243.2-5247.5" + attribute \src "ls180.v:5359.2-5363.5" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5243.6-5243.43" + attribute \src "ls180.v:5359.6-5359.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5245.6-5245.10" + attribute \src "ls180.v:5361.6-5361.10" case assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end sync always update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:525.5-525.54" - process $proc$ls180.v:525$3063 - assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:5251.1-5258.4" - process $proc$ls180.v:5251$990 + attribute \src "ls180.v:5367.1-5374.4" + process $proc$ls180.v:5367$1089 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5253.2-5257.5" + attribute \src "ls180.v:5369.2-5373.5" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5253.6-5253.43" + attribute \src "ls180.v:5369.6-5369.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5255.6-5255.10" + attribute \src "ls180.v:5371.6-5371.10" case assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:5261.1-5268.4" - process $proc$ls180.v:5261$1001 + attribute \src "ls180.v:5377.1-5384.4" + process $proc$ls180.v:5377$1100 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5263.2-5267.5" + attribute \src "ls180.v:5379.2-5383.5" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5263.6-5263.43" + attribute \src "ls180.v:5379.6-5379.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5265.6-5265.10" + attribute \src "ls180.v:5381.6-5381.10" case assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:527.32-527.76" - process $proc$ls180.v:527$3064 + attribute \src "ls180.v:538.11-538.68" + process $proc$ls180.v:538$3277 assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:5271.1-5278.4" - process $proc$ls180.v:5271$1012 + attribute \src "ls180.v:5387.1-5394.4" + process $proc$ls180.v:5387$1111 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5273.2-5277.5" + attribute \src "ls180.v:5389.2-5393.5" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5273.6-5273.43" + attribute \src "ls180.v:5389.6-5389.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5275.6-5275.10" + attribute \src "ls180.v:5391.6-5391.10" case assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:5279.1-5469.4" - process $proc$ls180.v:5279$1013 + attribute \src "ls180.v:539.5-539.64" + process $proc$ls180.v:539$3278 assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:5395.1-5585.4" + process $proc$ls180.v:5395$1112 assign { } { } assign { } { } assign { } { } @@ -273893,52 +292411,53 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 assign { } { } + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign { } { } assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 assign $0\main_sdphy_datar_sink_last[0:0] 1'0 assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5320.2-5468.9" + attribute \src "ls180.v:5436.2-5584.9" switch \builder_sdcore_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5323.4-5343.11" + attribute \src "ls180.v:5439.4-5459.11" switch \main_sdcore_cmd_count attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -273958,27 +292477,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5341$1014_Y + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5457$1113_Y case end - attribute \src "ls180.v:5344.4-5356.7" - switch $and$ls180.v:5344$1015_Y - attribute \src "ls180.v:5344.8-5344.65" + attribute \src "ls180.v:5460.4-5472.7" + switch $and$ls180.v:5460$1114_Y + attribute \src "ls180.v:5460.8-5460.65" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5345$1016_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5461$1115_Y assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5347.5-5355.8" - switch $eq$ls180.v:5347$1017_Y - attribute \src "ls180.v:5347.9-5347.40" + attribute \src "ls180.v:5463.5-5471.8" + switch $eq$ls180.v:5463$1116_Y + attribute \src "ls180.v:5463.9-5463.40" case 1'1 - attribute \src "ls180.v:5348.6-5354.9" - switch $eq$ls180.v:5348$1018_Y - attribute \src "ls180.v:5348.10-5348.40" + attribute \src "ls180.v:5464.6-5470.9" + switch $eq$ls180.v:5464$1117_Y + attribute \src "ls180.v:5464.10-5464.40" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5352.10-5352.14" + attribute \src "ls180.v:5468.10-5468.14" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 end @@ -273989,52 +292508,52 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5360$1019_Y + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5476$1118_Y assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5361.4-5365.7" - switch $eq$ls180.v:5361$1020_Y - attribute \src "ls180.v:5361.8-5361.38" + attribute \src "ls180.v:5477.4-5481.7" + switch $eq$ls180.v:5477$1119_Y + attribute \src "ls180.v:5477.8-5477.38" case 1'1 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5363.8-5363.12" + attribute \src "ls180.v:5479.8-5479.12" case assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5367.4-5388.7" + attribute \src "ls180.v:5483.4-5504.7" switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5367.8-5367.36" + attribute \src "ls180.v:5483.8-5483.36" case 1'1 - attribute \src "ls180.v:5368.5-5387.8" - switch $eq$ls180.v:5368$1021_Y - attribute \src "ls180.v:5368.9-5368.56" + attribute \src "ls180.v:5484.5-5503.8" + switch $eq$ls180.v:5484$1120_Y + attribute \src "ls180.v:5484.9-5484.56" case 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5372.9-5372.13" + attribute \src "ls180.v:5488.9-5488.13" case - attribute \src "ls180.v:5373.6-5386.9" + attribute \src "ls180.v:5489.6-5502.9" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5373.10-5373.37" + attribute \src "ls180.v:5489.10-5489.37" case 1'1 - attribute \src "ls180.v:5374.7-5382.10" - switch $eq$ls180.v:5374$1022_Y - attribute \src "ls180.v:5374.11-5374.42" + attribute \src "ls180.v:5490.7-5498.10" + switch $eq$ls180.v:5490$1121_Y + attribute \src "ls180.v:5490.11-5490.42" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5376.11-5376.15" + attribute \src "ls180.v:5492.11-5492.15" case - attribute \src "ls180.v:5377.8-5381.11" - switch $eq$ls180.v:5377$1023_Y - attribute \src "ls180.v:5377.12-5377.43" + attribute \src "ls180.v:5493.8-5497.11" + switch $eq$ls180.v:5493$1122_Y + attribute \src "ls180.v:5493.12-5493.43" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5379.12-5379.16" + attribute \src "ls180.v:5495.12-5495.16" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 end end - attribute \src "ls180.v:5383.10-5383.14" + attribute \src "ls180.v:5499.10-5499.14" case assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 @@ -274050,28 +292569,28 @@ module \ls180 assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5396.4-5402.7" - switch $and$ls180.v:5396$1025_Y - attribute \src "ls180.v:5396.8-5396.98" + attribute \src "ls180.v:5512.4-5518.7" + switch $and$ls180.v:5512$1124_Y + attribute \src "ls180.v:5512.8-5512.98" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5397$1026_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5513$1125_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5399.5-5401.8" - switch $eq$ls180.v:5399$1028_Y - attribute \src "ls180.v:5399.9-5399.77" + attribute \src "ls180.v:5515.5-5517.8" + switch $eq$ls180.v:5515$1127_Y + attribute \src "ls180.v:5515.9-5515.77" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 case end case end - attribute \src "ls180.v:5404.4-5409.7" + attribute \src "ls180.v:5520.4-5525.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5404.8-5404.37" + attribute \src "ls180.v:5520.8-5520.37" case 1'1 - attribute \src "ls180.v:5405.5-5408.8" - switch $ne$ls180.v:5405$1029_Y - attribute \src "ls180.v:5405.9-5405.57" + attribute \src "ls180.v:5521.5-5524.8" + switch $ne$ls180.v:5521$1128_Y + attribute \src "ls180.v:5521.9-5521.57" case 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 @@ -274083,42 +292602,42 @@ module \ls180 case 3'100 assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5414$1031_Y - attribute \src "ls180.v:5415.4-5441.7" + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5530$1130_Y + attribute \src "ls180.v:5531.4-5557.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5415.8-5415.37" + attribute \src "ls180.v:5531.8-5531.37" case 1'1 - attribute \src "ls180.v:5416.5-5440.8" - switch $eq$ls180.v:5416$1032_Y - attribute \src "ls180.v:5416.9-5416.57" + attribute \src "ls180.v:5532.5-5556.8" + switch $eq$ls180.v:5532$1131_Y + attribute \src "ls180.v:5532.9-5532.57" case 1'1 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5422.6-5430.9" - switch $and$ls180.v:5422$1033_Y - attribute \src "ls180.v:5422.10-5422.72" + attribute \src "ls180.v:5538.6-5546.9" + switch $and$ls180.v:5538$1132_Y + attribute \src "ls180.v:5538.10-5538.72" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5423$1034_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5539$1133_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5425.7-5429.10" - switch $eq$ls180.v:5425$1036_Y - attribute \src "ls180.v:5425.11-5425.79" + attribute \src "ls180.v:5541.7-5545.10" + switch $eq$ls180.v:5541$1135_Y + attribute \src "ls180.v:5541.11-5541.79" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5427.11-5427.15" + attribute \src "ls180.v:5543.11-5543.15" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 end case end - attribute \src "ls180.v:5431.9-5431.13" + attribute \src "ls180.v:5547.9-5547.13" case - attribute \src "ls180.v:5432.6-5439.9" - switch $eq$ls180.v:5432$1037_Y - attribute \src "ls180.v:5432.10-5432.58" + attribute \src "ls180.v:5548.6-5555.9" + switch $eq$ls180.v:5548$1136_Y + attribute \src "ls180.v:5548.10-5548.58" case 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 @@ -274141,9 +292660,9 @@ module \ls180 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5452.4-5466.7" + attribute \src "ls180.v:5568.4-5582.7" switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5452.8-5452.31" + attribute \src "ls180.v:5568.8-5568.31" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 @@ -274202,161 +292721,72 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:528.11-528.55" - process $proc$ls180.v:528$3065 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:530.32-530.75" - process $proc$ls180.v:530$3066 - assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:532.32-532.76" - process $proc$ls180.v:532$3067 - assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:538.5-538.51" - process $proc$ls180.v:538$3068 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - end - attribute \src "ls180.v:539.5-539.51" - process $proc$ls180.v:539$3069 - assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - end - attribute \src "ls180.v:541.5-541.47" - process $proc$ls180.v:541$3070 - assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] - end - attribute \src "ls180.v:542.5-542.45" - process $proc$ls180.v:542$3071 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] - end - attribute \src "ls180.v:543.5-543.45" - process $proc$ls180.v:543$3072 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:544.12-544.57" - process $proc$ls180.v:544$3073 + attribute \src "ls180.v:540.11-540.70" + process $proc$ls180.v:540$3279 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:546.5-546.51" - process $proc$ls180.v:546$3074 + attribute \src "ls180.v:541.11-541.70" + process $proc$ls180.v:541$3280 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:547.5-547.51" - process $proc$ls180.v:547$3075 + attribute \src "ls180.v:542.11-542.73" + process $proc$ls180.v:542$3281 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:548.5-548.50" - process $proc$ls180.v:548$3076 + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$3126 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $1\main_libresocsim_reset_storage[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] end - attribute \src "ls180.v:549.5-549.54" - process $proc$ls180.v:549$3077 + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$3127 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_libresocsim_reset_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] end - attribute \src "ls180.v:5497.1-5504.4" - process $proc$ls180.v:5497$1038 + attribute \src "ls180.v:5613.1-5620.4" + process $proc$ls180.v:5613$1137 assign { } { } assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5499.2-5503.5" + attribute \src "ls180.v:5615.2-5619.5" switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5499.6-5499.35" + attribute \src "ls180.v:5615.6-5615.35" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5500$1039_Y - attribute \src "ls180.v:5501.6-5501.10" + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5616$1138_Y + attribute \src "ls180.v:5617.6-5617.10" case assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce end sync always update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$2895 + attribute \src "ls180.v:563.5-563.59" + process $proc$ls180.v:563$3282 assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] - end - attribute \src "ls180.v:550.5-550.55" - process $proc$ls180.v:550$3078 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:551.5-551.56" - process $proc$ls180.v:551$3079 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:552.5-552.50" - process $proc$ls180.v:552$3080 - assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:5530.1-5569.4" - process $proc$ls180.v:5530$1049 - assign { } { } + attribute \src "ls180.v:5646.1-5685.4" + process $proc$ls180.v:5646$1148 assign { } { } assign { } { } assign { } { } @@ -274364,40 +292794,41 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 assign { } { } assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5540.2-5568.9" + attribute \src "ls180.v:5656.2-5684.9" switch \builder_sdblock2memdma_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5544$1050_Y + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5660$1149_Y assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5546.4-5557.7" - switch $and$ls180.v:5546$1051_Y - attribute \src "ls180.v:5546.8-5546.103" + attribute \src "ls180.v:5662.4-5673.7" + switch $and$ls180.v:5662$1150_Y + attribute \src "ls180.v:5662.8-5662.103" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5547$1052_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5663$1151_Y assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5549.5-5556.8" - switch $eq$ls180.v:5549$1054_Y - attribute \src "ls180.v:5549.9-5549.106" + attribute \src "ls180.v:5665.5-5672.8" + switch $eq$ls180.v:5665$1153_Y + attribute \src "ls180.v:5665.9-5665.106" case 1'1 - attribute \src "ls180.v:5550.6-5555.9" + attribute \src "ls180.v:5666.6-5671.9" switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5550.10-5550.57" + attribute \src "ls180.v:5666.10-5666.57" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5553.10-5553.14" + attribute \src "ls180.v:5669.10-5669.14" case assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 end @@ -274418,32 +292849,71 @@ module \ls180 sync always update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] - update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:555.5-555.67" - process $proc$ls180.v:555$3081 + attribute \src "ls180.v:565.5-565.59" + process $proc$ls180.v:565$3283 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:556.5-556.66" - process $proc$ls180.v:556$3082 + attribute \src "ls180.v:566.5-566.58" + process $proc$ls180.v:566$3284 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:5589.1-5626.4" - process $proc$ls180.v:5589$1056 + attribute \src "ls180.v:567.5-567.64" + process $proc$ls180.v:567$3285 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:568.12-568.74" + process $proc$ls180.v:568$3286 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:569.12-569.47" + process $proc$ls180.v:569$3287 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$3128 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:570.5-570.46" + process $proc$ls180.v:570$3288 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:5705.1-5742.4" + process $proc$ls180.v:5705$1155 assign { } { } assign { } { } assign { } { } @@ -274455,29 +292925,30 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 assign { } { } - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_adr[31:0] 0 + assign { } { } assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'0000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_interface1_bus_sel[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_cyc[0:0] 1'0 assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5603.2-5625.9" + attribute \src "ls180.v:5719.2-5741.9" switch \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last - assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5608.4-5611.7" + assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5724.4-5727.7" switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5608.8-5608.41" + attribute \src "ls180.v:5724.8-5724.41" case 1'1 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 @@ -274488,13 +292959,13 @@ module \ls180 assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'1111 + assign $0\main_interface1_bus_sel[7:0] 8'11111111 assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5619.4-5623.7" - switch $and$ls180.v:5619$1057_Y - attribute \src "ls180.v:5619.8-5619.59" + attribute \src "ls180.v:5735.4-5739.7" + switch $and$ls180.v:5735$1156_Y + attribute \src "ls180.v:5735.8-5735.59" case 1'1 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 case @@ -274502,67 +292973,83 @@ module \ls180 end sync always update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] - update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] - update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$2896 + attribute \src "ls180.v:572.5-572.44" + process $proc$ls180.v:572$3289 assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 sync always sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] end - attribute \src "ls180.v:5627.1-5663.4" - process $proc$ls180.v:5627$1058 + attribute \src "ls180.v:573.5-573.45" + process $proc$ls180.v:573$3290 assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:574.5-574.54" + process $proc$ls180.v:574$3291 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:5743.1-5779.4" + process $proc$ls180.v:5743$1157 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 assign { } { } - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign { } { } + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5636.2-5662.9" + attribute \src "ls180.v:5752.2-5778.9" switch \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5639$1060_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5640$1061_Y - attribute \src "ls180.v:5641.4-5652.7" + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5755$1159_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5756$1160_Y + attribute \src "ls180.v:5757.4-5768.7" switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5641.8-5641.39" + attribute \src "ls180.v:5757.8-5757.39" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5642$1062_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5758$1161_Y assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5644.5-5651.8" + attribute \src "ls180.v:5760.5-5767.8" switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5644.9-5644.39" + attribute \src "ls180.v:5760.9-5760.39" case 1'1 - attribute \src "ls180.v:5645.6-5650.9" + attribute \src "ls180.v:5761.6-5766.9" switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5645.10-5645.43" + attribute \src "ls180.v:5761.10-5761.43" case 1'1 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5648.10-5648.14" + attribute \src "ls180.v:5764.10-5764.14" case assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end @@ -274588,20 +293075,56 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:5675.1-5691.4" - process $proc$ls180.v:5675$1068 + attribute \src "ls180.v:576.32-576.76" + process $proc$ls180.v:576$3292 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:577.11-577.55" + process $proc$ls180.v:577$3293 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:579.32-579.75" + process $proc$ls180.v:579$3294 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:5791.1-5819.4" + process $proc$ls180.v:5791$1167 assign { } { } assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5677.2-5690.9" + attribute \src "ls180.v:5793.2-5818.9" switch \main_sdmem2block_converter_mux attribute \src "ls180.v:0.0-0.0" - case 2'00 + case 3'000 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] + attribute \src "ls180.v:0.0-0.0" + case 3'100 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] attribute \src "ls180.v:0.0-0.0" - case 2'01 + case 3'101 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] attribute \src "ls180.v:0.0-0.0" - case 2'10 + case 3'110 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] attribute \src "ls180.v:0.0-0.0" case @@ -274610,48 +293133,40 @@ module \ls180 sync always update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$2897 + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$3129 assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + assign $1\main_libresocsim_scratch_re[0:0] 1'0 sync always sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:581.32-581.76" + process $proc$ls180.v:581$3295 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init end - attribute \src "ls180.v:5705.1-5712.4" - process $proc$ls180.v:5705$1069 + attribute \src "ls180.v:5833.1-5840.4" + process $proc$ls180.v:5833$1168 assign { } { } assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5707.2-5711.5" + attribute \src "ls180.v:5835.2-5839.5" switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5707.6-5707.35" + attribute \src "ls180.v:5835.6-5835.35" case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5708$1070_Y - attribute \src "ls180.v:5709.6-5709.10" + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5836$1169_Y + attribute \src "ls180.v:5837.6-5837.10" case assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce end sync always update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:571.11-571.68" - process $proc$ls180.v:571$3083 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:572.5-572.64" - process $proc$ls180.v:572$3084 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:5720.1-5756.4" - process $proc$ls180.v:5720$1076 + attribute \src "ls180.v:5848.1-5884.4" + process $proc$ls180.v:5848$1175 assign { } { } assign { } { } assign { } { } @@ -274661,17 +293176,17 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 - assign { } { } assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign { } { } assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5731.2-5755.9" + attribute \src "ls180.v:5859.2-5883.9" switch \builder_state attribute \src "ls180.v:0.0-0.0" case 2'01 @@ -274689,13 +293204,13 @@ module \ls180 case assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5747.4-5753.7" - switch $and$ls180.v:5747$1077_Y - attribute \src "ls180.v:5747.8-5747.77" + attribute \src "ls180.v:5875.4-5881.7" + switch $and$ls180.v:5875$1176_Y + attribute \src "ls180.v:5875.8-5875.77" case 1'1 assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5750$1079_Y + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5878$1178_Y assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 assign $0\builder_next_state[1:0] 2'01 case @@ -274712,66 +293227,143 @@ module \ls180 update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:573.11-573.70" - process $proc$ls180.v:573$3085 + attribute \src "ls180.v:587.5-587.51" + process $proc$ls180.v:587$3296 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] end - attribute \src "ls180.v:574.11-574.70" - process $proc$ls180.v:574$3086 + attribute \src "ls180.v:588.5-588.51" + process $proc$ls180.v:588$3297 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] end - attribute \src "ls180.v:575.11-575.73" - process $proc$ls180.v:575$3087 + attribute \src "ls180.v:590.5-590.47" + process $proc$ls180.v:590$3298 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] end - attribute \src "ls180.v:5781.1-5791.4" - process $proc$ls180.v:5781$1100 + attribute \src "ls180.v:5909.1-5924.4" + process $proc$ls180.v:5909$1199 assign { } { } assign { } { } - assign $0\builder_slave_sel[7:0] [0] $eq$ls180.v:5783$1101_Y - assign $0\builder_slave_sel[7:0] [1] $eq$ls180.v:5784$1102_Y - assign $0\builder_slave_sel[7:0] [2] $eq$ls180.v:5785$1103_Y - assign $0\builder_slave_sel[7:0] [3] $eq$ls180.v:5786$1104_Y - assign $0\builder_slave_sel[7:0] [4] $eq$ls180.v:5787$1105_Y - assign $0\builder_slave_sel[7:0] [5] $eq$ls180.v:5788$1106_Y - assign $0\builder_slave_sel[7:0] [6] $eq$ls180.v:5789$1107_Y - assign $0\builder_slave_sel[7:0] [7] $eq$ls180.v:5790$1108_Y + assign $0\builder_slave_sel[12:0] [0] $eq$ls180.v:5911$1200_Y + assign $0\builder_slave_sel[12:0] [1] $eq$ls180.v:5912$1201_Y + assign $0\builder_slave_sel[12:0] [2] $eq$ls180.v:5913$1202_Y + assign $0\builder_slave_sel[12:0] [3] $eq$ls180.v:5914$1203_Y + assign $0\builder_slave_sel[12:0] [4] $eq$ls180.v:5915$1204_Y + assign $0\builder_slave_sel[12:0] [5] $eq$ls180.v:5916$1205_Y + assign $0\builder_slave_sel[12:0] [6] $eq$ls180.v:5917$1206_Y + assign $0\builder_slave_sel[12:0] [7] $eq$ls180.v:5918$1207_Y + assign $0\builder_slave_sel[12:0] [8] $eq$ls180.v:5919$1208_Y + assign $0\builder_slave_sel[12:0] [9] $eq$ls180.v:5920$1209_Y + assign $0\builder_slave_sel[12:0] [10] $eq$ls180.v:5921$1210_Y + assign $0\builder_slave_sel[12:0] [11] $eq$ls180.v:5922$1211_Y + assign $0\builder_slave_sel[12:0] [12] $eq$ls180.v:5923$1212_Y sync always - update \builder_slave_sel $0\builder_slave_sel[7:0] + update \builder_slave_sel $0\builder_slave_sel[12:0] end - attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$2898 + attribute \src "ls180.v:591.5-591.45" + process $proc$ls180.v:591$3299 assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:592.5-592.45" + process $proc$ls180.v:592$3300 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:5858.1-5869.4" - process $proc$ls180.v:5858$1127 + attribute \src "ls180.v:593.12-593.57" + process $proc$ls180.v:593$3301 assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:595.5-595.51" + process $proc$ls180.v:595$3302 assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:596.5-596.51" + process $proc$ls180.v:596$3303 assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:597.5-597.50" + process $proc$ls180.v:597$3304 assign { } { } - assign $0\builder_error[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:598.5-598.54" + process $proc$ls180.v:598$3305 assign { } { } - assign $0\builder_shared_ack[0:0] $or$ls180.v:5862$1134_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5863$1149_Y - attribute \src "ls180.v:5864.2-5868.5" + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:599.5-599.55" + process $proc$ls180.v:599$3306 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:600.5-600.56" + process $proc$ls180.v:600$3307 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:601.5-601.50" + process $proc$ls180.v:601$3308 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:6031.1-6042.4" + process $proc$ls180.v:6031$1241 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign $0\builder_shared_ack[0:0] $or$ls180.v:6035$1253_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:6036$1278_Y [31:0] + attribute \src "ls180.v:6037.2-6041.5" switch \builder_done - attribute \src "ls180.v:5864.6-5864.18" + attribute \src "ls180.v:6037.6-6037.18" case 1'1 assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 assign $0\builder_shared_ack[0:0] 1'1 @@ -274783,327 +293375,295 @@ module \ls180 update \builder_shared_ack $0\builder_shared_ack[0:0] update \builder_error $0\builder_error[0:0] end - attribute \src "ls180.v:596.5-596.59" - process $proc$ls180.v:596$3088 + attribute \src "ls180.v:604.5-604.67" + process $proc$ls180.v:604$3309 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:605.5-605.66" + process $proc$ls180.v:605$3310 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:620.11-620.68" + process $proc$ls180.v:620$3311 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:621.5-621.64" + process $proc$ls180.v:621$3312 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:622.11-622.70" + process $proc$ls180.v:622$3313 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:623.11-623.70" + process $proc$ls180.v:623$3314 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:624.11-624.73" + process $proc$ls180.v:624$3315 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$3130 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:645.5-645.59" + process $proc$ls180.v:645$3316 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:598.5-598.59" - process $proc$ls180.v:598$3089 + attribute \src "ls180.v:647.5-647.59" + process $proc$ls180.v:647$3317 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:599.5-599.58" - process $proc$ls180.v:599$3090 + attribute \src "ls180.v:648.5-648.58" + process $proc$ls180.v:648$3318 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:600.5-600.64" - process $proc$ls180.v:600$3091 + attribute \src "ls180.v:649.5-649.64" + process $proc$ls180.v:649$3319 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:601.12-601.74" - process $proc$ls180.v:601$3092 + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$3131 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:650.12-650.74" + process $proc$ls180.v:650$3320 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:602.12-602.47" - process $proc$ls180.v:602$3093 + attribute \src "ls180.v:651.12-651.47" + process $proc$ls180.v:651$3321 assign { } { } assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end - attribute \src "ls180.v:603.5-603.46" - process $proc$ls180.v:603$3094 + attribute \src "ls180.v:652.5-652.46" + process $proc$ls180.v:652$3322 assign { } { } assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end - attribute \src "ls180.v:605.5-605.44" - process $proc$ls180.v:605$3095 + attribute \src "ls180.v:654.5-654.44" + process $proc$ls180.v:654$3323 assign { } { } assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] end - attribute \src "ls180.v:606.5-606.45" - process $proc$ls180.v:606$3096 + attribute \src "ls180.v:655.5-655.45" + process $proc$ls180.v:655$3324 assign { } { } assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:607.5-607.54" - process $proc$ls180.v:607$3097 + attribute \src "ls180.v:6556.1-6561.4" + process $proc$ls180.v:6556$2152 + assign { } { } + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6558.2-6560.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6558.6-6558.25" + case 1'1 + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + case + end + sync always + update \main_spimaster9_start $0\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:656.5-656.54" + process $proc$ls180.v:656$3325 assign { } { } assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:609.32-609.76" - process $proc$ls180.v:609$3098 + attribute \src "ls180.v:658.32-658.76" + process $proc$ls180.v:658$3326 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "ls180.v:610.11-610.55" - process $proc$ls180.v:610$3099 + attribute \src "ls180.v:659.11-659.55" + process $proc$ls180.v:659$3327 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always sync init update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] end - attribute \src "ls180.v:612.32-612.75" - process $proc$ls180.v:612$3100 + attribute \src "ls180.v:6602.1-6607.4" + process $proc$ls180.v:6602$2217 + assign { } { } + assign $0\main_spisdcard_start1[0:0] 1'0 + attribute \src "ls180.v:6604.2-6606.5" + switch \main_spisdcard_control_re + attribute \src "ls180.v:6604.6-6604.31" + case 1'1 + assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + case + end + sync always + update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:661.32-661.75" + process $proc$ls180.v:661$3328 assign { } { } assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init end - attribute \src "ls180.v:614.32-614.76" - process $proc$ls180.v:614$3101 + attribute \src "ls180.v:663.32-663.76" + process $proc$ls180.v:663$3329 assign { } { } assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init end - attribute \src "ls180.v:620.5-620.51" - process $proc$ls180.v:620$3102 + attribute \src "ls180.v:669.5-669.51" + process $proc$ls180.v:669$3330 assign { } { } assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "ls180.v:621.5-621.51" - process $proc$ls180.v:621$3103 + attribute \src "ls180.v:670.5-670.51" + process $proc$ls180.v:670$3331 assign { } { } assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:623.5-623.47" - process $proc$ls180.v:623$3104 + attribute \src "ls180.v:672.5-672.47" + process $proc$ls180.v:672$3332 assign { } { } assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:624.5-624.45" - process $proc$ls180.v:624$3105 + attribute \src "ls180.v:673.5-673.45" + process $proc$ls180.v:673$3333 assign { } { } assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:625.5-625.45" - process $proc$ls180.v:625$3106 + attribute \src "ls180.v:674.5-674.45" + process $proc$ls180.v:674$3334 assign { } { } assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:626.12-626.57" - process $proc$ls180.v:626$3107 + attribute \src "ls180.v:675.12-675.57" + process $proc$ls180.v:675$3335 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:628.5-628.51" - process $proc$ls180.v:628$3108 + attribute \src "ls180.v:677.5-677.51" + process $proc$ls180.v:677$3336 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:629.5-629.51" - process $proc$ls180.v:629$3109 + attribute \src "ls180.v:678.5-678.51" + process $proc$ls180.v:678$3337 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$2899 - assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 - sync always - sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] - end - attribute \src "ls180.v:630.5-630.50" - process $proc$ls180.v:630$3110 + attribute \src "ls180.v:679.5-679.50" + process $proc$ls180.v:679$3338 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:631.5-631.54" - process $proc$ls180.v:631$3111 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:632.5-632.55" - process $proc$ls180.v:632$3112 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:633.5-633.56" - process $proc$ls180.v:633$3113 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:634.5-634.50" - process $proc$ls180.v:634$3114 - assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:637.5-637.67" - process $proc$ls180.v:637$3115 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:638.5-638.66" - process $proc$ls180.v:638$3116 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6383.1-6388.4" - process $proc$ls180.v:6383$2023 - assign { } { } - assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6385.2-6387.5" - switch \main_spimaster12_re - attribute \src "ls180.v:6385.6-6385.25" - case 1'1 - assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] - case - end - sync always - update \main_spimaster9_start $0\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:6429.1-6434.4" - process $proc$ls180.v:6429$2088 - assign { } { } - assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6431.2-6433.5" - switch \main_spisdcard_control_re - attribute \src "ls180.v:6431.6-6431.31" - case 1'1 - assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] - case - end - sync always - update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] - end - attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$2900 - assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:653.11-653.68" - process $proc$ls180.v:653$3117 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:654.5-654.64" - process $proc$ls180.v:654$3118 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:655.11-655.70" - process $proc$ls180.v:655$3119 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:656.11-656.70" - process $proc$ls180.v:656$3120 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:657.11-657.73" - process $proc$ls180.v:657$3121 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:6618.1-6634.4" - process $proc$ls180.v:6618$2309 + attribute \src "ls180.v:6791.1-6807.4" + process $proc$ls180.v:6791$2438 assign { } { } assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6620.2-6633.9" + attribute \src "ls180.v:6793.2-6806.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275121,11 +293681,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:6635.1-6651.4" - process $proc$ls180.v:6635$2310 + attribute \src "ls180.v:680.5-680.54" + process $proc$ls180.v:680$3339 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:6808.1-6824.4" + process $proc$ls180.v:6808$2439 assign { } { } assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6637.2-6650.9" + attribute \src "ls180.v:6810.2-6823.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275143,11 +293711,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:6652.1-6668.4" - process $proc$ls180.v:6652$2311 + attribute \src "ls180.v:681.5-681.55" + process $proc$ls180.v:681$3340 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:682.5-682.56" + process $proc$ls180.v:682$3341 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:6825.1-6841.4" + process $proc$ls180.v:6825$2440 assign { } { } assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6654.2-6667.9" + attribute \src "ls180.v:6827.2-6840.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275165,11 +293749,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:6669.1-6685.4" - process $proc$ls180.v:6669$2312 + attribute \src "ls180.v:683.5-683.50" + process $proc$ls180.v:683$3342 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:6842.1-6858.4" + process $proc$ls180.v:6842$2441 assign { } { } assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6671.2-6684.9" + attribute \src "ls180.v:6844.2-6857.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275187,11 +293779,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:6686.1-6702.4" - process $proc$ls180.v:6686$2313 + attribute \src "ls180.v:6859.1-6875.4" + process $proc$ls180.v:6859$2442 assign { } { } assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6688.2-6701.9" + attribute \src "ls180.v:6861.2-6874.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275209,11 +293801,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:6703.1-6719.4" - process $proc$ls180.v:6703$2314 + attribute \src "ls180.v:686.5-686.67" + process $proc$ls180.v:686$3343 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:687.5-687.66" + process $proc$ls180.v:687$3344 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6876.1-6892.4" + process $proc$ls180.v:6876$2443 assign { } { } assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6705.2-6718.9" + attribute \src "ls180.v:6878.2-6891.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275231,11 +293839,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:6720.1-6736.4" - process $proc$ls180.v:6720$2315 + attribute \src "ls180.v:6893.1-6909.4" + process $proc$ls180.v:6893$2444 assign { } { } assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6722.2-6735.9" + attribute \src "ls180.v:6895.2-6908.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275253,11 +293861,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:6737.1-6753.4" - process $proc$ls180.v:6737$2316 + attribute \src "ls180.v:6910.1-6926.4" + process $proc$ls180.v:6910$2445 assign { } { } assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6739.2-6752.9" + attribute \src "ls180.v:6912.2-6925.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275275,11 +293883,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:6754.1-6770.4" - process $proc$ls180.v:6754$2317 + attribute \src "ls180.v:6927.1-6943.4" + process $proc$ls180.v:6927$2446 assign { } { } assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6756.2-6769.9" + attribute \src "ls180.v:6929.2-6942.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275297,11 +293905,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:6771.1-6787.4" - process $proc$ls180.v:6771$2318 + attribute \src "ls180.v:6944.1-6960.4" + process $proc$ls180.v:6944$2447 assign { } { } assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6773.2-6786.9" + attribute \src "ls180.v:6946.2-6959.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275319,19 +293927,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:678.5-678.59" - process $proc$ls180.v:678$3122 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:6788.1-6804.4" - process $proc$ls180.v:6788$2319 + attribute \src "ls180.v:6961.1-6977.4" + process $proc$ls180.v:6961$2448 assign { } { } assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6790.2-6803.9" + attribute \src "ls180.v:6963.2-6976.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275349,19 +293949,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:680.5-680.59" - process $proc$ls180.v:680$3123 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:6805.1-6821.4" - process $proc$ls180.v:6805$2320 + attribute \src "ls180.v:6978.1-6994.4" + process $proc$ls180.v:6978$2449 assign { } { } assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6807.2-6820.9" + attribute \src "ls180.v:6980.2-6993.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275379,27 +293971,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:681.5-681.58" - process $proc$ls180.v:681$3124 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:682.5-682.64" - process $proc$ls180.v:682$3125 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:6822.1-6838.4" - process $proc$ls180.v:6822$2321 + attribute \src "ls180.v:6995.1-7011.4" + process $proc$ls180.v:6995$2450 assign { } { } assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6824.2-6837.9" + attribute \src "ls180.v:6997.2-7010.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275417,19 +293993,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:683.12-683.74" - process $proc$ls180.v:683$3126 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:6839.1-6855.4" - process $proc$ls180.v:6839$2322 + attribute \src "ls180.v:7012.1-7028.4" + process $proc$ls180.v:7012$2451 assign { } { } assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6841.2-6854.9" + attribute \src "ls180.v:7014.2-7027.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275447,27 +294015,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:684.12-684.47" - process $proc$ls180.v:684$3127 - assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:685.5-685.46" - process $proc$ls180.v:685$3128 + attribute \src "ls180.v:702.11-702.68" + process $proc$ls180.v:702$3345 assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:6856.1-6872.4" - process $proc$ls180.v:6856$2323 + attribute \src "ls180.v:7029.1-7045.4" + process $proc$ls180.v:7029$2452 assign { } { } assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6858.2-6871.9" + attribute \src "ls180.v:7031.2-7044.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275485,19 +294045,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:687.5-687.44" - process $proc$ls180.v:687$3129 + attribute \src "ls180.v:703.5-703.64" + process $proc$ls180.v:703$3346 assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end - attribute \src "ls180.v:6873.1-6889.4" - process $proc$ls180.v:6873$2324 + attribute \src "ls180.v:704.11-704.70" + process $proc$ls180.v:704$3347 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:7046.1-7062.4" + process $proc$ls180.v:7046$2453 assign { } { } assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6875.2-6888.9" + attribute \src "ls180.v:7048.2-7061.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275515,27 +294083,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:688.5-688.45" - process $proc$ls180.v:688$3130 + attribute \src "ls180.v:705.11-705.70" + process $proc$ls180.v:705$3348 assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:689.5-689.54" - process $proc$ls180.v:689$3131 + attribute \src "ls180.v:706.11-706.73" + process $proc$ls180.v:706$3349 assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:6890.1-6906.4" - process $proc$ls180.v:6890$2325 + attribute \src "ls180.v:7063.1-7079.4" + process $proc$ls180.v:7063$2454 assign { } { } assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6892.2-6905.9" + attribute \src "ls180.v:7065.2-7078.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275553,11 +294121,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:6907.1-6923.4" - process $proc$ls180.v:6907$2326 + attribute \src "ls180.v:7080.1-7096.4" + process $proc$ls180.v:7080$2455 assign { } { } assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6909.2-6922.9" + attribute \src "ls180.v:7082.2-7095.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275575,27 +294143,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:691.32-691.76" - process $proc$ls180.v:691$3132 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - end - attribute \src "ls180.v:692.11-692.55" - process $proc$ls180.v:692$3133 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] - end - attribute \src "ls180.v:6924.1-6931.4" - process $proc$ls180.v:6924$2327 + attribute \src "ls180.v:7097.1-7104.4" + process $proc$ls180.v:7097$2456 assign { } { } assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6926.2-6930.9" + attribute \src "ls180.v:7099.2-7103.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -275604,11 +294156,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:6932.1-6939.4" - process $proc$ls180.v:6932$2328 + attribute \src "ls180.v:7105.1-7112.4" + process $proc$ls180.v:7105$2457 assign { } { } assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6934.2-6938.9" + attribute \src "ls180.v:7107.2-7111.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -275617,32 +294169,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:694.32-694.75" - process $proc$ls180.v:694$3134 - assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:6940.1-6947.4" - process $proc$ls180.v:6940$2329 + attribute \src "ls180.v:7113.1-7120.4" + process $proc$ls180.v:7113$2458 assign { } { } assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6942.2-6946.9" + attribute \src "ls180.v:7115.2-7119.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6944$2342_Y + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7117$2471_Y end sync always update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:6948.1-6955.4" - process $proc$ls180.v:6948$2343 + attribute \src "ls180.v:7121.1-7128.4" + process $proc$ls180.v:7121$2472 assign { } { } assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6950.2-6954.9" + attribute \src "ls180.v:7123.2-7127.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -275651,11 +294195,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:6956.1-6963.4" - process $proc$ls180.v:6956$2344 + attribute \src "ls180.v:7129.1-7136.4" + process $proc$ls180.v:7129$2473 assign { } { } assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6958.2-6962.9" + attribute \src "ls180.v:7131.2-7135.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -275664,32 +294208,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:696.32-696.76" - process $proc$ls180.v:696$3135 - assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:6964.1-6971.4" - process $proc$ls180.v:6964$2345 + attribute \src "ls180.v:7137.1-7144.4" + process $proc$ls180.v:7137$2474 assign { } { } assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6966.2-6970.9" + attribute \src "ls180.v:7139.2-7143.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6968$2358_Y + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7141$2487_Y end sync always update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:6972.1-6979.4" - process $proc$ls180.v:6972$2359 + attribute \src "ls180.v:7145.1-7152.4" + process $proc$ls180.v:7145$2488 assign { } { } assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6974.2-6978.9" + attribute \src "ls180.v:7147.2-7151.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -275698,11 +294234,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:6980.1-6987.4" - process $proc$ls180.v:6980$2360 + attribute \src "ls180.v:7153.1-7160.4" + process $proc$ls180.v:7153$2489 assign { } { } assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6982.2-6986.9" + attribute \src "ls180.v:7155.2-7159.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -275711,24 +294247,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:6988.1-6995.4" - process $proc$ls180.v:6988$2361 + attribute \src "ls180.v:7161.1-7168.4" + process $proc$ls180.v:7161$2490 assign { } { } assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6990.2-6994.9" + attribute \src "ls180.v:7163.2-7167.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6992$2374_Y + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7165$2503_Y end sync always update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:6996.1-7003.4" - process $proc$ls180.v:6996$2375 + attribute \src "ls180.v:7169.1-7176.4" + process $proc$ls180.v:7169$2504 assign { } { } assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6998.2-7002.9" + attribute \src "ls180.v:7171.2-7175.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -275737,11 +294273,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:7004.1-7011.4" - process $proc$ls180.v:7004$2376 + attribute \src "ls180.v:7177.1-7184.4" + process $proc$ls180.v:7177$2505 assign { } { } assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:7006.2-7010.9" + attribute \src "ls180.v:7179.2-7183.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -275750,42 +294286,34 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:7012.1-7019.4" - process $proc$ls180.v:7012$2377 + attribute \src "ls180.v:7185.1-7192.4" + process $proc$ls180.v:7185$2506 assign { } { } assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:7014.2-7018.9" + attribute \src "ls180.v:7187.2-7191.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7016$2390_Y + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7189$2519_Y end sync always update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:702.5-702.51" - process $proc$ls180.v:702$3136 - assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - end - attribute \src "ls180.v:7020.1-7039.4" - process $proc$ls180.v:7020$2391 + attribute \src "ls180.v:7193.1-7212.4" + process $proc$ls180.v:7193$2520 assign { } { } assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:7022.2-7038.9" + attribute \src "ls180.v:7195.2-7211.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr @@ -275796,111 +294324,71 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:703.5-703.51" - process $proc$ls180.v:703$3137 - assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - end - attribute \src "ls180.v:7040.1-7059.4" - process $proc$ls180.v:7040$2392 + attribute \src "ls180.v:7213.1-7232.4" + process $proc$ls180.v:7213$2521 assign { } { } - assign $0\builder_comb_rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:7042.2-7058.9" + assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "ls180.v:7215.2-7231.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w end sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:705.5-705.47" - process $proc$ls180.v:705$3138 - assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] - end - attribute \src "ls180.v:706.5-706.45" - process $proc$ls180.v:706$3139 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:7060.1-7079.4" - process $proc$ls180.v:7060$2393 + attribute \src "ls180.v:7233.1-7252.4" + process $proc$ls180.v:7233$2522 assign { } { } - assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:7062.2-7078.9" + assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + attribute \src "ls180.v:7235.2-7251.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel end sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] - end - attribute \src "ls180.v:707.5-707.45" - process $proc$ls180.v:707$3140 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:708.12-708.57" - process $proc$ls180.v:708$3141 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:7080.1-7099.4" - process $proc$ls180.v:7080$2394 + attribute \src "ls180.v:7253.1-7272.4" + process $proc$ls180.v:7253$2523 assign { } { } assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:7082.2-7098.9" + attribute \src "ls180.v:7255.2-7271.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc @@ -275911,29 +294399,29 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:710.5-710.51" - process $proc$ls180.v:710$3142 + attribute \src "ls180.v:727.5-727.59" + process $proc$ls180.v:727$3350 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:7100.1-7119.4" - process $proc$ls180.v:7100$2395 + attribute \src "ls180.v:7273.1-7292.4" + process $proc$ls180.v:7273$2524 assign { } { } assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7102.2-7118.9" + attribute \src "ls180.v:7275.2-7291.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb @@ -275944,37 +294432,29 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:711.5-711.51" - process $proc$ls180.v:711$3143 + attribute \src "ls180.v:729.5-729.59" + process $proc$ls180.v:729$3351 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:712.5-712.50" - process $proc$ls180.v:712$3144 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:7120.1-7139.4" - process $proc$ls180.v:7120$2396 + attribute \src "ls180.v:7293.1-7312.4" + process $proc$ls180.v:7293$2525 assign { } { } assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7122.2-7138.9" + attribute \src "ls180.v:7295.2-7311.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we @@ -275985,37 +294465,37 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:713.5-713.54" - process $proc$ls180.v:713$3145 + attribute \src "ls180.v:730.5-730.58" + process $proc$ls180.v:730$3352 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:714.5-714.55" - process $proc$ls180.v:714$3146 + attribute \src "ls180.v:731.5-731.64" + process $proc$ls180.v:731$3353 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:7140.1-7159.4" - process $proc$ls180.v:7140$2397 + attribute \src "ls180.v:7313.1-7332.4" + process $proc$ls180.v:7313$2526 assign { } { } assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7142.2-7158.9" + attribute \src "ls180.v:7315.2-7331.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti @@ -276026,37 +294506,37 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:715.5-715.56" - process $proc$ls180.v:715$3147 + attribute \src "ls180.v:732.12-732.74" + process $proc$ls180.v:732$3354 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:716.5-716.50" - process $proc$ls180.v:716$3148 + attribute \src "ls180.v:733.12-733.47" + process $proc$ls180.v:733$3355 assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] end - attribute \src "ls180.v:7160.1-7179.4" - process $proc$ls180.v:7160$2398 + attribute \src "ls180.v:7333.1-7352.4" + process $proc$ls180.v:7333$2527 assign { } { } assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7162.2-7178.9" + attribute \src "ls180.v:7335.2-7351.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte @@ -276067,11 +294547,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:7180.1-7196.4" - process $proc$ls180.v:7180$2399 + attribute \src "ls180.v:734.5-734.46" + process $proc$ls180.v:734$3356 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:7353.1-7369.4" + process $proc$ls180.v:7353$2528 assign { } { } assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7182.2-7195.9" + attribute \src "ls180.v:7355.2-7368.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -276089,19 +294577,27 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:719.5-719.67" - process $proc$ls180.v:719$3149 + attribute \src "ls180.v:736.5-736.44" + process $proc$ls180.v:736$3357 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:737.5-737.45" + process $proc$ls180.v:737$3358 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] end - attribute \src "ls180.v:7197.1-7213.4" - process $proc$ls180.v:7197$2400 + attribute \src "ls180.v:7370.1-7386.4" + process $proc$ls180.v:7370$2529 assign { } { } assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7199.2-7212.9" + attribute \src "ls180.v:7372.2-7385.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -276119,137 +294615,169 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:72.5-72.46" - process $proc$ls180.v:72$2901 + attribute \src "ls180.v:738.5-738.54" + process $proc$ls180.v:738$3359 assign { } { } - assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] - end - attribute \src "ls180.v:720.5-720.66" - process $proc$ls180.v:720$3150 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:7214.1-7230.4" - process $proc$ls180.v:7214$2401 + attribute \src "ls180.v:7387.1-7403.4" + process $proc$ls180.v:7387$2530 assign { } { } assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7216.2-7229.9" + attribute \src "ls180.v:7389.2-7402.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7221$2403_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7394$2532_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7224$2405_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7397$2534_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7227$2407_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7400$2536_Y end sync always update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:7231.1-7247.4" - process $proc$ls180.v:7231$2408 + attribute \src "ls180.v:74.11-74.52" + process $proc$ls180.v:74$3132 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] + sync init + end + attribute \src "ls180.v:740.32-740.76" + process $proc$ls180.v:740$3360 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:7404.1-7420.4" + process $proc$ls180.v:7404$2537 assign { } { } assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7233.2-7246.9" + attribute \src "ls180.v:7406.2-7419.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7238$2410_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7411$2539_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7241$2412_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7414$2541_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7244$2414_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7417$2543_Y end sync always update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:7248.1-7264.4" - process $proc$ls180.v:7248$2415 + attribute \src "ls180.v:741.11-741.55" + process $proc$ls180.v:741$3361 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:7421.1-7437.4" + process $proc$ls180.v:7421$2544 assign { } { } assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7250.2-7263.9" + attribute \src "ls180.v:7423.2-7436.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7255$2417_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7428$2546_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7258$2419_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7431$2548_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7261$2421_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7434$2550_Y end sync always update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:7265.1-7281.4" - process $proc$ls180.v:7265$2422 + attribute \src "ls180.v:743.32-743.75" + process $proc$ls180.v:743$3362 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:7438.1-7454.4" + process $proc$ls180.v:7438$2551 assign { } { } assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7267.2-7280.9" + attribute \src "ls180.v:7440.2-7453.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7272$2424_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7445$2553_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7275$2426_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7448$2555_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7278$2428_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7451$2557_Y end sync always update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:7282.1-7298.4" - process $proc$ls180.v:7282$2429 + attribute \src "ls180.v:745.32-745.76" + process $proc$ls180.v:745$3363 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:7455.1-7471.4" + process $proc$ls180.v:7455$2558 assign { } { } assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7284.2-7297.9" + attribute \src "ls180.v:7457.2-7470.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7289$2431_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7462$2560_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7292$2433_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7465$2562_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7295$2435_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7468$2564_Y end sync always update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:7299.1-7327.4" - process $proc$ls180.v:7299$2436 + attribute \src "ls180.v:7472.1-7500.4" + process $proc$ls180.v:7472$2565 assign { } { } assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7301.2-7326.9" + attribute \src "ls180.v:7474.2-7499.9" switch \main_spimaster34_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -276279,11 +294807,19 @@ module \ls180 sync always update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:7328.1-7356.4" - process $proc$ls180.v:7328$2437 + attribute \src "ls180.v:75.11-75.52" + process $proc$ls180.v:75$3133 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] + sync init + end + attribute \src "ls180.v:7501.1-7529.4" + process $proc$ls180.v:7501$2566 assign { } { } assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7330.2-7355.9" + attribute \src "ls180.v:7503.2-7528.9" switch \main_spisdcard_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -276313,86 +294849,133 @@ module \ls180 sync always update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:735.11-735.68" - process $proc$ls180.v:735$3151 + attribute \src "ls180.v:751.5-751.51" + process $proc$ls180.v:751$3364 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "ls180.v:736.5-736.64" - process $proc$ls180.v:736$3152 + attribute \src "ls180.v:752.5-752.51" + process $proc$ls180.v:752$3365 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end - attribute \src "ls180.v:737.11-737.70" - process $proc$ls180.v:737$3153 + attribute \src "ls180.v:754.5-754.47" + process $proc$ls180.v:754$3366 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] end - attribute \src "ls180.v:738.11-738.70" - process $proc$ls180.v:738$3154 + attribute \src "ls180.v:755.5-755.45" + process $proc$ls180.v:755$3367 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] end - attribute \src "ls180.v:739.11-739.73" - process $proc$ls180.v:739$3155 + attribute \src "ls180.v:756.5-756.45" + process $proc$ls180.v:756$3368 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:74.5-74.46" - process $proc$ls180.v:74$2902 + attribute \src "ls180.v:757.12-757.57" + process $proc$ls180.v:757$3369 assign { } { } - assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 sync always - update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:7414.1-7432.4" - process $proc$ls180.v:7414$2438 + attribute \src "ls180.v:7587.1-7597.4" + process $proc$ls180.v:7587$2567 assign { } { } + assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 + assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [7] \builder_multiregimpl8_regs1 + sync always + update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:759.5-759.51" + process $proc$ls180.v:759$3370 assign { } { } - assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 - assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 - assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 - assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 - assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 - assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 - assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 - assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 - assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 - assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 - assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 - assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 - assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 - assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 - assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 - assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always - update \main_gpio_status $0\main_gpio_status[15:0] + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "ls180.v:7453.1-7455.4" - process $proc$ls180.v:7453$2439 + attribute \src "ls180.v:7598.1-7608.4" + process $proc$ls180.v:7598$2568 + assign { } { } + assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 + assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] + end + attribute \src "ls180.v:760.5-760.51" + process $proc$ls180.v:760$3371 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:761.5-761.50" + process $proc$ls180.v:761$3372 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:762.5-762.54" + process $proc$ls180.v:762$3373 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:7629.1-7631.4" + process $proc$ls180.v:7629$2569 assign { } { } assign $0\main_int_rst[0:0] \sys_rst sync posedge \por_clk update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "ls180.v:7457.1-7527.4" - process $proc$ls180.v:7457$2440 + attribute \src "ls180.v:763.5-763.55" + process $proc$ls180.v:763$3374 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:7633.1-7703.4" + process $proc$ls180.v:7633$2570 assign { } { } assign { } { } assign { } { } @@ -276468,7 +295051,7 @@ module \ls180 assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7514$2442_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7690$2572_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -276482,6 +295065,11 @@ module \ls180 assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] sync posedge \sdrio_clk + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \sdram_a $0\sdram_a[12:0] update \sdram_dq_o $0\sdram_dq_o[15:0] update \sdram_dq_oe $0\sdram_dq_oe[0:0] @@ -276493,36 +295081,57 @@ module \ls180 update \sdram_ba $0\sdram_ba[1:0] update \sdram_dm $0\sdram_dm[1:0] update \sdram_clock $0\sdram_clock[0:0] - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:7529.1-10156.4" - process $proc$ls180.v:7529$2443 - assign $0\uart_tx[0:0] \uart_tx - assign $0\spisdcard_clk[0:0] \spisdcard_clk - assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + attribute \src "ls180.v:764.5-764.56" + process $proc$ls180.v:764$3375 assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:765.5-765.50" + process $proc$ls180.v:765$3376 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:768.5-768.67" + process $proc$ls180.v:768$3377 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:769.5-769.66" + process $proc$ls180.v:769$3378 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:7705.1-10349.4" + process $proc$ls180.v:7705$2573 + assign $0\uart_tx[0:0] \uart_tx assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } assign $0\pwm[1:0] \pwm assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage assign { } { } assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r assign { } { } assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage assign { } { } @@ -276542,6 +295151,11 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_converter0_counter[0:0] \main_converter0_counter + assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r + assign $0\main_converter1_counter[0:0] \main_converter1_counter + assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r + assign { } { } assign { } { } assign $0\main_sdram_storage[3:0] \main_sdram_storage assign { } { } @@ -276629,6 +295243,8 @@ module \ls180 assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count assign $0\main_sdram_time0[4:0] \main_sdram_time0 assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r assign $0\main_converter_counter[0:0] \main_converter_counter assign $0\main_converter_dat_r[31:0] \main_converter_dat_r assign $0\main_cmd_consumed[0:0] \main_cmd_consumed @@ -276663,9 +295279,9 @@ module \ls180 assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume - assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage + assign $0\main_gpiotristateasic1_oe_storage[15:0] \main_gpiotristateasic1_oe_storage assign { } { } - assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage + assign $0\main_gpiotristateasic1_out_storage[15:0] \main_gpiotristateasic1_out_storage assign { } { } assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage @@ -276808,9 +295424,9 @@ module \ls180 assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count - assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage assign { } { } @@ -276821,7 +295437,7 @@ module \ls180 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage assign { } { } assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage assign { } { } assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage @@ -276831,7 +295447,7 @@ module \ls180 assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage assign { } { } assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset - assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume @@ -276919,30 +295535,30 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7530$2444_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7531$2445_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7532$2446_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7533$2447_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7534$2448_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7535$2449_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7536$2450_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7537$2451_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7538$2452_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7539$2453_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7540$2454_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7541$2455_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7542$2456_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7543$2457_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7544$2458_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7545$2459_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7546$2460_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7547$2461_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7548$2462_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7549$2463_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7550$2464_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7551$2465_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7552$2466_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7553$2467_Y + assign $0\main_dummy[23:0] [0] $or$ls180.v:7706$2574_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7707$2575_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7708$2576_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7709$2577_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7710$2578_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7711$2579_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7712$2580_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7713$2581_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7714$2582_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7715$2583_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7716$2584_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7717$2585_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7718$2586_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7719$2587_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7720$2588_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7721$2589_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7722$2590_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7723$2591_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7724$2592_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7725$2593_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7726$2594_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7727$2595_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7728$2596_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7729$2597_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state @@ -276951,6 +295567,7 @@ module \ls180 assign $0\main_interface0_ram_bus_ack[0:0] 1'0 assign $0\main_interface1_ram_bus_ack[0:0] 1'0 assign $0\main_interface2_ram_bus_ack[0:0] 1'0 + assign $0\main_interface3_ram_bus_ack[0:0] 1'0 assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] assign $0\main_sdram_postponer_req_o[0:0] 1'0 @@ -276968,14 +295585,14 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8007$2573_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8008$2574_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8009$2575_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8187$2706_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8188$2707_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8189$2708_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8043$2593_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8044$2605_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8223$2726_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8224$2738_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 @@ -276985,11 +295602,11 @@ module \ls180 assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8202$2651_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8211$2654_Y + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8382$2784_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8391$2787_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8237$2656_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8246$2659_Y + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8417$2789_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8426$2792_Y assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 @@ -277005,13 +295622,13 @@ module \ls180 assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[7:0] \builder_slave_sel + assign $0\builder_slave_sel_r[12:0] \builder_slave_sel assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re - assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re + assign $0\main_gpiotristateasic1_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpiotristateasic1_out_re[0:0] \builder_csrbank1_out0_re assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 @@ -277068,207 +295685,214 @@ module \ls180 assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 - assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpiotristateasic0_pads_i [0] assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 - assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpiotristateasic0_pads_i [1] assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 - assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpiotristateasic0_pads_i [2] assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 - assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpiotristateasic0_pads_i [3] assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 - assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpiotristateasic0_pads_i [4] assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 - assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpiotristateasic0_pads_i [5] assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 - assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpiotristateasic0_pads_i [6] assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 - assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpiotristateasic0_pads_i [7] assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 - assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpiotristateasic1_pads_i [8] assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 - assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpiotristateasic1_pads_i [9] assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 - assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpiotristateasic1_pads_i [10] assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 - assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpiotristateasic1_pads_i [11] assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 - assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpiotristateasic1_pads_i [12] assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 - assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpiotristateasic1_pads_i [13] assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 - assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpiotristateasic1_pads_i [14] assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 - assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7554.2-7556.5" - switch $or$ls180.v:7554$2468_Y - attribute \src "ls180.v:7554.6-7554.94" + attribute \src "ls180.v:7730.2-7732.5" + switch $or$ls180.v:7730$2598_Y + attribute \src "ls180.v:7730.6-7730.69" case 1'1 - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r case end - attribute \src "ls180.v:7558.2-7560.5" - switch \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7558.6-7558.66" + attribute \src "ls180.v:7734.2-7736.5" + switch \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7734.6-7734.54" case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value case end - attribute \src "ls180.v:7561.2-7564.5" - switch \main_libresocsim_converter0_reset - attribute \src "ls180.v:7561.6-7561.39" + attribute \src "ls180.v:7737.2-7740.5" + switch \main_converter0_reset + attribute \src "ls180.v:7737.6-7737.27" case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 assign $0\builder_converter0_state[0:0] 1'0 case end - attribute \src "ls180.v:7565.2-7567.5" - switch $or$ls180.v:7565$2469_Y - attribute \src "ls180.v:7565.6-7565.94" + attribute \src "ls180.v:7741.2-7743.5" + switch $or$ls180.v:7741$2599_Y + attribute \src "ls180.v:7741.6-7741.69" case 1'1 - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r case end - attribute \src "ls180.v:7569.2-7571.5" - switch \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7569.6-7569.66" + attribute \src "ls180.v:7745.2-7747.5" + switch \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7745.6-7745.54" case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value case end - attribute \src "ls180.v:7572.2-7575.5" - switch \main_libresocsim_converter1_reset - attribute \src "ls180.v:7572.6-7572.39" + attribute \src "ls180.v:7748.2-7751.5" + switch \main_converter1_reset + attribute \src "ls180.v:7748.6-7748.27" case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 assign $0\builder_converter1_state[0:0] 1'0 case end - attribute \src "ls180.v:7576.2-7578.5" - switch $or$ls180.v:7576$2470_Y - attribute \src "ls180.v:7576.6-7576.94" + attribute \src "ls180.v:7752.2-7754.5" + switch $or$ls180.v:7752$2600_Y + attribute \src "ls180.v:7752.6-7752.51" case 1'1 - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r case end - attribute \src "ls180.v:7580.2-7582.5" - switch \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:7580.6-7580.66" + attribute \src "ls180.v:7756.2-7758.5" + switch \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:7756.6-7756.57" case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value case end - attribute \src "ls180.v:7583.2-7586.5" - switch \main_libresocsim_converter2_reset - attribute \src "ls180.v:7583.6-7583.39" + attribute \src "ls180.v:7759.2-7762.5" + switch \main_socbushandler_reset + attribute \src "ls180.v:7759.6-7759.30" case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\main_socbushandler_counter[0:0] 1'0 assign $0\builder_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7587.2-7591.5" - switch $ne$ls180.v:7587$2471_Y - attribute \src "ls180.v:7587.6-7587.53" + attribute \src "ls180.v:7763.2-7767.5" + switch $ne$ls180.v:7763$2601_Y + attribute \src "ls180.v:7763.6-7763.53" case 1'1 - attribute \src "ls180.v:7588.3-7590.6" + attribute \src "ls180.v:7764.3-7766.6" switch \main_libresocsim_bus_error - attribute \src "ls180.v:7588.7-7588.33" + attribute \src "ls180.v:7764.7-7764.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7589$2472_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7765$2602_Y case end case end - attribute \src "ls180.v:7593.2-7595.5" - switch $and$ls180.v:7593$2475_Y - attribute \src "ls180.v:7593.6-7593.103" + attribute \src "ls180.v:7769.2-7771.5" + switch $and$ls180.v:7769$2605_Y + attribute \src "ls180.v:7769.6-7769.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7596.2-7604.5" + attribute \src "ls180.v:7772.2-7780.5" switch \main_libresocsim_en_storage - attribute \src "ls180.v:7596.6-7596.33" + attribute \src "ls180.v:7772.6-7772.33" case 1'1 - attribute \src "ls180.v:7597.3-7601.6" - switch $eq$ls180.v:7597$2476_Y - attribute \src "ls180.v:7597.7-7597.39" + attribute \src "ls180.v:7773.3-7777.6" + switch $eq$ls180.v:7773$2606_Y + attribute \src "ls180.v:7773.7-7773.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7599.7-7599.11" + attribute \src "ls180.v:7775.7-7775.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7600$2477_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7776$2607_Y end - attribute \src "ls180.v:7602.6-7602.10" + attribute \src "ls180.v:7778.6-7778.10" case assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage end - attribute \src "ls180.v:7605.2-7607.5" + attribute \src "ls180.v:7781.2-7783.5" switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7605.6-7605.38" + attribute \src "ls180.v:7781.6-7781.38" case 1'1 assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value case end - attribute \src "ls180.v:7608.2-7610.5" + attribute \src "ls180.v:7784.2-7786.5" switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7608.6-7608.33" + attribute \src "ls180.v:7784.6-7784.33" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7612.2-7614.5" - switch $and$ls180.v:7612$2479_Y - attribute \src "ls180.v:7612.6-7612.76" + attribute \src "ls180.v:7788.2-7790.5" + switch $and$ls180.v:7788$2609_Y + attribute \src "ls180.v:7788.6-7788.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7616.2-7618.5" - switch $and$ls180.v:7616$2482_Y - attribute \src "ls180.v:7616.6-7616.100" + attribute \src "ls180.v:7792.2-7794.5" + switch $and$ls180.v:7792$2612_Y + attribute \src "ls180.v:7792.6-7792.100" case 1'1 assign $0\main_interface0_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7620.2-7622.5" - switch $and$ls180.v:7620$2485_Y - attribute \src "ls180.v:7620.6-7620.100" + attribute \src "ls180.v:7796.2-7798.5" + switch $and$ls180.v:7796$2615_Y + attribute \src "ls180.v:7796.6-7796.100" case 1'1 assign $0\main_interface1_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7624.2-7626.5" - switch $and$ls180.v:7624$2488_Y - attribute \src "ls180.v:7624.6-7624.100" + attribute \src "ls180.v:7800.2-7802.5" + switch $and$ls180.v:7800$2618_Y + attribute \src "ls180.v:7800.6-7800.100" case 1'1 assign $0\main_interface2_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7629.2-7631.5" + attribute \src "ls180.v:7804.2-7806.5" + switch $and$ls180.v:7804$2621_Y + attribute \src "ls180.v:7804.6-7804.100" + case 1'1 + assign $0\main_interface3_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7809.2-7811.5" switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7629.6-7629.37" + attribute \src "ls180.v:7809.6-7809.37" case 1'1 assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata case end - attribute \src "ls180.v:7632.2-7636.5" - switch $and$ls180.v:7632$2490_Y - attribute \src "ls180.v:7632.6-7632.57" + attribute \src "ls180.v:7812.2-7816.5" + switch $and$ls180.v:7812$2623_Y + attribute \src "ls180.v:7812.6-7812.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7633$2491_Y - attribute \src "ls180.v:7634.6-7634.10" + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7813$2624_Y + attribute \src "ls180.v:7814.6-7814.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7638.2-7644.5" + attribute \src "ls180.v:7818.2-7824.5" switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7638.6-7638.32" + attribute \src "ls180.v:7818.6-7818.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7639$2492_Y - attribute \src "ls180.v:7640.3-7643.6" - switch $eq$ls180.v:7640$2493_Y - attribute \src "ls180.v:7640.7-7640.43" + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7819$2625_Y + attribute \src "ls180.v:7820.3-7823.6" + switch $eq$ls180.v:7820$2626_Y + attribute \src "ls180.v:7820.7-7820.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 assign $0\main_sdram_postponer_req_o[0:0] 1'1 @@ -277276,30 +295900,30 @@ module \ls180 end case end - attribute \src "ls180.v:7645.2-7653.5" + attribute \src "ls180.v:7825.2-7833.5" switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7645.6-7645.33" + attribute \src "ls180.v:7825.6-7825.33" case 1'1 assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7647.6-7647.10" + attribute \src "ls180.v:7827.6-7827.10" case - attribute \src "ls180.v:7648.3-7652.6" + attribute \src "ls180.v:7828.3-7832.6" switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7648.7-7648.33" + attribute \src "ls180.v:7828.7-7828.33" case 1'1 - attribute \src "ls180.v:7649.4-7651.7" - switch $ne$ls180.v:7649$2494_Y - attribute \src "ls180.v:7649.8-7649.44" + attribute \src "ls180.v:7829.4-7831.7" + switch $ne$ls180.v:7829$2627_Y + attribute \src "ls180.v:7829.8-7829.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7650$2495_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7830$2628_Y case end case end end - attribute \src "ls180.v:7660.2-7666.5" - switch $and$ls180.v:7660$2497_Y - attribute \src "ls180.v:7660.6-7660.76" + attribute \src "ls180.v:7840.2-7846.5" + switch $and$ls180.v:7840$2630_Y + attribute \src "ls180.v:7840.6-7840.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -277308,9 +295932,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7667.2-7673.5" - switch $eq$ls180.v:7667$2498_Y - attribute \src "ls180.v:7667.6-7667.44" + attribute \src "ls180.v:7847.2-7853.5" + switch $eq$ls180.v:7847$2631_Y + attribute \src "ls180.v:7847.6-7847.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -277319,9 +295943,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7674.2-7681.5" - switch $eq$ls180.v:7674$2499_Y - attribute \src "ls180.v:7674.6-7674.44" + attribute \src "ls180.v:7854.2-7861.5" + switch $eq$ls180.v:7854$2632_Y + attribute \src "ls180.v:7854.6-7854.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -277331,83 +295955,83 @@ module \ls180 assign $0\main_sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7682.2-7692.5" - switch $eq$ls180.v:7682$2500_Y - attribute \src "ls180.v:7682.6-7682.44" + attribute \src "ls180.v:7862.2-7872.5" + switch $eq$ls180.v:7862$2633_Y + attribute \src "ls180.v:7862.6-7862.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7684.6-7684.10" + attribute \src "ls180.v:7864.6-7864.10" case - attribute \src "ls180.v:7685.3-7691.6" - switch $ne$ls180.v:7685$2501_Y - attribute \src "ls180.v:7685.7-7685.45" + attribute \src "ls180.v:7865.3-7871.6" + switch $ne$ls180.v:7865$2634_Y + attribute \src "ls180.v:7865.7-7865.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7686$2502_Y - attribute \src "ls180.v:7687.7-7687.11" + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7866$2635_Y + attribute \src "ls180.v:7867.7-7867.11" case - attribute \src "ls180.v:7688.4-7690.7" + attribute \src "ls180.v:7868.4-7870.7" switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7688.8-7688.35" + attribute \src "ls180.v:7868.8-7868.35" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7694.2-7701.5" + attribute \src "ls180.v:7874.2-7881.5" switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7694.6-7694.39" + attribute \src "ls180.v:7874.6-7874.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7696.6-7696.10" + attribute \src "ls180.v:7876.6-7876.10" case - attribute \src "ls180.v:7697.3-7700.6" + attribute \src "ls180.v:7877.3-7880.6" switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7697.7-7697.39" + attribute \src "ls180.v:7877.7-7877.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7702.2-7704.5" - switch $and$ls180.v:7702$2505_Y - attribute \src "ls180.v:7702.6-7702.191" + attribute \src "ls180.v:7882.2-7884.5" + switch $and$ls180.v:7882$2638_Y + attribute \src "ls180.v:7882.6-7882.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7703$2506_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7883$2639_Y case end - attribute \src "ls180.v:7705.2-7707.5" + attribute \src "ls180.v:7885.2-7887.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7705.6-7705.58" + attribute \src "ls180.v:7885.6-7885.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7706$2507_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7886$2640_Y case end - attribute \src "ls180.v:7708.2-7716.5" - switch $and$ls180.v:7708$2510_Y - attribute \src "ls180.v:7708.6-7708.191" + attribute \src "ls180.v:7888.2-7896.5" + switch $and$ls180.v:7888$2643_Y + attribute \src "ls180.v:7888.6-7888.191" case 1'1 - attribute \src "ls180.v:7709.3-7711.6" - switch $not$ls180.v:7709$2511_Y - attribute \src "ls180.v:7709.7-7709.62" + attribute \src "ls180.v:7889.3-7891.6" + switch $not$ls180.v:7889$2644_Y + attribute \src "ls180.v:7889.7-7889.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7710$2512_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7890$2645_Y case end - attribute \src "ls180.v:7712.6-7712.10" + attribute \src "ls180.v:7892.6-7892.10" case - attribute \src "ls180.v:7713.3-7715.6" + attribute \src "ls180.v:7893.3-7895.6" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7713.7-7713.59" + attribute \src "ls180.v:7893.7-7893.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7714$2513_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7894$2646_Y case end end - attribute \src "ls180.v:7717.2-7723.5" - switch $or$ls180.v:7717$2515_Y - attribute \src "ls180.v:7717.6-7717.108" + attribute \src "ls180.v:7897.2-7903.5" + switch $or$ls180.v:7897$2648_Y + attribute \src "ls180.v:7897.6-7897.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first @@ -277416,27 +296040,27 @@ module \ls180 assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7724.2-7738.5" + attribute \src "ls180.v:7904.2-7918.5" switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7724.6-7724.43" + attribute \src "ls180.v:7904.6-7904.43" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7726.3-7730.6" + attribute \src "ls180.v:7906.3-7910.6" switch 1'0 - attribute \src "ls180.v:7728.7-7728.11" + attribute \src "ls180.v:7908.7-7908.11" case assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7731.6-7731.10" + attribute \src "ls180.v:7911.6-7911.10" case - attribute \src "ls180.v:7732.3-7737.6" - switch $not$ls180.v:7732$2516_Y - attribute \src "ls180.v:7732.7-7732.47" + attribute \src "ls180.v:7912.3-7917.6" + switch $not$ls180.v:7912$2649_Y + attribute \src "ls180.v:7912.7-7912.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7733$2517_Y - attribute \src "ls180.v:7734.4-7736.7" - switch $eq$ls180.v:7734$2518_Y - attribute \src "ls180.v:7734.8-7734.55" + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7913$2650_Y + attribute \src "ls180.v:7914.4-7916.7" + switch $eq$ls180.v:7914$2651_Y + attribute \src "ls180.v:7914.8-7914.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case @@ -277444,60 +296068,60 @@ module \ls180 case end end - attribute \src "ls180.v:7740.2-7747.5" + attribute \src "ls180.v:7920.2-7927.5" switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7740.6-7740.39" + attribute \src "ls180.v:7920.6-7920.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7742.6-7742.10" + attribute \src "ls180.v:7922.6-7922.10" case - attribute \src "ls180.v:7743.3-7746.6" + attribute \src "ls180.v:7923.3-7926.6" switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7743.7-7743.39" + attribute \src "ls180.v:7923.7-7923.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7748.2-7750.5" - switch $and$ls180.v:7748$2521_Y - attribute \src "ls180.v:7748.6-7748.191" + attribute \src "ls180.v:7928.2-7930.5" + switch $and$ls180.v:7928$2654_Y + attribute \src "ls180.v:7928.6-7928.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7749$2522_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7929$2655_Y case end - attribute \src "ls180.v:7751.2-7753.5" + attribute \src "ls180.v:7931.2-7933.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7751.6-7751.58" + attribute \src "ls180.v:7931.6-7931.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7752$2523_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7932$2656_Y case end - attribute \src "ls180.v:7754.2-7762.5" - switch $and$ls180.v:7754$2526_Y - attribute \src "ls180.v:7754.6-7754.191" + attribute \src "ls180.v:7934.2-7942.5" + switch $and$ls180.v:7934$2659_Y + attribute \src "ls180.v:7934.6-7934.191" case 1'1 - attribute \src "ls180.v:7755.3-7757.6" - switch $not$ls180.v:7755$2527_Y - attribute \src "ls180.v:7755.7-7755.62" + attribute \src "ls180.v:7935.3-7937.6" + switch $not$ls180.v:7935$2660_Y + attribute \src "ls180.v:7935.7-7935.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7756$2528_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7936$2661_Y case end - attribute \src "ls180.v:7758.6-7758.10" + attribute \src "ls180.v:7938.6-7938.10" case - attribute \src "ls180.v:7759.3-7761.6" + attribute \src "ls180.v:7939.3-7941.6" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7759.7-7759.59" + attribute \src "ls180.v:7939.7-7939.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7760$2529_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7940$2662_Y case end end - attribute \src "ls180.v:7763.2-7769.5" - switch $or$ls180.v:7763$2531_Y - attribute \src "ls180.v:7763.6-7763.108" + attribute \src "ls180.v:7943.2-7949.5" + switch $or$ls180.v:7943$2664_Y + attribute \src "ls180.v:7943.6-7943.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first @@ -277506,27 +296130,27 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7770.2-7784.5" + attribute \src "ls180.v:7950.2-7964.5" switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7770.6-7770.43" + attribute \src "ls180.v:7950.6-7950.43" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7772.3-7776.6" + attribute \src "ls180.v:7952.3-7956.6" switch 1'0 - attribute \src "ls180.v:7774.7-7774.11" + attribute \src "ls180.v:7954.7-7954.11" case assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7777.6-7777.10" + attribute \src "ls180.v:7957.6-7957.10" case - attribute \src "ls180.v:7778.3-7783.6" - switch $not$ls180.v:7778$2532_Y - attribute \src "ls180.v:7778.7-7778.47" + attribute \src "ls180.v:7958.3-7963.6" + switch $not$ls180.v:7958$2665_Y + attribute \src "ls180.v:7958.7-7958.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7779$2533_Y - attribute \src "ls180.v:7780.4-7782.7" - switch $eq$ls180.v:7780$2534_Y - attribute \src "ls180.v:7780.8-7780.55" + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7959$2666_Y + attribute \src "ls180.v:7960.4-7962.7" + switch $eq$ls180.v:7960$2667_Y + attribute \src "ls180.v:7960.8-7960.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case @@ -277534,60 +296158,60 @@ module \ls180 case end end - attribute \src "ls180.v:7786.2-7793.5" + attribute \src "ls180.v:7966.2-7973.5" switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7786.6-7786.39" + attribute \src "ls180.v:7966.6-7966.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7788.6-7788.10" + attribute \src "ls180.v:7968.6-7968.10" case - attribute \src "ls180.v:7789.3-7792.6" + attribute \src "ls180.v:7969.3-7972.6" switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7789.7-7789.39" + attribute \src "ls180.v:7969.7-7969.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7794.2-7796.5" - switch $and$ls180.v:7794$2537_Y - attribute \src "ls180.v:7794.6-7794.191" + attribute \src "ls180.v:7974.2-7976.5" + switch $and$ls180.v:7974$2670_Y + attribute \src "ls180.v:7974.6-7974.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7795$2538_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7975$2671_Y case end - attribute \src "ls180.v:7797.2-7799.5" + attribute \src "ls180.v:7977.2-7979.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7797.6-7797.58" + attribute \src "ls180.v:7977.6-7977.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7798$2539_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7978$2672_Y case end - attribute \src "ls180.v:7800.2-7808.5" - switch $and$ls180.v:7800$2542_Y - attribute \src "ls180.v:7800.6-7800.191" + attribute \src "ls180.v:7980.2-7988.5" + switch $and$ls180.v:7980$2675_Y + attribute \src "ls180.v:7980.6-7980.191" case 1'1 - attribute \src "ls180.v:7801.3-7803.6" - switch $not$ls180.v:7801$2543_Y - attribute \src "ls180.v:7801.7-7801.62" + attribute \src "ls180.v:7981.3-7983.6" + switch $not$ls180.v:7981$2676_Y + attribute \src "ls180.v:7981.7-7981.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7802$2544_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7982$2677_Y case end - attribute \src "ls180.v:7804.6-7804.10" + attribute \src "ls180.v:7984.6-7984.10" case - attribute \src "ls180.v:7805.3-7807.6" + attribute \src "ls180.v:7985.3-7987.6" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7805.7-7805.59" + attribute \src "ls180.v:7985.7-7985.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7806$2545_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7986$2678_Y case end end - attribute \src "ls180.v:7809.2-7815.5" - switch $or$ls180.v:7809$2547_Y - attribute \src "ls180.v:7809.6-7809.108" + attribute \src "ls180.v:7989.2-7995.5" + switch $or$ls180.v:7989$2680_Y + attribute \src "ls180.v:7989.6-7989.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first @@ -277596,27 +296220,27 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7816.2-7830.5" + attribute \src "ls180.v:7996.2-8010.5" switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7816.6-7816.43" + attribute \src "ls180.v:7996.6-7996.43" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7818.3-7822.6" + attribute \src "ls180.v:7998.3-8002.6" switch 1'0 - attribute \src "ls180.v:7820.7-7820.11" + attribute \src "ls180.v:8000.7-8000.11" case assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7823.6-7823.10" + attribute \src "ls180.v:8003.6-8003.10" case - attribute \src "ls180.v:7824.3-7829.6" - switch $not$ls180.v:7824$2548_Y - attribute \src "ls180.v:7824.7-7824.47" + attribute \src "ls180.v:8004.3-8009.6" + switch $not$ls180.v:8004$2681_Y + attribute \src "ls180.v:8004.7-8004.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7825$2549_Y - attribute \src "ls180.v:7826.4-7828.7" - switch $eq$ls180.v:7826$2550_Y - attribute \src "ls180.v:7826.8-7826.55" + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8005$2682_Y + attribute \src "ls180.v:8006.4-8008.7" + switch $eq$ls180.v:8006$2683_Y + attribute \src "ls180.v:8006.8-8006.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case @@ -277624,60 +296248,60 @@ module \ls180 case end end - attribute \src "ls180.v:7832.2-7839.5" + attribute \src "ls180.v:8012.2-8019.5" switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7832.6-7832.39" + attribute \src "ls180.v:8012.6-8012.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7834.6-7834.10" + attribute \src "ls180.v:8014.6-8014.10" case - attribute \src "ls180.v:7835.3-7838.6" + attribute \src "ls180.v:8015.3-8018.6" switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7835.7-7835.39" + attribute \src "ls180.v:8015.7-8015.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7840.2-7842.5" - switch $and$ls180.v:7840$2553_Y - attribute \src "ls180.v:7840.6-7840.191" + attribute \src "ls180.v:8020.2-8022.5" + switch $and$ls180.v:8020$2686_Y + attribute \src "ls180.v:8020.6-8020.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7841$2554_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8021$2687_Y case end - attribute \src "ls180.v:7843.2-7845.5" + attribute \src "ls180.v:8023.2-8025.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7843.6-7843.58" + attribute \src "ls180.v:8023.6-8023.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7844$2555_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8024$2688_Y case end - attribute \src "ls180.v:7846.2-7854.5" - switch $and$ls180.v:7846$2558_Y - attribute \src "ls180.v:7846.6-7846.191" + attribute \src "ls180.v:8026.2-8034.5" + switch $and$ls180.v:8026$2691_Y + attribute \src "ls180.v:8026.6-8026.191" case 1'1 - attribute \src "ls180.v:7847.3-7849.6" - switch $not$ls180.v:7847$2559_Y - attribute \src "ls180.v:7847.7-7847.62" + attribute \src "ls180.v:8027.3-8029.6" + switch $not$ls180.v:8027$2692_Y + attribute \src "ls180.v:8027.7-8027.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7848$2560_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8028$2693_Y case end - attribute \src "ls180.v:7850.6-7850.10" + attribute \src "ls180.v:8030.6-8030.10" case - attribute \src "ls180.v:7851.3-7853.6" + attribute \src "ls180.v:8031.3-8033.6" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7851.7-7851.59" + attribute \src "ls180.v:8031.7-8031.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7852$2561_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8032$2694_Y case end end - attribute \src "ls180.v:7855.2-7861.5" - switch $or$ls180.v:7855$2563_Y - attribute \src "ls180.v:7855.6-7855.108" + attribute \src "ls180.v:8035.2-8041.5" + switch $or$ls180.v:8035$2696_Y + attribute \src "ls180.v:8035.6-8035.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first @@ -277686,27 +296310,27 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7862.2-7876.5" + attribute \src "ls180.v:8042.2-8056.5" switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7862.6-7862.43" + attribute \src "ls180.v:8042.6-8042.43" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7864.3-7868.6" + attribute \src "ls180.v:8044.3-8048.6" switch 1'0 - attribute \src "ls180.v:7866.7-7866.11" + attribute \src "ls180.v:8046.7-8046.11" case assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7869.6-7869.10" + attribute \src "ls180.v:8049.6-8049.10" case - attribute \src "ls180.v:7870.3-7875.6" - switch $not$ls180.v:7870$2564_Y - attribute \src "ls180.v:7870.7-7870.47" + attribute \src "ls180.v:8050.3-8055.6" + switch $not$ls180.v:8050$2697_Y + attribute \src "ls180.v:8050.7-8050.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7871$2565_Y - attribute \src "ls180.v:7872.4-7874.7" - switch $eq$ls180.v:7872$2566_Y - attribute \src "ls180.v:7872.8-7872.55" + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8051$2698_Y + attribute \src "ls180.v:8052.4-8054.7" + switch $eq$ls180.v:8052$2699_Y + attribute \src "ls180.v:8052.8-8052.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case @@ -277714,61 +296338,61 @@ module \ls180 case end end - attribute \src "ls180.v:7878.2-7884.5" - switch $not$ls180.v:7878$2567_Y - attribute \src "ls180.v:7878.6-7878.23" + attribute \src "ls180.v:8058.2-8064.5" + switch $not$ls180.v:8058$2700_Y + attribute \src "ls180.v:8058.6-8058.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7880.6-7880.10" + attribute \src "ls180.v:8060.6-8060.10" case - attribute \src "ls180.v:7881.3-7883.6" - switch $not$ls180.v:7881$2568_Y - attribute \src "ls180.v:7881.7-7881.30" + attribute \src "ls180.v:8061.3-8063.6" + switch $not$ls180.v:8061$2701_Y + attribute \src "ls180.v:8061.7-8061.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7882$2569_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:8062$2702_Y case end end - attribute \src "ls180.v:7885.2-7891.5" - switch $not$ls180.v:7885$2570_Y - attribute \src "ls180.v:7885.6-7885.23" + attribute \src "ls180.v:8065.2-8071.5" + switch $not$ls180.v:8065$2703_Y + attribute \src "ls180.v:8065.6-8065.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7887.6-7887.10" + attribute \src "ls180.v:8067.6-8067.10" case - attribute \src "ls180.v:7888.3-7890.6" - switch $not$ls180.v:7888$2571_Y - attribute \src "ls180.v:7888.7-7888.30" + attribute \src "ls180.v:8068.3-8070.6" + switch $not$ls180.v:8068$2704_Y + attribute \src "ls180.v:8068.7-8068.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7889$2572_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:8069$2705_Y case end end - attribute \src "ls180.v:7892.2-7947.5" + attribute \src "ls180.v:8072.2-8127.5" switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7892.6-7892.30" + attribute \src "ls180.v:8072.6-8072.30" case 1'1 - attribute \src "ls180.v:7893.3-7946.10" + attribute \src "ls180.v:8073.3-8126.10" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7895.5-7905.8" + attribute \src "ls180.v:8075.5-8085.8" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7895.9-7895.41" + attribute \src "ls180.v:8075.9-8075.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7897.9-7897.13" + attribute \src "ls180.v:8077.9-8077.13" case - attribute \src "ls180.v:7898.6-7904.9" + attribute \src "ls180.v:8078.6-8084.9" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7898.10-7898.42" + attribute \src "ls180.v:8078.10-8078.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7900.10-7900.14" + attribute \src "ls180.v:8080.10-8080.14" case - attribute \src "ls180.v:7901.7-7903.10" + attribute \src "ls180.v:8081.7-8083.10" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7901.11-7901.43" + attribute \src "ls180.v:8081.11-8081.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 case @@ -277777,23 +296401,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7908.5-7918.8" + attribute \src "ls180.v:8088.5-8098.8" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7908.9-7908.41" + attribute \src "ls180.v:8088.9-8088.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7910.9-7910.13" + attribute \src "ls180.v:8090.9-8090.13" case - attribute \src "ls180.v:7911.6-7917.9" + attribute \src "ls180.v:8091.6-8097.9" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7911.10-7911.42" + attribute \src "ls180.v:8091.10-8091.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7913.10-7913.14" + attribute \src "ls180.v:8093.10-8093.14" case - attribute \src "ls180.v:7914.7-7916.10" + attribute \src "ls180.v:8094.7-8096.10" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7914.11-7914.43" + attribute \src "ls180.v:8094.11-8094.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 case @@ -277802,23 +296426,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7921.5-7931.8" + attribute \src "ls180.v:8101.5-8111.8" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7921.9-7921.41" + attribute \src "ls180.v:8101.9-8101.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7923.9-7923.13" + attribute \src "ls180.v:8103.9-8103.13" case - attribute \src "ls180.v:7924.6-7930.9" + attribute \src "ls180.v:8104.6-8110.9" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7924.10-7924.42" + attribute \src "ls180.v:8104.10-8104.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7926.10-7926.14" + attribute \src "ls180.v:8106.10-8106.14" case - attribute \src "ls180.v:7927.7-7929.10" + attribute \src "ls180.v:8107.7-8109.10" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7927.11-7927.43" + attribute \src "ls180.v:8107.11-8107.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 case @@ -277827,23 +296451,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7934.5-7944.8" + attribute \src "ls180.v:8114.5-8124.8" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7934.9-7934.41" + attribute \src "ls180.v:8114.9-8114.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7936.9-7936.13" + attribute \src "ls180.v:8116.9-8116.13" case - attribute \src "ls180.v:7937.6-7943.9" + attribute \src "ls180.v:8117.6-8123.9" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7937.10-7937.42" + attribute \src "ls180.v:8117.10-8117.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7939.10-7939.14" + attribute \src "ls180.v:8119.10-8119.14" case - attribute \src "ls180.v:7940.7-7942.10" + attribute \src "ls180.v:8120.7-8122.10" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7940.11-7940.43" + attribute \src "ls180.v:8120.11-8120.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 case @@ -277854,31 +296478,31 @@ module \ls180 end case end - attribute \src "ls180.v:7948.2-8003.5" + attribute \src "ls180.v:8128.2-8183.5" switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7948.6-7948.30" + attribute \src "ls180.v:8128.6-8128.30" case 1'1 - attribute \src "ls180.v:7949.3-8002.10" + attribute \src "ls180.v:8129.3-8182.10" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7951.5-7961.8" + attribute \src "ls180.v:8131.5-8141.8" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7951.9-7951.41" + attribute \src "ls180.v:8131.9-8131.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7953.9-7953.13" + attribute \src "ls180.v:8133.9-8133.13" case - attribute \src "ls180.v:7954.6-7960.9" + attribute \src "ls180.v:8134.6-8140.9" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7954.10-7954.42" + attribute \src "ls180.v:8134.10-8134.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7956.10-7956.14" + attribute \src "ls180.v:8136.10-8136.14" case - attribute \src "ls180.v:7957.7-7959.10" + attribute \src "ls180.v:8137.7-8139.10" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7957.11-7957.43" + attribute \src "ls180.v:8137.11-8137.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 case @@ -277887,23 +296511,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7964.5-7974.8" + attribute \src "ls180.v:8144.5-8154.8" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7964.9-7964.41" + attribute \src "ls180.v:8144.9-8144.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7966.9-7966.13" + attribute \src "ls180.v:8146.9-8146.13" case - attribute \src "ls180.v:7967.6-7973.9" + attribute \src "ls180.v:8147.6-8153.9" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7967.10-7967.42" + attribute \src "ls180.v:8147.10-8147.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7969.10-7969.14" + attribute \src "ls180.v:8149.10-8149.14" case - attribute \src "ls180.v:7970.7-7972.10" + attribute \src "ls180.v:8150.7-8152.10" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7970.11-7970.43" + attribute \src "ls180.v:8150.11-8150.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 case @@ -277912,23 +296536,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7977.5-7987.8" + attribute \src "ls180.v:8157.5-8167.8" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7977.9-7977.41" + attribute \src "ls180.v:8157.9-8157.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7979.9-7979.13" + attribute \src "ls180.v:8159.9-8159.13" case - attribute \src "ls180.v:7980.6-7986.9" + attribute \src "ls180.v:8160.6-8166.9" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7980.10-7980.42" + attribute \src "ls180.v:8160.10-8160.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7982.10-7982.14" + attribute \src "ls180.v:8162.10-8162.14" case - attribute \src "ls180.v:7983.7-7985.10" + attribute \src "ls180.v:8163.7-8165.10" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7983.11-7983.43" + attribute \src "ls180.v:8163.11-8163.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 case @@ -277937,23 +296561,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7990.5-8000.8" + attribute \src "ls180.v:8170.5-8180.8" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7990.9-7990.41" + attribute \src "ls180.v:8170.9-8170.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7992.9-7992.13" + attribute \src "ls180.v:8172.9-8172.13" case - attribute \src "ls180.v:7993.6-7999.9" + attribute \src "ls180.v:8173.6-8179.9" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7993.10-7993.42" + attribute \src "ls180.v:8173.10-8173.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7995.10-7995.14" + attribute \src "ls180.v:8175.10-8175.14" case - attribute \src "ls180.v:7996.7-7998.10" + attribute \src "ls180.v:8176.7-8178.10" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7996.11-7996.43" + attribute \src "ls180.v:8176.11-8176.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 case @@ -277964,28 +296588,28 @@ module \ls180 end case end - attribute \src "ls180.v:8012.2-8026.5" + attribute \src "ls180.v:8192.2-8206.5" switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:8012.6-8012.30" + attribute \src "ls180.v:8192.6-8192.30" case 1'1 assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:8014.3-8018.6" + attribute \src "ls180.v:8194.3-8198.6" switch 1'1 - attribute \src "ls180.v:8014.7-8014.11" + attribute \src "ls180.v:8194.7-8194.11" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:8019.6-8019.10" + attribute \src "ls180.v:8199.6-8199.10" case - attribute \src "ls180.v:8020.3-8025.6" - switch $not$ls180.v:8020$2576_Y - attribute \src "ls180.v:8020.7-8020.34" + attribute \src "ls180.v:8200.3-8205.6" + switch $not$ls180.v:8200$2709_Y + attribute \src "ls180.v:8200.7-8200.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8021$2577_Y - attribute \src "ls180.v:8022.4-8024.7" - switch $eq$ls180.v:8022$2578_Y - attribute \src "ls180.v:8022.8-8022.42" + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8201$2710_Y + attribute \src "ls180.v:8202.4-8204.7" + switch $eq$ls180.v:8202$2711_Y + attribute \src "ls180.v:8202.8-8202.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case @@ -277993,27 +296617,27 @@ module \ls180 case end end - attribute \src "ls180.v:8027.2-8041.5" + attribute \src "ls180.v:8207.2-8221.5" switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:8027.6-8027.30" + attribute \src "ls180.v:8207.6-8207.30" case 1'1 assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:8029.3-8033.6" + attribute \src "ls180.v:8209.3-8213.6" switch 1'0 - attribute \src "ls180.v:8031.7-8031.11" + attribute \src "ls180.v:8211.7-8211.11" case assign $0\main_sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8034.6-8034.10" + attribute \src "ls180.v:8214.6-8214.10" case - attribute \src "ls180.v:8035.3-8040.6" - switch $not$ls180.v:8035$2579_Y - attribute \src "ls180.v:8035.7-8035.34" + attribute \src "ls180.v:8215.3-8220.6" + switch $not$ls180.v:8215$2712_Y + attribute \src "ls180.v:8215.7-8215.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8036$2580_Y - attribute \src "ls180.v:8037.4-8039.7" - switch $eq$ls180.v:8037$2581_Y - attribute \src "ls180.v:8037.8-8037.42" + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8216$2713_Y + attribute \src "ls180.v:8217.4-8219.7" + switch $eq$ls180.v:8217$2714_Y + attribute \src "ls180.v:8217.8-8217.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 case @@ -278021,81 +296645,81 @@ module \ls180 case end end - attribute \src "ls180.v:8048.2-8050.5" - switch $or$ls180.v:8048$2606_Y - attribute \src "ls180.v:8048.6-8048.50" + attribute \src "ls180.v:8228.2-8230.5" + switch $or$ls180.v:8228$2739_Y + attribute \src "ls180.v:8228.6-8228.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r case end - attribute \src "ls180.v:8052.2-8054.5" + attribute \src "ls180.v:8232.2-8234.5" switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:8052.6-8052.52" + attribute \src "ls180.v:8232.6-8232.52" case 1'1 assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value case end - attribute \src "ls180.v:8055.2-8058.5" + attribute \src "ls180.v:8235.2-8238.5" switch \main_converter_reset - attribute \src "ls180.v:8055.6-8055.26" + attribute \src "ls180.v:8235.6-8235.26" case 1'1 assign $0\main_converter_counter[0:0] 1'0 assign $0\builder_converter_state[0:0] 1'0 case end - attribute \src "ls180.v:8059.2-8069.5" + attribute \src "ls180.v:8239.2-8249.5" switch \main_litedram_wb_ack - attribute \src "ls180.v:8059.6-8059.26" + attribute \src "ls180.v:8239.6-8239.26" case 1'1 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:8062.6-8062.10" + attribute \src "ls180.v:8242.6-8242.10" case - attribute \src "ls180.v:8063.3-8065.6" - switch $and$ls180.v:8063$2607_Y - attribute \src "ls180.v:8063.7-8063.50" + attribute \src "ls180.v:8243.3-8245.6" + switch $and$ls180.v:8243$2740_Y + attribute \src "ls180.v:8243.7-8243.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:8066.3-8068.6" - switch $and$ls180.v:8066$2608_Y - attribute \src "ls180.v:8066.7-8066.54" + attribute \src "ls180.v:8246.3-8248.6" + switch $and$ls180.v:8246$2741_Y + attribute \src "ls180.v:8246.7-8246.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:8071.2-8092.5" - switch $and$ls180.v:8071$2612_Y - attribute \src "ls180.v:8071.6-8071.91" + attribute \src "ls180.v:8251.2-8272.5" + switch $and$ls180.v:8251$2745_Y + attribute \src "ls180.v:8251.6-8251.91" case 1'1 assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 assign $0\main_uart_phy_tx_busy[0:0] 1'1 assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:8076.6-8076.10" + attribute \src "ls180.v:8256.6-8256.10" case - attribute \src "ls180.v:8077.3-8091.6" - switch $and$ls180.v:8077$2613_Y - attribute \src "ls180.v:8077.7-8077.60" + attribute \src "ls180.v:8257.3-8271.6" + switch $and$ls180.v:8257$2746_Y + attribute \src "ls180.v:8257.7-8257.60" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8078$2614_Y - attribute \src "ls180.v:8079.4-8090.7" - switch $eq$ls180.v:8079$2615_Y - attribute \src "ls180.v:8079.8-8079.43" + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8258$2747_Y + attribute \src "ls180.v:8259.4-8270.7" + switch $eq$ls180.v:8259$2748_Y + attribute \src "ls180.v:8259.8-8259.43" case 1'1 assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:8081.8-8081.12" + attribute \src "ls180.v:8261.8-8261.12" case - attribute \src "ls180.v:8082.5-8089.8" - switch $eq$ls180.v:8082$2616_Y - attribute \src "ls180.v:8082.9-8082.44" + attribute \src "ls180.v:8262.5-8269.8" + switch $eq$ls180.v:8262$2749_Y + attribute \src "ls180.v:8262.9-8262.44" case 1'1 assign $0\uart_tx[0:0] 1'1 assign $0\main_uart_phy_tx_busy[0:0] 1'0 assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:8086.9-8086.13" + attribute \src "ls180.v:8266.9-8266.13" case assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } @@ -278104,61 +296728,61 @@ module \ls180 case end end - attribute \src "ls180.v:8093.2-8097.5" + attribute \src "ls180.v:8273.2-8277.5" switch \main_uart_phy_tx_busy - attribute \src "ls180.v:8093.6-8093.27" + attribute \src "ls180.v:8273.6-8273.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8094$2617_Y - attribute \src "ls180.v:8095.6-8095.10" + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8274$2750_Y + attribute \src "ls180.v:8275.6-8275.10" case assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } end - attribute \src "ls180.v:8100.2-8124.5" - switch $not$ls180.v:8100$2618_Y - attribute \src "ls180.v:8100.6-8100.30" + attribute \src "ls180.v:8280.2-8304.5" + switch $not$ls180.v:8280$2751_Y + attribute \src "ls180.v:8280.6-8280.30" case 1'1 - attribute \src "ls180.v:8101.3-8104.6" - switch $and$ls180.v:8101$2620_Y - attribute \src "ls180.v:8101.7-8101.49" + attribute \src "ls180.v:8281.3-8284.6" + switch $and$ls180.v:8281$2753_Y + attribute \src "ls180.v:8281.7-8281.49" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'1 assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:8105.6-8105.10" + attribute \src "ls180.v:8285.6-8285.10" case - attribute \src "ls180.v:8106.3-8123.6" + attribute \src "ls180.v:8286.3-8303.6" switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:8106.7-8106.34" + attribute \src "ls180.v:8286.7-8286.34" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8107$2621_Y - attribute \src "ls180.v:8108.4-8122.7" - switch $eq$ls180.v:8108$2622_Y - attribute \src "ls180.v:8108.8-8108.43" + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8287$2754_Y + attribute \src "ls180.v:8288.4-8302.7" + switch $eq$ls180.v:8288$2755_Y + attribute \src "ls180.v:8288.8-8288.43" case 1'1 - attribute \src "ls180.v:8109.5-8111.8" + attribute \src "ls180.v:8289.5-8291.8" switch \main_uart_phy_rx - attribute \src "ls180.v:8109.9-8109.25" + attribute \src "ls180.v:8289.9-8289.25" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:8112.8-8112.12" + attribute \src "ls180.v:8292.8-8292.12" case - attribute \src "ls180.v:8113.5-8121.8" - switch $eq$ls180.v:8113$2623_Y - attribute \src "ls180.v:8113.9-8113.44" + attribute \src "ls180.v:8293.5-8301.8" + switch $eq$ls180.v:8293$2756_Y + attribute \src "ls180.v:8293.9-8293.44" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8115.6-8118.9" + attribute \src "ls180.v:8295.6-8298.9" switch \main_uart_phy_rx - attribute \src "ls180.v:8115.10-8115.26" + attribute \src "ls180.v:8295.10-8295.26" case 1'1 assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg assign $0\main_uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:8119.9-8119.13" + attribute \src "ls180.v:8299.9-8299.13" case assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } end @@ -278166,146 +296790,146 @@ module \ls180 case end end - attribute \src "ls180.v:8125.2-8129.5" + attribute \src "ls180.v:8305.2-8309.5" switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8125.6-8125.27" + attribute \src "ls180.v:8305.6-8305.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8126$2624_Y - attribute \src "ls180.v:8127.6-8127.10" + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8306$2757_Y + attribute \src "ls180.v:8307.6-8307.10" case assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:8130.2-8132.5" + attribute \src "ls180.v:8310.2-8312.5" switch \main_uart_tx_clear - attribute \src "ls180.v:8130.6-8130.24" + attribute \src "ls180.v:8310.6-8310.24" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8134.2-8136.5" - switch $and$ls180.v:8134$2626_Y - attribute \src "ls180.v:8134.6-8134.58" + attribute \src "ls180.v:8314.2-8316.5" + switch $and$ls180.v:8314$2759_Y + attribute \src "ls180.v:8314.6-8314.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8137.2-8139.5" + attribute \src "ls180.v:8317.2-8319.5" switch \main_uart_rx_clear - attribute \src "ls180.v:8137.6-8137.24" + attribute \src "ls180.v:8317.6-8317.24" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8141.2-8143.5" - switch $and$ls180.v:8141$2628_Y - attribute \src "ls180.v:8141.6-8141.58" + attribute \src "ls180.v:8321.2-8323.5" + switch $and$ls180.v:8321$2761_Y + attribute \src "ls180.v:8321.6-8321.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8144.2-8150.5" + attribute \src "ls180.v:8324.2-8330.5" switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8144.6-8144.35" + attribute \src "ls180.v:8324.6-8324.35" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8146.6-8146.10" + attribute \src "ls180.v:8326.6-8326.10" case - attribute \src "ls180.v:8147.3-8149.6" + attribute \src "ls180.v:8327.3-8329.6" switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8147.7-8147.27" + attribute \src "ls180.v:8327.7-8327.27" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8151.2-8153.5" - switch $and$ls180.v:8151$2631_Y - attribute \src "ls180.v:8151.6-8151.108" + attribute \src "ls180.v:8331.2-8333.5" + switch $and$ls180.v:8331$2764_Y + attribute \src "ls180.v:8331.6-8331.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8152$2632_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8332$2765_Y case end - attribute \src "ls180.v:8154.2-8156.5" + attribute \src "ls180.v:8334.2-8336.5" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8154.6-8154.31" + attribute \src "ls180.v:8334.6-8334.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8155$2633_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8335$2766_Y case end - attribute \src "ls180.v:8157.2-8165.5" - switch $and$ls180.v:8157$2636_Y - attribute \src "ls180.v:8157.6-8157.108" + attribute \src "ls180.v:8337.2-8345.5" + switch $and$ls180.v:8337$2769_Y + attribute \src "ls180.v:8337.6-8337.108" case 1'1 - attribute \src "ls180.v:8158.3-8160.6" - switch $not$ls180.v:8158$2637_Y - attribute \src "ls180.v:8158.7-8158.35" + attribute \src "ls180.v:8338.3-8340.6" + switch $not$ls180.v:8338$2770_Y + attribute \src "ls180.v:8338.7-8338.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8159$2638_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8339$2771_Y case end - attribute \src "ls180.v:8161.6-8161.10" + attribute \src "ls180.v:8341.6-8341.10" case - attribute \src "ls180.v:8162.3-8164.6" + attribute \src "ls180.v:8342.3-8344.6" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8162.7-8162.32" + attribute \src "ls180.v:8342.7-8342.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8163$2639_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8343$2772_Y case end end - attribute \src "ls180.v:8166.2-8172.5" + attribute \src "ls180.v:8346.2-8352.5" switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8166.6-8166.35" + attribute \src "ls180.v:8346.6-8346.35" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8168.6-8168.10" + attribute \src "ls180.v:8348.6-8348.10" case - attribute \src "ls180.v:8169.3-8171.6" + attribute \src "ls180.v:8349.3-8351.6" switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8169.7-8169.27" + attribute \src "ls180.v:8349.7-8349.27" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8173.2-8175.5" - switch $and$ls180.v:8173$2642_Y - attribute \src "ls180.v:8173.6-8173.108" + attribute \src "ls180.v:8353.2-8355.5" + switch $and$ls180.v:8353$2775_Y + attribute \src "ls180.v:8353.6-8353.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8174$2643_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8354$2776_Y case end - attribute \src "ls180.v:8176.2-8178.5" + attribute \src "ls180.v:8356.2-8358.5" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8176.6-8176.31" + attribute \src "ls180.v:8356.6-8356.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8177$2644_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8357$2777_Y case end - attribute \src "ls180.v:8179.2-8187.5" - switch $and$ls180.v:8179$2647_Y - attribute \src "ls180.v:8179.6-8179.108" + attribute \src "ls180.v:8359.2-8367.5" + switch $and$ls180.v:8359$2780_Y + attribute \src "ls180.v:8359.6-8359.108" case 1'1 - attribute \src "ls180.v:8180.3-8182.6" - switch $not$ls180.v:8180$2648_Y - attribute \src "ls180.v:8180.7-8180.35" + attribute \src "ls180.v:8360.3-8362.6" + switch $not$ls180.v:8360$2781_Y + attribute \src "ls180.v:8360.7-8360.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8181$2649_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8361$2782_Y case end - attribute \src "ls180.v:8183.6-8183.10" + attribute \src "ls180.v:8363.6-8363.10" case - attribute \src "ls180.v:8184.3-8186.6" + attribute \src "ls180.v:8364.3-8366.6" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8184.7-8184.32" + attribute \src "ls180.v:8364.7-8364.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8185$2650_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8365$2783_Y case end end - attribute \src "ls180.v:8188.2-8201.5" + attribute \src "ls180.v:8368.2-8381.5" switch \main_uart_reset - attribute \src "ls180.v:8188.6-8188.21" + attribute \src "ls180.v:8368.6-8368.21" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 assign $0\main_uart_tx_old_trigger[0:0] 1'0 @@ -278321,38 +296945,38 @@ module \ls180 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:8203.2-8210.5" + attribute \src "ls180.v:8383.2-8390.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8203.6-8203.31" + attribute \src "ls180.v:8383.6-8383.31" case 1'1 assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8205.6-8205.10" + attribute \src "ls180.v:8385.6-8385.10" case - attribute \src "ls180.v:8206.3-8209.6" + attribute \src "ls180.v:8386.3-8389.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8206.7-8206.32" + attribute \src "ls180.v:8386.7-8386.32" case 1'1 assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 assign $0\spisdcard_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8212.2-8222.5" + attribute \src "ls180.v:8392.2-8402.5" switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8212.6-8212.33" + attribute \src "ls180.v:8392.6-8392.33" case 1'1 assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8215.6-8215.10" + attribute \src "ls180.v:8395.6-8395.10" case - attribute \src "ls180.v:8216.3-8221.6" + attribute \src "ls180.v:8396.3-8401.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8216.7-8216.32" + attribute \src "ls180.v:8396.7-8396.32" case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8220$2655_Y - attribute \src "ls180.v:8217.4-8219.7" + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8400$2788_Y + attribute \src "ls180.v:8397.4-8399.7" switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8217.8-8217.34" + attribute \src "ls180.v:8397.8-8397.34" case 1'1 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 case @@ -278360,67 +296984,67 @@ module \ls180 case end end - attribute \src "ls180.v:8223.2-8229.5" + attribute \src "ls180.v:8403.2-8409.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8223.6-8223.31" + attribute \src "ls180.v:8403.6-8403.31" case 1'1 - attribute \src "ls180.v:8224.3-8228.6" + attribute \src "ls180.v:8404.3-8408.6" switch \main_spimaster7_loopback - attribute \src "ls180.v:8224.7-8224.31" + attribute \src "ls180.v:8404.7-8404.31" case 1'1 assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8226.7-8226.11" + attribute \src "ls180.v:8406.7-8406.11" case assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } end case end - attribute \src "ls180.v:8230.2-8232.5" + attribute \src "ls180.v:8410.2-8412.5" switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8230.6-8230.33" + attribute \src "ls180.v:8410.6-8410.33" case 1'1 assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data case end - attribute \src "ls180.v:8234.2-8236.5" + attribute \src "ls180.v:8414.2-8416.5" switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8234.6-8234.53" + attribute \src "ls180.v:8414.6-8414.53" case 1'1 assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value case end - attribute \src "ls180.v:8238.2-8245.5" + attribute \src "ls180.v:8418.2-8425.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8238.6-8238.29" + attribute \src "ls180.v:8418.6-8418.29" case 1'1 assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8240.6-8240.10" + attribute \src "ls180.v:8420.6-8420.10" case - attribute \src "ls180.v:8241.3-8244.6" + attribute \src "ls180.v:8421.3-8424.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8241.7-8241.30" + attribute \src "ls180.v:8421.7-8421.30" case 1'1 assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 assign $0\spimaster_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8247.2-8257.5" + attribute \src "ls180.v:8427.2-8437.5" switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8247.6-8247.31" + attribute \src "ls180.v:8427.6-8427.31" case 1'1 assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8250.6-8250.10" + attribute \src "ls180.v:8430.6-8430.10" case - attribute \src "ls180.v:8251.3-8256.6" + attribute \src "ls180.v:8431.3-8436.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8251.7-8251.30" + attribute \src "ls180.v:8431.7-8431.30" case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8255$2660_Y - attribute \src "ls180.v:8252.4-8254.7" + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8435$2793_Y + attribute \src "ls180.v:8432.4-8434.7" switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8252.8-8252.32" + attribute \src "ls180.v:8432.8-8432.32" case 1'1 assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 case @@ -278428,169 +297052,169 @@ module \ls180 case end end - attribute \src "ls180.v:8258.2-8264.5" + attribute \src "ls180.v:8438.2-8444.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8258.6-8258.29" + attribute \src "ls180.v:8438.6-8438.29" case 1'1 - attribute \src "ls180.v:8259.3-8263.6" + attribute \src "ls180.v:8439.3-8443.6" switch \main_spisdcard_loopback - attribute \src "ls180.v:8259.7-8259.30" + attribute \src "ls180.v:8439.7-8439.30" case 1'1 assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8261.7-8261.11" + attribute \src "ls180.v:8441.7-8441.11" case assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } end case end - attribute \src "ls180.v:8265.2-8267.5" + attribute \src "ls180.v:8445.2-8447.5" switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8265.6-8265.31" + attribute \src "ls180.v:8445.6-8445.31" case 1'1 assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data case end - attribute \src "ls180.v:8269.2-8271.5" + attribute \src "ls180.v:8449.2-8451.5" switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8269.6-8269.51" + attribute \src "ls180.v:8449.6-8449.51" case 1'1 assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value case end - attribute \src "ls180.v:8272.2-8285.5" + attribute \src "ls180.v:8452.2-8465.5" switch \main_pwm0_enable - attribute \src "ls180.v:8272.6-8272.22" + attribute \src "ls180.v:8452.6-8452.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8273$2661_Y - attribute \src "ls180.v:8274.3-8278.6" - switch $lt$ls180.v:8274$2662_Y - attribute \src "ls180.v:8274.7-8274.44" + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8453$2794_Y + attribute \src "ls180.v:8454.3-8458.6" + switch $lt$ls180.v:8454$2795_Y + attribute \src "ls180.v:8454.7-8454.44" case 1'1 assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8276.7-8276.11" + attribute \src "ls180.v:8456.7-8456.11" case assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8279.3-8281.6" - switch $ge$ls180.v:8279$2664_Y - attribute \src "ls180.v:8279.7-8279.55" + attribute \src "ls180.v:8459.3-8461.6" + switch $ge$ls180.v:8459$2797_Y + attribute \src "ls180.v:8459.7-8459.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 case end - attribute \src "ls180.v:8282.6-8282.10" + attribute \src "ls180.v:8462.6-8462.10" case assign $0\main_pwm0_counter[31:0] 0 assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8286.2-8299.5" + attribute \src "ls180.v:8466.2-8479.5" switch \main_pwm1_enable - attribute \src "ls180.v:8286.6-8286.22" + attribute \src "ls180.v:8466.6-8466.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8287$2665_Y - attribute \src "ls180.v:8288.3-8292.6" - switch $lt$ls180.v:8288$2666_Y - attribute \src "ls180.v:8288.7-8288.44" + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8467$2798_Y + attribute \src "ls180.v:8468.3-8472.6" + switch $lt$ls180.v:8468$2799_Y + attribute \src "ls180.v:8468.7-8468.44" case 1'1 assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8290.7-8290.11" + attribute \src "ls180.v:8470.7-8470.11" case assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8293.3-8295.6" - switch $ge$ls180.v:8293$2668_Y - attribute \src "ls180.v:8293.7-8293.55" + attribute \src "ls180.v:8473.3-8475.6" + switch $ge$ls180.v:8473$2801_Y + attribute \src "ls180.v:8473.7-8473.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 case end - attribute \src "ls180.v:8296.6-8296.10" + attribute \src "ls180.v:8476.6-8476.10" case assign $0\main_pwm1_counter[31:0] 0 assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8300.2-8302.5" - switch $not$ls180.v:8300$2669_Y - attribute \src "ls180.v:8300.6-8300.32" + attribute \src "ls180.v:8480.2-8482.5" + switch $not$ls180.v:8480$2802_Y + attribute \src "ls180.v:8480.6-8480.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8301$2670_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8481$2803_Y case end - attribute \src "ls180.v:8306.2-8308.5" + attribute \src "ls180.v:8486.2-8488.5" switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8306.6-8306.57" + attribute \src "ls180.v:8486.6-8486.57" case 1'1 assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value case end - attribute \src "ls180.v:8310.2-8312.5" + attribute \src "ls180.v:8490.2-8492.5" switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8310.6-8310.57" + attribute \src "ls180.v:8490.6-8490.57" case 1'1 assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value case end - attribute \src "ls180.v:8313.2-8315.5" + attribute \src "ls180.v:8493.2-8495.5" switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8313.6-8313.40" + attribute \src "ls180.v:8493.6-8493.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8314$2671_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8494$2804_Y case end - attribute \src "ls180.v:8316.2-8318.5" + attribute \src "ls180.v:8496.2-8498.5" switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8316.6-8316.49" + attribute \src "ls180.v:8496.6-8496.49" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8319.2-8326.5" + attribute \src "ls180.v:8499.2-8506.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8319.6-8319.46" + attribute \src "ls180.v:8499.6-8499.46" case 1'1 - attribute \src "ls180.v:8320.3-8325.6" - switch $or$ls180.v:8320$2673_Y - attribute \src "ls180.v:8320.7-8320.98" + attribute \src "ls180.v:8500.3-8505.6" + switch $or$ls180.v:8500$2806_Y + attribute \src "ls180.v:8500.7-8500.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8323.7-8323.11" + attribute \src "ls180.v:8503.7-8503.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8324$2674_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8504$2807_Y end case end - attribute \src "ls180.v:8327.2-8340.5" - switch $and$ls180.v:8327$2675_Y - attribute \src "ls180.v:8327.6-8327.97" + attribute \src "ls180.v:8507.2-8520.5" + switch $and$ls180.v:8507$2808_Y + attribute \src "ls180.v:8507.6-8507.97" case 1'1 - attribute \src "ls180.v:8328.3-8334.6" - switch $and$ls180.v:8328$2676_Y - attribute \src "ls180.v:8328.7-8328.94" + attribute \src "ls180.v:8508.3-8514.6" + switch $and$ls180.v:8508$2809_Y + attribute \src "ls180.v:8508.7-8508.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8331.7-8331.11" + attribute \src "ls180.v:8511.7-8511.11" case assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8335.6-8335.10" + attribute \src "ls180.v:8515.6-8515.10" case - attribute \src "ls180.v:8336.3-8339.6" - switch $and$ls180.v:8336$2677_Y - attribute \src "ls180.v:8336.7-8336.94" + attribute \src "ls180.v:8516.3-8519.6" + switch $and$ls180.v:8516$2810_Y + attribute \src "ls180.v:8516.7-8516.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8337$2678_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8338$2679_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8517$2811_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8518$2812_Y case end end - attribute \src "ls180.v:8341.2-8368.5" + attribute \src "ls180.v:8521.2-8548.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8341.6-8341.46" + attribute \src "ls180.v:8521.6-8521.46" case 1'1 - attribute \src "ls180.v:8342.3-8367.10" + attribute \src "ls180.v:8522.3-8547.10" switch \main_sdphy_cmdr_cmdr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -278620,16 +297244,16 @@ module \ls180 end case end - attribute \src "ls180.v:8369.2-8371.5" + attribute \src "ls180.v:8549.2-8551.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8369.6-8369.46" + attribute \src "ls180.v:8549.6-8549.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8370$2680_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8550$2813_Y case end - attribute \src "ls180.v:8372.2-8377.5" - switch $or$ls180.v:8372$2682_Y - attribute \src "ls180.v:8372.6-8372.88" + attribute \src "ls180.v:8552.2-8557.5" + switch $or$ls180.v:8552$2815_Y + attribute \src "ls180.v:8552.6-8552.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first @@ -278637,9 +297261,9 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data case end - attribute \src "ls180.v:8378.2-8383.5" + attribute \src "ls180.v:8558.2-8563.5" switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8378.6-8378.32" + attribute \src "ls180.v:8558.6-8558.32" case 1'1 assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 @@ -278647,88 +297271,88 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8385.2-8387.5" + attribute \src "ls180.v:8565.2-8567.5" switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8385.6-8385.58" + attribute \src "ls180.v:8565.6-8565.58" case 1'1 assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 case end - attribute \src "ls180.v:8388.2-8390.5" + attribute \src "ls180.v:8568.2-8570.5" switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8388.6-8388.60" + attribute \src "ls180.v:8568.6-8568.60" case 1'1 assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 case end - attribute \src "ls180.v:8391.2-8393.5" + attribute \src "ls180.v:8571.2-8573.5" switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8391.6-8391.63" + attribute \src "ls180.v:8571.6-8571.63" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 case end - attribute \src "ls180.v:8394.2-8396.5" + attribute \src "ls180.v:8574.2-8576.5" switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8394.6-8394.41" + attribute \src "ls180.v:8574.6-8574.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8395$2683_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8575$2816_Y case end - attribute \src "ls180.v:8397.2-8399.5" + attribute \src "ls180.v:8577.2-8579.5" switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8397.6-8397.50" + attribute \src "ls180.v:8577.6-8577.50" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8400.2-8407.5" + attribute \src "ls180.v:8580.2-8587.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8400.6-8400.47" + attribute \src "ls180.v:8580.6-8580.47" case 1'1 - attribute \src "ls180.v:8401.3-8406.6" - switch $or$ls180.v:8401$2685_Y - attribute \src "ls180.v:8401.7-8401.100" + attribute \src "ls180.v:8581.3-8586.6" + switch $or$ls180.v:8581$2818_Y + attribute \src "ls180.v:8581.7-8581.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8404.7-8404.11" + attribute \src "ls180.v:8584.7-8584.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8405$2686_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8585$2819_Y end case end - attribute \src "ls180.v:8408.2-8421.5" - switch $and$ls180.v:8408$2687_Y - attribute \src "ls180.v:8408.6-8408.99" + attribute \src "ls180.v:8588.2-8601.5" + switch $and$ls180.v:8588$2820_Y + attribute \src "ls180.v:8588.6-8588.99" case 1'1 - attribute \src "ls180.v:8409.3-8415.6" - switch $and$ls180.v:8409$2688_Y - attribute \src "ls180.v:8409.7-8409.96" + attribute \src "ls180.v:8589.3-8595.6" + switch $and$ls180.v:8589$2821_Y + attribute \src "ls180.v:8589.7-8589.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8412.7-8412.11" + attribute \src "ls180.v:8592.7-8592.11" case assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8416.6-8416.10" + attribute \src "ls180.v:8596.6-8596.10" case - attribute \src "ls180.v:8417.3-8420.6" - switch $and$ls180.v:8417$2689_Y - attribute \src "ls180.v:8417.7-8417.96" + attribute \src "ls180.v:8597.3-8600.6" + switch $and$ls180.v:8597$2822_Y + attribute \src "ls180.v:8597.7-8597.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8418$2690_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8419$2691_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8598$2823_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8599$2824_Y case end end - attribute \src "ls180.v:8422.2-8449.5" + attribute \src "ls180.v:8602.2-8629.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8422.6-8422.47" + attribute \src "ls180.v:8602.6-8602.47" case 1'1 - attribute \src "ls180.v:8423.3-8448.10" + attribute \src "ls180.v:8603.3-8628.10" switch \main_sdphy_dataw_crcr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -278758,16 +297382,16 @@ module \ls180 end case end - attribute \src "ls180.v:8450.2-8452.5" + attribute \src "ls180.v:8630.2-8632.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8450.6-8450.47" + attribute \src "ls180.v:8630.6-8630.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8451$2692_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8631$2825_Y case end - attribute \src "ls180.v:8453.2-8458.5" - switch $or$ls180.v:8453$2694_Y - attribute \src "ls180.v:8453.6-8453.90" + attribute \src "ls180.v:8633.2-8638.5" + switch $or$ls180.v:8633$2827_Y + attribute \src "ls180.v:8633.6-8633.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first @@ -278775,9 +297399,9 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data case end - attribute \src "ls180.v:8459.2-8464.5" + attribute \src "ls180.v:8639.2-8644.5" switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8459.6-8459.33" + attribute \src "ls180.v:8639.6-8639.33" case 1'1 assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 @@ -278785,81 +297409,81 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8466.2-8468.5" + attribute \src "ls180.v:8646.2-8648.5" switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8466.6-8466.63" + attribute \src "ls180.v:8646.6-8646.63" case 1'1 assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value case end - attribute \src "ls180.v:8470.2-8472.5" + attribute \src "ls180.v:8650.2-8652.5" switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8470.6-8470.52" + attribute \src "ls180.v:8650.6-8650.52" case 1'1 assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value case end - attribute \src "ls180.v:8473.2-8475.5" + attribute \src "ls180.v:8653.2-8655.5" switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8473.6-8473.42" + attribute \src "ls180.v:8653.6-8653.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8474$2695_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8654$2828_Y case end - attribute \src "ls180.v:8476.2-8478.5" + attribute \src "ls180.v:8656.2-8658.5" switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8476.6-8476.51" + attribute \src "ls180.v:8656.6-8656.51" case 1'1 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8479.2-8486.5" + attribute \src "ls180.v:8659.2-8666.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8479.6-8479.48" + attribute \src "ls180.v:8659.6-8659.48" case 1'1 - attribute \src "ls180.v:8480.3-8485.6" - switch $or$ls180.v:8480$2697_Y - attribute \src "ls180.v:8480.7-8480.102" + attribute \src "ls180.v:8660.3-8665.6" + switch $or$ls180.v:8660$2830_Y + attribute \src "ls180.v:8660.7-8660.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8483.7-8483.11" + attribute \src "ls180.v:8663.7-8663.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8484$2698_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8664$2831_Y end case end - attribute \src "ls180.v:8487.2-8500.5" - switch $and$ls180.v:8487$2699_Y - attribute \src "ls180.v:8487.6-8487.101" + attribute \src "ls180.v:8667.2-8680.5" + switch $and$ls180.v:8667$2832_Y + attribute \src "ls180.v:8667.6-8667.101" case 1'1 - attribute \src "ls180.v:8488.3-8494.6" - switch $and$ls180.v:8488$2700_Y - attribute \src "ls180.v:8488.7-8488.98" + attribute \src "ls180.v:8668.3-8674.6" + switch $and$ls180.v:8668$2833_Y + attribute \src "ls180.v:8668.7-8668.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8491.7-8491.11" + attribute \src "ls180.v:8671.7-8671.11" case assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8495.6-8495.10" + attribute \src "ls180.v:8675.6-8675.10" case - attribute \src "ls180.v:8496.3-8499.6" - switch $and$ls180.v:8496$2701_Y - attribute \src "ls180.v:8496.7-8496.98" + attribute \src "ls180.v:8676.3-8679.6" + switch $and$ls180.v:8676$2834_Y + attribute \src "ls180.v:8676.7-8676.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8497$2702_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8498$2703_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8677$2835_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8678$2836_Y case end end - attribute \src "ls180.v:8501.2-8510.5" + attribute \src "ls180.v:8681.2-8690.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8501.6-8501.48" + attribute \src "ls180.v:8681.6-8681.48" case 1'1 - attribute \src "ls180.v:8502.3-8509.10" + attribute \src "ls180.v:8682.3-8689.10" switch \main_sdphy_datar_datar_converter_demux attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -278871,16 +297495,16 @@ module \ls180 end case end - attribute \src "ls180.v:8511.2-8513.5" + attribute \src "ls180.v:8691.2-8693.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8511.6-8511.48" + attribute \src "ls180.v:8691.6-8691.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8512$2704_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8692$2837_Y case end - attribute \src "ls180.v:8514.2-8519.5" - switch $or$ls180.v:8514$2706_Y - attribute \src "ls180.v:8514.6-8514.92" + attribute \src "ls180.v:8694.2-8699.5" + switch $or$ls180.v:8694$2839_Y + attribute \src "ls180.v:8694.6-8694.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first @@ -278888,9 +297512,9 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data case end - attribute \src "ls180.v:8520.2-8525.5" + attribute \src "ls180.v:8700.2-8705.5" switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8520.6-8520.34" + attribute \src "ls180.v:8700.6-8700.34" case 1'1 assign $0\main_sdphy_datar_datar_run[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 @@ -278898,598 +297522,610 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8527.2-8529.5" + attribute \src "ls180.v:8707.2-8709.5" switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8527.6-8527.60" + attribute \src "ls180.v:8707.6-8707.60" case 1'1 assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 case end - attribute \src "ls180.v:8530.2-8532.5" + attribute \src "ls180.v:8710.2-8712.5" switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8530.6-8530.62" + attribute \src "ls180.v:8710.6-8710.62" case 1'1 assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 case end - attribute \src "ls180.v:8533.2-8535.5" + attribute \src "ls180.v:8713.2-8715.5" switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8533.6-8533.66" + attribute \src "ls180.v:8713.6-8713.66" case 1'1 assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 case end - attribute \src "ls180.v:8536.2-8542.5" + attribute \src "ls180.v:8716.2-8722.5" switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8536.6-8536.35" + attribute \src "ls180.v:8716.6-8716.35" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8538.6-8538.10" + attribute \src "ls180.v:8718.6-8718.10" case - attribute \src "ls180.v:8539.3-8541.6" + attribute \src "ls180.v:8719.3-8721.6" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8539.7-8539.39" + attribute \src "ls180.v:8719.7-8719.39" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 case end end - attribute \src "ls180.v:8543.2-8549.5" + attribute \src "ls180.v:8723.2-8729.5" switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8543.6-8543.41" + attribute \src "ls180.v:8723.6-8723.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8545.6-8545.10" + attribute \src "ls180.v:8725.6-8725.10" case - attribute \src "ls180.v:8546.3-8548.6" + attribute \src "ls180.v:8726.3-8728.6" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8546.7-8546.45" + attribute \src "ls180.v:8726.7-8726.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 case end end - attribute \src "ls180.v:8550.2-8556.5" + attribute \src "ls180.v:8730.2-8736.5" switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8550.6-8550.41" + attribute \src "ls180.v:8730.6-8730.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8552.6-8552.10" + attribute \src "ls180.v:8732.6-8732.10" case - attribute \src "ls180.v:8553.3-8555.6" + attribute \src "ls180.v:8733.3-8735.6" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8553.7-8553.45" + attribute \src "ls180.v:8733.7-8733.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 case end end - attribute \src "ls180.v:8557.2-8563.5" + attribute \src "ls180.v:8737.2-8743.5" switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8557.6-8557.41" + attribute \src "ls180.v:8737.6-8737.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8559.6-8559.10" + attribute \src "ls180.v:8739.6-8739.10" case - attribute \src "ls180.v:8560.3-8562.6" + attribute \src "ls180.v:8740.3-8742.6" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8560.7-8560.45" + attribute \src "ls180.v:8740.7-8740.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 case end end - attribute \src "ls180.v:8564.2-8570.5" + attribute \src "ls180.v:8744.2-8750.5" switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8564.6-8564.41" + attribute \src "ls180.v:8744.6-8744.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8566.6-8566.10" + attribute \src "ls180.v:8746.6-8746.10" case - attribute \src "ls180.v:8567.3-8569.6" + attribute \src "ls180.v:8747.3-8749.6" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8567.7-8567.45" + attribute \src "ls180.v:8747.7-8747.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 case end end - attribute \src "ls180.v:8572.2-8574.5" + attribute \src "ls180.v:8752.2-8754.5" switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8572.6-8572.82" + attribute \src "ls180.v:8752.6-8752.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 case end - attribute \src "ls180.v:8575.2-8577.5" + attribute \src "ls180.v:8755.2-8757.5" switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8575.6-8575.82" + attribute \src "ls180.v:8755.6-8755.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 case end - attribute \src "ls180.v:8578.2-8580.5" + attribute \src "ls180.v:8758.2-8760.5" switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8578.6-8578.82" + attribute \src "ls180.v:8758.6-8758.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 case end - attribute \src "ls180.v:8581.2-8583.5" + attribute \src "ls180.v:8761.2-8763.5" switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8581.6-8581.82" + attribute \src "ls180.v:8761.6-8761.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 case end - attribute \src "ls180.v:8584.2-8586.5" + attribute \src "ls180.v:8764.2-8766.5" switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8584.6-8584.78" + attribute \src "ls180.v:8764.6-8764.78" case 1'1 assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 case end - attribute \src "ls180.v:8587.2-8589.5" - switch $and$ls180.v:8587$2707_Y - attribute \src "ls180.v:8587.6-8587.83" + attribute \src "ls180.v:8767.2-8769.5" + switch $and$ls180.v:8767$2840_Y + attribute \src "ls180.v:8767.6-8767.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end - attribute \src "ls180.v:8590.2-8592.5" - switch $and$ls180.v:8590$2708_Y - attribute \src "ls180.v:8590.6-8590.83" + attribute \src "ls180.v:8770.2-8772.5" + switch $and$ls180.v:8770$2841_Y + attribute \src "ls180.v:8770.6-8770.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end - attribute \src "ls180.v:8593.2-8595.5" - switch $and$ls180.v:8593$2709_Y - attribute \src "ls180.v:8593.6-8593.83" + attribute \src "ls180.v:8773.2-8775.5" + switch $and$ls180.v:8773$2842_Y + attribute \src "ls180.v:8773.6-8773.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end - attribute \src "ls180.v:8596.2-8598.5" - switch $and$ls180.v:8596$2710_Y - attribute \src "ls180.v:8596.6-8596.83" + attribute \src "ls180.v:8776.2-8778.5" + switch $and$ls180.v:8776$2843_Y + attribute \src "ls180.v:8776.6-8776.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc case end - attribute \src "ls180.v:8599.2-8603.5" - switch $and$ls180.v:8599$2711_Y - attribute \src "ls180.v:8599.6-8599.83" + attribute \src "ls180.v:8779.2-8783.5" + switch $and$ls180.v:8779$2844_Y + attribute \src "ls180.v:8779.6-8779.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] case end - attribute \src "ls180.v:8604.2-8608.5" - switch $and$ls180.v:8604$2712_Y - attribute \src "ls180.v:8604.6-8604.83" + attribute \src "ls180.v:8784.2-8788.5" + switch $and$ls180.v:8784$2845_Y + attribute \src "ls180.v:8784.6-8784.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] case end - attribute \src "ls180.v:8609.2-8613.5" - switch $and$ls180.v:8609$2713_Y - attribute \src "ls180.v:8609.6-8609.83" + attribute \src "ls180.v:8789.2-8793.5" + switch $and$ls180.v:8789$2846_Y + attribute \src "ls180.v:8789.6-8789.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] case end - attribute \src "ls180.v:8614.2-8618.5" - switch $and$ls180.v:8614$2714_Y - attribute \src "ls180.v:8614.6-8614.83" + attribute \src "ls180.v:8794.2-8798.5" + switch $and$ls180.v:8794$2847_Y + attribute \src "ls180.v:8794.6-8794.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] case end - attribute \src "ls180.v:8619.2-8627.5" - switch $and$ls180.v:8619$2715_Y - attribute \src "ls180.v:8619.6-8619.83" + attribute \src "ls180.v:8799.2-8807.5" + switch $and$ls180.v:8799$2848_Y + attribute \src "ls180.v:8799.6-8799.83" case 1'1 - attribute \src "ls180.v:8620.3-8626.6" + attribute \src "ls180.v:8800.3-8806.6" switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8620.7-8620.42" + attribute \src "ls180.v:8800.7-8800.42" case 1'1 assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8622.7-8622.11" + attribute \src "ls180.v:8802.7-8802.11" case - attribute \src "ls180.v:8623.4-8625.7" - switch $ne$ls180.v:8623$2716_Y - attribute \src "ls180.v:8623.8-8623.48" + attribute \src "ls180.v:8803.4-8805.7" + switch $ne$ls180.v:8803$2849_Y + attribute \src "ls180.v:8803.8-8803.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8624$2717_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8804$2850_Y case end end case end - attribute \src "ls180.v:8628.2-8634.5" + attribute \src "ls180.v:8808.2-8814.5" switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8628.6-8628.40" + attribute \src "ls180.v:8808.6-8808.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8630.6-8630.10" + attribute \src "ls180.v:8810.6-8810.10" case - attribute \src "ls180.v:8631.3-8633.6" + attribute \src "ls180.v:8811.3-8813.6" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8631.7-8631.44" + attribute \src "ls180.v:8811.7-8811.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 case end end - attribute \src "ls180.v:8635.2-8641.5" + attribute \src "ls180.v:8815.2-8821.5" switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8635.6-8635.40" + attribute \src "ls180.v:8815.6-8815.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8637.6-8637.10" + attribute \src "ls180.v:8817.6-8817.10" case - attribute \src "ls180.v:8638.3-8640.6" + attribute \src "ls180.v:8818.3-8820.6" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8638.7-8638.44" + attribute \src "ls180.v:8818.7-8818.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 case end end - attribute \src "ls180.v:8642.2-8648.5" + attribute \src "ls180.v:8822.2-8828.5" switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8642.6-8642.40" + attribute \src "ls180.v:8822.6-8822.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8644.6-8644.10" + attribute \src "ls180.v:8824.6-8824.10" case - attribute \src "ls180.v:8645.3-8647.6" + attribute \src "ls180.v:8825.3-8827.6" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8645.7-8645.44" + attribute \src "ls180.v:8825.7-8825.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 case end end - attribute \src "ls180.v:8649.2-8655.5" + attribute \src "ls180.v:8829.2-8835.5" switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8649.6-8649.40" + attribute \src "ls180.v:8829.6-8829.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8651.6-8651.10" + attribute \src "ls180.v:8831.6-8831.10" case - attribute \src "ls180.v:8652.3-8654.6" + attribute \src "ls180.v:8832.3-8834.6" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8652.7-8652.44" + attribute \src "ls180.v:8832.7-8832.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 case end end - attribute \src "ls180.v:8657.2-8659.5" + attribute \src "ls180.v:8837.2-8839.5" switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8657.6-8657.52" + attribute \src "ls180.v:8837.6-8837.52" case 1'1 assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 case end - attribute \src "ls180.v:8660.2-8662.5" + attribute \src "ls180.v:8840.2-8842.5" switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8660.6-8660.53" + attribute \src "ls180.v:8840.6-8840.53" case 1'1 assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 case end - attribute \src "ls180.v:8663.2-8665.5" + attribute \src "ls180.v:8843.2-8845.5" switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8663.6-8663.53" + attribute \src "ls180.v:8843.6-8843.53" case 1'1 assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 case end - attribute \src "ls180.v:8666.2-8668.5" + attribute \src "ls180.v:8846.2-8848.5" switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8666.6-8666.54" + attribute \src "ls180.v:8846.6-8846.54" case 1'1 assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 case end - attribute \src "ls180.v:8669.2-8671.5" + attribute \src "ls180.v:8849.2-8851.5" switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8669.6-8669.53" + attribute \src "ls180.v:8849.6-8849.53" case 1'1 assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 case end - attribute \src "ls180.v:8672.2-8674.5" + attribute \src "ls180.v:8852.2-8854.5" switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8672.6-8672.55" + attribute \src "ls180.v:8852.6-8852.55" case 1'1 assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 case end - attribute \src "ls180.v:8675.2-8677.5" + attribute \src "ls180.v:8855.2-8857.5" switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8675.6-8675.54" + attribute \src "ls180.v:8855.6-8855.54" case 1'1 assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 case end - attribute \src "ls180.v:8678.2-8680.5" + attribute \src "ls180.v:8858.2-8860.5" switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8678.6-8678.56" + attribute \src "ls180.v:8858.6-8858.56" case 1'1 assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 case end - attribute \src "ls180.v:8681.2-8683.5" + attribute \src "ls180.v:8861.2-8863.5" switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8681.6-8681.63" + attribute \src "ls180.v:8861.6-8861.63" case 1'1 assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 case end - attribute \src "ls180.v:8684.2-8686.5" - switch $and$ls180.v:8684$2720_Y - attribute \src "ls180.v:8684.6-8684.120" + attribute \src "ls180.v:8864.2-8866.5" + switch $and$ls180.v:8864$2853_Y + attribute \src "ls180.v:8864.6-8864.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8685$2721_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8865$2854_Y case end - attribute \src "ls180.v:8687.2-8689.5" + attribute \src "ls180.v:8867.2-8869.5" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8687.6-8687.35" + attribute \src "ls180.v:8867.6-8867.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8688$2722_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8868$2855_Y case end - attribute \src "ls180.v:8690.2-8698.5" - switch $and$ls180.v:8690$2725_Y - attribute \src "ls180.v:8690.6-8690.120" + attribute \src "ls180.v:8870.2-8878.5" + switch $and$ls180.v:8870$2858_Y + attribute \src "ls180.v:8870.6-8870.120" case 1'1 - attribute \src "ls180.v:8691.3-8693.6" - switch $not$ls180.v:8691$2726_Y - attribute \src "ls180.v:8691.7-8691.39" + attribute \src "ls180.v:8871.3-8873.6" + switch $not$ls180.v:8871$2859_Y + attribute \src "ls180.v:8871.7-8871.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8692$2727_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8872$2860_Y case end - attribute \src "ls180.v:8694.6-8694.10" + attribute \src "ls180.v:8874.6-8874.10" case - attribute \src "ls180.v:8695.3-8697.6" + attribute \src "ls180.v:8875.3-8877.6" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8695.7-8695.36" + attribute \src "ls180.v:8875.7-8875.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8696$2728_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8876$2861_Y case end end - attribute \src "ls180.v:8699.2-8701.5" + attribute \src "ls180.v:8879.2-8881.5" switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8699.6-8699.45" + attribute \src "ls180.v:8879.6-8879.45" case 1'1 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8702.2-8709.5" + attribute \src "ls180.v:8882.2-8889.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8702.6-8702.42" + attribute \src "ls180.v:8882.6-8882.42" case 1'1 - attribute \src "ls180.v:8703.3-8708.6" - switch $or$ls180.v:8703$2730_Y - attribute \src "ls180.v:8703.7-8703.90" + attribute \src "ls180.v:8883.3-8888.6" + switch $or$ls180.v:8883$2863_Y + attribute \src "ls180.v:8883.7-8883.90" case 1'1 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8706.7-8706.11" + attribute \src "ls180.v:8886.7-8886.11" case - assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8707$2731_Y + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8887$2864_Y end case end - attribute \src "ls180.v:8710.2-8723.5" - switch $and$ls180.v:8710$2732_Y - attribute \src "ls180.v:8710.6-8710.89" + attribute \src "ls180.v:8890.2-8903.5" + switch $and$ls180.v:8890$2865_Y + attribute \src "ls180.v:8890.6-8890.89" case 1'1 - attribute \src "ls180.v:8711.3-8717.6" - switch $and$ls180.v:8711$2733_Y - attribute \src "ls180.v:8711.7-8711.86" + attribute \src "ls180.v:8891.3-8897.6" + switch $and$ls180.v:8891$2866_Y + attribute \src "ls180.v:8891.7-8891.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8714.7-8714.11" + attribute \src "ls180.v:8894.7-8894.11" case assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8718.6-8718.10" + attribute \src "ls180.v:8898.6-8898.10" case - attribute \src "ls180.v:8719.3-8722.6" - switch $and$ls180.v:8719$2734_Y - attribute \src "ls180.v:8719.7-8719.86" + attribute \src "ls180.v:8899.3-8902.6" + switch $and$ls180.v:8899$2867_Y + attribute \src "ls180.v:8899.7-8899.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8720$2735_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8721$2736_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8900$2868_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8901$2869_Y case end end - attribute \src "ls180.v:8724.2-8739.5" + attribute \src "ls180.v:8904.2-8931.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8724.6-8724.42" + attribute \src "ls180.v:8904.6-8904.42" case 1'1 - attribute \src "ls180.v:8725.3-8738.10" + attribute \src "ls180.v:8905.3-8930.10" switch \main_sdblock2mem_converter_demux attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + case 3'000 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + case 3'001 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + case 3'010 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case 3'011 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data case end case end - attribute \src "ls180.v:8740.2-8742.5" + attribute \src "ls180.v:8932.2-8934.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8740.6-8740.42" + attribute \src "ls180.v:8932.6-8932.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8741$2737_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8933$2870_Y case end - attribute \src "ls180.v:8744.2-8746.5" + attribute \src "ls180.v:8936.2-8938.5" switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8744.6-8744.76" + attribute \src "ls180.v:8936.6-8936.76" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value case end - attribute \src "ls180.v:8747.2-8750.5" + attribute \src "ls180.v:8939.2-8942.5" switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8747.6-8747.46" + attribute \src "ls180.v:8939.6-8939.46" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 assign $0\builder_sdblock2memdma_state[1:0] 2'00 case end - attribute \src "ls180.v:8752.2-8754.5" + attribute \src "ls180.v:8944.2-8946.5" switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8752.6-8752.64" + attribute \src "ls180.v:8944.6-8944.64" case 1'1 - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value case end - attribute \src "ls180.v:8756.2-8758.5" + attribute \src "ls180.v:8948.2-8950.5" switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8756.6-8756.76" + attribute \src "ls180.v:8948.6-8948.76" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value case end - attribute \src "ls180.v:8759.2-8762.5" + attribute \src "ls180.v:8951.2-8954.5" switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8759.6-8759.32" + attribute \src "ls180.v:8951.6-8951.32" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 case end - attribute \src "ls180.v:8763.2-8769.5" - switch $and$ls180.v:8763$2738_Y - attribute \src "ls180.v:8763.6-8763.89" + attribute \src "ls180.v:8955.2-8961.5" + switch $and$ls180.v:8955$2871_Y + attribute \src "ls180.v:8955.6-8955.89" case 1'1 - attribute \src "ls180.v:8764.3-8768.6" + attribute \src "ls180.v:8956.3-8960.6" switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8764.7-8764.38" + attribute \src "ls180.v:8956.7-8956.38" case 1'1 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - attribute \src "ls180.v:8766.7-8766.11" + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + attribute \src "ls180.v:8958.7-8958.11" case - assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8767$2739_Y + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8959$2872_Y end case end - attribute \src "ls180.v:8770.2-8772.5" - switch $and$ls180.v:8770$2742_Y - attribute \src "ls180.v:8770.6-8770.120" + attribute \src "ls180.v:8962.2-8964.5" + switch $and$ls180.v:8962$2875_Y + attribute \src "ls180.v:8962.6-8962.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8771$2743_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8963$2876_Y case end - attribute \src "ls180.v:8773.2-8775.5" + attribute \src "ls180.v:8965.2-8967.5" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8773.6-8773.35" + attribute \src "ls180.v:8965.6-8965.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8774$2744_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8966$2877_Y case end - attribute \src "ls180.v:8776.2-8784.5" - switch $and$ls180.v:8776$2747_Y - attribute \src "ls180.v:8776.6-8776.120" + attribute \src "ls180.v:8968.2-8976.5" + switch $and$ls180.v:8968$2880_Y + attribute \src "ls180.v:8968.6-8968.120" case 1'1 - attribute \src "ls180.v:8777.3-8779.6" - switch $not$ls180.v:8777$2748_Y - attribute \src "ls180.v:8777.7-8777.39" + attribute \src "ls180.v:8969.3-8971.6" + switch $not$ls180.v:8969$2881_Y + attribute \src "ls180.v:8969.7-8969.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8778$2749_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8970$2882_Y case end - attribute \src "ls180.v:8780.6-8780.10" + attribute \src "ls180.v:8972.6-8972.10" case - attribute \src "ls180.v:8781.3-8783.6" + attribute \src "ls180.v:8973.3-8975.6" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8781.7-8781.36" + attribute \src "ls180.v:8973.7-8973.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8782$2750_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8974$2883_Y case end end - attribute \src "ls180.v:8786.2-8788.5" + attribute \src "ls180.v:8978.2-8980.5" switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8786.6-8786.46" + attribute \src "ls180.v:8978.6-8978.46" case 1'1 assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 case end - attribute \src "ls180.v:8789.2-8791.5" + attribute \src "ls180.v:8981.2-8983.5" switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8789.6-8789.44" + attribute \src "ls180.v:8981.6-8981.44" case 1'1 assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 case end - attribute \src "ls180.v:8792.2-8794.5" + attribute \src "ls180.v:8984.2-8986.5" switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8792.6-8792.43" + attribute \src "ls180.v:8984.6-8984.43" case 1'1 assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 case end - attribute \src "ls180.v:8795.2-8891.9" + attribute \src "ls180.v:8987.2-9083.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - attribute \src "ls180.v:8797.4-8813.7" - switch $not$ls180.v:8797$2751_Y - attribute \src "ls180.v:8797.8-8797.29" + attribute \src "ls180.v:8989.4-9005.7" + switch $not$ls180.v:8989$2884_Y + attribute \src "ls180.v:8989.8-8989.29" case 1'1 - attribute \src "ls180.v:8798.5-8812.8" + attribute \src "ls180.v:8990.5-9004.8" switch \builder_request [1] - attribute \src "ls180.v:8798.9-8798.27" + attribute \src "ls180.v:8990.9-8990.27" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8800.9-8800.13" + attribute \src "ls180.v:8992.9-8992.13" case - attribute \src "ls180.v:8801.6-8811.9" + attribute \src "ls180.v:8993.6-9003.9" switch \builder_request [2] - attribute \src "ls180.v:8801.10-8801.28" + attribute \src "ls180.v:8993.10-8993.28" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8803.10-8803.14" + attribute \src "ls180.v:8995.10-8995.14" case - attribute \src "ls180.v:8804.7-8810.10" + attribute \src "ls180.v:8996.7-9002.10" switch \builder_request [3] - attribute \src "ls180.v:8804.11-8804.29" + attribute \src "ls180.v:8996.11-8996.29" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8806.11-8806.15" + attribute \src "ls180.v:8998.11-8998.15" case - attribute \src "ls180.v:8807.8-8809.11" + attribute \src "ls180.v:8999.8-9001.11" switch \builder_request [4] - attribute \src "ls180.v:8807.12-8807.30" + attribute \src "ls180.v:8999.12-8999.30" case 1'1 assign $0\builder_grant[2:0] 3'100 case @@ -279501,34 +298137,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'001 - attribute \src "ls180.v:8816.4-8832.7" - switch $not$ls180.v:8816$2752_Y - attribute \src "ls180.v:8816.8-8816.29" + attribute \src "ls180.v:9008.4-9024.7" + switch $not$ls180.v:9008$2885_Y + attribute \src "ls180.v:9008.8-9008.29" case 1'1 - attribute \src "ls180.v:8817.5-8831.8" + attribute \src "ls180.v:9009.5-9023.8" switch \builder_request [2] - attribute \src "ls180.v:8817.9-8817.27" + attribute \src "ls180.v:9009.9-9009.27" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8819.9-8819.13" + attribute \src "ls180.v:9011.9-9011.13" case - attribute \src "ls180.v:8820.6-8830.9" + attribute \src "ls180.v:9012.6-9022.9" switch \builder_request [3] - attribute \src "ls180.v:8820.10-8820.28" + attribute \src "ls180.v:9012.10-9012.28" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8822.10-8822.14" + attribute \src "ls180.v:9014.10-9014.14" case - attribute \src "ls180.v:8823.7-8829.10" + attribute \src "ls180.v:9015.7-9021.10" switch \builder_request [4] - attribute \src "ls180.v:8823.11-8823.29" + attribute \src "ls180.v:9015.11-9015.29" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8825.11-8825.15" + attribute \src "ls180.v:9017.11-9017.15" case - attribute \src "ls180.v:8826.8-8828.11" + attribute \src "ls180.v:9018.8-9020.11" switch \builder_request [0] - attribute \src "ls180.v:8826.12-8826.30" + attribute \src "ls180.v:9018.12-9018.30" case 1'1 assign $0\builder_grant[2:0] 3'000 case @@ -279540,34 +298176,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'010 - attribute \src "ls180.v:8835.4-8851.7" - switch $not$ls180.v:8835$2753_Y - attribute \src "ls180.v:8835.8-8835.29" + attribute \src "ls180.v:9027.4-9043.7" + switch $not$ls180.v:9027$2886_Y + attribute \src "ls180.v:9027.8-9027.29" case 1'1 - attribute \src "ls180.v:8836.5-8850.8" + attribute \src "ls180.v:9028.5-9042.8" switch \builder_request [3] - attribute \src "ls180.v:8836.9-8836.27" + attribute \src "ls180.v:9028.9-9028.27" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8838.9-8838.13" + attribute \src "ls180.v:9030.9-9030.13" case - attribute \src "ls180.v:8839.6-8849.9" + attribute \src "ls180.v:9031.6-9041.9" switch \builder_request [4] - attribute \src "ls180.v:8839.10-8839.28" + attribute \src "ls180.v:9031.10-9031.28" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8841.10-8841.14" + attribute \src "ls180.v:9033.10-9033.14" case - attribute \src "ls180.v:8842.7-8848.10" + attribute \src "ls180.v:9034.7-9040.10" switch \builder_request [0] - attribute \src "ls180.v:8842.11-8842.29" + attribute \src "ls180.v:9034.11-9034.29" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8844.11-8844.15" + attribute \src "ls180.v:9036.11-9036.15" case - attribute \src "ls180.v:8845.8-8847.11" + attribute \src "ls180.v:9037.8-9039.11" switch \builder_request [1] - attribute \src "ls180.v:8845.12-8845.30" + attribute \src "ls180.v:9037.12-9037.30" case 1'1 assign $0\builder_grant[2:0] 3'001 case @@ -279579,34 +298215,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:8854.4-8870.7" - switch $not$ls180.v:8854$2754_Y - attribute \src "ls180.v:8854.8-8854.29" + attribute \src "ls180.v:9046.4-9062.7" + switch $not$ls180.v:9046$2887_Y + attribute \src "ls180.v:9046.8-9046.29" case 1'1 - attribute \src "ls180.v:8855.5-8869.8" + attribute \src "ls180.v:9047.5-9061.8" switch \builder_request [4] - attribute \src "ls180.v:8855.9-8855.27" + attribute \src "ls180.v:9047.9-9047.27" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8857.9-8857.13" + attribute \src "ls180.v:9049.9-9049.13" case - attribute \src "ls180.v:8858.6-8868.9" + attribute \src "ls180.v:9050.6-9060.9" switch \builder_request [0] - attribute \src "ls180.v:8858.10-8858.28" + attribute \src "ls180.v:9050.10-9050.28" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8860.10-8860.14" + attribute \src "ls180.v:9052.10-9052.14" case - attribute \src "ls180.v:8861.7-8867.10" + attribute \src "ls180.v:9053.7-9059.10" switch \builder_request [1] - attribute \src "ls180.v:8861.11-8861.29" + attribute \src "ls180.v:9053.11-9053.29" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8863.11-8863.15" + attribute \src "ls180.v:9055.11-9055.15" case - attribute \src "ls180.v:8864.8-8866.11" + attribute \src "ls180.v:9056.8-9058.11" switch \builder_request [2] - attribute \src "ls180.v:8864.12-8864.30" + attribute \src "ls180.v:9056.12-9056.30" case 1'1 assign $0\builder_grant[2:0] 3'010 case @@ -279618,34 +298254,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'100 - attribute \src "ls180.v:8873.4-8889.7" - switch $not$ls180.v:8873$2755_Y - attribute \src "ls180.v:8873.8-8873.29" + attribute \src "ls180.v:9065.4-9081.7" + switch $not$ls180.v:9065$2888_Y + attribute \src "ls180.v:9065.8-9065.29" case 1'1 - attribute \src "ls180.v:8874.5-8888.8" + attribute \src "ls180.v:9066.5-9080.8" switch \builder_request [0] - attribute \src "ls180.v:8874.9-8874.27" + attribute \src "ls180.v:9066.9-9066.27" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8876.9-8876.13" + attribute \src "ls180.v:9068.9-9068.13" case - attribute \src "ls180.v:8877.6-8887.9" + attribute \src "ls180.v:9069.6-9079.9" switch \builder_request [1] - attribute \src "ls180.v:8877.10-8877.28" + attribute \src "ls180.v:9069.10-9069.28" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8879.10-8879.14" + attribute \src "ls180.v:9071.10-9071.14" case - attribute \src "ls180.v:8880.7-8886.10" + attribute \src "ls180.v:9072.7-9078.10" switch \builder_request [2] - attribute \src "ls180.v:8880.11-8880.29" + attribute \src "ls180.v:9072.11-9072.29" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8882.11-8882.15" + attribute \src "ls180.v:9074.11-9074.15" case - attribute \src "ls180.v:8883.8-8885.11" + attribute \src "ls180.v:9075.8-9077.11" switch \builder_request [3] - attribute \src "ls180.v:8883.12-8883.30" + attribute \src "ls180.v:9075.12-9075.30" case 1'1 assign $0\builder_grant[2:0] 3'011 case @@ -279657,26 +298293,26 @@ module \ls180 end case end - attribute \src "ls180.v:8893.2-8899.5" + attribute \src "ls180.v:9085.2-9091.5" switch \builder_wait - attribute \src "ls180.v:8893.6-8893.18" + attribute \src "ls180.v:9085.6-9085.18" case 1'1 - attribute \src "ls180.v:8894.3-8896.6" - switch $not$ls180.v:8894$2756_Y - attribute \src "ls180.v:8894.7-8894.22" + attribute \src "ls180.v:9086.3-9088.6" + switch $not$ls180.v:9086$2889_Y + attribute \src "ls180.v:9086.7-9086.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8895$2757_Y + assign $0\builder_count[19:0] $sub$ls180.v:9087$2890_Y case end - attribute \src "ls180.v:8897.6-8897.10" + attribute \src "ls180.v:9089.6-9089.10" case assign $0\builder_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:8901.2-8931.5" + attribute \src "ls180.v:9093.2-9123.5" switch \builder_csrbank0_sel - attribute \src "ls180.v:8901.6-8901.26" + attribute \src "ls180.v:9093.6-9093.26" case 1'1 - attribute \src "ls180.v:8902.3-8930.10" + attribute \src "ls180.v:9094.3-9122.10" switch \builder_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -279709,46 +298345,46 @@ module \ls180 end case end - attribute \src "ls180.v:8932.2-8934.5" + attribute \src "ls180.v:9124.2-9126.5" switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8932.6-8932.32" + attribute \src "ls180.v:9124.6-9124.32" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r case end - attribute \src "ls180.v:8936.2-8938.5" + attribute \src "ls180.v:9128.2-9130.5" switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8936.6-8936.34" + attribute \src "ls180.v:9128.6-9128.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r case end - attribute \src "ls180.v:8939.2-8941.5" + attribute \src "ls180.v:9131.2-9133.5" switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8939.6-8939.34" + attribute \src "ls180.v:9131.6-9131.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r case end - attribute \src "ls180.v:8942.2-8944.5" + attribute \src "ls180.v:9134.2-9136.5" switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8942.6-8942.34" + attribute \src "ls180.v:9134.6-9134.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r case end - attribute \src "ls180.v:8945.2-8947.5" + attribute \src "ls180.v:9137.2-9139.5" switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8945.6-8945.34" + attribute \src "ls180.v:9137.6-9137.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r case end - attribute \src "ls180.v:8950.2-8971.5" + attribute \src "ls180.v:9142.2-9163.5" switch \builder_csrbank1_sel - attribute \src "ls180.v:8950.6-8950.26" + attribute \src "ls180.v:9142.6-9142.26" case 1'1 - attribute \src "ls180.v:8951.3-8970.10" + attribute \src "ls180.v:9143.3-9162.10" switch \builder_interface1_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -279772,39 +298408,39 @@ module \ls180 end case end - attribute \src "ls180.v:8972.2-8974.5" + attribute \src "ls180.v:9164.2-9166.5" switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:8972.6-8972.29" + attribute \src "ls180.v:9164.6-9164.29" case 1'1 - assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r case end - attribute \src "ls180.v:8975.2-8977.5" + attribute \src "ls180.v:9167.2-9169.5" switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:8975.6-8975.29" + attribute \src "ls180.v:9167.6-9167.29" case 1'1 - assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r case end - attribute \src "ls180.v:8979.2-8981.5" + attribute \src "ls180.v:9171.2-9173.5" switch \builder_csrbank1_out1_re - attribute \src "ls180.v:8979.6-8979.30" + attribute \src "ls180.v:9171.6-9171.30" case 1'1 - assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r case end - attribute \src "ls180.v:8982.2-8984.5" + attribute \src "ls180.v:9174.2-9176.5" switch \builder_csrbank1_out0_re - attribute \src "ls180.v:8982.6-8982.30" + attribute \src "ls180.v:9174.6-9174.30" case 1'1 - assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r case end - attribute \src "ls180.v:8987.2-8996.5" + attribute \src "ls180.v:9179.2-9188.5" switch \builder_csrbank2_sel - attribute \src "ls180.v:8987.6-8987.26" + attribute \src "ls180.v:9179.6-9179.26" case 1'1 - attribute \src "ls180.v:8988.3-8995.10" + attribute \src "ls180.v:9180.3-9187.10" switch \builder_interface2_bank_bus_adr [0] attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -279816,18 +298452,18 @@ module \ls180 end case end - attribute \src "ls180.v:8997.2-8999.5" + attribute \src "ls180.v:9189.2-9191.5" switch \builder_csrbank2_w0_re - attribute \src "ls180.v:8997.6-8997.28" + attribute \src "ls180.v:9189.6-9189.28" case 1'1 assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r case end - attribute \src "ls180.v:9002.2-9032.5" + attribute \src "ls180.v:9194.2-9224.5" switch \builder_csrbank3_sel - attribute \src "ls180.v:9002.6-9002.26" + attribute \src "ls180.v:9194.6-9194.26" case 1'1 - attribute \src "ls180.v:9003.3-9031.10" + attribute \src "ls180.v:9195.3-9223.10" switch \builder_interface3_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -279860,74 +298496,74 @@ module \ls180 end case end - attribute \src "ls180.v:9033.2-9035.5" + attribute \src "ls180.v:9225.2-9227.5" switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:9033.6-9033.33" + attribute \src "ls180.v:9225.6-9225.33" case 1'1 assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r case end - attribute \src "ls180.v:9037.2-9039.5" + attribute \src "ls180.v:9229.2-9231.5" switch \builder_csrbank3_width3_re - attribute \src "ls180.v:9037.6-9037.32" + attribute \src "ls180.v:9229.6-9229.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r case end - attribute \src "ls180.v:9040.2-9042.5" + attribute \src "ls180.v:9232.2-9234.5" switch \builder_csrbank3_width2_re - attribute \src "ls180.v:9040.6-9040.32" + attribute \src "ls180.v:9232.6-9232.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r case end - attribute \src "ls180.v:9043.2-9045.5" + attribute \src "ls180.v:9235.2-9237.5" switch \builder_csrbank3_width1_re - attribute \src "ls180.v:9043.6-9043.32" + attribute \src "ls180.v:9235.6-9235.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r case end - attribute \src "ls180.v:9046.2-9048.5" + attribute \src "ls180.v:9238.2-9240.5" switch \builder_csrbank3_width0_re - attribute \src "ls180.v:9046.6-9046.32" + attribute \src "ls180.v:9238.6-9238.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r case end - attribute \src "ls180.v:9050.2-9052.5" + attribute \src "ls180.v:9242.2-9244.5" switch \builder_csrbank3_period3_re - attribute \src "ls180.v:9050.6-9050.33" + attribute \src "ls180.v:9242.6-9242.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r case end - attribute \src "ls180.v:9053.2-9055.5" + attribute \src "ls180.v:9245.2-9247.5" switch \builder_csrbank3_period2_re - attribute \src "ls180.v:9053.6-9053.33" + attribute \src "ls180.v:9245.6-9245.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r case end - attribute \src "ls180.v:9056.2-9058.5" + attribute \src "ls180.v:9248.2-9250.5" switch \builder_csrbank3_period1_re - attribute \src "ls180.v:9056.6-9056.33" + attribute \src "ls180.v:9248.6-9248.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r case end - attribute \src "ls180.v:9059.2-9061.5" + attribute \src "ls180.v:9251.2-9253.5" switch \builder_csrbank3_period0_re - attribute \src "ls180.v:9059.6-9059.33" + attribute \src "ls180.v:9251.6-9251.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r case end - attribute \src "ls180.v:9064.2-9094.5" + attribute \src "ls180.v:9256.2-9286.5" switch \builder_csrbank4_sel - attribute \src "ls180.v:9064.6-9064.26" + attribute \src "ls180.v:9256.6-9256.26" case 1'1 - attribute \src "ls180.v:9065.3-9093.10" + attribute \src "ls180.v:9257.3-9285.10" switch \builder_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -279960,74 +298596,74 @@ module \ls180 end case end - attribute \src "ls180.v:9095.2-9097.5" + attribute \src "ls180.v:9287.2-9289.5" switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:9095.6-9095.33" + attribute \src "ls180.v:9287.6-9287.33" case 1'1 assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r case end - attribute \src "ls180.v:9099.2-9101.5" + attribute \src "ls180.v:9291.2-9293.5" switch \builder_csrbank4_width3_re - attribute \src "ls180.v:9099.6-9099.32" + attribute \src "ls180.v:9291.6-9291.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r case end - attribute \src "ls180.v:9102.2-9104.5" + attribute \src "ls180.v:9294.2-9296.5" switch \builder_csrbank4_width2_re - attribute \src "ls180.v:9102.6-9102.32" + attribute \src "ls180.v:9294.6-9294.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r case end - attribute \src "ls180.v:9105.2-9107.5" + attribute \src "ls180.v:9297.2-9299.5" switch \builder_csrbank4_width1_re - attribute \src "ls180.v:9105.6-9105.32" + attribute \src "ls180.v:9297.6-9297.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r case end - attribute \src "ls180.v:9108.2-9110.5" + attribute \src "ls180.v:9300.2-9302.5" switch \builder_csrbank4_width0_re - attribute \src "ls180.v:9108.6-9108.32" + attribute \src "ls180.v:9300.6-9300.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r case end - attribute \src "ls180.v:9112.2-9114.5" + attribute \src "ls180.v:9304.2-9306.5" switch \builder_csrbank4_period3_re - attribute \src "ls180.v:9112.6-9112.33" + attribute \src "ls180.v:9304.6-9304.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r case end - attribute \src "ls180.v:9115.2-9117.5" + attribute \src "ls180.v:9307.2-9309.5" switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9115.6-9115.33" + attribute \src "ls180.v:9307.6-9307.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r case end - attribute \src "ls180.v:9118.2-9120.5" + attribute \src "ls180.v:9310.2-9312.5" switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9118.6-9118.33" + attribute \src "ls180.v:9310.6-9310.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r case end - attribute \src "ls180.v:9121.2-9123.5" + attribute \src "ls180.v:9313.2-9315.5" switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9121.6-9121.33" + attribute \src "ls180.v:9313.6-9313.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r case end - attribute \src "ls180.v:9126.2-9174.5" + attribute \src "ls180.v:9318.2-9366.5" switch \builder_csrbank5_sel - attribute \src "ls180.v:9126.6-9126.26" + attribute \src "ls180.v:9318.6-9318.26" case 1'1 - attribute \src "ls180.v:9127.3-9173.10" + attribute \src "ls180.v:9319.3-9365.10" switch \builder_interface5_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -280078,109 +298714,109 @@ module \ls180 end case end - attribute \src "ls180.v:9175.2-9177.5" + attribute \src "ls180.v:9367.2-9369.5" switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9175.6-9175.35" + attribute \src "ls180.v:9367.6-9367.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r case end - attribute \src "ls180.v:9178.2-9180.5" + attribute \src "ls180.v:9370.2-9372.5" switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9178.6-9178.35" + attribute \src "ls180.v:9370.6-9370.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r case end - attribute \src "ls180.v:9181.2-9183.5" + attribute \src "ls180.v:9373.2-9375.5" switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9181.6-9181.35" + attribute \src "ls180.v:9373.6-9373.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r case end - attribute \src "ls180.v:9184.2-9186.5" + attribute \src "ls180.v:9376.2-9378.5" switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9184.6-9184.35" + attribute \src "ls180.v:9376.6-9376.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r case end - attribute \src "ls180.v:9187.2-9189.5" + attribute \src "ls180.v:9379.2-9381.5" switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9187.6-9187.35" + attribute \src "ls180.v:9379.6-9379.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r case end - attribute \src "ls180.v:9190.2-9192.5" + attribute \src "ls180.v:9382.2-9384.5" switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9190.6-9190.35" + attribute \src "ls180.v:9382.6-9382.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r case end - attribute \src "ls180.v:9193.2-9195.5" + attribute \src "ls180.v:9385.2-9387.5" switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9193.6-9193.35" + attribute \src "ls180.v:9385.6-9385.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r case end - attribute \src "ls180.v:9196.2-9198.5" + attribute \src "ls180.v:9388.2-9390.5" switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9196.6-9196.35" + attribute \src "ls180.v:9388.6-9388.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r case end - attribute \src "ls180.v:9200.2-9202.5" + attribute \src "ls180.v:9392.2-9394.5" switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9200.6-9200.37" + attribute \src "ls180.v:9392.6-9392.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r case end - attribute \src "ls180.v:9203.2-9205.5" + attribute \src "ls180.v:9395.2-9397.5" switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9203.6-9203.37" + attribute \src "ls180.v:9395.6-9395.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r case end - attribute \src "ls180.v:9206.2-9208.5" + attribute \src "ls180.v:9398.2-9400.5" switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9206.6-9206.37" + attribute \src "ls180.v:9398.6-9398.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r case end - attribute \src "ls180.v:9209.2-9211.5" + attribute \src "ls180.v:9401.2-9403.5" switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9209.6-9209.37" + attribute \src "ls180.v:9401.6-9401.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r case end - attribute \src "ls180.v:9213.2-9215.5" + attribute \src "ls180.v:9405.2-9407.5" switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9213.6-9213.37" + attribute \src "ls180.v:9405.6-9405.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r case end - attribute \src "ls180.v:9217.2-9219.5" + attribute \src "ls180.v:9409.2-9411.5" switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9217.6-9217.35" + attribute \src "ls180.v:9409.6-9409.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r case end - attribute \src "ls180.v:9222.2-9324.5" + attribute \src "ls180.v:9414.2-9516.5" switch \builder_csrbank6_sel - attribute \src "ls180.v:9222.6-9222.26" + attribute \src "ls180.v:9414.6-9414.26" case 1'1 - attribute \src "ls180.v:9223.3-9323.10" + attribute \src "ls180.v:9415.3-9515.10" switch \builder_interface6_bank_bus_adr [5:0] attribute \src "ls180.v:0.0-0.0" case 6'000000 @@ -280285,109 +298921,109 @@ module \ls180 end case end - attribute \src "ls180.v:9325.2-9327.5" + attribute \src "ls180.v:9517.2-9519.5" switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9325.6-9325.39" + attribute \src "ls180.v:9517.6-9517.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r case end - attribute \src "ls180.v:9328.2-9330.5" + attribute \src "ls180.v:9520.2-9522.5" switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9328.6-9328.39" + attribute \src "ls180.v:9520.6-9520.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r case end - attribute \src "ls180.v:9331.2-9333.5" + attribute \src "ls180.v:9523.2-9525.5" switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9331.6-9331.39" + attribute \src "ls180.v:9523.6-9523.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r case end - attribute \src "ls180.v:9334.2-9336.5" + attribute \src "ls180.v:9526.2-9528.5" switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9334.6-9334.39" + attribute \src "ls180.v:9526.6-9526.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r case end - attribute \src "ls180.v:9338.2-9340.5" + attribute \src "ls180.v:9530.2-9532.5" switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9338.6-9338.38" + attribute \src "ls180.v:9530.6-9530.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r case end - attribute \src "ls180.v:9341.2-9343.5" + attribute \src "ls180.v:9533.2-9535.5" switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9341.6-9341.38" + attribute \src "ls180.v:9533.6-9533.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r case end - attribute \src "ls180.v:9344.2-9346.5" + attribute \src "ls180.v:9536.2-9538.5" switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9344.6-9344.38" + attribute \src "ls180.v:9536.6-9536.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r case end - attribute \src "ls180.v:9347.2-9349.5" + attribute \src "ls180.v:9539.2-9541.5" switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9347.6-9347.38" + attribute \src "ls180.v:9539.6-9539.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r case end - attribute \src "ls180.v:9351.2-9353.5" + attribute \src "ls180.v:9543.2-9545.5" switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9351.6-9351.39" + attribute \src "ls180.v:9543.6-9543.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r case end - attribute \src "ls180.v:9354.2-9356.5" + attribute \src "ls180.v:9546.2-9548.5" switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9354.6-9354.39" + attribute \src "ls180.v:9546.6-9546.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r case end - attribute \src "ls180.v:9358.2-9360.5" + attribute \src "ls180.v:9550.2-9552.5" switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9358.6-9358.38" + attribute \src "ls180.v:9550.6-9550.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r case end - attribute \src "ls180.v:9361.2-9363.5" + attribute \src "ls180.v:9553.2-9555.5" switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9361.6-9361.38" + attribute \src "ls180.v:9553.6-9553.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r case end - attribute \src "ls180.v:9364.2-9366.5" + attribute \src "ls180.v:9556.2-9558.5" switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9364.6-9364.38" + attribute \src "ls180.v:9556.6-9556.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r case end - attribute \src "ls180.v:9367.2-9369.5" + attribute \src "ls180.v:9559.2-9561.5" switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9367.6-9367.38" + attribute \src "ls180.v:9559.6-9559.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r case end - attribute \src "ls180.v:9372.2-9432.5" + attribute \src "ls180.v:9564.2-9624.5" switch \builder_csrbank7_sel - attribute \src "ls180.v:9372.6-9372.26" + attribute \src "ls180.v:9564.6-9564.26" case 1'1 - attribute \src "ls180.v:9373.3-9431.10" + attribute \src "ls180.v:9565.3-9623.10" switch \builder_interface7_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -280450,109 +299086,109 @@ module \ls180 end case end - attribute \src "ls180.v:9433.2-9435.5" + attribute \src "ls180.v:9625.2-9627.5" switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9433.6-9433.35" + attribute \src "ls180.v:9625.6-9625.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r case end - attribute \src "ls180.v:9436.2-9438.5" + attribute \src "ls180.v:9628.2-9630.5" switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9436.6-9436.35" + attribute \src "ls180.v:9628.6-9628.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r case end - attribute \src "ls180.v:9439.2-9441.5" + attribute \src "ls180.v:9631.2-9633.5" switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9439.6-9439.35" + attribute \src "ls180.v:9631.6-9631.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r case end - attribute \src "ls180.v:9442.2-9444.5" + attribute \src "ls180.v:9634.2-9636.5" switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9442.6-9442.35" + attribute \src "ls180.v:9634.6-9634.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r case end - attribute \src "ls180.v:9445.2-9447.5" + attribute \src "ls180.v:9637.2-9639.5" switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9445.6-9445.35" + attribute \src "ls180.v:9637.6-9637.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r case end - attribute \src "ls180.v:9448.2-9450.5" + attribute \src "ls180.v:9640.2-9642.5" switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9448.6-9448.35" + attribute \src "ls180.v:9640.6-9640.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r case end - attribute \src "ls180.v:9451.2-9453.5" + attribute \src "ls180.v:9643.2-9645.5" switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9451.6-9451.35" + attribute \src "ls180.v:9643.6-9643.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r case end - attribute \src "ls180.v:9454.2-9456.5" + attribute \src "ls180.v:9646.2-9648.5" switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9454.6-9454.35" + attribute \src "ls180.v:9646.6-9646.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r case end - attribute \src "ls180.v:9458.2-9460.5" + attribute \src "ls180.v:9650.2-9652.5" switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9458.6-9458.37" + attribute \src "ls180.v:9650.6-9650.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r case end - attribute \src "ls180.v:9461.2-9463.5" + attribute \src "ls180.v:9653.2-9655.5" switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9461.6-9461.37" + attribute \src "ls180.v:9653.6-9653.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r case end - attribute \src "ls180.v:9464.2-9466.5" + attribute \src "ls180.v:9656.2-9658.5" switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9464.6-9464.37" + attribute \src "ls180.v:9656.6-9656.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r case end - attribute \src "ls180.v:9467.2-9469.5" + attribute \src "ls180.v:9659.2-9661.5" switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9467.6-9467.37" + attribute \src "ls180.v:9659.6-9659.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r case end - attribute \src "ls180.v:9471.2-9473.5" + attribute \src "ls180.v:9663.2-9665.5" switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9471.6-9471.37" + attribute \src "ls180.v:9663.6-9663.37" case 1'1 assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r case end - attribute \src "ls180.v:9475.2-9477.5" + attribute \src "ls180.v:9667.2-9669.5" switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9475.6-9475.35" + attribute \src "ls180.v:9667.6-9667.35" case 1'1 assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r case end - attribute \src "ls180.v:9480.2-9495.5" + attribute \src "ls180.v:9672.2-9687.5" switch \builder_csrbank8_sel - attribute \src "ls180.v:9480.6-9480.26" + attribute \src "ls180.v:9672.6-9672.26" case 1'1 - attribute \src "ls180.v:9481.3-9494.10" + attribute \src "ls180.v:9673.3-9686.10" switch \builder_interface8_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -280570,25 +299206,25 @@ module \ls180 end case end - attribute \src "ls180.v:9496.2-9498.5" + attribute \src "ls180.v:9688.2-9690.5" switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9496.6-9496.42" + attribute \src "ls180.v:9688.6-9688.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r case end - attribute \src "ls180.v:9499.2-9501.5" + attribute \src "ls180.v:9691.2-9693.5" switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9499.6-9499.42" + attribute \src "ls180.v:9691.6-9691.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r case end - attribute \src "ls180.v:9504.2-9537.5" + attribute \src "ls180.v:9696.2-9729.5" switch \builder_csrbank9_sel - attribute \src "ls180.v:9504.6-9504.26" + attribute \src "ls180.v:9696.6-9696.26" case 1'1 - attribute \src "ls180.v:9505.3-9536.10" + attribute \src "ls180.v:9697.3-9728.10" switch \builder_interface9_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -280624,60 +299260,60 @@ module \ls180 end case end - attribute \src "ls180.v:9538.2-9540.5" + attribute \src "ls180.v:9730.2-9732.5" switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9538.6-9538.39" + attribute \src "ls180.v:9730.6-9730.39" case 1'1 assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r case end - attribute \src "ls180.v:9542.2-9544.5" + attribute \src "ls180.v:9734.2-9736.5" switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9542.6-9542.43" + attribute \src "ls180.v:9734.6-9734.43" case 1'1 assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r case end - attribute \src "ls180.v:9546.2-9548.5" + attribute \src "ls180.v:9738.2-9740.5" switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9546.6-9546.43" + attribute \src "ls180.v:9738.6-9738.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r case end - attribute \src "ls180.v:9549.2-9551.5" + attribute \src "ls180.v:9741.2-9743.5" switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9549.6-9549.43" + attribute \src "ls180.v:9741.6-9741.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r case end - attribute \src "ls180.v:9553.2-9555.5" + attribute \src "ls180.v:9745.2-9747.5" switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9553.6-9553.44" + attribute \src "ls180.v:9745.6-9745.44" case 1'1 assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9557.2-9559.5" + attribute \src "ls180.v:9749.2-9751.5" switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9557.6-9557.42" + attribute \src "ls180.v:9749.6-9749.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9560.2-9562.5" + attribute \src "ls180.v:9752.2-9754.5" switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9560.6-9560.42" + attribute \src "ls180.v:9752.6-9752.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9565.2-9589.5" + attribute \src "ls180.v:9757.2-9781.5" switch \builder_csrbank10_sel - attribute \src "ls180.v:9565.6-9565.27" + attribute \src "ls180.v:9757.6-9757.27" case 1'1 - attribute \src "ls180.v:9566.3-9588.10" + attribute \src "ls180.v:9758.3-9780.10" switch \builder_interface10_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -280704,46 +299340,46 @@ module \ls180 end case end - attribute \src "ls180.v:9590.2-9592.5" + attribute \src "ls180.v:9782.2-9784.5" switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9590.6-9590.35" + attribute \src "ls180.v:9782.6-9782.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r case end - attribute \src "ls180.v:9593.2-9595.5" + attribute \src "ls180.v:9785.2-9787.5" switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9593.6-9593.35" + attribute \src "ls180.v:9785.6-9785.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r case end - attribute \src "ls180.v:9597.2-9599.5" + attribute \src "ls180.v:9789.2-9791.5" switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9597.6-9597.32" + attribute \src "ls180.v:9789.6-9789.32" case 1'1 assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r case end - attribute \src "ls180.v:9601.2-9603.5" + attribute \src "ls180.v:9793.2-9795.5" switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9601.6-9601.30" + attribute \src "ls180.v:9793.6-9793.30" case 1'1 assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r case end - attribute \src "ls180.v:9605.2-9607.5" + attribute \src "ls180.v:9797.2-9799.5" switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9605.6-9605.36" + attribute \src "ls180.v:9797.6-9797.36" case 1'1 assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r case end - attribute \src "ls180.v:9610.2-9640.5" + attribute \src "ls180.v:9802.2-9832.5" switch \builder_csrbank11_sel - attribute \src "ls180.v:9610.6-9610.27" + attribute \src "ls180.v:9802.6-9802.27" case 1'1 - attribute \src "ls180.v:9611.3-9639.10" + attribute \src "ls180.v:9803.3-9831.10" switch \builder_interface11_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -280776,60 +299412,60 @@ module \ls180 end case end - attribute \src "ls180.v:9641.2-9643.5" + attribute \src "ls180.v:9833.2-9835.5" switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9641.6-9641.35" + attribute \src "ls180.v:9833.6-9833.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r case end - attribute \src "ls180.v:9644.2-9646.5" + attribute \src "ls180.v:9836.2-9838.5" switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9644.6-9644.35" + attribute \src "ls180.v:9836.6-9836.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r case end - attribute \src "ls180.v:9648.2-9650.5" + attribute \src "ls180.v:9840.2-9842.5" switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9648.6-9648.32" + attribute \src "ls180.v:9840.6-9840.32" case 1'1 assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r case end - attribute \src "ls180.v:9652.2-9654.5" + attribute \src "ls180.v:9844.2-9846.5" switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9652.6-9652.30" + attribute \src "ls180.v:9844.6-9844.30" case 1'1 assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r case end - attribute \src "ls180.v:9656.2-9658.5" + attribute \src "ls180.v:9848.2-9850.5" switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9656.6-9656.36" + attribute \src "ls180.v:9848.6-9848.36" case 1'1 assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r case end - attribute \src "ls180.v:9660.2-9662.5" + attribute \src "ls180.v:9852.2-9854.5" switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9660.6-9660.39" + attribute \src "ls180.v:9852.6-9852.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r case end - attribute \src "ls180.v:9663.2-9665.5" + attribute \src "ls180.v:9855.2-9857.5" switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9663.6-9663.39" + attribute \src "ls180.v:9855.6-9855.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r case end - attribute \src "ls180.v:9668.2-9722.5" + attribute \src "ls180.v:9860.2-9914.5" switch \builder_csrbank12_sel - attribute \src "ls180.v:9668.6-9668.27" + attribute \src "ls180.v:9860.6-9860.27" case 1'1 - attribute \src "ls180.v:9669.3-9721.10" + attribute \src "ls180.v:9861.3-9913.10" switch \builder_interface12_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -280886,88 +299522,88 @@ module \ls180 end case end - attribute \src "ls180.v:9723.2-9725.5" + attribute \src "ls180.v:9915.2-9917.5" switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9723.6-9723.32" + attribute \src "ls180.v:9915.6-9915.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r case end - attribute \src "ls180.v:9726.2-9728.5" + attribute \src "ls180.v:9918.2-9920.5" switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9726.6-9726.32" + attribute \src "ls180.v:9918.6-9918.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r case end - attribute \src "ls180.v:9729.2-9731.5" + attribute \src "ls180.v:9921.2-9923.5" switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9729.6-9729.32" + attribute \src "ls180.v:9921.6-9921.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r case end - attribute \src "ls180.v:9732.2-9734.5" + attribute \src "ls180.v:9924.2-9926.5" switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9732.6-9732.32" + attribute \src "ls180.v:9924.6-9924.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r case end - attribute \src "ls180.v:9736.2-9738.5" + attribute \src "ls180.v:9928.2-9930.5" switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9736.6-9736.34" + attribute \src "ls180.v:9928.6-9928.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r case end - attribute \src "ls180.v:9739.2-9741.5" + attribute \src "ls180.v:9931.2-9933.5" switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9739.6-9739.34" + attribute \src "ls180.v:9931.6-9931.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r case end - attribute \src "ls180.v:9742.2-9744.5" + attribute \src "ls180.v:9934.2-9936.5" switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9742.6-9742.34" + attribute \src "ls180.v:9934.6-9934.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r case end - attribute \src "ls180.v:9745.2-9747.5" + attribute \src "ls180.v:9937.2-9939.5" switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9745.6-9745.34" + attribute \src "ls180.v:9937.6-9937.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r case end - attribute \src "ls180.v:9749.2-9751.5" + attribute \src "ls180.v:9941.2-9943.5" switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9749.6-9749.30" + attribute \src "ls180.v:9941.6-9941.30" case 1'1 assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r case end - attribute \src "ls180.v:9753.2-9755.5" + attribute \src "ls180.v:9945.2-9947.5" switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9753.6-9753.40" + attribute \src "ls180.v:9945.6-9945.40" case 1'1 assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r case end - attribute \src "ls180.v:9757.2-9759.5" + attribute \src "ls180.v:9949.2-9951.5" switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9757.6-9757.37" + attribute \src "ls180.v:9949.6-9949.37" case 1'1 assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r case end - attribute \src "ls180.v:9762.2-9789.5" + attribute \src "ls180.v:9954.2-9981.5" switch \builder_csrbank13_sel - attribute \src "ls180.v:9762.6-9762.27" + attribute \src "ls180.v:9954.6-9954.27" case 1'1 - attribute \src "ls180.v:9763.3-9788.10" + attribute \src "ls180.v:9955.3-9980.10" switch \builder_interface13_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -280997,18 +299633,18 @@ module \ls180 end case end - attribute \src "ls180.v:9790.2-9792.5" + attribute \src "ls180.v:9982.2-9984.5" switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9790.6-9790.37" + attribute \src "ls180.v:9982.6-9982.37" case 1'1 assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r case end - attribute \src "ls180.v:9795.2-9810.5" + attribute \src "ls180.v:9987.2-10002.5" switch \builder_csrbank14_sel - attribute \src "ls180.v:9795.6-9795.27" + attribute \src "ls180.v:9987.6-9987.27" case 1'1 - attribute \src "ls180.v:9796.3-9809.10" + attribute \src "ls180.v:9988.3-10001.10" switch \builder_interface14_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -281026,37 +299662,37 @@ module \ls180 end case end - attribute \src "ls180.v:9811.2-9813.5" + attribute \src "ls180.v:10003.2-10005.5" switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:9811.6-9811.39" + attribute \src "ls180.v:10003.6-10003.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r case end - attribute \src "ls180.v:9814.2-9816.5" + attribute \src "ls180.v:10006.2-10008.5" switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:9814.6-9814.39" + attribute \src "ls180.v:10006.6-10006.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r case end - attribute \src "ls180.v:9817.2-9819.5" + attribute \src "ls180.v:10009.2-10011.5" switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:9817.6-9817.39" + attribute \src "ls180.v:10009.6-10009.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r case end - attribute \src "ls180.v:9820.2-9822.5" + attribute \src "ls180.v:10012.2-10014.5" switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:9820.6-9820.39" + attribute \src "ls180.v:10012.6-10012.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r case end - attribute \src "ls180.v:9824.2-10121.5" + attribute \src "ls180.v:10016.2-10314.5" switch \sys_rst_1 - attribute \src "ls180.v:9824.6-9824.15" + attribute \src "ls180.v:10016.6-10016.15" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] 1'0 assign $0\main_libresocsim_reset_re[0:0] 1'0 @@ -281064,16 +299700,13 @@ module \ls180 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 assign $0\uart_tx[0:0] 1'1 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 assign $0\spimaster_clk[0:0] 1'0 assign $0\spimaster_mosi[0:0] 1'0 assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 assign $0\pwm[1:0] 2'00 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 assign $0\main_libresocsim_load_re[0:0] 1'0 @@ -281092,6 +299725,9 @@ module \ls180 assign $0\main_interface0_ram_bus_ack[0:0] 1'0 assign $0\main_interface1_ram_bus_ack[0:0] 1'0 assign $0\main_interface2_ram_bus_ack[0:0] 1'0 + assign $0\main_interface3_ram_bus_ack[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 assign $0\main_rddata_en[2:0] 3'000 assign $0\main_sdram_storage[3:0] 4'0001 @@ -281156,6 +299792,7 @@ module \ls180 assign $0\main_sdram_twtrcon_count[2:0] 3'000 assign $0\main_sdram_time0[4:0] 5'00000 assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_socbushandler_counter[0:0] 1'0 assign $0\main_converter_counter[0:0] 1'0 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 @@ -281182,10 +299819,10 @@ module \ls180 assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 - assign $0\main_gpio_oe_re[0:0] 1'0 - assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 - assign $0\main_gpio_out_re[0:0] 1'0 + assign $0\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_oe_re[0:0] 1'0 + assign $0\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_out_re[0:0] 1'0 assign $0\main_spimaster5_miso[7:0] 8'00000000 assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 assign $0\main_spimaster12_re[0:0] 1'0 @@ -281296,7 +299933,7 @@ module \ls180 assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 @@ -281307,7 +299944,7 @@ module \ls180 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\main_sdmem2block_dma_data[31:0] 0 + assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 assign $0\main_sdmem2block_dma_length_storage[31:0] 0 @@ -281317,7 +299954,7 @@ module \ls180 assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 @@ -281351,31 +299988,25 @@ module \ls180 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 assign $0\builder_libresocsim_we[0:0] 1'0 assign $0\builder_grant[2:0] 3'000 - assign $0\builder_slave_sel_r[7:0] 8'00000000 + assign $0\builder_slave_sel_r[12:0] 13'0000000000000 assign $0\builder_count[19:0] 20'11110100001001000000 assign $0\builder_state[1:0] 2'00 case end sync posedge \sys_clk_1 update \uart_tx $0\uart_tx[0:0] - update \spisdcard_clk $0\spisdcard_clk[0:0] - update \spisdcard_mosi $0\spisdcard_mosi[0:0] - update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] update \spimaster_clk $0\spimaster_clk[0:0] update \spimaster_mosi $0\spimaster_mosi[0:0] update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] update \pwm $0\pwm[1:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] - update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] - update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] - update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] - update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] - update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] @@ -281394,6 +300025,11 @@ module \ls180 update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0] update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0] update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0] + update \main_interface3_ram_bus_ack $0\main_interface3_ram_bus_ack[0:0] + update \main_converter0_counter $0\main_converter0_counter[0:0] + update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] + update \main_converter1_counter $0\main_converter1_counter[0:0] + update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] update \main_rddata_en $0\main_rddata_en[2:0] update \main_sdram_storage $0\main_sdram_storage[3:0] @@ -281482,6 +300118,8 @@ module \ls180 update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] update \main_sdram_time0 $0\main_sdram_time0[4:0] update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] + update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] update \main_converter_counter $0\main_converter_counter[0:0] update \main_converter_dat_r $0\main_converter_dat_r[31:0] update \main_cmd_consumed $0\main_cmd_consumed[0:0] @@ -281516,10 +300154,10 @@ module \ls180 update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] - update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] - update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] - update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] - update \main_gpio_out_re $0\main_gpio_out_re[0:0] + update \main_gpiotristateasic1_oe_storage $0\main_gpiotristateasic1_oe_storage[15:0] + update \main_gpiotristateasic1_oe_re $0\main_gpiotristateasic1_oe_re[0:0] + update \main_gpiotristateasic1_out_storage $0\main_gpiotristateasic1_out_storage[15:0] + update \main_gpiotristateasic1_out_re $0\main_gpiotristateasic1_out_re[0:0] update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] update \main_spimaster12_re $0\main_spimaster12_re[0:0] @@ -281661,9 +300299,9 @@ module \ls180 update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] - update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] - update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] @@ -281674,7 +300312,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] @@ -281684,7 +300322,7 @@ module \ls180 update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] - update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] @@ -281720,7 +300358,7 @@ module \ls180 update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] update \builder_grant $0\builder_grant[2:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[7:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[12:0] update \builder_count $0\builder_count[19:0] update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] @@ -281773,806 +300411,918 @@ module \ls180 update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:760.5-760.59" - process $proc$ls180.v:760$3156 + attribute \src "ls180.v:784.11-784.68" + process $proc$ls180.v:784$3379 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:785.5-785.64" + process $proc$ls180.v:785$3380 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:786.11-786.70" + process $proc$ls180.v:786$3381 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:787.11-787.70" + process $proc$ls180.v:787$3382 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:788.11-788.73" + process $proc$ls180.v:788$3383 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:809.5-809.59" + process $proc$ls180.v:809$3384 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:762.5-762.59" - process $proc$ls180.v:762$3157 + attribute \src "ls180.v:811.5-811.59" + process $proc$ls180.v:811$3385 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:763.5-763.58" - process $proc$ls180.v:763$3158 + attribute \src "ls180.v:812.5-812.58" + process $proc$ls180.v:812$3386 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:764.5-764.64" - process $proc$ls180.v:764$3159 + attribute \src "ls180.v:813.5-813.64" + process $proc$ls180.v:813$3387 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:765.12-765.74" - process $proc$ls180.v:765$3160 + attribute \src "ls180.v:814.12-814.74" + process $proc$ls180.v:814$3388 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:766.12-766.47" - process $proc$ls180.v:766$3161 + attribute \src "ls180.v:815.12-815.47" + process $proc$ls180.v:815$3389 assign { } { } assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "ls180.v:767.5-767.46" - process $proc$ls180.v:767$3162 + attribute \src "ls180.v:816.5-816.46" + process $proc$ls180.v:816$3390 assign { } { } assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end - attribute \src "ls180.v:769.5-769.44" - process $proc$ls180.v:769$3163 + attribute \src "ls180.v:818.5-818.44" + process $proc$ls180.v:818$3391 assign { } { } assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end - attribute \src "ls180.v:770.5-770.45" - process $proc$ls180.v:770$3164 + attribute \src "ls180.v:819.5-819.45" + process $proc$ls180.v:819$3392 assign { } { } assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end - attribute \src "ls180.v:771.5-771.54" - process $proc$ls180.v:771$3165 + attribute \src "ls180.v:820.5-820.54" + process $proc$ls180.v:820$3393 assign { } { } assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:773.32-773.76" - process $proc$ls180.v:773$3166 + attribute \src "ls180.v:822.32-822.76" + process $proc$ls180.v:822$3394 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "ls180.v:774.11-774.55" - process $proc$ls180.v:774$3167 + attribute \src "ls180.v:823.11-823.55" + process $proc$ls180.v:823$3395 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 sync always sync init update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end - attribute \src "ls180.v:776.32-776.75" - process $proc$ls180.v:776$3168 + attribute \src "ls180.v:825.32-825.75" + process $proc$ls180.v:825$3396 assign { } { } assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] sync init end - attribute \src "ls180.v:778.32-778.76" - process $proc$ls180.v:778$3169 + attribute \src "ls180.v:827.32-827.76" + process $proc$ls180.v:827$3397 assign { } { } assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] sync init end - attribute \src "ls180.v:781.5-781.44" - process $proc$ls180.v:781$3170 + attribute \src "ls180.v:830.5-830.44" + process $proc$ls180.v:830$3398 assign { } { } assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] sync init end - attribute \src "ls180.v:782.5-782.45" - process $proc$ls180.v:782$3171 + attribute \src "ls180.v:831.5-831.45" + process $proc$ls180.v:831$3399 assign { } { } assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] sync init end - attribute \src "ls180.v:783.5-783.43" - process $proc$ls180.v:783$3172 + attribute \src "ls180.v:832.5-832.43" + process $proc$ls180.v:832$3400 assign { } { } assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init end - attribute \src "ls180.v:784.5-784.48" - process $proc$ls180.v:784$3173 + attribute \src "ls180.v:833.5-833.48" + process $proc$ls180.v:833$3401 assign { } { } assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] sync init end - attribute \src "ls180.v:786.5-786.43" - process $proc$ls180.v:786$3174 + attribute \src "ls180.v:835.5-835.43" + process $proc$ls180.v:835$3402 assign { } { } assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] sync init end - attribute \src "ls180.v:789.5-789.49" - process $proc$ls180.v:789$3175 + attribute \src "ls180.v:838.5-838.49" + process $proc$ls180.v:838$3403 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:790.5-790.49" - process $proc$ls180.v:790$3176 + attribute \src "ls180.v:839.5-839.49" + process $proc$ls180.v:839$3404 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:791.5-791.48" - process $proc$ls180.v:791$3177 + attribute \src "ls180.v:840.5-840.48" + process $proc$ls180.v:840$3405 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:795.11-795.46" - process $proc$ls180.v:795$3178 + attribute \src "ls180.v:844.11-844.46" + process $proc$ls180.v:844$3406 assign { } { } assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:797.11-797.45" - process $proc$ls180.v:797$3179 + attribute \src "ls180.v:846.11-846.45" + process $proc$ls180.v:846$3407 assign { } { } assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end - attribute \src "ls180.v:799.5-799.44" - process $proc$ls180.v:799$3180 + attribute \src "ls180.v:848.5-848.44" + process $proc$ls180.v:848$3408 assign { } { } assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \src "ls180.v:800.5-800.45" - process $proc$ls180.v:800$3181 + attribute \src "ls180.v:849.5-849.45" + process $proc$ls180.v:849$3409 assign { } { } assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \src "ls180.v:802.5-802.48" - process $proc$ls180.v:802$3182 + attribute \src "ls180.v:85.11-85.52" + process $proc$ls180.v:85$3134 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] + sync init + end + attribute \src "ls180.v:851.5-851.48" + process $proc$ls180.v:851$3410 assign { } { } assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \src "ls180.v:804.5-804.43" - process $proc$ls180.v:804$3183 + attribute \src "ls180.v:853.5-853.43" + process $proc$ls180.v:853$3411 assign { } { } assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \src "ls180.v:807.5-807.49" - process $proc$ls180.v:807$3184 + attribute \src "ls180.v:856.5-856.49" + process $proc$ls180.v:856$3412 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:808.5-808.49" - process $proc$ls180.v:808$3185 + attribute \src "ls180.v:857.5-857.49" + process $proc$ls180.v:857$3413 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:809.5-809.48" - process $proc$ls180.v:809$3186 + attribute \src "ls180.v:858.5-858.48" + process $proc$ls180.v:858$3414 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:81.5-81.46" - process $proc$ls180.v:81$2903 + attribute \src "ls180.v:86.11-86.52" + process $proc$ls180.v:86$3135 assign { } { } - assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 sync always + update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] sync init - update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] end - attribute \src "ls180.v:813.11-813.46" - process $proc$ls180.v:813$3187 + attribute \src "ls180.v:862.11-862.46" + process $proc$ls180.v:862$3415 assign { } { } assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:815.11-815.45" - process $proc$ls180.v:815$3188 + attribute \src "ls180.v:864.11-864.45" + process $proc$ls180.v:864$3416 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "ls180.v:817.12-817.36" - process $proc$ls180.v:817$3189 + attribute \src "ls180.v:866.12-866.36" + process $proc$ls180.v:866$3417 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init end - attribute \src "ls180.v:818.11-818.35" - process $proc$ls180.v:818$3190 + attribute \src "ls180.v:867.11-867.35" + process $proc$ls180.v:867$3418 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init end - attribute \src "ls180.v:819.11-819.40" - process $proc$ls180.v:819$3191 + attribute \src "ls180.v:868.11-868.40" + process $proc$ls180.v:868$3419 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "ls180.v:820.5-820.31" - process $proc$ls180.v:820$3192 + attribute \src "ls180.v:869.5-869.31" + process $proc$ls180.v:869$3420 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init end - attribute \src "ls180.v:821.5-821.31" - process $proc$ls180.v:821$3193 + attribute \src "ls180.v:870.5-870.31" + process $proc$ls180.v:870$3421 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init end - attribute \src "ls180.v:823.32-823.63" - process $proc$ls180.v:823$3194 + attribute \src "ls180.v:872.32-872.63" + process $proc$ls180.v:872$3422 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init end - attribute \src "ls180.v:825.32-825.63" - process $proc$ls180.v:825$3195 + attribute \src "ls180.v:874.32-874.63" + process $proc$ls180.v:874$3423 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init end - attribute \src "ls180.v:827.32-827.63" - process $proc$ls180.v:827$3196 + attribute \src "ls180.v:876.32-876.63" + process $proc$ls180.v:876$3424 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "ls180.v:828.5-828.36" - process $proc$ls180.v:828$3197 + attribute \src "ls180.v:877.5-877.36" + process $proc$ls180.v:877$3425 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "ls180.v:83.5-83.46" - process $proc$ls180.v:83$2904 + attribute \src "ls180.v:879.32-879.63" + process $proc$ls180.v:879$3426 assign { } { } - assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always - update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] sync init + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:830.32-830.63" - process $proc$ls180.v:830$3198 + attribute \src "ls180.v:88.12-88.58" + process $proc$ls180.v:88$3136 assign { } { } - assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] end - attribute \src "ls180.v:831.11-831.42" - process $proc$ls180.v:831$3199 + attribute \src "ls180.v:880.11-880.42" + process $proc$ls180.v:880$3427 assign { } { } assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always sync init update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "ls180.v:834.5-834.26" - process $proc$ls180.v:834$3200 + attribute \src "ls180.v:883.5-883.26" + process $proc$ls180.v:883$3428 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always sync init update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "ls180.v:836.11-836.34" - process $proc$ls180.v:836$3201 + attribute \src "ls180.v:885.11-885.34" + process $proc$ls180.v:885$3429 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "ls180.v:837.5-837.26" - process $proc$ls180.v:837$3202 + attribute \src "ls180.v:886.5-886.26" + process $proc$ls180.v:886$3430 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always sync init update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "ls180.v:839.11-839.34" - process $proc$ls180.v:839$3203 + attribute \src "ls180.v:888.11-888.34" + process $proc$ls180.v:888$3431 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always sync init update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "ls180.v:860.5-860.29" - process $proc$ls180.v:860$3204 + attribute \src "ls180.v:89.12-89.60" + process $proc$ls180.v:89$3137 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + end + attribute \src "ls180.v:903.12-903.37" + process $proc$ls180.v:903$3432 + assign { } { } + assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] + end + attribute \src "ls180.v:904.12-904.39" + process $proc$ls180.v:904$3433 + assign { } { } + assign $1\main_wb_sdram_dat_w[31:0] 0 + sync always + sync init + update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:906.11-906.35" + process $proc$ls180.v:906$3434 + assign { } { } + assign $1\main_wb_sdram_sel[3:0] 4'0000 + sync always + sync init + update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] + end + attribute \src "ls180.v:907.5-907.29" + process $proc$ls180.v:907$3435 + assign { } { } + assign $1\main_wb_sdram_cyc[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] + end + attribute \src "ls180.v:908.5-908.29" + process $proc$ls180.v:908$3436 + assign { } { } + assign $1\main_wb_sdram_stb[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] + end + attribute \src "ls180.v:909.5-909.29" + process $proc$ls180.v:909$3437 assign { } { } assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "ls180.v:864.5-864.29" - process $proc$ls180.v:864$3205 + attribute \src "ls180.v:91.11-91.56" + process $proc$ls180.v:91$3138 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + end + attribute \src "ls180.v:910.5-910.28" + process $proc$ls180.v:910$3438 + assign { } { } + assign $1\main_wb_sdram_we[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] + end + attribute \src "ls180.v:917.5-917.54" + process $proc$ls180.v:917$3439 + assign { } { } + assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] + end + attribute \src "ls180.v:92.5-92.50" + process $proc$ls180.v:92$3139 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + end + attribute \src "ls180.v:921.5-921.54" + process $proc$ls180.v:921$3440 + assign { } { } + assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + sync always + update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:922.5-922.35" + process $proc$ls180.v:922$3441 + assign { } { } + assign $1\main_socbushandler_skip[0:0] 1'0 + sync always + sync init + update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] + end + attribute \src "ls180.v:923.5-923.38" + process $proc$ls180.v:923$3442 + assign { } { } + assign $1\main_socbushandler_counter[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] + end + attribute \src "ls180.v:925.12-925.44" + process $proc$ls180.v:925$3443 assign { } { } - assign $0\main_wb_sdram_err[0:0] 1'0 + assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] sync init + update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] end - attribute \src "ls180.v:865.12-865.40" - process $proc$ls180.v:865$3206 + attribute \src "ls180.v:926.12-926.40" + process $proc$ls180.v:926$3444 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "ls180.v:866.12-866.42" - process $proc$ls180.v:866$3207 + attribute \src "ls180.v:927.12-927.42" + process $proc$ls180.v:927$3445 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:868.11-868.38" - process $proc$ls180.v:868$3208 + attribute \src "ls180.v:929.11-929.38" + process $proc$ls180.v:929$3446 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "ls180.v:869.5-869.32" - process $proc$ls180.v:869$3209 + attribute \src "ls180.v:93.5-93.50" + process $proc$ls180.v:93$3140 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + end + attribute \src "ls180.v:930.5-930.32" + process $proc$ls180.v:930$3447 assign { } { } assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "ls180.v:870.5-870.32" - process $proc$ls180.v:870$3210 + attribute \src "ls180.v:931.5-931.32" + process $proc$ls180.v:931$3448 assign { } { } assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:872.5-872.31" - process $proc$ls180.v:872$3211 + attribute \src "ls180.v:933.5-933.31" + process $proc$ls180.v:933$3449 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "ls180.v:873.5-873.31" - process $proc$ls180.v:873$3212 + attribute \src "ls180.v:934.5-934.31" + process $proc$ls180.v:934$3450 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always sync init update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "ls180.v:874.5-874.34" - process $proc$ls180.v:874$3213 + attribute \src "ls180.v:935.5-935.34" + process $proc$ls180.v:935$3451 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always sync init update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "ls180.v:876.12-876.40" - process $proc$ls180.v:876$3214 + attribute \src "ls180.v:937.12-937.40" + process $proc$ls180.v:937$3452 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always sync init update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "ls180.v:877.5-877.29" - process $proc$ls180.v:877$3215 + attribute \src "ls180.v:938.5-938.29" + process $proc$ls180.v:938$3453 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "ls180.v:878.5-878.31" - process $proc$ls180.v:878$3216 + attribute \src "ls180.v:939.5-939.31" + process $proc$ls180.v:939$3454 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "ls180.v:882.12-882.47" - process $proc$ls180.v:882$3217 + attribute \src "ls180.v:943.12-943.47" + process $proc$ls180.v:943$3455 assign { } { } assign $1\main_uart_phy_storage[31:0] 9895604 sync always sync init update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end - attribute \src "ls180.v:883.5-883.28" - process $proc$ls180.v:883$3218 + attribute \src "ls180.v:944.5-944.28" + process $proc$ls180.v:944$3456 assign { } { } assign $1\main_uart_phy_re[0:0] 1'0 sync always sync init update \main_uart_phy_re $1\main_uart_phy_re[0:0] end - attribute \src "ls180.v:885.5-885.36" - process $proc$ls180.v:885$3219 + attribute \src "ls180.v:946.5-946.36" + process $proc$ls180.v:946$3457 assign { } { } assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always sync init update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:889.5-889.39" - process $proc$ls180.v:889$3220 + attribute \src "ls180.v:95.5-95.49" + process $proc$ls180.v:95$3141 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + end + attribute \src "ls180.v:950.5-950.39" + process $proc$ls180.v:950$3458 assign { } { } assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:890.12-890.54" - process $proc$ls180.v:890$3221 + attribute \src "ls180.v:951.12-951.54" + process $proc$ls180.v:951$3459 assign { } { } assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:891.11-891.38" - process $proc$ls180.v:891$3222 + attribute \src "ls180.v:952.11-952.38" + process $proc$ls180.v:952$3460 assign { } { } assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:892.11-892.43" - process $proc$ls180.v:892$3223 + attribute \src "ls180.v:953.11-953.43" + process $proc$ls180.v:953$3461 assign { } { } assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:893.5-893.33" - process $proc$ls180.v:893$3224 + attribute \src "ls180.v:954.5-954.33" + process $proc$ls180.v:954$3462 assign { } { } assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:894.5-894.38" - process $proc$ls180.v:894$3225 + attribute \src "ls180.v:955.5-955.38" + process $proc$ls180.v:955$3463 assign { } { } assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always sync init update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end - attribute \src "ls180.v:896.5-896.38" - process $proc$ls180.v:896$3226 + attribute \src "ls180.v:957.5-957.38" + process $proc$ls180.v:957$3464 assign { } { } assign $0\main_uart_phy_source_first[0:0] 1'0 sync always update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init end - attribute \src "ls180.v:897.5-897.37" - process $proc$ls180.v:897$3227 + attribute \src "ls180.v:958.5-958.37" + process $proc$ls180.v:958$3465 assign { } { } assign $0\main_uart_phy_source_last[0:0] 1'0 sync always update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] sync init end - attribute \src "ls180.v:898.11-898.51" - process $proc$ls180.v:898$3228 + attribute \src "ls180.v:959.11-959.51" + process $proc$ls180.v:959$3466 assign { } { } assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:899.5-899.39" - process $proc$ls180.v:899$3229 + attribute \src "ls180.v:960.5-960.39" + process $proc$ls180.v:960$3467 assign { } { } assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:900.12-900.54" - process $proc$ls180.v:900$3230 + attribute \src "ls180.v:961.12-961.54" + process $proc$ls180.v:961$3468 assign { } { } assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:902.5-902.30" - process $proc$ls180.v:902$3231 + attribute \src "ls180.v:963.5-963.30" + process $proc$ls180.v:963$3469 assign { } { } assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always sync init update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end - attribute \src "ls180.v:903.11-903.38" - process $proc$ls180.v:903$3232 + attribute \src "ls180.v:964.11-964.38" + process $proc$ls180.v:964$3470 assign { } { } assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:904.11-904.43" - process $proc$ls180.v:904$3233 + attribute \src "ls180.v:965.11-965.43" + process $proc$ls180.v:965$3471 assign { } { } assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:905.5-905.33" - process $proc$ls180.v:905$3234 + attribute \src "ls180.v:966.5-966.33" + process $proc$ls180.v:966$3472 assign { } { } assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] end - attribute \src "ls180.v:916.5-916.32" - process $proc$ls180.v:916$3235 + attribute \src "ls180.v:97.12-97.58" + process $proc$ls180.v:97$3142 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + end + attribute \src "ls180.v:977.5-977.32" + process $proc$ls180.v:977$3473 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:918.5-918.30" - process $proc$ls180.v:918$3236 + attribute \src "ls180.v:979.5-979.30" + process $proc$ls180.v:979$3474 assign { } { } assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:919.5-919.36" - process $proc$ls180.v:919$3237 + attribute \src "ls180.v:98.12-98.60" + process $proc$ls180.v:98$3143 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + end + attribute \src "ls180.v:980.5-980.36" + process $proc$ls180.v:980$3475 assign { } { } assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "ls180.v:921.5-921.32" - process $proc$ls180.v:921$3238 + attribute \src "ls180.v:982.5-982.32" + process $proc$ls180.v:982$3476 assign { } { } assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "ls180.v:923.5-923.30" - process $proc$ls180.v:923$3239 + attribute \src "ls180.v:984.5-984.30" + process $proc$ls180.v:984$3477 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:924.5-924.36" - process $proc$ls180.v:924$3240 + attribute \src "ls180.v:985.5-985.36" + process $proc$ls180.v:985$3478 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "ls180.v:928.11-928.49" - process $proc$ls180.v:928$3241 + attribute \src "ls180.v:989.11-989.49" + process $proc$ls180.v:989$3479 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:932.11-932.50" - process $proc$ls180.v:932$3242 + attribute \src "ls180.v:993.11-993.50" + process $proc$ls180.v:993$3480 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:933.11-933.48" - process $proc$ls180.v:933$3243 + attribute \src "ls180.v:994.11-994.48" + process $proc$ls180.v:994$3481 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "ls180.v:934.5-934.37" - process $proc$ls180.v:934$3244 + attribute \src "ls180.v:995.5-995.37" + process $proc$ls180.v:995$3482 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always sync init update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] end - attribute \src "ls180.v:951.5-951.40" - process $proc$ls180.v:951$3245 - assign { } { } - assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] - sync init - end - attribute \src "ls180.v:952.5-952.39" - process $proc$ls180.v:952$3246 - assign { } { } - assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] - sync init - end - attribute \src "ls180.v:960.5-960.38" - process $proc$ls180.v:960$3247 - assign { } { } - assign $1\main_uart_tx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] - end - attribute \src "ls180.v:967.11-967.42" - process $proc$ls180.v:967$3248 - assign { } { } - assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] - end - attribute \src "ls180.v:968.5-968.37" - process $proc$ls180.v:968$3249 - assign { } { } - assign $0\main_uart_tx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:969.11-969.43" - process $proc$ls180.v:969$3250 - assign { } { } - assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] - end - attribute \src "ls180.v:970.11-970.43" - process $proc$ls180.v:970$3251 - assign { } { } - assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] - end - attribute \src "ls180.v:971.11-971.46" - process $proc$ls180.v:971$3252 - assign { } { } - assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:997.5-997.38" - process $proc$ls180.v:997$3253 - assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] - end connect \main_libresocsim_libresoc_reset \main_libresocsim_reset connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o @@ -282593,31 +301343,34 @@ module \ls180 connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 connect \main_libresocsim_bus_error \builder_error - connect \main_libresocsim_converter0_reset $not$ls180.v:2818$26_Y - connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } - connect \main_libresocsim_converter1_reset $not$ls180.v:2878$37_Y - connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } - connect \main_libresocsim_converter2_reset $not$ls180.v:2938$48_Y - connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } + connect \main_converter0_reset $not$ls180.v:2893$50_Y + connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } + connect \main_converter1_reset $not$ls180.v:2953$61_Y + connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } + connect \main_socbushandler_reset $not$ls180.v:3013$72_Y + connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } connect \main_libresocsim_reset \main_libresocsim_reset_re connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:3010$72_Y + connect \main_libresocsim_zero_trigger $ne$ls180.v:3089$108_Y connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:3019$75_Y + connect \main_libresocsim_irq $and$ls180.v:3098$111_Y connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger - connect \main_sram0_adr \main_interface0_ram_bus_adr [6:0] + connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0] connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w - connect \main_sram1_adr \main_interface1_ram_bus_adr [6:0] + connect \main_sram1_adr \main_interface1_ram_bus_adr [5:0] connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w - connect \main_sram2_adr \main_interface2_ram_bus_adr [6:0] + connect \main_sram2_adr \main_interface2_ram_bus_adr [5:0] connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w + connect \main_sram3_adr \main_interface3_ram_bus_adr [5:0] + connect \main_interface3_ram_bus_dat_r \main_sram3_dat_r + connect \main_sram3_dat_w \main_interface3_ram_bus_dat_w connect \sys_clk_1 \sys_clk connect \por_clk \sys_clk connect \sys_rst_1 \main_int_rst @@ -282658,8 +301411,8 @@ module \ls180 connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n connect \main_sdram_inti_p0_address \main_sdram_address_storage connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3163$121_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3164$122_Y + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3268$218_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3269$219_Y connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage connect \main_sdram_inti_p0_wrdata_mask 2'00 connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid @@ -282690,14 +301443,14 @@ module \ls180 connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3195$123_Y + connect \main_sdram_timer_wait $not$ls180.v:3300$220_Y connect \main_sdram_postponer_req_i \main_sdram_timer_done0 connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3198$124_Y + connect \main_sdram_timer_done1 $eq$ls180.v:3303$221_Y connect \main_sdram_timer_done0 \main_sdram_timer_done1 connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3201$126_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3202$128_Y + connect \main_sdram_sequencer_start1 $or$ls180.v:3306$223_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3307$225_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we @@ -282708,13 +301461,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3244$130_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3245$131_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3246$132_Y + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3349$227_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3350$228_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3351$229_Y connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3256$137_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3257$139_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3258$141_Y + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3361$234_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3362$236_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3363$238_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable @@ -282730,13 +301483,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3290$149_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3291$150_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3395$246_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3396$247_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3294$151_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3295$152_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3296$154_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3399$248_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3400$249_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3401$251_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we @@ -282747,13 +301500,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3401$160_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3402$161_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3403$162_Y + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3506$257_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3507$258_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3508$259_Y connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3413$167_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3414$169_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3415$171_Y + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3518$264_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3519$266_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3520$268_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable @@ -282769,13 +301522,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3447$179_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3448$180_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3552$276_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3553$277_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3451$181_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3452$182_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3453$184_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3556$278_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3557$279_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3558$281_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we @@ -282786,13 +301539,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3558$190_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3559$191_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3560$192_Y + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3663$287_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3664$288_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3665$289_Y connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3570$197_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3571$199_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3572$201_Y + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3675$294_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3676$296_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3677$298_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable @@ -282808,13 +301561,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3604$209_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3605$210_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3709$306_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3710$307_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3608$211_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3609$212_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3610$214_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3713$308_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3714$309_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3715$311_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we @@ -282825,13 +301578,13 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3715$220_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3716$221_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3717$222_Y + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3820$317_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3821$318_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3822$319_Y connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3727$227_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3728$229_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3729$231_Y + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3832$324_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3833$326_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3834$328_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable @@ -282847,32 +301600,32 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3761$239_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3762$240_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3866$336_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3867$337_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3765$241_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3766$242_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3767$244_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3870$338_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3871$339_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3872$341_Y connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3863$255_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3864$261_Y - connect \main_sdram_ras_allowed $and$ls180.v:3865$262_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3866$265_Y + connect \main_sdram_trrdcon_valid $and$ls180.v:3968$352_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3969$358_Y + connect \main_sdram_ras_allowed $and$ls180.v:3970$359_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3971$362_Y connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3868$267_Y - connect \main_sdram_read_available $or$ls180.v:3869$274_Y - connect \main_sdram_write_available $or$ls180.v:3870$281_Y - connect \main_sdram_max_time0 $eq$ls180.v:3871$282_Y - connect \main_sdram_max_time1 $eq$ls180.v:3872$283_Y + connect \main_sdram_twtrcon_valid $and$ls180.v:3973$364_Y + connect \main_sdram_read_available $or$ls180.v:3974$371_Y + connect \main_sdram_write_available $or$ls180.v:3975$378_Y + connect \main_sdram_max_time0 $eq$ls180.v:3976$379_Y + connect \main_sdram_max_time1 $eq$ls180.v:3977$380_Y connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3877$286_Y + connect \main_sdram_go_to_refresh $and$ls180.v:3982$383_Y connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3880$287_Y + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3985$384_Y connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 @@ -282880,7 +301633,7 @@ module \ls180 connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3913$345_Y + connect \main_sdram_choose_cmd_ce $or$ls180.v:4018$442_Y connect \main_sdram_choose_req_request \main_sdram_choose_req_valids connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 @@ -282888,31 +301641,31 @@ module \ls180 connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3982$431_Y + connect \main_sdram_choose_req_ce $or$ls180.v:4087$528_Y connect \main_sdram_dfi_p0_reset_n 1'1 connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:4059$463_Y - connect \builder_roundrobin0_ce $and$ls180.v:4060$466_Y + connect \builder_roundrobin0_request $and$ls180.v:4164$560_Y + connect \builder_roundrobin0_ce $and$ls180.v:4165$563_Y connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:4064$479_Y - connect \builder_roundrobin1_ce $and$ls180.v:4065$482_Y + connect \builder_roundrobin1_request $and$ls180.v:4169$576_Y + connect \builder_roundrobin1_ce $and$ls180.v:4170$579_Y connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:4069$495_Y - connect \builder_roundrobin2_ce $and$ls180.v:4070$498_Y + connect \builder_roundrobin2_request $and$ls180.v:4174$592_Y + connect \builder_roundrobin2_ce $and$ls180.v:4175$595_Y connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:4074$511_Y - connect \builder_roundrobin3_ce $and$ls180.v:4075$514_Y + connect \builder_roundrobin3_request $and$ls180.v:4179$608_Y + connect \builder_roundrobin3_ce $and$ls180.v:4180$611_Y connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4079$578_Y + connect \main_port_cmd_ready $or$ls180.v:4184$675_Y connect \main_port_wdata_ready \builder_new_master_wdata_ready connect \main_port_rdata_valid \builder_new_master_rdata_valid3 connect \main_port_rdata_payload_data \main_sdram_interface_rdata @@ -282920,22 +301673,22 @@ module \ls180 connect \builder_roundrobin1_grant 1'0 connect \builder_roundrobin2_grant 1'0 connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4101$580_Y + connect \main_converter_reset $not$ls180.v:4206$677_Y connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4161$591_Y [23:0] + connect \main_port_cmd_payload_addr $sub$ls180.v:4266$688_Y [23:0] connect \main_port_cmd_payload_we \main_litedram_wb_we connect \main_port_wdata_payload_data \main_litedram_wb_dat_w connect \main_port_wdata_payload_we \main_litedram_wb_sel connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4166$592_Y - connect \main_port_cmd_last $not$ls180.v:4167$593_Y - connect \main_port_cmd_valid $and$ls180.v:4168$596_Y - connect \main_port_wdata_valid $and$ls180.v:4169$600_Y - connect \main_port_rdata_ready $and$ls180.v:4170$603_Y - connect \main_litedram_wb_ack $and$ls180.v:4171$608_Y - connect \main_ack_cmd $or$ls180.v:4172$610_Y - connect \main_ack_wdata $or$ls180.v:4173$612_Y - connect \main_ack_rdata $and$ls180.v:4174$613_Y + connect \main_port_flush $not$ls180.v:4271$689_Y + connect \main_port_cmd_last $not$ls180.v:4272$690_Y + connect \main_port_cmd_valid $and$ls180.v:4273$693_Y + connect \main_port_wdata_valid $and$ls180.v:4274$697_Y + connect \main_port_rdata_ready $and$ls180.v:4275$700_Y + connect \main_litedram_wb_ack $and$ls180.v:4276$705_Y + connect \main_ack_cmd $or$ls180.v:4277$707_Y + connect \main_ack_wdata $or$ls180.v:4278$709_Y + connect \main_ack_rdata $and$ls180.v:4279$710_Y connect \main_uart_uart_sink_valid \main_uart_phy_source_valid connect \main_uart_phy_source_ready \main_uart_uart_sink_ready connect \main_uart_uart_sink_first \main_uart_phy_source_first @@ -282948,25 +301701,25 @@ module \ls180 connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4187$614_Y - connect \main_uart_txempty_status $not$ls180.v:4188$615_Y + connect \main_uart_txfull_status $not$ls180.v:4292$711_Y + connect \main_uart_txempty_status $not$ls180.v:4293$712_Y connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4194$616_Y + connect \main_uart_tx_trigger $not$ls180.v:4299$713_Y connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4200$617_Y - connect \main_uart_rxfull_status $not$ls180.v:4201$618_Y + connect \main_uart_rxempty_status $not$ls180.v:4305$714_Y + connect \main_uart_rxfull_status $not$ls180.v:4306$715_Y connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4203$620_Y - connect \main_uart_rx_trigger $not$ls180.v:4204$621_Y - connect \main_uart_irq $or$ls180.v:4227$630_Y + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4308$717_Y + connect \main_uart_rx_trigger $not$ls180.v:4309$718_Y + connect \main_uart_irq $or$ls180.v:4332$727_Y connect \main_uart_tx_status \main_uart_tx_trigger connect \main_uart_rx_status \main_uart_rx_trigger connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } @@ -282981,16 +301734,16 @@ module \ls180 connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4242$633_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4243$634_Y + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4347$730_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4348$731_Y connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4253$638_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4254$639_Y + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4358$735_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4359$736_Y connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4258$640_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4259$641_Y + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4363$737_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4364$738_Y connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable @@ -283003,21 +301756,22 @@ module \ls180 connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4272$644_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4273$645_Y + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4377$741_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4378$742_Y connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4283$649_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4284$650_Y + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4388$746_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4389$747_Y connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4288$651_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4289$652_Y - connect \main_gpio_pads_i \gpio_i - connect \gpio_o \main_gpio_pads_o - connect \gpio_oe \main_gpio_pads_oe - connect \main_gpio_pads_oe \main_gpio_oe_storage - connect \main_gpio_pads_o \main_gpio_out_storage + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4393$748_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4394$749_Y + connect \main_gpiotristateasic0_pads_i \gpio_i + connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage + connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage + connect \main_gpiotristateasic1_pads_i \gpio_i + connect \main_gpiotristateasic1_pads_oe \main_gpiotristateasic1_oe_storage + connect \main_gpiotristateasic1_pads_o \main_gpiotristateasic1_out_storage connect \main_spimaster0_start \main_spimaster9_start connect \main_spimaster1_length \main_spimaster10_length connect \main_spimaster4_mosi \main_spimaster16_storage @@ -283025,8 +301779,8 @@ module \ls180 connect \main_spimaster18_status \main_spimaster5_miso connect \main_spimaster6_cs \main_spimaster21_storage connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4302$654_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4303$656_Y + connect \main_spimaster31_clk_rise $eq$ls180.v:4418$753_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4419$755_Y connect \main_spisdcard_start0 \main_spisdcard_start1 connect \main_spisdcard_length0 \main_spisdcard_length1 connect \main_spisdcard_mosi \main_spisdcard_mosi_storage @@ -283034,19 +301788,19 @@ module \ls180 connect \main_spisdcard_miso_status \main_spisdcard_miso connect \main_spisdcard_cs \main_spisdcard_cs_storage connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4360$662_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4361$664_Y + connect \main_spisdcard_clk_rise $eq$ls180.v:4476$761_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4477$763_Y connect \main_spisdcard_clk_divider0 \main_spimaster1_storage connect \i2c_scl \main_i2c_scl connect \i2c_sda_oe \main_i2c_oe connect \i2c_sda_o \main_i2c_sda0 connect \main_i2c_sda1 \i2c_sda_i connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4417$672_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4418$676_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4419$680_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4420$684_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4421$688_Y + connect \main_sdphy_sdpads_clk $or$ls180.v:4533$771_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4534$775_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4535$779_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4536$783_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4537$787_Y connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce @@ -283067,8 +301821,8 @@ module \ls180 connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4442$689_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4472$692_Y + connect \main_sdphy_clocker_stop $or$ls180.v:4558$788_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4588$791_Y connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first @@ -283080,8 +301834,8 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4595$702_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4596$704_Y + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4711$801_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4712$803_Y connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready @@ -283098,10 +301852,10 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4613$706_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4729$805_Y connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4615$707_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4616$709_Y + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4731$806_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4732$808_Y connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first @@ -283113,8 +301867,8 @@ module \ls180 connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4722$724_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4723$725_Y + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4838$823_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4839$824_Y connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready @@ -283131,10 +301885,10 @@ module \ls180 connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4740$727_Y + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4856$826_Y connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4742$728_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4743$730_Y + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4858$827_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4859$829_Y connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first @@ -283146,8 +301900,8 @@ module \ls180 connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4856$739_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4857$740_Y + connect \main_sdphy_datar_datar_start $eq$ls180.v:4972$838_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4973$839_Y connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready @@ -283164,10 +301918,10 @@ module \ls180 connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4874$742_Y + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4990$841_Y connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4876$743_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4877$745_Y + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4992$842_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4993$844_Y connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first @@ -283181,88 +301935,88 @@ module \ls180 connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:4993$760_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_data_event_status { $not$ls180.v:5109$859_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } connect \main_sdcore_crc7_inserter_clr 1'1 connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4997$763_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4997$761_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4998$766_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4998$764_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4999$769_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4999$767_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5000$772_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5000$770_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5001$775_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5001$773_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5002$778_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5002$776_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5003$781_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5003$779_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5004$784_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5004$782_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5005$787_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5005$785_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5006$790_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5006$788_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5007$793_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5007$791_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5008$796_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5008$794_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5009$799_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5009$797_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5010$802_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5010$800_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5011$805_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5011$803_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5012$808_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5012$806_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5013$811_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5013$809_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5014$814_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5014$812_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5015$817_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5015$815_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5016$820_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5016$818_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5017$823_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5017$821_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5018$826_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5018$824_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5019$829_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5019$827_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5020$832_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5020$830_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5021$835_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5021$833_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5022$838_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5022$836_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5023$841_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5023$839_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5024$844_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5024$842_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5025$847_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5025$845_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5026$850_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5026$848_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5027$853_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5027$851_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5028$856_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5028$854_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5029$859_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5029$857_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5030$862_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5030$860_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5031$865_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5031$863_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5032$868_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5032$866_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5033$871_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5033$869_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5034$874_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5034$872_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5035$877_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5035$875_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5036$880_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5036$878_Y } + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5113$862_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5113$860_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5114$865_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5114$863_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5115$868_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5115$866_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5116$871_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5116$869_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5117$874_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5117$872_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5118$877_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5118$875_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5119$880_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5119$878_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5120$883_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5120$881_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5121$886_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5121$884_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5122$889_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5122$887_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5123$892_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5123$890_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5124$895_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5124$893_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5125$898_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5125$896_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5126$901_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5126$899_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5127$904_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5127$902_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5128$907_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5128$905_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5129$910_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5129$908_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5130$913_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5130$911_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5131$916_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5131$914_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5132$919_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5132$917_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5133$922_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5133$920_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5134$925_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5134$923_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5135$928_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5135$926_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5136$931_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5136$929_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5137$934_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5137$932_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5138$937_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5138$935_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5139$940_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5139$938_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5140$943_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5140$941_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5141$946_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5141$944_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5142$949_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5142$947_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5143$952_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5143$950_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5144$955_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5144$953_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5145$958_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5145$956_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5146$961_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5146$959_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5147$964_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5147$962_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5148$967_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5148$965_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5149$970_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5149$968_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5150$973_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5150$971_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5151$976_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5151$974_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5152$979_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5152$977_Y } connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5046$883_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5047$884_Y + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5162$982_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5163$983_Y connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5049$886_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5050$887_Y + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5165$985_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5166$986_Y connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5052$889_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5053$890_Y + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5168$988_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5169$989_Y connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5055$892_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5056$893_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5057$898_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5057$896_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5057$894_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5058$903_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5058$901_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5058$899_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5067$909_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5067$907_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5067$905_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5068$914_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5068$912_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5068$910_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5077$920_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5077$918_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5077$916_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5078$925_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5078$923_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5078$921_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5087$931_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5087$929_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5087$927_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5088$936_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5088$934_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5088$932_Y } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5171$991_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5172$992_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5173$997_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5173$995_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5173$993_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5174$1002_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5174$1000_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5174$998_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5183$1008_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5183$1006_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5183$1004_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5184$1013_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5184$1011_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5184$1009_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5193$1019_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5193$1017_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5193$1015_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5194$1024_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5194$1022_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5194$1020_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5203$1030_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5203$1028_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5203$1026_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5204$1035_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5204$1033_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5204$1031_Y } connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5184$952_Y + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5300$1051_Y connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5194$955_Y + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5310$1054_Y connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5204$958_Y + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5320$1057_Y connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5214$961_Y + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5330$1060_Y connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5239$973_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5239$971_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5239$969_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5240$978_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5240$976_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5240$974_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5249$984_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5249$982_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5249$980_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5250$989_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5250$987_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5250$985_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5259$995_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5259$993_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5259$991_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5260$1000_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5260$998_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5260$996_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5269$1006_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5269$1004_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5269$1002_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5270$1011_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5270$1009_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5270$1007_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5355$1072_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5355$1070_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5355$1068_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5356$1077_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5356$1075_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5356$1073_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5365$1083_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5365$1081_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5365$1079_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5366$1088_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5366$1086_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5366$1084_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5375$1094_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5375$1092_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5375$1090_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5376$1099_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5376$1097_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5376$1095_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5385$1105_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5385$1103_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5385$1101_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5386$1110_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5386$1108_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5386$1106_Y } connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first @@ -283291,30 +302045,30 @@ module \ls180 connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5506$1041_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5507$1042_Y + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5622$1140_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5623$1141_Y connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5510$1043_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5511$1044_Y + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5626$1142_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5627$1143_Y connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5517$1046_Y + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5633$1145_Y connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5519$1047_Y + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5635$1146_Y connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_we 1'1 - connect \main_interface0_bus_sel 4'1111 + connect \main_interface0_bus_sel 8'11111111 connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address - connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack - connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] - connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5529$1048_Y + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] + connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5645$1147_Y connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first @@ -283330,21 +302084,21 @@ module \ls180 connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data - connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] - connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] + connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5588$1055_Y + connect \main_sdmem2block_dma_reset $not$ls180.v:5704$1154_Y connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5669$1063_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5670$1064_Y + connect \main_sdmem2block_converter_first $eq$ls180.v:5785$1162_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5786$1163_Y connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5672$1065_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5673$1066_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5674$1067_Y + connect \main_sdmem2block_converter_source_first $and$ls180.v:5788$1164_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5789$1165_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5790$1166_Y connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout @@ -283359,131 +302113,171 @@ module \ls180 connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5714$1072_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5715$1073_Y + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5842$1171_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5843$1172_Y connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5718$1074_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5719$1075_Y + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5846$1173_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5847$1174_Y connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 connect \builder_shared_stb \builder_comb_rhs_array_muxed28 connect \builder_shared_we \builder_comb_rhs_array_muxed29 connect \builder_shared_cti \builder_comb_rhs_array_muxed30 connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r - connect \main_interface0_bus_dat_r \builder_shared_dat_r - connect \main_interface1_bus_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5770$1081_Y - connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5771$1083_Y - connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5772$1085_Y - connect \main_interface0_bus_ack $and$ls180.v:5773$1087_Y - connect \main_interface1_bus_ack $and$ls180.v:5774$1089_Y - connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5775$1091_Y - connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5776$1093_Y - connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5777$1095_Y - connect \main_interface0_bus_err $and$ls180.v:5778$1097_Y - connect \main_interface1_bus_err $and$ls180.v:5779$1099_Y - connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5898$1180_Y + connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5899$1182_Y + connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5900$1184_Y + connect \main_interface0_bus_ack $and$ls180.v:5901$1186_Y + connect \main_interface1_bus_ack $and$ls180.v:5902$1188_Y + connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5903$1190_Y + connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5904$1192_Y + connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5905$1194_Y + connect \main_interface0_bus_err $and$ls180.v:5906$1196_Y + connect \main_interface1_bus_err $and$ls180.v:5907$1198_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w - connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_libresocsim_ram_bus_stb \builder_shared_stb connect \main_libresocsim_ram_bus_we \builder_shared_we connect \main_libresocsim_ram_bus_cti \builder_shared_cti connect \main_libresocsim_ram_bus_bte \builder_shared_bte connect \main_interface0_ram_bus_adr \builder_shared_adr - connect \main_interface0_ram_bus_dat_w \builder_shared_dat_w - connect \main_interface0_ram_bus_sel \builder_shared_sel + connect \main_interface0_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_interface0_ram_bus_stb \builder_shared_stb connect \main_interface0_ram_bus_we \builder_shared_we connect \main_interface0_ram_bus_cti \builder_shared_cti connect \main_interface0_ram_bus_bte \builder_shared_bte connect \main_interface1_ram_bus_adr \builder_shared_adr - connect \main_interface1_ram_bus_dat_w \builder_shared_dat_w - connect \main_interface1_ram_bus_sel \builder_shared_sel + connect \main_interface1_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_interface1_ram_bus_stb \builder_shared_stb connect \main_interface1_ram_bus_we \builder_shared_we connect \main_interface1_ram_bus_cti \builder_shared_cti connect \main_interface1_ram_bus_bte \builder_shared_bte connect \main_interface2_ram_bus_adr \builder_shared_adr - connect \main_interface2_ram_bus_dat_w \builder_shared_dat_w - connect \main_interface2_ram_bus_sel \builder_shared_sel + connect \main_interface2_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface2_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_interface2_ram_bus_stb \builder_shared_stb connect \main_interface2_ram_bus_we \builder_shared_we connect \main_interface2_ram_bus_cti \builder_shared_cti connect \main_interface2_ram_bus_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte - connect \main_wb_sdram_adr \builder_shared_adr - connect \main_wb_sdram_dat_w \builder_shared_dat_w - connect \main_wb_sdram_sel \builder_shared_sel - connect \main_wb_sdram_stb \builder_shared_stb - connect \main_wb_sdram_we \builder_shared_we - connect \main_wb_sdram_cti \builder_shared_cti - connect \main_wb_sdram_bte \builder_shared_bte - connect \builder_libresocsim_wishbone_adr \builder_shared_adr - connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w - connect \builder_libresocsim_wishbone_sel \builder_shared_sel - connect \builder_libresocsim_wishbone_stb \builder_shared_stb - connect \builder_libresocsim_wishbone_we \builder_shared_we - connect \builder_libresocsim_wishbone_cti \builder_shared_cti - connect \builder_libresocsim_wishbone_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5848$1109_Y - connect \main_interface0_ram_bus_cyc $and$ls180.v:5849$1110_Y - connect \main_interface1_ram_bus_cyc $and$ls180.v:5850$1111_Y - connect \main_interface2_ram_bus_cyc $and$ls180.v:5851$1112_Y - connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5852$1113_Y - connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5853$1114_Y - connect \main_wb_sdram_cyc $and$ls180.v:5854$1115_Y - connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5855$1116_Y - connect \builder_shared_err $or$ls180.v:5856$1123_Y - connect \builder_wait $and$ls180.v:5857$1126_Y - connect \builder_done $eq$ls180.v:5870$1150_Y - connect \builder_csrbank0_sel $eq$ls180.v:5871$1151_Y + connect \main_interface3_ram_bus_adr \builder_shared_adr + connect \main_interface3_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface3_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface3_ram_bus_stb \builder_shared_stb + connect \main_interface3_ram_bus_we \builder_shared_we + connect \main_interface3_ram_bus_cti \builder_shared_cti + connect \main_interface3_ram_bus_bte \builder_shared_bte + connect \main_interface0_converted_interface_adr \builder_shared_adr + connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_converted_interface_stb \builder_shared_stb + connect \main_interface0_converted_interface_we \builder_shared_we + connect \main_interface0_converted_interface_cti \builder_shared_cti + connect \main_interface0_converted_interface_bte \builder_shared_bte + connect \main_interface1_converted_interface_adr \builder_shared_adr + connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_converted_interface_stb \builder_shared_stb + connect \main_interface1_converted_interface_we \builder_shared_we + connect \main_interface1_converted_interface_cti \builder_shared_cti + connect \main_interface1_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface0_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface0_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface0_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface0_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface0_we \builder_shared_we + connect \main_libresocsim_libresoc_interface0_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface0_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface1_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface1_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface1_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface1_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface1_we \builder_shared_we + connect \main_libresocsim_libresoc_interface1_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface1_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface2_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface2_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface2_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface2_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface2_we \builder_shared_we + connect \main_libresocsim_libresoc_interface2_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface2_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface3_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface3_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface3_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface3_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface3_we \builder_shared_we + connect \main_libresocsim_libresoc_interface3_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface3_bte \builder_shared_bte + connect \main_socbushandler_converted_interface_adr \builder_shared_adr + connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_socbushandler_converted_interface_stb \builder_shared_stb + connect \main_socbushandler_converted_interface_we \builder_shared_we + connect \main_socbushandler_converted_interface_cti \builder_shared_cti + connect \main_socbushandler_converted_interface_bte \builder_shared_bte + connect \builder_libresocsim_converted_interface_adr \builder_shared_adr + connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \builder_libresocsim_converted_interface_stb \builder_shared_stb + connect \builder_libresocsim_converted_interface_we \builder_shared_we + connect \builder_libresocsim_converted_interface_cti \builder_shared_cti + connect \builder_libresocsim_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:6016$1213_Y + connect \main_interface0_ram_bus_cyc $and$ls180.v:6017$1214_Y + connect \main_interface1_ram_bus_cyc $and$ls180.v:6018$1215_Y + connect \main_interface2_ram_bus_cyc $and$ls180.v:6019$1216_Y + connect \main_interface3_ram_bus_cyc $and$ls180.v:6020$1217_Y + connect \main_interface0_converted_interface_cyc $and$ls180.v:6021$1218_Y + connect \main_interface1_converted_interface_cyc $and$ls180.v:6022$1219_Y + connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:6023$1220_Y + connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:6024$1221_Y + connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:6025$1222_Y + connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:6026$1223_Y + connect \main_socbushandler_converted_interface_cyc $and$ls180.v:6027$1224_Y + connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:6028$1225_Y + connect \builder_shared_err $or$ls180.v:6029$1237_Y + connect \builder_wait $and$ls180.v:6030$1240_Y + connect \builder_done $eq$ls180.v:6043$1279_Y + connect \builder_csrbank0_sel $eq$ls180.v:6044$1280_Y connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5873$1154_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5874$1158_Y + connect \builder_csrbank0_reset0_re $and$ls180.v:6046$1283_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:6047$1287_Y connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5876$1161_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5877$1165_Y + connect \builder_csrbank0_scratch3_re $and$ls180.v:6049$1290_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:6050$1294_Y connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5879$1168_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5880$1172_Y + connect \builder_csrbank0_scratch2_re $and$ls180.v:6052$1297_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:6053$1301_Y connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5882$1175_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5883$1179_Y + connect \builder_csrbank0_scratch1_re $and$ls180.v:6055$1304_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:6056$1308_Y connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5885$1182_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5886$1186_Y + connect \builder_csrbank0_scratch0_re $and$ls180.v:6058$1311_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:6059$1315_Y connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5888$1189_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5889$1193_Y + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:6061$1318_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:6062$1322_Y connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5891$1196_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5892$1200_Y + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:6064$1325_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:6065$1329_Y connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5894$1203_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5895$1207_Y + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:6067$1332_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:6068$1336_Y connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5897$1210_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5898$1214_Y + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:6070$1339_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:6071$1343_Y connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] @@ -283494,39 +302288,39 @@ module \ls180 connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5909$1215_Y + connect \builder_csrbank1_sel $eq$ls180.v:6082$1344_Y connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:5911$1218_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:5912$1222_Y + connect \builder_csrbank1_oe1_re $and$ls180.v:6084$1347_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:6085$1351_Y connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:5914$1225_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:5915$1229_Y + connect \builder_csrbank1_oe0_re $and$ls180.v:6087$1354_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:6088$1358_Y connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:5917$1232_Y - connect \builder_csrbank1_in1_we $and$ls180.v:5918$1236_Y + connect \builder_csrbank1_in1_re $and$ls180.v:6090$1361_Y + connect \builder_csrbank1_in1_we $and$ls180.v:6091$1365_Y connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:5920$1239_Y - connect \builder_csrbank1_in0_we $and$ls180.v:5921$1243_Y + connect \builder_csrbank1_in0_re $and$ls180.v:6093$1368_Y + connect \builder_csrbank1_in0_we $and$ls180.v:6094$1372_Y connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:5923$1246_Y - connect \builder_csrbank1_out1_we $and$ls180.v:5924$1250_Y + connect \builder_csrbank1_out1_re $and$ls180.v:6096$1375_Y + connect \builder_csrbank1_out1_we $and$ls180.v:6097$1379_Y connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:5926$1253_Y - connect \builder_csrbank1_out0_we $and$ls180.v:5927$1257_Y - connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] - connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] - connect \builder_csrbank1_in1_w \main_gpio_status [15:8] - connect \builder_csrbank1_in0_w \main_gpio_status [7:0] - connect \main_gpio_we \builder_csrbank1_in0_we - connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] - connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:5935$1258_Y + connect \builder_csrbank1_out0_re $and$ls180.v:6099$1382_Y + connect \builder_csrbank1_out0_we $and$ls180.v:6100$1386_Y + connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] + connect \builder_csrbank1_in0_w \main_gpiotristateasic1_status [7:0] + connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:6108$1387_Y connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:5937$1261_Y - connect \builder_csrbank2_w0_we $and$ls180.v:5938$1265_Y + connect \builder_csrbank2_w0_re $and$ls180.v:6110$1390_Y + connect \builder_csrbank2_w0_we $and$ls180.v:6111$1394_Y connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:5940$1268_Y - connect \builder_csrbank2_r_we $and$ls180.v:5941$1272_Y + connect \builder_csrbank2_r_re $and$ls180.v:6113$1397_Y + connect \builder_csrbank2_r_we $and$ls180.v:6114$1401_Y connect \main_i2c_scl \main_i2c_storage [0] connect \main_i2c_oe \main_i2c_storage [1] connect \main_i2c_sda0 \main_i2c_storage [2] @@ -283534,34 +302328,34 @@ module \ls180 connect \main_i2c_status \main_i2c_sda1 connect \builder_csrbank2_r_w \main_i2c_status connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:5949$1273_Y + connect \builder_csrbank3_sel $eq$ls180.v:6122$1402_Y connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:5951$1276_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:5952$1280_Y + connect \builder_csrbank3_enable0_re $and$ls180.v:6124$1405_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:6125$1409_Y connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:5954$1283_Y - connect \builder_csrbank3_width3_we $and$ls180.v:5955$1287_Y + connect \builder_csrbank3_width3_re $and$ls180.v:6127$1412_Y + connect \builder_csrbank3_width3_we $and$ls180.v:6128$1416_Y connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:5957$1290_Y - connect \builder_csrbank3_width2_we $and$ls180.v:5958$1294_Y + connect \builder_csrbank3_width2_re $and$ls180.v:6130$1419_Y + connect \builder_csrbank3_width2_we $and$ls180.v:6131$1423_Y connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:5960$1297_Y - connect \builder_csrbank3_width1_we $and$ls180.v:5961$1301_Y + connect \builder_csrbank3_width1_re $and$ls180.v:6133$1426_Y + connect \builder_csrbank3_width1_we $and$ls180.v:6134$1430_Y connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:5963$1304_Y - connect \builder_csrbank3_width0_we $and$ls180.v:5964$1308_Y + connect \builder_csrbank3_width0_re $and$ls180.v:6136$1433_Y + connect \builder_csrbank3_width0_we $and$ls180.v:6137$1437_Y connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:5966$1311_Y - connect \builder_csrbank3_period3_we $and$ls180.v:5967$1315_Y + connect \builder_csrbank3_period3_re $and$ls180.v:6139$1440_Y + connect \builder_csrbank3_period3_we $and$ls180.v:6140$1444_Y connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:5969$1318_Y - connect \builder_csrbank3_period2_we $and$ls180.v:5970$1322_Y + connect \builder_csrbank3_period2_re $and$ls180.v:6142$1447_Y + connect \builder_csrbank3_period2_we $and$ls180.v:6143$1451_Y connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:5972$1325_Y - connect \builder_csrbank3_period1_we $and$ls180.v:5973$1329_Y + connect \builder_csrbank3_period1_re $and$ls180.v:6145$1454_Y + connect \builder_csrbank3_period1_we $and$ls180.v:6146$1458_Y connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:5975$1332_Y - connect \builder_csrbank3_period0_we $and$ls180.v:5976$1336_Y + connect \builder_csrbank3_period0_re $and$ls180.v:6148$1461_Y + connect \builder_csrbank3_period0_we $and$ls180.v:6149$1465_Y connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] @@ -283571,34 +302365,34 @@ module \ls180 connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:5986$1337_Y + connect \builder_csrbank4_sel $eq$ls180.v:6159$1466_Y connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:5988$1340_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:5989$1344_Y + connect \builder_csrbank4_enable0_re $and$ls180.v:6161$1469_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:6162$1473_Y connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:5991$1347_Y - connect \builder_csrbank4_width3_we $and$ls180.v:5992$1351_Y + connect \builder_csrbank4_width3_re $and$ls180.v:6164$1476_Y + connect \builder_csrbank4_width3_we $and$ls180.v:6165$1480_Y connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:5994$1354_Y - connect \builder_csrbank4_width2_we $and$ls180.v:5995$1358_Y + connect \builder_csrbank4_width2_re $and$ls180.v:6167$1483_Y + connect \builder_csrbank4_width2_we $and$ls180.v:6168$1487_Y connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:5997$1361_Y - connect \builder_csrbank4_width1_we $and$ls180.v:5998$1365_Y + connect \builder_csrbank4_width1_re $and$ls180.v:6170$1490_Y + connect \builder_csrbank4_width1_we $and$ls180.v:6171$1494_Y connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:6000$1368_Y - connect \builder_csrbank4_width0_we $and$ls180.v:6001$1372_Y + connect \builder_csrbank4_width0_re $and$ls180.v:6173$1497_Y + connect \builder_csrbank4_width0_we $and$ls180.v:6174$1501_Y connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:6003$1375_Y - connect \builder_csrbank4_period3_we $and$ls180.v:6004$1379_Y + connect \builder_csrbank4_period3_re $and$ls180.v:6176$1504_Y + connect \builder_csrbank4_period3_we $and$ls180.v:6177$1508_Y connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:6006$1382_Y - connect \builder_csrbank4_period2_we $and$ls180.v:6007$1386_Y + connect \builder_csrbank4_period2_re $and$ls180.v:6179$1511_Y + connect \builder_csrbank4_period2_we $and$ls180.v:6180$1515_Y connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:6009$1389_Y - connect \builder_csrbank4_period1_we $and$ls180.v:6010$1393_Y + connect \builder_csrbank4_period1_re $and$ls180.v:6182$1518_Y + connect \builder_csrbank4_period1_we $and$ls180.v:6183$1522_Y connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:6012$1396_Y - connect \builder_csrbank4_period0_we $and$ls180.v:6013$1400_Y + connect \builder_csrbank4_period0_re $and$ls180.v:6185$1525_Y + connect \builder_csrbank4_period0_we $and$ls180.v:6186$1529_Y connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] @@ -283608,52 +302402,52 @@ module \ls180 connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:6023$1401_Y + connect \builder_csrbank5_sel $eq$ls180.v:6196$1530_Y connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:6025$1404_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:6026$1408_Y + connect \builder_csrbank5_dma_base7_re $and$ls180.v:6198$1533_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:6199$1537_Y connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:6028$1411_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:6029$1415_Y + connect \builder_csrbank5_dma_base6_re $and$ls180.v:6201$1540_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:6202$1544_Y connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:6031$1418_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:6032$1422_Y + connect \builder_csrbank5_dma_base5_re $and$ls180.v:6204$1547_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:6205$1551_Y connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:6034$1425_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:6035$1429_Y + connect \builder_csrbank5_dma_base4_re $and$ls180.v:6207$1554_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:6208$1558_Y connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:6037$1432_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:6038$1436_Y + connect \builder_csrbank5_dma_base3_re $and$ls180.v:6210$1561_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:6211$1565_Y connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:6040$1439_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:6041$1443_Y + connect \builder_csrbank5_dma_base2_re $and$ls180.v:6213$1568_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:6214$1572_Y connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:6043$1446_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:6044$1450_Y + connect \builder_csrbank5_dma_base1_re $and$ls180.v:6216$1575_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:6217$1579_Y connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:6046$1453_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:6047$1457_Y + connect \builder_csrbank5_dma_base0_re $and$ls180.v:6219$1582_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:6220$1586_Y connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:6049$1460_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:6050$1464_Y + connect \builder_csrbank5_dma_length3_re $and$ls180.v:6222$1589_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:6223$1593_Y connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:6052$1467_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:6053$1471_Y + connect \builder_csrbank5_dma_length2_re $and$ls180.v:6225$1596_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:6226$1600_Y connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:6055$1474_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:6056$1478_Y + connect \builder_csrbank5_dma_length1_re $and$ls180.v:6228$1603_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:6229$1607_Y connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:6058$1481_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:6059$1485_Y + connect \builder_csrbank5_dma_length0_re $and$ls180.v:6231$1610_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:6232$1614_Y connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6061$1488_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6062$1492_Y + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6234$1617_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6235$1621_Y connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:6064$1495_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:6065$1499_Y + connect \builder_csrbank5_dma_done_re $and$ls180.v:6237$1624_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:6238$1628_Y connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6067$1502_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6068$1506_Y + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6240$1631_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6241$1635_Y connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] @@ -283670,106 +302464,106 @@ module \ls180 connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:6085$1507_Y + connect \builder_csrbank6_sel $eq$ls180.v:6258$1636_Y connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6087$1510_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6088$1514_Y + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6260$1639_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6261$1643_Y connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6090$1517_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6091$1521_Y + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6263$1646_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6264$1650_Y connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6093$1524_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6094$1528_Y + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6266$1653_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6267$1657_Y connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6096$1531_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6097$1535_Y + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6269$1660_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6270$1664_Y connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6099$1538_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6100$1542_Y + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6272$1667_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6273$1671_Y connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6102$1545_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6103$1549_Y + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6275$1674_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6276$1678_Y connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6105$1552_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6106$1556_Y + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6278$1681_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6279$1685_Y connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6108$1559_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6109$1563_Y + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6281$1688_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6282$1692_Y connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6111$1566_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6112$1570_Y + connect \main_sdcore_cmd_send_re $and$ls180.v:6284$1695_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6285$1699_Y connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6114$1573_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6115$1577_Y + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6287$1702_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6288$1706_Y connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6117$1580_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6118$1584_Y + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6290$1709_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6291$1713_Y connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6120$1587_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6121$1591_Y + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6293$1716_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6294$1720_Y connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6123$1594_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6124$1598_Y + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6296$1723_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6297$1727_Y connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6126$1601_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6127$1605_Y + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6299$1730_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6300$1734_Y connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6129$1608_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6130$1612_Y + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6302$1737_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6303$1741_Y connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6132$1615_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6133$1619_Y + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6305$1744_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6306$1748_Y connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6135$1622_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6136$1626_Y + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6308$1751_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6309$1755_Y connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6138$1629_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6139$1633_Y + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6311$1758_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6312$1762_Y connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6141$1636_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6142$1640_Y + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6314$1765_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6315$1769_Y connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6144$1643_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6145$1647_Y + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6317$1772_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6318$1776_Y connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6147$1650_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6148$1654_Y + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6320$1779_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6321$1783_Y connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6150$1657_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6151$1661_Y + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6323$1786_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6324$1790_Y connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6153$1664_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6154$1668_Y + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6326$1793_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6327$1797_Y connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6156$1671_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6157$1675_Y + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6329$1800_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6330$1804_Y connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6159$1678_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6160$1682_Y + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6332$1807_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6333$1811_Y connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6162$1685_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6163$1689_Y + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6335$1814_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6336$1818_Y connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6165$1692_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6166$1696_Y + connect \builder_csrbank6_data_event_re $and$ls180.v:6338$1821_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6339$1825_Y connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6168$1699_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6169$1703_Y + connect \builder_csrbank6_block_length1_re $and$ls180.v:6341$1828_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6342$1832_Y connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6171$1706_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6172$1710_Y + connect \builder_csrbank6_block_length0_re $and$ls180.v:6344$1835_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6345$1839_Y connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6174$1713_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6175$1717_Y + connect \builder_csrbank6_block_count3_re $and$ls180.v:6347$1842_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6348$1846_Y connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6177$1720_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6178$1724_Y + connect \builder_csrbank6_block_count2_re $and$ls180.v:6350$1849_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6351$1853_Y connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6180$1727_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6181$1731_Y + connect \builder_csrbank6_block_count1_re $and$ls180.v:6353$1856_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6354$1860_Y connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6183$1734_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6184$1738_Y + connect \builder_csrbank6_block_count0_re $and$ls180.v:6356$1863_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6357$1867_Y connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] @@ -283805,64 +302599,64 @@ module \ls180 connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6220$1739_Y + connect \builder_csrbank7_sel $eq$ls180.v:6393$1868_Y connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6222$1742_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6223$1746_Y + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6395$1871_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6396$1875_Y connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6225$1749_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6226$1753_Y + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6398$1878_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6399$1882_Y connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6228$1756_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6229$1760_Y + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6401$1885_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6402$1889_Y connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6231$1763_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6232$1767_Y + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6404$1892_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6405$1896_Y connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6234$1770_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6235$1774_Y + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6407$1899_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6408$1903_Y connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6237$1777_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6238$1781_Y + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6410$1906_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6411$1910_Y connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6240$1784_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6241$1788_Y + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6413$1913_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6414$1917_Y connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6243$1791_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6244$1795_Y + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6416$1920_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6417$1924_Y connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6246$1798_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6247$1802_Y + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6419$1927_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6420$1931_Y connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6249$1805_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6250$1809_Y + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6422$1934_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6423$1938_Y connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6252$1812_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6253$1816_Y + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6425$1941_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6426$1945_Y connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6255$1819_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6256$1823_Y + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6428$1948_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6429$1952_Y connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6258$1826_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6259$1830_Y + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6431$1955_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6432$1959_Y connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6261$1833_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6262$1837_Y + connect \builder_csrbank7_dma_done_re $and$ls180.v:6434$1962_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6435$1966_Y connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6264$1840_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6265$1844_Y + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6437$1969_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6438$1973_Y connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6267$1847_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6268$1851_Y + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6440$1976_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6441$1980_Y connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6270$1854_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6271$1858_Y + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6443$1983_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6444$1987_Y connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6273$1861_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6274$1865_Y + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6446$1990_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6447$1994_Y connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6276$1868_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6277$1872_Y + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6449$1997_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6450$2001_Y connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] @@ -283884,54 +302678,54 @@ module \ls180 connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6299$1873_Y + connect \builder_csrbank8_sel $eq$ls180.v:6472$2002_Y connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6301$1876_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6302$1880_Y + connect \builder_csrbank8_card_detect_re $and$ls180.v:6474$2005_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6475$2009_Y connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6304$1883_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6305$1887_Y + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6477$2012_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6478$2016_Y connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6307$1890_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6308$1894_Y + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6480$2019_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6481$2023_Y connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6310$1897_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6311$1901_Y + connect \main_sdphy_init_initialize_re $and$ls180.v:6483$2026_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6484$2030_Y connect \builder_csrbank8_card_detect_w \main_sdphy_status connect \main_sdphy_we \builder_csrbank8_card_detect_we connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6316$1902_Y + connect \builder_csrbank9_sel $eq$ls180.v:6489$2031_Y connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6318$1905_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6319$1909_Y + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6491$2034_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6492$2038_Y connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6321$1912_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6322$1916_Y + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6494$2041_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6495$2045_Y connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6324$1919_Y - connect \main_sdram_command_issue_we $and$ls180.v:6325$1923_Y + connect \main_sdram_command_issue_re $and$ls180.v:6497$2048_Y + connect \main_sdram_command_issue_we $and$ls180.v:6498$2052_Y connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6327$1926_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6328$1930_Y + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6500$2055_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6501$2059_Y connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6330$1933_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6331$1937_Y + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6503$2062_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6504$2066_Y connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6333$1940_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6334$1944_Y + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6506$2069_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6507$2073_Y connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6336$1947_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6337$1951_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6509$2076_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6510$2080_Y connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6339$1954_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6340$1958_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6512$2083_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6513$2087_Y connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6342$1961_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6343$1965_Y + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6515$2090_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6516$2094_Y connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6345$1968_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6346$1972_Y + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6518$2097_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6519$2101_Y connect \main_sdram_sel \main_sdram_storage [0] connect \main_sdram_cke \main_sdram_storage [1] connect \main_sdram_odt \main_sdram_storage [2] @@ -283946,28 +302740,28 @@ module \ls180 connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6361$1973_Y + connect \builder_csrbank10_sel $eq$ls180.v:6534$2102_Y connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6363$1976_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6364$1980_Y + connect \builder_csrbank10_control1_re $and$ls180.v:6536$2105_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6537$2109_Y connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6366$1983_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6367$1987_Y + connect \builder_csrbank10_control0_re $and$ls180.v:6539$2112_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6540$2116_Y connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6369$1990_Y - connect \builder_csrbank10_status_we $and$ls180.v:6370$1994_Y + connect \builder_csrbank10_status_re $and$ls180.v:6542$2119_Y + connect \builder_csrbank10_status_we $and$ls180.v:6543$2123_Y connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6372$1997_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6373$2001_Y + connect \builder_csrbank10_mosi0_re $and$ls180.v:6545$2126_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6546$2130_Y connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6375$2004_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6376$2008_Y + connect \builder_csrbank10_miso_re $and$ls180.v:6548$2133_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6549$2137_Y connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6378$2011_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6379$2015_Y + connect \builder_csrbank10_cs0_re $and$ls180.v:6551$2140_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6552$2144_Y connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6381$2018_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6382$2022_Y + connect \builder_csrbank10_loopback0_re $and$ls180.v:6554$2147_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6555$2151_Y connect \main_spimaster10_length \main_spimaster11_storage [15:8] connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] @@ -283980,34 +302774,34 @@ module \ls180 connect \main_spimaster20_sel \main_spimaster21_storage connect \builder_csrbank10_cs0_w \main_spimaster21_storage connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6401$2024_Y + connect \builder_csrbank11_sel $eq$ls180.v:6574$2153_Y connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6403$2027_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6404$2031_Y + connect \builder_csrbank11_control1_re $and$ls180.v:6576$2156_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6577$2160_Y connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6406$2034_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6407$2038_Y + connect \builder_csrbank11_control0_re $and$ls180.v:6579$2163_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6580$2167_Y connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6409$2041_Y - connect \builder_csrbank11_status_we $and$ls180.v:6410$2045_Y + connect \builder_csrbank11_status_re $and$ls180.v:6582$2170_Y + connect \builder_csrbank11_status_we $and$ls180.v:6583$2174_Y connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6412$2048_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6413$2052_Y + connect \builder_csrbank11_mosi0_re $and$ls180.v:6585$2177_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6586$2181_Y connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6415$2055_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6416$2059_Y + connect \builder_csrbank11_miso_re $and$ls180.v:6588$2184_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6589$2188_Y connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6418$2062_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6419$2066_Y + connect \builder_csrbank11_cs0_re $and$ls180.v:6591$2191_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6592$2195_Y connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6421$2069_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6422$2073_Y + connect \builder_csrbank11_loopback0_re $and$ls180.v:6594$2198_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6595$2202_Y connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6424$2076_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6425$2080_Y + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6597$2205_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6598$2209_Y connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6427$2083_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6428$2087_Y + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6600$2212_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6601$2216_Y connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] @@ -284022,58 +302816,58 @@ module \ls180 connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6449$2089_Y + connect \builder_csrbank12_sel $eq$ls180.v:6622$2218_Y connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6451$2092_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6452$2096_Y + connect \builder_csrbank12_load3_re $and$ls180.v:6624$2221_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6625$2225_Y connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6454$2099_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6455$2103_Y + connect \builder_csrbank12_load2_re $and$ls180.v:6627$2228_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6628$2232_Y connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6457$2106_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6458$2110_Y + connect \builder_csrbank12_load1_re $and$ls180.v:6630$2235_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6631$2239_Y connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6460$2113_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6461$2117_Y + connect \builder_csrbank12_load0_re $and$ls180.v:6633$2242_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6634$2246_Y connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6463$2120_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6464$2124_Y + connect \builder_csrbank12_reload3_re $and$ls180.v:6636$2249_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6637$2253_Y connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6466$2127_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6467$2131_Y + connect \builder_csrbank12_reload2_re $and$ls180.v:6639$2256_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6640$2260_Y connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6469$2134_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6470$2138_Y + connect \builder_csrbank12_reload1_re $and$ls180.v:6642$2263_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6643$2267_Y connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6472$2141_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6473$2145_Y + connect \builder_csrbank12_reload0_re $and$ls180.v:6645$2270_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6646$2274_Y connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6475$2148_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6476$2152_Y + connect \builder_csrbank12_en0_re $and$ls180.v:6648$2277_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6649$2281_Y connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6478$2155_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6479$2159_Y + connect \builder_csrbank12_update_value0_re $and$ls180.v:6651$2284_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6652$2288_Y connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6481$2162_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6482$2166_Y + connect \builder_csrbank12_value3_re $and$ls180.v:6654$2291_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6655$2295_Y connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6484$2169_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6485$2173_Y + connect \builder_csrbank12_value2_re $and$ls180.v:6657$2298_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6658$2302_Y connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6487$2176_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6488$2180_Y + connect \builder_csrbank12_value1_re $and$ls180.v:6660$2305_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6661$2309_Y connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6490$2183_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6491$2187_Y + connect \builder_csrbank12_value0_re $and$ls180.v:6663$2312_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6664$2316_Y connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6493$2190_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6494$2194_Y + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6666$2319_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6667$2323_Y connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6496$2197_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6497$2201_Y + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6669$2326_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6670$2330_Y connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6499$2204_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6500$2208_Y + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6672$2333_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6673$2337_Y connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] @@ -284090,31 +302884,31 @@ module \ls180 connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] connect \main_libresocsim_value_we \builder_csrbank12_value0_we connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6517$2209_Y + connect \builder_csrbank13_sel $eq$ls180.v:6690$2338_Y connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6519$2212_Y - connect \main_uart_rxtx_we $and$ls180.v:6520$2216_Y + connect \main_uart_rxtx_re $and$ls180.v:6692$2341_Y + connect \main_uart_rxtx_we $and$ls180.v:6693$2345_Y connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6522$2219_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6523$2223_Y + connect \builder_csrbank13_txfull_re $and$ls180.v:6695$2348_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6696$2352_Y connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6525$2226_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6526$2230_Y + connect \builder_csrbank13_rxempty_re $and$ls180.v:6698$2355_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6699$2359_Y connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6528$2233_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6529$2237_Y + connect \main_uart_eventmanager_status_re $and$ls180.v:6701$2362_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6702$2366_Y connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6531$2240_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6532$2244_Y + connect \main_uart_eventmanager_pending_re $and$ls180.v:6704$2369_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6705$2373_Y connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6534$2247_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6535$2251_Y + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6707$2376_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6708$2380_Y connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6537$2254_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6538$2258_Y + connect \builder_csrbank13_txempty_re $and$ls180.v:6710$2383_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6711$2387_Y connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6540$2261_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6541$2265_Y + connect \builder_csrbank13_rxfull_re $and$ls180.v:6713$2390_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6714$2394_Y connect \builder_csrbank13_txfull_w \main_uart_txfull_status connect \main_uart_txfull_we \builder_csrbank13_txfull_we connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status @@ -284124,19 +302918,19 @@ module \ls180 connect \main_uart_txempty_we \builder_csrbank13_txempty_we connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6551$2266_Y + connect \builder_csrbank14_sel $eq$ls180.v:6724$2395_Y connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6553$2269_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6554$2273_Y + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6726$2398_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6727$2402_Y connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6556$2276_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6557$2280_Y + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6729$2405_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6730$2409_Y connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6559$2283_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6560$2287_Y + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6732$2412_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6733$2416_Y connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6562$2290_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6563$2294_Y + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6735$2419_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6736$2423_Y connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] @@ -284190,7 +302984,7 @@ module \ls180 connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6617$2308_Y + connect \builder_csr_interconnect_dat_r $or$ls180.v:6790$2437_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -284267,96 +303061,97 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10172$2771_DATA - connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10192$2785_DATA - connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10212$2799_DATA - connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10232$2813_DATA + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10373$2916_DATA + connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10401$2942_DATA + connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10429$2968_DATA + connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10457$2994_DATA + connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10485$3020_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10250$2820_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10503$3027_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10264$2827_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10517$3034_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10278$2834_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10531$3041_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10292$2841_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10545$3048_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10340$2862_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10593$3069_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10354$2869_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3076_DATA end -attribute \src "libresoc.v:135159.1-135217.10" +attribute \src "libresoc.v:144930.1-144988.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:135160.7-135160.20" + attribute \src "libresoc.v:144931.7-144931.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135205.3-135213.6" - wire $0\q_int$next[0:0]$6779 - attribute \src "libresoc.v:135203.3-135204.27" + attribute \src "libresoc.v:144976.3-144984.6" + wire $0\q_int$next[0:0]$7101 + attribute \src "libresoc.v:144974.3-144975.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:135205.3-135213.6" - wire $1\q_int$next[0:0]$6780 - attribute \src "libresoc.v:135182.7-135182.19" + attribute \src "libresoc.v:144976.3-144984.6" + wire $1\q_int$next[0:0]$7102 + attribute \src "libresoc.v:144953.7-144953.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:135195.17-135195.96" - wire $and$libresoc.v:135195$6769_Y - attribute \src "libresoc.v:135200.17-135200.96" - wire $and$libresoc.v:135200$6774_Y - attribute \src "libresoc.v:135197.18-135197.93" - wire $not$libresoc.v:135197$6771_Y - attribute \src "libresoc.v:135199.17-135199.92" - wire $not$libresoc.v:135199$6773_Y - attribute \src "libresoc.v:135202.17-135202.92" - wire $not$libresoc.v:135202$6776_Y - attribute \src "libresoc.v:135196.18-135196.98" - wire $or$libresoc.v:135196$6770_Y - attribute \src "libresoc.v:135198.18-135198.99" - wire $or$libresoc.v:135198$6772_Y - attribute \src "libresoc.v:135201.17-135201.97" - wire $or$libresoc.v:135201$6775_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:144966.17-144966.96" + wire $and$libresoc.v:144966$7091_Y + attribute \src "libresoc.v:144971.17-144971.96" + wire $and$libresoc.v:144971$7096_Y + attribute \src "libresoc.v:144968.18-144968.93" + wire $not$libresoc.v:144968$7093_Y + attribute \src "libresoc.v:144970.17-144970.92" + wire $not$libresoc.v:144970$7095_Y + attribute \src "libresoc.v:144973.17-144973.92" + wire $not$libresoc.v:144973$7098_Y + attribute \src "libresoc.v:144967.18-144967.98" + wire $or$libresoc.v:144967$7092_Y + attribute \src "libresoc.v:144969.18-144969.99" + wire $or$libresoc.v:144969$7094_Y + attribute \src "libresoc.v:144972.17-144972.97" + wire $or$libresoc.v:144972$7097_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:135160.7-135160.15" + attribute \src "libresoc.v:144931.7-144931.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:135195$6769 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:144966$7091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284364,10 +303159,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:135195$6769_Y + connect \Y $and$libresoc.v:144966$7091_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:135200$6774 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:144971$7096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284375,34 +303170,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:135200$6774_Y + connect \Y $and$libresoc.v:144971$7096_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:135197$6771 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:144968$7093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:135197$6771_Y + connect \Y $not$libresoc.v:144968$7093_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:135199$6773 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:144970$7095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:135199$6773_Y + connect \Y $not$libresoc.v:144970$7095_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:135202$6776 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:144973$7098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:135202$6776_Y + connect \Y $not$libresoc.v:144973$7098_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:135196$6770 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:144967$7092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284410,10 +303205,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:135196$6770_Y + connect \Y $or$libresoc.v:144967$7092_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:135198$6772 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:144969$7094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284421,10 +303216,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:135198$6772_Y + connect \Y $or$libresoc.v:144969$7094_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:135201$6775 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:144972$7097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284432,39 +303227,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:135201$6775_Y + connect \Y $or$libresoc.v:144972$7097_Y end - attribute \src "libresoc.v:135160.7-135160.20" - process $proc$libresoc.v:135160$6781 + attribute \src "libresoc.v:144931.7-144931.20" + process $proc$libresoc.v:144931$7103 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135182.7-135182.19" - process $proc$libresoc.v:135182$6782 + attribute \src "libresoc.v:144953.7-144953.19" + process $proc$libresoc.v:144953$7104 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:135203.3-135204.27" - process $proc$libresoc.v:135203$6777 + attribute \src "libresoc.v:144974.3-144975.27" + process $proc$libresoc.v:144974$7099 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:135205.3-135213.6" - process $proc$libresoc.v:135205$6778 + attribute \src "libresoc.v:144976.3-144984.6" + process $proc$libresoc.v:144976$7100 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6779 $1\q_int$next[0:0]$6780 - attribute \src "libresoc.v:135206.5-135206.29" + assign $0\q_int$next[0:0]$7101 $1\q_int$next[0:0]$7102 + attribute \src "libresoc.v:144977.5-144977.29" switch \initial - attribute \src "libresoc.v:135206.9-135206.17" + attribute \src "libresoc.v:144977.9-144977.17" case 1'1 case end @@ -284473,266 +303268,266 @@ module \lsd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6780 1'0 + assign $1\q_int$next[0:0]$7102 1'0 case - assign $1\q_int$next[0:0]$6780 \$5 + assign $1\q_int$next[0:0]$7102 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6779 + update \q_int$next $0\q_int$next[0:0]$7101 end - connect \$9 $and$libresoc.v:135195$6769_Y - connect \$11 $or$libresoc.v:135196$6770_Y - connect \$13 $not$libresoc.v:135197$6771_Y - connect \$15 $or$libresoc.v:135198$6772_Y - connect \$1 $not$libresoc.v:135199$6773_Y - connect \$3 $and$libresoc.v:135200$6774_Y - connect \$5 $or$libresoc.v:135201$6775_Y - connect \$7 $not$libresoc.v:135202$6776_Y + connect \$9 $and$libresoc.v:144966$7091_Y + connect \$11 $or$libresoc.v:144967$7092_Y + connect \$13 $not$libresoc.v:144968$7093_Y + connect \$15 $or$libresoc.v:144969$7094_Y + connect \$1 $not$libresoc.v:144970$7095_Y + connect \$3 $and$libresoc.v:144971$7096_Y + connect \$5 $or$libresoc.v:144972$7097_Y + connect \$7 $not$libresoc.v:144973$7098_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:135221.1-135755.10" +attribute \src "libresoc.v:144992.1-145526.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:135609.3-135634.6" - wire width 45 $0\dbus__adr$next[44:0]$6868 - attribute \src "libresoc.v:135459.3-135460.35" + attribute \src "libresoc.v:145380.3-145405.6" + wire width 45 $0\dbus__adr$next[44:0]$7190 + attribute \src "libresoc.v:145230.3-145231.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:135469.3-135496.6" - wire $0\dbus__cyc$next[0:0]$6842 - attribute \src "libresoc.v:135467.3-135468.35" + attribute \src "libresoc.v:145240.3-145267.6" + wire $0\dbus__cyc$next[0:0]$7164 + attribute \src "libresoc.v:145238.3-145239.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:135661.3-135686.6" - wire width 64 $0\dbus__dat_w$next[63:0]$6878 - attribute \src "libresoc.v:135455.3-135456.39" + attribute \src "libresoc.v:145432.3-145457.6" + wire width 64 $0\dbus__dat_w$next[63:0]$7200 + attribute \src "libresoc.v:145226.3-145227.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:135553.3-135583.6" - wire width 8 $0\dbus__sel$next[7:0]$6856 - attribute \src "libresoc.v:135463.3-135464.35" + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $0\dbus__sel$next[7:0]$7178 + attribute \src "libresoc.v:145234.3-145235.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:135497.3-135524.6" - wire $0\dbus__stb$next[0:0]$6848 - attribute \src "libresoc.v:135465.3-135466.35" + attribute \src "libresoc.v:145268.3-145295.6" + wire $0\dbus__stb$next[0:0]$7170 + attribute \src "libresoc.v:145236.3-145237.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:135635.3-135660.6" - wire $0\dbus__we$next[0:0]$6873 - attribute \src "libresoc.v:135457.3-135458.33" + attribute \src "libresoc.v:145406.3-145431.6" + wire $0\dbus__we$next[0:0]$7195 + attribute \src "libresoc.v:145228.3-145229.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:135222.7-135222.20" + attribute \src "libresoc.v:144993.7-144993.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135733.3-135752.6" - wire width 45 $0\m_badaddr_o$next[44:0]$6893 - attribute \src "libresoc.v:135449.3-135450.39" + attribute \src "libresoc.v:145504.3-145523.6" + wire width 45 $0\m_badaddr_o$next[44:0]$7215 + attribute \src "libresoc.v:145220.3-145221.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:135535.3-135552.6" + attribute \src "libresoc.v:145306.3-145323.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:135584.3-135608.6" - wire width 64 $0\m_ld_data_o$next[63:0]$6862 - attribute \src "libresoc.v:135461.3-135462.39" + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $0\m_ld_data_o$next[63:0]$7184 + attribute \src "libresoc.v:145232.3-145233.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:135687.3-135709.6" - wire $0\m_load_err_o$next[0:0]$6883 - attribute \src "libresoc.v:135453.3-135454.41" + attribute \src "libresoc.v:145458.3-145480.6" + wire $0\m_load_err_o$next[0:0]$7205 + attribute \src "libresoc.v:145224.3-145225.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:135710.3-135732.6" - wire $0\m_store_err_o$next[0:0]$6888 - attribute \src "libresoc.v:135451.3-135452.43" + attribute \src "libresoc.v:145481.3-145503.6" + wire $0\m_store_err_o$next[0:0]$7210 + attribute \src "libresoc.v:145222.3-145223.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:135525.3-135534.6" + attribute \src "libresoc.v:145296.3-145305.6" wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:135609.3-135634.6" - wire width 45 $1\dbus__adr$next[44:0]$6869 - attribute \src "libresoc.v:135327.14-135327.42" + attribute \src "libresoc.v:145380.3-145405.6" + wire width 45 $1\dbus__adr$next[44:0]$7191 + attribute \src "libresoc.v:145098.14-145098.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:135469.3-135496.6" - wire $1\dbus__cyc$next[0:0]$6843 - attribute \src "libresoc.v:135332.7-135332.23" + attribute \src "libresoc.v:145240.3-145267.6" + wire $1\dbus__cyc$next[0:0]$7165 + attribute \src "libresoc.v:145103.7-145103.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:135661.3-135686.6" - wire width 64 $1\dbus__dat_w$next[63:0]$6879 - attribute \src "libresoc.v:135339.14-135339.48" + attribute \src "libresoc.v:145432.3-145457.6" + wire width 64 $1\dbus__dat_w$next[63:0]$7201 + attribute \src "libresoc.v:145110.14-145110.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:135553.3-135583.6" - wire width 8 $1\dbus__sel$next[7:0]$6857 - attribute \src "libresoc.v:135346.13-135346.30" + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $1\dbus__sel$next[7:0]$7179 + attribute \src "libresoc.v:145117.13-145117.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:135497.3-135524.6" - wire $1\dbus__stb$next[0:0]$6849 - attribute \src "libresoc.v:135351.7-135351.23" + attribute \src "libresoc.v:145268.3-145295.6" + wire $1\dbus__stb$next[0:0]$7171 + attribute \src "libresoc.v:145122.7-145122.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:135635.3-135660.6" - wire $1\dbus__we$next[0:0]$6874 - attribute \src "libresoc.v:135356.7-135356.22" + attribute \src "libresoc.v:145406.3-145431.6" + wire $1\dbus__we$next[0:0]$7196 + attribute \src "libresoc.v:145127.7-145127.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:135733.3-135752.6" - wire width 45 $1\m_badaddr_o$next[44:0]$6894 - attribute \src "libresoc.v:135360.14-135360.44" + attribute \src "libresoc.v:145504.3-145523.6" + wire width 45 $1\m_badaddr_o$next[44:0]$7216 + attribute \src "libresoc.v:145131.14-145131.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:135535.3-135552.6" + attribute \src "libresoc.v:145306.3-145323.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:135584.3-135608.6" - wire width 64 $1\m_ld_data_o$next[63:0]$6863 - attribute \src "libresoc.v:135367.14-135367.48" + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $1\m_ld_data_o$next[63:0]$7185 + attribute \src "libresoc.v:145138.14-145138.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:135687.3-135709.6" - wire $1\m_load_err_o$next[0:0]$6884 - attribute \src "libresoc.v:135371.7-135371.26" + attribute \src "libresoc.v:145458.3-145480.6" + wire $1\m_load_err_o$next[0:0]$7206 + attribute \src "libresoc.v:145142.7-145142.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:135710.3-135732.6" - wire $1\m_store_err_o$next[0:0]$6889 - attribute \src "libresoc.v:135377.7-135377.27" + attribute \src "libresoc.v:145481.3-145503.6" + wire $1\m_store_err_o$next[0:0]$7211 + attribute \src "libresoc.v:145148.7-145148.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:135525.3-135534.6" + attribute \src "libresoc.v:145296.3-145305.6" wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:135609.3-135634.6" - wire width 45 $2\dbus__adr$next[44:0]$6870 - attribute \src "libresoc.v:135469.3-135496.6" - wire $2\dbus__cyc$next[0:0]$6844 - attribute \src "libresoc.v:135661.3-135686.6" - wire width 64 $2\dbus__dat_w$next[63:0]$6880 - attribute \src "libresoc.v:135553.3-135583.6" - wire width 8 $2\dbus__sel$next[7:0]$6858 - attribute \src "libresoc.v:135497.3-135524.6" - wire $2\dbus__stb$next[0:0]$6850 - attribute \src "libresoc.v:135635.3-135660.6" - wire $2\dbus__we$next[0:0]$6875 - attribute \src "libresoc.v:135733.3-135752.6" - wire width 45 $2\m_badaddr_o$next[44:0]$6895 - attribute \src "libresoc.v:135535.3-135552.6" + attribute \src "libresoc.v:145380.3-145405.6" + wire width 45 $2\dbus__adr$next[44:0]$7192 + attribute \src "libresoc.v:145240.3-145267.6" + wire $2\dbus__cyc$next[0:0]$7166 + attribute \src "libresoc.v:145432.3-145457.6" + wire width 64 $2\dbus__dat_w$next[63:0]$7202 + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $2\dbus__sel$next[7:0]$7180 + attribute \src "libresoc.v:145268.3-145295.6" + wire $2\dbus__stb$next[0:0]$7172 + attribute \src "libresoc.v:145406.3-145431.6" + wire $2\dbus__we$next[0:0]$7197 + attribute \src "libresoc.v:145504.3-145523.6" + wire width 45 $2\m_badaddr_o$next[44:0]$7217 + attribute \src "libresoc.v:145306.3-145323.6" wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:135584.3-135608.6" - wire width 64 $2\m_ld_data_o$next[63:0]$6864 - attribute \src "libresoc.v:135687.3-135709.6" - wire $2\m_load_err_o$next[0:0]$6885 - attribute \src "libresoc.v:135710.3-135732.6" - wire $2\m_store_err_o$next[0:0]$6890 - attribute \src "libresoc.v:135609.3-135634.6" - wire width 45 $3\dbus__adr$next[44:0]$6871 - attribute \src "libresoc.v:135469.3-135496.6" - wire $3\dbus__cyc$next[0:0]$6845 - attribute \src "libresoc.v:135661.3-135686.6" - wire width 64 $3\dbus__dat_w$next[63:0]$6881 - attribute \src "libresoc.v:135553.3-135583.6" - wire width 8 $3\dbus__sel$next[7:0]$6859 - attribute \src "libresoc.v:135497.3-135524.6" - wire $3\dbus__stb$next[0:0]$6851 - attribute \src "libresoc.v:135635.3-135660.6" - wire $3\dbus__we$next[0:0]$6876 - attribute \src "libresoc.v:135733.3-135752.6" - wire width 45 $3\m_badaddr_o$next[44:0]$6896 - attribute \src "libresoc.v:135584.3-135608.6" - wire width 64 $3\m_ld_data_o$next[63:0]$6865 - attribute \src "libresoc.v:135687.3-135709.6" - wire $3\m_load_err_o$next[0:0]$6886 - attribute \src "libresoc.v:135710.3-135732.6" - wire $3\m_store_err_o$next[0:0]$6891 - attribute \src "libresoc.v:135469.3-135496.6" - wire $4\dbus__cyc$next[0:0]$6846 - attribute \src "libresoc.v:135553.3-135583.6" - wire width 8 $4\dbus__sel$next[7:0]$6860 - attribute \src "libresoc.v:135497.3-135524.6" - wire $4\dbus__stb$next[0:0]$6852 - attribute \src "libresoc.v:135584.3-135608.6" - wire width 64 $4\m_ld_data_o$next[63:0]$6866 - attribute \src "libresoc.v:135405.18-135405.116" - wire $and$libresoc.v:135405$6787_Y - attribute \src "libresoc.v:135408.18-135408.111" - wire $and$libresoc.v:135408$6790_Y - attribute \src "libresoc.v:135413.18-135413.116" - wire $and$libresoc.v:135413$6795_Y - attribute \src "libresoc.v:135415.18-135415.111" - wire $and$libresoc.v:135415$6797_Y - attribute \src "libresoc.v:135417.17-135417.114" - wire $and$libresoc.v:135417$6799_Y - attribute \src "libresoc.v:135421.18-135421.116" - wire $and$libresoc.v:135421$6803_Y - attribute \src "libresoc.v:135423.18-135423.111" - wire $and$libresoc.v:135423$6805_Y - attribute \src "libresoc.v:135429.18-135429.116" - wire $and$libresoc.v:135429$6811_Y - attribute \src "libresoc.v:135431.18-135431.111" - wire $and$libresoc.v:135431$6813_Y - attribute \src "libresoc.v:135433.18-135433.116" - wire $and$libresoc.v:135433$6815_Y - attribute \src "libresoc.v:135435.18-135435.111" - wire $and$libresoc.v:135435$6817_Y - attribute \src "libresoc.v:135437.18-135437.116" - wire $and$libresoc.v:135437$6819_Y - attribute \src "libresoc.v:135439.17-135439.108" - wire $and$libresoc.v:135439$6821_Y - attribute \src "libresoc.v:135440.18-135440.111" - wire $and$libresoc.v:135440$6822_Y - attribute \src "libresoc.v:135441.18-135441.120" - wire $and$libresoc.v:135441$6823_Y - attribute \src "libresoc.v:135444.18-135444.120" - wire $and$libresoc.v:135444$6826_Y - attribute \src "libresoc.v:135446.18-135446.120" - wire $and$libresoc.v:135446$6828_Y - attribute \src "libresoc.v:135402.18-135402.110" - wire $not$libresoc.v:135402$6784_Y - attribute \src "libresoc.v:135407.18-135407.110" - wire $not$libresoc.v:135407$6789_Y - attribute \src "libresoc.v:135410.18-135410.110" - wire $not$libresoc.v:135410$6792_Y - attribute \src "libresoc.v:135414.18-135414.110" - wire $not$libresoc.v:135414$6796_Y - attribute \src "libresoc.v:135418.18-135418.110" - wire $not$libresoc.v:135418$6800_Y - attribute \src "libresoc.v:135422.18-135422.110" - wire $not$libresoc.v:135422$6804_Y - attribute \src "libresoc.v:135425.18-135425.110" - wire $not$libresoc.v:135425$6807_Y - attribute \src "libresoc.v:135428.17-135428.109" - wire $not$libresoc.v:135428$6810_Y - attribute \src "libresoc.v:135430.18-135430.110" - wire $not$libresoc.v:135430$6812_Y - attribute \src "libresoc.v:135434.18-135434.110" - wire $not$libresoc.v:135434$6816_Y - attribute \src "libresoc.v:135438.18-135438.110" - wire $not$libresoc.v:135438$6820_Y - attribute \src "libresoc.v:135442.18-135442.110" - wire $not$libresoc.v:135442$6824_Y - attribute \src "libresoc.v:135443.18-135443.109" - wire $not$libresoc.v:135443$6825_Y - attribute \src "libresoc.v:135445.18-135445.110" - wire $not$libresoc.v:135445$6827_Y - attribute \src "libresoc.v:135447.18-135447.110" - wire $not$libresoc.v:135447$6829_Y - attribute \src "libresoc.v:135401.17-135401.119" - wire $or$libresoc.v:135401$6783_Y - attribute \src "libresoc.v:135403.18-135403.110" - wire $or$libresoc.v:135403$6785_Y - attribute \src "libresoc.v:135404.18-135404.114" - wire $or$libresoc.v:135404$6786_Y - attribute \src "libresoc.v:135406.17-135406.113" - wire $or$libresoc.v:135406$6788_Y - attribute \src "libresoc.v:135409.18-135409.120" - wire $or$libresoc.v:135409$6791_Y - attribute \src "libresoc.v:135411.18-135411.111" - wire $or$libresoc.v:135411$6793_Y - attribute \src "libresoc.v:135412.18-135412.114" - wire $or$libresoc.v:135412$6794_Y - attribute \src "libresoc.v:135416.18-135416.120" - wire $or$libresoc.v:135416$6798_Y - attribute \src "libresoc.v:135419.18-135419.111" - wire $or$libresoc.v:135419$6801_Y - attribute \src "libresoc.v:135420.18-135420.114" - wire $or$libresoc.v:135420$6802_Y - attribute \src "libresoc.v:135424.18-135424.120" - wire $or$libresoc.v:135424$6806_Y - attribute \src "libresoc.v:135426.18-135426.111" - wire $or$libresoc.v:135426$6808_Y - attribute \src "libresoc.v:135427.18-135427.114" - wire $or$libresoc.v:135427$6809_Y - attribute \src "libresoc.v:135432.18-135432.114" - wire $or$libresoc.v:135432$6814_Y - attribute \src "libresoc.v:135436.18-135436.114" - wire $or$libresoc.v:135436$6818_Y - attribute \src "libresoc.v:135448.18-135448.127" - wire $or$libresoc.v:135448$6830_Y + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $2\m_ld_data_o$next[63:0]$7186 + attribute \src "libresoc.v:145458.3-145480.6" + wire $2\m_load_err_o$next[0:0]$7207 + attribute \src "libresoc.v:145481.3-145503.6" + wire $2\m_store_err_o$next[0:0]$7212 + attribute \src "libresoc.v:145380.3-145405.6" + wire width 45 $3\dbus__adr$next[44:0]$7193 + attribute \src "libresoc.v:145240.3-145267.6" + wire $3\dbus__cyc$next[0:0]$7167 + attribute \src "libresoc.v:145432.3-145457.6" + wire width 64 $3\dbus__dat_w$next[63:0]$7203 + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $3\dbus__sel$next[7:0]$7181 + attribute \src "libresoc.v:145268.3-145295.6" + wire $3\dbus__stb$next[0:0]$7173 + attribute \src "libresoc.v:145406.3-145431.6" + wire $3\dbus__we$next[0:0]$7198 + attribute \src "libresoc.v:145504.3-145523.6" + wire width 45 $3\m_badaddr_o$next[44:0]$7218 + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $3\m_ld_data_o$next[63:0]$7187 + attribute \src "libresoc.v:145458.3-145480.6" + wire $3\m_load_err_o$next[0:0]$7208 + attribute \src "libresoc.v:145481.3-145503.6" + wire $3\m_store_err_o$next[0:0]$7213 + attribute \src "libresoc.v:145240.3-145267.6" + wire $4\dbus__cyc$next[0:0]$7168 + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $4\dbus__sel$next[7:0]$7182 + attribute \src "libresoc.v:145268.3-145295.6" + wire $4\dbus__stb$next[0:0]$7174 + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $4\m_ld_data_o$next[63:0]$7188 + attribute \src "libresoc.v:145176.18-145176.116" + wire $and$libresoc.v:145176$7109_Y + attribute \src "libresoc.v:145179.18-145179.111" + wire $and$libresoc.v:145179$7112_Y + attribute \src "libresoc.v:145184.18-145184.116" + wire $and$libresoc.v:145184$7117_Y + attribute \src "libresoc.v:145186.18-145186.111" + wire $and$libresoc.v:145186$7119_Y + attribute \src "libresoc.v:145188.17-145188.114" + wire $and$libresoc.v:145188$7121_Y + attribute \src "libresoc.v:145192.18-145192.116" + wire $and$libresoc.v:145192$7125_Y + attribute \src "libresoc.v:145194.18-145194.111" + wire $and$libresoc.v:145194$7127_Y + attribute \src "libresoc.v:145200.18-145200.116" + wire $and$libresoc.v:145200$7133_Y + attribute \src "libresoc.v:145202.18-145202.111" + wire $and$libresoc.v:145202$7135_Y + attribute \src "libresoc.v:145204.18-145204.116" + wire $and$libresoc.v:145204$7137_Y + attribute \src "libresoc.v:145206.18-145206.111" + wire $and$libresoc.v:145206$7139_Y + attribute \src "libresoc.v:145208.18-145208.116" + wire $and$libresoc.v:145208$7141_Y + attribute \src "libresoc.v:145210.17-145210.108" + wire $and$libresoc.v:145210$7143_Y + attribute \src "libresoc.v:145211.18-145211.111" + wire $and$libresoc.v:145211$7144_Y + attribute \src "libresoc.v:145212.18-145212.120" + wire $and$libresoc.v:145212$7145_Y + attribute \src "libresoc.v:145215.18-145215.120" + wire $and$libresoc.v:145215$7148_Y + attribute \src "libresoc.v:145217.18-145217.120" + wire $and$libresoc.v:145217$7150_Y + attribute \src "libresoc.v:145173.18-145173.110" + wire $not$libresoc.v:145173$7106_Y + attribute \src "libresoc.v:145178.18-145178.110" + wire $not$libresoc.v:145178$7111_Y + attribute \src "libresoc.v:145181.18-145181.110" + wire $not$libresoc.v:145181$7114_Y + attribute \src "libresoc.v:145185.18-145185.110" + wire $not$libresoc.v:145185$7118_Y + attribute \src "libresoc.v:145189.18-145189.110" + wire $not$libresoc.v:145189$7122_Y + attribute \src "libresoc.v:145193.18-145193.110" + wire $not$libresoc.v:145193$7126_Y + attribute \src "libresoc.v:145196.18-145196.110" + wire $not$libresoc.v:145196$7129_Y + attribute \src "libresoc.v:145199.17-145199.109" + wire $not$libresoc.v:145199$7132_Y + attribute \src "libresoc.v:145201.18-145201.110" + wire $not$libresoc.v:145201$7134_Y + attribute \src "libresoc.v:145205.18-145205.110" + wire $not$libresoc.v:145205$7138_Y + attribute \src "libresoc.v:145209.18-145209.110" + wire $not$libresoc.v:145209$7142_Y + attribute \src "libresoc.v:145213.18-145213.110" + wire $not$libresoc.v:145213$7146_Y + attribute \src "libresoc.v:145214.18-145214.109" + wire $not$libresoc.v:145214$7147_Y + attribute \src "libresoc.v:145216.18-145216.110" + wire $not$libresoc.v:145216$7149_Y + attribute \src "libresoc.v:145218.18-145218.110" + wire $not$libresoc.v:145218$7151_Y + attribute \src "libresoc.v:145172.17-145172.119" + wire $or$libresoc.v:145172$7105_Y + attribute \src "libresoc.v:145174.18-145174.110" + wire $or$libresoc.v:145174$7107_Y + attribute \src "libresoc.v:145175.18-145175.114" + wire $or$libresoc.v:145175$7108_Y + attribute \src "libresoc.v:145177.17-145177.113" + wire $or$libresoc.v:145177$7110_Y + attribute \src "libresoc.v:145180.18-145180.120" + wire $or$libresoc.v:145180$7113_Y + attribute \src "libresoc.v:145182.18-145182.111" + wire $or$libresoc.v:145182$7115_Y + attribute \src "libresoc.v:145183.18-145183.114" + wire $or$libresoc.v:145183$7116_Y + attribute \src "libresoc.v:145187.18-145187.120" + wire $or$libresoc.v:145187$7120_Y + attribute \src "libresoc.v:145190.18-145190.111" + wire $or$libresoc.v:145190$7123_Y + attribute \src "libresoc.v:145191.18-145191.114" + wire $or$libresoc.v:145191$7124_Y + attribute \src "libresoc.v:145195.18-145195.120" + wire $or$libresoc.v:145195$7128_Y + attribute \src "libresoc.v:145197.18-145197.111" + wire $or$libresoc.v:145197$7130_Y + attribute \src "libresoc.v:145198.18-145198.114" + wire $or$libresoc.v:145198$7131_Y + attribute \src "libresoc.v:145203.18-145203.114" + wire $or$libresoc.v:145203$7136_Y + attribute \src "libresoc.v:145207.18-145207.114" + wire $or$libresoc.v:145207$7140_Y + attribute \src "libresoc.v:145219.18-145219.127" + wire $or$libresoc.v:145219$7152_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" @@ -284829,9 +303624,9 @@ module \lsmem wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 13 \dbus__ack @@ -284863,7 +303658,7 @@ module \lsmem wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:135222.7-135222.15" + attribute \src "libresoc.v:144993.7-144993.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o @@ -284887,7 +303682,7 @@ module \lsmem wire \m_store_err_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" wire input 9 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 11 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" wire width 48 input 3 \x_addr_i @@ -284906,7 +303701,7 @@ module \lsmem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135405$6787 + cell $and $and$libresoc.v:145176$7109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284914,10 +303709,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:135405$6787_Y + connect \Y $and$libresoc.v:145176$7109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135408$6790 + cell $and $and$libresoc.v:145179$7112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284925,10 +303720,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:135408$6790_Y + connect \Y $and$libresoc.v:145179$7112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135413$6795 + cell $and $and$libresoc.v:145184$7117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284936,10 +303731,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:135413$6795_Y + connect \Y $and$libresoc.v:145184$7117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135415$6797 + cell $and $and$libresoc.v:145186$7119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284947,10 +303742,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:135415$6797_Y + connect \Y $and$libresoc.v:145186$7119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135417$6799 + cell $and $and$libresoc.v:145188$7121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284958,10 +303753,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:135417$6799_Y + connect \Y $and$libresoc.v:145188$7121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135421$6803 + cell $and $and$libresoc.v:145192$7125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284969,10 +303764,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:135421$6803_Y + connect \Y $and$libresoc.v:145192$7125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135423$6805 + cell $and $and$libresoc.v:145194$7127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284980,10 +303775,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:135423$6805_Y + connect \Y $and$libresoc.v:145194$7127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135429$6811 + cell $and $and$libresoc.v:145200$7133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284991,10 +303786,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:135429$6811_Y + connect \Y $and$libresoc.v:145200$7133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135431$6813 + cell $and $and$libresoc.v:145202$7135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285002,10 +303797,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:135431$6813_Y + connect \Y $and$libresoc.v:145202$7135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135433$6815 + cell $and $and$libresoc.v:145204$7137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285013,10 +303808,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:135433$6815_Y + connect \Y $and$libresoc.v:145204$7137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135435$6817 + cell $and $and$libresoc.v:145206$7139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285024,10 +303819,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:135435$6817_Y + connect \Y $and$libresoc.v:145206$7139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135437$6819 + cell $and $and$libresoc.v:145208$7141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285035,10 +303830,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:135437$6819_Y + connect \Y $and$libresoc.v:145208$7141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135439$6821 + cell $and $and$libresoc.v:145210$7143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285046,10 +303841,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:135439$6821_Y + connect \Y $and$libresoc.v:145210$7143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:135440$6822 + cell $and $and$libresoc.v:145211$7144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285057,10 +303852,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:135440$6822_Y + connect \Y $and$libresoc.v:145211$7144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:135441$6823 + cell $and $and$libresoc.v:145212$7145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285068,10 +303863,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:135441$6823_Y + connect \Y $and$libresoc.v:145212$7145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:135444$6826 + cell $and $and$libresoc.v:145215$7148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285079,10 +303874,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:135444$6826_Y + connect \Y $and$libresoc.v:145215$7148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:135446$6828 + cell $and $and$libresoc.v:145217$7150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285090,130 +303885,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:135446$6828_Y + connect \Y $and$libresoc.v:145217$7150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:135402$6784 + cell $not $not$libresoc.v:145173$7106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:135402$6784_Y + connect \Y $not$libresoc.v:145173$7106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:135407$6789 + cell $not $not$libresoc.v:145178$7111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:135407$6789_Y + connect \Y $not$libresoc.v:145178$7111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:135410$6792 + cell $not $not$libresoc.v:145181$7114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:135410$6792_Y + connect \Y $not$libresoc.v:145181$7114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:135414$6796 + cell $not $not$libresoc.v:145185$7118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:135414$6796_Y + connect \Y $not$libresoc.v:145185$7118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:135418$6800 + cell $not $not$libresoc.v:145189$7122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:135418$6800_Y + connect \Y $not$libresoc.v:145189$7122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:135422$6804 + cell $not $not$libresoc.v:145193$7126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:135422$6804_Y + connect \Y $not$libresoc.v:145193$7126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:135425$6807 + cell $not $not$libresoc.v:145196$7129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:135425$6807_Y + connect \Y $not$libresoc.v:145196$7129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:135428$6810 + cell $not $not$libresoc.v:145199$7132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:135428$6810_Y + connect \Y $not$libresoc.v:145199$7132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:135430$6812 + cell $not $not$libresoc.v:145201$7134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:135430$6812_Y + connect \Y $not$libresoc.v:145201$7134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:135434$6816 + cell $not $not$libresoc.v:145205$7138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:135434$6816_Y + connect \Y $not$libresoc.v:145205$7138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:135438$6820 + cell $not $not$libresoc.v:145209$7142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:135438$6820_Y + connect \Y $not$libresoc.v:145209$7142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:135442$6824 + cell $not $not$libresoc.v:145213$7146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:135442$6824_Y + connect \Y $not$libresoc.v:145213$7146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:135443$6825 + cell $not $not$libresoc.v:145214$7147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:135443$6825_Y + connect \Y $not$libresoc.v:145214$7147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:135445$6827 + cell $not $not$libresoc.v:145216$7149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:135445$6827_Y + connect \Y $not$libresoc.v:145216$7149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:135447$6829 + cell $not $not$libresoc.v:145218$7151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:135447$6829_Y + connect \Y $not$libresoc.v:145218$7151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135401$6783 + cell $or $or$libresoc.v:145172$7105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285221,10 +304016,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:135401$6783_Y + connect \Y $or$libresoc.v:145172$7105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135403$6785 + cell $or $or$libresoc.v:145174$7107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285232,10 +304027,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:135403$6785_Y + connect \Y $or$libresoc.v:145174$7107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135404$6786 + cell $or $or$libresoc.v:145175$7108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285243,10 +304038,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:135404$6786_Y + connect \Y $or$libresoc.v:145175$7108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135406$6788 + cell $or $or$libresoc.v:145177$7110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285254,10 +304049,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:135406$6788_Y + connect \Y $or$libresoc.v:145177$7110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135409$6791 + cell $or $or$libresoc.v:145180$7113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285265,10 +304060,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:135409$6791_Y + connect \Y $or$libresoc.v:145180$7113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135411$6793 + cell $or $or$libresoc.v:145182$7115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285276,10 +304071,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:135411$6793_Y + connect \Y $or$libresoc.v:145182$7115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135412$6794 + cell $or $or$libresoc.v:145183$7116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285287,10 +304082,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:135412$6794_Y + connect \Y $or$libresoc.v:145183$7116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135416$6798 + cell $or $or$libresoc.v:145187$7120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285298,10 +304093,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:135416$6798_Y + connect \Y $or$libresoc.v:145187$7120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135419$6801 + cell $or $or$libresoc.v:145190$7123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285309,10 +304104,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:135419$6801_Y + connect \Y $or$libresoc.v:145190$7123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135420$6802 + cell $or $or$libresoc.v:145191$7124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285320,10 +304115,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:135420$6802_Y + connect \Y $or$libresoc.v:145191$7124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135424$6806 + cell $or $or$libresoc.v:145195$7128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285331,10 +304126,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:135424$6806_Y + connect \Y $or$libresoc.v:145195$7128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135426$6808 + cell $or $or$libresoc.v:145197$7130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285342,10 +304137,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:135426$6808_Y + connect \Y $or$libresoc.v:145197$7130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135427$6809 + cell $or $or$libresoc.v:145198$7131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285353,10 +304148,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:135427$6809_Y + connect \Y $or$libresoc.v:145198$7131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135432$6814 + cell $or $or$libresoc.v:145203$7136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285364,10 +304159,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:135432$6814_Y + connect \Y $or$libresoc.v:145203$7136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135436$6818 + cell $or $or$libresoc.v:145207$7140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285375,10 +304170,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:135436$6818_Y + connect \Y $or$libresoc.v:145207$7140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:135448$6830 + cell $or $or$libresoc.v:145219$7152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285386,175 +304181,175 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:135448$6830_Y + connect \Y $or$libresoc.v:145219$7152_Y end - attribute \src "libresoc.v:135222.7-135222.20" - process $proc$libresoc.v:135222$6897 + attribute \src "libresoc.v:144993.7-144993.20" + process $proc$libresoc.v:144993$7219 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135327.14-135327.42" - process $proc$libresoc.v:135327$6898 + attribute \src "libresoc.v:145098.14-145098.42" + process $proc$libresoc.v:145098$7220 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:135332.7-135332.23" - process $proc$libresoc.v:135332$6899 + attribute \src "libresoc.v:145103.7-145103.23" + process $proc$libresoc.v:145103$7221 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:135339.14-135339.48" - process $proc$libresoc.v:135339$6900 + attribute \src "libresoc.v:145110.14-145110.48" + process $proc$libresoc.v:145110$7222 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:135346.13-135346.30" - process $proc$libresoc.v:135346$6901 + attribute \src "libresoc.v:145117.13-145117.30" + process $proc$libresoc.v:145117$7223 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:135351.7-135351.23" - process $proc$libresoc.v:135351$6902 + attribute \src "libresoc.v:145122.7-145122.23" + process $proc$libresoc.v:145122$7224 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:135356.7-135356.22" - process $proc$libresoc.v:135356$6903 + attribute \src "libresoc.v:145127.7-145127.22" + process $proc$libresoc.v:145127$7225 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:135360.14-135360.44" - process $proc$libresoc.v:135360$6904 + attribute \src "libresoc.v:145131.14-145131.44" + process $proc$libresoc.v:145131$7226 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:135367.14-135367.48" - process $proc$libresoc.v:135367$6905 + attribute \src "libresoc.v:145138.14-145138.48" + process $proc$libresoc.v:145138$7227 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:135371.7-135371.26" - process $proc$libresoc.v:135371$6906 + attribute \src "libresoc.v:145142.7-145142.26" + process $proc$libresoc.v:145142$7228 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:135377.7-135377.27" - process $proc$libresoc.v:135377$6907 + attribute \src "libresoc.v:145148.7-145148.27" + process $proc$libresoc.v:145148$7229 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:135449.3-135450.39" - process $proc$libresoc.v:135449$6831 + attribute \src "libresoc.v:145220.3-145221.39" + process $proc$libresoc.v:145220$7153 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:135451.3-135452.43" - process $proc$libresoc.v:135451$6832 + attribute \src "libresoc.v:145222.3-145223.43" + process $proc$libresoc.v:145222$7154 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:135453.3-135454.41" - process $proc$libresoc.v:135453$6833 + attribute \src "libresoc.v:145224.3-145225.41" + process $proc$libresoc.v:145224$7155 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:135455.3-135456.39" - process $proc$libresoc.v:135455$6834 + attribute \src "libresoc.v:145226.3-145227.39" + process $proc$libresoc.v:145226$7156 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:135457.3-135458.33" - process $proc$libresoc.v:135457$6835 + attribute \src "libresoc.v:145228.3-145229.33" + process $proc$libresoc.v:145228$7157 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:135459.3-135460.35" - process $proc$libresoc.v:135459$6836 + attribute \src "libresoc.v:145230.3-145231.35" + process $proc$libresoc.v:145230$7158 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:135461.3-135462.39" - process $proc$libresoc.v:135461$6837 + attribute \src "libresoc.v:145232.3-145233.39" + process $proc$libresoc.v:145232$7159 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:135463.3-135464.35" - process $proc$libresoc.v:135463$6838 + attribute \src "libresoc.v:145234.3-145235.35" + process $proc$libresoc.v:145234$7160 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:135465.3-135466.35" - process $proc$libresoc.v:135465$6839 + attribute \src "libresoc.v:145236.3-145237.35" + process $proc$libresoc.v:145236$7161 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:135467.3-135468.35" - process $proc$libresoc.v:135467$6840 + attribute \src "libresoc.v:145238.3-145239.35" + process $proc$libresoc.v:145238$7162 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:135469.3-135496.6" - process $proc$libresoc.v:135469$6841 + attribute \src "libresoc.v:145240.3-145267.6" + process $proc$libresoc.v:145240$7163 assign { } { } assign { } { } assign { } { } - assign $0\dbus__cyc$next[0:0]$6842 $4\dbus__cyc$next[0:0]$6846 - attribute \src "libresoc.v:135470.5-135470.29" + assign $0\dbus__cyc$next[0:0]$7164 $4\dbus__cyc$next[0:0]$7168 + attribute \src "libresoc.v:145241.5-145241.29" switch \initial - attribute \src "libresoc.v:135470.9-135470.17" + attribute \src "libresoc.v:145241.9-145241.17" case 1'1 case end @@ -285563,53 +304358,53 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__cyc$next[0:0]$6843 $2\dbus__cyc$next[0:0]$6844 + assign $1\dbus__cyc$next[0:0]$7165 $2\dbus__cyc$next[0:0]$7166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$7 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__cyc$next[0:0]$6844 $3\dbus__cyc$next[0:0]$6845 + assign $2\dbus__cyc$next[0:0]$7166 $3\dbus__cyc$next[0:0]$7167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__cyc$next[0:0]$6845 1'0 + assign $3\dbus__cyc$next[0:0]$7167 1'0 case - assign $3\dbus__cyc$next[0:0]$6845 \dbus__cyc + assign $3\dbus__cyc$next[0:0]$7167 \dbus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__cyc$next[0:0]$6844 1'1 + assign $2\dbus__cyc$next[0:0]$7166 1'1 case - assign $2\dbus__cyc$next[0:0]$6844 \dbus__cyc + assign $2\dbus__cyc$next[0:0]$7166 \dbus__cyc end case - assign $1\dbus__cyc$next[0:0]$6843 \dbus__cyc + assign $1\dbus__cyc$next[0:0]$7165 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__cyc$next[0:0]$6846 1'0 + assign $4\dbus__cyc$next[0:0]$7168 1'0 case - assign $4\dbus__cyc$next[0:0]$6846 $1\dbus__cyc$next[0:0]$6843 + assign $4\dbus__cyc$next[0:0]$7168 $1\dbus__cyc$next[0:0]$7165 end sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$6842 + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7164 end - attribute \src "libresoc.v:135497.3-135524.6" - process $proc$libresoc.v:135497$6847 + attribute \src "libresoc.v:145268.3-145295.6" + process $proc$libresoc.v:145268$7169 assign { } { } assign { } { } assign { } { } - assign $0\dbus__stb$next[0:0]$6848 $4\dbus__stb$next[0:0]$6852 - attribute \src "libresoc.v:135498.5-135498.29" + assign $0\dbus__stb$next[0:0]$7170 $4\dbus__stb$next[0:0]$7174 + attribute \src "libresoc.v:145269.5-145269.29" switch \initial - attribute \src "libresoc.v:135498.9-135498.17" + attribute \src "libresoc.v:145269.9-145269.17" case 1'1 case end @@ -285618,52 +304413,52 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__stb$next[0:0]$6849 $2\dbus__stb$next[0:0]$6850 + assign $1\dbus__stb$next[0:0]$7171 $2\dbus__stb$next[0:0]$7172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$21 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__stb$next[0:0]$6850 $3\dbus__stb$next[0:0]$6851 + assign $2\dbus__stb$next[0:0]$7172 $3\dbus__stb$next[0:0]$7173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__stb$next[0:0]$6851 1'0 + assign $3\dbus__stb$next[0:0]$7173 1'0 case - assign $3\dbus__stb$next[0:0]$6851 \dbus__stb + assign $3\dbus__stb$next[0:0]$7173 \dbus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__stb$next[0:0]$6850 1'1 + assign $2\dbus__stb$next[0:0]$7172 1'1 case - assign $2\dbus__stb$next[0:0]$6850 \dbus__stb + assign $2\dbus__stb$next[0:0]$7172 \dbus__stb end case - assign $1\dbus__stb$next[0:0]$6849 \dbus__stb + assign $1\dbus__stb$next[0:0]$7171 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__stb$next[0:0]$6852 1'0 + assign $4\dbus__stb$next[0:0]$7174 1'0 case - assign $4\dbus__stb$next[0:0]$6852 $1\dbus__stb$next[0:0]$6849 + assign $4\dbus__stb$next[0:0]$7174 $1\dbus__stb$next[0:0]$7171 end sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$6848 + update \dbus__stb$next $0\dbus__stb$next[0:0]$7170 end - attribute \src "libresoc.v:135525.3-135534.6" - process $proc$libresoc.v:135525$6853 + attribute \src "libresoc.v:145296.3-145305.6" + process $proc$libresoc.v:145296$7175 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:135526.5-135526.29" + attribute \src "libresoc.v:145297.5-145297.29" switch \initial - attribute \src "libresoc.v:135526.9-135526.17" + attribute \src "libresoc.v:145297.9-145297.17" case 1'1 case end @@ -285679,14 +304474,14 @@ module \lsmem sync always update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:135535.3-135552.6" - process $proc$libresoc.v:135535$6854 + attribute \src "libresoc.v:145306.3-145323.6" + process $proc$libresoc.v:145306$7176 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:135536.5-135536.29" + attribute \src "libresoc.v:145307.5-145307.29" switch \initial - attribute \src "libresoc.v:135536.9-135536.17" + attribute \src "libresoc.v:145307.9-145307.17" case 1'1 case end @@ -285713,15 +304508,15 @@ module \lsmem sync always update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:135553.3-135583.6" - process $proc$libresoc.v:135553$6855 + attribute \src "libresoc.v:145324.3-145354.6" + process $proc$libresoc.v:145324$7177 assign { } { } assign { } { } assign { } { } - assign $0\dbus__sel$next[7:0]$6856 $4\dbus__sel$next[7:0]$6860 - attribute \src "libresoc.v:135554.5-135554.29" + assign $0\dbus__sel$next[7:0]$7178 $4\dbus__sel$next[7:0]$7182 + attribute \src "libresoc.v:145325.5-145325.29" switch \initial - attribute \src "libresoc.v:135554.9-135554.17" + attribute \src "libresoc.v:145325.9-145325.17" case 1'1 case end @@ -285730,55 +304525,55 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__sel$next[7:0]$6857 $2\dbus__sel$next[7:0]$6858 + assign $1\dbus__sel$next[7:0]$7179 $2\dbus__sel$next[7:0]$7180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$35 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__sel$next[7:0]$6858 $3\dbus__sel$next[7:0]$6859 + assign $2\dbus__sel$next[7:0]$7180 $3\dbus__sel$next[7:0]$7181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__sel$next[7:0]$6859 8'00000000 + assign $3\dbus__sel$next[7:0]$7181 8'00000000 case - assign $3\dbus__sel$next[7:0]$6859 \dbus__sel + assign $3\dbus__sel$next[7:0]$7181 \dbus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__sel$next[7:0]$6858 \x_mask_i + assign $2\dbus__sel$next[7:0]$7180 \x_mask_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__sel$next[7:0]$6858 8'00000000 + assign $2\dbus__sel$next[7:0]$7180 8'00000000 end case - assign $1\dbus__sel$next[7:0]$6857 \dbus__sel + assign $1\dbus__sel$next[7:0]$7179 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__sel$next[7:0]$6860 8'00000000 + assign $4\dbus__sel$next[7:0]$7182 8'00000000 case - assign $4\dbus__sel$next[7:0]$6860 $1\dbus__sel$next[7:0]$6857 + assign $4\dbus__sel$next[7:0]$7182 $1\dbus__sel$next[7:0]$7179 end sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$6856 + update \dbus__sel$next $0\dbus__sel$next[7:0]$7178 end - attribute \src "libresoc.v:135584.3-135608.6" - process $proc$libresoc.v:135584$6861 + attribute \src "libresoc.v:145355.3-145379.6" + process $proc$libresoc.v:145355$7183 assign { } { } assign { } { } assign { } { } - assign $0\m_ld_data_o$next[63:0]$6862 $4\m_ld_data_o$next[63:0]$6866 - attribute \src "libresoc.v:135585.5-135585.29" + assign $0\m_ld_data_o$next[63:0]$7184 $4\m_ld_data_o$next[63:0]$7188 + attribute \src "libresoc.v:145356.5-145356.29" switch \initial - attribute \src "libresoc.v:135585.9-135585.17" + attribute \src "libresoc.v:145356.9-145356.17" case 1'1 case end @@ -285787,49 +304582,49 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_ld_data_o$next[63:0]$6863 $2\m_ld_data_o$next[63:0]$6864 + assign $1\m_ld_data_o$next[63:0]$7185 $2\m_ld_data_o$next[63:0]$7186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$49 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_ld_data_o$next[63:0]$6864 $3\m_ld_data_o$next[63:0]$6865 + assign $2\m_ld_data_o$next[63:0]$7186 $3\m_ld_data_o$next[63:0]$7187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_ld_data_o$next[63:0]$6865 \dbus__dat_r + assign $3\m_ld_data_o$next[63:0]$7187 \dbus__dat_r case - assign $3\m_ld_data_o$next[63:0]$6865 \m_ld_data_o + assign $3\m_ld_data_o$next[63:0]$7187 \m_ld_data_o end case - assign $2\m_ld_data_o$next[63:0]$6864 \m_ld_data_o + assign $2\m_ld_data_o$next[63:0]$7186 \m_ld_data_o end case - assign $1\m_ld_data_o$next[63:0]$6863 \m_ld_data_o + assign $1\m_ld_data_o$next[63:0]$7185 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\m_ld_data_o$next[63:0]$6866 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\m_ld_data_o$next[63:0]$7188 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\m_ld_data_o$next[63:0]$6866 $1\m_ld_data_o$next[63:0]$6863 + assign $4\m_ld_data_o$next[63:0]$7188 $1\m_ld_data_o$next[63:0]$7185 end sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$6862 + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7184 end - attribute \src "libresoc.v:135609.3-135634.6" - process $proc$libresoc.v:135609$6867 + attribute \src "libresoc.v:145380.3-145405.6" + process $proc$libresoc.v:145380$7189 assign { } { } assign { } { } assign { } { } - assign $0\dbus__adr$next[44:0]$6868 $3\dbus__adr$next[44:0]$6871 - attribute \src "libresoc.v:135610.5-135610.29" + assign $0\dbus__adr$next[44:0]$7190 $3\dbus__adr$next[44:0]$7193 + attribute \src "libresoc.v:145381.5-145381.29" switch \initial - attribute \src "libresoc.v:135610.9-135610.17" + attribute \src "libresoc.v:145381.9-145381.17" case 1'1 case end @@ -285838,45 +304633,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__adr$next[44:0]$6869 $2\dbus__adr$next[44:0]$6870 + assign $1\dbus__adr$next[44:0]$7191 $2\dbus__adr$next[44:0]$7192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$63 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__adr$next[44:0]$6870 \dbus__adr + assign $2\dbus__adr$next[44:0]$7192 \dbus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__adr$next[44:0]$6870 \x_addr_i [47:3] + assign $2\dbus__adr$next[44:0]$7192 \x_addr_i [47:3] attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__adr$next[44:0]$6870 45'000000000000000000000000000000000000000000000 + assign $2\dbus__adr$next[44:0]$7192 45'000000000000000000000000000000000000000000000 end case - assign $1\dbus__adr$next[44:0]$6869 \dbus__adr + assign $1\dbus__adr$next[44:0]$7191 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__adr$next[44:0]$6871 45'000000000000000000000000000000000000000000000 + assign $3\dbus__adr$next[44:0]$7193 45'000000000000000000000000000000000000000000000 case - assign $3\dbus__adr$next[44:0]$6871 $1\dbus__adr$next[44:0]$6869 + assign $3\dbus__adr$next[44:0]$7193 $1\dbus__adr$next[44:0]$7191 end sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$6868 + update \dbus__adr$next $0\dbus__adr$next[44:0]$7190 end - attribute \src "libresoc.v:135635.3-135660.6" - process $proc$libresoc.v:135635$6872 + attribute \src "libresoc.v:145406.3-145431.6" + process $proc$libresoc.v:145406$7194 assign { } { } assign { } { } assign { } { } - assign $0\dbus__we$next[0:0]$6873 $3\dbus__we$next[0:0]$6876 - attribute \src "libresoc.v:135636.5-135636.29" + assign $0\dbus__we$next[0:0]$7195 $3\dbus__we$next[0:0]$7198 + attribute \src "libresoc.v:145407.5-145407.29" switch \initial - attribute \src "libresoc.v:135636.9-135636.17" + attribute \src "libresoc.v:145407.9-145407.17" case 1'1 case end @@ -285885,45 +304680,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__we$next[0:0]$6874 $2\dbus__we$next[0:0]$6875 + assign $1\dbus__we$next[0:0]$7196 $2\dbus__we$next[0:0]$7197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$71 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__we$next[0:0]$6875 \dbus__we + assign $2\dbus__we$next[0:0]$7197 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__we$next[0:0]$6875 \x_st_i + assign $2\dbus__we$next[0:0]$7197 \x_st_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__we$next[0:0]$6875 1'0 + assign $2\dbus__we$next[0:0]$7197 1'0 end case - assign $1\dbus__we$next[0:0]$6874 \dbus__we + assign $1\dbus__we$next[0:0]$7196 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__we$next[0:0]$6876 1'0 + assign $3\dbus__we$next[0:0]$7198 1'0 case - assign $3\dbus__we$next[0:0]$6876 $1\dbus__we$next[0:0]$6874 + assign $3\dbus__we$next[0:0]$7198 $1\dbus__we$next[0:0]$7196 end sync always - update \dbus__we$next $0\dbus__we$next[0:0]$6873 + update \dbus__we$next $0\dbus__we$next[0:0]$7195 end - attribute \src "libresoc.v:135661.3-135686.6" - process $proc$libresoc.v:135661$6877 + attribute \src "libresoc.v:145432.3-145457.6" + process $proc$libresoc.v:145432$7199 assign { } { } assign { } { } assign { } { } - assign $0\dbus__dat_w$next[63:0]$6878 $3\dbus__dat_w$next[63:0]$6881 - attribute \src "libresoc.v:135662.5-135662.29" + assign $0\dbus__dat_w$next[63:0]$7200 $3\dbus__dat_w$next[63:0]$7203 + attribute \src "libresoc.v:145433.5-145433.29" switch \initial - attribute \src "libresoc.v:135662.9-135662.17" + attribute \src "libresoc.v:145433.9-145433.17" case 1'1 case end @@ -285932,45 +304727,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__dat_w$next[63:0]$6879 $2\dbus__dat_w$next[63:0]$6880 + assign $1\dbus__dat_w$next[63:0]$7201 $2\dbus__dat_w$next[63:0]$7202 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$79 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__dat_w$next[63:0]$6880 \dbus__dat_w + assign $2\dbus__dat_w$next[63:0]$7202 \dbus__dat_w attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__dat_w$next[63:0]$6880 \x_st_data_i + assign $2\dbus__dat_w$next[63:0]$7202 \x_st_data_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__dat_w$next[63:0]$6880 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dbus__dat_w$next[63:0]$7202 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\dbus__dat_w$next[63:0]$6879 \dbus__dat_w + assign $1\dbus__dat_w$next[63:0]$7201 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__dat_w$next[63:0]$6881 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dbus__dat_w$next[63:0]$7203 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dbus__dat_w$next[63:0]$6881 $1\dbus__dat_w$next[63:0]$6879 + assign $3\dbus__dat_w$next[63:0]$7203 $1\dbus__dat_w$next[63:0]$7201 end sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$6878 + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7200 end - attribute \src "libresoc.v:135687.3-135709.6" - process $proc$libresoc.v:135687$6882 + attribute \src "libresoc.v:145458.3-145480.6" + process $proc$libresoc.v:145458$7204 assign { } { } assign { } { } assign { } { } - assign $0\m_load_err_o$next[0:0]$6883 $3\m_load_err_o$next[0:0]$6886 - attribute \src "libresoc.v:135688.5-135688.29" + assign $0\m_load_err_o$next[0:0]$7205 $3\m_load_err_o$next[0:0]$7208 + attribute \src "libresoc.v:145459.5-145459.29" switch \initial - attribute \src "libresoc.v:135688.9-135688.17" + attribute \src "libresoc.v:145459.9-145459.17" case 1'1 case end @@ -285979,44 +304774,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_load_err_o$next[0:0]$6884 $2\m_load_err_o$next[0:0]$6885 + assign $1\m_load_err_o$next[0:0]$7206 $2\m_load_err_o$next[0:0]$7207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_load_err_o$next[0:0]$6885 \$85 + assign $2\m_load_err_o$next[0:0]$7207 \$85 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_load_err_o$next[0:0]$6885 1'0 + assign $2\m_load_err_o$next[0:0]$7207 1'0 case - assign $2\m_load_err_o$next[0:0]$6885 \m_load_err_o + assign $2\m_load_err_o$next[0:0]$7207 \m_load_err_o end case - assign $1\m_load_err_o$next[0:0]$6884 \m_load_err_o + assign $1\m_load_err_o$next[0:0]$7206 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_load_err_o$next[0:0]$6886 1'0 + assign $3\m_load_err_o$next[0:0]$7208 1'0 case - assign $3\m_load_err_o$next[0:0]$6886 $1\m_load_err_o$next[0:0]$6884 + assign $3\m_load_err_o$next[0:0]$7208 $1\m_load_err_o$next[0:0]$7206 end sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$6883 + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7205 end - attribute \src "libresoc.v:135710.3-135732.6" - process $proc$libresoc.v:135710$6887 + attribute \src "libresoc.v:145481.3-145503.6" + process $proc$libresoc.v:145481$7209 assign { } { } assign { } { } assign { } { } - assign $0\m_store_err_o$next[0:0]$6888 $3\m_store_err_o$next[0:0]$6891 - attribute \src "libresoc.v:135711.5-135711.29" + assign $0\m_store_err_o$next[0:0]$7210 $3\m_store_err_o$next[0:0]$7213 + attribute \src "libresoc.v:145482.5-145482.29" switch \initial - attribute \src "libresoc.v:135711.9-135711.17" + attribute \src "libresoc.v:145482.9-145482.17" case 1'1 case end @@ -286025,44 +304820,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_store_err_o$next[0:0]$6889 $2\m_store_err_o$next[0:0]$6890 + assign $1\m_store_err_o$next[0:0]$7211 $2\m_store_err_o$next[0:0]$7212 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$89 \$87 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_store_err_o$next[0:0]$6890 \dbus__we + assign $2\m_store_err_o$next[0:0]$7212 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_store_err_o$next[0:0]$6890 1'0 + assign $2\m_store_err_o$next[0:0]$7212 1'0 case - assign $2\m_store_err_o$next[0:0]$6890 \m_store_err_o + assign $2\m_store_err_o$next[0:0]$7212 \m_store_err_o end case - assign $1\m_store_err_o$next[0:0]$6889 \m_store_err_o + assign $1\m_store_err_o$next[0:0]$7211 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_store_err_o$next[0:0]$6891 1'0 + assign $3\m_store_err_o$next[0:0]$7213 1'0 case - assign $3\m_store_err_o$next[0:0]$6891 $1\m_store_err_o$next[0:0]$6889 + assign $3\m_store_err_o$next[0:0]$7213 $1\m_store_err_o$next[0:0]$7211 end sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$6888 + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7210 end - attribute \src "libresoc.v:135733.3-135752.6" - process $proc$libresoc.v:135733$6892 + attribute \src "libresoc.v:145504.3-145523.6" + process $proc$libresoc.v:145504$7214 assign { } { } assign { } { } assign { } { } - assign $0\m_badaddr_o$next[44:0]$6893 $3\m_badaddr_o$next[44:0]$6896 - attribute \src "libresoc.v:135734.5-135734.29" + assign $0\m_badaddr_o$next[44:0]$7215 $3\m_badaddr_o$next[44:0]$7218 + attribute \src "libresoc.v:145505.5-145505.29" switch \initial - attribute \src "libresoc.v:135734.9-135734.17" + attribute \src "libresoc.v:145505.9-145505.17" case 1'1 case end @@ -286071,343 +304866,343 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_badaddr_o$next[44:0]$6894 $2\m_badaddr_o$next[44:0]$6895 + assign $1\m_badaddr_o$next[44:0]$7216 $2\m_badaddr_o$next[44:0]$7217 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$93 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_badaddr_o$next[44:0]$6895 \dbus__adr + assign $2\m_badaddr_o$next[44:0]$7217 \dbus__adr case - assign $2\m_badaddr_o$next[44:0]$6895 \m_badaddr_o + assign $2\m_badaddr_o$next[44:0]$7217 \m_badaddr_o end case - assign $1\m_badaddr_o$next[44:0]$6894 \m_badaddr_o + assign $1\m_badaddr_o$next[44:0]$7216 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_badaddr_o$next[44:0]$6896 45'000000000000000000000000000000000000000000000 - case - assign $3\m_badaddr_o$next[44:0]$6896 $1\m_badaddr_o$next[44:0]$6894 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$6893 - end - connect \$9 $or$libresoc.v:135401$6783_Y - connect \$11 $not$libresoc.v:135402$6784_Y - connect \$13 $or$libresoc.v:135403$6785_Y - connect \$15 $or$libresoc.v:135404$6786_Y - connect \$17 $and$libresoc.v:135405$6787_Y - connect \$1 $or$libresoc.v:135406$6788_Y - connect \$19 $not$libresoc.v:135407$6789_Y - connect \$21 $and$libresoc.v:135408$6790_Y - connect \$23 $or$libresoc.v:135409$6791_Y - connect \$25 $not$libresoc.v:135410$6792_Y - connect \$27 $or$libresoc.v:135411$6793_Y - connect \$29 $or$libresoc.v:135412$6794_Y - connect \$31 $and$libresoc.v:135413$6795_Y - connect \$33 $not$libresoc.v:135414$6796_Y - connect \$35 $and$libresoc.v:135415$6797_Y - connect \$37 $or$libresoc.v:135416$6798_Y - connect \$3 $and$libresoc.v:135417$6799_Y - connect \$39 $not$libresoc.v:135418$6800_Y - connect \$41 $or$libresoc.v:135419$6801_Y - connect \$43 $or$libresoc.v:135420$6802_Y - connect \$45 $and$libresoc.v:135421$6803_Y - connect \$47 $not$libresoc.v:135422$6804_Y - connect \$49 $and$libresoc.v:135423$6805_Y - connect \$51 $or$libresoc.v:135424$6806_Y - connect \$53 $not$libresoc.v:135425$6807_Y - connect \$55 $or$libresoc.v:135426$6808_Y - connect \$57 $or$libresoc.v:135427$6809_Y - connect \$5 $not$libresoc.v:135428$6810_Y - connect \$59 $and$libresoc.v:135429$6811_Y - connect \$61 $not$libresoc.v:135430$6812_Y - connect \$63 $and$libresoc.v:135431$6813_Y - connect \$65 $or$libresoc.v:135432$6814_Y - connect \$67 $and$libresoc.v:135433$6815_Y - connect \$69 $not$libresoc.v:135434$6816_Y - connect \$71 $and$libresoc.v:135435$6817_Y - connect \$73 $or$libresoc.v:135436$6818_Y - connect \$75 $and$libresoc.v:135437$6819_Y - connect \$77 $not$libresoc.v:135438$6820_Y - connect \$7 $and$libresoc.v:135439$6821_Y - connect \$79 $and$libresoc.v:135440$6822_Y - connect \$81 $and$libresoc.v:135441$6823_Y - connect \$83 $not$libresoc.v:135442$6824_Y - connect \$85 $not$libresoc.v:135443$6825_Y - connect \$87 $and$libresoc.v:135444$6826_Y - connect \$89 $not$libresoc.v:135445$6827_Y - connect \$91 $and$libresoc.v:135446$6828_Y - connect \$93 $not$libresoc.v:135447$6829_Y - connect \$95 $or$libresoc.v:135448$6830_Y + assign $3\m_badaddr_o$next[44:0]$7218 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$7218 $1\m_badaddr_o$next[44:0]$7216 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7215 + end + connect \$9 $or$libresoc.v:145172$7105_Y + connect \$11 $not$libresoc.v:145173$7106_Y + connect \$13 $or$libresoc.v:145174$7107_Y + connect \$15 $or$libresoc.v:145175$7108_Y + connect \$17 $and$libresoc.v:145176$7109_Y + connect \$1 $or$libresoc.v:145177$7110_Y + connect \$19 $not$libresoc.v:145178$7111_Y + connect \$21 $and$libresoc.v:145179$7112_Y + connect \$23 $or$libresoc.v:145180$7113_Y + connect \$25 $not$libresoc.v:145181$7114_Y + connect \$27 $or$libresoc.v:145182$7115_Y + connect \$29 $or$libresoc.v:145183$7116_Y + connect \$31 $and$libresoc.v:145184$7117_Y + connect \$33 $not$libresoc.v:145185$7118_Y + connect \$35 $and$libresoc.v:145186$7119_Y + connect \$37 $or$libresoc.v:145187$7120_Y + connect \$3 $and$libresoc.v:145188$7121_Y + connect \$39 $not$libresoc.v:145189$7122_Y + connect \$41 $or$libresoc.v:145190$7123_Y + connect \$43 $or$libresoc.v:145191$7124_Y + connect \$45 $and$libresoc.v:145192$7125_Y + connect \$47 $not$libresoc.v:145193$7126_Y + connect \$49 $and$libresoc.v:145194$7127_Y + connect \$51 $or$libresoc.v:145195$7128_Y + connect \$53 $not$libresoc.v:145196$7129_Y + connect \$55 $or$libresoc.v:145197$7130_Y + connect \$57 $or$libresoc.v:145198$7131_Y + connect \$5 $not$libresoc.v:145199$7132_Y + connect \$59 $and$libresoc.v:145200$7133_Y + connect \$61 $not$libresoc.v:145201$7134_Y + connect \$63 $and$libresoc.v:145202$7135_Y + connect \$65 $or$libresoc.v:145203$7136_Y + connect \$67 $and$libresoc.v:145204$7137_Y + connect \$69 $not$libresoc.v:145205$7138_Y + connect \$71 $and$libresoc.v:145206$7139_Y + connect \$73 $or$libresoc.v:145207$7140_Y + connect \$75 $and$libresoc.v:145208$7141_Y + connect \$77 $not$libresoc.v:145209$7142_Y + connect \$7 $and$libresoc.v:145210$7143_Y + connect \$79 $and$libresoc.v:145211$7144_Y + connect \$81 $and$libresoc.v:145212$7145_Y + connect \$83 $not$libresoc.v:145213$7146_Y + connect \$85 $not$libresoc.v:145214$7147_Y + connect \$87 $and$libresoc.v:145215$7148_Y + connect \$89 $not$libresoc.v:145216$7149_Y + connect \$91 $and$libresoc.v:145217$7150_Y + connect \$93 $not$libresoc.v:145218$7151_Y + connect \$95 $or$libresoc.v:145219$7152_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end -attribute \src "libresoc.v:135759.1-136714.10" +attribute \src "libresoc.v:145530.1-146491.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:136286.3-136308.6" + attribute \src "libresoc.v:146063.3-146085.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:136385.3-136411.6" + attribute \src "libresoc.v:146162.3-146188.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:136666.3-136676.6" + attribute \src "libresoc.v:146443.3-146453.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:136636.3-136645.6" + attribute \src "libresoc.v:146413.3-146422.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:136646.3-136655.6" + attribute \src "libresoc.v:146423.3-146432.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:136656.3-136665.6" + attribute \src "libresoc.v:146433.3-146442.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:136524.3-136546.6" + attribute \src "libresoc.v:146301.3-146323.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:136510.3-136523.6" + attribute \src "libresoc.v:146287.3-146300.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:136677.3-136687.6" + attribute \src "libresoc.v:146454.3-146464.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:136688.3-136698.6" + attribute \src "libresoc.v:146465.3-146475.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:136412.3-136437.6" + attribute \src "libresoc.v:146189.3-146214.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:136438.3-136452.6" + attribute \src "libresoc.v:146215.3-146229.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:136616.3-136635.6" + attribute \src "libresoc.v:146393.3-146412.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:135760.7-135760.20" + attribute \src "libresoc.v:145531.7-145531.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136276.3-136285.6" + attribute \src "libresoc.v:146053.3-146062.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:136347.3-136365.6" + attribute \src "libresoc.v:146124.3-146142.6" wire $0\msb_a[0:0] - attribute \src "libresoc.v:136366.3-136384.6" + attribute \src "libresoc.v:146143.3-146161.6" wire $0\msb_b[0:0] - attribute \src "libresoc.v:136453.3-136490.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:136491.3-136509.6" + attribute \src "libresoc.v:146268.3-146286.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:136569.3-136582.6" + attribute \src "libresoc.v:146346.3-146359.6" wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:136605.3-136615.6" + attribute \src "libresoc.v:146382.3-146392.6" wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:136320.3-136346.6" + attribute \src "libresoc.v:146097.3-146123.6" wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:136547.3-136557.6" - wire width 2 $0\xer_ca$20[1:0]$6983 - attribute \src "libresoc.v:136558.3-136568.6" + attribute \src "libresoc.v:146324.3-146334.6" + wire width 2 $0\xer_ca$20[1:0]$7305 + attribute \src "libresoc.v:146335.3-146345.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:136583.3-136593.6" + attribute \src "libresoc.v:146360.3-146370.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:136594.3-136604.6" + attribute \src "libresoc.v:146371.3-146381.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:136309.3-136319.6" + attribute \src "libresoc.v:146086.3-146096.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:136699.3-136709.6" + attribute \src "libresoc.v:146476.3-146486.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:136286.3-136308.6" + attribute \src "libresoc.v:146063.3-146085.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:136385.3-136411.6" + attribute \src "libresoc.v:146162.3-146188.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:136666.3-136676.6" + attribute \src "libresoc.v:146443.3-146453.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:136636.3-136645.6" + attribute \src "libresoc.v:146413.3-146422.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:136646.3-136655.6" + attribute \src "libresoc.v:146423.3-146432.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:136656.3-136665.6" + attribute \src "libresoc.v:146433.3-146442.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:136524.3-136546.6" + attribute \src "libresoc.v:146301.3-146323.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:136510.3-136523.6" + attribute \src "libresoc.v:146287.3-146300.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:136677.3-136687.6" + attribute \src "libresoc.v:146454.3-146464.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:136688.3-136698.6" + attribute \src "libresoc.v:146465.3-146475.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:136412.3-136437.6" + attribute \src "libresoc.v:146189.3-146214.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:136438.3-136452.6" + attribute \src "libresoc.v:146215.3-146229.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:136616.3-136635.6" + attribute \src "libresoc.v:146393.3-146412.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:136276.3-136285.6" + attribute \src "libresoc.v:146053.3-146062.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:136347.3-136365.6" + attribute \src "libresoc.v:146124.3-146142.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:136366.3-136384.6" + attribute \src "libresoc.v:146143.3-146161.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:136453.3-136490.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:136491.3-136509.6" + attribute \src "libresoc.v:146268.3-146286.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:136569.3-136582.6" + attribute \src "libresoc.v:146346.3-146359.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:136605.3-136615.6" + attribute \src "libresoc.v:146382.3-146392.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:136320.3-136346.6" + attribute \src "libresoc.v:146097.3-146123.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:136547.3-136557.6" - wire width 2 $1\xer_ca$20[1:0]$6984 - attribute \src "libresoc.v:136558.3-136568.6" + attribute \src "libresoc.v:146324.3-146334.6" + wire width 2 $1\xer_ca$20[1:0]$7306 + attribute \src "libresoc.v:146335.3-146345.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:136583.3-136593.6" + attribute \src "libresoc.v:146360.3-146370.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:136594.3-136604.6" + attribute \src "libresoc.v:146371.3-146381.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:136309.3-136319.6" + attribute \src "libresoc.v:146086.3-146096.6" wire $1\zerohi[0:0] - attribute \src "libresoc.v:136699.3-136709.6" + attribute \src "libresoc.v:146476.3-146486.6" wire $1\zerolo[0:0] - attribute \src "libresoc.v:136286.3-136308.6" + attribute \src "libresoc.v:146063.3-146085.6" wire width 64 $2\a_i[63:0] - attribute \src "libresoc.v:136385.3-136411.6" + attribute \src "libresoc.v:146162.3-146188.6" wire $2\a_lt[0:0] - attribute \src "libresoc.v:136524.3-136546.6" + attribute \src "libresoc.v:146301.3-146323.6" wire width 64 $2\b_i[63:0] - attribute \src "libresoc.v:136412.3-136437.6" + attribute \src "libresoc.v:146189.3-146214.6" wire width 2 $2\cr_a[3:2] - attribute \src "libresoc.v:136347.3-136365.6" + attribute \src "libresoc.v:146124.3-146142.6" wire $2\msb_a[0:0] - attribute \src "libresoc.v:136366.3-136384.6" + attribute \src "libresoc.v:146143.3-146161.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:136453.3-136490.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:136320.3-136346.6" + attribute \src "libresoc.v:146097.3-146123.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:136385.3-136411.6" + attribute \src "libresoc.v:146162.3-146188.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:136453.3-136490.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:136320.3-136346.6" + attribute \src "libresoc.v:146097.3-146123.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:136453.3-136490.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:136251.18-136251.105" - wire width 67 $add$libresoc.v:136251$6944_Y - attribute \src "libresoc.v:136225.19-136225.107" - wire $and$libresoc.v:136225$6918_Y - attribute \src "libresoc.v:136229.19-136229.107" - wire $and$libresoc.v:136229$6922_Y - attribute \src "libresoc.v:136262.18-136262.106" - wire $and$libresoc.v:136262$6955_Y - attribute \src "libresoc.v:136267.18-136267.106" - wire $and$libresoc.v:136267$6960_Y - attribute \src "libresoc.v:136270.18-136270.106" - wire $and$libresoc.v:136270$6963_Y - attribute \src "libresoc.v:136273.18-136273.106" - wire $and$libresoc.v:136273$6966_Y - attribute \src "libresoc.v:136216.19-136216.118" - wire $eq$libresoc.v:136216$6909_Y - attribute \src "libresoc.v:136217.19-136217.118" - wire $eq$libresoc.v:136217$6910_Y - attribute \src "libresoc.v:136218.19-136218.118" - wire $eq$libresoc.v:136218$6911_Y - attribute \src "libresoc.v:136230.19-136230.109" - wire $eq$libresoc.v:136230$6923_Y - attribute \src "libresoc.v:136231.19-136231.110" - wire $eq$libresoc.v:136231$6924_Y - attribute \src "libresoc.v:136232.19-136232.111" - wire $eq$libresoc.v:136232$6925_Y - attribute \src "libresoc.v:136233.19-136233.111" - wire $eq$libresoc.v:136233$6926_Y - attribute \src "libresoc.v:136234.19-136234.111" - wire $eq$libresoc.v:136234$6927_Y - attribute \src "libresoc.v:136235.19-136235.111" - wire $eq$libresoc.v:136235$6928_Y - attribute \src "libresoc.v:136236.19-136236.111" - wire $eq$libresoc.v:136236$6929_Y - attribute \src "libresoc.v:136237.19-136237.111" - wire $eq$libresoc.v:136237$6930_Y - attribute \src "libresoc.v:136238.18-136238.118" - wire $eq$libresoc.v:136238$6931_Y - attribute \src "libresoc.v:136240.18-136240.118" - wire $eq$libresoc.v:136240$6933_Y - attribute \src "libresoc.v:136241.18-136241.118" - wire $eq$libresoc.v:136241$6934_Y - attribute \src "libresoc.v:136242.18-136242.118" - wire $eq$libresoc.v:136242$6935_Y - attribute \src "libresoc.v:136243.18-136243.118" - wire $eq$libresoc.v:136243$6936_Y - attribute \src "libresoc.v:136245.18-136245.118" - wire $eq$libresoc.v:136245$6938_Y - attribute \src "libresoc.v:136246.18-136246.118" - wire $eq$libresoc.v:136246$6939_Y - attribute \src "libresoc.v:136248.18-136248.118" - wire $eq$libresoc.v:136248$6941_Y - attribute \src "libresoc.v:136249.18-136249.118" - wire $eq$libresoc.v:136249$6942_Y - attribute \src "libresoc.v:136263.18-136263.107" - wire $ne$libresoc.v:136263$6956_Y - attribute \src "libresoc.v:136274.18-136274.107" - wire $ne$libresoc.v:136274$6967_Y - attribute \src "libresoc.v:136224.19-136224.100" - wire $not$libresoc.v:136224$6917_Y - attribute \src "libresoc.v:136228.19-136228.100" - wire $not$libresoc.v:136228$6921_Y - attribute \src "libresoc.v:136239.18-136239.110" - wire $not$libresoc.v:136239$6932_Y - attribute \src "libresoc.v:136252.18-136252.97" - wire width 64 $not$libresoc.v:136252$6945_Y - attribute \src "libresoc.v:136257.18-136257.99" - wire $not$libresoc.v:136257$6950_Y - attribute \src "libresoc.v:136260.18-136260.99" - wire $not$libresoc.v:136260$6953_Y - attribute \src "libresoc.v:136264.18-136264.99" - wire $not$libresoc.v:136264$6957_Y - attribute \src "libresoc.v:136265.18-136265.99" - wire $not$libresoc.v:136265$6958_Y - attribute \src "libresoc.v:136244.18-136244.104" - wire $or$libresoc.v:136244$6937_Y - attribute \src "libresoc.v:136247.18-136247.104" - wire $or$libresoc.v:136247$6940_Y - attribute \src "libresoc.v:136250.18-136250.104" - wire $or$libresoc.v:136250$6943_Y - attribute \src "libresoc.v:136261.18-136261.110" - wire $or$libresoc.v:136261$6954_Y - attribute \src "libresoc.v:136266.18-136266.110" - wire $or$libresoc.v:136266$6959_Y - attribute \src "libresoc.v:136269.18-136269.110" - wire $or$libresoc.v:136269$6962_Y - attribute \src "libresoc.v:136272.18-136272.110" - wire $or$libresoc.v:136272$6965_Y - attribute \src "libresoc.v:136215.18-136215.98" - wire $reduce_or$libresoc.v:136215$6908_Y - attribute \src "libresoc.v:136219.19-136219.99" - wire $reduce_or$libresoc.v:136219$6912_Y - attribute \src "libresoc.v:136256.18-136256.99" - wire $reduce_or$libresoc.v:136256$6949_Y - attribute \src "libresoc.v:136259.18-136259.99" - wire $reduce_or$libresoc.v:136259$6952_Y - attribute \src "libresoc.v:136268.18-136268.121" - wire $ternary$libresoc.v:136268$6961_Y - attribute \src "libresoc.v:136271.18-136271.119" - wire $ternary$libresoc.v:136271$6964_Y - attribute \src "libresoc.v:136275.18-136275.123" - wire $ternary$libresoc.v:136275$6968_Y - attribute \src "libresoc.v:136220.19-136220.111" - wire $xor$libresoc.v:136220$6913_Y - attribute \src "libresoc.v:136221.19-136221.111" - wire $xor$libresoc.v:136221$6914_Y - attribute \src "libresoc.v:136222.19-136222.110" - wire $xor$libresoc.v:136222$6915_Y - attribute \src "libresoc.v:136223.19-136223.110" - wire $xor$libresoc.v:136223$6916_Y - attribute \src "libresoc.v:136226.19-136226.110" - wire $xor$libresoc.v:136226$6919_Y - attribute \src "libresoc.v:136227.19-136227.110" - wire $xor$libresoc.v:136227$6920_Y - attribute \src "libresoc.v:136253.18-136253.111" - wire $xor$libresoc.v:136253$6946_Y - attribute \src "libresoc.v:136254.18-136254.107" - wire $xor$libresoc.v:136254$6947_Y - attribute \src "libresoc.v:136255.18-136255.113" - wire width 32 $xor$libresoc.v:136255$6948_Y - attribute \src "libresoc.v:136258.18-136258.115" - wire width 32 $xor$libresoc.v:136258$6951_Y + attribute \src "libresoc.v:146028.18-146028.105" + wire width 67 $add$libresoc.v:146028$7266_Y + attribute \src "libresoc.v:146002.19-146002.107" + wire $and$libresoc.v:146002$7240_Y + attribute \src "libresoc.v:146006.19-146006.107" + wire $and$libresoc.v:146006$7244_Y + attribute \src "libresoc.v:146039.18-146039.106" + wire $and$libresoc.v:146039$7277_Y + attribute \src "libresoc.v:146044.18-146044.106" + wire $and$libresoc.v:146044$7282_Y + attribute \src "libresoc.v:146047.18-146047.106" + wire $and$libresoc.v:146047$7285_Y + attribute \src "libresoc.v:146050.18-146050.106" + wire $and$libresoc.v:146050$7288_Y + attribute \src "libresoc.v:145993.19-145993.118" + wire $eq$libresoc.v:145993$7231_Y + attribute \src "libresoc.v:145994.19-145994.118" + wire $eq$libresoc.v:145994$7232_Y + attribute \src "libresoc.v:145995.19-145995.118" + wire $eq$libresoc.v:145995$7233_Y + attribute \src "libresoc.v:146007.19-146007.109" + wire $eq$libresoc.v:146007$7245_Y + attribute \src "libresoc.v:146008.19-146008.110" + wire $eq$libresoc.v:146008$7246_Y + attribute \src "libresoc.v:146009.19-146009.111" + wire $eq$libresoc.v:146009$7247_Y + attribute \src "libresoc.v:146010.19-146010.111" + wire $eq$libresoc.v:146010$7248_Y + attribute \src "libresoc.v:146011.19-146011.111" + wire $eq$libresoc.v:146011$7249_Y + attribute \src "libresoc.v:146012.19-146012.111" + wire $eq$libresoc.v:146012$7250_Y + attribute \src "libresoc.v:146013.19-146013.111" + wire $eq$libresoc.v:146013$7251_Y + attribute \src "libresoc.v:146014.19-146014.111" + wire $eq$libresoc.v:146014$7252_Y + attribute \src "libresoc.v:146015.18-146015.118" + wire $eq$libresoc.v:146015$7253_Y + attribute \src "libresoc.v:146017.18-146017.118" + wire $eq$libresoc.v:146017$7255_Y + attribute \src "libresoc.v:146018.18-146018.118" + wire $eq$libresoc.v:146018$7256_Y + attribute \src "libresoc.v:146019.18-146019.118" + wire $eq$libresoc.v:146019$7257_Y + attribute \src "libresoc.v:146020.18-146020.118" + wire $eq$libresoc.v:146020$7258_Y + attribute \src "libresoc.v:146022.18-146022.118" + wire $eq$libresoc.v:146022$7260_Y + attribute \src "libresoc.v:146023.18-146023.118" + wire $eq$libresoc.v:146023$7261_Y + attribute \src "libresoc.v:146025.18-146025.118" + wire $eq$libresoc.v:146025$7263_Y + attribute \src "libresoc.v:146026.18-146026.118" + wire $eq$libresoc.v:146026$7264_Y + attribute \src "libresoc.v:146040.18-146040.107" + wire $ne$libresoc.v:146040$7278_Y + attribute \src "libresoc.v:146051.18-146051.107" + wire $ne$libresoc.v:146051$7289_Y + attribute \src "libresoc.v:146001.19-146001.100" + wire $not$libresoc.v:146001$7239_Y + attribute \src "libresoc.v:146005.19-146005.100" + wire $not$libresoc.v:146005$7243_Y + attribute \src "libresoc.v:146016.18-146016.110" + wire $not$libresoc.v:146016$7254_Y + attribute \src "libresoc.v:146029.18-146029.97" + wire width 64 $not$libresoc.v:146029$7267_Y + attribute \src "libresoc.v:146034.18-146034.99" + wire $not$libresoc.v:146034$7272_Y + attribute \src "libresoc.v:146037.18-146037.99" + wire $not$libresoc.v:146037$7275_Y + attribute \src "libresoc.v:146041.18-146041.99" + wire $not$libresoc.v:146041$7279_Y + attribute \src "libresoc.v:146042.18-146042.99" + wire $not$libresoc.v:146042$7280_Y + attribute \src "libresoc.v:146021.18-146021.104" + wire $or$libresoc.v:146021$7259_Y + attribute \src "libresoc.v:146024.18-146024.104" + wire $or$libresoc.v:146024$7262_Y + attribute \src "libresoc.v:146027.18-146027.104" + wire $or$libresoc.v:146027$7265_Y + attribute \src "libresoc.v:146038.18-146038.110" + wire $or$libresoc.v:146038$7276_Y + attribute \src "libresoc.v:146043.18-146043.110" + wire $or$libresoc.v:146043$7281_Y + attribute \src "libresoc.v:146046.18-146046.110" + wire $or$libresoc.v:146046$7284_Y + attribute \src "libresoc.v:146049.18-146049.110" + wire $or$libresoc.v:146049$7287_Y + attribute \src "libresoc.v:145992.18-145992.98" + wire $reduce_or$libresoc.v:145992$7230_Y + attribute \src "libresoc.v:145996.19-145996.99" + wire $reduce_or$libresoc.v:145996$7234_Y + attribute \src "libresoc.v:146033.18-146033.99" + wire $reduce_or$libresoc.v:146033$7271_Y + attribute \src "libresoc.v:146036.18-146036.99" + wire $reduce_or$libresoc.v:146036$7274_Y + attribute \src "libresoc.v:146045.18-146045.121" + wire $ternary$libresoc.v:146045$7283_Y + attribute \src "libresoc.v:146048.18-146048.119" + wire $ternary$libresoc.v:146048$7286_Y + attribute \src "libresoc.v:146052.18-146052.123" + wire $ternary$libresoc.v:146052$7290_Y + attribute \src "libresoc.v:145997.19-145997.111" + wire $xor$libresoc.v:145997$7235_Y + attribute \src "libresoc.v:145998.19-145998.111" + wire $xor$libresoc.v:145998$7236_Y + attribute \src "libresoc.v:145999.19-145999.110" + wire $xor$libresoc.v:145999$7237_Y + attribute \src "libresoc.v:146000.19-146000.110" + wire $xor$libresoc.v:146000$7238_Y + attribute \src "libresoc.v:146003.19-146003.110" + wire $xor$libresoc.v:146003$7241_Y + attribute \src "libresoc.v:146004.19-146004.110" + wire $xor$libresoc.v:146004$7242_Y + attribute \src "libresoc.v:146030.18-146030.111" + wire $xor$libresoc.v:146030$7268_Y + attribute \src "libresoc.v:146031.18-146031.107" + wire $xor$libresoc.v:146031$7269_Y + attribute \src "libresoc.v:146032.18-146032.113" + wire width 32 $xor$libresoc.v:146032$7270_Y + attribute \src "libresoc.v:146035.18-146035.115" + wire width 32 $xor$libresoc.v:146035$7273_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" @@ -286549,35 +305344,39 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \alu_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \alu_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -286676,6 +305475,7 @@ module \main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -286752,6 +305552,7 @@ module \main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -286812,7 +305613,7 @@ module \main wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:135760.7-135760.15" + attribute \src "libresoc.v:145531.7-145531.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit @@ -286820,9 +305621,9 @@ module \main wire \msb_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" wire \msb_b - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 42 \o @@ -286857,7 +305658,7 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:136251$6944 + cell $add $add$libresoc.v:146028$7266 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -286865,10 +305666,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:136251$6944_Y + connect \Y $add$libresoc.v:146028$7266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:136225$6918 + cell $and $and$libresoc.v:146002$7240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286876,10 +305677,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:136225$6918_Y + connect \Y $and$libresoc.v:146002$7240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:136229$6922 + cell $and $and$libresoc.v:146006$7244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286887,10 +305688,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:136229$6922_Y + connect \Y $and$libresoc.v:146006$7244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:136262$6955 + cell $and $and$libresoc.v:146039$7277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286898,10 +305699,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:136262$6955_Y + connect \Y $and$libresoc.v:146039$7277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:136267$6960 + cell $and $and$libresoc.v:146044$7282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286909,10 +305710,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:136267$6960_Y + connect \Y $and$libresoc.v:146044$7282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:136270$6963 + cell $and $and$libresoc.v:146047$7285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286920,10 +305721,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:136270$6963_Y + connect \Y $and$libresoc.v:146047$7285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:136273$6966 + cell $and $and$libresoc.v:146050$7288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286931,10 +305732,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:136273$6966_Y + connect \Y $and$libresoc.v:146050$7288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:136216$6909 + cell $eq $eq$libresoc.v:145993$7231 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -286942,10 +305743,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:136216$6909_Y + connect \Y $eq$libresoc.v:145993$7231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:136217$6910 + cell $eq $eq$libresoc.v:145994$7232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -286953,10 +305754,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:136217$6910_Y + connect \Y $eq$libresoc.v:145994$7232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:136218$6911 + cell $eq $eq$libresoc.v:145995$7233 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -286964,10 +305765,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:136218$6911_Y + connect \Y $eq$libresoc.v:145995$7233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136230$6923 + cell $eq $eq$libresoc.v:146007$7245 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -286975,10 +305776,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136230$6923_Y + connect \Y $eq$libresoc.v:146007$7245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136231$6924 + cell $eq $eq$libresoc.v:146008$7246 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -286986,10 +305787,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136231$6924_Y + connect \Y $eq$libresoc.v:146008$7246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136232$6925 + cell $eq $eq$libresoc.v:146009$7247 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -286997,10 +305798,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136232$6925_Y + connect \Y $eq$libresoc.v:146009$7247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136233$6926 + cell $eq $eq$libresoc.v:146010$7248 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -287008,10 +305809,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136233$6926_Y + connect \Y $eq$libresoc.v:146010$7248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136234$6927 + cell $eq $eq$libresoc.v:146011$7249 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -287019,10 +305820,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136234$6927_Y + connect \Y $eq$libresoc.v:146011$7249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136235$6928 + cell $eq $eq$libresoc.v:146012$7250 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -287030,10 +305831,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136235$6928_Y + connect \Y $eq$libresoc.v:146012$7250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136236$6929 + cell $eq $eq$libresoc.v:146013$7251 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -287041,10 +305842,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136236$6929_Y + connect \Y $eq$libresoc.v:146013$7251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136237$6930 + cell $eq $eq$libresoc.v:146014$7252 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -287052,10 +305853,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136237$6930_Y + connect \Y $eq$libresoc.v:146014$7252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:136238$6931 + cell $eq $eq$libresoc.v:146015$7253 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287063,10 +305864,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:136238$6931_Y + connect \Y $eq$libresoc.v:146015$7253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:136240$6933 + cell $eq $eq$libresoc.v:146017$7255 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287074,10 +305875,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:136240$6933_Y + connect \Y $eq$libresoc.v:146017$7255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:136241$6934 + cell $eq $eq$libresoc.v:146018$7256 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287085,10 +305886,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:136241$6934_Y + connect \Y $eq$libresoc.v:146018$7256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:136242$6935 + cell $eq $eq$libresoc.v:146019$7257 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287096,10 +305897,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:136242$6935_Y + connect \Y $eq$libresoc.v:146019$7257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:136243$6936 + cell $eq $eq$libresoc.v:146020$7258 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287107,10 +305908,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:136243$6936_Y + connect \Y $eq$libresoc.v:146020$7258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:136245$6938 + cell $eq $eq$libresoc.v:146022$7260 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287118,10 +305919,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:136245$6938_Y + connect \Y $eq$libresoc.v:146022$7260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:136246$6939 + cell $eq $eq$libresoc.v:146023$7261 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287129,10 +305930,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:136246$6939_Y + connect \Y $eq$libresoc.v:146023$7261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:136248$6941 + cell $eq $eq$libresoc.v:146025$7263 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287140,10 +305941,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:136248$6941_Y + connect \Y $eq$libresoc.v:146025$7263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:136249$6942 + cell $eq $eq$libresoc.v:146026$7264 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -287151,10 +305952,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:136249$6942_Y + connect \Y $eq$libresoc.v:146026$7264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:136263$6956 + cell $ne $ne$libresoc.v:146040$7278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287162,10 +305963,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:136263$6956_Y + connect \Y $ne$libresoc.v:146040$7278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:136274$6967 + cell $ne $ne$libresoc.v:146051$7289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287173,74 +305974,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:136274$6967_Y + connect \Y $ne$libresoc.v:146051$7289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:136224$6917 + cell $not $not$libresoc.v:146001$7239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:136224$6917_Y + connect \Y $not$libresoc.v:146001$7239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:136228$6921 + cell $not $not$libresoc.v:146005$7243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:136228$6921_Y + connect \Y $not$libresoc.v:146005$7243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:136239$6932 + cell $not $not$libresoc.v:146016$7254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:136239$6932_Y + connect \Y $not$libresoc.v:146016$7254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:136252$6945 + cell $not $not$libresoc.v:146029$7267 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:136252$6945_Y + connect \Y $not$libresoc.v:146029$7267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:136257$6950 + cell $not $not$libresoc.v:146034$7272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:136257$6950_Y + connect \Y $not$libresoc.v:146034$7272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:136260$6953 + cell $not $not$libresoc.v:146037$7275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:136260$6953_Y + connect \Y $not$libresoc.v:146037$7275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:136264$6957 + cell $not $not$libresoc.v:146041$7279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:136264$6957_Y + connect \Y $not$libresoc.v:146041$7279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:136265$6958 + cell $not $not$libresoc.v:146042$7280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:136265$6958_Y + connect \Y $not$libresoc.v:146042$7280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:136244$6937 + cell $or $or$libresoc.v:146021$7259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287248,10 +306049,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:136244$6937_Y + connect \Y $or$libresoc.v:146021$7259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:136247$6940 + cell $or $or$libresoc.v:146024$7262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287259,10 +306060,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:136247$6940_Y + connect \Y $or$libresoc.v:146024$7262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:136250$6943 + cell $or $or$libresoc.v:146027$7265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287270,10 +306071,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:136250$6943_Y + connect \Y $or$libresoc.v:146027$7265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:136261$6954 + cell $or $or$libresoc.v:146038$7276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287281,10 +306082,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:136261$6954_Y + connect \Y $or$libresoc.v:146038$7276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:136266$6959 + cell $or $or$libresoc.v:146043$7281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287292,10 +306093,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:136266$6959_Y + connect \Y $or$libresoc.v:146043$7281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:136269$6962 + cell $or $or$libresoc.v:146046$7284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287303,10 +306104,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:136269$6962_Y + connect \Y $or$libresoc.v:146046$7284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:136272$6965 + cell $or $or$libresoc.v:146049$7287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287314,66 +306115,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:136272$6965_Y + connect \Y $or$libresoc.v:146049$7287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:136215$6908 + cell $reduce_or $reduce_or$libresoc.v:145992$7230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:136215$6908_Y + connect \Y $reduce_or$libresoc.v:145992$7230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:136219$6912 + cell $reduce_or $reduce_or$libresoc.v:145996$7234 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:136219$6912_Y + connect \Y $reduce_or$libresoc.v:145996$7234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:136256$6949 + cell $reduce_or $reduce_or$libresoc.v:146033$7271 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:136256$6949_Y + connect \Y $reduce_or$libresoc.v:146033$7271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:136259$6952 + cell $reduce_or $reduce_or$libresoc.v:146036$7274 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:136259$6952_Y + connect \Y $reduce_or$libresoc.v:146036$7274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:136268$6961 + cell $mux $ternary$libresoc.v:146045$7283 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:136268$6961_Y + connect \Y $ternary$libresoc.v:146045$7283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:136271$6964 + cell $mux $ternary$libresoc.v:146048$7286 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:136271$6964_Y + connect \Y $ternary$libresoc.v:146048$7286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:136275$6968 + cell $mux $ternary$libresoc.v:146052$7290 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:136275$6968_Y + connect \Y $ternary$libresoc.v:146052$7290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:136220$6913 + cell $xor $xor$libresoc.v:145997$7235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287381,10 +306182,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:136220$6913_Y + connect \Y $xor$libresoc.v:145997$7235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:136221$6914 + cell $xor $xor$libresoc.v:145998$7236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287392,10 +306193,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:136221$6914_Y + connect \Y $xor$libresoc.v:145998$7236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:136222$6915 + cell $xor $xor$libresoc.v:145999$7237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287403,10 +306204,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:136222$6915_Y + connect \Y $xor$libresoc.v:145999$7237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:136223$6916 + cell $xor $xor$libresoc.v:146000$7238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287414,10 +306215,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:136223$6916_Y + connect \Y $xor$libresoc.v:146000$7238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:136226$6919 + cell $xor $xor$libresoc.v:146003$7241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287425,10 +306226,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:136226$6919_Y + connect \Y $xor$libresoc.v:146003$7241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:136227$6920 + cell $xor $xor$libresoc.v:146004$7242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287436,10 +306237,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:136227$6920_Y + connect \Y $xor$libresoc.v:146004$7242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:136253$6946 + cell $xor $xor$libresoc.v:146030$7268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287447,10 +306248,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:136253$6946_Y + connect \Y $xor$libresoc.v:146030$7268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:136254$6947 + cell $xor $xor$libresoc.v:146031$7269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287458,10 +306259,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:136254$6947_Y + connect \Y $xor$libresoc.v:146031$7269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:136255$6948 + cell $xor $xor$libresoc.v:146032$7270 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -287469,10 +306270,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:136255$6948_Y + connect \Y $xor$libresoc.v:146032$7270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:136258$6951 + cell $xor $xor$libresoc.v:146035$7273 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -287480,24 +306281,24 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:136258$6951_Y + connect \Y $xor$libresoc.v:146035$7273_Y end - attribute \src "libresoc.v:135760.7-135760.20" - process $proc$libresoc.v:135760$6998 + attribute \src "libresoc.v:145531.7-145531.20" + process $proc$libresoc.v:145531$7320 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136276.3-136285.6" - process $proc$libresoc.v:136276$6969 + attribute \src "libresoc.v:146053.3-146062.6" + process $proc$libresoc.v:146053$7291 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:136277.5-136277.29" + attribute \src "libresoc.v:146054.5-146054.29" switch \initial - attribute \src "libresoc.v:136277.9-136277.17" + attribute \src "libresoc.v:146054.9-146054.17" case 1'1 case end @@ -287513,13 +306314,13 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:136286.3-136308.6" - process $proc$libresoc.v:136286$6970 + attribute \src "libresoc.v:146063.3-146085.6" + process $proc$libresoc.v:146063$7292 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:136287.5-136287.29" + attribute \src "libresoc.v:146064.5-146064.29" switch \initial - attribute \src "libresoc.v:136287.9-136287.17" + attribute \src "libresoc.v:146064.9-146064.17" case 1'1 case end @@ -287552,14 +306353,14 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:136309.3-136319.6" - process $proc$libresoc.v:136309$6971 + attribute \src "libresoc.v:146086.3-146096.6" + process $proc$libresoc.v:146086$7293 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:136310.5-136310.29" + attribute \src "libresoc.v:146087.5-146087.29" switch \initial - attribute \src "libresoc.v:136310.9-136310.17" + attribute \src "libresoc.v:146087.9-146087.17" case 1'1 case end @@ -287575,14 +306376,14 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:136320.3-136346.6" - process $proc$libresoc.v:136320$6972 + attribute \src "libresoc.v:146097.3-146123.6" + process $proc$libresoc.v:146097$7294 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:136321.5-136321.29" + attribute \src "libresoc.v:146098.5-146098.29" switch \initial - attribute \src "libresoc.v:136321.9-136321.17" + attribute \src "libresoc.v:146098.9-146098.17" case 1'1 case end @@ -287620,14 +306421,14 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:136347.3-136365.6" - process $proc$libresoc.v:136347$6973 + attribute \src "libresoc.v:146124.3-146142.6" + process $proc$libresoc.v:146124$7295 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:136348.5-136348.29" + attribute \src "libresoc.v:146125.5-146125.29" switch \initial - attribute \src "libresoc.v:136348.9-136348.17" + attribute \src "libresoc.v:146125.9-146125.17" case 1'1 case end @@ -287653,14 +306454,14 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:136366.3-136384.6" - process $proc$libresoc.v:136366$6974 + attribute \src "libresoc.v:146143.3-146161.6" + process $proc$libresoc.v:146143$7296 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:136367.5-136367.29" + attribute \src "libresoc.v:146144.5-146144.29" switch \initial - attribute \src "libresoc.v:136367.9-136367.17" + attribute \src "libresoc.v:146144.9-146144.17" case 1'1 case end @@ -287686,14 +306487,14 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:136385.3-136411.6" - process $proc$libresoc.v:136385$6975 + attribute \src "libresoc.v:146162.3-146188.6" + process $proc$libresoc.v:146162$7297 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:136386.5-136386.29" + attribute \src "libresoc.v:146163.5-146163.29" switch \initial - attribute \src "libresoc.v:136386.9-136386.17" + attribute \src "libresoc.v:146163.9-146163.17" case 1'1 case end @@ -287729,14 +306530,14 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:136412.3-136437.6" - process $proc$libresoc.v:136412$6976 + attribute \src "libresoc.v:146189.3-146214.6" + process $proc$libresoc.v:146189$7298 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:136413.5-136413.29" + attribute \src "libresoc.v:146190.5-146190.29" switch \initial - attribute \src "libresoc.v:136413.9-136413.17" + attribute \src "libresoc.v:146190.9-146190.17" case 1'1 case end @@ -287768,14 +306569,14 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:136438.3-136452.6" - process $proc$libresoc.v:136438$6977 + attribute \src "libresoc.v:146215.3-146229.6" + process $proc$libresoc.v:146215$7299 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:136439.5-136439.29" + attribute \src "libresoc.v:146216.5-146216.29" switch \initial - attribute \src "libresoc.v:136439.9-136439.17" + attribute \src "libresoc.v:146216.9-146216.17" case 1'1 case end @@ -287795,14 +306596,14 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:136453.3-136490.6" - process $proc$libresoc.v:136453$6978 + attribute \src "libresoc.v:146230.3-146267.6" + process $proc$libresoc.v:146230$7300 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:136454.5-136454.29" + attribute \src "libresoc.v:146231.5-146231.29" switch \initial - attribute \src "libresoc.v:136454.9-136454.17" + attribute \src "libresoc.v:146231.9-146231.17" case 1'1 case end @@ -287855,14 +306656,14 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:136491.3-136509.6" - process $proc$libresoc.v:136491$6979 + attribute \src "libresoc.v:146268.3-146286.6" + process $proc$libresoc.v:146268$7301 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:136492.5-136492.29" + attribute \src "libresoc.v:146269.5-146269.29" switch \initial - attribute \src "libresoc.v:136492.9-136492.17" + attribute \src "libresoc.v:146269.9-146269.17" case 1'1 case end @@ -287886,14 +306687,14 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:136510.3-136523.6" - process $proc$libresoc.v:136510$6980 + attribute \src "libresoc.v:146287.3-146300.6" + process $proc$libresoc.v:146287$7302 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:136511.5-136511.29" + attribute \src "libresoc.v:146288.5-146288.29" switch \initial - attribute \src "libresoc.v:136511.9-136511.17" + attribute \src "libresoc.v:146288.9-146288.17" case 1'1 case end @@ -287910,13 +306711,13 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:136524.3-136546.6" - process $proc$libresoc.v:136524$6981 + attribute \src "libresoc.v:146301.3-146323.6" + process $proc$libresoc.v:146301$7303 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:136525.5-136525.29" + attribute \src "libresoc.v:146302.5-146302.29" switch \initial - attribute \src "libresoc.v:136525.9-136525.17" + attribute \src "libresoc.v:146302.9-146302.17" case 1'1 case end @@ -287949,14 +306750,14 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:136547.3-136557.6" - process $proc$libresoc.v:136547$6982 + attribute \src "libresoc.v:146324.3-146334.6" + process $proc$libresoc.v:146324$7304 assign { } { } assign { } { } - assign $0\xer_ca$20[1:0]$6983 $1\xer_ca$20[1:0]$6984 - attribute \src "libresoc.v:136548.5-136548.29" + assign $0\xer_ca$20[1:0]$7305 $1\xer_ca$20[1:0]$7306 + attribute \src "libresoc.v:146325.5-146325.29" switch \initial - attribute \src "libresoc.v:136548.9-136548.17" + attribute \src "libresoc.v:146325.9-146325.17" case 1'1 case end @@ -287965,21 +306766,21 @@ module \main attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } - assign $1\xer_ca$20[1:0]$6984 \ca + assign $1\xer_ca$20[1:0]$7306 \ca case - assign $1\xer_ca$20[1:0]$6984 2'00 + assign $1\xer_ca$20[1:0]$7306 2'00 end sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$6983 + update \xer_ca$20 $0\xer_ca$20[1:0]$7305 end - attribute \src "libresoc.v:136558.3-136568.6" - process $proc$libresoc.v:136558$6985 + attribute \src "libresoc.v:146335.3-146345.6" + process $proc$libresoc.v:146335$7307 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:136559.5-136559.29" + attribute \src "libresoc.v:146336.5-146336.29" switch \initial - attribute \src "libresoc.v:136559.9-136559.17" + attribute \src "libresoc.v:146336.9-146336.17" case 1'1 case end @@ -287995,14 +306796,14 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:136569.3-136582.6" - process $proc$libresoc.v:136569$6986 + attribute \src "libresoc.v:146346.3-146359.6" + process $proc$libresoc.v:146346$7308 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:136570.5-136570.29" + attribute \src "libresoc.v:146347.5-146347.29" switch \initial - attribute \src "libresoc.v:136570.9-136570.17" + attribute \src "libresoc.v:146347.9-146347.17" case 1'1 case end @@ -288019,14 +306820,14 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:136583.3-136593.6" - process $proc$libresoc.v:136583$6987 + attribute \src "libresoc.v:146360.3-146370.6" + process $proc$libresoc.v:146360$7309 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:136584.5-136584.29" + attribute \src "libresoc.v:146361.5-146361.29" switch \initial - attribute \src "libresoc.v:136584.9-136584.17" + attribute \src "libresoc.v:146361.9-146361.17" case 1'1 case end @@ -288042,14 +306843,14 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:136594.3-136604.6" - process $proc$libresoc.v:136594$6988 + attribute \src "libresoc.v:146371.3-146381.6" + process $proc$libresoc.v:146371$7310 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:136595.5-136595.29" + attribute \src "libresoc.v:146372.5-146372.29" switch \initial - attribute \src "libresoc.v:136595.9-136595.17" + attribute \src "libresoc.v:146372.9-146372.17" case 1'1 case end @@ -288065,14 +306866,14 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:136605.3-136615.6" - process $proc$libresoc.v:136605$6989 + attribute \src "libresoc.v:146382.3-146392.6" + process $proc$libresoc.v:146382$7311 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:136606.5-136606.29" + attribute \src "libresoc.v:146383.5-146383.29" switch \initial - attribute \src "libresoc.v:136606.9-136606.17" + attribute \src "libresoc.v:146383.9-146383.17" case 1'1 case end @@ -288088,14 +306889,14 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:136616.3-136635.6" - process $proc$libresoc.v:136616$6990 + attribute \src "libresoc.v:146393.3-146412.6" + process $proc$libresoc.v:146393$7312 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:136617.5-136617.29" + attribute \src "libresoc.v:146394.5-146394.29" switch \initial - attribute \src "libresoc.v:136617.9-136617.17" + attribute \src "libresoc.v:146394.9-146394.17" case 1'1 case end @@ -288118,14 +306919,14 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:136636.3-136645.6" - process $proc$libresoc.v:136636$6991 + attribute \src "libresoc.v:146413.3-146422.6" + process $proc$libresoc.v:146413$7313 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:136637.5-136637.29" + attribute \src "libresoc.v:146414.5-146414.29" switch \initial - attribute \src "libresoc.v:136637.9-136637.17" + attribute \src "libresoc.v:146414.9-146414.17" case 1'1 case end @@ -288141,14 +306942,14 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:136646.3-136655.6" - process $proc$libresoc.v:136646$6992 + attribute \src "libresoc.v:146423.3-146432.6" + process $proc$libresoc.v:146423$7314 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:136647.5-136647.29" + attribute \src "libresoc.v:146424.5-146424.29" switch \initial - attribute \src "libresoc.v:136647.9-136647.17" + attribute \src "libresoc.v:146424.9-146424.17" case 1'1 case end @@ -288164,14 +306965,14 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:136656.3-136665.6" - process $proc$libresoc.v:136656$6993 + attribute \src "libresoc.v:146433.3-146442.6" + process $proc$libresoc.v:146433$7315 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:136657.5-136657.29" + attribute \src "libresoc.v:146434.5-146434.29" switch \initial - attribute \src "libresoc.v:136657.9-136657.17" + attribute \src "libresoc.v:146434.9-146434.17" case 1'1 case end @@ -288187,14 +306988,14 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:136666.3-136676.6" - process $proc$libresoc.v:136666$6994 + attribute \src "libresoc.v:146443.3-146453.6" + process $proc$libresoc.v:146443$7316 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:136667.5-136667.29" + attribute \src "libresoc.v:146444.5-146444.29" switch \initial - attribute \src "libresoc.v:136667.9-136667.17" + attribute \src "libresoc.v:146444.9-146444.17" case 1'1 case end @@ -288210,14 +307011,14 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:136677.3-136687.6" - process $proc$libresoc.v:136677$6995 + attribute \src "libresoc.v:146454.3-146464.6" + process $proc$libresoc.v:146454$7317 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:136678.5-136678.29" + attribute \src "libresoc.v:146455.5-146455.29" switch \initial - attribute \src "libresoc.v:136678.9-136678.17" + attribute \src "libresoc.v:146455.9-146455.17" case 1'1 case end @@ -288233,14 +307034,14 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:136688.3-136698.6" - process $proc$libresoc.v:136688$6996 + attribute \src "libresoc.v:146465.3-146475.6" + process $proc$libresoc.v:146465$7318 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:136689.5-136689.29" + attribute \src "libresoc.v:146466.5-146466.29" switch \initial - attribute \src "libresoc.v:136689.9-136689.17" + attribute \src "libresoc.v:146466.9-146466.17" case 1'1 case end @@ -288256,14 +307057,14 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:136699.3-136709.6" - process $proc$libresoc.v:136699$6997 + attribute \src "libresoc.v:146476.3-146486.6" + process $proc$libresoc.v:146476$7319 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:136700.5-136700.29" + attribute \src "libresoc.v:146477.5-146477.29" switch \initial - attribute \src "libresoc.v:136700.9-136700.17" + attribute \src "libresoc.v:146477.9-146477.17" case 1'1 case end @@ -288279,88 +307080,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:136215$6908_Y - connect \$101 $eq$libresoc.v:136216$6909_Y - connect \$103 $eq$libresoc.v:136217$6910_Y - connect \$105 $eq$libresoc.v:136218$6911_Y - connect \$107 $reduce_or$libresoc.v:136219$6912_Y - connect \$109 $xor$libresoc.v:136220$6913_Y - connect \$111 $xor$libresoc.v:136221$6914_Y - connect \$113 $xor$libresoc.v:136222$6915_Y - connect \$116 $xor$libresoc.v:136223$6916_Y - connect \$115 $not$libresoc.v:136224$6917_Y - connect \$119 $and$libresoc.v:136225$6918_Y - connect \$121 $xor$libresoc.v:136226$6919_Y - connect \$124 $xor$libresoc.v:136227$6920_Y - connect \$123 $not$libresoc.v:136228$6921_Y - connect \$127 $and$libresoc.v:136229$6922_Y - connect \$129 $eq$libresoc.v:136230$6923_Y - connect \$131 $eq$libresoc.v:136231$6924_Y - connect \$133 $eq$libresoc.v:136232$6925_Y - connect \$135 $eq$libresoc.v:136233$6926_Y - connect \$137 $eq$libresoc.v:136234$6927_Y - connect \$139 $eq$libresoc.v:136235$6928_Y - connect \$141 $eq$libresoc.v:136236$6929_Y - connect \$143 $eq$libresoc.v:136237$6930_Y - connect \$22 $eq$libresoc.v:136238$6931_Y - connect \$24 $not$libresoc.v:136239$6932_Y - connect \$26 $eq$libresoc.v:136240$6933_Y - connect \$28 $eq$libresoc.v:136241$6934_Y - connect \$30 $eq$libresoc.v:136242$6935_Y - connect \$32 $eq$libresoc.v:136243$6936_Y - connect \$34 $or$libresoc.v:136244$6937_Y - connect \$36 $eq$libresoc.v:136245$6938_Y - connect \$38 $eq$libresoc.v:136246$6939_Y - connect \$40 $or$libresoc.v:136247$6940_Y - connect \$42 $eq$libresoc.v:136248$6941_Y - connect \$44 $eq$libresoc.v:136249$6942_Y - connect \$46 $or$libresoc.v:136250$6943_Y - connect \$49 $add$libresoc.v:136251$6944_Y - connect \$51 $not$libresoc.v:136252$6945_Y - connect \$53 $xor$libresoc.v:136253$6946_Y - connect \$55 $xor$libresoc.v:136254$6947_Y - connect \$59 $xor$libresoc.v:136255$6948_Y - connect \$58 $reduce_or$libresoc.v:136256$6949_Y - connect \$57 $not$libresoc.v:136257$6950_Y - connect \$65 $xor$libresoc.v:136258$6951_Y - connect \$64 $reduce_or$libresoc.v:136259$6952_Y - connect \$63 $not$libresoc.v:136260$6953_Y - connect \$69 $or$libresoc.v:136261$6954_Y - connect \$71 $and$libresoc.v:136262$6955_Y - connect \$73 $ne$libresoc.v:136263$6956_Y - connect \$75 $not$libresoc.v:136264$6957_Y - connect \$77 $not$libresoc.v:136265$6958_Y - connect \$79 $or$libresoc.v:136266$6959_Y - connect \$81 $and$libresoc.v:136267$6960_Y - connect \$83 $ternary$libresoc.v:136268$6961_Y - connect \$85 $or$libresoc.v:136269$6962_Y - connect \$87 $and$libresoc.v:136270$6963_Y - connect \$89 $ternary$libresoc.v:136271$6964_Y - connect \$91 $or$libresoc.v:136272$6965_Y - connect \$93 $and$libresoc.v:136273$6966_Y - connect \$95 $ne$libresoc.v:136274$6967_Y - connect \$97 $ternary$libresoc.v:136275$6968_Y + connect \$99 $reduce_or$libresoc.v:145992$7230_Y + connect \$101 $eq$libresoc.v:145993$7231_Y + connect \$103 $eq$libresoc.v:145994$7232_Y + connect \$105 $eq$libresoc.v:145995$7233_Y + connect \$107 $reduce_or$libresoc.v:145996$7234_Y + connect \$109 $xor$libresoc.v:145997$7235_Y + connect \$111 $xor$libresoc.v:145998$7236_Y + connect \$113 $xor$libresoc.v:145999$7237_Y + connect \$116 $xor$libresoc.v:146000$7238_Y + connect \$115 $not$libresoc.v:146001$7239_Y + connect \$119 $and$libresoc.v:146002$7240_Y + connect \$121 $xor$libresoc.v:146003$7241_Y + connect \$124 $xor$libresoc.v:146004$7242_Y + connect \$123 $not$libresoc.v:146005$7243_Y + connect \$127 $and$libresoc.v:146006$7244_Y + connect \$129 $eq$libresoc.v:146007$7245_Y + connect \$131 $eq$libresoc.v:146008$7246_Y + connect \$133 $eq$libresoc.v:146009$7247_Y + connect \$135 $eq$libresoc.v:146010$7248_Y + connect \$137 $eq$libresoc.v:146011$7249_Y + connect \$139 $eq$libresoc.v:146012$7250_Y + connect \$141 $eq$libresoc.v:146013$7251_Y + connect \$143 $eq$libresoc.v:146014$7252_Y + connect \$22 $eq$libresoc.v:146015$7253_Y + connect \$24 $not$libresoc.v:146016$7254_Y + connect \$26 $eq$libresoc.v:146017$7255_Y + connect \$28 $eq$libresoc.v:146018$7256_Y + connect \$30 $eq$libresoc.v:146019$7257_Y + connect \$32 $eq$libresoc.v:146020$7258_Y + connect \$34 $or$libresoc.v:146021$7259_Y + connect \$36 $eq$libresoc.v:146022$7260_Y + connect \$38 $eq$libresoc.v:146023$7261_Y + connect \$40 $or$libresoc.v:146024$7262_Y + connect \$42 $eq$libresoc.v:146025$7263_Y + connect \$44 $eq$libresoc.v:146026$7264_Y + connect \$46 $or$libresoc.v:146027$7265_Y + connect \$49 $add$libresoc.v:146028$7266_Y + connect \$51 $not$libresoc.v:146029$7267_Y + connect \$53 $xor$libresoc.v:146030$7268_Y + connect \$55 $xor$libresoc.v:146031$7269_Y + connect \$59 $xor$libresoc.v:146032$7270_Y + connect \$58 $reduce_or$libresoc.v:146033$7271_Y + connect \$57 $not$libresoc.v:146034$7272_Y + connect \$65 $xor$libresoc.v:146035$7273_Y + connect \$64 $reduce_or$libresoc.v:146036$7274_Y + connect \$63 $not$libresoc.v:146037$7275_Y + connect \$69 $or$libresoc.v:146038$7276_Y + connect \$71 $and$libresoc.v:146039$7277_Y + connect \$73 $ne$libresoc.v:146040$7278_Y + connect \$75 $not$libresoc.v:146041$7279_Y + connect \$77 $not$libresoc.v:146042$7280_Y + connect \$79 $or$libresoc.v:146043$7281_Y + connect \$81 $and$libresoc.v:146044$7282_Y + connect \$83 $ternary$libresoc.v:146045$7283_Y + connect \$85 $or$libresoc.v:146046$7284_Y + connect \$87 $and$libresoc.v:146047$7285_Y + connect \$89 $ternary$libresoc.v:146048$7286_Y + connect \$91 $or$libresoc.v:146049$7287_Y + connect \$93 $and$libresoc.v:146050$7288_Y + connect \$95 $ne$libresoc.v:146051$7289_Y + connect \$97 $ternary$libresoc.v:146052$7290_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:136718.1-137126.10" +attribute \src "libresoc.v:146495.1-146909.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 - attribute \src "libresoc.v:136719.7-136719.20" + attribute \src "libresoc.v:146496.7-146496.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137078.3-137108.6" + attribute \src "libresoc.v:146861.3-146891.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:137043.3-137077.6" + attribute \src "libresoc.v:146826.3-146860.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:137078.3-137108.6" + attribute \src "libresoc.v:146861.3-146891.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:137043.3-137077.6" + attribute \src "libresoc.v:146826.3-146860.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:136719.7-136719.15" + attribute \src "libresoc.v:146496.7-146496.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -288370,9 +307171,9 @@ module \main$114 wire width 5 \me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" wire width 4 \mode - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 40 \o @@ -288413,35 +307214,39 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire \rotator_sign_ext_rs attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \sr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -288544,6 +307349,7 @@ module \main$114 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -288620,6 +307426,7 @@ module \main$114 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -288669,7 +307476,7 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:137027.11-137042.4" + attribute \src "libresoc.v:146810.11-146825.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -288686,22 +307493,22 @@ module \main$114 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:136719.7-136719.20" - process $proc$libresoc.v:136719$7001 + attribute \src "libresoc.v:146496.7-146496.20" + process $proc$libresoc.v:146496$7323 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137043.3-137077.6" - process $proc$libresoc.v:137043$6999 + attribute \src "libresoc.v:146826.3-146860.6" + process $proc$libresoc.v:146826$7321 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:137044.5-137044.29" + attribute \src "libresoc.v:146827.5-146827.29" switch \initial - attribute \src "libresoc.v:137044.9-137044.17" + attribute \src "libresoc.v:146827.9-146827.17" case 1'1 case end @@ -288733,14 +307540,14 @@ module \main$114 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:137078.3-137108.6" - process $proc$libresoc.v:137078$7000 + attribute \src "libresoc.v:146861.3-146891.6" + process $proc$libresoc.v:146861$7322 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:137079.5-137079.29" + attribute \src "libresoc.v:146862.5-146862.29" switch \initial - attribute \src "libresoc.v:137079.9-137079.17" + attribute \src "libresoc.v:146862.9-146862.17" case 1'1 case end @@ -288794,109 +307601,109 @@ module \main$114 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:137130.1-137660.10" +attribute \src "libresoc.v:146913.1-147449.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:137567.3-137590.6" + attribute \src "libresoc.v:147356.3-147379.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:137446.3-137457.6" + attribute \src "libresoc.v:147235.3-147246.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:137458.3-137484.6" + attribute \src "libresoc.v:147247.3-147273.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:137485.3-137503.6" + attribute \src "libresoc.v:147274.3-147292.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:137539.3-137553.6" + attribute \src "libresoc.v:147328.3-147342.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:137617.3-137637.6" + attribute \src "libresoc.v:147406.3-147426.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:137591.3-137603.6" + attribute \src "libresoc.v:147380.3-147392.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:137554.3-137566.6" + attribute \src "libresoc.v:147343.3-147355.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:137638.3-137650.6" + attribute \src "libresoc.v:147427.3-147439.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:137604.3-137616.6" - wire width 64 $0\fast1$10[63:0]$7034 - attribute \src "libresoc.v:137504.3-137518.6" + attribute \src "libresoc.v:147393.3-147405.6" + wire width 64 $0\fast1$10[63:0]$7356 + attribute \src "libresoc.v:147293.3-147307.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:137519.3-137528.6" - wire width 64 $0\fast2$11[63:0]$7026 - attribute \src "libresoc.v:137529.3-137538.6" + attribute \src "libresoc.v:147308.3-147317.6" + wire width 64 $0\fast2$11[63:0]$7348 + attribute \src "libresoc.v:147318.3-147327.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:137131.7-137131.20" + attribute \src "libresoc.v:146914.7-146914.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137567.3-137590.6" + attribute \src "libresoc.v:147356.3-147379.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:137446.3-137457.6" + attribute \src "libresoc.v:147235.3-147246.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:137458.3-137484.6" + attribute \src "libresoc.v:147247.3-147273.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:137485.3-137503.6" + attribute \src "libresoc.v:147274.3-147292.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:137539.3-137553.6" + attribute \src "libresoc.v:147328.3-147342.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:137617.3-137637.6" + attribute \src "libresoc.v:147406.3-147426.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:137591.3-137603.6" + attribute \src "libresoc.v:147380.3-147392.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:137554.3-137566.6" + attribute \src "libresoc.v:147343.3-147355.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:137638.3-137650.6" + attribute \src "libresoc.v:147427.3-147439.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:137604.3-137616.6" - wire width 64 $1\fast1$10[63:0]$7035 - attribute \src "libresoc.v:137504.3-137518.6" + attribute \src "libresoc.v:147393.3-147405.6" + wire width 64 $1\fast1$10[63:0]$7357 + attribute \src "libresoc.v:147293.3-147307.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:137519.3-137528.6" - wire width 64 $1\fast2$11[63:0]$7027 - attribute \src "libresoc.v:137529.3-137538.6" + attribute \src "libresoc.v:147308.3-147317.6" + wire width 64 $1\fast2$11[63:0]$7349 + attribute \src "libresoc.v:147318.3-147327.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:137567.3-137590.6" + attribute \src "libresoc.v:147356.3-147379.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:137458.3-137484.6" + attribute \src "libresoc.v:147247.3-147273.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:137617.3-137637.6" + attribute \src "libresoc.v:147406.3-147426.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:137430.18-137430.119" - wire width 65 $add$libresoc.v:137430$7004_Y - attribute \src "libresoc.v:137445.18-137445.113" - wire width 65 $add$libresoc.v:137445$7020_Y - attribute \src "libresoc.v:137437.18-137437.115" - wire $and$libresoc.v:137437$7011_Y - attribute \src "libresoc.v:137438.18-137438.117" - wire $and$libresoc.v:137438$7012_Y - attribute \src "libresoc.v:137444.18-137444.118" - wire $and$libresoc.v:137444$7019_Y - attribute \src "libresoc.v:137428.18-137428.120" - wire $eq$libresoc.v:137428$7002_Y - attribute \src "libresoc.v:137431.18-137431.111" - wire $eq$libresoc.v:137431$7005_Y - attribute \src "libresoc.v:137433.18-137433.111" - wire $eq$libresoc.v:137433$7007_Y - attribute \src "libresoc.v:137434.18-137434.111" - wire $eq$libresoc.v:137434$7008_Y - attribute \src "libresoc.v:137435.18-137435.109" - wire $eq$libresoc.v:137435$7009_Y - attribute \src "libresoc.v:137440.18-137440.98" - wire width 64 $extend$libresoc.v:137440$7014_Y - attribute \src "libresoc.v:137436.18-137436.104" - wire $not$libresoc.v:137436$7010_Y - attribute \src "libresoc.v:137443.18-137443.112" - wire $not$libresoc.v:137443$7018_Y - attribute \src "libresoc.v:137429.18-137429.116" - wire $or$libresoc.v:137429$7003_Y - attribute \src "libresoc.v:137432.18-137432.109" - wire $or$libresoc.v:137432$7006_Y - attribute \src "libresoc.v:137440.18-137440.98" - wire width 64 $pos$libresoc.v:137440$7015_Y - attribute \src "libresoc.v:137441.18-137441.103" - wire $reduce_or$libresoc.v:137441$7016_Y - attribute \src "libresoc.v:137439.18-137439.108" - wire width 65 $sub$libresoc.v:137439$7013_Y - attribute \src "libresoc.v:137442.18-137442.108" - wire $xor$libresoc.v:137442$7017_Y + attribute \src "libresoc.v:147219.18-147219.119" + wire width 65 $add$libresoc.v:147219$7326_Y + attribute \src "libresoc.v:147234.18-147234.113" + wire width 65 $add$libresoc.v:147234$7342_Y + attribute \src "libresoc.v:147226.18-147226.115" + wire $and$libresoc.v:147226$7333_Y + attribute \src "libresoc.v:147227.18-147227.117" + wire $and$libresoc.v:147227$7334_Y + attribute \src "libresoc.v:147233.18-147233.118" + wire $and$libresoc.v:147233$7341_Y + attribute \src "libresoc.v:147217.18-147217.120" + wire $eq$libresoc.v:147217$7324_Y + attribute \src "libresoc.v:147220.18-147220.111" + wire $eq$libresoc.v:147220$7327_Y + attribute \src "libresoc.v:147222.18-147222.111" + wire $eq$libresoc.v:147222$7329_Y + attribute \src "libresoc.v:147223.18-147223.111" + wire $eq$libresoc.v:147223$7330_Y + attribute \src "libresoc.v:147224.18-147224.109" + wire $eq$libresoc.v:147224$7331_Y + attribute \src "libresoc.v:147229.18-147229.98" + wire width 64 $extend$libresoc.v:147229$7336_Y + attribute \src "libresoc.v:147225.18-147225.104" + wire $not$libresoc.v:147225$7332_Y + attribute \src "libresoc.v:147232.18-147232.112" + wire $not$libresoc.v:147232$7340_Y + attribute \src "libresoc.v:147218.18-147218.116" + wire $or$libresoc.v:147218$7325_Y + attribute \src "libresoc.v:147221.18-147221.109" + wire $or$libresoc.v:147221$7328_Y + attribute \src "libresoc.v:147229.18-147229.98" + wire width 64 $pos$libresoc.v:147229$7337_Y + attribute \src "libresoc.v:147230.18-147230.103" + wire $reduce_or$libresoc.v:147230$7338_Y + attribute \src "libresoc.v:147228.18-147228.108" + wire width 65 $sub$libresoc.v:147228$7335_Y + attribute \src "libresoc.v:147231.18-147231.108" + wire $xor$libresoc.v:147231$7339_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -288954,35 +307761,39 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 13 \br_op__cia$2 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \br_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 15 \br_op__fn_unit$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 15 \br_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 5 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -289069,6 +307880,7 @@ module \main$22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \br_op__insn_type attribute \enum_base_type "MicrOp" @@ -289145,6 +307957,7 @@ module \main$22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 14 \br_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -289181,18 +307994,18 @@ module \main$22 wire width 64 output 23 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \fast2_ok - attribute \src "libresoc.v:137131.7-137131.15" + attribute \src "libresoc.v:146914.7-146914.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 12 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 25 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:137430$7004 + cell $add $add$libresoc.v:147219$7326 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -289200,10 +308013,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:137430$7004_Y + connect \Y $add$libresoc.v:147219$7326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:137445$7020 + cell $add $add$libresoc.v:147234$7342 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -289211,10 +308024,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:137445$7020_Y + connect \Y $add$libresoc.v:147234$7342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:137437$7011 + cell $and $and$libresoc.v:147226$7333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -289222,10 +308035,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:137437$7011_Y + connect \Y $and$libresoc.v:147226$7333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:137438$7012 + cell $and $and$libresoc.v:147227$7334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -289233,10 +308046,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:137438$7012_Y + connect \Y $and$libresoc.v:147227$7334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:137444$7019 + cell $and $and$libresoc.v:147233$7341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -289244,10 +308057,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:137444$7019_Y + connect \Y $and$libresoc.v:147233$7341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:137428$7002 + cell $eq $eq$libresoc.v:147217$7324 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -289255,10 +308068,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:137428$7002_Y + connect \Y $eq$libresoc.v:147217$7324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:137431$7005 + cell $eq $eq$libresoc.v:147220$7327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -289266,10 +308079,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:137431$7005_Y + connect \Y $eq$libresoc.v:147220$7327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:137433$7007 + cell $eq $eq$libresoc.v:147222$7329 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -289277,10 +308090,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:137433$7007_Y + connect \Y $eq$libresoc.v:147222$7329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:137434$7008 + cell $eq $eq$libresoc.v:147223$7330 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -289288,10 +308101,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:137434$7008_Y + connect \Y $eq$libresoc.v:147223$7330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:137435$7009 + cell $eq $eq$libresoc.v:147224$7331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -289299,34 +308112,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:137435$7009_Y + connect \Y $eq$libresoc.v:147224$7331_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:137440$7014 + cell $pos $extend$libresoc.v:147229$7336 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:137440$7014_Y + connect \Y $extend$libresoc.v:147229$7336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:137436$7010 + cell $not $not$libresoc.v:147225$7332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:137436$7010_Y + connect \Y $not$libresoc.v:147225$7332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:137443$7018 + cell $not $not$libresoc.v:147232$7340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:137443$7018_Y + connect \Y $not$libresoc.v:147232$7340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:137429$7003 + cell $or $or$libresoc.v:147218$7325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -289334,10 +308147,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:137429$7003_Y + connect \Y $or$libresoc.v:147218$7325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:137432$7006 + cell $or $or$libresoc.v:147221$7328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -289345,26 +308158,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:137432$7006_Y + connect \Y $or$libresoc.v:147221$7328_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:137440$7015 + cell $pos $pos$libresoc.v:147229$7337 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:137440$7014_Y - connect \Y $pos$libresoc.v:137440$7015_Y + connect \A $extend$libresoc.v:147229$7336_Y + connect \Y $pos$libresoc.v:147229$7337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:137441$7016 + cell $reduce_or $reduce_or$libresoc.v:147230$7338 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:137441$7016_Y + connect \Y $reduce_or$libresoc.v:147230$7338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:137439$7013 + cell $sub $sub$libresoc.v:147228$7335 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -289372,10 +308185,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:137439$7013_Y + connect \Y $sub$libresoc.v:147228$7335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:137442$7017 + cell $xor $xor$libresoc.v:147231$7339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -289383,23 +308196,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:137442$7017_Y + connect \Y $xor$libresoc.v:147231$7339_Y end - attribute \src "libresoc.v:137131.7-137131.20" - process $proc$libresoc.v:137131$7038 + attribute \src "libresoc.v:146914.7-146914.20" + process $proc$libresoc.v:146914$7360 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137446.3-137457.6" - process $proc$libresoc.v:137446$7021 + attribute \src "libresoc.v:147235.3-147246.6" + process $proc$libresoc.v:147235$7343 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:137447.5-137447.29" + attribute \src "libresoc.v:147236.5-147236.29" switch \initial - attribute \src "libresoc.v:137447.9-137447.17" + attribute \src "libresoc.v:147236.9-147236.17" case 1'1 case end @@ -289417,14 +308230,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:137458.3-137484.6" - process $proc$libresoc.v:137458$7022 + attribute \src "libresoc.v:147247.3-147273.6" + process $proc$libresoc.v:147247$7344 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:137459.5-137459.29" + attribute \src "libresoc.v:147248.5-147248.29" switch \initial - attribute \src "libresoc.v:137459.9-137459.17" + attribute \src "libresoc.v:147248.9-147248.17" case 1'1 case end @@ -289459,14 +308272,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:137485.3-137503.6" - process $proc$libresoc.v:137485$7023 + attribute \src "libresoc.v:147274.3-147292.6" + process $proc$libresoc.v:147274$7345 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:137486.5-137486.29" + attribute \src "libresoc.v:147275.5-147275.29" switch \initial - attribute \src "libresoc.v:137486.9-137486.17" + attribute \src "libresoc.v:147275.9-147275.17" case 1'1 case end @@ -289490,14 +308303,14 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:137504.3-137518.6" - process $proc$libresoc.v:137504$7024 + attribute \src "libresoc.v:147293.3-147307.6" + process $proc$libresoc.v:147293$7346 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:137505.5-137505.29" + attribute \src "libresoc.v:147294.5-147294.29" switch \initial - attribute \src "libresoc.v:137505.9-137505.17" + attribute \src "libresoc.v:147294.9-147294.17" case 1'1 case end @@ -289517,14 +308330,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:137519.3-137528.6" - process $proc$libresoc.v:137519$7025 + attribute \src "libresoc.v:147308.3-147317.6" + process $proc$libresoc.v:147308$7347 assign { } { } assign { } { } - assign $0\fast2$11[63:0]$7026 $1\fast2$11[63:0]$7027 - attribute \src "libresoc.v:137520.5-137520.29" + assign $0\fast2$11[63:0]$7348 $1\fast2$11[63:0]$7349 + attribute \src "libresoc.v:147309.5-147309.29" switch \initial - attribute \src "libresoc.v:137520.9-137520.17" + attribute \src "libresoc.v:147309.9-147309.17" case 1'1 case end @@ -289533,21 +308346,21 @@ module \main$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast2$11[63:0]$7027 \$48 [63:0] + assign $1\fast2$11[63:0]$7349 \$48 [63:0] case - assign $1\fast2$11[63:0]$7027 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$11[63:0]$7349 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$11 $0\fast2$11[63:0]$7026 + update \fast2$11 $0\fast2$11[63:0]$7348 end - attribute \src "libresoc.v:137529.3-137538.6" - process $proc$libresoc.v:137529$7028 + attribute \src "libresoc.v:147318.3-147327.6" + process $proc$libresoc.v:147318$7350 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:137530.5-137530.29" + attribute \src "libresoc.v:147319.5-147319.29" switch \initial - attribute \src "libresoc.v:137530.9-137530.17" + attribute \src "libresoc.v:147319.9-147319.17" case 1'1 case end @@ -289563,14 +308376,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:137539.3-137553.6" - process $proc$libresoc.v:137539$7029 + attribute \src "libresoc.v:147328.3-147342.6" + process $proc$libresoc.v:147328$7351 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:137540.5-137540.29" + attribute \src "libresoc.v:147329.5-147329.29" switch \initial - attribute \src "libresoc.v:137540.9-137540.17" + attribute \src "libresoc.v:147329.9-147329.17" case 1'1 case end @@ -289598,14 +308411,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:137554.3-137566.6" - process $proc$libresoc.v:137554$7030 + attribute \src "libresoc.v:147343.3-147355.6" + process $proc$libresoc.v:147343$7352 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:137555.5-137555.29" + attribute \src "libresoc.v:147344.5-147344.29" switch \initial - attribute \src "libresoc.v:137555.9-137555.17" + attribute \src "libresoc.v:147344.9-147344.17" case 1'1 case end @@ -289622,14 +308435,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:137567.3-137590.6" - process $proc$libresoc.v:137567$7031 + attribute \src "libresoc.v:147356.3-147379.6" + process $proc$libresoc.v:147356$7353 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:137568.5-137568.29" + attribute \src "libresoc.v:147357.5-147357.29" switch \initial - attribute \src "libresoc.v:137568.9-137568.17" + attribute \src "libresoc.v:147357.9-147357.17" case 1'1 case end @@ -289664,14 +308477,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:137591.3-137603.6" - process $proc$libresoc.v:137591$7032 + attribute \src "libresoc.v:147380.3-147392.6" + process $proc$libresoc.v:147380$7354 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:137592.5-137592.29" + attribute \src "libresoc.v:147381.5-147381.29" switch \initial - attribute \src "libresoc.v:137592.9-137592.17" + attribute \src "libresoc.v:147381.9-147381.17" case 1'1 case end @@ -289688,14 +308501,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:137604.3-137616.6" - process $proc$libresoc.v:137604$7033 + attribute \src "libresoc.v:147393.3-147405.6" + process $proc$libresoc.v:147393$7355 assign { } { } assign { } { } - assign $0\fast1$10[63:0]$7034 $1\fast1$10[63:0]$7035 - attribute \src "libresoc.v:137605.5-137605.29" + assign $0\fast1$10[63:0]$7356 $1\fast1$10[63:0]$7357 + attribute \src "libresoc.v:147394.5-147394.29" switch \initial - attribute \src "libresoc.v:137605.9-137605.17" + attribute \src "libresoc.v:147394.9-147394.17" case 1'1 case end @@ -289703,23 +308516,23 @@ module \main$22 switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $1\fast1$10[63:0]$7035 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$10[63:0]$7357 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\fast1$10[63:0]$7035 \ctr_n + assign $1\fast1$10[63:0]$7357 \ctr_n end sync always - update \fast1$10 $0\fast1$10[63:0]$7034 + update \fast1$10 $0\fast1$10[63:0]$7356 end - attribute \src "libresoc.v:137617.3-137637.6" - process $proc$libresoc.v:137617$7036 + attribute \src "libresoc.v:147406.3-147426.6" + process $proc$libresoc.v:147406$7358 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:137618.5-137618.29" + attribute \src "libresoc.v:147407.5-147407.29" switch \initial - attribute \src "libresoc.v:137618.9-137618.17" + attribute \src "libresoc.v:147407.9-147407.17" case 1'1 case end @@ -289747,14 +308560,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:137638.3-137650.6" - process $proc$libresoc.v:137638$7037 + attribute \src "libresoc.v:147427.3-147439.6" + process $proc$libresoc.v:147427$7359 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:137639.5-137639.29" + attribute \src "libresoc.v:147428.5-147428.29" switch \initial - attribute \src "libresoc.v:137639.9-137639.17" + attribute \src "libresoc.v:147428.9-147428.17" case 1'1 case end @@ -289771,24 +308584,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:137428$7002_Y - connect \$14 $or$libresoc.v:137429$7003_Y - connect \$17 $add$libresoc.v:137430$7004_Y - connect \$19 $eq$libresoc.v:137431$7005_Y - connect \$21 $or$libresoc.v:137432$7006_Y - connect \$23 $eq$libresoc.v:137433$7007_Y - connect \$25 $eq$libresoc.v:137434$7008_Y - connect \$27 $eq$libresoc.v:137435$7009_Y - connect \$29 $not$libresoc.v:137436$7010_Y - connect \$31 $and$libresoc.v:137437$7011_Y - connect \$33 $and$libresoc.v:137438$7012_Y - connect \$36 $sub$libresoc.v:137439$7013_Y - connect \$38 $pos$libresoc.v:137440$7015_Y - connect \$40 $reduce_or$libresoc.v:137441$7016_Y - connect \$42 $xor$libresoc.v:137442$7017_Y - connect \$44 $not$libresoc.v:137443$7018_Y - connect \$46 $and$libresoc.v:137444$7019_Y - connect \$49 $add$libresoc.v:137445$7020_Y + connect \$12 $eq$libresoc.v:147217$7324_Y + connect \$14 $or$libresoc.v:147218$7325_Y + connect \$17 $add$libresoc.v:147219$7326_Y + connect \$19 $eq$libresoc.v:147220$7327_Y + connect \$21 $or$libresoc.v:147221$7328_Y + connect \$23 $eq$libresoc.v:147222$7329_Y + connect \$25 $eq$libresoc.v:147223$7330_Y + connect \$27 $eq$libresoc.v:147224$7331_Y + connect \$29 $not$libresoc.v:147225$7332_Y + connect \$31 $and$libresoc.v:147226$7333_Y + connect \$33 $and$libresoc.v:147227$7334_Y + connect \$36 $sub$libresoc.v:147228$7335_Y + connect \$38 $pos$libresoc.v:147229$7337_Y + connect \$40 $reduce_or$libresoc.v:147230$7338_Y + connect \$42 $xor$libresoc.v:147231$7339_Y + connect \$44 $not$libresoc.v:147232$7340_Y + connect \$46 $and$libresoc.v:147233$7341_Y + connect \$49 $add$libresoc.v:147234$7342_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -289799,279 +308612,279 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:137664.1-138608.10" +attribute \src "libresoc.v:147453.1-148403.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 - attribute \src "libresoc.v:138573.3-138584.6" + attribute \src "libresoc.v:148368.3-148379.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:138071.3-138082.6" + attribute \src "libresoc.v:147866.3-147877.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:138585.3-138596.6" + attribute \src "libresoc.v:148380.3-148391.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:138354.3-138365.6" + attribute \src "libresoc.v:148149.3-148160.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:138147.3-138178.6" - wire width 64 $0\fast1$11[63:0]$7084 - attribute \src "libresoc.v:138179.3-138210.6" + attribute \src "libresoc.v:147942.3-147973.6" + wire width 64 $0\fast1$11[63:0]$7406 + attribute \src "libresoc.v:147974.3-148005.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:138211.3-138293.6" - wire width 64 $0\fast2$12[63:0]$7089 - attribute \src "libresoc.v:138294.3-138325.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire width 64 $0\fast2$12[63:0]$7411 + attribute \src "libresoc.v:148089.3-148120.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:137665.7-137665.20" + attribute \src "libresoc.v:147454.7-147454.20" wire $0\initial[0:0] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:138083.3-138114.6" + attribute \src "libresoc.v:147878.3-147909.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:138115.3-138146.6" + attribute \src "libresoc.v:147910.3-147941.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:138535.3-138553.6" + attribute \src "libresoc.v:148330.3-148348.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:138554.3-138572.6" + attribute \src "libresoc.v:148349.3-148367.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:138326.3-138353.6" - wire $0\trapexc_$signal$60[0:0]$7103 - attribute \src "libresoc.v:138326.3-138353.6" - wire $0\trapexc_$signal$61[0:0]$7104 - attribute \src "libresoc.v:138326.3-138353.6" - wire $0\trapexc_$signal$62[0:0]$7105 - attribute \src "libresoc.v:138326.3-138353.6" - wire $0\trapexc_$signal$67[0:0]$7106 - attribute \src "libresoc.v:138326.3-138353.6" - wire $0\trapexc_$signal$68[0:0]$7107 - attribute \src "libresoc.v:138326.3-138353.6" - wire $0\trapexc_$signal$69[0:0]$7108 - attribute \src "libresoc.v:138326.3-138353.6" - wire $0\trapexc_$signal$70[0:0]$7109 - attribute \src "libresoc.v:138326.3-138353.6" - wire $0\trapexc_$signal[0:0]$7102 - attribute \src "libresoc.v:138211.3-138293.6" - wire $10\fast2$12[19:19]$7099 - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$60[0:0]$7425 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$61[0:0]$7426 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$62[0:0]$7427 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$67[0:0]$7428 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$68[0:0]$7429 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$69[0:0]$7430 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$70[0:0]$7431 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal[0:0]$7424 + attribute \src "libresoc.v:148006.3-148088.6" + wire $10\fast2$12[19:19]$7421 + attribute \src "libresoc.v:148161.3-148329.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $11\msr[15:15] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $12\msr[12:12] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $13\msr[60:60] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $14\msr[12:12] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $15\msr[12:12] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $17\msr[15:15] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:138573.3-138584.6" + attribute \src "libresoc.v:148368.3-148379.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:138071.3-138082.6" + attribute \src "libresoc.v:147866.3-147877.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:138585.3-138596.6" + attribute \src "libresoc.v:148380.3-148391.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:138354.3-138365.6" + attribute \src "libresoc.v:148149.3-148160.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:138147.3-138178.6" - wire width 64 $1\fast1$11[63:0]$7085 - attribute \src "libresoc.v:138179.3-138210.6" + attribute \src "libresoc.v:147942.3-147973.6" + wire width 64 $1\fast1$11[63:0]$7407 + attribute \src "libresoc.v:147974.3-148005.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:138211.3-138293.6" - wire width 64 $1\fast2$12[63:0]$7090 - attribute \src "libresoc.v:138294.3-138325.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire width 64 $1\fast2$12[63:0]$7412 + attribute \src "libresoc.v:148089.3-148120.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:138083.3-138114.6" + attribute \src "libresoc.v:147878.3-147909.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:138115.3-138146.6" + attribute \src "libresoc.v:147910.3-147941.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:138535.3-138553.6" + attribute \src "libresoc.v:148330.3-148348.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:138554.3-138572.6" + attribute \src "libresoc.v:148349.3-148367.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:138326.3-138353.6" - wire $1\trapexc_$signal$60[0:0]$7111 - attribute \src "libresoc.v:138326.3-138353.6" - wire $1\trapexc_$signal$61[0:0]$7112 - attribute \src "libresoc.v:138326.3-138353.6" - wire $1\trapexc_$signal$62[0:0]$7113 - attribute \src "libresoc.v:138326.3-138353.6" - wire $1\trapexc_$signal$67[0:0]$7114 - attribute \src "libresoc.v:138326.3-138353.6" - wire $1\trapexc_$signal$68[0:0]$7115 - attribute \src "libresoc.v:138326.3-138353.6" - wire $1\trapexc_$signal$69[0:0]$7116 - attribute \src "libresoc.v:138326.3-138353.6" - wire $1\trapexc_$signal$70[0:0]$7117 - attribute \src "libresoc.v:138326.3-138353.6" - wire $1\trapexc_$signal[0:0]$7110 - attribute \src "libresoc.v:138147.3-138178.6" - wire width 64 $2\fast1$11[63:0]$7086 - attribute \src "libresoc.v:138179.3-138210.6" + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$60[0:0]$7433 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$61[0:0]$7434 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$62[0:0]$7435 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$67[0:0]$7436 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$68[0:0]$7437 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$69[0:0]$7438 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$70[0:0]$7439 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal[0:0]$7432 + attribute \src "libresoc.v:147942.3-147973.6" + wire width 64 $2\fast1$11[63:0]$7408 + attribute \src "libresoc.v:147974.3-148005.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:138211.3-138293.6" - wire width 64 $2\fast2$12[63:0]$7091 - attribute \src "libresoc.v:138294.3-138325.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire width 64 $2\fast2$12[63:0]$7413 + attribute \src "libresoc.v:148089.3-148120.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:138083.3-138114.6" + attribute \src "libresoc.v:147878.3-147909.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:138115.3-138146.6" + attribute \src "libresoc.v:147910.3-147941.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:138326.3-138353.6" - wire $2\trapexc_$signal$60[0:0]$7119 - attribute \src "libresoc.v:138326.3-138353.6" - wire $2\trapexc_$signal$61[0:0]$7120 - attribute \src "libresoc.v:138326.3-138353.6" - wire $2\trapexc_$signal$62[0:0]$7121 - attribute \src "libresoc.v:138326.3-138353.6" - wire $2\trapexc_$signal$67[0:0]$7122 - attribute \src "libresoc.v:138326.3-138353.6" - wire $2\trapexc_$signal$68[0:0]$7123 - attribute \src "libresoc.v:138326.3-138353.6" - wire $2\trapexc_$signal$69[0:0]$7124 - attribute \src "libresoc.v:138326.3-138353.6" - wire $2\trapexc_$signal$70[0:0]$7125 - attribute \src "libresoc.v:138326.3-138353.6" - wire $2\trapexc_$signal[0:0]$7118 - attribute \src "libresoc.v:138211.3-138293.6" - wire $3\fast2$12[17:17]$7092 - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$60[0:0]$7441 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$61[0:0]$7442 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$62[0:0]$7443 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$67[0:0]$7444 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$68[0:0]$7445 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$69[0:0]$7446 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$70[0:0]$7447 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal[0:0]$7440 + attribute \src "libresoc.v:148006.3-148088.6" + wire $3\fast2$12[17:17]$7414 + attribute \src "libresoc.v:148161.3-148329.6" wire width 11 $3\msr[11:1] - attribute \src "libresoc.v:138326.3-138353.6" - wire $3\trapexc_$signal$60[0:0]$7127 - attribute \src "libresoc.v:138326.3-138353.6" - wire $3\trapexc_$signal$61[0:0]$7128 - attribute \src "libresoc.v:138326.3-138353.6" - wire $3\trapexc_$signal$62[0:0]$7129 - attribute \src "libresoc.v:138326.3-138353.6" - wire $3\trapexc_$signal$67[0:0]$7130 - attribute \src "libresoc.v:138326.3-138353.6" - wire $3\trapexc_$signal$68[0:0]$7131 - attribute \src "libresoc.v:138326.3-138353.6" - wire $3\trapexc_$signal$69[0:0]$7132 - attribute \src "libresoc.v:138326.3-138353.6" - wire $3\trapexc_$signal$70[0:0]$7133 - attribute \src "libresoc.v:138326.3-138353.6" - wire $3\trapexc_$signal[0:0]$7126 - attribute \src "libresoc.v:138211.3-138293.6" - wire $4\fast2$12[18:18]$7093 - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$60[0:0]$7449 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$61[0:0]$7450 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$62[0:0]$7451 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$67[0:0]$7452 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$68[0:0]$7453 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$69[0:0]$7454 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$70[0:0]$7455 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal[0:0]$7448 + attribute \src "libresoc.v:148006.3-148088.6" + wire $4\fast2$12[18:18]$7415 + attribute \src "libresoc.v:148161.3-148329.6" wire width 47 $4\msr[59:13] - attribute \src "libresoc.v:138211.3-138293.6" - wire $5\fast2$12[20:20]$7094 - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire $5\fast2$12[20:20]$7416 + attribute \src "libresoc.v:148161.3-148329.6" wire width 3 $5\msr[63:61] - attribute \src "libresoc.v:138211.3-138293.6" - wire $6\fast2$12[16:16]$7095 - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire $6\fast2$12[16:16]$7417 + attribute \src "libresoc.v:148161.3-148329.6" wire width 11 $6\msr[11:1] - attribute \src "libresoc.v:138211.3-138293.6" - wire width 2 $7\fast2$12[19:18]$7096 - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire width 2 $7\fast2$12[19:18]$7418 + attribute \src "libresoc.v:148161.3-148329.6" wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:138211.3-138293.6" - wire $8\fast2$12[28:28]$7097 - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire $8\fast2$12[28:28]$7419 + attribute \src "libresoc.v:148161.3-148329.6" wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:138211.3-138293.6" - wire $9\fast2$12[30:30]$7098 - attribute \src "libresoc.v:138366.3-138534.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire $9\fast2$12[30:30]$7420 + attribute \src "libresoc.v:148161.3-148329.6" wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:138047.18-138047.113" - wire width 65 $add$libresoc.v:138047$7055_Y - attribute \src "libresoc.v:138041.18-138041.108" - wire width 5 $and$libresoc.v:138041$7048_Y - attribute \src "libresoc.v:138049.18-138049.118" - wire width 8 $and$libresoc.v:138049$7057_Y - attribute \src "libresoc.v:138051.18-138051.118" - wire width 8 $and$libresoc.v:138051$7059_Y - attribute \src "libresoc.v:138053.18-138053.118" - wire width 8 $and$libresoc.v:138053$7061_Y - attribute \src "libresoc.v:138055.18-138055.119" - wire width 8 $and$libresoc.v:138055$7063_Y - attribute \src "libresoc.v:138057.18-138057.119" - wire width 8 $and$libresoc.v:138057$7065_Y - attribute \src "libresoc.v:138059.18-138059.119" - wire width 8 $and$libresoc.v:138059$7067_Y - attribute \src "libresoc.v:138065.18-138065.106" - wire $and$libresoc.v:138065$7074_Y - attribute \src "libresoc.v:138070.18-138070.106" - wire $and$libresoc.v:138070$7079_Y - attribute \src "libresoc.v:138040.18-138040.100" - wire $eq$libresoc.v:138040$7047_Y - attribute \src "libresoc.v:138048.18-138048.119" - wire $eq$libresoc.v:138048$7056_Y - attribute \src "libresoc.v:138062.18-138062.121" - wire $eq$libresoc.v:138062$7071_Y - attribute \src "libresoc.v:138063.18-138063.121" - wire $eq$libresoc.v:138063$7072_Y - attribute \src "libresoc.v:138064.18-138064.111" - wire $eq$libresoc.v:138064$7073_Y - attribute \src "libresoc.v:138068.18-138068.121" - wire $eq$libresoc.v:138068$7077_Y - attribute \src "libresoc.v:138069.18-138069.114" - wire $eq$libresoc.v:138069$7078_Y - attribute \src "libresoc.v:138034.18-138034.95" - wire width 64 $extend$libresoc.v:138034$7039_Y - attribute \src "libresoc.v:138035.18-138035.95" - wire width 64 $extend$libresoc.v:138035$7041_Y - attribute \src "libresoc.v:138046.18-138046.100" - wire width 64 $extend$libresoc.v:138046$7053_Y - attribute \src "libresoc.v:138061.18-138061.109" - wire width 65 $extend$libresoc.v:138061$7069_Y - attribute \src "libresoc.v:138037.18-138037.121" - wire $gt$libresoc.v:138037$7044_Y - attribute \src "libresoc.v:138039.18-138039.99" - wire $gt$libresoc.v:138039$7046_Y - attribute \src "libresoc.v:138036.18-138036.121" - wire $lt$libresoc.v:138036$7043_Y - attribute \src "libresoc.v:138038.18-138038.99" - wire $lt$libresoc.v:138038$7045_Y - attribute \src "libresoc.v:138066.18-138066.112" - wire $not$libresoc.v:138066$7075_Y - attribute \src "libresoc.v:138067.18-138067.112" - wire $not$libresoc.v:138067$7076_Y - attribute \src "libresoc.v:138044.18-138044.106" - wire $or$libresoc.v:138044$7051_Y - attribute \src "libresoc.v:138034.18-138034.95" - wire width 64 $pos$libresoc.v:138034$7040_Y - attribute \src "libresoc.v:138035.18-138035.95" - wire width 64 $pos$libresoc.v:138035$7042_Y - attribute \src "libresoc.v:138046.18-138046.100" - wire width 64 $pos$libresoc.v:138046$7054_Y - attribute \src "libresoc.v:138061.18-138061.109" - wire width 65 $pos$libresoc.v:138061$7070_Y - attribute \src "libresoc.v:138042.18-138042.100" - wire $reduce_or$libresoc.v:138042$7049_Y - attribute \src "libresoc.v:138043.18-138043.113" - wire $reduce_or$libresoc.v:138043$7050_Y - attribute \src "libresoc.v:138050.18-138050.91" - wire $reduce_or$libresoc.v:138050$7058_Y - attribute \src "libresoc.v:138052.18-138052.91" - wire $reduce_or$libresoc.v:138052$7060_Y - attribute \src "libresoc.v:138054.18-138054.91" - wire $reduce_or$libresoc.v:138054$7062_Y - attribute \src "libresoc.v:138056.18-138056.91" - wire $reduce_or$libresoc.v:138056$7064_Y - attribute \src "libresoc.v:138058.18-138058.91" - wire $reduce_or$libresoc.v:138058$7066_Y - attribute \src "libresoc.v:138060.18-138060.91" - wire $reduce_or$libresoc.v:138060$7068_Y - attribute \src "libresoc.v:138045.18-138045.120" - wire width 20 $sshl$libresoc.v:138045$7052_Y + attribute \src "libresoc.v:147842.18-147842.113" + wire width 65 $add$libresoc.v:147842$7377_Y + attribute \src "libresoc.v:147836.18-147836.108" + wire width 5 $and$libresoc.v:147836$7370_Y + attribute \src "libresoc.v:147844.18-147844.118" + wire width 8 $and$libresoc.v:147844$7379_Y + attribute \src "libresoc.v:147846.18-147846.118" + wire width 8 $and$libresoc.v:147846$7381_Y + attribute \src "libresoc.v:147848.18-147848.118" + wire width 8 $and$libresoc.v:147848$7383_Y + attribute \src "libresoc.v:147850.18-147850.119" + wire width 8 $and$libresoc.v:147850$7385_Y + attribute \src "libresoc.v:147852.18-147852.119" + wire width 8 $and$libresoc.v:147852$7387_Y + attribute \src "libresoc.v:147854.18-147854.119" + wire width 8 $and$libresoc.v:147854$7389_Y + attribute \src "libresoc.v:147860.18-147860.106" + wire $and$libresoc.v:147860$7396_Y + attribute \src "libresoc.v:147865.18-147865.106" + wire $and$libresoc.v:147865$7401_Y + attribute \src "libresoc.v:147835.18-147835.100" + wire $eq$libresoc.v:147835$7369_Y + attribute \src "libresoc.v:147843.18-147843.119" + wire $eq$libresoc.v:147843$7378_Y + attribute \src "libresoc.v:147857.18-147857.121" + wire $eq$libresoc.v:147857$7393_Y + attribute \src "libresoc.v:147858.18-147858.121" + wire $eq$libresoc.v:147858$7394_Y + attribute \src "libresoc.v:147859.18-147859.111" + wire $eq$libresoc.v:147859$7395_Y + attribute \src "libresoc.v:147863.18-147863.121" + wire $eq$libresoc.v:147863$7399_Y + attribute \src "libresoc.v:147864.18-147864.114" + wire $eq$libresoc.v:147864$7400_Y + attribute \src "libresoc.v:147829.18-147829.95" + wire width 64 $extend$libresoc.v:147829$7361_Y + attribute \src "libresoc.v:147830.18-147830.95" + wire width 64 $extend$libresoc.v:147830$7363_Y + attribute \src "libresoc.v:147841.18-147841.100" + wire width 64 $extend$libresoc.v:147841$7375_Y + attribute \src "libresoc.v:147856.18-147856.109" + wire width 65 $extend$libresoc.v:147856$7391_Y + attribute \src "libresoc.v:147832.18-147832.121" + wire $gt$libresoc.v:147832$7366_Y + attribute \src "libresoc.v:147834.18-147834.99" + wire $gt$libresoc.v:147834$7368_Y + attribute \src "libresoc.v:147831.18-147831.121" + wire $lt$libresoc.v:147831$7365_Y + attribute \src "libresoc.v:147833.18-147833.99" + wire $lt$libresoc.v:147833$7367_Y + attribute \src "libresoc.v:147861.18-147861.112" + wire $not$libresoc.v:147861$7397_Y + attribute \src "libresoc.v:147862.18-147862.112" + wire $not$libresoc.v:147862$7398_Y + attribute \src "libresoc.v:147839.18-147839.106" + wire $or$libresoc.v:147839$7373_Y + attribute \src "libresoc.v:147829.18-147829.95" + wire width 64 $pos$libresoc.v:147829$7362_Y + attribute \src "libresoc.v:147830.18-147830.95" + wire width 64 $pos$libresoc.v:147830$7364_Y + attribute \src "libresoc.v:147841.18-147841.100" + wire width 64 $pos$libresoc.v:147841$7376_Y + attribute \src "libresoc.v:147856.18-147856.109" + wire width 65 $pos$libresoc.v:147856$7392_Y + attribute \src "libresoc.v:147837.18-147837.100" + wire $reduce_or$libresoc.v:147837$7371_Y + attribute \src "libresoc.v:147838.18-147838.113" + wire $reduce_or$libresoc.v:147838$7372_Y + attribute \src "libresoc.v:147845.18-147845.91" + wire $reduce_or$libresoc.v:147845$7380_Y + attribute \src "libresoc.v:147847.18-147847.91" + wire $reduce_or$libresoc.v:147847$7382_Y + attribute \src "libresoc.v:147849.18-147849.91" + wire $reduce_or$libresoc.v:147849$7384_Y + attribute \src "libresoc.v:147851.18-147851.91" + wire $reduce_or$libresoc.v:147851$7386_Y + attribute \src "libresoc.v:147853.18-147853.91" + wire $reduce_or$libresoc.v:147853$7388_Y + attribute \src "libresoc.v:147855.18-147855.91" + wire $reduce_or$libresoc.v:147855$7390_Y + attribute \src "libresoc.v:147840.18-147840.120" + wire width 20 $sshl$libresoc.v:147840$7374_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" @@ -290174,7 +308987,7 @@ module \main$38 wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:137665.7-137665.15" + attribute \src "libresoc.v:147454.7-147454.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s @@ -290184,9 +308997,9 @@ module \main$38 wire width 64 output 32 \msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 34 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 14 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 30 \nia @@ -290211,35 +309024,39 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \trap_op__cia$6 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 16 \trap_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 16 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -290318,6 +309135,7 @@ module \main$38 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -290394,6 +309212,7 @@ module \main$38 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 15 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -290433,7 +309252,7 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:138047$7055 + cell $add $add$libresoc.v:147842$7377 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -290441,10 +309260,10 @@ module \main$38 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:138047$7055_Y + connect \Y $add$libresoc.v:147842$7377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:138041$7048 + cell $and $and$libresoc.v:147836$7370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -290452,10 +309271,10 @@ module \main$38 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:138041$7048_Y + connect \Y $and$libresoc.v:147836$7370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:138049$7057 + cell $and $and$libresoc.v:147844$7379 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -290463,10 +309282,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:138049$7057_Y + connect \Y $and$libresoc.v:147844$7379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:138051$7059 + cell $and $and$libresoc.v:147846$7381 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -290474,10 +309293,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:138051$7059_Y + connect \Y $and$libresoc.v:147846$7381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:138053$7061 + cell $and $and$libresoc.v:147848$7383 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -290485,10 +309304,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:138053$7061_Y + connect \Y $and$libresoc.v:147848$7383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:138055$7063 + cell $and $and$libresoc.v:147850$7385 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -290496,10 +309315,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:138055$7063_Y + connect \Y $and$libresoc.v:147850$7385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:138057$7065 + cell $and $and$libresoc.v:147852$7387 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -290507,10 +309326,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 - connect \Y $and$libresoc.v:138057$7065_Y + connect \Y $and$libresoc.v:147852$7387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:138059$7067 + cell $and $and$libresoc.v:147854$7389 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -290518,10 +309337,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:138059$7067_Y + connect \Y $and$libresoc.v:147854$7389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:138065$7074 + cell $and $and$libresoc.v:147860$7396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -290529,10 +309348,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:138065$7074_Y + connect \Y $and$libresoc.v:147860$7396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:138070$7079 + cell $and $and$libresoc.v:147865$7401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -290540,10 +309359,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:138070$7079_Y + connect \Y $and$libresoc.v:147865$7401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:138040$7047 + cell $eq $eq$libresoc.v:147835$7369 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -290551,10 +309370,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:138040$7047_Y + connect \Y $eq$libresoc.v:147835$7369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:138048$7056 + cell $eq $eq$libresoc.v:147843$7378 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -290562,10 +309381,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:138048$7056_Y + connect \Y $eq$libresoc.v:147843$7378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:138062$7071 + cell $eq $eq$libresoc.v:147857$7393 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -290573,10 +309392,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:138062$7071_Y + connect \Y $eq$libresoc.v:147857$7393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:138063$7072 + cell $eq $eq$libresoc.v:147858$7394 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -290584,10 +309403,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:138063$7072_Y + connect \Y $eq$libresoc.v:147858$7394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:138064$7073 + cell $eq $eq$libresoc.v:147859$7395 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -290595,10 +309414,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:138064$7073_Y + connect \Y $eq$libresoc.v:147859$7395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:138068$7077 + cell $eq $eq$libresoc.v:147863$7399 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -290606,10 +309425,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:138068$7077_Y + connect \Y $eq$libresoc.v:147863$7399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:138069$7078 + cell $eq $eq$libresoc.v:147864$7400 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -290617,42 +309436,42 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:138069$7078_Y + connect \Y $eq$libresoc.v:147864$7400_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:138034$7039 + cell $pos $extend$libresoc.v:147829$7361 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:138034$7039_Y + connect \Y $extend$libresoc.v:147829$7361_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:138035$7041 + cell $pos $extend$libresoc.v:147830$7363 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:138035$7041_Y + connect \Y $extend$libresoc.v:147830$7363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:138046$7053 + cell $pos $extend$libresoc.v:147841$7375 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 - connect \Y $extend$libresoc.v:138046$7053_Y + connect \Y $extend$libresoc.v:147841$7375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:138061$7069 + cell $pos $extend$libresoc.v:147856$7391 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:138061$7069_Y + connect \Y $extend$libresoc.v:147856$7391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:138037$7044 + cell $gt $gt$libresoc.v:147832$7366 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -290660,10 +309479,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:138037$7044_Y + connect \Y $gt$libresoc.v:147832$7366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:138039$7046 + cell $gt $gt$libresoc.v:147834$7368 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -290671,10 +309490,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:138039$7046_Y + connect \Y $gt$libresoc.v:147834$7368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:138036$7043 + cell $lt $lt$libresoc.v:147831$7365 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -290682,10 +309501,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:138036$7043_Y + connect \Y $lt$libresoc.v:147831$7365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:138038$7045 + cell $lt $lt$libresoc.v:147833$7367 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -290693,26 +309512,26 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:138038$7045_Y + connect \Y $lt$libresoc.v:147833$7367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:138066$7075 + cell $not $not$libresoc.v:147861$7397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:138066$7075_Y + connect \Y $not$libresoc.v:147861$7397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:138067$7076 + cell $not $not$libresoc.v:147862$7398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:138067$7076_Y + connect \Y $not$libresoc.v:147862$7398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:138044$7051 + cell $or $or$libresoc.v:147839$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -290720,106 +309539,106 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 - connect \Y $or$libresoc.v:138044$7051_Y + connect \Y $or$libresoc.v:147839$7373_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:138034$7040 + cell $pos $pos$libresoc.v:147829$7362 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:138034$7039_Y - connect \Y $pos$libresoc.v:138034$7040_Y + connect \A $extend$libresoc.v:147829$7361_Y + connect \Y $pos$libresoc.v:147829$7362_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:138035$7042 + cell $pos $pos$libresoc.v:147830$7364 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:138035$7041_Y - connect \Y $pos$libresoc.v:138035$7042_Y + connect \A $extend$libresoc.v:147830$7363_Y + connect \Y $pos$libresoc.v:147830$7364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:138046$7054 + cell $pos $pos$libresoc.v:147841$7376 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:138046$7053_Y - connect \Y $pos$libresoc.v:138046$7054_Y + connect \A $extend$libresoc.v:147841$7375_Y + connect \Y $pos$libresoc.v:147841$7376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:138061$7070 + cell $pos $pos$libresoc.v:147856$7392 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:138061$7069_Y - connect \Y $pos$libresoc.v:138061$7070_Y + connect \A $extend$libresoc.v:147856$7391_Y + connect \Y $pos$libresoc.v:147856$7392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:138042$7049 + cell $reduce_or $reduce_or$libresoc.v:147837$7371 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $reduce_or$libresoc.v:138042$7049_Y + connect \Y $reduce_or$libresoc.v:147837$7371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:138043$7050 + cell $reduce_or $reduce_or$libresoc.v:147838$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:138043$7050_Y + connect \Y $reduce_or$libresoc.v:147838$7372_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138050$7058 + cell $reduce_or $reduce_or$libresoc.v:147845$7380 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 - connect \Y $reduce_or$libresoc.v:138050$7058_Y + connect \Y $reduce_or$libresoc.v:147845$7380_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138052$7060 + cell $reduce_or $reduce_or$libresoc.v:147847$7382 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 - connect \Y $reduce_or$libresoc.v:138052$7060_Y + connect \Y $reduce_or$libresoc.v:147847$7382_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138054$7062 + cell $reduce_or $reduce_or$libresoc.v:147849$7384 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 - connect \Y $reduce_or$libresoc.v:138054$7062_Y + connect \Y $reduce_or$libresoc.v:147849$7384_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138056$7064 + cell $reduce_or $reduce_or$libresoc.v:147851$7386 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 - connect \Y $reduce_or$libresoc.v:138056$7064_Y + connect \Y $reduce_or$libresoc.v:147851$7386_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138058$7066 + cell $reduce_or $reduce_or$libresoc.v:147853$7388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $reduce_or$libresoc.v:138058$7066_Y + connect \Y $reduce_or$libresoc.v:147853$7388_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138060$7068 + cell $reduce_or $reduce_or$libresoc.v:147855$7390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $reduce_or$libresoc.v:138060$7068_Y + connect \Y $reduce_or$libresoc.v:147855$7390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:138045$7052 + cell $sshl $sshl$libresoc.v:147840$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -290827,23 +309646,23 @@ module \main$38 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:138045$7052_Y + connect \Y $sshl$libresoc.v:147840$7374_Y end - attribute \src "libresoc.v:137665.7-137665.20" - process $proc$libresoc.v:137665$7140 + attribute \src "libresoc.v:147454.7-147454.20" + process $proc$libresoc.v:147454$7462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:138071.3-138082.6" - process $proc$libresoc.v:138071$7080 + attribute \src "libresoc.v:147866.3-147877.6" + process $proc$libresoc.v:147866$7402 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:138072.5-138072.29" + attribute \src "libresoc.v:147867.5-147867.29" switch \initial - attribute \src "libresoc.v:138072.9-138072.17" + attribute \src "libresoc.v:147867.9-147867.17" case 1'1 case end @@ -290861,14 +309680,14 @@ module \main$38 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:138083.3-138114.6" - process $proc$libresoc.v:138083$7081 + attribute \src "libresoc.v:147878.3-147909.6" + process $proc$libresoc.v:147878$7403 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:138084.5-138084.29" + attribute \src "libresoc.v:147879.5-147879.29" switch \initial - attribute \src "libresoc.v:138084.9-138084.17" + attribute \src "libresoc.v:147879.9-147879.17" case 1'1 case end @@ -290907,14 +309726,14 @@ module \main$38 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:138115.3-138146.6" - process $proc$libresoc.v:138115$7082 + attribute \src "libresoc.v:147910.3-147941.6" + process $proc$libresoc.v:147910$7404 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:138116.5-138116.29" + attribute \src "libresoc.v:147911.5-147911.29" switch \initial - attribute \src "libresoc.v:138116.9-138116.17" + attribute \src "libresoc.v:147911.9-147911.17" case 1'1 case end @@ -290953,14 +309772,14 @@ module \main$38 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:138147.3-138178.6" - process $proc$libresoc.v:138147$7083 + attribute \src "libresoc.v:147942.3-147973.6" + process $proc$libresoc.v:147942$7405 assign { } { } assign { } { } - assign $0\fast1$11[63:0]$7084 $1\fast1$11[63:0]$7085 - attribute \src "libresoc.v:138148.5-138148.29" + assign $0\fast1$11[63:0]$7406 $1\fast1$11[63:0]$7407 + attribute \src "libresoc.v:147943.5-147943.29" switch \initial - attribute \src "libresoc.v:138148.9-138148.17" + attribute \src "libresoc.v:147943.9-147943.17" case 1'1 case end @@ -290969,43 +309788,43 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast1$11[63:0]$7085 $2\fast1$11[63:0]$7086 + assign $1\fast1$11[63:0]$7407 $2\fast1$11[63:0]$7408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1$11[63:0]$7086 \trap_op__cia + assign $2\fast1$11[63:0]$7408 \trap_op__cia case - assign $2\fast1$11[63:0]$7086 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$11[63:0]$7408 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast1$11[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast1$11[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast1$11[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign $1\fast1$11[63:0]$7085 \$39 [63:0] + assign $1\fast1$11[63:0]$7407 \$39 [63:0] case - assign $1\fast1$11[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$11 $0\fast1$11[63:0]$7084 + update \fast1$11 $0\fast1$11[63:0]$7406 end - attribute \src "libresoc.v:138179.3-138210.6" - process $proc$libresoc.v:138179$7087 + attribute \src "libresoc.v:147974.3-148005.6" + process $proc$libresoc.v:147974$7409 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:138180.5-138180.29" + attribute \src "libresoc.v:147975.5-147975.29" switch \initial - attribute \src "libresoc.v:138180.9-138180.17" + attribute \src "libresoc.v:147975.9-147975.17" case 1'1 case end @@ -291043,14 +309862,14 @@ module \main$38 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:138211.3-138293.6" - process $proc$libresoc.v:138211$7088 + attribute \src "libresoc.v:148006.3-148088.6" + process $proc$libresoc.v:148006$7410 assign { } { } assign { } { } - assign $0\fast2$12[63:0]$7089 $1\fast2$12[63:0]$7090 - attribute \src "libresoc.v:138212.5-138212.29" + assign $0\fast2$12[63:0]$7411 $1\fast2$12[63:0]$7412 + attribute \src "libresoc.v:148007.5-148007.29" switch \initial - attribute \src "libresoc.v:138212.9-138212.17" + attribute \src "libresoc.v:148007.9-148007.17" case 1'1 case end @@ -291059,59 +309878,59 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast2$12[63:0]$7090 $2\fast2$12[63:0]$7091 + assign $1\fast2$12[63:0]$7412 $2\fast2$12[63:0]$7413 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { $2\fast2$12[63:0]$7091 [29] $2\fast2$12[63:0]$7091 [27] $2\fast2$12[63:0]$7091 [21] } 3'000 - assign $2\fast2$12[63:0]$7091 [15:0] \trap_op__msr [15:0] - assign $2\fast2$12[63:0]$7091 [26:22] \trap_op__msr [26:22] - assign $2\fast2$12[63:0]$7091 [63:31] \trap_op__msr [63:31] - assign $2\fast2$12[63:0]$7091 [17] $3\fast2$12[17:17]$7092 - assign { } { } - assign $2\fast2$12[63:0]$7091 [20] $5\fast2$12[20:20]$7094 - assign $2\fast2$12[63:0]$7091 [16] $6\fast2$12[16:16]$7095 - assign $2\fast2$12[63:0]$7091 [18] $7\fast2$12[19:18]$7096 [0] - assign $2\fast2$12[63:0]$7091 [28] $8\fast2$12[28:28]$7097 - assign $2\fast2$12[63:0]$7091 [30] $9\fast2$12[30:30]$7098 - assign $2\fast2$12[63:0]$7091 [19] $10\fast2$12[19:19]$7099 + assign { $2\fast2$12[63:0]$7413 [29] $2\fast2$12[63:0]$7413 [27] $2\fast2$12[63:0]$7413 [21] } 3'000 + assign $2\fast2$12[63:0]$7413 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7413 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7413 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7413 [17] $3\fast2$12[17:17]$7414 + assign { } { } + assign $2\fast2$12[63:0]$7413 [20] $5\fast2$12[20:20]$7416 + assign $2\fast2$12[63:0]$7413 [16] $6\fast2$12[16:16]$7417 + assign $2\fast2$12[63:0]$7413 [18] $7\fast2$12[19:18]$7418 [0] + assign $2\fast2$12[63:0]$7413 [28] $8\fast2$12[28:28]$7419 + assign $2\fast2$12[63:0]$7413 [30] $9\fast2$12[30:30]$7420 + assign $2\fast2$12[63:0]$7413 [19] $10\fast2$12[19:19]$7421 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fast2$12[17:17]$7092 1'1 + assign $3\fast2$12[17:17]$7414 1'1 case - assign $3\fast2$12[17:17]$7092 1'0 + assign $3\fast2$12[17:17]$7414 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fast2$12[18:18]$7093 1'1 + assign $4\fast2$12[18:18]$7415 1'1 case - assign $4\fast2$12[18:18]$7093 1'0 + assign $4\fast2$12[18:18]$7415 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fast2$12[20:20]$7094 1'1 + assign $5\fast2$12[20:20]$7416 1'1 case - assign $5\fast2$12[20:20]$7094 1'0 + assign $5\fast2$12[20:20]$7416 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fast2$12[16:16]$7095 1'1 + assign $6\fast2$12[16:16]$7417 1'1 case - assign $6\fast2$12[16:16]$7095 1'0 + assign $6\fast2$12[16:16]$7417 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$56 @@ -291120,57 +309939,57 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $9\fast2$12[30:30]$7098 \trapexc_$signal - assign $8\fast2$12[28:28]$7097 \trapexc_$signal$60 - assign $7\fast2$12[19:18]$7096 [1] \trapexc_$signal$61 - assign $7\fast2$12[19:18]$7096 [0] \trapexc_$signal$62 + assign $9\fast2$12[30:30]$7420 \trapexc_$signal + assign $8\fast2$12[28:28]$7419 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7418 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7418 [0] \trapexc_$signal$62 case - assign $7\fast2$12[19:18]$7096 { 1'0 $4\fast2$12[18:18]$7093 } - assign $8\fast2$12[28:28]$7097 1'0 - assign $9\fast2$12[30:30]$7098 1'0 + assign $7\fast2$12[19:18]$7418 { 1'0 $4\fast2$12[18:18]$7415 } + assign $8\fast2$12[28:28]$7419 1'0 + assign $9\fast2$12[30:30]$7420 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\fast2$12[19:19]$7099 1'1 + assign $10\fast2$12[19:19]$7421 1'1 case - assign $10\fast2$12[19:19]$7099 $7\fast2$12[19:18]$7096 [1] + assign $10\fast2$12[19:19]$7421 $7\fast2$12[19:18]$7418 [1] end case - assign $2\fast2$12[63:0]$7091 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast2$12[63:0]$7413 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast2$12[63:0]$7090 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast2$12[63:0]$7090 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast2$12[63:0]$7090 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign { $1\fast2$12[63:0]$7090 [30:27] $1\fast2$12[63:0]$7090 [21:16] } 10'0000000000 - assign $1\fast2$12[63:0]$7090 [15:0] \trap_op__msr [15:0] - assign $1\fast2$12[63:0]$7090 [26:22] \trap_op__msr [26:22] - assign $1\fast2$12[63:0]$7090 [63:31] \trap_op__msr [63:31] + assign { $1\fast2$12[63:0]$7412 [30:27] $1\fast2$12[63:0]$7412 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7412 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7412 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7412 [63:31] \trap_op__msr [63:31] case - assign $1\fast2$12[63:0]$7090 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$12 $0\fast2$12[63:0]$7089 + update \fast2$12 $0\fast2$12[63:0]$7411 end - attribute \src "libresoc.v:138294.3-138325.6" - process $proc$libresoc.v:138294$7100 + attribute \src "libresoc.v:148089.3-148120.6" + process $proc$libresoc.v:148089$7422 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:138295.5-138295.29" + attribute \src "libresoc.v:148090.5-148090.29" switch \initial - attribute \src "libresoc.v:138295.9-138295.17" + attribute \src "libresoc.v:148090.9-148090.17" case 1'1 case end @@ -291208,8 +310027,8 @@ module \main$38 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:138326.3-138353.6" - process $proc$libresoc.v:138326$7101 + attribute \src "libresoc.v:148121.3-148148.6" + process $proc$libresoc.v:148121$7423 assign { } { } assign { } { } assign { } { } @@ -291226,17 +310045,17 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $0\trapexc_$signal[0:0]$7102 $1\trapexc_$signal[0:0]$7110 - assign $0\trapexc_$signal$60[0:0]$7103 $1\trapexc_$signal$60[0:0]$7111 - assign $0\trapexc_$signal$61[0:0]$7104 $1\trapexc_$signal$61[0:0]$7112 - assign $0\trapexc_$signal$62[0:0]$7105 $1\trapexc_$signal$62[0:0]$7113 - assign $0\trapexc_$signal$67[0:0]$7106 $1\trapexc_$signal$67[0:0]$7114 - assign $0\trapexc_$signal$68[0:0]$7107 $1\trapexc_$signal$68[0:0]$7115 - assign $0\trapexc_$signal$69[0:0]$7108 $1\trapexc_$signal$69[0:0]$7116 - assign $0\trapexc_$signal$70[0:0]$7109 $1\trapexc_$signal$70[0:0]$7117 - attribute \src "libresoc.v:138327.5-138327.29" + assign $0\trapexc_$signal[0:0]$7424 $1\trapexc_$signal[0:0]$7432 + assign $0\trapexc_$signal$60[0:0]$7425 $1\trapexc_$signal$60[0:0]$7433 + assign $0\trapexc_$signal$61[0:0]$7426 $1\trapexc_$signal$61[0:0]$7434 + assign $0\trapexc_$signal$62[0:0]$7427 $1\trapexc_$signal$62[0:0]$7435 + assign $0\trapexc_$signal$67[0:0]$7428 $1\trapexc_$signal$67[0:0]$7436 + assign $0\trapexc_$signal$68[0:0]$7429 $1\trapexc_$signal$68[0:0]$7437 + assign $0\trapexc_$signal$69[0:0]$7430 $1\trapexc_$signal$69[0:0]$7438 + assign $0\trapexc_$signal$70[0:0]$7431 $1\trapexc_$signal$70[0:0]$7439 + attribute \src "libresoc.v:148122.5-148122.29" switch \initial - attribute \src "libresoc.v:138327.9-138327.17" + attribute \src "libresoc.v:148122.9-148122.17" case 1'1 case end @@ -291252,14 +310071,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $1\trapexc_$signal[0:0]$7110 $2\trapexc_$signal[0:0]$7118 - assign $1\trapexc_$signal$60[0:0]$7111 $2\trapexc_$signal$60[0:0]$7119 - assign $1\trapexc_$signal$61[0:0]$7112 $2\trapexc_$signal$61[0:0]$7120 - assign $1\trapexc_$signal$62[0:0]$7113 $2\trapexc_$signal$62[0:0]$7121 - assign $1\trapexc_$signal$67[0:0]$7114 $2\trapexc_$signal$67[0:0]$7122 - assign $1\trapexc_$signal$68[0:0]$7115 $2\trapexc_$signal$68[0:0]$7123 - assign $1\trapexc_$signal$69[0:0]$7116 $2\trapexc_$signal$69[0:0]$7124 - assign $1\trapexc_$signal$70[0:0]$7117 $2\trapexc_$signal$70[0:0]$7125 + assign $1\trapexc_$signal[0:0]$7432 $2\trapexc_$signal[0:0]$7440 + assign $1\trapexc_$signal$60[0:0]$7433 $2\trapexc_$signal$60[0:0]$7441 + assign $1\trapexc_$signal$61[0:0]$7434 $2\trapexc_$signal$61[0:0]$7442 + assign $1\trapexc_$signal$62[0:0]$7435 $2\trapexc_$signal$62[0:0]$7443 + assign $1\trapexc_$signal$67[0:0]$7436 $2\trapexc_$signal$67[0:0]$7444 + assign $1\trapexc_$signal$68[0:0]$7437 $2\trapexc_$signal$68[0:0]$7445 + assign $1\trapexc_$signal$69[0:0]$7438 $2\trapexc_$signal$69[0:0]$7446 + assign $1\trapexc_$signal$70[0:0]$7439 $2\trapexc_$signal$70[0:0]$7447 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" @@ -291272,14 +310091,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $2\trapexc_$signal[0:0]$7118 $3\trapexc_$signal[0:0]$7126 - assign $2\trapexc_$signal$60[0:0]$7119 $3\trapexc_$signal$60[0:0]$7127 - assign $2\trapexc_$signal$61[0:0]$7120 $3\trapexc_$signal$61[0:0]$7128 - assign $2\trapexc_$signal$62[0:0]$7121 $3\trapexc_$signal$62[0:0]$7129 - assign $2\trapexc_$signal$67[0:0]$7122 $3\trapexc_$signal$67[0:0]$7130 - assign $2\trapexc_$signal$68[0:0]$7123 $3\trapexc_$signal$68[0:0]$7131 - assign $2\trapexc_$signal$69[0:0]$7124 $3\trapexc_$signal$69[0:0]$7132 - assign $2\trapexc_$signal$70[0:0]$7125 $3\trapexc_$signal$70[0:0]$7133 + assign $2\trapexc_$signal[0:0]$7440 $3\trapexc_$signal[0:0]$7448 + assign $2\trapexc_$signal$60[0:0]$7441 $3\trapexc_$signal$60[0:0]$7449 + assign $2\trapexc_$signal$61[0:0]$7442 $3\trapexc_$signal$61[0:0]$7450 + assign $2\trapexc_$signal$62[0:0]$7443 $3\trapexc_$signal$62[0:0]$7451 + assign $2\trapexc_$signal$67[0:0]$7444 $3\trapexc_$signal$67[0:0]$7452 + assign $2\trapexc_$signal$68[0:0]$7445 $3\trapexc_$signal$68[0:0]$7453 + assign $2\trapexc_$signal$69[0:0]$7446 $3\trapexc_$signal$69[0:0]$7454 + assign $2\trapexc_$signal$70[0:0]$7447 $3\trapexc_$signal$70[0:0]$7455 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$71 attribute \src "libresoc.v:0.0-0.0" @@ -291292,54 +310111,54 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign { $3\trapexc_$signal$70[0:0]$7133 $3\trapexc_$signal$62[0:0]$7129 $3\trapexc_$signal$60[0:0]$7127 $3\trapexc_$signal$61[0:0]$7128 $3\trapexc_$signal[0:0]$7126 $3\trapexc_$signal$69[0:0]$7132 $3\trapexc_$signal$68[0:0]$7131 $3\trapexc_$signal$67[0:0]$7130 } \trap_op__ldst_exc + assign { $3\trapexc_$signal$70[0:0]$7455 $3\trapexc_$signal$62[0:0]$7451 $3\trapexc_$signal$60[0:0]$7449 $3\trapexc_$signal$61[0:0]$7450 $3\trapexc_$signal[0:0]$7448 $3\trapexc_$signal$69[0:0]$7454 $3\trapexc_$signal$68[0:0]$7453 $3\trapexc_$signal$67[0:0]$7452 } \trap_op__ldst_exc case - assign $3\trapexc_$signal[0:0]$7126 1'0 - assign $3\trapexc_$signal$60[0:0]$7127 1'0 - assign $3\trapexc_$signal$61[0:0]$7128 1'0 - assign $3\trapexc_$signal$62[0:0]$7129 1'0 - assign $3\trapexc_$signal$67[0:0]$7130 1'0 - assign $3\trapexc_$signal$68[0:0]$7131 1'0 - assign $3\trapexc_$signal$69[0:0]$7132 1'0 - assign $3\trapexc_$signal$70[0:0]$7133 1'0 + assign $3\trapexc_$signal[0:0]$7448 1'0 + assign $3\trapexc_$signal$60[0:0]$7449 1'0 + assign $3\trapexc_$signal$61[0:0]$7450 1'0 + assign $3\trapexc_$signal$62[0:0]$7451 1'0 + assign $3\trapexc_$signal$67[0:0]$7452 1'0 + assign $3\trapexc_$signal$68[0:0]$7453 1'0 + assign $3\trapexc_$signal$69[0:0]$7454 1'0 + assign $3\trapexc_$signal$70[0:0]$7455 1'0 end case - assign $2\trapexc_$signal[0:0]$7118 1'0 - assign $2\trapexc_$signal$60[0:0]$7119 1'0 - assign $2\trapexc_$signal$61[0:0]$7120 1'0 - assign $2\trapexc_$signal$62[0:0]$7121 1'0 - assign $2\trapexc_$signal$67[0:0]$7122 1'0 - assign $2\trapexc_$signal$68[0:0]$7123 1'0 - assign $2\trapexc_$signal$69[0:0]$7124 1'0 - assign $2\trapexc_$signal$70[0:0]$7125 1'0 - end - case - assign $1\trapexc_$signal[0:0]$7110 1'0 - assign $1\trapexc_$signal$60[0:0]$7111 1'0 - assign $1\trapexc_$signal$61[0:0]$7112 1'0 - assign $1\trapexc_$signal$62[0:0]$7113 1'0 - assign $1\trapexc_$signal$67[0:0]$7114 1'0 - assign $1\trapexc_$signal$68[0:0]$7115 1'0 - assign $1\trapexc_$signal$69[0:0]$7116 1'0 - assign $1\trapexc_$signal$70[0:0]$7117 1'0 - end - sync always - update \trapexc_$signal $0\trapexc_$signal[0:0]$7102 - update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7103 - update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7104 - update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7105 - update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7106 - update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7107 - update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7108 - update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7109 - end - attribute \src "libresoc.v:138354.3-138365.6" - process $proc$libresoc.v:138354$7134 + assign $2\trapexc_$signal[0:0]$7440 1'0 + assign $2\trapexc_$signal$60[0:0]$7441 1'0 + assign $2\trapexc_$signal$61[0:0]$7442 1'0 + assign $2\trapexc_$signal$62[0:0]$7443 1'0 + assign $2\trapexc_$signal$67[0:0]$7444 1'0 + assign $2\trapexc_$signal$68[0:0]$7445 1'0 + assign $2\trapexc_$signal$69[0:0]$7446 1'0 + assign $2\trapexc_$signal$70[0:0]$7447 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7432 1'0 + assign $1\trapexc_$signal$60[0:0]$7433 1'0 + assign $1\trapexc_$signal$61[0:0]$7434 1'0 + assign $1\trapexc_$signal$62[0:0]$7435 1'0 + assign $1\trapexc_$signal$67[0:0]$7436 1'0 + assign $1\trapexc_$signal$68[0:0]$7437 1'0 + assign $1\trapexc_$signal$69[0:0]$7438 1'0 + assign $1\trapexc_$signal$70[0:0]$7439 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7424 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7425 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7426 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7427 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7428 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7429 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7430 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7431 + end + attribute \src "libresoc.v:148149.3-148160.6" + process $proc$libresoc.v:148149$7456 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:138355.5-138355.29" + attribute \src "libresoc.v:148150.5-148150.29" switch \initial - attribute \src "libresoc.v:138355.9-138355.17" + attribute \src "libresoc.v:148150.9-148150.17" case 1'1 case end @@ -291357,17 +310176,17 @@ module \main$38 sync always update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:138366.3-138534.6" - process $proc$libresoc.v:138366$7135 + attribute \src "libresoc.v:148161.3-148329.6" + process $proc$libresoc.v:148161$7457 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:138367.5-138367.29" + attribute \src "libresoc.v:148162.5-148162.29" switch \initial - attribute \src "libresoc.v:138367.9-138367.17" + attribute \src "libresoc.v:148162.9-148162.17" case 1'1 case end @@ -291581,14 +310400,14 @@ module \main$38 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:138535.3-138553.6" - process $proc$libresoc.v:138535$7136 + attribute \src "libresoc.v:148330.3-148348.6" + process $proc$libresoc.v:148330$7458 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:138536.5-138536.29" + attribute \src "libresoc.v:148331.5-148331.29" switch \initial - attribute \src "libresoc.v:138536.9-138536.17" + attribute \src "libresoc.v:148331.9-148331.17" case 1'1 case end @@ -291610,14 +310429,14 @@ module \main$38 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:138554.3-138572.6" - process $proc$libresoc.v:138554$7137 + attribute \src "libresoc.v:148349.3-148367.6" + process $proc$libresoc.v:148349$7459 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:138555.5-138555.29" + attribute \src "libresoc.v:148350.5-148350.29" switch \initial - attribute \src "libresoc.v:138555.9-138555.17" + attribute \src "libresoc.v:148350.9-148350.17" case 1'1 case end @@ -291639,13 +310458,13 @@ module \main$38 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:138573.3-138584.6" - process $proc$libresoc.v:138573$7138 + attribute \src "libresoc.v:148368.3-148379.6" + process $proc$libresoc.v:148368$7460 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:138574.5-138574.29" + attribute \src "libresoc.v:148369.5-148369.29" switch \initial - attribute \src "libresoc.v:138574.9-138574.17" + attribute \src "libresoc.v:148369.9-148369.17" case 1'1 case end @@ -291663,13 +310482,13 @@ module \main$38 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:138585.3-138596.6" - process $proc$libresoc.v:138585$7139 + attribute \src "libresoc.v:148380.3-148391.6" + process $proc$libresoc.v:148380$7461 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:138586.5-138586.29" + attribute \src "libresoc.v:148381.5-148381.29" switch \initial - attribute \src "libresoc.v:138586.9-138586.17" + attribute \src "libresoc.v:148381.9-148381.17" case 1'1 case end @@ -291687,43 +310506,43 @@ module \main$38 sync always update \b $0\b[63:0] end - connect \$13 $pos$libresoc.v:138034$7040_Y - connect \$15 $pos$libresoc.v:138035$7042_Y - connect \$17 $lt$libresoc.v:138036$7043_Y - connect \$19 $gt$libresoc.v:138037$7044_Y - connect \$21 $lt$libresoc.v:138038$7045_Y - connect \$23 $gt$libresoc.v:138039$7046_Y - connect \$25 $eq$libresoc.v:138040$7047_Y - connect \$28 $and$libresoc.v:138041$7048_Y - connect \$27 $reduce_or$libresoc.v:138042$7049_Y - connect \$31 $reduce_or$libresoc.v:138043$7050_Y - connect \$33 $or$libresoc.v:138044$7051_Y - connect \$36 $sshl$libresoc.v:138045$7052_Y - connect \$35 $pos$libresoc.v:138046$7054_Y - connect \$40 $add$libresoc.v:138047$7055_Y - connect \$42 $eq$libresoc.v:138048$7056_Y - connect \$45 $and$libresoc.v:138049$7057_Y - connect \$44 $reduce_or$libresoc.v:138050$7058_Y - connect \$49 $and$libresoc.v:138051$7059_Y - connect \$48 $reduce_or$libresoc.v:138052$7060_Y - connect \$53 $and$libresoc.v:138053$7061_Y - connect \$52 $reduce_or$libresoc.v:138054$7062_Y - connect \$57 $and$libresoc.v:138055$7063_Y - connect \$56 $reduce_or$libresoc.v:138056$7064_Y - connect \$64 $and$libresoc.v:138057$7065_Y - connect \$63 $reduce_or$libresoc.v:138058$7066_Y - connect \$72 $and$libresoc.v:138059$7067_Y - connect \$71 $reduce_or$libresoc.v:138060$7068_Y - connect \$75 $pos$libresoc.v:138061$7070_Y - connect \$77 $eq$libresoc.v:138062$7071_Y - connect \$79 $eq$libresoc.v:138063$7072_Y - connect \$81 $eq$libresoc.v:138064$7073_Y - connect \$83 $and$libresoc.v:138065$7074_Y - connect \$85 $not$libresoc.v:138066$7075_Y - connect \$87 $not$libresoc.v:138067$7076_Y - connect \$89 $eq$libresoc.v:138068$7077_Y - connect \$91 $eq$libresoc.v:138069$7078_Y - connect \$93 $and$libresoc.v:138070$7079_Y + connect \$13 $pos$libresoc.v:147829$7362_Y + connect \$15 $pos$libresoc.v:147830$7364_Y + connect \$17 $lt$libresoc.v:147831$7365_Y + connect \$19 $gt$libresoc.v:147832$7366_Y + connect \$21 $lt$libresoc.v:147833$7367_Y + connect \$23 $gt$libresoc.v:147834$7368_Y + connect \$25 $eq$libresoc.v:147835$7369_Y + connect \$28 $and$libresoc.v:147836$7370_Y + connect \$27 $reduce_or$libresoc.v:147837$7371_Y + connect \$31 $reduce_or$libresoc.v:147838$7372_Y + connect \$33 $or$libresoc.v:147839$7373_Y + connect \$36 $sshl$libresoc.v:147840$7374_Y + connect \$35 $pos$libresoc.v:147841$7376_Y + connect \$40 $add$libresoc.v:147842$7377_Y + connect \$42 $eq$libresoc.v:147843$7378_Y + connect \$45 $and$libresoc.v:147844$7379_Y + connect \$44 $reduce_or$libresoc.v:147845$7380_Y + connect \$49 $and$libresoc.v:147846$7381_Y + connect \$48 $reduce_or$libresoc.v:147847$7382_Y + connect \$53 $and$libresoc.v:147848$7383_Y + connect \$52 $reduce_or$libresoc.v:147849$7384_Y + connect \$57 $and$libresoc.v:147850$7385_Y + connect \$56 $reduce_or$libresoc.v:147851$7386_Y + connect \$64 $and$libresoc.v:147852$7387_Y + connect \$63 $reduce_or$libresoc.v:147853$7388_Y + connect \$72 $and$libresoc.v:147854$7389_Y + connect \$71 $reduce_or$libresoc.v:147855$7390_Y + connect \$75 $pos$libresoc.v:147856$7392_Y + connect \$77 $eq$libresoc.v:147857$7393_Y + connect \$79 $eq$libresoc.v:147858$7394_Y + connect \$81 $eq$libresoc.v:147859$7395_Y + connect \$83 $and$libresoc.v:147860$7396_Y + connect \$85 $not$libresoc.v:147861$7397_Y + connect \$87 $not$libresoc.v:147862$7398_Y + connect \$89 $eq$libresoc.v:147863$7399_Y + connect \$91 $eq$libresoc.v:147864$7400_Y + connect \$93 $and$libresoc.v:147865$7401_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid @@ -291736,239 +310555,239 @@ module \main$38 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:138612.1-139355.10" +attribute \src "libresoc.v:148407.1-149156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 - attribute \src "libresoc.v:139322.3-139332.6" + attribute \src "libresoc.v:149123.3-149133.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:139267.3-139277.6" + attribute \src "libresoc.v:149068.3-149078.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:139245.3-139255.6" + attribute \src "libresoc.v:149046.3-149056.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:139234.3-139244.6" + attribute \src "libresoc.v:149035.3-149045.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:139223.3-139233.6" + attribute \src "libresoc.v:149024.3-149034.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:139333.3-139351.6" + attribute \src "libresoc.v:149134.3-149152.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:139311.3-139321.6" + attribute \src "libresoc.v:149112.3-149122.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:138613.7-138613.20" + attribute \src "libresoc.v:148408.7-148408.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139168.3-139222.6" + attribute \src "libresoc.v:148969.3-149023.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:139168.3-139222.6" + attribute \src "libresoc.v:148969.3-149023.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:139289.3-139299.6" + attribute \src "libresoc.v:149090.3-149100.6" wire $0\par0[0:0] - attribute \src "libresoc.v:139300.3-139310.6" + attribute \src "libresoc.v:149101.3-149111.6" wire $0\par1[0:0] - attribute \src "libresoc.v:139256.3-139266.6" + attribute \src "libresoc.v:149057.3-149067.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:139278.3-139288.6" + attribute \src "libresoc.v:149079.3-149089.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:139322.3-139332.6" + attribute \src "libresoc.v:149123.3-149133.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:139267.3-139277.6" + attribute \src "libresoc.v:149068.3-149078.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:139245.3-139255.6" + attribute \src "libresoc.v:149046.3-149056.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:139234.3-139244.6" + attribute \src "libresoc.v:149035.3-149045.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:139223.3-139233.6" + attribute \src "libresoc.v:149024.3-149034.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:139333.3-139351.6" + attribute \src "libresoc.v:149134.3-149152.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:139311.3-139321.6" + attribute \src "libresoc.v:149112.3-149122.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:139168.3-139222.6" + attribute \src "libresoc.v:148969.3-149023.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:139168.3-139222.6" + attribute \src "libresoc.v:148969.3-149023.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:139289.3-139299.6" + attribute \src "libresoc.v:149090.3-149100.6" wire $1\par0[0:0] - attribute \src "libresoc.v:139300.3-139310.6" + attribute \src "libresoc.v:149101.3-149111.6" wire $1\par1[0:0] - attribute \src "libresoc.v:139256.3-139266.6" + attribute \src "libresoc.v:149057.3-149067.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:139278.3-139288.6" + attribute \src "libresoc.v:149079.3-149089.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:139333.3-139351.6" + attribute \src "libresoc.v:149134.3-149152.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:139168.3-139222.6" + attribute \src "libresoc.v:148969.3-149023.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:139115.18-139115.103" - wire width 64 $and$libresoc.v:139115$7187_Y - attribute \src "libresoc.v:139074.18-139074.118" - wire $eq$libresoc.v:139074$7141_Y - attribute \src "libresoc.v:139075.19-139075.119" - wire $eq$libresoc.v:139075$7142_Y - attribute \src "libresoc.v:139076.19-139076.119" - wire $eq$libresoc.v:139076$7143_Y - attribute \src "libresoc.v:139077.19-139077.119" - wire $eq$libresoc.v:139077$7144_Y - attribute \src "libresoc.v:139078.19-139078.119" - wire $eq$libresoc.v:139078$7145_Y - attribute \src "libresoc.v:139079.19-139079.119" - wire $eq$libresoc.v:139079$7146_Y - attribute \src "libresoc.v:139080.19-139080.119" - wire $eq$libresoc.v:139080$7147_Y - attribute \src "libresoc.v:139081.19-139081.119" - wire $eq$libresoc.v:139081$7148_Y - attribute \src "libresoc.v:139082.19-139082.119" - wire $eq$libresoc.v:139082$7149_Y - attribute \src "libresoc.v:139083.19-139083.119" - wire $eq$libresoc.v:139083$7150_Y - attribute \src "libresoc.v:139084.19-139084.119" - wire $eq$libresoc.v:139084$7151_Y - attribute \src "libresoc.v:139085.19-139085.119" - wire $eq$libresoc.v:139085$7152_Y - attribute \src "libresoc.v:139086.19-139086.119" - wire $eq$libresoc.v:139086$7153_Y - attribute \src "libresoc.v:139087.19-139087.119" - wire $eq$libresoc.v:139087$7154_Y - attribute \src "libresoc.v:139088.19-139088.119" - wire $eq$libresoc.v:139088$7155_Y - attribute \src "libresoc.v:139089.19-139089.119" - wire $eq$libresoc.v:139089$7156_Y - attribute \src "libresoc.v:139090.19-139090.119" - wire $eq$libresoc.v:139090$7157_Y - attribute \src "libresoc.v:139091.19-139091.119" - wire $eq$libresoc.v:139091$7158_Y - attribute \src "libresoc.v:139092.19-139092.119" - wire $eq$libresoc.v:139092$7159_Y - attribute \src "libresoc.v:139093.19-139093.119" - wire $eq$libresoc.v:139093$7160_Y - attribute \src "libresoc.v:139094.19-139094.119" - wire $eq$libresoc.v:139094$7161_Y - attribute \src "libresoc.v:139095.19-139095.119" - wire $eq$libresoc.v:139095$7162_Y - attribute \src "libresoc.v:139096.19-139096.119" - wire $eq$libresoc.v:139096$7163_Y - attribute \src "libresoc.v:139097.19-139097.119" - wire $eq$libresoc.v:139097$7164_Y - attribute \src "libresoc.v:139098.19-139098.119" - wire $eq$libresoc.v:139098$7165_Y - attribute \src "libresoc.v:139099.19-139099.119" - wire $eq$libresoc.v:139099$7166_Y - attribute \src "libresoc.v:139100.19-139100.119" - wire $eq$libresoc.v:139100$7167_Y - attribute \src "libresoc.v:139101.19-139101.119" - wire $eq$libresoc.v:139101$7168_Y - attribute \src "libresoc.v:139102.19-139102.128" - wire $eq$libresoc.v:139102$7169_Y - attribute \src "libresoc.v:139118.18-139118.114" - wire $eq$libresoc.v:139118$7190_Y - attribute \src "libresoc.v:139119.18-139119.114" - wire $eq$libresoc.v:139119$7191_Y - attribute \src "libresoc.v:139120.18-139120.114" - wire $eq$libresoc.v:139120$7192_Y - attribute \src "libresoc.v:139121.18-139121.114" - wire $eq$libresoc.v:139121$7193_Y - attribute \src "libresoc.v:139122.18-139122.114" - wire $eq$libresoc.v:139122$7194_Y - attribute \src "libresoc.v:139123.18-139123.114" - wire $eq$libresoc.v:139123$7195_Y - attribute \src "libresoc.v:139124.18-139124.114" - wire $eq$libresoc.v:139124$7196_Y - attribute \src "libresoc.v:139125.18-139125.114" - wire $eq$libresoc.v:139125$7197_Y - attribute \src "libresoc.v:139126.18-139126.116" - wire $eq$libresoc.v:139126$7198_Y - attribute \src "libresoc.v:139127.18-139127.116" - wire $eq$libresoc.v:139127$7199_Y - attribute \src "libresoc.v:139128.18-139128.116" - wire $eq$libresoc.v:139128$7200_Y - attribute \src "libresoc.v:139129.18-139129.116" - wire $eq$libresoc.v:139129$7201_Y - attribute \src "libresoc.v:139130.18-139130.116" - wire $eq$libresoc.v:139130$7202_Y - attribute \src "libresoc.v:139131.18-139131.116" - wire $eq$libresoc.v:139131$7203_Y - attribute \src "libresoc.v:139132.18-139132.116" - wire $eq$libresoc.v:139132$7204_Y - attribute \src "libresoc.v:139133.18-139133.116" - wire $eq$libresoc.v:139133$7205_Y - attribute \src "libresoc.v:139134.18-139134.118" - wire $eq$libresoc.v:139134$7206_Y - attribute \src "libresoc.v:139135.18-139135.118" - wire $eq$libresoc.v:139135$7207_Y - attribute \src "libresoc.v:139136.18-139136.118" - wire $eq$libresoc.v:139136$7208_Y - attribute \src "libresoc.v:139137.18-139137.118" - wire $eq$libresoc.v:139137$7209_Y - attribute \src "libresoc.v:139138.18-139138.118" - wire $eq$libresoc.v:139138$7210_Y - attribute \src "libresoc.v:139139.18-139139.118" - wire $eq$libresoc.v:139139$7211_Y - attribute \src "libresoc.v:139140.18-139140.118" - wire $eq$libresoc.v:139140$7212_Y - attribute \src "libresoc.v:139141.18-139141.118" - wire $eq$libresoc.v:139141$7213_Y - attribute \src "libresoc.v:139142.18-139142.118" - wire $eq$libresoc.v:139142$7214_Y - attribute \src "libresoc.v:139143.18-139143.118" - wire $eq$libresoc.v:139143$7215_Y - attribute \src "libresoc.v:139144.18-139144.118" - wire $eq$libresoc.v:139144$7216_Y - attribute \src "libresoc.v:139145.18-139145.118" - wire $eq$libresoc.v:139145$7217_Y - attribute \src "libresoc.v:139146.18-139146.118" - wire $eq$libresoc.v:139146$7218_Y - attribute \src "libresoc.v:139147.18-139147.118" - wire $eq$libresoc.v:139147$7219_Y - attribute \src "libresoc.v:139148.18-139148.118" - wire $eq$libresoc.v:139148$7220_Y - attribute \src "libresoc.v:139149.18-139149.118" - wire $eq$libresoc.v:139149$7221_Y - attribute \src "libresoc.v:139150.18-139150.118" - wire $eq$libresoc.v:139150$7222_Y - attribute \src "libresoc.v:139151.18-139151.118" - wire $eq$libresoc.v:139151$7223_Y - attribute \src "libresoc.v:139152.18-139152.118" - wire $eq$libresoc.v:139152$7224_Y - attribute \src "libresoc.v:139153.18-139153.118" - wire $eq$libresoc.v:139153$7225_Y - attribute \src "libresoc.v:139104.19-139104.104" - wire width 64 $extend$libresoc.v:139104$7171_Y - attribute \src "libresoc.v:139106.19-139106.93" - wire width 8 $extend$libresoc.v:139106$7174_Y - attribute \src "libresoc.v:139108.19-139108.105" - wire width 64 $extend$libresoc.v:139108$7177_Y - attribute \src "libresoc.v:139109.19-139109.118" - wire width 64 $extend$libresoc.v:139109$7179_Y - attribute \src "libresoc.v:139113.19-139113.105" - wire width 64 $extend$libresoc.v:139113$7184_Y - attribute \src "libresoc.v:139116.18-139116.103" - wire width 64 $or$libresoc.v:139116$7188_Y - attribute \src "libresoc.v:139104.19-139104.104" - wire width 64 $pos$libresoc.v:139104$7172_Y - attribute \src "libresoc.v:139106.19-139106.93" - wire width 8 $pos$libresoc.v:139106$7175_Y - attribute \src "libresoc.v:139108.19-139108.105" - wire width 64 $pos$libresoc.v:139108$7178_Y - attribute \src "libresoc.v:139109.19-139109.118" - wire width 64 $pos$libresoc.v:139109$7180_Y - attribute \src "libresoc.v:139113.19-139113.105" - wire width 64 $pos$libresoc.v:139113$7185_Y - attribute \src "libresoc.v:139110.19-139110.131" - wire $reduce_xor$libresoc.v:139110$7181_Y - attribute \src "libresoc.v:139111.19-139111.133" - wire $reduce_xor$libresoc.v:139111$7182_Y - attribute \src "libresoc.v:139105.19-139105.112" - wire width 8 $sub$libresoc.v:139105$7173_Y - attribute \src "libresoc.v:139107.19-139107.135" - wire width 8 $ternary$libresoc.v:139107$7176_Y - attribute \src "libresoc.v:139112.19-139112.398" - wire width 32 $ternary$libresoc.v:139112$7183_Y - attribute \src "libresoc.v:139114.19-139114.621" - wire width 64 $ternary$libresoc.v:139114$7186_Y - attribute \src "libresoc.v:139103.19-139103.108" - wire $xor$libresoc.v:139103$7170_Y - attribute \src "libresoc.v:139117.18-139117.103" - wire width 64 $xor$libresoc.v:139117$7189_Y + attribute \src "libresoc.v:148916.18-148916.103" + wire width 64 $and$libresoc.v:148916$7509_Y + attribute \src "libresoc.v:148875.18-148875.118" + wire $eq$libresoc.v:148875$7463_Y + attribute \src "libresoc.v:148876.19-148876.119" + wire $eq$libresoc.v:148876$7464_Y + attribute \src "libresoc.v:148877.19-148877.119" + wire $eq$libresoc.v:148877$7465_Y + attribute \src "libresoc.v:148878.19-148878.119" + wire $eq$libresoc.v:148878$7466_Y + attribute \src "libresoc.v:148879.19-148879.119" + wire $eq$libresoc.v:148879$7467_Y + attribute \src "libresoc.v:148880.19-148880.119" + wire $eq$libresoc.v:148880$7468_Y + attribute \src "libresoc.v:148881.19-148881.119" + wire $eq$libresoc.v:148881$7469_Y + attribute \src "libresoc.v:148882.19-148882.119" + wire $eq$libresoc.v:148882$7470_Y + attribute \src "libresoc.v:148883.19-148883.119" + wire $eq$libresoc.v:148883$7471_Y + attribute \src "libresoc.v:148884.19-148884.119" + wire $eq$libresoc.v:148884$7472_Y + attribute \src "libresoc.v:148885.19-148885.119" + wire $eq$libresoc.v:148885$7473_Y + attribute \src "libresoc.v:148886.19-148886.119" + wire $eq$libresoc.v:148886$7474_Y + attribute \src "libresoc.v:148887.19-148887.119" + wire $eq$libresoc.v:148887$7475_Y + attribute \src "libresoc.v:148888.19-148888.119" + wire $eq$libresoc.v:148888$7476_Y + attribute \src "libresoc.v:148889.19-148889.119" + wire $eq$libresoc.v:148889$7477_Y + attribute \src "libresoc.v:148890.19-148890.119" + wire $eq$libresoc.v:148890$7478_Y + attribute \src "libresoc.v:148891.19-148891.119" + wire $eq$libresoc.v:148891$7479_Y + attribute \src "libresoc.v:148892.19-148892.119" + wire $eq$libresoc.v:148892$7480_Y + attribute \src "libresoc.v:148893.19-148893.119" + wire $eq$libresoc.v:148893$7481_Y + attribute \src "libresoc.v:148894.19-148894.119" + wire $eq$libresoc.v:148894$7482_Y + attribute \src "libresoc.v:148895.19-148895.119" + wire $eq$libresoc.v:148895$7483_Y + attribute \src "libresoc.v:148896.19-148896.119" + wire $eq$libresoc.v:148896$7484_Y + attribute \src "libresoc.v:148897.19-148897.119" + wire $eq$libresoc.v:148897$7485_Y + attribute \src "libresoc.v:148898.19-148898.119" + wire $eq$libresoc.v:148898$7486_Y + attribute \src "libresoc.v:148899.19-148899.119" + wire $eq$libresoc.v:148899$7487_Y + attribute \src "libresoc.v:148900.19-148900.119" + wire $eq$libresoc.v:148900$7488_Y + attribute \src "libresoc.v:148901.19-148901.119" + wire $eq$libresoc.v:148901$7489_Y + attribute \src "libresoc.v:148902.19-148902.119" + wire $eq$libresoc.v:148902$7490_Y + attribute \src "libresoc.v:148903.19-148903.128" + wire $eq$libresoc.v:148903$7491_Y + attribute \src "libresoc.v:148919.18-148919.114" + wire $eq$libresoc.v:148919$7512_Y + attribute \src "libresoc.v:148920.18-148920.114" + wire $eq$libresoc.v:148920$7513_Y + attribute \src "libresoc.v:148921.18-148921.114" + wire $eq$libresoc.v:148921$7514_Y + attribute \src "libresoc.v:148922.18-148922.114" + wire $eq$libresoc.v:148922$7515_Y + attribute \src "libresoc.v:148923.18-148923.114" + wire $eq$libresoc.v:148923$7516_Y + attribute \src "libresoc.v:148924.18-148924.114" + wire $eq$libresoc.v:148924$7517_Y + attribute \src "libresoc.v:148925.18-148925.114" + wire $eq$libresoc.v:148925$7518_Y + attribute \src "libresoc.v:148926.18-148926.114" + wire $eq$libresoc.v:148926$7519_Y + attribute \src "libresoc.v:148927.18-148927.116" + wire $eq$libresoc.v:148927$7520_Y + attribute \src "libresoc.v:148928.18-148928.116" + wire $eq$libresoc.v:148928$7521_Y + attribute \src "libresoc.v:148929.18-148929.116" + wire $eq$libresoc.v:148929$7522_Y + attribute \src "libresoc.v:148930.18-148930.116" + wire $eq$libresoc.v:148930$7523_Y + attribute \src "libresoc.v:148931.18-148931.116" + wire $eq$libresoc.v:148931$7524_Y + attribute \src "libresoc.v:148932.18-148932.116" + wire $eq$libresoc.v:148932$7525_Y + attribute \src "libresoc.v:148933.18-148933.116" + wire $eq$libresoc.v:148933$7526_Y + attribute \src "libresoc.v:148934.18-148934.116" + wire $eq$libresoc.v:148934$7527_Y + attribute \src "libresoc.v:148935.18-148935.118" + wire $eq$libresoc.v:148935$7528_Y + attribute \src "libresoc.v:148936.18-148936.118" + wire $eq$libresoc.v:148936$7529_Y + attribute \src "libresoc.v:148937.18-148937.118" + wire $eq$libresoc.v:148937$7530_Y + attribute \src "libresoc.v:148938.18-148938.118" + wire $eq$libresoc.v:148938$7531_Y + attribute \src "libresoc.v:148939.18-148939.118" + wire $eq$libresoc.v:148939$7532_Y + attribute \src "libresoc.v:148940.18-148940.118" + wire $eq$libresoc.v:148940$7533_Y + attribute \src "libresoc.v:148941.18-148941.118" + wire $eq$libresoc.v:148941$7534_Y + attribute \src "libresoc.v:148942.18-148942.118" + wire $eq$libresoc.v:148942$7535_Y + attribute \src "libresoc.v:148943.18-148943.118" + wire $eq$libresoc.v:148943$7536_Y + attribute \src "libresoc.v:148944.18-148944.118" + wire $eq$libresoc.v:148944$7537_Y + attribute \src "libresoc.v:148945.18-148945.118" + wire $eq$libresoc.v:148945$7538_Y + attribute \src "libresoc.v:148946.18-148946.118" + wire $eq$libresoc.v:148946$7539_Y + attribute \src "libresoc.v:148947.18-148947.118" + wire $eq$libresoc.v:148947$7540_Y + attribute \src "libresoc.v:148948.18-148948.118" + wire $eq$libresoc.v:148948$7541_Y + attribute \src "libresoc.v:148949.18-148949.118" + wire $eq$libresoc.v:148949$7542_Y + attribute \src "libresoc.v:148950.18-148950.118" + wire $eq$libresoc.v:148950$7543_Y + attribute \src "libresoc.v:148951.18-148951.118" + wire $eq$libresoc.v:148951$7544_Y + attribute \src "libresoc.v:148952.18-148952.118" + wire $eq$libresoc.v:148952$7545_Y + attribute \src "libresoc.v:148953.18-148953.118" + wire $eq$libresoc.v:148953$7546_Y + attribute \src "libresoc.v:148954.18-148954.118" + wire $eq$libresoc.v:148954$7547_Y + attribute \src "libresoc.v:148905.19-148905.104" + wire width 64 $extend$libresoc.v:148905$7493_Y + attribute \src "libresoc.v:148907.19-148907.93" + wire width 8 $extend$libresoc.v:148907$7496_Y + attribute \src "libresoc.v:148909.19-148909.105" + wire width 64 $extend$libresoc.v:148909$7499_Y + attribute \src "libresoc.v:148910.19-148910.118" + wire width 64 $extend$libresoc.v:148910$7501_Y + attribute \src "libresoc.v:148914.19-148914.105" + wire width 64 $extend$libresoc.v:148914$7506_Y + attribute \src "libresoc.v:148917.18-148917.103" + wire width 64 $or$libresoc.v:148917$7510_Y + attribute \src "libresoc.v:148905.19-148905.104" + wire width 64 $pos$libresoc.v:148905$7494_Y + attribute \src "libresoc.v:148907.19-148907.93" + wire width 8 $pos$libresoc.v:148907$7497_Y + attribute \src "libresoc.v:148909.19-148909.105" + wire width 64 $pos$libresoc.v:148909$7500_Y + attribute \src "libresoc.v:148910.19-148910.118" + wire width 64 $pos$libresoc.v:148910$7502_Y + attribute \src "libresoc.v:148914.19-148914.105" + wire width 64 $pos$libresoc.v:148914$7507_Y + attribute \src "libresoc.v:148911.19-148911.131" + wire $reduce_xor$libresoc.v:148911$7503_Y + attribute \src "libresoc.v:148912.19-148912.133" + wire $reduce_xor$libresoc.v:148912$7504_Y + attribute \src "libresoc.v:148906.19-148906.112" + wire width 8 $sub$libresoc.v:148906$7495_Y + attribute \src "libresoc.v:148908.19-148908.135" + wire width 8 $ternary$libresoc.v:148908$7498_Y + attribute \src "libresoc.v:148913.19-148913.398" + wire width 32 $ternary$libresoc.v:148913$7505_Y + attribute \src "libresoc.v:148915.19-148915.621" + wire width 64 $ternary$libresoc.v:148915$7508_Y + attribute \src "libresoc.v:148904.19-148904.108" + wire $xor$libresoc.v:148904$7492_Y + attribute \src "libresoc.v:148918.18-148918.103" + wire width 64 $xor$libresoc.v:148918$7511_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -292033,7 +310852,7 @@ module \main$51 wire width 64 \$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" wire width 8 \$162 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 8 \$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" wire width 8 \$166 @@ -292139,50 +310958,54 @@ module \main$51 wire width 64 \bpermd_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 \bpermd_rs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 7 \clz_lz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" wire width 64 \clz_sig_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:138613.7-138613.15" + attribute \src "libresoc.v:148408.7-148408.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -292281,6 +311104,7 @@ module \main$51 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -292357,6 +311181,7 @@ module \main$51 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -292403,9 +311228,9 @@ module \main$51 wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 41 \o @@ -292430,7 +311255,7 @@ module \main$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:139115$7187 + cell $and $and$libresoc.v:148916$7509 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -292438,10 +311263,10 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:139115$7187_Y + connect \Y $and$libresoc.v:148916$7509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139074$7141 + cell $eq $eq$libresoc.v:148875$7463 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292449,10 +311274,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139074$7141_Y + connect \Y $eq$libresoc.v:148875$7463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139075$7142 + cell $eq $eq$libresoc.v:148876$7464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292460,10 +311285,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139075$7142_Y + connect \Y $eq$libresoc.v:148876$7464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139076$7143 + cell $eq $eq$libresoc.v:148877$7465 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292471,10 +311296,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139076$7143_Y + connect \Y $eq$libresoc.v:148877$7465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139077$7144 + cell $eq $eq$libresoc.v:148878$7466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292482,10 +311307,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139077$7144_Y + connect \Y $eq$libresoc.v:148878$7466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139078$7145 + cell $eq $eq$libresoc.v:148879$7467 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292493,10 +311318,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139078$7145_Y + connect \Y $eq$libresoc.v:148879$7467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139079$7146 + cell $eq $eq$libresoc.v:148880$7468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292504,10 +311329,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139079$7146_Y + connect \Y $eq$libresoc.v:148880$7468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139080$7147 + cell $eq $eq$libresoc.v:148881$7469 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292515,10 +311340,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139080$7147_Y + connect \Y $eq$libresoc.v:148881$7469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139081$7148 + cell $eq $eq$libresoc.v:148882$7470 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292526,10 +311351,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139081$7148_Y + connect \Y $eq$libresoc.v:148882$7470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139082$7149 + cell $eq $eq$libresoc.v:148883$7471 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292537,10 +311362,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139082$7149_Y + connect \Y $eq$libresoc.v:148883$7471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139083$7150 + cell $eq $eq$libresoc.v:148884$7472 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292548,10 +311373,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139083$7150_Y + connect \Y $eq$libresoc.v:148884$7472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139084$7151 + cell $eq $eq$libresoc.v:148885$7473 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292559,10 +311384,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139084$7151_Y + connect \Y $eq$libresoc.v:148885$7473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139085$7152 + cell $eq $eq$libresoc.v:148886$7474 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292570,10 +311395,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139085$7152_Y + connect \Y $eq$libresoc.v:148886$7474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139086$7153 + cell $eq $eq$libresoc.v:148887$7475 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292581,10 +311406,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139086$7153_Y + connect \Y $eq$libresoc.v:148887$7475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139087$7154 + cell $eq $eq$libresoc.v:148888$7476 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292592,10 +311417,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139087$7154_Y + connect \Y $eq$libresoc.v:148888$7476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139088$7155 + cell $eq $eq$libresoc.v:148889$7477 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292603,10 +311428,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139088$7155_Y + connect \Y $eq$libresoc.v:148889$7477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139089$7156 + cell $eq $eq$libresoc.v:148890$7478 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292614,10 +311439,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139089$7156_Y + connect \Y $eq$libresoc.v:148890$7478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139090$7157 + cell $eq $eq$libresoc.v:148891$7479 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292625,10 +311450,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139090$7157_Y + connect \Y $eq$libresoc.v:148891$7479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139091$7158 + cell $eq $eq$libresoc.v:148892$7480 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292636,10 +311461,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139091$7158_Y + connect \Y $eq$libresoc.v:148892$7480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139092$7159 + cell $eq $eq$libresoc.v:148893$7481 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292647,10 +311472,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139092$7159_Y + connect \Y $eq$libresoc.v:148893$7481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139093$7160 + cell $eq $eq$libresoc.v:148894$7482 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292658,10 +311483,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139093$7160_Y + connect \Y $eq$libresoc.v:148894$7482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139094$7161 + cell $eq $eq$libresoc.v:148895$7483 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292669,10 +311494,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139094$7161_Y + connect \Y $eq$libresoc.v:148895$7483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139095$7162 + cell $eq $eq$libresoc.v:148896$7484 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292680,10 +311505,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139095$7162_Y + connect \Y $eq$libresoc.v:148896$7484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139096$7163 + cell $eq $eq$libresoc.v:148897$7485 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292691,10 +311516,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139096$7163_Y + connect \Y $eq$libresoc.v:148897$7485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139097$7164 + cell $eq $eq$libresoc.v:148898$7486 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292702,10 +311527,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139097$7164_Y + connect \Y $eq$libresoc.v:148898$7486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139098$7165 + cell $eq $eq$libresoc.v:148899$7487 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292713,10 +311538,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139098$7165_Y + connect \Y $eq$libresoc.v:148899$7487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139099$7166 + cell $eq $eq$libresoc.v:148900$7488 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292724,10 +311549,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139099$7166_Y + connect \Y $eq$libresoc.v:148900$7488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139100$7167 + cell $eq $eq$libresoc.v:148901$7489 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292735,10 +311560,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139100$7167_Y + connect \Y $eq$libresoc.v:148901$7489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139101$7168 + cell $eq $eq$libresoc.v:148902$7490 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292746,10 +311571,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139101$7168_Y + connect \Y $eq$libresoc.v:148902$7490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:139102$7169 + cell $eq $eq$libresoc.v:148903$7491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -292757,10 +311582,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:139102$7169_Y + connect \Y $eq$libresoc.v:148903$7491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139118$7190 + cell $eq $eq$libresoc.v:148919$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292768,10 +311593,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139118$7190_Y + connect \Y $eq$libresoc.v:148919$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139119$7191 + cell $eq $eq$libresoc.v:148920$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292779,10 +311604,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139119$7191_Y + connect \Y $eq$libresoc.v:148920$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139120$7192 + cell $eq $eq$libresoc.v:148921$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292790,10 +311615,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139120$7192_Y + connect \Y $eq$libresoc.v:148921$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139121$7193 + cell $eq $eq$libresoc.v:148922$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292801,10 +311626,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139121$7193_Y + connect \Y $eq$libresoc.v:148922$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139122$7194 + cell $eq $eq$libresoc.v:148923$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292812,10 +311637,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139122$7194_Y + connect \Y $eq$libresoc.v:148923$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139123$7195 + cell $eq $eq$libresoc.v:148924$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292823,10 +311648,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139123$7195_Y + connect \Y $eq$libresoc.v:148924$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139124$7196 + cell $eq $eq$libresoc.v:148925$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292834,10 +311659,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139124$7196_Y + connect \Y $eq$libresoc.v:148925$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139125$7197 + cell $eq $eq$libresoc.v:148926$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292845,10 +311670,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139125$7197_Y + connect \Y $eq$libresoc.v:148926$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139126$7198 + cell $eq $eq$libresoc.v:148927$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292856,10 +311681,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139126$7198_Y + connect \Y $eq$libresoc.v:148927$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139127$7199 + cell $eq $eq$libresoc.v:148928$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292867,10 +311692,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139127$7199_Y + connect \Y $eq$libresoc.v:148928$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139128$7200 + cell $eq $eq$libresoc.v:148929$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292878,10 +311703,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139128$7200_Y + connect \Y $eq$libresoc.v:148929$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139129$7201 + cell $eq $eq$libresoc.v:148930$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292889,10 +311714,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139129$7201_Y + connect \Y $eq$libresoc.v:148930$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139130$7202 + cell $eq $eq$libresoc.v:148931$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292900,10 +311725,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139130$7202_Y + connect \Y $eq$libresoc.v:148931$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139131$7203 + cell $eq $eq$libresoc.v:148932$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292911,10 +311736,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139131$7203_Y + connect \Y $eq$libresoc.v:148932$7525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139132$7204 + cell $eq $eq$libresoc.v:148933$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292922,10 +311747,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139132$7204_Y + connect \Y $eq$libresoc.v:148933$7526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139133$7205 + cell $eq $eq$libresoc.v:148934$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292933,10 +311758,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139133$7205_Y + connect \Y $eq$libresoc.v:148934$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139134$7206 + cell $eq $eq$libresoc.v:148935$7528 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292944,10 +311769,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139134$7206_Y + connect \Y $eq$libresoc.v:148935$7528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139135$7207 + cell $eq $eq$libresoc.v:148936$7529 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292955,10 +311780,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139135$7207_Y + connect \Y $eq$libresoc.v:148936$7529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139136$7208 + cell $eq $eq$libresoc.v:148937$7530 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292966,10 +311791,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139136$7208_Y + connect \Y $eq$libresoc.v:148937$7530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139137$7209 + cell $eq $eq$libresoc.v:148938$7531 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292977,10 +311802,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139137$7209_Y + connect \Y $eq$libresoc.v:148938$7531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139138$7210 + cell $eq $eq$libresoc.v:148939$7532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292988,10 +311813,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139138$7210_Y + connect \Y $eq$libresoc.v:148939$7532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139139$7211 + cell $eq $eq$libresoc.v:148940$7533 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -292999,10 +311824,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139139$7211_Y + connect \Y $eq$libresoc.v:148940$7533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139140$7212 + cell $eq $eq$libresoc.v:148941$7534 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293010,10 +311835,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139140$7212_Y + connect \Y $eq$libresoc.v:148941$7534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139141$7213 + cell $eq $eq$libresoc.v:148942$7535 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293021,10 +311846,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139141$7213_Y + connect \Y $eq$libresoc.v:148942$7535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139142$7214 + cell $eq $eq$libresoc.v:148943$7536 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293032,10 +311857,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139142$7214_Y + connect \Y $eq$libresoc.v:148943$7536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139143$7215 + cell $eq $eq$libresoc.v:148944$7537 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293043,10 +311868,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139143$7215_Y + connect \Y $eq$libresoc.v:148944$7537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139144$7216 + cell $eq $eq$libresoc.v:148945$7538 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293054,10 +311879,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139144$7216_Y + connect \Y $eq$libresoc.v:148945$7538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139145$7217 + cell $eq $eq$libresoc.v:148946$7539 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293065,10 +311890,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139145$7217_Y + connect \Y $eq$libresoc.v:148946$7539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139146$7218 + cell $eq $eq$libresoc.v:148947$7540 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293076,10 +311901,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139146$7218_Y + connect \Y $eq$libresoc.v:148947$7540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139147$7219 + cell $eq $eq$libresoc.v:148948$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293087,10 +311912,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139147$7219_Y + connect \Y $eq$libresoc.v:148948$7541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139148$7220 + cell $eq $eq$libresoc.v:148949$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293098,10 +311923,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139148$7220_Y + connect \Y $eq$libresoc.v:148949$7542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139149$7221 + cell $eq $eq$libresoc.v:148950$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293109,10 +311934,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139149$7221_Y + connect \Y $eq$libresoc.v:148950$7543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139150$7222 + cell $eq $eq$libresoc.v:148951$7544 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293120,10 +311945,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139150$7222_Y + connect \Y $eq$libresoc.v:148951$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139151$7223 + cell $eq $eq$libresoc.v:148952$7545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293131,10 +311956,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139151$7223_Y + connect \Y $eq$libresoc.v:148952$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139152$7224 + cell $eq $eq$libresoc.v:148953$7546 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293142,10 +311967,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139152$7224_Y + connect \Y $eq$libresoc.v:148953$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139153$7225 + cell $eq $eq$libresoc.v:148954$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -293153,50 +311978,50 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139153$7225_Y + connect \Y $eq$libresoc.v:148954$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:139104$7171 + cell $pos $extend$libresoc.v:148905$7493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:139104$7171_Y + connect \Y $extend$libresoc.v:148905$7493_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $extend$libresoc.v:139106$7174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + cell $pos $extend$libresoc.v:148907$7496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:139106$7174_Y + connect \Y $extend$libresoc.v:148907$7496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:139108$7177 + cell $pos $extend$libresoc.v:148909$7499 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:139108$7177_Y + connect \Y $extend$libresoc.v:148909$7499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:139109$7179 + cell $pos $extend$libresoc.v:148910$7501 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:139109$7179_Y + connect \Y $extend$libresoc.v:148910$7501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:139113$7184 + cell $pos $extend$libresoc.v:148914$7506 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:139113$7184_Y + connect \Y $extend$libresoc.v:148914$7506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:139116$7188 + cell $or $or$libresoc.v:148917$7510 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -293204,66 +312029,66 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:139116$7188_Y + connect \Y $or$libresoc.v:148917$7510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:139104$7172 + cell $pos $pos$libresoc.v:148905$7494 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139104$7171_Y - connect \Y $pos$libresoc.v:139104$7172_Y + connect \A $extend$libresoc.v:148905$7493_Y + connect \Y $pos$libresoc.v:148905$7494_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $pos$libresoc.v:139106$7175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + cell $pos $pos$libresoc.v:148907$7497 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:139106$7174_Y - connect \Y $pos$libresoc.v:139106$7175_Y + connect \A $extend$libresoc.v:148907$7496_Y + connect \Y $pos$libresoc.v:148907$7497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:139108$7178 + cell $pos $pos$libresoc.v:148909$7500 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139108$7177_Y - connect \Y $pos$libresoc.v:139108$7178_Y + connect \A $extend$libresoc.v:148909$7499_Y + connect \Y $pos$libresoc.v:148909$7500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:139109$7180 + cell $pos $pos$libresoc.v:148910$7502 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139109$7179_Y - connect \Y $pos$libresoc.v:139109$7180_Y + connect \A $extend$libresoc.v:148910$7501_Y + connect \Y $pos$libresoc.v:148910$7502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:139113$7185 + cell $pos $pos$libresoc.v:148914$7507 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139113$7184_Y - connect \Y $pos$libresoc.v:139113$7185_Y + connect \A $extend$libresoc.v:148914$7506_Y + connect \Y $pos$libresoc.v:148914$7507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:139110$7181 + cell $reduce_xor $reduce_xor$libresoc.v:148911$7503 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:139110$7181_Y + connect \Y $reduce_xor$libresoc.v:148911$7503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:139111$7182 + cell $reduce_xor $reduce_xor$libresoc.v:148912$7504 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:139111$7182_Y + connect \Y $reduce_xor$libresoc.v:148912$7504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:139105$7173 + cell $sub $sub$libresoc.v:148906$7495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -293271,34 +312096,34 @@ module \main$51 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:139105$7173_Y + connect \Y $sub$libresoc.v:148906$7495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:139107$7176 + cell $mux $ternary$libresoc.v:148908$7498 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:139107$7176_Y + connect \Y $ternary$libresoc.v:148908$7498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:139112$7183 + cell $mux $ternary$libresoc.v:148913$7505 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:139112$7183_Y + connect \Y $ternary$libresoc.v:148913$7505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:139114$7186 + cell $mux $ternary$libresoc.v:148915$7508 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:139114$7186_Y + connect \Y $ternary$libresoc.v:148915$7508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:139103$7170 + cell $xor $xor$libresoc.v:148904$7492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293306,10 +312131,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:139103$7170_Y + connect \Y $xor$libresoc.v:148904$7492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:139117$7189 + cell $xor $xor$libresoc.v:148918$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -293317,47 +312142,47 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:139117$7189_Y + connect \Y $xor$libresoc.v:148918$7511_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:139154.10-139158.4" + attribute \src "libresoc.v:148955.10-148959.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:139159.7-139162.4" + attribute \src "libresoc.v:148960.7-148963.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:139163.12-139167.4" + attribute \src "libresoc.v:148964.12-148968.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:138613.7-138613.20" - process $proc$libresoc.v:138613$7238 + attribute \src "libresoc.v:148408.7-148408.20" + process $proc$libresoc.v:148408$7560 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139168.3-139222.6" - process $proc$libresoc.v:139168$7226 + attribute \src "libresoc.v:148969.3-149023.6" + process $proc$libresoc.v:148969$7548 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:139169.5-139169.29" + attribute \src "libresoc.v:148970.5-148970.29" switch \initial - attribute \src "libresoc.v:139169.9-139169.17" + attribute \src "libresoc.v:148970.9-148970.17" case 1'1 case end @@ -293425,14 +312250,14 @@ module \main$51 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:139223.3-139233.6" - process $proc$libresoc.v:139223$7227 + attribute \src "libresoc.v:149024.3-149034.6" + process $proc$libresoc.v:149024$7549 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:139224.5-139224.29" + attribute \src "libresoc.v:149025.5-149025.29" switch \initial - attribute \src "libresoc.v:139224.9-139224.17" + attribute \src "libresoc.v:149025.9-149025.17" case 1'1 case end @@ -293448,14 +312273,14 @@ module \main$51 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:139234.3-139244.6" - process $proc$libresoc.v:139234$7228 + attribute \src "libresoc.v:149035.3-149045.6" + process $proc$libresoc.v:149035$7550 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:139235.5-139235.29" + attribute \src "libresoc.v:149036.5-149036.29" switch \initial - attribute \src "libresoc.v:139235.9-139235.17" + attribute \src "libresoc.v:149036.9-149036.17" case 1'1 case end @@ -293471,14 +312296,14 @@ module \main$51 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:139245.3-139255.6" - process $proc$libresoc.v:139245$7229 + attribute \src "libresoc.v:149046.3-149056.6" + process $proc$libresoc.v:149046$7551 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:139246.5-139246.29" + attribute \src "libresoc.v:149047.5-149047.29" switch \initial - attribute \src "libresoc.v:139246.9-139246.17" + attribute \src "libresoc.v:149047.9-149047.17" case 1'1 case end @@ -293494,14 +312319,14 @@ module \main$51 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:139256.3-139266.6" - process $proc$libresoc.v:139256$7230 + attribute \src "libresoc.v:149057.3-149067.6" + process $proc$libresoc.v:149057$7552 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:139257.5-139257.29" + attribute \src "libresoc.v:149058.5-149058.29" switch \initial - attribute \src "libresoc.v:139257.9-139257.17" + attribute \src "libresoc.v:149058.9-149058.17" case 1'1 case end @@ -293517,14 +312342,14 @@ module \main$51 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:139267.3-139277.6" - process $proc$libresoc.v:139267$7231 + attribute \src "libresoc.v:149068.3-149078.6" + process $proc$libresoc.v:149068$7553 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:139268.5-139268.29" + attribute \src "libresoc.v:149069.5-149069.29" switch \initial - attribute \src "libresoc.v:139268.9-139268.17" + attribute \src "libresoc.v:149069.9-149069.17" case 1'1 case end @@ -293540,14 +312365,14 @@ module \main$51 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:139278.3-139288.6" - process $proc$libresoc.v:139278$7232 + attribute \src "libresoc.v:149079.3-149089.6" + process $proc$libresoc.v:149079$7554 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:139279.5-139279.29" + attribute \src "libresoc.v:149080.5-149080.29" switch \initial - attribute \src "libresoc.v:139279.9-139279.17" + attribute \src "libresoc.v:149080.9-149080.17" case 1'1 case end @@ -293563,14 +312388,14 @@ module \main$51 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:139289.3-139299.6" - process $proc$libresoc.v:139289$7233 + attribute \src "libresoc.v:149090.3-149100.6" + process $proc$libresoc.v:149090$7555 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:139290.5-139290.29" + attribute \src "libresoc.v:149091.5-149091.29" switch \initial - attribute \src "libresoc.v:139290.9-139290.17" + attribute \src "libresoc.v:149091.9-149091.17" case 1'1 case end @@ -293586,14 +312411,14 @@ module \main$51 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:139300.3-139310.6" - process $proc$libresoc.v:139300$7234 + attribute \src "libresoc.v:149101.3-149111.6" + process $proc$libresoc.v:149101$7556 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:139301.5-139301.29" + attribute \src "libresoc.v:149102.5-149102.29" switch \initial - attribute \src "libresoc.v:139301.9-139301.17" + attribute \src "libresoc.v:149102.9-149102.17" case 1'1 case end @@ -293609,14 +312434,14 @@ module \main$51 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:139311.3-139321.6" - process $proc$libresoc.v:139311$7235 + attribute \src "libresoc.v:149112.3-149122.6" + process $proc$libresoc.v:149112$7557 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:139312.5-139312.29" + attribute \src "libresoc.v:149113.5-149113.29" switch \initial - attribute \src "libresoc.v:139312.9-139312.17" + attribute \src "libresoc.v:149113.9-149113.17" case 1'1 case end @@ -293632,14 +312457,14 @@ module \main$51 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:139322.3-139332.6" - process $proc$libresoc.v:139322$7236 + attribute \src "libresoc.v:149123.3-149133.6" + process $proc$libresoc.v:149123$7558 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:139323.5-139323.29" + attribute \src "libresoc.v:149124.5-149124.29" switch \initial - attribute \src "libresoc.v:139323.9-139323.17" + attribute \src "libresoc.v:149124.9-149124.17" case 1'1 case end @@ -293655,14 +312480,14 @@ module \main$51 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:139333.3-139351.6" - process $proc$libresoc.v:139333$7237 + attribute \src "libresoc.v:149134.3-149152.6" + process $proc$libresoc.v:149134$7559 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:139334.5-139334.29" + attribute \src "libresoc.v:149135.5-149135.29" switch \initial - attribute \src "libresoc.v:139334.9-139334.17" + attribute \src "libresoc.v:149135.9-149135.17" case 1'1 case end @@ -293689,193 +312514,193 @@ module \main$51 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:139074$7141_Y - connect \$101 $eq$libresoc.v:139075$7142_Y - connect \$103 $eq$libresoc.v:139076$7143_Y - connect \$105 $eq$libresoc.v:139077$7144_Y - connect \$107 $eq$libresoc.v:139078$7145_Y - connect \$109 $eq$libresoc.v:139079$7146_Y - connect \$111 $eq$libresoc.v:139080$7147_Y - connect \$113 $eq$libresoc.v:139081$7148_Y - connect \$115 $eq$libresoc.v:139082$7149_Y - connect \$117 $eq$libresoc.v:139083$7150_Y - connect \$119 $eq$libresoc.v:139084$7151_Y - connect \$121 $eq$libresoc.v:139085$7152_Y - connect \$123 $eq$libresoc.v:139086$7153_Y - connect \$125 $eq$libresoc.v:139087$7154_Y - connect \$127 $eq$libresoc.v:139088$7155_Y - connect \$129 $eq$libresoc.v:139089$7156_Y - connect \$131 $eq$libresoc.v:139090$7157_Y - connect \$133 $eq$libresoc.v:139091$7158_Y - connect \$135 $eq$libresoc.v:139092$7159_Y - connect \$137 $eq$libresoc.v:139093$7160_Y - connect \$139 $eq$libresoc.v:139094$7161_Y - connect \$141 $eq$libresoc.v:139095$7162_Y - connect \$143 $eq$libresoc.v:139096$7163_Y - connect \$145 $eq$libresoc.v:139097$7164_Y - connect \$147 $eq$libresoc.v:139098$7165_Y - connect \$149 $eq$libresoc.v:139099$7166_Y - connect \$151 $eq$libresoc.v:139100$7167_Y - connect \$153 $eq$libresoc.v:139101$7168_Y - connect \$155 $eq$libresoc.v:139102$7169_Y - connect \$158 $xor$libresoc.v:139103$7170_Y - connect \$157 $pos$libresoc.v:139104$7172_Y - connect \$162 $sub$libresoc.v:139105$7173_Y - connect \$164 $pos$libresoc.v:139106$7175_Y - connect \$166 $ternary$libresoc.v:139107$7176_Y - connect \$161 $pos$libresoc.v:139108$7178_Y - connect \$169 $pos$libresoc.v:139109$7180_Y - connect \$171 $reduce_xor$libresoc.v:139110$7181_Y - connect \$173 $reduce_xor$libresoc.v:139111$7182_Y - connect \$176 $ternary$libresoc.v:139112$7183_Y - connect \$175 $pos$libresoc.v:139113$7185_Y - connect \$179 $ternary$libresoc.v:139114$7186_Y - connect \$21 $and$libresoc.v:139115$7187_Y - connect \$23 $or$libresoc.v:139116$7188_Y - connect \$25 $xor$libresoc.v:139117$7189_Y - connect \$27 $eq$libresoc.v:139118$7190_Y - connect \$29 $eq$libresoc.v:139119$7191_Y - connect \$31 $eq$libresoc.v:139120$7192_Y - connect \$33 $eq$libresoc.v:139121$7193_Y - connect \$35 $eq$libresoc.v:139122$7194_Y - connect \$37 $eq$libresoc.v:139123$7195_Y - connect \$39 $eq$libresoc.v:139124$7196_Y - connect \$41 $eq$libresoc.v:139125$7197_Y - connect \$43 $eq$libresoc.v:139126$7198_Y - connect \$45 $eq$libresoc.v:139127$7199_Y - connect \$47 $eq$libresoc.v:139128$7200_Y - connect \$49 $eq$libresoc.v:139129$7201_Y - connect \$51 $eq$libresoc.v:139130$7202_Y - connect \$53 $eq$libresoc.v:139131$7203_Y - connect \$55 $eq$libresoc.v:139132$7204_Y - connect \$57 $eq$libresoc.v:139133$7205_Y - connect \$59 $eq$libresoc.v:139134$7206_Y - connect \$61 $eq$libresoc.v:139135$7207_Y - connect \$63 $eq$libresoc.v:139136$7208_Y - connect \$65 $eq$libresoc.v:139137$7209_Y - connect \$67 $eq$libresoc.v:139138$7210_Y - connect \$69 $eq$libresoc.v:139139$7211_Y - connect \$71 $eq$libresoc.v:139140$7212_Y - connect \$73 $eq$libresoc.v:139141$7213_Y - connect \$75 $eq$libresoc.v:139142$7214_Y - connect \$77 $eq$libresoc.v:139143$7215_Y - connect \$79 $eq$libresoc.v:139144$7216_Y - connect \$81 $eq$libresoc.v:139145$7217_Y - connect \$83 $eq$libresoc.v:139146$7218_Y - connect \$85 $eq$libresoc.v:139147$7219_Y - connect \$87 $eq$libresoc.v:139148$7220_Y - connect \$89 $eq$libresoc.v:139149$7221_Y - connect \$91 $eq$libresoc.v:139150$7222_Y - connect \$93 $eq$libresoc.v:139151$7223_Y - connect \$95 $eq$libresoc.v:139152$7224_Y - connect \$97 $eq$libresoc.v:139153$7225_Y + connect \$99 $eq$libresoc.v:148875$7463_Y + connect \$101 $eq$libresoc.v:148876$7464_Y + connect \$103 $eq$libresoc.v:148877$7465_Y + connect \$105 $eq$libresoc.v:148878$7466_Y + connect \$107 $eq$libresoc.v:148879$7467_Y + connect \$109 $eq$libresoc.v:148880$7468_Y + connect \$111 $eq$libresoc.v:148881$7469_Y + connect \$113 $eq$libresoc.v:148882$7470_Y + connect \$115 $eq$libresoc.v:148883$7471_Y + connect \$117 $eq$libresoc.v:148884$7472_Y + connect \$119 $eq$libresoc.v:148885$7473_Y + connect \$121 $eq$libresoc.v:148886$7474_Y + connect \$123 $eq$libresoc.v:148887$7475_Y + connect \$125 $eq$libresoc.v:148888$7476_Y + connect \$127 $eq$libresoc.v:148889$7477_Y + connect \$129 $eq$libresoc.v:148890$7478_Y + connect \$131 $eq$libresoc.v:148891$7479_Y + connect \$133 $eq$libresoc.v:148892$7480_Y + connect \$135 $eq$libresoc.v:148893$7481_Y + connect \$137 $eq$libresoc.v:148894$7482_Y + connect \$139 $eq$libresoc.v:148895$7483_Y + connect \$141 $eq$libresoc.v:148896$7484_Y + connect \$143 $eq$libresoc.v:148897$7485_Y + connect \$145 $eq$libresoc.v:148898$7486_Y + connect \$147 $eq$libresoc.v:148899$7487_Y + connect \$149 $eq$libresoc.v:148900$7488_Y + connect \$151 $eq$libresoc.v:148901$7489_Y + connect \$153 $eq$libresoc.v:148902$7490_Y + connect \$155 $eq$libresoc.v:148903$7491_Y + connect \$158 $xor$libresoc.v:148904$7492_Y + connect \$157 $pos$libresoc.v:148905$7494_Y + connect \$162 $sub$libresoc.v:148906$7495_Y + connect \$164 $pos$libresoc.v:148907$7497_Y + connect \$166 $ternary$libresoc.v:148908$7498_Y + connect \$161 $pos$libresoc.v:148909$7500_Y + connect \$169 $pos$libresoc.v:148910$7502_Y + connect \$171 $reduce_xor$libresoc.v:148911$7503_Y + connect \$173 $reduce_xor$libresoc.v:148912$7504_Y + connect \$176 $ternary$libresoc.v:148913$7505_Y + connect \$175 $pos$libresoc.v:148914$7507_Y + connect \$179 $ternary$libresoc.v:148915$7508_Y + connect \$21 $and$libresoc.v:148916$7509_Y + connect \$23 $or$libresoc.v:148917$7510_Y + connect \$25 $xor$libresoc.v:148918$7511_Y + connect \$27 $eq$libresoc.v:148919$7512_Y + connect \$29 $eq$libresoc.v:148920$7513_Y + connect \$31 $eq$libresoc.v:148921$7514_Y + connect \$33 $eq$libresoc.v:148922$7515_Y + connect \$35 $eq$libresoc.v:148923$7516_Y + connect \$37 $eq$libresoc.v:148924$7517_Y + connect \$39 $eq$libresoc.v:148925$7518_Y + connect \$41 $eq$libresoc.v:148926$7519_Y + connect \$43 $eq$libresoc.v:148927$7520_Y + connect \$45 $eq$libresoc.v:148928$7521_Y + connect \$47 $eq$libresoc.v:148929$7522_Y + connect \$49 $eq$libresoc.v:148930$7523_Y + connect \$51 $eq$libresoc.v:148931$7524_Y + connect \$53 $eq$libresoc.v:148932$7525_Y + connect \$55 $eq$libresoc.v:148933$7526_Y + connect \$57 $eq$libresoc.v:148934$7527_Y + connect \$59 $eq$libresoc.v:148935$7528_Y + connect \$61 $eq$libresoc.v:148936$7529_Y + connect \$63 $eq$libresoc.v:148937$7530_Y + connect \$65 $eq$libresoc.v:148938$7531_Y + connect \$67 $eq$libresoc.v:148939$7532_Y + connect \$69 $eq$libresoc.v:148940$7533_Y + connect \$71 $eq$libresoc.v:148941$7534_Y + connect \$73 $eq$libresoc.v:148942$7535_Y + connect \$75 $eq$libresoc.v:148943$7536_Y + connect \$77 $eq$libresoc.v:148944$7537_Y + connect \$79 $eq$libresoc.v:148945$7538_Y + connect \$81 $eq$libresoc.v:148946$7539_Y + connect \$83 $eq$libresoc.v:148947$7540_Y + connect \$85 $eq$libresoc.v:148948$7541_Y + connect \$87 $eq$libresoc.v:148949$7542_Y + connect \$89 $eq$libresoc.v:148950$7543_Y + connect \$91 $eq$libresoc.v:148951$7544_Y + connect \$93 $eq$libresoc.v:148952$7545_Y + connect \$95 $eq$libresoc.v:148953$7546_Y + connect \$97 $eq$libresoc.v:148954$7547_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:139359.1-139868.10" +attribute \src "libresoc.v:149160.1-149675.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:139723.3-139733.6" + attribute \src "libresoc.v:149530.3-149540.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:139777.3-139787.6" + attribute \src "libresoc.v:149584.3-149594.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:139788.3-139798.6" + attribute \src "libresoc.v:149595.3-149605.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:139799.3-139819.6" + attribute \src "libresoc.v:149606.3-149626.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:139820.3-139840.6" + attribute \src "libresoc.v:149627.3-149647.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:139841.3-139851.6" + attribute \src "libresoc.v:149648.3-149658.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:139766.3-139776.6" + attribute \src "libresoc.v:149573.3-149583.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:139635.3-139669.6" - wire width 4 $0\cr_a$6[3:0]$7253 - attribute \src "libresoc.v:139635.3-139669.6" + attribute \src "libresoc.v:149442.3-149476.6" + wire width 4 $0\cr_a$6[3:0]$7575 + attribute \src "libresoc.v:149442.3-149476.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:139734.3-139754.6" + attribute \src "libresoc.v:149541.3-149561.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:139852.3-139862.6" - wire width 32 $0\full_cr$5[31:0]$7268 - attribute \src "libresoc.v:139670.3-139680.6" + attribute \src "libresoc.v:149659.3-149669.6" + wire width 32 $0\full_cr$5[31:0]$7590 + attribute \src "libresoc.v:149477.3-149487.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:139360.7-139360.20" + attribute \src "libresoc.v:149161.7-149161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139755.3-139765.6" + attribute \src "libresoc.v:149562.3-149572.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:139681.3-139722.6" + attribute \src "libresoc.v:149488.3-149529.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:139681.3-139722.6" + attribute \src "libresoc.v:149488.3-149529.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:139723.3-139733.6" + attribute \src "libresoc.v:149530.3-149540.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:139777.3-139787.6" + attribute \src "libresoc.v:149584.3-149594.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:139788.3-139798.6" + attribute \src "libresoc.v:149595.3-149605.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:139799.3-139819.6" + attribute \src "libresoc.v:149606.3-149626.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:139820.3-139840.6" + attribute \src "libresoc.v:149627.3-149647.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:139841.3-139851.6" + attribute \src "libresoc.v:149648.3-149658.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:139766.3-139776.6" + attribute \src "libresoc.v:149573.3-149583.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:139635.3-139669.6" - wire width 4 $1\cr_a$6[3:0]$7254 - attribute \src "libresoc.v:139635.3-139669.6" + attribute \src "libresoc.v:149442.3-149476.6" + wire width 4 $1\cr_a$6[3:0]$7576 + attribute \src "libresoc.v:149442.3-149476.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:139734.3-139754.6" + attribute \src "libresoc.v:149541.3-149561.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:139852.3-139862.6" - wire width 32 $1\full_cr$5[31:0]$7269 - attribute \src "libresoc.v:139670.3-139680.6" + attribute \src "libresoc.v:149659.3-149669.6" + wire width 32 $1\full_cr$5[31:0]$7591 + attribute \src "libresoc.v:149477.3-149487.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:139755.3-139765.6" + attribute \src "libresoc.v:149562.3-149572.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:139681.3-139722.6" + attribute \src "libresoc.v:149488.3-149529.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:139681.3-139722.6" + attribute \src "libresoc.v:149488.3-149529.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:139799.3-139819.6" + attribute \src "libresoc.v:149606.3-149626.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:139820.3-139840.6" + attribute \src "libresoc.v:149627.3-149647.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:139635.3-139669.6" - wire width 4 $2\cr_a$6[3:0]$7255 - attribute \src "libresoc.v:139734.3-139754.6" + attribute \src "libresoc.v:149442.3-149476.6" + wire width 4 $2\cr_a$6[3:0]$7577 + attribute \src "libresoc.v:149541.3-149561.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:139681.3-139722.6" + attribute \src "libresoc.v:149488.3-149529.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:139631.18-139631.96" - wire width 64 $extend$libresoc.v:139631$7245_Y - attribute \src "libresoc.v:139633.18-139633.98" - wire width 65 $extend$libresoc.v:139633$7248_Y - attribute \src "libresoc.v:139634.17-139634.92" - wire width 5 $extend$libresoc.v:139634$7250_Y - attribute \src "libresoc.v:139631.18-139631.96" - wire width 64 $pos$libresoc.v:139631$7246_Y - attribute \src "libresoc.v:139633.18-139633.98" - wire width 65 $pos$libresoc.v:139633$7249_Y - attribute \src "libresoc.v:139634.17-139634.92" - wire width 5 $pos$libresoc.v:139634$7251_Y - attribute \src "libresoc.v:139625.18-139625.116" - wire width 3 $sub$libresoc.v:139625$7239_Y - attribute \src "libresoc.v:139626.18-139626.116" - wire width 3 $sub$libresoc.v:139626$7240_Y - attribute \src "libresoc.v:139627.18-139627.116" - wire width 3 $sub$libresoc.v:139627$7241_Y - attribute \src "libresoc.v:139628.18-139628.114" - wire $ternary$libresoc.v:139628$7242_Y - attribute \src "libresoc.v:139629.18-139629.115" - wire $ternary$libresoc.v:139629$7243_Y - attribute \src "libresoc.v:139630.18-139630.112" - wire $ternary$libresoc.v:139630$7244_Y - attribute \src "libresoc.v:139632.18-139632.108" - wire width 64 $ternary$libresoc.v:139632$7247_Y + attribute \src "libresoc.v:149438.18-149438.96" + wire width 64 $extend$libresoc.v:149438$7567_Y + attribute \src "libresoc.v:149440.18-149440.98" + wire width 65 $extend$libresoc.v:149440$7570_Y + attribute \src "libresoc.v:149441.17-149441.92" + wire width 5 $extend$libresoc.v:149441$7572_Y + attribute \src "libresoc.v:149438.18-149438.96" + wire width 64 $pos$libresoc.v:149438$7568_Y + attribute \src "libresoc.v:149440.18-149440.98" + wire width 65 $pos$libresoc.v:149440$7571_Y + attribute \src "libresoc.v:149441.17-149441.92" + wire width 5 $pos$libresoc.v:149441$7573_Y + attribute \src "libresoc.v:149432.18-149432.116" + wire width 3 $sub$libresoc.v:149432$7561_Y + attribute \src "libresoc.v:149433.18-149433.116" + wire width 3 $sub$libresoc.v:149433$7562_Y + attribute \src "libresoc.v:149434.18-149434.116" + wire width 3 $sub$libresoc.v:149434$7563_Y + attribute \src "libresoc.v:149435.18-149435.114" + wire $ternary$libresoc.v:149435$7564_Y + attribute \src "libresoc.v:149436.18-149436.115" + wire $ternary$libresoc.v:149436$7565_Y + attribute \src "libresoc.v:149437.18-149437.112" + wire $ternary$libresoc.v:149437$7566_Y + attribute \src "libresoc.v:149439.18-149439.108" + wire width 64 $ternary$libresoc.v:149439$7569_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -293929,35 +312754,39 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 9 \cr_c attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \cr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 12 \cr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 12 \cr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -294036,6 +312865,7 @@ module \main$9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \cr_op__insn_type attribute \enum_base_type "MicrOp" @@ -294112,6 +312942,7 @@ module \main$9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 11 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -294120,13 +312951,13 @@ module \main$9 wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \full_cr_ok - attribute \src "libresoc.v:139360.7-139360.15" + attribute \src "libresoc.v:149161.7-149161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 20 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 10 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 14 \o @@ -294137,55 +312968,55 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:139631$7245 + cell $pos $extend$libresoc.v:149438$7567 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:139631$7245_Y + connect \Y $extend$libresoc.v:149438$7567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:139633$7248 + cell $pos $extend$libresoc.v:149440$7570 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:139633$7248_Y + connect \Y $extend$libresoc.v:149440$7570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:139634$7250 + cell $pos $extend$libresoc.v:149441$7572 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:139634$7250_Y + connect \Y $extend$libresoc.v:149441$7572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:139631$7246 + cell $pos $pos$libresoc.v:149438$7568 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139631$7245_Y - connect \Y $pos$libresoc.v:139631$7246_Y + connect \A $extend$libresoc.v:149438$7567_Y + connect \Y $pos$libresoc.v:149438$7568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:139633$7249 + cell $pos $pos$libresoc.v:149440$7571 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:139633$7248_Y - connect \Y $pos$libresoc.v:139633$7249_Y + connect \A $extend$libresoc.v:149440$7570_Y + connect \Y $pos$libresoc.v:149440$7571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:139634$7251 + cell $pos $pos$libresoc.v:149441$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:139634$7250_Y - connect \Y $pos$libresoc.v:139634$7251_Y + connect \A $extend$libresoc.v:149441$7572_Y + connect \Y $pos$libresoc.v:149441$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:139625$7239 + cell $sub $sub$libresoc.v:149432$7561 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -294193,10 +313024,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:139625$7239_Y + connect \Y $sub$libresoc.v:149432$7561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:139626$7240 + cell $sub $sub$libresoc.v:149433$7562 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -294204,10 +313035,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:139626$7240_Y + connect \Y $sub$libresoc.v:149433$7562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:139627$7241 + cell $sub $sub$libresoc.v:149434$7563 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -294215,59 +313046,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:139627$7241_Y + connect \Y $sub$libresoc.v:149434$7563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:139628$7242 + cell $mux $ternary$libresoc.v:149435$7564 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:139628$7242_Y + connect \Y $ternary$libresoc.v:149435$7564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:139629$7243 + cell $mux $ternary$libresoc.v:149436$7565 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:139629$7243_Y + connect \Y $ternary$libresoc.v:149436$7565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:139630$7244 + cell $mux $ternary$libresoc.v:149437$7566 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:139630$7244_Y + connect \Y $ternary$libresoc.v:149437$7566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:139632$7247 + cell $mux $ternary$libresoc.v:149439$7569 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:139632$7247_Y + connect \Y $ternary$libresoc.v:149439$7569_Y end - attribute \src "libresoc.v:139360.7-139360.20" - process $proc$libresoc.v:139360$7270 + attribute \src "libresoc.v:149161.7-149161.20" + process $proc$libresoc.v:149161$7592 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139635.3-139669.6" - process $proc$libresoc.v:139635$7252 + attribute \src "libresoc.v:149442.3-149476.6" + process $proc$libresoc.v:149442$7574 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$7253 $1\cr_a$6[3:0]$7254 - attribute \src "libresoc.v:139636.5-139636.29" + assign $0\cr_a$6[3:0]$7575 $1\cr_a$6[3:0]$7576 + attribute \src "libresoc.v:149443.5-149443.29" switch \initial - attribute \src "libresoc.v:139636.9-139636.17" + attribute \src "libresoc.v:149443.9-149443.17" case 1'1 case end @@ -294277,52 +313108,52 @@ module \main$9 case 7'0101010 assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7254 \$7 [3:0] + assign $1\cr_a$6[3:0]$7576 \$7 [3:0] assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7254 $2\cr_a$6[3:0]$7255 + assign $1\cr_a$6[3:0]$7576 $2\cr_a$6[3:0]$7577 assign $1\cr_a_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $2\cr_a$6[3:0]$7255 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$7255 [0] \bit_o + assign $2\cr_a$6[3:0]$7577 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7577 [0] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'01 - assign { $2\cr_a$6[3:0]$7255 [3:2] $2\cr_a$6[3:0]$7255 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$7255 [1] \bit_o + assign { $2\cr_a$6[3:0]$7577 [3:2] $2\cr_a$6[3:0]$7577 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7577 [1] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'10 - assign { $2\cr_a$6[3:0]$7255 [3] $2\cr_a$6[3:0]$7255 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$7255 [2] \bit_o + assign { $2\cr_a$6[3:0]$7577 [3] $2\cr_a$6[3:0]$7577 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7577 [2] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'-- - assign $2\cr_a$6[3:0]$7255 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$7255 [3] \bit_o + assign $2\cr_a$6[3:0]$7577 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7577 [3] \bit_o case - assign $2\cr_a$6[3:0]$7255 \cr_c + assign $2\cr_a$6[3:0]$7577 \cr_c end case assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$7254 4'0000 + assign $1\cr_a$6[3:0]$7576 4'0000 end sync always update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$7253 + update \cr_a$6 $0\cr_a$6[3:0]$7575 end - attribute \src "libresoc.v:139670.3-139680.6" - process $proc$libresoc.v:139670$7256 + attribute \src "libresoc.v:149477.3-149487.6" + process $proc$libresoc.v:149477$7578 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:139671.5-139671.29" + attribute \src "libresoc.v:149478.5-149478.29" switch \initial - attribute \src "libresoc.v:139671.9-139671.17" + attribute \src "libresoc.v:149478.9-149478.17" case 1'1 case end @@ -294338,17 +313169,17 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:139681.3-139722.6" - process $proc$libresoc.v:139681$7257 + attribute \src "libresoc.v:149488.3-149529.6" + process $proc$libresoc.v:149488$7579 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:139682.5-139682.29" + attribute \src "libresoc.v:149489.5-149489.29" switch \initial - attribute \src "libresoc.v:139682.9-139682.17" + attribute \src "libresoc.v:149489.9-149489.17" case 1'1 case end @@ -294395,14 +313226,14 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:139723.3-139733.6" - process $proc$libresoc.v:139723$7258 + attribute \src "libresoc.v:149530.3-149540.6" + process $proc$libresoc.v:149530$7580 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:139724.5-139724.29" + attribute \src "libresoc.v:149531.5-149531.29" switch \initial - attribute \src "libresoc.v:139724.9-139724.17" + attribute \src "libresoc.v:149531.9-149531.17" case 1'1 case end @@ -294418,14 +313249,14 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:139734.3-139754.6" - process $proc$libresoc.v:139734$7259 + attribute \src "libresoc.v:149541.3-149561.6" + process $proc$libresoc.v:149541$7581 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:139735.5-139735.29" + attribute \src "libresoc.v:149542.5-149542.29" switch \initial - attribute \src "libresoc.v:139735.9-139735.17" + attribute \src "libresoc.v:149542.9-149542.17" case 1'1 case end @@ -294462,14 +313293,14 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:139755.3-139765.6" - process $proc$libresoc.v:139755$7260 + attribute \src "libresoc.v:149562.3-149572.6" + process $proc$libresoc.v:149562$7582 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:139756.5-139756.29" + attribute \src "libresoc.v:149563.5-149563.29" switch \initial - attribute \src "libresoc.v:139756.9-139756.17" + attribute \src "libresoc.v:149563.9-149563.17" case 1'1 case end @@ -294485,14 +313316,14 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:139766.3-139776.6" - process $proc$libresoc.v:139766$7261 + attribute \src "libresoc.v:149573.3-149583.6" + process $proc$libresoc.v:149573$7583 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:139767.5-139767.29" + attribute \src "libresoc.v:149574.5-149574.29" switch \initial - attribute \src "libresoc.v:139767.9-139767.17" + attribute \src "libresoc.v:149574.9-149574.17" case 1'1 case end @@ -294508,14 +313339,14 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:139777.3-139787.6" - process $proc$libresoc.v:139777$7262 + attribute \src "libresoc.v:149584.3-149594.6" + process $proc$libresoc.v:149584$7584 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:139778.5-139778.29" + attribute \src "libresoc.v:149585.5-149585.29" switch \initial - attribute \src "libresoc.v:139778.9-139778.17" + attribute \src "libresoc.v:149585.9-149585.17" case 1'1 case end @@ -294531,14 +313362,14 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:139788.3-139798.6" - process $proc$libresoc.v:139788$7263 + attribute \src "libresoc.v:149595.3-149605.6" + process $proc$libresoc.v:149595$7585 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:139789.5-139789.29" + attribute \src "libresoc.v:149596.5-149596.29" switch \initial - attribute \src "libresoc.v:139789.9-139789.17" + attribute \src "libresoc.v:149596.9-149596.17" case 1'1 case end @@ -294554,14 +313385,14 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:139799.3-139819.6" - process $proc$libresoc.v:139799$7264 + attribute \src "libresoc.v:149606.3-149626.6" + process $proc$libresoc.v:149606$7586 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:139800.5-139800.29" + attribute \src "libresoc.v:149607.5-149607.29" switch \initial - attribute \src "libresoc.v:139800.9-139800.17" + attribute \src "libresoc.v:149607.9-149607.17" case 1'1 case end @@ -294598,14 +313429,14 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:139820.3-139840.6" - process $proc$libresoc.v:139820$7265 + attribute \src "libresoc.v:149627.3-149647.6" + process $proc$libresoc.v:149627$7587 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:139821.5-139821.29" + attribute \src "libresoc.v:149628.5-149628.29" switch \initial - attribute \src "libresoc.v:139821.9-139821.17" + attribute \src "libresoc.v:149628.9-149628.17" case 1'1 case end @@ -294642,14 +313473,14 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:139841.3-139851.6" - process $proc$libresoc.v:139841$7266 + attribute \src "libresoc.v:149648.3-149658.6" + process $proc$libresoc.v:149648$7588 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:139842.5-139842.29" + attribute \src "libresoc.v:149649.5-149649.29" switch \initial - attribute \src "libresoc.v:139842.9-139842.17" + attribute \src "libresoc.v:149649.9-149649.17" case 1'1 case end @@ -294665,14 +313496,14 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:139852.3-139862.6" - process $proc$libresoc.v:139852$7267 + attribute \src "libresoc.v:149659.3-149669.6" + process $proc$libresoc.v:149659$7589 assign { } { } assign { } { } - assign $0\full_cr$5[31:0]$7268 $1\full_cr$5[31:0]$7269 - attribute \src "libresoc.v:139853.5-139853.29" + assign $0\full_cr$5[31:0]$7590 $1\full_cr$5[31:0]$7591 + attribute \src "libresoc.v:149660.5-149660.29" switch \initial - attribute \src "libresoc.v:139853.9-139853.17" + attribute \src "libresoc.v:149660.9-149660.17" case 1'1 case end @@ -294681,508 +313512,508 @@ module \main$9 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } - assign $1\full_cr$5[31:0]$7269 \ra [31:0] + assign $1\full_cr$5[31:0]$7591 \ra [31:0] case - assign $1\full_cr$5[31:0]$7269 0 + assign $1\full_cr$5[31:0]$7591 0 end sync always - update \full_cr$5 $0\full_cr$5[31:0]$7268 + update \full_cr$5 $0\full_cr$5[31:0]$7590 end - connect \$10 $sub$libresoc.v:139625$7239_Y - connect \$13 $sub$libresoc.v:139626$7240_Y - connect \$16 $sub$libresoc.v:139627$7241_Y - connect \$18 $ternary$libresoc.v:139628$7242_Y - connect \$20 $ternary$libresoc.v:139629$7243_Y - connect \$22 $ternary$libresoc.v:139630$7244_Y - connect \$24 $pos$libresoc.v:139631$7246_Y - connect \$27 $ternary$libresoc.v:139632$7247_Y - connect \$26 $pos$libresoc.v:139633$7249_Y - connect \$7 $pos$libresoc.v:139634$7251_Y + connect \$10 $sub$libresoc.v:149432$7561_Y + connect \$13 $sub$libresoc.v:149433$7562_Y + connect \$16 $sub$libresoc.v:149434$7563_Y + connect \$18 $ternary$libresoc.v:149435$7564_Y + connect \$20 $ternary$libresoc.v:149436$7565_Y + connect \$22 $ternary$libresoc.v:149437$7566_Y + connect \$24 $pos$libresoc.v:149438$7568_Y + connect \$27 $ternary$libresoc.v:149439$7569_Y + connect \$26 $pos$libresoc.v:149440$7571_Y + connect \$7 $pos$libresoc.v:149441$7573_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:139872.1-141027.10" +attribute \src "libresoc.v:149679.1-150840.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:140598.3-140599.25" + attribute \src "libresoc.v:150411.3-150412.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:140596.3-140597.40" + attribute \src "libresoc.v:150409.3-150410.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:140939.3-140947.6" - wire $0\alu_l_r_alu$next[0:0]$7476 - attribute \src "libresoc.v:140524.3-140525.39" + attribute \src "libresoc.v:150752.3-150760.6" + wire $0\alu_l_r_alu$next[0:0]$7798 + attribute \src "libresoc.v:150337.3-150338.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 12 $0\alu_mul0_mul_op__fn_unit$next[11:0]$7401 - attribute \src "libresoc.v:140552.3-140553.65" - wire width 12 $0\alu_mul0_mul_op__fn_unit[11:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7402 - attribute \src "libresoc.v:140554.3-140555.79" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 + attribute \src "libresoc.v:150365.3-150366.65" + wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] + attribute \src "libresoc.v:150592.3-150624.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 + attribute \src "libresoc.v:150367.3-150368.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7403 - attribute \src "libresoc.v:140556.3-140557.75" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 + attribute \src "libresoc.v:150369.3-150370.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7404 - attribute \src "libresoc.v:140572.3-140573.59" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7726 + attribute \src "libresoc.v:150385.3-150386.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7405 - attribute \src "libresoc.v:140550.3-140551.69" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 + attribute \src "libresoc.v:150363.3-150364.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7406 - attribute \src "libresoc.v:140568.3-140569.67" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 + attribute \src "libresoc.v:150381.3-150382.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7407 - attribute \src "libresoc.v:140570.3-140571.69" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 + attribute \src "libresoc.v:150383.3-150384.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7408 - attribute \src "libresoc.v:140562.3-140563.63" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 + attribute \src "libresoc.v:150375.3-150376.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7409 - attribute \src "libresoc.v:140564.3-140565.63" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 + attribute \src "libresoc.v:150377.3-150378.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7410 - attribute \src "libresoc.v:140560.3-140561.63" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 + attribute \src "libresoc.v:150373.3-150374.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7411 - attribute \src "libresoc.v:140558.3-140559.63" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 + attribute \src "libresoc.v:150371.3-150372.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7412 - attribute \src "libresoc.v:140566.3-140567.69" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 + attribute \src "libresoc.v:150379.3-150380.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:140930.3-140938.6" - wire $0\alui_l_r_alui$next[0:0]$7473 - attribute \src "libresoc.v:140526.3-140527.43" + attribute \src "libresoc.v:150743.3-150751.6" + wire $0\alui_l_r_alui$next[0:0]$7795 + attribute \src "libresoc.v:150339.3-150340.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:140812.3-140833.6" - wire width 64 $0\data_r0__o$next[63:0]$7432 - attribute \src "libresoc.v:140546.3-140547.37" + attribute \src "libresoc.v:150625.3-150646.6" + wire width 64 $0\data_r0__o$next[63:0]$7754 + attribute \src "libresoc.v:150359.3-150360.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:140812.3-140833.6" - wire $0\data_r0__o_ok$next[0:0]$7433 - attribute \src "libresoc.v:140548.3-140549.43" + attribute \src "libresoc.v:150625.3-150646.6" + wire $0\data_r0__o_ok$next[0:0]$7755 + attribute \src "libresoc.v:150361.3-150362.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:140834.3-140855.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7440 - attribute \src "libresoc.v:140542.3-140543.43" + attribute \src "libresoc.v:150647.3-150668.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7762 + attribute \src "libresoc.v:150355.3-150356.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:140834.3-140855.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7441 - attribute \src "libresoc.v:140544.3-140545.49" + attribute \src "libresoc.v:150647.3-150668.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7763 + attribute \src "libresoc.v:150357.3-150358.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:140856.3-140877.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7448 - attribute \src "libresoc.v:140538.3-140539.47" + attribute \src "libresoc.v:150669.3-150690.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7770 + attribute \src "libresoc.v:150351.3-150352.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:140856.3-140877.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7449 - attribute \src "libresoc.v:140540.3-140541.53" + attribute \src "libresoc.v:150669.3-150690.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7771 + attribute \src "libresoc.v:150353.3-150354.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:140878.3-140899.6" - wire $0\data_r3__xer_so$next[0:0]$7456 - attribute \src "libresoc.v:140534.3-140535.47" + attribute \src "libresoc.v:150691.3-150712.6" + wire $0\data_r3__xer_so$next[0:0]$7778 + attribute \src "libresoc.v:150347.3-150348.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:140878.3-140899.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7457 - attribute \src "libresoc.v:140536.3-140537.53" + attribute \src "libresoc.v:150691.3-150712.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7779 + attribute \src "libresoc.v:150349.3-150350.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:140948.3-140957.6" + attribute \src "libresoc.v:150761.3-150770.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:140958.3-140967.6" + attribute \src "libresoc.v:150771.3-150780.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:140968.3-140977.6" + attribute \src "libresoc.v:150781.3-150790.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:140978.3-140987.6" + attribute \src "libresoc.v:150791.3-150800.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:139873.7-139873.20" + attribute \src "libresoc.v:149680.7-149680.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140734.3-140742.6" - wire $0\opc_l_r_opc$next[0:0]$7386 - attribute \src "libresoc.v:140582.3-140583.39" + attribute \src "libresoc.v:150547.3-150555.6" + wire $0\opc_l_r_opc$next[0:0]$7708 + attribute \src "libresoc.v:150395.3-150396.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140725.3-140733.6" - wire $0\opc_l_s_opc$next[0:0]$7383 - attribute \src "libresoc.v:140584.3-140585.39" + attribute \src "libresoc.v:150538.3-150546.6" + wire $0\opc_l_s_opc$next[0:0]$7705 + attribute \src "libresoc.v:150397.3-150398.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:140988.3-140996.6" - wire width 4 $0\prev_wr_go$next[3:0]$7483 - attribute \src "libresoc.v:140594.3-140595.37" + attribute \src "libresoc.v:150801.3-150809.6" + wire width 4 $0\prev_wr_go$next[3:0]$7805 + attribute \src "libresoc.v:150407.3-150408.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:140679.3-140688.6" + attribute \src "libresoc.v:150492.3-150501.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:140770.3-140778.6" - wire width 4 $0\req_l_r_req$next[3:0]$7398 - attribute \src "libresoc.v:140574.3-140575.39" + attribute \src "libresoc.v:150583.3-150591.6" + wire width 4 $0\req_l_r_req$next[3:0]$7720 + attribute \src "libresoc.v:150387.3-150388.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:140761.3-140769.6" - wire width 4 $0\req_l_s_req$next[3:0]$7395 - attribute \src "libresoc.v:140576.3-140577.39" + attribute \src "libresoc.v:150574.3-150582.6" + wire width 4 $0\req_l_s_req$next[3:0]$7717 + attribute \src "libresoc.v:150389.3-150390.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:140698.3-140706.6" - wire $0\rok_l_r_rdok$next[0:0]$7374 - attribute \src "libresoc.v:140590.3-140591.41" + attribute \src "libresoc.v:150511.3-150519.6" + wire $0\rok_l_r_rdok$next[0:0]$7696 + attribute \src "libresoc.v:150403.3-150404.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:140689.3-140697.6" - wire $0\rok_l_s_rdok$next[0:0]$7371 - attribute \src "libresoc.v:140592.3-140593.41" + attribute \src "libresoc.v:150502.3-150510.6" + wire $0\rok_l_s_rdok$next[0:0]$7693 + attribute \src "libresoc.v:150405.3-150406.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:140716.3-140724.6" - wire $0\rst_l_r_rst$next[0:0]$7380 - attribute \src "libresoc.v:140586.3-140587.39" + attribute \src "libresoc.v:150529.3-150537.6" + wire $0\rst_l_r_rst$next[0:0]$7702 + attribute \src "libresoc.v:150399.3-150400.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:140707.3-140715.6" - wire $0\rst_l_s_rst$next[0:0]$7377 - attribute \src "libresoc.v:140588.3-140589.39" + attribute \src "libresoc.v:150520.3-150528.6" + wire $0\rst_l_s_rst$next[0:0]$7699 + attribute \src "libresoc.v:150401.3-150402.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:140752.3-140760.6" - wire width 3 $0\src_l_r_src$next[2:0]$7392 - attribute \src "libresoc.v:140578.3-140579.39" + attribute \src "libresoc.v:150565.3-150573.6" + wire width 3 $0\src_l_r_src$next[2:0]$7714 + attribute \src "libresoc.v:150391.3-150392.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:140743.3-140751.6" - wire width 3 $0\src_l_s_src$next[2:0]$7389 - attribute \src "libresoc.v:140580.3-140581.39" + attribute \src "libresoc.v:150556.3-150564.6" + wire width 3 $0\src_l_s_src$next[2:0]$7711 + attribute \src "libresoc.v:150393.3-150394.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:140900.3-140909.6" - wire width 64 $0\src_r0$next[63:0]$7464 - attribute \src "libresoc.v:140532.3-140533.29" + attribute \src "libresoc.v:150713.3-150722.6" + wire width 64 $0\src_r0$next[63:0]$7786 + attribute \src "libresoc.v:150345.3-150346.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:140910.3-140919.6" - wire width 64 $0\src_r1$next[63:0]$7467 - attribute \src "libresoc.v:140530.3-140531.29" + attribute \src "libresoc.v:150723.3-150732.6" + wire width 64 $0\src_r1$next[63:0]$7789 + attribute \src "libresoc.v:150343.3-150344.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:140920.3-140929.6" - wire $0\src_r2$next[0:0]$7470 - attribute \src "libresoc.v:140528.3-140529.29" + attribute \src "libresoc.v:150733.3-150742.6" + wire $0\src_r2$next[0:0]$7792 + attribute \src "libresoc.v:150341.3-150342.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:139997.7-139997.24" + attribute \src "libresoc.v:149804.7-149804.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:140007.7-140007.26" + attribute \src "libresoc.v:149814.7-149814.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:140939.3-140947.6" - wire $1\alu_l_r_alu$next[0:0]$7477 - attribute \src "libresoc.v:140015.7-140015.25" + attribute \src "libresoc.v:150752.3-150760.6" + wire $1\alu_l_r_alu$next[0:0]$7799 + attribute \src "libresoc.v:149822.7-149822.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 12 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7413 - attribute \src "libresoc.v:140036.14-140036.48" - wire width 12 $1\alu_mul0_mul_op__fn_unit[11:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7414 - attribute \src "libresoc.v:140040.14-140040.68" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 + attribute \src "libresoc.v:149845.14-149845.49" + wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] + attribute \src "libresoc.v:150592.3-150624.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 + attribute \src "libresoc.v:149849.14-149849.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7415 - attribute \src "libresoc.v:140044.7-140044.43" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 + attribute \src "libresoc.v:149853.7-149853.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7416 - attribute \src "libresoc.v:140048.14-140048.43" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7738 + attribute \src "libresoc.v:149857.14-149857.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7417 - attribute \src "libresoc.v:140126.13-140126.47" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 + attribute \src "libresoc.v:149936.13-149936.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7418 - attribute \src "libresoc.v:140130.7-140130.39" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 + attribute \src "libresoc.v:149940.7-149940.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7419 - attribute \src "libresoc.v:140134.7-140134.40" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 + attribute \src "libresoc.v:149944.7-149944.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7420 - attribute \src "libresoc.v:140138.7-140138.37" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 + attribute \src "libresoc.v:149948.7-149948.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7421 - attribute \src "libresoc.v:140142.7-140142.37" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 + attribute \src "libresoc.v:149952.7-149952.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7422 - attribute \src "libresoc.v:140146.7-140146.37" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 + attribute \src "libresoc.v:149956.7-149956.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7423 - attribute \src "libresoc.v:140150.7-140150.37" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 + attribute \src "libresoc.v:149960.7-149960.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7424 - attribute \src "libresoc.v:140154.7-140154.40" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 + attribute \src "libresoc.v:149964.7-149964.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:140930.3-140938.6" - wire $1\alui_l_r_alui$next[0:0]$7474 - attribute \src "libresoc.v:140184.7-140184.27" + attribute \src "libresoc.v:150743.3-150751.6" + wire $1\alui_l_r_alui$next[0:0]$7796 + attribute \src "libresoc.v:149994.7-149994.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:140812.3-140833.6" - wire width 64 $1\data_r0__o$next[63:0]$7434 - attribute \src "libresoc.v:140218.14-140218.47" + attribute \src "libresoc.v:150625.3-150646.6" + wire width 64 $1\data_r0__o$next[63:0]$7756 + attribute \src "libresoc.v:150028.14-150028.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:140812.3-140833.6" - wire $1\data_r0__o_ok$next[0:0]$7435 - attribute \src "libresoc.v:140222.7-140222.27" + attribute \src "libresoc.v:150625.3-150646.6" + wire $1\data_r0__o_ok$next[0:0]$7757 + attribute \src "libresoc.v:150032.7-150032.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:140834.3-140855.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$7442 - attribute \src "libresoc.v:140226.13-140226.33" + attribute \src "libresoc.v:150647.3-150668.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7764 + attribute \src "libresoc.v:150036.13-150036.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:140834.3-140855.6" - wire $1\data_r1__cr_a_ok$next[0:0]$7443 - attribute \src "libresoc.v:140230.7-140230.30" + attribute \src "libresoc.v:150647.3-150668.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7765 + attribute \src "libresoc.v:150040.7-150040.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:140856.3-140877.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$7450 - attribute \src "libresoc.v:140234.13-140234.35" + attribute \src "libresoc.v:150669.3-150690.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7772 + attribute \src "libresoc.v:150044.13-150044.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:140856.3-140877.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$7451 - attribute \src "libresoc.v:140238.7-140238.32" + attribute \src "libresoc.v:150669.3-150690.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7773 + attribute \src "libresoc.v:150048.7-150048.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:140878.3-140899.6" - wire $1\data_r3__xer_so$next[0:0]$7458 - attribute \src "libresoc.v:140242.7-140242.29" + attribute \src "libresoc.v:150691.3-150712.6" + wire $1\data_r3__xer_so$next[0:0]$7780 + attribute \src "libresoc.v:150052.7-150052.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:140878.3-140899.6" - wire $1\data_r3__xer_so_ok$next[0:0]$7459 - attribute \src "libresoc.v:140246.7-140246.32" + attribute \src "libresoc.v:150691.3-150712.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7781 + attribute \src "libresoc.v:150056.7-150056.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:140948.3-140957.6" + attribute \src "libresoc.v:150761.3-150770.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:140958.3-140967.6" + attribute \src "libresoc.v:150771.3-150780.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:140968.3-140977.6" + attribute \src "libresoc.v:150781.3-150790.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:140978.3-140987.6" + attribute \src "libresoc.v:150791.3-150800.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:140734.3-140742.6" - wire $1\opc_l_r_opc$next[0:0]$7387 - attribute \src "libresoc.v:140266.7-140266.25" + attribute \src "libresoc.v:150547.3-150555.6" + wire $1\opc_l_r_opc$next[0:0]$7709 + attribute \src "libresoc.v:150076.7-150076.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140725.3-140733.6" - wire $1\opc_l_s_opc$next[0:0]$7384 - attribute \src "libresoc.v:140270.7-140270.25" + attribute \src "libresoc.v:150538.3-150546.6" + wire $1\opc_l_s_opc$next[0:0]$7706 + attribute \src "libresoc.v:150080.7-150080.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:140988.3-140996.6" - wire width 4 $1\prev_wr_go$next[3:0]$7484 - attribute \src "libresoc.v:140385.13-140385.30" + attribute \src "libresoc.v:150801.3-150809.6" + wire width 4 $1\prev_wr_go$next[3:0]$7806 + attribute \src "libresoc.v:150198.13-150198.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:140679.3-140688.6" + attribute \src "libresoc.v:150492.3-150501.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:140770.3-140778.6" - wire width 4 $1\req_l_r_req$next[3:0]$7399 - attribute \src "libresoc.v:140393.13-140393.31" + attribute \src "libresoc.v:150583.3-150591.6" + wire width 4 $1\req_l_r_req$next[3:0]$7721 + attribute \src "libresoc.v:150206.13-150206.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:140761.3-140769.6" - wire width 4 $1\req_l_s_req$next[3:0]$7396 - attribute \src "libresoc.v:140397.13-140397.31" + attribute \src "libresoc.v:150574.3-150582.6" + wire width 4 $1\req_l_s_req$next[3:0]$7718 + attribute \src "libresoc.v:150210.13-150210.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:140698.3-140706.6" - wire $1\rok_l_r_rdok$next[0:0]$7375 - attribute \src "libresoc.v:140409.7-140409.26" + attribute \src "libresoc.v:150511.3-150519.6" + wire $1\rok_l_r_rdok$next[0:0]$7697 + attribute \src "libresoc.v:150222.7-150222.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:140689.3-140697.6" - wire $1\rok_l_s_rdok$next[0:0]$7372 - attribute \src "libresoc.v:140413.7-140413.26" + attribute \src "libresoc.v:150502.3-150510.6" + wire $1\rok_l_s_rdok$next[0:0]$7694 + attribute \src "libresoc.v:150226.7-150226.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:140716.3-140724.6" - wire $1\rst_l_r_rst$next[0:0]$7381 - attribute \src "libresoc.v:140417.7-140417.25" + attribute \src "libresoc.v:150529.3-150537.6" + wire $1\rst_l_r_rst$next[0:0]$7703 + attribute \src "libresoc.v:150230.7-150230.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:140707.3-140715.6" - wire $1\rst_l_s_rst$next[0:0]$7378 - attribute \src "libresoc.v:140421.7-140421.25" + attribute \src "libresoc.v:150520.3-150528.6" + wire $1\rst_l_s_rst$next[0:0]$7700 + attribute \src "libresoc.v:150234.7-150234.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:140752.3-140760.6" - wire width 3 $1\src_l_r_src$next[2:0]$7393 - attribute \src "libresoc.v:140435.13-140435.31" + attribute \src "libresoc.v:150565.3-150573.6" + wire width 3 $1\src_l_r_src$next[2:0]$7715 + attribute \src "libresoc.v:150248.13-150248.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:140743.3-140751.6" - wire width 3 $1\src_l_s_src$next[2:0]$7390 - attribute \src "libresoc.v:140439.13-140439.31" + attribute \src "libresoc.v:150556.3-150564.6" + wire width 3 $1\src_l_s_src$next[2:0]$7712 + attribute \src "libresoc.v:150252.13-150252.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:140900.3-140909.6" - wire width 64 $1\src_r0$next[63:0]$7465 - attribute \src "libresoc.v:140445.14-140445.43" + attribute \src "libresoc.v:150713.3-150722.6" + wire width 64 $1\src_r0$next[63:0]$7787 + attribute \src "libresoc.v:150258.14-150258.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:140910.3-140919.6" - wire width 64 $1\src_r1$next[63:0]$7468 - attribute \src "libresoc.v:140449.14-140449.43" + attribute \src "libresoc.v:150723.3-150732.6" + wire width 64 $1\src_r1$next[63:0]$7790 + attribute \src "libresoc.v:150262.14-150262.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:140920.3-140929.6" - wire $1\src_r2$next[0:0]$7471 - attribute \src "libresoc.v:140453.7-140453.20" + attribute \src "libresoc.v:150733.3-150742.6" + wire $1\src_r2$next[0:0]$7793 + attribute \src "libresoc.v:150266.7-150266.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:140779.3-140811.6" - wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7425 - attribute \src "libresoc.v:140779.3-140811.6" - wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7426 - attribute \src "libresoc.v:140779.3-140811.6" - wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7427 - attribute \src "libresoc.v:140779.3-140811.6" - wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7428 - attribute \src "libresoc.v:140779.3-140811.6" - wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7429 - attribute \src "libresoc.v:140779.3-140811.6" - wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7430 - attribute \src "libresoc.v:140812.3-140833.6" - wire width 64 $2\data_r0__o$next[63:0]$7436 - attribute \src "libresoc.v:140812.3-140833.6" - wire $2\data_r0__o_ok$next[0:0]$7437 - attribute \src "libresoc.v:140834.3-140855.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$7444 - attribute \src "libresoc.v:140834.3-140855.6" - wire $2\data_r1__cr_a_ok$next[0:0]$7445 - attribute \src "libresoc.v:140856.3-140877.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$7452 - attribute \src "libresoc.v:140856.3-140877.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$7453 - attribute \src "libresoc.v:140878.3-140899.6" - wire $2\data_r3__xer_so$next[0:0]$7460 - attribute \src "libresoc.v:140878.3-140899.6" - wire $2\data_r3__xer_so_ok$next[0:0]$7461 - attribute \src "libresoc.v:140812.3-140833.6" - wire $3\data_r0__o_ok$next[0:0]$7438 - attribute \src "libresoc.v:140834.3-140855.6" - wire $3\data_r1__cr_a_ok$next[0:0]$7446 - attribute \src "libresoc.v:140856.3-140877.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$7454 - attribute \src "libresoc.v:140878.3-140899.6" - wire $3\data_r3__xer_so_ok$next[0:0]$7462 - attribute \src "libresoc.v:140464.19-140464.113" - wire width 3 $and$libresoc.v:140464$7271_Y - attribute \src "libresoc.v:140465.19-140465.125" - wire $and$libresoc.v:140465$7272_Y - attribute \src "libresoc.v:140466.19-140466.125" - wire $and$libresoc.v:140466$7273_Y - attribute \src "libresoc.v:140467.19-140467.125" - wire $and$libresoc.v:140467$7274_Y - attribute \src "libresoc.v:140468.19-140468.125" - wire $and$libresoc.v:140468$7275_Y - attribute \src "libresoc.v:140469.18-140469.110" - wire $and$libresoc.v:140469$7276_Y - attribute \src "libresoc.v:140470.19-140470.149" - wire width 4 $and$libresoc.v:140470$7277_Y - attribute \src "libresoc.v:140471.19-140471.121" - wire width 4 $and$libresoc.v:140471$7278_Y - attribute \src "libresoc.v:140472.19-140472.127" - wire $and$libresoc.v:140472$7279_Y - attribute \src "libresoc.v:140473.19-140473.127" - wire $and$libresoc.v:140473$7280_Y - attribute \src "libresoc.v:140474.19-140474.127" - wire $and$libresoc.v:140474$7281_Y - attribute \src "libresoc.v:140475.19-140475.127" - wire $and$libresoc.v:140475$7282_Y - attribute \src "libresoc.v:140477.18-140477.98" - wire $and$libresoc.v:140477$7284_Y - attribute \src "libresoc.v:140479.18-140479.100" - wire $and$libresoc.v:140479$7286_Y - attribute \src "libresoc.v:140480.18-140480.160" - wire width 4 $and$libresoc.v:140480$7287_Y - attribute \src "libresoc.v:140482.18-140482.119" - wire width 4 $and$libresoc.v:140482$7289_Y - attribute \src "libresoc.v:140485.17-140485.123" - wire $and$libresoc.v:140485$7292_Y - attribute \src "libresoc.v:140486.18-140486.116" - wire $and$libresoc.v:140486$7293_Y - attribute \src "libresoc.v:140491.18-140491.113" - wire $and$libresoc.v:140491$7298_Y - attribute \src "libresoc.v:140492.18-140492.125" - wire width 4 $and$libresoc.v:140492$7299_Y - attribute \src "libresoc.v:140494.18-140494.112" - wire $and$libresoc.v:140494$7301_Y - attribute \src "libresoc.v:140496.18-140496.126" - wire $and$libresoc.v:140496$7303_Y - attribute \src "libresoc.v:140497.18-140497.126" - wire $and$libresoc.v:140497$7304_Y - attribute \src "libresoc.v:140498.18-140498.117" - wire $and$libresoc.v:140498$7305_Y - attribute \src "libresoc.v:140504.18-140504.130" - wire $and$libresoc.v:140504$7311_Y - attribute \src "libresoc.v:140505.18-140505.124" - wire width 4 $and$libresoc.v:140505$7312_Y - attribute \src "libresoc.v:140507.18-140507.116" - wire $and$libresoc.v:140507$7314_Y - attribute \src "libresoc.v:140508.18-140508.119" - wire $and$libresoc.v:140508$7315_Y - attribute \src "libresoc.v:140509.18-140509.121" - wire $and$libresoc.v:140509$7316_Y - attribute \src "libresoc.v:140510.18-140510.121" - wire $and$libresoc.v:140510$7317_Y - attribute \src "libresoc.v:140517.18-140517.134" - wire $and$libresoc.v:140517$7324_Y - attribute \src "libresoc.v:140519.18-140519.132" - wire $and$libresoc.v:140519$7326_Y - attribute \src "libresoc.v:140520.18-140520.149" - wire width 3 $and$libresoc.v:140520$7327_Y - attribute \src "libresoc.v:140522.18-140522.129" - wire width 3 $and$libresoc.v:140522$7329_Y - attribute \src "libresoc.v:140493.18-140493.113" - wire $eq$libresoc.v:140493$7300_Y - attribute \src "libresoc.v:140495.18-140495.119" - wire $eq$libresoc.v:140495$7302_Y - attribute \src "libresoc.v:140476.18-140476.97" - wire $not$libresoc.v:140476$7283_Y - attribute \src "libresoc.v:140478.18-140478.99" - wire $not$libresoc.v:140478$7285_Y - attribute \src "libresoc.v:140481.18-140481.113" - wire width 4 $not$libresoc.v:140481$7288_Y - attribute \src "libresoc.v:140484.18-140484.106" - wire $not$libresoc.v:140484$7291_Y - attribute \src "libresoc.v:140490.18-140490.120" - wire $not$libresoc.v:140490$7297_Y - attribute \src "libresoc.v:140501.17-140501.113" - wire width 3 $not$libresoc.v:140501$7308_Y - attribute \src "libresoc.v:140521.18-140521.131" - wire $not$libresoc.v:140521$7328_Y - attribute \src "libresoc.v:140523.18-140523.114" - wire width 3 $not$libresoc.v:140523$7330_Y - attribute \src "libresoc.v:140489.18-140489.112" - wire $or$libresoc.v:140489$7296_Y - attribute \src "libresoc.v:140499.18-140499.122" - wire $or$libresoc.v:140499$7306_Y - attribute \src "libresoc.v:140500.18-140500.124" - wire $or$libresoc.v:140500$7307_Y - attribute \src "libresoc.v:140502.18-140502.168" - wire width 4 $or$libresoc.v:140502$7309_Y - attribute \src "libresoc.v:140503.18-140503.155" - wire width 3 $or$libresoc.v:140503$7310_Y - attribute \src "libresoc.v:140506.18-140506.120" - wire width 4 $or$libresoc.v:140506$7313_Y - attribute \src "libresoc.v:140512.17-140512.117" - wire width 3 $or$libresoc.v:140512$7319_Y - attribute \src "libresoc.v:140518.17-140518.104" - wire $reduce_and$libresoc.v:140518$7325_Y - attribute \src "libresoc.v:140483.18-140483.106" - wire $reduce_or$libresoc.v:140483$7290_Y - attribute \src "libresoc.v:140487.18-140487.113" - wire $reduce_or$libresoc.v:140487$7294_Y - attribute \src "libresoc.v:140488.18-140488.112" - wire $reduce_or$libresoc.v:140488$7295_Y - attribute \src "libresoc.v:140511.18-140511.160" - wire $ternary$libresoc.v:140511$7318_Y - attribute \src "libresoc.v:140513.18-140513.172" - wire width 64 $ternary$libresoc.v:140513$7320_Y - attribute \src "libresoc.v:140514.18-140514.118" - wire width 64 $ternary$libresoc.v:140514$7321_Y - attribute \src "libresoc.v:140515.18-140515.115" - wire width 64 $ternary$libresoc.v:140515$7322_Y - attribute \src "libresoc.v:140516.18-140516.118" - wire $ternary$libresoc.v:140516$7323_Y + attribute \src "libresoc.v:150592.3-150624.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 + attribute \src "libresoc.v:150592.3-150624.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 + attribute \src "libresoc.v:150592.3-150624.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 + attribute \src "libresoc.v:150592.3-150624.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 + attribute \src "libresoc.v:150592.3-150624.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 + attribute \src "libresoc.v:150592.3-150624.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 + attribute \src "libresoc.v:150625.3-150646.6" + wire width 64 $2\data_r0__o$next[63:0]$7758 + attribute \src "libresoc.v:150625.3-150646.6" + wire $2\data_r0__o_ok$next[0:0]$7759 + attribute \src "libresoc.v:150647.3-150668.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$7766 + attribute \src "libresoc.v:150647.3-150668.6" + wire $2\data_r1__cr_a_ok$next[0:0]$7767 + attribute \src "libresoc.v:150669.3-150690.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$7774 + attribute \src "libresoc.v:150669.3-150690.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$7775 + attribute \src "libresoc.v:150691.3-150712.6" + wire $2\data_r3__xer_so$next[0:0]$7782 + attribute \src "libresoc.v:150691.3-150712.6" + wire $2\data_r3__xer_so_ok$next[0:0]$7783 + attribute \src "libresoc.v:150625.3-150646.6" + wire $3\data_r0__o_ok$next[0:0]$7760 + attribute \src "libresoc.v:150647.3-150668.6" + wire $3\data_r1__cr_a_ok$next[0:0]$7768 + attribute \src "libresoc.v:150669.3-150690.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$7776 + attribute \src "libresoc.v:150691.3-150712.6" + wire $3\data_r3__xer_so_ok$next[0:0]$7784 + attribute \src "libresoc.v:150277.19-150277.113" + wire width 3 $and$libresoc.v:150277$7593_Y + attribute \src "libresoc.v:150278.19-150278.125" + wire $and$libresoc.v:150278$7594_Y + attribute \src "libresoc.v:150279.19-150279.125" + wire $and$libresoc.v:150279$7595_Y + attribute \src "libresoc.v:150280.19-150280.125" + wire $and$libresoc.v:150280$7596_Y + attribute \src "libresoc.v:150281.19-150281.125" + wire $and$libresoc.v:150281$7597_Y + attribute \src "libresoc.v:150282.18-150282.110" + wire $and$libresoc.v:150282$7598_Y + attribute \src "libresoc.v:150283.19-150283.149" + wire width 4 $and$libresoc.v:150283$7599_Y + attribute \src "libresoc.v:150284.19-150284.121" + wire width 4 $and$libresoc.v:150284$7600_Y + attribute \src "libresoc.v:150285.19-150285.127" + wire $and$libresoc.v:150285$7601_Y + attribute \src "libresoc.v:150286.19-150286.127" + wire $and$libresoc.v:150286$7602_Y + attribute \src "libresoc.v:150287.19-150287.127" + wire $and$libresoc.v:150287$7603_Y + attribute \src "libresoc.v:150288.19-150288.127" + wire $and$libresoc.v:150288$7604_Y + attribute \src "libresoc.v:150290.18-150290.98" + wire $and$libresoc.v:150290$7606_Y + attribute \src "libresoc.v:150292.18-150292.100" + wire $and$libresoc.v:150292$7608_Y + attribute \src "libresoc.v:150293.18-150293.160" + wire width 4 $and$libresoc.v:150293$7609_Y + attribute \src "libresoc.v:150295.18-150295.119" + wire width 4 $and$libresoc.v:150295$7611_Y + attribute \src "libresoc.v:150298.17-150298.123" + wire $and$libresoc.v:150298$7614_Y + attribute \src "libresoc.v:150299.18-150299.116" + wire $and$libresoc.v:150299$7615_Y + attribute \src "libresoc.v:150304.18-150304.113" + wire $and$libresoc.v:150304$7620_Y + attribute \src "libresoc.v:150305.18-150305.125" + wire width 4 $and$libresoc.v:150305$7621_Y + attribute \src "libresoc.v:150307.18-150307.112" + wire $and$libresoc.v:150307$7623_Y + attribute \src "libresoc.v:150309.18-150309.126" + wire $and$libresoc.v:150309$7625_Y + attribute \src "libresoc.v:150310.18-150310.126" + wire $and$libresoc.v:150310$7626_Y + attribute \src "libresoc.v:150311.18-150311.117" + wire $and$libresoc.v:150311$7627_Y + attribute \src "libresoc.v:150317.18-150317.130" + wire $and$libresoc.v:150317$7633_Y + attribute \src "libresoc.v:150318.18-150318.124" + wire width 4 $and$libresoc.v:150318$7634_Y + attribute \src "libresoc.v:150320.18-150320.116" + wire $and$libresoc.v:150320$7636_Y + attribute \src "libresoc.v:150321.18-150321.119" + wire $and$libresoc.v:150321$7637_Y + attribute \src "libresoc.v:150322.18-150322.121" + wire $and$libresoc.v:150322$7638_Y + attribute \src "libresoc.v:150323.18-150323.121" + wire $and$libresoc.v:150323$7639_Y + attribute \src "libresoc.v:150330.18-150330.134" + wire $and$libresoc.v:150330$7646_Y + attribute \src "libresoc.v:150332.18-150332.132" + wire $and$libresoc.v:150332$7648_Y + attribute \src "libresoc.v:150333.18-150333.149" + wire width 3 $and$libresoc.v:150333$7649_Y + attribute \src "libresoc.v:150335.18-150335.129" + wire width 3 $and$libresoc.v:150335$7651_Y + attribute \src "libresoc.v:150306.18-150306.113" + wire $eq$libresoc.v:150306$7622_Y + attribute \src "libresoc.v:150308.18-150308.119" + wire $eq$libresoc.v:150308$7624_Y + attribute \src "libresoc.v:150289.18-150289.97" + wire $not$libresoc.v:150289$7605_Y + attribute \src "libresoc.v:150291.18-150291.99" + wire $not$libresoc.v:150291$7607_Y + attribute \src "libresoc.v:150294.18-150294.113" + wire width 4 $not$libresoc.v:150294$7610_Y + attribute \src "libresoc.v:150297.18-150297.106" + wire $not$libresoc.v:150297$7613_Y + attribute \src "libresoc.v:150303.18-150303.120" + wire $not$libresoc.v:150303$7619_Y + attribute \src "libresoc.v:150314.17-150314.113" + wire width 3 $not$libresoc.v:150314$7630_Y + attribute \src "libresoc.v:150334.18-150334.131" + wire $not$libresoc.v:150334$7650_Y + attribute \src "libresoc.v:150336.18-150336.114" + wire width 3 $not$libresoc.v:150336$7652_Y + attribute \src "libresoc.v:150302.18-150302.112" + wire $or$libresoc.v:150302$7618_Y + attribute \src "libresoc.v:150312.18-150312.122" + wire $or$libresoc.v:150312$7628_Y + attribute \src "libresoc.v:150313.18-150313.124" + wire $or$libresoc.v:150313$7629_Y + attribute \src "libresoc.v:150315.18-150315.168" + wire width 4 $or$libresoc.v:150315$7631_Y + attribute \src "libresoc.v:150316.18-150316.155" + wire width 3 $or$libresoc.v:150316$7632_Y + attribute \src "libresoc.v:150319.18-150319.120" + wire width 4 $or$libresoc.v:150319$7635_Y + attribute \src "libresoc.v:150325.17-150325.117" + wire width 3 $or$libresoc.v:150325$7641_Y + attribute \src "libresoc.v:150331.17-150331.104" + wire $reduce_and$libresoc.v:150331$7647_Y + attribute \src "libresoc.v:150296.18-150296.106" + wire $reduce_or$libresoc.v:150296$7612_Y + attribute \src "libresoc.v:150300.18-150300.113" + wire $reduce_or$libresoc.v:150300$7616_Y + attribute \src "libresoc.v:150301.18-150301.112" + wire $reduce_or$libresoc.v:150301$7617_Y + attribute \src "libresoc.v:150324.18-150324.160" + wire $ternary$libresoc.v:150324$7640_Y + attribute \src "libresoc.v:150326.18-150326.172" + wire width 64 $ternary$libresoc.v:150326$7642_Y + attribute \src "libresoc.v:150327.18-150327.118" + wire width 64 $ternary$libresoc.v:150327$7643_Y + attribute \src "libresoc.v:150328.18-150328.115" + wire width 64 $ternary$libresoc.v:150328$7644_Y + attribute \src "libresoc.v:150329.18-150329.118" + wire $ternary$libresoc.v:150329$7645_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -295205,15 +314036,15 @@ module \mul0 wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$118 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$120 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$2 @@ -295285,11 +314116,11 @@ module \mul0 wire \$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$80 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$82 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$84 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$88 @@ -295305,49 +314136,51 @@ module \mul0 wire width 3 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_mul0_cr_a attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_mul0_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_mul0_mul_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_mul0_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_mul0_mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_mul0_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -295434,6 +314267,7 @@ module \mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_mul0_mul_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -295466,15 +314300,15 @@ module \mul0 wire \alu_mul0_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_mul0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_mul0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_mul0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_mul0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_mul0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_mul0_ra @@ -295490,17 +314324,17 @@ module \mul0 wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 4 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \cr_a_ok @@ -295566,35 +314400,37 @@ module \mul0 wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o - attribute \src "libresoc.v:139873.7-139873.15" + attribute \src "libresoc.v:149680.7-149680.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_mul0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -295675,6 +314511,7 @@ module \mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -295697,15 +314534,15 @@ module \mul0 wire width 4 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -295713,23 +314550,23 @@ module \mul0 wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 4 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -295739,29 +314576,29 @@ module \mul0 wire width 64 input 20 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 21 \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel @@ -295772,7 +314609,7 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:140464$7271 + cell $and $and$libresoc.v:150277$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -295780,10 +314617,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:140464$7271_Y + connect \Y $and$libresoc.v:150277$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:140465$7272 + cell $and $and$libresoc.v:150278$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295791,10 +314628,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140465$7272_Y + connect \Y $and$libresoc.v:150278$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:140466$7273 + cell $and $and$libresoc.v:150279$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295802,10 +314639,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140466$7273_Y + connect \Y $and$libresoc.v:150279$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:140467$7274 + cell $and $and$libresoc.v:150280$7596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295813,10 +314650,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140467$7274_Y + connect \Y $and$libresoc.v:150280$7596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:140468$7275 + cell $and $and$libresoc.v:150281$7597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295824,10 +314661,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140468$7275_Y + connect \Y $and$libresoc.v:150281$7597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:140469$7276 + cell $and $and$libresoc.v:150282$7598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295835,10 +314672,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:140469$7276_Y + connect \Y $and$libresoc.v:150282$7598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:140470$7277 + cell $and $and$libresoc.v:150283$7599 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -295846,10 +314683,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:140470$7277_Y + connect \Y $and$libresoc.v:150283$7599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:140471$7278 + cell $and $and$libresoc.v:150284$7600 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -295857,10 +314694,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:140471$7278_Y + connect \Y $and$libresoc.v:150284$7600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:140472$7279 + cell $and $and$libresoc.v:150285$7601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295868,10 +314705,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:140472$7279_Y + connect \Y $and$libresoc.v:150285$7601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:140473$7280 + cell $and $and$libresoc.v:150286$7602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295879,10 +314716,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:140473$7280_Y + connect \Y $and$libresoc.v:150286$7602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:140474$7281 + cell $and $and$libresoc.v:150287$7603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295890,10 +314727,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:140474$7281_Y + connect \Y $and$libresoc.v:150287$7603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:140475$7282 + cell $and $and$libresoc.v:150288$7604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295901,10 +314738,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:140475$7282_Y + connect \Y $and$libresoc.v:150288$7604_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:140477$7284 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:150290$7606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295912,10 +314749,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:140477$7284_Y + connect \Y $and$libresoc.v:150290$7606_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:140479$7286 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:150292$7608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295923,10 +314760,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:140479$7286_Y + connect \Y $and$libresoc.v:150292$7608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:140480$7287 + cell $and $and$libresoc.v:150293$7609 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -295934,10 +314771,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:140480$7287_Y + connect \Y $and$libresoc.v:150293$7609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:140482$7289 + cell $and $and$libresoc.v:150295$7611 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -295945,10 +314782,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:140482$7289_Y + connect \Y $and$libresoc.v:150295$7611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:140485$7292 + cell $and $and$libresoc.v:150298$7614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295956,10 +314793,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:140485$7292_Y + connect \Y $and$libresoc.v:150298$7614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:140486$7293 + cell $and $and$libresoc.v:150299$7615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295967,10 +314804,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:140486$7293_Y + connect \Y $and$libresoc.v:150299$7615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:140491$7298 + cell $and $and$libresoc.v:150304$7620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295978,10 +314815,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:140491$7298_Y + connect \Y $and$libresoc.v:150304$7620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:140492$7299 + cell $and $and$libresoc.v:150305$7621 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -295989,10 +314826,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:140492$7299_Y + connect \Y $and$libresoc.v:150305$7621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:140494$7301 + cell $and $and$libresoc.v:150307$7623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296000,10 +314837,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:140494$7301_Y + connect \Y $and$libresoc.v:150307$7623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:140496$7303 + cell $and $and$libresoc.v:150309$7625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296011,10 +314848,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:140496$7303_Y + connect \Y $and$libresoc.v:150309$7625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:140497$7304 + cell $and $and$libresoc.v:150310$7626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296022,10 +314859,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:140497$7304_Y + connect \Y $and$libresoc.v:150310$7626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:140498$7305 + cell $and $and$libresoc.v:150311$7627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296033,10 +314870,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:140498$7305_Y + connect \Y $and$libresoc.v:150311$7627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:140504$7311 + cell $and $and$libresoc.v:150317$7633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296044,10 +314881,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:140504$7311_Y + connect \Y $and$libresoc.v:150317$7633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:140505$7312 + cell $and $and$libresoc.v:150318$7634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -296055,10 +314892,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:140505$7312_Y + connect \Y $and$libresoc.v:150318$7634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:140507$7314 + cell $and $and$libresoc.v:150320$7636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296066,10 +314903,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:140507$7314_Y + connect \Y $and$libresoc.v:150320$7636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:140508$7315 + cell $and $and$libresoc.v:150321$7637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296077,10 +314914,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:140508$7315_Y + connect \Y $and$libresoc.v:150321$7637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:140509$7316 + cell $and $and$libresoc.v:150322$7638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296088,10 +314925,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:140509$7316_Y + connect \Y $and$libresoc.v:150322$7638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:140510$7317 + cell $and $and$libresoc.v:150323$7639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296099,10 +314936,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:140510$7317_Y + connect \Y $and$libresoc.v:150323$7639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:140517$7324 + cell $and $and$libresoc.v:150330$7646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296110,10 +314947,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:140517$7324_Y + connect \Y $and$libresoc.v:150330$7646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:140519$7326 + cell $and $and$libresoc.v:150332$7648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296121,10 +314958,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:140519$7326_Y + connect \Y $and$libresoc.v:150332$7648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:140520$7327 + cell $and $and$libresoc.v:150333$7649 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -296132,10 +314969,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:140520$7327_Y + connect \Y $and$libresoc.v:150333$7649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:140522$7329 + cell $and $and$libresoc.v:150335$7651 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -296143,10 +314980,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:140522$7329_Y + connect \Y $and$libresoc.v:150335$7651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:140493$7300 + cell $eq $eq$libresoc.v:150306$7622 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -296154,10 +314991,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:140493$7300_Y + connect \Y $eq$libresoc.v:150306$7622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:140495$7302 + cell $eq $eq$libresoc.v:150308$7624 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -296165,74 +315002,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:140495$7302_Y + connect \Y $eq$libresoc.v:150308$7624_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:140476$7283 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:150289$7605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:140476$7283_Y + connect \Y $not$libresoc.v:150289$7605_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:140478$7285 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:150291$7607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:140478$7285_Y + connect \Y $not$libresoc.v:150291$7607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:140481$7288 + cell $not $not$libresoc.v:150294$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:140481$7288_Y + connect \Y $not$libresoc.v:150294$7610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:140484$7291 + cell $not $not$libresoc.v:150297$7613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:140484$7291_Y + connect \Y $not$libresoc.v:150297$7613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:140490$7297 + cell $not $not$libresoc.v:150303$7619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:140490$7297_Y + connect \Y $not$libresoc.v:150303$7619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:140501$7308 + cell $not $not$libresoc.v:150314$7630 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:140501$7308_Y + connect \Y $not$libresoc.v:150314$7630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:140521$7328 + cell $not $not$libresoc.v:150334$7650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:140521$7328_Y + connect \Y $not$libresoc.v:150334$7650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:140523$7330 + cell $not $not$libresoc.v:150336$7652 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:140523$7330_Y + connect \Y $not$libresoc.v:150336$7652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:140489$7296 + cell $or $or$libresoc.v:150302$7618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296240,10 +315077,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:140489$7296_Y + connect \Y $or$libresoc.v:150302$7618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:140499$7306 + cell $or $or$libresoc.v:150312$7628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296251,10 +315088,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140499$7306_Y + connect \Y $or$libresoc.v:150312$7628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:140500$7307 + cell $or $or$libresoc.v:150313$7629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296262,10 +315099,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140500$7307_Y + connect \Y $or$libresoc.v:150313$7629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:140502$7309 + cell $or $or$libresoc.v:150315$7631 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -296273,10 +315110,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:140502$7309_Y + connect \Y $or$libresoc.v:150315$7631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:140503$7310 + cell $or $or$libresoc.v:150316$7632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -296284,10 +315121,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:140503$7310_Y + connect \Y $or$libresoc.v:150316$7632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:140506$7313 + cell $or $or$libresoc.v:150319$7635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -296295,10 +315132,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:140506$7313_Y + connect \Y $or$libresoc.v:150319$7635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:140512$7319 + cell $or $or$libresoc.v:150325$7641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -296306,82 +315143,82 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:140512$7319_Y + connect \Y $or$libresoc.v:150325$7641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:140518$7325 + cell $reduce_and $reduce_and$libresoc.v:150331$7647 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:140518$7325_Y + connect \Y $reduce_and$libresoc.v:150331$7647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:140483$7290 + cell $reduce_or $reduce_or$libresoc.v:150296$7612 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:140483$7290_Y + connect \Y $reduce_or$libresoc.v:150296$7612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:140487$7294 + cell $reduce_or $reduce_or$libresoc.v:150300$7616 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:140487$7294_Y + connect \Y $reduce_or$libresoc.v:150300$7616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:140488$7295 + cell $reduce_or $reduce_or$libresoc.v:150301$7617 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:140488$7295_Y + connect \Y $reduce_or$libresoc.v:150301$7617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:140511$7318 + cell $mux $ternary$libresoc.v:150324$7640 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:140511$7318_Y + connect \Y $ternary$libresoc.v:150324$7640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:140513$7320 + cell $mux $ternary$libresoc.v:150326$7642 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:140513$7320_Y + connect \Y $ternary$libresoc.v:150326$7642_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:140514$7321 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:150327$7643 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:140514$7321_Y + connect \Y $ternary$libresoc.v:150327$7643_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:140515$7322 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:150328$7644 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:140515$7322_Y + connect \Y $ternary$libresoc.v:150328$7644_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:140516$7323 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:150329$7645 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:140516$7323_Y + connect \Y $ternary$libresoc.v:150329$7645_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:140600.15-140606.4" + attribute \src "libresoc.v:150413.15-150419.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -296390,7 +315227,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:140607.12-140637.4" + attribute \src "libresoc.v:150420.12-150450.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -296423,7 +315260,7 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:140638.16-140644.4" + attribute \src "libresoc.v:150451.16-150457.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -296432,7 +315269,7 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:140645.15-140651.4" + attribute \src "libresoc.v:150458.15-150464.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -296441,7 +315278,7 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:140652.15-140658.4" + attribute \src "libresoc.v:150465.15-150471.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -296450,7 +315287,7 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:140659.15-140665.4" + attribute \src "libresoc.v:150472.15-150478.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -296459,7 +315296,7 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:140666.15-140671.4" + attribute \src "libresoc.v:150479.15-150484.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -296467,7 +315304,7 @@ module \mul0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:140672.15-140678.4" + attribute \src "libresoc.v:150485.15-150491.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -296475,592 +315312,592 @@ module \mul0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:139873.7-139873.20" - process $proc$libresoc.v:139873$7485 + attribute \src "libresoc.v:149680.7-149680.20" + process $proc$libresoc.v:149680$7807 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139997.7-139997.24" - process $proc$libresoc.v:139997$7486 + attribute \src "libresoc.v:149804.7-149804.24" + process $proc$libresoc.v:149804$7808 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:140007.7-140007.26" - process $proc$libresoc.v:140007$7487 + attribute \src "libresoc.v:149814.7-149814.26" + process $proc$libresoc.v:149814$7809 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:140015.7-140015.25" - process $proc$libresoc.v:140015$7488 + attribute \src "libresoc.v:149822.7-149822.25" + process $proc$libresoc.v:149822$7810 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:140036.14-140036.48" - process $proc$libresoc.v:140036$7489 + attribute \src "libresoc.v:149845.14-149845.49" + process $proc$libresoc.v:149845$7811 assign { } { } - assign $1\alu_mul0_mul_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[11:0] + update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:140040.14-140040.68" - process $proc$libresoc.v:140040$7490 + attribute \src "libresoc.v:149849.14-149849.68" + process $proc$libresoc.v:149849$7812 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:140044.7-140044.43" - process $proc$libresoc.v:140044$7491 + attribute \src "libresoc.v:149853.7-149853.43" + process $proc$libresoc.v:149853$7813 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:140048.14-140048.43" - process $proc$libresoc.v:140048$7492 + attribute \src "libresoc.v:149857.14-149857.43" + process $proc$libresoc.v:149857$7814 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:140126.13-140126.47" - process $proc$libresoc.v:140126$7493 + attribute \src "libresoc.v:149936.13-149936.47" + process $proc$libresoc.v:149936$7815 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:140130.7-140130.39" - process $proc$libresoc.v:140130$7494 + attribute \src "libresoc.v:149940.7-149940.39" + process $proc$libresoc.v:149940$7816 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:140134.7-140134.40" - process $proc$libresoc.v:140134$7495 + attribute \src "libresoc.v:149944.7-149944.40" + process $proc$libresoc.v:149944$7817 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:140138.7-140138.37" - process $proc$libresoc.v:140138$7496 + attribute \src "libresoc.v:149948.7-149948.37" + process $proc$libresoc.v:149948$7818 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:140142.7-140142.37" - process $proc$libresoc.v:140142$7497 + attribute \src "libresoc.v:149952.7-149952.37" + process $proc$libresoc.v:149952$7819 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:140146.7-140146.37" - process $proc$libresoc.v:140146$7498 + attribute \src "libresoc.v:149956.7-149956.37" + process $proc$libresoc.v:149956$7820 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:140150.7-140150.37" - process $proc$libresoc.v:140150$7499 + attribute \src "libresoc.v:149960.7-149960.37" + process $proc$libresoc.v:149960$7821 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:140154.7-140154.40" - process $proc$libresoc.v:140154$7500 + attribute \src "libresoc.v:149964.7-149964.40" + process $proc$libresoc.v:149964$7822 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:140184.7-140184.27" - process $proc$libresoc.v:140184$7501 + attribute \src "libresoc.v:149994.7-149994.27" + process $proc$libresoc.v:149994$7823 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:140218.14-140218.47" - process $proc$libresoc.v:140218$7502 + attribute \src "libresoc.v:150028.14-150028.47" + process $proc$libresoc.v:150028$7824 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:140222.7-140222.27" - process $proc$libresoc.v:140222$7503 + attribute \src "libresoc.v:150032.7-150032.27" + process $proc$libresoc.v:150032$7825 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:140226.13-140226.33" - process $proc$libresoc.v:140226$7504 + attribute \src "libresoc.v:150036.13-150036.33" + process $proc$libresoc.v:150036$7826 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:140230.7-140230.30" - process $proc$libresoc.v:140230$7505 + attribute \src "libresoc.v:150040.7-150040.30" + process $proc$libresoc.v:150040$7827 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:140234.13-140234.35" - process $proc$libresoc.v:140234$7506 + attribute \src "libresoc.v:150044.13-150044.35" + process $proc$libresoc.v:150044$7828 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:140238.7-140238.32" - process $proc$libresoc.v:140238$7507 + attribute \src "libresoc.v:150048.7-150048.32" + process $proc$libresoc.v:150048$7829 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:140242.7-140242.29" - process $proc$libresoc.v:140242$7508 + attribute \src "libresoc.v:150052.7-150052.29" + process $proc$libresoc.v:150052$7830 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:140246.7-140246.32" - process $proc$libresoc.v:140246$7509 + attribute \src "libresoc.v:150056.7-150056.32" + process $proc$libresoc.v:150056$7831 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:140266.7-140266.25" - process $proc$libresoc.v:140266$7510 + attribute \src "libresoc.v:150076.7-150076.25" + process $proc$libresoc.v:150076$7832 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:140270.7-140270.25" - process $proc$libresoc.v:140270$7511 + attribute \src "libresoc.v:150080.7-150080.25" + process $proc$libresoc.v:150080$7833 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:140385.13-140385.30" - process $proc$libresoc.v:140385$7512 + attribute \src "libresoc.v:150198.13-150198.30" + process $proc$libresoc.v:150198$7834 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:140393.13-140393.31" - process $proc$libresoc.v:140393$7513 + attribute \src "libresoc.v:150206.13-150206.31" + process $proc$libresoc.v:150206$7835 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:140397.13-140397.31" - process $proc$libresoc.v:140397$7514 + attribute \src "libresoc.v:150210.13-150210.31" + process $proc$libresoc.v:150210$7836 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:140409.7-140409.26" - process $proc$libresoc.v:140409$7515 + attribute \src "libresoc.v:150222.7-150222.26" + process $proc$libresoc.v:150222$7837 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:140413.7-140413.26" - process $proc$libresoc.v:140413$7516 + attribute \src "libresoc.v:150226.7-150226.26" + process $proc$libresoc.v:150226$7838 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:140417.7-140417.25" - process $proc$libresoc.v:140417$7517 + attribute \src "libresoc.v:150230.7-150230.25" + process $proc$libresoc.v:150230$7839 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:140421.7-140421.25" - process $proc$libresoc.v:140421$7518 + attribute \src "libresoc.v:150234.7-150234.25" + process $proc$libresoc.v:150234$7840 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:140435.13-140435.31" - process $proc$libresoc.v:140435$7519 + attribute \src "libresoc.v:150248.13-150248.31" + process $proc$libresoc.v:150248$7841 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:140439.13-140439.31" - process $proc$libresoc.v:140439$7520 + attribute \src "libresoc.v:150252.13-150252.31" + process $proc$libresoc.v:150252$7842 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:140445.14-140445.43" - process $proc$libresoc.v:140445$7521 + attribute \src "libresoc.v:150258.14-150258.43" + process $proc$libresoc.v:150258$7843 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:140449.14-140449.43" - process $proc$libresoc.v:140449$7522 + attribute \src "libresoc.v:150262.14-150262.43" + process $proc$libresoc.v:150262$7844 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:140453.7-140453.20" - process $proc$libresoc.v:140453$7523 + attribute \src "libresoc.v:150266.7-150266.20" + process $proc$libresoc.v:150266$7845 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:140524.3-140525.39" - process $proc$libresoc.v:140524$7331 + attribute \src "libresoc.v:150337.3-150338.39" + process $proc$libresoc.v:150337$7653 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:140526.3-140527.43" - process $proc$libresoc.v:140526$7332 + attribute \src "libresoc.v:150339.3-150340.43" + process $proc$libresoc.v:150339$7654 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:140528.3-140529.29" - process $proc$libresoc.v:140528$7333 + attribute \src "libresoc.v:150341.3-150342.29" + process $proc$libresoc.v:150341$7655 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:140530.3-140531.29" - process $proc$libresoc.v:140530$7334 + attribute \src "libresoc.v:150343.3-150344.29" + process $proc$libresoc.v:150343$7656 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:140532.3-140533.29" - process $proc$libresoc.v:140532$7335 + attribute \src "libresoc.v:150345.3-150346.29" + process $proc$libresoc.v:150345$7657 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:140534.3-140535.47" - process $proc$libresoc.v:140534$7336 + attribute \src "libresoc.v:150347.3-150348.47" + process $proc$libresoc.v:150347$7658 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:140536.3-140537.53" - process $proc$libresoc.v:140536$7337 + attribute \src "libresoc.v:150349.3-150350.53" + process $proc$libresoc.v:150349$7659 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:140538.3-140539.47" - process $proc$libresoc.v:140538$7338 + attribute \src "libresoc.v:150351.3-150352.47" + process $proc$libresoc.v:150351$7660 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:140540.3-140541.53" - process $proc$libresoc.v:140540$7339 + attribute \src "libresoc.v:150353.3-150354.53" + process $proc$libresoc.v:150353$7661 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:140542.3-140543.43" - process $proc$libresoc.v:140542$7340 + attribute \src "libresoc.v:150355.3-150356.43" + process $proc$libresoc.v:150355$7662 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:140544.3-140545.49" - process $proc$libresoc.v:140544$7341 + attribute \src "libresoc.v:150357.3-150358.49" + process $proc$libresoc.v:150357$7663 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:140546.3-140547.37" - process $proc$libresoc.v:140546$7342 + attribute \src "libresoc.v:150359.3-150360.37" + process $proc$libresoc.v:150359$7664 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:140548.3-140549.43" - process $proc$libresoc.v:140548$7343 + attribute \src "libresoc.v:150361.3-150362.43" + process $proc$libresoc.v:150361$7665 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:140550.3-140551.69" - process $proc$libresoc.v:140550$7344 + attribute \src "libresoc.v:150363.3-150364.69" + process $proc$libresoc.v:150363$7666 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:140552.3-140553.65" - process $proc$libresoc.v:140552$7345 + attribute \src "libresoc.v:150365.3-150366.65" + process $proc$libresoc.v:150365$7667 assign { } { } - assign $0\alu_mul0_mul_op__fn_unit[11:0] \alu_mul0_mul_op__fn_unit$next + assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk - update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[11:0] + update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:140554.3-140555.79" - process $proc$libresoc.v:140554$7346 + attribute \src "libresoc.v:150367.3-150368.79" + process $proc$libresoc.v:150367$7668 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:140556.3-140557.75" - process $proc$libresoc.v:140556$7347 + attribute \src "libresoc.v:150369.3-150370.75" + process $proc$libresoc.v:150369$7669 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:140558.3-140559.63" - process $proc$libresoc.v:140558$7348 + attribute \src "libresoc.v:150371.3-150372.63" + process $proc$libresoc.v:150371$7670 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:140560.3-140561.63" - process $proc$libresoc.v:140560$7349 + attribute \src "libresoc.v:150373.3-150374.63" + process $proc$libresoc.v:150373$7671 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:140562.3-140563.63" - process $proc$libresoc.v:140562$7350 + attribute \src "libresoc.v:150375.3-150376.63" + process $proc$libresoc.v:150375$7672 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:140564.3-140565.63" - process $proc$libresoc.v:140564$7351 + attribute \src "libresoc.v:150377.3-150378.63" + process $proc$libresoc.v:150377$7673 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:140566.3-140567.69" - process $proc$libresoc.v:140566$7352 + attribute \src "libresoc.v:150379.3-150380.69" + process $proc$libresoc.v:150379$7674 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:140568.3-140569.67" - process $proc$libresoc.v:140568$7353 + attribute \src "libresoc.v:150381.3-150382.67" + process $proc$libresoc.v:150381$7675 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:140570.3-140571.69" - process $proc$libresoc.v:140570$7354 + attribute \src "libresoc.v:150383.3-150384.69" + process $proc$libresoc.v:150383$7676 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:140572.3-140573.59" - process $proc$libresoc.v:140572$7355 + attribute \src "libresoc.v:150385.3-150386.59" + process $proc$libresoc.v:150385$7677 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:140574.3-140575.39" - process $proc$libresoc.v:140574$7356 + attribute \src "libresoc.v:150387.3-150388.39" + process $proc$libresoc.v:150387$7678 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:140576.3-140577.39" - process $proc$libresoc.v:140576$7357 + attribute \src "libresoc.v:150389.3-150390.39" + process $proc$libresoc.v:150389$7679 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:140578.3-140579.39" - process $proc$libresoc.v:140578$7358 + attribute \src "libresoc.v:150391.3-150392.39" + process $proc$libresoc.v:150391$7680 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:140580.3-140581.39" - process $proc$libresoc.v:140580$7359 + attribute \src "libresoc.v:150393.3-150394.39" + process $proc$libresoc.v:150393$7681 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:140582.3-140583.39" - process $proc$libresoc.v:140582$7360 + attribute \src "libresoc.v:150395.3-150396.39" + process $proc$libresoc.v:150395$7682 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:140584.3-140585.39" - process $proc$libresoc.v:140584$7361 + attribute \src "libresoc.v:150397.3-150398.39" + process $proc$libresoc.v:150397$7683 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:140586.3-140587.39" - process $proc$libresoc.v:140586$7362 + attribute \src "libresoc.v:150399.3-150400.39" + process $proc$libresoc.v:150399$7684 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:140588.3-140589.39" - process $proc$libresoc.v:140588$7363 + attribute \src "libresoc.v:150401.3-150402.39" + process $proc$libresoc.v:150401$7685 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:140590.3-140591.41" - process $proc$libresoc.v:140590$7364 + attribute \src "libresoc.v:150403.3-150404.41" + process $proc$libresoc.v:150403$7686 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:140592.3-140593.41" - process $proc$libresoc.v:140592$7365 + attribute \src "libresoc.v:150405.3-150406.41" + process $proc$libresoc.v:150405$7687 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:140594.3-140595.37" - process $proc$libresoc.v:140594$7366 + attribute \src "libresoc.v:150407.3-150408.37" + process $proc$libresoc.v:150407$7688 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:140596.3-140597.40" - process $proc$libresoc.v:140596$7367 + attribute \src "libresoc.v:150409.3-150410.40" + process $proc$libresoc.v:150409$7689 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:140598.3-140599.25" - process $proc$libresoc.v:140598$7368 + attribute \src "libresoc.v:150411.3-150412.25" + process $proc$libresoc.v:150411$7690 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:140679.3-140688.6" - process $proc$libresoc.v:140679$7369 + attribute \src "libresoc.v:150492.3-150501.6" + process $proc$libresoc.v:150492$7691 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:140680.5-140680.29" + attribute \src "libresoc.v:150493.5-150493.29" switch \initial - attribute \src "libresoc.v:140680.9-140680.17" + attribute \src "libresoc.v:150493.9-150493.17" case 1'1 case end @@ -297076,14 +315913,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:140689.3-140697.6" - process $proc$libresoc.v:140689$7370 + attribute \src "libresoc.v:150502.3-150510.6" + process $proc$libresoc.v:150502$7692 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7371 $1\rok_l_s_rdok$next[0:0]$7372 - attribute \src "libresoc.v:140690.5-140690.29" + assign $0\rok_l_s_rdok$next[0:0]$7693 $1\rok_l_s_rdok$next[0:0]$7694 + attribute \src "libresoc.v:150503.5-150503.29" switch \initial - attribute \src "libresoc.v:140690.9-140690.17" + attribute \src "libresoc.v:150503.9-150503.17" case 1'1 case end @@ -297092,21 +315929,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7372 1'0 + assign $1\rok_l_s_rdok$next[0:0]$7694 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$7372 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$7694 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7371 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7693 end - attribute \src "libresoc.v:140698.3-140706.6" - process $proc$libresoc.v:140698$7373 + attribute \src "libresoc.v:150511.3-150519.6" + process $proc$libresoc.v:150511$7695 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7374 $1\rok_l_r_rdok$next[0:0]$7375 - attribute \src "libresoc.v:140699.5-140699.29" + assign $0\rok_l_r_rdok$next[0:0]$7696 $1\rok_l_r_rdok$next[0:0]$7697 + attribute \src "libresoc.v:150512.5-150512.29" switch \initial - attribute \src "libresoc.v:140699.9-140699.17" + attribute \src "libresoc.v:150512.9-150512.17" case 1'1 case end @@ -297115,21 +315952,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7375 1'1 + assign $1\rok_l_r_rdok$next[0:0]$7697 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$7375 \$64 + assign $1\rok_l_r_rdok$next[0:0]$7697 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7374 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7696 end - attribute \src "libresoc.v:140707.3-140715.6" - process $proc$libresoc.v:140707$7376 + attribute \src "libresoc.v:150520.3-150528.6" + process $proc$libresoc.v:150520$7698 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7377 $1\rst_l_s_rst$next[0:0]$7378 - attribute \src "libresoc.v:140708.5-140708.29" + assign $0\rst_l_s_rst$next[0:0]$7699 $1\rst_l_s_rst$next[0:0]$7700 + attribute \src "libresoc.v:150521.5-150521.29" switch \initial - attribute \src "libresoc.v:140708.9-140708.17" + attribute \src "libresoc.v:150521.9-150521.17" case 1'1 case end @@ -297138,21 +315975,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7378 1'0 + assign $1\rst_l_s_rst$next[0:0]$7700 1'0 case - assign $1\rst_l_s_rst$next[0:0]$7378 \all_rd + assign $1\rst_l_s_rst$next[0:0]$7700 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7377 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7699 end - attribute \src "libresoc.v:140716.3-140724.6" - process $proc$libresoc.v:140716$7379 + attribute \src "libresoc.v:150529.3-150537.6" + process $proc$libresoc.v:150529$7701 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7380 $1\rst_l_r_rst$next[0:0]$7381 - attribute \src "libresoc.v:140717.5-140717.29" + assign $0\rst_l_r_rst$next[0:0]$7702 $1\rst_l_r_rst$next[0:0]$7703 + attribute \src "libresoc.v:150530.5-150530.29" switch \initial - attribute \src "libresoc.v:140717.9-140717.17" + attribute \src "libresoc.v:150530.9-150530.17" case 1'1 case end @@ -297161,21 +315998,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7381 1'1 + assign $1\rst_l_r_rst$next[0:0]$7703 1'1 case - assign $1\rst_l_r_rst$next[0:0]$7381 \rst_r + assign $1\rst_l_r_rst$next[0:0]$7703 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7380 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7702 end - attribute \src "libresoc.v:140725.3-140733.6" - process $proc$libresoc.v:140725$7382 + attribute \src "libresoc.v:150538.3-150546.6" + process $proc$libresoc.v:150538$7704 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7383 $1\opc_l_s_opc$next[0:0]$7384 - attribute \src "libresoc.v:140726.5-140726.29" + assign $0\opc_l_s_opc$next[0:0]$7705 $1\opc_l_s_opc$next[0:0]$7706 + attribute \src "libresoc.v:150539.5-150539.29" switch \initial - attribute \src "libresoc.v:140726.9-140726.17" + attribute \src "libresoc.v:150539.9-150539.17" case 1'1 case end @@ -297184,21 +316021,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7384 1'0 + assign $1\opc_l_s_opc$next[0:0]$7706 1'0 case - assign $1\opc_l_s_opc$next[0:0]$7384 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$7706 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7383 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7705 end - attribute \src "libresoc.v:140734.3-140742.6" - process $proc$libresoc.v:140734$7385 + attribute \src "libresoc.v:150547.3-150555.6" + process $proc$libresoc.v:150547$7707 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7386 $1\opc_l_r_opc$next[0:0]$7387 - attribute \src "libresoc.v:140735.5-140735.29" + assign $0\opc_l_r_opc$next[0:0]$7708 $1\opc_l_r_opc$next[0:0]$7709 + attribute \src "libresoc.v:150548.5-150548.29" switch \initial - attribute \src "libresoc.v:140735.9-140735.17" + attribute \src "libresoc.v:150548.9-150548.17" case 1'1 case end @@ -297207,21 +316044,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7387 1'1 + assign $1\opc_l_r_opc$next[0:0]$7709 1'1 case - assign $1\opc_l_r_opc$next[0:0]$7387 \req_done + assign $1\opc_l_r_opc$next[0:0]$7709 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7386 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7708 end - attribute \src "libresoc.v:140743.3-140751.6" - process $proc$libresoc.v:140743$7388 + attribute \src "libresoc.v:150556.3-150564.6" + process $proc$libresoc.v:150556$7710 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$7389 $1\src_l_s_src$next[2:0]$7390 - attribute \src "libresoc.v:140744.5-140744.29" + assign $0\src_l_s_src$next[2:0]$7711 $1\src_l_s_src$next[2:0]$7712 + attribute \src "libresoc.v:150557.5-150557.29" switch \initial - attribute \src "libresoc.v:140744.9-140744.17" + attribute \src "libresoc.v:150557.9-150557.17" case 1'1 case end @@ -297230,21 +316067,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$7390 3'000 + assign $1\src_l_s_src$next[2:0]$7712 3'000 case - assign $1\src_l_s_src$next[2:0]$7390 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$7712 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7389 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7711 end - attribute \src "libresoc.v:140752.3-140760.6" - process $proc$libresoc.v:140752$7391 + attribute \src "libresoc.v:150565.3-150573.6" + process $proc$libresoc.v:150565$7713 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$7392 $1\src_l_r_src$next[2:0]$7393 - attribute \src "libresoc.v:140753.5-140753.29" + assign $0\src_l_r_src$next[2:0]$7714 $1\src_l_r_src$next[2:0]$7715 + attribute \src "libresoc.v:150566.5-150566.29" switch \initial - attribute \src "libresoc.v:140753.9-140753.17" + attribute \src "libresoc.v:150566.9-150566.17" case 1'1 case end @@ -297253,21 +316090,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$7393 3'111 + assign $1\src_l_r_src$next[2:0]$7715 3'111 case - assign $1\src_l_r_src$next[2:0]$7393 \reset_r + assign $1\src_l_r_src$next[2:0]$7715 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7392 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7714 end - attribute \src "libresoc.v:140761.3-140769.6" - process $proc$libresoc.v:140761$7394 + attribute \src "libresoc.v:150574.3-150582.6" + process $proc$libresoc.v:150574$7716 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$7395 $1\req_l_s_req$next[3:0]$7396 - attribute \src "libresoc.v:140762.5-140762.29" + assign $0\req_l_s_req$next[3:0]$7717 $1\req_l_s_req$next[3:0]$7718 + attribute \src "libresoc.v:150575.5-150575.29" switch \initial - attribute \src "libresoc.v:140762.9-140762.17" + attribute \src "libresoc.v:150575.9-150575.17" case 1'1 case end @@ -297276,21 +316113,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$7396 4'0000 + assign $1\req_l_s_req$next[3:0]$7718 4'0000 case - assign $1\req_l_s_req$next[3:0]$7396 \$66 + assign $1\req_l_s_req$next[3:0]$7718 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7395 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7717 end - attribute \src "libresoc.v:140770.3-140778.6" - process $proc$libresoc.v:140770$7397 + attribute \src "libresoc.v:150583.3-150591.6" + process $proc$libresoc.v:150583$7719 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$7398 $1\req_l_r_req$next[3:0]$7399 - attribute \src "libresoc.v:140771.5-140771.29" + assign $0\req_l_r_req$next[3:0]$7720 $1\req_l_r_req$next[3:0]$7721 + attribute \src "libresoc.v:150584.5-150584.29" switch \initial - attribute \src "libresoc.v:140771.9-140771.17" + attribute \src "libresoc.v:150584.9-150584.17" case 1'1 case end @@ -297299,15 +316136,15 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$7399 4'1111 + assign $1\req_l_r_req$next[3:0]$7721 4'1111 case - assign $1\req_l_r_req$next[3:0]$7399 \$68 + assign $1\req_l_r_req$next[3:0]$7721 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7398 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7720 end - attribute \src "libresoc.v:140779.3-140811.6" - process $proc$libresoc.v:140779$7400 + attribute \src "libresoc.v:150592.3-150624.6" + process $proc$libresoc.v:150592$7722 assign { } { } assign { } { } assign { } { } @@ -297332,27 +316169,27 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[11:0]$7401 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7413 + assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7404 $1\alu_mul0_mul_op__insn$next[31:0]$7416 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7405 $1\alu_mul0_mul_op__insn_type$next[6:0]$7417 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7406 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7418 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7407 $1\alu_mul0_mul_op__is_signed$next[0:0]$7419 + assign $0\alu_mul0_mul_op__insn$next[31:0]$7726 $1\alu_mul0_mul_op__insn$next[31:0]$7738 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7412 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7424 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7402 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7425 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7403 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7426 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7408 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7427 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7409 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7428 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7410 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7429 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7411 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7430 - attribute \src "libresoc.v:140780.5-140780.29" + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 + attribute \src "libresoc.v:150593.5-150593.29" switch \initial - attribute \src "libresoc.v:140780.9-140780.17" + attribute \src "libresoc.v:150593.9-150593.17" case 1'1 case end @@ -297372,20 +316209,20 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7416 $1\alu_mul0_mul_op__is_signed$next[0:0]$7419 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7418 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7424 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7421 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7420 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7422 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7423 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7415 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7414 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7413 $1\alu_mul0_mul_op__insn_type$next[6:0]$7417 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7738 $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } case - assign $1\alu_mul0_mul_op__fn_unit$next[11:0]$7413 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7414 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7415 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7416 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7417 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7418 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7419 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7420 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7421 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7422 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7423 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7424 \alu_mul0_mul_op__write_cr0 + assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7738 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 \alu_mul0_mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -297397,48 +316234,48 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7425 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7426 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7430 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7429 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7427 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7428 1'0 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 1'0 case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7425 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7414 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7426 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7415 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7427 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7420 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7428 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7421 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7429 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7422 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7430 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7423 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 end sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[11:0]$7401 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7402 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7403 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7404 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7405 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7406 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7407 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7408 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7409 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7410 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7411 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7412 + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7726 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 end - attribute \src "libresoc.v:140812.3-140833.6" - process $proc$libresoc.v:140812$7431 + attribute \src "libresoc.v:150625.3-150646.6" + process $proc$libresoc.v:150625$7753 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$7432 $2\data_r0__o$next[63:0]$7436 + assign $0\data_r0__o$next[63:0]$7754 $2\data_r0__o$next[63:0]$7758 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7433 $3\data_r0__o_ok$next[0:0]$7438 - attribute \src "libresoc.v:140813.5-140813.29" + assign $0\data_r0__o_ok$next[0:0]$7755 $3\data_r0__o_ok$next[0:0]$7760 + attribute \src "libresoc.v:150626.5-150626.29" switch \initial - attribute \src "libresoc.v:140813.9-140813.17" + attribute \src "libresoc.v:150626.9-150626.17" case 1'1 case end @@ -297448,10 +316285,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7435 $1\data_r0__o$next[63:0]$7434 } { \o_ok \alu_mul0_o } + assign { $1\data_r0__o_ok$next[0:0]$7757 $1\data_r0__o$next[63:0]$7756 } { \o_ok \alu_mul0_o } case - assign $1\data_r0__o$next[63:0]$7434 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7435 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$7756 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7757 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -297459,38 +316296,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7437 $2\data_r0__o$next[63:0]$7436 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$7759 $2\data_r0__o$next[63:0]$7758 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$7436 $1\data_r0__o$next[63:0]$7434 - assign $2\data_r0__o_ok$next[0:0]$7437 $1\data_r0__o_ok$next[0:0]$7435 + assign $2\data_r0__o$next[63:0]$7758 $1\data_r0__o$next[63:0]$7756 + assign $2\data_r0__o_ok$next[0:0]$7759 $1\data_r0__o_ok$next[0:0]$7757 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7438 1'0 + assign $3\data_r0__o_ok$next[0:0]$7760 1'0 case - assign $3\data_r0__o_ok$next[0:0]$7438 $2\data_r0__o_ok$next[0:0]$7437 + assign $3\data_r0__o_ok$next[0:0]$7760 $2\data_r0__o_ok$next[0:0]$7759 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7432 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7433 + update \data_r0__o$next $0\data_r0__o$next[63:0]$7754 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7755 end - attribute \src "libresoc.v:140834.3-140855.6" - process $proc$libresoc.v:140834$7439 + attribute \src "libresoc.v:150647.3-150668.6" + process $proc$libresoc.v:150647$7761 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7440 $2\data_r1__cr_a$next[3:0]$7444 + assign $0\data_r1__cr_a$next[3:0]$7762 $2\data_r1__cr_a$next[3:0]$7766 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7441 $3\data_r1__cr_a_ok$next[0:0]$7446 - attribute \src "libresoc.v:140835.5-140835.29" + assign $0\data_r1__cr_a_ok$next[0:0]$7763 $3\data_r1__cr_a_ok$next[0:0]$7768 + attribute \src "libresoc.v:150648.5-150648.29" switch \initial - attribute \src "libresoc.v:140835.9-140835.17" + attribute \src "libresoc.v:150648.9-150648.17" case 1'1 case end @@ -297500,10 +316337,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7443 $1\data_r1__cr_a$next[3:0]$7442 } { \cr_a_ok \alu_mul0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$7765 $1\data_r1__cr_a$next[3:0]$7764 } { \cr_a_ok \alu_mul0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$7442 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7443 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$7764 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7765 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -297511,38 +316348,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7445 $2\data_r1__cr_a$next[3:0]$7444 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$7767 $2\data_r1__cr_a$next[3:0]$7766 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$7444 $1\data_r1__cr_a$next[3:0]$7442 - assign $2\data_r1__cr_a_ok$next[0:0]$7445 $1\data_r1__cr_a_ok$next[0:0]$7443 + assign $2\data_r1__cr_a$next[3:0]$7766 $1\data_r1__cr_a$next[3:0]$7764 + assign $2\data_r1__cr_a_ok$next[0:0]$7767 $1\data_r1__cr_a_ok$next[0:0]$7765 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7446 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$7768 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$7446 $2\data_r1__cr_a_ok$next[0:0]$7445 + assign $3\data_r1__cr_a_ok$next[0:0]$7768 $2\data_r1__cr_a_ok$next[0:0]$7767 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7440 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7441 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7762 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7763 end - attribute \src "libresoc.v:140856.3-140877.6" - process $proc$libresoc.v:140856$7447 + attribute \src "libresoc.v:150669.3-150690.6" + process $proc$libresoc.v:150669$7769 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7448 $2\data_r2__xer_ov$next[1:0]$7452 + assign $0\data_r2__xer_ov$next[1:0]$7770 $2\data_r2__xer_ov$next[1:0]$7774 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7449 $3\data_r2__xer_ov_ok$next[0:0]$7454 - attribute \src "libresoc.v:140857.5-140857.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$7771 $3\data_r2__xer_ov_ok$next[0:0]$7776 + attribute \src "libresoc.v:150670.5-150670.29" switch \initial - attribute \src "libresoc.v:140857.9-140857.17" + attribute \src "libresoc.v:150670.9-150670.17" case 1'1 case end @@ -297552,10 +316389,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7451 $1\data_r2__xer_ov$next[1:0]$7450 } { \xer_ov_ok \alu_mul0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7773 $1\data_r2__xer_ov$next[1:0]$7772 } { \xer_ov_ok \alu_mul0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$7450 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7451 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$7772 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7773 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -297563,38 +316400,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7453 $2\data_r2__xer_ov$next[1:0]$7452 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$7775 $2\data_r2__xer_ov$next[1:0]$7774 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$7452 $1\data_r2__xer_ov$next[1:0]$7450 - assign $2\data_r2__xer_ov_ok$next[0:0]$7453 $1\data_r2__xer_ov_ok$next[0:0]$7451 + assign $2\data_r2__xer_ov$next[1:0]$7774 $1\data_r2__xer_ov$next[1:0]$7772 + assign $2\data_r2__xer_ov_ok$next[0:0]$7775 $1\data_r2__xer_ov_ok$next[0:0]$7773 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7454 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$7776 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$7454 $2\data_r2__xer_ov_ok$next[0:0]$7453 + assign $3\data_r2__xer_ov_ok$next[0:0]$7776 $2\data_r2__xer_ov_ok$next[0:0]$7775 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7448 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7449 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7770 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7771 end - attribute \src "libresoc.v:140878.3-140899.6" - process $proc$libresoc.v:140878$7455 + attribute \src "libresoc.v:150691.3-150712.6" + process $proc$libresoc.v:150691$7777 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7456 $2\data_r3__xer_so$next[0:0]$7460 + assign $0\data_r3__xer_so$next[0:0]$7778 $2\data_r3__xer_so$next[0:0]$7782 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7457 $3\data_r3__xer_so_ok$next[0:0]$7462 - attribute \src "libresoc.v:140879.5-140879.29" + assign $0\data_r3__xer_so_ok$next[0:0]$7779 $3\data_r3__xer_so_ok$next[0:0]$7784 + attribute \src "libresoc.v:150692.5-150692.29" switch \initial - attribute \src "libresoc.v:140879.9-140879.17" + attribute \src "libresoc.v:150692.9-150692.17" case 1'1 case end @@ -297604,10 +316441,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7459 $1\data_r3__xer_so$next[0:0]$7458 } { \xer_so_ok \alu_mul0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$7781 $1\data_r3__xer_so$next[0:0]$7780 } { \xer_so_ok \alu_mul0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$7458 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7459 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$7780 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7781 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -297615,101 +316452,101 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7461 $2\data_r3__xer_so$next[0:0]$7460 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$7783 $2\data_r3__xer_so$next[0:0]$7782 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$7460 $1\data_r3__xer_so$next[0:0]$7458 - assign $2\data_r3__xer_so_ok$next[0:0]$7461 $1\data_r3__xer_so_ok$next[0:0]$7459 + assign $2\data_r3__xer_so$next[0:0]$7782 $1\data_r3__xer_so$next[0:0]$7780 + assign $2\data_r3__xer_so_ok$next[0:0]$7783 $1\data_r3__xer_so_ok$next[0:0]$7781 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7462 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$7784 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$7462 $2\data_r3__xer_so_ok$next[0:0]$7461 + assign $3\data_r3__xer_so_ok$next[0:0]$7784 $2\data_r3__xer_so_ok$next[0:0]$7783 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7456 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7457 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7778 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7779 end - attribute \src "libresoc.v:140900.3-140909.6" - process $proc$libresoc.v:140900$7463 + attribute \src "libresoc.v:150713.3-150722.6" + process $proc$libresoc.v:150713$7785 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$7464 $1\src_r0$next[63:0]$7465 - attribute \src "libresoc.v:140901.5-140901.29" + assign $0\src_r0$next[63:0]$7786 $1\src_r0$next[63:0]$7787 + attribute \src "libresoc.v:150714.5-150714.29" switch \initial - attribute \src "libresoc.v:140901.9-140901.17" + attribute \src "libresoc.v:150714.9-150714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$7465 \src1_i + assign $1\src_r0$next[63:0]$7787 \src1_i case - assign $1\src_r0$next[63:0]$7465 \src_r0 + assign $1\src_r0$next[63:0]$7787 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$7464 + update \src_r0$next $0\src_r0$next[63:0]$7786 end - attribute \src "libresoc.v:140910.3-140919.6" - process $proc$libresoc.v:140910$7466 + attribute \src "libresoc.v:150723.3-150732.6" + process $proc$libresoc.v:150723$7788 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$7467 $1\src_r1$next[63:0]$7468 - attribute \src "libresoc.v:140911.5-140911.29" + assign $0\src_r1$next[63:0]$7789 $1\src_r1$next[63:0]$7790 + attribute \src "libresoc.v:150724.5-150724.29" switch \initial - attribute \src "libresoc.v:140911.9-140911.17" + attribute \src "libresoc.v:150724.9-150724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$7468 \src_or_imm + assign $1\src_r1$next[63:0]$7790 \src_or_imm case - assign $1\src_r1$next[63:0]$7468 \src_r1 + assign $1\src_r1$next[63:0]$7790 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$7467 + update \src_r1$next $0\src_r1$next[63:0]$7789 end - attribute \src "libresoc.v:140920.3-140929.6" - process $proc$libresoc.v:140920$7469 + attribute \src "libresoc.v:150733.3-150742.6" + process $proc$libresoc.v:150733$7791 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$7470 $1\src_r2$next[0:0]$7471 - attribute \src "libresoc.v:140921.5-140921.29" + assign $0\src_r2$next[0:0]$7792 $1\src_r2$next[0:0]$7793 + attribute \src "libresoc.v:150734.5-150734.29" switch \initial - attribute \src "libresoc.v:140921.9-140921.17" + attribute \src "libresoc.v:150734.9-150734.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$7471 \src3_i + assign $1\src_r2$next[0:0]$7793 \src3_i case - assign $1\src_r2$next[0:0]$7471 \src_r2 + assign $1\src_r2$next[0:0]$7793 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$7470 + update \src_r2$next $0\src_r2$next[0:0]$7792 end - attribute \src "libresoc.v:140930.3-140938.6" - process $proc$libresoc.v:140930$7472 + attribute \src "libresoc.v:150743.3-150751.6" + process $proc$libresoc.v:150743$7794 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7473 $1\alui_l_r_alui$next[0:0]$7474 - attribute \src "libresoc.v:140931.5-140931.29" + assign $0\alui_l_r_alui$next[0:0]$7795 $1\alui_l_r_alui$next[0:0]$7796 + attribute \src "libresoc.v:150744.5-150744.29" switch \initial - attribute \src "libresoc.v:140931.9-140931.17" + attribute \src "libresoc.v:150744.9-150744.17" case 1'1 case end @@ -297718,21 +316555,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7474 1'1 + assign $1\alui_l_r_alui$next[0:0]$7796 1'1 case - assign $1\alui_l_r_alui$next[0:0]$7474 \$88 + assign $1\alui_l_r_alui$next[0:0]$7796 \$88 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7473 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7795 end - attribute \src "libresoc.v:140939.3-140947.6" - process $proc$libresoc.v:140939$7475 + attribute \src "libresoc.v:150752.3-150760.6" + process $proc$libresoc.v:150752$7797 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7476 $1\alu_l_r_alu$next[0:0]$7477 - attribute \src "libresoc.v:140940.5-140940.29" + assign $0\alu_l_r_alu$next[0:0]$7798 $1\alu_l_r_alu$next[0:0]$7799 + attribute \src "libresoc.v:150753.5-150753.29" switch \initial - attribute \src "libresoc.v:140940.9-140940.17" + attribute \src "libresoc.v:150753.9-150753.17" case 1'1 case end @@ -297741,21 +316578,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7477 1'1 + assign $1\alu_l_r_alu$next[0:0]$7799 1'1 case - assign $1\alu_l_r_alu$next[0:0]$7477 \$90 + assign $1\alu_l_r_alu$next[0:0]$7799 \$90 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7476 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7798 end - attribute \src "libresoc.v:140948.3-140957.6" - process $proc$libresoc.v:140948$7478 + attribute \src "libresoc.v:150761.3-150770.6" + process $proc$libresoc.v:150761$7800 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:140949.5-140949.29" + attribute \src "libresoc.v:150762.5-150762.29" switch \initial - attribute \src "libresoc.v:140949.9-140949.17" + attribute \src "libresoc.v:150762.9-150762.17" case 1'1 case end @@ -297771,14 +316608,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:140958.3-140967.6" - process $proc$libresoc.v:140958$7479 + attribute \src "libresoc.v:150771.3-150780.6" + process $proc$libresoc.v:150771$7801 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:140959.5-140959.29" + attribute \src "libresoc.v:150772.5-150772.29" switch \initial - attribute \src "libresoc.v:140959.9-140959.17" + attribute \src "libresoc.v:150772.9-150772.17" case 1'1 case end @@ -297794,14 +316631,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:140968.3-140977.6" - process $proc$libresoc.v:140968$7480 + attribute \src "libresoc.v:150781.3-150790.6" + process $proc$libresoc.v:150781$7802 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:140969.5-140969.29" + attribute \src "libresoc.v:150782.5-150782.29" switch \initial - attribute \src "libresoc.v:140969.9-140969.17" + attribute \src "libresoc.v:150782.9-150782.17" case 1'1 case end @@ -297817,14 +316654,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:140978.3-140987.6" - process $proc$libresoc.v:140978$7481 + attribute \src "libresoc.v:150791.3-150800.6" + process $proc$libresoc.v:150791$7803 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:140979.5-140979.29" + attribute \src "libresoc.v:150792.5-150792.29" switch \initial - attribute \src "libresoc.v:140979.9-140979.17" + attribute \src "libresoc.v:150792.9-150792.17" case 1'1 case end @@ -297840,14 +316677,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:140988.3-140996.6" - process $proc$libresoc.v:140988$7482 + attribute \src "libresoc.v:150801.3-150809.6" + process $proc$libresoc.v:150801$7804 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$7483 $1\prev_wr_go$next[3:0]$7484 - attribute \src "libresoc.v:140989.5-140989.29" + assign $0\prev_wr_go$next[3:0]$7805 $1\prev_wr_go$next[3:0]$7806 + attribute \src "libresoc.v:150802.5-150802.29" switch \initial - attribute \src "libresoc.v:140989.9-140989.17" + attribute \src "libresoc.v:150802.9-150802.17" case 1'1 case end @@ -297856,73 +316693,73 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$7484 4'0000 - case - assign $1\prev_wr_go$next[3:0]$7484 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7483 - end - connect \$100 $and$libresoc.v:140464$7271_Y - connect \$102 $and$libresoc.v:140465$7272_Y - connect \$104 $and$libresoc.v:140466$7273_Y - connect \$106 $and$libresoc.v:140467$7274_Y - connect \$108 $and$libresoc.v:140468$7275_Y - connect \$10 $and$libresoc.v:140469$7276_Y - connect \$110 $and$libresoc.v:140470$7277_Y - connect \$112 $and$libresoc.v:140471$7278_Y - connect \$114 $and$libresoc.v:140472$7279_Y - connect \$116 $and$libresoc.v:140473$7280_Y - connect \$118 $and$libresoc.v:140474$7281_Y - connect \$120 $and$libresoc.v:140475$7282_Y - connect \$12 $not$libresoc.v:140476$7283_Y - connect \$14 $and$libresoc.v:140477$7284_Y - connect \$16 $not$libresoc.v:140478$7285_Y - connect \$18 $and$libresoc.v:140479$7286_Y - connect \$20 $and$libresoc.v:140480$7287_Y - connect \$24 $not$libresoc.v:140481$7288_Y - connect \$26 $and$libresoc.v:140482$7289_Y - connect \$23 $reduce_or$libresoc.v:140483$7290_Y - connect \$22 $not$libresoc.v:140484$7291_Y - connect \$2 $and$libresoc.v:140485$7292_Y - connect \$30 $and$libresoc.v:140486$7293_Y - connect \$32 $reduce_or$libresoc.v:140487$7294_Y - connect \$34 $reduce_or$libresoc.v:140488$7295_Y - connect \$36 $or$libresoc.v:140489$7296_Y - connect \$38 $not$libresoc.v:140490$7297_Y - connect \$40 $and$libresoc.v:140491$7298_Y - connect \$42 $and$libresoc.v:140492$7299_Y - connect \$44 $eq$libresoc.v:140493$7300_Y - connect \$46 $and$libresoc.v:140494$7301_Y - connect \$48 $eq$libresoc.v:140495$7302_Y - connect \$50 $and$libresoc.v:140496$7303_Y - connect \$52 $and$libresoc.v:140497$7304_Y - connect \$54 $and$libresoc.v:140498$7305_Y - connect \$56 $or$libresoc.v:140499$7306_Y - connect \$58 $or$libresoc.v:140500$7307_Y - connect \$5 $not$libresoc.v:140501$7308_Y - connect \$60 $or$libresoc.v:140502$7309_Y - connect \$62 $or$libresoc.v:140503$7310_Y - connect \$64 $and$libresoc.v:140504$7311_Y - connect \$66 $and$libresoc.v:140505$7312_Y - connect \$68 $or$libresoc.v:140506$7313_Y - connect \$70 $and$libresoc.v:140507$7314_Y - connect \$72 $and$libresoc.v:140508$7315_Y - connect \$74 $and$libresoc.v:140509$7316_Y - connect \$76 $and$libresoc.v:140510$7317_Y - connect \$78 $ternary$libresoc.v:140511$7318_Y - connect \$7 $or$libresoc.v:140512$7319_Y - connect \$80 $ternary$libresoc.v:140513$7320_Y - connect \$82 $ternary$libresoc.v:140514$7321_Y - connect \$84 $ternary$libresoc.v:140515$7322_Y - connect \$86 $ternary$libresoc.v:140516$7323_Y - connect \$88 $and$libresoc.v:140517$7324_Y - connect \$4 $reduce_and$libresoc.v:140518$7325_Y - connect \$90 $and$libresoc.v:140519$7326_Y - connect \$92 $and$libresoc.v:140520$7327_Y - connect \$94 $not$libresoc.v:140521$7328_Y - connect \$96 $and$libresoc.v:140522$7329_Y - connect \$98 $not$libresoc.v:140523$7330_Y + assign $1\prev_wr_go$next[3:0]$7806 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7806 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7805 + end + connect \$100 $and$libresoc.v:150277$7593_Y + connect \$102 $and$libresoc.v:150278$7594_Y + connect \$104 $and$libresoc.v:150279$7595_Y + connect \$106 $and$libresoc.v:150280$7596_Y + connect \$108 $and$libresoc.v:150281$7597_Y + connect \$10 $and$libresoc.v:150282$7598_Y + connect \$110 $and$libresoc.v:150283$7599_Y + connect \$112 $and$libresoc.v:150284$7600_Y + connect \$114 $and$libresoc.v:150285$7601_Y + connect \$116 $and$libresoc.v:150286$7602_Y + connect \$118 $and$libresoc.v:150287$7603_Y + connect \$120 $and$libresoc.v:150288$7604_Y + connect \$12 $not$libresoc.v:150289$7605_Y + connect \$14 $and$libresoc.v:150290$7606_Y + connect \$16 $not$libresoc.v:150291$7607_Y + connect \$18 $and$libresoc.v:150292$7608_Y + connect \$20 $and$libresoc.v:150293$7609_Y + connect \$24 $not$libresoc.v:150294$7610_Y + connect \$26 $and$libresoc.v:150295$7611_Y + connect \$23 $reduce_or$libresoc.v:150296$7612_Y + connect \$22 $not$libresoc.v:150297$7613_Y + connect \$2 $and$libresoc.v:150298$7614_Y + connect \$30 $and$libresoc.v:150299$7615_Y + connect \$32 $reduce_or$libresoc.v:150300$7616_Y + connect \$34 $reduce_or$libresoc.v:150301$7617_Y + connect \$36 $or$libresoc.v:150302$7618_Y + connect \$38 $not$libresoc.v:150303$7619_Y + connect \$40 $and$libresoc.v:150304$7620_Y + connect \$42 $and$libresoc.v:150305$7621_Y + connect \$44 $eq$libresoc.v:150306$7622_Y + connect \$46 $and$libresoc.v:150307$7623_Y + connect \$48 $eq$libresoc.v:150308$7624_Y + connect \$50 $and$libresoc.v:150309$7625_Y + connect \$52 $and$libresoc.v:150310$7626_Y + connect \$54 $and$libresoc.v:150311$7627_Y + connect \$56 $or$libresoc.v:150312$7628_Y + connect \$58 $or$libresoc.v:150313$7629_Y + connect \$5 $not$libresoc.v:150314$7630_Y + connect \$60 $or$libresoc.v:150315$7631_Y + connect \$62 $or$libresoc.v:150316$7632_Y + connect \$64 $and$libresoc.v:150317$7633_Y + connect \$66 $and$libresoc.v:150318$7634_Y + connect \$68 $or$libresoc.v:150319$7635_Y + connect \$70 $and$libresoc.v:150320$7636_Y + connect \$72 $and$libresoc.v:150321$7637_Y + connect \$74 $and$libresoc.v:150322$7638_Y + connect \$76 $and$libresoc.v:150323$7639_Y + connect \$78 $ternary$libresoc.v:150324$7640_Y + connect \$7 $or$libresoc.v:150325$7641_Y + connect \$80 $ternary$libresoc.v:150326$7642_Y + connect \$82 $ternary$libresoc.v:150327$7643_Y + connect \$84 $ternary$libresoc.v:150328$7644_Y + connect \$86 $ternary$libresoc.v:150329$7645_Y + connect \$88 $and$libresoc.v:150330$7646_Y + connect \$4 $reduce_and$libresoc.v:150331$7647_Y + connect \$90 $and$libresoc.v:150332$7648_Y + connect \$92 $and$libresoc.v:150333$7649_Y + connect \$94 $not$libresoc.v:150334$7650_Y + connect \$96 $and$libresoc.v:150335$7651_Y + connect \$98 $not$libresoc.v:150336$7652_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -297954,51 +316791,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:141031.1-141358.10" +attribute \src "libresoc.v:150844.1-151177.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:141325.18-141325.116" - wire $and$libresoc.v:141325$7525_Y - attribute \src "libresoc.v:141327.18-141327.116" - wire $and$libresoc.v:141327$7527_Y - attribute \src "libresoc.v:141328.18-141328.117" - wire $and$libresoc.v:141328$7528_Y - attribute \src "libresoc.v:141329.18-141329.117" - wire $and$libresoc.v:141329$7529_Y - attribute \src "libresoc.v:141332.18-141332.95" - wire width 65 $extend$libresoc.v:141332$7532_Y - attribute \src "libresoc.v:141333.18-141333.91" - wire width 65 $extend$libresoc.v:141333$7534_Y - attribute \src "libresoc.v:141335.18-141335.95" - wire width 65 $extend$libresoc.v:141335$7537_Y - attribute \src "libresoc.v:141336.18-141336.91" - wire width 65 $extend$libresoc.v:141336$7539_Y - attribute \src "libresoc.v:141332.18-141332.95" - wire width 65 $neg$libresoc.v:141332$7533_Y - attribute \src "libresoc.v:141335.18-141335.95" - wire width 65 $neg$libresoc.v:141335$7538_Y - attribute \src "libresoc.v:141333.18-141333.91" - wire width 65 $pos$libresoc.v:141333$7535_Y - attribute \src "libresoc.v:141336.18-141336.91" - wire width 65 $pos$libresoc.v:141336$7540_Y - attribute \src "libresoc.v:141324.18-141324.125" - wire $ternary$libresoc.v:141324$7524_Y - attribute \src "libresoc.v:141326.18-141326.125" - wire $ternary$libresoc.v:141326$7526_Y - attribute \src "libresoc.v:141334.18-141334.112" - wire width 65 $ternary$libresoc.v:141334$7536_Y - attribute \src "libresoc.v:141337.18-141337.112" - wire width 65 $ternary$libresoc.v:141337$7541_Y - attribute \src "libresoc.v:141338.18-141338.116" - wire width 32 $ternary$libresoc.v:141338$7542_Y - attribute \src "libresoc.v:141339.18-141339.116" - wire width 32 $ternary$libresoc.v:141339$7543_Y - attribute \src "libresoc.v:141330.18-141330.106" - wire $xor$libresoc.v:141330$7530_Y - attribute \src "libresoc.v:141331.18-141331.110" - wire $xor$libresoc.v:141331$7531_Y + attribute \src "libresoc.v:151144.18-151144.116" + wire $and$libresoc.v:151144$7847_Y + attribute \src "libresoc.v:151146.18-151146.116" + wire $and$libresoc.v:151146$7849_Y + attribute \src "libresoc.v:151147.18-151147.117" + wire $and$libresoc.v:151147$7850_Y + attribute \src "libresoc.v:151148.18-151148.117" + wire $and$libresoc.v:151148$7851_Y + attribute \src "libresoc.v:151151.18-151151.95" + wire width 65 $extend$libresoc.v:151151$7854_Y + attribute \src "libresoc.v:151152.18-151152.91" + wire width 65 $extend$libresoc.v:151152$7856_Y + attribute \src "libresoc.v:151154.18-151154.95" + wire width 65 $extend$libresoc.v:151154$7859_Y + attribute \src "libresoc.v:151155.18-151155.91" + wire width 65 $extend$libresoc.v:151155$7861_Y + attribute \src "libresoc.v:151151.18-151151.95" + wire width 65 $neg$libresoc.v:151151$7855_Y + attribute \src "libresoc.v:151154.18-151154.95" + wire width 65 $neg$libresoc.v:151154$7860_Y + attribute \src "libresoc.v:151152.18-151152.91" + wire width 65 $pos$libresoc.v:151152$7857_Y + attribute \src "libresoc.v:151155.18-151155.91" + wire width 65 $pos$libresoc.v:151155$7862_Y + attribute \src "libresoc.v:151143.18-151143.125" + wire $ternary$libresoc.v:151143$7846_Y + attribute \src "libresoc.v:151145.18-151145.125" + wire $ternary$libresoc.v:151145$7848_Y + attribute \src "libresoc.v:151153.18-151153.112" + wire width 65 $ternary$libresoc.v:151153$7858_Y + attribute \src "libresoc.v:151156.18-151156.112" + wire width 65 $ternary$libresoc.v:151156$7863_Y + attribute \src "libresoc.v:151157.18-151157.116" + wire width 32 $ternary$libresoc.v:151157$7864_Y + attribute \src "libresoc.v:151158.18-151158.116" + wire width 32 $ternary$libresoc.v:151158$7865_Y + attribute \src "libresoc.v:151149.18-151149.106" + wire $xor$libresoc.v:151149$7852_Y + attribute \src "libresoc.v:151150.18-151150.110" + wire $xor$libresoc.v:151150$7853_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -298031,9 +316868,9 @@ module \mul1 wire width 65 \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" wire width 65 \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" wire width 32 \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" wire width 32 \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" wire width 64 \abs_a @@ -298042,35 +316879,39 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" wire \is_32bit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -298157,6 +316998,7 @@ module \mul1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -298233,6 +317075,7 @@ module \mul1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -298263,9 +317106,9 @@ module \mul1 wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 34 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 16 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire output 32 \neg_res @@ -298292,7 +317135,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:141325$7525 + cell $and $and$libresoc.v:151144$7847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298300,10 +317143,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:141325$7525_Y + connect \Y $and$libresoc.v:151144$7847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:141327$7527 + cell $and $and$libresoc.v:151146$7849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298311,10 +317154,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:141327$7527_Y + connect \Y $and$libresoc.v:151146$7849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:141328$7528 + cell $and $and$libresoc.v:151147$7850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298322,10 +317165,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:141328$7528_Y + connect \Y $and$libresoc.v:151147$7850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:141329$7529 + cell $and $and$libresoc.v:151148$7851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298333,122 +317176,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:141329$7529_Y + connect \Y $and$libresoc.v:151148$7851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:141332$7532 + cell $pos $extend$libresoc.v:151151$7854 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:141332$7532_Y + connect \Y $extend$libresoc.v:151151$7854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:141333$7534 + cell $pos $extend$libresoc.v:151152$7856 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:141333$7534_Y + connect \Y $extend$libresoc.v:151152$7856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:141335$7537 + cell $pos $extend$libresoc.v:151154$7859 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:141335$7537_Y + connect \Y $extend$libresoc.v:151154$7859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:141336$7539 + cell $pos $extend$libresoc.v:151155$7861 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:141336$7539_Y + connect \Y $extend$libresoc.v:151155$7861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:141332$7533 + cell $neg $neg$libresoc.v:151151$7855 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:141332$7532_Y - connect \Y $neg$libresoc.v:141332$7533_Y + connect \A $extend$libresoc.v:151151$7854_Y + connect \Y $neg$libresoc.v:151151$7855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:141335$7538 + cell $neg $neg$libresoc.v:151154$7860 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:141335$7537_Y - connect \Y $neg$libresoc.v:141335$7538_Y + connect \A $extend$libresoc.v:151154$7859_Y + connect \Y $neg$libresoc.v:151154$7860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:141333$7535 + cell $pos $pos$libresoc.v:151152$7857 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:141333$7534_Y - connect \Y $pos$libresoc.v:141333$7535_Y + connect \A $extend$libresoc.v:151152$7856_Y + connect \Y $pos$libresoc.v:151152$7857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:141336$7540 + cell $pos $pos$libresoc.v:151155$7862 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:141336$7539_Y - connect \Y $pos$libresoc.v:141336$7540_Y + connect \A $extend$libresoc.v:151155$7861_Y + connect \Y $pos$libresoc.v:151155$7862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:141324$7524 + cell $mux $ternary$libresoc.v:151143$7846 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:141324$7524_Y + connect \Y $ternary$libresoc.v:151143$7846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:141326$7526 + cell $mux $ternary$libresoc.v:151145$7848 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:141326$7526_Y + connect \Y $ternary$libresoc.v:151145$7848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:141334$7536 + cell $mux $ternary$libresoc.v:151153$7858 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:141334$7536_Y + connect \Y $ternary$libresoc.v:151153$7858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:141337$7541 + cell $mux $ternary$libresoc.v:151156$7863 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:141337$7541_Y + connect \Y $ternary$libresoc.v:151156$7863_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:141338$7542 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:151157$7864 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:141338$7542_Y + connect \Y $ternary$libresoc.v:151157$7864_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:141339$7543 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:151158$7865 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:141339$7543_Y + connect \Y $ternary$libresoc.v:151158$7865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:141330$7530 + cell $xor $xor$libresoc.v:151149$7852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298456,10 +317299,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:141330$7530_Y + connect \Y $xor$libresoc.v:151149$7852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:141331$7531 + cell $xor $xor$libresoc.v:151150$7853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298467,24 +317310,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:141331$7531_Y - end - connect \$17 $ternary$libresoc.v:141324$7524_Y - connect \$19 $and$libresoc.v:141325$7525_Y - connect \$21 $ternary$libresoc.v:141326$7526_Y - connect \$23 $and$libresoc.v:141327$7527_Y - connect \$25 $and$libresoc.v:141328$7528_Y - connect \$27 $and$libresoc.v:141329$7529_Y - connect \$29 $xor$libresoc.v:141330$7530_Y - connect \$31 $xor$libresoc.v:141331$7531_Y - connect \$34 $neg$libresoc.v:141332$7533_Y - connect \$36 $pos$libresoc.v:141333$7535_Y - connect \$38 $ternary$libresoc.v:141334$7536_Y - connect \$41 $neg$libresoc.v:141335$7538_Y - connect \$43 $pos$libresoc.v:141336$7540_Y - connect \$45 $ternary$libresoc.v:141337$7541_Y - connect \$47 $ternary$libresoc.v:141338$7542_Y - connect \$49 $ternary$libresoc.v:141339$7543_Y + connect \Y $xor$libresoc.v:151150$7853_Y + end + connect \$17 $ternary$libresoc.v:151143$7846_Y + connect \$19 $and$libresoc.v:151144$7847_Y + connect \$21 $ternary$libresoc.v:151145$7848_Y + connect \$23 $and$libresoc.v:151146$7849_Y + connect \$25 $and$libresoc.v:151147$7850_Y + connect \$27 $and$libresoc.v:151148$7851_Y + connect \$29 $xor$libresoc.v:151149$7852_Y + connect \$31 $xor$libresoc.v:151150$7853_Y + connect \$34 $neg$libresoc.v:151151$7855_Y + connect \$36 $pos$libresoc.v:151152$7857_Y + connect \$38 $ternary$libresoc.v:151153$7858_Y + connect \$41 $neg$libresoc.v:151154$7860_Y + connect \$43 $pos$libresoc.v:151155$7862_Y + connect \$45 $ternary$libresoc.v:151156$7863_Y + connect \$47 $ternary$libresoc.v:151157$7864_Y + connect \$49 $ternary$libresoc.v:151158$7865_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -298504,51 +317347,55 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:141362.1-141619.10" +attribute \src "libresoc.v:151181.1-151444.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:141612.18-141612.98" - wire width 129 $extend$libresoc.v:141612$7545_Y - attribute \src "libresoc.v:141611.18-141611.99" - wire width 128 $mul$libresoc.v:141611$7544_Y - attribute \src "libresoc.v:141612.18-141612.98" - wire width 129 $pos$libresoc.v:141612$7546_Y + attribute \src "libresoc.v:151437.18-151437.98" + wire width 129 $extend$libresoc.v:151437$7867_Y + attribute \src "libresoc.v:151436.18-151436.99" + wire width 128 $mul$libresoc.v:151436$7866_Y + attribute \src "libresoc.v:151437.18-151437.98" + wire width 129 $pos$libresoc.v:151437$7868_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 128 \$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 20 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -298635,6 +317482,7 @@ module \mul2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -298711,6 +317559,7 @@ module \mul2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 19 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -298741,9 +317590,9 @@ module \mul2 wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 35 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 18 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire input 16 \neg_res @@ -298764,15 +317613,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:141612$7545 + cell $pos $extend$libresoc.v:151437$7867 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:141612$7545_Y + connect \Y $extend$libresoc.v:151437$7867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:141611$7544 + cell $mul $mul$libresoc.v:151436$7866 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -298780,18 +317629,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:141611$7544_Y + connect \Y $mul$libresoc.v:151436$7866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:141612$7546 + cell $pos $pos$libresoc.v:151437$7868 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:141612$7545_Y - connect \Y $pos$libresoc.v:141612$7546_Y + connect \A $extend$libresoc.v:151437$7867_Y + connect \Y $pos$libresoc.v:151437$7868_Y end - connect \$18 $mul$libresoc.v:141611$7544_Y - connect \$17 $pos$libresoc.v:141612$7546_Y + connect \$18 $mul$libresoc.v:151436$7866_Y + connect \$17 $pos$libresoc.v:151437$7868_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -298799,65 +317648,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:141623.1-142002.10" +attribute \src "libresoc.v:151448.1-151833.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:141624.7-141624.20" + attribute \src "libresoc.v:151449.7-151449.20" wire $0\initial[0:0] - attribute \src "libresoc.v:141955.3-141973.6" + attribute \src "libresoc.v:151786.3-151804.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:141917.3-141935.6" - wire width 64 $0\o$14[63:0]$7563 - attribute \src "libresoc.v:141936.3-141954.6" + attribute \src "libresoc.v:151748.3-151766.6" + wire width 64 $0\o$14[63:0]$7885 + attribute \src "libresoc.v:151767.3-151785.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:141974.3-141984.6" + attribute \src "libresoc.v:151805.3-151815.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:141985.3-141995.6" + attribute \src "libresoc.v:151816.3-151826.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:141955.3-141973.6" + attribute \src "libresoc.v:151786.3-151804.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:141917.3-141935.6" - wire width 64 $1\o$14[63:0]$7564 - attribute \src "libresoc.v:141936.3-141954.6" + attribute \src "libresoc.v:151748.3-151766.6" + wire width 64 $1\o$14[63:0]$7886 + attribute \src "libresoc.v:151767.3-151785.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:141974.3-141984.6" + attribute \src "libresoc.v:151805.3-151815.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:141985.3-141995.6" + attribute \src "libresoc.v:151816.3-151826.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:141955.3-141973.6" + attribute \src "libresoc.v:151786.3-151804.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:141911.18-141911.104" - wire $and$libresoc.v:141911$7555_Y - attribute \src "libresoc.v:141915.18-141915.104" - wire $and$libresoc.v:141915$7559_Y - attribute \src "libresoc.v:141905.18-141905.95" - wire width 130 $extend$libresoc.v:141905$7547_Y - attribute \src "libresoc.v:141906.18-141906.90" - wire width 130 $extend$libresoc.v:141906$7549_Y - attribute \src "libresoc.v:141916.18-141916.95" - wire width 2 $extend$libresoc.v:141916$7560_Y - attribute \src "libresoc.v:141905.18-141905.95" - wire width 130 $neg$libresoc.v:141905$7548_Y - attribute \src "libresoc.v:141910.18-141910.98" - wire $not$libresoc.v:141910$7554_Y - attribute \src "libresoc.v:141914.18-141914.98" - wire $not$libresoc.v:141914$7558_Y - attribute \src "libresoc.v:141906.18-141906.90" - wire width 130 $pos$libresoc.v:141906$7550_Y - attribute \src "libresoc.v:141916.18-141916.95" - wire width 2 $pos$libresoc.v:141916$7561_Y - attribute \src "libresoc.v:141909.18-141909.106" - wire $reduce_and$libresoc.v:141909$7553_Y - attribute \src "libresoc.v:141913.18-141913.107" - wire $reduce_and$libresoc.v:141913$7557_Y - attribute \src "libresoc.v:141908.18-141908.106" - wire $reduce_or$libresoc.v:141908$7552_Y - attribute \src "libresoc.v:141912.18-141912.107" - wire $reduce_or$libresoc.v:141912$7556_Y - attribute \src "libresoc.v:141907.18-141907.114" - wire width 130 $ternary$libresoc.v:141907$7551_Y + attribute \src "libresoc.v:151742.18-151742.104" + wire $and$libresoc.v:151742$7877_Y + attribute \src "libresoc.v:151746.18-151746.104" + wire $and$libresoc.v:151746$7881_Y + attribute \src "libresoc.v:151736.18-151736.95" + wire width 130 $extend$libresoc.v:151736$7869_Y + attribute \src "libresoc.v:151737.18-151737.90" + wire width 130 $extend$libresoc.v:151737$7871_Y + attribute \src "libresoc.v:151747.18-151747.95" + wire width 2 $extend$libresoc.v:151747$7882_Y + attribute \src "libresoc.v:151736.18-151736.95" + wire width 130 $neg$libresoc.v:151736$7870_Y + attribute \src "libresoc.v:151741.18-151741.98" + wire $not$libresoc.v:151741$7876_Y + attribute \src "libresoc.v:151745.18-151745.98" + wire $not$libresoc.v:151745$7880_Y + attribute \src "libresoc.v:151737.18-151737.90" + wire width 130 $pos$libresoc.v:151737$7872_Y + attribute \src "libresoc.v:151747.18-151747.95" + wire width 2 $pos$libresoc.v:151747$7883_Y + attribute \src "libresoc.v:151740.18-151740.106" + wire $reduce_and$libresoc.v:151740$7875_Y + attribute \src "libresoc.v:151744.18-151744.107" + wire $reduce_and$libresoc.v:151744$7879_Y + attribute \src "libresoc.v:151739.18-151739.106" + wire $reduce_or$libresoc.v:151739$7874_Y + attribute \src "libresoc.v:151743.18-151743.107" + wire $reduce_or$libresoc.v:151743$7878_Y + attribute \src "libresoc.v:151738.18-151738.114" + wire width 130 $ternary$libresoc.v:151738$7873_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -298884,42 +317733,46 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:141624.7-141624.15" + attribute \src "libresoc.v:151449.7-151449.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" wire width 129 \mul_o attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -299006,6 +317859,7 @@ module \mul3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -299082,6 +317936,7 @@ module \mul3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -299114,9 +317969,9 @@ module \mul3 wire output 25 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" wire \mul_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 35 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 16 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire input 15 \neg_res @@ -299137,7 +317992,7 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:141911$7555 + cell $and $and$libresoc.v:151742$7877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299145,10 +318000,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:141911$7555_Y + connect \Y $and$libresoc.v:151742$7877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:141915$7559 + cell $and $and$libresoc.v:151746$7881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299156,128 +318011,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:141915$7559_Y + connect \Y $and$libresoc.v:151746$7881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:141905$7547 + cell $pos $extend$libresoc.v:151736$7869 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:141905$7547_Y + connect \Y $extend$libresoc.v:151736$7869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:141906$7549 + cell $pos $extend$libresoc.v:151737$7871 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:141906$7549_Y + connect \Y $extend$libresoc.v:151737$7871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:141916$7560 + cell $pos $extend$libresoc.v:151747$7882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:141916$7560_Y + connect \Y $extend$libresoc.v:151747$7882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:141905$7548 + cell $neg $neg$libresoc.v:151736$7870 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:141905$7547_Y - connect \Y $neg$libresoc.v:141905$7548_Y + connect \A $extend$libresoc.v:151736$7869_Y + connect \Y $neg$libresoc.v:151736$7870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:141910$7554 + cell $not $not$libresoc.v:151741$7876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:141910$7554_Y + connect \Y $not$libresoc.v:151741$7876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:141914$7558 + cell $not $not$libresoc.v:151745$7880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:141914$7558_Y + connect \Y $not$libresoc.v:151745$7880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:141906$7550 + cell $pos $pos$libresoc.v:151737$7872 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:141906$7549_Y - connect \Y $pos$libresoc.v:141906$7550_Y + connect \A $extend$libresoc.v:151737$7871_Y + connect \Y $pos$libresoc.v:151737$7872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:141916$7561 + cell $pos $pos$libresoc.v:151747$7883 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:141916$7560_Y - connect \Y $pos$libresoc.v:141916$7561_Y + connect \A $extend$libresoc.v:151747$7882_Y + connect \Y $pos$libresoc.v:151747$7883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:141909$7553 + cell $reduce_and $reduce_and$libresoc.v:151740$7875 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:141909$7553_Y + connect \Y $reduce_and$libresoc.v:151740$7875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:141913$7557 + cell $reduce_and $reduce_and$libresoc.v:151744$7879 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:141913$7557_Y + connect \Y $reduce_and$libresoc.v:151744$7879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:141908$7552 + cell $reduce_or $reduce_or$libresoc.v:151739$7874 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:141908$7552_Y + connect \Y $reduce_or$libresoc.v:151739$7874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:141912$7556 + cell $reduce_or $reduce_or$libresoc.v:151743$7878 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:141912$7556_Y + connect \Y $reduce_or$libresoc.v:151743$7878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:141907$7551 + cell $mux $ternary$libresoc.v:151738$7873 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:141907$7551_Y + connect \Y $ternary$libresoc.v:151738$7873_Y end - attribute \src "libresoc.v:141624.7-141624.20" - process $proc$libresoc.v:141624$7569 + attribute \src "libresoc.v:151449.7-151449.20" + process $proc$libresoc.v:151449$7891 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141917.3-141935.6" - process $proc$libresoc.v:141917$7562 + attribute \src "libresoc.v:151748.3-151766.6" + process $proc$libresoc.v:151748$7884 assign { } { } assign { } { } - assign $0\o$14[63:0]$7563 $1\o$14[63:0]$7564 - attribute \src "libresoc.v:141918.5-141918.29" + assign $0\o$14[63:0]$7885 $1\o$14[63:0]$7886 + attribute \src "libresoc.v:151749.5-151749.29" switch \initial - attribute \src "libresoc.v:141918.9-141918.17" + attribute \src "libresoc.v:151749.9-151749.17" case 1'1 case end @@ -299286,29 +318141,29 @@ module \mul3 attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } - assign $1\o$14[63:0]$7564 { \mul_o [63:32] \mul_o [63:32] } + assign $1\o$14[63:0]$7886 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } - assign $1\o$14[63:0]$7564 \mul_o [127:64] + assign $1\o$14[63:0]$7886 \mul_o [127:64] attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } - assign $1\o$14[63:0]$7564 \mul_o [63:0] + assign $1\o$14[63:0]$7886 \mul_o [63:0] case - assign $1\o$14[63:0]$7564 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o$14[63:0]$7886 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$14 $0\o$14[63:0]$7563 + update \o$14 $0\o$14[63:0]$7885 end - attribute \src "libresoc.v:141936.3-141954.6" - process $proc$libresoc.v:141936$7565 + attribute \src "libresoc.v:151767.3-151785.6" + process $proc$libresoc.v:151767$7887 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:141937.5-141937.29" + attribute \src "libresoc.v:151768.5-151768.29" switch \initial - attribute \src "libresoc.v:141937.9-141937.17" + attribute \src "libresoc.v:151768.9-151768.17" case 1'1 case end @@ -299332,14 +318187,14 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:141955.3-141973.6" - process $proc$libresoc.v:141955$7566 + attribute \src "libresoc.v:151786.3-151804.6" + process $proc$libresoc.v:151786$7888 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:141956.5-141956.29" + attribute \src "libresoc.v:151787.5-151787.29" switch \initial - attribute \src "libresoc.v:141956.9-141956.17" + attribute \src "libresoc.v:151787.9-151787.17" case 1'1 case end @@ -299366,14 +318221,14 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:141974.3-141984.6" - process $proc$libresoc.v:141974$7567 + attribute \src "libresoc.v:151805.3-151815.6" + process $proc$libresoc.v:151805$7889 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:141975.5-141975.29" + attribute \src "libresoc.v:151806.5-151806.29" switch \initial - attribute \src "libresoc.v:141975.9-141975.17" + attribute \src "libresoc.v:151806.9-151806.17" case 1'1 case end @@ -299389,14 +318244,14 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:141985.3-141995.6" - process $proc$libresoc.v:141985$7568 + attribute \src "libresoc.v:151816.3-151826.6" + process $proc$libresoc.v:151816$7890 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:141986.5-141986.29" + attribute \src "libresoc.v:151817.5-151817.29" switch \initial - attribute \src "libresoc.v:141986.9-141986.17" + attribute \src "libresoc.v:151817.9-151817.17" case 1'1 case end @@ -299412,18 +318267,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:141905$7548_Y - connect \$19 $pos$libresoc.v:141906$7550_Y - connect \$21 $ternary$libresoc.v:141907$7551_Y - connect \$23 $reduce_or$libresoc.v:141908$7552_Y - connect \$26 $reduce_and$libresoc.v:141909$7553_Y - connect \$25 $not$libresoc.v:141910$7554_Y - connect \$29 $and$libresoc.v:141911$7555_Y - connect \$31 $reduce_or$libresoc.v:141912$7556_Y - connect \$34 $reduce_and$libresoc.v:141913$7557_Y - connect \$33 $not$libresoc.v:141914$7558_Y - connect \$37 $and$libresoc.v:141915$7559_Y - connect \$39 $pos$libresoc.v:141916$7561_Y + connect \$17 $neg$libresoc.v:151736$7870_Y + connect \$19 $pos$libresoc.v:151737$7872_Y + connect \$21 $ternary$libresoc.v:151738$7873_Y + connect \$23 $reduce_or$libresoc.v:151739$7874_Y + connect \$26 $reduce_and$libresoc.v:151740$7875_Y + connect \$25 $not$libresoc.v:151741$7876_Y + connect \$29 $and$libresoc.v:151742$7877_Y + connect \$31 $reduce_or$libresoc.v:151743$7878_Y + connect \$34 $reduce_and$libresoc.v:151744$7879_Y + connect \$33 $not$libresoc.v:151745$7880_Y + connect \$37 $and$libresoc.v:151746$7881_Y + connect \$39 $pos$libresoc.v:151747$7883_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -299431,219 +318286,223 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:142006.1-143202.10" +attribute \src "libresoc.v:151837.1-153054.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:142007.7-142007.20" + attribute \src "libresoc.v:151838.7-151838.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 12 $0\mul_op__fn_unit$next[11:0]$7598 - attribute \src "libresoc.v:142944.3-142945.47" - wire width 12 $0\mul_op__fn_unit[11:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7599 - attribute \src "libresoc.v:142946.3-142947.61" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 14 $0\mul_op__fn_unit$next[13:0]$7920 + attribute \src "libresoc.v:152796.3-152797.47" + wire width 14 $0\mul_op__fn_unit[13:0] + attribute \src "libresoc.v:152931.3-152966.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7921 + attribute \src "libresoc.v:152798.3-152799.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7600 - attribute \src "libresoc.v:142948.3-142949.57" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7922 + attribute \src "libresoc.v:152800.3-152801.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 32 $0\mul_op__insn$next[31:0]$7601 - attribute \src "libresoc.v:142964.3-142965.41" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 32 $0\mul_op__insn$next[31:0]$7923 + attribute \src "libresoc.v:152816.3-152817.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7602 - attribute \src "libresoc.v:142942.3-142943.51" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7924 + attribute \src "libresoc.v:152794.3-152795.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $0\mul_op__is_32bit$next[0:0]$7603 - attribute \src "libresoc.v:142960.3-142961.49" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__is_32bit$next[0:0]$7925 + attribute \src "libresoc.v:152812.3-152813.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $0\mul_op__is_signed$next[0:0]$7604 - attribute \src "libresoc.v:142962.3-142963.51" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__is_signed$next[0:0]$7926 + attribute \src "libresoc.v:152814.3-152815.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $0\mul_op__oe__oe$next[0:0]$7605 - attribute \src "libresoc.v:142954.3-142955.45" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__oe__oe$next[0:0]$7927 + attribute \src "libresoc.v:152806.3-152807.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $0\mul_op__oe__ok$next[0:0]$7606 - attribute \src "libresoc.v:142956.3-142957.45" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__oe__ok$next[0:0]$7928 + attribute \src "libresoc.v:152808.3-152809.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $0\mul_op__rc__ok$next[0:0]$7607 - attribute \src "libresoc.v:142952.3-142953.45" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__rc__ok$next[0:0]$7929 + attribute \src "libresoc.v:152804.3-152805.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $0\mul_op__rc__rc$next[0:0]$7608 - attribute \src "libresoc.v:142950.3-142951.45" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__rc__rc$next[0:0]$7930 + attribute \src "libresoc.v:152802.3-152803.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $0\mul_op__write_cr0$next[0:0]$7609 - attribute \src "libresoc.v:142958.3-142959.51" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__write_cr0$next[0:0]$7931 + attribute \src "libresoc.v:152810.3-152811.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:143066.3-143078.6" - wire width 2 $0\muxid$next[1:0]$7595 - attribute \src "libresoc.v:142966.3-142967.27" + attribute \src "libresoc.v:152918.3-152930.6" + wire width 2 $0\muxid$next[1:0]$7917 + attribute \src "libresoc.v:152818.3-152819.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:143154.3-143166.6" - wire $0\neg_res$next[0:0]$7638 - attribute \src "libresoc.v:143167.3-143179.6" - wire $0\neg_res32$next[0:0]$7641 - attribute \src "libresoc.v:142932.3-142933.35" + attribute \src "libresoc.v:153006.3-153018.6" + wire $0\neg_res$next[0:0]$7960 + attribute \src "libresoc.v:153019.3-153031.6" + wire $0\neg_res32$next[0:0]$7963 + attribute \src "libresoc.v:152784.3-152785.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:142934.3-142935.31" + attribute \src "libresoc.v:152786.3-152787.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:143048.3-143065.6" - wire $0\r_busy$next[0:0]$7591 - attribute \src "libresoc.v:142968.3-142969.29" + attribute \src "libresoc.v:152900.3-152917.6" + wire $0\r_busy$next[0:0]$7913 + attribute \src "libresoc.v:152820.3-152821.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:143115.3-143127.6" - wire width 64 $0\ra$next[63:0]$7629 - attribute \src "libresoc.v:142940.3-142941.21" + attribute \src "libresoc.v:152967.3-152979.6" + wire width 64 $0\ra$next[63:0]$7951 + attribute \src "libresoc.v:152792.3-152793.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:143128.3-143140.6" - wire width 64 $0\rb$next[63:0]$7632 - attribute \src "libresoc.v:142938.3-142939.21" + attribute \src "libresoc.v:152980.3-152992.6" + wire width 64 $0\rb$next[63:0]$7954 + attribute \src "libresoc.v:152790.3-152791.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:143141.3-143153.6" - wire $0\xer_so$next[0:0]$7635 - attribute \src "libresoc.v:142936.3-142937.29" + attribute \src "libresoc.v:152993.3-153005.6" + wire $0\xer_so$next[0:0]$7957 + attribute \src "libresoc.v:152788.3-152789.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 12 $1\mul_op__fn_unit$next[11:0]$7610 - attribute \src "libresoc.v:142509.14-142509.39" - wire width 12 $1\mul_op__fn_unit[11:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7611 - attribute \src "libresoc.v:142544.14-142544.59" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 14 $1\mul_op__fn_unit$next[13:0]$7932 + attribute \src "libresoc.v:152354.14-152354.40" + wire width 14 $1\mul_op__fn_unit[13:0] + attribute \src "libresoc.v:152931.3-152966.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7933 + attribute \src "libresoc.v:152393.14-152393.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7612 - attribute \src "libresoc.v:142553.7-142553.34" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7934 + attribute \src "libresoc.v:152402.7-152402.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 32 $1\mul_op__insn$next[31:0]$7613 - attribute \src "libresoc.v:142562.14-142562.34" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 32 $1\mul_op__insn$next[31:0]$7935 + attribute \src "libresoc.v:152411.14-152411.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7614 - attribute \src "libresoc.v:142645.13-142645.38" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7936 + attribute \src "libresoc.v:152495.13-152495.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $1\mul_op__is_32bit$next[0:0]$7615 - attribute \src "libresoc.v:142802.7-142802.30" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__is_32bit$next[0:0]$7937 + attribute \src "libresoc.v:152654.7-152654.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $1\mul_op__is_signed$next[0:0]$7616 - attribute \src "libresoc.v:142811.7-142811.31" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__is_signed$next[0:0]$7938 + attribute \src "libresoc.v:152663.7-152663.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $1\mul_op__oe__oe$next[0:0]$7617 - attribute \src "libresoc.v:142820.7-142820.28" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__oe__oe$next[0:0]$7939 + attribute \src "libresoc.v:152672.7-152672.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $1\mul_op__oe__ok$next[0:0]$7618 - attribute \src "libresoc.v:142829.7-142829.28" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__oe__ok$next[0:0]$7940 + attribute \src "libresoc.v:152681.7-152681.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $1\mul_op__rc__ok$next[0:0]$7619 - attribute \src "libresoc.v:142838.7-142838.28" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__rc__ok$next[0:0]$7941 + attribute \src "libresoc.v:152690.7-152690.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $1\mul_op__rc__rc$next[0:0]$7620 - attribute \src "libresoc.v:142847.7-142847.28" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__rc__rc$next[0:0]$7942 + attribute \src "libresoc.v:152699.7-152699.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire $1\mul_op__write_cr0$next[0:0]$7621 - attribute \src "libresoc.v:142856.7-142856.31" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__write_cr0$next[0:0]$7943 + attribute \src "libresoc.v:152708.7-152708.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:143066.3-143078.6" - wire width 2 $1\muxid$next[1:0]$7596 - attribute \src "libresoc.v:142865.13-142865.25" + attribute \src "libresoc.v:152918.3-152930.6" + wire width 2 $1\muxid$next[1:0]$7918 + attribute \src "libresoc.v:152717.13-152717.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:143154.3-143166.6" - wire $1\neg_res$next[0:0]$7639 - attribute \src "libresoc.v:143167.3-143179.6" - wire $1\neg_res32$next[0:0]$7642 - attribute \src "libresoc.v:142887.7-142887.23" + attribute \src "libresoc.v:153006.3-153018.6" + wire $1\neg_res$next[0:0]$7961 + attribute \src "libresoc.v:153019.3-153031.6" + wire $1\neg_res32$next[0:0]$7964 + attribute \src "libresoc.v:152739.7-152739.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:142880.7-142880.21" + attribute \src "libresoc.v:152732.7-152732.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:143048.3-143065.6" - wire $1\r_busy$next[0:0]$7592 - attribute \src "libresoc.v:142901.7-142901.20" + attribute \src "libresoc.v:152900.3-152917.6" + wire $1\r_busy$next[0:0]$7914 + attribute \src "libresoc.v:152753.7-152753.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:143115.3-143127.6" - wire width 64 $1\ra$next[63:0]$7630 - attribute \src "libresoc.v:142906.14-142906.39" + attribute \src "libresoc.v:152967.3-152979.6" + wire width 64 $1\ra$next[63:0]$7952 + attribute \src "libresoc.v:152758.14-152758.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:143128.3-143140.6" - wire width 64 $1\rb$next[63:0]$7633 - attribute \src "libresoc.v:142915.14-142915.39" + attribute \src "libresoc.v:152980.3-152992.6" + wire width 64 $1\rb$next[63:0]$7955 + attribute \src "libresoc.v:152767.14-152767.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:143141.3-143153.6" - wire $1\xer_so$next[0:0]$7636 - attribute \src "libresoc.v:142924.7-142924.20" + attribute \src "libresoc.v:152993.3-153005.6" + wire $1\xer_so$next[0:0]$7958 + attribute \src "libresoc.v:152776.7-152776.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:143079.3-143114.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7622 - attribute \src "libresoc.v:143079.3-143114.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7623 - attribute \src "libresoc.v:143079.3-143114.6" - wire $2\mul_op__oe__oe$next[0:0]$7624 - attribute \src "libresoc.v:143079.3-143114.6" - wire $2\mul_op__oe__ok$next[0:0]$7625 - attribute \src "libresoc.v:143079.3-143114.6" - wire $2\mul_op__rc__ok$next[0:0]$7626 - attribute \src "libresoc.v:143079.3-143114.6" - wire $2\mul_op__rc__rc$next[0:0]$7627 - attribute \src "libresoc.v:143048.3-143065.6" - wire $2\r_busy$next[0:0]$7593 - attribute \src "libresoc.v:142931.18-142931.118" - wire $and$libresoc.v:142931$7570_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7944 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7945 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__oe__oe$next[0:0]$7946 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__oe__ok$next[0:0]$7947 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__rc__ok$next[0:0]$7948 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__rc__rc$next[0:0]$7949 + attribute \src "libresoc.v:152900.3-152917.6" + wire $2\r_busy$next[0:0]$7915 + attribute \src "libresoc.v:152783.18-152783.118" + wire $and$libresoc.v:152783$7892_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:142007.7-142007.15" + attribute \src "libresoc.v:151838.7-151838.15" wire \initial attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_mul_op__fn_unit$19 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_mul_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -299730,6 +318589,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -299806,6 +318666,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_mul_op__insn_type$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -299836,9 +318697,9 @@ module \mul_pipe1 wire \input_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__write_cr0$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra @@ -299853,35 +318714,39 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so$32 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul1_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul1_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul1_mul_op__fn_unit$35 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul1_mul_op__fn_unit$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul1_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -299968,6 +318833,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul1_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -300044,6 +318910,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul1_mul_op__insn_type$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -300074,9 +318941,9 @@ module \mul_pipe1 wire \mul1_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__write_cr0$42 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul1_muxid$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \mul1_neg_res @@ -300095,52 +318962,58 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul1_xer_so$48 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 26 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 26 \mul_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -300239,6 +319112,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -300315,6 +319189,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 25 \mul_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -300391,6 +319266,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -300451,19 +319327,19 @@ module \mul_pipe1 wire \mul_op__write_cr0$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire output 20 \neg_res @@ -300477,17 +319353,17 @@ module \mul_pipe1 wire \neg_res32$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire \neg_res32$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 23 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 22 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 17 \ra @@ -300513,8 +319389,8 @@ module \mul_pipe1 wire \xer_so$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:142931$7570 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:152783$7892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300522,10 +319398,10 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:142931$7570_Y + connect \Y $and$libresoc.v:152783$7892_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:142970.14-143003.4" + attribute \src "libresoc.v:152822.14-152855.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 @@ -300561,7 +319437,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:143004.8-143039.4" + attribute \src "libresoc.v:152856.8-152891.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -300599,376 +319475,376 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:143040.10-143043.4" + attribute \src "libresoc.v:152892.10-152895.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:143044.10-143047.4" + attribute \src "libresoc.v:152896.10-152899.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:142007.7-142007.20" - process $proc$libresoc.v:142007$7643 + attribute \src "libresoc.v:151838.7-151838.20" + process $proc$libresoc.v:151838$7965 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142509.14-142509.39" - process $proc$libresoc.v:142509$7644 + attribute \src "libresoc.v:152354.14-152354.40" + process $proc$libresoc.v:152354$7966 assign { } { } - assign $1\mul_op__fn_unit[11:0] 12'000000000000 + assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \mul_op__fn_unit $1\mul_op__fn_unit[11:0] + update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:142544.14-142544.59" - process $proc$libresoc.v:142544$7645 + attribute \src "libresoc.v:152393.14-152393.59" + process $proc$libresoc.v:152393$7967 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:142553.7-142553.34" - process $proc$libresoc.v:142553$7646 + attribute \src "libresoc.v:152402.7-152402.34" + process $proc$libresoc.v:152402$7968 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:142562.14-142562.34" - process $proc$libresoc.v:142562$7647 + attribute \src "libresoc.v:152411.14-152411.34" + process $proc$libresoc.v:152411$7969 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:142645.13-142645.38" - process $proc$libresoc.v:142645$7648 + attribute \src "libresoc.v:152495.13-152495.38" + process $proc$libresoc.v:152495$7970 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:142802.7-142802.30" - process $proc$libresoc.v:142802$7649 + attribute \src "libresoc.v:152654.7-152654.30" + process $proc$libresoc.v:152654$7971 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:142811.7-142811.31" - process $proc$libresoc.v:142811$7650 + attribute \src "libresoc.v:152663.7-152663.31" + process $proc$libresoc.v:152663$7972 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:142820.7-142820.28" - process $proc$libresoc.v:142820$7651 + attribute \src "libresoc.v:152672.7-152672.28" + process $proc$libresoc.v:152672$7973 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:142829.7-142829.28" - process $proc$libresoc.v:142829$7652 + attribute \src "libresoc.v:152681.7-152681.28" + process $proc$libresoc.v:152681$7974 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:142838.7-142838.28" - process $proc$libresoc.v:142838$7653 + attribute \src "libresoc.v:152690.7-152690.28" + process $proc$libresoc.v:152690$7975 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:142847.7-142847.28" - process $proc$libresoc.v:142847$7654 + attribute \src "libresoc.v:152699.7-152699.28" + process $proc$libresoc.v:152699$7976 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:142856.7-142856.31" - process $proc$libresoc.v:142856$7655 + attribute \src "libresoc.v:152708.7-152708.31" + process $proc$libresoc.v:152708$7977 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:142865.13-142865.25" - process $proc$libresoc.v:142865$7656 + attribute \src "libresoc.v:152717.13-152717.25" + process $proc$libresoc.v:152717$7978 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:142880.7-142880.21" - process $proc$libresoc.v:142880$7657 + attribute \src "libresoc.v:152732.7-152732.21" + process $proc$libresoc.v:152732$7979 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:142887.7-142887.23" - process $proc$libresoc.v:142887$7658 + attribute \src "libresoc.v:152739.7-152739.23" + process $proc$libresoc.v:152739$7980 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:142901.7-142901.20" - process $proc$libresoc.v:142901$7659 + attribute \src "libresoc.v:152753.7-152753.20" + process $proc$libresoc.v:152753$7981 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:142906.14-142906.39" - process $proc$libresoc.v:142906$7660 + attribute \src "libresoc.v:152758.14-152758.39" + process $proc$libresoc.v:152758$7982 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:142915.14-142915.39" - process $proc$libresoc.v:142915$7661 + attribute \src "libresoc.v:152767.14-152767.39" + process $proc$libresoc.v:152767$7983 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:142924.7-142924.20" - process $proc$libresoc.v:142924$7662 + attribute \src "libresoc.v:152776.7-152776.20" + process $proc$libresoc.v:152776$7984 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:142932.3-142933.35" - process $proc$libresoc.v:142932$7571 + attribute \src "libresoc.v:152784.3-152785.35" + process $proc$libresoc.v:152784$7893 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:142934.3-142935.31" - process $proc$libresoc.v:142934$7572 + attribute \src "libresoc.v:152786.3-152787.31" + process $proc$libresoc.v:152786$7894 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:142936.3-142937.29" - process $proc$libresoc.v:142936$7573 + attribute \src "libresoc.v:152788.3-152789.29" + process $proc$libresoc.v:152788$7895 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:142938.3-142939.21" - process $proc$libresoc.v:142938$7574 + attribute \src "libresoc.v:152790.3-152791.21" + process $proc$libresoc.v:152790$7896 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:142940.3-142941.21" - process $proc$libresoc.v:142940$7575 + attribute \src "libresoc.v:152792.3-152793.21" + process $proc$libresoc.v:152792$7897 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:142942.3-142943.51" - process $proc$libresoc.v:142942$7576 + attribute \src "libresoc.v:152794.3-152795.51" + process $proc$libresoc.v:152794$7898 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:142944.3-142945.47" - process $proc$libresoc.v:142944$7577 + attribute \src "libresoc.v:152796.3-152797.47" + process $proc$libresoc.v:152796$7899 assign { } { } - assign $0\mul_op__fn_unit[11:0] \mul_op__fn_unit$next + assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk - update \mul_op__fn_unit $0\mul_op__fn_unit[11:0] + update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:142946.3-142947.61" - process $proc$libresoc.v:142946$7578 + attribute \src "libresoc.v:152798.3-152799.61" + process $proc$libresoc.v:152798$7900 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:142948.3-142949.57" - process $proc$libresoc.v:142948$7579 + attribute \src "libresoc.v:152800.3-152801.57" + process $proc$libresoc.v:152800$7901 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:142950.3-142951.45" - process $proc$libresoc.v:142950$7580 + attribute \src "libresoc.v:152802.3-152803.45" + process $proc$libresoc.v:152802$7902 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:142952.3-142953.45" - process $proc$libresoc.v:142952$7581 + attribute \src "libresoc.v:152804.3-152805.45" + process $proc$libresoc.v:152804$7903 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:142954.3-142955.45" - process $proc$libresoc.v:142954$7582 + attribute \src "libresoc.v:152806.3-152807.45" + process $proc$libresoc.v:152806$7904 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:142956.3-142957.45" - process $proc$libresoc.v:142956$7583 + attribute \src "libresoc.v:152808.3-152809.45" + process $proc$libresoc.v:152808$7905 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:142958.3-142959.51" - process $proc$libresoc.v:142958$7584 + attribute \src "libresoc.v:152810.3-152811.51" + process $proc$libresoc.v:152810$7906 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:142960.3-142961.49" - process $proc$libresoc.v:142960$7585 + attribute \src "libresoc.v:152812.3-152813.49" + process $proc$libresoc.v:152812$7907 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:142962.3-142963.51" - process $proc$libresoc.v:142962$7586 + attribute \src "libresoc.v:152814.3-152815.51" + process $proc$libresoc.v:152814$7908 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:142964.3-142965.41" - process $proc$libresoc.v:142964$7587 + attribute \src "libresoc.v:152816.3-152817.41" + process $proc$libresoc.v:152816$7909 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:142966.3-142967.27" - process $proc$libresoc.v:142966$7588 + attribute \src "libresoc.v:152818.3-152819.27" + process $proc$libresoc.v:152818$7910 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:142968.3-142969.29" - process $proc$libresoc.v:142968$7589 + attribute \src "libresoc.v:152820.3-152821.29" + process $proc$libresoc.v:152820$7911 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:143048.3-143065.6" - process $proc$libresoc.v:143048$7590 + attribute \src "libresoc.v:152900.3-152917.6" + process $proc$libresoc.v:152900$7912 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7591 $2\r_busy$next[0:0]$7593 - attribute \src "libresoc.v:143049.5-143049.29" + assign $0\r_busy$next[0:0]$7913 $2\r_busy$next[0:0]$7915 + attribute \src "libresoc.v:152901.5-152901.29" switch \initial - attribute \src "libresoc.v:143049.9-143049.17" + attribute \src "libresoc.v:152901.9-152901.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7592 1'1 + assign $1\r_busy$next[0:0]$7914 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7592 1'0 + assign $1\r_busy$next[0:0]$7914 1'0 case - assign $1\r_busy$next[0:0]$7592 \r_busy + assign $1\r_busy$next[0:0]$7914 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7593 1'0 + assign $2\r_busy$next[0:0]$7915 1'0 case - assign $2\r_busy$next[0:0]$7593 $1\r_busy$next[0:0]$7592 + assign $2\r_busy$next[0:0]$7915 $1\r_busy$next[0:0]$7914 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7591 + update \r_busy$next $0\r_busy$next[0:0]$7913 end - attribute \src "libresoc.v:143066.3-143078.6" - process $proc$libresoc.v:143066$7594 + attribute \src "libresoc.v:152918.3-152930.6" + process $proc$libresoc.v:152918$7916 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$7595 $1\muxid$next[1:0]$7596 - attribute \src "libresoc.v:143067.5-143067.29" + assign $0\muxid$next[1:0]$7917 $1\muxid$next[1:0]$7918 + attribute \src "libresoc.v:152919.5-152919.29" switch \initial - attribute \src "libresoc.v:143067.9-143067.17" + attribute \src "libresoc.v:152919.9-152919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$7596 \muxid$52 + assign $1\muxid$next[1:0]$7918 \muxid$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$7596 \muxid$52 + assign $1\muxid$next[1:0]$7918 \muxid$52 case - assign $1\muxid$next[1:0]$7596 \muxid + assign $1\muxid$next[1:0]$7918 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$7595 + update \muxid$next $0\muxid$next[1:0]$7917 end - attribute \src "libresoc.v:143079.3-143114.6" - process $proc$libresoc.v:143079$7597 + attribute \src "libresoc.v:152931.3-152966.6" + process $proc$libresoc.v:152931$7919 assign { } { } assign { } { } assign { } { } @@ -300993,31 +319869,31 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$next[11:0]$7598 $1\mul_op__fn_unit$next[11:0]$7610 + assign $0\mul_op__fn_unit$next[13:0]$7920 $1\mul_op__fn_unit$next[13:0]$7932 assign { } { } assign { } { } - assign $0\mul_op__insn$next[31:0]$7601 $1\mul_op__insn$next[31:0]$7613 - assign $0\mul_op__insn_type$next[6:0]$7602 $1\mul_op__insn_type$next[6:0]$7614 - assign $0\mul_op__is_32bit$next[0:0]$7603 $1\mul_op__is_32bit$next[0:0]$7615 - assign $0\mul_op__is_signed$next[0:0]$7604 $1\mul_op__is_signed$next[0:0]$7616 + assign $0\mul_op__insn$next[31:0]$7923 $1\mul_op__insn$next[31:0]$7935 + assign $0\mul_op__insn_type$next[6:0]$7924 $1\mul_op__insn_type$next[6:0]$7936 + assign $0\mul_op__is_32bit$next[0:0]$7925 $1\mul_op__is_32bit$next[0:0]$7937 + assign $0\mul_op__is_signed$next[0:0]$7926 $1\mul_op__is_signed$next[0:0]$7938 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7609 $1\mul_op__write_cr0$next[0:0]$7621 - assign $0\mul_op__imm_data__data$next[63:0]$7599 $2\mul_op__imm_data__data$next[63:0]$7622 - assign $0\mul_op__imm_data__ok$next[0:0]$7600 $2\mul_op__imm_data__ok$next[0:0]$7623 - assign $0\mul_op__oe__oe$next[0:0]$7605 $2\mul_op__oe__oe$next[0:0]$7624 - assign $0\mul_op__oe__ok$next[0:0]$7606 $2\mul_op__oe__ok$next[0:0]$7625 - assign $0\mul_op__rc__ok$next[0:0]$7607 $2\mul_op__rc__ok$next[0:0]$7626 - assign $0\mul_op__rc__rc$next[0:0]$7608 $2\mul_op__rc__rc$next[0:0]$7627 - attribute \src "libresoc.v:143080.5-143080.29" + assign $0\mul_op__write_cr0$next[0:0]$7931 $1\mul_op__write_cr0$next[0:0]$7943 + assign $0\mul_op__imm_data__data$next[63:0]$7921 $2\mul_op__imm_data__data$next[63:0]$7944 + assign $0\mul_op__imm_data__ok$next[0:0]$7922 $2\mul_op__imm_data__ok$next[0:0]$7945 + assign $0\mul_op__oe__oe$next[0:0]$7927 $2\mul_op__oe__oe$next[0:0]$7946 + assign $0\mul_op__oe__ok$next[0:0]$7928 $2\mul_op__oe__ok$next[0:0]$7947 + assign $0\mul_op__rc__ok$next[0:0]$7929 $2\mul_op__rc__ok$next[0:0]$7948 + assign $0\mul_op__rc__rc$next[0:0]$7930 $2\mul_op__rc__rc$next[0:0]$7949 + attribute \src "libresoc.v:152932.5-152932.29" switch \initial - attribute \src "libresoc.v:143080.9-143080.17" + attribute \src "libresoc.v:152932.9-152932.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -301033,7 +319909,7 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7613 $1\mul_op__is_signed$next[0:0]$7616 $1\mul_op__is_32bit$next[0:0]$7615 $1\mul_op__write_cr0$next[0:0]$7621 $1\mul_op__oe__ok$next[0:0]$7618 $1\mul_op__oe__oe$next[0:0]$7617 $1\mul_op__rc__ok$next[0:0]$7619 $1\mul_op__rc__rc$next[0:0]$7620 $1\mul_op__imm_data__ok$next[0:0]$7612 $1\mul_op__imm_data__data$next[63:0]$7611 $1\mul_op__fn_unit$next[11:0]$7610 $1\mul_op__insn_type$next[6:0]$7614 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7935 $1\mul_op__is_signed$next[0:0]$7938 $1\mul_op__is_32bit$next[0:0]$7937 $1\mul_op__write_cr0$next[0:0]$7943 $1\mul_op__oe__ok$next[0:0]$7940 $1\mul_op__oe__oe$next[0:0]$7939 $1\mul_op__rc__ok$next[0:0]$7941 $1\mul_op__rc__rc$next[0:0]$7942 $1\mul_op__imm_data__ok$next[0:0]$7934 $1\mul_op__imm_data__data$next[63:0]$7933 $1\mul_op__fn_unit$next[13:0]$7932 $1\mul_op__insn_type$next[6:0]$7936 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -301048,20 +319924,20 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7613 $1\mul_op__is_signed$next[0:0]$7616 $1\mul_op__is_32bit$next[0:0]$7615 $1\mul_op__write_cr0$next[0:0]$7621 $1\mul_op__oe__ok$next[0:0]$7618 $1\mul_op__oe__oe$next[0:0]$7617 $1\mul_op__rc__ok$next[0:0]$7619 $1\mul_op__rc__rc$next[0:0]$7620 $1\mul_op__imm_data__ok$next[0:0]$7612 $1\mul_op__imm_data__data$next[63:0]$7611 $1\mul_op__fn_unit$next[11:0]$7610 $1\mul_op__insn_type$next[6:0]$7614 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7935 $1\mul_op__is_signed$next[0:0]$7938 $1\mul_op__is_32bit$next[0:0]$7937 $1\mul_op__write_cr0$next[0:0]$7943 $1\mul_op__oe__ok$next[0:0]$7940 $1\mul_op__oe__oe$next[0:0]$7939 $1\mul_op__rc__ok$next[0:0]$7941 $1\mul_op__rc__rc$next[0:0]$7942 $1\mul_op__imm_data__ok$next[0:0]$7934 $1\mul_op__imm_data__data$next[63:0]$7933 $1\mul_op__fn_unit$next[13:0]$7932 $1\mul_op__insn_type$next[6:0]$7936 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } case - assign $1\mul_op__fn_unit$next[11:0]$7610 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7611 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7612 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7613 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7614 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7615 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7616 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7617 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7618 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7619 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7620 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7621 \mul_op__write_cr0 + assign $1\mul_op__fn_unit$next[13:0]$7932 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7933 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7934 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7935 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7936 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7937 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7938 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7939 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7940 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7941 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7942 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7943 \mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -301073,170 +319949,170 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7622 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7623 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7627 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7626 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7624 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7625 1'0 + assign $2\mul_op__imm_data__data$next[63:0]$7944 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7945 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7949 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7948 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7946 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7947 1'0 case - assign $2\mul_op__imm_data__data$next[63:0]$7622 $1\mul_op__imm_data__data$next[63:0]$7611 - assign $2\mul_op__imm_data__ok$next[0:0]$7623 $1\mul_op__imm_data__ok$next[0:0]$7612 - assign $2\mul_op__oe__oe$next[0:0]$7624 $1\mul_op__oe__oe$next[0:0]$7617 - assign $2\mul_op__oe__ok$next[0:0]$7625 $1\mul_op__oe__ok$next[0:0]$7618 - assign $2\mul_op__rc__ok$next[0:0]$7626 $1\mul_op__rc__ok$next[0:0]$7619 - assign $2\mul_op__rc__rc$next[0:0]$7627 $1\mul_op__rc__rc$next[0:0]$7620 + assign $2\mul_op__imm_data__data$next[63:0]$7944 $1\mul_op__imm_data__data$next[63:0]$7933 + assign $2\mul_op__imm_data__ok$next[0:0]$7945 $1\mul_op__imm_data__ok$next[0:0]$7934 + assign $2\mul_op__oe__oe$next[0:0]$7946 $1\mul_op__oe__oe$next[0:0]$7939 + assign $2\mul_op__oe__ok$next[0:0]$7947 $1\mul_op__oe__ok$next[0:0]$7940 + assign $2\mul_op__rc__ok$next[0:0]$7948 $1\mul_op__rc__ok$next[0:0]$7941 + assign $2\mul_op__rc__rc$next[0:0]$7949 $1\mul_op__rc__rc$next[0:0]$7942 end sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[11:0]$7598 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7599 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7600 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7601 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7602 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7603 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7604 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7605 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7606 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7607 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7608 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7609 + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7920 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7921 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7922 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7923 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7924 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7925 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7926 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7927 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7928 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7929 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7930 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7931 end - attribute \src "libresoc.v:143115.3-143127.6" - process $proc$libresoc.v:143115$7628 + attribute \src "libresoc.v:152967.3-152979.6" + process $proc$libresoc.v:152967$7950 assign { } { } assign { } { } - assign $0\ra$next[63:0]$7629 $1\ra$next[63:0]$7630 - attribute \src "libresoc.v:143116.5-143116.29" + assign $0\ra$next[63:0]$7951 $1\ra$next[63:0]$7952 + attribute \src "libresoc.v:152968.5-152968.29" switch \initial - attribute \src "libresoc.v:143116.9-143116.17" + attribute \src "libresoc.v:152968.9-152968.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$7630 \ra$65 + assign $1\ra$next[63:0]$7952 \ra$65 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$7630 \ra$65 + assign $1\ra$next[63:0]$7952 \ra$65 case - assign $1\ra$next[63:0]$7630 \ra + assign $1\ra$next[63:0]$7952 \ra end sync always - update \ra$next $0\ra$next[63:0]$7629 + update \ra$next $0\ra$next[63:0]$7951 end - attribute \src "libresoc.v:143128.3-143140.6" - process $proc$libresoc.v:143128$7631 + attribute \src "libresoc.v:152980.3-152992.6" + process $proc$libresoc.v:152980$7953 assign { } { } assign { } { } - assign $0\rb$next[63:0]$7632 $1\rb$next[63:0]$7633 - attribute \src "libresoc.v:143129.5-143129.29" + assign $0\rb$next[63:0]$7954 $1\rb$next[63:0]$7955 + attribute \src "libresoc.v:152981.5-152981.29" switch \initial - attribute \src "libresoc.v:143129.9-143129.17" + attribute \src "libresoc.v:152981.9-152981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$7633 \rb$66 + assign $1\rb$next[63:0]$7955 \rb$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$7633 \rb$66 + assign $1\rb$next[63:0]$7955 \rb$66 case - assign $1\rb$next[63:0]$7633 \rb + assign $1\rb$next[63:0]$7955 \rb end sync always - update \rb$next $0\rb$next[63:0]$7632 + update \rb$next $0\rb$next[63:0]$7954 end - attribute \src "libresoc.v:143141.3-143153.6" - process $proc$libresoc.v:143141$7634 + attribute \src "libresoc.v:152993.3-153005.6" + process $proc$libresoc.v:152993$7956 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$7635 $1\xer_so$next[0:0]$7636 - attribute \src "libresoc.v:143142.5-143142.29" + assign $0\xer_so$next[0:0]$7957 $1\xer_so$next[0:0]$7958 + attribute \src "libresoc.v:152994.5-152994.29" switch \initial - attribute \src "libresoc.v:143142.9-143142.17" + attribute \src "libresoc.v:152994.9-152994.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$7636 \xer_so$67 + assign $1\xer_so$next[0:0]$7958 \xer_so$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$7636 \xer_so$67 + assign $1\xer_so$next[0:0]$7958 \xer_so$67 case - assign $1\xer_so$next[0:0]$7636 \xer_so + assign $1\xer_so$next[0:0]$7958 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$7635 + update \xer_so$next $0\xer_so$next[0:0]$7957 end - attribute \src "libresoc.v:143154.3-143166.6" - process $proc$libresoc.v:143154$7637 + attribute \src "libresoc.v:153006.3-153018.6" + process $proc$libresoc.v:153006$7959 assign { } { } assign { } { } - assign $0\neg_res$next[0:0]$7638 $1\neg_res$next[0:0]$7639 - attribute \src "libresoc.v:143155.5-143155.29" + assign $0\neg_res$next[0:0]$7960 $1\neg_res$next[0:0]$7961 + attribute \src "libresoc.v:153007.5-153007.29" switch \initial - attribute \src "libresoc.v:143155.9-143155.17" + attribute \src "libresoc.v:153007.9-153007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$next[0:0]$7639 \neg_res$68 + assign $1\neg_res$next[0:0]$7961 \neg_res$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$next[0:0]$7639 \neg_res$68 + assign $1\neg_res$next[0:0]$7961 \neg_res$68 case - assign $1\neg_res$next[0:0]$7639 \neg_res + assign $1\neg_res$next[0:0]$7961 \neg_res end sync always - update \neg_res$next $0\neg_res$next[0:0]$7638 + update \neg_res$next $0\neg_res$next[0:0]$7960 end - attribute \src "libresoc.v:143167.3-143179.6" - process $proc$libresoc.v:143167$7640 + attribute \src "libresoc.v:153019.3-153031.6" + process $proc$libresoc.v:153019$7962 assign { } { } assign { } { } - assign $0\neg_res32$next[0:0]$7641 $1\neg_res32$next[0:0]$7642 - attribute \src "libresoc.v:143168.5-143168.29" + assign $0\neg_res32$next[0:0]$7963 $1\neg_res32$next[0:0]$7964 + attribute \src "libresoc.v:153020.5-153020.29" switch \initial - attribute \src "libresoc.v:143168.9-143168.17" + attribute \src "libresoc.v:153020.9-153020.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$next[0:0]$7642 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7964 \neg_res32$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$next[0:0]$7642 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7964 \neg_res32$69 case - assign $1\neg_res32$next[0:0]$7642 \neg_res32 + assign $1\neg_res32$next[0:0]$7964 \neg_res32 end sync always - update \neg_res32$next $0\neg_res32$next[0:0]$7641 + update \neg_res32$next $0\neg_res32$next[0:0]$7963 end - connect \$50 $and$libresoc.v:142931$7570_Y + connect \$50 $and$libresoc.v:152783$7892_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -301260,211 +320136,215 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:143206.1-144111.10" +attribute \src "libresoc.v:153058.1-153978.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:143207.7-143207.20" + attribute \src "libresoc.v:153059.7-153059.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144005.3-144040.6" - wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7706 - attribute \src "libresoc.v:143903.3-143904.53" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7674 - attribute \src "libresoc.v:143488.14-143488.43" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7750 - attribute \src "libresoc.v:144005.3-144040.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7707 - attribute \src "libresoc.v:143905.3-143906.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7676 - attribute \src "libresoc.v:143512.14-143512.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7752 - attribute \src "libresoc.v:144005.3-144040.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$7708 - attribute \src "libresoc.v:143907.3-143908.63" - wire $0\mul_op__imm_data__ok$5[0:0]$7678 - attribute \src "libresoc.v:143521.7-143521.38" - wire $0\mul_op__imm_data__ok$5[0:0]$7754 - attribute \src "libresoc.v:144005.3-144040.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$7709 - attribute \src "libresoc.v:143923.3-143924.49" - wire width 32 $0\mul_op__insn$13[31:0]$7694 - attribute \src "libresoc.v:143528.14-143528.39" - wire width 32 $0\mul_op__insn$13[31:0]$7756 - attribute \src "libresoc.v:144005.3-144040.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$7710 - attribute \src "libresoc.v:143901.3-143902.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7672 - attribute \src "libresoc.v:143685.13-143685.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$7758 - attribute \src "libresoc.v:144005.3-144040.6" - wire $0\mul_op__is_32bit$11$next[0:0]$7711 - attribute \src "libresoc.v:143919.3-143920.57" - wire $0\mul_op__is_32bit$11[0:0]$7690 - attribute \src "libresoc.v:143768.7-143768.35" - wire $0\mul_op__is_32bit$11[0:0]$7760 - attribute \src "libresoc.v:144005.3-144040.6" - wire $0\mul_op__is_signed$12$next[0:0]$7712 - attribute \src "libresoc.v:143921.3-143922.59" - wire $0\mul_op__is_signed$12[0:0]$7692 - attribute \src "libresoc.v:143777.7-143777.36" - wire $0\mul_op__is_signed$12[0:0]$7762 - attribute \src "libresoc.v:144005.3-144040.6" - wire $0\mul_op__oe__oe$8$next[0:0]$7713 - attribute \src "libresoc.v:143913.3-143914.51" - wire $0\mul_op__oe__oe$8[0:0]$7684 - attribute \src "libresoc.v:143788.7-143788.32" - wire $0\mul_op__oe__oe$8[0:0]$7764 - attribute \src "libresoc.v:144005.3-144040.6" - wire $0\mul_op__oe__ok$9$next[0:0]$7714 - attribute \src "libresoc.v:143915.3-143916.51" - wire $0\mul_op__oe__ok$9[0:0]$7686 - attribute \src "libresoc.v:143797.7-143797.32" - wire $0\mul_op__oe__ok$9[0:0]$7766 - attribute \src "libresoc.v:144005.3-144040.6" - wire $0\mul_op__rc__ok$7$next[0:0]$7715 - attribute \src "libresoc.v:143911.3-143912.51" - wire $0\mul_op__rc__ok$7[0:0]$7682 - attribute \src "libresoc.v:143806.7-143806.32" - wire $0\mul_op__rc__ok$7[0:0]$7768 - attribute \src "libresoc.v:144005.3-144040.6" - wire $0\mul_op__rc__rc$6$next[0:0]$7716 - attribute \src "libresoc.v:143909.3-143910.51" - wire $0\mul_op__rc__rc$6[0:0]$7680 - attribute \src "libresoc.v:143815.7-143815.32" - wire $0\mul_op__rc__rc$6[0:0]$7770 - attribute \src "libresoc.v:144005.3-144040.6" - wire $0\mul_op__write_cr0$10$next[0:0]$7717 - attribute \src "libresoc.v:143917.3-143918.59" - wire $0\mul_op__write_cr0$10[0:0]$7688 - attribute \src "libresoc.v:143822.7-143822.36" - wire $0\mul_op__write_cr0$10[0:0]$7772 - attribute \src "libresoc.v:143992.3-144004.6" - wire width 2 $0\muxid$1$next[1:0]$7703 - attribute \src "libresoc.v:143925.3-143926.33" - wire width 2 $0\muxid$1[1:0]$7696 - attribute \src "libresoc.v:143831.13-143831.29" - wire width 2 $0\muxid$1[1:0]$7774 - attribute \src "libresoc.v:144067.3-144079.6" - wire $0\neg_res$15$next[0:0]$7743 - attribute \src "libresoc.v:143895.3-143896.39" - wire $0\neg_res$15[0:0]$7667 - attribute \src "libresoc.v:143846.7-143846.26" - wire $0\neg_res$15[0:0]$7776 - attribute \src "libresoc.v:144080.3-144092.6" - wire $0\neg_res32$16$next[0:0]$7746 - attribute \src "libresoc.v:143893.3-143894.43" - wire $0\neg_res32$16[0:0]$7665 - attribute \src "libresoc.v:143855.7-143855.28" - wire $0\neg_res32$16[0:0]$7778 - attribute \src "libresoc.v:144041.3-144053.6" - wire width 129 $0\o$next[128:0]$7737 - attribute \src "libresoc.v:143899.3-143900.19" + attribute \src "libresoc.v:153872.3-153907.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8028 + attribute \src "libresoc.v:153770.3-153771.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$7996 + attribute \src "libresoc.v:153350.14-153350.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8072 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8029 + attribute \src "libresoc.v:153772.3-153773.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7998 + attribute \src "libresoc.v:153376.14-153376.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8074 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8030 + attribute \src "libresoc.v:153774.3-153775.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8000 + attribute \src "libresoc.v:153385.7-153385.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8076 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8031 + attribute \src "libresoc.v:153790.3-153791.49" + wire width 32 $0\mul_op__insn$13[31:0]$8016 + attribute \src "libresoc.v:153392.14-153392.39" + wire width 32 $0\mul_op__insn$13[31:0]$8078 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8032 + attribute \src "libresoc.v:153768.3-153769.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7994 + attribute \src "libresoc.v:153551.13-153551.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8080 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8033 + attribute \src "libresoc.v:153786.3-153787.57" + wire $0\mul_op__is_32bit$11[0:0]$8012 + attribute \src "libresoc.v:153635.7-153635.35" + wire $0\mul_op__is_32bit$11[0:0]$8082 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__is_signed$12$next[0:0]$8034 + attribute \src "libresoc.v:153788.3-153789.59" + wire $0\mul_op__is_signed$12[0:0]$8014 + attribute \src "libresoc.v:153644.7-153644.36" + wire $0\mul_op__is_signed$12[0:0]$8084 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8035 + attribute \src "libresoc.v:153780.3-153781.51" + wire $0\mul_op__oe__oe$8[0:0]$8006 + attribute \src "libresoc.v:153655.7-153655.32" + wire $0\mul_op__oe__oe$8[0:0]$8086 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8036 + attribute \src "libresoc.v:153782.3-153783.51" + wire $0\mul_op__oe__ok$9[0:0]$8008 + attribute \src "libresoc.v:153664.7-153664.32" + wire $0\mul_op__oe__ok$9[0:0]$8088 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8037 + attribute \src "libresoc.v:153778.3-153779.51" + wire $0\mul_op__rc__ok$7[0:0]$8004 + attribute \src "libresoc.v:153673.7-153673.32" + wire $0\mul_op__rc__ok$7[0:0]$8090 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8038 + attribute \src "libresoc.v:153776.3-153777.51" + wire $0\mul_op__rc__rc$6[0:0]$8002 + attribute \src "libresoc.v:153682.7-153682.32" + wire $0\mul_op__rc__rc$6[0:0]$8092 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8039 + attribute \src "libresoc.v:153784.3-153785.59" + wire $0\mul_op__write_cr0$10[0:0]$8010 + attribute \src "libresoc.v:153689.7-153689.36" + wire $0\mul_op__write_cr0$10[0:0]$8094 + attribute \src "libresoc.v:153859.3-153871.6" + wire width 2 $0\muxid$1$next[1:0]$8025 + attribute \src "libresoc.v:153792.3-153793.33" + wire width 2 $0\muxid$1[1:0]$8018 + attribute \src "libresoc.v:153698.13-153698.29" + wire width 2 $0\muxid$1[1:0]$8096 + attribute \src "libresoc.v:153934.3-153946.6" + wire $0\neg_res$15$next[0:0]$8065 + attribute \src "libresoc.v:153762.3-153763.39" + wire $0\neg_res$15[0:0]$7989 + attribute \src "libresoc.v:153713.7-153713.26" + wire $0\neg_res$15[0:0]$8098 + attribute \src "libresoc.v:153947.3-153959.6" + wire $0\neg_res32$16$next[0:0]$8068 + attribute \src "libresoc.v:153760.3-153761.43" + wire $0\neg_res32$16[0:0]$7987 + attribute \src "libresoc.v:153722.7-153722.28" + wire $0\neg_res32$16[0:0]$8100 + attribute \src "libresoc.v:153908.3-153920.6" + wire width 129 $0\o$next[128:0]$8059 + attribute \src "libresoc.v:153766.3-153767.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:143974.3-143991.6" - wire $0\r_busy$next[0:0]$7699 - attribute \src "libresoc.v:143927.3-143928.29" + attribute \src "libresoc.v:153841.3-153858.6" + wire $0\r_busy$next[0:0]$8021 + attribute \src "libresoc.v:153794.3-153795.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:144054.3-144066.6" - wire $0\xer_so$14$next[0:0]$7740 - attribute \src "libresoc.v:143897.3-143898.37" - wire $0\xer_so$14[0:0]$7669 - attribute \src "libresoc.v:143887.7-143887.25" - wire $0\xer_so$14[0:0]$7782 - attribute \src "libresoc.v:144005.3-144040.6" - wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7718 - attribute \src "libresoc.v:144005.3-144040.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7719 - attribute \src "libresoc.v:144005.3-144040.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$7720 - attribute \src "libresoc.v:144005.3-144040.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$7721 - attribute \src "libresoc.v:144005.3-144040.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$7722 - attribute \src "libresoc.v:144005.3-144040.6" - wire $1\mul_op__is_32bit$11$next[0:0]$7723 - attribute \src "libresoc.v:144005.3-144040.6" - wire $1\mul_op__is_signed$12$next[0:0]$7724 - attribute \src "libresoc.v:144005.3-144040.6" - wire $1\mul_op__oe__oe$8$next[0:0]$7725 - attribute \src "libresoc.v:144005.3-144040.6" - wire $1\mul_op__oe__ok$9$next[0:0]$7726 - attribute \src "libresoc.v:144005.3-144040.6" - wire $1\mul_op__rc__ok$7$next[0:0]$7727 - attribute \src "libresoc.v:144005.3-144040.6" - wire $1\mul_op__rc__rc$6$next[0:0]$7728 - attribute \src "libresoc.v:144005.3-144040.6" - wire $1\mul_op__write_cr0$10$next[0:0]$7729 - attribute \src "libresoc.v:143992.3-144004.6" - wire width 2 $1\muxid$1$next[1:0]$7704 - attribute \src "libresoc.v:144067.3-144079.6" - wire $1\neg_res$15$next[0:0]$7744 - attribute \src "libresoc.v:144080.3-144092.6" - wire $1\neg_res32$16$next[0:0]$7747 - attribute \src "libresoc.v:144041.3-144053.6" - wire width 129 $1\o$next[128:0]$7738 - attribute \src "libresoc.v:143862.15-143862.57" + attribute \src "libresoc.v:153921.3-153933.6" + wire $0\xer_so$14$next[0:0]$8062 + attribute \src "libresoc.v:153764.3-153765.37" + wire $0\xer_so$14[0:0]$7991 + attribute \src "libresoc.v:153754.7-153754.25" + wire $0\xer_so$14[0:0]$8104 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8040 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8041 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8042 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8043 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8044 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8045 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__is_signed$12$next[0:0]$8046 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8047 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8048 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8049 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8050 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8051 + attribute \src "libresoc.v:153859.3-153871.6" + wire width 2 $1\muxid$1$next[1:0]$8026 + attribute \src "libresoc.v:153934.3-153946.6" + wire $1\neg_res$15$next[0:0]$8066 + attribute \src "libresoc.v:153947.3-153959.6" + wire $1\neg_res32$16$next[0:0]$8069 + attribute \src "libresoc.v:153908.3-153920.6" + wire width 129 $1\o$next[128:0]$8060 + attribute \src "libresoc.v:153729.15-153729.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:143974.3-143991.6" - wire $1\r_busy$next[0:0]$7700 - attribute \src "libresoc.v:143876.7-143876.20" + attribute \src "libresoc.v:153841.3-153858.6" + wire $1\r_busy$next[0:0]$8022 + attribute \src "libresoc.v:153743.7-153743.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:144054.3-144066.6" - wire $1\xer_so$14$next[0:0]$7741 - attribute \src "libresoc.v:144005.3-144040.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7730 - attribute \src "libresoc.v:144005.3-144040.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$7731 - attribute \src "libresoc.v:144005.3-144040.6" - wire $2\mul_op__oe__oe$8$next[0:0]$7732 - attribute \src "libresoc.v:144005.3-144040.6" - wire $2\mul_op__oe__ok$9$next[0:0]$7733 - attribute \src "libresoc.v:144005.3-144040.6" - wire $2\mul_op__rc__ok$7$next[0:0]$7734 - attribute \src "libresoc.v:144005.3-144040.6" - wire $2\mul_op__rc__rc$6$next[0:0]$7735 - attribute \src "libresoc.v:143974.3-143991.6" - wire $2\r_busy$next[0:0]$7701 - attribute \src "libresoc.v:143892.18-143892.118" - wire $and$libresoc.v:143892$7663_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + attribute \src "libresoc.v:153921.3-153933.6" + wire $1\xer_so$14$next[0:0]$8063 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8052 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8053 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8054 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8055 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8056 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8057 + attribute \src "libresoc.v:153841.3-153858.6" + wire $2\r_busy$next[0:0]$8023 + attribute \src "libresoc.v:153759.18-153759.118" + wire $and$libresoc.v:153759$7985_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:143207.7-143207.15" + attribute \src "libresoc.v:153059.7-153059.15" wire \initial attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul2_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul2_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul2_mul_op__fn_unit$19 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul2_mul_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul2_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -301551,6 +320431,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul2_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -301627,6 +320508,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul2_mul_op__insn_type$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -301657,9 +320539,9 @@ module \mul_pipe2 wire \mul2_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__write_cr0$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul2_muxid$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \mul2_neg_res @@ -301680,52 +320562,58 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul2_xer_so$30 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 26 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$38 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -301824,6 +320712,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -301900,6 +320789,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 25 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -301978,6 +320868,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -302036,19 +320927,19 @@ module \mul_pipe2 wire \mul_op__write_cr0$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 23 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 22 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire input 20 \neg_res @@ -302072,17 +320963,17 @@ module \mul_pipe2 wire width 129 \o$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 17 \ra @@ -302096,8 +320987,8 @@ module \mul_pipe2 wire \xer_so$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:143892$7663 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:153759$7985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302105,10 +320996,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:143892$7663_Y + connect \Y $and$libresoc.v:153759$7985_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:143929.8-143965.4" + attribute \src "libresoc.v:153796.8-153832.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -302147,361 +321038,361 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:143966.10-143969.4" + attribute \src "libresoc.v:153833.10-153836.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:143970.10-143973.4" + attribute \src "libresoc.v:153837.10-153840.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:143207.7-143207.20" - process $proc$libresoc.v:143207$7748 + attribute \src "libresoc.v:153059.7-153059.20" + process $proc$libresoc.v:153059$8070 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143488.14-143488.43" - process $proc$libresoc.v:143488$7749 + attribute \src "libresoc.v:153350.14-153350.44" + process $proc$libresoc.v:153350$8071 assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7750 12'000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8072 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7750 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8072 end - attribute \src "libresoc.v:143512.14-143512.63" - process $proc$libresoc.v:143512$7751 + attribute \src "libresoc.v:153376.14-153376.63" + process $proc$libresoc.v:153376$8073 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7752 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8074 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7752 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8074 end - attribute \src "libresoc.v:143521.7-143521.38" - process $proc$libresoc.v:143521$7753 + attribute \src "libresoc.v:153385.7-153385.38" + process $proc$libresoc.v:153385$8075 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7754 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8076 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7754 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8076 end - attribute \src "libresoc.v:143528.14-143528.39" - process $proc$libresoc.v:143528$7755 + attribute \src "libresoc.v:153392.14-153392.39" + process $proc$libresoc.v:153392$8077 assign { } { } - assign $0\mul_op__insn$13[31:0]$7756 0 + assign $0\mul_op__insn$13[31:0]$8078 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7756 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8078 end - attribute \src "libresoc.v:143685.13-143685.42" - process $proc$libresoc.v:143685$7757 + attribute \src "libresoc.v:153551.13-153551.42" + process $proc$libresoc.v:153551$8079 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7758 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8080 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7758 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8080 end - attribute \src "libresoc.v:143768.7-143768.35" - process $proc$libresoc.v:143768$7759 + attribute \src "libresoc.v:153635.7-153635.35" + process $proc$libresoc.v:153635$8081 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7760 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8082 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7760 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8082 end - attribute \src "libresoc.v:143777.7-143777.36" - process $proc$libresoc.v:143777$7761 + attribute \src "libresoc.v:153644.7-153644.36" + process $proc$libresoc.v:153644$8083 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7762 1'0 + assign $0\mul_op__is_signed$12[0:0]$8084 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7762 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8084 end - attribute \src "libresoc.v:143788.7-143788.32" - process $proc$libresoc.v:143788$7763 + attribute \src "libresoc.v:153655.7-153655.32" + process $proc$libresoc.v:153655$8085 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7764 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8086 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7764 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8086 end - attribute \src "libresoc.v:143797.7-143797.32" - process $proc$libresoc.v:143797$7765 + attribute \src "libresoc.v:153664.7-153664.32" + process $proc$libresoc.v:153664$8087 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7766 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8088 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7766 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8088 end - attribute \src "libresoc.v:143806.7-143806.32" - process $proc$libresoc.v:143806$7767 + attribute \src "libresoc.v:153673.7-153673.32" + process $proc$libresoc.v:153673$8089 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7768 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8090 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7768 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8090 end - attribute \src "libresoc.v:143815.7-143815.32" - process $proc$libresoc.v:143815$7769 + attribute \src "libresoc.v:153682.7-153682.32" + process $proc$libresoc.v:153682$8091 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7770 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8092 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7770 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8092 end - attribute \src "libresoc.v:143822.7-143822.36" - process $proc$libresoc.v:143822$7771 + attribute \src "libresoc.v:153689.7-153689.36" + process $proc$libresoc.v:153689$8093 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7772 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8094 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7772 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8094 end - attribute \src "libresoc.v:143831.13-143831.29" - process $proc$libresoc.v:143831$7773 + attribute \src "libresoc.v:153698.13-153698.29" + process $proc$libresoc.v:153698$8095 assign { } { } - assign $0\muxid$1[1:0]$7774 2'00 + assign $0\muxid$1[1:0]$8096 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7774 + update \muxid$1 $0\muxid$1[1:0]$8096 end - attribute \src "libresoc.v:143846.7-143846.26" - process $proc$libresoc.v:143846$7775 + attribute \src "libresoc.v:153713.7-153713.26" + process $proc$libresoc.v:153713$8097 assign { } { } - assign $0\neg_res$15[0:0]$7776 1'0 + assign $0\neg_res$15[0:0]$8098 1'0 sync always sync init - update \neg_res$15 $0\neg_res$15[0:0]$7776 + update \neg_res$15 $0\neg_res$15[0:0]$8098 end - attribute \src "libresoc.v:143855.7-143855.28" - process $proc$libresoc.v:143855$7777 + attribute \src "libresoc.v:153722.7-153722.28" + process $proc$libresoc.v:153722$8099 assign { } { } - assign $0\neg_res32$16[0:0]$7778 1'0 + assign $0\neg_res32$16[0:0]$8100 1'0 sync always sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$7778 + update \neg_res32$16 $0\neg_res32$16[0:0]$8100 end - attribute \src "libresoc.v:143862.15-143862.57" - process $proc$libresoc.v:143862$7779 + attribute \src "libresoc.v:153729.15-153729.57" + process $proc$libresoc.v:153729$8101 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:143876.7-143876.20" - process $proc$libresoc.v:143876$7780 + attribute \src "libresoc.v:153743.7-153743.20" + process $proc$libresoc.v:153743$8102 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:143887.7-143887.25" - process $proc$libresoc.v:143887$7781 + attribute \src "libresoc.v:153754.7-153754.25" + process $proc$libresoc.v:153754$8103 assign { } { } - assign $0\xer_so$14[0:0]$7782 1'0 + assign $0\xer_so$14[0:0]$8104 1'0 sync always sync init - update \xer_so$14 $0\xer_so$14[0:0]$7782 + update \xer_so$14 $0\xer_so$14[0:0]$8104 end - attribute \src "libresoc.v:143893.3-143894.43" - process $proc$libresoc.v:143893$7664 + attribute \src "libresoc.v:153760.3-153761.43" + process $proc$libresoc.v:153760$7986 assign { } { } - assign $0\neg_res32$16[0:0]$7665 \neg_res32$16$next + assign $0\neg_res32$16[0:0]$7987 \neg_res32$16$next sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$7665 + update \neg_res32$16 $0\neg_res32$16[0:0]$7987 end - attribute \src "libresoc.v:143895.3-143896.39" - process $proc$libresoc.v:143895$7666 + attribute \src "libresoc.v:153762.3-153763.39" + process $proc$libresoc.v:153762$7988 assign { } { } - assign $0\neg_res$15[0:0]$7667 \neg_res$15$next + assign $0\neg_res$15[0:0]$7989 \neg_res$15$next sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$7667 + update \neg_res$15 $0\neg_res$15[0:0]$7989 end - attribute \src "libresoc.v:143897.3-143898.37" - process $proc$libresoc.v:143897$7668 + attribute \src "libresoc.v:153764.3-153765.37" + process $proc$libresoc.v:153764$7990 assign { } { } - assign $0\xer_so$14[0:0]$7669 \xer_so$14$next + assign $0\xer_so$14[0:0]$7991 \xer_so$14$next sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$7669 + update \xer_so$14 $0\xer_so$14[0:0]$7991 end - attribute \src "libresoc.v:143899.3-143900.19" - process $proc$libresoc.v:143899$7670 + attribute \src "libresoc.v:153766.3-153767.19" + process $proc$libresoc.v:153766$7992 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:143901.3-143902.57" - process $proc$libresoc.v:143901$7671 + attribute \src "libresoc.v:153768.3-153769.57" + process $proc$libresoc.v:153768$7993 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7672 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$7994 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7672 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7994 end - attribute \src "libresoc.v:143903.3-143904.53" - process $proc$libresoc.v:143903$7673 + attribute \src "libresoc.v:153770.3-153771.53" + process $proc$libresoc.v:153770$7995 assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7674 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$7996 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7674 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$7996 end - attribute \src "libresoc.v:143905.3-143906.67" - process $proc$libresoc.v:143905$7675 + attribute \src "libresoc.v:153772.3-153773.67" + process $proc$libresoc.v:153772$7997 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7676 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$7998 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7676 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7998 end - attribute \src "libresoc.v:143907.3-143908.63" - process $proc$libresoc.v:143907$7677 + attribute \src "libresoc.v:153774.3-153775.63" + process $proc$libresoc.v:153774$7999 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7678 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8000 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7678 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8000 end - attribute \src "libresoc.v:143909.3-143910.51" - process $proc$libresoc.v:143909$7679 + attribute \src "libresoc.v:153776.3-153777.51" + process $proc$libresoc.v:153776$8001 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7680 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8002 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7680 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8002 end - attribute \src "libresoc.v:143911.3-143912.51" - process $proc$libresoc.v:143911$7681 + attribute \src "libresoc.v:153778.3-153779.51" + process $proc$libresoc.v:153778$8003 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7682 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8004 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7682 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8004 end - attribute \src "libresoc.v:143913.3-143914.51" - process $proc$libresoc.v:143913$7683 + attribute \src "libresoc.v:153780.3-153781.51" + process $proc$libresoc.v:153780$8005 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7684 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8006 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7684 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8006 end - attribute \src "libresoc.v:143915.3-143916.51" - process $proc$libresoc.v:143915$7685 + attribute \src "libresoc.v:153782.3-153783.51" + process $proc$libresoc.v:153782$8007 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7686 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8008 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7686 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8008 end - attribute \src "libresoc.v:143917.3-143918.59" - process $proc$libresoc.v:143917$7687 + attribute \src "libresoc.v:153784.3-153785.59" + process $proc$libresoc.v:153784$8009 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7688 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8010 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7688 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8010 end - attribute \src "libresoc.v:143919.3-143920.57" - process $proc$libresoc.v:143919$7689 + attribute \src "libresoc.v:153786.3-153787.57" + process $proc$libresoc.v:153786$8011 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7690 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8012 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7690 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8012 end - attribute \src "libresoc.v:143921.3-143922.59" - process $proc$libresoc.v:143921$7691 + attribute \src "libresoc.v:153788.3-153789.59" + process $proc$libresoc.v:153788$8013 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7692 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8014 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7692 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8014 end - attribute \src "libresoc.v:143923.3-143924.49" - process $proc$libresoc.v:143923$7693 + attribute \src "libresoc.v:153790.3-153791.49" + process $proc$libresoc.v:153790$8015 assign { } { } - assign $0\mul_op__insn$13[31:0]$7694 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8016 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7694 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8016 end - attribute \src "libresoc.v:143925.3-143926.33" - process $proc$libresoc.v:143925$7695 + attribute \src "libresoc.v:153792.3-153793.33" + process $proc$libresoc.v:153792$8017 assign { } { } - assign $0\muxid$1[1:0]$7696 \muxid$1$next + assign $0\muxid$1[1:0]$8018 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7696 + update \muxid$1 $0\muxid$1[1:0]$8018 end - attribute \src "libresoc.v:143927.3-143928.29" - process $proc$libresoc.v:143927$7697 + attribute \src "libresoc.v:153794.3-153795.29" + process $proc$libresoc.v:153794$8019 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:143974.3-143991.6" - process $proc$libresoc.v:143974$7698 + attribute \src "libresoc.v:153841.3-153858.6" + process $proc$libresoc.v:153841$8020 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7699 $2\r_busy$next[0:0]$7701 - attribute \src "libresoc.v:143975.5-143975.29" + assign $0\r_busy$next[0:0]$8021 $2\r_busy$next[0:0]$8023 + attribute \src "libresoc.v:153842.5-153842.29" switch \initial - attribute \src "libresoc.v:143975.9-143975.17" + attribute \src "libresoc.v:153842.9-153842.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7700 1'1 + assign $1\r_busy$next[0:0]$8022 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7700 1'0 + assign $1\r_busy$next[0:0]$8022 1'0 case - assign $1\r_busy$next[0:0]$7700 \r_busy + assign $1\r_busy$next[0:0]$8022 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7701 1'0 + assign $2\r_busy$next[0:0]$8023 1'0 case - assign $2\r_busy$next[0:0]$7701 $1\r_busy$next[0:0]$7700 + assign $2\r_busy$next[0:0]$8023 $1\r_busy$next[0:0]$8022 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7699 + update \r_busy$next $0\r_busy$next[0:0]$8021 end - attribute \src "libresoc.v:143992.3-144004.6" - process $proc$libresoc.v:143992$7702 + attribute \src "libresoc.v:153859.3-153871.6" + process $proc$libresoc.v:153859$8024 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$7703 $1\muxid$1$next[1:0]$7704 - attribute \src "libresoc.v:143993.5-143993.29" + assign $0\muxid$1$next[1:0]$8025 $1\muxid$1$next[1:0]$8026 + attribute \src "libresoc.v:153860.5-153860.29" switch \initial - attribute \src "libresoc.v:143993.9-143993.17" + attribute \src "libresoc.v:153860.9-153860.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$7704 \muxid$36 + assign $1\muxid$1$next[1:0]$8026 \muxid$36 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$7704 \muxid$36 + assign $1\muxid$1$next[1:0]$8026 \muxid$36 case - assign $1\muxid$1$next[1:0]$7704 \muxid$1 + assign $1\muxid$1$next[1:0]$8026 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7703 + update \muxid$1$next $0\muxid$1$next[1:0]$8025 end - attribute \src "libresoc.v:144005.3-144040.6" - process $proc$libresoc.v:144005$7705 + attribute \src "libresoc.v:153872.3-153907.6" + process $proc$libresoc.v:153872$8027 assign { } { } assign { } { } assign { } { } @@ -302526,31 +321417,31 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[11:0]$7706 $1\mul_op__fn_unit$3$next[11:0]$7718 + assign $0\mul_op__fn_unit$3$next[13:0]$8028 $1\mul_op__fn_unit$3$next[13:0]$8040 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7709 $1\mul_op__insn$13$next[31:0]$7721 - assign $0\mul_op__insn_type$2$next[6:0]$7710 $1\mul_op__insn_type$2$next[6:0]$7722 - assign $0\mul_op__is_32bit$11$next[0:0]$7711 $1\mul_op__is_32bit$11$next[0:0]$7723 - assign $0\mul_op__is_signed$12$next[0:0]$7712 $1\mul_op__is_signed$12$next[0:0]$7724 + assign $0\mul_op__insn$13$next[31:0]$8031 $1\mul_op__insn$13$next[31:0]$8043 + assign $0\mul_op__insn_type$2$next[6:0]$8032 $1\mul_op__insn_type$2$next[6:0]$8044 + assign $0\mul_op__is_32bit$11$next[0:0]$8033 $1\mul_op__is_32bit$11$next[0:0]$8045 + assign $0\mul_op__is_signed$12$next[0:0]$8034 $1\mul_op__is_signed$12$next[0:0]$8046 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7717 $1\mul_op__write_cr0$10$next[0:0]$7729 - assign $0\mul_op__imm_data__data$4$next[63:0]$7707 $2\mul_op__imm_data__data$4$next[63:0]$7730 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7708 $2\mul_op__imm_data__ok$5$next[0:0]$7731 - assign $0\mul_op__oe__oe$8$next[0:0]$7713 $2\mul_op__oe__oe$8$next[0:0]$7732 - assign $0\mul_op__oe__ok$9$next[0:0]$7714 $2\mul_op__oe__ok$9$next[0:0]$7733 - assign $0\mul_op__rc__ok$7$next[0:0]$7715 $2\mul_op__rc__ok$7$next[0:0]$7734 - assign $0\mul_op__rc__rc$6$next[0:0]$7716 $2\mul_op__rc__rc$6$next[0:0]$7735 - attribute \src "libresoc.v:144006.5-144006.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8039 $1\mul_op__write_cr0$10$next[0:0]$8051 + assign $0\mul_op__imm_data__data$4$next[63:0]$8029 $2\mul_op__imm_data__data$4$next[63:0]$8052 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8030 $2\mul_op__imm_data__ok$5$next[0:0]$8053 + assign $0\mul_op__oe__oe$8$next[0:0]$8035 $2\mul_op__oe__oe$8$next[0:0]$8054 + assign $0\mul_op__oe__ok$9$next[0:0]$8036 $2\mul_op__oe__ok$9$next[0:0]$8055 + assign $0\mul_op__rc__ok$7$next[0:0]$8037 $2\mul_op__rc__ok$7$next[0:0]$8056 + assign $0\mul_op__rc__rc$6$next[0:0]$8038 $2\mul_op__rc__rc$6$next[0:0]$8057 + attribute \src "libresoc.v:153873.5-153873.29" switch \initial - attribute \src "libresoc.v:144006.9-144006.17" + attribute \src "libresoc.v:153873.9-153873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -302566,7 +321457,7 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7721 $1\mul_op__is_signed$12$next[0:0]$7724 $1\mul_op__is_32bit$11$next[0:0]$7723 $1\mul_op__write_cr0$10$next[0:0]$7729 $1\mul_op__oe__ok$9$next[0:0]$7726 $1\mul_op__oe__oe$8$next[0:0]$7725 $1\mul_op__rc__ok$7$next[0:0]$7727 $1\mul_op__rc__rc$6$next[0:0]$7728 $1\mul_op__imm_data__ok$5$next[0:0]$7720 $1\mul_op__imm_data__data$4$next[63:0]$7719 $1\mul_op__fn_unit$3$next[11:0]$7718 $1\mul_op__insn_type$2$next[6:0]$7722 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8043 $1\mul_op__is_signed$12$next[0:0]$8046 $1\mul_op__is_32bit$11$next[0:0]$8045 $1\mul_op__write_cr0$10$next[0:0]$8051 $1\mul_op__oe__ok$9$next[0:0]$8048 $1\mul_op__oe__oe$8$next[0:0]$8047 $1\mul_op__rc__ok$7$next[0:0]$8049 $1\mul_op__rc__rc$6$next[0:0]$8050 $1\mul_op__imm_data__ok$5$next[0:0]$8042 $1\mul_op__imm_data__data$4$next[63:0]$8041 $1\mul_op__fn_unit$3$next[13:0]$8040 $1\mul_op__insn_type$2$next[6:0]$8044 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -302581,20 +321472,20 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7721 $1\mul_op__is_signed$12$next[0:0]$7724 $1\mul_op__is_32bit$11$next[0:0]$7723 $1\mul_op__write_cr0$10$next[0:0]$7729 $1\mul_op__oe__ok$9$next[0:0]$7726 $1\mul_op__oe__oe$8$next[0:0]$7725 $1\mul_op__rc__ok$7$next[0:0]$7727 $1\mul_op__rc__rc$6$next[0:0]$7728 $1\mul_op__imm_data__ok$5$next[0:0]$7720 $1\mul_op__imm_data__data$4$next[63:0]$7719 $1\mul_op__fn_unit$3$next[11:0]$7718 $1\mul_op__insn_type$2$next[6:0]$7722 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8043 $1\mul_op__is_signed$12$next[0:0]$8046 $1\mul_op__is_32bit$11$next[0:0]$8045 $1\mul_op__write_cr0$10$next[0:0]$8051 $1\mul_op__oe__ok$9$next[0:0]$8048 $1\mul_op__oe__oe$8$next[0:0]$8047 $1\mul_op__rc__ok$7$next[0:0]$8049 $1\mul_op__rc__rc$6$next[0:0]$8050 $1\mul_op__imm_data__ok$5$next[0:0]$8042 $1\mul_op__imm_data__data$4$next[63:0]$8041 $1\mul_op__fn_unit$3$next[13:0]$8040 $1\mul_op__insn_type$2$next[6:0]$8044 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case - assign $1\mul_op__fn_unit$3$next[11:0]$7718 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7719 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7720 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7721 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7722 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$7723 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$7724 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$7725 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$7726 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$7727 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$7728 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$7729 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8040 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8041 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8042 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8043 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8044 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8045 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8046 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8047 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8048 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8049 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8050 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8051 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -302606,143 +321497,143 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$7730 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7731 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$7735 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$7734 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$7732 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$7733 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8052 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8053 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8057 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8056 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8054 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8055 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$7730 $1\mul_op__imm_data__data$4$next[63:0]$7719 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7731 $1\mul_op__imm_data__ok$5$next[0:0]$7720 - assign $2\mul_op__oe__oe$8$next[0:0]$7732 $1\mul_op__oe__oe$8$next[0:0]$7725 - assign $2\mul_op__oe__ok$9$next[0:0]$7733 $1\mul_op__oe__ok$9$next[0:0]$7726 - assign $2\mul_op__rc__ok$7$next[0:0]$7734 $1\mul_op__rc__ok$7$next[0:0]$7727 - assign $2\mul_op__rc__rc$6$next[0:0]$7735 $1\mul_op__rc__rc$6$next[0:0]$7728 + assign $2\mul_op__imm_data__data$4$next[63:0]$8052 $1\mul_op__imm_data__data$4$next[63:0]$8041 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8053 $1\mul_op__imm_data__ok$5$next[0:0]$8042 + assign $2\mul_op__oe__oe$8$next[0:0]$8054 $1\mul_op__oe__oe$8$next[0:0]$8047 + assign $2\mul_op__oe__ok$9$next[0:0]$8055 $1\mul_op__oe__ok$9$next[0:0]$8048 + assign $2\mul_op__rc__ok$7$next[0:0]$8056 $1\mul_op__rc__ok$7$next[0:0]$8049 + assign $2\mul_op__rc__rc$6$next[0:0]$8057 $1\mul_op__rc__rc$6$next[0:0]$8050 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7706 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7707 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7708 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7709 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7710 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7711 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7712 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7713 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7714 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7715 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7716 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7717 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8028 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8029 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8030 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8031 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8032 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8033 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8034 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8035 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8036 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8037 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8038 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8039 end - attribute \src "libresoc.v:144041.3-144053.6" - process $proc$libresoc.v:144041$7736 + attribute \src "libresoc.v:153908.3-153920.6" + process $proc$libresoc.v:153908$8058 assign { } { } assign { } { } - assign $0\o$next[128:0]$7737 $1\o$next[128:0]$7738 - attribute \src "libresoc.v:144042.5-144042.29" + assign $0\o$next[128:0]$8059 $1\o$next[128:0]$8060 + attribute \src "libresoc.v:153909.5-153909.29" switch \initial - attribute \src "libresoc.v:144042.9-144042.17" + attribute \src "libresoc.v:153909.9-153909.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\o$next[128:0]$7738 \o$49 + assign $1\o$next[128:0]$8060 \o$49 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\o$next[128:0]$7738 \o$49 + assign $1\o$next[128:0]$8060 \o$49 case - assign $1\o$next[128:0]$7738 \o + assign $1\o$next[128:0]$8060 \o end sync always - update \o$next $0\o$next[128:0]$7737 + update \o$next $0\o$next[128:0]$8059 end - attribute \src "libresoc.v:144054.3-144066.6" - process $proc$libresoc.v:144054$7739 + attribute \src "libresoc.v:153921.3-153933.6" + process $proc$libresoc.v:153921$8061 assign { } { } assign { } { } - assign $0\xer_so$14$next[0:0]$7740 $1\xer_so$14$next[0:0]$7741 - attribute \src "libresoc.v:144055.5-144055.29" + assign $0\xer_so$14$next[0:0]$8062 $1\xer_so$14$next[0:0]$8063 + attribute \src "libresoc.v:153922.5-153922.29" switch \initial - attribute \src "libresoc.v:144055.9-144055.17" + attribute \src "libresoc.v:153922.9-153922.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$14$next[0:0]$7741 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8063 \xer_so$50 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$14$next[0:0]$7741 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8063 \xer_so$50 case - assign $1\xer_so$14$next[0:0]$7741 \xer_so$14 + assign $1\xer_so$14$next[0:0]$8063 \xer_so$14 end sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$7740 + update \xer_so$14$next $0\xer_so$14$next[0:0]$8062 end - attribute \src "libresoc.v:144067.3-144079.6" - process $proc$libresoc.v:144067$7742 + attribute \src "libresoc.v:153934.3-153946.6" + process $proc$libresoc.v:153934$8064 assign { } { } assign { } { } - assign $0\neg_res$15$next[0:0]$7743 $1\neg_res$15$next[0:0]$7744 - attribute \src "libresoc.v:144068.5-144068.29" + assign $0\neg_res$15$next[0:0]$8065 $1\neg_res$15$next[0:0]$8066 + attribute \src "libresoc.v:153935.5-153935.29" switch \initial - attribute \src "libresoc.v:144068.9-144068.17" + attribute \src "libresoc.v:153935.9-153935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$15$next[0:0]$7744 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8066 \neg_res$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$15$next[0:0]$7744 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8066 \neg_res$51 case - assign $1\neg_res$15$next[0:0]$7744 \neg_res$15 + assign $1\neg_res$15$next[0:0]$8066 \neg_res$15 end sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$7743 + update \neg_res$15$next $0\neg_res$15$next[0:0]$8065 end - attribute \src "libresoc.v:144080.3-144092.6" - process $proc$libresoc.v:144080$7745 + attribute \src "libresoc.v:153947.3-153959.6" + process $proc$libresoc.v:153947$8067 assign { } { } assign { } { } - assign $0\neg_res32$16$next[0:0]$7746 $1\neg_res32$16$next[0:0]$7747 - attribute \src "libresoc.v:144081.5-144081.29" + assign $0\neg_res32$16$next[0:0]$8068 $1\neg_res32$16$next[0:0]$8069 + attribute \src "libresoc.v:153948.5-153948.29" switch \initial - attribute \src "libresoc.v:144081.9-144081.17" + attribute \src "libresoc.v:153948.9-153948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$16$next[0:0]$7747 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$16$next[0:0]$7747 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$52 case - assign $1\neg_res32$16$next[0:0]$7747 \neg_res32$16 + assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$16 end sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$7746 + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8068 end - connect \$34 $and$libresoc.v:143892$7663_Y + connect \$34 $and$libresoc.v:153759$7985_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -302762,218 +321653,218 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:144115.1-145390.10" +attribute \src "libresoc.v:153982.1-155278.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:145308.3-145326.6" - wire width 4 $0\cr_a$next[3:0]$7866 - attribute \src "libresoc.v:145100.3-145101.25" + attribute \src "libresoc.v:155196.3-155214.6" + wire width 4 $0\cr_a$next[3:0]$8188 + attribute \src "libresoc.v:154988.3-154989.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:145308.3-145326.6" - wire $0\cr_a_ok$next[0:0]$7867 - attribute \src "libresoc.v:145102.3-145103.31" + attribute \src "libresoc.v:155196.3-155214.6" + wire $0\cr_a_ok$next[0:0]$8189 + attribute \src "libresoc.v:154990.3-154991.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:144116.7-144116.20" + attribute \src "libresoc.v:153983.7-153983.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145253.3-145288.6" - wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7829 - attribute \src "libresoc.v:145110.3-145111.53" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7797 - attribute \src "libresoc.v:144417.14-144417.43" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7887 - attribute \src "libresoc.v:145253.3-145288.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7830 - attribute \src "libresoc.v:145112.3-145113.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7799 - attribute \src "libresoc.v:144439.14-144439.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7889 - attribute \src "libresoc.v:145253.3-145288.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$7831 - attribute \src "libresoc.v:145114.3-145115.63" - wire $0\mul_op__imm_data__ok$5[0:0]$7801 - attribute \src "libresoc.v:144448.7-144448.38" - wire $0\mul_op__imm_data__ok$5[0:0]$7891 - attribute \src "libresoc.v:145253.3-145288.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$7832 - attribute \src "libresoc.v:145130.3-145131.49" - wire width 32 $0\mul_op__insn$13[31:0]$7817 - attribute \src "libresoc.v:144457.14-144457.39" - wire width 32 $0\mul_op__insn$13[31:0]$7893 - attribute \src "libresoc.v:145253.3-145288.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$7833 - attribute \src "libresoc.v:145108.3-145109.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7795 - attribute \src "libresoc.v:144614.13-144614.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$7895 - attribute \src "libresoc.v:145253.3-145288.6" - wire $0\mul_op__is_32bit$11$next[0:0]$7834 - attribute \src "libresoc.v:145126.3-145127.57" - wire $0\mul_op__is_32bit$11[0:0]$7813 - attribute \src "libresoc.v:144697.7-144697.35" - wire $0\mul_op__is_32bit$11[0:0]$7897 - attribute \src "libresoc.v:145253.3-145288.6" - wire $0\mul_op__is_signed$12$next[0:0]$7835 - attribute \src "libresoc.v:145128.3-145129.59" - wire $0\mul_op__is_signed$12[0:0]$7815 - attribute \src "libresoc.v:144706.7-144706.36" - wire $0\mul_op__is_signed$12[0:0]$7899 - attribute \src "libresoc.v:145253.3-145288.6" - wire $0\mul_op__oe__oe$8$next[0:0]$7836 - attribute \src "libresoc.v:145120.3-145121.51" - wire $0\mul_op__oe__oe$8[0:0]$7807 - attribute \src "libresoc.v:144717.7-144717.32" - wire $0\mul_op__oe__oe$8[0:0]$7901 - attribute \src "libresoc.v:145253.3-145288.6" - wire $0\mul_op__oe__ok$9$next[0:0]$7837 - attribute \src "libresoc.v:145122.3-145123.51" - wire $0\mul_op__oe__ok$9[0:0]$7809 - attribute \src "libresoc.v:144726.7-144726.32" - wire $0\mul_op__oe__ok$9[0:0]$7903 - attribute \src "libresoc.v:145253.3-145288.6" - wire $0\mul_op__rc__ok$7$next[0:0]$7838 - attribute \src "libresoc.v:145118.3-145119.51" - wire $0\mul_op__rc__ok$7[0:0]$7805 - attribute \src "libresoc.v:144735.7-144735.32" - wire $0\mul_op__rc__ok$7[0:0]$7905 - attribute \src "libresoc.v:145253.3-145288.6" - wire $0\mul_op__rc__rc$6$next[0:0]$7839 - attribute \src "libresoc.v:145116.3-145117.51" - wire $0\mul_op__rc__rc$6[0:0]$7803 - attribute \src "libresoc.v:144742.7-144742.32" - wire $0\mul_op__rc__rc$6[0:0]$7907 - attribute \src "libresoc.v:145253.3-145288.6" - wire $0\mul_op__write_cr0$10$next[0:0]$7840 - attribute \src "libresoc.v:145124.3-145125.59" - wire $0\mul_op__write_cr0$10[0:0]$7811 - attribute \src "libresoc.v:144751.7-144751.36" - wire $0\mul_op__write_cr0$10[0:0]$7909 - attribute \src "libresoc.v:145240.3-145252.6" - wire width 2 $0\muxid$1$next[1:0]$7826 - attribute \src "libresoc.v:145132.3-145133.33" - wire width 2 $0\muxid$1[1:0]$7819 - attribute \src "libresoc.v:144760.13-144760.29" - wire width 2 $0\muxid$1[1:0]$7911 - attribute \src "libresoc.v:145289.3-145307.6" - wire width 64 $0\o$14$next[63:0]$7861 - attribute \src "libresoc.v:145104.3-145105.27" - wire width 64 $0\o$14[63:0]$7792 - attribute \src "libresoc.v:144781.14-144781.43" - wire width 64 $0\o$14[63:0]$7913 - attribute \src "libresoc.v:145289.3-145307.6" - wire $0\o_ok$next[0:0]$7860 - attribute \src "libresoc.v:145106.3-145107.25" + attribute \src "libresoc.v:155141.3-155176.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8151 + attribute \src "libresoc.v:154998.3-154999.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8119 + attribute \src "libresoc.v:154294.14-154294.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8209 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8152 + attribute \src "libresoc.v:155000.3-155001.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8121 + attribute \src "libresoc.v:154318.14-154318.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8211 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8153 + attribute \src "libresoc.v:155002.3-155003.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8123 + attribute \src "libresoc.v:154327.7-154327.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8213 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8154 + attribute \src "libresoc.v:155018.3-155019.49" + wire width 32 $0\mul_op__insn$13[31:0]$8139 + attribute \src "libresoc.v:154336.14-154336.39" + wire width 32 $0\mul_op__insn$13[31:0]$8215 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8155 + attribute \src "libresoc.v:154996.3-154997.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8117 + attribute \src "libresoc.v:154495.13-154495.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8217 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8156 + attribute \src "libresoc.v:155014.3-155015.57" + wire $0\mul_op__is_32bit$11[0:0]$8135 + attribute \src "libresoc.v:154579.7-154579.35" + wire $0\mul_op__is_32bit$11[0:0]$8219 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__is_signed$12$next[0:0]$8157 + attribute \src "libresoc.v:155016.3-155017.59" + wire $0\mul_op__is_signed$12[0:0]$8137 + attribute \src "libresoc.v:154588.7-154588.36" + wire $0\mul_op__is_signed$12[0:0]$8221 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8158 + attribute \src "libresoc.v:155008.3-155009.51" + wire $0\mul_op__oe__oe$8[0:0]$8129 + attribute \src "libresoc.v:154599.7-154599.32" + wire $0\mul_op__oe__oe$8[0:0]$8223 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8159 + attribute \src "libresoc.v:155010.3-155011.51" + wire $0\mul_op__oe__ok$9[0:0]$8131 + attribute \src "libresoc.v:154608.7-154608.32" + wire $0\mul_op__oe__ok$9[0:0]$8225 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8160 + attribute \src "libresoc.v:155006.3-155007.51" + wire $0\mul_op__rc__ok$7[0:0]$8127 + attribute \src "libresoc.v:154617.7-154617.32" + wire $0\mul_op__rc__ok$7[0:0]$8227 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8161 + attribute \src "libresoc.v:155004.3-155005.51" + wire $0\mul_op__rc__rc$6[0:0]$8125 + attribute \src "libresoc.v:154624.7-154624.32" + wire $0\mul_op__rc__rc$6[0:0]$8229 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8162 + attribute \src "libresoc.v:155012.3-155013.59" + wire $0\mul_op__write_cr0$10[0:0]$8133 + attribute \src "libresoc.v:154633.7-154633.36" + wire $0\mul_op__write_cr0$10[0:0]$8231 + attribute \src "libresoc.v:155128.3-155140.6" + wire width 2 $0\muxid$1$next[1:0]$8148 + attribute \src "libresoc.v:155020.3-155021.33" + wire width 2 $0\muxid$1[1:0]$8141 + attribute \src "libresoc.v:154642.13-154642.29" + wire width 2 $0\muxid$1[1:0]$8233 + attribute \src "libresoc.v:155177.3-155195.6" + wire width 64 $0\o$14$next[63:0]$8183 + attribute \src "libresoc.v:154992.3-154993.27" + wire width 64 $0\o$14[63:0]$8114 + attribute \src "libresoc.v:154663.14-154663.43" + wire width 64 $0\o$14[63:0]$8235 + attribute \src "libresoc.v:155177.3-155195.6" + wire $0\o_ok$next[0:0]$8182 + attribute \src "libresoc.v:154994.3-154995.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:145222.3-145239.6" - wire $0\r_busy$next[0:0]$7822 - attribute \src "libresoc.v:145134.3-145135.29" + attribute \src "libresoc.v:155110.3-155127.6" + wire $0\r_busy$next[0:0]$8144 + attribute \src "libresoc.v:155022.3-155023.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:145327.3-145345.6" - wire width 2 $0\xer_ov$next[1:0]$7872 - attribute \src "libresoc.v:145096.3-145097.29" + attribute \src "libresoc.v:155215.3-155233.6" + wire width 2 $0\xer_ov$next[1:0]$8194 + attribute \src "libresoc.v:154984.3-154985.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:145327.3-145345.6" - wire $0\xer_ov_ok$next[0:0]$7873 - attribute \src "libresoc.v:145098.3-145099.35" + attribute \src "libresoc.v:155215.3-155233.6" + wire $0\xer_ov_ok$next[0:0]$8195 + attribute \src "libresoc.v:154986.3-154987.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:145346.3-145364.6" - wire $0\xer_so$15$next[0:0]$7879 - attribute \src "libresoc.v:145092.3-145093.37" - wire $0\xer_so$15[0:0]$7785 - attribute \src "libresoc.v:145077.7-145077.25" - wire $0\xer_so$15[0:0]$7919 - attribute \src "libresoc.v:145346.3-145364.6" - wire $0\xer_so_ok$next[0:0]$7878 - attribute \src "libresoc.v:145094.3-145095.35" + attribute \src "libresoc.v:155234.3-155252.6" + wire $0\xer_so$15$next[0:0]$8201 + attribute \src "libresoc.v:154980.3-154981.37" + wire $0\xer_so$15[0:0]$8107 + attribute \src "libresoc.v:154965.7-154965.25" + wire $0\xer_so$15[0:0]$8241 + attribute \src "libresoc.v:155234.3-155252.6" + wire $0\xer_so_ok$next[0:0]$8200 + attribute \src "libresoc.v:154982.3-154983.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:145308.3-145326.6" - wire width 4 $1\cr_a$next[3:0]$7868 - attribute \src "libresoc.v:144125.13-144125.24" + attribute \src "libresoc.v:155196.3-155214.6" + wire width 4 $1\cr_a$next[3:0]$8190 + attribute \src "libresoc.v:153992.13-153992.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:145308.3-145326.6" - wire $1\cr_a_ok$next[0:0]$7869 - attribute \src "libresoc.v:144134.7-144134.21" + attribute \src "libresoc.v:155196.3-155214.6" + wire $1\cr_a_ok$next[0:0]$8191 + attribute \src "libresoc.v:154001.7-154001.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:145253.3-145288.6" - wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7841 - attribute \src "libresoc.v:145253.3-145288.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7842 - attribute \src "libresoc.v:145253.3-145288.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$7843 - attribute \src "libresoc.v:145253.3-145288.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$7844 - attribute \src "libresoc.v:145253.3-145288.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$7845 - attribute \src "libresoc.v:145253.3-145288.6" - wire $1\mul_op__is_32bit$11$next[0:0]$7846 - attribute \src "libresoc.v:145253.3-145288.6" - wire $1\mul_op__is_signed$12$next[0:0]$7847 - attribute \src "libresoc.v:145253.3-145288.6" - wire $1\mul_op__oe__oe$8$next[0:0]$7848 - attribute \src "libresoc.v:145253.3-145288.6" - wire $1\mul_op__oe__ok$9$next[0:0]$7849 - attribute \src "libresoc.v:145253.3-145288.6" - wire $1\mul_op__rc__ok$7$next[0:0]$7850 - attribute \src "libresoc.v:145253.3-145288.6" - wire $1\mul_op__rc__rc$6$next[0:0]$7851 - attribute \src "libresoc.v:145253.3-145288.6" - wire $1\mul_op__write_cr0$10$next[0:0]$7852 - attribute \src "libresoc.v:145240.3-145252.6" - wire width 2 $1\muxid$1$next[1:0]$7827 - attribute \src "libresoc.v:145289.3-145307.6" - wire width 64 $1\o$14$next[63:0]$7863 - attribute \src "libresoc.v:145289.3-145307.6" - wire $1\o_ok$next[0:0]$7862 - attribute \src "libresoc.v:144788.7-144788.18" + attribute \src "libresoc.v:155141.3-155176.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8163 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8164 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8165 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8166 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8167 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8168 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__is_signed$12$next[0:0]$8169 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8170 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8171 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8172 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8173 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8174 + attribute \src "libresoc.v:155128.3-155140.6" + wire width 2 $1\muxid$1$next[1:0]$8149 + attribute \src "libresoc.v:155177.3-155195.6" + wire width 64 $1\o$14$next[63:0]$8185 + attribute \src "libresoc.v:155177.3-155195.6" + wire $1\o_ok$next[0:0]$8184 + attribute \src "libresoc.v:154670.7-154670.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:145222.3-145239.6" - wire $1\r_busy$next[0:0]$7823 - attribute \src "libresoc.v:145054.7-145054.20" + attribute \src "libresoc.v:155110.3-155127.6" + wire $1\r_busy$next[0:0]$8145 + attribute \src "libresoc.v:154942.7-154942.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:145327.3-145345.6" - wire width 2 $1\xer_ov$next[1:0]$7874 - attribute \src "libresoc.v:145059.13-145059.26" + attribute \src "libresoc.v:155215.3-155233.6" + wire width 2 $1\xer_ov$next[1:0]$8196 + attribute \src "libresoc.v:154947.13-154947.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:145327.3-145345.6" - wire $1\xer_ov_ok$next[0:0]$7875 - attribute \src "libresoc.v:145066.7-145066.23" + attribute \src "libresoc.v:155215.3-155233.6" + wire $1\xer_ov_ok$next[0:0]$8197 + attribute \src "libresoc.v:154954.7-154954.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:145346.3-145364.6" - wire $1\xer_so$15$next[0:0]$7881 - attribute \src "libresoc.v:145346.3-145364.6" - wire $1\xer_so_ok$next[0:0]$7880 - attribute \src "libresoc.v:145084.7-145084.23" + attribute \src "libresoc.v:155234.3-155252.6" + wire $1\xer_so$15$next[0:0]$8203 + attribute \src "libresoc.v:155234.3-155252.6" + wire $1\xer_so_ok$next[0:0]$8202 + attribute \src "libresoc.v:154972.7-154972.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:145308.3-145326.6" - wire $2\cr_a_ok$next[0:0]$7870 - attribute \src "libresoc.v:145253.3-145288.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7853 - attribute \src "libresoc.v:145253.3-145288.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$7854 - attribute \src "libresoc.v:145253.3-145288.6" - wire $2\mul_op__oe__oe$8$next[0:0]$7855 - attribute \src "libresoc.v:145253.3-145288.6" - wire $2\mul_op__oe__ok$9$next[0:0]$7856 - attribute \src "libresoc.v:145253.3-145288.6" - wire $2\mul_op__rc__ok$7$next[0:0]$7857 - attribute \src "libresoc.v:145253.3-145288.6" - wire $2\mul_op__rc__rc$6$next[0:0]$7858 - attribute \src "libresoc.v:145289.3-145307.6" - wire $2\o_ok$next[0:0]$7864 - attribute \src "libresoc.v:145222.3-145239.6" - wire $2\r_busy$next[0:0]$7824 - attribute \src "libresoc.v:145327.3-145345.6" - wire $2\xer_ov_ok$next[0:0]$7876 - attribute \src "libresoc.v:145346.3-145364.6" - wire $2\xer_so_ok$next[0:0]$7882 - attribute \src "libresoc.v:145091.18-145091.118" - wire $and$libresoc.v:145091$7783_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + attribute \src "libresoc.v:155196.3-155214.6" + wire $2\cr_a_ok$next[0:0]$8192 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8175 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8176 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8177 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8178 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8179 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8180 + attribute \src "libresoc.v:155177.3-155195.6" + wire $2\o_ok$next[0:0]$8186 + attribute \src "libresoc.v:155110.3-155127.6" + wire $2\r_busy$next[0:0]$8146 + attribute \src "libresoc.v:155215.3-155233.6" + wire $2\xer_ov_ok$next[0:0]$8198 + attribute \src "libresoc.v:155234.3-155252.6" + wire $2\xer_so_ok$next[0:0]$8204 + attribute \src "libresoc.v:154979.18-154979.118" + wire $and$libresoc.v:154979$8105_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 38 \cr_a @@ -302993,38 +321884,42 @@ module \mul_pipe3 wire \cr_a_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:144116.7-144116.15" + attribute \src "libresoc.v:153983.7-153983.15" wire \initial attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul3_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul3_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul3_mul_op__fn_unit$18 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul3_mul_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -303111,6 +322006,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul3_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -303187,6 +322083,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul3_mul_op__insn_type$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -303217,9 +322114,9 @@ module \mul_pipe3 wire \mul3_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__write_cr0$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul3_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul3_muxid$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire \mul3_neg_res @@ -303240,52 +322137,58 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul3_xer_so_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$60 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -303384,6 +322287,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -303460,6 +322364,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -303538,6 +322443,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -303596,19 +322502,19 @@ module \mul_pipe3 wire \mul_op__write_cr0$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 22 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 21 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire input 19 \neg_res @@ -303637,35 +322543,39 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_cr_a_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_mul_op__fn_unit$33 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_mul_op__fn_unit$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -303752,6 +322662,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -303828,6 +322739,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_mul_op__insn_type$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -303858,9 +322770,9 @@ module \mul_pipe3 wire \output_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__write_cr0$40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_o @@ -303882,17 +322794,17 @@ module \mul_pipe3 wire \output_xer_so$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 40 \xer_ov @@ -303924,8 +322836,8 @@ module \mul_pipe3 wire \xer_so_ok$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:145091$7783 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:154979$8105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303933,10 +322845,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:145091$7783_Y + connect \Y $and$libresoc.v:154979$8105_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:145136.8-145172.4" + attribute \src "libresoc.v:155024.8-155060.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -303975,13 +322887,13 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:145173.10-145176.4" + attribute \src "libresoc.v:155061.10-155064.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:145177.16-145217.4" + attribute \src "libresoc.v:155065.16-155105.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 @@ -304024,415 +322936,415 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:145218.10-145221.4" + attribute \src "libresoc.v:155106.10-155109.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:144116.7-144116.20" - process $proc$libresoc.v:144116$7883 + attribute \src "libresoc.v:153983.7-153983.20" + process $proc$libresoc.v:153983$8205 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144125.13-144125.24" - process $proc$libresoc.v:144125$7884 + attribute \src "libresoc.v:153992.13-153992.24" + process $proc$libresoc.v:153992$8206 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:144134.7-144134.21" - process $proc$libresoc.v:144134$7885 + attribute \src "libresoc.v:154001.7-154001.21" + process $proc$libresoc.v:154001$8207 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:144417.14-144417.43" - process $proc$libresoc.v:144417$7886 + attribute \src "libresoc.v:154294.14-154294.44" + process $proc$libresoc.v:154294$8208 assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7887 12'000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8209 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7887 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8209 end - attribute \src "libresoc.v:144439.14-144439.63" - process $proc$libresoc.v:144439$7888 + attribute \src "libresoc.v:154318.14-154318.63" + process $proc$libresoc.v:154318$8210 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7889 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8211 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7889 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8211 end - attribute \src "libresoc.v:144448.7-144448.38" - process $proc$libresoc.v:144448$7890 + attribute \src "libresoc.v:154327.7-154327.38" + process $proc$libresoc.v:154327$8212 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7891 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8213 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7891 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8213 end - attribute \src "libresoc.v:144457.14-144457.39" - process $proc$libresoc.v:144457$7892 + attribute \src "libresoc.v:154336.14-154336.39" + process $proc$libresoc.v:154336$8214 assign { } { } - assign $0\mul_op__insn$13[31:0]$7893 0 + assign $0\mul_op__insn$13[31:0]$8215 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7893 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8215 end - attribute \src "libresoc.v:144614.13-144614.42" - process $proc$libresoc.v:144614$7894 + attribute \src "libresoc.v:154495.13-154495.42" + process $proc$libresoc.v:154495$8216 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7895 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8217 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7895 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8217 end - attribute \src "libresoc.v:144697.7-144697.35" - process $proc$libresoc.v:144697$7896 + attribute \src "libresoc.v:154579.7-154579.35" + process $proc$libresoc.v:154579$8218 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7897 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8219 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7897 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8219 end - attribute \src "libresoc.v:144706.7-144706.36" - process $proc$libresoc.v:144706$7898 + attribute \src "libresoc.v:154588.7-154588.36" + process $proc$libresoc.v:154588$8220 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7899 1'0 + assign $0\mul_op__is_signed$12[0:0]$8221 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7899 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8221 end - attribute \src "libresoc.v:144717.7-144717.32" - process $proc$libresoc.v:144717$7900 + attribute \src "libresoc.v:154599.7-154599.32" + process $proc$libresoc.v:154599$8222 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7901 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8223 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7901 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8223 end - attribute \src "libresoc.v:144726.7-144726.32" - process $proc$libresoc.v:144726$7902 + attribute \src "libresoc.v:154608.7-154608.32" + process $proc$libresoc.v:154608$8224 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7903 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8225 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7903 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8225 end - attribute \src "libresoc.v:144735.7-144735.32" - process $proc$libresoc.v:144735$7904 + attribute \src "libresoc.v:154617.7-154617.32" + process $proc$libresoc.v:154617$8226 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7905 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8227 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7905 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8227 end - attribute \src "libresoc.v:144742.7-144742.32" - process $proc$libresoc.v:144742$7906 + attribute \src "libresoc.v:154624.7-154624.32" + process $proc$libresoc.v:154624$8228 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7907 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8229 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7907 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8229 end - attribute \src "libresoc.v:144751.7-144751.36" - process $proc$libresoc.v:144751$7908 + attribute \src "libresoc.v:154633.7-154633.36" + process $proc$libresoc.v:154633$8230 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7909 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8231 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7909 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8231 end - attribute \src "libresoc.v:144760.13-144760.29" - process $proc$libresoc.v:144760$7910 + attribute \src "libresoc.v:154642.13-154642.29" + process $proc$libresoc.v:154642$8232 assign { } { } - assign $0\muxid$1[1:0]$7911 2'00 + assign $0\muxid$1[1:0]$8233 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7911 + update \muxid$1 $0\muxid$1[1:0]$8233 end - attribute \src "libresoc.v:144781.14-144781.43" - process $proc$libresoc.v:144781$7912 + attribute \src "libresoc.v:154663.14-154663.43" + process $proc$libresoc.v:154663$8234 assign { } { } - assign $0\o$14[63:0]$7913 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$14[63:0]$8235 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$14 $0\o$14[63:0]$7913 + update \o$14 $0\o$14[63:0]$8235 end - attribute \src "libresoc.v:144788.7-144788.18" - process $proc$libresoc.v:144788$7914 + attribute \src "libresoc.v:154670.7-154670.18" + process $proc$libresoc.v:154670$8236 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:145054.7-145054.20" - process $proc$libresoc.v:145054$7915 + attribute \src "libresoc.v:154942.7-154942.20" + process $proc$libresoc.v:154942$8237 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:145059.13-145059.26" - process $proc$libresoc.v:145059$7916 + attribute \src "libresoc.v:154947.13-154947.26" + process $proc$libresoc.v:154947$8238 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:145066.7-145066.23" - process $proc$libresoc.v:145066$7917 + attribute \src "libresoc.v:154954.7-154954.23" + process $proc$libresoc.v:154954$8239 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:145077.7-145077.25" - process $proc$libresoc.v:145077$7918 + attribute \src "libresoc.v:154965.7-154965.25" + process $proc$libresoc.v:154965$8240 assign { } { } - assign $0\xer_so$15[0:0]$7919 1'0 + assign $0\xer_so$15[0:0]$8241 1'0 sync always sync init - update \xer_so$15 $0\xer_so$15[0:0]$7919 + update \xer_so$15 $0\xer_so$15[0:0]$8241 end - attribute \src "libresoc.v:145084.7-145084.23" - process $proc$libresoc.v:145084$7920 + attribute \src "libresoc.v:154972.7-154972.23" + process $proc$libresoc.v:154972$8242 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:145092.3-145093.37" - process $proc$libresoc.v:145092$7784 + attribute \src "libresoc.v:154980.3-154981.37" + process $proc$libresoc.v:154980$8106 assign { } { } - assign $0\xer_so$15[0:0]$7785 \xer_so$15$next + assign $0\xer_so$15[0:0]$8107 \xer_so$15$next sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$7785 + update \xer_so$15 $0\xer_so$15[0:0]$8107 end - attribute \src "libresoc.v:145094.3-145095.35" - process $proc$libresoc.v:145094$7786 + attribute \src "libresoc.v:154982.3-154983.35" + process $proc$libresoc.v:154982$8108 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:145096.3-145097.29" - process $proc$libresoc.v:145096$7787 + attribute \src "libresoc.v:154984.3-154985.29" + process $proc$libresoc.v:154984$8109 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:145098.3-145099.35" - process $proc$libresoc.v:145098$7788 + attribute \src "libresoc.v:154986.3-154987.35" + process $proc$libresoc.v:154986$8110 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:145100.3-145101.25" - process $proc$libresoc.v:145100$7789 + attribute \src "libresoc.v:154988.3-154989.25" + process $proc$libresoc.v:154988$8111 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:145102.3-145103.31" - process $proc$libresoc.v:145102$7790 + attribute \src "libresoc.v:154990.3-154991.31" + process $proc$libresoc.v:154990$8112 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:145104.3-145105.27" - process $proc$libresoc.v:145104$7791 + attribute \src "libresoc.v:154992.3-154993.27" + process $proc$libresoc.v:154992$8113 assign { } { } - assign $0\o$14[63:0]$7792 \o$14$next + assign $0\o$14[63:0]$8114 \o$14$next sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$7792 + update \o$14 $0\o$14[63:0]$8114 end - attribute \src "libresoc.v:145106.3-145107.25" - process $proc$libresoc.v:145106$7793 + attribute \src "libresoc.v:154994.3-154995.25" + process $proc$libresoc.v:154994$8115 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:145108.3-145109.57" - process $proc$libresoc.v:145108$7794 + attribute \src "libresoc.v:154996.3-154997.57" + process $proc$libresoc.v:154996$8116 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7795 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8117 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7795 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8117 end - attribute \src "libresoc.v:145110.3-145111.53" - process $proc$libresoc.v:145110$7796 + attribute \src "libresoc.v:154998.3-154999.53" + process $proc$libresoc.v:154998$8118 assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7797 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8119 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7797 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8119 end - attribute \src "libresoc.v:145112.3-145113.67" - process $proc$libresoc.v:145112$7798 + attribute \src "libresoc.v:155000.3-155001.67" + process $proc$libresoc.v:155000$8120 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7799 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8121 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7799 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8121 end - attribute \src "libresoc.v:145114.3-145115.63" - process $proc$libresoc.v:145114$7800 + attribute \src "libresoc.v:155002.3-155003.63" + process $proc$libresoc.v:155002$8122 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7801 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8123 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7801 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8123 end - attribute \src "libresoc.v:145116.3-145117.51" - process $proc$libresoc.v:145116$7802 + attribute \src "libresoc.v:155004.3-155005.51" + process $proc$libresoc.v:155004$8124 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7803 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8125 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7803 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8125 end - attribute \src "libresoc.v:145118.3-145119.51" - process $proc$libresoc.v:145118$7804 + attribute \src "libresoc.v:155006.3-155007.51" + process $proc$libresoc.v:155006$8126 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7805 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8127 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7805 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8127 end - attribute \src "libresoc.v:145120.3-145121.51" - process $proc$libresoc.v:145120$7806 + attribute \src "libresoc.v:155008.3-155009.51" + process $proc$libresoc.v:155008$8128 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7807 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8129 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7807 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8129 end - attribute \src "libresoc.v:145122.3-145123.51" - process $proc$libresoc.v:145122$7808 + attribute \src "libresoc.v:155010.3-155011.51" + process $proc$libresoc.v:155010$8130 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7809 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8131 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7809 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8131 end - attribute \src "libresoc.v:145124.3-145125.59" - process $proc$libresoc.v:145124$7810 + attribute \src "libresoc.v:155012.3-155013.59" + process $proc$libresoc.v:155012$8132 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7811 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8133 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7811 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8133 end - attribute \src "libresoc.v:145126.3-145127.57" - process $proc$libresoc.v:145126$7812 + attribute \src "libresoc.v:155014.3-155015.57" + process $proc$libresoc.v:155014$8134 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7813 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8135 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7813 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8135 end - attribute \src "libresoc.v:145128.3-145129.59" - process $proc$libresoc.v:145128$7814 + attribute \src "libresoc.v:155016.3-155017.59" + process $proc$libresoc.v:155016$8136 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7815 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8137 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7815 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8137 end - attribute \src "libresoc.v:145130.3-145131.49" - process $proc$libresoc.v:145130$7816 + attribute \src "libresoc.v:155018.3-155019.49" + process $proc$libresoc.v:155018$8138 assign { } { } - assign $0\mul_op__insn$13[31:0]$7817 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8139 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7817 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8139 end - attribute \src "libresoc.v:145132.3-145133.33" - process $proc$libresoc.v:145132$7818 + attribute \src "libresoc.v:155020.3-155021.33" + process $proc$libresoc.v:155020$8140 assign { } { } - assign $0\muxid$1[1:0]$7819 \muxid$1$next + assign $0\muxid$1[1:0]$8141 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7819 + update \muxid$1 $0\muxid$1[1:0]$8141 end - attribute \src "libresoc.v:145134.3-145135.29" - process $proc$libresoc.v:145134$7820 + attribute \src "libresoc.v:155022.3-155023.29" + process $proc$libresoc.v:155022$8142 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:145222.3-145239.6" - process $proc$libresoc.v:145222$7821 + attribute \src "libresoc.v:155110.3-155127.6" + process $proc$libresoc.v:155110$8143 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7822 $2\r_busy$next[0:0]$7824 - attribute \src "libresoc.v:145223.5-145223.29" + assign $0\r_busy$next[0:0]$8144 $2\r_busy$next[0:0]$8146 + attribute \src "libresoc.v:155111.5-155111.29" switch \initial - attribute \src "libresoc.v:145223.9-145223.17" + attribute \src "libresoc.v:155111.9-155111.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7823 1'1 + assign $1\r_busy$next[0:0]$8145 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7823 1'0 + assign $1\r_busy$next[0:0]$8145 1'0 case - assign $1\r_busy$next[0:0]$7823 \r_busy + assign $1\r_busy$next[0:0]$8145 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7824 1'0 + assign $2\r_busy$next[0:0]$8146 1'0 case - assign $2\r_busy$next[0:0]$7824 $1\r_busy$next[0:0]$7823 + assign $2\r_busy$next[0:0]$8146 $1\r_busy$next[0:0]$8145 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7822 + update \r_busy$next $0\r_busy$next[0:0]$8144 end - attribute \src "libresoc.v:145240.3-145252.6" - process $proc$libresoc.v:145240$7825 + attribute \src "libresoc.v:155128.3-155140.6" + process $proc$libresoc.v:155128$8147 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$7826 $1\muxid$1$next[1:0]$7827 - attribute \src "libresoc.v:145241.5-145241.29" + assign $0\muxid$1$next[1:0]$8148 $1\muxid$1$next[1:0]$8149 + attribute \src "libresoc.v:155129.5-155129.29" switch \initial - attribute \src "libresoc.v:145241.9-145241.17" + attribute \src "libresoc.v:155129.9-155129.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$7827 \muxid$58 + assign $1\muxid$1$next[1:0]$8149 \muxid$58 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$7827 \muxid$58 + assign $1\muxid$1$next[1:0]$8149 \muxid$58 case - assign $1\muxid$1$next[1:0]$7827 \muxid$1 + assign $1\muxid$1$next[1:0]$8149 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7826 + update \muxid$1$next $0\muxid$1$next[1:0]$8148 end - attribute \src "libresoc.v:145253.3-145288.6" - process $proc$libresoc.v:145253$7828 + attribute \src "libresoc.v:155141.3-155176.6" + process $proc$libresoc.v:155141$8150 assign { } { } assign { } { } assign { } { } @@ -304457,31 +323369,31 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[11:0]$7829 $1\mul_op__fn_unit$3$next[11:0]$7841 + assign $0\mul_op__fn_unit$3$next[13:0]$8151 $1\mul_op__fn_unit$3$next[13:0]$8163 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7832 $1\mul_op__insn$13$next[31:0]$7844 - assign $0\mul_op__insn_type$2$next[6:0]$7833 $1\mul_op__insn_type$2$next[6:0]$7845 - assign $0\mul_op__is_32bit$11$next[0:0]$7834 $1\mul_op__is_32bit$11$next[0:0]$7846 - assign $0\mul_op__is_signed$12$next[0:0]$7835 $1\mul_op__is_signed$12$next[0:0]$7847 + assign $0\mul_op__insn$13$next[31:0]$8154 $1\mul_op__insn$13$next[31:0]$8166 + assign $0\mul_op__insn_type$2$next[6:0]$8155 $1\mul_op__insn_type$2$next[6:0]$8167 + assign $0\mul_op__is_32bit$11$next[0:0]$8156 $1\mul_op__is_32bit$11$next[0:0]$8168 + assign $0\mul_op__is_signed$12$next[0:0]$8157 $1\mul_op__is_signed$12$next[0:0]$8169 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7840 $1\mul_op__write_cr0$10$next[0:0]$7852 - assign $0\mul_op__imm_data__data$4$next[63:0]$7830 $2\mul_op__imm_data__data$4$next[63:0]$7853 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7831 $2\mul_op__imm_data__ok$5$next[0:0]$7854 - assign $0\mul_op__oe__oe$8$next[0:0]$7836 $2\mul_op__oe__oe$8$next[0:0]$7855 - assign $0\mul_op__oe__ok$9$next[0:0]$7837 $2\mul_op__oe__ok$9$next[0:0]$7856 - assign $0\mul_op__rc__ok$7$next[0:0]$7838 $2\mul_op__rc__ok$7$next[0:0]$7857 - assign $0\mul_op__rc__rc$6$next[0:0]$7839 $2\mul_op__rc__rc$6$next[0:0]$7858 - attribute \src "libresoc.v:145254.5-145254.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8162 $1\mul_op__write_cr0$10$next[0:0]$8174 + assign $0\mul_op__imm_data__data$4$next[63:0]$8152 $2\mul_op__imm_data__data$4$next[63:0]$8175 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8153 $2\mul_op__imm_data__ok$5$next[0:0]$8176 + assign $0\mul_op__oe__oe$8$next[0:0]$8158 $2\mul_op__oe__oe$8$next[0:0]$8177 + assign $0\mul_op__oe__ok$9$next[0:0]$8159 $2\mul_op__oe__ok$9$next[0:0]$8178 + assign $0\mul_op__rc__ok$7$next[0:0]$8160 $2\mul_op__rc__ok$7$next[0:0]$8179 + assign $0\mul_op__rc__rc$6$next[0:0]$8161 $2\mul_op__rc__rc$6$next[0:0]$8180 + attribute \src "libresoc.v:155142.5-155142.29" switch \initial - attribute \src "libresoc.v:145254.9-145254.17" + attribute \src "libresoc.v:155142.9-155142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -304497,7 +323409,7 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7844 $1\mul_op__is_signed$12$next[0:0]$7847 $1\mul_op__is_32bit$11$next[0:0]$7846 $1\mul_op__write_cr0$10$next[0:0]$7852 $1\mul_op__oe__ok$9$next[0:0]$7849 $1\mul_op__oe__oe$8$next[0:0]$7848 $1\mul_op__rc__ok$7$next[0:0]$7850 $1\mul_op__rc__rc$6$next[0:0]$7851 $1\mul_op__imm_data__ok$5$next[0:0]$7843 $1\mul_op__imm_data__data$4$next[63:0]$7842 $1\mul_op__fn_unit$3$next[11:0]$7841 $1\mul_op__insn_type$2$next[6:0]$7845 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8166 $1\mul_op__is_signed$12$next[0:0]$8169 $1\mul_op__is_32bit$11$next[0:0]$8168 $1\mul_op__write_cr0$10$next[0:0]$8174 $1\mul_op__oe__ok$9$next[0:0]$8171 $1\mul_op__oe__oe$8$next[0:0]$8170 $1\mul_op__rc__ok$7$next[0:0]$8172 $1\mul_op__rc__rc$6$next[0:0]$8173 $1\mul_op__imm_data__ok$5$next[0:0]$8165 $1\mul_op__imm_data__data$4$next[63:0]$8164 $1\mul_op__fn_unit$3$next[13:0]$8163 $1\mul_op__insn_type$2$next[6:0]$8167 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -304512,20 +323424,20 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7844 $1\mul_op__is_signed$12$next[0:0]$7847 $1\mul_op__is_32bit$11$next[0:0]$7846 $1\mul_op__write_cr0$10$next[0:0]$7852 $1\mul_op__oe__ok$9$next[0:0]$7849 $1\mul_op__oe__oe$8$next[0:0]$7848 $1\mul_op__rc__ok$7$next[0:0]$7850 $1\mul_op__rc__rc$6$next[0:0]$7851 $1\mul_op__imm_data__ok$5$next[0:0]$7843 $1\mul_op__imm_data__data$4$next[63:0]$7842 $1\mul_op__fn_unit$3$next[11:0]$7841 $1\mul_op__insn_type$2$next[6:0]$7845 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8166 $1\mul_op__is_signed$12$next[0:0]$8169 $1\mul_op__is_32bit$11$next[0:0]$8168 $1\mul_op__write_cr0$10$next[0:0]$8174 $1\mul_op__oe__ok$9$next[0:0]$8171 $1\mul_op__oe__oe$8$next[0:0]$8170 $1\mul_op__rc__ok$7$next[0:0]$8172 $1\mul_op__rc__rc$6$next[0:0]$8173 $1\mul_op__imm_data__ok$5$next[0:0]$8165 $1\mul_op__imm_data__data$4$next[63:0]$8164 $1\mul_op__fn_unit$3$next[13:0]$8163 $1\mul_op__insn_type$2$next[6:0]$8167 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } case - assign $1\mul_op__fn_unit$3$next[11:0]$7841 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7842 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7843 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7844 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7845 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$7846 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$7847 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$7848 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$7849 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$7850 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$7851 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$7852 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8163 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8164 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8165 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8166 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8167 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8168 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8169 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8170 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8171 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8172 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8173 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8174 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -304537,211 +323449,211 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$7853 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7854 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$7858 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$7857 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$7855 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$7856 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8175 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8176 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8180 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8179 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8177 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8178 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$7853 $1\mul_op__imm_data__data$4$next[63:0]$7842 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7854 $1\mul_op__imm_data__ok$5$next[0:0]$7843 - assign $2\mul_op__oe__oe$8$next[0:0]$7855 $1\mul_op__oe__oe$8$next[0:0]$7848 - assign $2\mul_op__oe__ok$9$next[0:0]$7856 $1\mul_op__oe__ok$9$next[0:0]$7849 - assign $2\mul_op__rc__ok$7$next[0:0]$7857 $1\mul_op__rc__ok$7$next[0:0]$7850 - assign $2\mul_op__rc__rc$6$next[0:0]$7858 $1\mul_op__rc__rc$6$next[0:0]$7851 + assign $2\mul_op__imm_data__data$4$next[63:0]$8175 $1\mul_op__imm_data__data$4$next[63:0]$8164 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8176 $1\mul_op__imm_data__ok$5$next[0:0]$8165 + assign $2\mul_op__oe__oe$8$next[0:0]$8177 $1\mul_op__oe__oe$8$next[0:0]$8170 + assign $2\mul_op__oe__ok$9$next[0:0]$8178 $1\mul_op__oe__ok$9$next[0:0]$8171 + assign $2\mul_op__rc__ok$7$next[0:0]$8179 $1\mul_op__rc__ok$7$next[0:0]$8172 + assign $2\mul_op__rc__rc$6$next[0:0]$8180 $1\mul_op__rc__rc$6$next[0:0]$8173 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7829 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7830 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7831 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7832 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7833 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7834 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7835 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7836 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7837 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7838 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7839 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7840 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8151 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8152 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8153 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8154 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8155 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8156 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8157 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8158 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8159 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8160 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8161 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8162 end - attribute \src "libresoc.v:145289.3-145307.6" - process $proc$libresoc.v:145289$7859 + attribute \src "libresoc.v:155177.3-155195.6" + process $proc$libresoc.v:155177$8181 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$14$next[63:0]$7861 $1\o$14$next[63:0]$7863 - assign $0\o_ok$next[0:0]$7860 $2\o_ok$next[0:0]$7864 - attribute \src "libresoc.v:145290.5-145290.29" + assign $0\o$14$next[63:0]$8183 $1\o$14$next[63:0]$8185 + assign $0\o_ok$next[0:0]$8182 $2\o_ok$next[0:0]$8186 + attribute \src "libresoc.v:155178.5-155178.29" switch \initial - attribute \src "libresoc.v:145290.9-145290.17" + attribute \src "libresoc.v:155178.9-155178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$7862 $1\o$14$next[63:0]$7863 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8184 $1\o$14$next[63:0]$8185 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$7862 $1\o$14$next[63:0]$7863 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8184 $1\o$14$next[63:0]$8185 } { \o_ok$72 \o$71 } case - assign $1\o_ok$next[0:0]$7862 \o_ok - assign $1\o$14$next[63:0]$7863 \o$14 + assign $1\o_ok$next[0:0]$8184 \o_ok + assign $1\o$14$next[63:0]$8185 \o$14 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$7864 1'0 + assign $2\o_ok$next[0:0]$8186 1'0 case - assign $2\o_ok$next[0:0]$7864 $1\o_ok$next[0:0]$7862 + assign $2\o_ok$next[0:0]$8186 $1\o_ok$next[0:0]$8184 end sync always - update \o_ok$next $0\o_ok$next[0:0]$7860 - update \o$14$next $0\o$14$next[63:0]$7861 + update \o_ok$next $0\o_ok$next[0:0]$8182 + update \o$14$next $0\o$14$next[63:0]$8183 end - attribute \src "libresoc.v:145308.3-145326.6" - process $proc$libresoc.v:145308$7865 + attribute \src "libresoc.v:155196.3-155214.6" + process $proc$libresoc.v:155196$8187 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$7866 $1\cr_a$next[3:0]$7868 + assign $0\cr_a$next[3:0]$8188 $1\cr_a$next[3:0]$8190 assign { } { } - assign $0\cr_a_ok$next[0:0]$7867 $2\cr_a_ok$next[0:0]$7870 - attribute \src "libresoc.v:145309.5-145309.29" + assign $0\cr_a_ok$next[0:0]$8189 $2\cr_a_ok$next[0:0]$8192 + attribute \src "libresoc.v:155197.5-155197.29" switch \initial - attribute \src "libresoc.v:145309.9-145309.17" + attribute \src "libresoc.v:155197.9-155197.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$7869 $1\cr_a$next[3:0]$7868 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8191 $1\cr_a$next[3:0]$8190 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$7869 $1\cr_a$next[3:0]$7868 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8191 $1\cr_a$next[3:0]$8190 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$next[3:0]$7868 \cr_a - assign $1\cr_a_ok$next[0:0]$7869 \cr_a_ok + assign $1\cr_a$next[3:0]$8190 \cr_a + assign $1\cr_a_ok$next[0:0]$8191 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$7870 1'0 + assign $2\cr_a_ok$next[0:0]$8192 1'0 case - assign $2\cr_a_ok$next[0:0]$7870 $1\cr_a_ok$next[0:0]$7869 + assign $2\cr_a_ok$next[0:0]$8192 $1\cr_a_ok$next[0:0]$8191 end sync always - update \cr_a$next $0\cr_a$next[3:0]$7866 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7867 + update \cr_a$next $0\cr_a$next[3:0]$8188 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8189 end - attribute \src "libresoc.v:145327.3-145345.6" - process $proc$libresoc.v:145327$7871 + attribute \src "libresoc.v:155215.3-155233.6" + process $proc$libresoc.v:155215$8193 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$7872 $1\xer_ov$next[1:0]$7874 + assign $0\xer_ov$next[1:0]$8194 $1\xer_ov$next[1:0]$8196 assign { } { } - assign $0\xer_ov_ok$next[0:0]$7873 $2\xer_ov_ok$next[0:0]$7876 - attribute \src "libresoc.v:145328.5-145328.29" + assign $0\xer_ov_ok$next[0:0]$8195 $2\xer_ov_ok$next[0:0]$8198 + attribute \src "libresoc.v:155216.5-155216.29" switch \initial - attribute \src "libresoc.v:145328.9-145328.17" + attribute \src "libresoc.v:155216.9-155216.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$7875 $1\xer_ov$next[1:0]$7874 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8197 $1\xer_ov$next[1:0]$8196 } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$7875 $1\xer_ov$next[1:0]$7874 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8197 $1\xer_ov$next[1:0]$8196 } { \xer_ov_ok$76 \xer_ov$75 } case - assign $1\xer_ov$next[1:0]$7874 \xer_ov - assign $1\xer_ov_ok$next[0:0]$7875 \xer_ov_ok + assign $1\xer_ov$next[1:0]$8196 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8197 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$7876 1'0 + assign $2\xer_ov_ok$next[0:0]$8198 1'0 case - assign $2\xer_ov_ok$next[0:0]$7876 $1\xer_ov_ok$next[0:0]$7875 + assign $2\xer_ov_ok$next[0:0]$8198 $1\xer_ov_ok$next[0:0]$8197 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$7872 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$7873 + update \xer_ov$next $0\xer_ov$next[1:0]$8194 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8195 end - attribute \src "libresoc.v:145346.3-145364.6" - process $proc$libresoc.v:145346$7877 + attribute \src "libresoc.v:155234.3-155252.6" + process $proc$libresoc.v:155234$8199 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$15$next[0:0]$7879 $1\xer_so$15$next[0:0]$7881 - assign $0\xer_so_ok$next[0:0]$7878 $2\xer_so_ok$next[0:0]$7882 - attribute \src "libresoc.v:145347.5-145347.29" + assign $0\xer_so$15$next[0:0]$8201 $1\xer_so$15$next[0:0]$8203 + assign $0\xer_so_ok$next[0:0]$8200 $2\xer_so_ok$next[0:0]$8204 + attribute \src "libresoc.v:155235.5-155235.29" switch \initial - attribute \src "libresoc.v:145347.9-145347.17" + attribute \src "libresoc.v:155235.9-155235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$7880 $1\xer_so$15$next[0:0]$7881 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8202 $1\xer_so$15$next[0:0]$8203 } { \xer_so_ok$78 \xer_so$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$7880 $1\xer_so$15$next[0:0]$7881 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8202 $1\xer_so$15$next[0:0]$8203 } { \xer_so_ok$78 \xer_so$77 } case - assign $1\xer_so_ok$next[0:0]$7880 \xer_so_ok - assign $1\xer_so$15$next[0:0]$7881 \xer_so$15 + assign $1\xer_so_ok$next[0:0]$8202 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8203 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$7882 1'0 + assign $2\xer_so_ok$next[0:0]$8204 1'0 case - assign $2\xer_so_ok$next[0:0]$7882 $1\xer_so_ok$next[0:0]$7880 + assign $2\xer_so_ok$next[0:0]$8204 $1\xer_so_ok$next[0:0]$8202 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$7878 - update \xer_so$15$next $0\xer_so$15$next[0:0]$7879 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8200 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8201 end - connect \$56 $and$libresoc.v:145091$7783_Y + connect \$56 $and$libresoc.v:154979$8105_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -304768,23 +323680,23 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:145394.1-145405.10" +attribute \src "libresoc.v:155282.1-155293.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:145403.17-145403.111" - wire $and$libresoc.v:145403$7921_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155291.17-155291.111" + wire $and$libresoc.v:155291$8243_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145403$7921 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155291$8243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304792,28 +323704,28 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145403$7921_Y + connect \Y $and$libresoc.v:155291$8243_Y end - connect \$1 $and$libresoc.v:145403$7921_Y + connect \$1 $and$libresoc.v:155291$8243_Y connect \trigger \$1 end -attribute \src "libresoc.v:145409.1-145420.10" +attribute \src "libresoc.v:155297.1-155308.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 - attribute \src "libresoc.v:145418.17-145418.111" - wire $and$libresoc.v:145418$7922_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155306.17-155306.111" + wire $and$libresoc.v:155306$8244_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145418$7922 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155306$8244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304821,28 +323733,28 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145418$7922_Y + connect \Y $and$libresoc.v:155306$8244_Y end - connect \$1 $and$libresoc.v:145418$7922_Y + connect \$1 $and$libresoc.v:155306$8244_Y connect \trigger \$1 end -attribute \src "libresoc.v:145424.1-145435.10" +attribute \src "libresoc.v:155312.1-155323.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 - attribute \src "libresoc.v:145433.17-145433.111" - wire $and$libresoc.v:145433$7923_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155321.17-155321.111" + wire $and$libresoc.v:155321$8245_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145433$7923 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155321$8245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304850,28 +323762,28 @@ module \n$112 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145433$7923_Y + connect \Y $and$libresoc.v:155321$8245_Y end - connect \$1 $and$libresoc.v:145433$7923_Y + connect \$1 $and$libresoc.v:155321$8245_Y connect \trigger \$1 end -attribute \src "libresoc.v:145439.1-145450.10" +attribute \src "libresoc.v:155327.1-155338.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 - attribute \src "libresoc.v:145448.17-145448.111" - wire $and$libresoc.v:145448$7924_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155336.17-155336.111" + wire $and$libresoc.v:155336$8246_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145448$7924 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155336$8246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304879,28 +323791,28 @@ module \n$117 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145448$7924_Y + connect \Y $and$libresoc.v:155336$8246_Y end - connect \$1 $and$libresoc.v:145448$7924_Y + connect \$1 $and$libresoc.v:155336$8246_Y connect \trigger \$1 end -attribute \src "libresoc.v:145454.1-145465.10" +attribute \src "libresoc.v:155342.1-155353.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:145463.17-145463.111" - wire $and$libresoc.v:145463$7925_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155351.17-155351.111" + wire $and$libresoc.v:155351$8247_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145463$7925 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155351$8247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304908,28 +323820,28 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145463$7925_Y + connect \Y $and$libresoc.v:155351$8247_Y end - connect \$1 $and$libresoc.v:145463$7925_Y + connect \$1 $and$libresoc.v:155351$8247_Y connect \trigger \$1 end -attribute \src "libresoc.v:145469.1-145480.10" +attribute \src "libresoc.v:155357.1-155368.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:145478.17-145478.111" - wire $and$libresoc.v:145478$7926_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155366.17-155366.111" + wire $and$libresoc.v:155366$8248_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145478$7926 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155366$8248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304937,28 +323849,28 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145478$7926_Y + connect \Y $and$libresoc.v:155366$8248_Y end - connect \$1 $and$libresoc.v:145478$7926_Y + connect \$1 $and$libresoc.v:155366$8248_Y connect \trigger \$1 end -attribute \src "libresoc.v:145484.1-145495.10" +attribute \src "libresoc.v:155372.1-155383.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:145493.17-145493.111" - wire $and$libresoc.v:145493$7927_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155381.17-155381.111" + wire $and$libresoc.v:155381$8249_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145493$7927 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155381$8249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304966,28 +323878,28 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145493$7927_Y + connect \Y $and$libresoc.v:155381$8249_Y end - connect \$1 $and$libresoc.v:145493$7927_Y + connect \$1 $and$libresoc.v:155381$8249_Y connect \trigger \$1 end -attribute \src "libresoc.v:145499.1-145510.10" +attribute \src "libresoc.v:155387.1-155398.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:145508.17-145508.111" - wire $and$libresoc.v:145508$7928_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155396.17-155396.111" + wire $and$libresoc.v:155396$8250_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145508$7928 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155396$8250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304995,28 +323907,28 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145508$7928_Y + connect \Y $and$libresoc.v:155396$8250_Y end - connect \$1 $and$libresoc.v:145508$7928_Y + connect \$1 $and$libresoc.v:155396$8250_Y connect \trigger \$1 end -attribute \src "libresoc.v:145514.1-145525.10" +attribute \src "libresoc.v:155402.1-155413.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:145523.17-145523.111" - wire $and$libresoc.v:145523$7929_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155411.17-155411.111" + wire $and$libresoc.v:155411$8251_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145523$7929 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155411$8251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305024,28 +323936,28 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145523$7929_Y + connect \Y $and$libresoc.v:155411$8251_Y end - connect \$1 $and$libresoc.v:145523$7929_Y + connect \$1 $and$libresoc.v:155411$8251_Y connect \trigger \$1 end -attribute \src "libresoc.v:145529.1-145540.10" +attribute \src "libresoc.v:155417.1-155428.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 - attribute \src "libresoc.v:145538.17-145538.111" - wire $and$libresoc.v:145538$7930_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155426.17-155426.111" + wire $and$libresoc.v:155426$8252_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145538$7930 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155426$8252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305053,28 +323965,28 @@ module \n$37 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145538$7930_Y + connect \Y $and$libresoc.v:155426$8252_Y end - connect \$1 $and$libresoc.v:145538$7930_Y + connect \$1 $and$libresoc.v:155426$8252_Y connect \trigger \$1 end -attribute \src "libresoc.v:145544.1-145555.10" +attribute \src "libresoc.v:155432.1-155443.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 - attribute \src "libresoc.v:145553.17-145553.111" - wire $and$libresoc.v:145553$7931_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155441.17-155441.111" + wire $and$libresoc.v:155441$8253_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145553$7931 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155441$8253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305082,28 +323994,28 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145553$7931_Y + connect \Y $and$libresoc.v:155441$8253_Y end - connect \$1 $and$libresoc.v:145553$7931_Y + connect \$1 $and$libresoc.v:155441$8253_Y connect \trigger \$1 end -attribute \src "libresoc.v:145559.1-145570.10" +attribute \src "libresoc.v:155447.1-155458.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 - attribute \src "libresoc.v:145568.17-145568.111" - wire $and$libresoc.v:145568$7932_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155456.17-155456.111" + wire $and$libresoc.v:155456$8254_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145568$7932 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155456$8254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305111,28 +324023,28 @@ module \n$47 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145568$7932_Y + connect \Y $and$libresoc.v:155456$8254_Y end - connect \$1 $and$libresoc.v:145568$7932_Y + connect \$1 $and$libresoc.v:155456$8254_Y connect \trigger \$1 end -attribute \src "libresoc.v:145574.1-145585.10" +attribute \src "libresoc.v:155462.1-155473.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 - attribute \src "libresoc.v:145583.17-145583.111" - wire $and$libresoc.v:145583$7933_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155471.17-155471.111" + wire $and$libresoc.v:155471$8255_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145583$7933 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155471$8255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305140,28 +324052,28 @@ module \n$49 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145583$7933_Y + connect \Y $and$libresoc.v:155471$8255_Y end - connect \$1 $and$libresoc.v:145583$7933_Y + connect \$1 $and$libresoc.v:155471$8255_Y connect \trigger \$1 end -attribute \src "libresoc.v:145589.1-145600.10" +attribute \src "libresoc.v:155477.1-155488.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 - attribute \src "libresoc.v:145598.17-145598.111" - wire $and$libresoc.v:145598$7934_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155486.17-155486.111" + wire $and$libresoc.v:155486$8256_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145598$7934 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155486$8256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305169,28 +324081,28 @@ module \n$53 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145598$7934_Y + connect \Y $and$libresoc.v:155486$8256_Y end - connect \$1 $and$libresoc.v:145598$7934_Y + connect \$1 $and$libresoc.v:155486$8256_Y connect \trigger \$1 end -attribute \src "libresoc.v:145604.1-145615.10" +attribute \src "libresoc.v:155492.1-155503.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 - attribute \src "libresoc.v:145613.17-145613.111" - wire $and$libresoc.v:145613$7935_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155501.17-155501.111" + wire $and$libresoc.v:155501$8257_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145613$7935 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155501$8257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305198,28 +324110,28 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145613$7935_Y + connect \Y $and$libresoc.v:155501$8257_Y end - connect \$1 $and$libresoc.v:145613$7935_Y + connect \$1 $and$libresoc.v:155501$8257_Y connect \trigger \$1 end -attribute \src "libresoc.v:145619.1-145630.10" +attribute \src "libresoc.v:155507.1-155518.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:145628.17-145628.111" - wire $and$libresoc.v:145628$7936_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155516.17-155516.111" + wire $and$libresoc.v:155516$8258_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145628$7936 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155516$8258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305227,28 +324139,28 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145628$7936_Y + connect \Y $and$libresoc.v:155516$8258_Y end - connect \$1 $and$libresoc.v:145628$7936_Y + connect \$1 $and$libresoc.v:155516$8258_Y connect \trigger \$1 end -attribute \src "libresoc.v:145634.1-145645.10" +attribute \src "libresoc.v:155522.1-155533.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 - attribute \src "libresoc.v:145643.17-145643.111" - wire $and$libresoc.v:145643$7937_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155531.17-155531.111" + wire $and$libresoc.v:155531$8259_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145643$7937 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155531$8259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305256,28 +324168,28 @@ module \n$66 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145643$7937_Y + connect \Y $and$libresoc.v:155531$8259_Y end - connect \$1 $and$libresoc.v:145643$7937_Y + connect \$1 $and$libresoc.v:155531$8259_Y connect \trigger \$1 end -attribute \src "libresoc.v:145649.1-145660.10" +attribute \src "libresoc.v:155537.1-155548.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 - attribute \src "libresoc.v:145658.17-145658.111" - wire $and$libresoc.v:145658$7938_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155546.17-155546.111" + wire $and$libresoc.v:155546$8260_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145658$7938 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155546$8260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305285,28 +324197,28 @@ module \n$75 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145658$7938_Y + connect \Y $and$libresoc.v:155546$8260_Y end - connect \$1 $and$libresoc.v:145658$7938_Y + connect \$1 $and$libresoc.v:155546$8260_Y connect \trigger \$1 end -attribute \src "libresoc.v:145664.1-145675.10" +attribute \src "libresoc.v:155552.1-155563.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:145673.17-145673.111" - wire $and$libresoc.v:145673$7939_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155561.17-155561.111" + wire $and$libresoc.v:155561$8261_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145673$7939 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155561$8261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305314,28 +324226,28 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145673$7939_Y + connect \Y $and$libresoc.v:155561$8261_Y end - connect \$1 $and$libresoc.v:145673$7939_Y + connect \$1 $and$libresoc.v:155561$8261_Y connect \trigger \$1 end -attribute \src "libresoc.v:145679.1-145690.10" +attribute \src "libresoc.v:155567.1-155578.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 - attribute \src "libresoc.v:145688.17-145688.111" - wire $and$libresoc.v:145688$7940_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155576.17-155576.111" + wire $and$libresoc.v:155576$8262_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145688$7940 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155576$8262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305343,28 +324255,28 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145688$7940_Y + connect \Y $and$libresoc.v:155576$8262_Y end - connect \$1 $and$libresoc.v:145688$7940_Y + connect \$1 $and$libresoc.v:155576$8262_Y connect \trigger \$1 end -attribute \src "libresoc.v:145694.1-145705.10" +attribute \src "libresoc.v:155582.1-155593.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 - attribute \src "libresoc.v:145703.17-145703.111" - wire $and$libresoc.v:145703$7941_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155591.17-155591.111" + wire $and$libresoc.v:155591$8263_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145703$7941 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155591$8263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305372,28 +324284,28 @@ module \n$80 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145703$7941_Y + connect \Y $and$libresoc.v:155591$8263_Y end - connect \$1 $and$libresoc.v:145703$7941_Y + connect \$1 $and$libresoc.v:155591$8263_Y connect \trigger \$1 end -attribute \src "libresoc.v:145709.1-145720.10" +attribute \src "libresoc.v:155597.1-155608.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 - attribute \src "libresoc.v:145718.17-145718.111" - wire $and$libresoc.v:145718$7942_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155606.17-155606.111" + wire $and$libresoc.v:155606$8264_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145718$7942 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155606$8264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305401,28 +324313,28 @@ module \n$82 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145718$7942_Y + connect \Y $and$libresoc.v:155606$8264_Y end - connect \$1 $and$libresoc.v:145718$7942_Y + connect \$1 $and$libresoc.v:155606$8264_Y connect \trigger \$1 end -attribute \src "libresoc.v:145724.1-145735.10" +attribute \src "libresoc.v:155612.1-155623.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 - attribute \src "libresoc.v:145733.17-145733.111" - wire $and$libresoc.v:145733$7943_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155621.17-155621.111" + wire $and$libresoc.v:155621$8265_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145733$7943 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155621$8265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305430,28 +324342,28 @@ module \n$92 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145733$7943_Y + connect \Y $and$libresoc.v:155621$8265_Y end - connect \$1 $and$libresoc.v:145733$7943_Y + connect \$1 $and$libresoc.v:155621$8265_Y connect \trigger \$1 end -attribute \src "libresoc.v:145739.1-145750.10" +attribute \src "libresoc.v:155627.1-155638.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:145748.17-145748.111" - wire $and$libresoc.v:145748$7944_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155636.17-155636.111" + wire $and$libresoc.v:155636$8266_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145748$7944 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155636$8266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305459,28 +324371,28 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145748$7944_Y + connect \Y $and$libresoc.v:155636$8266_Y end - connect \$1 $and$libresoc.v:145748$7944_Y + connect \$1 $and$libresoc.v:155636$8266_Y connect \trigger \$1 end -attribute \src "libresoc.v:145754.1-145765.10" +attribute \src "libresoc.v:155642.1-155653.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 - attribute \src "libresoc.v:145763.17-145763.111" - wire $and$libresoc.v:145763$7945_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155651.17-155651.111" + wire $and$libresoc.v:155651$8267_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145763$7945 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155651$8267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305488,28 +324400,28 @@ module \n$97 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145763$7945_Y + connect \Y $and$libresoc.v:155651$8267_Y end - connect \$1 $and$libresoc.v:145763$7945_Y + connect \$1 $and$libresoc.v:155651$8267_Y connect \trigger \$1 end -attribute \src "libresoc.v:145769.1-145780.10" +attribute \src "libresoc.v:155657.1-155668.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 - attribute \src "libresoc.v:145778.17-145778.111" - wire $and$libresoc.v:145778$7946_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + attribute \src "libresoc.v:155666.17-155666.111" + wire $and$libresoc.v:155666$8268_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145778$7946 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155666$8268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305517,80 +324429,80 @@ module \n$99 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:145778$7946_Y + connect \Y $and$libresoc.v:155666$8268_Y end - connect \$1 $and$libresoc.v:145778$7946_Y + connect \$1 $and$libresoc.v:155666$8268_Y connect \trigger \$1 end -attribute \src "libresoc.v:145784.1-145842.10" +attribute \src "libresoc.v:155672.1-155730.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l - attribute \src "libresoc.v:145785.7-145785.20" + attribute \src "libresoc.v:155673.7-155673.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145830.3-145838.6" - wire $0\q_int$next[0:0]$7957 - attribute \src "libresoc.v:145828.3-145829.27" + attribute \src "libresoc.v:155718.3-155726.6" + wire $0\q_int$next[0:0]$8279 + attribute \src "libresoc.v:155716.3-155717.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:145830.3-145838.6" - wire $1\q_int$next[0:0]$7958 - attribute \src "libresoc.v:145807.7-145807.19" + attribute \src "libresoc.v:155718.3-155726.6" + wire $1\q_int$next[0:0]$8280 + attribute \src "libresoc.v:155695.7-155695.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:145820.17-145820.96" - wire $and$libresoc.v:145820$7947_Y - attribute \src "libresoc.v:145825.17-145825.96" - wire $and$libresoc.v:145825$7952_Y - attribute \src "libresoc.v:145822.18-145822.93" - wire $not$libresoc.v:145822$7949_Y - attribute \src "libresoc.v:145824.17-145824.92" - wire $not$libresoc.v:145824$7951_Y - attribute \src "libresoc.v:145827.17-145827.92" - wire $not$libresoc.v:145827$7954_Y - attribute \src "libresoc.v:145821.18-145821.98" - wire $or$libresoc.v:145821$7948_Y - attribute \src "libresoc.v:145823.18-145823.99" - wire $or$libresoc.v:145823$7950_Y - attribute \src "libresoc.v:145826.17-145826.97" - wire $or$libresoc.v:145826$7953_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:155708.17-155708.96" + wire $and$libresoc.v:155708$8269_Y + attribute \src "libresoc.v:155713.17-155713.96" + wire $and$libresoc.v:155713$8274_Y + attribute \src "libresoc.v:155710.18-155710.93" + wire $not$libresoc.v:155710$8271_Y + attribute \src "libresoc.v:155712.17-155712.92" + wire $not$libresoc.v:155712$8273_Y + attribute \src "libresoc.v:155715.17-155715.92" + wire $not$libresoc.v:155715$8276_Y + attribute \src "libresoc.v:155709.18-155709.98" + wire $or$libresoc.v:155709$8270_Y + attribute \src "libresoc.v:155711.18-155711.99" + wire $or$libresoc.v:155711$8272_Y + attribute \src "libresoc.v:155714.17-155714.97" + wire $or$libresoc.v:155714$8275_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:145785.7-145785.15" + attribute \src "libresoc.v:155673.7-155673.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:145820$7947 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:155708$8269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305598,10 +324510,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:145820$7947_Y + connect \Y $and$libresoc.v:155708$8269_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:145825$7952 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:155713$8274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305609,34 +324521,34 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:145825$7952_Y + connect \Y $and$libresoc.v:155713$8274_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:145822$7949 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:155710$8271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:145822$7949_Y + connect \Y $not$libresoc.v:155710$8271_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:145824$7951 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:155712$8273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:145824$7951_Y + connect \Y $not$libresoc.v:155712$8273_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:145827$7954 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:155715$8276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:145827$7954_Y + connect \Y $not$libresoc.v:155715$8276_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:145821$7948 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:155709$8270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305644,10 +324556,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:145821$7948_Y + connect \Y $or$libresoc.v:155709$8270_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:145823$7950 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:155711$8272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305655,10 +324567,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:145823$7950_Y + connect \Y $or$libresoc.v:155711$8272_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:145826$7953 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:155714$8275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305666,39 +324578,39 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:145826$7953_Y + connect \Y $or$libresoc.v:155714$8275_Y end - attribute \src "libresoc.v:145785.7-145785.20" - process $proc$libresoc.v:145785$7959 + attribute \src "libresoc.v:155673.7-155673.20" + process $proc$libresoc.v:155673$8281 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145807.7-145807.19" - process $proc$libresoc.v:145807$7960 + attribute \src "libresoc.v:155695.7-155695.19" + process $proc$libresoc.v:155695$8282 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:145828.3-145829.27" - process $proc$libresoc.v:145828$7955 + attribute \src "libresoc.v:155716.3-155717.27" + process $proc$libresoc.v:155716$8277 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:145830.3-145838.6" - process $proc$libresoc.v:145830$7956 + attribute \src "libresoc.v:155718.3-155726.6" + process $proc$libresoc.v:155718$8278 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7957 $1\q_int$next[0:0]$7958 - attribute \src "libresoc.v:145831.5-145831.29" + assign $0\q_int$next[0:0]$8279 $1\q_int$next[0:0]$8280 + attribute \src "libresoc.v:155719.5-155719.29" switch \initial - attribute \src "libresoc.v:145831.9-145831.17" + attribute \src "libresoc.v:155719.9-155719.17" case 1'1 case end @@ -305707,94 +324619,94 @@ module \opc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7958 1'0 + assign $1\q_int$next[0:0]$8280 1'0 case - assign $1\q_int$next[0:0]$7958 \$5 + assign $1\q_int$next[0:0]$8280 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7957 + update \q_int$next $0\q_int$next[0:0]$8279 end - connect \$9 $and$libresoc.v:145820$7947_Y - connect \$11 $or$libresoc.v:145821$7948_Y - connect \$13 $not$libresoc.v:145822$7949_Y - connect \$15 $or$libresoc.v:145823$7950_Y - connect \$1 $not$libresoc.v:145824$7951_Y - connect \$3 $and$libresoc.v:145825$7952_Y - connect \$5 $or$libresoc.v:145826$7953_Y - connect \$7 $not$libresoc.v:145827$7954_Y + connect \$9 $and$libresoc.v:155708$8269_Y + connect \$11 $or$libresoc.v:155709$8270_Y + connect \$13 $not$libresoc.v:155710$8271_Y + connect \$15 $or$libresoc.v:155711$8272_Y + connect \$1 $not$libresoc.v:155712$8273_Y + connect \$3 $and$libresoc.v:155713$8274_Y + connect \$5 $or$libresoc.v:155714$8275_Y + connect \$7 $not$libresoc.v:155715$8276_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:145846.1-145904.10" +attribute \src "libresoc.v:155734.1-155792.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 - attribute \src "libresoc.v:145847.7-145847.20" + attribute \src "libresoc.v:155735.7-155735.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145892.3-145900.6" - wire $0\q_int$next[0:0]$7971 - attribute \src "libresoc.v:145890.3-145891.27" + attribute \src "libresoc.v:155780.3-155788.6" + wire $0\q_int$next[0:0]$8293 + attribute \src "libresoc.v:155778.3-155779.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:145892.3-145900.6" - wire $1\q_int$next[0:0]$7972 - attribute \src "libresoc.v:145869.7-145869.19" + attribute \src "libresoc.v:155780.3-155788.6" + wire $1\q_int$next[0:0]$8294 + attribute \src "libresoc.v:155757.7-155757.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:145882.17-145882.96" - wire $and$libresoc.v:145882$7961_Y - attribute \src "libresoc.v:145887.17-145887.96" - wire $and$libresoc.v:145887$7966_Y - attribute \src "libresoc.v:145884.18-145884.93" - wire $not$libresoc.v:145884$7963_Y - attribute \src "libresoc.v:145886.17-145886.92" - wire $not$libresoc.v:145886$7965_Y - attribute \src "libresoc.v:145889.17-145889.92" - wire $not$libresoc.v:145889$7968_Y - attribute \src "libresoc.v:145883.18-145883.98" - wire $or$libresoc.v:145883$7962_Y - attribute \src "libresoc.v:145885.18-145885.99" - wire $or$libresoc.v:145885$7964_Y - attribute \src "libresoc.v:145888.17-145888.97" - wire $or$libresoc.v:145888$7967_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:155770.17-155770.96" + wire $and$libresoc.v:155770$8283_Y + attribute \src "libresoc.v:155775.17-155775.96" + wire $and$libresoc.v:155775$8288_Y + attribute \src "libresoc.v:155772.18-155772.93" + wire $not$libresoc.v:155772$8285_Y + attribute \src "libresoc.v:155774.17-155774.92" + wire $not$libresoc.v:155774$8287_Y + attribute \src "libresoc.v:155777.17-155777.92" + wire $not$libresoc.v:155777$8290_Y + attribute \src "libresoc.v:155771.18-155771.98" + wire $or$libresoc.v:155771$8284_Y + attribute \src "libresoc.v:155773.18-155773.99" + wire $or$libresoc.v:155773$8286_Y + attribute \src "libresoc.v:155776.17-155776.97" + wire $or$libresoc.v:155776$8289_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:145847.7-145847.15" + attribute \src "libresoc.v:155735.7-155735.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:145882$7961 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:155770$8283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305802,10 +324714,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:145882$7961_Y + connect \Y $and$libresoc.v:155770$8283_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:145887$7966 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:155775$8288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305813,34 +324725,34 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:145887$7966_Y + connect \Y $and$libresoc.v:155775$8288_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:145884$7963 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:155772$8285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:145884$7963_Y + connect \Y $not$libresoc.v:155772$8285_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:145886$7965 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:155774$8287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:145886$7965_Y + connect \Y $not$libresoc.v:155774$8287_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:145889$7968 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:155777$8290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:145889$7968_Y + connect \Y $not$libresoc.v:155777$8290_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:145883$7962 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:155771$8284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305848,10 +324760,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:145883$7962_Y + connect \Y $or$libresoc.v:155771$8284_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:145885$7964 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:155773$8286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305859,10 +324771,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:145885$7964_Y + connect \Y $or$libresoc.v:155773$8286_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:145888$7967 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:155776$8289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305870,39 +324782,39 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:145888$7967_Y + connect \Y $or$libresoc.v:155776$8289_Y end - attribute \src "libresoc.v:145847.7-145847.20" - process $proc$libresoc.v:145847$7973 + attribute \src "libresoc.v:155735.7-155735.20" + process $proc$libresoc.v:155735$8295 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145869.7-145869.19" - process $proc$libresoc.v:145869$7974 + attribute \src "libresoc.v:155757.7-155757.19" + process $proc$libresoc.v:155757$8296 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:145890.3-145891.27" - process $proc$libresoc.v:145890$7969 + attribute \src "libresoc.v:155778.3-155779.27" + process $proc$libresoc.v:155778$8291 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:145892.3-145900.6" - process $proc$libresoc.v:145892$7970 + attribute \src "libresoc.v:155780.3-155788.6" + process $proc$libresoc.v:155780$8292 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7971 $1\q_int$next[0:0]$7972 - attribute \src "libresoc.v:145893.5-145893.29" + assign $0\q_int$next[0:0]$8293 $1\q_int$next[0:0]$8294 + attribute \src "libresoc.v:155781.5-155781.29" switch \initial - attribute \src "libresoc.v:145893.9-145893.17" + attribute \src "libresoc.v:155781.9-155781.17" case 1'1 case end @@ -305911,94 +324823,94 @@ module \opc_l$102 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7972 1'0 + assign $1\q_int$next[0:0]$8294 1'0 case - assign $1\q_int$next[0:0]$7972 \$5 + assign $1\q_int$next[0:0]$8294 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7971 + update \q_int$next $0\q_int$next[0:0]$8293 end - connect \$9 $and$libresoc.v:145882$7961_Y - connect \$11 $or$libresoc.v:145883$7962_Y - connect \$13 $not$libresoc.v:145884$7963_Y - connect \$15 $or$libresoc.v:145885$7964_Y - connect \$1 $not$libresoc.v:145886$7965_Y - connect \$3 $and$libresoc.v:145887$7966_Y - connect \$5 $or$libresoc.v:145888$7967_Y - connect \$7 $not$libresoc.v:145889$7968_Y + connect \$9 $and$libresoc.v:155770$8283_Y + connect \$11 $or$libresoc.v:155771$8284_Y + connect \$13 $not$libresoc.v:155772$8285_Y + connect \$15 $or$libresoc.v:155773$8286_Y + connect \$1 $not$libresoc.v:155774$8287_Y + connect \$3 $and$libresoc.v:155775$8288_Y + connect \$5 $or$libresoc.v:155776$8289_Y + connect \$7 $not$libresoc.v:155777$8290_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:145908.1-145966.10" +attribute \src "libresoc.v:155796.1-155854.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 - attribute \src "libresoc.v:145909.7-145909.20" + attribute \src "libresoc.v:155797.7-155797.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145954.3-145962.6" - wire $0\q_int$next[0:0]$7985 - attribute \src "libresoc.v:145952.3-145953.27" + attribute \src "libresoc.v:155842.3-155850.6" + wire $0\q_int$next[0:0]$8307 + attribute \src "libresoc.v:155840.3-155841.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:145954.3-145962.6" - wire $1\q_int$next[0:0]$7986 - attribute \src "libresoc.v:145931.7-145931.19" + attribute \src "libresoc.v:155842.3-155850.6" + wire $1\q_int$next[0:0]$8308 + attribute \src "libresoc.v:155819.7-155819.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:145944.17-145944.96" - wire $and$libresoc.v:145944$7975_Y - attribute \src "libresoc.v:145949.17-145949.96" - wire $and$libresoc.v:145949$7980_Y - attribute \src "libresoc.v:145946.18-145946.93" - wire $not$libresoc.v:145946$7977_Y - attribute \src "libresoc.v:145948.17-145948.92" - wire $not$libresoc.v:145948$7979_Y - attribute \src "libresoc.v:145951.17-145951.92" - wire $not$libresoc.v:145951$7982_Y - attribute \src "libresoc.v:145945.18-145945.98" - wire $or$libresoc.v:145945$7976_Y - attribute \src "libresoc.v:145947.18-145947.99" - wire $or$libresoc.v:145947$7978_Y - attribute \src "libresoc.v:145950.17-145950.97" - wire $or$libresoc.v:145950$7981_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:155832.17-155832.96" + wire $and$libresoc.v:155832$8297_Y + attribute \src "libresoc.v:155837.17-155837.96" + wire $and$libresoc.v:155837$8302_Y + attribute \src "libresoc.v:155834.18-155834.93" + wire $not$libresoc.v:155834$8299_Y + attribute \src "libresoc.v:155836.17-155836.92" + wire $not$libresoc.v:155836$8301_Y + attribute \src "libresoc.v:155839.17-155839.92" + wire $not$libresoc.v:155839$8304_Y + attribute \src "libresoc.v:155833.18-155833.98" + wire $or$libresoc.v:155833$8298_Y + attribute \src "libresoc.v:155835.18-155835.99" + wire $or$libresoc.v:155835$8300_Y + attribute \src "libresoc.v:155838.17-155838.97" + wire $or$libresoc.v:155838$8303_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:145909.7-145909.15" + attribute \src "libresoc.v:155797.7-155797.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:145944$7975 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:155832$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306006,10 +324918,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:145944$7975_Y + connect \Y $and$libresoc.v:155832$8297_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:145949$7980 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:155837$8302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306017,34 +324929,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:145949$7980_Y + connect \Y $and$libresoc.v:155837$8302_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:145946$7977 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:155834$8299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:145946$7977_Y + connect \Y $not$libresoc.v:155834$8299_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:145948$7979 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:155836$8301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:145948$7979_Y + connect \Y $not$libresoc.v:155836$8301_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:145951$7982 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:155839$8304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:145951$7982_Y + connect \Y $not$libresoc.v:155839$8304_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:145945$7976 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:155833$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306052,10 +324964,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:145945$7976_Y + connect \Y $or$libresoc.v:155833$8298_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:145947$7978 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:155835$8300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306063,10 +324975,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:145947$7978_Y + connect \Y $or$libresoc.v:155835$8300_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:145950$7981 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:155838$8303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306074,39 +324986,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:145950$7981_Y + connect \Y $or$libresoc.v:155838$8303_Y end - attribute \src "libresoc.v:145909.7-145909.20" - process $proc$libresoc.v:145909$7987 + attribute \src "libresoc.v:155797.7-155797.20" + process $proc$libresoc.v:155797$8309 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145931.7-145931.19" - process $proc$libresoc.v:145931$7988 + attribute \src "libresoc.v:155819.7-155819.19" + process $proc$libresoc.v:155819$8310 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:145952.3-145953.27" - process $proc$libresoc.v:145952$7983 + attribute \src "libresoc.v:155840.3-155841.27" + process $proc$libresoc.v:155840$8305 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:145954.3-145962.6" - process $proc$libresoc.v:145954$7984 + attribute \src "libresoc.v:155842.3-155850.6" + process $proc$libresoc.v:155842$8306 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7985 $1\q_int$next[0:0]$7986 - attribute \src "libresoc.v:145955.5-145955.29" + assign $0\q_int$next[0:0]$8307 $1\q_int$next[0:0]$8308 + attribute \src "libresoc.v:155843.5-155843.29" switch \initial - attribute \src "libresoc.v:145955.9-145955.17" + attribute \src "libresoc.v:155843.9-155843.17" case 1'1 case end @@ -306115,94 +325027,94 @@ module \opc_l$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7986 1'0 + assign $1\q_int$next[0:0]$8308 1'0 case - assign $1\q_int$next[0:0]$7986 \$5 + assign $1\q_int$next[0:0]$8308 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7985 + update \q_int$next $0\q_int$next[0:0]$8307 end - connect \$9 $and$libresoc.v:145944$7975_Y - connect \$11 $or$libresoc.v:145945$7976_Y - connect \$13 $not$libresoc.v:145946$7977_Y - connect \$15 $or$libresoc.v:145947$7978_Y - connect \$1 $not$libresoc.v:145948$7979_Y - connect \$3 $and$libresoc.v:145949$7980_Y - connect \$5 $or$libresoc.v:145950$7981_Y - connect \$7 $not$libresoc.v:145951$7982_Y + connect \$9 $and$libresoc.v:155832$8297_Y + connect \$11 $or$libresoc.v:155833$8298_Y + connect \$13 $not$libresoc.v:155834$8299_Y + connect \$15 $or$libresoc.v:155835$8300_Y + connect \$1 $not$libresoc.v:155836$8301_Y + connect \$3 $and$libresoc.v:155837$8302_Y + connect \$5 $or$libresoc.v:155838$8303_Y + connect \$7 $not$libresoc.v:155839$8304_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:145970.1-146028.10" +attribute \src "libresoc.v:155858.1-155916.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 - attribute \src "libresoc.v:145971.7-145971.20" + attribute \src "libresoc.v:155859.7-155859.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146016.3-146024.6" - wire $0\q_int$next[0:0]$7999 - attribute \src "libresoc.v:146014.3-146015.27" + attribute \src "libresoc.v:155904.3-155912.6" + wire $0\q_int$next[0:0]$8321 + attribute \src "libresoc.v:155902.3-155903.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146016.3-146024.6" - wire $1\q_int$next[0:0]$8000 - attribute \src "libresoc.v:145993.7-145993.19" + attribute \src "libresoc.v:155904.3-155912.6" + wire $1\q_int$next[0:0]$8322 + attribute \src "libresoc.v:155881.7-155881.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146006.17-146006.96" - wire $and$libresoc.v:146006$7989_Y - attribute \src "libresoc.v:146011.17-146011.96" - wire $and$libresoc.v:146011$7994_Y - attribute \src "libresoc.v:146008.18-146008.93" - wire $not$libresoc.v:146008$7991_Y - attribute \src "libresoc.v:146010.17-146010.92" - wire $not$libresoc.v:146010$7993_Y - attribute \src "libresoc.v:146013.17-146013.92" - wire $not$libresoc.v:146013$7996_Y - attribute \src "libresoc.v:146007.18-146007.98" - wire $or$libresoc.v:146007$7990_Y - attribute \src "libresoc.v:146009.18-146009.99" - wire $or$libresoc.v:146009$7992_Y - attribute \src "libresoc.v:146012.17-146012.97" - wire $or$libresoc.v:146012$7995_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:155894.17-155894.96" + wire $and$libresoc.v:155894$8311_Y + attribute \src "libresoc.v:155899.17-155899.96" + wire $and$libresoc.v:155899$8316_Y + attribute \src "libresoc.v:155896.18-155896.93" + wire $not$libresoc.v:155896$8313_Y + attribute \src "libresoc.v:155898.17-155898.92" + wire $not$libresoc.v:155898$8315_Y + attribute \src "libresoc.v:155901.17-155901.92" + wire $not$libresoc.v:155901$8318_Y + attribute \src "libresoc.v:155895.18-155895.98" + wire $or$libresoc.v:155895$8312_Y + attribute \src "libresoc.v:155897.18-155897.99" + wire $or$libresoc.v:155897$8314_Y + attribute \src "libresoc.v:155900.17-155900.97" + wire $or$libresoc.v:155900$8317_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:145971.7-145971.15" + attribute \src "libresoc.v:155859.7-155859.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146006$7989 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:155894$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306210,10 +325122,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146006$7989_Y + connect \Y $and$libresoc.v:155894$8311_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146011$7994 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:155899$8316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306221,34 +325133,34 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146011$7994_Y + connect \Y $and$libresoc.v:155899$8316_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146008$7991 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:155896$8313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:146008$7991_Y + connect \Y $not$libresoc.v:155896$8313_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146010$7993 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:155898$8315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146010$7993_Y + connect \Y $not$libresoc.v:155898$8315_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146013$7996 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:155901$8318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146013$7996_Y + connect \Y $not$libresoc.v:155901$8318_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146007$7990 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:155895$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306256,10 +325168,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:146007$7990_Y + connect \Y $or$libresoc.v:155895$8312_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146009$7992 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:155897$8314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306267,10 +325179,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:146009$7992_Y + connect \Y $or$libresoc.v:155897$8314_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146012$7995 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:155900$8317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306278,39 +325190,39 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:146012$7995_Y + connect \Y $or$libresoc.v:155900$8317_Y end - attribute \src "libresoc.v:145971.7-145971.20" - process $proc$libresoc.v:145971$8001 + attribute \src "libresoc.v:155859.7-155859.20" + process $proc$libresoc.v:155859$8323 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145993.7-145993.19" - process $proc$libresoc.v:145993$8002 + attribute \src "libresoc.v:155881.7-155881.19" + process $proc$libresoc.v:155881$8324 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146014.3-146015.27" - process $proc$libresoc.v:146014$7997 + attribute \src "libresoc.v:155902.3-155903.27" + process $proc$libresoc.v:155902$8319 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146016.3-146024.6" - process $proc$libresoc.v:146016$7998 + attribute \src "libresoc.v:155904.3-155912.6" + process $proc$libresoc.v:155904$8320 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7999 $1\q_int$next[0:0]$8000 - attribute \src "libresoc.v:146017.5-146017.29" + assign $0\q_int$next[0:0]$8321 $1\q_int$next[0:0]$8322 + attribute \src "libresoc.v:155905.5-155905.29" switch \initial - attribute \src "libresoc.v:146017.9-146017.17" + attribute \src "libresoc.v:155905.9-155905.17" case 1'1 case end @@ -306319,94 +325231,94 @@ module \opc_l$120 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8000 1'0 + assign $1\q_int$next[0:0]$8322 1'0 case - assign $1\q_int$next[0:0]$8000 \$5 + assign $1\q_int$next[0:0]$8322 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7999 + update \q_int$next $0\q_int$next[0:0]$8321 end - connect \$9 $and$libresoc.v:146006$7989_Y - connect \$11 $or$libresoc.v:146007$7990_Y - connect \$13 $not$libresoc.v:146008$7991_Y - connect \$15 $or$libresoc.v:146009$7992_Y - connect \$1 $not$libresoc.v:146010$7993_Y - connect \$3 $and$libresoc.v:146011$7994_Y - connect \$5 $or$libresoc.v:146012$7995_Y - connect \$7 $not$libresoc.v:146013$7996_Y + connect \$9 $and$libresoc.v:155894$8311_Y + connect \$11 $or$libresoc.v:155895$8312_Y + connect \$13 $not$libresoc.v:155896$8313_Y + connect \$15 $or$libresoc.v:155897$8314_Y + connect \$1 $not$libresoc.v:155898$8315_Y + connect \$3 $and$libresoc.v:155899$8316_Y + connect \$5 $or$libresoc.v:155900$8317_Y + connect \$7 $not$libresoc.v:155901$8318_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:146032.1-146090.10" +attribute \src "libresoc.v:155920.1-155978.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 - attribute \src "libresoc.v:146033.7-146033.20" + attribute \src "libresoc.v:155921.7-155921.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146078.3-146086.6" - wire $0\q_int$next[0:0]$8013 - attribute \src "libresoc.v:146076.3-146077.27" + attribute \src "libresoc.v:155966.3-155974.6" + wire $0\q_int$next[0:0]$8335 + attribute \src "libresoc.v:155964.3-155965.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146078.3-146086.6" - wire $1\q_int$next[0:0]$8014 - attribute \src "libresoc.v:146055.7-146055.19" + attribute \src "libresoc.v:155966.3-155974.6" + wire $1\q_int$next[0:0]$8336 + attribute \src "libresoc.v:155943.7-155943.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146068.17-146068.96" - wire $and$libresoc.v:146068$8003_Y - attribute \src "libresoc.v:146073.17-146073.96" - wire $and$libresoc.v:146073$8008_Y - attribute \src "libresoc.v:146070.18-146070.93" - wire $not$libresoc.v:146070$8005_Y - attribute \src "libresoc.v:146072.17-146072.92" - wire $not$libresoc.v:146072$8007_Y - attribute \src "libresoc.v:146075.17-146075.92" - wire $not$libresoc.v:146075$8010_Y - attribute \src "libresoc.v:146069.18-146069.98" - wire $or$libresoc.v:146069$8004_Y - attribute \src "libresoc.v:146071.18-146071.99" - wire $or$libresoc.v:146071$8006_Y - attribute \src "libresoc.v:146074.17-146074.97" - wire $or$libresoc.v:146074$8009_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:155956.17-155956.96" + wire $and$libresoc.v:155956$8325_Y + attribute \src "libresoc.v:155961.17-155961.96" + wire $and$libresoc.v:155961$8330_Y + attribute \src "libresoc.v:155958.18-155958.93" + wire $not$libresoc.v:155958$8327_Y + attribute \src "libresoc.v:155960.17-155960.92" + wire $not$libresoc.v:155960$8329_Y + attribute \src "libresoc.v:155963.17-155963.92" + wire $not$libresoc.v:155963$8332_Y + attribute \src "libresoc.v:155957.18-155957.98" + wire $or$libresoc.v:155957$8326_Y + attribute \src "libresoc.v:155959.18-155959.99" + wire $or$libresoc.v:155959$8328_Y + attribute \src "libresoc.v:155962.17-155962.97" + wire $or$libresoc.v:155962$8331_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:146033.7-146033.15" + attribute \src "libresoc.v:155921.7-155921.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146068$8003 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:155956$8325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306414,10 +325326,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146068$8003_Y + connect \Y $and$libresoc.v:155956$8325_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146073$8008 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:155961$8330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306425,34 +325337,34 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146073$8008_Y + connect \Y $and$libresoc.v:155961$8330_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146070$8005 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:155958$8327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:146070$8005_Y + connect \Y $not$libresoc.v:155958$8327_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146072$8007 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:155960$8329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146072$8007_Y + connect \Y $not$libresoc.v:155960$8329_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146075$8010 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:155963$8332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146075$8010_Y + connect \Y $not$libresoc.v:155963$8332_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146069$8004 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:155957$8326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306460,10 +325372,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:146069$8004_Y + connect \Y $or$libresoc.v:155957$8326_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146071$8006 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:155959$8328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306471,10 +325383,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:146071$8006_Y + connect \Y $or$libresoc.v:155959$8328_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146074$8009 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:155962$8331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306482,39 +325394,39 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:146074$8009_Y + connect \Y $or$libresoc.v:155962$8331_Y end - attribute \src "libresoc.v:146033.7-146033.20" - process $proc$libresoc.v:146033$8015 + attribute \src "libresoc.v:155921.7-155921.20" + process $proc$libresoc.v:155921$8337 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146055.7-146055.19" - process $proc$libresoc.v:146055$8016 + attribute \src "libresoc.v:155943.7-155943.19" + process $proc$libresoc.v:155943$8338 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146076.3-146077.27" - process $proc$libresoc.v:146076$8011 + attribute \src "libresoc.v:155964.3-155965.27" + process $proc$libresoc.v:155964$8333 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146078.3-146086.6" - process $proc$libresoc.v:146078$8012 + attribute \src "libresoc.v:155966.3-155974.6" + process $proc$libresoc.v:155966$8334 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8013 $1\q_int$next[0:0]$8014 - attribute \src "libresoc.v:146079.5-146079.29" + assign $0\q_int$next[0:0]$8335 $1\q_int$next[0:0]$8336 + attribute \src "libresoc.v:155967.5-155967.29" switch \initial - attribute \src "libresoc.v:146079.9-146079.17" + attribute \src "libresoc.v:155967.9-155967.17" case 1'1 case end @@ -306523,94 +325435,94 @@ module \opc_l$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8014 1'0 + assign $1\q_int$next[0:0]$8336 1'0 case - assign $1\q_int$next[0:0]$8014 \$5 + assign $1\q_int$next[0:0]$8336 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8013 + update \q_int$next $0\q_int$next[0:0]$8335 end - connect \$9 $and$libresoc.v:146068$8003_Y - connect \$11 $or$libresoc.v:146069$8004_Y - connect \$13 $not$libresoc.v:146070$8005_Y - connect \$15 $or$libresoc.v:146071$8006_Y - connect \$1 $not$libresoc.v:146072$8007_Y - connect \$3 $and$libresoc.v:146073$8008_Y - connect \$5 $or$libresoc.v:146074$8009_Y - connect \$7 $not$libresoc.v:146075$8010_Y + connect \$9 $and$libresoc.v:155956$8325_Y + connect \$11 $or$libresoc.v:155957$8326_Y + connect \$13 $not$libresoc.v:155958$8327_Y + connect \$15 $or$libresoc.v:155959$8328_Y + connect \$1 $not$libresoc.v:155960$8329_Y + connect \$3 $and$libresoc.v:155961$8330_Y + connect \$5 $or$libresoc.v:155962$8331_Y + connect \$7 $not$libresoc.v:155963$8332_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:146094.1-146152.10" +attribute \src "libresoc.v:155982.1-156040.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 - attribute \src "libresoc.v:146095.7-146095.20" + attribute \src "libresoc.v:155983.7-155983.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146140.3-146148.6" - wire $0\q_int$next[0:0]$8027 - attribute \src "libresoc.v:146138.3-146139.27" + attribute \src "libresoc.v:156028.3-156036.6" + wire $0\q_int$next[0:0]$8349 + attribute \src "libresoc.v:156026.3-156027.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146140.3-146148.6" - wire $1\q_int$next[0:0]$8028 - attribute \src "libresoc.v:146117.7-146117.19" + attribute \src "libresoc.v:156028.3-156036.6" + wire $1\q_int$next[0:0]$8350 + attribute \src "libresoc.v:156005.7-156005.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146130.17-146130.96" - wire $and$libresoc.v:146130$8017_Y - attribute \src "libresoc.v:146135.17-146135.96" - wire $and$libresoc.v:146135$8022_Y - attribute \src "libresoc.v:146132.18-146132.93" - wire $not$libresoc.v:146132$8019_Y - attribute \src "libresoc.v:146134.17-146134.92" - wire $not$libresoc.v:146134$8021_Y - attribute \src "libresoc.v:146137.17-146137.92" - wire $not$libresoc.v:146137$8024_Y - attribute \src "libresoc.v:146131.18-146131.98" - wire $or$libresoc.v:146131$8018_Y - attribute \src "libresoc.v:146133.18-146133.99" - wire $or$libresoc.v:146133$8020_Y - attribute \src "libresoc.v:146136.17-146136.97" - wire $or$libresoc.v:146136$8023_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:156018.17-156018.96" + wire $and$libresoc.v:156018$8339_Y + attribute \src "libresoc.v:156023.17-156023.96" + wire $and$libresoc.v:156023$8344_Y + attribute \src "libresoc.v:156020.18-156020.93" + wire $not$libresoc.v:156020$8341_Y + attribute \src "libresoc.v:156022.17-156022.92" + wire $not$libresoc.v:156022$8343_Y + attribute \src "libresoc.v:156025.17-156025.92" + wire $not$libresoc.v:156025$8346_Y + attribute \src "libresoc.v:156019.18-156019.98" + wire $or$libresoc.v:156019$8340_Y + attribute \src "libresoc.v:156021.18-156021.99" + wire $or$libresoc.v:156021$8342_Y + attribute \src "libresoc.v:156024.17-156024.97" + wire $or$libresoc.v:156024$8345_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:146095.7-146095.15" + attribute \src "libresoc.v:155983.7-155983.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146130$8017 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156018$8339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306618,10 +325530,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146130$8017_Y + connect \Y $and$libresoc.v:156018$8339_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146135$8022 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156023$8344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306629,34 +325541,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146135$8022_Y + connect \Y $and$libresoc.v:156023$8344_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146132$8019 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156020$8341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:146132$8019_Y + connect \Y $not$libresoc.v:156020$8341_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146134$8021 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156022$8343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146134$8021_Y + connect \Y $not$libresoc.v:156022$8343_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146137$8024 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156025$8346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146137$8024_Y + connect \Y $not$libresoc.v:156025$8346_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146131$8018 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156019$8340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306664,10 +325576,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:146131$8018_Y + connect \Y $or$libresoc.v:156019$8340_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146133$8020 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156021$8342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306675,10 +325587,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:146133$8020_Y + connect \Y $or$libresoc.v:156021$8342_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146136$8023 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156024$8345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306686,39 +325598,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:146136$8023_Y + connect \Y $or$libresoc.v:156024$8345_Y end - attribute \src "libresoc.v:146095.7-146095.20" - process $proc$libresoc.v:146095$8029 + attribute \src "libresoc.v:155983.7-155983.20" + process $proc$libresoc.v:155983$8351 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146117.7-146117.19" - process $proc$libresoc.v:146117$8030 + attribute \src "libresoc.v:156005.7-156005.19" + process $proc$libresoc.v:156005$8352 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146138.3-146139.27" - process $proc$libresoc.v:146138$8025 + attribute \src "libresoc.v:156026.3-156027.27" + process $proc$libresoc.v:156026$8347 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146140.3-146148.6" - process $proc$libresoc.v:146140$8026 + attribute \src "libresoc.v:156028.3-156036.6" + process $proc$libresoc.v:156028$8348 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8027 $1\q_int$next[0:0]$8028 - attribute \src "libresoc.v:146141.5-146141.29" + assign $0\q_int$next[0:0]$8349 $1\q_int$next[0:0]$8350 + attribute \src "libresoc.v:156029.5-156029.29" switch \initial - attribute \src "libresoc.v:146141.9-146141.17" + attribute \src "libresoc.v:156029.9-156029.17" case 1'1 case end @@ -306727,94 +325639,94 @@ module \opc_l$24 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8028 1'0 + assign $1\q_int$next[0:0]$8350 1'0 case - assign $1\q_int$next[0:0]$8028 \$5 + assign $1\q_int$next[0:0]$8350 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8027 + update \q_int$next $0\q_int$next[0:0]$8349 end - connect \$9 $and$libresoc.v:146130$8017_Y - connect \$11 $or$libresoc.v:146131$8018_Y - connect \$13 $not$libresoc.v:146132$8019_Y - connect \$15 $or$libresoc.v:146133$8020_Y - connect \$1 $not$libresoc.v:146134$8021_Y - connect \$3 $and$libresoc.v:146135$8022_Y - connect \$5 $or$libresoc.v:146136$8023_Y - connect \$7 $not$libresoc.v:146137$8024_Y + connect \$9 $and$libresoc.v:156018$8339_Y + connect \$11 $or$libresoc.v:156019$8340_Y + connect \$13 $not$libresoc.v:156020$8341_Y + connect \$15 $or$libresoc.v:156021$8342_Y + connect \$1 $not$libresoc.v:156022$8343_Y + connect \$3 $and$libresoc.v:156023$8344_Y + connect \$5 $or$libresoc.v:156024$8345_Y + connect \$7 $not$libresoc.v:156025$8346_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:146156.1-146214.10" +attribute \src "libresoc.v:156044.1-156102.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 - attribute \src "libresoc.v:146157.7-146157.20" + attribute \src "libresoc.v:156045.7-156045.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146202.3-146210.6" - wire $0\q_int$next[0:0]$8041 - attribute \src "libresoc.v:146200.3-146201.27" + attribute \src "libresoc.v:156090.3-156098.6" + wire $0\q_int$next[0:0]$8363 + attribute \src "libresoc.v:156088.3-156089.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146202.3-146210.6" - wire $1\q_int$next[0:0]$8042 - attribute \src "libresoc.v:146179.7-146179.19" + attribute \src "libresoc.v:156090.3-156098.6" + wire $1\q_int$next[0:0]$8364 + attribute \src "libresoc.v:156067.7-156067.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146192.17-146192.96" - wire $and$libresoc.v:146192$8031_Y - attribute \src "libresoc.v:146197.17-146197.96" - wire $and$libresoc.v:146197$8036_Y - attribute \src "libresoc.v:146194.18-146194.93" - wire $not$libresoc.v:146194$8033_Y - attribute \src "libresoc.v:146196.17-146196.92" - wire $not$libresoc.v:146196$8035_Y - attribute \src "libresoc.v:146199.17-146199.92" - wire $not$libresoc.v:146199$8038_Y - attribute \src "libresoc.v:146193.18-146193.98" - wire $or$libresoc.v:146193$8032_Y - attribute \src "libresoc.v:146195.18-146195.99" - wire $or$libresoc.v:146195$8034_Y - attribute \src "libresoc.v:146198.17-146198.97" - wire $or$libresoc.v:146198$8037_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:156080.17-156080.96" + wire $and$libresoc.v:156080$8353_Y + attribute \src "libresoc.v:156085.17-156085.96" + wire $and$libresoc.v:156085$8358_Y + attribute \src "libresoc.v:156082.18-156082.93" + wire $not$libresoc.v:156082$8355_Y + attribute \src "libresoc.v:156084.17-156084.92" + wire $not$libresoc.v:156084$8357_Y + attribute \src "libresoc.v:156087.17-156087.92" + wire $not$libresoc.v:156087$8360_Y + attribute \src "libresoc.v:156081.18-156081.98" + wire $or$libresoc.v:156081$8354_Y + attribute \src "libresoc.v:156083.18-156083.99" + wire $or$libresoc.v:156083$8356_Y + attribute \src "libresoc.v:156086.17-156086.97" + wire $or$libresoc.v:156086$8359_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:146157.7-146157.15" + attribute \src "libresoc.v:156045.7-156045.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146192$8031 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156080$8353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306822,10 +325734,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146192$8031_Y + connect \Y $and$libresoc.v:156080$8353_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146197$8036 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156085$8358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306833,34 +325745,34 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146197$8036_Y + connect \Y $and$libresoc.v:156085$8358_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146194$8033 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156082$8355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:146194$8033_Y + connect \Y $not$libresoc.v:156082$8355_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146196$8035 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156084$8357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146196$8035_Y + connect \Y $not$libresoc.v:156084$8357_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146199$8038 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156087$8360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146199$8038_Y + connect \Y $not$libresoc.v:156087$8360_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146193$8032 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156081$8354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306868,10 +325780,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:146193$8032_Y + connect \Y $or$libresoc.v:156081$8354_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146195$8034 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156083$8356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306879,10 +325791,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:146195$8034_Y + connect \Y $or$libresoc.v:156083$8356_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146198$8037 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156086$8359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306890,39 +325802,39 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:146198$8037_Y + connect \Y $or$libresoc.v:156086$8359_Y end - attribute \src "libresoc.v:146157.7-146157.20" - process $proc$libresoc.v:146157$8043 + attribute \src "libresoc.v:156045.7-156045.20" + process $proc$libresoc.v:156045$8365 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146179.7-146179.19" - process $proc$libresoc.v:146179$8044 + attribute \src "libresoc.v:156067.7-156067.19" + process $proc$libresoc.v:156067$8366 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146200.3-146201.27" - process $proc$libresoc.v:146200$8039 + attribute \src "libresoc.v:156088.3-156089.27" + process $proc$libresoc.v:156088$8361 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146202.3-146210.6" - process $proc$libresoc.v:146202$8040 + attribute \src "libresoc.v:156090.3-156098.6" + process $proc$libresoc.v:156090$8362 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8041 $1\q_int$next[0:0]$8042 - attribute \src "libresoc.v:146203.5-146203.29" + assign $0\q_int$next[0:0]$8363 $1\q_int$next[0:0]$8364 + attribute \src "libresoc.v:156091.5-156091.29" switch \initial - attribute \src "libresoc.v:146203.9-146203.17" + attribute \src "libresoc.v:156091.9-156091.17" case 1'1 case end @@ -306931,94 +325843,94 @@ module \opc_l$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8042 1'0 + assign $1\q_int$next[0:0]$8364 1'0 case - assign $1\q_int$next[0:0]$8042 \$5 + assign $1\q_int$next[0:0]$8364 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8041 + update \q_int$next $0\q_int$next[0:0]$8363 end - connect \$9 $and$libresoc.v:146192$8031_Y - connect \$11 $or$libresoc.v:146193$8032_Y - connect \$13 $not$libresoc.v:146194$8033_Y - connect \$15 $or$libresoc.v:146195$8034_Y - connect \$1 $not$libresoc.v:146196$8035_Y - connect \$3 $and$libresoc.v:146197$8036_Y - connect \$5 $or$libresoc.v:146198$8037_Y - connect \$7 $not$libresoc.v:146199$8038_Y + connect \$9 $and$libresoc.v:156080$8353_Y + connect \$11 $or$libresoc.v:156081$8354_Y + connect \$13 $not$libresoc.v:156082$8355_Y + connect \$15 $or$libresoc.v:156083$8356_Y + connect \$1 $not$libresoc.v:156084$8357_Y + connect \$3 $and$libresoc.v:156085$8358_Y + connect \$5 $or$libresoc.v:156086$8359_Y + connect \$7 $not$libresoc.v:156087$8360_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:146218.1-146276.10" +attribute \src "libresoc.v:156106.1-156164.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 - attribute \src "libresoc.v:146219.7-146219.20" + attribute \src "libresoc.v:156107.7-156107.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146264.3-146272.6" - wire $0\q_int$next[0:0]$8055 - attribute \src "libresoc.v:146262.3-146263.27" + attribute \src "libresoc.v:156152.3-156160.6" + wire $0\q_int$next[0:0]$8377 + attribute \src "libresoc.v:156150.3-156151.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146264.3-146272.6" - wire $1\q_int$next[0:0]$8056 - attribute \src "libresoc.v:146241.7-146241.19" + attribute \src "libresoc.v:156152.3-156160.6" + wire $1\q_int$next[0:0]$8378 + attribute \src "libresoc.v:156129.7-156129.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146254.17-146254.96" - wire $and$libresoc.v:146254$8045_Y - attribute \src "libresoc.v:146259.17-146259.96" - wire $and$libresoc.v:146259$8050_Y - attribute \src "libresoc.v:146256.18-146256.93" - wire $not$libresoc.v:146256$8047_Y - attribute \src "libresoc.v:146258.17-146258.92" - wire $not$libresoc.v:146258$8049_Y - attribute \src "libresoc.v:146261.17-146261.92" - wire $not$libresoc.v:146261$8052_Y - attribute \src "libresoc.v:146255.18-146255.98" - wire $or$libresoc.v:146255$8046_Y - attribute \src "libresoc.v:146257.18-146257.99" - wire $or$libresoc.v:146257$8048_Y - attribute \src "libresoc.v:146260.17-146260.97" - wire $or$libresoc.v:146260$8051_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:156142.17-156142.96" + wire $and$libresoc.v:156142$8367_Y + attribute \src "libresoc.v:156147.17-156147.96" + wire $and$libresoc.v:156147$8372_Y + attribute \src "libresoc.v:156144.18-156144.93" + wire $not$libresoc.v:156144$8369_Y + attribute \src "libresoc.v:156146.17-156146.92" + wire $not$libresoc.v:156146$8371_Y + attribute \src "libresoc.v:156149.17-156149.92" + wire $not$libresoc.v:156149$8374_Y + attribute \src "libresoc.v:156143.18-156143.98" + wire $or$libresoc.v:156143$8368_Y + attribute \src "libresoc.v:156145.18-156145.99" + wire $or$libresoc.v:156145$8370_Y + attribute \src "libresoc.v:156148.17-156148.97" + wire $or$libresoc.v:156148$8373_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:146219.7-146219.15" + attribute \src "libresoc.v:156107.7-156107.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146254$8045 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156142$8367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307026,10 +325938,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146254$8045_Y + connect \Y $and$libresoc.v:156142$8367_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146259$8050 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156147$8372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307037,34 +325949,34 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146259$8050_Y + connect \Y $and$libresoc.v:156147$8372_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146256$8047 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156144$8369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:146256$8047_Y + connect \Y $not$libresoc.v:156144$8369_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146258$8049 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156146$8371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146258$8049_Y + connect \Y $not$libresoc.v:156146$8371_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146261$8052 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156149$8374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146261$8052_Y + connect \Y $not$libresoc.v:156149$8374_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146255$8046 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156143$8368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307072,10 +325984,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:146255$8046_Y + connect \Y $or$libresoc.v:156143$8368_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146257$8048 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156145$8370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307083,10 +325995,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:146257$8048_Y + connect \Y $or$libresoc.v:156145$8370_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146260$8051 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156148$8373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307094,39 +326006,39 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:146260$8051_Y + connect \Y $or$libresoc.v:156148$8373_Y end - attribute \src "libresoc.v:146219.7-146219.20" - process $proc$libresoc.v:146219$8057 + attribute \src "libresoc.v:156107.7-156107.20" + process $proc$libresoc.v:156107$8379 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146241.7-146241.19" - process $proc$libresoc.v:146241$8058 + attribute \src "libresoc.v:156129.7-156129.19" + process $proc$libresoc.v:156129$8380 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146262.3-146263.27" - process $proc$libresoc.v:146262$8053 + attribute \src "libresoc.v:156150.3-156151.27" + process $proc$libresoc.v:156150$8375 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146264.3-146272.6" - process $proc$libresoc.v:146264$8054 + attribute \src "libresoc.v:156152.3-156160.6" + process $proc$libresoc.v:156152$8376 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8055 $1\q_int$next[0:0]$8056 - attribute \src "libresoc.v:146265.5-146265.29" + assign $0\q_int$next[0:0]$8377 $1\q_int$next[0:0]$8378 + attribute \src "libresoc.v:156153.5-156153.29" switch \initial - attribute \src "libresoc.v:146265.9-146265.17" + attribute \src "libresoc.v:156153.9-156153.17" case 1'1 case end @@ -307135,94 +326047,94 @@ module \opc_l$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8056 1'0 + assign $1\q_int$next[0:0]$8378 1'0 case - assign $1\q_int$next[0:0]$8056 \$5 + assign $1\q_int$next[0:0]$8378 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8055 + update \q_int$next $0\q_int$next[0:0]$8377 end - connect \$9 $and$libresoc.v:146254$8045_Y - connect \$11 $or$libresoc.v:146255$8046_Y - connect \$13 $not$libresoc.v:146256$8047_Y - connect \$15 $or$libresoc.v:146257$8048_Y - connect \$1 $not$libresoc.v:146258$8049_Y - connect \$3 $and$libresoc.v:146259$8050_Y - connect \$5 $or$libresoc.v:146260$8051_Y - connect \$7 $not$libresoc.v:146261$8052_Y + connect \$9 $and$libresoc.v:156142$8367_Y + connect \$11 $or$libresoc.v:156143$8368_Y + connect \$13 $not$libresoc.v:156144$8369_Y + connect \$15 $or$libresoc.v:156145$8370_Y + connect \$1 $not$libresoc.v:156146$8371_Y + connect \$3 $and$libresoc.v:156147$8372_Y + connect \$5 $or$libresoc.v:156148$8373_Y + connect \$7 $not$libresoc.v:156149$8374_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:146280.1-146338.10" +attribute \src "libresoc.v:156168.1-156226.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 - attribute \src "libresoc.v:146281.7-146281.20" + attribute \src "libresoc.v:156169.7-156169.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146326.3-146334.6" - wire $0\q_int$next[0:0]$8069 - attribute \src "libresoc.v:146324.3-146325.27" + attribute \src "libresoc.v:156214.3-156222.6" + wire $0\q_int$next[0:0]$8391 + attribute \src "libresoc.v:156212.3-156213.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146326.3-146334.6" - wire $1\q_int$next[0:0]$8070 - attribute \src "libresoc.v:146303.7-146303.19" + attribute \src "libresoc.v:156214.3-156222.6" + wire $1\q_int$next[0:0]$8392 + attribute \src "libresoc.v:156191.7-156191.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146316.17-146316.96" - wire $and$libresoc.v:146316$8059_Y - attribute \src "libresoc.v:146321.17-146321.96" - wire $and$libresoc.v:146321$8064_Y - attribute \src "libresoc.v:146318.18-146318.93" - wire $not$libresoc.v:146318$8061_Y - attribute \src "libresoc.v:146320.17-146320.92" - wire $not$libresoc.v:146320$8063_Y - attribute \src "libresoc.v:146323.17-146323.92" - wire $not$libresoc.v:146323$8066_Y - attribute \src "libresoc.v:146317.18-146317.98" - wire $or$libresoc.v:146317$8060_Y - attribute \src "libresoc.v:146319.18-146319.99" - wire $or$libresoc.v:146319$8062_Y - attribute \src "libresoc.v:146322.17-146322.97" - wire $or$libresoc.v:146322$8065_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:156204.17-156204.96" + wire $and$libresoc.v:156204$8381_Y + attribute \src "libresoc.v:156209.17-156209.96" + wire $and$libresoc.v:156209$8386_Y + attribute \src "libresoc.v:156206.18-156206.93" + wire $not$libresoc.v:156206$8383_Y + attribute \src "libresoc.v:156208.17-156208.92" + wire $not$libresoc.v:156208$8385_Y + attribute \src "libresoc.v:156211.17-156211.92" + wire $not$libresoc.v:156211$8388_Y + attribute \src "libresoc.v:156205.18-156205.98" + wire $or$libresoc.v:156205$8382_Y + attribute \src "libresoc.v:156207.18-156207.99" + wire $or$libresoc.v:156207$8384_Y + attribute \src "libresoc.v:156210.17-156210.97" + wire $or$libresoc.v:156210$8387_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:146281.7-146281.15" + attribute \src "libresoc.v:156169.7-156169.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146316$8059 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156204$8381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307230,10 +326142,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146316$8059_Y + connect \Y $and$libresoc.v:156204$8381_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146321$8064 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156209$8386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307241,34 +326153,34 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146321$8064_Y + connect \Y $and$libresoc.v:156209$8386_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146318$8061 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156206$8383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:146318$8061_Y + connect \Y $not$libresoc.v:156206$8383_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146320$8063 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156208$8385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146320$8063_Y + connect \Y $not$libresoc.v:156208$8385_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146323$8066 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156211$8388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146323$8066_Y + connect \Y $not$libresoc.v:156211$8388_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146317$8060 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156205$8382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307276,10 +326188,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:146317$8060_Y + connect \Y $or$libresoc.v:156205$8382_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146319$8062 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156207$8384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307287,10 +326199,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:146319$8062_Y + connect \Y $or$libresoc.v:156207$8384_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146322$8065 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156210$8387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307298,39 +326210,39 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:146322$8065_Y + connect \Y $or$libresoc.v:156210$8387_Y end - attribute \src "libresoc.v:146281.7-146281.20" - process $proc$libresoc.v:146281$8071 + attribute \src "libresoc.v:156169.7-156169.20" + process $proc$libresoc.v:156169$8393 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146303.7-146303.19" - process $proc$libresoc.v:146303$8072 + attribute \src "libresoc.v:156191.7-156191.19" + process $proc$libresoc.v:156191$8394 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146324.3-146325.27" - process $proc$libresoc.v:146324$8067 + attribute \src "libresoc.v:156212.3-156213.27" + process $proc$libresoc.v:156212$8389 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146326.3-146334.6" - process $proc$libresoc.v:146326$8068 + attribute \src "libresoc.v:156214.3-156222.6" + process $proc$libresoc.v:156214$8390 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8069 $1\q_int$next[0:0]$8070 - attribute \src "libresoc.v:146327.5-146327.29" + assign $0\q_int$next[0:0]$8391 $1\q_int$next[0:0]$8392 + attribute \src "libresoc.v:156215.5-156215.29" switch \initial - attribute \src "libresoc.v:146327.9-146327.17" + attribute \src "libresoc.v:156215.9-156215.17" case 1'1 case end @@ -307339,94 +326251,94 @@ module \opc_l$68 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8070 1'0 + assign $1\q_int$next[0:0]$8392 1'0 case - assign $1\q_int$next[0:0]$8070 \$5 + assign $1\q_int$next[0:0]$8392 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8069 + update \q_int$next $0\q_int$next[0:0]$8391 end - connect \$9 $and$libresoc.v:146316$8059_Y - connect \$11 $or$libresoc.v:146317$8060_Y - connect \$13 $not$libresoc.v:146318$8061_Y - connect \$15 $or$libresoc.v:146319$8062_Y - connect \$1 $not$libresoc.v:146320$8063_Y - connect \$3 $and$libresoc.v:146321$8064_Y - connect \$5 $or$libresoc.v:146322$8065_Y - connect \$7 $not$libresoc.v:146323$8066_Y + connect \$9 $and$libresoc.v:156204$8381_Y + connect \$11 $or$libresoc.v:156205$8382_Y + connect \$13 $not$libresoc.v:156206$8383_Y + connect \$15 $or$libresoc.v:156207$8384_Y + connect \$1 $not$libresoc.v:156208$8385_Y + connect \$3 $and$libresoc.v:156209$8386_Y + connect \$5 $or$libresoc.v:156210$8387_Y + connect \$7 $not$libresoc.v:156211$8388_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:146342.1-146400.10" +attribute \src "libresoc.v:156230.1-156288.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 - attribute \src "libresoc.v:146343.7-146343.20" + attribute \src "libresoc.v:156231.7-156231.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146388.3-146396.6" - wire $0\q_int$next[0:0]$8083 - attribute \src "libresoc.v:146386.3-146387.27" + attribute \src "libresoc.v:156276.3-156284.6" + wire $0\q_int$next[0:0]$8405 + attribute \src "libresoc.v:156274.3-156275.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146388.3-146396.6" - wire $1\q_int$next[0:0]$8084 - attribute \src "libresoc.v:146365.7-146365.19" + attribute \src "libresoc.v:156276.3-156284.6" + wire $1\q_int$next[0:0]$8406 + attribute \src "libresoc.v:156253.7-156253.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146378.17-146378.96" - wire $and$libresoc.v:146378$8073_Y - attribute \src "libresoc.v:146383.17-146383.96" - wire $and$libresoc.v:146383$8078_Y - attribute \src "libresoc.v:146380.18-146380.93" - wire $not$libresoc.v:146380$8075_Y - attribute \src "libresoc.v:146382.17-146382.92" - wire $not$libresoc.v:146382$8077_Y - attribute \src "libresoc.v:146385.17-146385.92" - wire $not$libresoc.v:146385$8080_Y - attribute \src "libresoc.v:146379.18-146379.98" - wire $or$libresoc.v:146379$8074_Y - attribute \src "libresoc.v:146381.18-146381.99" - wire $or$libresoc.v:146381$8076_Y - attribute \src "libresoc.v:146384.17-146384.97" - wire $or$libresoc.v:146384$8079_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:156266.17-156266.96" + wire $and$libresoc.v:156266$8395_Y + attribute \src "libresoc.v:156271.17-156271.96" + wire $and$libresoc.v:156271$8400_Y + attribute \src "libresoc.v:156268.18-156268.93" + wire $not$libresoc.v:156268$8397_Y + attribute \src "libresoc.v:156270.17-156270.92" + wire $not$libresoc.v:156270$8399_Y + attribute \src "libresoc.v:156273.17-156273.92" + wire $not$libresoc.v:156273$8402_Y + attribute \src "libresoc.v:156267.18-156267.98" + wire $or$libresoc.v:156267$8396_Y + attribute \src "libresoc.v:156269.18-156269.99" + wire $or$libresoc.v:156269$8398_Y + attribute \src "libresoc.v:156272.17-156272.97" + wire $or$libresoc.v:156272$8401_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:146343.7-146343.15" + attribute \src "libresoc.v:156231.7-156231.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146378$8073 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156266$8395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307434,10 +326346,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146378$8073_Y + connect \Y $and$libresoc.v:156266$8395_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146383$8078 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156271$8400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307445,34 +326357,34 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146383$8078_Y + connect \Y $and$libresoc.v:156271$8400_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146380$8075 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156268$8397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:146380$8075_Y + connect \Y $not$libresoc.v:156268$8397_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146382$8077 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156270$8399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146382$8077_Y + connect \Y $not$libresoc.v:156270$8399_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146385$8080 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156273$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:146385$8080_Y + connect \Y $not$libresoc.v:156273$8402_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146379$8074 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156267$8396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307480,10 +326392,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:146379$8074_Y + connect \Y $or$libresoc.v:156267$8396_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146381$8076 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156269$8398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307491,10 +326403,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:146381$8076_Y + connect \Y $or$libresoc.v:156269$8398_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146384$8079 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156272$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307502,39 +326414,39 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:146384$8079_Y + connect \Y $or$libresoc.v:156272$8401_Y end - attribute \src "libresoc.v:146343.7-146343.20" - process $proc$libresoc.v:146343$8085 + attribute \src "libresoc.v:156231.7-156231.20" + process $proc$libresoc.v:156231$8407 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146365.7-146365.19" - process $proc$libresoc.v:146365$8086 + attribute \src "libresoc.v:156253.7-156253.19" + process $proc$libresoc.v:156253$8408 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146386.3-146387.27" - process $proc$libresoc.v:146386$8081 + attribute \src "libresoc.v:156274.3-156275.27" + process $proc$libresoc.v:156274$8403 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146388.3-146396.6" - process $proc$libresoc.v:146388$8082 + attribute \src "libresoc.v:156276.3-156284.6" + process $proc$libresoc.v:156276$8404 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8083 $1\q_int$next[0:0]$8084 - attribute \src "libresoc.v:146389.5-146389.29" + assign $0\q_int$next[0:0]$8405 $1\q_int$next[0:0]$8406 + attribute \src "libresoc.v:156277.5-156277.29" switch \initial - attribute \src "libresoc.v:146389.9-146389.17" + attribute \src "libresoc.v:156277.9-156277.17" case 1'1 case end @@ -307543,90 +326455,90 @@ module \opc_l$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8084 1'0 + assign $1\q_int$next[0:0]$8406 1'0 case - assign $1\q_int$next[0:0]$8084 \$5 + assign $1\q_int$next[0:0]$8406 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8083 + update \q_int$next $0\q_int$next[0:0]$8405 end - connect \$9 $and$libresoc.v:146378$8073_Y - connect \$11 $or$libresoc.v:146379$8074_Y - connect \$13 $not$libresoc.v:146380$8075_Y - connect \$15 $or$libresoc.v:146381$8076_Y - connect \$1 $not$libresoc.v:146382$8077_Y - connect \$3 $and$libresoc.v:146383$8078_Y - connect \$5 $or$libresoc.v:146384$8079_Y - connect \$7 $not$libresoc.v:146385$8080_Y + connect \$9 $and$libresoc.v:156266$8395_Y + connect \$11 $or$libresoc.v:156267$8396_Y + connect \$13 $not$libresoc.v:156268$8397_Y + connect \$15 $or$libresoc.v:156269$8398_Y + connect \$1 $not$libresoc.v:156270$8399_Y + connect \$3 $and$libresoc.v:156271$8400_Y + connect \$5 $or$libresoc.v:156272$8401_Y + connect \$7 $not$libresoc.v:156273$8402_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:146404.1-146856.10" +attribute \src "libresoc.v:156292.1-156750.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:146775.3-146786.6" + attribute \src "libresoc.v:156669.3-156680.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:146405.7-146405.20" + attribute \src "libresoc.v:156293.7-156293.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146787.3-146798.6" - wire width 65 $0\o$28[64:0]$8105 - attribute \src "libresoc.v:146763.3-146774.6" + attribute \src "libresoc.v:156681.3-156692.6" + wire width 65 $0\o$28[64:0]$8427 + attribute \src "libresoc.v:156657.3-156668.6" wire $0\so[0:0] - attribute \src "libresoc.v:146819.3-146828.6" - wire width 2 $0\xer_ov$24[1:0]$8112 - attribute \src "libresoc.v:146829.3-146838.6" + attribute \src "libresoc.v:156713.3-156722.6" + wire width 2 $0\xer_ov$24[1:0]$8434 + attribute \src "libresoc.v:156723.3-156732.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:146799.3-146808.6" - wire $0\xer_so$25[0:0]$8108 - attribute \src "libresoc.v:146809.3-146818.6" + attribute \src "libresoc.v:156693.3-156702.6" + wire $0\xer_so$25[0:0]$8430 + attribute \src "libresoc.v:156703.3-156712.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:146775.3-146786.6" + attribute \src "libresoc.v:156669.3-156680.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:146787.3-146798.6" - wire width 65 $1\o$28[64:0]$8106 - attribute \src "libresoc.v:146763.3-146774.6" + attribute \src "libresoc.v:156681.3-156692.6" + wire width 65 $1\o$28[64:0]$8428 + attribute \src "libresoc.v:156657.3-156668.6" wire $1\so[0:0] - attribute \src "libresoc.v:146819.3-146828.6" - wire width 2 $1\xer_ov$24[1:0]$8113 - attribute \src "libresoc.v:146829.3-146838.6" + attribute \src "libresoc.v:156713.3-156722.6" + wire width 2 $1\xer_ov$24[1:0]$8435 + attribute \src "libresoc.v:156723.3-156732.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:146799.3-146808.6" - wire $1\xer_so$25[0:0]$8109 - attribute \src "libresoc.v:146809.3-146818.6" + attribute \src "libresoc.v:156693.3-156702.6" + wire $1\xer_so$25[0:0]$8431 + attribute \src "libresoc.v:156703.3-156712.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:146750.18-146750.128" - wire $and$libresoc.v:146750$8087_Y - attribute \src "libresoc.v:146758.18-146758.112" - wire $and$libresoc.v:146758$8097_Y - attribute \src "libresoc.v:146761.18-146761.125" - wire $and$libresoc.v:146761$8100_Y - attribute \src "libresoc.v:146754.18-146754.123" - wire $eq$libresoc.v:146754$8093_Y - attribute \src "libresoc.v:146755.18-146755.123" - wire $eq$libresoc.v:146755$8094_Y - attribute \src "libresoc.v:146752.18-146752.103" - wire width 65 $extend$libresoc.v:146752$8089_Y - attribute \src "libresoc.v:146753.18-146753.101" - wire width 65 $extend$libresoc.v:146753$8091_Y - attribute \src "libresoc.v:146751.18-146751.100" - wire width 64 $not$libresoc.v:146751$8088_Y - attribute \src "libresoc.v:146757.18-146757.107" - wire $not$libresoc.v:146757$8096_Y - attribute \src "libresoc.v:146760.18-146760.107" - wire $not$libresoc.v:146760$8099_Y - attribute \src "libresoc.v:146759.18-146759.115" - wire $or$libresoc.v:146759$8098_Y - attribute \src "libresoc.v:146762.18-146762.112" - wire $or$libresoc.v:146762$8101_Y - attribute \src "libresoc.v:146752.18-146752.103" - wire width 65 $pos$libresoc.v:146752$8090_Y - attribute \src "libresoc.v:146753.18-146753.101" - wire width 65 $pos$libresoc.v:146753$8092_Y - attribute \src "libresoc.v:146756.18-146756.105" - wire $reduce_or$libresoc.v:146756$8095_Y + attribute \src "libresoc.v:156644.18-156644.128" + wire $and$libresoc.v:156644$8409_Y + attribute \src "libresoc.v:156652.18-156652.112" + wire $and$libresoc.v:156652$8419_Y + attribute \src "libresoc.v:156655.18-156655.125" + wire $and$libresoc.v:156655$8422_Y + attribute \src "libresoc.v:156648.18-156648.123" + wire $eq$libresoc.v:156648$8415_Y + attribute \src "libresoc.v:156649.18-156649.123" + wire $eq$libresoc.v:156649$8416_Y + attribute \src "libresoc.v:156646.18-156646.103" + wire width 65 $extend$libresoc.v:156646$8411_Y + attribute \src "libresoc.v:156647.18-156647.101" + wire width 65 $extend$libresoc.v:156647$8413_Y + attribute \src "libresoc.v:156645.18-156645.100" + wire width 64 $not$libresoc.v:156645$8410_Y + attribute \src "libresoc.v:156651.18-156651.107" + wire $not$libresoc.v:156651$8418_Y + attribute \src "libresoc.v:156654.18-156654.107" + wire $not$libresoc.v:156654$8421_Y + attribute \src "libresoc.v:156653.18-156653.115" + wire $or$libresoc.v:156653$8420_Y + attribute \src "libresoc.v:156656.18-156656.112" + wire $or$libresoc.v:156656$8423_Y + attribute \src "libresoc.v:156646.18-156646.103" + wire width 65 $pos$libresoc.v:156646$8412_Y + attribute \src "libresoc.v:156647.18-156647.101" + wire width 65 $pos$libresoc.v:156647$8414_Y + attribute \src "libresoc.v:156650.18-156650.105" + wire $reduce_or$libresoc.v:156650$8417_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -307658,35 +326570,39 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 42 \alu_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 27 \alu_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 27 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -307785,6 +326701,7 @@ module \output attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -307861,6 +326778,7 @@ module \output attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 26 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -307915,7 +326833,7 @@ module \output wire width 4 output 46 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \cr_a_ok - attribute \src "libresoc.v:146405.7-146405.15" + attribute \src "libresoc.v:156293.7-156293.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -307929,9 +326847,9 @@ module \output wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 54 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 25 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 19 \o @@ -307970,7 +326888,7 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:146750$8087 + cell $and $and$libresoc.v:156644$8409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307978,10 +326896,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:146750$8087_Y + connect \Y $and$libresoc.v:156644$8409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:146758$8097 + cell $and $and$libresoc.v:156652$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307989,10 +326907,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:146758$8097_Y + connect \Y $and$libresoc.v:156652$8419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:146761$8100 + cell $and $and$libresoc.v:156655$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308000,10 +326918,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:146761$8100_Y + connect \Y $and$libresoc.v:156655$8422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:146754$8093 + cell $eq $eq$libresoc.v:156648$8415 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308011,10 +326929,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146754$8093_Y + connect \Y $eq$libresoc.v:156648$8415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:146755$8094 + cell $eq $eq$libresoc.v:156649$8416 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308022,50 +326940,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:146755$8094_Y + connect \Y $eq$libresoc.v:156649$8416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:146752$8089 + cell $pos $extend$libresoc.v:156646$8411 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:146752$8089_Y + connect \Y $extend$libresoc.v:156646$8411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:146753$8091 + cell $pos $extend$libresoc.v:156647$8413 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:146753$8091_Y + connect \Y $extend$libresoc.v:156647$8413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:146751$8088 + cell $not $not$libresoc.v:156645$8410 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:146751$8088_Y + connect \Y $not$libresoc.v:156645$8410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:146757$8096 + cell $not $not$libresoc.v:156651$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:146757$8096_Y + connect \Y $not$libresoc.v:156651$8418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:146760$8099 + cell $not $not$libresoc.v:156654$8421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:146760$8099_Y + connect \Y $not$libresoc.v:156654$8421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:146759$8098 + cell $or $or$libresoc.v:156653$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308073,10 +326991,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:146759$8098_Y + connect \Y $or$libresoc.v:156653$8420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:146762$8101 + cell $or $or$libresoc.v:156656$8423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308084,47 +327002,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:146762$8101_Y + connect \Y $or$libresoc.v:156656$8423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:146752$8090 + cell $pos $pos$libresoc.v:156646$8412 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:146752$8089_Y - connect \Y $pos$libresoc.v:146752$8090_Y + connect \A $extend$libresoc.v:156646$8411_Y + connect \Y $pos$libresoc.v:156646$8412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:146753$8092 + cell $pos $pos$libresoc.v:156647$8414 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:146753$8091_Y - connect \Y $pos$libresoc.v:146753$8092_Y + connect \A $extend$libresoc.v:156647$8413_Y + connect \Y $pos$libresoc.v:156647$8414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:146756$8095 + cell $reduce_or $reduce_or$libresoc.v:156650$8417 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:146756$8095_Y + connect \Y $reduce_or$libresoc.v:156650$8417_Y end - attribute \src "libresoc.v:146405.7-146405.20" - process $proc$libresoc.v:146405$8115 + attribute \src "libresoc.v:156293.7-156293.20" + process $proc$libresoc.v:156293$8437 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146763.3-146774.6" - process $proc$libresoc.v:146763$8102 + attribute \src "libresoc.v:156657.3-156668.6" + process $proc$libresoc.v:156657$8424 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:146764.5-146764.29" + attribute \src "libresoc.v:156658.5-156658.29" switch \initial - attribute \src "libresoc.v:146764.9-146764.17" + attribute \src "libresoc.v:156658.9-156658.17" case 1'1 case end @@ -308142,13 +327060,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:146775.3-146786.6" - process $proc$libresoc.v:146775$8103 + attribute \src "libresoc.v:156669.3-156680.6" + process $proc$libresoc.v:156669$8425 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:146776.5-146776.29" + attribute \src "libresoc.v:156670.5-156670.29" switch \initial - attribute \src "libresoc.v:146776.9-146776.17" + attribute \src "libresoc.v:156670.9-156670.17" case 1'1 case end @@ -308166,13 +327084,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:146787.3-146798.6" - process $proc$libresoc.v:146787$8104 + attribute \src "libresoc.v:156681.3-156692.6" + process $proc$libresoc.v:156681$8426 assign { } { } - assign $0\o$28[64:0]$8105 $1\o$28[64:0]$8106 - attribute \src "libresoc.v:146788.5-146788.29" + assign $0\o$28[64:0]$8427 $1\o$28[64:0]$8428 + attribute \src "libresoc.v:156682.5-156682.29" switch \initial - attribute \src "libresoc.v:146788.9-146788.17" + attribute \src "libresoc.v:156682.9-156682.17" case 1'1 case end @@ -308181,23 +327099,23 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$28[64:0]$8106 \$29 + assign $1\o$28[64:0]$8428 \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$28[64:0]$8106 \$33 + assign $1\o$28[64:0]$8428 \$33 end sync always - update \o$28 $0\o$28[64:0]$8105 + update \o$28 $0\o$28[64:0]$8427 end - attribute \src "libresoc.v:146799.3-146808.6" - process $proc$libresoc.v:146799$8107 + attribute \src "libresoc.v:156693.3-156702.6" + process $proc$libresoc.v:156693$8429 assign { } { } assign { } { } - assign $0\xer_so$25[0:0]$8108 $1\xer_so$25[0:0]$8109 - attribute \src "libresoc.v:146800.5-146800.29" + assign $0\xer_so$25[0:0]$8430 $1\xer_so$25[0:0]$8431 + attribute \src "libresoc.v:156694.5-156694.29" switch \initial - attribute \src "libresoc.v:146800.9-146800.17" + attribute \src "libresoc.v:156694.9-156694.17" case 1'1 case end @@ -308206,21 +327124,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$25[0:0]$8109 \$52 + assign $1\xer_so$25[0:0]$8431 \$52 case - assign $1\xer_so$25[0:0]$8109 1'0 + assign $1\xer_so$25[0:0]$8431 1'0 end sync always - update \xer_so$25 $0\xer_so$25[0:0]$8108 + update \xer_so$25 $0\xer_so$25[0:0]$8430 end - attribute \src "libresoc.v:146809.3-146818.6" - process $proc$libresoc.v:146809$8110 + attribute \src "libresoc.v:156703.3-156712.6" + process $proc$libresoc.v:156703$8432 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:146810.5-146810.29" + attribute \src "libresoc.v:156704.5-156704.29" switch \initial - attribute \src "libresoc.v:146810.9-146810.17" + attribute \src "libresoc.v:156704.9-156704.17" case 1'1 case end @@ -308236,14 +327154,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:146819.3-146828.6" - process $proc$libresoc.v:146819$8111 + attribute \src "libresoc.v:156713.3-156722.6" + process $proc$libresoc.v:156713$8433 assign { } { } assign { } { } - assign $0\xer_ov$24[1:0]$8112 $1\xer_ov$24[1:0]$8113 - attribute \src "libresoc.v:146820.5-146820.29" + assign $0\xer_ov$24[1:0]$8434 $1\xer_ov$24[1:0]$8435 + attribute \src "libresoc.v:156714.5-156714.29" switch \initial - attribute \src "libresoc.v:146820.9-146820.17" + attribute \src "libresoc.v:156714.9-156714.17" case 1'1 case end @@ -308252,21 +327170,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$24[1:0]$8113 \xer_ov + assign $1\xer_ov$24[1:0]$8435 \xer_ov case - assign $1\xer_ov$24[1:0]$8113 2'00 + assign $1\xer_ov$24[1:0]$8435 2'00 end sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$8112 + update \xer_ov$24 $0\xer_ov$24[1:0]$8434 end - attribute \src "libresoc.v:146829.3-146838.6" - process $proc$libresoc.v:146829$8114 + attribute \src "libresoc.v:156723.3-156732.6" + process $proc$libresoc.v:156723$8436 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:146830.5-146830.29" + attribute \src "libresoc.v:156724.5-156724.29" switch \initial - attribute \src "libresoc.v:146830.9-146830.17" + attribute \src "libresoc.v:156724.9-156724.17" case 1'1 case end @@ -308282,19 +327200,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:146750$8087_Y - connect \$30 $not$libresoc.v:146751$8088_Y - connect \$29 $pos$libresoc.v:146752$8090_Y - connect \$33 $pos$libresoc.v:146753$8092_Y - connect \$35 $eq$libresoc.v:146754$8093_Y - connect \$37 $eq$libresoc.v:146755$8094_Y - connect \$39 $reduce_or$libresoc.v:146756$8095_Y - connect \$41 $not$libresoc.v:146757$8096_Y - connect \$43 $and$libresoc.v:146758$8097_Y - connect \$45 $or$libresoc.v:146759$8098_Y - connect \$47 $not$libresoc.v:146760$8099_Y - connect \$50 $and$libresoc.v:146761$8100_Y - connect \$52 $or$libresoc.v:146762$8101_Y + connect \$26 $and$libresoc.v:156644$8409_Y + connect \$30 $not$libresoc.v:156645$8410_Y + connect \$29 $pos$libresoc.v:156646$8412_Y + connect \$33 $pos$libresoc.v:156647$8414_Y + connect \$35 $eq$libresoc.v:156648$8415_Y + connect \$37 $eq$libresoc.v:156649$8416_Y + connect \$39 $reduce_or$libresoc.v:156650$8417_Y + connect \$41 $not$libresoc.v:156651$8418_Y + connect \$43 $and$libresoc.v:156652$8419_Y + connect \$45 $or$libresoc.v:156653$8420_Y + connect \$47 $not$libresoc.v:156654$8421_Y + connect \$50 $and$libresoc.v:156655$8422_Y + connect \$52 $or$libresoc.v:156656$8423_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -308313,61 +327231,61 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:146860.1-147255.10" +attribute \src "libresoc.v:156754.1-157155.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 - attribute \src "libresoc.v:147187.3-147198.6" + attribute \src "libresoc.v:157087.3-157098.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:146861.7-146861.20" + attribute \src "libresoc.v:156755.7-156755.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147175.3-147186.6" + attribute \src "libresoc.v:157075.3-157086.6" wire $0\so[0:0] - attribute \src "libresoc.v:147219.3-147228.6" - wire width 2 $0\xer_ov$17[1:0]$8135 - attribute \src "libresoc.v:147229.3-147238.6" + attribute \src "libresoc.v:157119.3-157128.6" + wire width 2 $0\xer_ov$17[1:0]$8457 + attribute \src "libresoc.v:157129.3-157138.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:147199.3-147208.6" - wire $0\xer_so$18[0:0]$8131 - attribute \src "libresoc.v:147209.3-147218.6" + attribute \src "libresoc.v:157099.3-157108.6" + wire $0\xer_so$18[0:0]$8453 + attribute \src "libresoc.v:157109.3-157118.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:147187.3-147198.6" + attribute \src "libresoc.v:157087.3-157098.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:147175.3-147186.6" + attribute \src "libresoc.v:157075.3-157086.6" wire $1\so[0:0] - attribute \src "libresoc.v:147219.3-147228.6" - wire width 2 $1\xer_ov$17[1:0]$8136 - attribute \src "libresoc.v:147229.3-147238.6" + attribute \src "libresoc.v:157119.3-157128.6" + wire width 2 $1\xer_ov$17[1:0]$8458 + attribute \src "libresoc.v:157129.3-157138.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:147199.3-147208.6" - wire $1\xer_so$18[0:0]$8132 - attribute \src "libresoc.v:147209.3-147218.6" + attribute \src "libresoc.v:157099.3-157108.6" + wire $1\xer_so$18[0:0]$8454 + attribute \src "libresoc.v:157109.3-157118.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:147164.18-147164.128" - wire $and$libresoc.v:147164$8116_Y - attribute \src "libresoc.v:147170.18-147170.112" - wire $and$libresoc.v:147170$8123_Y - attribute \src "libresoc.v:147173.18-147173.125" - wire $and$libresoc.v:147173$8126_Y - attribute \src "libresoc.v:147166.18-147166.123" - wire $eq$libresoc.v:147166$8119_Y - attribute \src "libresoc.v:147167.18-147167.123" - wire $eq$libresoc.v:147167$8120_Y - attribute \src "libresoc.v:147165.18-147165.101" - wire width 65 $extend$libresoc.v:147165$8117_Y - attribute \src "libresoc.v:147169.18-147169.107" - wire $not$libresoc.v:147169$8122_Y - attribute \src "libresoc.v:147172.18-147172.107" - wire $not$libresoc.v:147172$8125_Y - attribute \src "libresoc.v:147171.18-147171.115" - wire $or$libresoc.v:147171$8124_Y - attribute \src "libresoc.v:147174.18-147174.112" - wire $or$libresoc.v:147174$8127_Y - attribute \src "libresoc.v:147165.18-147165.101" - wire width 65 $pos$libresoc.v:147165$8118_Y - attribute \src "libresoc.v:147168.18-147168.105" - wire $reduce_or$libresoc.v:147168$8121_Y + attribute \src "libresoc.v:157064.18-157064.128" + wire $and$libresoc.v:157064$8438_Y + attribute \src "libresoc.v:157070.18-157070.112" + wire $and$libresoc.v:157070$8445_Y + attribute \src "libresoc.v:157073.18-157073.125" + wire $and$libresoc.v:157073$8448_Y + attribute \src "libresoc.v:157066.18-157066.123" + wire $eq$libresoc.v:157066$8441_Y + attribute \src "libresoc.v:157067.18-157067.123" + wire $eq$libresoc.v:157067$8442_Y + attribute \src "libresoc.v:157065.18-157065.101" + wire width 65 $extend$libresoc.v:157065$8439_Y + attribute \src "libresoc.v:157069.18-157069.107" + wire $not$libresoc.v:157069$8444_Y + attribute \src "libresoc.v:157072.18-157072.107" + wire $not$libresoc.v:157072$8447_Y + attribute \src "libresoc.v:157071.18-157071.115" + wire $or$libresoc.v:157071$8446_Y + attribute \src "libresoc.v:157074.18-157074.112" + wire $or$libresoc.v:157074$8449_Y + attribute \src "libresoc.v:157065.18-157065.101" + wire width 65 $pos$libresoc.v:157065$8440_Y + attribute \src "libresoc.v:157068.18-157068.105" + wire $reduce_or$libresoc.v:157068$8443_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -308398,7 +327316,7 @@ module \output$100 wire width 4 output 33 \cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \cr_a_ok - attribute \src "libresoc.v:146861.7-146861.15" + attribute \src "libresoc.v:156755.7-156755.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -308413,35 +327331,39 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 20 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -308528,6 +327450,7 @@ module \output$100 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -308604,6 +327527,7 @@ module \output$100 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 19 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -308634,9 +327558,9 @@ module \output$100 wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 39 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 18 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 13 \o @@ -308669,7 +327593,7 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:147164$8116 + cell $and $and$libresoc.v:157064$8438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308677,10 +327601,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:147164$8116_Y + connect \Y $and$libresoc.v:157064$8438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:147170$8123 + cell $and $and$libresoc.v:157070$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308688,10 +327612,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 - connect \Y $and$libresoc.v:147170$8123_Y + connect \Y $and$libresoc.v:157070$8445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:147173$8126 + cell $and $and$libresoc.v:157073$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308699,10 +327623,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:147173$8126_Y + connect \Y $and$libresoc.v:157073$8448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:147166$8119 + cell $eq $eq$libresoc.v:157066$8441 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308710,10 +327634,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147166$8119_Y + connect \Y $eq$libresoc.v:157066$8441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:147167$8120 + cell $eq $eq$libresoc.v:157067$8442 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308721,34 +327645,34 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:147167$8120_Y + connect \Y $eq$libresoc.v:157067$8442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:147165$8117 + cell $pos $extend$libresoc.v:157065$8439 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:147165$8117_Y + connect \Y $extend$libresoc.v:157065$8439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:147169$8122 + cell $not $not$libresoc.v:157069$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:147169$8122_Y + connect \Y $not$libresoc.v:157069$8444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:147172$8125 + cell $not $not$libresoc.v:157072$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:147172$8125_Y + connect \Y $not$libresoc.v:157072$8447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:147171$8124 + cell $or $or$libresoc.v:157071$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308756,10 +327680,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:147171$8124_Y + connect \Y $or$libresoc.v:157071$8446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:147174$8127 + cell $or $or$libresoc.v:157074$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308767,39 +327691,39 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:147174$8127_Y + connect \Y $or$libresoc.v:157074$8449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:147165$8118 + cell $pos $pos$libresoc.v:157065$8440 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:147165$8117_Y - connect \Y $pos$libresoc.v:147165$8118_Y + connect \A $extend$libresoc.v:157065$8439_Y + connect \Y $pos$libresoc.v:157065$8440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:147168$8121 + cell $reduce_or $reduce_or$libresoc.v:157068$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:147168$8121_Y + connect \Y $reduce_or$libresoc.v:157068$8443_Y end - attribute \src "libresoc.v:146861.7-146861.20" - process $proc$libresoc.v:146861$8138 + attribute \src "libresoc.v:156755.7-156755.20" + process $proc$libresoc.v:156755$8460 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147175.3-147186.6" - process $proc$libresoc.v:147175$8128 + attribute \src "libresoc.v:157075.3-157086.6" + process $proc$libresoc.v:157075$8450 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:147176.5-147176.29" + attribute \src "libresoc.v:157076.5-157076.29" switch \initial - attribute \src "libresoc.v:147176.9-147176.17" + attribute \src "libresoc.v:157076.9-157076.17" case 1'1 case end @@ -308817,13 +327741,13 @@ module \output$100 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:147187.3-147198.6" - process $proc$libresoc.v:147187$8129 + attribute \src "libresoc.v:157087.3-157098.6" + process $proc$libresoc.v:157087$8451 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:147188.5-147188.29" + attribute \src "libresoc.v:157088.5-157088.29" switch \initial - attribute \src "libresoc.v:147188.9-147188.17" + attribute \src "libresoc.v:157088.9-157088.17" case 1'1 case end @@ -308841,14 +327765,14 @@ module \output$100 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:147199.3-147208.6" - process $proc$libresoc.v:147199$8130 + attribute \src "libresoc.v:157099.3-157108.6" + process $proc$libresoc.v:157099$8452 assign { } { } assign { } { } - assign $0\xer_so$18[0:0]$8131 $1\xer_so$18[0:0]$8132 - attribute \src "libresoc.v:147200.5-147200.29" + assign $0\xer_so$18[0:0]$8453 $1\xer_so$18[0:0]$8454 + attribute \src "libresoc.v:157100.5-157100.29" switch \initial - attribute \src "libresoc.v:147200.9-147200.17" + attribute \src "libresoc.v:157100.9-157100.17" case 1'1 case end @@ -308857,21 +327781,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$18[0:0]$8132 \$41 + assign $1\xer_so$18[0:0]$8454 \$41 case - assign $1\xer_so$18[0:0]$8132 1'0 + assign $1\xer_so$18[0:0]$8454 1'0 end sync always - update \xer_so$18 $0\xer_so$18[0:0]$8131 + update \xer_so$18 $0\xer_so$18[0:0]$8453 end - attribute \src "libresoc.v:147209.3-147218.6" - process $proc$libresoc.v:147209$8133 + attribute \src "libresoc.v:157109.3-157118.6" + process $proc$libresoc.v:157109$8455 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:147210.5-147210.29" + attribute \src "libresoc.v:157110.5-157110.29" switch \initial - attribute \src "libresoc.v:147210.9-147210.17" + attribute \src "libresoc.v:157110.9-157110.17" case 1'1 case end @@ -308887,14 +327811,14 @@ module \output$100 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:147219.3-147228.6" - process $proc$libresoc.v:147219$8134 + attribute \src "libresoc.v:157119.3-157128.6" + process $proc$libresoc.v:157119$8456 assign { } { } assign { } { } - assign $0\xer_ov$17[1:0]$8135 $1\xer_ov$17[1:0]$8136 - attribute \src "libresoc.v:147220.5-147220.29" + assign $0\xer_ov$17[1:0]$8457 $1\xer_ov$17[1:0]$8458 + attribute \src "libresoc.v:157120.5-157120.29" switch \initial - attribute \src "libresoc.v:147220.9-147220.17" + attribute \src "libresoc.v:157120.9-157120.17" case 1'1 case end @@ -308903,21 +327827,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$17[1:0]$8136 \xer_ov + assign $1\xer_ov$17[1:0]$8458 \xer_ov case - assign $1\xer_ov$17[1:0]$8136 2'00 + assign $1\xer_ov$17[1:0]$8458 2'00 end sync always - update \xer_ov$17 $0\xer_ov$17[1:0]$8135 + update \xer_ov$17 $0\xer_ov$17[1:0]$8457 end - attribute \src "libresoc.v:147229.3-147238.6" - process $proc$libresoc.v:147229$8137 + attribute \src "libresoc.v:157129.3-157138.6" + process $proc$libresoc.v:157129$8459 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:147230.5-147230.29" + attribute \src "libresoc.v:157130.5-157130.29" switch \initial - attribute \src "libresoc.v:147230.9-147230.17" + attribute \src "libresoc.v:157130.9-157130.17" case 1'1 case end @@ -308933,17 +327857,17 @@ module \output$100 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$19 $and$libresoc.v:147164$8116_Y - connect \$22 $pos$libresoc.v:147165$8118_Y - connect \$24 $eq$libresoc.v:147166$8119_Y - connect \$26 $eq$libresoc.v:147167$8120_Y - connect \$28 $reduce_or$libresoc.v:147168$8121_Y - connect \$30 $not$libresoc.v:147169$8122_Y - connect \$32 $and$libresoc.v:147170$8123_Y - connect \$34 $or$libresoc.v:147171$8124_Y - connect \$36 $not$libresoc.v:147172$8125_Y - connect \$39 $and$libresoc.v:147173$8126_Y - connect \$41 $or$libresoc.v:147174$8127_Y + connect \$19 $and$libresoc.v:157064$8438_Y + connect \$22 $pos$libresoc.v:157065$8440_Y + connect \$24 $eq$libresoc.v:157066$8441_Y + connect \$26 $eq$libresoc.v:157067$8442_Y + connect \$28 $reduce_or$libresoc.v:157068$8443_Y + connect \$30 $not$libresoc.v:157069$8444_Y + connect \$32 $and$libresoc.v:157070$8445_Y + connect \$34 $or$libresoc.v:157071$8446_Y + connect \$36 $not$libresoc.v:157072$8447_Y + connect \$39 $and$libresoc.v:157073$8448_Y + connect \$41 $or$libresoc.v:157074$8449_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -308961,35 +327885,35 @@ module \output$100 connect \o$21 \$22 connect \oe \$19 end -attribute \src "libresoc.v:147259.1-147607.10" +attribute \src "libresoc.v:157159.1-157513.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 - attribute \src "libresoc.v:147579.3-147590.6" + attribute \src "libresoc.v:157485.3-157496.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:147260.7-147260.20" + attribute \src "libresoc.v:157160.7-157160.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147579.3-147590.6" + attribute \src "libresoc.v:157485.3-157496.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:147576.18-147576.112" - wire $and$libresoc.v:147576$8145_Y - attribute \src "libresoc.v:147572.18-147572.122" - wire $eq$libresoc.v:147572$8141_Y - attribute \src "libresoc.v:147573.18-147573.122" - wire $eq$libresoc.v:147573$8142_Y - attribute \src "libresoc.v:147571.18-147571.101" - wire width 65 $extend$libresoc.v:147571$8139_Y - attribute \src "libresoc.v:147575.18-147575.107" - wire $not$libresoc.v:147575$8144_Y - attribute \src "libresoc.v:147578.18-147578.107" - wire $not$libresoc.v:147578$8147_Y - attribute \src "libresoc.v:147577.18-147577.115" - wire $or$libresoc.v:147577$8146_Y - attribute \src "libresoc.v:147571.18-147571.101" - wire width 65 $pos$libresoc.v:147571$8140_Y - attribute \src "libresoc.v:147574.18-147574.105" - wire $reduce_or$libresoc.v:147574$8143_Y + attribute \src "libresoc.v:157482.18-157482.112" + wire $and$libresoc.v:157482$8467_Y + attribute \src "libresoc.v:157478.18-157478.122" + wire $eq$libresoc.v:157478$8463_Y + attribute \src "libresoc.v:157479.18-157479.122" + wire $eq$libresoc.v:157479$8464_Y + attribute \src "libresoc.v:157477.18-157477.101" + wire width 65 $extend$libresoc.v:157477$8461_Y + attribute \src "libresoc.v:157481.18-157481.107" + wire $not$libresoc.v:157481$8466_Y + attribute \src "libresoc.v:157484.18-157484.107" + wire $not$libresoc.v:157484$8469_Y + attribute \src "libresoc.v:157483.18-157483.115" + wire $or$libresoc.v:157483$8468_Y + attribute \src "libresoc.v:157477.18-157477.101" + wire width 65 $pos$libresoc.v:157477$8462_Y + attribute \src "libresoc.v:157480.18-157480.105" + wire $reduce_or$libresoc.v:157480$8465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" @@ -309014,7 +327938,7 @@ module \output$118 wire width 4 output 43 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \cr_a_ok - attribute \src "libresoc.v:147260.7-147260.15" + attribute \src "libresoc.v:157160.7-157160.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -309028,9 +327952,9 @@ module \output$118 wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 47 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 18 \o @@ -309043,35 +327967,39 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \o_ok$20 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \sr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -309174,6 +328102,7 @@ module \output$118 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -309250,6 +328179,7 @@ module \output$118 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -309303,7 +328233,7 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:147576$8145 + cell $and $and$libresoc.v:157482$8467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309311,10 +328241,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 - connect \Y $and$libresoc.v:147576$8145_Y + connect \Y $and$libresoc.v:157482$8467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:147572$8141 + cell $eq $eq$libresoc.v:157478$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -309322,10 +328252,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147572$8141_Y + connect \Y $eq$libresoc.v:157478$8463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:147573$8142 + cell $eq $eq$libresoc.v:157479$8464 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -309333,34 +328263,34 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:147573$8142_Y + connect \Y $eq$libresoc.v:157479$8464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:147571$8139 + cell $pos $extend$libresoc.v:157477$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:147571$8139_Y + connect \Y $extend$libresoc.v:157477$8461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:147575$8144 + cell $not $not$libresoc.v:157481$8466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:147575$8144_Y + connect \Y $not$libresoc.v:157481$8466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:147578$8147 + cell $not $not$libresoc.v:157484$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:147578$8147_Y + connect \Y $not$libresoc.v:157484$8469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:147577$8146 + cell $or $or$libresoc.v:157483$8468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309368,39 +328298,39 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:147577$8146_Y + connect \Y $or$libresoc.v:157483$8468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:147571$8140 + cell $pos $pos$libresoc.v:157477$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:147571$8139_Y - connect \Y $pos$libresoc.v:147571$8140_Y + connect \A $extend$libresoc.v:157477$8461_Y + connect \Y $pos$libresoc.v:157477$8462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:147574$8143 + cell $reduce_or $reduce_or$libresoc.v:157480$8465 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:147574$8143_Y + connect \Y $reduce_or$libresoc.v:157480$8465_Y end - attribute \src "libresoc.v:147260.7-147260.20" - process $proc$libresoc.v:147260$8149 + attribute \src "libresoc.v:157160.7-157160.20" + process $proc$libresoc.v:157160$8471 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147579.3-147590.6" - process $proc$libresoc.v:147579$8148 + attribute \src "libresoc.v:157485.3-157496.6" + process $proc$libresoc.v:157485$8470 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:147580.5-147580.29" + attribute \src "libresoc.v:157486.5-157486.29" switch \initial - attribute \src "libresoc.v:147580.9-147580.17" + attribute \src "libresoc.v:157486.9-157486.17" case 1'1 case end @@ -309418,14 +328348,14 @@ module \output$118 sync always update \cr0 $0\cr0[3:0] end - connect \$24 $pos$libresoc.v:147571$8140_Y - connect \$26 $eq$libresoc.v:147572$8141_Y - connect \$28 $eq$libresoc.v:147573$8142_Y - connect \$30 $reduce_or$libresoc.v:147574$8143_Y - connect \$32 $not$libresoc.v:147575$8144_Y - connect \$34 $and$libresoc.v:147576$8145_Y - connect \$36 $or$libresoc.v:147577$8146_Y - connect \$38 $not$libresoc.v:147578$8147_Y + connect \$24 $pos$libresoc.v:157477$8462_Y + connect \$26 $eq$libresoc.v:157478$8463_Y + connect \$28 $eq$libresoc.v:157479$8464_Y + connect \$30 $reduce_or$libresoc.v:157480$8465_Y + connect \$32 $not$libresoc.v:157481$8466_Y + connect \$34 $and$libresoc.v:157482$8467_Y + connect \$36 $or$libresoc.v:157483$8468_Y + connect \$38 $not$libresoc.v:157484$8469_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 @@ -309443,45 +328373,45 @@ module \output$118 connect \target \o$23 [63:0] connect \o$23 \$24 end -attribute \src "libresoc.v:147611.1-147972.10" +attribute \src "libresoc.v:157517.1-157884.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 - attribute \src "libresoc.v:147947.3-147958.6" + attribute \src "libresoc.v:157859.3-157870.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:147612.7-147612.20" + attribute \src "libresoc.v:157518.7-157518.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147935.3-147946.6" - wire width 65 $0\o$23[64:0]$8163 - attribute \src "libresoc.v:147947.3-147958.6" + attribute \src "libresoc.v:157847.3-157858.6" + wire width 65 $0\o$23[64:0]$8485 + attribute \src "libresoc.v:157859.3-157870.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:147935.3-147946.6" - wire width 65 $1\o$23[64:0]$8164 - attribute \src "libresoc.v:147932.18-147932.112" - wire $and$libresoc.v:147932$8159_Y - attribute \src "libresoc.v:147928.18-147928.127" - wire $eq$libresoc.v:147928$8155_Y - attribute \src "libresoc.v:147929.18-147929.127" - wire $eq$libresoc.v:147929$8156_Y - attribute \src "libresoc.v:147926.18-147926.103" - wire width 65 $extend$libresoc.v:147926$8151_Y - attribute \src "libresoc.v:147927.18-147927.101" - wire width 65 $extend$libresoc.v:147927$8153_Y - attribute \src "libresoc.v:147925.18-147925.100" - wire width 64 $not$libresoc.v:147925$8150_Y - attribute \src "libresoc.v:147931.18-147931.107" - wire $not$libresoc.v:147931$8158_Y - attribute \src "libresoc.v:147934.18-147934.107" - wire $not$libresoc.v:147934$8161_Y - attribute \src "libresoc.v:147933.18-147933.115" - wire $or$libresoc.v:147933$8160_Y - attribute \src "libresoc.v:147926.18-147926.103" - wire width 65 $pos$libresoc.v:147926$8152_Y - attribute \src "libresoc.v:147927.18-147927.101" - wire width 65 $pos$libresoc.v:147927$8154_Y - attribute \src "libresoc.v:147930.18-147930.105" - wire $reduce_or$libresoc.v:147930$8157_Y + attribute \src "libresoc.v:157847.3-157858.6" + wire width 65 $1\o$23[64:0]$8486 + attribute \src "libresoc.v:157844.18-157844.112" + wire $and$libresoc.v:157844$8481_Y + attribute \src "libresoc.v:157840.18-157840.127" + wire $eq$libresoc.v:157840$8477_Y + attribute \src "libresoc.v:157841.18-157841.127" + wire $eq$libresoc.v:157841$8478_Y + attribute \src "libresoc.v:157838.18-157838.103" + wire width 65 $extend$libresoc.v:157838$8473_Y + attribute \src "libresoc.v:157839.18-157839.101" + wire width 65 $extend$libresoc.v:157839$8475_Y + attribute \src "libresoc.v:157837.18-157837.100" + wire width 64 $not$libresoc.v:157837$8472_Y + attribute \src "libresoc.v:157843.18-157843.107" + wire $not$libresoc.v:157843$8480_Y + attribute \src "libresoc.v:157846.18-157846.107" + wire $not$libresoc.v:157846$8483_Y + attribute \src "libresoc.v:157845.18-157845.115" + wire $or$libresoc.v:157845$8482_Y + attribute \src "libresoc.v:157838.18-157838.103" + wire width 65 $pos$libresoc.v:157838$8474_Y + attribute \src "libresoc.v:157839.18-157839.101" + wire width 65 $pos$libresoc.v:157839$8476_Y + attribute \src "libresoc.v:157842.18-157842.105" + wire $reduce_or$libresoc.v:157842$8479_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -309510,7 +328440,7 @@ module \output$54 wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \cr_a_ok - attribute \src "libresoc.v:147612.7-147612.15" + attribute \src "libresoc.v:157518.7-157518.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -309527,35 +328457,39 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -309654,6 +328588,7 @@ module \output$54 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -309730,6 +328665,7 @@ module \output$54 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -309778,9 +328714,9 @@ module \output$54 wire output 33 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 19 \o @@ -309797,7 +328733,7 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:147932$8159 + cell $and $and$libresoc.v:157844$8481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309805,10 +328741,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:147932$8159_Y + connect \Y $and$libresoc.v:157844$8481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:147928$8155 + cell $eq $eq$libresoc.v:157840$8477 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -309816,10 +328752,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147928$8155_Y + connect \Y $eq$libresoc.v:157840$8477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:147929$8156 + cell $eq $eq$libresoc.v:157841$8478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -309827,50 +328763,50 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:147929$8156_Y + connect \Y $eq$libresoc.v:157841$8478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:147926$8151 + cell $pos $extend$libresoc.v:157838$8473 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:147926$8151_Y + connect \Y $extend$libresoc.v:157838$8473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:147927$8153 + cell $pos $extend$libresoc.v:157839$8475 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:147927$8153_Y + connect \Y $extend$libresoc.v:157839$8475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:147925$8150 + cell $not $not$libresoc.v:157837$8472 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:147925$8150_Y + connect \Y $not$libresoc.v:157837$8472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:147931$8158 + cell $not $not$libresoc.v:157843$8480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:147931$8158_Y + connect \Y $not$libresoc.v:157843$8480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:147934$8161 + cell $not $not$libresoc.v:157846$8483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:147934$8161_Y + connect \Y $not$libresoc.v:157846$8483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:147933$8160 + cell $or $or$libresoc.v:157845$8482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309878,47 +328814,47 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:147933$8160_Y + connect \Y $or$libresoc.v:157845$8482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:147926$8152 + cell $pos $pos$libresoc.v:157838$8474 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:147926$8151_Y - connect \Y $pos$libresoc.v:147926$8152_Y + connect \A $extend$libresoc.v:157838$8473_Y + connect \Y $pos$libresoc.v:157838$8474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:147927$8154 + cell $pos $pos$libresoc.v:157839$8476 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:147927$8153_Y - connect \Y $pos$libresoc.v:147927$8154_Y + connect \A $extend$libresoc.v:157839$8475_Y + connect \Y $pos$libresoc.v:157839$8476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:147930$8157 + cell $reduce_or $reduce_or$libresoc.v:157842$8479 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:147930$8157_Y + connect \Y $reduce_or$libresoc.v:157842$8479_Y end - attribute \src "libresoc.v:147612.7-147612.20" - process $proc$libresoc.v:147612$8166 + attribute \src "libresoc.v:157518.7-157518.20" + process $proc$libresoc.v:157518$8488 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147935.3-147946.6" - process $proc$libresoc.v:147935$8162 + attribute \src "libresoc.v:157847.3-157858.6" + process $proc$libresoc.v:157847$8484 assign { } { } - assign $0\o$23[64:0]$8163 $1\o$23[64:0]$8164 - attribute \src "libresoc.v:147936.5-147936.29" + assign $0\o$23[64:0]$8485 $1\o$23[64:0]$8486 + attribute \src "libresoc.v:157848.5-157848.29" switch \initial - attribute \src "libresoc.v:147936.9-147936.17" + attribute \src "libresoc.v:157848.9-157848.17" case 1'1 case end @@ -309927,22 +328863,22 @@ module \output$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$23[64:0]$8164 \$24 + assign $1\o$23[64:0]$8486 \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$23[64:0]$8164 \$28 + assign $1\o$23[64:0]$8486 \$28 end sync always - update \o$23 $0\o$23[64:0]$8163 + update \o$23 $0\o$23[64:0]$8485 end - attribute \src "libresoc.v:147947.3-147958.6" - process $proc$libresoc.v:147947$8165 + attribute \src "libresoc.v:157859.3-157870.6" + process $proc$libresoc.v:157859$8487 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:147948.5-147948.29" + attribute \src "libresoc.v:157860.5-157860.29" switch \initial - attribute \src "libresoc.v:147948.9-147948.17" + attribute \src "libresoc.v:157860.9-157860.17" case 1'1 case end @@ -309960,16 +328896,16 @@ module \output$54 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:147925$8150_Y - connect \$24 $pos$libresoc.v:147926$8152_Y - connect \$28 $pos$libresoc.v:147927$8154_Y - connect \$30 $eq$libresoc.v:147928$8155_Y - connect \$32 $eq$libresoc.v:147929$8156_Y - connect \$34 $reduce_or$libresoc.v:147930$8157_Y - connect \$36 $not$libresoc.v:147931$8158_Y - connect \$38 $and$libresoc.v:147932$8159_Y - connect \$40 $or$libresoc.v:147933$8160_Y - connect \$42 $not$libresoc.v:147934$8161_Y + connect \$25 $not$libresoc.v:157837$8472_Y + connect \$24 $pos$libresoc.v:157838$8474_Y + connect \$28 $pos$libresoc.v:157839$8476_Y + connect \$30 $eq$libresoc.v:157840$8477_Y + connect \$32 $eq$libresoc.v:157841$8478_Y + connect \$34 $reduce_or$libresoc.v:157842$8479_Y + connect \$36 $not$libresoc.v:157843$8480_Y + connect \$38 $and$libresoc.v:157844$8481_Y + connect \$40 $or$libresoc.v:157845$8482_Y + connect \$42 $not$libresoc.v:157846$8483_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -309984,71 +328920,71 @@ module \output$54 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:147976.1-148420.10" +attribute \src "libresoc.v:157888.1-158338.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 - attribute \src "libresoc.v:148341.3-148352.6" + attribute \src "libresoc.v:158259.3-158270.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:147977.7-147977.20" + attribute \src "libresoc.v:157889.7-157889.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148353.3-148364.6" - wire width 65 $0\o$27[64:0]$8185 - attribute \src "libresoc.v:148329.3-148340.6" + attribute \src "libresoc.v:158271.3-158282.6" + wire width 65 $0\o$27[64:0]$8507 + attribute \src "libresoc.v:158247.3-158258.6" wire $0\so[0:0] - attribute \src "libresoc.v:148385.3-148394.6" - wire width 2 $0\xer_ov$23[1:0]$8192 - attribute \src "libresoc.v:148395.3-148404.6" + attribute \src "libresoc.v:158303.3-158312.6" + wire width 2 $0\xer_ov$23[1:0]$8514 + attribute \src "libresoc.v:158313.3-158322.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:148365.3-148374.6" - wire $0\xer_so$24[0:0]$8188 - attribute \src "libresoc.v:148375.3-148384.6" + attribute \src "libresoc.v:158283.3-158292.6" + wire $0\xer_so$24[0:0]$8510 + attribute \src "libresoc.v:158293.3-158302.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:148341.3-148352.6" + attribute \src "libresoc.v:158259.3-158270.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:148353.3-148364.6" - wire width 65 $1\o$27[64:0]$8186 - attribute \src "libresoc.v:148329.3-148340.6" + attribute \src "libresoc.v:158271.3-158282.6" + wire width 65 $1\o$27[64:0]$8508 + attribute \src "libresoc.v:158247.3-158258.6" wire $1\so[0:0] - attribute \src "libresoc.v:148385.3-148394.6" - wire width 2 $1\xer_ov$23[1:0]$8193 - attribute \src "libresoc.v:148395.3-148404.6" + attribute \src "libresoc.v:158303.3-158312.6" + wire width 2 $1\xer_ov$23[1:0]$8515 + attribute \src "libresoc.v:158313.3-158322.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:148365.3-148374.6" - wire $1\xer_so$24[0:0]$8189 - attribute \src "libresoc.v:148375.3-148384.6" + attribute \src "libresoc.v:158283.3-158292.6" + wire $1\xer_so$24[0:0]$8511 + attribute \src "libresoc.v:158293.3-158302.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:148316.18-148316.136" - wire $and$libresoc.v:148316$8167_Y - attribute \src "libresoc.v:148324.18-148324.112" - wire $and$libresoc.v:148324$8177_Y - attribute \src "libresoc.v:148327.18-148327.133" - wire $and$libresoc.v:148327$8180_Y - attribute \src "libresoc.v:148320.18-148320.127" - wire $eq$libresoc.v:148320$8173_Y - attribute \src "libresoc.v:148321.18-148321.127" - wire $eq$libresoc.v:148321$8174_Y - attribute \src "libresoc.v:148318.18-148318.103" - wire width 65 $extend$libresoc.v:148318$8169_Y - attribute \src "libresoc.v:148319.18-148319.101" - wire width 65 $extend$libresoc.v:148319$8171_Y - attribute \src "libresoc.v:148317.18-148317.100" - wire width 64 $not$libresoc.v:148317$8168_Y - attribute \src "libresoc.v:148323.18-148323.107" - wire $not$libresoc.v:148323$8176_Y - attribute \src "libresoc.v:148326.18-148326.107" - wire $not$libresoc.v:148326$8179_Y - attribute \src "libresoc.v:148325.18-148325.115" - wire $or$libresoc.v:148325$8178_Y - attribute \src "libresoc.v:148328.18-148328.112" - wire $or$libresoc.v:148328$8181_Y - attribute \src "libresoc.v:148318.18-148318.103" - wire width 65 $pos$libresoc.v:148318$8170_Y - attribute \src "libresoc.v:148319.18-148319.101" - wire width 65 $pos$libresoc.v:148319$8172_Y - attribute \src "libresoc.v:148322.18-148322.105" - wire $reduce_or$libresoc.v:148322$8175_Y + attribute \src "libresoc.v:158234.18-158234.136" + wire $and$libresoc.v:158234$8489_Y + attribute \src "libresoc.v:158242.18-158242.112" + wire $and$libresoc.v:158242$8499_Y + attribute \src "libresoc.v:158245.18-158245.133" + wire $and$libresoc.v:158245$8502_Y + attribute \src "libresoc.v:158238.18-158238.127" + wire $eq$libresoc.v:158238$8495_Y + attribute \src "libresoc.v:158239.18-158239.127" + wire $eq$libresoc.v:158239$8496_Y + attribute \src "libresoc.v:158236.18-158236.103" + wire width 65 $extend$libresoc.v:158236$8491_Y + attribute \src "libresoc.v:158237.18-158237.101" + wire width 65 $extend$libresoc.v:158237$8493_Y + attribute \src "libresoc.v:158235.18-158235.100" + wire width 64 $not$libresoc.v:158235$8490_Y + attribute \src "libresoc.v:158241.18-158241.107" + wire $not$libresoc.v:158241$8498_Y + attribute \src "libresoc.v:158244.18-158244.107" + wire $not$libresoc.v:158244$8501_Y + attribute \src "libresoc.v:158243.18-158243.115" + wire $or$libresoc.v:158243$8500_Y + attribute \src "libresoc.v:158246.18-158246.112" + wire $or$libresoc.v:158246$8503_Y + attribute \src "libresoc.v:158236.18-158236.103" + wire width 65 $pos$libresoc.v:158236$8492_Y + attribute \src "libresoc.v:158237.18-158237.101" + wire width 65 $pos$libresoc.v:158237$8494_Y + attribute \src "libresoc.v:158240.18-158240.105" + wire $reduce_or$libresoc.v:158240$8497_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -310083,7 +329019,7 @@ module \output$83 wire width 4 output 45 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \cr_a_ok - attribute \src "libresoc.v:147977.7-147977.15" + attribute \src "libresoc.v:157889.7-157889.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -310100,35 +329036,39 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 41 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 26 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 26 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -310227,6 +329167,7 @@ module \output$83 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -310303,6 +329244,7 @@ module \output$83 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 25 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -310351,9 +329293,9 @@ module \output$83 wire output 34 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 24 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 19 \o @@ -310386,7 +329328,7 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:148316$8167 + cell $and $and$libresoc.v:158234$8489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310394,10 +329336,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:148316$8167_Y + connect \Y $and$libresoc.v:158234$8489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:148324$8177 + cell $and $and$libresoc.v:158242$8499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310405,10 +329347,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:148324$8177_Y + connect \Y $and$libresoc.v:158242$8499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:148327$8180 + cell $and $and$libresoc.v:158245$8502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310416,10 +329358,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:148327$8180_Y + connect \Y $and$libresoc.v:158245$8502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:148320$8173 + cell $eq $eq$libresoc.v:158238$8495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -310427,10 +329369,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:148320$8173_Y + connect \Y $eq$libresoc.v:158238$8495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:148321$8174 + cell $eq $eq$libresoc.v:158239$8496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -310438,50 +329380,50 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:148321$8174_Y + connect \Y $eq$libresoc.v:158239$8496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:148318$8169 + cell $pos $extend$libresoc.v:158236$8491 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:148318$8169_Y + connect \Y $extend$libresoc.v:158236$8491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:148319$8171 + cell $pos $extend$libresoc.v:158237$8493 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:148319$8171_Y + connect \Y $extend$libresoc.v:158237$8493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:148317$8168 + cell $not $not$libresoc.v:158235$8490 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:148317$8168_Y + connect \Y $not$libresoc.v:158235$8490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:148323$8176 + cell $not $not$libresoc.v:158241$8498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:148323$8176_Y + connect \Y $not$libresoc.v:158241$8498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:148326$8179 + cell $not $not$libresoc.v:158244$8501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:148326$8179_Y + connect \Y $not$libresoc.v:158244$8501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:148325$8178 + cell $or $or$libresoc.v:158243$8500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310489,10 +329431,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:148325$8178_Y + connect \Y $or$libresoc.v:158243$8500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:148328$8181 + cell $or $or$libresoc.v:158246$8503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310500,47 +329442,47 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:148328$8181_Y + connect \Y $or$libresoc.v:158246$8503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:148318$8170 + cell $pos $pos$libresoc.v:158236$8492 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:148318$8169_Y - connect \Y $pos$libresoc.v:148318$8170_Y + connect \A $extend$libresoc.v:158236$8491_Y + connect \Y $pos$libresoc.v:158236$8492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:148319$8172 + cell $pos $pos$libresoc.v:158237$8494 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:148319$8171_Y - connect \Y $pos$libresoc.v:148319$8172_Y + connect \A $extend$libresoc.v:158237$8493_Y + connect \Y $pos$libresoc.v:158237$8494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:148322$8175 + cell $reduce_or $reduce_or$libresoc.v:158240$8497 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:148322$8175_Y + connect \Y $reduce_or$libresoc.v:158240$8497_Y end - attribute \src "libresoc.v:147977.7-147977.20" - process $proc$libresoc.v:147977$8195 + attribute \src "libresoc.v:157889.7-157889.20" + process $proc$libresoc.v:157889$8517 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148329.3-148340.6" - process $proc$libresoc.v:148329$8182 + attribute \src "libresoc.v:158247.3-158258.6" + process $proc$libresoc.v:158247$8504 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:148330.5-148330.29" + attribute \src "libresoc.v:158248.5-158248.29" switch \initial - attribute \src "libresoc.v:148330.9-148330.17" + attribute \src "libresoc.v:158248.9-158248.17" case 1'1 case end @@ -310558,13 +329500,13 @@ module \output$83 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:148341.3-148352.6" - process $proc$libresoc.v:148341$8183 + attribute \src "libresoc.v:158259.3-158270.6" + process $proc$libresoc.v:158259$8505 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:148342.5-148342.29" + attribute \src "libresoc.v:158260.5-158260.29" switch \initial - attribute \src "libresoc.v:148342.9-148342.17" + attribute \src "libresoc.v:158260.9-158260.17" case 1'1 case end @@ -310582,13 +329524,13 @@ module \output$83 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:148353.3-148364.6" - process $proc$libresoc.v:148353$8184 + attribute \src "libresoc.v:158271.3-158282.6" + process $proc$libresoc.v:158271$8506 assign { } { } - assign $0\o$27[64:0]$8185 $1\o$27[64:0]$8186 - attribute \src "libresoc.v:148354.5-148354.29" + assign $0\o$27[64:0]$8507 $1\o$27[64:0]$8508 + attribute \src "libresoc.v:158272.5-158272.29" switch \initial - attribute \src "libresoc.v:148354.9-148354.17" + attribute \src "libresoc.v:158272.9-158272.17" case 1'1 case end @@ -310597,23 +329539,23 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$27[64:0]$8186 \$28 + assign $1\o$27[64:0]$8508 \$28 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$27[64:0]$8186 \$32 + assign $1\o$27[64:0]$8508 \$32 end sync always - update \o$27 $0\o$27[64:0]$8185 + update \o$27 $0\o$27[64:0]$8507 end - attribute \src "libresoc.v:148365.3-148374.6" - process $proc$libresoc.v:148365$8187 + attribute \src "libresoc.v:158283.3-158292.6" + process $proc$libresoc.v:158283$8509 assign { } { } assign { } { } - assign $0\xer_so$24[0:0]$8188 $1\xer_so$24[0:0]$8189 - attribute \src "libresoc.v:148366.5-148366.29" + assign $0\xer_so$24[0:0]$8510 $1\xer_so$24[0:0]$8511 + attribute \src "libresoc.v:158284.5-158284.29" switch \initial - attribute \src "libresoc.v:148366.9-148366.17" + attribute \src "libresoc.v:158284.9-158284.17" case 1'1 case end @@ -310622,21 +329564,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$24[0:0]$8189 \$51 + assign $1\xer_so$24[0:0]$8511 \$51 case - assign $1\xer_so$24[0:0]$8189 1'0 + assign $1\xer_so$24[0:0]$8511 1'0 end sync always - update \xer_so$24 $0\xer_so$24[0:0]$8188 + update \xer_so$24 $0\xer_so$24[0:0]$8510 end - attribute \src "libresoc.v:148375.3-148384.6" - process $proc$libresoc.v:148375$8190 + attribute \src "libresoc.v:158293.3-158302.6" + process $proc$libresoc.v:158293$8512 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:148376.5-148376.29" + attribute \src "libresoc.v:158294.5-158294.29" switch \initial - attribute \src "libresoc.v:148376.9-148376.17" + attribute \src "libresoc.v:158294.9-158294.17" case 1'1 case end @@ -310652,14 +329594,14 @@ module \output$83 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:148385.3-148394.6" - process $proc$libresoc.v:148385$8191 + attribute \src "libresoc.v:158303.3-158312.6" + process $proc$libresoc.v:158303$8513 assign { } { } assign { } { } - assign $0\xer_ov$23[1:0]$8192 $1\xer_ov$23[1:0]$8193 - attribute \src "libresoc.v:148386.5-148386.29" + assign $0\xer_ov$23[1:0]$8514 $1\xer_ov$23[1:0]$8515 + attribute \src "libresoc.v:158304.5-158304.29" switch \initial - attribute \src "libresoc.v:148386.9-148386.17" + attribute \src "libresoc.v:158304.9-158304.17" case 1'1 case end @@ -310668,21 +329610,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$23[1:0]$8193 \xer_ov + assign $1\xer_ov$23[1:0]$8515 \xer_ov case - assign $1\xer_ov$23[1:0]$8193 2'00 + assign $1\xer_ov$23[1:0]$8515 2'00 end sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$8192 + update \xer_ov$23 $0\xer_ov$23[1:0]$8514 end - attribute \src "libresoc.v:148395.3-148404.6" - process $proc$libresoc.v:148395$8194 + attribute \src "libresoc.v:158313.3-158322.6" + process $proc$libresoc.v:158313$8516 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:148396.5-148396.29" + attribute \src "libresoc.v:158314.5-158314.29" switch \initial - attribute \src "libresoc.v:148396.9-148396.17" + attribute \src "libresoc.v:158314.9-158314.17" case 1'1 case end @@ -310698,19 +329640,19 @@ module \output$83 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:148316$8167_Y - connect \$29 $not$libresoc.v:148317$8168_Y - connect \$28 $pos$libresoc.v:148318$8170_Y - connect \$32 $pos$libresoc.v:148319$8172_Y - connect \$34 $eq$libresoc.v:148320$8173_Y - connect \$36 $eq$libresoc.v:148321$8174_Y - connect \$38 $reduce_or$libresoc.v:148322$8175_Y - connect \$40 $not$libresoc.v:148323$8176_Y - connect \$42 $and$libresoc.v:148324$8177_Y - connect \$44 $or$libresoc.v:148325$8178_Y - connect \$46 $not$libresoc.v:148326$8179_Y - connect \$49 $and$libresoc.v:148327$8180_Y - connect \$51 $or$libresoc.v:148328$8181_Y + connect \$25 $and$libresoc.v:158234$8489_Y + connect \$29 $not$libresoc.v:158235$8490_Y + connect \$28 $pos$libresoc.v:158236$8492_Y + connect \$32 $pos$libresoc.v:158237$8494_Y + connect \$34 $eq$libresoc.v:158238$8495_Y + connect \$36 $eq$libresoc.v:158239$8496_Y + connect \$38 $reduce_or$libresoc.v:158240$8497_Y + connect \$40 $not$libresoc.v:158241$8498_Y + connect \$42 $and$libresoc.v:158242$8499_Y + connect \$44 $or$libresoc.v:158243$8500_Y + connect \$46 $not$libresoc.v:158244$8501_Y + connect \$49 $and$libresoc.v:158245$8502_Y + connect \$51 $or$libresoc.v:158246$8503_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -310727,93 +329669,93 @@ module \output$83 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:148424.1-148900.10" +attribute \src "libresoc.v:158342.1-158824.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage - attribute \src "libresoc.v:148425.7-148425.20" + attribute \src "libresoc.v:158343.7-158343.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:148853.3-148886.6" + attribute \src "libresoc.v:158777.3-158810.6" wire $0\ov[0:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:148853.3-148886.6" + attribute \src "libresoc.v:158777.3-158810.6" wire $1\ov[0:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:148853.3-148886.6" + attribute \src "libresoc.v:158777.3-158810.6" wire $2\ov[0:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:148853.3-148886.6" + attribute \src "libresoc.v:158777.3-158810.6" wire $3\ov[0:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $5\o[63:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:148781.3-148852.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:148772.18-148772.122" - wire $and$libresoc.v:148772$8209_Y - attribute \src "libresoc.v:148764.18-148764.109" - wire width 65 $extend$libresoc.v:148764$8197_Y - attribute \src "libresoc.v:148765.18-148765.100" - wire width 65 $extend$libresoc.v:148765$8199_Y - attribute \src "libresoc.v:148767.18-148767.113" - wire width 65 $extend$libresoc.v:148767$8202_Y - attribute \src "libresoc.v:148768.18-148768.104" - wire width 65 $extend$libresoc.v:148768$8204_Y - attribute \src "libresoc.v:148776.18-148776.114" - wire width 64 $extend$libresoc.v:148776$8213_Y - attribute \src "libresoc.v:148777.18-148777.114" - wire width 64 $extend$libresoc.v:148777$8215_Y - attribute \src "libresoc.v:148778.18-148778.114" - wire width 64 $extend$libresoc.v:148778$8217_Y - attribute \src "libresoc.v:148779.18-148779.114" - wire width 64 $extend$libresoc.v:148779$8219_Y - attribute \src "libresoc.v:148780.18-148780.115" - wire width 64 $extend$libresoc.v:148780$8221_Y - attribute \src "libresoc.v:148773.18-148773.128" - wire $ne$libresoc.v:148773$8210_Y - attribute \src "libresoc.v:148764.18-148764.109" - wire width 65 $neg$libresoc.v:148764$8198_Y - attribute \src "libresoc.v:148767.18-148767.113" - wire width 65 $neg$libresoc.v:148767$8203_Y - attribute \src "libresoc.v:148770.18-148770.116" - wire $not$libresoc.v:148770$8207_Y - attribute \src "libresoc.v:148775.18-148775.99" - wire $not$libresoc.v:148775$8212_Y - attribute \src "libresoc.v:148765.18-148765.100" - wire width 65 $pos$libresoc.v:148765$8200_Y - attribute \src "libresoc.v:148768.18-148768.104" - wire width 65 $pos$libresoc.v:148768$8205_Y - attribute \src "libresoc.v:148774.18-148774.118" - wire width 64 $pos$libresoc.v:148774$8211_Y - attribute \src "libresoc.v:148776.18-148776.114" - wire width 64 $pos$libresoc.v:148776$8214_Y - attribute \src "libresoc.v:148777.18-148777.114" - wire width 64 $pos$libresoc.v:148777$8216_Y - attribute \src "libresoc.v:148778.18-148778.114" - wire width 64 $pos$libresoc.v:148778$8218_Y - attribute \src "libresoc.v:148779.18-148779.114" - wire width 64 $pos$libresoc.v:148779$8220_Y - attribute \src "libresoc.v:148780.18-148780.115" - wire width 64 $pos$libresoc.v:148780$8222_Y - attribute \src "libresoc.v:148766.18-148766.121" - wire width 65 $ternary$libresoc.v:148766$8201_Y - attribute \src "libresoc.v:148769.18-148769.122" - wire width 65 $ternary$libresoc.v:148769$8206_Y - attribute \src "libresoc.v:148763.18-148763.120" - wire $xor$libresoc.v:148763$8196_Y - attribute \src "libresoc.v:148771.18-148771.127" - wire $xor$libresoc.v:148771$8208_Y + attribute \src "libresoc.v:158696.18-158696.122" + wire $and$libresoc.v:158696$8531_Y + attribute \src "libresoc.v:158688.18-158688.109" + wire width 65 $extend$libresoc.v:158688$8519_Y + attribute \src "libresoc.v:158689.18-158689.100" + wire width 65 $extend$libresoc.v:158689$8521_Y + attribute \src "libresoc.v:158691.18-158691.113" + wire width 65 $extend$libresoc.v:158691$8524_Y + attribute \src "libresoc.v:158692.18-158692.104" + wire width 65 $extend$libresoc.v:158692$8526_Y + attribute \src "libresoc.v:158700.18-158700.114" + wire width 64 $extend$libresoc.v:158700$8535_Y + attribute \src "libresoc.v:158701.18-158701.114" + wire width 64 $extend$libresoc.v:158701$8537_Y + attribute \src "libresoc.v:158702.18-158702.114" + wire width 64 $extend$libresoc.v:158702$8539_Y + attribute \src "libresoc.v:158703.18-158703.114" + wire width 64 $extend$libresoc.v:158703$8541_Y + attribute \src "libresoc.v:158704.18-158704.115" + wire width 64 $extend$libresoc.v:158704$8543_Y + attribute \src "libresoc.v:158697.18-158697.128" + wire $ne$libresoc.v:158697$8532_Y + attribute \src "libresoc.v:158688.18-158688.109" + wire width 65 $neg$libresoc.v:158688$8520_Y + attribute \src "libresoc.v:158691.18-158691.113" + wire width 65 $neg$libresoc.v:158691$8525_Y + attribute \src "libresoc.v:158694.18-158694.116" + wire $not$libresoc.v:158694$8529_Y + attribute \src "libresoc.v:158699.18-158699.99" + wire $not$libresoc.v:158699$8534_Y + attribute \src "libresoc.v:158689.18-158689.100" + wire width 65 $pos$libresoc.v:158689$8522_Y + attribute \src "libresoc.v:158692.18-158692.104" + wire width 65 $pos$libresoc.v:158692$8527_Y + attribute \src "libresoc.v:158698.18-158698.118" + wire width 64 $pos$libresoc.v:158698$8533_Y + attribute \src "libresoc.v:158700.18-158700.114" + wire width 64 $pos$libresoc.v:158700$8536_Y + attribute \src "libresoc.v:158701.18-158701.114" + wire width 64 $pos$libresoc.v:158701$8538_Y + attribute \src "libresoc.v:158702.18-158702.114" + wire width 64 $pos$libresoc.v:158702$8540_Y + attribute \src "libresoc.v:158703.18-158703.114" + wire width 64 $pos$libresoc.v:158703$8542_Y + attribute \src "libresoc.v:158704.18-158704.115" + wire width 64 $pos$libresoc.v:158704$8544_Y + attribute \src "libresoc.v:158690.18-158690.121" + wire width 65 $ternary$libresoc.v:158690$8523_Y + attribute \src "libresoc.v:158693.18-158693.122" + wire width 65 $ternary$libresoc.v:158693$8528_Y + attribute \src "libresoc.v:158687.18-158687.120" + wire $xor$libresoc.v:158687$8518_Y + attribute \src "libresoc.v:158695.18-158695.127" + wire $xor$libresoc.v:158695$8530_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -310862,42 +329804,46 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:148425.7-148425.15" + attribute \src "libresoc.v:158343.7-158343.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 44 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 29 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 29 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -310996,6 +329942,7 @@ module \output_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -311072,6 +330019,7 @@ module \output_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 28 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -311118,9 +330066,9 @@ module \output_stage wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 27 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 46 \o @@ -311153,7 +330101,7 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:148772$8209 + cell $and $and$libresoc.v:158696$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311161,82 +330109,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:148772$8209_Y + connect \Y $and$libresoc.v:158696$8531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:148764$8197 + cell $pos $extend$libresoc.v:158688$8519 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:148764$8197_Y + connect \Y $extend$libresoc.v:158688$8519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:148765$8199 + cell $pos $extend$libresoc.v:158689$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:148765$8199_Y + connect \Y $extend$libresoc.v:158689$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:148767$8202 + cell $pos $extend$libresoc.v:158691$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:148767$8202_Y + connect \Y $extend$libresoc.v:158691$8524_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:148768$8204 + cell $pos $extend$libresoc.v:158692$8526 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:148768$8204_Y + connect \Y $extend$libresoc.v:158692$8526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:148776$8213 + cell $pos $extend$libresoc.v:158700$8535 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:148776$8213_Y + connect \Y $extend$libresoc.v:158700$8535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:148777$8215 + cell $pos $extend$libresoc.v:158701$8537 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:148777$8215_Y + connect \Y $extend$libresoc.v:158701$8537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:148778$8217 + cell $pos $extend$libresoc.v:158702$8539 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:148778$8217_Y + connect \Y $extend$libresoc.v:158702$8539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:148779$8219 + cell $pos $extend$libresoc.v:158703$8541 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:148779$8219_Y + connect \Y $extend$libresoc.v:158703$8541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:148780$8221 + cell $pos $extend$libresoc.v:158704$8543 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:148780$8221_Y + connect \Y $extend$libresoc.v:158704$8543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:148773$8210 + cell $ne $ne$libresoc.v:158697$8532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311244,122 +330192,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:148773$8210_Y + connect \Y $ne$libresoc.v:158697$8532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:148764$8198 + cell $neg $neg$libresoc.v:158688$8520 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:148764$8197_Y - connect \Y $neg$libresoc.v:148764$8198_Y + connect \A $extend$libresoc.v:158688$8519_Y + connect \Y $neg$libresoc.v:158688$8520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:148767$8203 + cell $neg $neg$libresoc.v:158691$8525 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:148767$8202_Y - connect \Y $neg$libresoc.v:148767$8203_Y + connect \A $extend$libresoc.v:158691$8524_Y + connect \Y $neg$libresoc.v:158691$8525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:148770$8207 + cell $not $not$libresoc.v:158694$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:148770$8207_Y + connect \Y $not$libresoc.v:158694$8529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:148775$8212 + cell $not $not$libresoc.v:158699$8534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:148775$8212_Y + connect \Y $not$libresoc.v:158699$8534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:148765$8200 + cell $pos $pos$libresoc.v:158689$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:148765$8199_Y - connect \Y $pos$libresoc.v:148765$8200_Y + connect \A $extend$libresoc.v:158689$8521_Y + connect \Y $pos$libresoc.v:158689$8522_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:148768$8205 + cell $pos $pos$libresoc.v:158692$8527 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:148768$8204_Y - connect \Y $pos$libresoc.v:148768$8205_Y + connect \A $extend$libresoc.v:158692$8526_Y + connect \Y $pos$libresoc.v:158692$8527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:148774$8211 + cell $pos $pos$libresoc.v:158698$8533 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:148774$8211_Y + connect \Y $pos$libresoc.v:158698$8533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:148776$8214 + cell $pos $pos$libresoc.v:158700$8536 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148776$8213_Y - connect \Y $pos$libresoc.v:148776$8214_Y + connect \A $extend$libresoc.v:158700$8535_Y + connect \Y $pos$libresoc.v:158700$8536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:148777$8216 + cell $pos $pos$libresoc.v:158701$8538 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148777$8215_Y - connect \Y $pos$libresoc.v:148777$8216_Y + connect \A $extend$libresoc.v:158701$8537_Y + connect \Y $pos$libresoc.v:158701$8538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:148778$8218 + cell $pos $pos$libresoc.v:158702$8540 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148778$8217_Y - connect \Y $pos$libresoc.v:148778$8218_Y + connect \A $extend$libresoc.v:158702$8539_Y + connect \Y $pos$libresoc.v:158702$8540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:148779$8220 + cell $pos $pos$libresoc.v:158703$8542 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148779$8219_Y - connect \Y $pos$libresoc.v:148779$8220_Y + connect \A $extend$libresoc.v:158703$8541_Y + connect \Y $pos$libresoc.v:158703$8542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:148780$8222 + cell $pos $pos$libresoc.v:158704$8544 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148780$8221_Y - connect \Y $pos$libresoc.v:148780$8222_Y + connect \A $extend$libresoc.v:158704$8543_Y + connect \Y $pos$libresoc.v:158704$8544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:148766$8201 + cell $mux $ternary$libresoc.v:158690$8523 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:148766$8201_Y + connect \Y $ternary$libresoc.v:158690$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:148769$8206 + cell $mux $ternary$libresoc.v:158693$8528 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:148769$8206_Y + connect \Y $ternary$libresoc.v:158693$8528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:148763$8196 + cell $xor $xor$libresoc.v:158687$8518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311367,10 +330315,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:148763$8196_Y + connect \Y $xor$libresoc.v:158687$8518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:148771$8208 + cell $xor $xor$libresoc.v:158695$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311378,24 +330326,24 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:148771$8208_Y + connect \Y $xor$libresoc.v:158695$8530_Y end - attribute \src "libresoc.v:148425.7-148425.20" - process $proc$libresoc.v:148425$8225 + attribute \src "libresoc.v:158343.7-158343.20" + process $proc$libresoc.v:158343$8547 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148781.3-148852.6" - process $proc$libresoc.v:148781$8223 + attribute \src "libresoc.v:158705.3-158776.6" + process $proc$libresoc.v:158705$8545 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:148782.5-148782.29" + attribute \src "libresoc.v:158706.5-158706.29" switch \initial - attribute \src "libresoc.v:148782.9-148782.17" + attribute \src "libresoc.v:158706.9-158706.17" case 1'1 case end @@ -311494,13 +330442,13 @@ module \output_stage sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:148853.3-148886.6" - process $proc$libresoc.v:148853$8224 + attribute \src "libresoc.v:158777.3-158810.6" + process $proc$libresoc.v:158777$8546 assign { } { } assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:148854.5-148854.29" + attribute \src "libresoc.v:158778.5-158778.29" switch \initial - attribute \src "libresoc.v:148854.9-148854.17" + attribute \src "libresoc.v:158778.9-158778.17" case 1'1 case end @@ -311546,24 +330494,24 @@ module \output_stage sync always update \ov $0\ov[0:0] end - connect \$21 $xor$libresoc.v:148763$8196_Y - connect \$23 $neg$libresoc.v:148764$8198_Y - connect \$25 $pos$libresoc.v:148765$8200_Y - connect \$27 $ternary$libresoc.v:148766$8201_Y - connect \$30 $neg$libresoc.v:148767$8203_Y - connect \$32 $pos$libresoc.v:148768$8205_Y - connect \$34 $ternary$libresoc.v:148769$8206_Y - connect \$36 $not$libresoc.v:148770$8207_Y - connect \$38 $xor$libresoc.v:148771$8208_Y - connect \$40 $and$libresoc.v:148772$8209_Y - connect \$42 $ne$libresoc.v:148773$8210_Y - connect \$44 $pos$libresoc.v:148774$8211_Y - connect \$46 $not$libresoc.v:148775$8212_Y - connect \$48 $pos$libresoc.v:148776$8214_Y - connect \$50 $pos$libresoc.v:148777$8216_Y - connect \$52 $pos$libresoc.v:148778$8218_Y - connect \$54 $pos$libresoc.v:148779$8220_Y - connect \$56 $pos$libresoc.v:148780$8222_Y + connect \$21 $xor$libresoc.v:158687$8518_Y + connect \$23 $neg$libresoc.v:158688$8520_Y + connect \$25 $pos$libresoc.v:158689$8522_Y + connect \$27 $ternary$libresoc.v:158690$8523_Y + connect \$30 $neg$libresoc.v:158691$8525_Y + connect \$32 $pos$libresoc.v:158692$8527_Y + connect \$34 $ternary$libresoc.v:158693$8528_Y + connect \$36 $not$libresoc.v:158694$8529_Y + connect \$38 $xor$libresoc.v:158695$8530_Y + connect \$40 $and$libresoc.v:158696$8531_Y + connect \$42 $ne$libresoc.v:158697$8532_Y + connect \$44 $pos$libresoc.v:158698$8533_Y + connect \$46 $not$libresoc.v:158699$8534_Y + connect \$48 $pos$libresoc.v:158700$8536_Y + connect \$50 $pos$libresoc.v:158701$8538_Y + connect \$52 $pos$libresoc.v:158702$8540_Y + connect \$54 $pos$libresoc.v:158703$8542_Y + connect \$56 $pos$libresoc.v:158704$8544_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -311578,23 +330526,23 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:148904.1-148915.10" +attribute \src "libresoc.v:158828.1-158839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:148913.17-148913.111" - wire $and$libresoc.v:148913$8226_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158837.17-158837.111" + wire $and$libresoc.v:158837$8548_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:148913$8226 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158837$8548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311602,28 +330550,28 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:148913$8226_Y + connect \Y $and$libresoc.v:158837$8548_Y end - connect \$1 $and$libresoc.v:148913$8226_Y + connect \$1 $and$libresoc.v:158837$8548_Y connect \trigger \$1 end -attribute \src "libresoc.v:148919.1-148930.10" +attribute \src "libresoc.v:158843.1-158854.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:148928.17-148928.111" - wire $and$libresoc.v:148928$8227_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158852.17-158852.111" + wire $and$libresoc.v:158852$8549_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:148928$8227 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158852$8549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311631,28 +330579,28 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:148928$8227_Y + connect \Y $and$libresoc.v:158852$8549_Y end - connect \$1 $and$libresoc.v:148928$8227_Y + connect \$1 $and$libresoc.v:158852$8549_Y connect \trigger \$1 end -attribute \src "libresoc.v:148934.1-148945.10" +attribute \src "libresoc.v:158858.1-158869.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 - attribute \src "libresoc.v:148943.17-148943.111" - wire $and$libresoc.v:148943$8228_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158867.17-158867.111" + wire $and$libresoc.v:158867$8550_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:148943$8228 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158867$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311660,28 +330608,28 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:148943$8228_Y + connect \Y $and$libresoc.v:158867$8550_Y end - connect \$1 $and$libresoc.v:148943$8228_Y + connect \$1 $and$libresoc.v:158867$8550_Y connect \trigger \$1 end -attribute \src "libresoc.v:148949.1-148960.10" +attribute \src "libresoc.v:158873.1-158884.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 - attribute \src "libresoc.v:148958.17-148958.111" - wire $and$libresoc.v:148958$8229_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158882.17-158882.111" + wire $and$libresoc.v:158882$8551_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:148958$8229 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158882$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311689,28 +330637,28 @@ module \p$111 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:148958$8229_Y + connect \Y $and$libresoc.v:158882$8551_Y end - connect \$1 $and$libresoc.v:148958$8229_Y + connect \$1 $and$libresoc.v:158882$8551_Y connect \trigger \$1 end -attribute \src "libresoc.v:148964.1-148975.10" +attribute \src "libresoc.v:158888.1-158899.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 - attribute \src "libresoc.v:148973.17-148973.111" - wire $and$libresoc.v:148973$8230_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158897.17-158897.111" + wire $and$libresoc.v:158897$8552_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:148973$8230 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158897$8552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311718,28 +330666,28 @@ module \p$116 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:148973$8230_Y + connect \Y $and$libresoc.v:158897$8552_Y end - connect \$1 $and$libresoc.v:148973$8230_Y + connect \$1 $and$libresoc.v:158897$8552_Y connect \trigger \$1 end -attribute \src "libresoc.v:148979.1-148990.10" +attribute \src "libresoc.v:158903.1-158914.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:148988.17-148988.111" - wire $and$libresoc.v:148988$8231_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158912.17-158912.111" + wire $and$libresoc.v:158912$8553_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:148988$8231 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158912$8553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311747,28 +330695,28 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:148988$8231_Y + connect \Y $and$libresoc.v:158912$8553_Y end - connect \$1 $and$libresoc.v:148988$8231_Y + connect \$1 $and$libresoc.v:158912$8553_Y connect \trigger \$1 end -attribute \src "libresoc.v:148994.1-149005.10" +attribute \src "libresoc.v:158918.1-158929.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:149003.17-149003.111" - wire $and$libresoc.v:149003$8232_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158927.17-158927.111" + wire $and$libresoc.v:158927$8554_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149003$8232 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158927$8554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311776,28 +330724,28 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149003$8232_Y + connect \Y $and$libresoc.v:158927$8554_Y end - connect \$1 $and$libresoc.v:149003$8232_Y + connect \$1 $and$libresoc.v:158927$8554_Y connect \trigger \$1 end -attribute \src "libresoc.v:149009.1-149020.10" +attribute \src "libresoc.v:158933.1-158944.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:149018.17-149018.111" - wire $and$libresoc.v:149018$8233_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158942.17-158942.111" + wire $and$libresoc.v:158942$8555_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149018$8233 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158942$8555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311805,28 +330753,28 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149018$8233_Y + connect \Y $and$libresoc.v:158942$8555_Y end - connect \$1 $and$libresoc.v:149018$8233_Y + connect \$1 $and$libresoc.v:158942$8555_Y connect \trigger \$1 end -attribute \src "libresoc.v:149024.1-149035.10" +attribute \src "libresoc.v:158948.1-158959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:149033.17-149033.111" - wire $and$libresoc.v:149033$8234_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158957.17-158957.111" + wire $and$libresoc.v:158957$8556_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149033$8234 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158957$8556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311834,28 +330782,28 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149033$8234_Y + connect \Y $and$libresoc.v:158957$8556_Y end - connect \$1 $and$libresoc.v:149033$8234_Y + connect \$1 $and$libresoc.v:158957$8556_Y connect \trigger \$1 end -attribute \src "libresoc.v:149039.1-149050.10" +attribute \src "libresoc.v:158963.1-158974.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:149048.17-149048.111" - wire $and$libresoc.v:149048$8235_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158972.17-158972.111" + wire $and$libresoc.v:158972$8557_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149048$8235 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158972$8557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311863,28 +330811,28 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149048$8235_Y + connect \Y $and$libresoc.v:158972$8557_Y end - connect \$1 $and$libresoc.v:149048$8235_Y + connect \$1 $and$libresoc.v:158972$8557_Y connect \trigger \$1 end -attribute \src "libresoc.v:149054.1-149065.10" +attribute \src "libresoc.v:158978.1-158989.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 - attribute \src "libresoc.v:149063.17-149063.111" - wire $and$libresoc.v:149063$8236_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:158987.17-158987.111" + wire $and$libresoc.v:158987$8558_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149063$8236 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:158987$8558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311892,28 +330840,28 @@ module \p$36 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149063$8236_Y + connect \Y $and$libresoc.v:158987$8558_Y end - connect \$1 $and$libresoc.v:149063$8236_Y + connect \$1 $and$libresoc.v:158987$8558_Y connect \trigger \$1 end -attribute \src "libresoc.v:149069.1-149080.10" +attribute \src "libresoc.v:158993.1-159004.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 - attribute \src "libresoc.v:149078.17-149078.111" - wire $and$libresoc.v:149078$8237_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159002.17-159002.111" + wire $and$libresoc.v:159002$8559_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149078$8237 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159002$8559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311921,28 +330869,28 @@ module \p$46 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149078$8237_Y + connect \Y $and$libresoc.v:159002$8559_Y end - connect \$1 $and$libresoc.v:149078$8237_Y + connect \$1 $and$libresoc.v:159002$8559_Y connect \trigger \$1 end -attribute \src "libresoc.v:149084.1-149095.10" +attribute \src "libresoc.v:159008.1-159019.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 - attribute \src "libresoc.v:149093.17-149093.111" - wire $and$libresoc.v:149093$8238_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159017.17-159017.111" + wire $and$libresoc.v:159017$8560_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149093$8238 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159017$8560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311950,28 +330898,28 @@ module \p$48 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149093$8238_Y + connect \Y $and$libresoc.v:159017$8560_Y end - connect \$1 $and$libresoc.v:149093$8238_Y + connect \$1 $and$libresoc.v:159017$8560_Y connect \trigger \$1 end -attribute \src "libresoc.v:149099.1-149110.10" +attribute \src "libresoc.v:159023.1-159034.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:149108.17-149108.111" - wire $and$libresoc.v:149108$8239_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159032.17-159032.111" + wire $and$libresoc.v:159032$8561_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149108$8239 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159032$8561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311979,28 +330927,28 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149108$8239_Y + connect \Y $and$libresoc.v:159032$8561_Y end - connect \$1 $and$libresoc.v:149108$8239_Y + connect \$1 $and$libresoc.v:159032$8561_Y connect \trigger \$1 end -attribute \src "libresoc.v:149114.1-149125.10" +attribute \src "libresoc.v:159038.1-159049.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 - attribute \src "libresoc.v:149123.17-149123.111" - wire $and$libresoc.v:149123$8240_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159047.17-159047.111" + wire $and$libresoc.v:159047$8562_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149123$8240 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159047$8562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312008,28 +330956,28 @@ module \p$52 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149123$8240_Y + connect \Y $and$libresoc.v:159047$8562_Y end - connect \$1 $and$libresoc.v:149123$8240_Y + connect \$1 $and$libresoc.v:159047$8562_Y connect \trigger \$1 end -attribute \src "libresoc.v:149129.1-149140.10" +attribute \src "libresoc.v:159053.1-159064.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:149138.17-149138.111" - wire $and$libresoc.v:149138$8241_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159062.17-159062.111" + wire $and$libresoc.v:159062$8563_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149138$8241 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159062$8563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312037,28 +330985,28 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149138$8241_Y + connect \Y $and$libresoc.v:159062$8563_Y end - connect \$1 $and$libresoc.v:149138$8241_Y + connect \$1 $and$libresoc.v:159062$8563_Y connect \trigger \$1 end -attribute \src "libresoc.v:149144.1-149155.10" +attribute \src "libresoc.v:159068.1-159079.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 - attribute \src "libresoc.v:149153.17-149153.111" - wire $and$libresoc.v:149153$8242_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159077.17-159077.111" + wire $and$libresoc.v:159077$8564_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149153$8242 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159077$8564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312066,28 +331014,28 @@ module \p$65 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149153$8242_Y + connect \Y $and$libresoc.v:159077$8564_Y end - connect \$1 $and$libresoc.v:149153$8242_Y + connect \$1 $and$libresoc.v:159077$8564_Y connect \trigger \$1 end -attribute \src "libresoc.v:149159.1-149170.10" +attribute \src "libresoc.v:159083.1-159094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 - attribute \src "libresoc.v:149168.17-149168.111" - wire $and$libresoc.v:149168$8243_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159092.17-159092.111" + wire $and$libresoc.v:159092$8565_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149168$8243 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159092$8565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312095,28 +331043,28 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149168$8243_Y + connect \Y $and$libresoc.v:159092$8565_Y end - connect \$1 $and$libresoc.v:149168$8243_Y + connect \$1 $and$libresoc.v:159092$8565_Y connect \trigger \$1 end -attribute \src "libresoc.v:149174.1-149185.10" +attribute \src "libresoc.v:159098.1-159109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 - attribute \src "libresoc.v:149183.17-149183.111" - wire $and$libresoc.v:149183$8244_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159107.17-159107.111" + wire $and$libresoc.v:159107$8566_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149183$8244 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159107$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312124,28 +331072,28 @@ module \p$74 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149183$8244_Y + connect \Y $and$libresoc.v:159107$8566_Y end - connect \$1 $and$libresoc.v:149183$8244_Y + connect \$1 $and$libresoc.v:159107$8566_Y connect \trigger \$1 end -attribute \src "libresoc.v:149189.1-149200.10" +attribute \src "libresoc.v:159113.1-159124.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:149198.17-149198.111" - wire $and$libresoc.v:149198$8245_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159122.17-159122.111" + wire $and$libresoc.v:159122$8567_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149198$8245 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159122$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312153,28 +331101,28 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149198$8245_Y + connect \Y $and$libresoc.v:159122$8567_Y end - connect \$1 $and$libresoc.v:149198$8245_Y + connect \$1 $and$libresoc.v:159122$8567_Y connect \trigger \$1 end -attribute \src "libresoc.v:149204.1-149215.10" +attribute \src "libresoc.v:159128.1-159139.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 - attribute \src "libresoc.v:149213.17-149213.111" - wire $and$libresoc.v:149213$8246_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159137.17-159137.111" + wire $and$libresoc.v:159137$8568_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149213$8246 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159137$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312182,28 +331130,28 @@ module \p$79 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149213$8246_Y + connect \Y $and$libresoc.v:159137$8568_Y end - connect \$1 $and$libresoc.v:149213$8246_Y + connect \$1 $and$libresoc.v:159137$8568_Y connect \trigger \$1 end -attribute \src "libresoc.v:149219.1-149230.10" +attribute \src "libresoc.v:159143.1-159154.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 - attribute \src "libresoc.v:149228.17-149228.111" - wire $and$libresoc.v:149228$8247_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159152.17-159152.111" + wire $and$libresoc.v:159152$8569_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149228$8247 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159152$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312211,28 +331159,28 @@ module \p$81 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149228$8247_Y + connect \Y $and$libresoc.v:159152$8569_Y end - connect \$1 $and$libresoc.v:149228$8247_Y + connect \$1 $and$libresoc.v:159152$8569_Y connect \trigger \$1 end -attribute \src "libresoc.v:149234.1-149245.10" +attribute \src "libresoc.v:159158.1-159169.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 - attribute \src "libresoc.v:149243.17-149243.111" - wire $and$libresoc.v:149243$8248_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159167.17-159167.111" + wire $and$libresoc.v:159167$8570_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149243$8248 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159167$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312240,28 +331188,28 @@ module \p$91 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149243$8248_Y + connect \Y $and$libresoc.v:159167$8570_Y end - connect \$1 $and$libresoc.v:149243$8248_Y + connect \$1 $and$libresoc.v:159167$8570_Y connect \trigger \$1 end -attribute \src "libresoc.v:149249.1-149260.10" +attribute \src "libresoc.v:159173.1-159184.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:149258.17-149258.111" - wire $and$libresoc.v:149258$8249_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159182.17-159182.111" + wire $and$libresoc.v:159182$8571_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149258$8249 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159182$8571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312269,28 +331217,28 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149258$8249_Y + connect \Y $and$libresoc.v:159182$8571_Y end - connect \$1 $and$libresoc.v:149258$8249_Y + connect \$1 $and$libresoc.v:159182$8571_Y connect \trigger \$1 end -attribute \src "libresoc.v:149264.1-149275.10" +attribute \src "libresoc.v:159188.1-159199.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 - attribute \src "libresoc.v:149273.17-149273.111" - wire $and$libresoc.v:149273$8250_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159197.17-159197.111" + wire $and$libresoc.v:159197$8572_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149273$8250 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159197$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312298,28 +331246,28 @@ module \p$96 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149273$8250_Y + connect \Y $and$libresoc.v:159197$8572_Y end - connect \$1 $and$libresoc.v:149273$8250_Y + connect \$1 $and$libresoc.v:159197$8572_Y connect \trigger \$1 end -attribute \src "libresoc.v:149279.1-149290.10" +attribute \src "libresoc.v:159203.1-159214.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 - attribute \src "libresoc.v:149288.17-149288.111" - wire $and$libresoc.v:149288$8251_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + attribute \src "libresoc.v:159212.17-159212.111" + wire $and$libresoc.v:159212$8573_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149288$8251 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159212$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312327,36 +331275,36 @@ module \p$98 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:149288$8251_Y + connect \Y $and$libresoc.v:159212$8573_Y end - connect \$1 $and$libresoc.v:149288$8251_Y + connect \$1 $and$libresoc.v:159212$8573_Y connect \trigger \$1 end -attribute \src "libresoc.v:149294.1-149317.10" +attribute \src "libresoc.v:159218.1-159241.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:149295.7-149295.20" + attribute \src "libresoc.v:159219.7-159219.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149306.3-149315.6" + attribute \src "libresoc.v:159230.3-159239.6" wire $0\o[0:0] - attribute \src "libresoc.v:149306.3-149315.6" + attribute \src "libresoc.v:159230.3-159239.6" wire $1\o[0:0] - attribute \src "libresoc.v:149305.17-149305.95" - wire $eq$libresoc.v:149305$8252_Y + attribute \src "libresoc.v:159229.17-159229.95" + wire $eq$libresoc.v:159229$8574_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:149295.7-149295.15" + attribute \src "libresoc.v:159219.7-159219.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:149305$8252 + cell $eq $eq$libresoc.v:159229$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312364,24 +331312,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:149305$8252_Y + connect \Y $eq$libresoc.v:159229$8574_Y end - attribute \src "libresoc.v:149295.7-149295.20" - process $proc$libresoc.v:149295$8254 + attribute \src "libresoc.v:159219.7-159219.20" + process $proc$libresoc.v:159219$8576 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149306.3-149315.6" - process $proc$libresoc.v:149306$8253 + attribute \src "libresoc.v:159230.3-159239.6" + process $proc$libresoc.v:159230$8575 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:149307.5-149307.29" + attribute \src "libresoc.v:159231.5-159231.29" switch \initial - attribute \src "libresoc.v:149307.9-149307.17" + attribute \src "libresoc.v:159231.9-159231.17" case 1'1 case end @@ -312397,307 +331345,307 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:149305$8252_Y + connect \$1 $eq$libresoc.v:159229$8574_Y connect \n \$1 end -attribute \src "libresoc.v:149321.1-150135.10" +attribute \src "libresoc.v:159245.1-160059.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:150098.3-150113.6" + attribute \src "libresoc.v:160022.3-160037.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:150062.3-150097.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8344 - attribute \src "libresoc.v:149620.3-149621.57" + attribute \src "libresoc.v:159986.3-160021.6" + wire $0\adrok_l_s_addr_acked$next[0:0]$8666 + attribute \src "libresoc.v:159544.3-159545.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:149712.3-149720.6" - wire $0\busy_delay$next[0:0]$8312 - attribute \src "libresoc.v:149618.3-149619.37" + attribute \src "libresoc.v:159636.3-159644.6" + wire $0\busy_delay$next[0:0]$8634 + attribute \src "libresoc.v:159542.3-159543.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:150046.3-150061.6" + attribute \src "libresoc.v:159970.3-159985.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:150036.3-150045.6" + attribute \src "libresoc.v:159960.3-159969.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:150026.3-150035.6" + attribute \src "libresoc.v:159950.3-159959.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:150007.3-150016.6" + attribute \src "libresoc.v:159931.3-159940.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:149968.3-150006.6" - wire width 2 $0\fsm_state$next[1:0]$8330 - attribute \src "libresoc.v:149610.3-149611.35" + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $0\fsm_state$next[1:0]$8652 + attribute \src "libresoc.v:159534.3-159535.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:149322.7-149322.20" + attribute \src "libresoc.v:159246.7-159246.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149908.3-149917.6" + attribute \src "libresoc.v:159832.3-159841.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:149616.3-149617.35" + attribute \src "libresoc.v:159540.3-159541.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:149841.3-149871.6" + attribute \src "libresoc.v:159765.3-159795.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149898.3-149907.6" + attribute \src "libresoc.v:159822.3-159831.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:149918.3-149927.6" + attribute \src "libresoc.v:159842.3-159851.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:149747.3-149762.6" + attribute \src "libresoc.v:159671.3-159686.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:149731.3-149746.6" + attribute \src "libresoc.v:159655.3-159670.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:150017.3-150025.6" - wire $0\lsui_active_dly$next[0:0]$8338 - attribute \src "libresoc.v:149608.3-149609.47" + attribute \src "libresoc.v:159941.3-159949.6" + wire $0\lsui_active_dly$next[0:0]$8660 + attribute \src "libresoc.v:159532.3-159533.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:149948.3-149967.6" + attribute \src "libresoc.v:159872.3-159891.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:149612.3-149613.36" + attribute \src "libresoc.v:159536.3-159537.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:149888.3-149897.6" + attribute \src "libresoc.v:159812.3-159821.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:149872.3-149887.6" + attribute \src "libresoc.v:159796.3-159811.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:149721.3-149730.6" + attribute \src "libresoc.v:159645.3-159654.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:149702.3-149711.6" + attribute \src "libresoc.v:159626.3-159635.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:149687.3-149701.6" - wire $0\st_done_s_st_done$next[0:0]$8307 - attribute \src "libresoc.v:149622.3-149623.51" + attribute \src "libresoc.v:159611.3-159625.6" + wire $0\st_done_s_st_done$next[0:0]$8629 + attribute \src "libresoc.v:159546.3-159547.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:149928.3-149937.6" + attribute \src "libresoc.v:159852.3-159861.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:149614.3-149615.35" + attribute \src "libresoc.v:159538.3-159539.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:149763.3-149788.6" + attribute \src "libresoc.v:159687.3-159712.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:149815.3-149840.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:149789.3-149814.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:149938.3-149947.6" + attribute \src "libresoc.v:159862.3-159871.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:150098.3-150113.6" + attribute \src "libresoc.v:160022.3-160037.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:150062.3-150097.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8345 - attribute \src "libresoc.v:149416.7-149416.34" + attribute \src "libresoc.v:159986.3-160021.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8667 + attribute \src "libresoc.v:159340.7-159340.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:149712.3-149720.6" - wire $1\busy_delay$next[0:0]$8313 - attribute \src "libresoc.v:149420.7-149420.24" + attribute \src "libresoc.v:159636.3-159644.6" + wire $1\busy_delay$next[0:0]$8635 + attribute \src "libresoc.v:159344.7-159344.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:150046.3-150061.6" + attribute \src "libresoc.v:159970.3-159985.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:150036.3-150045.6" + attribute \src "libresoc.v:159960.3-159969.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:150026.3-150035.6" + attribute \src "libresoc.v:159950.3-159959.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:150007.3-150016.6" + attribute \src "libresoc.v:159931.3-159940.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:149968.3-150006.6" - wire width 2 $1\fsm_state$next[1:0]$8331 - attribute \src "libresoc.v:149442.13-149442.29" + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $1\fsm_state$next[1:0]$8653 + attribute \src "libresoc.v:159366.13-159366.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:149908.3-149917.6" + attribute \src "libresoc.v:159832.3-159841.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:149456.7-149456.21" + attribute \src "libresoc.v:159380.7-159380.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:149841.3-149871.6" + attribute \src "libresoc.v:159765.3-159795.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149898.3-149907.6" + attribute \src "libresoc.v:159822.3-159831.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:149918.3-149927.6" + attribute \src "libresoc.v:159842.3-159851.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:149747.3-149762.6" + attribute \src "libresoc.v:159671.3-159686.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:149731.3-149746.6" + attribute \src "libresoc.v:159655.3-159670.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:150017.3-150025.6" - wire $1\lsui_active_dly$next[0:0]$8339 - attribute \src "libresoc.v:149499.7-149499.29" + attribute \src "libresoc.v:159941.3-159949.6" + wire $1\lsui_active_dly$next[0:0]$8661 + attribute \src "libresoc.v:159423.7-159423.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:149948.3-149967.6" + attribute \src "libresoc.v:159872.3-159891.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:149511.7-149511.25" + attribute \src "libresoc.v:159435.7-159435.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:149888.3-149897.6" + attribute \src "libresoc.v:159812.3-159821.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:149872.3-149887.6" + attribute \src "libresoc.v:159796.3-159811.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:149721.3-149730.6" + attribute \src "libresoc.v:159645.3-159654.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:149702.3-149711.6" + attribute \src "libresoc.v:159626.3-159635.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:149687.3-149701.6" - wire $1\st_done_s_st_done$next[0:0]$8308 - attribute \src "libresoc.v:149531.7-149531.31" + attribute \src "libresoc.v:159611.3-159625.6" + wire $1\st_done_s_st_done$next[0:0]$8630 + attribute \src "libresoc.v:159455.7-159455.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:149928.3-149937.6" + attribute \src "libresoc.v:159852.3-159861.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:149539.7-149539.21" + attribute \src "libresoc.v:159463.7-159463.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:149763.3-149788.6" + attribute \src "libresoc.v:159687.3-159712.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:149815.3-149840.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:149789.3-149814.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:149938.3-149947.6" + attribute \src "libresoc.v:159862.3-159871.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:150098.3-150113.6" + attribute \src "libresoc.v:160022.3-160037.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:150062.3-150097.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8346 - attribute \src "libresoc.v:150046.3-150061.6" + attribute \src "libresoc.v:159986.3-160021.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8668 + attribute \src "libresoc.v:159970.3-159985.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:149968.3-150006.6" - wire width 2 $2\fsm_state$next[1:0]$8332 - attribute \src "libresoc.v:149841.3-149871.6" + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $2\fsm_state$next[1:0]$8654 + attribute \src "libresoc.v:159765.3-159795.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149747.3-149762.6" + attribute \src "libresoc.v:159671.3-159686.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:149731.3-149746.6" + attribute \src "libresoc.v:159655.3-159670.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:149948.3-149967.6" + attribute \src "libresoc.v:159872.3-159891.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:149872.3-149887.6" + attribute \src "libresoc.v:159796.3-159811.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:149687.3-149701.6" - wire $2\st_done_s_st_done$next[0:0]$8309 - attribute \src "libresoc.v:149763.3-149788.6" + attribute \src "libresoc.v:159611.3-159625.6" + wire $2\st_done_s_st_done$next[0:0]$8631 + attribute \src "libresoc.v:159687.3-159712.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:149815.3-149840.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:149789.3-149814.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:150062.3-150097.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8347 - attribute \src "libresoc.v:149968.3-150006.6" - wire width 2 $3\fsm_state$next[1:0]$8333 - attribute \src "libresoc.v:149841.3-149871.6" + attribute \src "libresoc.v:159986.3-160021.6" + wire $3\adrok_l_s_addr_acked$next[0:0]$8669 + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $3\fsm_state$next[1:0]$8655 + attribute \src "libresoc.v:159765.3-159795.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149763.3-149788.6" + attribute \src "libresoc.v:159687.3-159712.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:149815.3-149840.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:149789.3-149814.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:150062.3-150097.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8348 - attribute \src "libresoc.v:149968.3-150006.6" - wire width 2 $4\fsm_state$next[1:0]$8334 - attribute \src "libresoc.v:149841.3-149871.6" + attribute \src "libresoc.v:159986.3-160021.6" + wire $4\adrok_l_s_addr_acked$next[0:0]$8670 + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $4\fsm_state$next[1:0]$8656 + attribute \src "libresoc.v:159765.3-159795.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149763.3-149788.6" + attribute \src "libresoc.v:159687.3-159712.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:149815.3-149840.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:149789.3-149814.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:150062.3-150097.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$8349 - attribute \src "libresoc.v:149968.3-150006.6" - wire width 2 $5\fsm_state$next[1:0]$8335 - attribute \src "libresoc.v:149841.3-149871.6" + attribute \src "libresoc.v:159986.3-160021.6" + wire $5\adrok_l_s_addr_acked$next[0:0]$8671 + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $5\fsm_state$next[1:0]$8657 + attribute \src "libresoc.v:159765.3-159795.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:150062.3-150097.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$8350 - attribute \src "libresoc.v:149568.18-149568.115" - wire $and$libresoc.v:149568$8256_Y - attribute \src "libresoc.v:149570.18-149570.95" - wire $and$libresoc.v:149570$8258_Y - attribute \src "libresoc.v:149572.17-149572.138" - wire $and$libresoc.v:149572$8260_Y - attribute \src "libresoc.v:149573.18-149573.95" - wire $and$libresoc.v:149573$8261_Y - attribute \src "libresoc.v:149576.18-149576.136" - wire $and$libresoc.v:149576$8266_Y - attribute \src "libresoc.v:149577.18-149577.136" - wire $and$libresoc.v:149577$8267_Y - attribute \src "libresoc.v:149578.18-149578.136" - wire $and$libresoc.v:149578$8268_Y - attribute \src "libresoc.v:149579.18-149579.136" - wire $and$libresoc.v:149579$8269_Y - attribute \src "libresoc.v:149580.18-149580.136" - wire $and$libresoc.v:149580$8270_Y - attribute \src "libresoc.v:149585.18-149585.119" - wire width 176 $and$libresoc.v:149585$8275_Y - attribute \src "libresoc.v:149588.18-149588.136" - wire $and$libresoc.v:149588$8278_Y - attribute \src "libresoc.v:149589.18-149589.136" - wire $and$libresoc.v:149589$8279_Y - attribute \src "libresoc.v:149591.18-149591.139" - wire $and$libresoc.v:149591$8281_Y - attribute \src "libresoc.v:149595.18-149595.139" - wire $and$libresoc.v:149595$8285_Y - attribute \src "libresoc.v:149597.18-149597.114" - wire $and$libresoc.v:149597$8287_Y - attribute \src "libresoc.v:149599.18-149599.114" - wire $and$libresoc.v:149599$8289_Y - attribute \src "libresoc.v:149603.18-149603.103" - wire $and$libresoc.v:149603$8293_Y - attribute \src "libresoc.v:149604.17-149604.135" - wire $and$libresoc.v:149604$8294_Y - attribute \src "libresoc.v:149607.18-149607.103" - wire $and$libresoc.v:149607$8297_Y - attribute \src "libresoc.v:149574.18-149574.109" - wire width 4 $extend$libresoc.v:149574$8262_Y - attribute \src "libresoc.v:149575.18-149575.109" - wire width 4 $extend$libresoc.v:149575$8264_Y - attribute \src "libresoc.v:149586.18-149586.112" - wire width 8 $mul$libresoc.v:149586$8276_Y - attribute \src "libresoc.v:149592.18-149592.112" - wire width 8 $mul$libresoc.v:149592$8282_Y - attribute \src "libresoc.v:149567.17-149567.103" - wire $not$libresoc.v:149567$8255_Y - attribute \src "libresoc.v:149569.18-149569.94" - wire $not$libresoc.v:149569$8257_Y - attribute \src "libresoc.v:149571.18-149571.94" - wire $not$libresoc.v:149571$8259_Y - attribute \src "libresoc.v:149581.18-149581.102" - wire $not$libresoc.v:149581$8271_Y - attribute \src "libresoc.v:149584.18-149584.97" - wire $not$libresoc.v:149584$8274_Y - attribute \src "libresoc.v:149590.18-149590.102" - wire $not$libresoc.v:149590$8280_Y - attribute \src "libresoc.v:149593.17-149593.103" - wire $not$libresoc.v:149593$8283_Y - attribute \src "libresoc.v:149600.18-149600.101" - wire $not$libresoc.v:149600$8290_Y - attribute \src "libresoc.v:149601.18-149601.111" - wire $not$libresoc.v:149601$8291_Y - attribute \src "libresoc.v:149602.18-149602.110" - wire $not$libresoc.v:149602$8292_Y - attribute \src "libresoc.v:149605.18-149605.102" - wire $not$libresoc.v:149605$8295_Y - attribute \src "libresoc.v:149606.18-149606.102" - wire $not$libresoc.v:149606$8296_Y - attribute \src "libresoc.v:149582.18-149582.111" - wire $or$libresoc.v:149582$8272_Y - attribute \src "libresoc.v:149583.17-149583.130" - wire $or$libresoc.v:149583$8273_Y - attribute \src "libresoc.v:149596.18-149596.130" - wire $or$libresoc.v:149596$8286_Y - attribute \src "libresoc.v:149598.18-149598.130" - wire $or$libresoc.v:149598$8288_Y - attribute \src "libresoc.v:149574.18-149574.109" - wire width 4 $pos$libresoc.v:149574$8263_Y - attribute \src "libresoc.v:149575.18-149575.109" - wire width 4 $pos$libresoc.v:149575$8265_Y - attribute \src "libresoc.v:149594.18-149594.121" - wire width 319 $sshl$libresoc.v:149594$8284_Y - attribute \src "libresoc.v:149587.18-149587.106" - wire width 176 $sshr$libresoc.v:149587$8277_Y + attribute \src "libresoc.v:159986.3-160021.6" + wire $6\adrok_l_s_addr_acked$next[0:0]$8672 + attribute \src "libresoc.v:159492.18-159492.115" + wire $and$libresoc.v:159492$8578_Y + attribute \src "libresoc.v:159494.18-159494.95" + wire $and$libresoc.v:159494$8580_Y + attribute \src "libresoc.v:159496.17-159496.138" + wire $and$libresoc.v:159496$8582_Y + attribute \src "libresoc.v:159497.18-159497.95" + wire $and$libresoc.v:159497$8583_Y + attribute \src "libresoc.v:159500.18-159500.136" + wire $and$libresoc.v:159500$8588_Y + attribute \src "libresoc.v:159501.18-159501.136" + wire $and$libresoc.v:159501$8589_Y + attribute \src "libresoc.v:159502.18-159502.136" + wire $and$libresoc.v:159502$8590_Y + attribute \src "libresoc.v:159503.18-159503.136" + wire $and$libresoc.v:159503$8591_Y + attribute \src "libresoc.v:159504.18-159504.136" + wire $and$libresoc.v:159504$8592_Y + attribute \src "libresoc.v:159509.18-159509.119" + wire width 176 $and$libresoc.v:159509$8597_Y + attribute \src "libresoc.v:159512.18-159512.136" + wire $and$libresoc.v:159512$8600_Y + attribute \src "libresoc.v:159513.18-159513.136" + wire $and$libresoc.v:159513$8601_Y + attribute \src "libresoc.v:159515.18-159515.139" + wire $and$libresoc.v:159515$8603_Y + attribute \src "libresoc.v:159519.18-159519.139" + wire $and$libresoc.v:159519$8607_Y + attribute \src "libresoc.v:159521.18-159521.114" + wire $and$libresoc.v:159521$8609_Y + attribute \src "libresoc.v:159523.18-159523.114" + wire $and$libresoc.v:159523$8611_Y + attribute \src "libresoc.v:159527.18-159527.103" + wire $and$libresoc.v:159527$8615_Y + attribute \src "libresoc.v:159528.17-159528.135" + wire $and$libresoc.v:159528$8616_Y + attribute \src "libresoc.v:159531.18-159531.103" + wire $and$libresoc.v:159531$8619_Y + attribute \src "libresoc.v:159498.18-159498.109" + wire width 4 $extend$libresoc.v:159498$8584_Y + attribute \src "libresoc.v:159499.18-159499.109" + wire width 4 $extend$libresoc.v:159499$8586_Y + attribute \src "libresoc.v:159510.18-159510.112" + wire width 8 $mul$libresoc.v:159510$8598_Y + attribute \src "libresoc.v:159516.18-159516.112" + wire width 8 $mul$libresoc.v:159516$8604_Y + attribute \src "libresoc.v:159491.17-159491.103" + wire $not$libresoc.v:159491$8577_Y + attribute \src "libresoc.v:159493.18-159493.94" + wire $not$libresoc.v:159493$8579_Y + attribute \src "libresoc.v:159495.18-159495.94" + wire $not$libresoc.v:159495$8581_Y + attribute \src "libresoc.v:159505.18-159505.102" + wire $not$libresoc.v:159505$8593_Y + attribute \src "libresoc.v:159508.18-159508.97" + wire $not$libresoc.v:159508$8596_Y + attribute \src "libresoc.v:159514.18-159514.102" + wire $not$libresoc.v:159514$8602_Y + attribute \src "libresoc.v:159517.17-159517.103" + wire $not$libresoc.v:159517$8605_Y + attribute \src "libresoc.v:159524.18-159524.101" + wire $not$libresoc.v:159524$8612_Y + attribute \src "libresoc.v:159525.18-159525.111" + wire $not$libresoc.v:159525$8613_Y + attribute \src "libresoc.v:159526.18-159526.110" + wire $not$libresoc.v:159526$8614_Y + attribute \src "libresoc.v:159529.18-159529.102" + wire $not$libresoc.v:159529$8617_Y + attribute \src "libresoc.v:159530.18-159530.102" + wire $not$libresoc.v:159530$8618_Y + attribute \src "libresoc.v:159506.18-159506.111" + wire $or$libresoc.v:159506$8594_Y + attribute \src "libresoc.v:159507.17-159507.130" + wire $or$libresoc.v:159507$8595_Y + attribute \src "libresoc.v:159520.18-159520.130" + wire $or$libresoc.v:159520$8608_Y + attribute \src "libresoc.v:159522.18-159522.130" + wire $or$libresoc.v:159522$8610_Y + attribute \src "libresoc.v:159498.18-159498.109" + wire width 4 $pos$libresoc.v:159498$8585_Y + attribute \src "libresoc.v:159499.18-159499.109" + wire width 4 $pos$libresoc.v:159499$8587_Y + attribute \src "libresoc.v:159518.18-159518.121" + wire width 319 $sshl$libresoc.v:159518$8606_Y + attribute \src "libresoc.v:159511.18-159511.106" + wire width 176 $sshr$libresoc.v:159511$8599_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 4 \$21 @@ -312767,21 +331715,21 @@ module \pimem wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \adrok_l_q_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \adrok_l_qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \adrok_l_r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \adrok_l_s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \adrok_l_s_addr_acked$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" wire \busy_delay @@ -312789,43 +331737,43 @@ module \pimem wire \busy_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" wire \busy_edge - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \busy_l_q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \busy_l_r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \cyc_l_q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \cyc_l_r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \cyc_l_s_cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:149322.7-149322.15" + attribute \src "libresoc.v:159246.7-159246.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \ld_active_r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \ld_active_s_ld_active attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" wire width 64 \lddata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" wire \lds - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \lds_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \lds_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \lds_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 48 input 6 \ldst_port0_addr_i @@ -312861,11 +331809,11 @@ module \pimem wire width 176 \lenexp_rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" wire \lsui_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \lsui_active_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \lsui_active_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \lsui_active_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" wire \lsui_busy @@ -312877,41 +331825,41 @@ module \pimem wire \reset_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" wire \reset_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \reset_l_q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \st_active_q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \st_active_r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \st_active_s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \st_done_q_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \st_done_r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \st_done_s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \st_done_s_st_done$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" wire width 64 \stdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" wire \sts - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \sts_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \sts_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \sts_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \valid_l_q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \valid_l_r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \valid_l_s_valid attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" wire width 48 output 9 \x_addr_i @@ -312928,7 +331876,7 @@ module \pimem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:149568$8256 + cell $and $and$libresoc.v:159492$8578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312936,10 +331884,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:149568$8256_Y + connect \Y $and$libresoc.v:159492$8578_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:149570$8258 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:159494$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312947,10 +331895,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:149570$8258_Y + connect \Y $and$libresoc.v:159494$8580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:149572$8260 + cell $and $and$libresoc.v:159496$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312958,10 +331906,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:149572$8260_Y + connect \Y $and$libresoc.v:159496$8582_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:149573$8261 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:159497$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312969,10 +331917,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:149573$8261_Y + connect \Y $and$libresoc.v:159497$8583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149576$8266 + cell $and $and$libresoc.v:159500$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312980,10 +331928,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149576$8266_Y + connect \Y $and$libresoc.v:159500$8588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149577$8267 + cell $and $and$libresoc.v:159501$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312991,10 +331939,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149577$8267_Y + connect \Y $and$libresoc.v:159501$8589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149578$8268 + cell $and $and$libresoc.v:159502$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313002,10 +331950,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149578$8268_Y + connect \Y $and$libresoc.v:159502$8590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149579$8269 + cell $and $and$libresoc.v:159503$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313013,10 +331961,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149579$8269_Y + connect \Y $and$libresoc.v:159503$8591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:149580$8270 + cell $and $and$libresoc.v:159504$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313024,10 +331972,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:149580$8270_Y + connect \Y $and$libresoc.v:159504$8592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:149585$8275 + cell $and $and$libresoc.v:159509$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -313035,10 +331983,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:149585$8275_Y + connect \Y $and$libresoc.v:159509$8597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:149588$8278 + cell $and $and$libresoc.v:159512$8600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313046,10 +331994,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:149588$8278_Y + connect \Y $and$libresoc.v:159512$8600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:149589$8279 + cell $and $and$libresoc.v:159513$8601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313057,10 +332005,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:149589$8279_Y + connect \Y $and$libresoc.v:159513$8601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:149591$8281 + cell $and $and$libresoc.v:159515$8603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313068,10 +332016,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:149591$8281_Y + connect \Y $and$libresoc.v:159515$8603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:149595$8285 + cell $and $and$libresoc.v:159519$8607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313079,10 +332027,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:149595$8285_Y + connect \Y $and$libresoc.v:159519$8607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:149597$8287 + cell $and $and$libresoc.v:159521$8609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313090,10 +332038,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:149597$8287_Y + connect \Y $and$libresoc.v:159521$8609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:149599$8289 + cell $and $and$libresoc.v:159523$8611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313101,10 +332049,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:149599$8289_Y + connect \Y $and$libresoc.v:159523$8611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:149603$8293 + cell $and $and$libresoc.v:159527$8615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313112,10 +332060,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:149603$8293_Y + connect \Y $and$libresoc.v:159527$8615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149604$8294 + cell $and $and$libresoc.v:159528$8616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313123,10 +332071,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149604$8294_Y + connect \Y $and$libresoc.v:159528$8616_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:149607$8297 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:159531$8619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313134,26 +332082,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:149607$8297_Y + connect \Y $and$libresoc.v:159531$8619_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149574$8262 + cell $pos $extend$libresoc.v:159498$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:149574$8262_Y + connect \Y $extend$libresoc.v:159498$8584_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149575$8264 + cell $pos $extend$libresoc.v:159499$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:149575$8264_Y + connect \Y $extend$libresoc.v:159499$8586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:149586$8276 + cell $mul $mul$libresoc.v:159510$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -313161,10 +332109,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:149586$8276_Y + connect \Y $mul$libresoc.v:159510$8598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:149592$8282 + cell $mul $mul$libresoc.v:159516$8604 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -313172,106 +332120,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:149592$8282_Y + connect \Y $mul$libresoc.v:159516$8604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:149567$8255 + cell $not $not$libresoc.v:159491$8577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:149567$8255_Y + connect \Y $not$libresoc.v:159491$8577_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:149569$8257 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:159493$8579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:149569$8257_Y + connect \Y $not$libresoc.v:159493$8579_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:149571$8259 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:159495$8581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:149571$8259_Y + connect \Y $not$libresoc.v:159495$8581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:149581$8271 + cell $not $not$libresoc.v:159505$8593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:149581$8271_Y + connect \Y $not$libresoc.v:159505$8593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:149584$8274 + cell $not $not$libresoc.v:159508$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:149584$8274_Y + connect \Y $not$libresoc.v:159508$8596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:149590$8280 + cell $not $not$libresoc.v:159514$8602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:149590$8280_Y + connect \Y $not$libresoc.v:159514$8602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:149593$8283 + cell $not $not$libresoc.v:159517$8605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:149593$8283_Y + connect \Y $not$libresoc.v:159517$8605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:149600$8290 + cell $not $not$libresoc.v:159524$8612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:149600$8290_Y + connect \Y $not$libresoc.v:159524$8612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:149601$8291 + cell $not $not$libresoc.v:159525$8613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:149601$8291_Y + connect \Y $not$libresoc.v:159525$8613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:149602$8292 + cell $not $not$libresoc.v:159526$8614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:149602$8292_Y + connect \Y $not$libresoc.v:159526$8614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:149605$8295 + cell $not $not$libresoc.v:159529$8617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:149605$8295_Y + connect \Y $not$libresoc.v:159529$8617_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:149606$8296 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:159530$8618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:149606$8296_Y + connect \Y $not$libresoc.v:159530$8618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:149582$8272 + cell $or $or$libresoc.v:159506$8594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313279,10 +332227,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:149582$8272_Y + connect \Y $or$libresoc.v:159506$8594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:149583$8273 + cell $or $or$libresoc.v:159507$8595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313290,10 +332238,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:149583$8273_Y + connect \Y $or$libresoc.v:159507$8595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:149596$8286 + cell $or $or$libresoc.v:159520$8608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313301,10 +332249,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:149596$8286_Y + connect \Y $or$libresoc.v:159520$8608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:149598$8288 + cell $or $or$libresoc.v:159522$8610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313312,26 +332260,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:149598$8288_Y + connect \Y $or$libresoc.v:159522$8610_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149574$8263 + cell $pos $pos$libresoc.v:159498$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:149574$8262_Y - connect \Y $pos$libresoc.v:149574$8263_Y + connect \A $extend$libresoc.v:159498$8584_Y + connect \Y $pos$libresoc.v:159498$8585_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149575$8265 + cell $pos $pos$libresoc.v:159499$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:149575$8264_Y - connect \Y $pos$libresoc.v:149575$8265_Y + connect \A $extend$libresoc.v:159499$8586_Y + connect \Y $pos$libresoc.v:159499$8587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:149594$8284 + cell $sshl $sshl$libresoc.v:159518$8606 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -313339,10 +332287,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:149594$8284_Y + connect \Y $sshl$libresoc.v:159518$8606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:149587$8277 + cell $sshr $sshr$libresoc.v:159511$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -313350,10 +332298,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:149587$8277_Y + connect \Y $sshr$libresoc.v:159511$8599_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:149624.11-149631.4" + attribute \src "libresoc.v:159548.11-159555.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -313363,7 +332311,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:149632.10-149638.4" + attribute \src "libresoc.v:159556.10-159562.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -313372,7 +332320,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:149639.9-149645.4" + attribute \src "libresoc.v:159563.9-159569.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -313381,7 +332329,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:149646.13-149652.4" + attribute \src "libresoc.v:159570.13-159576.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -313390,7 +332338,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:149653.10-149658.4" + attribute \src "libresoc.v:159577.10-159582.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -313398,7 +332346,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:149659.11-149665.4" + attribute \src "libresoc.v:159583.11-159589.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -313407,7 +332355,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:149666.13-149672.4" + attribute \src "libresoc.v:159590.13-159596.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -313416,7 +332364,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:149673.11-149679.4" + attribute \src "libresoc.v:159597.11-159603.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -313425,3934 +332373,1279 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:149680.11-149686.4" + attribute \src "libresoc.v:159604.11-159610.4" cell \valid_l \valid_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_valid \valid_l_q_valid - connect \r_valid \valid_l_r_valid - connect \s_valid \valid_l_s_valid - end - attribute \src "libresoc.v:149322.7-149322.20" - process $proc$libresoc.v:149322$8352 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:149416.7-149416.34" - process $proc$libresoc.v:149416$8353 - assign { } { } - assign $1\adrok_l_s_addr_acked[0:0] 1'0 - sync always - sync init - update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] - end - attribute \src "libresoc.v:149420.7-149420.24" - process $proc$libresoc.v:149420$8354 - assign { } { } - assign $1\busy_delay[0:0] 1'0 - sync always - sync init - update \busy_delay $1\busy_delay[0:0] - end - attribute \src "libresoc.v:149442.13-149442.29" - process $proc$libresoc.v:149442$8355 - assign { } { } - assign $1\fsm_state[1:0] 2'00 - sync always - sync init - update \fsm_state $1\fsm_state[1:0] - end - attribute \src "libresoc.v:149456.7-149456.21" - process $proc$libresoc.v:149456$8356 - assign { } { } - assign $1\lds_dly[0:0] 1'0 - sync always - sync init - update \lds_dly $1\lds_dly[0:0] - end - attribute \src "libresoc.v:149499.7-149499.29" - process $proc$libresoc.v:149499$8357 - assign { } { } - assign $1\lsui_active_dly[0:0] 1'0 - sync always - sync init - update \lsui_active_dly $1\lsui_active_dly[0:0] - end - attribute \src "libresoc.v:149511.7-149511.25" - process $proc$libresoc.v:149511$8358 - assign { } { } - assign $1\reset_delay[0:0] 1'0 - sync always - sync init - update \reset_delay $1\reset_delay[0:0] - end - attribute \src "libresoc.v:149531.7-149531.31" - process $proc$libresoc.v:149531$8359 - assign { } { } - assign $1\st_done_s_st_done[0:0] 1'0 - sync always - sync init - update \st_done_s_st_done $1\st_done_s_st_done[0:0] - end - attribute \src "libresoc.v:149539.7-149539.21" - process $proc$libresoc.v:149539$8360 - assign { } { } - assign $1\sts_dly[0:0] 1'0 - sync always - sync init - update \sts_dly $1\sts_dly[0:0] - end - attribute \src "libresoc.v:149608.3-149609.47" - process $proc$libresoc.v:149608$8298 - assign { } { } - assign $0\lsui_active_dly[0:0] \lsui_active_dly$next - sync posedge \coresync_clk - update \lsui_active_dly $0\lsui_active_dly[0:0] - end - attribute \src "libresoc.v:149610.3-149611.35" - process $proc$libresoc.v:149610$8299 - assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next - sync posedge \coresync_clk - update \fsm_state $0\fsm_state[1:0] - end - attribute \src "libresoc.v:149612.3-149613.36" - process $proc$libresoc.v:149612$8300 - assign { } { } - assign $0\reset_delay[0:0] \reset_l_q_reset - sync posedge \coresync_clk - update \reset_delay $0\reset_delay[0:0] - end - attribute \src "libresoc.v:149614.3-149615.35" - process $proc$libresoc.v:149614$8301 - assign { } { } - assign $0\sts_dly[0:0] \ldst_port0_is_st_i - sync posedge \coresync_clk - update \sts_dly $0\sts_dly[0:0] - end - attribute \src "libresoc.v:149616.3-149617.35" - process $proc$libresoc.v:149616$8302 - assign { } { } - assign $0\lds_dly[0:0] \ldst_port0_is_ld_i - sync posedge \coresync_clk - update \lds_dly $0\lds_dly[0:0] - end - attribute \src "libresoc.v:149618.3-149619.37" - process $proc$libresoc.v:149618$8303 - assign { } { } - assign $0\busy_delay[0:0] \busy_delay$next - sync posedge \coresync_clk - update \busy_delay $0\busy_delay[0:0] - end - attribute \src "libresoc.v:149620.3-149621.57" - process $proc$libresoc.v:149620$8304 - assign { } { } - assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next - sync posedge \coresync_clk - update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] - end - attribute \src "libresoc.v:149622.3-149623.51" - process $proc$libresoc.v:149622$8305 - assign { } { } - assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next - sync posedge \coresync_clk - update \st_done_s_st_done $0\st_done_s_st_done[0:0] - end - attribute \src "libresoc.v:149687.3-149701.6" - process $proc$libresoc.v:149687$8306 - assign { } { } - assign { } { } - assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8307 $2\st_done_s_st_done$next[0:0]$8309 - attribute \src "libresoc.v:149688.5-149688.29" - switch \initial - attribute \src "libresoc.v:149688.9-149688.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8308 1'1 - case - assign $1\st_done_s_st_done$next[0:0]$8308 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8309 1'0 - case - assign $2\st_done_s_st_done$next[0:0]$8309 $1\st_done_s_st_done$next[0:0]$8308 - end - sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8307 - end - attribute \src "libresoc.v:149702.3-149711.6" - process $proc$libresoc.v:149702$8310 - assign { } { } - assign { } { } - assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:149703.5-149703.29" - switch \initial - attribute \src "libresoc.v:149703.9-149703.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_done_r_st_done[0:0] 1'1 - case - assign $1\st_done_r_st_done[0:0] 1'0 - end - sync always - update \st_done_r_st_done $0\st_done_r_st_done[0:0] - end - attribute \src "libresoc.v:149712.3-149720.6" - process $proc$libresoc.v:149712$8311 - assign { } { } - assign { } { } - assign $0\busy_delay$next[0:0]$8312 $1\busy_delay$next[0:0]$8313 - attribute \src "libresoc.v:149713.5-149713.29" - switch \initial - attribute \src "libresoc.v:149713.9-149713.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\busy_delay$next[0:0]$8313 1'0 - case - assign $1\busy_delay$next[0:0]$8313 \ldst_port0_busy_o - end - sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8312 - end - attribute \src "libresoc.v:149721.3-149730.6" - process $proc$libresoc.v:149721$8314 - assign { } { } - assign { } { } - assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:149722.5-149722.29" - switch \initial - attribute \src "libresoc.v:149722.9-149722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_active_r_st_active[0:0] 1'1 - case - assign $1\st_active_r_st_active[0:0] 1'0 - end - sync always - update \st_active_r_st_active $0\st_active_r_st_active[0:0] - end - attribute \src "libresoc.v:149731.3-149746.6" - process $proc$libresoc.v:149731$8315 - assign { } { } - assign { } { } - assign { } { } - assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:149732.5-149732.29" - switch \initial - attribute \src "libresoc.v:149732.9-149732.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lenexp_len_i[3:0] \ldst_port0_data_len - case - assign $1\lenexp_len_i[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lenexp_len_i[3:0] \ldst_port0_data_len - case - assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] - end - sync always - update \lenexp_len_i $0\lenexp_len_i[3:0] - end - attribute \src "libresoc.v:149747.3-149762.6" - process $proc$libresoc.v:149747$8316 - assign { } { } - assign { } { } - assign { } { } - assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:149748.5-149748.29" - switch \initial - attribute \src "libresoc.v:149748.9-149748.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lenexp_addr_i[3:0] \$21 - case - assign $1\lenexp_addr_i[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lenexp_addr_i[3:0] \$23 - case - assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] - end - sync always - update \lenexp_addr_i $0\lenexp_addr_i[3:0] - end - attribute \src "libresoc.v:149763.3-149788.6" - process $proc$libresoc.v:149763$8317 - assign { } { } - assign { } { } - assign { } { } - assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:149764.5-149764.29" - switch \initial - attribute \src "libresoc.v:149764.9-149764.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\valid_l_s_valid[0:0] 1'1 - case - assign $2\valid_l_s_valid[0:0] 1'0 - end - case - assign $1\valid_l_s_valid[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\valid_l_s_valid[0:0] 1'1 - case - assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] - end - case - assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] - end - sync always - update \valid_l_s_valid $0\valid_l_s_valid[0:0] - end - attribute \src "libresoc.v:149789.3-149814.6" - process $proc$libresoc.v:149789$8318 - assign { } { } - assign { } { } - assign { } { } - assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:149790.5-149790.29" - switch \initial - attribute \src "libresoc.v:149790.9-149790.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] - case - assign $2\x_mask_i[7:0] 8'00000000 - end - case - assign $1\x_mask_i[7:0] 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] - case - assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] - end - case - assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] - end - sync always - update \x_mask_i $0\x_mask_i[7:0] - end - attribute \src "libresoc.v:149815.3-149840.6" - process $proc$libresoc.v:149815$8319 - assign { } { } - assign { } { } - assign { } { } - assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:149816.5-149816.29" - switch \initial - attribute \src "libresoc.v:149816.9-149816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\x_addr_i[47:0] \ldst_port0_addr_i - case - assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - case - assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\x_addr_i[47:0] \ldst_port0_addr_i - case - assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] - end - case - assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] - end - sync always - update \x_addr_i $0\x_addr_i[47:0] - end - attribute \src "libresoc.v:149841.3-149871.6" - process $proc$libresoc.v:149841$8320 - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149842.5-149842.29" - switch \initial - attribute \src "libresoc.v:149842.9-149842.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ldst_port0_addr_ok_o[0:0] 1'1 - case - assign $2\ldst_port0_addr_ok_o[0:0] 1'0 - end - case - assign $1\ldst_port0_addr_ok_o[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - switch \adrok_l_qn_addr_acked - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\ldst_port0_addr_ok_o[0:0] 1'1 - case - assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - case - assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - case - assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - sync always - update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] - end - attribute \src "libresoc.v:149872.3-149887.6" - process $proc$libresoc.v:149872$8321 - assign { } { } - assign { } { } - assign { } { } - assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:149873.5-149873.29" - switch \initial - attribute \src "libresoc.v:149873.9-149873.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$33 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_s_reset[0:0] \$35 - case - assign $1\reset_l_s_reset[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" - switch \st_done_q_st_done - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reset_l_s_reset[0:0] \$37 - case - assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - end - sync always - update \reset_l_s_reset $0\reset_l_s_reset[0:0] - end - attribute \src "libresoc.v:149888.3-149897.6" - process $proc$libresoc.v:149888$8322 - assign { } { } - assign { } { } - assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:149889.5-149889.29" - switch \initial - attribute \src "libresoc.v:149889.9-149889.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_r_reset[0:0] 1'1 - case - assign $1\reset_l_r_reset[0:0] 1'0 - end - sync always - update \reset_l_r_reset $0\reset_l_r_reset[0:0] + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_valid \valid_l_q_valid + connect \r_valid \valid_l_r_valid + connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:149898.3-149907.6" - process $proc$libresoc.v:149898$8323 - assign { } { } + attribute \src "libresoc.v:159246.7-159246.20" + process $proc$libresoc.v:159246$8674 assign { } { } - assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:149899.5-149899.29" - switch \initial - attribute \src "libresoc.v:149899.9-149899.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_ld_data_o[63:0] \lddata - case - assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $0\initial[0:0] 1'0 sync always - update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:149908.3-149917.6" - process $proc$libresoc.v:149908$8324 + attribute \src "libresoc.v:159340.7-159340.34" + process $proc$libresoc.v:159340$8675 assign { } { } - assign { } { } - assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:149909.5-149909.29" - switch \initial - attribute \src "libresoc.v:149909.9-149909.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ld_active_r_ld_active[0:0] 1'1 - case - assign $1\ld_active_r_ld_active[0:0] 1'0 - end + assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always - update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] + sync init + update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:149918.3-149927.6" - process $proc$libresoc.v:149918$8325 - assign { } { } + attribute \src "libresoc.v:159344.7-159344.24" + process $proc$libresoc.v:159344$8676 assign { } { } - assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:149919.5-149919.29" - switch \initial - attribute \src "libresoc.v:149919.9-149919.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$50 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 - case - assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 - end + assign $1\busy_delay[0:0] 1'0 sync always - update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + sync init + update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:149928.3-149937.6" - process $proc$libresoc.v:149928$8326 + attribute \src "libresoc.v:159366.13-159366.29" + process $proc$libresoc.v:159366$8677 assign { } { } - assign { } { } - assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:149929.5-149929.29" - switch \initial - attribute \src "libresoc.v:149929.9-149929.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$54 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\stdata[63:0] \$56 [63:0] - case - assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\fsm_state[1:0] 2'00 sync always - update \stdata $0\stdata[63:0] + sync init + update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:149938.3-149947.6" - process $proc$libresoc.v:149938$8327 - assign { } { } + attribute \src "libresoc.v:159380.7-159380.21" + process $proc$libresoc.v:159380$8678 assign { } { } - assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:149939.5-149939.29" - switch \initial - attribute \src "libresoc.v:149939.9-149939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$61 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_st_data_i[63:0] \stdata - case - assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\lds_dly[0:0] 1'0 sync always - update \x_st_data_i $0\x_st_data_i[63:0] + sync init + update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:149948.3-149967.6" - process $proc$libresoc.v:149948$8328 + attribute \src "libresoc.v:159423.7-159423.29" + process $proc$libresoc.v:159423$8679 assign { } { } - assign { } { } - assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:149949.5-149949.29" - switch \initial - attribute \src "libresoc.v:149949.9-149949.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch \$65 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lsui_busy[0:0] 1'1 - case - assign $2\lsui_busy[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\lsui_busy[0:0] 1'1 - case - assign $1\lsui_busy[0:0] 1'0 - end + assign $1\lsui_active_dly[0:0] 1'0 sync always - update \lsui_busy $0\lsui_busy[0:0] + sync init + update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:149968.3-150006.6" - process $proc$libresoc.v:149968$8329 + attribute \src "libresoc.v:159435.7-159435.25" + process $proc$libresoc.v:159435$8680 assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:159455.7-159455.31" + process $proc$libresoc.v:159455$8681 assign { } { } + assign $1\st_done_s_st_done[0:0] 1'0 + sync always + sync init + update \st_done_s_st_done $1\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:159463.7-159463.21" + process $proc$libresoc.v:159463$8682 assign { } { } - assign $0\fsm_state$next[1:0]$8330 $5\fsm_state$next[1:0]$8335 - attribute \src "libresoc.v:149969.5-149969.29" - switch \initial - attribute \src "libresoc.v:149969.9-149969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\fsm_state$next[1:0]$8331 $2\fsm_state$next[1:0]$8332 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$8332 2'01 - case - assign $2\fsm_state$next[1:0]$8332 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\fsm_state$next[1:0]$8331 $3\fsm_state$next[1:0]$8333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - switch \$71 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[1:0]$8333 2'10 - case - assign $3\fsm_state$next[1:0]$8333 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\fsm_state$next[1:0]$8331 $4\fsm_state$next[1:0]$8334 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$8334 2'00 - case - assign $4\fsm_state$next[1:0]$8334 \fsm_state - end - case - assign $1\fsm_state$next[1:0]$8331 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$next[1:0]$8335 2'00 - case - assign $5\fsm_state$next[1:0]$8335 $1\fsm_state$next[1:0]$8331 - end + assign $1\sts_dly[0:0] 1'0 sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8330 + sync init + update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:150007.3-150016.6" - process $proc$libresoc.v:150007$8336 + attribute \src "libresoc.v:159532.3-159533.47" + process $proc$libresoc.v:159532$8620 assign { } { } + assign $0\lsui_active_dly[0:0] \lsui_active_dly$next + sync posedge \coresync_clk + update \lsui_active_dly $0\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:159534.3-159535.35" + process $proc$libresoc.v:159534$8621 assign { } { } - assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:150008.5-150008.29" - switch \initial - attribute \src "libresoc.v:150008.9-150008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" - switch \reset_l_s_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cyc_l_s_cyc[0:0] 1'1 - case - assign $1\cyc_l_s_cyc[0:0] 1'0 - end - sync always - update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \coresync_clk + update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:150017.3-150025.6" - process $proc$libresoc.v:150017$8337 + attribute \src "libresoc.v:159536.3-159537.36" + process $proc$libresoc.v:159536$8622 assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:159538.3-159539.35" + process $proc$libresoc.v:159538$8623 assign { } { } - assign $0\lsui_active_dly$next[0:0]$8338 $1\lsui_active_dly$next[0:0]$8339 - attribute \src "libresoc.v:150018.5-150018.29" - switch \initial - attribute \src "libresoc.v:150018.9-150018.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lsui_active_dly$next[0:0]$8339 1'0 - case - assign $1\lsui_active_dly$next[0:0]$8339 \lsui_active - end - sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8338 + assign $0\sts_dly[0:0] \ldst_port0_is_st_i + sync posedge \coresync_clk + update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:150026.3-150035.6" - process $proc$libresoc.v:150026$8340 + attribute \src "libresoc.v:159540.3-159541.35" + process $proc$libresoc.v:159540$8624 assign { } { } + assign $0\lds_dly[0:0] \ldst_port0_is_ld_i + sync posedge \coresync_clk + update \lds_dly $0\lds_dly[0:0] + end + attribute \src "libresoc.v:159542.3-159543.37" + process $proc$libresoc.v:159542$8625 assign { } { } - assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:150027.5-150027.29" - switch \initial - attribute \src "libresoc.v:150027.9-150027.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" - switch \cyc_l_q_cyc - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cyc_l_r_cyc[0:0] 1'1 - case - assign $1\cyc_l_r_cyc[0:0] 1'0 - end - sync always - update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] + assign $0\busy_delay[0:0] \busy_delay$next + sync posedge \coresync_clk + update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:150036.3-150045.6" - process $proc$libresoc.v:150036$8341 + attribute \src "libresoc.v:159544.3-159545.57" + process $proc$libresoc.v:159544$8626 assign { } { } + assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next + sync posedge \coresync_clk + update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:159546.3-159547.51" + process $proc$libresoc.v:159546$8627 assign { } { } - assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:150037.5-150037.29" - switch \initial - attribute \src "libresoc.v:150037.9-150037.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\busy_l_s_busy[0:0] \$5 - case - assign $1\busy_l_s_busy[0:0] 1'0 - end - sync always - update \busy_l_s_busy $0\busy_l_s_busy[0:0] + assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next + sync posedge \coresync_clk + update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:150046.3-150061.6" - process $proc$libresoc.v:150046$8342 + attribute \src "libresoc.v:159611.3-159625.6" + process $proc$libresoc.v:159611$8628 assign { } { } assign { } { } assign { } { } - assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:150047.5-150047.29" + assign $0\st_done_s_st_done$next[0:0]$8629 $2\st_done_s_st_done$next[0:0]$8631 + attribute \src "libresoc.v:159612.5-159612.29" switch \initial - attribute \src "libresoc.v:150047.9-150047.17" + attribute \src "libresoc.v:159612.9-159612.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" - switch \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_l_r_busy[0:0] 1'1 + assign $1\st_done_s_st_done$next[0:0]$8630 1'1 case - assign $1\busy_l_r_busy[0:0] 1'0 + assign $1\st_done_s_st_done$next[0:0]$8630 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" - switch \cyc_l_q_cyc + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\busy_l_r_busy[0:0] 1'1 + assign $2\st_done_s_st_done$next[0:0]$8631 1'0 case - assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] + assign $2\st_done_s_st_done$next[0:0]$8631 $1\st_done_s_st_done$next[0:0]$8630 end sync always - update \busy_l_r_busy $0\busy_l_r_busy[0:0] + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8629 end - attribute \src "libresoc.v:150062.3-150097.6" - process $proc$libresoc.v:150062$8343 + attribute \src "libresoc.v:159626.3-159635.6" + process $proc$libresoc.v:159626$8632 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8344 $6\adrok_l_s_addr_acked$next[0:0]$8350 - attribute \src "libresoc.v:150063.5-150063.29" + assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] + attribute \src "libresoc.v:159627.5-159627.29" switch \initial - attribute \src "libresoc.v:150063.9-150063.17" + attribute \src "libresoc.v:159627.9-159627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8345 $2\adrok_l_s_addr_acked$next[0:0]$8346 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8346 1'1 - case - assign $2\adrok_l_s_addr_acked$next[0:0]$8346 1'0 - end + assign $1\st_done_r_st_done[0:0] 1'1 case - assign $1\adrok_l_s_addr_acked$next[0:0]$8345 1'0 + assign $1\st_done_r_st_done[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" + sync always + update \st_done_r_st_done $0\st_done_r_st_done[0:0] + end + attribute \src "libresoc.v:159636.3-159644.6" + process $proc$libresoc.v:159636$8633 + assign { } { } + assign { } { } + assign $0\busy_delay$next[0:0]$8634 $1\busy_delay$next[0:0]$8635 + attribute \src "libresoc.v:159637.5-159637.29" + switch \initial + attribute \src "libresoc.v:159637.9-159637.17" case 1'1 - assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8347 $4\adrok_l_s_addr_acked$next[0:0]$8348 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8348 $5\adrok_l_s_addr_acked$next[0:0]$8349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - switch \adrok_l_qn_addr_acked - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$8349 1'1 - case - assign $5\adrok_l_s_addr_acked$next[0:0]$8349 $1\adrok_l_s_addr_acked$next[0:0]$8345 - end - case - assign $4\adrok_l_s_addr_acked$next[0:0]$8348 $1\adrok_l_s_addr_acked$next[0:0]$8345 - end case - assign $3\adrok_l_s_addr_acked$next[0:0]$8347 $1\adrok_l_s_addr_acked$next[0:0]$8345 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8350 1'0 + assign $1\busy_delay$next[0:0]$8635 1'0 case - assign $6\adrok_l_s_addr_acked$next[0:0]$8350 $3\adrok_l_s_addr_acked$next[0:0]$8347 + assign $1\busy_delay$next[0:0]$8635 \ldst_port0_busy_o end sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8344 + update \busy_delay$next $0\busy_delay$next[0:0]$8634 end - attribute \src "libresoc.v:150098.3-150113.6" - process $proc$libresoc.v:150098$8351 + attribute \src "libresoc.v:159645.3-159654.6" + process $proc$libresoc.v:159645$8636 assign { } { } assign { } { } - assign { } { } - assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:150099.5-150099.29" + assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] + attribute \src "libresoc.v:159646.5-159646.29" switch \initial - attribute \src "libresoc.v:150099.9-150099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" - switch \reset_delay - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:159646.9-159646.17" case 1'1 - assign { } { } - assign $1\adrok_l_r_addr_acked[0:0] 1'1 case - assign $1\adrok_l_r_addr_acked[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\adrok_l_r_addr_acked[0:0] 1'1 + assign $1\st_active_r_st_active[0:0] 1'1 case - assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] + assign $1\st_active_r_st_active[0:0] 1'0 end sync always - update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] - end - connect \$9 $not$libresoc.v:149567$8255_Y - connect \$11 $and$libresoc.v:149568$8256_Y - connect \$13 $not$libresoc.v:149569$8257_Y - connect \$15 $and$libresoc.v:149570$8258_Y - connect \$17 $not$libresoc.v:149571$8259_Y - connect \$1 $and$libresoc.v:149572$8260_Y - connect \$19 $and$libresoc.v:149573$8261_Y - connect \$21 $pos$libresoc.v:149574$8263_Y - connect \$23 $pos$libresoc.v:149575$8265_Y - connect \$25 $and$libresoc.v:149576$8266_Y - connect \$27 $and$libresoc.v:149577$8267_Y - connect \$29 $and$libresoc.v:149578$8268_Y - connect \$31 $and$libresoc.v:149579$8269_Y - connect \$33 $and$libresoc.v:149580$8270_Y - connect \$35 $not$libresoc.v:149581$8271_Y - connect \$38 $or$libresoc.v:149582$8272_Y - connect \$3 $or$libresoc.v:149583$8273_Y - connect \$37 $not$libresoc.v:149584$8274_Y - connect \$42 $and$libresoc.v:149585$8275_Y - connect \$44 $mul$libresoc.v:149586$8276_Y - connect \$46 $sshr$libresoc.v:149587$8277_Y - connect \$48 $and$libresoc.v:149588$8278_Y - connect \$50 $and$libresoc.v:149589$8279_Y - connect \$52 $not$libresoc.v:149590$8280_Y - connect \$54 $and$libresoc.v:149591$8281_Y - connect \$57 $mul$libresoc.v:149592$8282_Y - connect \$5 $not$libresoc.v:149593$8283_Y - connect \$59 $sshl$libresoc.v:149594$8284_Y - connect \$61 $and$libresoc.v:149595$8285_Y - connect \$63 $or$libresoc.v:149596$8286_Y - connect \$65 $and$libresoc.v:149597$8287_Y - connect \$67 $or$libresoc.v:149598$8288_Y - connect \$69 $and$libresoc.v:149599$8289_Y - connect \$71 $not$libresoc.v:149600$8290_Y - connect \$73 $not$libresoc.v:149601$8291_Y - connect \$75 $not$libresoc.v:149602$8292_Y - connect \$77 $and$libresoc.v:149603$8293_Y - connect \$7 $and$libresoc.v:149604$8294_Y - connect \$79 $not$libresoc.v:149605$8295_Y - connect \$81 $not$libresoc.v:149606$8296_Y - connect \$83 $and$libresoc.v:149607$8297_Y - connect \$41 \$46 - connect \$56 \$59 - connect \valid_l_r_valid \lsui_active_rise - connect \lsui_active_rise \$83 - connect \lsui_active \$79 - connect \x_valid_i \valid_l_q_valid - connect \m_valid_i \valid_l_q_valid - connect \x_st_i \ldst_port0_is_st_i - connect \x_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_busy_o \busy_l_q_busy - connect \reset_delay$next \reset_l_q_reset - connect \lddata \$46 [63:0] - connect \st_active_s_st_active \sts_rise - connect \sts_rise \$19 - connect \sts_dly$next \sts - connect \ld_active_s_ld_active \lds_rise - connect \lds_rise \$15 - connect \lds_dly$next \lds - connect \busy_edge \$11 - connect \sts \ldst_port0_is_st_i - connect \lds \ldst_port0_is_ld_i -end -attribute \src "libresoc.v:150139.1-150904.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" -attribute \generator "nMigen" -module \pipe - attribute \src "libresoc.v:150867.3-150885.6" - wire width 4 $0\cr_a$6$next[3:0]$8407 - attribute \src "libresoc.v:150731.3-150732.31" - wire width 4 $0\cr_a$6[3:0]$8363 - attribute \src "libresoc.v:150153.13-150153.28" - wire width 4 $0\cr_a$6[3:0]$8413 - attribute \src "libresoc.v:150867.3-150885.6" - wire $0\cr_a_ok$next[0:0]$8406 - attribute \src "libresoc.v:150733.3-150734.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:150814.3-150828.6" - wire width 12 $0\cr_op__fn_unit$3$next[11:0]$8387 - attribute \src "libresoc.v:150745.3-150746.51" - wire width 12 $0\cr_op__fn_unit$3[11:0]$8373 - attribute \src "libresoc.v:150212.14-150212.42" - wire width 12 $0\cr_op__fn_unit$3[11:0]$8416 - attribute \src "libresoc.v:150814.3-150828.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$8388 - attribute \src "libresoc.v:150747.3-150748.45" - wire width 32 $0\cr_op__insn$4[31:0]$8375 - attribute \src "libresoc.v:150221.14-150221.37" - wire width 32 $0\cr_op__insn$4[31:0]$8418 - attribute \src "libresoc.v:150814.3-150828.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$8389 - attribute \src "libresoc.v:150743.3-150744.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$8371 - attribute \src "libresoc.v:150452.13-150452.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$8420 - attribute \src "libresoc.v:150848.3-150866.6" - wire width 32 $0\full_cr$5$next[31:0]$8400 - attribute \src "libresoc.v:150735.3-150736.37" - wire width 32 $0\full_cr$5[31:0]$8366 - attribute \src "libresoc.v:150461.14-150461.33" - wire width 32 $0\full_cr$5[31:0]$8422 - attribute \src "libresoc.v:150848.3-150866.6" - wire $0\full_cr_ok$next[0:0]$8401 - attribute \src "libresoc.v:150737.3-150738.37" - wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:150140.7-150140.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:150801.3-150813.6" - wire width 2 $0\muxid$1$next[1:0]$8384 - attribute \src "libresoc.v:150749.3-150750.33" - wire width 2 $0\muxid$1[1:0]$8377 - attribute \src "libresoc.v:150689.13-150689.29" - wire width 2 $0\muxid$1[1:0]$8425 - attribute \src "libresoc.v:150829.3-150847.6" - wire width 64 $0\o$next[63:0]$8394 - attribute \src "libresoc.v:150739.3-150740.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:150829.3-150847.6" - wire $0\o_ok$next[0:0]$8395 - attribute \src "libresoc.v:150741.3-150742.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:150783.3-150800.6" - wire $0\r_busy$next[0:0]$8380 - attribute \src "libresoc.v:150751.3-150752.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:150867.3-150885.6" - wire width 4 $1\cr_a$6$next[3:0]$8409 - attribute \src "libresoc.v:150867.3-150885.6" - wire $1\cr_a_ok$next[0:0]$8408 - attribute \src "libresoc.v:150158.7-150158.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:150814.3-150828.6" - wire width 12 $1\cr_op__fn_unit$3$next[11:0]$8390 - attribute \src "libresoc.v:150814.3-150828.6" - wire width 32 $1\cr_op__insn$4$next[31:0]$8391 - attribute \src "libresoc.v:150814.3-150828.6" - wire width 7 $1\cr_op__insn_type$2$next[6:0]$8392 - attribute \src "libresoc.v:150848.3-150866.6" - wire width 32 $1\full_cr$5$next[31:0]$8402 - attribute \src "libresoc.v:150848.3-150866.6" - wire $1\full_cr_ok$next[0:0]$8403 - attribute \src "libresoc.v:150466.7-150466.24" - wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:150801.3-150813.6" - wire width 2 $1\muxid$1$next[1:0]$8385 - attribute \src "libresoc.v:150829.3-150847.6" - wire width 64 $1\o$next[63:0]$8396 - attribute \src "libresoc.v:150702.14-150702.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:150829.3-150847.6" - wire $1\o_ok$next[0:0]$8397 - attribute \src "libresoc.v:150709.7-150709.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:150783.3-150800.6" - wire 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"TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_cr_op__fn_unit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn$10 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \main_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 \main_full_cr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 15 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 14 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 21 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 8 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:150730$8361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$13 - connect \B \p_ready_o - connect \Y $and$libresoc.v:150730$8361_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:150753.12-150774.4" - cell \main$9 \main - connect \cr_a \main_cr_a - connect \cr_a$6 \main_cr_a$12 - connect \cr_a_ok \main_cr_a_ok - connect \cr_b \main_cr_b - connect \cr_c \main_cr_c - connect \cr_op__fn_unit \main_cr_op__fn_unit - connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 - connect \cr_op__insn \main_cr_op__insn - connect \cr_op__insn$4 \main_cr_op__insn$10 - connect \cr_op__insn_type \main_cr_op__insn_type - connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 - connect \full_cr \main_full_cr - connect \full_cr$5 \main_full_cr$11 - connect \full_cr_ok \main_full_cr_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$7 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:150775.9-150778.4" - cell \n$8 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:150779.9-150782.4" - cell \p$7 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:150140.7-150140.20" - process $proc$libresoc.v:150140$8411 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:150153.13-150153.28" - process $proc$libresoc.v:150153$8412 - assign { } { } - assign $0\cr_a$6[3:0]$8413 4'0000 - sync always - sync init - update \cr_a$6 $0\cr_a$6[3:0]$8413 - end - attribute \src "libresoc.v:150158.7-150158.21" - process $proc$libresoc.v:150158$8414 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:150212.14-150212.42" - process $proc$libresoc.v:150212$8415 - assign { } { } - assign $0\cr_op__fn_unit$3[11:0]$8416 12'000000000000 - sync always - sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8416 - end - attribute \src "libresoc.v:150221.14-150221.37" - process $proc$libresoc.v:150221$8417 - assign { } { } - assign $0\cr_op__insn$4[31:0]$8418 0 - sync always - sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8418 - end - attribute \src "libresoc.v:150452.13-150452.41" - process $proc$libresoc.v:150452$8419 - assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8420 7'0000000 - sync always - sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8420 - end - attribute \src "libresoc.v:150461.14-150461.33" - process $proc$libresoc.v:150461$8421 - assign { } { } - assign $0\full_cr$5[31:0]$8422 0 - sync always - sync init - update \full_cr$5 $0\full_cr$5[31:0]$8422 - end - attribute \src "libresoc.v:150466.7-150466.24" - process $proc$libresoc.v:150466$8423 - assign { } { } - assign $1\full_cr_ok[0:0] 1'0 - sync always - sync init - update \full_cr_ok $1\full_cr_ok[0:0] - end - attribute \src "libresoc.v:150689.13-150689.29" - process $proc$libresoc.v:150689$8424 - assign { } { } - assign $0\muxid$1[1:0]$8425 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8425 - end - attribute \src "libresoc.v:150702.14-150702.38" - process $proc$libresoc.v:150702$8426 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:150709.7-150709.18" - process $proc$libresoc.v:150709$8427 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:150723.7-150723.20" - process $proc$libresoc.v:150723$8428 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:150731.3-150732.31" - process $proc$libresoc.v:150731$8362 - assign { } { } - assign $0\cr_a$6[3:0]$8363 \cr_a$6$next - sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8363 - end - attribute \src "libresoc.v:150733.3-150734.31" - process $proc$libresoc.v:150733$8364 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:150735.3-150736.37" - process $proc$libresoc.v:150735$8365 - assign { } { } - assign $0\full_cr$5[31:0]$8366 \full_cr$5$next - sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8366 - end - attribute \src "libresoc.v:150737.3-150738.37" - process $proc$libresoc.v:150737$8367 - assign { } { } - assign $0\full_cr_ok[0:0] \full_cr_ok$next - sync posedge \coresync_clk - update \full_cr_ok $0\full_cr_ok[0:0] - end - attribute \src "libresoc.v:150739.3-150740.19" - process $proc$libresoc.v:150739$8368 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:150741.3-150742.25" - process $proc$libresoc.v:150741$8369 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:150743.3-150744.55" - process $proc$libresoc.v:150743$8370 - assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8371 \cr_op__insn_type$2$next - sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8371 - end - attribute \src "libresoc.v:150745.3-150746.51" - process $proc$libresoc.v:150745$8372 - assign { } { } - assign $0\cr_op__fn_unit$3[11:0]$8373 \cr_op__fn_unit$3$next - sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8373 - end - attribute \src "libresoc.v:150747.3-150748.45" - process $proc$libresoc.v:150747$8374 - assign { } { } - assign $0\cr_op__insn$4[31:0]$8375 \cr_op__insn$4$next - sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8375 - end - attribute \src "libresoc.v:150749.3-150750.33" - process $proc$libresoc.v:150749$8376 - assign { } { } - assign $0\muxid$1[1:0]$8377 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8377 - end - attribute \src "libresoc.v:150751.3-150752.29" - process $proc$libresoc.v:150751$8378 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:150783.3-150800.6" - process $proc$libresoc.v:150783$8379 + attribute \src "libresoc.v:159655.3-159670.6" + process $proc$libresoc.v:159655$8637 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8380 $2\r_busy$next[0:0]$8382 - attribute \src "libresoc.v:150784.5-150784.29" + assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] + attribute \src "libresoc.v:159656.5-159656.29" switch \initial - attribute \src "libresoc.v:150784.9-150784.17" + attribute \src "libresoc.v:159656.9-159656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$8381 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\r_busy$next[0:0]$8381 1'0 + assign $1\lenexp_len_i[3:0] \ldst_port0_data_len case - assign $1\r_busy$next[0:0]$8381 \r_busy + assign $1\lenexp_len_i[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8382 1'0 + assign $2\lenexp_len_i[3:0] \ldst_port0_data_len case - assign $2\r_busy$next[0:0]$8382 $1\r_busy$next[0:0]$8381 + assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] end sync always - update \r_busy$next $0\r_busy$next[0:0]$8380 + update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:150801.3-150813.6" - process $proc$libresoc.v:150801$8383 + attribute \src "libresoc.v:159671.3-159686.6" + process $proc$libresoc.v:159671$8638 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8384 $1\muxid$1$next[1:0]$8385 - attribute \src "libresoc.v:150802.5-150802.29" + assign { } { } + assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] + attribute \src "libresoc.v:159672.5-159672.29" switch \initial - attribute \src "libresoc.v:150802.9-150802.17" + attribute \src "libresoc.v:159672.9-159672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\muxid$1$next[1:0]$8385 \muxid$16 + assign $1\lenexp_addr_i[3:0] \$21 + case + assign $1\lenexp_addr_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\muxid$1$next[1:0]$8385 \muxid$16 + assign $2\lenexp_addr_i[3:0] \$23 case - assign $1\muxid$1$next[1:0]$8385 \muxid$1 + assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8384 + update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:150814.3-150828.6" - process $proc$libresoc.v:150814$8386 - assign { } { } - assign { } { } + attribute \src "libresoc.v:159687.3-159712.6" + process $proc$libresoc.v:159687$8639 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\cr_op__fn_unit$3$next[11:0]$8387 $1\cr_op__fn_unit$3$next[11:0]$8390 - assign $0\cr_op__insn$4$next[31:0]$8388 $1\cr_op__insn$4$next[31:0]$8391 - assign $0\cr_op__insn_type$2$next[6:0]$8389 $1\cr_op__insn_type$2$next[6:0]$8392 - attribute \src "libresoc.v:150815.5-150815.29" + assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] + attribute \src "libresoc.v:159688.5-159688.29" switch \initial - attribute \src "libresoc.v:150815.9-150815.17" + attribute \src "libresoc.v:159688.9-159688.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } + case 1'1 assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8391 $1\cr_op__fn_unit$3$next[11:0]$8390 $1\cr_op__insn_type$2$next[6:0]$8392 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\valid_l_s_valid[0:0] 1'1 + case + assign $2\valid_l_s_valid[0:0] 1'0 + end + case + assign $1\valid_l_s_valid[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } + case 1'1 assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8391 $1\cr_op__fn_unit$3$next[11:0]$8390 $1\cr_op__insn_type$2$next[6:0]$8392 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\valid_l_s_valid[0:0] 1'1 + case + assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end case - assign $1\cr_op__fn_unit$3$next[11:0]$8390 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8391 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8392 \cr_op__insn_type$2 + assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] end sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[11:0]$8387 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8388 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8389 + update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:150829.3-150847.6" - process $proc$libresoc.v:150829$8393 + attribute \src "libresoc.v:159713.3-159738.6" + process $proc$libresoc.v:159713$8640 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\o$next[63:0]$8394 $1\o$next[63:0]$8396 - assign { } { } - assign $0\o_ok$next[0:0]$8395 $2\o_ok$next[0:0]$8398 - attribute \src "libresoc.v:150830.5-150830.29" + assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] + attribute \src "libresoc.v:159714.5-159714.29" switch \initial - attribute \src "libresoc.v:150830.9-150830.17" + attribute \src "libresoc.v:159714.9-159714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8397 $1\o$next[63:0]$8396 } { \o_ok$21 \o$20 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1'1 assign { } { } - assign { $1\o_ok$next[0:0]$8397 $1\o$next[63:0]$8396 } { \o_ok$21 \o$20 } + assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $2\x_mask_i[7:0] 8'00000000 + end case - assign $1\o$next[63:0]$8396 \o - assign $1\o_ok$next[0:0]$8397 \o_ok + assign $1\x_mask_i[7:0] 8'00000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8398 1'0 + assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] + end case - assign $2\o_ok$next[0:0]$8398 $1\o_ok$next[0:0]$8397 + assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] end sync always - update \o$next $0\o$next[63:0]$8394 - update \o_ok$next $0\o_ok$next[0:0]$8395 + update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:150848.3-150866.6" - process $proc$libresoc.v:150848$8399 + attribute \src "libresoc.v:159739.3-159764.6" + process $proc$libresoc.v:159739$8641 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\full_cr$5$next[31:0]$8400 $1\full_cr$5$next[31:0]$8402 - assign { } { } - assign $0\full_cr_ok$next[0:0]$8401 $2\full_cr_ok$next[0:0]$8404 - attribute \src "libresoc.v:150849.5-150849.29" + assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] + attribute \src "libresoc.v:159740.5-159740.29" switch \initial - attribute \src "libresoc.v:150849.9-150849.17" + attribute \src "libresoc.v:159740.9-159740.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\full_cr_ok$next[0:0]$8403 $1\full_cr$5$next[31:0]$8402 } { \full_cr_ok$23 \full_cr$22 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1'1 assign { } { } - assign { $1\full_cr_ok$next[0:0]$8403 $1\full_cr$5$next[31:0]$8402 } { \full_cr_ok$23 \full_cr$22 } + assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end case - assign $1\full_cr$5$next[31:0]$8402 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8403 \full_cr_ok + assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\full_cr_ok$next[0:0]$8404 1'0 + assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] + end case - assign $2\full_cr_ok$next[0:0]$8404 $1\full_cr_ok$next[0:0]$8403 + assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] end sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8400 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8401 + update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:150867.3-150885.6" - process $proc$libresoc.v:150867$8405 + attribute \src "libresoc.v:159765.3-159795.6" + process $proc$libresoc.v:159765$8642 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$6$next[3:0]$8407 $1\cr_a$6$next[3:0]$8409 - assign $0\cr_a_ok$next[0:0]$8406 $2\cr_a_ok$next[0:0]$8410 - attribute \src "libresoc.v:150868.5-150868.29" + assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:159766.5-159766.29" switch \initial - attribute \src "libresoc.v:150868.9-150868.17" + attribute \src "libresoc.v:159766.9-159766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8408 $1\cr_a$6$next[3:0]$8409 } { \cr_a_ok$25 \cr_a$24 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1'1 assign { } { } - assign { $1\cr_a_ok$next[0:0]$8408 $1\cr_a$6$next[3:0]$8409 } { \cr_a_ok$25 \cr_a$24 } + assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $2\ldst_port0_addr_ok_o[0:0] 1'0 + end case - assign $1\cr_a_ok$next[0:0]$8408 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8409 \cr_a$6 + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8410 1'0 + assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end case - assign $2\cr_a_ok$next[0:0]$8410 $1\cr_a_ok$next[0:0]$8408 + assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8406 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8407 - end - connect \$14 $and$libresoc.v:150730$8361_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } - connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } - connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } - connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } - connect \muxid$16 \main_muxid$7 - connect \p_valid_i_p_ready_o \$14 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$13 \p_valid_i - connect \main_cr_c \cr_c - connect \main_cr_b \cr_b - connect \main_cr_a \cr_a - connect \main_full_cr \full_cr - connect \main_rb \rb - connect \main_ra \ra - connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - connect \main_muxid \muxid -end -attribute \src "libresoc.v:150908.1-151753.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" -attribute \generator "nMigen" -module \pipe$19 - attribute \src "libresoc.v:151653.3-151680.6" - wire width 64 $0\br_op__cia$2$next[63:0]$8465 - attribute \src "libresoc.v:151565.3-151566.43" - wire width 64 $0\br_op__cia$2[63:0]$8439 - attribute \src "libresoc.v:150916.14-150916.51" - wire width 64 $0\br_op__cia$2[63:0]$8503 - attribute \src "libresoc.v:151653.3-151680.6" - wire width 12 $0\br_op__fn_unit$4$next[11:0]$8466 - attribute \src "libresoc.v:151569.3-151570.51" - wire width 12 $0\br_op__fn_unit$4[11:0]$8443 - attribute \src "libresoc.v:150966.14-150966.42" - wire width 12 $0\br_op__fn_unit$4[11:0]$8505 - attribute \src "libresoc.v:151653.3-151680.6" - wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8467 - attribute \src "libresoc.v:151573.3-151574.65" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8447 - attribute \src "libresoc.v:150975.14-150975.62" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8507 - attribute \src "libresoc.v:151653.3-151680.6" - wire $0\br_op__imm_data__ok$7$next[0:0]$8468 - attribute \src "libresoc.v:151575.3-151576.61" - wire $0\br_op__imm_data__ok$7[0:0]$8449 - attribute \src "libresoc.v:150984.7-150984.37" - wire $0\br_op__imm_data__ok$7[0:0]$8509 - attribute \src "libresoc.v:151653.3-151680.6" - wire width 32 $0\br_op__insn$5$next[31:0]$8469 - attribute \src "libresoc.v:151571.3-151572.45" - wire width 32 $0\br_op__insn$5[31:0]$8445 - attribute \src "libresoc.v:150993.14-150993.37" - wire width 32 $0\br_op__insn$5[31:0]$8511 - attribute \src "libresoc.v:151653.3-151680.6" - wire width 7 $0\br_op__insn_type$3$next[6:0]$8470 - attribute \src "libresoc.v:151567.3-151568.55" - wire width 7 $0\br_op__insn_type$3[6:0]$8441 - attribute \src "libresoc.v:151224.13-151224.41" - wire width 7 $0\br_op__insn_type$3[6:0]$8513 - attribute \src "libresoc.v:151653.3-151680.6" - wire $0\br_op__is_32bit$9$next[0:0]$8471 - attribute \src "libresoc.v:151579.3-151580.53" - wire $0\br_op__is_32bit$9[0:0]$8453 - attribute \src "libresoc.v:151233.7-151233.33" - wire $0\br_op__is_32bit$9[0:0]$8515 - attribute \src "libresoc.v:151653.3-151680.6" - wire $0\br_op__lk$8$next[0:0]$8472 - attribute \src "libresoc.v:151577.3-151578.41" - wire $0\br_op__lk$8[0:0]$8451 - attribute \src "libresoc.v:151242.7-151242.27" - wire $0\br_op__lk$8[0:0]$8517 - attribute \src "libresoc.v:151681.3-151699.6" - wire width 64 $0\fast1$10$next[63:0]$8484 - attribute \src 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\br_op__lk$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 15 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 27 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 29 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast2$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast2$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast2_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast2_ok$next - attribute \src "libresoc.v:150909.7-150909.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__cia$13 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_br_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_br_op__fn_unit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__imm_data__data$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__imm_data__ok$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_br_op__insn$16 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute 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attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute 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\enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_br_op__insn_type$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__lk$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_fast1$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_fast2$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 17 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 16 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 31 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \nia_ok - attribute \src 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parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 - connect \B \p_ready_o - connect \Y $and$libresoc.v:151552$8429_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:151585.13-151613.4" - cell \main$22 \main - connect \br_op__cia \main_br_op__cia - connect \br_op__cia$2 \main_br_op__cia$13 - connect \br_op__fn_unit \main_br_op__fn_unit - connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 - connect \br_op__imm_data__data \main_br_op__imm_data__data - connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 - connect \br_op__imm_data__ok \main_br_op__imm_data__ok - connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 - connect \br_op__insn \main_br_op__insn - connect \br_op__insn$5 \main_br_op__insn$16 - connect \br_op__insn_type \main_br_op__insn_type - connect \br_op__insn_type$3 \main_br_op__insn_type$14 - connect \br_op__is_32bit \main_br_op__is_32bit - connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 - connect \br_op__lk \main_br_op__lk - connect \br_op__lk$8 \main_br_op__lk$19 - connect \cr_a \main_cr_a - connect \fast1 \main_fast1 - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2 \main_fast2 - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$12 - connect \nia \main_nia - connect \nia_ok \main_nia_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:151614.10-151617.4" - cell \n$21 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:151618.10-151621.4" - cell \p$20 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:150909.7-150909.20" - process $proc$libresoc.v:150909$8501 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:150916.14-150916.51" - process $proc$libresoc.v:150916$8502 - assign { } { } - assign $0\br_op__cia$2[63:0]$8503 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8503 - end - attribute \src "libresoc.v:150966.14-150966.42" - process $proc$libresoc.v:150966$8504 - assign { } { } - assign $0\br_op__fn_unit$4[11:0]$8505 12'000000000000 - sync always - sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8505 - end - attribute \src "libresoc.v:150975.14-150975.62" - process $proc$libresoc.v:150975$8506 - assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8507 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8507 - end - attribute \src "libresoc.v:150984.7-150984.37" - process $proc$libresoc.v:150984$8508 - assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8509 1'0 - sync always - sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8509 - end - attribute \src "libresoc.v:150993.14-150993.37" - process $proc$libresoc.v:150993$8510 - assign { } { } - assign $0\br_op__insn$5[31:0]$8511 0 - sync always - sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8511 - end - attribute \src "libresoc.v:151224.13-151224.41" - process $proc$libresoc.v:151224$8512 - assign { } { } - assign $0\br_op__insn_type$3[6:0]$8513 7'0000000 - sync always - sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8513 - end - attribute \src "libresoc.v:151233.7-151233.33" - process $proc$libresoc.v:151233$8514 - assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8515 1'0 - sync always - sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8515 + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:151242.7-151242.27" - process $proc$libresoc.v:151242$8516 + attribute \src "libresoc.v:159796.3-159811.6" + process $proc$libresoc.v:159796$8643 assign { } { } - assign $0\br_op__lk$8[0:0]$8517 1'0 - sync always - sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8517 - end - attribute \src "libresoc.v:151255.14-151255.47" - process $proc$libresoc.v:151255$8518 assign { } { } - assign $0\fast1$10[63:0]$8519 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$10 $0\fast1$10[63:0]$8519 - end - attribute \src "libresoc.v:151262.7-151262.22" - process $proc$libresoc.v:151262$8520 assign { } { } - assign $1\fast1_ok[0:0] 1'0 + assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:159797.5-159797.29" + switch \initial + attribute \src "libresoc.v:159797.9-159797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] \$35 + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" + switch \st_done_q_st_done + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] \$37 + case + assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + end sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] + update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:151271.14-151271.47" - process $proc$libresoc.v:151271$8521 + attribute \src "libresoc.v:159812.3-159821.6" + process $proc$libresoc.v:159812$8644 assign { } { } - assign $0\fast2$11[63:0]$8522 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast2$11 $0\fast2$11[63:0]$8522 - end - attribute \src "libresoc.v:151278.7-151278.22" - process $proc$libresoc.v:151278$8523 assign { } { } - assign $1\fast2_ok[0:0] 1'0 + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:159813.5-159813.29" + switch \initial + attribute \src "libresoc.v:159813.9-159813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end sync always - sync init - update \fast2_ok $1\fast2_ok[0:0] + update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:151515.13-151515.29" - process $proc$libresoc.v:151515$8524 + attribute \src "libresoc.v:159822.3-159831.6" + process $proc$libresoc.v:159822$8645 assign { } { } - assign $0\muxid$1[1:0]$8525 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8525 - end - attribute \src "libresoc.v:151528.14-151528.40" - process $proc$libresoc.v:151528$8526 assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:159823.5-159823.29" + switch \initial + attribute \src "libresoc.v:159823.9-159823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o[63:0] \lddata + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end sync always - sync init - update \nia $1\nia[63:0] + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:151535.7-151535.20" - process $proc$libresoc.v:151535$8527 + attribute \src "libresoc.v:159832.3-159841.6" + process $proc$libresoc.v:159832$8646 assign { } { } - assign $1\nia_ok[0:0] 1'0 - sync always - sync init - update \nia_ok $1\nia_ok[0:0] - end - attribute \src "libresoc.v:151549.7-151549.20" - process $proc$libresoc.v:151549$8528 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:159833.5-159833.29" + switch \initial + attribute \src "libresoc.v:159833.9-159833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ld_active_r_ld_active[0:0] 1'1 + case + assign $1\ld_active_r_ld_active[0:0] 1'0 + end sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:151553.3-151554.23" - process $proc$libresoc.v:151553$8430 - assign { } { } - assign $0\nia[63:0] \nia$next - sync posedge \coresync_clk - update \nia $0\nia[63:0] - end - attribute \src "libresoc.v:151555.3-151556.29" - process $proc$libresoc.v:151555$8431 - assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next - sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] - end - attribute \src "libresoc.v:151557.3-151558.35" - process $proc$libresoc.v:151557$8432 - assign { } { } - assign $0\fast2$11[63:0]$8433 \fast2$11$next - sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8433 - end - attribute \src "libresoc.v:151559.3-151560.33" - process $proc$libresoc.v:151559$8434 - assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next - sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "libresoc.v:151561.3-151562.35" - process $proc$libresoc.v:151561$8435 - assign { } { } - assign $0\fast1$10[63:0]$8436 \fast1$10$next - sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8436 - end - attribute \src "libresoc.v:151563.3-151564.33" - process $proc$libresoc.v:151563$8437 - assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next - sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "libresoc.v:151565.3-151566.43" - process $proc$libresoc.v:151565$8438 - assign { } { } - assign $0\br_op__cia$2[63:0]$8439 \br_op__cia$2$next - sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8439 - end - attribute \src "libresoc.v:151567.3-151568.55" - process $proc$libresoc.v:151567$8440 - assign { } { } - assign $0\br_op__insn_type$3[6:0]$8441 \br_op__insn_type$3$next - sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8441 - end - attribute \src "libresoc.v:151569.3-151570.51" - process $proc$libresoc.v:151569$8442 - assign { } { } - assign $0\br_op__fn_unit$4[11:0]$8443 \br_op__fn_unit$4$next - sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8443 - end - attribute \src "libresoc.v:151571.3-151572.45" - process $proc$libresoc.v:151571$8444 - assign { } { } - assign $0\br_op__insn$5[31:0]$8445 \br_op__insn$5$next - sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8445 - end - attribute \src "libresoc.v:151573.3-151574.65" - process $proc$libresoc.v:151573$8446 - assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8447 \br_op__imm_data__data$6$next - sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8447 - end - attribute \src "libresoc.v:151575.3-151576.61" - process $proc$libresoc.v:151575$8448 - assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8449 \br_op__imm_data__ok$7$next - sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8449 - end - attribute \src "libresoc.v:151577.3-151578.41" - process $proc$libresoc.v:151577$8450 - assign { } { } - assign $0\br_op__lk$8[0:0]$8451 \br_op__lk$8$next - sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8451 - end - attribute \src "libresoc.v:151579.3-151580.53" - process $proc$libresoc.v:151579$8452 - assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8453 \br_op__is_32bit$9$next - sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8453 + update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:151581.3-151582.33" - process $proc$libresoc.v:151581$8454 + attribute \src "libresoc.v:159842.3-159851.6" + process $proc$libresoc.v:159842$8647 assign { } { } - assign $0\muxid$1[1:0]$8455 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8455 - end - attribute \src "libresoc.v:151583.3-151584.29" - process $proc$libresoc.v:151583$8456 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:159843.5-159843.29" + switch \initial + attribute \src "libresoc.v:159843.9-159843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$50 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 + case + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:151622.3-151639.6" - process $proc$libresoc.v:151622$8457 - assign { } { } + attribute \src "libresoc.v:159852.3-159861.6" + process $proc$libresoc.v:159852$8648 assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8458 $2\r_busy$next[0:0]$8460 - attribute \src "libresoc.v:151623.5-151623.29" + assign $0\stdata[63:0] $1\stdata[63:0] + attribute \src "libresoc.v:159853.5-159853.29" switch \initial - attribute \src "libresoc.v:151623.9-151623.17" + attribute \src "libresoc.v:159853.9-159853.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$8459 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$54 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\r_busy$next[0:0]$8459 1'0 + assign $1\stdata[63:0] \$56 [63:0] case - assign $1\r_busy$next[0:0]$8459 \r_busy + assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + sync always + update \stdata $0\stdata[63:0] + end + attribute \src "libresoc.v:159862.3-159871.6" + process $proc$libresoc.v:159862$8649 + assign { } { } + assign { } { } + assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] + attribute \src "libresoc.v:159863.5-159863.29" + switch \initial + attribute \src "libresoc.v:159863.9-159863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8460 1'0 + assign $1\x_st_data_i[63:0] \stdata case - assign $2\r_busy$next[0:0]$8460 $1\r_busy$next[0:0]$8459 + assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8458 + update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:151640.3-151652.6" - process $proc$libresoc.v:151640$8461 + attribute \src "libresoc.v:159872.3-159891.6" + process $proc$libresoc.v:159872$8650 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8462 $1\muxid$1$next[1:0]$8463 - attribute \src "libresoc.v:151641.5-151641.29" + assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] + attribute \src "libresoc.v:159873.5-159873.29" switch \initial - attribute \src "libresoc.v:151641.9-151641.17" + attribute \src "libresoc.v:159873.9-159873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 2'00 assign { } { } - assign $1\muxid$1$next[1:0]$8463 \muxid$26 + assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lsui_busy[0:0] 1'1 + case + assign $2\lsui_busy[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 2'01 assign { } { } - assign $1\muxid$1$next[1:0]$8463 \muxid$26 + assign $1\lsui_busy[0:0] 1'1 case - assign $1\muxid$1$next[1:0]$8463 \muxid$1 + assign $1\lsui_busy[0:0] 1'0 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8462 + update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:151653.3-151680.6" - process $proc$libresoc.v:151653$8464 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:159892.3-159930.6" + process $proc$libresoc.v:159892$8651 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\br_op__cia$2$next[63:0]$8465 $1\br_op__cia$2$next[63:0]$8473 - assign $0\br_op__fn_unit$4$next[11:0]$8466 $1\br_op__fn_unit$4$next[11:0]$8474 - assign { } { } - assign { } { } - assign $0\br_op__insn$5$next[31:0]$8469 $1\br_op__insn$5$next[31:0]$8477 - assign $0\br_op__insn_type$3$next[6:0]$8470 $1\br_op__insn_type$3$next[6:0]$8478 - assign $0\br_op__is_32bit$9$next[0:0]$8471 $1\br_op__is_32bit$9$next[0:0]$8479 - assign $0\br_op__lk$8$next[0:0]$8472 $1\br_op__lk$8$next[0:0]$8480 - assign $0\br_op__imm_data__data$6$next[63:0]$8467 $2\br_op__imm_data__data$6$next[63:0]$8481 - assign $0\br_op__imm_data__ok$7$next[0:0]$8468 $2\br_op__imm_data__ok$7$next[0:0]$8482 - attribute \src "libresoc.v:151654.5-151654.29" + assign $0\fsm_state$next[1:0]$8652 $5\fsm_state$next[1:0]$8657 + attribute \src "libresoc.v:159893.5-159893.29" switch \initial - attribute \src "libresoc.v:151654.9-151654.17" + attribute \src "libresoc.v:159893.9-159893.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 2'00 assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8479 $1\br_op__lk$8$next[0:0]$8480 $1\br_op__imm_data__ok$7$next[0:0]$8476 $1\br_op__imm_data__data$6$next[63:0]$8475 $1\br_op__insn$5$next[31:0]$8477 $1\br_op__fn_unit$4$next[11:0]$8474 $1\br_op__insn_type$3$next[6:0]$8478 $1\br_op__cia$2$next[63:0]$8473 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign $1\fsm_state$next[1:0]$8653 $2\fsm_state$next[1:0]$8654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$8654 2'01 + case + assign $2\fsm_state$next[1:0]$8654 \fsm_state + end attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 2'01 assign { } { } + assign $1\fsm_state$next[1:0]$8653 $3\fsm_state$next[1:0]$8655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[1:0]$8655 2'10 + case + assign $3\fsm_state$next[1:0]$8655 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8479 $1\br_op__lk$8$next[0:0]$8480 $1\br_op__imm_data__ok$7$next[0:0]$8476 $1\br_op__imm_data__data$6$next[63:0]$8475 $1\br_op__insn$5$next[31:0]$8477 $1\br_op__fn_unit$4$next[11:0]$8474 $1\br_op__insn_type$3$next[6:0]$8478 $1\br_op__cia$2$next[63:0]$8473 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign $1\fsm_state$next[1:0]$8653 $4\fsm_state$next[1:0]$8656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$8656 2'00 + case + assign $4\fsm_state$next[1:0]$8656 \fsm_state + end case - assign $1\br_op__cia$2$next[63:0]$8473 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[11:0]$8474 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8475 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8476 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8477 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8478 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8479 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8480 \br_op__lk$8 + assign $1\fsm_state$next[1:0]$8653 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8481 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8482 1'0 + assign $5\fsm_state$next[1:0]$8657 2'00 case - assign $2\br_op__imm_data__data$6$next[63:0]$8481 $1\br_op__imm_data__data$6$next[63:0]$8475 - assign $2\br_op__imm_data__ok$7$next[0:0]$8482 $1\br_op__imm_data__ok$7$next[0:0]$8476 + assign $5\fsm_state$next[1:0]$8657 $1\fsm_state$next[1:0]$8653 end sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8465 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[11:0]$8466 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8467 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8468 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8469 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8470 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8471 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8472 + update \fsm_state$next $0\fsm_state$next[1:0]$8652 end - attribute \src "libresoc.v:151681.3-151699.6" - process $proc$libresoc.v:151681$8483 - assign { } { } + attribute \src "libresoc.v:159931.3-159940.6" + process $proc$libresoc.v:159931$8658 assign { } { } assign { } { } + assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:159932.5-159932.29" + switch \initial + attribute \src "libresoc.v:159932.9-159932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" + switch \reset_l_s_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_s_cyc[0:0] 1'1 + case + assign $1\cyc_l_s_cyc[0:0] 1'0 + end + sync always + update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] + end + attribute \src "libresoc.v:159941.3-159949.6" + process $proc$libresoc.v:159941$8659 assign { } { } - assign $0\fast1$10$next[63:0]$8484 $1\fast1$10$next[63:0]$8486 assign { } { } - assign $0\fast1_ok$next[0:0]$8485 $2\fast1_ok$next[0:0]$8488 - attribute \src "libresoc.v:151682.5-151682.29" + assign $0\lsui_active_dly$next[0:0]$8660 $1\lsui_active_dly$next[0:0]$8661 + attribute \src "libresoc.v:159942.5-159942.29" switch \initial - attribute \src "libresoc.v:151682.9-151682.17" + attribute \src "libresoc.v:159942.9-159942.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } + assign $1\lsui_active_dly$next[0:0]$8661 1'0 + case + assign $1\lsui_active_dly$next[0:0]$8661 \lsui_active + end + sync always + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8660 + end + attribute \src "libresoc.v:159950.3-159959.6" + process $proc$libresoc.v:159950$8662 + assign { } { } + assign { } { } + assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:159951.5-159951.29" + switch \initial + attribute \src "libresoc.v:159951.9-159951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { $1\fast1_ok$next[0:0]$8487 $1\fast1$10$next[63:0]$8486 } { \fast1_ok$36 \fast1$35 } + assign $1\cyc_l_r_cyc[0:0] 1'1 + case + assign $1\cyc_l_r_cyc[0:0] 1'0 + end + sync always + update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] + end + attribute \src "libresoc.v:159960.3-159969.6" + process $proc$libresoc.v:159960$8663 + assign { } { } + assign { } { } + assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] + attribute \src "libresoc.v:159961.5-159961.29" + switch \initial + attribute \src "libresoc.v:159961.9-159961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch \$3 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } + assign $1\busy_l_s_busy[0:0] \$5 + case + assign $1\busy_l_s_busy[0:0] 1'0 + end + sync always + update \busy_l_s_busy $0\busy_l_s_busy[0:0] + end + attribute \src "libresoc.v:159970.3-159985.6" + process $proc$libresoc.v:159970$8664 + assign { } { } + assign { } { } + assign { } { } + assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] + attribute \src "libresoc.v:159971.5-159971.29" + switch \initial + attribute \src "libresoc.v:159971.9-159971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" + switch \ldst_port0_exc_$signal + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { $1\fast1_ok$next[0:0]$8487 $1\fast1$10$next[63:0]$8486 } { \fast1_ok$36 \fast1$35 } + assign $1\busy_l_r_busy[0:0] 1'1 case - assign $1\fast1$10$next[63:0]$8486 \fast1$10 - assign $1\fast1_ok$next[0:0]$8487 \fast1_ok + assign $1\busy_l_r_busy[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8488 1'0 + assign $2\busy_l_r_busy[0:0] 1'1 case - assign $2\fast1_ok$next[0:0]$8488 $1\fast1_ok$next[0:0]$8487 + assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8484 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8485 + update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:151700.3-151718.6" - process $proc$libresoc.v:151700$8489 + attribute \src "libresoc.v:159986.3-160021.6" + process $proc$libresoc.v:159986$8665 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8490 $1\fast2$11$next[63:0]$8492 - assign { } { } - assign $0\fast2_ok$next[0:0]$8491 $2\fast2_ok$next[0:0]$8494 - attribute \src "libresoc.v:151701.5-151701.29" + assign $0\adrok_l_s_addr_acked$next[0:0]$8666 $6\adrok_l_s_addr_acked$next[0:0]$8672 + attribute \src "libresoc.v:159987.5-159987.29" switch \initial - attribute \src "libresoc.v:151701.9-151701.17" + attribute \src "libresoc.v:159987.9-159987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } + case 1'1 assign { } { } - assign { $1\fast2_ok$next[0:0]$8493 $1\fast2$11$next[63:0]$8492 } { \fast2_ok$38 \fast2$37 } + assign $1\adrok_l_s_addr_acked$next[0:0]$8667 $2\adrok_l_s_addr_acked$next[0:0]$8668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_s_addr_acked$next[0:0]$8668 1'1 + case + assign $2\adrok_l_s_addr_acked$next[0:0]$8668 1'0 + end + case + assign $1\adrok_l_s_addr_acked$next[0:0]$8667 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1'1 assign { } { } - assign { $1\fast2_ok$next[0:0]$8493 $1\fast2$11$next[63:0]$8492 } { \fast2_ok$38 \fast2$37 } + assign $3\adrok_l_s_addr_acked$next[0:0]$8669 $4\adrok_l_s_addr_acked$next[0:0]$8670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\adrok_l_s_addr_acked$next[0:0]$8670 $5\adrok_l_s_addr_acked$next[0:0]$8671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\adrok_l_s_addr_acked$next[0:0]$8671 1'1 + case + assign $5\adrok_l_s_addr_acked$next[0:0]$8671 $1\adrok_l_s_addr_acked$next[0:0]$8667 + end + case + assign $4\adrok_l_s_addr_acked$next[0:0]$8670 $1\adrok_l_s_addr_acked$next[0:0]$8667 + end case - assign $1\fast2$11$next[63:0]$8492 \fast2$11 - assign $1\fast2_ok$next[0:0]$8493 \fast2_ok + assign $3\adrok_l_s_addr_acked$next[0:0]$8669 $1\adrok_l_s_addr_acked$next[0:0]$8667 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8494 1'0 + assign $6\adrok_l_s_addr_acked$next[0:0]$8672 1'0 case - assign $2\fast2_ok$next[0:0]$8494 $1\fast2_ok$next[0:0]$8493 + assign $6\adrok_l_s_addr_acked$next[0:0]$8672 $3\adrok_l_s_addr_acked$next[0:0]$8669 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8490 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8491 + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8666 end - attribute \src "libresoc.v:151719.3-151737.6" - process $proc$libresoc.v:151719$8495 - assign { } { } + attribute \src "libresoc.v:160022.3-160037.6" + process $proc$libresoc.v:160022$8673 assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8496 $1\nia$next[63:0]$8498 - assign { } { } - assign $0\nia_ok$next[0:0]$8497 $2\nia_ok$next[0:0]$8500 - attribute \src "libresoc.v:151720.5-151720.29" + assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:160023.5-160023.29" switch \initial - attribute \src "libresoc.v:151720.9-151720.17" + attribute \src "libresoc.v:160023.9-160023.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\nia_ok$next[0:0]$8499 $1\nia$next[63:0]$8498 } { \nia_ok$40 \nia$39 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" + switch \reset_delay attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1'1 assign { } { } - assign { $1\nia_ok$next[0:0]$8499 $1\nia$next[63:0]$8498 } { \nia_ok$40 \nia$39 } + assign $1\adrok_l_r_addr_acked[0:0] 1'1 case - assign $1\nia$next[63:0]$8498 \nia - assign $1\nia_ok$next[0:0]$8499 \nia_ok + assign $1\adrok_l_r_addr_acked[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8500 1'0 + assign $2\adrok_l_r_addr_acked[0:0] 1'1 case - assign $2\nia_ok$next[0:0]$8500 $1\nia_ok$next[0:0]$8499 + assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] end sync always - update \nia$next $0\nia$next[63:0]$8496 - update \nia_ok$next $0\nia_ok$next[0:0]$8497 + update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$24 $and$libresoc.v:151552$8429_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } - connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } - connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } - connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } - connect \muxid$26 \main_muxid$12 - connect \p_valid_i_p_ready_o \$24 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$23 \p_valid_i - connect \main_cr_a \cr_a - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \main_muxid \muxid + connect \$9 $not$libresoc.v:159491$8577_Y + connect \$11 $and$libresoc.v:159492$8578_Y + connect \$13 $not$libresoc.v:159493$8579_Y + connect \$15 $and$libresoc.v:159494$8580_Y + connect \$17 $not$libresoc.v:159495$8581_Y + connect \$1 $and$libresoc.v:159496$8582_Y + connect \$19 $and$libresoc.v:159497$8583_Y + connect \$21 $pos$libresoc.v:159498$8585_Y + connect \$23 $pos$libresoc.v:159499$8587_Y + connect \$25 $and$libresoc.v:159500$8588_Y + connect \$27 $and$libresoc.v:159501$8589_Y + connect \$29 $and$libresoc.v:159502$8590_Y + connect \$31 $and$libresoc.v:159503$8591_Y + connect \$33 $and$libresoc.v:159504$8592_Y + connect \$35 $not$libresoc.v:159505$8593_Y + connect \$38 $or$libresoc.v:159506$8594_Y + connect \$3 $or$libresoc.v:159507$8595_Y + connect \$37 $not$libresoc.v:159508$8596_Y + connect \$42 $and$libresoc.v:159509$8597_Y + connect \$44 $mul$libresoc.v:159510$8598_Y + connect \$46 $sshr$libresoc.v:159511$8599_Y + connect \$48 $and$libresoc.v:159512$8600_Y + connect \$50 $and$libresoc.v:159513$8601_Y + connect \$52 $not$libresoc.v:159514$8602_Y + connect \$54 $and$libresoc.v:159515$8603_Y + connect \$57 $mul$libresoc.v:159516$8604_Y + connect \$5 $not$libresoc.v:159517$8605_Y + connect \$59 $sshl$libresoc.v:159518$8606_Y + connect \$61 $and$libresoc.v:159519$8607_Y + connect \$63 $or$libresoc.v:159520$8608_Y + connect \$65 $and$libresoc.v:159521$8609_Y + connect \$67 $or$libresoc.v:159522$8610_Y + connect \$69 $and$libresoc.v:159523$8611_Y + connect \$71 $not$libresoc.v:159524$8612_Y + connect \$73 $not$libresoc.v:159525$8613_Y + connect \$75 $not$libresoc.v:159526$8614_Y + connect \$77 $and$libresoc.v:159527$8615_Y + connect \$7 $and$libresoc.v:159528$8616_Y + connect \$79 $not$libresoc.v:159529$8617_Y + connect \$81 $not$libresoc.v:159530$8618_Y + connect \$83 $and$libresoc.v:159531$8619_Y + connect \$41 \$46 + connect \$56 \$59 + connect \valid_l_r_valid \lsui_active_rise + connect \lsui_active_rise \$83 + connect \lsui_active \$79 + connect \x_valid_i \valid_l_q_valid + connect \m_valid_i \valid_l_q_valid + connect \x_st_i \ldst_port0_is_st_i + connect \x_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_busy_o \busy_l_q_busy + connect \reset_delay$next \reset_l_q_reset + connect \lddata \$46 [63:0] + connect \st_active_s_st_active \sts_rise + connect \sts_rise \$19 + connect \sts_dly$next \sts + connect \ld_active_s_ld_active \lds_rise + connect \lds_rise \$15 + connect \lds_dly$next \lds + connect \busy_edge \$11 + connect \sts \ldst_port0_is_st_i + connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:151757.1-152672.10" +attribute \src "libresoc.v:160063.1-160843.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" -module \pipe$64 - attribute \src "libresoc.v:152575.3-152593.6" - wire width 64 $0\fast1$7$next[63:0]$8588 - attribute \src "libresoc.v:152428.3-152429.33" - wire width 64 $0\fast1$7[63:0]$8540 - attribute \src "libresoc.v:151771.14-151771.46" - wire width 64 $0\fast1$7[63:0]$8612 - attribute \src "libresoc.v:152575.3-152593.6" - wire $0\fast1_ok$next[0:0]$8587 - attribute \src "libresoc.v:152430.3-152431.33" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:151758.7-151758.20" +module \pipe + attribute \src "libresoc.v:160806.3-160824.6" + wire width 4 $0\cr_a$6$next[3:0]$8729 + attribute \src "libresoc.v:160670.3-160671.31" + wire width 4 $0\cr_a$6[3:0]$8685 + attribute \src "libresoc.v:160077.13-160077.28" + wire width 4 $0\cr_a$6[3:0]$8735 + attribute \src "libresoc.v:160806.3-160824.6" + wire $0\cr_a_ok$next[0:0]$8728 + attribute \src "libresoc.v:160672.3-160673.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:160753.3-160767.6" + wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8709 + attribute \src "libresoc.v:160684.3-160685.51" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8695 + attribute \src "libresoc.v:160142.14-160142.43" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8738 + attribute \src "libresoc.v:160753.3-160767.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8710 + attribute \src "libresoc.v:160686.3-160687.45" + wire width 32 $0\cr_op__insn$4[31:0]$8697 + attribute \src "libresoc.v:160151.14-160151.37" + wire width 32 $0\cr_op__insn$4[31:0]$8740 + attribute \src "libresoc.v:160753.3-160767.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8711 + attribute \src "libresoc.v:160682.3-160683.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8693 + attribute \src "libresoc.v:160385.13-160385.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8742 + attribute \src "libresoc.v:160787.3-160805.6" + wire width 32 $0\full_cr$5$next[31:0]$8722 + attribute \src "libresoc.v:160674.3-160675.37" + wire width 32 $0\full_cr$5[31:0]$8688 + attribute \src "libresoc.v:160394.14-160394.33" + wire width 32 $0\full_cr$5[31:0]$8744 + attribute \src "libresoc.v:160787.3-160805.6" + wire $0\full_cr_ok$next[0:0]$8723 + attribute \src "libresoc.v:160676.3-160677.37" + wire $0\full_cr_ok[0:0] + attribute \src "libresoc.v:160064.7-160064.20" wire $0\initial[0:0] - attribute \src "libresoc.v:152508.3-152520.6" - wire width 2 $0\muxid$1$next[1:0]$8563 - attribute \src "libresoc.v:152448.3-152449.33" - wire width 2 $0\muxid$1[1:0]$8556 - attribute \src "libresoc.v:151785.13-151785.29" - wire width 2 $0\muxid$1[1:0]$8615 - attribute \src "libresoc.v:152537.3-152555.6" - wire width 64 $0\o$next[63:0]$8575 - attribute \src "libresoc.v:152436.3-152437.19" + attribute \src "libresoc.v:160740.3-160752.6" + wire width 2 $0\muxid$1$next[1:0]$8706 + attribute \src "libresoc.v:160688.3-160689.33" + wire width 2 $0\muxid$1[1:0]$8699 + attribute \src "libresoc.v:160628.13-160628.29" + wire width 2 $0\muxid$1[1:0]$8747 + attribute \src "libresoc.v:160768.3-160786.6" + wire width 64 $0\o$next[63:0]$8716 + attribute \src "libresoc.v:160678.3-160679.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:152537.3-152555.6" - wire $0\o_ok$next[0:0]$8576 - attribute \src "libresoc.v:152438.3-152439.25" + attribute \src "libresoc.v:160768.3-160786.6" + wire $0\o_ok$next[0:0]$8717 + attribute \src "libresoc.v:160680.3-160681.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:152490.3-152507.6" - wire $0\r_busy$next[0:0]$8559 - attribute \src "libresoc.v:152450.3-152451.29" + attribute \src "libresoc.v:160722.3-160739.6" + wire $0\r_busy$next[0:0]$8702 + attribute \src "libresoc.v:160690.3-160691.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:152556.3-152574.6" - wire width 64 $0\spr1$6$next[63:0]$8581 - attribute \src "libresoc.v:152432.3-152433.31" - wire width 64 $0\spr1$6[63:0]$8543 - attribute \src "libresoc.v:151830.14-151830.45" - wire width 64 $0\spr1$6[63:0]$8620 - attribute \src "libresoc.v:152556.3-152574.6" - wire $0\spr1_ok$next[0:0]$8582 - attribute \src "libresoc.v:152434.3-152435.31" - wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:152521.3-152536.6" - wire width 12 $0\spr_op__fn_unit$3$next[11:0]$8566 - attribute \src "libresoc.v:152442.3-152443.53" - wire width 12 $0\spr_op__fn_unit$3[11:0]$8550 - attribute \src "libresoc.v:152115.14-152115.43" - wire width 12 $0\spr_op__fn_unit$3[11:0]$8623 - attribute \src "libresoc.v:152521.3-152536.6" - wire width 32 $0\spr_op__insn$4$next[31:0]$8567 - attribute \src "libresoc.v:152444.3-152445.47" - wire width 32 $0\spr_op__insn$4[31:0]$8552 - attribute \src "libresoc.v:152124.14-152124.38" - wire width 32 $0\spr_op__insn$4[31:0]$8625 - attribute \src "libresoc.v:152521.3-152536.6" - wire width 7 $0\spr_op__insn_type$2$next[6:0]$8568 - attribute \src "libresoc.v:152440.3-152441.57" - wire width 7 $0\spr_op__insn_type$2[6:0]$8548 - attribute \src "libresoc.v:152279.13-152279.42" - wire width 7 $0\spr_op__insn_type$2[6:0]$8627 - attribute \src "libresoc.v:152521.3-152536.6" - wire $0\spr_op__is_32bit$5$next[0:0]$8569 - attribute \src "libresoc.v:152446.3-152447.55" - wire $0\spr_op__is_32bit$5[0:0]$8554 - attribute \src "libresoc.v:152364.7-152364.34" - wire $0\spr_op__is_32bit$5[0:0]$8629 - attribute \src "libresoc.v:152632.3-152650.6" - wire width 2 $0\xer_ca$10$next[1:0]$8605 - attribute \src "libresoc.v:152416.3-152417.37" - wire width 2 $0\xer_ca$10[1:0]$8531 - attribute \src "libresoc.v:152371.13-152371.31" - wire width 2 $0\xer_ca$10[1:0]$8631 - attribute \src "libresoc.v:152632.3-152650.6" - wire $0\xer_ca_ok$next[0:0]$8606 - attribute \src "libresoc.v:152418.3-152419.35" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:152613.3-152631.6" - wire width 2 $0\xer_ov$9$next[1:0]$8600 - attribute \src "libresoc.v:152420.3-152421.35" - wire width 2 $0\xer_ov$9[1:0]$8534 - attribute \src "libresoc.v:152389.13-152389.30" - wire width 2 $0\xer_ov$9[1:0]$8634 - attribute \src "libresoc.v:152613.3-152631.6" - wire $0\xer_ov_ok$next[0:0]$8599 - attribute \src "libresoc.v:152422.3-152423.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:152594.3-152612.6" - wire $0\xer_so$8$next[0:0]$8594 - attribute \src "libresoc.v:152424.3-152425.35" - wire $0\xer_so$8[0:0]$8537 - attribute \src "libresoc.v:152405.7-152405.24" - wire $0\xer_so$8[0:0]$8637 - attribute \src "libresoc.v:152594.3-152612.6" - wire $0\xer_so_ok$next[0:0]$8593 - attribute \src "libresoc.v:152426.3-152427.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:152575.3-152593.6" - wire width 64 $1\fast1$7$next[63:0]$8590 - attribute \src "libresoc.v:152575.3-152593.6" - wire $1\fast1_ok$next[0:0]$8589 - attribute \src "libresoc.v:151776.7-151776.22" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:152508.3-152520.6" - wire width 2 $1\muxid$1$next[1:0]$8564 - attribute \src "libresoc.v:152537.3-152555.6" - wire width 64 $1\o$next[63:0]$8577 - attribute \src "libresoc.v:151798.14-151798.38" + attribute \src "libresoc.v:160806.3-160824.6" + wire width 4 $1\cr_a$6$next[3:0]$8731 + attribute \src "libresoc.v:160806.3-160824.6" + wire $1\cr_a_ok$next[0:0]$8730 + attribute \src "libresoc.v:160082.7-160082.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:160753.3-160767.6" + wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8712 + attribute \src "libresoc.v:160753.3-160767.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8713 + attribute \src "libresoc.v:160753.3-160767.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8714 + attribute \src "libresoc.v:160787.3-160805.6" + wire width 32 $1\full_cr$5$next[31:0]$8724 + attribute \src "libresoc.v:160787.3-160805.6" + wire $1\full_cr_ok$next[0:0]$8725 + attribute \src "libresoc.v:160399.7-160399.24" + wire $1\full_cr_ok[0:0] + attribute \src "libresoc.v:160740.3-160752.6" + wire width 2 $1\muxid$1$next[1:0]$8707 + attribute \src "libresoc.v:160768.3-160786.6" + wire width 64 $1\o$next[63:0]$8718 + attribute \src "libresoc.v:160641.14-160641.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:152537.3-152555.6" - wire $1\o_ok$next[0:0]$8578 - attribute \src "libresoc.v:151805.7-151805.18" + attribute \src "libresoc.v:160768.3-160786.6" + wire $1\o_ok$next[0:0]$8719 + attribute \src "libresoc.v:160648.7-160648.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:152490.3-152507.6" - wire $1\r_busy$next[0:0]$8560 - attribute \src "libresoc.v:151819.7-151819.20" + attribute \src "libresoc.v:160722.3-160739.6" + wire $1\r_busy$next[0:0]$8703 + attribute \src "libresoc.v:160662.7-160662.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:152556.3-152574.6" - wire width 64 $1\spr1$6$next[63:0]$8583 - attribute \src "libresoc.v:152556.3-152574.6" - wire $1\spr1_ok$next[0:0]$8584 - attribute \src "libresoc.v:151835.7-151835.21" - wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:152521.3-152536.6" - wire width 12 $1\spr_op__fn_unit$3$next[11:0]$8570 - attribute \src "libresoc.v:152521.3-152536.6" - wire width 32 $1\spr_op__insn$4$next[31:0]$8571 - attribute \src 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attribute \src "libresoc.v:152537.3-152555.6" - wire $2\o_ok$next[0:0]$8579 - attribute \src "libresoc.v:152490.3-152507.6" - wire $2\r_busy$next[0:0]$8561 - attribute \src "libresoc.v:152556.3-152574.6" - wire $2\spr1_ok$next[0:0]$8585 - attribute \src "libresoc.v:152632.3-152650.6" - wire $2\xer_ca_ok$next[0:0]$8609 - attribute \src "libresoc.v:152613.3-152631.6" - wire $2\xer_ov_ok$next[0:0]$8603 - attribute \src "libresoc.v:152594.3-152612.6" - wire $2\xer_so_ok$next[0:0]$8597 - attribute \src "libresoc.v:152415.18-152415.118" - wire $and$libresoc.v:152415$8529_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "libresoc.v:160806.3-160824.6" + wire $2\cr_a_ok$next[0:0]$8732 + attribute \src "libresoc.v:160787.3-160805.6" + wire $2\full_cr_ok$next[0:0]$8726 + attribute \src "libresoc.v:160768.3-160786.6" + wire $2\o_ok$next[0:0]$8720 + attribute \src "libresoc.v:160722.3-160739.6" + wire $2\r_busy$next[0:0]$8704 + attribute \src "libresoc.v:160669.18-160669.118" + wire $and$libresoc.v:160669$8683_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 26 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 27 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$next - attribute \src "libresoc.v:151758.7-151758.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 17 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 16 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 15 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr1$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 24 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr1$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 25 \spr1_ok + wire width 4 input 11 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr1_ok$32 + wire width 4 \cr_a$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_fast1 + wire width 4 output 24 \cr_a$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr_main_fast1$17 + wire width 4 \cr_a$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \spr_main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \spr_main_muxid$11 + wire output 25 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr_main_o + wire \cr_a_ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_o_ok + wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_ra + wire width 4 input 12 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr_main_spr1$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_spr1_ok + wire width 4 input 13 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_main_spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \cr_op__fn_unit$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_main_spr_op__fn_unit$13 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \cr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn + wire width 32 input 7 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn$14 + wire width 32 \cr_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \cr_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -317427,8 +333720,9 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type + wire width 7 input 5 \cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -317503,85 +333797,9 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_main_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_main_spr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \spr_main_xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \spr_main_xer_ov$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \spr_main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_xer_so_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \spr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_op__fn_unit$26 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 19 \spr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 20 \spr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$4$next + wire width 7 \cr_op__insn_type$17 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -317656,8 +333874,75 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \spr_op__insn_type + wire width 7 output 17 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 10 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \full_cr$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 22 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \full_cr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \full_cr_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \full_cr_ok$next + attribute \src "libresoc.v:160064.7-160064.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_cr_op__fn_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn$10 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -317732,10 +334017,9 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 18 \spr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$2$next + wire width 7 \main_cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -317810,1316 +334094,782 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_op__is_32bit$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \spr_op__is_32bit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_op__is_32bit$5$next + wire width 7 \main_cr_op__insn_type$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 14 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 32 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$10$next + wire width 32 \main_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$39 + wire width 32 \main_full_cr$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \xer_ca_ok + wire \main_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$40 + wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$next + wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 13 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 30 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next + wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 12 \xer_so + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 15 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 14 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$35 + wire width 64 output 20 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \xer_so$8 + wire width 64 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$8$next + wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 29 \xer_so_ok + wire output 21 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$36 + wire \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:152415$8529 + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 8 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:160669$8683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$21 + connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:152415$8529_Y + connect \Y $and$libresoc.v:160669$8683_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:152452.10-152455.4" - cell \n$66 \n + attribute \src "libresoc.v:160692.12-160713.4" + cell \main$9 \main + connect \cr_a \main_cr_a + connect \cr_a$6 \main_cr_a$12 + connect \cr_a_ok \main_cr_a_ok + connect \cr_b \main_cr_b + connect \cr_c \main_cr_c + connect \cr_op__fn_unit \main_cr_op__fn_unit + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 + connect \cr_op__insn \main_cr_op__insn + connect \cr_op__insn$4 \main_cr_op__insn$10 + connect \cr_op__insn_type \main_cr_op__insn_type + connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 + connect \full_cr \main_full_cr + connect \full_cr$5 \main_full_cr$11 + connect \full_cr_ok \main_full_cr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$7 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:160714.9-160717.4" + cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:152456.10-152459.4" - cell \p$65 \p + attribute \src "libresoc.v:160718.9-160721.4" + cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \module_not_derived 1 - attribute \src "libresoc.v:152460.12-152489.4" - cell \spr_main \spr_main - connect \fast1 \spr_main_fast1 - connect \fast1$7 \spr_main_fast1$17 - connect \fast1_ok \spr_main_fast1_ok - connect \muxid \spr_main_muxid - connect \muxid$1 \spr_main_muxid$11 - connect \o \spr_main_o - connect \o_ok \spr_main_o_ok - connect \ra \spr_main_ra - connect \spr1 \spr_main_spr1 - connect \spr1$6 \spr_main_spr1$16 - connect \spr1_ok \spr_main_spr1_ok - connect \spr_op__fn_unit \spr_main_spr_op__fn_unit - connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 - connect \spr_op__insn \spr_main_spr_op__insn - connect \spr_op__insn$4 \spr_main_spr_op__insn$14 - connect \spr_op__insn_type \spr_main_spr_op__insn_type - connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 - connect \spr_op__is_32bit \spr_main_spr_op__is_32bit - connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 - connect \xer_ca \spr_main_xer_ca - connect \xer_ca$10 \spr_main_xer_ca$20 - connect \xer_ca_ok \spr_main_xer_ca_ok - connect \xer_ov \spr_main_xer_ov - connect \xer_ov$9 \spr_main_xer_ov$19 - connect \xer_ov_ok \spr_main_xer_ov_ok - connect \xer_so \spr_main_xer_so - connect \xer_so$8 \spr_main_xer_so$18 - connect \xer_so_ok \spr_main_xer_so_ok - end - attribute \src "libresoc.v:151758.7-151758.20" - process $proc$libresoc.v:151758$8610 + attribute \src "libresoc.v:160064.7-160064.20" + process $proc$libresoc.v:160064$8733 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151771.14-151771.46" - process $proc$libresoc.v:151771$8611 - assign { } { } - assign $0\fast1$7[63:0]$8612 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$7 $0\fast1$7[63:0]$8612 - end - attribute \src "libresoc.v:151776.7-151776.22" - process $proc$libresoc.v:151776$8613 - assign { } { } - assign $1\fast1_ok[0:0] 1'0 - sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] - end - attribute \src "libresoc.v:151785.13-151785.29" - process $proc$libresoc.v:151785$8614 - assign { } { } - assign $0\muxid$1[1:0]$8615 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8615 - end - attribute \src "libresoc.v:151798.14-151798.38" - process $proc$libresoc.v:151798$8616 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:151805.7-151805.18" - process $proc$libresoc.v:151805$8617 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:151819.7-151819.20" - process $proc$libresoc.v:151819$8618 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:151830.14-151830.45" - process $proc$libresoc.v:151830$8619 - assign { } { } - assign $0\spr1$6[63:0]$8620 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \spr1$6 $0\spr1$6[63:0]$8620 - end - attribute \src "libresoc.v:151835.7-151835.21" - process $proc$libresoc.v:151835$8621 + attribute \src "libresoc.v:160077.13-160077.28" + process $proc$libresoc.v:160077$8734 assign { } { } - assign $1\spr1_ok[0:0] 1'0 + assign $0\cr_a$6[3:0]$8735 4'0000 sync always sync init - update \spr1_ok $1\spr1_ok[0:0] + update \cr_a$6 $0\cr_a$6[3:0]$8735 end - attribute \src "libresoc.v:152115.14-152115.43" - process $proc$libresoc.v:152115$8622 + attribute \src "libresoc.v:160082.7-160082.21" + process $proc$libresoc.v:160082$8736 assign { } { } - assign $0\spr_op__fn_unit$3[11:0]$8623 12'000000000000 + assign $1\cr_a_ok[0:0] 1'0 sync always sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8623 + update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:152124.14-152124.38" - process $proc$libresoc.v:152124$8624 + attribute \src "libresoc.v:160142.14-160142.43" + process $proc$libresoc.v:160142$8737 assign { } { } - assign $0\spr_op__insn$4[31:0]$8625 0 + assign $0\cr_op__fn_unit$3[13:0]$8738 14'00000000000000 sync always sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8625 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8738 end - attribute \src "libresoc.v:152279.13-152279.42" - process $proc$libresoc.v:152279$8626 + attribute \src "libresoc.v:160151.14-160151.37" + process $proc$libresoc.v:160151$8739 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8627 7'0000000 + assign $0\cr_op__insn$4[31:0]$8740 0 sync always sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8627 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8740 end - attribute \src "libresoc.v:152364.7-152364.34" - process $proc$libresoc.v:152364$8628 + attribute \src "libresoc.v:160385.13-160385.41" + process $proc$libresoc.v:160385$8741 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8629 1'0 + assign $0\cr_op__insn_type$2[6:0]$8742 7'0000000 sync always sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8629 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8742 end - attribute \src "libresoc.v:152371.13-152371.31" - process $proc$libresoc.v:152371$8630 + attribute \src "libresoc.v:160394.14-160394.33" + process $proc$libresoc.v:160394$8743 assign { } { } - assign $0\xer_ca$10[1:0]$8631 2'00 + assign $0\full_cr$5[31:0]$8744 0 sync always sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$8631 + update \full_cr$5 $0\full_cr$5[31:0]$8744 end - attribute \src "libresoc.v:152378.7-152378.23" - process $proc$libresoc.v:152378$8632 + attribute \src "libresoc.v:160399.7-160399.24" + process $proc$libresoc.v:160399$8745 assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 + assign $1\full_cr_ok[0:0] 1'0 sync always sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] + update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:152389.13-152389.30" - process $proc$libresoc.v:152389$8633 + attribute \src "libresoc.v:160628.13-160628.29" + process $proc$libresoc.v:160628$8746 assign { } { } - assign $0\xer_ov$9[1:0]$8634 2'00 + assign $0\muxid$1[1:0]$8747 2'00 sync always sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$8634 + update \muxid$1 $0\muxid$1[1:0]$8747 end - attribute \src "libresoc.v:152394.7-152394.23" - process $proc$libresoc.v:152394$8635 + attribute \src "libresoc.v:160641.14-160641.38" + process $proc$libresoc.v:160641$8748 assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] + update \o $1\o[63:0] end - attribute \src "libresoc.v:152405.7-152405.24" - process $proc$libresoc.v:152405$8636 + attribute \src "libresoc.v:160648.7-160648.18" + process $proc$libresoc.v:160648$8749 assign { } { } - assign $0\xer_so$8[0:0]$8637 1'0 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \xer_so$8 $0\xer_so$8[0:0]$8637 + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:152410.7-152410.23" - process $proc$libresoc.v:152410$8638 + attribute \src "libresoc.v:160662.7-160662.20" + process $proc$libresoc.v:160662$8750 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:152416.3-152417.37" - process $proc$libresoc.v:152416$8530 - assign { } { } - assign $0\xer_ca$10[1:0]$8531 \xer_ca$10$next - sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8531 - end - attribute \src "libresoc.v:152418.3-152419.35" - process $proc$libresoc.v:152418$8532 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:152420.3-152421.35" - process $proc$libresoc.v:152420$8533 - assign { } { } - assign $0\xer_ov$9[1:0]$8534 \xer_ov$9$next - sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8534 - end - attribute \src "libresoc.v:152422.3-152423.35" - process $proc$libresoc.v:152422$8535 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:152424.3-152425.35" - process $proc$libresoc.v:152424$8536 - assign { } { } - assign $0\xer_so$8[0:0]$8537 \xer_so$8$next - sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8537 - end - attribute \src "libresoc.v:152426.3-152427.35" - process $proc$libresoc.v:152426$8538 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:152428.3-152429.33" - process $proc$libresoc.v:152428$8539 + attribute \src "libresoc.v:160670.3-160671.31" + process $proc$libresoc.v:160670$8684 assign { } { } - assign $0\fast1$7[63:0]$8540 \fast1$7$next + assign $0\cr_a$6[3:0]$8685 \cr_a$6$next sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8540 + update \cr_a$6 $0\cr_a$6[3:0]$8685 end - attribute \src "libresoc.v:152430.3-152431.33" - process $proc$libresoc.v:152430$8541 + attribute \src "libresoc.v:160672.3-160673.31" + process $proc$libresoc.v:160672$8686 assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next + assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:152432.3-152433.31" - process $proc$libresoc.v:152432$8542 + attribute \src "libresoc.v:160674.3-160675.37" + process $proc$libresoc.v:160674$8687 assign { } { } - assign $0\spr1$6[63:0]$8543 \spr1$6$next + assign $0\full_cr$5[31:0]$8688 \full_cr$5$next sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8543 + update \full_cr$5 $0\full_cr$5[31:0]$8688 end - attribute \src "libresoc.v:152434.3-152435.31" - process $proc$libresoc.v:152434$8544 + attribute \src "libresoc.v:160676.3-160677.37" + process $proc$libresoc.v:160676$8689 assign { } { } - assign $0\spr1_ok[0:0] \spr1_ok$next + assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk - update \spr1_ok $0\spr1_ok[0:0] + update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:152436.3-152437.19" - process $proc$libresoc.v:152436$8545 + attribute \src "libresoc.v:160678.3-160679.19" + process $proc$libresoc.v:160678$8690 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:152438.3-152439.25" - process $proc$libresoc.v:152438$8546 + attribute \src "libresoc.v:160680.3-160681.25" + process $proc$libresoc.v:160680$8691 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:152440.3-152441.57" - process $proc$libresoc.v:152440$8547 - assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8548 \spr_op__insn_type$2$next - sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8548 - end - attribute \src "libresoc.v:152442.3-152443.53" - process $proc$libresoc.v:152442$8549 + attribute \src "libresoc.v:160682.3-160683.55" + process $proc$libresoc.v:160682$8692 assign { } { } - assign $0\spr_op__fn_unit$3[11:0]$8550 \spr_op__fn_unit$3$next + assign $0\cr_op__insn_type$2[6:0]$8693 \cr_op__insn_type$2$next sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8550 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8693 end - attribute \src "libresoc.v:152444.3-152445.47" - process $proc$libresoc.v:152444$8551 + attribute \src "libresoc.v:160684.3-160685.51" + process $proc$libresoc.v:160684$8694 assign { } { } - assign $0\spr_op__insn$4[31:0]$8552 \spr_op__insn$4$next + assign $0\cr_op__fn_unit$3[13:0]$8695 \cr_op__fn_unit$3$next sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8552 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8695 end - attribute \src "libresoc.v:152446.3-152447.55" - process $proc$libresoc.v:152446$8553 + attribute \src "libresoc.v:160686.3-160687.45" + process $proc$libresoc.v:160686$8696 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8554 \spr_op__is_32bit$5$next + assign $0\cr_op__insn$4[31:0]$8697 \cr_op__insn$4$next sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8554 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8697 end - attribute \src "libresoc.v:152448.3-152449.33" - process $proc$libresoc.v:152448$8555 + attribute \src "libresoc.v:160688.3-160689.33" + process $proc$libresoc.v:160688$8698 assign { } { } - assign $0\muxid$1[1:0]$8556 \muxid$1$next + assign $0\muxid$1[1:0]$8699 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8556 + update \muxid$1 $0\muxid$1[1:0]$8699 end - attribute \src "libresoc.v:152450.3-152451.29" - process $proc$libresoc.v:152450$8557 + attribute \src "libresoc.v:160690.3-160691.29" + process $proc$libresoc.v:160690$8700 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:152490.3-152507.6" - process $proc$libresoc.v:152490$8558 + attribute \src "libresoc.v:160722.3-160739.6" + process $proc$libresoc.v:160722$8701 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8559 $2\r_busy$next[0:0]$8561 - attribute \src "libresoc.v:152491.5-152491.29" + assign $0\r_busy$next[0:0]$8702 $2\r_busy$next[0:0]$8704 + attribute \src "libresoc.v:160723.5-160723.29" switch \initial - attribute \src "libresoc.v:152491.9-152491.17" + attribute \src "libresoc.v:160723.9-160723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8560 1'1 + assign $1\r_busy$next[0:0]$8703 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8560 1'0 + assign $1\r_busy$next[0:0]$8703 1'0 case - assign $1\r_busy$next[0:0]$8560 \r_busy + assign $1\r_busy$next[0:0]$8703 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8561 1'0 - case - assign $2\r_busy$next[0:0]$8561 $1\r_busy$next[0:0]$8560 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8559 - end - attribute \src "libresoc.v:152508.3-152520.6" - process $proc$libresoc.v:152508$8562 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$8563 $1\muxid$1$next[1:0]$8564 - attribute \src "libresoc.v:152509.5-152509.29" - switch \initial - attribute \src "libresoc.v:152509.9-152509.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$8564 \muxid$24 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$8564 \muxid$24 + assign $2\r_busy$next[0:0]$8704 1'0 case - assign $1\muxid$1$next[1:0]$8564 \muxid$1 + assign $2\r_busy$next[0:0]$8704 $1\r_busy$next[0:0]$8703 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8563 + update \r_busy$next $0\r_busy$next[0:0]$8702 end - attribute \src "libresoc.v:152521.3-152536.6" - process $proc$libresoc.v:152521$8565 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:160740.3-160752.6" + process $proc$libresoc.v:160740$8705 assign { } { } assign { } { } - assign { } { } - assign $0\spr_op__fn_unit$3$next[11:0]$8566 $1\spr_op__fn_unit$3$next[11:0]$8570 - assign $0\spr_op__insn$4$next[31:0]$8567 $1\spr_op__insn$4$next[31:0]$8571 - assign $0\spr_op__insn_type$2$next[6:0]$8568 $1\spr_op__insn_type$2$next[6:0]$8572 - assign $0\spr_op__is_32bit$5$next[0:0]$8569 $1\spr_op__is_32bit$5$next[0:0]$8573 - attribute \src "libresoc.v:152522.5-152522.29" + assign $0\muxid$1$next[1:0]$8706 $1\muxid$1$next[1:0]$8707 + attribute \src "libresoc.v:160741.5-160741.29" switch \initial - attribute \src "libresoc.v:152522.9-152522.17" + attribute \src "libresoc.v:160741.9-160741.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8573 $1\spr_op__insn$4$next[31:0]$8571 $1\spr_op__fn_unit$3$next[11:0]$8570 $1\spr_op__insn_type$2$next[6:0]$8572 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign $1\muxid$1$next[1:0]$8707 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8573 $1\spr_op__insn$4$next[31:0]$8571 $1\spr_op__fn_unit$3$next[11:0]$8570 $1\spr_op__insn_type$2$next[6:0]$8572 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign $1\muxid$1$next[1:0]$8707 \muxid$16 case - assign $1\spr_op__fn_unit$3$next[11:0]$8570 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8571 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8572 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8573 \spr_op__is_32bit$5 + assign $1\muxid$1$next[1:0]$8707 \muxid$1 end sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[11:0]$8566 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8567 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8568 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8569 + update \muxid$1$next $0\muxid$1$next[1:0]$8706 end - attribute \src "libresoc.v:152537.3-152555.6" - process $proc$libresoc.v:152537$8574 - assign { } { } + attribute \src "libresoc.v:160753.3-160767.6" + process $proc$libresoc.v:160753$8708 assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8575 $1\o$next[63:0]$8577 assign { } { } - assign $0\o_ok$next[0:0]$8576 $2\o_ok$next[0:0]$8579 - attribute \src "libresoc.v:152538.5-152538.29" - switch \initial - attribute \src "libresoc.v:152538.9-152538.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8578 $1\o$next[63:0]$8577 } { \o_ok$30 \o$29 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8578 $1\o$next[63:0]$8577 } { \o_ok$30 \o$29 } - case - assign $1\o$next[63:0]$8577 \o - assign $1\o_ok$next[0:0]$8578 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8579 1'0 - case - assign $2\o_ok$next[0:0]$8579 $1\o_ok$next[0:0]$8578 - end - sync always - update \o$next $0\o$next[63:0]$8575 - update \o_ok$next $0\o_ok$next[0:0]$8576 - end - attribute \src "libresoc.v:152556.3-152574.6" - process $proc$libresoc.v:152556$8580 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\spr1$6$next[63:0]$8581 $1\spr1$6$next[63:0]$8583 - assign { } { } - assign $0\spr1_ok$next[0:0]$8582 $2\spr1_ok$next[0:0]$8585 - attribute \src "libresoc.v:152557.5-152557.29" + assign $0\cr_op__fn_unit$3$next[13:0]$8709 $1\cr_op__fn_unit$3$next[13:0]$8712 + assign $0\cr_op__insn$4$next[31:0]$8710 $1\cr_op__insn$4$next[31:0]$8713 + assign $0\cr_op__insn_type$2$next[6:0]$8711 $1\cr_op__insn_type$2$next[6:0]$8714 + attribute \src "libresoc.v:160754.5-160754.29" switch \initial - attribute \src "libresoc.v:152557.9-152557.17" + attribute \src "libresoc.v:160754.9-160754.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\spr1_ok$next[0:0]$8584 $1\spr1$6$next[63:0]$8583 } { \spr1_ok$32 \spr1$31 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\spr1_ok$next[0:0]$8584 $1\spr1$6$next[63:0]$8583 } { \spr1_ok$32 \spr1$31 } - case - assign $1\spr1$6$next[63:0]$8583 \spr1$6 - assign $1\spr1_ok$next[0:0]$8584 \spr1_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\spr1_ok$next[0:0]$8585 1'0 - case - assign $2\spr1_ok$next[0:0]$8585 $1\spr1_ok$next[0:0]$8584 - end - sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8581 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8582 - end - attribute \src "libresoc.v:152575.3-152593.6" - process $proc$libresoc.v:152575$8586 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast1$7$next[63:0]$8588 $1\fast1$7$next[63:0]$8590 - assign $0\fast1_ok$next[0:0]$8587 $2\fast1_ok$next[0:0]$8591 - attribute \src "libresoc.v:152576.5-152576.29" - switch \initial - attribute \src "libresoc.v:152576.9-152576.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8589 $1\fast1$7$next[63:0]$8590 } { \fast1_ok$34 \fast1$33 } + assign { $1\cr_op__insn$4$next[31:0]$8713 $1\cr_op__fn_unit$3$next[13:0]$8712 $1\cr_op__insn_type$2$next[6:0]$8714 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8589 $1\fast1$7$next[63:0]$8590 } { \fast1_ok$34 \fast1$33 } - case - assign $1\fast1_ok$next[0:0]$8589 \fast1_ok - assign $1\fast1$7$next[63:0]$8590 \fast1$7 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8591 1'0 + assign { $1\cr_op__insn$4$next[31:0]$8713 $1\cr_op__fn_unit$3$next[13:0]$8712 $1\cr_op__insn_type$2$next[6:0]$8714 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case - assign $2\fast1_ok$next[0:0]$8591 $1\fast1_ok$next[0:0]$8589 + assign $1\cr_op__fn_unit$3$next[13:0]$8712 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8713 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8714 \cr_op__insn_type$2 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8587 - update \fast1$7$next $0\fast1$7$next[63:0]$8588 + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8709 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8710 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8711 end - attribute \src "libresoc.v:152594.3-152612.6" - process $proc$libresoc.v:152594$8592 + attribute \src "libresoc.v:160768.3-160786.6" + process $proc$libresoc.v:160768$8715 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\o$next[63:0]$8716 $1\o$next[63:0]$8718 assign { } { } - assign $0\xer_so$8$next[0:0]$8594 $1\xer_so$8$next[0:0]$8596 - assign $0\xer_so_ok$next[0:0]$8593 $2\xer_so_ok$next[0:0]$8597 - attribute \src "libresoc.v:152595.5-152595.29" + assign $0\o_ok$next[0:0]$8717 $2\o_ok$next[0:0]$8720 + attribute \src "libresoc.v:160769.5-160769.29" switch \initial - attribute \src "libresoc.v:152595.9-152595.17" + attribute \src "libresoc.v:160769.9-160769.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8595 $1\xer_so$8$next[0:0]$8596 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\o_ok$next[0:0]$8719 $1\o$next[63:0]$8718 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8595 $1\xer_so$8$next[0:0]$8596 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\o_ok$next[0:0]$8719 $1\o$next[63:0]$8718 } { \o_ok$21 \o$20 } case - assign $1\xer_so_ok$next[0:0]$8595 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8596 \xer_so$8 + assign $1\o$next[63:0]$8718 \o + assign $1\o_ok$next[0:0]$8719 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8597 1'0 + assign $2\o_ok$next[0:0]$8720 1'0 case - assign $2\xer_so_ok$next[0:0]$8597 $1\xer_so_ok$next[0:0]$8595 + assign $2\o_ok$next[0:0]$8720 $1\o_ok$next[0:0]$8719 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8593 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8594 + update \o$next $0\o$next[63:0]$8716 + update \o_ok$next $0\o_ok$next[0:0]$8717 end - attribute \src "libresoc.v:152613.3-152631.6" - process $proc$libresoc.v:152613$8598 + attribute \src "libresoc.v:160787.3-160805.6" + process $proc$libresoc.v:160787$8721 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\full_cr$5$next[31:0]$8722 $1\full_cr$5$next[31:0]$8724 assign { } { } - assign $0\xer_ov$9$next[1:0]$8600 $1\xer_ov$9$next[1:0]$8602 - assign $0\xer_ov_ok$next[0:0]$8599 $2\xer_ov_ok$next[0:0]$8603 - attribute \src "libresoc.v:152614.5-152614.29" + assign $0\full_cr_ok$next[0:0]$8723 $2\full_cr_ok$next[0:0]$8726 + attribute \src "libresoc.v:160788.5-160788.29" switch \initial - attribute \src "libresoc.v:152614.9-152614.17" + attribute \src "libresoc.v:160788.9-160788.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8601 $1\xer_ov$9$next[1:0]$8602 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\full_cr_ok$next[0:0]$8725 $1\full_cr$5$next[31:0]$8724 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8601 $1\xer_ov$9$next[1:0]$8602 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\full_cr_ok$next[0:0]$8725 $1\full_cr$5$next[31:0]$8724 } { \full_cr_ok$23 \full_cr$22 } case - assign $1\xer_ov_ok$next[0:0]$8601 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8602 \xer_ov$9 + assign $1\full_cr$5$next[31:0]$8724 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8725 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8603 1'0 + assign $2\full_cr_ok$next[0:0]$8726 1'0 case - assign $2\xer_ov_ok$next[0:0]$8603 $1\xer_ov_ok$next[0:0]$8601 + assign $2\full_cr_ok$next[0:0]$8726 $1\full_cr_ok$next[0:0]$8725 end sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8599 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8600 + update \full_cr$5$next $0\full_cr$5$next[31:0]$8722 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8723 end - attribute \src "libresoc.v:152632.3-152650.6" - process $proc$libresoc.v:152632$8604 + attribute \src "libresoc.v:160806.3-160824.6" + process $proc$libresoc.v:160806$8727 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$10$next[1:0]$8605 $1\xer_ca$10$next[1:0]$8607 assign { } { } - assign $0\xer_ca_ok$next[0:0]$8606 $2\xer_ca_ok$next[0:0]$8609 - attribute \src "libresoc.v:152633.5-152633.29" + assign $0\cr_a$6$next[3:0]$8729 $1\cr_a$6$next[3:0]$8731 + assign $0\cr_a_ok$next[0:0]$8728 $2\cr_a_ok$next[0:0]$8732 + attribute \src "libresoc.v:160807.5-160807.29" switch \initial - attribute \src "libresoc.v:152633.9-152633.17" + attribute \src "libresoc.v:160807.9-160807.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8608 $1\xer_ca$10$next[1:0]$8607 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\cr_a_ok$next[0:0]$8730 $1\cr_a$6$next[3:0]$8731 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8608 $1\xer_ca$10$next[1:0]$8607 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\cr_a_ok$next[0:0]$8730 $1\cr_a$6$next[3:0]$8731 } { \cr_a_ok$25 \cr_a$24 } case - assign $1\xer_ca$10$next[1:0]$8607 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8608 \xer_ca_ok + assign $1\cr_a_ok$next[0:0]$8730 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8731 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8609 1'0 + assign $2\cr_a_ok$next[0:0]$8732 1'0 case - assign $2\xer_ca_ok$next[0:0]$8609 $1\xer_ca_ok$next[0:0]$8608 + assign $2\cr_a_ok$next[0:0]$8732 $1\cr_a_ok$next[0:0]$8730 end sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8605 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8606 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8728 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8729 end - connect \$22 $and$libresoc.v:152415$8529_Y + connect \$14 $and$libresoc.v:160669$8683_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } - connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } - connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } - connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } - connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } - connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } - connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } - connect \muxid$24 \spr_main_muxid$11 - connect \p_valid_i_p_ready_o \$22 + connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } + connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } + connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } + connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } + connect \muxid$16 \main_muxid$7 + connect \p_valid_i_p_ready_o \$14 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$21 \p_valid_i - connect \spr_main_xer_ca \xer_ca - connect \spr_main_xer_ov \xer_ov - connect \spr_main_xer_so \xer_so - connect \spr_main_fast1 \fast1 - connect \spr_main_spr1 \spr1 - connect \spr_main_ra \ra - connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \spr_main_muxid \muxid + connect \p_valid_i$13 \p_valid_i + connect \main_cr_c \cr_c + connect \main_cr_b \cr_b + connect \main_cr_a \cr_a + connect \main_full_cr \full_cr + connect \main_rb \rb + connect \main_ra \ra + connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \main_muxid \muxid end -attribute \src "libresoc.v:152676.1-154147.10" +attribute \src "libresoc.v:160847.1-161707.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" -attribute \generator "nMigen" -module \pipe1 - attribute \src "libresoc.v:154061.3-154102.6" - wire width 4 $0\alu_op__data_len$next[3:0]$8702 - attribute \src "libresoc.v:153837.3-153838.49" - wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 12 $0\alu_op__fn_unit$next[11:0]$8703 - attribute \src "libresoc.v:153807.3-153808.47" - wire width 12 $0\alu_op__fn_unit[11:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$8704 - attribute \src "libresoc.v:153809.3-153810.61" - wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__imm_data__ok$next[0:0]$8705 - attribute \src "libresoc.v:153811.3-153812.57" - wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$8706 - attribute \src "libresoc.v:153829.3-153830.55" - wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 32 $0\alu_op__insn$next[31:0]$8707 - attribute \src "libresoc.v:153839.3-153840.41" - wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$8708 - attribute \src "libresoc.v:153805.3-153806.51" - wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__invert_in$next[0:0]$8709 - attribute \src "libresoc.v:153821.3-153822.51" - wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__invert_out$next[0:0]$8710 - attribute \src "libresoc.v:153825.3-153826.53" - wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__is_32bit$next[0:0]$8711 - attribute \src "libresoc.v:153833.3-153834.49" - wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__is_signed$next[0:0]$8712 - attribute \src "libresoc.v:153835.3-153836.51" - wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__oe__oe$next[0:0]$8713 - attribute \src "libresoc.v:153817.3-153818.45" - wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__oe__ok$next[0:0]$8714 - attribute \src "libresoc.v:153819.3-153820.45" - wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__output_carry$next[0:0]$8715 - attribute \src "libresoc.v:153831.3-153832.57" - wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__rc__ok$next[0:0]$8716 - attribute \src "libresoc.v:153815.3-153816.45" - wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__rc__rc$next[0:0]$8717 - attribute \src "libresoc.v:153813.3-153814.45" - wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__write_cr0$next[0:0]$8718 - attribute \src "libresoc.v:153827.3-153828.51" - wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $0\alu_op__zero_a$next[0:0]$8719 - attribute \src "libresoc.v:153823.3-153824.45" - wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:153954.3-153972.6" - wire width 4 $0\cr_a$next[3:0]$8671 - attribute \src "libresoc.v:153797.3-153798.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:153954.3-153972.6" - wire $0\cr_a_ok$next[0:0]$8672 - attribute \src "libresoc.v:153799.3-153800.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:152677.7-152677.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:154048.3-154060.6" - wire width 2 $0\muxid$next[1:0]$8699 - attribute \src "libresoc.v:153841.3-153842.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:154103.3-154121.6" - wire width 64 $0\o$next[63:0]$8745 - attribute \src "libresoc.v:153801.3-153802.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:154103.3-154121.6" - wire $0\o_ok$next[0:0]$8746 - attribute \src "libresoc.v:153803.3-153804.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:154030.3-154047.6" - wire $0\r_busy$next[0:0]$8695 - attribute \src "libresoc.v:153843.3-153844.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:153973.3-153991.6" - wire width 2 $0\xer_ca$next[1:0]$8678 - attribute \src "libresoc.v:153793.3-153794.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:153973.3-153991.6" - wire $0\xer_ca_ok$next[0:0]$8677 - attribute \src "libresoc.v:153795.3-153796.35" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:153992.3-154010.6" - wire width 2 $0\xer_ov$next[1:0]$8683 - attribute \src "libresoc.v:153789.3-153790.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:153992.3-154010.6" - wire $0\xer_ov_ok$next[0:0]$8684 - attribute \src "libresoc.v:153791.3-153792.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:154011.3-154029.6" - wire $0\xer_so$next[0:0]$8689 - attribute \src "libresoc.v:153785.3-153786.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:154011.3-154029.6" - wire $0\xer_so_ok$next[0:0]$8690 - attribute \src "libresoc.v:153787.3-153788.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 4 $1\alu_op__data_len$next[3:0]$8720 - attribute \src "libresoc.v:152682.13-152682.36" - wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 12 $1\alu_op__fn_unit$next[11:0]$8721 - attribute \src "libresoc.v:152704.14-152704.39" - wire width 12 $1\alu_op__fn_unit[11:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$8722 - attribute \src "libresoc.v:152739.14-152739.59" - wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__imm_data__ok$next[0:0]$8723 - attribute \src "libresoc.v:152748.7-152748.34" - wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$8724 - attribute \src "libresoc.v:152761.13-152761.39" - wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 32 $1\alu_op__insn$next[31:0]$8725 - attribute \src "libresoc.v:152778.14-152778.34" - wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$8726 - attribute \src "libresoc.v:152861.13-152861.38" - wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__invert_in$next[0:0]$8727 - attribute \src "libresoc.v:153018.7-153018.31" - wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__invert_out$next[0:0]$8728 - attribute \src "libresoc.v:153027.7-153027.32" - wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__is_32bit$next[0:0]$8729 - attribute \src "libresoc.v:153036.7-153036.30" - wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__is_signed$next[0:0]$8730 - attribute \src "libresoc.v:153045.7-153045.31" - wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__oe__oe$next[0:0]$8731 - attribute \src "libresoc.v:153054.7-153054.28" - wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__oe__ok$next[0:0]$8732 - attribute \src "libresoc.v:153063.7-153063.28" - wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__output_carry$next[0:0]$8733 - attribute \src "libresoc.v:153072.7-153072.34" - wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__rc__ok$next[0:0]$8734 - attribute \src "libresoc.v:153081.7-153081.28" - wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__rc__rc$next[0:0]$8735 - attribute \src "libresoc.v:153090.7-153090.28" - wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__write_cr0$next[0:0]$8736 - attribute \src "libresoc.v:153099.7-153099.31" - wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire $1\alu_op__zero_a$next[0:0]$8737 - attribute \src "libresoc.v:153108.7-153108.28" - wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:153954.3-153972.6" - wire width 4 $1\cr_a$next[3:0]$8673 - attribute \src "libresoc.v:153121.13-153121.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:153954.3-153972.6" - wire $1\cr_a_ok$next[0:0]$8674 - attribute \src "libresoc.v:153128.7-153128.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:154048.3-154060.6" - wire width 2 $1\muxid$next[1:0]$8700 - attribute \src "libresoc.v:153693.13-153693.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:154103.3-154121.6" - wire width 64 $1\o$next[63:0]$8747 - attribute \src "libresoc.v:153708.14-153708.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:154103.3-154121.6" - wire $1\o_ok$next[0:0]$8748 - attribute \src "libresoc.v:153715.7-153715.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:154030.3-154047.6" - wire $1\r_busy$next[0:0]$8696 - attribute \src "libresoc.v:153729.7-153729.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:153973.3-153991.6" - wire width 2 $1\xer_ca$next[1:0]$8680 - attribute \src "libresoc.v:153738.13-153738.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:153973.3-153991.6" - wire $1\xer_ca_ok$next[0:0]$8679 - attribute \src "libresoc.v:153747.7-153747.23" - wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:153992.3-154010.6" - wire width 2 $1\xer_ov$next[1:0]$8685 - attribute \src "libresoc.v:153754.13-153754.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:153992.3-154010.6" - wire $1\xer_ov_ok$next[0:0]$8686 - attribute \src "libresoc.v:153761.7-153761.23" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:154011.3-154029.6" - wire $1\xer_so$next[0:0]$8691 - attribute \src "libresoc.v:153768.7-153768.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:154011.3-154029.6" - wire $1\xer_so_ok$next[0:0]$8692 - attribute \src "libresoc.v:153777.7-153777.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:154061.3-154102.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$8738 - attribute \src "libresoc.v:154061.3-154102.6" - wire $2\alu_op__imm_data__ok$next[0:0]$8739 - attribute \src "libresoc.v:154061.3-154102.6" - wire $2\alu_op__oe__oe$next[0:0]$8740 - attribute \src "libresoc.v:154061.3-154102.6" - wire $2\alu_op__oe__ok$next[0:0]$8741 - attribute \src "libresoc.v:154061.3-154102.6" - wire $2\alu_op__rc__ok$next[0:0]$8742 - attribute \src "libresoc.v:154061.3-154102.6" - wire $2\alu_op__rc__rc$next[0:0]$8743 - attribute \src "libresoc.v:153954.3-153972.6" - wire $2\cr_a_ok$next[0:0]$8675 - attribute \src "libresoc.v:154103.3-154121.6" - wire $2\o_ok$next[0:0]$8749 - attribute \src "libresoc.v:154030.3-154047.6" - wire $2\r_busy$next[0:0]$8697 - attribute \src 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attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute 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"libresoc.v:161607.3-161634.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8791 + attribute \src "libresoc.v:161525.3-161526.45" + wire width 32 $0\br_op__insn$5[31:0]$8767 + attribute \src "libresoc.v:160938.14-160938.37" + wire width 32 $0\br_op__insn$5[31:0]$8833 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8792 + attribute \src "libresoc.v:161521.3-161522.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8763 + attribute \src "libresoc.v:161172.13-161172.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8835 + attribute \src "libresoc.v:161607.3-161634.6" + wire $0\br_op__is_32bit$9$next[0:0]$8793 + attribute \src "libresoc.v:161533.3-161534.53" + wire $0\br_op__is_32bit$9[0:0]$8775 + attribute \src "libresoc.v:161181.7-161181.33" + wire $0\br_op__is_32bit$9[0:0]$8837 + attribute \src "libresoc.v:161607.3-161634.6" + wire $0\br_op__lk$8$next[0:0]$8794 + attribute \src "libresoc.v:161531.3-161532.41" + wire $0\br_op__lk$8[0:0]$8773 + attribute \src "libresoc.v:161190.7-161190.27" + wire $0\br_op__lk$8[0:0]$8839 + attribute \src "libresoc.v:161635.3-161653.6" + wire width 64 $0\fast1$10$next[63:0]$8806 + attribute \src "libresoc.v:161515.3-161516.35" + wire width 64 $0\fast1$10[63:0]$8758 + attribute \src "libresoc.v:161203.14-161203.47" + wire width 64 $0\fast1$10[63:0]$8841 + attribute \src "libresoc.v:161635.3-161653.6" + wire $0\fast1_ok$next[0:0]$8807 + attribute \src "libresoc.v:161517.3-161518.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:161654.3-161672.6" + wire width 64 $0\fast2$11$next[63:0]$8812 + attribute \src "libresoc.v:161511.3-161512.35" + wire width 64 $0\fast2$11[63:0]$8755 + attribute \src "libresoc.v:161219.14-161219.47" + wire width 64 $0\fast2$11[63:0]$8844 + attribute \src "libresoc.v:161654.3-161672.6" + wire $0\fast2_ok$next[0:0]$8813 + attribute \src "libresoc.v:161513.3-161514.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:160848.7-160848.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:161594.3-161606.6" + wire width 2 $0\muxid$1$next[1:0]$8784 + attribute \src "libresoc.v:161535.3-161536.33" + wire width 2 $0\muxid$1[1:0]$8777 + attribute \src "libresoc.v:161469.13-161469.29" + wire width 2 $0\muxid$1[1:0]$8847 + attribute \src "libresoc.v:161673.3-161691.6" + wire width 64 $0\nia$next[63:0]$8818 + attribute \src "libresoc.v:161507.3-161508.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:161673.3-161691.6" + wire $0\nia_ok$next[0:0]$8819 + attribute \src "libresoc.v:161509.3-161510.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:161576.3-161593.6" + wire $0\r_busy$next[0:0]$8780 + attribute \src "libresoc.v:161537.3-161538.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:161607.3-161634.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8795 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 14 $1\br_op__fn_unit$4$next[13:0]$8796 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8797 + attribute \src "libresoc.v:161607.3-161634.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8798 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8799 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8800 + attribute \src "libresoc.v:161607.3-161634.6" + wire $1\br_op__is_32bit$9$next[0:0]$8801 + attribute \src "libresoc.v:161607.3-161634.6" + wire $1\br_op__lk$8$next[0:0]$8802 + attribute \src "libresoc.v:161635.3-161653.6" + wire width 64 $1\fast1$10$next[63:0]$8808 + attribute \src "libresoc.v:161635.3-161653.6" + wire $1\fast1_ok$next[0:0]$8809 + attribute \src "libresoc.v:161210.7-161210.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:161654.3-161672.6" + wire width 64 $1\fast2$11$next[63:0]$8814 + attribute \src "libresoc.v:161654.3-161672.6" + wire $1\fast2_ok$next[0:0]$8815 + attribute \src "libresoc.v:161226.7-161226.22" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:161594.3-161606.6" + wire width 2 $1\muxid$1$next[1:0]$8785 + attribute \src "libresoc.v:161673.3-161691.6" + wire width 64 $1\nia$next[63:0]$8820 + attribute \src "libresoc.v:161482.14-161482.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:161673.3-161691.6" + wire $1\nia_ok$next[0:0]$8821 + attribute \src "libresoc.v:161489.7-161489.20" + wire $1\nia_ok[0:0] + attribute \src "libresoc.v:161576.3-161593.6" + wire $1\r_busy$next[0:0]$8781 + attribute \src "libresoc.v:161503.7-161503.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:161607.3-161634.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8803 + attribute \src "libresoc.v:161607.3-161634.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8804 + attribute \src "libresoc.v:161635.3-161653.6" + wire $2\fast1_ok$next[0:0]$8810 + attribute \src "libresoc.v:161654.3-161672.6" + wire $2\fast2_ok$next[0:0]$8816 + attribute \src "libresoc.v:161673.3-161691.6" + wire $2\nia_ok$next[0:0]$8822 + attribute \src "libresoc.v:161576.3-161593.6" + wire $2\r_busy$next[0:0]$8782 + attribute \src "libresoc.v:161506.18-161506.118" + wire $and$libresoc.v:161506$8751_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 64 input 5 \br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 36 \alu_op__insn_type$2 + wire width 64 output 19 \br_op__cia$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$27 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$29 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 21 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 8 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \br_op__insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$5$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -319194,174 +334944,9 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "libresoc.v:152677.7-152677.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len$39 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_alu_op__fn_unit$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok$26 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn$40 + wire width 7 input 6 \br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -319436,8 +335021,9 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type + wire width 7 \br_op__insn_type$28 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -319512,130 +335098,113 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_in$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_32bit$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_signed$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__oe$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__output_carry + wire width 7 output 20 \br_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__output_carry$36 + wire width 7 \br_op__insn_type$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__ok + wire input 12 \br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__ok$28 + wire \br_op__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__rc + wire output 26 \br_op__is_32bit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__rc$27 + wire \br_op__is_32bit$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__write_cr0 + wire input 11 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__write_cr0$34 + wire \br_op__lk$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__zero_a + wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__zero_a$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca + wire \br_op__lk$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$44 + wire width 4 input 15 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so + wire width 64 input 13 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 27 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$43 + wire width 64 input 14 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$next + attribute \src "libresoc.v:160848.7-160848.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len + wire width 64 \main_br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len$62 + wire width 64 \main_br_op__cia$13 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_alu_op__fn_unit$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data$48 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_br_op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__imm_data__ok + wire width 64 \main_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__imm_data__ok$49 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 \main_br_op__imm_data__data$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \main_br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry$58 + wire \main_br_op__imm_data__ok$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn + wire width 32 \main_br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn$63 + wire width 32 \main_br_op__insn$16 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -319710,8 +335279,9 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_alu_op__insn_type + wire width 7 \main_br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -319786,1856 +335356,985 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_alu_op__insn_type$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_out$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__output_carry$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__ok$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__rc$50 + wire width 7 \main_br_op__insn_type$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__write_cr0 + wire \main_br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__write_cr0$57 + wire \main_br_op__is_32bit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__zero_a + wire \main_br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__zero_a$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_br_op__lk$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o + wire width 64 \main_fast1$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb + wire \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \main_xer_ca$64 + wire width 64 \main_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_ca_ok + wire width 64 \main_fast2$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \main_xer_ov + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so + wire width 64 \main_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_so$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 17 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 16 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 23 \o + wire width 64 output 31 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$88 + wire width 64 \nia$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next + wire width 64 \nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 24 \o_ok + wire output 32 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$89 + wire \nia_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 34 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 54 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 57 \xer_ca$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 56 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:153784$8639 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:161506$8751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$66 + connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:153784$8639_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:153845.11-153892.4" - cell \input \input - connect \alu_op__data_len \input_alu_op__data_len - connect \alu_op__data_len$18 \input_alu_op__data_len$39 - connect \alu_op__fn_unit \input_alu_op__fn_unit - connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 - connect \alu_op__imm_data__data \input_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 - connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 - connect \alu_op__input_carry \input_alu_op__input_carry - connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 - connect \alu_op__insn \input_alu_op__insn - connect \alu_op__insn$19 \input_alu_op__insn$40 - connect \alu_op__insn_type \input_alu_op__insn_type - connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 - connect \alu_op__invert_in \input_alu_op__invert_in - connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 - connect \alu_op__invert_out \input_alu_op__invert_out - connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 - connect \alu_op__is_32bit \input_alu_op__is_32bit - connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 - connect \alu_op__is_signed \input_alu_op__is_signed - connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 - connect \alu_op__oe__oe \input_alu_op__oe__oe - connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 - connect \alu_op__oe__ok \input_alu_op__oe__ok - connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 - connect \alu_op__output_carry \input_alu_op__output_carry - connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 - connect \alu_op__rc__ok \input_alu_op__rc__ok - connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 - connect \alu_op__rc__rc \input_alu_op__rc__rc - connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 - connect \alu_op__write_cr0 \input_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 - connect \alu_op__zero_a \input_alu_op__zero_a - connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$22 - connect \ra \input_ra - connect \ra$20 \input_ra$41 - connect \rb \input_rb - connect \rb$21 \input_rb$42 - connect \xer_ca \input_xer_ca - connect \xer_ca$23 \input_xer_ca$44 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$43 + connect \Y $and$libresoc.v:161506$8751_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:153893.8-153945.4" - cell \main \main - connect \alu_op__data_len \main_alu_op__data_len - connect \alu_op__data_len$18 \main_alu_op__data_len$62 - connect \alu_op__fn_unit \main_alu_op__fn_unit - connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 - connect \alu_op__imm_data__data \main_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 - connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 - connect \alu_op__input_carry \main_alu_op__input_carry - connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 - connect \alu_op__insn \main_alu_op__insn - connect \alu_op__insn$19 \main_alu_op__insn$63 - connect \alu_op__insn_type \main_alu_op__insn_type - connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 - connect \alu_op__invert_in \main_alu_op__invert_in - connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 - connect \alu_op__invert_out \main_alu_op__invert_out - connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 - connect \alu_op__is_32bit \main_alu_op__is_32bit - connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 - connect \alu_op__is_signed \main_alu_op__is_signed - connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 - connect \alu_op__oe__oe \main_alu_op__oe__oe - connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 - connect \alu_op__oe__ok \main_alu_op__oe__ok - connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 - connect \alu_op__output_carry \main_alu_op__output_carry - connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 - connect \alu_op__rc__ok \main_alu_op__rc__ok - connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 - connect \alu_op__rc__rc \main_alu_op__rc__rc - connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 - connect \alu_op__write_cr0 \main_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 - connect \alu_op__zero_a \main_alu_op__zero_a - connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + attribute \src "libresoc.v:161539.13-161567.4" + cell \main$22 \main + connect \br_op__cia \main_br_op__cia + connect \br_op__cia$2 \main_br_op__cia$13 + connect \br_op__fn_unit \main_br_op__fn_unit + connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 + connect \br_op__imm_data__data \main_br_op__imm_data__data + connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 + connect \br_op__imm_data__ok \main_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 + connect \br_op__insn \main_br_op__insn + connect \br_op__insn$5 \main_br_op__insn$16 + connect \br_op__insn_type \main_br_op__insn_type + connect \br_op__insn_type$3 \main_br_op__insn_type$14 + connect \br_op__is_32bit \main_br_op__is_32bit + connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 + connect \br_op__lk \main_br_op__lk + connect \br_op__lk$8 \main_br_op__lk$19 connect \cr_a \main_cr_a - connect \cr_a_ok \main_cr_a_ok + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok connect \muxid \main_muxid - connect \muxid$1 \main_muxid$45 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \xer_ca \main_xer_ca - connect \xer_ca$20 \main_xer_ca$64 - connect \xer_ca_ok \main_xer_ca_ok - connect \xer_ov \main_xer_ov - connect \xer_ov_ok \main_xer_ov_ok - connect \xer_so \main_xer_so - connect \xer_so$21 \main_xer_so$65 + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:153946.9-153949.4" - cell \n$2 \n + attribute \src "libresoc.v:161568.10-161571.4" + cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:153950.9-153953.4" - cell \p$1 \p + attribute \src "libresoc.v:161572.10-161575.4" + cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:152677.7-152677.20" - process $proc$libresoc.v:152677$8750 + attribute \src "libresoc.v:160848.7-160848.20" + process $proc$libresoc.v:160848$8823 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:152682.13-152682.36" - process $proc$libresoc.v:152682$8751 - assign { } { } - assign $1\alu_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_op__data_len $1\alu_op__data_len[3:0] - end - attribute \src "libresoc.v:152704.14-152704.39" - process $proc$libresoc.v:152704$8752 - assign { } { } - assign $1\alu_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_op__fn_unit $1\alu_op__fn_unit[11:0] - end - attribute \src "libresoc.v:152739.14-152739.59" - process $proc$libresoc.v:152739$8753 - assign { } { } - assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:152748.7-152748.34" - process $proc$libresoc.v:152748$8754 - assign { } { } - assign $1\alu_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:152761.13-152761.39" - process $proc$libresoc.v:152761$8755 - assign { } { } - assign $1\alu_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_op__input_carry $1\alu_op__input_carry[1:0] - end - attribute \src "libresoc.v:152778.14-152778.34" - process $proc$libresoc.v:152778$8756 - assign { } { } - assign $1\alu_op__insn[31:0] 0 - sync always - sync init - update \alu_op__insn $1\alu_op__insn[31:0] - end - attribute \src "libresoc.v:152861.13-152861.38" - process $proc$libresoc.v:152861$8757 - assign { } { } - assign $1\alu_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_op__insn_type $1\alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:153018.7-153018.31" - process $proc$libresoc.v:153018$8758 - assign { } { } - assign $1\alu_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_op__invert_in $1\alu_op__invert_in[0:0] - end - attribute \src "libresoc.v:153027.7-153027.32" - process $proc$libresoc.v:153027$8759 + attribute \src "libresoc.v:160855.14-160855.51" + process $proc$libresoc.v:160855$8824 assign { } { } - assign $1\alu_op__invert_out[0:0] 1'0 + assign $0\br_op__cia$2[63:0]$8825 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__invert_out $1\alu_op__invert_out[0:0] + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8825 end - attribute \src "libresoc.v:153036.7-153036.30" - process $proc$libresoc.v:153036$8760 + attribute \src "libresoc.v:160911.14-160911.43" + process $proc$libresoc.v:160911$8826 assign { } { } - assign $1\alu_op__is_32bit[0:0] 1'0 + assign $0\br_op__fn_unit$4[13:0]$8827 14'00000000000000 sync always sync init - update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8827 end - attribute \src "libresoc.v:153045.7-153045.31" - process $proc$libresoc.v:153045$8761 + attribute \src "libresoc.v:160920.14-160920.62" + process $proc$libresoc.v:160920$8828 assign { } { } - assign $1\alu_op__is_signed[0:0] 1'0 + assign $0\br_op__imm_data__data$6[63:0]$8829 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__is_signed $1\alu_op__is_signed[0:0] + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8829 end - attribute \src "libresoc.v:153054.7-153054.28" - process $proc$libresoc.v:153054$8762 + attribute \src "libresoc.v:160929.7-160929.37" + process $proc$libresoc.v:160929$8830 assign { } { } - assign $1\alu_op__oe__oe[0:0] 1'0 + assign $0\br_op__imm_data__ok$7[0:0]$8831 1'0 sync always sync init - update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8831 end - attribute \src "libresoc.v:153063.7-153063.28" - process $proc$libresoc.v:153063$8763 + attribute \src "libresoc.v:160938.14-160938.37" + process $proc$libresoc.v:160938$8832 assign { } { } - assign $1\alu_op__oe__ok[0:0] 1'0 + assign $0\br_op__insn$5[31:0]$8833 0 sync always sync init - update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8833 end - attribute \src "libresoc.v:153072.7-153072.34" - process $proc$libresoc.v:153072$8764 + attribute \src "libresoc.v:161172.13-161172.41" + process $proc$libresoc.v:161172$8834 assign { } { } - assign $1\alu_op__output_carry[0:0] 1'0 + assign $0\br_op__insn_type$3[6:0]$8835 7'0000000 sync always sync init - update \alu_op__output_carry $1\alu_op__output_carry[0:0] + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8835 end - attribute \src "libresoc.v:153081.7-153081.28" - process $proc$libresoc.v:153081$8765 + attribute \src "libresoc.v:161181.7-161181.33" + process $proc$libresoc.v:161181$8836 assign { } { } - assign $1\alu_op__rc__ok[0:0] 1'0 + assign $0\br_op__is_32bit$9[0:0]$8837 1'0 sync always sync init - update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8837 end - attribute \src "libresoc.v:153090.7-153090.28" - process $proc$libresoc.v:153090$8766 + attribute \src "libresoc.v:161190.7-161190.27" + process $proc$libresoc.v:161190$8838 assign { } { } - assign $1\alu_op__rc__rc[0:0] 1'0 + assign $0\br_op__lk$8[0:0]$8839 1'0 sync always sync init - update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8839 end - attribute \src "libresoc.v:153099.7-153099.31" - process $proc$libresoc.v:153099$8767 + attribute \src "libresoc.v:161203.14-161203.47" + process $proc$libresoc.v:161203$8840 assign { } { } - assign $1\alu_op__write_cr0[0:0] 1'0 + assign $0\fast1$10[63:0]$8841 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + update \fast1$10 $0\fast1$10[63:0]$8841 end - attribute \src "libresoc.v:153108.7-153108.28" - process $proc$libresoc.v:153108$8768 + attribute \src "libresoc.v:161210.7-161210.22" + process $proc$libresoc.v:161210$8842 assign { } { } - assign $1\alu_op__zero_a[0:0] 1'0 + assign $1\fast1_ok[0:0] 1'0 sync always sync init - update \alu_op__zero_a $1\alu_op__zero_a[0:0] + update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:153121.13-153121.24" - process $proc$libresoc.v:153121$8769 + attribute \src "libresoc.v:161219.14-161219.47" + process $proc$libresoc.v:161219$8843 assign { } { } - assign $1\cr_a[3:0] 4'0000 + assign $0\fast2$11[63:0]$8844 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \cr_a $1\cr_a[3:0] + update \fast2$11 $0\fast2$11[63:0]$8844 end - attribute \src "libresoc.v:153128.7-153128.21" - process $proc$libresoc.v:153128$8770 + attribute \src "libresoc.v:161226.7-161226.22" + process $proc$libresoc.v:161226$8845 assign { } { } - assign $1\cr_a_ok[0:0] 1'0 + assign $1\fast2_ok[0:0] 1'0 sync always sync init - update \cr_a_ok $1\cr_a_ok[0:0] + update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:153693.13-153693.25" - process $proc$libresoc.v:153693$8771 + attribute \src "libresoc.v:161469.13-161469.29" + process $proc$libresoc.v:161469$8846 assign { } { } - assign $1\muxid[1:0] 2'00 + assign $0\muxid$1[1:0]$8847 2'00 sync always sync init - update \muxid $1\muxid[1:0] + update \muxid$1 $0\muxid$1[1:0]$8847 end - attribute \src "libresoc.v:153708.14-153708.38" - process $proc$libresoc.v:153708$8772 + attribute \src "libresoc.v:161482.14-161482.40" + process $proc$libresoc.v:161482$8848 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o $1\o[63:0] + update \nia $1\nia[63:0] end - attribute \src "libresoc.v:153715.7-153715.18" - process $proc$libresoc.v:153715$8773 + attribute \src "libresoc.v:161489.7-161489.20" + process $proc$libresoc.v:161489$8849 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $1\nia_ok[0:0] 1'0 sync always sync init - update \o_ok $1\o_ok[0:0] + update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:153729.7-153729.20" - process $proc$libresoc.v:153729$8774 + attribute \src "libresoc.v:161503.7-161503.20" + process $proc$libresoc.v:161503$8850 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:153738.13-153738.26" - process $proc$libresoc.v:153738$8775 - assign { } { } - assign $1\xer_ca[1:0] 2'00 - sync always - sync init - update \xer_ca $1\xer_ca[1:0] - end - attribute \src "libresoc.v:153747.7-153747.23" - process $proc$libresoc.v:153747$8776 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 - sync always - sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:153754.13-153754.26" - process $proc$libresoc.v:153754$8777 - assign { } { } - assign $1\xer_ov[1:0] 2'00 - sync always - sync init - update \xer_ov $1\xer_ov[1:0] - end - attribute \src "libresoc.v:153761.7-153761.23" - process $proc$libresoc.v:153761$8778 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:153768.7-153768.20" - process $proc$libresoc.v:153768$8779 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:153777.7-153777.23" - process $proc$libresoc.v:153777$8780 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:153785.3-153786.29" - process $proc$libresoc.v:153785$8640 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:153787.3-153788.35" - process $proc$libresoc.v:153787$8641 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:153789.3-153790.29" - process $proc$libresoc.v:153789$8642 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "libresoc.v:153791.3-153792.35" - process $proc$libresoc.v:153791$8643 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:153793.3-153794.29" - process $proc$libresoc.v:153793$8644 - assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next - sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] - end - attribute \src "libresoc.v:153795.3-153796.35" - process $proc$libresoc.v:153795$8645 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:153797.3-153798.25" - process $proc$libresoc.v:153797$8646 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:153799.3-153800.31" - process $proc$libresoc.v:153799$8647 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:153801.3-153802.19" - process $proc$libresoc.v:153801$8648 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:153803.3-153804.25" - process $proc$libresoc.v:153803$8649 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:153805.3-153806.51" - process $proc$libresoc.v:153805$8650 - assign { } { } - assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next - sync posedge \coresync_clk - update \alu_op__insn_type $0\alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:153807.3-153808.47" - process $proc$libresoc.v:153807$8651 + attribute \src "libresoc.v:161507.3-161508.23" + process $proc$libresoc.v:161507$8752 assign { } { } - assign $0\alu_op__fn_unit[11:0] \alu_op__fn_unit$next - sync posedge \coresync_clk - update \alu_op__fn_unit $0\alu_op__fn_unit[11:0] - end - attribute \src "libresoc.v:153809.3-153810.61" - process $proc$libresoc.v:153809$8652 - assign { } { } - assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:153811.3-153812.57" - process $proc$libresoc.v:153811$8653 - assign { } { } - assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:153813.3-153814.45" - process $proc$libresoc.v:153813$8654 - assign { } { } - assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + assign $0\nia[63:0] \nia$next sync posedge \coresync_clk - update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:153815.3-153816.45" - process $proc$libresoc.v:153815$8655 + attribute \src "libresoc.v:161509.3-161510.29" + process $proc$libresoc.v:161509$8753 assign { } { } - assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk - update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:153817.3-153818.45" - process $proc$libresoc.v:153817$8656 + attribute \src "libresoc.v:161511.3-161512.35" + process $proc$libresoc.v:161511$8754 assign { } { } - assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + assign $0\fast2$11[63:0]$8755 \fast2$11$next sync posedge \coresync_clk - update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + update \fast2$11 $0\fast2$11[63:0]$8755 end - attribute \src "libresoc.v:153819.3-153820.45" - process $proc$libresoc.v:153819$8657 + attribute \src "libresoc.v:161513.3-161514.33" + process $proc$libresoc.v:161513$8756 assign { } { } - assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk - update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:153821.3-153822.51" - process $proc$libresoc.v:153821$8658 + attribute \src "libresoc.v:161515.3-161516.35" + process $proc$libresoc.v:161515$8757 assign { } { } - assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + assign $0\fast1$10[63:0]$8758 \fast1$10$next sync posedge \coresync_clk - update \alu_op__invert_in $0\alu_op__invert_in[0:0] + update \fast1$10 $0\fast1$10[63:0]$8758 end - attribute \src "libresoc.v:153823.3-153824.45" - process $proc$libresoc.v:153823$8659 + attribute \src "libresoc.v:161517.3-161518.33" + process $proc$libresoc.v:161517$8759 assign { } { } - assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \alu_op__zero_a $0\alu_op__zero_a[0:0] + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:153825.3-153826.53" - process $proc$libresoc.v:153825$8660 + attribute \src "libresoc.v:161519.3-161520.43" + process $proc$libresoc.v:161519$8760 assign { } { } - assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + assign $0\br_op__cia$2[63:0]$8761 \br_op__cia$2$next sync posedge \coresync_clk - update \alu_op__invert_out $0\alu_op__invert_out[0:0] + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8761 end - attribute \src "libresoc.v:153827.3-153828.51" - process $proc$libresoc.v:153827$8661 + attribute \src "libresoc.v:161521.3-161522.55" + process $proc$libresoc.v:161521$8762 assign { } { } - assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + assign $0\br_op__insn_type$3[6:0]$8763 \br_op__insn_type$3$next sync posedge \coresync_clk - update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8763 end - attribute \src "libresoc.v:153829.3-153830.55" - process $proc$libresoc.v:153829$8662 + attribute \src "libresoc.v:161523.3-161524.51" + process $proc$libresoc.v:161523$8764 assign { } { } - assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + assign $0\br_op__fn_unit$4[13:0]$8765 \br_op__fn_unit$4$next sync posedge \coresync_clk - update \alu_op__input_carry $0\alu_op__input_carry[1:0] + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8765 end - attribute \src "libresoc.v:153831.3-153832.57" - process $proc$libresoc.v:153831$8663 + attribute \src "libresoc.v:161525.3-161526.45" + process $proc$libresoc.v:161525$8766 assign { } { } - assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + assign $0\br_op__insn$5[31:0]$8767 \br_op__insn$5$next sync posedge \coresync_clk - update \alu_op__output_carry $0\alu_op__output_carry[0:0] + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8767 end - attribute \src "libresoc.v:153833.3-153834.49" - process $proc$libresoc.v:153833$8664 + attribute \src "libresoc.v:161527.3-161528.65" + process $proc$libresoc.v:161527$8768 assign { } { } - assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + assign $0\br_op__imm_data__data$6[63:0]$8769 \br_op__imm_data__data$6$next sync posedge \coresync_clk - update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8769 end - attribute \src "libresoc.v:153835.3-153836.51" - process $proc$libresoc.v:153835$8665 + attribute \src "libresoc.v:161529.3-161530.61" + process $proc$libresoc.v:161529$8770 assign { } { } - assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + assign $0\br_op__imm_data__ok$7[0:0]$8771 \br_op__imm_data__ok$7$next sync posedge \coresync_clk - update \alu_op__is_signed $0\alu_op__is_signed[0:0] + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8771 end - attribute \src "libresoc.v:153837.3-153838.49" - process $proc$libresoc.v:153837$8666 + attribute \src "libresoc.v:161531.3-161532.41" + process $proc$libresoc.v:161531$8772 assign { } { } - assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + assign $0\br_op__lk$8[0:0]$8773 \br_op__lk$8$next sync posedge \coresync_clk - update \alu_op__data_len $0\alu_op__data_len[3:0] + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8773 end - attribute \src "libresoc.v:153839.3-153840.41" - process $proc$libresoc.v:153839$8667 + attribute \src "libresoc.v:161533.3-161534.53" + process $proc$libresoc.v:161533$8774 assign { } { } - assign $0\alu_op__insn[31:0] \alu_op__insn$next + assign $0\br_op__is_32bit$9[0:0]$8775 \br_op__is_32bit$9$next sync posedge \coresync_clk - update \alu_op__insn $0\alu_op__insn[31:0] + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8775 end - attribute \src "libresoc.v:153841.3-153842.27" - process $proc$libresoc.v:153841$8668 + attribute \src "libresoc.v:161535.3-161536.33" + process $proc$libresoc.v:161535$8776 assign { } { } - assign $0\muxid[1:0] \muxid$next + assign $0\muxid$1[1:0]$8777 \muxid$1$next sync posedge \coresync_clk - update \muxid $0\muxid[1:0] + update \muxid$1 $0\muxid$1[1:0]$8777 end - attribute \src "libresoc.v:153843.3-153844.29" - process $proc$libresoc.v:153843$8669 + attribute \src "libresoc.v:161537.3-161538.29" + process $proc$libresoc.v:161537$8778 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:153954.3-153972.6" - process $proc$libresoc.v:153954$8670 - assign { } { } + attribute \src "libresoc.v:161576.3-161593.6" + process $proc$libresoc.v:161576$8779 assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8671 $1\cr_a$next[3:0]$8673 - assign { } { } - assign $0\cr_a_ok$next[0:0]$8672 $2\cr_a_ok$next[0:0]$8675 - attribute \src "libresoc.v:153955.5-153955.29" + assign $0\r_busy$next[0:0]$8780 $2\r_busy$next[0:0]$8782 + attribute \src "libresoc.v:161577.5-161577.29" switch \initial - attribute \src "libresoc.v:153955.9-153955.17" + attribute \src "libresoc.v:161577.9-161577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8674 $1\cr_a$next[3:0]$8673 } { \cr_a_ok$91 \cr_a$90 } + assign $1\r_busy$next[0:0]$8781 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8674 $1\cr_a$next[3:0]$8673 } { \cr_a_ok$91 \cr_a$90 } + assign $1\r_busy$next[0:0]$8781 1'0 case - assign $1\cr_a$next[3:0]$8673 \cr_a - assign $1\cr_a_ok$next[0:0]$8674 \cr_a_ok + assign $1\r_busy$next[0:0]$8781 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8675 1'0 + assign $2\r_busy$next[0:0]$8782 1'0 case - assign $2\cr_a_ok$next[0:0]$8675 $1\cr_a_ok$next[0:0]$8674 + assign $2\r_busy$next[0:0]$8782 $1\r_busy$next[0:0]$8781 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8671 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8672 + update \r_busy$next $0\r_busy$next[0:0]$8780 end - attribute \src "libresoc.v:153973.3-153991.6" - process $proc$libresoc.v:153973$8676 - assign { } { } + attribute \src "libresoc.v:161594.3-161606.6" + process $proc$libresoc.v:161594$8783 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$next[1:0]$8678 $1\xer_ca$next[1:0]$8680 - assign $0\xer_ca_ok$next[0:0]$8677 $2\xer_ca_ok$next[0:0]$8681 - attribute \src "libresoc.v:153974.5-153974.29" + assign $0\muxid$1$next[1:0]$8784 $1\muxid$1$next[1:0]$8785 + attribute \src "libresoc.v:161595.5-161595.29" switch \initial - attribute \src "libresoc.v:153974.9-153974.17" + attribute \src "libresoc.v:161595.9-161595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8679 $1\xer_ca$next[1:0]$8680 } { \xer_ca_ok$93 \xer_ca$92 } + assign $1\muxid$1$next[1:0]$8785 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8679 $1\xer_ca$next[1:0]$8680 } { \xer_ca_ok$93 \xer_ca$92 } - case - assign $1\xer_ca_ok$next[0:0]$8679 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8680 \xer_ca - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$next[0:0]$8681 1'0 + assign $1\muxid$1$next[1:0]$8785 \muxid$26 case - assign $2\xer_ca_ok$next[0:0]$8681 $1\xer_ca_ok$next[0:0]$8679 + assign $1\muxid$1$next[1:0]$8785 \muxid$1 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8677 - update \xer_ca$next $0\xer_ca$next[1:0]$8678 + update \muxid$1$next $0\muxid$1$next[1:0]$8784 end - attribute \src "libresoc.v:153992.3-154010.6" - process $proc$libresoc.v:153992$8682 + attribute \src "libresoc.v:161607.3-161634.6" + process $proc$libresoc.v:161607$8786 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8683 $1\xer_ov$next[1:0]$8685 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8684 $2\xer_ov_ok$next[0:0]$8687 - attribute \src "libresoc.v:153993.5-153993.29" - switch \initial - attribute \src "libresoc.v:153993.9-153993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8686 $1\xer_ov$next[1:0]$8685 } { \xer_ov_ok$95 \xer_ov$94 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8686 $1\xer_ov$next[1:0]$8685 } { \xer_ov_ok$95 \xer_ov$94 } - case - assign $1\xer_ov$next[1:0]$8685 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8686 \xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$next[0:0]$8687 1'0 - case - assign $2\xer_ov_ok$next[0:0]$8687 $1\xer_ov_ok$next[0:0]$8686 - end - sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8683 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8684 - end - attribute \src "libresoc.v:154011.3-154029.6" - process $proc$libresoc.v:154011$8688 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8689 $1\xer_so$next[0:0]$8691 assign { } { } - assign $0\xer_so_ok$next[0:0]$8690 $2\xer_so_ok$next[0:0]$8693 - attribute \src "libresoc.v:154012.5-154012.29" + assign { } { } + assign $0\br_op__cia$2$next[63:0]$8787 $1\br_op__cia$2$next[63:0]$8795 + assign $0\br_op__fn_unit$4$next[13:0]$8788 $1\br_op__fn_unit$4$next[13:0]$8796 + assign { } { } + assign { } { } + assign $0\br_op__insn$5$next[31:0]$8791 $1\br_op__insn$5$next[31:0]$8799 + assign $0\br_op__insn_type$3$next[6:0]$8792 $1\br_op__insn_type$3$next[6:0]$8800 + assign $0\br_op__is_32bit$9$next[0:0]$8793 $1\br_op__is_32bit$9$next[0:0]$8801 + assign $0\br_op__lk$8$next[0:0]$8794 $1\br_op__lk$8$next[0:0]$8802 + assign $0\br_op__imm_data__data$6$next[63:0]$8789 $2\br_op__imm_data__data$6$next[63:0]$8803 + assign $0\br_op__imm_data__ok$7$next[0:0]$8790 $2\br_op__imm_data__ok$7$next[0:0]$8804 + attribute \src "libresoc.v:161608.5-161608.29" switch \initial - attribute \src "libresoc.v:154012.9-154012.17" + attribute \src "libresoc.v:161608.9-161608.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8692 $1\xer_so$next[0:0]$8691 } { \xer_so_ok$97 \xer_so$96 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8692 $1\xer_so$next[0:0]$8691 } { \xer_so_ok$97 \xer_so$96 } - case - assign $1\xer_so$next[0:0]$8691 \xer_so - assign $1\xer_so_ok$next[0:0]$8692 \xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8693 1'0 - case - assign $2\xer_so_ok$next[0:0]$8693 $1\xer_so_ok$next[0:0]$8692 - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$8689 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8690 - end - attribute \src "libresoc.v:154030.3-154047.6" - process $proc$libresoc.v:154030$8694 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8695 $2\r_busy$next[0:0]$8697 - attribute \src "libresoc.v:154031.5-154031.29" - switch \initial - attribute \src "libresoc.v:154031.9-154031.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8696 1'1 + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8801 $1\br_op__lk$8$next[0:0]$8802 $1\br_op__imm_data__ok$7$next[0:0]$8798 $1\br_op__imm_data__data$6$next[63:0]$8797 $1\br_op__insn$5$next[31:0]$8799 $1\br_op__fn_unit$4$next[13:0]$8796 $1\br_op__insn_type$3$next[6:0]$8800 $1\br_op__cia$2$next[63:0]$8795 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8696 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8801 $1\br_op__lk$8$next[0:0]$8802 $1\br_op__imm_data__ok$7$next[0:0]$8798 $1\br_op__imm_data__data$6$next[63:0]$8797 $1\br_op__insn$5$next[31:0]$8799 $1\br_op__fn_unit$4$next[13:0]$8796 $1\br_op__insn_type$3$next[6:0]$8800 $1\br_op__cia$2$next[63:0]$8795 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case - assign $1\r_busy$next[0:0]$8696 \r_busy + assign $1\br_op__cia$2$next[63:0]$8795 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[13:0]$8796 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8797 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8798 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8799 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8800 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8801 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8802 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8697 1'0 + assign { } { } + assign $2\br_op__imm_data__data$6$next[63:0]$8803 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8804 1'0 case - assign $2\r_busy$next[0:0]$8697 $1\r_busy$next[0:0]$8696 + assign $2\br_op__imm_data__data$6$next[63:0]$8803 $1\br_op__imm_data__data$6$next[63:0]$8797 + assign $2\br_op__imm_data__ok$7$next[0:0]$8804 $1\br_op__imm_data__ok$7$next[0:0]$8798 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8695 + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8787 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8788 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8789 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8790 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8791 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8792 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8793 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8794 end - attribute \src "libresoc.v:154048.3-154060.6" - process $proc$libresoc.v:154048$8698 + attribute \src "libresoc.v:161635.3-161653.6" + process $proc$libresoc.v:161635$8805 + assign { } { } assign { } { } assign { } { } - assign $0\muxid$next[1:0]$8699 $1\muxid$next[1:0]$8700 - attribute \src "libresoc.v:154049.5-154049.29" + assign { } { } + assign $0\fast1$10$next[63:0]$8806 $1\fast1$10$next[63:0]$8808 + assign { } { } + assign $0\fast1_ok$next[0:0]$8807 $2\fast1_ok$next[0:0]$8810 + attribute \src "libresoc.v:161636.5-161636.29" switch \initial - attribute \src "libresoc.v:154049.9-154049.17" + attribute \src "libresoc.v:161636.9-161636.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$8700 \muxid$69 + assign { } { } + assign { $1\fast1_ok$next[0:0]$8809 $1\fast1$10$next[63:0]$8808 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$8700 \muxid$69 + assign { } { } + assign { $1\fast1_ok$next[0:0]$8809 $1\fast1$10$next[63:0]$8808 } { \fast1_ok$36 \fast1$35 } case - assign $1\muxid$next[1:0]$8700 \muxid + assign $1\fast1$10$next[63:0]$8808 \fast1$10 + assign $1\fast1_ok$next[0:0]$8809 \fast1_ok end - sync always - update \muxid$next $0\muxid$next[1:0]$8699 - end - attribute \src "libresoc.v:154061.3-154102.6" - process $proc$libresoc.v:154061$8701 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_op__data_len$next[3:0]$8702 $1\alu_op__data_len$next[3:0]$8720 - assign $0\alu_op__fn_unit$next[11:0]$8703 $1\alu_op__fn_unit$next[11:0]$8721 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8810 1'0 + case + assign $2\fast1_ok$next[0:0]$8810 $1\fast1_ok$next[0:0]$8809 + end + sync always + update \fast1$10$next $0\fast1$10$next[63:0]$8806 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8807 + end + attribute \src "libresoc.v:161654.3-161672.6" + process $proc$libresoc.v:161654$8811 assign { } { } - assign $0\alu_op__input_carry$next[1:0]$8706 $1\alu_op__input_carry$next[1:0]$8724 - assign $0\alu_op__insn$next[31:0]$8707 $1\alu_op__insn$next[31:0]$8725 - assign $0\alu_op__insn_type$next[6:0]$8708 $1\alu_op__insn_type$next[6:0]$8726 - assign $0\alu_op__invert_in$next[0:0]$8709 $1\alu_op__invert_in$next[0:0]$8727 - assign $0\alu_op__invert_out$next[0:0]$8710 $1\alu_op__invert_out$next[0:0]$8728 - assign $0\alu_op__is_32bit$next[0:0]$8711 $1\alu_op__is_32bit$next[0:0]$8729 - assign $0\alu_op__is_signed$next[0:0]$8712 $1\alu_op__is_signed$next[0:0]$8730 assign { } { } assign { } { } - assign $0\alu_op__output_carry$next[0:0]$8715 $1\alu_op__output_carry$next[0:0]$8733 assign { } { } + assign $0\fast2$11$next[63:0]$8812 $1\fast2$11$next[63:0]$8814 assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$8718 $1\alu_op__write_cr0$next[0:0]$8736 - assign $0\alu_op__zero_a$next[0:0]$8719 $1\alu_op__zero_a$next[0:0]$8737 - assign $0\alu_op__imm_data__data$next[63:0]$8704 $2\alu_op__imm_data__data$next[63:0]$8738 - assign $0\alu_op__imm_data__ok$next[0:0]$8705 $2\alu_op__imm_data__ok$next[0:0]$8739 - assign $0\alu_op__oe__oe$next[0:0]$8713 $2\alu_op__oe__oe$next[0:0]$8740 - assign $0\alu_op__oe__ok$next[0:0]$8714 $2\alu_op__oe__ok$next[0:0]$8741 - assign $0\alu_op__rc__ok$next[0:0]$8716 $2\alu_op__rc__ok$next[0:0]$8742 - assign $0\alu_op__rc__rc$next[0:0]$8717 $2\alu_op__rc__rc$next[0:0]$8743 - attribute \src "libresoc.v:154062.5-154062.29" + assign $0\fast2_ok$next[0:0]$8813 $2\fast2_ok$next[0:0]$8816 + attribute \src "libresoc.v:161655.5-161655.29" switch \initial - attribute \src "libresoc.v:154062.9-154062.17" + attribute \src "libresoc.v:161655.9-161655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$next[31:0]$8725 $1\alu_op__data_len$next[3:0]$8720 $1\alu_op__is_signed$next[0:0]$8730 $1\alu_op__is_32bit$next[0:0]$8729 $1\alu_op__output_carry$next[0:0]$8733 $1\alu_op__input_carry$next[1:0]$8724 $1\alu_op__write_cr0$next[0:0]$8736 $1\alu_op__invert_out$next[0:0]$8728 $1\alu_op__zero_a$next[0:0]$8737 $1\alu_op__invert_in$next[0:0]$8727 $1\alu_op__oe__ok$next[0:0]$8732 $1\alu_op__oe__oe$next[0:0]$8731 $1\alu_op__rc__ok$next[0:0]$8734 $1\alu_op__rc__rc$next[0:0]$8735 $1\alu_op__imm_data__ok$next[0:0]$8723 $1\alu_op__imm_data__data$next[63:0]$8722 $1\alu_op__fn_unit$next[11:0]$8721 $1\alu_op__insn_type$next[6:0]$8726 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\fast2_ok$next[0:0]$8815 $1\fast2$11$next[63:0]$8814 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$next[31:0]$8725 $1\alu_op__data_len$next[3:0]$8720 $1\alu_op__is_signed$next[0:0]$8730 $1\alu_op__is_32bit$next[0:0]$8729 $1\alu_op__output_carry$next[0:0]$8733 $1\alu_op__input_carry$next[1:0]$8724 $1\alu_op__write_cr0$next[0:0]$8736 $1\alu_op__invert_out$next[0:0]$8728 $1\alu_op__zero_a$next[0:0]$8737 $1\alu_op__invert_in$next[0:0]$8727 $1\alu_op__oe__ok$next[0:0]$8732 $1\alu_op__oe__oe$next[0:0]$8731 $1\alu_op__rc__ok$next[0:0]$8734 $1\alu_op__rc__rc$next[0:0]$8735 $1\alu_op__imm_data__ok$next[0:0]$8723 $1\alu_op__imm_data__data$next[63:0]$8722 $1\alu_op__fn_unit$next[11:0]$8721 $1\alu_op__insn_type$next[6:0]$8726 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\fast2_ok$next[0:0]$8815 $1\fast2$11$next[63:0]$8814 } { \fast2_ok$38 \fast2$37 } case - assign $1\alu_op__data_len$next[3:0]$8720 \alu_op__data_len - assign $1\alu_op__fn_unit$next[11:0]$8721 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$8722 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$8723 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$8724 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$8725 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$8726 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$8727 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$8728 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$8729 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$8730 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$8731 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$8732 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$8733 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$8734 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$8735 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$8736 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$8737 \alu_op__zero_a + assign $1\fast2$11$next[63:0]$8814 \fast2$11 + assign $1\fast2_ok$next[0:0]$8815 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$8738 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$8739 1'0 - assign $2\alu_op__rc__rc$next[0:0]$8743 1'0 - assign $2\alu_op__rc__ok$next[0:0]$8742 1'0 - assign $2\alu_op__oe__oe$next[0:0]$8740 1'0 - assign $2\alu_op__oe__ok$next[0:0]$8741 1'0 + assign $2\fast2_ok$next[0:0]$8816 1'0 case - assign $2\alu_op__imm_data__data$next[63:0]$8738 $1\alu_op__imm_data__data$next[63:0]$8722 - assign $2\alu_op__imm_data__ok$next[0:0]$8739 $1\alu_op__imm_data__ok$next[0:0]$8723 - assign $2\alu_op__oe__oe$next[0:0]$8740 $1\alu_op__oe__oe$next[0:0]$8731 - assign $2\alu_op__oe__ok$next[0:0]$8741 $1\alu_op__oe__ok$next[0:0]$8732 - assign $2\alu_op__rc__ok$next[0:0]$8742 $1\alu_op__rc__ok$next[0:0]$8734 - assign $2\alu_op__rc__rc$next[0:0]$8743 $1\alu_op__rc__rc$next[0:0]$8735 + assign $2\fast2_ok$next[0:0]$8816 $1\fast2_ok$next[0:0]$8815 end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8702 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[11:0]$8703 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8704 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8705 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8706 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8707 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8708 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8709 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8710 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8711 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8712 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8713 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8714 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8715 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8716 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8717 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8718 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8719 + update \fast2$11$next $0\fast2$11$next[63:0]$8812 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8813 end - attribute \src "libresoc.v:154103.3-154121.6" - process $proc$libresoc.v:154103$8744 + attribute \src "libresoc.v:161673.3-161691.6" + process $proc$libresoc.v:161673$8817 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8745 $1\o$next[63:0]$8747 + assign $0\nia$next[63:0]$8818 $1\nia$next[63:0]$8820 assign { } { } - assign $0\o_ok$next[0:0]$8746 $2\o_ok$next[0:0]$8749 - attribute \src "libresoc.v:154104.5-154104.29" + assign $0\nia_ok$next[0:0]$8819 $2\nia_ok$next[0:0]$8822 + attribute \src "libresoc.v:161674.5-161674.29" switch \initial - attribute \src "libresoc.v:154104.9-154104.17" + attribute \src "libresoc.v:161674.9-161674.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8748 $1\o$next[63:0]$8747 } { \o_ok$89 \o$88 } + assign { $1\nia_ok$next[0:0]$8821 $1\nia$next[63:0]$8820 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8748 $1\o$next[63:0]$8747 } { \o_ok$89 \o$88 } + assign { $1\nia_ok$next[0:0]$8821 $1\nia$next[63:0]$8820 } { \nia_ok$40 \nia$39 } case - assign $1\o$next[63:0]$8747 \o - assign $1\o_ok$next[0:0]$8748 \o_ok + assign $1\nia$next[63:0]$8820 \nia + assign $1\nia_ok$next[0:0]$8821 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8749 1'0 + assign $2\nia_ok$next[0:0]$8822 1'0 case - assign $2\o_ok$next[0:0]$8749 $1\o_ok$next[0:0]$8748 + assign $2\nia_ok$next[0:0]$8822 $1\nia_ok$next[0:0]$8821 end sync always - update \o$next $0\o$next[63:0]$8745 - update \o_ok$next $0\o_ok$next[0:0]$8746 + update \nia$next $0\nia$next[63:0]$8818 + update \nia_ok$next $0\nia_ok$next[0:0]$8819 end - connect \$67 $and$libresoc.v:153784$8639_Y - connect \xer_so_ok$98 1'0 + connect \$24 $and$libresoc.v:161506$8751_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } - connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } - connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } - connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } - connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } - connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } - connect \muxid$69 \main_muxid$45 - connect \p_valid_i_p_ready_o \$67 + connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$66 \p_valid_i - connect \main_xer_ca \input_xer_ca$44 - connect \main_xer_so \input_xer_so$43 - connect \main_rb \input_rb$42 - connect \main_ra \input_ra$41 - connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } - connect \main_muxid \input_muxid$22 - connect \input_xer_ca \xer_ca$21 - connect \input_xer_so \xer_so$20 - connect \input_rb \rb - connect \input_ra \ra - connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } - connect \input_muxid \muxid$1 + connect \p_valid_i$23 \p_valid_i + connect \main_cr_a \cr_a + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \main_muxid \muxid end -attribute \src "libresoc.v:154151.1-155566.10" +attribute \src "libresoc.v:161711.1-162641.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" -module \pipe1$110 - attribute \src "libresoc.v:155499.3-155517.6" - wire width 4 $0\cr_a$next[3:0]$8870 - attribute \src "libresoc.v:155241.3-155242.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:155499.3-155517.6" - wire $0\cr_a_ok$next[0:0]$8871 - attribute \src "libresoc.v:155243.3-155244.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:154152.7-154152.20" +module \pipe$64 + attribute \src "libresoc.v:162544.3-162562.6" + wire width 64 $0\fast1$7$next[63:0]$8910 + attribute \src "libresoc.v:162397.3-162398.33" + wire width 64 $0\fast1$7[63:0]$8862 + attribute \src "libresoc.v:161725.14-161725.46" + wire width 64 $0\fast1$7[63:0]$8934 + attribute \src "libresoc.v:162544.3-162562.6" + wire $0\fast1_ok$next[0:0]$8909 + attribute \src "libresoc.v:162399.3-162400.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:161712.7-161712.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155426.3-155438.6" - wire width 2 $0\muxid$next[1:0]$8820 - attribute \src "libresoc.v:155283.3-155284.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:155480.3-155498.6" - wire width 64 $0\o$next[63:0]$8864 - attribute \src "libresoc.v:155245.3-155246.19" + attribute \src "libresoc.v:162477.3-162489.6" + wire width 2 $0\muxid$1$next[1:0]$8885 + attribute \src "libresoc.v:162417.3-162418.33" + wire width 2 $0\muxid$1[1:0]$8878 + attribute \src "libresoc.v:161739.13-161739.29" + wire width 2 $0\muxid$1[1:0]$8937 + attribute \src "libresoc.v:162506.3-162524.6" + wire width 64 $0\o$next[63:0]$8897 + attribute \src "libresoc.v:162405.3-162406.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:155480.3-155498.6" - wire $0\o_ok$next[0:0]$8865 - attribute \src "libresoc.v:155247.3-155248.25" + attribute \src "libresoc.v:162506.3-162524.6" + wire $0\o_ok$next[0:0]$8898 + attribute \src "libresoc.v:162407.3-162408.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:155408.3-155425.6" - wire $0\r_busy$next[0:0]$8816 - attribute \src "libresoc.v:155285.3-155286.29" + attribute \src "libresoc.v:162459.3-162476.6" + wire $0\r_busy$next[0:0]$8881 + attribute \src "libresoc.v:162419.3-162420.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 12 $0\sr_op__fn_unit$next[11:0]$8823 - attribute \src "libresoc.v:155251.3-155252.45" - wire width 12 $0\sr_op__fn_unit[11:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$8824 - attribute \src "libresoc.v:155253.3-155254.59" - wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__imm_data__ok$next[0:0]$8825 - attribute \src "libresoc.v:155255.3-155256.55" - wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$8826 - attribute \src "libresoc.v:155269.3-155270.53" - wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__input_cr$next[0:0]$8827 - attribute \src "libresoc.v:155273.3-155274.47" - wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 32 $0\sr_op__insn$next[31:0]$8828 - attribute \src "libresoc.v:155281.3-155282.39" - wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$8829 - attribute \src "libresoc.v:155249.3-155250.49" - wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__invert_in$next[0:0]$8830 - attribute \src "libresoc.v:155267.3-155268.49" - wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__is_32bit$next[0:0]$8831 - attribute \src "libresoc.v:155277.3-155278.47" - wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__is_signed$next[0:0]$8832 - attribute \src "libresoc.v:155279.3-155280.49" - wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__oe__oe$next[0:0]$8833 - attribute \src "libresoc.v:155261.3-155262.43" - wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__oe__ok$next[0:0]$8834 - attribute \src "libresoc.v:155263.3-155264.43" - wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__output_carry$next[0:0]$8835 - attribute \src "libresoc.v:155271.3-155272.55" - wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__output_cr$next[0:0]$8836 - attribute \src "libresoc.v:155275.3-155276.49" - wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__rc__ok$next[0:0]$8837 - attribute \src "libresoc.v:155259.3-155260.43" - wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__rc__rc$next[0:0]$8838 - attribute \src "libresoc.v:155257.3-155258.43" - wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $0\sr_op__write_cr0$next[0:0]$8839 - attribute \src "libresoc.v:155265.3-155266.49" - wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:155389.3-155407.6" - wire width 2 $0\xer_ca$next[1:0]$8811 - attribute \src "libresoc.v:155233.3-155234.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:155389.3-155407.6" - wire $0\xer_ca_ok$next[0:0]$8810 - attribute \src "libresoc.v:155235.3-155236.35" + attribute \src "libresoc.v:162525.3-162543.6" + wire width 64 $0\spr1$6$next[63:0]$8903 + attribute \src "libresoc.v:162401.3-162402.31" + wire width 64 $0\spr1$6[63:0]$8865 + attribute \src "libresoc.v:161784.14-161784.45" + wire width 64 $0\spr1$6[63:0]$8942 + attribute \src "libresoc.v:162525.3-162543.6" + wire $0\spr1_ok$next[0:0]$8904 + attribute \src "libresoc.v:162403.3-162404.31" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:162490.3-162505.6" + wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8888 + attribute \src "libresoc.v:162411.3-162412.53" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8872 + attribute \src "libresoc.v:162081.14-162081.44" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8945 + attribute \src "libresoc.v:162490.3-162505.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8889 + attribute \src "libresoc.v:162413.3-162414.47" + wire width 32 $0\spr_op__insn$4[31:0]$8874 + attribute \src "libresoc.v:162090.14-162090.38" + wire width 32 $0\spr_op__insn$4[31:0]$8947 + attribute \src "libresoc.v:162490.3-162505.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8890 + attribute \src "libresoc.v:162409.3-162410.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8870 + attribute \src "libresoc.v:162247.13-162247.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8949 + attribute \src "libresoc.v:162490.3-162505.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8891 + attribute \src "libresoc.v:162415.3-162416.55" + wire $0\spr_op__is_32bit$5[0:0]$8876 + attribute \src "libresoc.v:162333.7-162333.34" + wire $0\spr_op__is_32bit$5[0:0]$8951 + attribute \src "libresoc.v:162601.3-162619.6" + wire width 2 $0\xer_ca$10$next[1:0]$8927 + attribute \src "libresoc.v:162385.3-162386.37" + wire width 2 $0\xer_ca$10[1:0]$8853 + attribute \src "libresoc.v:162340.13-162340.31" + wire width 2 $0\xer_ca$10[1:0]$8953 + attribute \src "libresoc.v:162601.3-162619.6" + wire $0\xer_ca_ok$next[0:0]$8928 + attribute \src "libresoc.v:162387.3-162388.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:155518.3-155536.6" - wire $0\xer_so$next[0:0]$8876 - attribute \src "libresoc.v:155237.3-155238.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:155518.3-155536.6" - wire $0\xer_so_ok$next[0:0]$8877 - attribute \src "libresoc.v:155239.3-155240.35" + attribute \src "libresoc.v:162582.3-162600.6" + wire width 2 $0\xer_ov$9$next[1:0]$8922 + attribute \src "libresoc.v:162389.3-162390.35" + wire width 2 $0\xer_ov$9[1:0]$8856 + attribute \src "libresoc.v:162358.13-162358.30" + wire width 2 $0\xer_ov$9[1:0]$8956 + attribute \src "libresoc.v:162582.3-162600.6" + wire $0\xer_ov_ok$next[0:0]$8921 + attribute \src "libresoc.v:162391.3-162392.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:162563.3-162581.6" + wire $0\xer_so$8$next[0:0]$8916 + attribute \src "libresoc.v:162393.3-162394.35" + wire $0\xer_so$8[0:0]$8859 + attribute \src "libresoc.v:162374.7-162374.24" + wire $0\xer_so$8[0:0]$8959 + attribute \src "libresoc.v:162563.3-162581.6" + wire $0\xer_so_ok$next[0:0]$8915 + attribute \src "libresoc.v:162395.3-162396.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:155499.3-155517.6" - wire width 4 $1\cr_a$next[3:0]$8872 - attribute \src "libresoc.v:154161.13-154161.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:155499.3-155517.6" - wire $1\cr_a_ok$next[0:0]$8873 - attribute \src "libresoc.v:154170.7-154170.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:155426.3-155438.6" - wire width 2 $1\muxid$next[1:0]$8821 - attribute \src "libresoc.v:154723.13-154723.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:155480.3-155498.6" - wire width 64 $1\o$next[63:0]$8866 - attribute \src "libresoc.v:154738.14-154738.38" + attribute \src "libresoc.v:162544.3-162562.6" + wire width 64 $1\fast1$7$next[63:0]$8912 + attribute \src "libresoc.v:162544.3-162562.6" + wire $1\fast1_ok$next[0:0]$8911 + attribute \src "libresoc.v:161730.7-161730.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:162477.3-162489.6" + wire width 2 $1\muxid$1$next[1:0]$8886 + attribute \src "libresoc.v:162506.3-162524.6" + wire width 64 $1\o$next[63:0]$8899 + attribute \src "libresoc.v:161752.14-161752.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:155480.3-155498.6" - wire $1\o_ok$next[0:0]$8867 - attribute \src "libresoc.v:154745.7-154745.18" + attribute \src "libresoc.v:162506.3-162524.6" + wire $1\o_ok$next[0:0]$8900 + attribute \src "libresoc.v:161759.7-161759.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:155408.3-155425.6" - wire $1\r_busy$next[0:0]$8817 - attribute \src "libresoc.v:154759.7-154759.20" + attribute \src "libresoc.v:162459.3-162476.6" + wire $1\r_busy$next[0:0]$8882 + attribute \src "libresoc.v:161773.7-161773.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 12 $1\sr_op__fn_unit$next[11:0]$8840 - attribute \src "libresoc.v:154783.14-154783.38" - wire width 12 $1\sr_op__fn_unit[11:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$8841 - attribute \src "libresoc.v:154818.14-154818.58" - wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__imm_data__ok$next[0:0]$8842 - attribute \src "libresoc.v:154827.7-154827.33" - wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$8843 - attribute \src "libresoc.v:154840.13-154840.38" - wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__input_cr$next[0:0]$8844 - attribute \src "libresoc.v:154857.7-154857.29" - wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 32 $1\sr_op__insn$next[31:0]$8845 - attribute \src "libresoc.v:154866.14-154866.33" - wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$8846 - attribute \src "libresoc.v:154949.13-154949.37" - wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__invert_in$next[0:0]$8847 - attribute \src "libresoc.v:155106.7-155106.30" - wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__is_32bit$next[0:0]$8848 - attribute \src "libresoc.v:155115.7-155115.29" - wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__is_signed$next[0:0]$8849 - attribute \src "libresoc.v:155124.7-155124.30" - wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__oe__oe$next[0:0]$8850 - attribute \src "libresoc.v:155133.7-155133.27" - wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__oe__ok$next[0:0]$8851 - attribute \src "libresoc.v:155142.7-155142.27" - wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__output_carry$next[0:0]$8852 - attribute \src "libresoc.v:155151.7-155151.33" - wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__output_cr$next[0:0]$8853 - attribute \src "libresoc.v:155160.7-155160.30" - wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__rc__ok$next[0:0]$8854 - attribute \src "libresoc.v:155169.7-155169.27" - wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__rc__rc$next[0:0]$8855 - attribute \src "libresoc.v:155178.7-155178.27" - wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:155439.3-155479.6" - wire $1\sr_op__write_cr0$next[0:0]$8856 - attribute \src "libresoc.v:155187.7-155187.30" - wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:155389.3-155407.6" - wire width 2 $1\xer_ca$next[1:0]$8813 - attribute \src "libresoc.v:155196.13-155196.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:155389.3-155407.6" - wire $1\xer_ca_ok$next[0:0]$8812 - attribute \src "libresoc.v:155207.7-155207.23" + attribute \src "libresoc.v:162525.3-162543.6" + wire width 64 $1\spr1$6$next[63:0]$8905 + attribute \src "libresoc.v:162525.3-162543.6" + wire $1\spr1_ok$next[0:0]$8906 + attribute \src "libresoc.v:161789.7-161789.21" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:162490.3-162505.6" + wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8892 + attribute \src "libresoc.v:162490.3-162505.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8893 + attribute \src "libresoc.v:162490.3-162505.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8894 + attribute \src "libresoc.v:162490.3-162505.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8895 + attribute \src "libresoc.v:162601.3-162619.6" + wire width 2 $1\xer_ca$10$next[1:0]$8929 + attribute \src "libresoc.v:162601.3-162619.6" + wire $1\xer_ca_ok$next[0:0]$8930 + attribute \src "libresoc.v:162347.7-162347.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:155518.3-155536.6" - wire $1\xer_so$next[0:0]$8878 - attribute \src "libresoc.v:155216.7-155216.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:155518.3-155536.6" - wire $1\xer_so_ok$next[0:0]$8879 - attribute \src "libresoc.v:155225.7-155225.23" + attribute \src "libresoc.v:162582.3-162600.6" + wire width 2 $1\xer_ov$9$next[1:0]$8924 + attribute \src "libresoc.v:162582.3-162600.6" + wire $1\xer_ov_ok$next[0:0]$8923 + attribute \src "libresoc.v:162363.7-162363.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:162563.3-162581.6" + wire $1\xer_so$8$next[0:0]$8918 + attribute \src "libresoc.v:162563.3-162581.6" + wire $1\xer_so_ok$next[0:0]$8917 + attribute \src "libresoc.v:162379.7-162379.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:155499.3-155517.6" - wire $2\cr_a_ok$next[0:0]$8874 - attribute \src "libresoc.v:155480.3-155498.6" - wire $2\o_ok$next[0:0]$8868 - attribute \src "libresoc.v:155408.3-155425.6" - wire $2\r_busy$next[0:0]$8818 - attribute \src "libresoc.v:155439.3-155479.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$8857 - attribute \src "libresoc.v:155439.3-155479.6" - wire $2\sr_op__imm_data__ok$next[0:0]$8858 - attribute \src "libresoc.v:155439.3-155479.6" - wire $2\sr_op__oe__oe$next[0:0]$8859 - attribute \src "libresoc.v:155439.3-155479.6" - wire $2\sr_op__oe__ok$next[0:0]$8860 - attribute \src "libresoc.v:155439.3-155479.6" - wire $2\sr_op__rc__ok$next[0:0]$8861 - attribute \src "libresoc.v:155439.3-155479.6" - wire $2\sr_op__rc__rc$next[0:0]$8862 - attribute \src "libresoc.v:155389.3-155407.6" - wire $2\xer_ca_ok$next[0:0]$8814 - attribute \src "libresoc.v:155518.3-155536.6" - wire $2\xer_so_ok$next[0:0]$8880 - attribute \src "libresoc.v:155232.18-155232.118" - wire $and$libresoc.v:155232$8781_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "libresoc.v:162544.3-162562.6" + wire $2\fast1_ok$next[0:0]$8913 + attribute \src "libresoc.v:162506.3-162524.6" + wire $2\o_ok$next[0:0]$8901 + attribute \src "libresoc.v:162459.3-162476.6" + wire $2\r_busy$next[0:0]$8883 + attribute \src "libresoc.v:162525.3-162543.6" + wire $2\spr1_ok$next[0:0]$8907 + attribute \src "libresoc.v:162601.3-162619.6" + wire $2\xer_ca_ok$next[0:0]$8931 + attribute \src "libresoc.v:162582.3-162600.6" + wire $2\xer_ov_ok$next[0:0]$8925 + attribute \src "libresoc.v:162563.3-162581.6" + wire $2\xer_so_ok$next[0:0]$8919 + attribute \src "libresoc.v:162384.18-162384.118" + wire $and$libresoc.v:162384$8851_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 24 \cr_a + wire width 64 \fast1$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$87 + wire width 64 output 26 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$89 + wire width 64 \fast1$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next + wire output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 25 \cr_a_ok + wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$88 + wire \fast1_ok$next + attribute \src "libresoc.v:161712.7-161712.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 17 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 16 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 15 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$90 + wire width 64 output 22 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "libresoc.v:154152.7-154152.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc$41 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_sr_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__imm_data__ok$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__input_cr$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn$38 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 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attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 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\enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__invert_in$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_32bit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_signed$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_carry$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_cr$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__write_cr0$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$43 + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so + wire width 64 input 9 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$42 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$44 + wire width 64 input 10 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o + wire width 64 \spr1$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra + wire width 64 \spr_main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_fast1$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \spr_main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \spr_main_muxid$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb + wire width 64 \spr_main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rc + wire width 64 \spr_main_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_spr1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_spr1_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_main_spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_sr_op__fn_unit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__data$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__imm_data__ok$48 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__input_cr + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_main_spr_op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__input_cr$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn + wire width 32 \spr_main_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn$61 + wire width 32 \spr_main_spr_op__insn$14 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -321710,8 +336409,9 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type + wire width 7 \spr_main_spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -321786,197 +336486,92 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__invert_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_32bit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_signed$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__oe$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_carry$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_cr$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__rc$49 + wire width 7 \spr_main_spr_op__insn_type$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__write_cr0 + wire \spr_main_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__write_cr0$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \main_xer_ca + wire \spr_main_spr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_so$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 32 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o + wire width 2 \spr_main_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 22 \o + wire width 2 \spr_main_xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$85 + wire \spr_main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \spr_main_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next + wire width 2 \spr_main_xer_ov$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 23 \o_ok + wire \spr_main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \spr_main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$86 + wire \spr_main_xer_so$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 31 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 30 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$64 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 50 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 51 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 52 \rc + wire \spr_main_xer_so_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 34 \sr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_op__fn_unit$26 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 35 \sr_op__imm_data__data$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 19 \spr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 36 \sr_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 15 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 43 \sr_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 21 \sr_op__insn + wire width 32 input 7 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 49 \sr_op__insn$18 + wire width 32 \spr_op__insn$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$84 + wire width 32 output 20 \spr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$next + wire width 32 \spr_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -322051,8 +336646,9 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \sr_op__insn_type + wire width 7 input 5 \spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -322127,8 +336723,11 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 33 \sr_op__insn_type$2 + wire width 7 output 18 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -322203,1293 +336802,1171 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \sr_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 48 \sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \sr_op__output_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \sr_op__output_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 37 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$next + wire width 7 \spr_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \sr_op__write_cr0 + wire input 8 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \sr_op__write_cr0$10 + wire \spr_op__is_32bit$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$76 + wire output 21 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 28 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 54 \xer_ca$20 + wire \spr_op__is_32bit$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \xer_ca$63 + wire width 2 input 14 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$94 + wire width 2 output 32 \xer_ca$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$next + wire width 2 \xer_ca$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 29 \xer_ca_ok + wire width 2 \xer_ca$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$95 + wire output 33 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$96 + wire \xer_ca_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \xer_so + wire width 2 \xer_ov$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 53 \xer_so$19 + wire input 12 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$91 + wire \xer_so$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$next + wire output 28 \xer_so$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 27 \xer_so_ok + wire \xer_so$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$92 + wire output 29 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$93 + wire \xer_so_ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:155232$8781 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:162384$8851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$64 + connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:155232$8781_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:155287.15-155334.4" - cell \input$113 \input - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$21 - connect \ra \input_ra - connect \ra$19 \input_ra$39 - connect \rb \input_rb - connect \rb$20 \input_rb$40 - connect \rc \input_rc - connect \rc$21 \input_rc$41 - connect \sr_op__fn_unit \input_sr_op__fn_unit - connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 - connect \sr_op__imm_data__data \input_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 - connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 - connect \sr_op__input_carry \input_sr_op__input_carry - connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 - connect \sr_op__input_cr \input_sr_op__input_cr - connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 - connect \sr_op__insn \input_sr_op__insn - connect \sr_op__insn$18 \input_sr_op__insn$38 - connect \sr_op__insn_type \input_sr_op__insn_type - connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 - connect \sr_op__invert_in \input_sr_op__invert_in - connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 - connect \sr_op__is_32bit \input_sr_op__is_32bit - connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 - connect \sr_op__is_signed \input_sr_op__is_signed - connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 - connect \sr_op__oe__oe \input_sr_op__oe__oe - connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 - connect \sr_op__oe__ok \input_sr_op__oe__ok - connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 - connect \sr_op__output_carry \input_sr_op__output_carry - connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 - connect \sr_op__output_cr \input_sr_op__output_cr - connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 - connect \sr_op__rc__ok \input_sr_op__rc__ok - connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 - connect \sr_op__rc__rc \input_sr_op__rc__rc - connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 - connect \sr_op__write_cr0 \input_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 - connect \xer_ca \input_xer_ca - connect \xer_ca$23 \input_xer_ca$43 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$42 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:155335.14-155380.4" - cell \main$114 \main - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$44 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \rc \main_rc - connect \sr_op__fn_unit \main_sr_op__fn_unit - connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 - connect \sr_op__imm_data__data \main_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 - connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 - connect \sr_op__input_carry \main_sr_op__input_carry - connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 - connect \sr_op__input_cr \main_sr_op__input_cr - connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 - connect \sr_op__insn \main_sr_op__insn - connect \sr_op__insn$18 \main_sr_op__insn$61 - connect \sr_op__insn_type \main_sr_op__insn_type - connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 - connect \sr_op__invert_in \main_sr_op__invert_in - connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 - connect \sr_op__is_32bit \main_sr_op__is_32bit - connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 - connect \sr_op__is_signed \main_sr_op__is_signed - connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 - connect \sr_op__oe__oe \main_sr_op__oe__oe - connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 - connect \sr_op__oe__ok \main_sr_op__oe__ok - connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 - connect \sr_op__output_carry \main_sr_op__output_carry - connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 - connect \sr_op__output_cr \main_sr_op__output_cr - connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 - connect \sr_op__rc__ok \main_sr_op__rc__ok - connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 - connect \sr_op__rc__rc \main_sr_op__rc__rc - connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 - connect \sr_op__write_cr0 \main_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 - connect \xer_ca \main_xer_ca - connect \xer_so \main_xer_so - connect \xer_so$19 \main_xer_so$62 + connect \Y $and$libresoc.v:162384$8851_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:155381.11-155384.4" - cell \n$112 \n + attribute \src "libresoc.v:162421.10-162424.4" + cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:155385.11-155388.4" - cell \p$111 \p + attribute \src "libresoc.v:162425.10-162428.4" + cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:154152.7-154152.20" - process $proc$libresoc.v:154152$8881 + attribute \module_not_derived 1 + attribute \src "libresoc.v:162429.12-162458.4" + cell \spr_main \spr_main + connect \fast1 \spr_main_fast1 + connect \fast1$7 \spr_main_fast1$17 + connect \fast1_ok \spr_main_fast1_ok + connect \muxid \spr_main_muxid + connect \muxid$1 \spr_main_muxid$11 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \xer_ca \spr_main_xer_ca + connect \xer_ca$10 \spr_main_xer_ca$20 + connect \xer_ca_ok \spr_main_xer_ca_ok + connect \xer_ov \spr_main_xer_ov + connect \xer_ov$9 \spr_main_xer_ov$19 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_so \spr_main_xer_so + connect \xer_so$8 \spr_main_xer_so$18 + connect \xer_so_ok \spr_main_xer_so_ok + end + attribute \src "libresoc.v:161712.7-161712.20" + process $proc$libresoc.v:161712$8932 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154161.13-154161.24" - process $proc$libresoc.v:154161$8882 + attribute \src "libresoc.v:161725.14-161725.46" + process $proc$libresoc.v:161725$8933 assign { } { } - assign $1\cr_a[3:0] 4'0000 + assign $0\fast1$7[63:0]$8934 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \cr_a $1\cr_a[3:0] + update \fast1$7 $0\fast1$7[63:0]$8934 end - attribute \src "libresoc.v:154170.7-154170.21" - process $proc$libresoc.v:154170$8883 + attribute \src "libresoc.v:161730.7-161730.22" + process $proc$libresoc.v:161730$8935 assign { } { } - assign $1\cr_a_ok[0:0] 1'0 + assign $1\fast1_ok[0:0] 1'0 sync always sync init - update \cr_a_ok $1\cr_a_ok[0:0] + update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:154723.13-154723.25" - process $proc$libresoc.v:154723$8884 + attribute \src "libresoc.v:161739.13-161739.29" + process $proc$libresoc.v:161739$8936 assign { } { } - assign $1\muxid[1:0] 2'00 + assign $0\muxid$1[1:0]$8937 2'00 sync always sync init - update \muxid $1\muxid[1:0] + update \muxid$1 $0\muxid$1[1:0]$8937 end - attribute \src "libresoc.v:154738.14-154738.38" - process $proc$libresoc.v:154738$8885 + attribute \src "libresoc.v:161752.14-161752.38" + process $proc$libresoc.v:161752$8938 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:154745.7-154745.18" - process $proc$libresoc.v:154745$8886 + attribute \src "libresoc.v:161759.7-161759.18" + process $proc$libresoc.v:161759$8939 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:154759.7-154759.20" - process $proc$libresoc.v:154759$8887 + attribute \src "libresoc.v:161773.7-161773.20" + process $proc$libresoc.v:161773$8940 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:154783.14-154783.38" - process $proc$libresoc.v:154783$8888 - assign { } { } - assign $1\sr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \sr_op__fn_unit $1\sr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:154818.14-154818.58" - process $proc$libresoc.v:154818$8889 - assign { } { } - assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:154827.7-154827.33" - process $proc$libresoc.v:154827$8890 - assign { } { } - assign $1\sr_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:154840.13-154840.38" - process $proc$libresoc.v:154840$8891 - assign { } { } - assign $1\sr_op__input_carry[1:0] 2'00 - sync always - sync init - update \sr_op__input_carry $1\sr_op__input_carry[1:0] - end - attribute \src "libresoc.v:154857.7-154857.29" - process $proc$libresoc.v:154857$8892 - assign { } { } - assign $1\sr_op__input_cr[0:0] 1'0 - sync always - sync init - update \sr_op__input_cr $1\sr_op__input_cr[0:0] - end - attribute \src "libresoc.v:154866.14-154866.33" - process $proc$libresoc.v:154866$8893 - assign { } { } - assign $1\sr_op__insn[31:0] 0 - sync always - sync init - update \sr_op__insn $1\sr_op__insn[31:0] - end - attribute \src "libresoc.v:154949.13-154949.37" - process $proc$libresoc.v:154949$8894 - assign { } { } - assign $1\sr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \sr_op__insn_type $1\sr_op__insn_type[6:0] - end - attribute \src "libresoc.v:155106.7-155106.30" - process $proc$libresoc.v:155106$8895 - assign { } { } - assign $1\sr_op__invert_in[0:0] 1'0 - sync always - sync init - update \sr_op__invert_in $1\sr_op__invert_in[0:0] - end - attribute \src "libresoc.v:155115.7-155115.29" - process $proc$libresoc.v:155115$8896 + attribute \src "libresoc.v:161784.14-161784.45" + process $proc$libresoc.v:161784$8941 assign { } { } - assign $1\sr_op__is_32bit[0:0] 1'0 - sync always - sync init - update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:155124.7-155124.30" - process $proc$libresoc.v:155124$8897 - assign { } { } - assign $1\sr_op__is_signed[0:0] 1'0 + assign $0\spr1$6[63:0]$8942 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__is_signed $1\sr_op__is_signed[0:0] + update \spr1$6 $0\spr1$6[63:0]$8942 end - attribute \src "libresoc.v:155133.7-155133.27" - process $proc$libresoc.v:155133$8898 + attribute \src "libresoc.v:161789.7-161789.21" + process $proc$libresoc.v:161789$8943 assign { } { } - assign $1\sr_op__oe__oe[0:0] 1'0 + assign $1\spr1_ok[0:0] 1'0 sync always sync init - update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:155142.7-155142.27" - process $proc$libresoc.v:155142$8899 + attribute \src "libresoc.v:162081.14-162081.44" + process $proc$libresoc.v:162081$8944 assign { } { } - assign $1\sr_op__oe__ok[0:0] 1'0 + assign $0\spr_op__fn_unit$3[13:0]$8945 14'00000000000000 sync always sync init - update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8945 end - attribute \src "libresoc.v:155151.7-155151.33" - process $proc$libresoc.v:155151$8900 + attribute \src "libresoc.v:162090.14-162090.38" + process $proc$libresoc.v:162090$8946 assign { } { } - assign $1\sr_op__output_carry[0:0] 1'0 + assign $0\spr_op__insn$4[31:0]$8947 0 sync always sync init - update \sr_op__output_carry $1\sr_op__output_carry[0:0] + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8947 end - attribute \src "libresoc.v:155160.7-155160.30" - process $proc$libresoc.v:155160$8901 + attribute \src "libresoc.v:162247.13-162247.42" + process $proc$libresoc.v:162247$8948 assign { } { } - assign $1\sr_op__output_cr[0:0] 1'0 + assign $0\spr_op__insn_type$2[6:0]$8949 7'0000000 sync always sync init - update \sr_op__output_cr $1\sr_op__output_cr[0:0] + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8949 end - attribute \src "libresoc.v:155169.7-155169.27" - process $proc$libresoc.v:155169$8902 + attribute \src "libresoc.v:162333.7-162333.34" + process $proc$libresoc.v:162333$8950 assign { } { } - assign $1\sr_op__rc__ok[0:0] 1'0 + assign $0\spr_op__is_32bit$5[0:0]$8951 1'0 sync always sync init - update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8951 end - attribute \src "libresoc.v:155178.7-155178.27" - process $proc$libresoc.v:155178$8903 + attribute \src "libresoc.v:162340.13-162340.31" + process $proc$libresoc.v:162340$8952 assign { } { } - assign $1\sr_op__rc__rc[0:0] 1'0 + assign $0\xer_ca$10[1:0]$8953 2'00 sync always sync init - update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] + update \xer_ca$10 $0\xer_ca$10[1:0]$8953 end - attribute \src "libresoc.v:155187.7-155187.30" - process $proc$libresoc.v:155187$8904 + attribute \src "libresoc.v:162347.7-162347.23" + process $proc$libresoc.v:162347$8954 assign { } { } - assign $1\sr_op__write_cr0[0:0] 1'0 + assign $1\xer_ca_ok[0:0] 1'0 sync always sync init - update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] + update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:155196.13-155196.26" - process $proc$libresoc.v:155196$8905 + attribute \src "libresoc.v:162358.13-162358.30" + process $proc$libresoc.v:162358$8955 assign { } { } - assign $1\xer_ca[1:0] 2'00 + assign $0\xer_ov$9[1:0]$8956 2'00 sync always sync init - update \xer_ca $1\xer_ca[1:0] + update \xer_ov$9 $0\xer_ov$9[1:0]$8956 end - attribute \src "libresoc.v:155207.7-155207.23" - process $proc$libresoc.v:155207$8906 + attribute \src "libresoc.v:162363.7-162363.23" + process $proc$libresoc.v:162363$8957 assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 + assign $1\xer_ov_ok[0:0] 1'0 sync always sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] + update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:155216.7-155216.20" - process $proc$libresoc.v:155216$8907 + attribute \src "libresoc.v:162374.7-162374.24" + process $proc$libresoc.v:162374$8958 assign { } { } - assign $1\xer_so[0:0] 1'0 + assign $0\xer_so$8[0:0]$8959 1'0 sync always sync init - update \xer_so $1\xer_so[0:0] + update \xer_so$8 $0\xer_so$8[0:0]$8959 end - attribute \src "libresoc.v:155225.7-155225.23" - process $proc$libresoc.v:155225$8908 + attribute \src "libresoc.v:162379.7-162379.23" + process $proc$libresoc.v:162379$8960 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:155233.3-155234.29" - process $proc$libresoc.v:155233$8782 + attribute \src "libresoc.v:162385.3-162386.37" + process $proc$libresoc.v:162385$8852 assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next + assign $0\xer_ca$10[1:0]$8853 \xer_ca$10$next sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] + update \xer_ca$10 $0\xer_ca$10[1:0]$8853 end - attribute \src "libresoc.v:155235.3-155236.35" - process $proc$libresoc.v:155235$8783 + attribute \src "libresoc.v:162387.3-162388.35" + process $proc$libresoc.v:162387$8854 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:155237.3-155238.29" - process $proc$libresoc.v:155237$8784 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:155239.3-155240.35" - process $proc$libresoc.v:155239$8785 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:155241.3-155242.25" - process $proc$libresoc.v:155241$8786 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:155243.3-155244.31" - process $proc$libresoc.v:155243$8787 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:155245.3-155246.19" - process $proc$libresoc.v:155245$8788 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:155247.3-155248.25" - process $proc$libresoc.v:155247$8789 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:155249.3-155250.49" - process $proc$libresoc.v:155249$8790 - assign { } { } - assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next - sync posedge \coresync_clk - update \sr_op__insn_type $0\sr_op__insn_type[6:0] - end - attribute \src "libresoc.v:155251.3-155252.45" - process $proc$libresoc.v:155251$8791 - assign { } { } - assign $0\sr_op__fn_unit[11:0] \sr_op__fn_unit$next - sync posedge \coresync_clk - update \sr_op__fn_unit $0\sr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:155253.3-155254.59" - process $proc$libresoc.v:155253$8792 - assign { } { } - assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next - sync posedge \coresync_clk - update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] + update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:155255.3-155256.55" - process $proc$libresoc.v:155255$8793 + attribute \src "libresoc.v:162389.3-162390.35" + process $proc$libresoc.v:162389$8855 assign { } { } - assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next + assign $0\xer_ov$9[1:0]$8856 \xer_ov$9$next sync posedge \coresync_clk - update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] + update \xer_ov$9 $0\xer_ov$9[1:0]$8856 end - attribute \src "libresoc.v:155257.3-155258.43" - process $proc$libresoc.v:155257$8794 + attribute \src "libresoc.v:162391.3-162392.35" + process $proc$libresoc.v:162391$8857 assign { } { } - assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk - update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] + update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:155259.3-155260.43" - process $proc$libresoc.v:155259$8795 + attribute \src "libresoc.v:162393.3-162394.35" + process $proc$libresoc.v:162393$8858 assign { } { } - assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next + assign $0\xer_so$8[0:0]$8859 \xer_so$8$next sync posedge \coresync_clk - update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] + update \xer_so$8 $0\xer_so$8[0:0]$8859 end - attribute \src "libresoc.v:155261.3-155262.43" - process $proc$libresoc.v:155261$8796 + attribute \src "libresoc.v:162395.3-162396.35" + process $proc$libresoc.v:162395$8860 assign { } { } - assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next + assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk - update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:155263.3-155264.43" - process $proc$libresoc.v:155263$8797 + attribute \src "libresoc.v:162397.3-162398.33" + process $proc$libresoc.v:162397$8861 assign { } { } - assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next + assign $0\fast1$7[63:0]$8862 \fast1$7$next sync posedge \coresync_clk - update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] + update \fast1$7 $0\fast1$7[63:0]$8862 end - attribute \src "libresoc.v:155265.3-155266.49" - process $proc$libresoc.v:155265$8798 + attribute \src "libresoc.v:162399.3-162400.33" + process $proc$libresoc.v:162399$8863 assign { } { } - assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:155267.3-155268.49" - process $proc$libresoc.v:155267$8799 + attribute \src "libresoc.v:162401.3-162402.31" + process $proc$libresoc.v:162401$8864 assign { } { } - assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next + assign $0\spr1$6[63:0]$8865 \spr1$6$next sync posedge \coresync_clk - update \sr_op__invert_in $0\sr_op__invert_in[0:0] + update \spr1$6 $0\spr1$6[63:0]$8865 end - attribute \src "libresoc.v:155269.3-155270.53" - process $proc$libresoc.v:155269$8800 + attribute \src "libresoc.v:162403.3-162404.31" + process $proc$libresoc.v:162403$8866 assign { } { } - assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next + assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk - update \sr_op__input_carry $0\sr_op__input_carry[1:0] + update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:155271.3-155272.55" - process $proc$libresoc.v:155271$8801 + attribute \src "libresoc.v:162405.3-162406.19" + process $proc$libresoc.v:162405$8867 assign { } { } - assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \sr_op__output_carry $0\sr_op__output_carry[0:0] + update \o $0\o[63:0] end - attribute \src "libresoc.v:155273.3-155274.47" - process $proc$libresoc.v:155273$8802 + attribute \src "libresoc.v:162407.3-162408.25" + process $proc$libresoc.v:162407$8868 assign { } { } - assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \sr_op__input_cr $0\sr_op__input_cr[0:0] + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:155275.3-155276.49" - process $proc$libresoc.v:155275$8803 + attribute \src "libresoc.v:162409.3-162410.57" + process $proc$libresoc.v:162409$8869 assign { } { } - assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next + assign $0\spr_op__insn_type$2[6:0]$8870 \spr_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__output_cr $0\sr_op__output_cr[0:0] + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8870 end - attribute \src "libresoc.v:155277.3-155278.47" - process $proc$libresoc.v:155277$8804 + attribute \src "libresoc.v:162411.3-162412.53" + process $proc$libresoc.v:162411$8871 assign { } { } - assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next + assign $0\spr_op__fn_unit$3[13:0]$8872 \spr_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8872 end - attribute \src "libresoc.v:155279.3-155280.49" - process $proc$libresoc.v:155279$8805 + attribute \src "libresoc.v:162413.3-162414.47" + process $proc$libresoc.v:162413$8873 assign { } { } - assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next + assign $0\spr_op__insn$4[31:0]$8874 \spr_op__insn$4$next sync posedge \coresync_clk - update \sr_op__is_signed $0\sr_op__is_signed[0:0] + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8874 end - attribute \src "libresoc.v:155281.3-155282.39" - process $proc$libresoc.v:155281$8806 + attribute \src "libresoc.v:162415.3-162416.55" + process $proc$libresoc.v:162415$8875 assign { } { } - assign $0\sr_op__insn[31:0] \sr_op__insn$next + assign $0\spr_op__is_32bit$5[0:0]$8876 \spr_op__is_32bit$5$next sync posedge \coresync_clk - update \sr_op__insn $0\sr_op__insn[31:0] + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8876 end - attribute \src "libresoc.v:155283.3-155284.27" - process $proc$libresoc.v:155283$8807 + attribute \src "libresoc.v:162417.3-162418.33" + process $proc$libresoc.v:162417$8877 assign { } { } - assign $0\muxid[1:0] \muxid$next + assign $0\muxid$1[1:0]$8878 \muxid$1$next sync posedge \coresync_clk - update \muxid $0\muxid[1:0] + update \muxid$1 $0\muxid$1[1:0]$8878 end - attribute \src "libresoc.v:155285.3-155286.29" - process $proc$libresoc.v:155285$8808 + attribute \src "libresoc.v:162419.3-162420.29" + process $proc$libresoc.v:162419$8879 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:155389.3-155407.6" - process $proc$libresoc.v:155389$8809 - assign { } { } + attribute \src "libresoc.v:162459.3-162476.6" + process $proc$libresoc.v:162459$8880 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\xer_ca$next[1:0]$8811 $1\xer_ca$next[1:0]$8813 - assign $0\xer_ca_ok$next[0:0]$8810 $2\xer_ca_ok$next[0:0]$8814 - attribute \src "libresoc.v:155390.5-155390.29" + assign $0\r_busy$next[0:0]$8881 $2\r_busy$next[0:0]$8883 + attribute \src "libresoc.v:162460.5-162460.29" switch \initial - attribute \src "libresoc.v:155390.9-155390.17" + attribute \src "libresoc.v:162460.9-162460.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8812 $1\xer_ca$next[1:0]$8813 } { \xer_ca_ok$95 \xer_ca$94 } + assign $1\r_busy$next[0:0]$8882 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8812 $1\xer_ca$next[1:0]$8813 } { \xer_ca_ok$95 \xer_ca$94 } + assign $1\r_busy$next[0:0]$8882 1'0 case - assign $1\xer_ca_ok$next[0:0]$8812 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8813 \xer_ca + assign $1\r_busy$next[0:0]$8882 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8814 1'0 + assign $2\r_busy$next[0:0]$8883 1'0 case - assign $2\xer_ca_ok$next[0:0]$8814 $1\xer_ca_ok$next[0:0]$8812 + assign $2\r_busy$next[0:0]$8883 $1\r_busy$next[0:0]$8882 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8810 - update \xer_ca$next $0\xer_ca$next[1:0]$8811 + update \r_busy$next $0\r_busy$next[0:0]$8881 end - attribute \src "libresoc.v:155408.3-155425.6" - process $proc$libresoc.v:155408$8815 - assign { } { } + attribute \src "libresoc.v:162477.3-162489.6" + process $proc$libresoc.v:162477$8884 assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8816 $2\r_busy$next[0:0]$8818 - attribute \src "libresoc.v:155409.5-155409.29" + assign $0\muxid$1$next[1:0]$8885 $1\muxid$1$next[1:0]$8886 + attribute \src "libresoc.v:162478.5-162478.29" switch \initial - attribute \src "libresoc.v:155409.9-155409.17" + attribute \src "libresoc.v:162478.9-162478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8817 1'1 + assign $1\muxid$1$next[1:0]$8886 \muxid$24 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8817 1'0 + assign $1\muxid$1$next[1:0]$8886 \muxid$24 case - assign $1\r_busy$next[0:0]$8817 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$8818 1'0 - case - assign $2\r_busy$next[0:0]$8818 $1\r_busy$next[0:0]$8817 + assign $1\muxid$1$next[1:0]$8886 \muxid$1 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8816 + update \muxid$1$next $0\muxid$1$next[1:0]$8885 end - attribute \src "libresoc.v:155426.3-155438.6" - process $proc$libresoc.v:155426$8819 + attribute \src "libresoc.v:162490.3-162505.6" + process $proc$libresoc.v:162490$8887 + assign { } { } assign { } { } assign { } { } - assign $0\muxid$next[1:0]$8820 $1\muxid$next[1:0]$8821 - attribute \src "libresoc.v:155427.5-155427.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_op__fn_unit$3$next[13:0]$8888 $1\spr_op__fn_unit$3$next[13:0]$8892 + assign $0\spr_op__insn$4$next[31:0]$8889 $1\spr_op__insn$4$next[31:0]$8893 + assign $0\spr_op__insn_type$2$next[6:0]$8890 $1\spr_op__insn_type$2$next[6:0]$8894 + assign $0\spr_op__is_32bit$5$next[0:0]$8891 $1\spr_op__is_32bit$5$next[0:0]$8895 + attribute \src "libresoc.v:162491.5-162491.29" switch \initial - attribute \src "libresoc.v:155427.9-155427.17" + attribute \src "libresoc.v:162491.9-162491.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$8821 \muxid$67 + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8895 $1\spr_op__insn$4$next[31:0]$8893 $1\spr_op__fn_unit$3$next[13:0]$8892 $1\spr_op__insn_type$2$next[6:0]$8894 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$8821 \muxid$67 + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8895 $1\spr_op__insn$4$next[31:0]$8893 $1\spr_op__fn_unit$3$next[13:0]$8892 $1\spr_op__insn_type$2$next[6:0]$8894 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } case - assign $1\muxid$next[1:0]$8821 \muxid + assign $1\spr_op__fn_unit$3$next[13:0]$8892 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8893 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8894 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8895 \spr_op__is_32bit$5 end sync always - update \muxid$next $0\muxid$next[1:0]$8820 + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8888 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8889 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8890 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8891 end - attribute \src "libresoc.v:155439.3-155479.6" - process $proc$libresoc.v:155439$8822 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:162506.3-162524.6" + process $proc$libresoc.v:162506$8896 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\o$next[63:0]$8897 $1\o$next[63:0]$8899 assign { } { } - assign $0\sr_op__fn_unit$next[11:0]$8823 $1\sr_op__fn_unit$next[11:0]$8840 - assign { } { } - assign { } { } - assign $0\sr_op__input_carry$next[1:0]$8826 $1\sr_op__input_carry$next[1:0]$8843 - assign $0\sr_op__input_cr$next[0:0]$8827 $1\sr_op__input_cr$next[0:0]$8844 - assign $0\sr_op__insn$next[31:0]$8828 $1\sr_op__insn$next[31:0]$8845 - assign $0\sr_op__insn_type$next[6:0]$8829 $1\sr_op__insn_type$next[6:0]$8846 - assign $0\sr_op__invert_in$next[0:0]$8830 $1\sr_op__invert_in$next[0:0]$8847 - assign $0\sr_op__is_32bit$next[0:0]$8831 $1\sr_op__is_32bit$next[0:0]$8848 - assign $0\sr_op__is_signed$next[0:0]$8832 $1\sr_op__is_signed$next[0:0]$8849 - assign { } { } - assign { } { } - assign $0\sr_op__output_carry$next[0:0]$8835 $1\sr_op__output_carry$next[0:0]$8852 - assign $0\sr_op__output_cr$next[0:0]$8836 $1\sr_op__output_cr$next[0:0]$8853 - assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$8839 $1\sr_op__write_cr0$next[0:0]$8856 - assign $0\sr_op__imm_data__data$next[63:0]$8824 $2\sr_op__imm_data__data$next[63:0]$8857 - assign $0\sr_op__imm_data__ok$next[0:0]$8825 $2\sr_op__imm_data__ok$next[0:0]$8858 - assign $0\sr_op__oe__oe$next[0:0]$8833 $2\sr_op__oe__oe$next[0:0]$8859 - assign $0\sr_op__oe__ok$next[0:0]$8834 $2\sr_op__oe__ok$next[0:0]$8860 - assign $0\sr_op__rc__ok$next[0:0]$8837 $2\sr_op__rc__ok$next[0:0]$8861 - assign $0\sr_op__rc__rc$next[0:0]$8838 $2\sr_op__rc__rc$next[0:0]$8862 - attribute \src "libresoc.v:155440.5-155440.29" + assign $0\o_ok$next[0:0]$8898 $2\o_ok$next[0:0]$8901 + attribute \src "libresoc.v:162507.5-162507.29" switch \initial - attribute \src "libresoc.v:155440.9-155440.17" + attribute \src "libresoc.v:162507.9-162507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$next[31:0]$8845 $1\sr_op__is_signed$next[0:0]$8849 $1\sr_op__is_32bit$next[0:0]$8848 $1\sr_op__output_cr$next[0:0]$8853 $1\sr_op__input_cr$next[0:0]$8844 $1\sr_op__output_carry$next[0:0]$8852 $1\sr_op__input_carry$next[1:0]$8843 $1\sr_op__invert_in$next[0:0]$8847 $1\sr_op__write_cr0$next[0:0]$8856 $1\sr_op__oe__ok$next[0:0]$8851 $1\sr_op__oe__oe$next[0:0]$8850 $1\sr_op__rc__ok$next[0:0]$8854 $1\sr_op__rc__rc$next[0:0]$8855 $1\sr_op__imm_data__ok$next[0:0]$8842 $1\sr_op__imm_data__data$next[63:0]$8841 $1\sr_op__fn_unit$next[11:0]$8840 $1\sr_op__insn_type$next[6:0]$8846 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\o_ok$next[0:0]$8900 $1\o$next[63:0]$8899 } { \o_ok$30 \o$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } + assign { $1\o_ok$next[0:0]$8900 $1\o$next[63:0]$8899 } { \o_ok$30 \o$29 } + case + assign $1\o$next[63:0]$8899 \o + assign $1\o_ok$next[0:0]$8900 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $2\o_ok$next[0:0]$8901 1'0 + case + assign $2\o_ok$next[0:0]$8901 $1\o_ok$next[0:0]$8900 + end + sync always + update \o$next $0\o$next[63:0]$8897 + update \o_ok$next $0\o_ok$next[0:0]$8898 + end + attribute \src "libresoc.v:162525.3-162543.6" + process $proc$libresoc.v:162525$8902 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr1$6$next[63:0]$8903 $1\spr1$6$next[63:0]$8905 + assign { } { } + assign $0\spr1_ok$next[0:0]$8904 $2\spr1_ok$next[0:0]$8907 + attribute \src "libresoc.v:162526.5-162526.29" + switch \initial + attribute \src "libresoc.v:162526.9-162526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } assign { } { } + assign { $1\spr1_ok$next[0:0]$8906 $1\spr1$6$next[63:0]$8905 } { \spr1_ok$32 \spr1$31 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$next[31:0]$8845 $1\sr_op__is_signed$next[0:0]$8849 $1\sr_op__is_32bit$next[0:0]$8848 $1\sr_op__output_cr$next[0:0]$8853 $1\sr_op__input_cr$next[0:0]$8844 $1\sr_op__output_carry$next[0:0]$8852 $1\sr_op__input_carry$next[1:0]$8843 $1\sr_op__invert_in$next[0:0]$8847 $1\sr_op__write_cr0$next[0:0]$8856 $1\sr_op__oe__ok$next[0:0]$8851 $1\sr_op__oe__oe$next[0:0]$8850 $1\sr_op__rc__ok$next[0:0]$8854 $1\sr_op__rc__rc$next[0:0]$8855 $1\sr_op__imm_data__ok$next[0:0]$8842 $1\sr_op__imm_data__data$next[63:0]$8841 $1\sr_op__fn_unit$next[11:0]$8840 $1\sr_op__insn_type$next[6:0]$8846 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\spr1_ok$next[0:0]$8906 $1\spr1$6$next[63:0]$8905 } { \spr1_ok$32 \spr1$31 } case - assign $1\sr_op__fn_unit$next[11:0]$8840 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$8841 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$8842 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$8843 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$8844 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$8845 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$8846 \sr_op__insn_type - assign $1\sr_op__invert_in$next[0:0]$8847 \sr_op__invert_in - assign $1\sr_op__is_32bit$next[0:0]$8848 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$8849 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$8850 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$8851 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$8852 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$8853 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$8854 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$8855 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$8856 \sr_op__write_cr0 + assign $1\spr1$6$next[63:0]$8905 \spr1$6 + assign $1\spr1_ok$next[0:0]$8906 \spr1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $2\spr1_ok$next[0:0]$8907 1'0 + case + assign $2\spr1_ok$next[0:0]$8907 $1\spr1_ok$next[0:0]$8906 + end + sync always + update \spr1$6$next $0\spr1$6$next[63:0]$8903 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8904 + end + attribute \src "libresoc.v:162544.3-162562.6" + process $proc$libresoc.v:162544$8908 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$7$next[63:0]$8910 $1\fast1$7$next[63:0]$8912 + assign $0\fast1_ok$next[0:0]$8909 $2\fast1_ok$next[0:0]$8913 + attribute \src "libresoc.v:162545.5-162545.29" + switch \initial + attribute \src "libresoc.v:162545.9-162545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } assign { } { } + assign { $1\fast1_ok$next[0:0]$8911 $1\fast1$7$next[63:0]$8912 } { \fast1_ok$34 \fast1$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } assign { } { } + assign { $1\fast1_ok$next[0:0]$8911 $1\fast1$7$next[63:0]$8912 } { \fast1_ok$34 \fast1$33 } + case + assign $1\fast1_ok$next[0:0]$8911 \fast1_ok + assign $1\fast1$7$next[63:0]$8912 \fast1$7 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$8857 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$8858 1'0 - assign $2\sr_op__rc__rc$next[0:0]$8862 1'0 - assign $2\sr_op__rc__ok$next[0:0]$8861 1'0 - assign $2\sr_op__oe__oe$next[0:0]$8859 1'0 - assign $2\sr_op__oe__ok$next[0:0]$8860 1'0 + assign $2\fast1_ok$next[0:0]$8913 1'0 case - assign $2\sr_op__imm_data__data$next[63:0]$8857 $1\sr_op__imm_data__data$next[63:0]$8841 - assign $2\sr_op__imm_data__ok$next[0:0]$8858 $1\sr_op__imm_data__ok$next[0:0]$8842 - assign $2\sr_op__oe__oe$next[0:0]$8859 $1\sr_op__oe__oe$next[0:0]$8850 - assign $2\sr_op__oe__ok$next[0:0]$8860 $1\sr_op__oe__ok$next[0:0]$8851 - assign $2\sr_op__rc__ok$next[0:0]$8861 $1\sr_op__rc__ok$next[0:0]$8854 - assign $2\sr_op__rc__rc$next[0:0]$8862 $1\sr_op__rc__rc$next[0:0]$8855 + assign $2\fast1_ok$next[0:0]$8913 $1\fast1_ok$next[0:0]$8911 end sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[11:0]$8823 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$8824 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$8825 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$8826 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$8827 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$8828 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$8829 - update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$8830 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$8831 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$8832 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$8833 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$8834 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$8835 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$8836 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$8837 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$8838 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$8839 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8909 + update \fast1$7$next $0\fast1$7$next[63:0]$8910 end - attribute \src "libresoc.v:155480.3-155498.6" - process $proc$libresoc.v:155480$8863 + attribute \src "libresoc.v:162563.3-162581.6" + process $proc$libresoc.v:162563$8914 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8864 $1\o$next[63:0]$8866 assign { } { } - assign $0\o_ok$next[0:0]$8865 $2\o_ok$next[0:0]$8868 - attribute \src "libresoc.v:155481.5-155481.29" + assign $0\xer_so$8$next[0:0]$8916 $1\xer_so$8$next[0:0]$8918 + assign $0\xer_so_ok$next[0:0]$8915 $2\xer_so_ok$next[0:0]$8919 + attribute \src "libresoc.v:162564.5-162564.29" switch \initial - attribute \src "libresoc.v:155481.9-155481.17" + attribute \src "libresoc.v:162564.9-162564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8867 $1\o$next[63:0]$8866 } { \o_ok$86 \o$85 } + assign { $1\xer_so_ok$next[0:0]$8917 $1\xer_so$8$next[0:0]$8918 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8867 $1\o$next[63:0]$8866 } { \o_ok$86 \o$85 } + assign { $1\xer_so_ok$next[0:0]$8917 $1\xer_so$8$next[0:0]$8918 } { \xer_so_ok$36 \xer_so$35 } case - assign $1\o$next[63:0]$8866 \o - assign $1\o_ok$next[0:0]$8867 \o_ok + assign $1\xer_so_ok$next[0:0]$8917 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8918 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8868 1'0 + assign $2\xer_so_ok$next[0:0]$8919 1'0 case - assign $2\o_ok$next[0:0]$8868 $1\o_ok$next[0:0]$8867 + assign $2\xer_so_ok$next[0:0]$8919 $1\xer_so_ok$next[0:0]$8917 end sync always - update \o$next $0\o$next[63:0]$8864 - update \o_ok$next $0\o_ok$next[0:0]$8865 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8915 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8916 end - attribute \src "libresoc.v:155499.3-155517.6" - process $proc$libresoc.v:155499$8869 + attribute \src "libresoc.v:162582.3-162600.6" + process $proc$libresoc.v:162582$8920 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8870 $1\cr_a$next[3:0]$8872 assign { } { } - assign $0\cr_a_ok$next[0:0]$8871 $2\cr_a_ok$next[0:0]$8874 - attribute \src "libresoc.v:155500.5-155500.29" + assign $0\xer_ov$9$next[1:0]$8922 $1\xer_ov$9$next[1:0]$8924 + assign $0\xer_ov_ok$next[0:0]$8921 $2\xer_ov_ok$next[0:0]$8925 + attribute \src "libresoc.v:162583.5-162583.29" switch \initial - attribute \src "libresoc.v:155500.9-155500.17" + attribute \src "libresoc.v:162583.9-162583.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8873 $1\cr_a$next[3:0]$8872 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\xer_ov_ok$next[0:0]$8923 $1\xer_ov$9$next[1:0]$8924 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8873 $1\cr_a$next[3:0]$8872 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\xer_ov_ok$next[0:0]$8923 $1\xer_ov$9$next[1:0]$8924 } { \xer_ov_ok$38 \xer_ov$37 } case - assign $1\cr_a$next[3:0]$8872 \cr_a - assign $1\cr_a_ok$next[0:0]$8873 \cr_a_ok + assign $1\xer_ov_ok$next[0:0]$8923 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8924 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8874 1'0 + assign $2\xer_ov_ok$next[0:0]$8925 1'0 case - assign $2\cr_a_ok$next[0:0]$8874 $1\cr_a_ok$next[0:0]$8873 + assign $2\xer_ov_ok$next[0:0]$8925 $1\xer_ov_ok$next[0:0]$8923 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8870 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8871 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8921 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8922 end - attribute \src "libresoc.v:155518.3-155536.6" - process $proc$libresoc.v:155518$8875 + attribute \src "libresoc.v:162601.3-162619.6" + process $proc$libresoc.v:162601$8926 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8876 $1\xer_so$next[0:0]$8878 + assign $0\xer_ca$10$next[1:0]$8927 $1\xer_ca$10$next[1:0]$8929 assign { } { } - assign $0\xer_so_ok$next[0:0]$8877 $2\xer_so_ok$next[0:0]$8880 - attribute \src "libresoc.v:155519.5-155519.29" + assign $0\xer_ca_ok$next[0:0]$8928 $2\xer_ca_ok$next[0:0]$8931 + attribute \src "libresoc.v:162602.5-162602.29" switch \initial - attribute \src "libresoc.v:155519.9-155519.17" + attribute \src "libresoc.v:162602.9-162602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8879 $1\xer_so$next[0:0]$8878 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_ca_ok$next[0:0]$8930 $1\xer_ca$10$next[1:0]$8929 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8879 $1\xer_so$next[0:0]$8878 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_ca_ok$next[0:0]$8930 $1\xer_ca$10$next[1:0]$8929 } { \xer_ca_ok$40 \xer_ca$39 } case - assign $1\xer_so$next[0:0]$8878 \xer_so - assign $1\xer_so_ok$next[0:0]$8879 \xer_so_ok + assign $1\xer_ca$10$next[1:0]$8929 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8930 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8880 1'0 + assign $2\xer_ca_ok$next[0:0]$8931 1'0 case - assign $2\xer_so_ok$next[0:0]$8880 $1\xer_so_ok$next[0:0]$8879 + assign $2\xer_ca_ok$next[0:0]$8931 $1\xer_ca_ok$next[0:0]$8930 end sync always - update \xer_so$next $0\xer_so$next[0:0]$8876 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8877 + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8927 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8928 end - connect \$65 $and$libresoc.v:155232$8781_Y - connect \cr_a$89 4'0000 - connect \cr_a_ok$90 1'0 - connect \xer_so_ok$93 1'0 - connect \xer_ca_ok$96 1'0 + connect \$22 $and$libresoc.v:162384$8851_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } - connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } - connect { \cr_a_ok$88 \cr_a$87 } 5'00000 - connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } - connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } - connect \muxid$67 \main_muxid$44 - connect \p_valid_i_p_ready_o \$65 + connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } + connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } + connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } + connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } + connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } + connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + connect \muxid$24 \spr_main_muxid$11 + connect \p_valid_i_p_ready_o \$22 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$64 \p_valid_i - connect \xer_ca$63 \input_xer_ca$43 - connect \main_xer_so \input_xer_so$42 - connect \main_rc \input_rc$41 - connect \main_rb \input_rb$40 - connect \main_ra \input_ra$39 - connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } - connect \main_muxid \input_muxid$21 - connect \input_xer_ca \xer_ca$20 - connect \input_xer_so \xer_so$19 - connect \input_rc \rc - connect \input_rb \rb - connect \input_ra \ra - connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } - connect \input_muxid \muxid$1 + connect \p_valid_i$21 \p_valid_i + connect \spr_main_xer_ca \xer_ca + connect \spr_main_xer_ov \xer_ov + connect \spr_main_xer_so \xer_so + connect \spr_main_fast1 \fast1 + connect \spr_main_spr1 \spr1 + connect \spr_main_ra \ra + connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:155570.1-156403.10" +attribute \src "libresoc.v:162645.1-164137.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" -module \pipe1$32 - attribute \src "libresoc.v:156360.3-156372.6" - wire width 64 $0\fast1$next[63:0]$8958 - attribute \src "libresoc.v:156234.3-156235.27" - wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:156373.3-156385.6" - wire width 64 $0\fast2$next[63:0]$8961 - attribute \src "libresoc.v:156232.3-156233.27" - wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:155571.7-155571.20" +module \pipe1 + attribute \src "libresoc.v:164051.3-164092.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9024 + attribute \src "libresoc.v:163827.3-163828.49" + wire width 4 $0\alu_op__data_len[3:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 14 $0\alu_op__fn_unit$next[13:0]$9025 + attribute \src "libresoc.v:163797.3-163798.47" + wire width 14 $0\alu_op__fn_unit[13:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9026 + attribute \src "libresoc.v:163799.3-163800.61" + wire width 64 $0\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9027 + attribute \src "libresoc.v:163801.3-163802.57" + wire $0\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9028 + attribute \src "libresoc.v:163819.3-163820.55" + wire width 2 $0\alu_op__input_carry[1:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 32 $0\alu_op__insn$next[31:0]$9029 + attribute \src "libresoc.v:163829.3-163830.41" + wire width 32 $0\alu_op__insn[31:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9030 + attribute \src "libresoc.v:163795.3-163796.51" + wire width 7 $0\alu_op__insn_type[6:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__invert_in$next[0:0]$9031 + attribute \src "libresoc.v:163811.3-163812.51" + wire $0\alu_op__invert_in[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__invert_out$next[0:0]$9032 + attribute \src "libresoc.v:163815.3-163816.53" + wire $0\alu_op__invert_out[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__is_32bit$next[0:0]$9033 + attribute \src "libresoc.v:163823.3-163824.49" + wire $0\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__is_signed$next[0:0]$9034 + attribute \src "libresoc.v:163825.3-163826.51" + wire $0\alu_op__is_signed[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__oe__oe$next[0:0]$9035 + attribute \src "libresoc.v:163807.3-163808.45" + wire $0\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__oe__ok$next[0:0]$9036 + attribute \src "libresoc.v:163809.3-163810.45" + wire $0\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__output_carry$next[0:0]$9037 + attribute \src "libresoc.v:163821.3-163822.57" + wire $0\alu_op__output_carry[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__rc__ok$next[0:0]$9038 + attribute \src "libresoc.v:163805.3-163806.45" + wire $0\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__rc__rc$next[0:0]$9039 + attribute \src "libresoc.v:163803.3-163804.45" + wire $0\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__write_cr0$next[0:0]$9040 + attribute \src "libresoc.v:163817.3-163818.51" + wire $0\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__zero_a$next[0:0]$9041 + attribute \src "libresoc.v:163813.3-163814.45" + wire $0\alu_op__zero_a[0:0] + attribute \src "libresoc.v:163944.3-163962.6" + wire width 4 $0\cr_a$next[3:0]$8993 + attribute \src "libresoc.v:163787.3-163788.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:163944.3-163962.6" + wire $0\cr_a_ok$next[0:0]$8994 + attribute \src "libresoc.v:163789.3-163790.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:162646.7-162646.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156300.3-156312.6" - wire width 2 $0\muxid$next[1:0]$8930 - attribute \src "libresoc.v:156228.3-156229.27" + attribute \src "libresoc.v:164038.3-164050.6" + wire width 2 $0\muxid$next[1:0]$9021 + attribute \src "libresoc.v:163831.3-163832.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:156282.3-156299.6" - wire $0\r_busy$next[0:0]$8926 - attribute \src "libresoc.v:156230.3-156231.29" + attribute \src "libresoc.v:164093.3-164111.6" + wire width 64 $0\o$next[63:0]$9067 + attribute \src "libresoc.v:163791.3-163792.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:164093.3-164111.6" + wire $0\o_ok$next[0:0]$9068 + attribute \src "libresoc.v:163793.3-163794.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:164020.3-164037.6" + wire $0\r_busy$next[0:0]$9017 + attribute \src "libresoc.v:163833.3-163834.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:156334.3-156346.6" - wire width 64 $0\ra$next[63:0]$8952 - attribute \src "libresoc.v:156238.3-156239.21" - wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:156347.3-156359.6" - wire width 64 $0\rb$next[63:0]$8955 - attribute \src "libresoc.v:156236.3-156237.21" - wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 64 $0\trap_op__cia$next[63:0]$8933 - attribute \src "libresoc.v:156218.3-156219.41" - wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 12 $0\trap_op__fn_unit$next[11:0]$8934 - attribute \src "libresoc.v:156242.3-156243.49" - wire width 12 $0\trap_op__fn_unit[11:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 32 $0\trap_op__insn$next[31:0]$8935 - attribute \src "libresoc.v:156214.3-156215.43" - wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 7 $0\trap_op__insn_type$next[6:0]$8936 - attribute \src "libresoc.v:156240.3-156241.53" - wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire $0\trap_op__is_32bit$next[0:0]$8937 - attribute \src "libresoc.v:156220.3-156221.51" - wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 8 $0\trap_op__ldst_exc$next[7:0]$8938 - attribute \src "libresoc.v:156226.3-156227.51" - wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 64 $0\trap_op__msr$next[63:0]$8939 - attribute \src "libresoc.v:156216.3-156217.41" - wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 13 $0\trap_op__trapaddr$next[12:0]$8940 - attribute \src "libresoc.v:156224.3-156225.51" - wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 8 $0\trap_op__traptype$next[7:0]$8941 - attribute \src "libresoc.v:156222.3-156223.51" - wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:156360.3-156372.6" - wire width 64 $1\fast1$next[63:0]$8959 - attribute \src "libresoc.v:155810.14-155810.42" - wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:156373.3-156385.6" - wire width 64 $1\fast2$next[63:0]$8962 - attribute \src "libresoc.v:155819.14-155819.42" - wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:156300.3-156312.6" - wire width 2 $1\muxid$next[1:0]$8931 - attribute \src "libresoc.v:155828.13-155828.25" + attribute \src "libresoc.v:163963.3-163981.6" + wire width 2 $0\xer_ca$next[1:0]$9000 + attribute \src "libresoc.v:163783.3-163784.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:163963.3-163981.6" + wire $0\xer_ca_ok$next[0:0]$8999 + attribute \src "libresoc.v:163785.3-163786.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:163982.3-164000.6" + wire width 2 $0\xer_ov$next[1:0]$9005 + attribute \src "libresoc.v:163779.3-163780.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:163982.3-164000.6" + wire $0\xer_ov_ok$next[0:0]$9006 + attribute \src "libresoc.v:163781.3-163782.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:164001.3-164019.6" + wire $0\xer_so$next[0:0]$9011 + attribute \src "libresoc.v:163775.3-163776.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:164001.3-164019.6" + wire $0\xer_so_ok$next[0:0]$9012 + attribute \src "libresoc.v:163777.3-163778.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9042 + attribute \src "libresoc.v:162651.13-162651.36" + wire width 4 $1\alu_op__data_len[3:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 14 $1\alu_op__fn_unit$next[13:0]$9043 + attribute \src "libresoc.v:162675.14-162675.40" + wire width 14 $1\alu_op__fn_unit[13:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9044 + attribute \src "libresoc.v:162714.14-162714.59" + wire width 64 $1\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9045 + attribute \src "libresoc.v:162723.7-162723.34" + wire $1\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9046 + attribute \src "libresoc.v:162736.13-162736.39" + wire width 2 $1\alu_op__input_carry[1:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 32 $1\alu_op__insn$next[31:0]$9047 + attribute \src "libresoc.v:162753.14-162753.34" + wire width 32 $1\alu_op__insn[31:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9048 + attribute \src "libresoc.v:162837.13-162837.38" + wire width 7 $1\alu_op__insn_type[6:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__invert_in$next[0:0]$9049 + attribute \src "libresoc.v:162996.7-162996.31" + wire $1\alu_op__invert_in[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__invert_out$next[0:0]$9050 + attribute \src "libresoc.v:163005.7-163005.32" + wire $1\alu_op__invert_out[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__is_32bit$next[0:0]$9051 + attribute \src "libresoc.v:163014.7-163014.30" + wire $1\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__is_signed$next[0:0]$9052 + attribute \src "libresoc.v:163023.7-163023.31" + wire $1\alu_op__is_signed[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__oe__oe$next[0:0]$9053 + attribute \src "libresoc.v:163032.7-163032.28" + wire $1\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__oe__ok$next[0:0]$9054 + attribute \src "libresoc.v:163041.7-163041.28" + wire $1\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__output_carry$next[0:0]$9055 + attribute \src "libresoc.v:163050.7-163050.34" + wire $1\alu_op__output_carry[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__rc__ok$next[0:0]$9056 + attribute \src "libresoc.v:163059.7-163059.28" + wire $1\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__rc__rc$next[0:0]$9057 + attribute \src "libresoc.v:163068.7-163068.28" + wire $1\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__write_cr0$next[0:0]$9058 + attribute \src "libresoc.v:163077.7-163077.31" + wire $1\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__zero_a$next[0:0]$9059 + attribute \src "libresoc.v:163086.7-163086.28" + wire $1\alu_op__zero_a[0:0] + attribute \src "libresoc.v:163944.3-163962.6" + wire width 4 $1\cr_a$next[3:0]$8995 + attribute \src "libresoc.v:163099.13-163099.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:163944.3-163962.6" + wire $1\cr_a_ok$next[0:0]$8996 + attribute \src "libresoc.v:163106.7-163106.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:164038.3-164050.6" + wire width 2 $1\muxid$next[1:0]$9022 + attribute \src "libresoc.v:163683.13-163683.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:156282.3-156299.6" - wire $1\r_busy$next[0:0]$8927 - attribute \src "libresoc.v:155850.7-155850.20" + attribute \src "libresoc.v:164093.3-164111.6" + wire width 64 $1\o$next[63:0]$9069 + attribute \src "libresoc.v:163698.14-163698.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:164093.3-164111.6" + wire $1\o_ok$next[0:0]$9070 + attribute \src "libresoc.v:163705.7-163705.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:164020.3-164037.6" + wire $1\r_busy$next[0:0]$9018 + attribute \src "libresoc.v:163719.7-163719.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:156334.3-156346.6" - wire width 64 $1\ra$next[63:0]$8953 - attribute \src "libresoc.v:155855.14-155855.39" - wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:156347.3-156359.6" - wire width 64 $1\rb$next[63:0]$8956 - attribute \src "libresoc.v:155864.14-155864.39" - wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 64 $1\trap_op__cia$next[63:0]$8942 - attribute \src "libresoc.v:155873.14-155873.49" - wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 12 $1\trap_op__fn_unit$next[11:0]$8943 - attribute \src "libresoc.v:155895.14-155895.40" - wire width 12 $1\trap_op__fn_unit[11:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 32 $1\trap_op__insn$next[31:0]$8944 - attribute \src "libresoc.v:155930.14-155930.35" - wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 7 $1\trap_op__insn_type$next[6:0]$8945 - attribute \src "libresoc.v:156013.13-156013.39" - wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire $1\trap_op__is_32bit$next[0:0]$8946 - attribute \src "libresoc.v:156170.7-156170.31" - wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 8 $1\trap_op__ldst_exc$next[7:0]$8947 - attribute \src "libresoc.v:156179.13-156179.38" - wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 64 $1\trap_op__msr$next[63:0]$8948 - attribute \src "libresoc.v:156188.14-156188.49" - wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 13 $1\trap_op__trapaddr$next[12:0]$8949 - attribute \src "libresoc.v:156197.14-156197.42" - wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:156313.3-156333.6" - wire width 8 $1\trap_op__traptype$next[7:0]$8950 - attribute \src "libresoc.v:156206.13-156206.38" - wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:156282.3-156299.6" - wire $2\r_busy$next[0:0]$8928 - attribute \src "libresoc.v:156213.18-156213.118" - wire $and$libresoc.v:156213$8909_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast1$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast2$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \dummy_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \dummy_muxid$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_ra$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_rb$26 + attribute \src "libresoc.v:163963.3-163981.6" + wire width 2 $1\xer_ca$next[1:0]$9002 + attribute \src "libresoc.v:163728.13-163728.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:163963.3-163981.6" + wire $1\xer_ca_ok$next[0:0]$9001 + attribute \src "libresoc.v:163737.7-163737.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:163982.3-164000.6" + wire width 2 $1\xer_ov$next[1:0]$9007 + attribute \src "libresoc.v:163744.13-163744.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:163982.3-164000.6" + wire $1\xer_ov_ok$next[0:0]$9008 + attribute \src "libresoc.v:163751.7-163751.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:164001.3-164019.6" + wire $1\xer_so$next[0:0]$9013 + attribute \src "libresoc.v:163758.7-163758.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:164001.3-164019.6" + wire $1\xer_so_ok$next[0:0]$9014 + attribute \src "libresoc.v:163767.7-163767.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$9060 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__imm_data__ok$next[0:0]$9061 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__oe__oe$next[0:0]$9062 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__oe__ok$next[0:0]$9063 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__rc__ok$next[0:0]$9064 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__rc__rc$next[0:0]$9065 + attribute \src "libresoc.v:163944.3-163962.6" + wire $2\cr_a_ok$next[0:0]$8997 + attribute \src "libresoc.v:164093.3-164111.6" + wire $2\o_ok$next[0:0]$9071 + attribute \src "libresoc.v:164020.3-164037.6" + wire $2\r_busy$next[0:0]$9019 + attribute \src "libresoc.v:163963.3-163981.6" + wire $2\xer_ca_ok$next[0:0]$9003 + attribute \src "libresoc.v:163982.3-164000.6" + wire $2\xer_ov_ok$next[0:0]$9009 + attribute \src "libresoc.v:164001.3-164019.6" + wire $2\xer_so_ok$next[0:0]$9015 + attribute \src "libresoc.v:163774.18-163774.118" + wire $and$libresoc.v:163774$8961_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__cia + wire width 4 output 21 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__cia$20 + wire width 4 input 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dummy_trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dummy_trap_op__fn_unit$17 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 37 \alu_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dummy_trap_op__insn + wire width 64 output 7 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dummy_trap_op__insn$18 + wire width 64 input 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -323564,8 +338041,9 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dummy_trap_op__insn_type + wire width 7 output 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -323640,151 +338118,256 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dummy_trap_op__insn_type$16 + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dummy_trap_op__is_32bit + wire width 7 \alu_op__insn_type$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dummy_trap_op__is_32bit$21 + wire width 7 \alu_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \dummy_trap_op__ldst_exc + wire output 13 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \dummy_trap_op__ldst_exc$24 + wire input 44 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__msr + wire \alu_op__invert_in$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__msr$19 + wire \alu_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dummy_trap_op__trapaddr + wire output 15 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dummy_trap_op__trapaddr$23 + wire input 46 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \dummy_trap_op__traptype + wire \alu_op__invert_out$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \dummy_trap_op__traptype$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 16 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 32 \fast1$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \fast1$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 17 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 33 \fast2$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \fast2$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \fast2$next - attribute \src "libresoc.v:155571.7-155571.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 20 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 19 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 18 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 14 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 30 \ra$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 15 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 31 \rb$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next + wire \alu_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 9 \trap_op__cia + wire output 19 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$37 + wire input 50 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 25 \trap_op__cia$6 + wire \alu_op__is_32bit$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \trap_op__fn_unit + wire \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:162646.7-162646.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len$39 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 22 \trap_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_alu_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 7 \trap_op__insn + wire width 64 \input_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$35 + wire width 64 \input_alu_op__imm_data__data$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 23 \trap_op__insn$4 + wire \input_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$next + wire \input_alu_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -323859,8 +338442,9 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \trap_op__insn_type + wire width 7 \input_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -323935,8 +338519,135 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 21 \trap_op__insn_type$2 + wire width 7 \input_alu_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_alu_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -324011,986 +338722,1666 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$33 + wire width 7 \main_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$next + wire width 7 \main_alu_op__insn_type$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \trap_op__is_32bit + wire \main_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$38 + wire \main_alu_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 26 \trap_op__is_32bit$7 + wire \main_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$next + wire \main_alu_op__invert_out$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 13 \trap_op__ldst_exc + wire \main_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 29 \trap_op__ldst_exc$10 + wire \main_alu_op__is_32bit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$41 + wire \main_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$next + wire \main_alu_op__is_signed$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 8 \trap_op__msr + wire \main_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$36 + wire \main_alu_op__oe__oe$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 24 \trap_op__msr$5 + wire \main_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$next + wire \main_alu_op__oe__ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 12 \trap_op__trapaddr + wire \main_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$40 + wire \main_alu_op__output_carry$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 28 \trap_op__trapaddr$9 + wire \main_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$next + wire \main_alu_op__rc__ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 11 \trap_op__traptype + wire \main_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$39 + wire \main_alu_op__rc__rc$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 27 \trap_op__traptype$8 + wire \main_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$next + wire \main_alu_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:156213$8909 + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:163774$8961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$29 + connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:156213$8909_Y + connect \Y $and$libresoc.v:163774$8961_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:156244.9-156273.4" - cell \dummy \dummy - connect \fast1 \dummy_fast1 - connect \fast1$13 \dummy_fast1$27 - connect \fast2 \dummy_fast2 - connect \fast2$14 \dummy_fast2$28 - connect \muxid \dummy_muxid - connect \muxid$1 \dummy_muxid$15 - connect \ra \dummy_ra - connect \ra$11 \dummy_ra$25 - connect \rb \dummy_rb - connect \rb$12 \dummy_rb$26 - connect \trap_op__cia \dummy_trap_op__cia - connect \trap_op__cia$6 \dummy_trap_op__cia$20 - connect \trap_op__fn_unit \dummy_trap_op__fn_unit - connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 - connect \trap_op__insn \dummy_trap_op__insn - connect \trap_op__insn$4 \dummy_trap_op__insn$18 - connect \trap_op__insn_type \dummy_trap_op__insn_type - connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 - connect \trap_op__is_32bit \dummy_trap_op__is_32bit - connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 - connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc - connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 - connect \trap_op__msr \dummy_trap_op__msr - connect \trap_op__msr$5 \dummy_trap_op__msr$19 - connect \trap_op__trapaddr \dummy_trap_op__trapaddr - connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 - connect \trap_op__traptype \dummy_trap_op__traptype - connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 + attribute \src "libresoc.v:163835.11-163882.4" + cell \input \input + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__insn \input_alu_op__insn + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__ok \input_alu_op__oe__ok + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__rc__ok \input_alu_op__rc__ok + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$22 + connect \ra \input_ra + connect \ra$20 \input_ra$41 + connect \rb \input_rb + connect \rb$21 \input_rb$42 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$44 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:156274.10-156277.4" - cell \n$34 \n + attribute \src "libresoc.v:163883.8-163935.4" + cell \main \main + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__insn \main_alu_op__insn + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__ok \main_alu_op__oe__ok + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__rc__ok \main_alu_op__rc__ok + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$45 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_ca \main_xer_ca + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so \main_xer_so + connect \xer_so$21 \main_xer_so$65 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:163936.9-163939.4" + cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:156278.10-156281.4" - cell \p$33 \p + attribute \src "libresoc.v:163940.9-163943.4" + cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:155571.7-155571.20" - process $proc$libresoc.v:155571$8963 + attribute \src "libresoc.v:162646.7-162646.20" + process $proc$libresoc.v:162646$9072 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155810.14-155810.42" - process $proc$libresoc.v:155810$8964 + attribute \src "libresoc.v:162651.13-162651.36" + process $proc$libresoc.v:162651$9073 assign { } { } - assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init - update \fast1 $1\fast1[63:0] + update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:155819.14-155819.42" - process $proc$libresoc.v:155819$8965 + attribute \src "libresoc.v:162675.14-162675.40" + process $proc$libresoc.v:162675$9074 assign { } { } - assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \fast2 $1\fast2[63:0] + update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:155828.13-155828.25" - process $proc$libresoc.v:155828$8966 + attribute \src "libresoc.v:162714.14-162714.59" + process $proc$libresoc.v:162714$9075 assign { } { } - assign $1\muxid[1:0] 2'00 + assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \muxid $1\muxid[1:0] + update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:155850.7-155850.20" - process $proc$libresoc.v:155850$8967 + attribute \src "libresoc.v:162723.7-162723.34" + process $proc$libresoc.v:162723$9076 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:155855.14-155855.39" - process $proc$libresoc.v:155855$8968 + attribute \src "libresoc.v:162736.13-162736.39" + process $proc$libresoc.v:162736$9077 assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init - update \ra $1\ra[63:0] + update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:155864.14-155864.39" - process $proc$libresoc.v:155864$8969 + attribute \src "libresoc.v:162753.14-162753.34" + process $proc$libresoc.v:162753$9078 assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__insn[31:0] 0 sync always sync init - update \rb $1\rb[63:0] + update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:155873.14-155873.49" - process $proc$libresoc.v:155873$8970 + attribute \src "libresoc.v:162837.13-162837.38" + process $proc$libresoc.v:162837$9079 assign { } { } - assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init - update \trap_op__cia $1\trap_op__cia[63:0] + update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:155895.14-155895.40" - process $proc$libresoc.v:155895$8971 + attribute \src "libresoc.v:162996.7-162996.31" + process $proc$libresoc.v:162996$9080 assign { } { } - assign $1\trap_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init - update \trap_op__fn_unit $1\trap_op__fn_unit[11:0] + update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:155930.14-155930.35" - process $proc$libresoc.v:155930$8972 + attribute \src "libresoc.v:163005.7-163005.32" + process $proc$libresoc.v:163005$9081 assign { } { } - assign $1\trap_op__insn[31:0] 0 + assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init - update \trap_op__insn $1\trap_op__insn[31:0] + update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:156013.13-156013.39" - process $proc$libresoc.v:156013$8973 + attribute \src "libresoc.v:163014.7-163014.30" + process $proc$libresoc.v:163014$9082 assign { } { } - assign $1\trap_op__insn_type[6:0] 7'0000000 + assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init - update \trap_op__insn_type $1\trap_op__insn_type[6:0] + update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:156170.7-156170.31" - process $proc$libresoc.v:156170$8974 + attribute \src "libresoc.v:163023.7-163023.31" + process $proc$libresoc.v:163023$9083 assign { } { } - assign $1\trap_op__is_32bit[0:0] 1'0 + assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init - update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] + update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:156179.13-156179.38" - process $proc$libresoc.v:156179$8975 + attribute \src "libresoc.v:163032.7-163032.28" + process $proc$libresoc.v:163032$9084 assign { } { } - assign $1\trap_op__ldst_exc[7:0] 8'00000000 + assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init - update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] + update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:156188.14-156188.49" - process $proc$libresoc.v:156188$8976 + attribute \src "libresoc.v:163041.7-163041.28" + process $proc$libresoc.v:163041$9085 assign { } { } - assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init - update \trap_op__msr $1\trap_op__msr[63:0] + update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:156197.14-156197.42" - process $proc$libresoc.v:156197$8977 + attribute \src "libresoc.v:163050.7-163050.34" + process $proc$libresoc.v:163050$9086 assign { } { } - assign $1\trap_op__trapaddr[12:0] 13'0000000000000 + assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init - update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] + update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:156206.13-156206.38" - process $proc$libresoc.v:156206$8978 + attribute \src "libresoc.v:163059.7-163059.28" + process $proc$libresoc.v:163059$9087 assign { } { } - assign $1\trap_op__traptype[7:0] 8'00000000 + assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init - update \trap_op__traptype $1\trap_op__traptype[7:0] + update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:156214.3-156215.43" - process $proc$libresoc.v:156214$8910 + attribute \src "libresoc.v:163068.7-163068.28" + process $proc$libresoc.v:163068$9088 assign { } { } - assign $0\trap_op__insn[31:0] \trap_op__insn$next + assign $1\alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:163077.7-163077.31" + process $proc$libresoc.v:163077$9089 + assign { } { } + assign $1\alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:163086.7-163086.28" + process $proc$libresoc.v:163086$9090 + assign { } { } + assign $1\alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_op__zero_a $1\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:163099.13-163099.24" + process $proc$libresoc.v:163099$9091 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:163106.7-163106.21" + process $proc$libresoc.v:163106$9092 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:163683.13-163683.25" + process $proc$libresoc.v:163683$9093 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:163698.14-163698.38" + process $proc$libresoc.v:163698$9094 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:163705.7-163705.18" + process $proc$libresoc.v:163705$9095 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:163719.7-163719.20" + process $proc$libresoc.v:163719$9096 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:163728.13-163728.26" + process $proc$libresoc.v:163728$9097 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:163737.7-163737.23" + process $proc$libresoc.v:163737$9098 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:163744.13-163744.26" + process $proc$libresoc.v:163744$9099 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:163751.7-163751.23" + process $proc$libresoc.v:163751$9100 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:163758.7-163758.20" + process $proc$libresoc.v:163758$9101 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:163767.7-163767.23" + process $proc$libresoc.v:163767$9102 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:163775.3-163776.29" + process $proc$libresoc.v:163775$8962 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk - update \trap_op__insn $0\trap_op__insn[31:0] + update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:156216.3-156217.41" - process $proc$libresoc.v:156216$8911 + attribute \src "libresoc.v:163777.3-163778.35" + process $proc$libresoc.v:163777$8963 assign { } { } - assign $0\trap_op__msr[63:0] \trap_op__msr$next + assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk - update \trap_op__msr $0\trap_op__msr[63:0] + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:156218.3-156219.41" - process $proc$libresoc.v:156218$8912 + attribute \src "libresoc.v:163779.3-163780.29" + process $proc$libresoc.v:163779$8964 assign { } { } - assign $0\trap_op__cia[63:0] \trap_op__cia$next + assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk - update \trap_op__cia $0\trap_op__cia[63:0] + update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:156220.3-156221.51" - process $proc$libresoc.v:156220$8913 + attribute \src "libresoc.v:163781.3-163782.35" + process $proc$libresoc.v:163781$8965 assign { } { } - assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk - update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] + update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:156222.3-156223.51" - process $proc$libresoc.v:156222$8914 + attribute \src "libresoc.v:163783.3-163784.29" + process $proc$libresoc.v:163783$8966 assign { } { } - assign $0\trap_op__traptype[7:0] \trap_op__traptype$next + assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk - update \trap_op__traptype $0\trap_op__traptype[7:0] + update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:156224.3-156225.51" - process $proc$libresoc.v:156224$8915 + attribute \src "libresoc.v:163785.3-163786.35" + process $proc$libresoc.v:163785$8967 assign { } { } - assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk - update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] + update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:156226.3-156227.51" - process $proc$libresoc.v:156226$8916 + attribute \src "libresoc.v:163787.3-163788.25" + process $proc$libresoc.v:163787$8968 assign { } { } - assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next + assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk - update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] + update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:156228.3-156229.27" - process $proc$libresoc.v:156228$8917 + attribute \src "libresoc.v:163789.3-163790.31" + process $proc$libresoc.v:163789$8969 assign { } { } - assign $0\muxid[1:0] \muxid$next + assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk - update \muxid $0\muxid[1:0] + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:156230.3-156231.29" - process $proc$libresoc.v:156230$8918 + attribute \src "libresoc.v:163791.3-163792.19" + process $proc$libresoc.v:163791$8970 assign { } { } - assign $0\r_busy[0:0] \r_busy$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + update \o $0\o[63:0] end - attribute \src "libresoc.v:156232.3-156233.27" - process $proc$libresoc.v:156232$8919 + attribute \src "libresoc.v:163793.3-163794.25" + process $proc$libresoc.v:163793$8971 assign { } { } - assign $0\fast2[63:0] \fast2$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \fast2 $0\fast2[63:0] + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:156234.3-156235.27" - process $proc$libresoc.v:156234$8920 + attribute \src "libresoc.v:163795.3-163796.51" + process $proc$libresoc.v:163795$8972 assign { } { } - assign $0\fast1[63:0] \fast1$next + assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk - update \fast1 $0\fast1[63:0] + update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:156236.3-156237.21" - process $proc$libresoc.v:156236$8921 + attribute \src "libresoc.v:163797.3-163798.47" + process $proc$libresoc.v:163797$8973 assign { } { } - assign $0\rb[63:0] \rb$next + assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk - update \rb $0\rb[63:0] + update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:156238.3-156239.21" - process $proc$libresoc.v:156238$8922 + attribute \src "libresoc.v:163799.3-163800.61" + process $proc$libresoc.v:163799$8974 assign { } { } - assign $0\ra[63:0] \ra$next + assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk - update \ra $0\ra[63:0] + update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:156240.3-156241.53" - process $proc$libresoc.v:156240$8923 + attribute \src "libresoc.v:163801.3-163802.57" + process $proc$libresoc.v:163801$8975 assign { } { } - assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next + assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk - update \trap_op__insn_type $0\trap_op__insn_type[6:0] + update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:163803.3-163804.45" + process $proc$libresoc.v:163803$8976 + assign { } { } + assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:163805.3-163806.45" + process $proc$libresoc.v:163805$8977 + assign { } { } + assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:163807.3-163808.45" + process $proc$libresoc.v:163807$8978 + assign { } { } + assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:163809.3-163810.45" + process $proc$libresoc.v:163809$8979 + assign { } { } + assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:163811.3-163812.51" + process $proc$libresoc.v:163811$8980 + assign { } { } + assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_op__invert_in $0\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:163813.3-163814.45" + process $proc$libresoc.v:163813$8981 + assign { } { } + assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_op__zero_a $0\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:163815.3-163816.53" + process $proc$libresoc.v:163815$8982 + assign { } { } + assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_op__invert_out $0\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:163817.3-163818.51" + process $proc$libresoc.v:163817$8983 + assign { } { } + assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:163819.3-163820.55" + process $proc$libresoc.v:163819$8984 + assign { } { } + assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_op__input_carry $0\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:163821.3-163822.57" + process $proc$libresoc.v:163821$8985 + assign { } { } + assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_op__output_carry $0\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:163823.3-163824.49" + process $proc$libresoc.v:163823$8986 + assign { } { } + assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:163825.3-163826.51" + process $proc$libresoc.v:163825$8987 + assign { } { } + assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_op__is_signed $0\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:163827.3-163828.49" + process $proc$libresoc.v:163827$8988 + assign { } { } + assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + sync posedge \coresync_clk + update \alu_op__data_len $0\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:163829.3-163830.41" + process $proc$libresoc.v:163829$8989 + assign { } { } + assign $0\alu_op__insn[31:0] \alu_op__insn$next + sync posedge \coresync_clk + update \alu_op__insn $0\alu_op__insn[31:0] + end + attribute \src "libresoc.v:163831.3-163832.27" + process $proc$libresoc.v:163831$8990 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:156242.3-156243.49" - process $proc$libresoc.v:156242$8924 + attribute \src "libresoc.v:163833.3-163834.29" + process $proc$libresoc.v:163833$8991 assign { } { } - assign $0\trap_op__fn_unit[11:0] \trap_op__fn_unit$next + assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk - update \trap_op__fn_unit $0\trap_op__fn_unit[11:0] + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:156282.3-156299.6" - process $proc$libresoc.v:156282$8925 + attribute \src "libresoc.v:163944.3-163962.6" + process $proc$libresoc.v:163944$8992 + assign { } { } + assign { } { } assign { } { } assign { } { } + assign $0\cr_a$next[3:0]$8993 $1\cr_a$next[3:0]$8995 assign { } { } - assign $0\r_busy$next[0:0]$8926 $2\r_busy$next[0:0]$8928 - attribute \src "libresoc.v:156283.5-156283.29" + assign $0\cr_a_ok$next[0:0]$8994 $2\cr_a_ok$next[0:0]$8997 + attribute \src "libresoc.v:163945.5-163945.29" switch \initial - attribute \src "libresoc.v:156283.9-156283.17" + attribute \src "libresoc.v:163945.9-163945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8927 1'1 + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8996 $1\cr_a$next[3:0]$8995 } { \cr_a_ok$91 \cr_a$90 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8927 1'0 + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8996 $1\cr_a$next[3:0]$8995 } { \cr_a_ok$91 \cr_a$90 } case - assign $1\r_busy$next[0:0]$8927 \r_busy + assign $1\cr_a$next[3:0]$8995 \cr_a + assign $1\cr_a_ok$next[0:0]$8996 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8928 1'0 + assign $2\cr_a_ok$next[0:0]$8997 1'0 case - assign $2\r_busy$next[0:0]$8928 $1\r_busy$next[0:0]$8927 + assign $2\cr_a_ok$next[0:0]$8997 $1\cr_a_ok$next[0:0]$8996 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8926 + update \cr_a$next $0\cr_a$next[3:0]$8993 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8994 end - attribute \src "libresoc.v:156300.3-156312.6" - process $proc$libresoc.v:156300$8929 + attribute \src "libresoc.v:163963.3-163981.6" + process $proc$libresoc.v:163963$8998 + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\muxid$next[1:0]$8930 $1\muxid$next[1:0]$8931 - attribute \src "libresoc.v:156301.5-156301.29" + assign { } { } + assign $0\xer_ca$next[1:0]$9000 $1\xer_ca$next[1:0]$9002 + assign $0\xer_ca_ok$next[0:0]$8999 $2\xer_ca_ok$next[0:0]$9003 + attribute \src "libresoc.v:163964.5-163964.29" switch \initial - attribute \src "libresoc.v:156301.9-156301.17" + attribute \src "libresoc.v:163964.9-163964.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$8931 \muxid$32 + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9001 $1\xer_ca$next[1:0]$9002 } { \xer_ca_ok$93 \xer_ca$92 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$8931 \muxid$32 + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9001 $1\xer_ca$next[1:0]$9002 } { \xer_ca_ok$93 \xer_ca$92 } + case + assign $1\xer_ca_ok$next[0:0]$9001 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9002 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$9003 1'0 case - assign $1\muxid$next[1:0]$8931 \muxid + assign $2\xer_ca_ok$next[0:0]$9003 $1\xer_ca_ok$next[0:0]$9001 end sync always - update \muxid$next $0\muxid$next[1:0]$8930 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8999 + update \xer_ca$next $0\xer_ca$next[1:0]$9000 end - attribute \src "libresoc.v:156313.3-156333.6" - process $proc$libresoc.v:156313$8932 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:163982.3-164000.6" + process $proc$libresoc.v:163982$9004 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\xer_ov$next[1:0]$9005 $1\xer_ov$next[1:0]$9007 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\trap_op__cia$next[63:0]$8933 $1\trap_op__cia$next[63:0]$8942 - assign $0\trap_op__fn_unit$next[11:0]$8934 $1\trap_op__fn_unit$next[11:0]$8943 - assign $0\trap_op__insn$next[31:0]$8935 $1\trap_op__insn$next[31:0]$8944 - assign $0\trap_op__insn_type$next[6:0]$8936 $1\trap_op__insn_type$next[6:0]$8945 - assign $0\trap_op__is_32bit$next[0:0]$8937 $1\trap_op__is_32bit$next[0:0]$8946 - assign $0\trap_op__ldst_exc$next[7:0]$8938 $1\trap_op__ldst_exc$next[7:0]$8947 - assign $0\trap_op__msr$next[63:0]$8939 $1\trap_op__msr$next[63:0]$8948 - assign $0\trap_op__trapaddr$next[12:0]$8940 $1\trap_op__trapaddr$next[12:0]$8949 - assign $0\trap_op__traptype$next[7:0]$8941 $1\trap_op__traptype$next[7:0]$8950 - attribute \src "libresoc.v:156314.5-156314.29" + assign $0\xer_ov_ok$next[0:0]$9006 $2\xer_ov_ok$next[0:0]$9009 + attribute \src "libresoc.v:163983.5-163983.29" switch \initial - attribute \src "libresoc.v:156314.9-156314.17" + attribute \src "libresoc.v:163983.9-163983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$8947 $1\trap_op__trapaddr$next[12:0]$8949 $1\trap_op__traptype$next[7:0]$8950 $1\trap_op__is_32bit$next[0:0]$8946 $1\trap_op__cia$next[63:0]$8942 $1\trap_op__msr$next[63:0]$8948 $1\trap_op__insn$next[31:0]$8944 $1\trap_op__fn_unit$next[11:0]$8943 $1\trap_op__insn_type$next[6:0]$8945 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\xer_ov_ok$next[0:0]$9008 $1\xer_ov$next[1:0]$9007 } { \xer_ov_ok$95 \xer_ov$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9008 $1\xer_ov$next[1:0]$9007 } { \xer_ov_ok$95 \xer_ov$94 } + case + assign $1\xer_ov$next[1:0]$9007 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9008 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $2\xer_ov_ok$next[0:0]$9009 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9009 $1\xer_ov_ok$next[0:0]$9008 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9005 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9006 + end + attribute \src "libresoc.v:164001.3-164019.6" + process $proc$libresoc.v:164001$9010 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$9011 $1\xer_so$next[0:0]$9013 + assign { } { } + assign $0\xer_so_ok$next[0:0]$9012 $2\xer_so_ok$next[0:0]$9015 + attribute \src "libresoc.v:164002.5-164002.29" + switch \initial + attribute \src "libresoc.v:164002.9-164002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } assign { } { } + assign { $1\xer_so_ok$next[0:0]$9014 $1\xer_so$next[0:0]$9013 } { \xer_so_ok$97 \xer_so$96 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } assign { } { } + assign { $1\xer_so_ok$next[0:0]$9014 $1\xer_so$next[0:0]$9013 } { \xer_so_ok$97 \xer_so$96 } + case + assign $1\xer_so$next[0:0]$9013 \xer_so + assign $1\xer_so_ok$next[0:0]$9014 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$8947 $1\trap_op__trapaddr$next[12:0]$8949 $1\trap_op__traptype$next[7:0]$8950 $1\trap_op__is_32bit$next[0:0]$8946 $1\trap_op__cia$next[63:0]$8942 $1\trap_op__msr$next[63:0]$8948 $1\trap_op__insn$next[31:0]$8944 $1\trap_op__fn_unit$next[11:0]$8943 $1\trap_op__insn_type$next[6:0]$8945 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign $2\xer_so_ok$next[0:0]$9015 1'0 case - assign $1\trap_op__cia$next[63:0]$8942 \trap_op__cia - assign $1\trap_op__fn_unit$next[11:0]$8943 \trap_op__fn_unit - assign $1\trap_op__insn$next[31:0]$8944 \trap_op__insn - assign $1\trap_op__insn_type$next[6:0]$8945 \trap_op__insn_type - assign $1\trap_op__is_32bit$next[0:0]$8946 \trap_op__is_32bit - assign $1\trap_op__ldst_exc$next[7:0]$8947 \trap_op__ldst_exc - assign $1\trap_op__msr$next[63:0]$8948 \trap_op__msr - assign $1\trap_op__trapaddr$next[12:0]$8949 \trap_op__trapaddr - assign $1\trap_op__traptype$next[7:0]$8950 \trap_op__traptype + assign $2\xer_so_ok$next[0:0]$9015 $1\xer_so_ok$next[0:0]$9014 end sync always - update \trap_op__cia$next $0\trap_op__cia$next[63:0]$8933 - update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[11:0]$8934 - update \trap_op__insn$next $0\trap_op__insn$next[31:0]$8935 - update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$8936 - update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$8937 - update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$8938 - update \trap_op__msr$next $0\trap_op__msr$next[63:0]$8939 - update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$8940 - update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$8941 + update \xer_so$next $0\xer_so$next[0:0]$9011 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9012 end - attribute \src "libresoc.v:156334.3-156346.6" - process $proc$libresoc.v:156334$8951 + attribute \src "libresoc.v:164020.3-164037.6" + process $proc$libresoc.v:164020$9016 + assign { } { } assign { } { } assign { } { } - assign $0\ra$next[63:0]$8952 $1\ra$next[63:0]$8953 - attribute \src "libresoc.v:156335.5-156335.29" + assign $0\r_busy$next[0:0]$9017 $2\r_busy$next[0:0]$9019 + attribute \src "libresoc.v:164021.5-164021.29" switch \initial - attribute \src "libresoc.v:156335.9-156335.17" + attribute \src "libresoc.v:164021.9-164021.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$8953 \ra$42 + assign $1\r_busy$next[0:0]$9018 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$8953 \ra$42 + assign $1\r_busy$next[0:0]$9018 1'0 + case + assign $1\r_busy$next[0:0]$9018 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9019 1'0 case - assign $1\ra$next[63:0]$8953 \ra + assign $2\r_busy$next[0:0]$9019 $1\r_busy$next[0:0]$9018 end sync always - update \ra$next $0\ra$next[63:0]$8952 + update \r_busy$next $0\r_busy$next[0:0]$9017 end - attribute \src "libresoc.v:156347.3-156359.6" - process $proc$libresoc.v:156347$8954 + attribute \src "libresoc.v:164038.3-164050.6" + process $proc$libresoc.v:164038$9020 assign { } { } assign { } { } - assign $0\rb$next[63:0]$8955 $1\rb$next[63:0]$8956 - attribute \src "libresoc.v:156348.5-156348.29" + assign $0\muxid$next[1:0]$9021 $1\muxid$next[1:0]$9022 + attribute \src "libresoc.v:164039.5-164039.29" switch \initial - attribute \src "libresoc.v:156348.9-156348.17" + attribute \src "libresoc.v:164039.9-164039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$8956 \rb$43 + assign $1\muxid$next[1:0]$9022 \muxid$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$8956 \rb$43 + assign $1\muxid$next[1:0]$9022 \muxid$69 case - assign $1\rb$next[63:0]$8956 \rb + assign $1\muxid$next[1:0]$9022 \muxid end sync always - update \rb$next $0\rb$next[63:0]$8955 + update \muxid$next $0\muxid$next[1:0]$9021 end - attribute \src "libresoc.v:156360.3-156372.6" - process $proc$libresoc.v:156360$8957 + attribute \src "libresoc.v:164051.3-164092.6" + process $proc$libresoc.v:164051$9023 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\fast1$next[63:0]$8958 $1\fast1$next[63:0]$8959 - attribute \src "libresoc.v:156361.5-156361.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$next[3:0]$9024 $1\alu_op__data_len$next[3:0]$9042 + assign $0\alu_op__fn_unit$next[13:0]$9025 $1\alu_op__fn_unit$next[13:0]$9043 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$next[1:0]$9028 $1\alu_op__input_carry$next[1:0]$9046 + assign $0\alu_op__insn$next[31:0]$9029 $1\alu_op__insn$next[31:0]$9047 + assign $0\alu_op__insn_type$next[6:0]$9030 $1\alu_op__insn_type$next[6:0]$9048 + assign $0\alu_op__invert_in$next[0:0]$9031 $1\alu_op__invert_in$next[0:0]$9049 + assign $0\alu_op__invert_out$next[0:0]$9032 $1\alu_op__invert_out$next[0:0]$9050 + assign $0\alu_op__is_32bit$next[0:0]$9033 $1\alu_op__is_32bit$next[0:0]$9051 + assign $0\alu_op__is_signed$next[0:0]$9034 $1\alu_op__is_signed$next[0:0]$9052 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$next[0:0]$9037 $1\alu_op__output_carry$next[0:0]$9055 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$next[0:0]$9040 $1\alu_op__write_cr0$next[0:0]$9058 + assign $0\alu_op__zero_a$next[0:0]$9041 $1\alu_op__zero_a$next[0:0]$9059 + assign $0\alu_op__imm_data__data$next[63:0]$9026 $2\alu_op__imm_data__data$next[63:0]$9060 + assign $0\alu_op__imm_data__ok$next[0:0]$9027 $2\alu_op__imm_data__ok$next[0:0]$9061 + assign $0\alu_op__oe__oe$next[0:0]$9035 $2\alu_op__oe__oe$next[0:0]$9062 + assign $0\alu_op__oe__ok$next[0:0]$9036 $2\alu_op__oe__ok$next[0:0]$9063 + assign $0\alu_op__rc__ok$next[0:0]$9038 $2\alu_op__rc__ok$next[0:0]$9064 + assign $0\alu_op__rc__rc$next[0:0]$9039 $2\alu_op__rc__rc$next[0:0]$9065 + attribute \src "libresoc.v:164052.5-164052.29" switch \initial - attribute \src "libresoc.v:156361.9-156361.17" + attribute \src "libresoc.v:164052.9-164052.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast1$next[63:0]$8959 \fast1$44 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$9047 $1\alu_op__data_len$next[3:0]$9042 $1\alu_op__is_signed$next[0:0]$9052 $1\alu_op__is_32bit$next[0:0]$9051 $1\alu_op__output_carry$next[0:0]$9055 $1\alu_op__input_carry$next[1:0]$9046 $1\alu_op__write_cr0$next[0:0]$9058 $1\alu_op__invert_out$next[0:0]$9050 $1\alu_op__zero_a$next[0:0]$9059 $1\alu_op__invert_in$next[0:0]$9049 $1\alu_op__oe__ok$next[0:0]$9054 $1\alu_op__oe__oe$next[0:0]$9053 $1\alu_op__rc__ok$next[0:0]$9056 $1\alu_op__rc__rc$next[0:0]$9057 $1\alu_op__imm_data__ok$next[0:0]$9045 $1\alu_op__imm_data__data$next[63:0]$9044 $1\alu_op__fn_unit$next[13:0]$9043 $1\alu_op__insn_type$next[6:0]$9048 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast1$next[63:0]$8959 \fast1$44 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$9047 $1\alu_op__data_len$next[3:0]$9042 $1\alu_op__is_signed$next[0:0]$9052 $1\alu_op__is_32bit$next[0:0]$9051 $1\alu_op__output_carry$next[0:0]$9055 $1\alu_op__input_carry$next[1:0]$9046 $1\alu_op__write_cr0$next[0:0]$9058 $1\alu_op__invert_out$next[0:0]$9050 $1\alu_op__zero_a$next[0:0]$9059 $1\alu_op__invert_in$next[0:0]$9049 $1\alu_op__oe__ok$next[0:0]$9054 $1\alu_op__oe__oe$next[0:0]$9053 $1\alu_op__rc__ok$next[0:0]$9056 $1\alu_op__rc__rc$next[0:0]$9057 $1\alu_op__imm_data__ok$next[0:0]$9045 $1\alu_op__imm_data__data$next[63:0]$9044 $1\alu_op__fn_unit$next[13:0]$9043 $1\alu_op__insn_type$next[6:0]$9048 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + case + assign $1\alu_op__data_len$next[3:0]$9042 \alu_op__data_len + assign $1\alu_op__fn_unit$next[13:0]$9043 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9044 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9045 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9046 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9047 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9048 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9049 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9050 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9051 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9052 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9053 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9054 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9055 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9056 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9057 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9058 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9059 \alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$next[63:0]$9060 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9061 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9065 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9064 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9062 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9063 1'0 case - assign $1\fast1$next[63:0]$8959 \fast1 + assign $2\alu_op__imm_data__data$next[63:0]$9060 $1\alu_op__imm_data__data$next[63:0]$9044 + assign $2\alu_op__imm_data__ok$next[0:0]$9061 $1\alu_op__imm_data__ok$next[0:0]$9045 + assign $2\alu_op__oe__oe$next[0:0]$9062 $1\alu_op__oe__oe$next[0:0]$9053 + assign $2\alu_op__oe__ok$next[0:0]$9063 $1\alu_op__oe__ok$next[0:0]$9054 + assign $2\alu_op__rc__ok$next[0:0]$9064 $1\alu_op__rc__ok$next[0:0]$9056 + assign $2\alu_op__rc__rc$next[0:0]$9065 $1\alu_op__rc__rc$next[0:0]$9057 end sync always - update \fast1$next $0\fast1$next[63:0]$8958 + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9024 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9025 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9026 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9027 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9028 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9029 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9030 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9031 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9032 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9033 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9034 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9035 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9036 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9037 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9038 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9039 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9040 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9041 end - attribute \src "libresoc.v:156373.3-156385.6" - process $proc$libresoc.v:156373$8960 + attribute \src "libresoc.v:164093.3-164111.6" + process $proc$libresoc.v:164093$9066 + assign { } { } assign { } { } assign { } { } - assign $0\fast2$next[63:0]$8961 $1\fast2$next[63:0]$8962 - attribute \src "libresoc.v:156374.5-156374.29" + assign { } { } + assign $0\o$next[63:0]$9067 $1\o$next[63:0]$9069 + assign { } { } + assign $0\o_ok$next[0:0]$9068 $2\o_ok$next[0:0]$9071 + attribute \src "libresoc.v:164094.5-164094.29" switch \initial - attribute \src "libresoc.v:156374.9-156374.17" + attribute \src "libresoc.v:164094.9-164094.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast2$next[63:0]$8962 \fast2$45 + assign { } { } + assign { $1\o_ok$next[0:0]$9070 $1\o$next[63:0]$9069 } { \o_ok$89 \o$88 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast2$next[63:0]$8962 \fast2$45 + assign { } { } + assign { $1\o_ok$next[0:0]$9070 $1\o$next[63:0]$9069 } { \o_ok$89 \o$88 } case - assign $1\fast2$next[63:0]$8962 \fast2 + assign $1\o$next[63:0]$9069 \o + assign $1\o_ok$next[0:0]$9070 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9071 1'0 + case + assign $2\o_ok$next[0:0]$9071 $1\o_ok$next[0:0]$9070 end sync always - update \fast2$next $0\fast2$next[63:0]$8961 + update \o$next $0\o$next[63:0]$9067 + update \o_ok$next $0\o_ok$next[0:0]$9068 end - connect \$30 $and$libresoc.v:156213$8909_Y + connect \$67 $and$libresoc.v:163774$8961_Y + connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect \fast2$45 \dummy_fast2$28 - connect \fast1$44 \dummy_fast1$27 - connect \rb$43 \dummy_rb$26 - connect \ra$42 \dummy_ra$25 - connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } - connect \muxid$32 \dummy_muxid$15 - connect \p_valid_i_p_ready_o \$30 + connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } + connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } + connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + connect \muxid$69 \main_muxid$45 + connect \p_valid_i_p_ready_o \$67 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$29 \p_valid_i - connect \dummy_fast2 \fast2$14 - connect \dummy_fast1 \fast1$13 - connect \dummy_rb \rb$12 - connect \dummy_ra \ra$11 - connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } - connect \dummy_muxid \muxid$1 + connect \p_valid_i$66 \p_valid_i + connect \main_xer_ca \input_xer_ca$44 + connect \main_xer_so \input_xer_so$43 + connect \main_rb \input_rb$42 + connect \main_ra \input_ra$41 + connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + connect \main_muxid \input_muxid$22 + connect \input_xer_ca \xer_ca$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } + connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:156407.1-157577.10" +attribute \src "libresoc.v:164141.1-165577.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" -module \pipe2 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$9047 - attribute \src "libresoc.v:157318.3-157319.57" - wire width 4 $0\alu_op__data_len$18[3:0]$9033 - attribute \src "libresoc.v:156415.13-156415.41" - wire width 4 $0\alu_op__data_len$18[3:0]$9121 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 12 $0\alu_op__fn_unit$3$next[11:0]$9048 - attribute \src "libresoc.v:157288.3-157289.53" - wire width 12 $0\alu_op__fn_unit$3[11:0]$9003 - attribute \src "libresoc.v:156450.14-156450.43" - wire width 12 $0\alu_op__fn_unit$3[11:0]$9123 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9049 - attribute \src "libresoc.v:157290.3-157291.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9005 - attribute \src "libresoc.v:156472.14-156472.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9125 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$9050 - attribute \src "libresoc.v:157292.3-157293.63" - wire $0\alu_op__imm_data__ok$5[0:0]$9007 - attribute \src "libresoc.v:156481.7-156481.38" - wire $0\alu_op__imm_data__ok$5[0:0]$9127 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$9051 - attribute \src "libresoc.v:157310.3-157311.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$9025 - attribute \src "libresoc.v:156498.13-156498.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$9129 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$9052 - attribute \src "libresoc.v:157320.3-157321.49" - wire width 32 $0\alu_op__insn$19[31:0]$9035 - attribute \src "libresoc.v:156511.14-156511.39" - wire width 32 $0\alu_op__insn$19[31:0]$9131 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$9053 - attribute \src "libresoc.v:157286.3-157287.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$9001 - attribute \src "libresoc.v:156668.13-156668.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$9133 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__invert_in$10$next[0:0]$9054 - attribute \src "libresoc.v:157302.3-157303.59" - wire $0\alu_op__invert_in$10[0:0]$9017 - attribute \src "libresoc.v:156751.7-156751.36" - wire $0\alu_op__invert_in$10[0:0]$9135 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__invert_out$12$next[0:0]$9055 - attribute \src "libresoc.v:157306.3-157307.61" - wire $0\alu_op__invert_out$12[0:0]$9021 - attribute \src "libresoc.v:156760.7-156760.37" - wire $0\alu_op__invert_out$12[0:0]$9137 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__is_32bit$16$next[0:0]$9056 - attribute \src "libresoc.v:157314.3-157315.57" - wire $0\alu_op__is_32bit$16[0:0]$9029 - attribute \src "libresoc.v:156769.7-156769.35" - wire $0\alu_op__is_32bit$16[0:0]$9139 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__is_signed$17$next[0:0]$9057 - attribute \src "libresoc.v:157316.3-157317.59" - wire $0\alu_op__is_signed$17[0:0]$9031 - attribute \src "libresoc.v:156778.7-156778.36" - wire $0\alu_op__is_signed$17[0:0]$9141 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__oe__oe$8$next[0:0]$9058 - attribute \src "libresoc.v:157298.3-157299.51" - wire $0\alu_op__oe__oe$8[0:0]$9013 - attribute \src "libresoc.v:156789.7-156789.32" - wire $0\alu_op__oe__oe$8[0:0]$9143 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__oe__ok$9$next[0:0]$9059 - attribute \src "libresoc.v:157300.3-157301.51" - wire $0\alu_op__oe__ok$9[0:0]$9015 - attribute \src "libresoc.v:156798.7-156798.32" - wire $0\alu_op__oe__ok$9[0:0]$9145 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__output_carry$15$next[0:0]$9060 - attribute \src "libresoc.v:157312.3-157313.65" - wire $0\alu_op__output_carry$15[0:0]$9027 - attribute \src "libresoc.v:156805.7-156805.39" - wire $0\alu_op__output_carry$15[0:0]$9147 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__rc__ok$7$next[0:0]$9061 - attribute \src "libresoc.v:157296.3-157297.51" - wire $0\alu_op__rc__ok$7[0:0]$9011 - attribute \src "libresoc.v:156816.7-156816.32" - wire $0\alu_op__rc__ok$7[0:0]$9149 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__rc__rc$6$next[0:0]$9062 - attribute \src "libresoc.v:157294.3-157295.51" - wire $0\alu_op__rc__rc$6[0:0]$9009 - attribute \src "libresoc.v:156823.7-156823.32" - wire $0\alu_op__rc__rc$6[0:0]$9151 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__write_cr0$13$next[0:0]$9063 - attribute \src "libresoc.v:157308.3-157309.59" - wire $0\alu_op__write_cr0$13[0:0]$9023 - attribute \src "libresoc.v:156832.7-156832.36" - wire $0\alu_op__write_cr0$13[0:0]$9153 - attribute \src "libresoc.v:157421.3-157462.6" - wire $0\alu_op__zero_a$11$next[0:0]$9064 - attribute \src "libresoc.v:157304.3-157305.53" - wire $0\alu_op__zero_a$11[0:0]$9019 - attribute \src "libresoc.v:156841.7-156841.33" - wire $0\alu_op__zero_a$11[0:0]$9155 - attribute \src "libresoc.v:157482.3-157500.6" - wire width 4 $0\cr_a$22$next[3:0]$9096 - attribute \src "libresoc.v:157278.3-157279.33" - wire width 4 $0\cr_a$22[3:0]$8993 - attribute \src "libresoc.v:156854.13-156854.29" - wire width 4 $0\cr_a$22[3:0]$9157 - attribute \src "libresoc.v:157482.3-157500.6" - wire $0\cr_a_ok$23$next[0:0]$9097 - attribute \src "libresoc.v:157280.3-157281.39" - wire $0\cr_a_ok$23[0:0]$8995 - attribute \src "libresoc.v:156863.7-156863.26" - wire $0\cr_a_ok$23[0:0]$9159 - attribute \src "libresoc.v:156408.7-156408.20" +module \pipe1$110 + attribute \src "libresoc.v:165510.3-165528.6" + wire width 4 $0\cr_a$next[3:0]$9192 + attribute \src "libresoc.v:165252.3-165253.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:165510.3-165528.6" + wire $0\cr_a_ok$next[0:0]$9193 + attribute \src "libresoc.v:165254.3-165255.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:164142.7-164142.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157408.3-157420.6" - wire width 2 $0\muxid$1$next[1:0]$9044 - attribute \src "libresoc.v:157322.3-157323.33" - wire width 2 $0\muxid$1[1:0]$9037 - attribute \src "libresoc.v:156874.13-156874.29" - wire width 2 $0\muxid$1[1:0]$9161 - attribute \src "libresoc.v:157463.3-157481.6" - wire width 64 $0\o$20$next[63:0]$9090 - attribute \src "libresoc.v:157282.3-157283.27" - wire width 64 $0\o$20[63:0]$8997 - attribute \src "libresoc.v:156889.14-156889.43" - wire width 64 $0\o$20[63:0]$9163 - attribute \src "libresoc.v:157463.3-157481.6" - wire $0\o_ok$21$next[0:0]$9091 - attribute \src "libresoc.v:157284.3-157285.33" - wire $0\o_ok$21[0:0]$8999 - attribute \src "libresoc.v:156898.7-156898.23" - wire $0\o_ok$21[0:0]$9165 - attribute \src "libresoc.v:157390.3-157407.6" - wire $0\r_busy$next[0:0]$9040 - attribute \src "libresoc.v:157324.3-157325.29" + attribute \src "libresoc.v:165437.3-165449.6" + wire width 2 $0\muxid$next[1:0]$9142 + attribute \src "libresoc.v:165294.3-165295.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:165491.3-165509.6" + wire width 64 $0\o$next[63:0]$9186 + attribute \src "libresoc.v:165256.3-165257.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:165491.3-165509.6" + wire $0\o_ok$next[0:0]$9187 + attribute \src "libresoc.v:165258.3-165259.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:165419.3-165436.6" + wire $0\r_busy$next[0:0]$9138 + attribute \src "libresoc.v:165296.3-165297.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:157501.3-157519.6" - wire width 2 $0\xer_ca$24$next[1:0]$9102 - attribute \src "libresoc.v:157274.3-157275.37" - wire width 2 $0\xer_ca$24[1:0]$8989 - attribute \src "libresoc.v:157209.13-157209.31" - wire width 2 $0\xer_ca$24[1:0]$9168 - attribute \src "libresoc.v:157501.3-157519.6" - wire $0\xer_ca_ok$25$next[0:0]$9103 - attribute \src "libresoc.v:157276.3-157277.43" - wire $0\xer_ca_ok$25[0:0]$8991 - attribute \src "libresoc.v:157218.7-157218.28" - wire $0\xer_ca_ok$25[0:0]$9170 - attribute \src "libresoc.v:157520.3-157538.6" - wire width 2 $0\xer_ov$26$next[1:0]$9108 - attribute \src "libresoc.v:157270.3-157271.37" - wire width 2 $0\xer_ov$26[1:0]$8985 - attribute \src "libresoc.v:157229.13-157229.31" - wire width 2 $0\xer_ov$26[1:0]$9172 - attribute \src "libresoc.v:157520.3-157538.6" - wire $0\xer_ov_ok$27$next[0:0]$9109 - attribute \src "libresoc.v:157272.3-157273.43" - wire $0\xer_ov_ok$27[0:0]$8987 - attribute \src "libresoc.v:157238.7-157238.28" - wire $0\xer_ov_ok$27[0:0]$9174 - attribute \src "libresoc.v:157539.3-157557.6" - wire $0\xer_so$28$next[0:0]$9114 - attribute \src "libresoc.v:157266.3-157267.37" - wire $0\xer_so$28[0:0]$8981 - attribute \src "libresoc.v:157249.7-157249.25" - wire $0\xer_so$28[0:0]$9176 - attribute \src "libresoc.v:157539.3-157557.6" - wire $0\xer_so_ok$29$next[0:0]$9115 - attribute \src "libresoc.v:157268.3-157269.43" - wire $0\xer_so_ok$29[0:0]$8983 - attribute \src "libresoc.v:157258.7-157258.28" - wire $0\xer_so_ok$29[0:0]$9178 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$9065 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 12 $1\alu_op__fn_unit$3$next[11:0]$9066 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9067 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$9068 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$9069 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$9070 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$9071 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__invert_in$10$next[0:0]$9072 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__invert_out$12$next[0:0]$9073 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__is_32bit$16$next[0:0]$9074 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__is_signed$17$next[0:0]$9075 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__oe__oe$8$next[0:0]$9076 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__oe__ok$9$next[0:0]$9077 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__output_carry$15$next[0:0]$9078 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__rc__ok$7$next[0:0]$9079 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__rc__rc$6$next[0:0]$9080 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__write_cr0$13$next[0:0]$9081 - attribute \src "libresoc.v:157421.3-157462.6" - wire $1\alu_op__zero_a$11$next[0:0]$9082 - attribute \src "libresoc.v:157482.3-157500.6" - wire width 4 $1\cr_a$22$next[3:0]$9098 - attribute \src "libresoc.v:157482.3-157500.6" - wire $1\cr_a_ok$23$next[0:0]$9099 - attribute \src "libresoc.v:157408.3-157420.6" - wire width 2 $1\muxid$1$next[1:0]$9045 - attribute \src "libresoc.v:157463.3-157481.6" - wire width 64 $1\o$20$next[63:0]$9092 - attribute \src "libresoc.v:157463.3-157481.6" - wire $1\o_ok$21$next[0:0]$9093 - attribute \src "libresoc.v:157390.3-157407.6" - wire $1\r_busy$next[0:0]$9041 - attribute \src "libresoc.v:157202.7-157202.20" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 14 $0\sr_op__fn_unit$next[13:0]$9145 + attribute \src "libresoc.v:165262.3-165263.45" + wire width 14 $0\sr_op__fn_unit[13:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9146 + attribute \src "libresoc.v:165264.3-165265.59" + wire width 64 $0\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9147 + attribute \src "libresoc.v:165266.3-165267.55" + wire $0\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9148 + attribute \src "libresoc.v:165280.3-165281.53" + wire width 2 $0\sr_op__input_carry[1:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__input_cr$next[0:0]$9149 + attribute \src "libresoc.v:165284.3-165285.47" + wire $0\sr_op__input_cr[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 32 $0\sr_op__insn$next[31:0]$9150 + attribute \src "libresoc.v:165292.3-165293.39" + wire width 32 $0\sr_op__insn[31:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9151 + attribute \src "libresoc.v:165260.3-165261.49" + wire width 7 $0\sr_op__insn_type[6:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__invert_in$next[0:0]$9152 + attribute \src "libresoc.v:165278.3-165279.49" + wire $0\sr_op__invert_in[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__is_32bit$next[0:0]$9153 + attribute \src "libresoc.v:165288.3-165289.47" + wire $0\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__is_signed$next[0:0]$9154 + attribute \src "libresoc.v:165290.3-165291.49" + wire $0\sr_op__is_signed[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__oe__oe$next[0:0]$9155 + attribute \src "libresoc.v:165272.3-165273.43" + wire $0\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__oe__ok$next[0:0]$9156 + attribute \src "libresoc.v:165274.3-165275.43" + wire $0\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__output_carry$next[0:0]$9157 + attribute \src "libresoc.v:165282.3-165283.55" + wire $0\sr_op__output_carry[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__output_cr$next[0:0]$9158 + attribute \src "libresoc.v:165286.3-165287.49" + wire $0\sr_op__output_cr[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__rc__ok$next[0:0]$9159 + attribute \src "libresoc.v:165270.3-165271.43" + wire $0\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__rc__rc$next[0:0]$9160 + attribute \src "libresoc.v:165268.3-165269.43" + wire $0\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__write_cr0$next[0:0]$9161 + attribute \src "libresoc.v:165276.3-165277.49" + wire $0\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:165400.3-165418.6" + wire width 2 $0\xer_ca$next[1:0]$9133 + attribute \src "libresoc.v:165244.3-165245.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:165400.3-165418.6" + wire $0\xer_ca_ok$next[0:0]$9132 + attribute \src "libresoc.v:165246.3-165247.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:165529.3-165547.6" + wire $0\xer_so$next[0:0]$9198 + attribute \src "libresoc.v:165248.3-165249.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:165529.3-165547.6" + wire $0\xer_so_ok$next[0:0]$9199 + attribute \src "libresoc.v:165250.3-165251.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:165510.3-165528.6" + wire width 4 $1\cr_a$next[3:0]$9194 + attribute \src "libresoc.v:164151.13-164151.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:165510.3-165528.6" + wire $1\cr_a_ok$next[0:0]$9195 + attribute \src "libresoc.v:164160.7-164160.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:165437.3-165449.6" + wire width 2 $1\muxid$next[1:0]$9143 + attribute \src "libresoc.v:164725.13-164725.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:165491.3-165509.6" + wire width 64 $1\o$next[63:0]$9188 + attribute \src "libresoc.v:164740.14-164740.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:165491.3-165509.6" + wire $1\o_ok$next[0:0]$9189 + attribute \src "libresoc.v:164747.7-164747.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:165419.3-165436.6" + wire $1\r_busy$next[0:0]$9139 + attribute \src "libresoc.v:164761.7-164761.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:157501.3-157519.6" - wire width 2 $1\xer_ca$24$next[1:0]$9104 - attribute \src "libresoc.v:157501.3-157519.6" - wire $1\xer_ca_ok$25$next[0:0]$9105 - attribute \src "libresoc.v:157520.3-157538.6" - wire width 2 $1\xer_ov$26$next[1:0]$9110 - attribute \src "libresoc.v:157520.3-157538.6" - wire $1\xer_ov_ok$27$next[0:0]$9111 - attribute \src "libresoc.v:157539.3-157557.6" - wire $1\xer_so$28$next[0:0]$9116 - attribute \src "libresoc.v:157539.3-157557.6" - wire $1\xer_so_ok$29$next[0:0]$9117 - attribute \src "libresoc.v:157421.3-157462.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9083 - attribute \src "libresoc.v:157421.3-157462.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$9084 - attribute \src "libresoc.v:157421.3-157462.6" - wire $2\alu_op__oe__oe$8$next[0:0]$9085 - attribute \src "libresoc.v:157421.3-157462.6" - wire $2\alu_op__oe__ok$9$next[0:0]$9086 - attribute \src "libresoc.v:157421.3-157462.6" - wire $2\alu_op__rc__ok$7$next[0:0]$9087 - attribute \src "libresoc.v:157421.3-157462.6" - wire $2\alu_op__rc__rc$6$next[0:0]$9088 - attribute \src "libresoc.v:157482.3-157500.6" - wire $2\cr_a_ok$23$next[0:0]$9100 - attribute \src "libresoc.v:157463.3-157481.6" - wire $2\o_ok$21$next[0:0]$9094 - attribute \src "libresoc.v:157390.3-157407.6" - wire $2\r_busy$next[0:0]$9042 - attribute \src "libresoc.v:157501.3-157519.6" - wire $2\xer_ca_ok$25$next[0:0]$9106 - attribute \src "libresoc.v:157520.3-157538.6" - wire $2\xer_ov_ok$27$next[0:0]$9112 - attribute \src "libresoc.v:157539.3-157557.6" - wire $2\xer_so_ok$29$next[0:0]$9118 - attribute \src "libresoc.v:157265.18-157265.118" - wire $and$libresoc.v:157265$8979_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$79 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \alu_op__fn_unit + attribute \src "libresoc.v:165450.3-165490.6" + wire width 14 $1\sr_op__fn_unit$next[13:0]$9162 + attribute \src "libresoc.v:164787.14-164787.39" + wire width 14 $1\sr_op__fn_unit[13:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9163 + attribute \src "libresoc.v:164826.14-164826.58" + wire width 64 $1\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9164 + attribute \src "libresoc.v:164835.7-164835.33" + wire $1\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9165 + attribute \src "libresoc.v:164848.13-164848.38" + wire width 2 $1\sr_op__input_carry[1:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__input_cr$next[0:0]$9166 + attribute \src "libresoc.v:164865.7-164865.29" + wire $1\sr_op__input_cr[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 32 $1\sr_op__insn$next[31:0]$9167 + attribute \src "libresoc.v:164874.14-164874.33" + wire width 32 $1\sr_op__insn[31:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9168 + attribute \src "libresoc.v:164958.13-164958.37" + wire width 7 $1\sr_op__insn_type[6:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__invert_in$next[0:0]$9169 + attribute \src "libresoc.v:165117.7-165117.30" + wire $1\sr_op__invert_in[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__is_32bit$next[0:0]$9170 + attribute \src "libresoc.v:165126.7-165126.29" + wire $1\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__is_signed$next[0:0]$9171 + attribute \src "libresoc.v:165135.7-165135.30" + wire $1\sr_op__is_signed[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__oe__oe$next[0:0]$9172 + attribute \src "libresoc.v:165144.7-165144.27" + wire $1\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__oe__ok$next[0:0]$9173 + attribute \src "libresoc.v:165153.7-165153.27" + wire $1\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__output_carry$next[0:0]$9174 + attribute \src "libresoc.v:165162.7-165162.33" + wire $1\sr_op__output_carry[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__output_cr$next[0:0]$9175 + attribute \src "libresoc.v:165171.7-165171.30" + wire $1\sr_op__output_cr[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__rc__ok$next[0:0]$9176 + attribute \src "libresoc.v:165180.7-165180.27" + wire $1\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__rc__rc$next[0:0]$9177 + attribute \src "libresoc.v:165189.7-165189.27" + wire $1\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__write_cr0$next[0:0]$9178 + attribute \src "libresoc.v:165198.7-165198.30" + wire $1\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:165400.3-165418.6" + wire width 2 $1\xer_ca$next[1:0]$9135 + attribute \src "libresoc.v:165207.13-165207.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:165400.3-165418.6" + wire $1\xer_ca_ok$next[0:0]$9134 + attribute \src "libresoc.v:165218.7-165218.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:165529.3-165547.6" + wire $1\xer_so$next[0:0]$9200 + attribute \src "libresoc.v:165227.7-165227.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:165529.3-165547.6" + wire $1\xer_so_ok$next[0:0]$9201 + attribute \src "libresoc.v:165236.7-165236.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:165510.3-165528.6" + wire $2\cr_a_ok$next[0:0]$9196 + attribute \src "libresoc.v:165491.3-165509.6" + wire $2\o_ok$next[0:0]$9190 + attribute \src "libresoc.v:165419.3-165436.6" + wire $2\r_busy$next[0:0]$9140 + attribute \src "libresoc.v:165450.3-165490.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9179 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9180 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__oe__oe$next[0:0]$9181 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__oe__ok$next[0:0]$9182 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__rc__ok$next[0:0]$9183 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__rc__rc$next[0:0]$9184 + attribute \src "libresoc.v:165400.3-165418.6" + wire $2\xer_ca_ok$next[0:0]$9136 + attribute \src "libresoc.v:165529.3-165547.6" + wire $2\xer_so_ok$next[0:0]$9202 + attribute \src "libresoc.v:165243.18-165243.118" + wire $and$libresoc.v:165243$9103_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 55 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:164142.7-164142.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$41 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 37 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \alu_op__imm_data__data + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_sr_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__imm_data__ok$5 + wire width 64 \input_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$5$next + wire width 64 \input_sr_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$66 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \input_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \alu_op__input_carry + wire \input_sr_op__imm_data__ok$25 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 48 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$14$next + wire width 2 \input_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$75 + wire width 2 \input_sr_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \alu_op__insn + wire \input_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \alu_op__insn$19 + wire \input_sr_op__input_cr$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$19$next + wire width 32 \input_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$80 + wire width 32 \input_sr_op__insn$38 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -325065,8 +340456,9 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \alu_op__insn_type + wire width 7 \input_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -325141,10 +340533,133 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \alu_op__insn_type$2 + wire width 7 \input_sr_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$2$next + wire \input_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_sr_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn$61 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -325219,208 +340734,281 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \alu_op__oe__ok$9 + wire width 7 \main_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$9$next + wire width 7 \main_sr_op__insn_type$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \alu_op__output_carry + wire \main_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \alu_op__output_carry$15 + wire \main_sr_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$15$next + wire \main_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$76 + wire \main_sr_op__is_32bit$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__rc__ok + wire \main_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$68 + wire \main_sr_op__is_signed$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \alu_op__rc__ok$7 + wire \main_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$7$next + wire \main_sr_op__oe__oe$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__rc__rc + wire \main_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \alu_op__rc__rc$6 + wire \main_sr_op__oe__ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$6$next + wire \main_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$67 + wire \main_sr_op__output_carry$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__write_cr0 + wire \main_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \alu_op__write_cr0$13 + wire \main_sr_op__output_cr$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$13$next + wire \main_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$74 + wire \main_sr_op__rc__ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__zero_a + wire \main_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \alu_op__zero_a$11 + wire \main_sr_op__rc__rc$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$11$next + wire \main_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 56 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 57 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$23$next + wire \main_sr_op__write_cr0$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$55 + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$84 - attribute \src "libresoc.v:156408.7-156408.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$20$next + wire width 64 output 22 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$81 + wire width 64 \o$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 24 \o_ok + wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \o_ok$21 + wire output 23 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$21$next + wire \o_ok$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$82 + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 31 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 30 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 52 \rc + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 34 \sr_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len + wire width 64 output 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len$47 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_alu_op__fn_unit$32 + wire output 8 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__data + wire input 36 \sr_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__data$33 + wire \sr_op__imm_data__ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__imm_data__ok + wire \sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__imm_data__ok$34 + wire width 2 output 15 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_alu_op__input_carry + wire width 2 input 43 \sr_op__input_carry$12 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_alu_op__input_carry$43 + wire width 2 \sr_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_alu_op__insn + wire width 2 \sr_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_alu_op__insn$48 + wire output 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -325495,8 +341083,9 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_alu_op__insn_type + wire width 7 output 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -325571,761 +341160,846 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_alu_op__insn_type$31 + wire width 7 input 33 \sr_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_in + wire width 7 \sr_op__insn_type$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_in$39 + wire width 7 \sr_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_out + wire output 14 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_out$41 + wire input 42 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_32bit + wire \sr_op__invert_in$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_32bit$45 + wire \sr_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_signed + wire output 19 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_signed$46 + wire input 47 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__oe + wire \sr_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__oe$37 + wire \sr_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__ok + wire output 20 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__ok$38 + wire input 48 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__output_carry + wire \sr_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__output_carry$44 + wire \sr_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__ok + wire output 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__ok$36 + wire \sr_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__rc + wire input 39 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__rc$35 + wire \sr_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__write_cr0 + wire output 12 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__write_cr0$42 + wire \sr_op__oe__ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__zero_a + wire input 40 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__zero_a$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 58 \xer_ca$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 59 \xer_ca_ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 60 \xer_ov$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$87 + wire \sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 30 \xer_ov_ok + wire width 2 output 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 54 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \xer_ca$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 61 \xer_ov_ok$27 + wire width 2 \xer_ca$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$27$next + wire width 2 \xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$57 + wire output 29 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$88 + wire \xer_ca_ok$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 31 \xer_so + wire \xer_ca_ok$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 62 \xer_so$28 + wire \xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$28$next + wire output 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 53 \xer_so$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$89 + wire \xer_so$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 32 \xer_so_ok + wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 63 \xer_so_ok$29 + wire output 27 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$29$next + wire \xer_so_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$58 + wire \xer_so_ok$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$90 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:157265$8979 + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:165243$9103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$59 + connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:157265$8979_Y + connect \Y $and$libresoc.v:165243$9103_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:157326.9-157329.4" - cell \n$4 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:165298.15-165345.4" + cell \input$113 \input + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$19 \input_ra$39 + connect \rb \input_rb + connect \rb$20 \input_rb$40 + connect \rc \input_rc + connect \rc$21 \input_rc$41 + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 + connect \sr_op__insn \input_sr_op__insn + connect \sr_op__insn$18 \input_sr_op__insn$38 + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 + connect \sr_op__invert_in \input_sr_op__invert_in + connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 + connect \sr_op__rc__ok \input_sr_op__rc__ok + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 + connect \sr_op__write_cr0 \input_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:157330.12-157385.4" - cell \output \output - connect \alu_op__data_len \output_alu_op__data_len - connect \alu_op__data_len$18 \output_alu_op__data_len$47 - connect \alu_op__fn_unit \output_alu_op__fn_unit - connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 - connect \alu_op__imm_data__data \output_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 - connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 - connect \alu_op__input_carry \output_alu_op__input_carry - connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 - connect \alu_op__insn \output_alu_op__insn - connect \alu_op__insn$19 \output_alu_op__insn$48 - connect \alu_op__insn_type \output_alu_op__insn_type - connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 - connect \alu_op__invert_in \output_alu_op__invert_in - connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 - connect \alu_op__invert_out \output_alu_op__invert_out - connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 - connect \alu_op__is_32bit \output_alu_op__is_32bit - connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 - connect \alu_op__is_signed \output_alu_op__is_signed - connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 - connect \alu_op__oe__oe \output_alu_op__oe__oe - connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 - connect \alu_op__oe__ok \output_alu_op__oe__ok - connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 - connect \alu_op__output_carry \output_alu_op__output_carry - connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 - connect \alu_op__rc__ok \output_alu_op__rc__ok - connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 - connect \alu_op__rc__rc \output_alu_op__rc__rc - connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 - connect \alu_op__write_cr0 \output_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 - connect \alu_op__zero_a \output_alu_op__zero_a - connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$51 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$30 - connect \o \output_o - connect \o$20 \output_o$49 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$50 - connect \xer_ca \output_xer_ca - connect \xer_ca$23 \output_xer_ca$52 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_ov \output_xer_ov - connect \xer_ov$24 \output_xer_ov$53 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$25 \output_xer_so$54 - connect \xer_so_ok \output_xer_so_ok + attribute \src "libresoc.v:165346.14-165391.4" + cell \main$114 \main + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$44 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 + connect \sr_op__insn \main_sr_op__insn + connect \sr_op__insn$18 \main_sr_op__insn$61 + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 + connect \sr_op__invert_in \main_sr_op__invert_in + connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 + connect \sr_op__rc__ok \main_sr_op__rc__ok + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 + connect \sr_op__write_cr0 \main_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 + connect \xer_ca \main_xer_ca + connect \xer_so \main_xer_so + connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:157386.9-157389.4" - cell \p$3 \p + attribute \src "libresoc.v:165392.11-165395.4" + cell \n$112 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165396.11-165399.4" + cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:156408.7-156408.20" - process $proc$libresoc.v:156408$9119 + attribute \src "libresoc.v:164142.7-164142.20" + process $proc$libresoc.v:164142$9203 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156415.13-156415.41" - process $proc$libresoc.v:156415$9120 - assign { } { } - assign $0\alu_op__data_len$18[3:0]$9121 4'0000 - sync always - sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9121 - end - attribute \src "libresoc.v:156450.14-156450.43" - process $proc$libresoc.v:156450$9122 - assign { } { } - assign $0\alu_op__fn_unit$3[11:0]$9123 12'000000000000 - sync always - sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$9123 - end - attribute \src "libresoc.v:156472.14-156472.63" - process $proc$libresoc.v:156472$9124 - assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9125 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9125 - end - attribute \src "libresoc.v:156481.7-156481.38" - process $proc$libresoc.v:156481$9126 + attribute \src "libresoc.v:164151.13-164151.24" + process $proc$libresoc.v:164151$9204 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9127 1'0 + assign $1\cr_a[3:0] 4'0000 sync always sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9127 + update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:156498.13-156498.44" - process $proc$libresoc.v:156498$9128 + attribute \src "libresoc.v:164160.7-164160.21" + process $proc$libresoc.v:164160$9205 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9129 2'00 + assign $1\cr_a_ok[0:0] 1'0 sync always sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9129 + update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:156511.14-156511.39" - process $proc$libresoc.v:156511$9130 + attribute \src "libresoc.v:164725.13-164725.25" + process $proc$libresoc.v:164725$9206 assign { } { } - assign $0\alu_op__insn$19[31:0]$9131 0 + assign $1\muxid[1:0] 2'00 sync always sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9131 + update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:156668.13-156668.42" - process $proc$libresoc.v:156668$9132 + attribute \src "libresoc.v:164740.14-164740.38" + process $proc$libresoc.v:164740$9207 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9133 7'0000000 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9133 + update \o $1\o[63:0] end - attribute \src "libresoc.v:156751.7-156751.36" - process $proc$libresoc.v:156751$9134 + attribute \src "libresoc.v:164747.7-164747.18" + process $proc$libresoc.v:164747$9208 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9135 1'0 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9135 + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:156760.7-156760.37" - process $proc$libresoc.v:156760$9136 + attribute \src "libresoc.v:164761.7-164761.20" + process $proc$libresoc.v:164761$9209 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9137 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9137 + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:156769.7-156769.35" - process $proc$libresoc.v:156769$9138 + attribute \src "libresoc.v:164787.14-164787.39" + process $proc$libresoc.v:164787$9210 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9139 1'0 + assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9139 + update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:156778.7-156778.36" - process $proc$libresoc.v:156778$9140 + attribute \src "libresoc.v:164826.14-164826.58" + process $proc$libresoc.v:164826$9211 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9141 1'0 + assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9141 + update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:156789.7-156789.32" - process $proc$libresoc.v:156789$9142 + attribute \src "libresoc.v:164835.7-164835.33" + process $proc$libresoc.v:164835$9212 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9143 1'0 + assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9143 + update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:156798.7-156798.32" - process $proc$libresoc.v:156798$9144 + attribute \src "libresoc.v:164848.13-164848.38" + process $proc$libresoc.v:164848$9213 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9145 1'0 + assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9145 + update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:156805.7-156805.39" - process $proc$libresoc.v:156805$9146 + attribute \src "libresoc.v:164865.7-164865.29" + process $proc$libresoc.v:164865$9214 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9147 1'0 + assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9147 + update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:156816.7-156816.32" - process $proc$libresoc.v:156816$9148 + attribute \src "libresoc.v:164874.14-164874.33" + process $proc$libresoc.v:164874$9215 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9149 1'0 + assign $1\sr_op__insn[31:0] 0 sync always sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9149 + update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:156823.7-156823.32" - process $proc$libresoc.v:156823$9150 + attribute \src "libresoc.v:164958.13-164958.37" + process $proc$libresoc.v:164958$9216 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9151 1'0 + assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9151 + update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:156832.7-156832.36" - process $proc$libresoc.v:156832$9152 + attribute \src "libresoc.v:165117.7-165117.30" + process $proc$libresoc.v:165117$9217 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9153 1'0 + assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9153 + update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:156841.7-156841.33" - process $proc$libresoc.v:156841$9154 + attribute \src "libresoc.v:165126.7-165126.29" + process $proc$libresoc.v:165126$9218 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9155 1'0 + assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9155 + update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:156854.13-156854.29" - process $proc$libresoc.v:156854$9156 + attribute \src "libresoc.v:165135.7-165135.30" + process $proc$libresoc.v:165135$9219 assign { } { } - assign $0\cr_a$22[3:0]$9157 4'0000 + assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$9157 + update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:156863.7-156863.26" - process $proc$libresoc.v:156863$9158 + attribute \src "libresoc.v:165144.7-165144.27" + process $proc$libresoc.v:165144$9220 assign { } { } - assign $0\cr_a_ok$23[0:0]$9159 1'0 + assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9159 + update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:156874.13-156874.29" - process $proc$libresoc.v:156874$9160 + attribute \src "libresoc.v:165153.7-165153.27" + process $proc$libresoc.v:165153$9221 assign { } { } - assign $0\muxid$1[1:0]$9161 2'00 + assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9161 + update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:156889.14-156889.43" - process $proc$libresoc.v:156889$9162 + attribute \src "libresoc.v:165162.7-165162.33" + process $proc$libresoc.v:165162$9222 assign { } { } - assign $0\o$20[63:0]$9163 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init - update \o$20 $0\o$20[63:0]$9163 + update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:156898.7-156898.23" - process $proc$libresoc.v:156898$9164 + attribute \src "libresoc.v:165171.7-165171.30" + process $proc$libresoc.v:165171$9223 assign { } { } - assign $0\o_ok$21[0:0]$9165 1'0 + assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$9165 + update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:157202.7-157202.20" - process $proc$libresoc.v:157202$9166 + attribute \src "libresoc.v:165180.7-165180.27" + process $proc$libresoc.v:165180$9224 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:157209.13-157209.31" - process $proc$libresoc.v:157209$9167 + attribute \src "libresoc.v:165189.7-165189.27" + process $proc$libresoc.v:165189$9225 assign { } { } - assign $0\xer_ca$24[1:0]$9168 2'00 + assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$9168 + update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:157218.7-157218.28" - process $proc$libresoc.v:157218$9169 + attribute \src "libresoc.v:165198.7-165198.30" + process $proc$libresoc.v:165198$9226 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9170 1'0 + assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9170 + update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:157229.13-157229.31" - process $proc$libresoc.v:157229$9171 + attribute \src "libresoc.v:165207.13-165207.26" + process $proc$libresoc.v:165207$9227 assign { } { } - assign $0\xer_ov$26[1:0]$9172 2'00 + assign $1\xer_ca[1:0] 2'00 sync always sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$9172 + update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:157238.7-157238.28" - process $proc$libresoc.v:157238$9173 + attribute \src "libresoc.v:165218.7-165218.23" + process $proc$libresoc.v:165218$9228 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9174 1'0 + assign $1\xer_ca_ok[0:0] 1'0 sync always sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9174 + update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:157249.7-157249.25" - process $proc$libresoc.v:157249$9175 + attribute \src "libresoc.v:165227.7-165227.20" + process $proc$libresoc.v:165227$9229 assign { } { } - assign $0\xer_so$28[0:0]$9176 1'0 + assign $1\xer_so[0:0] 1'0 sync always sync init - update \xer_so$28 $0\xer_so$28[0:0]$9176 + update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:157258.7-157258.28" - process $proc$libresoc.v:157258$9177 + attribute \src "libresoc.v:165236.7-165236.23" + process $proc$libresoc.v:165236$9230 assign { } { } - assign $0\xer_so_ok$29[0:0]$9178 1'0 + assign $1\xer_so_ok[0:0] 1'0 sync always sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9178 - end - attribute \src "libresoc.v:157266.3-157267.37" - process $proc$libresoc.v:157266$8980 - assign { } { } - assign $0\xer_so$28[0:0]$8981 \xer_so$28$next - sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$8981 - end - attribute \src "libresoc.v:157268.3-157269.43" - process $proc$libresoc.v:157268$8982 - assign { } { } - assign $0\xer_so_ok$29[0:0]$8983 \xer_so_ok$29$next - sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8983 - end - attribute \src "libresoc.v:157270.3-157271.37" - process $proc$libresoc.v:157270$8984 - assign { } { } - assign $0\xer_ov$26[1:0]$8985 \xer_ov$26$next - sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$8985 + update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:157272.3-157273.43" - process $proc$libresoc.v:157272$8986 + attribute \src "libresoc.v:165244.3-165245.29" + process $proc$libresoc.v:165244$9104 assign { } { } - assign $0\xer_ov_ok$27[0:0]$8987 \xer_ov_ok$27$next + assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8987 + update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:157274.3-157275.37" - process $proc$libresoc.v:157274$8988 + attribute \src "libresoc.v:165246.3-165247.35" + process $proc$libresoc.v:165246$9105 assign { } { } - assign $0\xer_ca$24[1:0]$8989 \xer_ca$24$next + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$8989 + update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:157276.3-157277.43" - process $proc$libresoc.v:157276$8990 + attribute \src "libresoc.v:165248.3-165249.29" + process $proc$libresoc.v:165248$9106 assign { } { } - assign $0\xer_ca_ok$25[0:0]$8991 \xer_ca_ok$25$next + assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8991 + update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:157278.3-157279.33" - process $proc$libresoc.v:157278$8992 + attribute \src "libresoc.v:165250.3-165251.35" + process $proc$libresoc.v:165250$9107 assign { } { } - assign $0\cr_a$22[3:0]$8993 \cr_a$22$next + assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$8993 + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:157280.3-157281.39" - process $proc$libresoc.v:157280$8994 + attribute \src "libresoc.v:165252.3-165253.25" + process $proc$libresoc.v:165252$9108 assign { } { } - assign $0\cr_a_ok$23[0:0]$8995 \cr_a_ok$23$next + assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8995 + update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:157282.3-157283.27" - process $proc$libresoc.v:157282$8996 + attribute \src "libresoc.v:165254.3-165255.31" + process $proc$libresoc.v:165254$9109 assign { } { } - assign $0\o$20[63:0]$8997 \o$20$next + assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$8997 + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:157284.3-157285.33" - process $proc$libresoc.v:157284$8998 + attribute \src "libresoc.v:165256.3-165257.19" + process $proc$libresoc.v:165256$9110 assign { } { } - assign $0\o_ok$21[0:0]$8999 \o_ok$21$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$8999 + update \o $0\o[63:0] end - attribute \src "libresoc.v:157286.3-157287.57" - process $proc$libresoc.v:157286$9000 + attribute \src "libresoc.v:165258.3-165259.25" + process $proc$libresoc.v:165258$9111 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9001 \alu_op__insn_type$2$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9001 + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:157288.3-157289.53" - process $proc$libresoc.v:157288$9002 + attribute \src "libresoc.v:165260.3-165261.49" + process $proc$libresoc.v:165260$9112 assign { } { } - assign $0\alu_op__fn_unit$3[11:0]$9003 \alu_op__fn_unit$3$next + assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$9003 + update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:157290.3-157291.67" - process $proc$libresoc.v:157290$9004 + attribute \src "libresoc.v:165262.3-165263.45" + process $proc$libresoc.v:165262$9113 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9005 \alu_op__imm_data__data$4$next + assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9005 + update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:157292.3-157293.63" - process $proc$libresoc.v:157292$9006 + attribute \src "libresoc.v:165264.3-165265.59" + process $proc$libresoc.v:165264$9114 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9007 \alu_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9007 + update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:157294.3-157295.51" - process $proc$libresoc.v:157294$9008 + attribute \src "libresoc.v:165266.3-165267.55" + process $proc$libresoc.v:165266$9115 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9009 \alu_op__rc__rc$6$next + assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9009 + update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:157296.3-157297.51" - process $proc$libresoc.v:157296$9010 + attribute \src "libresoc.v:165268.3-165269.43" + process $proc$libresoc.v:165268$9116 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9011 \alu_op__rc__ok$7$next + assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9011 + update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:157298.3-157299.51" - process $proc$libresoc.v:157298$9012 + attribute \src "libresoc.v:165270.3-165271.43" + process $proc$libresoc.v:165270$9117 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9013 \alu_op__oe__oe$8$next + assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9013 + update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:157300.3-157301.51" - process $proc$libresoc.v:157300$9014 + attribute \src "libresoc.v:165272.3-165273.43" + process $proc$libresoc.v:165272$9118 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9015 \alu_op__oe__ok$9$next + assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9015 + update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:157302.3-157303.59" - process $proc$libresoc.v:157302$9016 + attribute \src "libresoc.v:165274.3-165275.43" + process $proc$libresoc.v:165274$9119 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9017 \alu_op__invert_in$10$next + assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9017 + update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:157304.3-157305.53" - process $proc$libresoc.v:157304$9018 + attribute \src "libresoc.v:165276.3-165277.49" + process $proc$libresoc.v:165276$9120 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9019 \alu_op__zero_a$11$next + assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9019 + update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:157306.3-157307.61" - process $proc$libresoc.v:157306$9020 + attribute \src "libresoc.v:165278.3-165279.49" + process $proc$libresoc.v:165278$9121 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9021 \alu_op__invert_out$12$next + assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9021 + update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:157308.3-157309.59" - process $proc$libresoc.v:157308$9022 + attribute \src "libresoc.v:165280.3-165281.53" + process $proc$libresoc.v:165280$9122 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9023 \alu_op__write_cr0$13$next + assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9023 + update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:157310.3-157311.63" - process $proc$libresoc.v:157310$9024 + attribute \src "libresoc.v:165282.3-165283.55" + process $proc$libresoc.v:165282$9123 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9025 \alu_op__input_carry$14$next + assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9025 + update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:157312.3-157313.65" - process $proc$libresoc.v:157312$9026 + attribute \src "libresoc.v:165284.3-165285.47" + process $proc$libresoc.v:165284$9124 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9027 \alu_op__output_carry$15$next + assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9027 + update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:157314.3-157315.57" - process $proc$libresoc.v:157314$9028 + attribute \src "libresoc.v:165286.3-165287.49" + process $proc$libresoc.v:165286$9125 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9029 \alu_op__is_32bit$16$next + assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9029 + update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:157316.3-157317.59" - process $proc$libresoc.v:157316$9030 + attribute \src "libresoc.v:165288.3-165289.47" + process $proc$libresoc.v:165288$9126 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9031 \alu_op__is_signed$17$next + assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9031 + update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:157318.3-157319.57" - process $proc$libresoc.v:157318$9032 + attribute \src "libresoc.v:165290.3-165291.49" + process $proc$libresoc.v:165290$9127 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9033 \alu_op__data_len$18$next + assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9033 + update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:157320.3-157321.49" - process $proc$libresoc.v:157320$9034 + attribute \src "libresoc.v:165292.3-165293.39" + process $proc$libresoc.v:165292$9128 assign { } { } - assign $0\alu_op__insn$19[31:0]$9035 \alu_op__insn$19$next + assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9035 + update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:157322.3-157323.33" - process $proc$libresoc.v:157322$9036 + attribute \src "libresoc.v:165294.3-165295.27" + process $proc$libresoc.v:165294$9129 assign { } { } - assign $0\muxid$1[1:0]$9037 \muxid$1$next + assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9037 + update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:157324.3-157325.29" - process $proc$libresoc.v:157324$9038 + attribute \src "libresoc.v:165296.3-165297.29" + process $proc$libresoc.v:165296$9130 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:157390.3-157407.6" - process $proc$libresoc.v:157390$9039 + attribute \src "libresoc.v:165400.3-165418.6" + process $proc$libresoc.v:165400$9131 + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9040 $2\r_busy$next[0:0]$9042 - attribute \src "libresoc.v:157391.5-157391.29" + assign { } { } + assign $0\xer_ca$next[1:0]$9133 $1\xer_ca$next[1:0]$9135 + assign $0\xer_ca_ok$next[0:0]$9132 $2\xer_ca_ok$next[0:0]$9136 + attribute \src "libresoc.v:165401.5-165401.29" switch \initial - attribute \src "libresoc.v:157391.9-157391.17" + attribute \src "libresoc.v:165401.9-165401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9041 1'1 + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9134 $1\xer_ca$next[1:0]$9135 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9041 1'0 + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9134 $1\xer_ca$next[1:0]$9135 } { \xer_ca_ok$95 \xer_ca$94 } case - assign $1\r_busy$next[0:0]$9041 \r_busy + assign $1\xer_ca_ok$next[0:0]$9134 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9135 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9042 1'0 + assign $2\xer_ca_ok$next[0:0]$9136 1'0 case - assign $2\r_busy$next[0:0]$9042 $1\r_busy$next[0:0]$9041 + assign $2\xer_ca_ok$next[0:0]$9136 $1\xer_ca_ok$next[0:0]$9134 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9040 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9132 + update \xer_ca$next $0\xer_ca$next[1:0]$9133 end - attribute \src "libresoc.v:157408.3-157420.6" - process $proc$libresoc.v:157408$9043 + attribute \src "libresoc.v:165419.3-165436.6" + process $proc$libresoc.v:165419$9137 + assign { } { } assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9044 $1\muxid$1$next[1:0]$9045 - attribute \src "libresoc.v:157409.5-157409.29" + assign $0\r_busy$next[0:0]$9138 $2\r_busy$next[0:0]$9140 + attribute \src "libresoc.v:165420.5-165420.29" switch \initial - attribute \src "libresoc.v:157409.9-157409.17" + attribute \src "libresoc.v:165420.9-165420.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9045 \muxid$62 + assign $1\r_busy$next[0:0]$9139 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9045 \muxid$62 + assign $1\r_busy$next[0:0]$9139 1'0 case - assign $1\muxid$1$next[1:0]$9045 \muxid$1 + assign $1\r_busy$next[0:0]$9139 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9140 1'0 + case + assign $2\r_busy$next[0:0]$9140 $1\r_busy$next[0:0]$9139 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9044 + update \r_busy$next $0\r_busy$next[0:0]$9138 end - attribute \src "libresoc.v:157421.3-157462.6" - process $proc$libresoc.v:157421$9046 + attribute \src "libresoc.v:165437.3-165449.6" + process $proc$libresoc.v:165437$9141 assign { } { } assign { } { } + assign $0\muxid$next[1:0]$9142 $1\muxid$next[1:0]$9143 + attribute \src "libresoc.v:165438.5-165438.29" + switch \initial + attribute \src "libresoc.v:165438.9-165438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9143 \muxid$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9143 \muxid$67 + case + assign $1\muxid$next[1:0]$9143 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9142 + end + attribute \src "libresoc.v:165450.3-165490.6" + process $proc$libresoc.v:165450$9144 assign { } { } assign { } { } assign { } { } @@ -326360,37 +342034,36 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$9047 $1\alu_op__data_len$18$next[3:0]$9065 - assign $0\alu_op__fn_unit$3$next[11:0]$9048 $1\alu_op__fn_unit$3$next[11:0]$9066 + assign $0\sr_op__fn_unit$next[13:0]$9145 $1\sr_op__fn_unit$next[13:0]$9162 assign { } { } assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$9051 $1\alu_op__input_carry$14$next[1:0]$9069 - assign $0\alu_op__insn$19$next[31:0]$9052 $1\alu_op__insn$19$next[31:0]$9070 - assign $0\alu_op__insn_type$2$next[6:0]$9053 $1\alu_op__insn_type$2$next[6:0]$9071 - assign $0\alu_op__invert_in$10$next[0:0]$9054 $1\alu_op__invert_in$10$next[0:0]$9072 - assign $0\alu_op__invert_out$12$next[0:0]$9055 $1\alu_op__invert_out$12$next[0:0]$9073 - assign $0\alu_op__is_32bit$16$next[0:0]$9056 $1\alu_op__is_32bit$16$next[0:0]$9074 - assign $0\alu_op__is_signed$17$next[0:0]$9057 $1\alu_op__is_signed$17$next[0:0]$9075 + assign $0\sr_op__input_carry$next[1:0]$9148 $1\sr_op__input_carry$next[1:0]$9165 + assign $0\sr_op__input_cr$next[0:0]$9149 $1\sr_op__input_cr$next[0:0]$9166 + assign $0\sr_op__insn$next[31:0]$9150 $1\sr_op__insn$next[31:0]$9167 + assign $0\sr_op__insn_type$next[6:0]$9151 $1\sr_op__insn_type$next[6:0]$9168 + assign $0\sr_op__invert_in$next[0:0]$9152 $1\sr_op__invert_in$next[0:0]$9169 + assign $0\sr_op__is_32bit$next[0:0]$9153 $1\sr_op__is_32bit$next[0:0]$9170 + assign $0\sr_op__is_signed$next[0:0]$9154 $1\sr_op__is_signed$next[0:0]$9171 assign { } { } assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$9060 $1\alu_op__output_carry$15$next[0:0]$9078 + assign $0\sr_op__output_carry$next[0:0]$9157 $1\sr_op__output_carry$next[0:0]$9174 + assign $0\sr_op__output_cr$next[0:0]$9158 $1\sr_op__output_cr$next[0:0]$9175 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$9063 $1\alu_op__write_cr0$13$next[0:0]$9081 - assign $0\alu_op__zero_a$11$next[0:0]$9064 $1\alu_op__zero_a$11$next[0:0]$9082 - assign $0\alu_op__imm_data__data$4$next[63:0]$9049 $2\alu_op__imm_data__data$4$next[63:0]$9083 - assign $0\alu_op__imm_data__ok$5$next[0:0]$9050 $2\alu_op__imm_data__ok$5$next[0:0]$9084 - assign $0\alu_op__oe__oe$8$next[0:0]$9058 $2\alu_op__oe__oe$8$next[0:0]$9085 - assign $0\alu_op__oe__ok$9$next[0:0]$9059 $2\alu_op__oe__ok$9$next[0:0]$9086 - assign $0\alu_op__rc__ok$7$next[0:0]$9061 $2\alu_op__rc__ok$7$next[0:0]$9087 - assign $0\alu_op__rc__rc$6$next[0:0]$9062 $2\alu_op__rc__rc$6$next[0:0]$9088 - attribute \src "libresoc.v:157422.5-157422.29" + assign $0\sr_op__write_cr0$next[0:0]$9161 $1\sr_op__write_cr0$next[0:0]$9178 + assign $0\sr_op__imm_data__data$next[63:0]$9146 $2\sr_op__imm_data__data$next[63:0]$9179 + assign $0\sr_op__imm_data__ok$next[0:0]$9147 $2\sr_op__imm_data__ok$next[0:0]$9180 + assign $0\sr_op__oe__oe$next[0:0]$9155 $2\sr_op__oe__oe$next[0:0]$9181 + assign $0\sr_op__oe__ok$next[0:0]$9156 $2\sr_op__oe__ok$next[0:0]$9182 + assign $0\sr_op__rc__ok$next[0:0]$9159 $2\sr_op__rc__ok$next[0:0]$9183 + assign $0\sr_op__rc__rc$next[0:0]$9160 $2\sr_op__rc__rc$next[0:0]$9184 + attribute \src "libresoc.v:165451.5-165451.29" switch \initial - attribute \src "libresoc.v:157422.9-157422.17" + attribute \src "libresoc.v:165451.9-165451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -326411,8 +342084,7 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9070 $1\alu_op__data_len$18$next[3:0]$9065 $1\alu_op__is_signed$17$next[0:0]$9075 $1\alu_op__is_32bit$16$next[0:0]$9074 $1\alu_op__output_carry$15$next[0:0]$9078 $1\alu_op__input_carry$14$next[1:0]$9069 $1\alu_op__write_cr0$13$next[0:0]$9081 $1\alu_op__invert_out$12$next[0:0]$9073 $1\alu_op__zero_a$11$next[0:0]$9082 $1\alu_op__invert_in$10$next[0:0]$9072 $1\alu_op__oe__ok$9$next[0:0]$9077 $1\alu_op__oe__oe$8$next[0:0]$9076 $1\alu_op__rc__ok$7$next[0:0]$9079 $1\alu_op__rc__rc$6$next[0:0]$9080 $1\alu_op__imm_data__ok$5$next[0:0]$9068 $1\alu_op__imm_data__data$4$next[63:0]$9067 $1\alu_op__fn_unit$3$next[11:0]$9066 $1\alu_op__insn_type$2$next[6:0]$9071 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\sr_op__insn$next[31:0]$9167 $1\sr_op__is_signed$next[0:0]$9171 $1\sr_op__is_32bit$next[0:0]$9170 $1\sr_op__output_cr$next[0:0]$9175 $1\sr_op__input_cr$next[0:0]$9166 $1\sr_op__output_carry$next[0:0]$9174 $1\sr_op__input_carry$next[1:0]$9165 $1\sr_op__invert_in$next[0:0]$9169 $1\sr_op__write_cr0$next[0:0]$9178 $1\sr_op__oe__ok$next[0:0]$9173 $1\sr_op__oe__oe$next[0:0]$9172 $1\sr_op__rc__ok$next[0:0]$9176 $1\sr_op__rc__rc$next[0:0]$9177 $1\sr_op__imm_data__ok$next[0:0]$9164 $1\sr_op__imm_data__data$next[63:0]$9163 $1\sr_op__fn_unit$next[13:0]$9162 $1\sr_op__insn_type$next[6:0]$9168 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -326432,674 +342104,431 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9070 $1\alu_op__data_len$18$next[3:0]$9065 $1\alu_op__is_signed$17$next[0:0]$9075 $1\alu_op__is_32bit$16$next[0:0]$9074 $1\alu_op__output_carry$15$next[0:0]$9078 $1\alu_op__input_carry$14$next[1:0]$9069 $1\alu_op__write_cr0$13$next[0:0]$9081 $1\alu_op__invert_out$12$next[0:0]$9073 $1\alu_op__zero_a$11$next[0:0]$9082 $1\alu_op__invert_in$10$next[0:0]$9072 $1\alu_op__oe__ok$9$next[0:0]$9077 $1\alu_op__oe__oe$8$next[0:0]$9076 $1\alu_op__rc__ok$7$next[0:0]$9079 $1\alu_op__rc__rc$6$next[0:0]$9080 $1\alu_op__imm_data__ok$5$next[0:0]$9068 $1\alu_op__imm_data__data$4$next[63:0]$9067 $1\alu_op__fn_unit$3$next[11:0]$9066 $1\alu_op__insn_type$2$next[6:0]$9071 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } - case - assign $1\alu_op__data_len$18$next[3:0]$9065 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[11:0]$9066 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$9067 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$9068 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$9069 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$9070 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$9071 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$9072 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$9073 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$9074 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$9075 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$9076 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$9077 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$9078 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$9079 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$9080 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$9081 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$9082 \alu_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$9083 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9084 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$9088 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$9087 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$9085 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$9086 1'0 - case - assign $2\alu_op__imm_data__data$4$next[63:0]$9083 $1\alu_op__imm_data__data$4$next[63:0]$9067 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9084 $1\alu_op__imm_data__ok$5$next[0:0]$9068 - assign $2\alu_op__oe__oe$8$next[0:0]$9085 $1\alu_op__oe__oe$8$next[0:0]$9076 - assign $2\alu_op__oe__ok$9$next[0:0]$9086 $1\alu_op__oe__ok$9$next[0:0]$9077 - assign $2\alu_op__rc__ok$7$next[0:0]$9087 $1\alu_op__rc__ok$7$next[0:0]$9079 - assign $2\alu_op__rc__rc$6$next[0:0]$9088 $1\alu_op__rc__rc$6$next[0:0]$9080 - end - sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9047 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[11:0]$9048 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9049 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9050 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9051 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9052 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9053 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9054 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9055 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9056 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9057 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9058 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9059 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9060 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9061 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9062 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9063 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9064 - end - attribute \src "libresoc.v:157463.3-157481.6" - process $proc$libresoc.v:157463$9089 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$20$next[63:0]$9090 $1\o$20$next[63:0]$9092 - assign { } { } - assign $0\o_ok$21$next[0:0]$9091 $2\o_ok$21$next[0:0]$9094 - attribute \src "libresoc.v:157464.5-157464.29" - switch \initial - attribute \src "libresoc.v:157464.9-157464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$9093 $1\o$20$next[63:0]$9092 } { \o_ok$82 \o$81 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$9093 $1\o$20$next[63:0]$9092 } { \o_ok$82 \o$81 } + assign { $1\sr_op__insn$next[31:0]$9167 $1\sr_op__is_signed$next[0:0]$9171 $1\sr_op__is_32bit$next[0:0]$9170 $1\sr_op__output_cr$next[0:0]$9175 $1\sr_op__input_cr$next[0:0]$9166 $1\sr_op__output_carry$next[0:0]$9174 $1\sr_op__input_carry$next[1:0]$9165 $1\sr_op__invert_in$next[0:0]$9169 $1\sr_op__write_cr0$next[0:0]$9178 $1\sr_op__oe__ok$next[0:0]$9173 $1\sr_op__oe__oe$next[0:0]$9172 $1\sr_op__rc__ok$next[0:0]$9176 $1\sr_op__rc__rc$next[0:0]$9177 $1\sr_op__imm_data__ok$next[0:0]$9164 $1\sr_op__imm_data__data$next[63:0]$9163 $1\sr_op__fn_unit$next[13:0]$9162 $1\sr_op__insn_type$next[6:0]$9168 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case - assign $1\o$20$next[63:0]$9092 \o$20 - assign $1\o_ok$21$next[0:0]$9093 \o_ok$21 + assign $1\sr_op__fn_unit$next[13:0]$9162 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9163 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9164 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9165 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9166 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9167 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9168 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9169 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9170 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9171 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9172 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9173 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9174 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9175 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9176 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9177 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9178 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$9094 1'0 - case - assign $2\o_ok$21$next[0:0]$9094 $1\o_ok$21$next[0:0]$9093 - end - sync always - update \o$20$next $0\o$20$next[63:0]$9090 - update \o_ok$21$next $0\o_ok$21$next[0:0]$9091 - end - attribute \src "libresoc.v:157482.3-157500.6" - process $proc$libresoc.v:157482$9095 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$22$next[3:0]$9096 $1\cr_a$22$next[3:0]$9098 - assign { } { } - assign $0\cr_a_ok$23$next[0:0]$9097 $2\cr_a_ok$23$next[0:0]$9100 - attribute \src "libresoc.v:157483.5-157483.29" - switch \initial - attribute \src "libresoc.v:157483.9-157483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9099 $1\cr_a$22$next[3:0]$9098 } { \cr_a_ok$84 \cr_a$83 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9099 $1\cr_a$22$next[3:0]$9098 } { \cr_a_ok$84 \cr_a$83 } - case - assign $1\cr_a$22$next[3:0]$9098 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$9099 \cr_a_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$9100 1'0 + assign $2\sr_op__imm_data__data$next[63:0]$9179 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9180 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9184 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9183 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9181 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9182 1'0 case - assign $2\cr_a_ok$23$next[0:0]$9100 $1\cr_a_ok$23$next[0:0]$9099 + assign $2\sr_op__imm_data__data$next[63:0]$9179 $1\sr_op__imm_data__data$next[63:0]$9163 + assign $2\sr_op__imm_data__ok$next[0:0]$9180 $1\sr_op__imm_data__ok$next[0:0]$9164 + assign $2\sr_op__oe__oe$next[0:0]$9181 $1\sr_op__oe__oe$next[0:0]$9172 + assign $2\sr_op__oe__ok$next[0:0]$9182 $1\sr_op__oe__ok$next[0:0]$9173 + assign $2\sr_op__rc__ok$next[0:0]$9183 $1\sr_op__rc__ok$next[0:0]$9176 + assign $2\sr_op__rc__rc$next[0:0]$9184 $1\sr_op__rc__rc$next[0:0]$9177 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$9096 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9097 + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9145 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9146 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9147 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9148 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9149 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9150 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9151 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9152 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9153 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9154 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9155 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9156 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9157 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9158 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9159 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9160 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9161 end - attribute \src "libresoc.v:157501.3-157519.6" - process $proc$libresoc.v:157501$9101 + attribute \src "libresoc.v:165491.3-165509.6" + process $proc$libresoc.v:165491$9185 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$24$next[1:0]$9102 $1\xer_ca$24$next[1:0]$9104 + assign $0\o$next[63:0]$9186 $1\o$next[63:0]$9188 assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$9103 $2\xer_ca_ok$25$next[0:0]$9106 - attribute \src "libresoc.v:157502.5-157502.29" + assign $0\o_ok$next[0:0]$9187 $2\o_ok$next[0:0]$9190 + attribute \src "libresoc.v:165492.5-165492.29" switch \initial - attribute \src "libresoc.v:157502.9-157502.17" + attribute \src "libresoc.v:165492.9-165492.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9105 $1\xer_ca$24$next[1:0]$9104 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\o_ok$next[0:0]$9189 $1\o$next[63:0]$9188 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9105 $1\xer_ca$24$next[1:0]$9104 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\o_ok$next[0:0]$9189 $1\o$next[63:0]$9188 } { \o_ok$86 \o$85 } case - assign $1\xer_ca$24$next[1:0]$9104 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$9105 \xer_ca_ok$25 + assign $1\o$next[63:0]$9188 \o + assign $1\o_ok$next[0:0]$9189 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$9106 1'0 + assign $2\o_ok$next[0:0]$9190 1'0 case - assign $2\xer_ca_ok$25$next[0:0]$9106 $1\xer_ca_ok$25$next[0:0]$9105 + assign $2\o_ok$next[0:0]$9190 $1\o_ok$next[0:0]$9189 end sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9102 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9103 + update \o$next $0\o$next[63:0]$9186 + update \o_ok$next $0\o_ok$next[0:0]$9187 end - attribute \src "libresoc.v:157520.3-157538.6" - process $proc$libresoc.v:157520$9107 + attribute \src "libresoc.v:165510.3-165528.6" + process $proc$libresoc.v:165510$9191 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$26$next[1:0]$9108 $1\xer_ov$26$next[1:0]$9110 + assign $0\cr_a$next[3:0]$9192 $1\cr_a$next[3:0]$9194 assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$9109 $2\xer_ov_ok$27$next[0:0]$9112 - attribute \src "libresoc.v:157521.5-157521.29" + assign $0\cr_a_ok$next[0:0]$9193 $2\cr_a_ok$next[0:0]$9196 + attribute \src "libresoc.v:165511.5-165511.29" switch \initial - attribute \src "libresoc.v:157521.9-157521.17" + attribute \src "libresoc.v:165511.9-165511.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9111 $1\xer_ov$26$next[1:0]$9110 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\cr_a_ok$next[0:0]$9195 $1\cr_a$next[3:0]$9194 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9111 $1\xer_ov$26$next[1:0]$9110 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\cr_a_ok$next[0:0]$9195 $1\cr_a$next[3:0]$9194 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\xer_ov$26$next[1:0]$9110 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$9111 \xer_ov_ok$27 + assign $1\cr_a$next[3:0]$9194 \cr_a + assign $1\cr_a_ok$next[0:0]$9195 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$9112 1'0 + assign $2\cr_a_ok$next[0:0]$9196 1'0 case - assign $2\xer_ov_ok$27$next[0:0]$9112 $1\xer_ov_ok$27$next[0:0]$9111 + assign $2\cr_a_ok$next[0:0]$9196 $1\cr_a_ok$next[0:0]$9195 end sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9108 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9109 + update \cr_a$next $0\cr_a$next[3:0]$9192 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9193 end - attribute \src "libresoc.v:157539.3-157557.6" - process $proc$libresoc.v:157539$9113 + attribute \src "libresoc.v:165529.3-165547.6" + process $proc$libresoc.v:165529$9197 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$28$next[0:0]$9114 $1\xer_so$28$next[0:0]$9116 + assign $0\xer_so$next[0:0]$9198 $1\xer_so$next[0:0]$9200 assign { } { } - assign $0\xer_so_ok$29$next[0:0]$9115 $2\xer_so_ok$29$next[0:0]$9118 - attribute \src "libresoc.v:157540.5-157540.29" + assign $0\xer_so_ok$next[0:0]$9199 $2\xer_so_ok$next[0:0]$9202 + attribute \src "libresoc.v:165530.5-165530.29" switch \initial - attribute \src "libresoc.v:157540.9-157540.17" + attribute \src "libresoc.v:165530.9-165530.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9117 $1\xer_so$28$next[0:0]$9116 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$next[0:0]$9201 $1\xer_so$next[0:0]$9200 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9117 $1\xer_so$28$next[0:0]$9116 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$next[0:0]$9201 $1\xer_so$next[0:0]$9200 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$28$next[0:0]$9116 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$9117 \xer_so_ok$29 + assign $1\xer_so$next[0:0]$9200 \xer_so + assign $1\xer_so_ok$next[0:0]$9201 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$29$next[0:0]$9118 1'0 + assign $2\xer_so_ok$next[0:0]$9202 1'0 case - assign $2\xer_so_ok$29$next[0:0]$9118 $1\xer_so_ok$29$next[0:0]$9117 + assign $2\xer_so_ok$next[0:0]$9202 $1\xer_so_ok$next[0:0]$9201 end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$9114 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9115 + update \xer_so$next $0\xer_so$next[0:0]$9198 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9199 end - connect \$60 $and$libresoc.v:157265$8979_Y + connect \$65 $and$libresoc.v:165243$9103_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \xer_ca_ok$96 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } - connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } - connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } - connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } - connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } - connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } - connect \muxid$62 \output_muxid$30 - connect \p_valid_i_p_ready_o \$60 + connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } + connect \muxid$67 \main_muxid$44 + connect \p_valid_i_p_ready_o \$65 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$59 \p_valid_i - connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } - connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } - connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \output_muxid \muxid + connect \p_valid_i$64 \p_valid_i + connect \xer_ca$63 \input_xer_ca$43 + connect \main_xer_so \input_xer_so$42 + connect \main_rc \input_rc$41 + connect \main_rb \input_rb$40 + connect \main_ra \input_ra$39 + connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_ca \xer_ca$20 + connect \input_xer_so \xer_so$19 + connect \input_rc \rc + connect \input_rb \rb + connect \input_ra \ra + connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } + connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:157581.1-158635.10" +attribute \src "libresoc.v:165581.1-166429.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" -module \pipe2$115 - attribute \src "libresoc.v:158581.3-158599.6" - wire width 4 $0\cr_a$21$next[3:0]$9284 - attribute \src "libresoc.v:158387.3-158388.33" - wire width 4 $0\cr_a$21[3:0]$9185 - attribute \src "libresoc.v:157593.13-157593.29" - wire width 4 $0\cr_a$21[3:0]$9297 - attribute \src "libresoc.v:158581.3-158599.6" - wire $0\cr_a_ok$22$next[0:0]$9285 - attribute \src "libresoc.v:158389.3-158390.39" - wire $0\cr_a_ok$22[0:0]$9187 - attribute \src "libresoc.v:157602.7-157602.26" - wire $0\cr_a_ok$22[0:0]$9299 - attribute \src "libresoc.v:157582.7-157582.20" +module \pipe1$32 + attribute \src "libresoc.v:166386.3-166398.6" + wire width 64 $0\fast1$next[63:0]$9280 + attribute \src "libresoc.v:166242.3-166243.27" + wire width 64 $0\fast1[63:0] + attribute \src "libresoc.v:166399.3-166411.6" + wire width 64 $0\fast2$next[63:0]$9283 + attribute \src "libresoc.v:166240.3-166241.27" + wire width 64 $0\fast2[63:0] + attribute \src "libresoc.v:165582.7-165582.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158508.3-158520.6" - wire width 2 $0\muxid$1$next[1:0]$9234 - attribute \src "libresoc.v:158429.3-158430.33" - wire width 2 $0\muxid$1[1:0]$9227 - attribute \src "libresoc.v:157613.13-157613.29" - wire width 2 $0\muxid$1[1:0]$9301 - attribute \src "libresoc.v:158562.3-158580.6" - wire width 64 $0\o$19$next[63:0]$9278 - attribute \src "libresoc.v:158391.3-158392.27" - wire width 64 $0\o$19[63:0]$9189 - attribute \src "libresoc.v:157628.14-157628.43" - wire width 64 $0\o$19[63:0]$9303 - attribute \src "libresoc.v:158562.3-158580.6" - wire $0\o_ok$20$next[0:0]$9279 - attribute \src "libresoc.v:158393.3-158394.33" - wire $0\o_ok$20[0:0]$9191 - attribute \src "libresoc.v:157637.7-157637.23" - wire $0\o_ok$20[0:0]$9305 - attribute \src "libresoc.v:158490.3-158507.6" - wire $0\r_busy$next[0:0]$9230 - attribute \src "libresoc.v:158431.3-158432.29" + attribute \src "libresoc.v:166326.3-166338.6" + wire width 2 $0\muxid$next[1:0]$9252 + attribute \src "libresoc.v:166266.3-166267.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:166308.3-166325.6" + wire $0\r_busy$next[0:0]$9248 + attribute \src "libresoc.v:166268.3-166269.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:158521.3-158561.6" - wire width 12 $0\sr_op__fn_unit$3$next[11:0]$9237 - attribute \src "libresoc.v:158397.3-158398.51" - wire width 12 $0\sr_op__fn_unit$3[11:0]$9195 - attribute \src "libresoc.v:157960.14-157960.42" - wire width 12 $0\sr_op__fn_unit$3[11:0]$9308 - attribute \src "libresoc.v:158521.3-158561.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9238 - attribute \src "libresoc.v:158399.3-158400.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9197 - attribute \src "libresoc.v:157982.14-157982.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9310 - attribute \src "libresoc.v:158521.3-158561.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9239 - attribute \src "libresoc.v:158401.3-158402.61" - wire $0\sr_op__imm_data__ok$5[0:0]$9199 - attribute \src "libresoc.v:157991.7-157991.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9312 - attribute \src "libresoc.v:158521.3-158561.6" - wire width 2 $0\sr_op__input_carry$12$next[1:0]$9240 - attribute \src "libresoc.v:158415.3-158416.61" - wire width 2 $0\sr_op__input_carry$12[1:0]$9213 - attribute \src "libresoc.v:158008.13-158008.43" - wire width 2 $0\sr_op__input_carry$12[1:0]$9314 - attribute \src "libresoc.v:158521.3-158561.6" - wire $0\sr_op__input_cr$14$next[0:0]$9241 - attribute \src "libresoc.v:158419.3-158420.55" - wire $0\sr_op__input_cr$14[0:0]$9217 - attribute \src "libresoc.v:158021.7-158021.34" - wire $0\sr_op__input_cr$14[0:0]$9316 - attribute \src "libresoc.v:158521.3-158561.6" - wire width 32 $0\sr_op__insn$18$next[31:0]$9242 - attribute \src "libresoc.v:158427.3-158428.47" - wire width 32 $0\sr_op__insn$18[31:0]$9225 - attribute \src "libresoc.v:158030.14-158030.38" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 53 \cr_a_ok$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$74 - attribute \src "libresoc.v:157582.7-157582.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 32 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 31 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 30 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 50 \o$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 51 \o_ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$44 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_sr_op__fn_unit$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok$29 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \dummy_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \dummy_muxid$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr + wire width 64 \dummy_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr$38 + wire width 64 \dummy_trap_op__cia$20 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dummy_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dummy_trap_op__fn_unit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn + wire width 32 \dummy_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn$42 + wire width 32 \dummy_trap_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -327174,8 +342603,9 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type + wire width 7 \dummy_trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -327250,167 +342680,158 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__invert_in$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_32bit$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_signed$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__oe$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__ok$33 + wire width 7 \dummy_trap_op__insn_type$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_carry + wire \dummy_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_carry$37 + wire \dummy_trap_op__is_32bit$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_cr + wire width 8 \dummy_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_cr$39 + wire width 8 \dummy_trap_op__ldst_exc$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__ok + wire width 64 \dummy_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__ok$31 + wire width 64 \dummy_trap_op__msr$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__rc + wire width 13 \dummy_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__rc$30 + wire width 13 \dummy_trap_op__trapaddr$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__write_cr0 + wire width 8 \dummy_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 8 \dummy_trap_op__traptype$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \fast1$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast1$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \fast2$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast2$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast2$next + attribute \src "libresoc.v:165582.7-165582.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 19 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 18 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 34 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 35 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$57 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 43 \sr_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$12$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 15 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \sr_op__input_cr + wire width 64 output 9 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \sr_op__input_cr$14 + wire width 64 \trap_op__cia$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$14$next + wire width 64 input 25 \trap_op__cia$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$66 + wire width 64 \trap_op__cia$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 22 \trap_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 21 \sr_op__insn + wire width 32 output 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 49 \sr_op__insn$18 + wire width 32 \trap_op__insn$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$18$next + wire width 32 input 23 \trap_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$70 + wire width 32 \trap_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -327485,8 +342906,9 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \sr_op__insn_type + wire width 7 output 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -327560,11 +342982,10 @@ module \pipe2$115 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 33 \sr_op__insn_type$2 + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$2$next + wire width 7 input 21 \trap_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -327639,636 +343060,405 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \sr_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \sr_op__oe__ok$9 + wire width 7 \trap_op__insn_type$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$9$next + wire width 7 \trap_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__output_carry + wire output 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \sr_op__output_carry$13 + wire \trap_op__is_32bit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$13$next + wire input 26 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$65 + wire \trap_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \sr_op__output_cr + wire width 8 output 13 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \sr_op__output_cr$15 + wire width 8 input 29 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$15$next + wire width 8 \trap_op__ldst_exc$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$67 + wire width 8 \trap_op__ldst_exc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__rc__ok + wire width 64 output 8 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$59 + wire width 64 \trap_op__msr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__rc__ok$7 + wire width 64 input 24 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$7$next + wire width 64 \trap_op__msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__rc__rc + wire width 13 output 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$58 + wire width 13 \trap_op__trapaddr$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__rc__rc$6 + wire width 13 input 28 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$6$next + wire width 13 \trap_op__trapaddr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__write_cr0 + wire width 8 output 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \sr_op__write_cr0$10 + wire width 8 \trap_op__traptype$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$10$next + wire width 8 input 27 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 28 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 54 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 29 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \xer_ca_ok$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 27 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:158382$9179 + wire width 8 \trap_op__traptype$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:166239$9231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$50 + connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:158382$9179_Y + connect \Y $and$libresoc.v:166239$9231_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:158433.11-158436.4" - cell \n$117 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:166270.9-166299.4" + cell \dummy \dummy + connect \fast1 \dummy_fast1 + connect \fast1$13 \dummy_fast1$27 + connect \fast2 \dummy_fast2 + connect \fast2$14 \dummy_fast2$28 + connect \muxid \dummy_muxid + connect \muxid$1 \dummy_muxid$15 + connect \ra \dummy_ra + connect \ra$11 \dummy_ra$25 + connect \rb \dummy_rb + connect \rb$12 \dummy_rb$26 + connect \trap_op__cia \dummy_trap_op__cia + connect \trap_op__cia$6 \dummy_trap_op__cia$20 + connect \trap_op__fn_unit \dummy_trap_op__fn_unit + connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 + connect \trap_op__insn \dummy_trap_op__insn + connect \trap_op__insn$4 \dummy_trap_op__insn$18 + connect \trap_op__insn_type \dummy_trap_op__insn_type + connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 + connect \trap_op__is_32bit \dummy_trap_op__is_32bit + connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 + connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 + connect \trap_op__msr \dummy_trap_op__msr + connect \trap_op__msr$5 \dummy_trap_op__msr$19 + connect \trap_op__trapaddr \dummy_trap_op__trapaddr + connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 + connect \trap_op__traptype \dummy_trap_op__traptype + connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:158437.16-158485.4" - cell \output$118 \output - connect \cr_a \output_cr_a - connect \cr_a$21 \output_cr_a$45 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$25 - connect \o \output_o - connect \o$19 \output_o$43 - connect \o_ok \output_o_ok - connect \o_ok$20 \output_o_ok$44 - connect \sr_op__fn_unit \output_sr_op__fn_unit - connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 - connect \sr_op__imm_data__data \output_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 - connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 - connect \sr_op__input_carry \output_sr_op__input_carry - connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 - connect \sr_op__input_cr \output_sr_op__input_cr - connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 - connect \sr_op__insn \output_sr_op__insn - connect \sr_op__insn$18 \output_sr_op__insn$42 - connect \sr_op__insn_type \output_sr_op__insn_type - connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 - connect \sr_op__invert_in \output_sr_op__invert_in - connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 - connect \sr_op__is_32bit \output_sr_op__is_32bit - connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 - connect \sr_op__is_signed \output_sr_op__is_signed - connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 - connect \sr_op__oe__oe \output_sr_op__oe__oe - connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 - connect \sr_op__oe__ok \output_sr_op__oe__ok - connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 - connect \sr_op__output_carry \output_sr_op__output_carry - connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 - connect \sr_op__output_cr \output_sr_op__output_cr - connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 - connect \sr_op__rc__ok \output_sr_op__rc__ok - connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 - connect \sr_op__rc__rc \output_sr_op__rc__rc - connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 - connect \sr_op__write_cr0 \output_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 - connect \xer_ca \output_xer_ca - connect \xer_ca$22 \output_xer_ca$46 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_so \output_xer_so + attribute \src "libresoc.v:166300.10-166303.4" + cell \n$34 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:158486.11-158489.4" - cell \p$116 \p + attribute \src "libresoc.v:166304.10-166307.4" + cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:157582.7-157582.20" - process $proc$libresoc.v:157582$9295 + attribute \src "libresoc.v:165582.7-165582.20" + process $proc$libresoc.v:165582$9285 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157593.13-157593.29" - process $proc$libresoc.v:157593$9296 - assign { } { } - assign $0\cr_a$21[3:0]$9297 4'0000 - sync always - sync init - update \cr_a$21 $0\cr_a$21[3:0]$9297 - end - attribute \src "libresoc.v:157602.7-157602.26" - process $proc$libresoc.v:157602$9298 - assign { } { } - assign $0\cr_a_ok$22[0:0]$9299 1'0 - sync always - sync init - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9299 - end - attribute \src "libresoc.v:157613.13-157613.29" - process $proc$libresoc.v:157613$9300 + attribute \src "libresoc.v:165827.14-165827.42" + process $proc$libresoc.v:165827$9286 assign { } { } - assign $0\muxid$1[1:0]$9301 2'00 + assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9301 + update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:157628.14-157628.43" - process $proc$libresoc.v:157628$9302 + attribute \src "libresoc.v:165836.14-165836.42" + process $proc$libresoc.v:165836$9287 assign { } { } - assign $0\o$19[63:0]$9303 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$19 $0\o$19[63:0]$9303 + update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:157637.7-157637.23" - process $proc$libresoc.v:157637$9304 + attribute \src "libresoc.v:165845.13-165845.25" + process $proc$libresoc.v:165845$9288 assign { } { } - assign $0\o_ok$20[0:0]$9305 1'0 + assign $1\muxid[1:0] 2'00 sync always sync init - update \o_ok$20 $0\o_ok$20[0:0]$9305 + update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:157927.7-157927.20" - process $proc$libresoc.v:157927$9306 + attribute \src "libresoc.v:165867.7-165867.20" + process $proc$libresoc.v:165867$9289 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:157960.14-157960.42" - process $proc$libresoc.v:157960$9307 - assign { } { } - assign $0\sr_op__fn_unit$3[11:0]$9308 12'000000000000 - sync always - sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9308 - end - attribute \src "libresoc.v:157982.14-157982.62" - process $proc$libresoc.v:157982$9309 - assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9310 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9310 - end - attribute \src "libresoc.v:157991.7-157991.37" - process $proc$libresoc.v:157991$9311 - assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9312 1'0 - sync always - sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9312 - end - attribute \src "libresoc.v:158008.13-158008.43" - process $proc$libresoc.v:158008$9313 - assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9314 2'00 - sync always - sync init - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9314 - end - attribute \src "libresoc.v:158021.7-158021.34" - process $proc$libresoc.v:158021$9315 - assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9316 1'0 - sync always - sync init - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9316 - end - attribute \src "libresoc.v:158030.14-158030.38" - process $proc$libresoc.v:158030$9317 - assign { } { } - assign $0\sr_op__insn$18[31:0]$9318 0 - sync always - sync init - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9318 - end - attribute \src "libresoc.v:158187.13-158187.41" - process $proc$libresoc.v:158187$9319 - assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9320 7'0000000 - sync always - sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9320 - end - attribute \src "libresoc.v:158270.7-158270.35" - process $proc$libresoc.v:158270$9321 - assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9322 1'0 - sync always - sync init - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9322 - end - attribute \src "libresoc.v:158279.7-158279.34" - process $proc$libresoc.v:158279$9323 + attribute \src "libresoc.v:165872.14-165872.39" + process $proc$libresoc.v:165872$9290 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9324 1'0 + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9324 + update \ra $1\ra[63:0] end - attribute \src "libresoc.v:158288.7-158288.35" - process $proc$libresoc.v:158288$9325 + attribute \src "libresoc.v:165881.14-165881.39" + process $proc$libresoc.v:165881$9291 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9326 1'0 + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9326 + update \rb $1\rb[63:0] end - attribute \src "libresoc.v:158299.7-158299.31" - process $proc$libresoc.v:158299$9327 + attribute \src "libresoc.v:165890.14-165890.49" + process $proc$libresoc.v:165890$9292 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9328 1'0 + assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9328 + update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:158308.7-158308.31" - process $proc$libresoc.v:158308$9329 + attribute \src "libresoc.v:165914.14-165914.41" + process $proc$libresoc.v:165914$9293 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9330 1'0 + assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9330 + update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:158315.7-158315.38" - process $proc$libresoc.v:158315$9331 + attribute \src "libresoc.v:165953.14-165953.35" + process $proc$libresoc.v:165953$9294 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9332 1'0 + assign $1\trap_op__insn[31:0] 0 sync always sync init - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9332 + update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:158324.7-158324.35" - process $proc$libresoc.v:158324$9333 + attribute \src "libresoc.v:166037.13-166037.39" + process $proc$libresoc.v:166037$9295 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9334 1'0 + assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9334 + update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:158335.7-158335.31" - process $proc$libresoc.v:158335$9335 + attribute \src "libresoc.v:166196.7-166196.31" + process $proc$libresoc.v:166196$9296 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9336 1'0 + assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9336 + update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:158344.7-158344.31" - process $proc$libresoc.v:158344$9337 + attribute \src "libresoc.v:166205.13-166205.38" + process $proc$libresoc.v:166205$9297 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9338 1'0 + assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9338 + update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:158351.7-158351.35" - process $proc$libresoc.v:158351$9339 + attribute \src "libresoc.v:166214.14-166214.49" + process $proc$libresoc.v:166214$9298 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9340 1'0 + assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9340 + update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:158360.13-158360.31" - process $proc$libresoc.v:158360$9341 + attribute \src "libresoc.v:166223.14-166223.42" + process $proc$libresoc.v:166223$9299 assign { } { } - assign $0\xer_ca$23[1:0]$9342 2'00 + assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init - update \xer_ca$23 $0\xer_ca$23[1:0]$9342 + update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:158369.7-158369.28" - process $proc$libresoc.v:158369$9343 + attribute \src "libresoc.v:166232.13-166232.38" + process $proc$libresoc.v:166232$9300 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9344 1'0 + assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9344 - end - attribute \src "libresoc.v:158383.3-158384.37" - process $proc$libresoc.v:158383$9180 - assign { } { } - assign $0\xer_ca$23[1:0]$9181 \xer_ca$23$next - sync posedge \coresync_clk - update \xer_ca$23 $0\xer_ca$23[1:0]$9181 - end - attribute \src "libresoc.v:158385.3-158386.43" - process $proc$libresoc.v:158385$9182 - assign { } { } - assign $0\xer_ca_ok$24[0:0]$9183 \xer_ca_ok$24$next - sync posedge \coresync_clk - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9183 - end - attribute \src "libresoc.v:158387.3-158388.33" - process $proc$libresoc.v:158387$9184 - assign { } { } - assign $0\cr_a$21[3:0]$9185 \cr_a$21$next - sync posedge \coresync_clk - update \cr_a$21 $0\cr_a$21[3:0]$9185 - end - attribute \src "libresoc.v:158389.3-158390.39" - process $proc$libresoc.v:158389$9186 - assign { } { } - assign $0\cr_a_ok$22[0:0]$9187 \cr_a_ok$22$next - sync posedge \coresync_clk - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9187 - end - attribute \src "libresoc.v:158391.3-158392.27" - process $proc$libresoc.v:158391$9188 - assign { } { } - assign $0\o$19[63:0]$9189 \o$19$next - sync posedge \coresync_clk - update \o$19 $0\o$19[63:0]$9189 - end - attribute \src "libresoc.v:158393.3-158394.33" - process $proc$libresoc.v:158393$9190 - assign { } { } - assign $0\o_ok$20[0:0]$9191 \o_ok$20$next - sync posedge \coresync_clk - update \o_ok$20 $0\o_ok$20[0:0]$9191 - end - attribute \src "libresoc.v:158395.3-158396.55" - process $proc$libresoc.v:158395$9192 - assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9193 \sr_op__insn_type$2$next - sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9193 - end - attribute \src "libresoc.v:158397.3-158398.51" - process $proc$libresoc.v:158397$9194 - assign { } { } - assign $0\sr_op__fn_unit$3[11:0]$9195 \sr_op__fn_unit$3$next - sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9195 - end - attribute \src "libresoc.v:158399.3-158400.65" - process $proc$libresoc.v:158399$9196 - assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9197 \sr_op__imm_data__data$4$next - sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9197 - end - attribute \src "libresoc.v:158401.3-158402.61" - process $proc$libresoc.v:158401$9198 - assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9199 \sr_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9199 + update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:158403.3-158404.49" - process $proc$libresoc.v:158403$9200 + attribute \src "libresoc.v:166240.3-166241.27" + process $proc$libresoc.v:166240$9232 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9201 \sr_op__rc__rc$6$next + assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9201 + update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:158405.3-158406.49" - process $proc$libresoc.v:158405$9202 + attribute \src "libresoc.v:166242.3-166243.27" + process $proc$libresoc.v:166242$9233 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9203 \sr_op__rc__ok$7$next + assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9203 + update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:158407.3-158408.49" - process $proc$libresoc.v:158407$9204 + attribute \src "libresoc.v:166244.3-166245.21" + process $proc$libresoc.v:166244$9234 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9205 \sr_op__oe__oe$8$next + assign $0\rb[63:0] \rb$next sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9205 + update \rb $0\rb[63:0] end - attribute \src "libresoc.v:158409.3-158410.49" - process $proc$libresoc.v:158409$9206 + attribute \src "libresoc.v:166246.3-166247.21" + process $proc$libresoc.v:166246$9235 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9207 \sr_op__oe__ok$9$next + assign $0\ra[63:0] \ra$next sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9207 + update \ra $0\ra[63:0] end - attribute \src "libresoc.v:158411.3-158412.57" - process $proc$libresoc.v:158411$9208 + attribute \src "libresoc.v:166248.3-166249.53" + process $proc$libresoc.v:166248$9236 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9209 \sr_op__write_cr0$10$next + assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9209 + update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:158413.3-158414.57" - process $proc$libresoc.v:158413$9210 + attribute \src "libresoc.v:166250.3-166251.49" + process $proc$libresoc.v:166250$9237 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9211 \sr_op__invert_in$11$next + assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9211 + update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:158415.3-158416.61" - process $proc$libresoc.v:158415$9212 + attribute \src "libresoc.v:166252.3-166253.43" + process $proc$libresoc.v:166252$9238 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9213 \sr_op__input_carry$12$next + assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9213 + update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:158417.3-158418.63" - process $proc$libresoc.v:158417$9214 + attribute \src "libresoc.v:166254.3-166255.41" + process $proc$libresoc.v:166254$9239 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9215 \sr_op__output_carry$13$next + assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9215 + update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:158419.3-158420.55" - process $proc$libresoc.v:158419$9216 + attribute \src "libresoc.v:166256.3-166257.41" + process $proc$libresoc.v:166256$9240 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9217 \sr_op__input_cr$14$next + assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9217 + update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:158421.3-158422.57" - process $proc$libresoc.v:158421$9218 + attribute \src "libresoc.v:166258.3-166259.51" + process $proc$libresoc.v:166258$9241 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9219 \sr_op__output_cr$15$next + assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9219 + update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:158423.3-158424.55" - process $proc$libresoc.v:158423$9220 + attribute \src "libresoc.v:166260.3-166261.51" + process $proc$libresoc.v:166260$9242 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9221 \sr_op__is_32bit$16$next + assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9221 + update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:158425.3-158426.57" - process $proc$libresoc.v:158425$9222 + attribute \src "libresoc.v:166262.3-166263.51" + process $proc$libresoc.v:166262$9243 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9223 \sr_op__is_signed$17$next + assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9223 + update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:158427.3-158428.47" - process $proc$libresoc.v:158427$9224 + attribute \src "libresoc.v:166264.3-166265.51" + process $proc$libresoc.v:166264$9244 assign { } { } - assign $0\sr_op__insn$18[31:0]$9225 \sr_op__insn$18$next + assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9225 + update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:158429.3-158430.33" - process $proc$libresoc.v:158429$9226 + attribute \src "libresoc.v:166266.3-166267.27" + process $proc$libresoc.v:166266$9245 assign { } { } - assign $0\muxid$1[1:0]$9227 \muxid$1$next + assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9227 + update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:158431.3-158432.29" - process $proc$libresoc.v:158431$9228 + attribute \src "libresoc.v:166268.3-166269.29" + process $proc$libresoc.v:166268$9246 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:158490.3-158507.6" - process $proc$libresoc.v:158490$9229 + attribute \src "libresoc.v:166308.3-166325.6" + process $proc$libresoc.v:166308$9247 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9230 $2\r_busy$next[0:0]$9232 - attribute \src "libresoc.v:158491.5-158491.29" + assign $0\r_busy$next[0:0]$9248 $2\r_busy$next[0:0]$9250 + attribute \src "libresoc.v:166309.5-166309.29" switch \initial - attribute \src "libresoc.v:158491.9-158491.17" + attribute \src "libresoc.v:166309.9-166309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9231 1'1 + assign $1\r_busy$next[0:0]$9249 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9231 1'0 + assign $1\r_busy$next[0:0]$9249 1'0 case - assign $1\r_busy$next[0:0]$9231 \r_busy + assign $1\r_busy$next[0:0]$9249 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9232 1'0 + assign $2\r_busy$next[0:0]$9250 1'0 case - assign $2\r_busy$next[0:0]$9232 $1\r_busy$next[0:0]$9231 + assign $2\r_busy$next[0:0]$9250 $1\r_busy$next[0:0]$9249 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9230 + update \r_busy$next $0\r_busy$next[0:0]$9248 end - attribute \src "libresoc.v:158508.3-158520.6" - process $proc$libresoc.v:158508$9233 + attribute \src "libresoc.v:166326.3-166338.6" + process $proc$libresoc.v:166326$9251 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9234 $1\muxid$1$next[1:0]$9235 - attribute \src "libresoc.v:158509.5-158509.29" + assign $0\muxid$next[1:0]$9252 $1\muxid$next[1:0]$9253 + attribute \src "libresoc.v:166327.5-166327.29" switch \initial - attribute \src "libresoc.v:158509.9-158509.17" + attribute \src "libresoc.v:166327.9-166327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9235 \muxid$53 + assign $1\muxid$next[1:0]$9253 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9235 \muxid$53 + assign $1\muxid$next[1:0]$9253 \muxid$32 case - assign $1\muxid$1$next[1:0]$9235 \muxid$1 + assign $1\muxid$next[1:0]$9253 \muxid end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9234 + update \muxid$next $0\muxid$next[1:0]$9252 end - attribute \src "libresoc.v:158521.3-158561.6" - process $proc$libresoc.v:158521$9236 - assign { } { } + attribute \src "libresoc.v:166339.3-166359.6" + process $proc$libresoc.v:166339$9254 assign { } { } assign { } { } assign { } { } @@ -328287,51 +343477,22 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr_op__fn_unit$3$next[11:0]$9237 $1\sr_op__fn_unit$3$next[11:0]$9254 - assign { } { } - assign { } { } - assign $0\sr_op__input_carry$12$next[1:0]$9240 $1\sr_op__input_carry$12$next[1:0]$9257 - assign $0\sr_op__input_cr$14$next[0:0]$9241 $1\sr_op__input_cr$14$next[0:0]$9258 - assign $0\sr_op__insn$18$next[31:0]$9242 $1\sr_op__insn$18$next[31:0]$9259 - assign $0\sr_op__insn_type$2$next[6:0]$9243 $1\sr_op__insn_type$2$next[6:0]$9260 - assign $0\sr_op__invert_in$11$next[0:0]$9244 $1\sr_op__invert_in$11$next[0:0]$9261 - assign $0\sr_op__is_32bit$16$next[0:0]$9245 $1\sr_op__is_32bit$16$next[0:0]$9262 - assign $0\sr_op__is_signed$17$next[0:0]$9246 $1\sr_op__is_signed$17$next[0:0]$9263 - assign { } { } - assign { } { } - assign $0\sr_op__output_carry$13$next[0:0]$9249 $1\sr_op__output_carry$13$next[0:0]$9266 - assign $0\sr_op__output_cr$15$next[0:0]$9250 $1\sr_op__output_cr$15$next[0:0]$9267 - assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9253 $1\sr_op__write_cr0$10$next[0:0]$9270 - assign $0\sr_op__imm_data__data$4$next[63:0]$9238 $2\sr_op__imm_data__data$4$next[63:0]$9271 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9239 $2\sr_op__imm_data__ok$5$next[0:0]$9272 - assign $0\sr_op__oe__oe$8$next[0:0]$9247 $2\sr_op__oe__oe$8$next[0:0]$9273 - assign $0\sr_op__oe__ok$9$next[0:0]$9248 $2\sr_op__oe__ok$9$next[0:0]$9274 - assign $0\sr_op__rc__ok$7$next[0:0]$9251 $2\sr_op__rc__ok$7$next[0:0]$9275 - assign $0\sr_op__rc__rc$6$next[0:0]$9252 $2\sr_op__rc__rc$6$next[0:0]$9276 - attribute \src "libresoc.v:158522.5-158522.29" + assign $0\trap_op__cia$next[63:0]$9255 $1\trap_op__cia$next[63:0]$9264 + assign $0\trap_op__fn_unit$next[13:0]$9256 $1\trap_op__fn_unit$next[13:0]$9265 + assign $0\trap_op__insn$next[31:0]$9257 $1\trap_op__insn$next[31:0]$9266 + assign $0\trap_op__insn_type$next[6:0]$9258 $1\trap_op__insn_type$next[6:0]$9267 + assign $0\trap_op__is_32bit$next[0:0]$9259 $1\trap_op__is_32bit$next[0:0]$9268 + assign $0\trap_op__ldst_exc$next[7:0]$9260 $1\trap_op__ldst_exc$next[7:0]$9269 + assign $0\trap_op__msr$next[63:0]$9261 $1\trap_op__msr$next[63:0]$9270 + assign $0\trap_op__trapaddr$next[12:0]$9262 $1\trap_op__trapaddr$next[12:0]$9271 + assign $0\trap_op__traptype$next[7:0]$9263 $1\trap_op__traptype$next[7:0]$9272 + attribute \src "libresoc.v:166340.5-166340.29" switch \initial - attribute \src "libresoc.v:158522.9-158522.17" + attribute \src "libresoc.v:166340.9-166340.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -328344,15 +343505,7 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9259 $1\sr_op__is_signed$17$next[0:0]$9263 $1\sr_op__is_32bit$16$next[0:0]$9262 $1\sr_op__output_cr$15$next[0:0]$9267 $1\sr_op__input_cr$14$next[0:0]$9258 $1\sr_op__output_carry$13$next[0:0]$9266 $1\sr_op__input_carry$12$next[1:0]$9257 $1\sr_op__invert_in$11$next[0:0]$9261 $1\sr_op__write_cr0$10$next[0:0]$9270 $1\sr_op__oe__ok$9$next[0:0]$9265 $1\sr_op__oe__oe$8$next[0:0]$9264 $1\sr_op__rc__ok$7$next[0:0]$9268 $1\sr_op__rc__rc$6$next[0:0]$9269 $1\sr_op__imm_data__ok$5$next[0:0]$9256 $1\sr_op__imm_data__data$4$next[63:0]$9255 $1\sr_op__fn_unit$3$next[11:0]$9254 $1\sr_op__insn_type$2$next[6:0]$9260 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\trap_op__ldst_exc$next[7:0]$9269 $1\trap_op__trapaddr$next[12:0]$9271 $1\trap_op__traptype$next[7:0]$9272 $1\trap_op__is_32bit$next[0:0]$9268 $1\trap_op__cia$next[63:0]$9264 $1\trap_op__msr$next[63:0]$9270 $1\trap_op__insn$next[31:0]$9266 $1\trap_op__fn_unit$next[13:0]$9265 $1\trap_op__insn_type$next[6:0]$9267 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -328364,522 +343517,536 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9259 $1\sr_op__is_signed$17$next[0:0]$9263 $1\sr_op__is_32bit$16$next[0:0]$9262 $1\sr_op__output_cr$15$next[0:0]$9267 $1\sr_op__input_cr$14$next[0:0]$9258 $1\sr_op__output_carry$13$next[0:0]$9266 $1\sr_op__input_carry$12$next[1:0]$9257 $1\sr_op__invert_in$11$next[0:0]$9261 $1\sr_op__write_cr0$10$next[0:0]$9270 $1\sr_op__oe__ok$9$next[0:0]$9265 $1\sr_op__oe__oe$8$next[0:0]$9264 $1\sr_op__rc__ok$7$next[0:0]$9268 $1\sr_op__rc__rc$6$next[0:0]$9269 $1\sr_op__imm_data__ok$5$next[0:0]$9256 $1\sr_op__imm_data__data$4$next[63:0]$9255 $1\sr_op__fn_unit$3$next[11:0]$9254 $1\sr_op__insn_type$2$next[6:0]$9260 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\trap_op__ldst_exc$next[7:0]$9269 $1\trap_op__trapaddr$next[12:0]$9271 $1\trap_op__traptype$next[7:0]$9272 $1\trap_op__is_32bit$next[0:0]$9268 $1\trap_op__cia$next[63:0]$9264 $1\trap_op__msr$next[63:0]$9270 $1\trap_op__insn$next[31:0]$9266 $1\trap_op__fn_unit$next[13:0]$9265 $1\trap_op__insn_type$next[6:0]$9267 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case - assign $1\sr_op__fn_unit$3$next[11:0]$9254 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9255 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9256 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$12$next[1:0]$9257 \sr_op__input_carry$12 - assign $1\sr_op__input_cr$14$next[0:0]$9258 \sr_op__input_cr$14 - assign $1\sr_op__insn$18$next[31:0]$9259 \sr_op__insn$18 - assign $1\sr_op__insn_type$2$next[6:0]$9260 \sr_op__insn_type$2 - assign $1\sr_op__invert_in$11$next[0:0]$9261 \sr_op__invert_in$11 - assign $1\sr_op__is_32bit$16$next[0:0]$9262 \sr_op__is_32bit$16 - assign $1\sr_op__is_signed$17$next[0:0]$9263 \sr_op__is_signed$17 - assign $1\sr_op__oe__oe$8$next[0:0]$9264 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9265 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$13$next[0:0]$9266 \sr_op__output_carry$13 - assign $1\sr_op__output_cr$15$next[0:0]$9267 \sr_op__output_cr$15 - assign $1\sr_op__rc__ok$7$next[0:0]$9268 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9269 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9270 \sr_op__write_cr0$10 + assign $1\trap_op__cia$next[63:0]$9264 \trap_op__cia + assign $1\trap_op__fn_unit$next[13:0]$9265 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9266 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9267 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9268 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9269 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9270 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9271 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9272 \trap_op__traptype end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9255 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9256 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9257 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9258 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9259 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9260 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9261 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9262 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9263 + end + attribute \src "libresoc.v:166360.3-166372.6" + process $proc$libresoc.v:166360$9273 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$9274 $1\ra$next[63:0]$9275 + attribute \src "libresoc.v:166361.5-166361.29" + switch \initial + attribute \src "libresoc.v:166361.9-166361.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } + assign $1\ra$next[63:0]$9275 \ra$42 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9271 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9272 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9276 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9275 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9273 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9274 1'0 + assign $1\ra$next[63:0]$9275 \ra$42 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9271 $1\sr_op__imm_data__data$4$next[63:0]$9255 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9272 $1\sr_op__imm_data__ok$5$next[0:0]$9256 - assign $2\sr_op__oe__oe$8$next[0:0]$9273 $1\sr_op__oe__oe$8$next[0:0]$9264 - assign $2\sr_op__oe__ok$9$next[0:0]$9274 $1\sr_op__oe__ok$9$next[0:0]$9265 - assign $2\sr_op__rc__ok$7$next[0:0]$9275 $1\sr_op__rc__ok$7$next[0:0]$9268 - assign $2\sr_op__rc__rc$6$next[0:0]$9276 $1\sr_op__rc__rc$6$next[0:0]$9269 + assign $1\ra$next[63:0]$9275 \ra end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[11:0]$9237 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9238 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9239 - update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9240 - update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9241 - update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9242 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9243 - update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9244 - update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9245 - update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9246 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9247 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9248 - update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9249 - update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9250 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9251 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9252 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9253 + update \ra$next $0\ra$next[63:0]$9274 end - attribute \src "libresoc.v:158562.3-158580.6" - process $proc$libresoc.v:158562$9277 + attribute \src "libresoc.v:166373.3-166385.6" + process $proc$libresoc.v:166373$9276 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\o$19$next[63:0]$9278 $1\o$19$next[63:0]$9280 - assign { } { } - assign $0\o_ok$20$next[0:0]$9279 $2\o_ok$20$next[0:0]$9282 - attribute \src "libresoc.v:158563.5-158563.29" + assign $0\rb$next[63:0]$9277 $1\rb$next[63:0]$9278 + attribute \src "libresoc.v:166374.5-166374.29" switch \initial - attribute \src "libresoc.v:158563.9-158563.17" + attribute \src "libresoc.v:166374.9-166374.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\o_ok$20$next[0:0]$9281 $1\o$19$next[63:0]$9280 } { \o_ok$72 \o$71 } + assign $1\rb$next[63:0]$9278 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\o_ok$20$next[0:0]$9281 $1\o$19$next[63:0]$9280 } { \o_ok$72 \o$71 } - case - assign $1\o$19$next[63:0]$9280 \o$19 - assign $1\o_ok$20$next[0:0]$9281 \o_ok$20 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$20$next[0:0]$9282 1'0 + assign $1\rb$next[63:0]$9278 \rb$43 case - assign $2\o_ok$20$next[0:0]$9282 $1\o_ok$20$next[0:0]$9281 + assign $1\rb$next[63:0]$9278 \rb end sync always - update \o$19$next $0\o$19$next[63:0]$9278 - update \o_ok$20$next $0\o_ok$20$next[0:0]$9279 + update \rb$next $0\rb$next[63:0]$9277 end - attribute \src "libresoc.v:158581.3-158599.6" - process $proc$libresoc.v:158581$9283 + attribute \src "libresoc.v:166386.3-166398.6" + process $proc$libresoc.v:166386$9279 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$21$next[3:0]$9284 $1\cr_a$21$next[3:0]$9286 - assign { } { } - assign $0\cr_a_ok$22$next[0:0]$9285 $2\cr_a_ok$22$next[0:0]$9288 - attribute \src "libresoc.v:158582.5-158582.29" + assign $0\fast1$next[63:0]$9280 $1\fast1$next[63:0]$9281 + attribute \src "libresoc.v:166387.5-166387.29" switch \initial - attribute \src "libresoc.v:158582.9-158582.17" + attribute \src "libresoc.v:166387.9-166387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9287 $1\cr_a$21$next[3:0]$9286 } { \cr_a_ok$74 \cr_a$73 } + assign $1\fast1$next[63:0]$9281 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9287 $1\cr_a$21$next[3:0]$9286 } { \cr_a_ok$74 \cr_a$73 } - case - assign $1\cr_a$21$next[3:0]$9286 \cr_a$21 - assign $1\cr_a_ok$22$next[0:0]$9287 \cr_a_ok$22 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$22$next[0:0]$9288 1'0 + assign $1\fast1$next[63:0]$9281 \fast1$44 case - assign $2\cr_a_ok$22$next[0:0]$9288 $1\cr_a_ok$22$next[0:0]$9287 + assign $1\fast1$next[63:0]$9281 \fast1 end sync always - update \cr_a$21$next $0\cr_a$21$next[3:0]$9284 - update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9285 + update \fast1$next $0\fast1$next[63:0]$9280 end - attribute \src "libresoc.v:158600.3-158618.6" - process $proc$libresoc.v:158600$9289 + attribute \src "libresoc.v:166399.3-166411.6" + process $proc$libresoc.v:166399$9282 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$23$next[1:0]$9290 $1\xer_ca$23$next[1:0]$9292 - assign { } { } - assign $0\xer_ca_ok$24$next[0:0]$9291 $2\xer_ca_ok$24$next[0:0]$9294 - attribute \src "libresoc.v:158601.5-158601.29" + assign $0\fast2$next[63:0]$9283 $1\fast2$next[63:0]$9284 + attribute \src "libresoc.v:166400.5-166400.29" switch \initial - attribute \src "libresoc.v:158601.9-158601.17" + attribute \src "libresoc.v:166400.9-166400.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9293 $1\xer_ca$23$next[1:0]$9292 } { \xer_ca_ok$76 \xer_ca$75 } + assign $1\fast2$next[63:0]$9284 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9293 $1\xer_ca$23$next[1:0]$9292 } { \xer_ca_ok$76 \xer_ca$75 } - case - assign $1\xer_ca$23$next[1:0]$9292 \xer_ca$23 - assign $1\xer_ca_ok$24$next[0:0]$9293 \xer_ca_ok$24 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$24$next[0:0]$9294 1'0 + assign $1\fast2$next[63:0]$9284 \fast2$45 case - assign $2\xer_ca_ok$24$next[0:0]$9294 $1\xer_ca_ok$24$next[0:0]$9293 + assign $1\fast2$next[63:0]$9284 \fast2 end sync always - update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9290 - update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9291 + update \fast2$next $0\fast2$next[63:0]$9283 end - connect \$51 $and$libresoc.v:158382$9179_Y + connect \$30 $and$libresoc.v:166239$9231_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } - connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } - connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } - connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } - connect \muxid$53 \output_muxid$25 - connect \p_valid_i_p_ready_o \$51 + connect \fast2$45 \dummy_fast2$28 + connect \fast1$44 \dummy_fast1$27 + connect \rb$43 \dummy_rb$26 + connect \ra$42 \dummy_ra$25 + connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } + connect \muxid$32 \dummy_muxid$15 + connect \p_valid_i_p_ready_o \$30 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$50 \p_valid_i - connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } - connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \output_muxid \muxid + connect \p_valid_i$29 \p_valid_i + connect \dummy_fast2 \fast2$14 + connect \dummy_fast1 \fast1$13 + connect \dummy_rb \rb$12 + connect \dummy_ra \ra$11 + connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } + connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:158639.1-159588.10" +attribute \src "libresoc.v:166433.1-167618.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" -module \pipe2$35 - attribute \src "libresoc.v:159494.3-159512.6" - wire width 64 $0\fast1$11$next[63:0]$9413 - attribute \src "libresoc.v:159349.3-159350.35" - wire width 64 $0\fast1$11[63:0]$9354 - attribute \src "libresoc.v:158651.14-158651.47" - wire width 64 $0\fast1$11[63:0]$9437 - attribute \src "libresoc.v:159494.3-159512.6" - wire $0\fast1_ok$next[0:0]$9412 - attribute \src "libresoc.v:159351.3-159352.33" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:159513.3-159531.6" - wire width 64 $0\fast2$12$next[63:0]$9419 - attribute \src "libresoc.v:159345.3-159346.35" - wire width 64 $0\fast2$12[63:0]$9351 - attribute \src "libresoc.v:158667.14-158667.47" - wire width 64 $0\fast2$12[63:0]$9440 - attribute \src "libresoc.v:159513.3-159531.6" - wire $0\fast2_ok$next[0:0]$9418 - attribute \src "libresoc.v:159347.3-159348.33" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:158640.7-158640.20" +module \pipe2 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9369 + attribute \src "libresoc.v:167359.3-167360.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9355 + attribute \src "libresoc.v:166441.13-166441.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9443 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9370 + attribute \src "libresoc.v:167329.3-167330.53" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9325 + attribute \src "libresoc.v:166480.14-166480.44" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9445 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9371 + attribute \src "libresoc.v:167331.3-167332.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9327 + attribute \src "libresoc.v:166504.14-166504.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9447 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9372 + attribute \src "libresoc.v:167333.3-167334.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9329 + attribute \src "libresoc.v:166513.7-166513.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9449 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9373 + attribute \src "libresoc.v:167351.3-167352.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9347 + attribute \src "libresoc.v:166530.13-166530.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9451 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9374 + attribute \src "libresoc.v:167361.3-167362.49" + wire width 32 $0\alu_op__insn$19[31:0]$9357 + attribute \src "libresoc.v:166543.14-166543.39" + wire width 32 $0\alu_op__insn$19[31:0]$9453 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9375 + attribute \src "libresoc.v:167327.3-167328.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9323 + attribute \src "libresoc.v:166702.13-166702.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9455 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__invert_in$10$next[0:0]$9376 + attribute \src "libresoc.v:167343.3-167344.59" + wire $0\alu_op__invert_in$10[0:0]$9339 + attribute \src "libresoc.v:166786.7-166786.36" + wire $0\alu_op__invert_in$10[0:0]$9457 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__invert_out$12$next[0:0]$9377 + attribute \src "libresoc.v:167347.3-167348.61" + wire $0\alu_op__invert_out$12[0:0]$9343 + attribute \src "libresoc.v:166795.7-166795.37" + wire $0\alu_op__invert_out$12[0:0]$9459 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9378 + attribute \src "libresoc.v:167355.3-167356.57" + wire $0\alu_op__is_32bit$16[0:0]$9351 + attribute \src "libresoc.v:166804.7-166804.35" + wire $0\alu_op__is_32bit$16[0:0]$9461 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__is_signed$17$next[0:0]$9379 + attribute \src "libresoc.v:167357.3-167358.59" + wire $0\alu_op__is_signed$17[0:0]$9353 + attribute \src "libresoc.v:166813.7-166813.36" + wire $0\alu_op__is_signed$17[0:0]$9463 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9380 + attribute \src "libresoc.v:167339.3-167340.51" + wire $0\alu_op__oe__oe$8[0:0]$9335 + attribute \src "libresoc.v:166824.7-166824.32" + wire $0\alu_op__oe__oe$8[0:0]$9465 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9381 + attribute \src "libresoc.v:167341.3-167342.51" + wire $0\alu_op__oe__ok$9[0:0]$9337 + attribute \src "libresoc.v:166833.7-166833.32" + wire $0\alu_op__oe__ok$9[0:0]$9467 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__output_carry$15$next[0:0]$9382 + attribute \src "libresoc.v:167353.3-167354.65" + wire $0\alu_op__output_carry$15[0:0]$9349 + attribute \src "libresoc.v:166840.7-166840.39" + wire $0\alu_op__output_carry$15[0:0]$9469 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9383 + attribute \src "libresoc.v:167337.3-167338.51" + wire $0\alu_op__rc__ok$7[0:0]$9333 + attribute \src "libresoc.v:166851.7-166851.32" + wire $0\alu_op__rc__ok$7[0:0]$9471 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9384 + attribute \src "libresoc.v:167335.3-167336.51" + wire $0\alu_op__rc__rc$6[0:0]$9331 + attribute \src "libresoc.v:166858.7-166858.32" + wire $0\alu_op__rc__rc$6[0:0]$9473 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9385 + attribute \src "libresoc.v:167349.3-167350.59" + wire $0\alu_op__write_cr0$13[0:0]$9345 + attribute \src "libresoc.v:166867.7-166867.36" + wire $0\alu_op__write_cr0$13[0:0]$9475 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__zero_a$11$next[0:0]$9386 + attribute \src "libresoc.v:167345.3-167346.53" + wire $0\alu_op__zero_a$11[0:0]$9341 + attribute \src "libresoc.v:166876.7-166876.33" + wire $0\alu_op__zero_a$11[0:0]$9477 + attribute \src "libresoc.v:167523.3-167541.6" + wire width 4 $0\cr_a$22$next[3:0]$9418 + attribute \src "libresoc.v:167319.3-167320.33" + wire width 4 $0\cr_a$22[3:0]$9315 + attribute \src "libresoc.v:166889.13-166889.29" + wire width 4 $0\cr_a$22[3:0]$9479 + attribute \src "libresoc.v:167523.3-167541.6" + wire $0\cr_a_ok$23$next[0:0]$9419 + attribute \src "libresoc.v:167321.3-167322.39" + wire $0\cr_a_ok$23[0:0]$9317 + attribute \src "libresoc.v:166898.7-166898.26" + wire $0\cr_a_ok$23[0:0]$9481 + attribute \src "libresoc.v:166434.7-166434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159551.3-159569.6" - wire width 64 $0\msr$next[63:0]$9430 - attribute \src "libresoc.v:159337.3-159338.23" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:159551.3-159569.6" - wire $0\msr_ok$next[0:0]$9431 - attribute \src "libresoc.v:159339.3-159340.29" - wire $0\msr_ok[0:0] - attribute \src "libresoc.v:159441.3-159453.6" - wire width 2 $0\muxid$1$next[1:0]$9384 - attribute \src "libresoc.v:159375.3-159376.33" - wire width 2 $0\muxid$1[1:0]$9377 - attribute \src "libresoc.v:158939.13-158939.29" - wire width 2 $0\muxid$1[1:0]$9445 - attribute \src "libresoc.v:159532.3-159550.6" - wire width 64 $0\nia$next[63:0]$9424 - attribute \src "libresoc.v:159341.3-159342.23" - wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:159532.3-159550.6" - wire $0\nia_ok$next[0:0]$9425 - attribute \src "libresoc.v:159343.3-159344.29" - wire $0\nia_ok[0:0] - attribute \src "libresoc.v:159475.3-159493.6" - wire width 64 $0\o$next[63:0]$9406 - attribute \src "libresoc.v:159353.3-159354.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:159475.3-159493.6" - wire $0\o_ok$next[0:0]$9407 - attribute \src "libresoc.v:159355.3-159356.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:159423.3-159440.6" - wire $0\r_busy$next[0:0]$9380 - attribute \src "libresoc.v:159377.3-159378.29" + attribute \src "libresoc.v:167449.3-167461.6" + wire width 2 $0\muxid$1$next[1:0]$9366 + attribute \src "libresoc.v:167363.3-167364.33" + wire width 2 $0\muxid$1[1:0]$9359 + attribute \src "libresoc.v:166909.13-166909.29" + wire width 2 $0\muxid$1[1:0]$9483 + attribute \src "libresoc.v:167504.3-167522.6" + wire width 64 $0\o$20$next[63:0]$9412 + attribute \src "libresoc.v:167323.3-167324.27" + wire width 64 $0\o$20[63:0]$9319 + attribute \src "libresoc.v:166924.14-166924.43" + wire width 64 $0\o$20[63:0]$9485 + attribute \src "libresoc.v:167504.3-167522.6" + wire $0\o_ok$21$next[0:0]$9413 + attribute \src "libresoc.v:167325.3-167326.33" + wire $0\o_ok$21[0:0]$9321 + attribute \src "libresoc.v:166933.7-166933.23" + wire $0\o_ok$21[0:0]$9487 + attribute \src "libresoc.v:167431.3-167448.6" + wire $0\r_busy$next[0:0]$9362 + attribute \src "libresoc.v:167365.3-167366.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:159454.3-159474.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$9387 - attribute \src "libresoc.v:159365.3-159366.47" - wire width 64 $0\trap_op__cia$6[63:0]$9367 - attribute \src "libresoc.v:159000.14-159000.53" - wire width 64 $0\trap_op__cia$6[63:0]$9452 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 12 $0\trap_op__fn_unit$3$next[11:0]$9388 - attribute \src "libresoc.v:159359.3-159360.55" - wire width 12 $0\trap_op__fn_unit$3[11:0]$9361 - attribute \src "libresoc.v:159033.14-159033.44" - wire width 12 $0\trap_op__fn_unit$3[11:0]$9454 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 32 $0\trap_op__insn$4$next[31:0]$9389 - attribute \src "libresoc.v:159361.3-159362.49" - wire width 32 $0\trap_op__insn$4[31:0]$9363 - attribute \src "libresoc.v:159057.14-159057.39" - wire width 32 $0\trap_op__insn$4[31:0]$9456 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 7 $0\trap_op__insn_type$2$next[6:0]$9390 - attribute \src "libresoc.v:159357.3-159358.59" - wire width 7 $0\trap_op__insn_type$2[6:0]$9359 - attribute \src "libresoc.v:159212.13-159212.43" - wire width 7 $0\trap_op__insn_type$2[6:0]$9458 - attribute \src "libresoc.v:159454.3-159474.6" - wire $0\trap_op__is_32bit$7$next[0:0]$9391 - attribute \src "libresoc.v:159367.3-159368.57" - wire $0\trap_op__is_32bit$7[0:0]$9369 - attribute \src "libresoc.v:159297.7-159297.35" - wire $0\trap_op__is_32bit$7[0:0]$9460 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9392 - attribute \src "libresoc.v:159373.3-159374.59" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9375 - attribute \src "libresoc.v:159304.13-159304.43" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9462 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 64 $0\trap_op__msr$5$next[63:0]$9393 - attribute \src "libresoc.v:159363.3-159364.47" - wire width 64 $0\trap_op__msr$5[63:0]$9365 - attribute \src "libresoc.v:159315.14-159315.53" - wire width 64 $0\trap_op__msr$5[63:0]$9464 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9394 - attribute \src "libresoc.v:159371.3-159372.57" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9373 - attribute \src "libresoc.v:159324.14-159324.46" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9466 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 8 $0\trap_op__traptype$8$next[7:0]$9395 - attribute \src "libresoc.v:159369.3-159370.57" - wire width 8 $0\trap_op__traptype$8[7:0]$9371 - attribute \src "libresoc.v:159333.13-159333.42" - wire width 8 $0\trap_op__traptype$8[7:0]$9468 - attribute \src "libresoc.v:159494.3-159512.6" - wire width 64 $1\fast1$11$next[63:0]$9415 - attribute \src "libresoc.v:159494.3-159512.6" - wire $1\fast1_ok$next[0:0]$9414 - attribute \src "libresoc.v:158658.7-158658.22" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:159513.3-159531.6" - wire width 64 $1\fast2$12$next[63:0]$9421 - attribute \src "libresoc.v:159513.3-159531.6" - wire $1\fast2_ok$next[0:0]$9420 - attribute \src "libresoc.v:158674.7-158674.22" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:159551.3-159569.6" - wire width 64 $1\msr$next[63:0]$9432 - attribute \src "libresoc.v:158923.14-158923.40" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:159551.3-159569.6" - wire $1\msr_ok$next[0:0]$9433 - attribute \src "libresoc.v:158930.7-158930.20" - wire $1\msr_ok[0:0] - attribute \src "libresoc.v:159441.3-159453.6" - wire width 2 $1\muxid$1$next[1:0]$9385 - attribute \src "libresoc.v:159532.3-159550.6" - wire width 64 $1\nia$next[63:0]$9426 - attribute \src "libresoc.v:158952.14-158952.40" - wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:159532.3-159550.6" - wire $1\nia_ok$next[0:0]$9427 - attribute \src "libresoc.v:158959.7-158959.20" - wire $1\nia_ok[0:0] - attribute \src "libresoc.v:159475.3-159493.6" - wire width 64 $1\o$next[63:0]$9408 - attribute \src "libresoc.v:158966.14-158966.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:159475.3-159493.6" - wire $1\o_ok$next[0:0]$9409 - attribute \src "libresoc.v:158973.7-158973.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:159423.3-159440.6" - wire $1\r_busy$next[0:0]$9381 - attribute \src "libresoc.v:158987.7-158987.20" + attribute \src "libresoc.v:167542.3-167560.6" + wire width 2 $0\xer_ca$24$next[1:0]$9424 + attribute \src "libresoc.v:167315.3-167316.37" + wire width 2 $0\xer_ca$24[1:0]$9311 + attribute \src "libresoc.v:167250.13-167250.31" + wire width 2 $0\xer_ca$24[1:0]$9490 + attribute \src "libresoc.v:167542.3-167560.6" + wire $0\xer_ca_ok$25$next[0:0]$9425 + attribute \src "libresoc.v:167317.3-167318.43" + wire $0\xer_ca_ok$25[0:0]$9313 + attribute \src "libresoc.v:167259.7-167259.28" + wire $0\xer_ca_ok$25[0:0]$9492 + attribute \src "libresoc.v:167561.3-167579.6" + wire width 2 $0\xer_ov$26$next[1:0]$9430 + attribute \src "libresoc.v:167311.3-167312.37" + wire width 2 $0\xer_ov$26[1:0]$9307 + attribute \src "libresoc.v:167270.13-167270.31" + wire width 2 $0\xer_ov$26[1:0]$9494 + attribute \src "libresoc.v:167561.3-167579.6" + wire $0\xer_ov_ok$27$next[0:0]$9431 + attribute \src "libresoc.v:167313.3-167314.43" + wire $0\xer_ov_ok$27[0:0]$9309 + attribute \src "libresoc.v:167279.7-167279.28" + wire $0\xer_ov_ok$27[0:0]$9496 + attribute \src "libresoc.v:167580.3-167598.6" + wire $0\xer_so$28$next[0:0]$9436 + attribute \src "libresoc.v:167307.3-167308.37" + wire $0\xer_so$28[0:0]$9303 + attribute \src "libresoc.v:167290.7-167290.25" + wire $0\xer_so$28[0:0]$9498 + attribute \src "libresoc.v:167580.3-167598.6" + wire $0\xer_so_ok$29$next[0:0]$9437 + attribute \src "libresoc.v:167309.3-167310.43" + wire $0\xer_so_ok$29[0:0]$9305 + attribute \src "libresoc.v:167299.7-167299.28" + wire $0\xer_so_ok$29[0:0]$9500 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9387 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9388 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9389 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9390 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9391 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9392 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9393 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__invert_in$10$next[0:0]$9394 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__invert_out$12$next[0:0]$9395 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9396 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__is_signed$17$next[0:0]$9397 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9398 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9399 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__output_carry$15$next[0:0]$9400 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9401 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9402 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9403 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__zero_a$11$next[0:0]$9404 + attribute \src "libresoc.v:167523.3-167541.6" + wire width 4 $1\cr_a$22$next[3:0]$9420 + attribute \src "libresoc.v:167523.3-167541.6" + wire $1\cr_a_ok$23$next[0:0]$9421 + attribute \src "libresoc.v:167449.3-167461.6" + wire width 2 $1\muxid$1$next[1:0]$9367 + attribute \src "libresoc.v:167504.3-167522.6" + wire width 64 $1\o$20$next[63:0]$9414 + attribute \src "libresoc.v:167504.3-167522.6" + wire $1\o_ok$21$next[0:0]$9415 + attribute \src "libresoc.v:167431.3-167448.6" + wire $1\r_busy$next[0:0]$9363 + attribute \src "libresoc.v:167243.7-167243.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:159454.3-159474.6" - wire width 64 $1\trap_op__cia$6$next[63:0]$9396 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 12 $1\trap_op__fn_unit$3$next[11:0]$9397 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 32 $1\trap_op__insn$4$next[31:0]$9398 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 7 $1\trap_op__insn_type$2$next[6:0]$9399 - attribute \src "libresoc.v:159454.3-159474.6" - wire $1\trap_op__is_32bit$7$next[0:0]$9400 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9401 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 64 $1\trap_op__msr$5$next[63:0]$9402 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9403 - attribute \src "libresoc.v:159454.3-159474.6" - wire width 8 $1\trap_op__traptype$8$next[7:0]$9404 - attribute \src "libresoc.v:159494.3-159512.6" - wire $2\fast1_ok$next[0:0]$9416 - attribute \src "libresoc.v:159513.3-159531.6" - wire $2\fast2_ok$next[0:0]$9422 - attribute \src "libresoc.v:159551.3-159569.6" - wire $2\msr_ok$next[0:0]$9434 - attribute \src "libresoc.v:159532.3-159550.6" - wire $2\nia_ok$next[0:0]$9428 - attribute \src "libresoc.v:159475.3-159493.6" - wire $2\o_ok$next[0:0]$9410 - attribute \src "libresoc.v:159423.3-159440.6" - wire $2\r_busy$next[0:0]$9382 - attribute \src "libresoc.v:159336.18-159336.118" - wire $and$libresoc.v:159336$9345_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 32 \fast1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 34 \fast2$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast2$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast2$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 35 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast2_ok$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast2_ok$next - attribute \src "libresoc.v:158640.7-158640.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_fast1$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_fast2$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb + attribute \src "libresoc.v:167542.3-167560.6" + wire width 2 $1\xer_ca$24$next[1:0]$9426 + attribute \src "libresoc.v:167542.3-167560.6" + wire $1\xer_ca_ok$25$next[0:0]$9427 + attribute \src "libresoc.v:167561.3-167579.6" + wire width 2 $1\xer_ov$26$next[1:0]$9432 + attribute \src "libresoc.v:167561.3-167579.6" + wire $1\xer_ov_ok$27$next[0:0]$9433 + attribute \src "libresoc.v:167580.3-167598.6" + wire $1\xer_so$28$next[0:0]$9438 + attribute \src "libresoc.v:167580.3-167598.6" + wire $1\xer_so_ok$29$next[0:0]$9439 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9405 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9406 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9407 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9408 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9409 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9410 + attribute \src "libresoc.v:167523.3-167541.6" + wire $2\cr_a_ok$23$next[0:0]$9422 + attribute \src "libresoc.v:167504.3-167522.6" + wire $2\o_ok$21$next[0:0]$9416 + attribute \src "libresoc.v:167431.3-167448.6" + wire $2\r_busy$next[0:0]$9364 + attribute \src "libresoc.v:167542.3-167560.6" + wire $2\xer_ca_ok$25$next[0:0]$9428 + attribute \src "libresoc.v:167561.3-167579.6" + wire $2\xer_ov_ok$27$next[0:0]$9434 + attribute \src "libresoc.v:167580.3-167598.6" + wire $2\xer_so_ok$29$next[0:0]$9440 + attribute \src "libresoc.v:167306.18-167306.118" + wire $and$libresoc.v:167306$9301_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia + wire width 4 input 21 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia$18 + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_trap_op__fn_unit$15 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn + wire width 64 input 7 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn$16 + wire width 64 output 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$66 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$14$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$80 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -328954,8 +344121,9 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__insn_type + wire width 7 input 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -329030,157 +344198,11 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__insn_type$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_trap_op__is_32bit$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \main_trap_op__ldst_exc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \main_trap_op__ldst_exc$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \main_trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \main_trap_op__traptype$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 38 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \msr$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 39 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \msr_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \msr_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 20 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 19 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 18 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 36 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 37 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \nia_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \nia_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 30 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 15 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \trap_op__cia$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$6$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \trap_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 22 \trap_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 23 \trap_op__insn$4 + wire width 7 output 36 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$4$next + wire width 7 \alu_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -329255,8 +344277,213 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \trap_op__insn_type + wire width 7 \alu_op__insn_type$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 64 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$84 + attribute \src "libresoc.v:166434.7-166434.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len$47 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_alu_op__fn_unit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn$48 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -329331,10 +344558,9 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 21 \trap_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$2$next + wire width 7 \output_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -329409,498 +344635,774 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$29 + wire width 7 \output_alu_op__insn_type$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \trap_op__is_32bit + wire \output_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$34 + wire \output_alu_op__invert_in$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \trap_op__is_32bit$7 + wire \output_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$7$next + wire \output_alu_op__invert_out$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 13 \trap_op__ldst_exc + wire \output_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 29 \trap_op__ldst_exc$10 + wire \output_alu_op__is_32bit$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$10$next + wire \output_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$37 + wire \output_alu_op__is_signed$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \trap_op__msr + wire \output_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$32 + wire \output_alu_op__oe__oe$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \trap_op__msr$5 + wire \output_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$5$next + wire \output_alu_op__oe__ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 12 \trap_op__trapaddr + wire \output_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$36 + wire \output_alu_op__output_carry$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 28 \trap_op__trapaddr$9 + wire \output_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$9$next + wire \output_alu_op__rc__ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 11 \trap_op__traptype + wire \output_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$35 + wire \output_alu_op__rc__rc$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 27 \trap_op__traptype$8 + wire \output_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$8$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:159336$9345 + wire \output_alu_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:167306$9301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$25 - connect \B \p_ready_o - connect \Y $and$libresoc.v:159336$9345_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:159379.13-159414.4" - cell \main$38 \main - connect \fast1 \main_fast1 - connect \fast1$11 \main_fast1$23 - connect \fast1_ok \main_fast1_ok - connect \fast2 \main_fast2 - connect \fast2$12 \main_fast2$24 - connect \fast2_ok \main_fast2_ok - connect \msr \main_msr - connect \msr_ok \main_msr_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$13 - connect \nia \main_nia - connect \nia_ok \main_nia_ok - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \trap_op__cia \main_trap_op__cia - connect \trap_op__cia$6 \main_trap_op__cia$18 - connect \trap_op__fn_unit \main_trap_op__fn_unit - connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 - connect \trap_op__insn \main_trap_op__insn - connect \trap_op__insn$4 \main_trap_op__insn$16 - connect \trap_op__insn_type \main_trap_op__insn_type - connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 - connect \trap_op__is_32bit \main_trap_op__is_32bit - connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 - connect \trap_op__ldst_exc \main_trap_op__ldst_exc - connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 - connect \trap_op__msr \main_trap_op__msr - connect \trap_op__msr$5 \main_trap_op__msr$17 - connect \trap_op__trapaddr \main_trap_op__trapaddr - connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 - connect \trap_op__traptype \main_trap_op__traptype - connect \trap_op__traptype$8 \main_trap_op__traptype$20 + connect \A \p_valid_i$59 + connect \B \p_ready_o + connect \Y $and$libresoc.v:167306$9301_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:159415.10-159418.4" - cell \n$37 \n + attribute \src "libresoc.v:167367.9-167370.4" + cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:159419.10-159422.4" - cell \p$36 \p + attribute \src "libresoc.v:167371.12-167426.4" + cell \output \output + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__insn \output_alu_op__insn + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__ok \output_alu_op__oe__ok + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__rc__ok \output_alu_op__rc__ok + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$30 + connect \o \output_o + connect \o$20 \output_o$49 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$50 + connect \xer_ca \output_xer_ca + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov \output_xer_ov + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:167427.9-167430.4" + cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:158640.7-158640.20" - process $proc$libresoc.v:158640$9435 + attribute \src "libresoc.v:166434.7-166434.20" + process $proc$libresoc.v:166434$9441 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158651.14-158651.47" - process $proc$libresoc.v:158651$9436 + attribute \src "libresoc.v:166441.13-166441.41" + process $proc$libresoc.v:166441$9442 assign { } { } - assign $0\fast1$11[63:0]$9437 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__data_len$18[3:0]$9443 4'0000 sync always sync init - update \fast1$11 $0\fast1$11[63:0]$9437 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9443 end - attribute \src "libresoc.v:158658.7-158658.22" - process $proc$libresoc.v:158658$9438 + attribute \src "libresoc.v:166480.14-166480.44" + process $proc$libresoc.v:166480$9444 assign { } { } - assign $1\fast1_ok[0:0] 1'0 + assign $0\alu_op__fn_unit$3[13:0]$9445 14'00000000000000 sync always sync init - update \fast1_ok $1\fast1_ok[0:0] + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9445 end - attribute \src "libresoc.v:158667.14-158667.47" - process $proc$libresoc.v:158667$9439 + attribute \src "libresoc.v:166504.14-166504.63" + process $proc$libresoc.v:166504$9446 assign { } { } - assign $0\fast2$12[63:0]$9440 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__imm_data__data$4[63:0]$9447 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$12 $0\fast2$12[63:0]$9440 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9447 end - attribute \src "libresoc.v:158674.7-158674.22" - process $proc$libresoc.v:158674$9441 + attribute \src "libresoc.v:166513.7-166513.38" + process $proc$libresoc.v:166513$9448 assign { } { } - assign $1\fast2_ok[0:0] 1'0 + assign $0\alu_op__imm_data__ok$5[0:0]$9449 1'0 sync always sync init - update \fast2_ok $1\fast2_ok[0:0] + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9449 end - attribute \src "libresoc.v:158923.14-158923.40" - process $proc$libresoc.v:158923$9442 + attribute \src "libresoc.v:166530.13-166530.44" + process $proc$libresoc.v:166530$9450 assign { } { } - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__input_carry$14[1:0]$9451 2'00 sync always sync init - update \msr $1\msr[63:0] + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9451 end - attribute \src "libresoc.v:158930.7-158930.20" - process $proc$libresoc.v:158930$9443 + attribute \src "libresoc.v:166543.14-166543.39" + process $proc$libresoc.v:166543$9452 assign { } { } - assign $1\msr_ok[0:0] 1'0 + assign $0\alu_op__insn$19[31:0]$9453 0 sync always sync init - update \msr_ok $1\msr_ok[0:0] + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9453 end - attribute \src "libresoc.v:158939.13-158939.29" - process $proc$libresoc.v:158939$9444 + attribute \src "libresoc.v:166702.13-166702.42" + process $proc$libresoc.v:166702$9454 assign { } { } - assign $0\muxid$1[1:0]$9445 2'00 + assign $0\alu_op__insn_type$2[6:0]$9455 7'0000000 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9445 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9455 end - attribute \src "libresoc.v:158952.14-158952.40" - process $proc$libresoc.v:158952$9446 + attribute \src "libresoc.v:166786.7-166786.36" + process $proc$libresoc.v:166786$9456 assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__invert_in$10[0:0]$9457 1'0 sync always sync init - update \nia $1\nia[63:0] + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9457 end - attribute \src "libresoc.v:158959.7-158959.20" - process $proc$libresoc.v:158959$9447 + attribute \src "libresoc.v:166795.7-166795.37" + process $proc$libresoc.v:166795$9458 assign { } { } - assign $1\nia_ok[0:0] 1'0 + assign $0\alu_op__invert_out$12[0:0]$9459 1'0 sync always sync init - update \nia_ok $1\nia_ok[0:0] + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9459 end - attribute \src "libresoc.v:158966.14-158966.38" - process $proc$libresoc.v:158966$9448 + attribute \src "libresoc.v:166804.7-166804.35" + process $proc$libresoc.v:166804$9460 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__is_32bit$16[0:0]$9461 1'0 sync always sync init - update \o $1\o[63:0] + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9461 end - attribute \src "libresoc.v:158973.7-158973.18" - process $proc$libresoc.v:158973$9449 + attribute \src "libresoc.v:166813.7-166813.36" + process $proc$libresoc.v:166813$9462 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $0\alu_op__is_signed$17[0:0]$9463 1'0 sync always sync init - update \o_ok $1\o_ok[0:0] + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9463 end - attribute \src "libresoc.v:158987.7-158987.20" - process $proc$libresoc.v:158987$9450 + attribute \src "libresoc.v:166824.7-166824.32" + process $proc$libresoc.v:166824$9464 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\alu_op__oe__oe$8[0:0]$9465 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9465 end - attribute \src "libresoc.v:159000.14-159000.53" - process $proc$libresoc.v:159000$9451 + attribute \src "libresoc.v:166833.7-166833.32" + process $proc$libresoc.v:166833$9466 assign { } { } - assign $0\trap_op__cia$6[63:0]$9452 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__oe__ok$9[0:0]$9467 1'0 sync always sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9452 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9467 end - attribute \src "libresoc.v:159033.14-159033.44" - process $proc$libresoc.v:159033$9453 + attribute \src "libresoc.v:166840.7-166840.39" + process $proc$libresoc.v:166840$9468 assign { } { } - assign $0\trap_op__fn_unit$3[11:0]$9454 12'000000000000 + assign $0\alu_op__output_carry$15[0:0]$9469 1'0 sync always sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$9454 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9469 end - attribute \src "libresoc.v:159057.14-159057.39" - process $proc$libresoc.v:159057$9455 + attribute \src "libresoc.v:166851.7-166851.32" + process $proc$libresoc.v:166851$9470 assign { } { } - assign $0\trap_op__insn$4[31:0]$9456 0 + assign $0\alu_op__rc__ok$7[0:0]$9471 1'0 sync always sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9456 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9471 end - attribute \src "libresoc.v:159212.13-159212.43" - process $proc$libresoc.v:159212$9457 + attribute \src "libresoc.v:166858.7-166858.32" + process $proc$libresoc.v:166858$9472 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9458 7'0000000 + assign $0\alu_op__rc__rc$6[0:0]$9473 1'0 sync always sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9458 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9473 end - attribute \src "libresoc.v:159297.7-159297.35" - process $proc$libresoc.v:159297$9459 + attribute \src "libresoc.v:166867.7-166867.36" + process $proc$libresoc.v:166867$9474 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9460 1'0 + assign $0\alu_op__write_cr0$13[0:0]$9475 1'0 sync always sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9460 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9475 end - attribute \src "libresoc.v:159304.13-159304.43" - process $proc$libresoc.v:159304$9461 + attribute \src "libresoc.v:166876.7-166876.33" + process $proc$libresoc.v:166876$9476 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9462 8'00000000 + assign $0\alu_op__zero_a$11[0:0]$9477 1'0 sync always sync init - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9462 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9477 end - attribute \src "libresoc.v:159315.14-159315.53" - process $proc$libresoc.v:159315$9463 + attribute \src "libresoc.v:166889.13-166889.29" + process $proc$libresoc.v:166889$9478 assign { } { } - assign $0\trap_op__msr$5[63:0]$9464 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\cr_a$22[3:0]$9479 4'0000 sync always sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9464 + update \cr_a$22 $0\cr_a$22[3:0]$9479 end - attribute \src "libresoc.v:159324.14-159324.46" - process $proc$libresoc.v:159324$9465 + attribute \src "libresoc.v:166898.7-166898.26" + process $proc$libresoc.v:166898$9480 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9466 13'0000000000000 + assign $0\cr_a_ok$23[0:0]$9481 1'0 sync always sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9466 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9481 end - attribute \src "libresoc.v:159333.13-159333.42" - process $proc$libresoc.v:159333$9467 + attribute \src "libresoc.v:166909.13-166909.29" + process $proc$libresoc.v:166909$9482 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9468 8'00000000 + assign $0\muxid$1[1:0]$9483 2'00 sync always sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9468 + update \muxid$1 $0\muxid$1[1:0]$9483 end - attribute \src "libresoc.v:159337.3-159338.23" - process $proc$libresoc.v:159337$9346 + attribute \src "libresoc.v:166924.14-166924.43" + process $proc$libresoc.v:166924$9484 assign { } { } - assign $0\msr[63:0] \msr$next + assign $0\o$20[63:0]$9485 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$9485 + end + attribute \src "libresoc.v:166933.7-166933.23" + process $proc$libresoc.v:166933$9486 + assign { } { } + assign $0\o_ok$21[0:0]$9487 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$9487 + end + attribute \src "libresoc.v:167243.7-167243.20" + process $proc$libresoc.v:167243$9488 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:167250.13-167250.31" + process $proc$libresoc.v:167250$9489 + assign { } { } + assign $0\xer_ca$24[1:0]$9490 2'00 + sync always + sync init + update \xer_ca$24 $0\xer_ca$24[1:0]$9490 + end + attribute \src "libresoc.v:167259.7-167259.28" + process $proc$libresoc.v:167259$9491 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$9492 1'0 + sync always + sync init + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9492 + end + attribute \src "libresoc.v:167270.13-167270.31" + process $proc$libresoc.v:167270$9493 + assign { } { } + assign $0\xer_ov$26[1:0]$9494 2'00 + sync always + sync init + update \xer_ov$26 $0\xer_ov$26[1:0]$9494 + end + attribute \src "libresoc.v:167279.7-167279.28" + process $proc$libresoc.v:167279$9495 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$9496 1'0 + sync always + sync init + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9496 + end + attribute \src "libresoc.v:167290.7-167290.25" + process $proc$libresoc.v:167290$9497 + assign { } { } + assign $0\xer_so$28[0:0]$9498 1'0 + sync always + sync init + update \xer_so$28 $0\xer_so$28[0:0]$9498 + end + attribute \src "libresoc.v:167299.7-167299.28" + process $proc$libresoc.v:167299$9499 + assign { } { } + assign $0\xer_so_ok$29[0:0]$9500 1'0 + sync always + sync init + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9500 + end + attribute \src "libresoc.v:167307.3-167308.37" + process $proc$libresoc.v:167307$9302 + assign { } { } + assign $0\xer_so$28[0:0]$9303 \xer_so$28$next sync posedge \coresync_clk - update \msr $0\msr[63:0] + update \xer_so$28 $0\xer_so$28[0:0]$9303 end - attribute \src "libresoc.v:159339.3-159340.29" - process $proc$libresoc.v:159339$9347 + attribute \src "libresoc.v:167309.3-167310.43" + process $proc$libresoc.v:167309$9304 assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next + assign $0\xer_so_ok$29[0:0]$9305 \xer_so_ok$29$next sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9305 end - attribute \src "libresoc.v:159341.3-159342.23" - process $proc$libresoc.v:159341$9348 + attribute \src "libresoc.v:167311.3-167312.37" + process $proc$libresoc.v:167311$9306 assign { } { } - assign $0\nia[63:0] \nia$next + assign $0\xer_ov$26[1:0]$9307 \xer_ov$26$next sync posedge \coresync_clk - update \nia $0\nia[63:0] + update \xer_ov$26 $0\xer_ov$26[1:0]$9307 end - attribute \src "libresoc.v:159343.3-159344.29" - process $proc$libresoc.v:159343$9349 + attribute \src "libresoc.v:167313.3-167314.43" + process $proc$libresoc.v:167313$9308 assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next + assign $0\xer_ov_ok$27[0:0]$9309 \xer_ov_ok$27$next sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9309 end - attribute \src "libresoc.v:159345.3-159346.35" - process $proc$libresoc.v:159345$9350 + attribute \src "libresoc.v:167315.3-167316.37" + process $proc$libresoc.v:167315$9310 assign { } { } - assign $0\fast2$12[63:0]$9351 \fast2$12$next + assign $0\xer_ca$24[1:0]$9311 \xer_ca$24$next sync posedge \coresync_clk - update \fast2$12 $0\fast2$12[63:0]$9351 + update \xer_ca$24 $0\xer_ca$24[1:0]$9311 end - attribute \src "libresoc.v:159347.3-159348.33" - process $proc$libresoc.v:159347$9352 + attribute \src "libresoc.v:167317.3-167318.43" + process $proc$libresoc.v:167317$9312 assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next + assign $0\xer_ca_ok$25[0:0]$9313 \xer_ca_ok$25$next sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9313 end - attribute \src "libresoc.v:159349.3-159350.35" - process $proc$libresoc.v:159349$9353 + attribute \src "libresoc.v:167319.3-167320.33" + process $proc$libresoc.v:167319$9314 assign { } { } - assign $0\fast1$11[63:0]$9354 \fast1$11$next + assign $0\cr_a$22[3:0]$9315 \cr_a$22$next sync posedge \coresync_clk - update \fast1$11 $0\fast1$11[63:0]$9354 + update \cr_a$22 $0\cr_a$22[3:0]$9315 end - attribute \src "libresoc.v:159351.3-159352.33" - process $proc$libresoc.v:159351$9355 + attribute \src "libresoc.v:167321.3-167322.39" + process $proc$libresoc.v:167321$9316 assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next + assign $0\cr_a_ok$23[0:0]$9317 \cr_a_ok$23$next sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9317 end - attribute \src "libresoc.v:159353.3-159354.19" - process $proc$libresoc.v:159353$9356 + attribute \src "libresoc.v:167323.3-167324.27" + process $proc$libresoc.v:167323$9318 assign { } { } - assign $0\o[63:0] \o$next + assign $0\o$20[63:0]$9319 \o$20$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \o$20 $0\o$20[63:0]$9319 end - attribute \src "libresoc.v:159355.3-159356.25" - process $proc$libresoc.v:159355$9357 + attribute \src "libresoc.v:167325.3-167326.33" + process $proc$libresoc.v:167325$9320 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\o_ok$21[0:0]$9321 \o_ok$21$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \o_ok$21 $0\o_ok$21[0:0]$9321 + end + attribute \src "libresoc.v:167327.3-167328.57" + process $proc$libresoc.v:167327$9322 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$9323 \alu_op__insn_type$2$next + sync posedge \coresync_clk + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9323 + end + attribute \src "libresoc.v:167329.3-167330.53" + process $proc$libresoc.v:167329$9324 + assign { } { } + assign $0\alu_op__fn_unit$3[13:0]$9325 \alu_op__fn_unit$3$next + sync posedge \coresync_clk + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9325 + end + attribute \src "libresoc.v:167331.3-167332.67" + process $proc$libresoc.v:167331$9326 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$9327 \alu_op__imm_data__data$4$next + sync posedge \coresync_clk + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9327 + end + attribute \src "libresoc.v:167333.3-167334.63" + process $proc$libresoc.v:167333$9328 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$9329 \alu_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9329 + end + attribute \src "libresoc.v:167335.3-167336.51" + process $proc$libresoc.v:167335$9330 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$9331 \alu_op__rc__rc$6$next + sync posedge \coresync_clk + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9331 + end + attribute \src "libresoc.v:167337.3-167338.51" + process $proc$libresoc.v:167337$9332 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$9333 \alu_op__rc__ok$7$next + sync posedge \coresync_clk + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9333 + end + attribute \src "libresoc.v:167339.3-167340.51" + process $proc$libresoc.v:167339$9334 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$9335 \alu_op__oe__oe$8$next + sync posedge \coresync_clk + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9335 + end + attribute \src "libresoc.v:167341.3-167342.51" + process $proc$libresoc.v:167341$9336 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$9337 \alu_op__oe__ok$9$next + sync posedge \coresync_clk + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9337 + end + attribute \src "libresoc.v:167343.3-167344.59" + process $proc$libresoc.v:167343$9338 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$9339 \alu_op__invert_in$10$next + sync posedge \coresync_clk + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9339 end - attribute \src "libresoc.v:159357.3-159358.59" - process $proc$libresoc.v:159357$9358 + attribute \src "libresoc.v:167345.3-167346.53" + process $proc$libresoc.v:167345$9340 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9359 \trap_op__insn_type$2$next + assign $0\alu_op__zero_a$11[0:0]$9341 \alu_op__zero_a$11$next sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9359 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9341 end - attribute \src "libresoc.v:159359.3-159360.55" - process $proc$libresoc.v:159359$9360 + attribute \src "libresoc.v:167347.3-167348.61" + process $proc$libresoc.v:167347$9342 assign { } { } - assign $0\trap_op__fn_unit$3[11:0]$9361 \trap_op__fn_unit$3$next + assign $0\alu_op__invert_out$12[0:0]$9343 \alu_op__invert_out$12$next sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$9361 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9343 end - attribute \src "libresoc.v:159361.3-159362.49" - process $proc$libresoc.v:159361$9362 + attribute \src "libresoc.v:167349.3-167350.59" + process $proc$libresoc.v:167349$9344 assign { } { } - assign $0\trap_op__insn$4[31:0]$9363 \trap_op__insn$4$next + assign $0\alu_op__write_cr0$13[0:0]$9345 \alu_op__write_cr0$13$next sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9363 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9345 end - attribute \src "libresoc.v:159363.3-159364.47" - process $proc$libresoc.v:159363$9364 + attribute \src "libresoc.v:167351.3-167352.63" + process $proc$libresoc.v:167351$9346 assign { } { } - assign $0\trap_op__msr$5[63:0]$9365 \trap_op__msr$5$next + assign $0\alu_op__input_carry$14[1:0]$9347 \alu_op__input_carry$14$next sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9365 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9347 end - attribute \src "libresoc.v:159365.3-159366.47" - process $proc$libresoc.v:159365$9366 + attribute \src "libresoc.v:167353.3-167354.65" + process $proc$libresoc.v:167353$9348 assign { } { } - assign $0\trap_op__cia$6[63:0]$9367 \trap_op__cia$6$next + assign $0\alu_op__output_carry$15[0:0]$9349 \alu_op__output_carry$15$next sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9367 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9349 end - attribute \src "libresoc.v:159367.3-159368.57" - process $proc$libresoc.v:159367$9368 + attribute \src "libresoc.v:167355.3-167356.57" + process $proc$libresoc.v:167355$9350 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9369 \trap_op__is_32bit$7$next + assign $0\alu_op__is_32bit$16[0:0]$9351 \alu_op__is_32bit$16$next sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9369 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9351 end - attribute \src "libresoc.v:159369.3-159370.57" - process $proc$libresoc.v:159369$9370 + attribute \src "libresoc.v:167357.3-167358.59" + process $proc$libresoc.v:167357$9352 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9371 \trap_op__traptype$8$next + assign $0\alu_op__is_signed$17[0:0]$9353 \alu_op__is_signed$17$next sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9371 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9353 end - attribute \src "libresoc.v:159371.3-159372.57" - process $proc$libresoc.v:159371$9372 + attribute \src "libresoc.v:167359.3-167360.57" + process $proc$libresoc.v:167359$9354 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9373 \trap_op__trapaddr$9$next + assign $0\alu_op__data_len$18[3:0]$9355 \alu_op__data_len$18$next sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9373 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9355 end - attribute \src "libresoc.v:159373.3-159374.59" - process $proc$libresoc.v:159373$9374 + attribute \src "libresoc.v:167361.3-167362.49" + process $proc$libresoc.v:167361$9356 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9375 \trap_op__ldst_exc$10$next + assign $0\alu_op__insn$19[31:0]$9357 \alu_op__insn$19$next sync posedge \coresync_clk - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9375 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9357 end - attribute \src "libresoc.v:159375.3-159376.33" - process $proc$libresoc.v:159375$9376 + attribute \src "libresoc.v:167363.3-167364.33" + process $proc$libresoc.v:167363$9358 assign { } { } - assign $0\muxid$1[1:0]$9377 \muxid$1$next + assign $0\muxid$1[1:0]$9359 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9377 + update \muxid$1 $0\muxid$1[1:0]$9359 end - attribute \src "libresoc.v:159377.3-159378.29" - process $proc$libresoc.v:159377$9378 + attribute \src "libresoc.v:167365.3-167366.29" + process $proc$libresoc.v:167365$9360 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:159423.3-159440.6" - process $proc$libresoc.v:159423$9379 + attribute \src "libresoc.v:167431.3-167448.6" + process $proc$libresoc.v:167431$9361 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9380 $2\r_busy$next[0:0]$9382 - attribute \src "libresoc.v:159424.5-159424.29" + assign $0\r_busy$next[0:0]$9362 $2\r_busy$next[0:0]$9364 + attribute \src "libresoc.v:167432.5-167432.29" switch \initial - attribute \src "libresoc.v:159424.9-159424.17" + attribute \src "libresoc.v:167432.9-167432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9381 1'1 + assign $1\r_busy$next[0:0]$9363 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9381 1'0 + assign $1\r_busy$next[0:0]$9363 1'0 case - assign $1\r_busy$next[0:0]$9381 \r_busy + assign $1\r_busy$next[0:0]$9363 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9382 1'0 + assign $2\r_busy$next[0:0]$9364 1'0 case - assign $2\r_busy$next[0:0]$9382 $1\r_busy$next[0:0]$9381 + assign $2\r_busy$next[0:0]$9364 $1\r_busy$next[0:0]$9363 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9380 + update \r_busy$next $0\r_busy$next[0:0]$9362 end - attribute \src "libresoc.v:159441.3-159453.6" - process $proc$libresoc.v:159441$9383 + attribute \src "libresoc.v:167449.3-167461.6" + process $proc$libresoc.v:167449$9365 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9384 $1\muxid$1$next[1:0]$9385 - attribute \src "libresoc.v:159442.5-159442.29" + assign $0\muxid$1$next[1:0]$9366 $1\muxid$1$next[1:0]$9367 + attribute \src "libresoc.v:167450.5-167450.29" switch \initial - attribute \src "libresoc.v:159442.9-159442.17" + attribute \src "libresoc.v:167450.9-167450.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9385 \muxid$28 + assign $1\muxid$1$next[1:0]$9367 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9385 \muxid$28 + assign $1\muxid$1$next[1:0]$9367 \muxid$62 case - assign $1\muxid$1$next[1:0]$9385 \muxid$1 + assign $1\muxid$1$next[1:0]$9367 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9384 + update \muxid$1$next $0\muxid$1$next[1:0]$9366 end - attribute \src "libresoc.v:159454.3-159474.6" - process $proc$libresoc.v:159454$9386 + attribute \src "libresoc.v:167462.3-167503.6" + process $proc$libresoc.v:167462$9368 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -329919,22 +345421,41 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$6$next[63:0]$9387 $1\trap_op__cia$6$next[63:0]$9396 - assign $0\trap_op__fn_unit$3$next[11:0]$9388 $1\trap_op__fn_unit$3$next[11:0]$9397 - assign $0\trap_op__insn$4$next[31:0]$9389 $1\trap_op__insn$4$next[31:0]$9398 - assign $0\trap_op__insn_type$2$next[6:0]$9390 $1\trap_op__insn_type$2$next[6:0]$9399 - assign $0\trap_op__is_32bit$7$next[0:0]$9391 $1\trap_op__is_32bit$7$next[0:0]$9400 - assign $0\trap_op__ldst_exc$10$next[7:0]$9392 $1\trap_op__ldst_exc$10$next[7:0]$9401 - assign $0\trap_op__msr$5$next[63:0]$9393 $1\trap_op__msr$5$next[63:0]$9402 - assign $0\trap_op__trapaddr$9$next[12:0]$9394 $1\trap_op__trapaddr$9$next[12:0]$9403 - assign $0\trap_op__traptype$8$next[7:0]$9395 $1\trap_op__traptype$8$next[7:0]$9404 - attribute \src "libresoc.v:159455.5-159455.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$18$next[3:0]$9369 $1\alu_op__data_len$18$next[3:0]$9387 + assign $0\alu_op__fn_unit$3$next[13:0]$9370 $1\alu_op__fn_unit$3$next[13:0]$9388 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$14$next[1:0]$9373 $1\alu_op__input_carry$14$next[1:0]$9391 + assign $0\alu_op__insn$19$next[31:0]$9374 $1\alu_op__insn$19$next[31:0]$9392 + assign $0\alu_op__insn_type$2$next[6:0]$9375 $1\alu_op__insn_type$2$next[6:0]$9393 + assign $0\alu_op__invert_in$10$next[0:0]$9376 $1\alu_op__invert_in$10$next[0:0]$9394 + assign $0\alu_op__invert_out$12$next[0:0]$9377 $1\alu_op__invert_out$12$next[0:0]$9395 + assign $0\alu_op__is_32bit$16$next[0:0]$9378 $1\alu_op__is_32bit$16$next[0:0]$9396 + assign $0\alu_op__is_signed$17$next[0:0]$9379 $1\alu_op__is_signed$17$next[0:0]$9397 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$15$next[0:0]$9382 $1\alu_op__output_carry$15$next[0:0]$9400 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$13$next[0:0]$9385 $1\alu_op__write_cr0$13$next[0:0]$9403 + assign $0\alu_op__zero_a$11$next[0:0]$9386 $1\alu_op__zero_a$11$next[0:0]$9404 + assign $0\alu_op__imm_data__data$4$next[63:0]$9371 $2\alu_op__imm_data__data$4$next[63:0]$9405 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9372 $2\alu_op__imm_data__ok$5$next[0:0]$9406 + assign $0\alu_op__oe__oe$8$next[0:0]$9380 $2\alu_op__oe__oe$8$next[0:0]$9407 + assign $0\alu_op__oe__ok$9$next[0:0]$9381 $2\alu_op__oe__ok$9$next[0:0]$9408 + assign $0\alu_op__rc__ok$7$next[0:0]$9383 $2\alu_op__rc__ok$7$next[0:0]$9409 + assign $0\alu_op__rc__rc$6$next[0:0]$9384 $2\alu_op__rc__rc$6$next[0:0]$9410 + attribute \src "libresoc.v:167463.5-167463.29" switch \initial - attribute \src "libresoc.v:159455.9-159455.17" + attribute \src "libresoc.v:167463.9-167463.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -329947,7 +345468,16 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9401 $1\trap_op__trapaddr$9$next[12:0]$9403 $1\trap_op__traptype$8$next[7:0]$9404 $1\trap_op__is_32bit$7$next[0:0]$9400 $1\trap_op__cia$6$next[63:0]$9396 $1\trap_op__msr$5$next[63:0]$9402 $1\trap_op__insn$4$next[31:0]$9398 $1\trap_op__fn_unit$3$next[11:0]$9397 $1\trap_op__insn_type$2$next[6:0]$9399 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9392 $1\alu_op__data_len$18$next[3:0]$9387 $1\alu_op__is_signed$17$next[0:0]$9397 $1\alu_op__is_32bit$16$next[0:0]$9396 $1\alu_op__output_carry$15$next[0:0]$9400 $1\alu_op__input_carry$14$next[1:0]$9391 $1\alu_op__write_cr0$13$next[0:0]$9403 $1\alu_op__invert_out$12$next[0:0]$9395 $1\alu_op__zero_a$11$next[0:0]$9404 $1\alu_op__invert_in$10$next[0:0]$9394 $1\alu_op__oe__ok$9$next[0:0]$9399 $1\alu_op__oe__oe$8$next[0:0]$9398 $1\alu_op__rc__ok$7$next[0:0]$9401 $1\alu_op__rc__rc$6$next[0:0]$9402 $1\alu_op__imm_data__ok$5$next[0:0]$9390 $1\alu_op__imm_data__data$4$next[63:0]$9389 $1\alu_op__fn_unit$3$next[13:0]$9388 $1\alu_op__insn_type$2$next[6:0]$9393 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -329959,735 +345489,686 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9401 $1\trap_op__trapaddr$9$next[12:0]$9403 $1\trap_op__traptype$8$next[7:0]$9404 $1\trap_op__is_32bit$7$next[0:0]$9400 $1\trap_op__cia$6$next[63:0]$9396 $1\trap_op__msr$5$next[63:0]$9402 $1\trap_op__insn$4$next[31:0]$9398 $1\trap_op__fn_unit$3$next[11:0]$9397 $1\trap_op__insn_type$2$next[6:0]$9399 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9392 $1\alu_op__data_len$18$next[3:0]$9387 $1\alu_op__is_signed$17$next[0:0]$9397 $1\alu_op__is_32bit$16$next[0:0]$9396 $1\alu_op__output_carry$15$next[0:0]$9400 $1\alu_op__input_carry$14$next[1:0]$9391 $1\alu_op__write_cr0$13$next[0:0]$9403 $1\alu_op__invert_out$12$next[0:0]$9395 $1\alu_op__zero_a$11$next[0:0]$9404 $1\alu_op__invert_in$10$next[0:0]$9394 $1\alu_op__oe__ok$9$next[0:0]$9399 $1\alu_op__oe__oe$8$next[0:0]$9398 $1\alu_op__rc__ok$7$next[0:0]$9401 $1\alu_op__rc__rc$6$next[0:0]$9402 $1\alu_op__imm_data__ok$5$next[0:0]$9390 $1\alu_op__imm_data__data$4$next[63:0]$9389 $1\alu_op__fn_unit$3$next[13:0]$9388 $1\alu_op__insn_type$2$next[6:0]$9393 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + case + assign $1\alu_op__data_len$18$next[3:0]$9387 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[13:0]$9388 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9389 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9390 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9391 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9392 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9393 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9394 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9395 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9396 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9397 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9398 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9399 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9400 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9401 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9402 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9403 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9404 \alu_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$4$next[63:0]$9405 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9406 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9410 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9409 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9407 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9408 1'0 case - assign $1\trap_op__cia$6$next[63:0]$9396 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[11:0]$9397 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$9398 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$9399 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$9400 \trap_op__is_32bit$7 - assign $1\trap_op__ldst_exc$10$next[7:0]$9401 \trap_op__ldst_exc$10 - assign $1\trap_op__msr$5$next[63:0]$9402 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$9403 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[7:0]$9404 \trap_op__traptype$8 + assign $2\alu_op__imm_data__data$4$next[63:0]$9405 $1\alu_op__imm_data__data$4$next[63:0]$9389 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9406 $1\alu_op__imm_data__ok$5$next[0:0]$9390 + assign $2\alu_op__oe__oe$8$next[0:0]$9407 $1\alu_op__oe__oe$8$next[0:0]$9398 + assign $2\alu_op__oe__ok$9$next[0:0]$9408 $1\alu_op__oe__ok$9$next[0:0]$9399 + assign $2\alu_op__rc__ok$7$next[0:0]$9409 $1\alu_op__rc__ok$7$next[0:0]$9401 + assign $2\alu_op__rc__rc$6$next[0:0]$9410 $1\alu_op__rc__rc$6$next[0:0]$9402 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9387 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[11:0]$9388 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9389 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9390 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9391 - update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9392 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9393 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9394 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9395 + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9369 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9370 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9371 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9372 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9373 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9374 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9375 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9376 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9377 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9378 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9379 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9380 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9381 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9382 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9383 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9384 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9385 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9386 end - attribute \src "libresoc.v:159475.3-159493.6" - process $proc$libresoc.v:159475$9405 + attribute \src "libresoc.v:167504.3-167522.6" + process $proc$libresoc.v:167504$9411 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9406 $1\o$next[63:0]$9408 + assign $0\o$20$next[63:0]$9412 $1\o$20$next[63:0]$9414 assign { } { } - assign $0\o_ok$next[0:0]$9407 $2\o_ok$next[0:0]$9410 - attribute \src "libresoc.v:159476.5-159476.29" + assign $0\o_ok$21$next[0:0]$9413 $2\o_ok$21$next[0:0]$9416 + attribute \src "libresoc.v:167505.5-167505.29" switch \initial - attribute \src "libresoc.v:159476.9-159476.17" + attribute \src "libresoc.v:167505.9-167505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9409 $1\o$next[63:0]$9408 } { \o_ok$39 \o$38 } + assign { $1\o_ok$21$next[0:0]$9415 $1\o$20$next[63:0]$9414 } { \o_ok$82 \o$81 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9409 $1\o$next[63:0]$9408 } { \o_ok$39 \o$38 } + assign { $1\o_ok$21$next[0:0]$9415 $1\o$20$next[63:0]$9414 } { \o_ok$82 \o$81 } case - assign $1\o$next[63:0]$9408 \o - assign $1\o_ok$next[0:0]$9409 \o_ok + assign $1\o$20$next[63:0]$9414 \o$20 + assign $1\o_ok$21$next[0:0]$9415 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9410 1'0 + assign $2\o_ok$21$next[0:0]$9416 1'0 case - assign $2\o_ok$next[0:0]$9410 $1\o_ok$next[0:0]$9409 + assign $2\o_ok$21$next[0:0]$9416 $1\o_ok$21$next[0:0]$9415 end sync always - update \o$next $0\o$next[63:0]$9406 - update \o_ok$next $0\o_ok$next[0:0]$9407 + update \o$20$next $0\o$20$next[63:0]$9412 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9413 end - attribute \src "libresoc.v:159494.3-159512.6" - process $proc$libresoc.v:159494$9411 + attribute \src "libresoc.v:167523.3-167541.6" + process $proc$libresoc.v:167523$9417 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\cr_a$22$next[3:0]$9418 $1\cr_a$22$next[3:0]$9420 assign { } { } - assign $0\fast1$11$next[63:0]$9413 $1\fast1$11$next[63:0]$9415 - assign $0\fast1_ok$next[0:0]$9412 $2\fast1_ok$next[0:0]$9416 - attribute \src "libresoc.v:159495.5-159495.29" + assign $0\cr_a_ok$23$next[0:0]$9419 $2\cr_a_ok$23$next[0:0]$9422 + attribute \src "libresoc.v:167524.5-167524.29" switch \initial - attribute \src "libresoc.v:159495.9-159495.17" + attribute \src "libresoc.v:167524.9-167524.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9414 $1\fast1$11$next[63:0]$9415 } { \fast1_ok$41 \fast1$40 } + assign { $1\cr_a_ok$23$next[0:0]$9421 $1\cr_a$22$next[3:0]$9420 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9414 $1\fast1$11$next[63:0]$9415 } { \fast1_ok$41 \fast1$40 } + assign { $1\cr_a_ok$23$next[0:0]$9421 $1\cr_a$22$next[3:0]$9420 } { \cr_a_ok$84 \cr_a$83 } case - assign $1\fast1_ok$next[0:0]$9414 \fast1_ok - assign $1\fast1$11$next[63:0]$9415 \fast1$11 + assign $1\cr_a$22$next[3:0]$9420 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9421 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$9416 1'0 + assign $2\cr_a_ok$23$next[0:0]$9422 1'0 case - assign $2\fast1_ok$next[0:0]$9416 $1\fast1_ok$next[0:0]$9414 + assign $2\cr_a_ok$23$next[0:0]$9422 $1\cr_a_ok$23$next[0:0]$9421 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$9412 - update \fast1$11$next $0\fast1$11$next[63:0]$9413 + update \cr_a$22$next $0\cr_a$22$next[3:0]$9418 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9419 end - attribute \src "libresoc.v:159513.3-159531.6" - process $proc$libresoc.v:159513$9417 + attribute \src "libresoc.v:167542.3-167560.6" + process $proc$libresoc.v:167542$9423 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\xer_ca$24$next[1:0]$9424 $1\xer_ca$24$next[1:0]$9426 assign { } { } - assign $0\fast2$12$next[63:0]$9419 $1\fast2$12$next[63:0]$9421 - assign $0\fast2_ok$next[0:0]$9418 $2\fast2_ok$next[0:0]$9422 - attribute \src "libresoc.v:159514.5-159514.29" + assign $0\xer_ca_ok$25$next[0:0]$9425 $2\xer_ca_ok$25$next[0:0]$9428 + attribute \src "libresoc.v:167543.5-167543.29" switch \initial - attribute \src "libresoc.v:159514.9-159514.17" + attribute \src "libresoc.v:167543.9-167543.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9420 $1\fast2$12$next[63:0]$9421 } { \fast2_ok$43 \fast2$42 } + assign { $1\xer_ca_ok$25$next[0:0]$9427 $1\xer_ca$24$next[1:0]$9426 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9420 $1\fast2$12$next[63:0]$9421 } { \fast2_ok$43 \fast2$42 } + assign { $1\xer_ca_ok$25$next[0:0]$9427 $1\xer_ca$24$next[1:0]$9426 } { \xer_ca_ok$86 \xer_ca$85 } case - assign $1\fast2_ok$next[0:0]$9420 \fast2_ok - assign $1\fast2$12$next[63:0]$9421 \fast2$12 + assign $1\xer_ca$24$next[1:0]$9426 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9427 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$9422 1'0 + assign $2\xer_ca_ok$25$next[0:0]$9428 1'0 case - assign $2\fast2_ok$next[0:0]$9422 $1\fast2_ok$next[0:0]$9420 + assign $2\xer_ca_ok$25$next[0:0]$9428 $1\xer_ca_ok$25$next[0:0]$9427 end sync always - update \fast2_ok$next $0\fast2_ok$next[0:0]$9418 - update \fast2$12$next $0\fast2$12$next[63:0]$9419 + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9424 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9425 end - attribute \src "libresoc.v:159532.3-159550.6" - process $proc$libresoc.v:159532$9423 + attribute \src "libresoc.v:167561.3-167579.6" + process $proc$libresoc.v:167561$9429 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$9424 $1\nia$next[63:0]$9426 + assign $0\xer_ov$26$next[1:0]$9430 $1\xer_ov$26$next[1:0]$9432 assign { } { } - assign $0\nia_ok$next[0:0]$9425 $2\nia_ok$next[0:0]$9428 - attribute \src "libresoc.v:159533.5-159533.29" + assign $0\xer_ov_ok$27$next[0:0]$9431 $2\xer_ov_ok$27$next[0:0]$9434 + attribute \src "libresoc.v:167562.5-167562.29" switch \initial - attribute \src "libresoc.v:159533.9-159533.17" + attribute \src "libresoc.v:167562.9-167562.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9427 $1\nia$next[63:0]$9426 } { \nia_ok$45 \nia$44 } + assign { $1\xer_ov_ok$27$next[0:0]$9433 $1\xer_ov$26$next[1:0]$9432 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9427 $1\nia$next[63:0]$9426 } { \nia_ok$45 \nia$44 } + assign { $1\xer_ov_ok$27$next[0:0]$9433 $1\xer_ov$26$next[1:0]$9432 } { \xer_ov_ok$88 \xer_ov$87 } case - assign $1\nia$next[63:0]$9426 \nia - assign $1\nia_ok$next[0:0]$9427 \nia_ok + assign $1\xer_ov$26$next[1:0]$9432 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9433 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$9428 1'0 + assign $2\xer_ov_ok$27$next[0:0]$9434 1'0 case - assign $2\nia_ok$next[0:0]$9428 $1\nia_ok$next[0:0]$9427 + assign $2\xer_ov_ok$27$next[0:0]$9434 $1\xer_ov_ok$27$next[0:0]$9433 end sync always - update \nia$next $0\nia$next[63:0]$9424 - update \nia_ok$next $0\nia_ok$next[0:0]$9425 + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9430 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9431 end - attribute \src "libresoc.v:159551.3-159569.6" - process $proc$libresoc.v:159551$9429 + attribute \src "libresoc.v:167580.3-167598.6" + process $proc$libresoc.v:167580$9435 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr$next[63:0]$9430 $1\msr$next[63:0]$9432 + assign $0\xer_so$28$next[0:0]$9436 $1\xer_so$28$next[0:0]$9438 assign { } { } - assign $0\msr_ok$next[0:0]$9431 $2\msr_ok$next[0:0]$9434 - attribute \src "libresoc.v:159552.5-159552.29" + assign $0\xer_so_ok$29$next[0:0]$9437 $2\xer_so_ok$29$next[0:0]$9440 + attribute \src "libresoc.v:167581.5-167581.29" switch \initial - attribute \src "libresoc.v:159552.9-159552.17" + attribute \src "libresoc.v:167581.9-167581.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9433 $1\msr$next[63:0]$9432 } { \msr_ok$47 \msr$46 } + assign { $1\xer_so_ok$29$next[0:0]$9439 $1\xer_so$28$next[0:0]$9438 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9433 $1\msr$next[63:0]$9432 } { \msr_ok$47 \msr$46 } + assign { $1\xer_so_ok$29$next[0:0]$9439 $1\xer_so$28$next[0:0]$9438 } { \xer_so_ok$90 \xer_so$89 } case - assign $1\msr$next[63:0]$9432 \msr - assign $1\msr_ok$next[0:0]$9433 \msr_ok + assign $1\xer_so$28$next[0:0]$9438 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9439 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_ok$next[0:0]$9434 1'0 + assign $2\xer_so_ok$29$next[0:0]$9440 1'0 case - assign $2\msr_ok$next[0:0]$9434 $1\msr_ok$next[0:0]$9433 + assign $2\xer_so_ok$29$next[0:0]$9440 $1\xer_so_ok$29$next[0:0]$9439 end sync always - update \msr$next $0\msr$next[63:0]$9430 - update \msr_ok$next $0\msr_ok$next[0:0]$9431 + update \xer_so$28$next $0\xer_so$28$next[0:0]$9436 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9437 end - connect \$26 $and$libresoc.v:159336$9345_Y + connect \$60 $and$libresoc.v:167306$9301_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } - connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } - connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } - connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } - connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } - connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } - connect \muxid$28 \main_muxid$13 - connect \p_valid_i_p_ready_o \$26 + connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } + connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + connect \muxid$62 \output_muxid$30 + connect \p_valid_i_p_ready_o \$60 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$25 \p_valid_i - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect \main_rb \rb - connect \main_ra \ra - connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \main_muxid \muxid + connect \p_valid_i$59 \p_valid_i + connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } + connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } + connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \output_muxid \muxid end -attribute \src "libresoc.v:159592.1-161074.10" +attribute \src "libresoc.v:167622.1-168691.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" -module \pipe_end - attribute \src "libresoc.v:160912.3-160930.6" - wire width 4 $0\cr_a$next[3:0]$9525 - attribute \src "libresoc.v:160731.3-160732.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:160912.3-160930.6" - wire $0\cr_a_ok$next[0:0]$9526 - attribute \src "libresoc.v:160733.3-160734.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:159593.7-159593.20" +module \pipe2$115 + attribute \src "libresoc.v:168637.3-168655.6" + wire width 4 $0\cr_a$21$next[3:0]$9606 + attribute \src "libresoc.v:168443.3-168444.33" + wire width 4 $0\cr_a$21[3:0]$9507 + attribute \src "libresoc.v:167634.13-167634.29" + wire width 4 $0\cr_a$21[3:0]$9619 + attribute \src "libresoc.v:168637.3-168655.6" + wire $0\cr_a_ok$22$next[0:0]$9607 + attribute \src "libresoc.v:168445.3-168446.39" + wire $0\cr_a_ok$22[0:0]$9509 + attribute \src "libresoc.v:167643.7-167643.26" + wire $0\cr_a_ok$22[0:0]$9621 + attribute \src "libresoc.v:167623.7-167623.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161000.3-161041.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9550 - attribute \src "libresoc.v:160771.3-160772.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9512 - attribute \src "libresoc.v:159634.13-159634.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9596 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 12 $0\logical_op__fn_unit$3$next[11:0]$9551 - attribute \src "libresoc.v:160741.3-160742.61" - wire width 12 $0\logical_op__fn_unit$3[11:0]$9482 - attribute \src "libresoc.v:159669.14-159669.47" - wire width 12 $0\logical_op__fn_unit$3[11:0]$9598 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9552 - attribute \src "libresoc.v:160743.3-160744.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9484 - attribute \src "libresoc.v:159691.14-159691.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9600 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9553 - attribute \src "libresoc.v:160745.3-160746.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9486 - attribute \src "libresoc.v:159700.7-159700.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9602 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9554 - attribute \src "libresoc.v:160759.3-160760.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9500 - attribute \src "libresoc.v:159717.13-159717.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9604 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9555 - attribute \src "libresoc.v:160773.3-160774.57" - wire width 32 $0\logical_op__insn$19[31:0]$9514 - attribute \src "libresoc.v:159730.14-159730.43" - wire width 32 $0\logical_op__insn$19[31:0]$9606 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9556 - attribute \src "libresoc.v:160739.3-160740.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9480 - attribute \src "libresoc.v:159887.13-159887.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9608 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__invert_in$10$next[0:0]$9557 - attribute \src "libresoc.v:160755.3-160756.67" - wire $0\logical_op__invert_in$10[0:0]$9496 - attribute \src "libresoc.v:159970.7-159970.40" - wire $0\logical_op__invert_in$10[0:0]$9610 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__invert_out$13$next[0:0]$9558 - attribute \src "libresoc.v:160761.3-160762.69" - wire $0\logical_op__invert_out$13[0:0]$9502 - attribute \src "libresoc.v:159979.7-159979.41" - wire $0\logical_op__invert_out$13[0:0]$9612 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9559 - attribute \src "libresoc.v:160767.3-160768.65" - wire $0\logical_op__is_32bit$16[0:0]$9508 - attribute \src "libresoc.v:159988.7-159988.39" - wire $0\logical_op__is_32bit$16[0:0]$9614 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__is_signed$17$next[0:0]$9560 - attribute \src "libresoc.v:160769.3-160770.67" - wire $0\logical_op__is_signed$17[0:0]$9510 - attribute \src "libresoc.v:159997.7-159997.40" - wire $0\logical_op__is_signed$17[0:0]$9616 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9561 - attribute \src "libresoc.v:160751.3-160752.59" - wire $0\logical_op__oe__oe$8[0:0]$9492 - attribute \src "libresoc.v:160006.7-160006.36" - wire $0\logical_op__oe__oe$8[0:0]$9618 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9562 - attribute \src "libresoc.v:160753.3-160754.59" - wire $0\logical_op__oe__ok$9[0:0]$9494 - attribute \src "libresoc.v:160017.7-160017.36" - wire $0\logical_op__oe__ok$9[0:0]$9620 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__output_carry$15$next[0:0]$9563 - attribute \src "libresoc.v:160765.3-160766.73" - wire $0\logical_op__output_carry$15[0:0]$9506 - attribute \src "libresoc.v:160024.7-160024.43" - wire $0\logical_op__output_carry$15[0:0]$9622 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9564 - attribute \src "libresoc.v:160749.3-160750.59" - wire $0\logical_op__rc__ok$7[0:0]$9490 - attribute \src "libresoc.v:160033.7-160033.36" - wire $0\logical_op__rc__ok$7[0:0]$9624 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9565 - attribute \src "libresoc.v:160747.3-160748.59" - wire $0\logical_op__rc__rc$6[0:0]$9488 - attribute \src "libresoc.v:160042.7-160042.36" - wire $0\logical_op__rc__rc$6[0:0]$9626 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9566 - attribute \src "libresoc.v:160763.3-160764.67" - wire $0\logical_op__write_cr0$14[0:0]$9504 - attribute \src "libresoc.v:160051.7-160051.40" - wire $0\logical_op__write_cr0$14[0:0]$9628 - attribute \src "libresoc.v:161000.3-161041.6" - wire $0\logical_op__zero_a$11$next[0:0]$9567 - attribute \src "libresoc.v:160757.3-160758.61" - wire $0\logical_op__zero_a$11[0:0]$9498 - attribute \src "libresoc.v:160060.7-160060.37" - wire $0\logical_op__zero_a$11[0:0]$9630 - attribute \src "libresoc.v:160987.3-160999.6" - wire width 2 $0\muxid$1$next[1:0]$9547 - attribute \src "libresoc.v:160775.3-160776.33" - wire width 2 $0\muxid$1[1:0]$9516 - attribute \src "libresoc.v:160069.13-160069.29" - wire width 2 $0\muxid$1[1:0]$9632 - attribute \src "libresoc.v:160893.3-160911.6" - wire width 64 $0\o$next[63:0]$9519 - attribute \src "libresoc.v:160735.3-160736.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:160893.3-160911.6" - wire $0\o_ok$next[0:0]$9520 - attribute \src "libresoc.v:160737.3-160738.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:160969.3-160986.6" - wire $0\r_busy$next[0:0]$9543 - attribute \src "libresoc.v:160777.3-160778.29" + attribute \src "libresoc.v:168564.3-168576.6" + wire width 2 $0\muxid$1$next[1:0]$9556 + attribute \src "libresoc.v:168485.3-168486.33" + wire width 2 $0\muxid$1[1:0]$9549 + attribute \src "libresoc.v:167654.13-167654.29" + wire width 2 $0\muxid$1[1:0]$9623 + attribute \src "libresoc.v:168618.3-168636.6" + wire width 64 $0\o$19$next[63:0]$9600 + attribute \src "libresoc.v:168447.3-168448.27" + wire width 64 $0\o$19[63:0]$9511 + attribute \src "libresoc.v:167669.14-167669.43" + wire width 64 $0\o$19[63:0]$9625 + attribute \src "libresoc.v:168618.3-168636.6" + wire $0\o_ok$20$next[0:0]$9601 + attribute \src "libresoc.v:168449.3-168450.33" + wire $0\o_ok$20[0:0]$9513 + attribute \src "libresoc.v:167678.7-167678.23" + wire $0\o_ok$20[0:0]$9627 + attribute \src "libresoc.v:168546.3-168563.6" + wire $0\r_busy$next[0:0]$9552 + attribute \src "libresoc.v:168487.3-168488.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:160931.3-160949.6" - wire width 2 $0\xer_ov$next[1:0]$9531 - attribute \src "libresoc.v:160727.3-160728.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:160931.3-160949.6" - wire $0\xer_ov_ok$next[0:0]$9532 - attribute \src "libresoc.v:160729.3-160730.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:160950.3-160968.6" - wire $0\xer_so$20$next[0:0]$9538 - attribute \src "libresoc.v:160723.3-160724.37" - wire $0\xer_so$20[0:0]$9471 - attribute \src "libresoc.v:160708.7-160708.25" - wire $0\xer_so$20[0:0]$9639 - attribute \src "libresoc.v:160950.3-160968.6" - wire $0\xer_so_ok$next[0:0]$9537 - attribute \src "libresoc.v:160725.3-160726.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:160912.3-160930.6" - wire width 4 $1\cr_a$next[3:0]$9527 - attribute \src "libresoc.v:159602.13-159602.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:160912.3-160930.6" - wire $1\cr_a_ok$next[0:0]$9528 - attribute \src "libresoc.v:159611.7-159611.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:161000.3-161041.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9568 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 12 $1\logical_op__fn_unit$3$next[11:0]$9569 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9570 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$9571 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$9572 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$9573 - attribute \src "libresoc.v:161000.3-161041.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$9574 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__invert_in$10$next[0:0]$9575 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__invert_out$13$next[0:0]$9576 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__is_32bit$16$next[0:0]$9577 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__is_signed$17$next[0:0]$9578 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__oe__oe$8$next[0:0]$9579 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__oe__ok$9$next[0:0]$9580 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__output_carry$15$next[0:0]$9581 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__rc__ok$7$next[0:0]$9582 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__rc__rc$6$next[0:0]$9583 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__write_cr0$14$next[0:0]$9584 - attribute \src "libresoc.v:161000.3-161041.6" - wire $1\logical_op__zero_a$11$next[0:0]$9585 - attribute \src "libresoc.v:160987.3-160999.6" - wire width 2 $1\muxid$1$next[1:0]$9548 - attribute \src "libresoc.v:160893.3-160911.6" - wire width 64 $1\o$next[63:0]$9521 - attribute \src "libresoc.v:160082.14-160082.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:160893.3-160911.6" - wire $1\o_ok$next[0:0]$9522 - attribute \src "libresoc.v:160089.7-160089.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:160969.3-160986.6" - wire $1\r_busy$next[0:0]$9544 - attribute \src "libresoc.v:160673.7-160673.20" + attribute \src "libresoc.v:168577.3-168617.6" + wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9559 + attribute \src "libresoc.v:168453.3-168454.51" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9517 + attribute \src "libresoc.v:168011.14-168011.43" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9630 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9560 + attribute \src "libresoc.v:168455.3-168456.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9519 + attribute \src "libresoc.v:168035.14-168035.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9632 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9561 + attribute \src "libresoc.v:168457.3-168458.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9521 + attribute \src "libresoc.v:168044.7-168044.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9634 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9562 + attribute \src "libresoc.v:168471.3-168472.61" + wire width 2 $0\sr_op__input_carry$12[1:0]$9535 + attribute \src "libresoc.v:168061.13-168061.43" + wire width 2 $0\sr_op__input_carry$12[1:0]$9636 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__input_cr$14$next[0:0]$9563 + attribute \src "libresoc.v:168475.3-168476.55" + wire $0\sr_op__input_cr$14[0:0]$9539 + attribute \src "libresoc.v:168074.7-168074.34" + wire $0\sr_op__input_cr$14[0:0]$9638 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 32 $0\sr_op__insn$18$next[31:0]$9564 + attribute \src "libresoc.v:168483.3-168484.47" + wire width 32 $0\sr_op__insn$18[31:0]$9547 + attribute \src "libresoc.v:168083.14-168083.38" + wire width 32 $0\sr_op__insn$18[31:0]$9640 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9565 + attribute \src "libresoc.v:168451.3-168452.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$9515 + attribute \src "libresoc.v:168242.13-168242.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9642 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__invert_in$11$next[0:0]$9566 + attribute \src "libresoc.v:168469.3-168470.57" + wire $0\sr_op__invert_in$11[0:0]$9533 + attribute \src "libresoc.v:168326.7-168326.35" + wire $0\sr_op__invert_in$11[0:0]$9644 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__is_32bit$16$next[0:0]$9567 + attribute \src "libresoc.v:168479.3-168480.55" + wire $0\sr_op__is_32bit$16[0:0]$9543 + attribute \src "libresoc.v:168335.7-168335.34" + wire $0\sr_op__is_32bit$16[0:0]$9646 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__is_signed$17$next[0:0]$9568 + attribute \src "libresoc.v:168481.3-168482.57" + wire $0\sr_op__is_signed$17[0:0]$9545 + attribute \src "libresoc.v:168344.7-168344.35" + wire $0\sr_op__is_signed$17[0:0]$9648 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__oe__oe$8$next[0:0]$9569 + attribute \src "libresoc.v:168463.3-168464.49" + wire $0\sr_op__oe__oe$8[0:0]$9527 + attribute \src "libresoc.v:168355.7-168355.31" + wire $0\sr_op__oe__oe$8[0:0]$9650 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__oe__ok$9$next[0:0]$9570 + attribute \src "libresoc.v:168465.3-168466.49" + wire $0\sr_op__oe__ok$9[0:0]$9529 + attribute \src "libresoc.v:168364.7-168364.31" + wire $0\sr_op__oe__ok$9[0:0]$9652 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__output_carry$13$next[0:0]$9571 + attribute \src "libresoc.v:168473.3-168474.63" + wire $0\sr_op__output_carry$13[0:0]$9537 + attribute \src "libresoc.v:168371.7-168371.38" + wire $0\sr_op__output_carry$13[0:0]$9654 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__output_cr$15$next[0:0]$9572 + attribute \src "libresoc.v:168477.3-168478.57" + wire $0\sr_op__output_cr$15[0:0]$9541 + attribute \src "libresoc.v:168380.7-168380.35" + wire $0\sr_op__output_cr$15[0:0]$9656 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__rc__ok$7$next[0:0]$9573 + attribute \src "libresoc.v:168461.3-168462.49" + wire $0\sr_op__rc__ok$7[0:0]$9525 + attribute \src "libresoc.v:168391.7-168391.31" + wire $0\sr_op__rc__ok$7[0:0]$9658 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__rc__rc$6$next[0:0]$9574 + attribute \src "libresoc.v:168459.3-168460.49" + wire $0\sr_op__rc__rc$6[0:0]$9523 + attribute \src "libresoc.v:168400.7-168400.31" + wire $0\sr_op__rc__rc$6[0:0]$9660 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__write_cr0$10$next[0:0]$9575 + attribute \src "libresoc.v:168467.3-168468.57" + wire $0\sr_op__write_cr0$10[0:0]$9531 + attribute \src "libresoc.v:168407.7-168407.35" + wire $0\sr_op__write_cr0$10[0:0]$9662 + attribute \src "libresoc.v:168656.3-168674.6" + wire width 2 $0\xer_ca$23$next[1:0]$9612 + attribute \src "libresoc.v:168439.3-168440.37" + wire width 2 $0\xer_ca$23[1:0]$9503 + attribute \src "libresoc.v:168416.13-168416.31" + wire width 2 $0\xer_ca$23[1:0]$9664 + attribute \src "libresoc.v:168656.3-168674.6" + wire $0\xer_ca_ok$24$next[0:0]$9613 + attribute \src "libresoc.v:168441.3-168442.43" + wire $0\xer_ca_ok$24[0:0]$9505 + attribute \src "libresoc.v:168425.7-168425.28" + wire $0\xer_ca_ok$24[0:0]$9666 + attribute \src "libresoc.v:168637.3-168655.6" + wire width 4 $1\cr_a$21$next[3:0]$9608 + attribute \src "libresoc.v:168637.3-168655.6" + wire $1\cr_a_ok$22$next[0:0]$9609 + attribute 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"libresoc.v:160722.18-160722.118" - wire $and$libresoc.v:160722$9469_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "libresoc.v:168577.3-168617.6" + wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9576 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9577 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9578 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 2 $1\sr_op__input_carry$12$next[1:0]$9579 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__input_cr$14$next[0:0]$9580 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 32 $1\sr_op__insn$18$next[31:0]$9581 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9582 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__invert_in$11$next[0:0]$9583 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__is_32bit$16$next[0:0]$9584 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__is_signed$17$next[0:0]$9585 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9586 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9587 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__output_carry$13$next[0:0]$9588 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__output_cr$15$next[0:0]$9589 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9590 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9591 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9592 + attribute \src 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"libresoc.v:168656.3-168674.6" + wire $2\xer_ca_ok$24$next[0:0]$9616 + attribute \src "libresoc.v:168438.18-168438.118" + wire $and$libresoc.v:168438$9501_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 56 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 56 \cr_a + wire width 4 input 24 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$68 + wire width 4 output 52 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$97 + wire width 4 \cr_a$21$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next + wire width 4 \cr_a$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 57 \cr_a_ok + wire input 25 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$67 + wire output 53 \cr_a_ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$69 + wire \cr_a_ok$22$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$98 + wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire input 26 \divisor_neg - attribute \src "libresoc.v:159593.7-159593.15" + wire \cr_a_ok$74 + attribute \src "libresoc.v:167623.7-167623.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$93 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 31 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 30 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 50 \o$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \o_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$44 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 37 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_sr_op__fn_unit$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__imm_data__ok$5 + wire width 64 \output_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$5$next + wire width 64 \output_sr_op__imm_data__data$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$80 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \output_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry + wire \output_sr_op__imm_data__ok$29 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 46 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next + wire width 2 \output_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn + wire width 2 \output_sr_op__input_carry$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \logical_op__insn$19 + wire \output_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next + wire \output_sr_op__input_cr$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$94 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 32 \output_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type + wire width 32 \output_sr_op__insn$42 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -330762,10 +346243,9 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next + wire width 7 \output_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -330840,186 +346320,174 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$9$next + wire width 7 \output_sr_op__insn_type$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry + wire \output_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \logical_op__output_carry$15 + wire \output_sr_op__invert_in$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$15$next + wire \output_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$90 + wire \output_sr_op__is_32bit$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok + wire \output_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__rc__ok$7 + wire \output_sr_op__is_signed$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$7$next + wire \output_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$82 + wire \output_sr_op__oe__oe$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc + wire \output_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__rc__rc$6 + wire \output_sr_op__oe__ok$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$6$next + wire \output_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$81 + wire \output_sr_op__output_carry$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 + wire \output_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \logical_op__write_cr0$14 + wire \output_sr_op__output_cr$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$14$next + wire \output_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$89 + wire \output_sr_op__rc__ok$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a + wire \output_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__zero_a$11 + wire \output_sr_op__rc__rc$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$11$next + wire \output_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$76 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 54 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$96 + wire \output_sr_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next + wire width 2 \output_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a + wire width 2 \output_xer_ca$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$62 + wire \output_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$58 + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit$43 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 34 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data + wire width 64 input 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data$44 + wire width 64 output 35 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok + wire width 64 \sr_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok$45 + wire width 64 \sr_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$57 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry + wire width 2 input 15 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$52 + wire width 2 output 43 \sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn + wire width 2 \sr_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$59 + wire width 2 \sr_op__input_carry$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$70 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -331094,8 +346562,9 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type + wire width 7 input 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -331170,132 +346639,11 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \output_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \output_stage_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \output_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \output_stage_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \output_stage_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_stage_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_stage_logical_op__data_len$38 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_stage_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_stage_logical_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__imm_data__ok$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_stage_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_stage_logical_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_stage_logical_op__insn + wire width 7 output 33 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_stage_logical_op__insn$39 + wire width 7 \sr_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -331370,1791 +346718,1561 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 7 \sr_op__insn_type$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type$22 + wire input 14 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_in + wire output 42 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_in$30 + wire \sr_op__invert_in$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_out + wire \sr_op__invert_in$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_out$33 + wire input 19 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_32bit + wire output 47 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_32bit$36 + wire \sr_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_signed + wire \sr_op__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_signed$37 + wire input 20 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__oe + wire output 48 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__oe$28 + wire \sr_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__ok + wire \sr_op__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__ok$29 + wire input 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__output_carry + wire \sr_op__oe__oe$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__output_carry$35 + wire output 39 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__ok + wire \sr_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__ok$27 + wire input 12 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__rc + wire \sr_op__oe__ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__rc$26 + wire output 40 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__write_cr0 + wire \sr_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__write_cr0$34 + wire input 16 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__zero_a + wire output 44 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__zero_a$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_stage_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \output_stage_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \output_stage_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_stage_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \output_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_xer_so$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 31 \quotient_root - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 input 32 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 58 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 59 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 60 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 61 \xer_so_ok + wire \sr_op__output_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$102 + wire width 2 input 28 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$71 + wire width 2 output 54 \xer_ca$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$72 + wire width 2 \xer_ca$23$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:160722$9469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$73 - connect \B \p_ready_o - connect \Y $and$libresoc.v:160722$9469_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:160779.10-160782.4" - cell \n$82 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:160783.15-160835.4" - cell \output$83 \output - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$62 - connect \cr_a_ok \output_cr_a_ok - connect \logical_op__data_len \output_logical_op__data_len - connect \logical_op__data_len$18 \output_logical_op__data_len$58 - connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 - connect \logical_op__imm_data__data \output_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 - connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 - connect \logical_op__input_carry \output_logical_op__input_carry - connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 - connect \logical_op__insn \output_logical_op__insn - connect \logical_op__insn$19 \output_logical_op__insn$59 - connect \logical_op__insn_type \output_logical_op__insn_type - connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 - connect \logical_op__invert_in \output_logical_op__invert_in - connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 - connect \logical_op__invert_out \output_logical_op__invert_out - connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 - connect \logical_op__is_32bit \output_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 - connect \logical_op__oe__ok \output_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 - connect \logical_op__rc__ok \output_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 + wire width 2 \xer_ca$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \xer_ca_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:168438$9501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$50 + connect \B \p_ready_o + connect \Y $and$libresoc.v:168438$9501_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:168489.11-168492.4" + cell \n$117 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:168493.16-168541.4" + cell \output$118 \output + connect \cr_a \output_cr_a + connect \cr_a$21 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok connect \muxid \output_muxid - connect \muxid$1 \output_muxid$41 + connect \muxid$1 \output_muxid$25 connect \o \output_o - connect \o$20 \output_o$60 + connect \o$19 \output_o$43 connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$61 - connect \xer_ov \output_xer_ov - connect \xer_ov$23 \output_xer_ov$63 - connect \xer_ov_ok \output_xer_ov_ok + connect \o_ok$20 \output_o_ok$44 + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 + connect \sr_op__insn \output_sr_op__insn + connect \sr_op__insn$18 \output_sr_op__insn$42 + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 + connect \sr_op__invert_in \output_sr_op__invert_in + connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 + connect \sr_op__rc__ok \output_sr_op__rc__ok + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 + connect \sr_op__write_cr0 \output_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 + connect \xer_ca \output_xer_ca + connect \xer_ca$22 \output_xer_ca$46 + connect \xer_ca_ok \output_xer_ca_ok connect \xer_so \output_xer_so - connect \xer_so$24 \output_xer_so$64 - connect \xer_so_ok \output_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:160836.16-160888.4" - cell \output_stage \output_stage - connect \div_by_zero \output_stage_div_by_zero - connect \dive_abs_ov32 \output_stage_dive_abs_ov32 - connect \dive_abs_ov64 \output_stage_dive_abs_ov64 - connect \dividend_neg \output_stage_dividend_neg - connect \divisor_neg \output_stage_divisor_neg - connect \logical_op__data_len \output_stage_logical_op__data_len - connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 - connect \logical_op__fn_unit \output_stage_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \output_stage_logical_op__input_carry - connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 - connect \logical_op__insn \output_stage_logical_op__insn - connect \logical_op__insn$19 \output_stage_logical_op__insn$39 - connect \logical_op__insn_type \output_stage_logical_op__insn_type - connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 - connect \logical_op__invert_in \output_stage_logical_op__invert_in - connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 - connect \logical_op__invert_out \output_stage_logical_op__invert_out - connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 - connect \logical_op__is_32bit \output_stage_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 - connect \logical_op__is_signed \output_stage_logical_op__is_signed - connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 - connect \logical_op__oe__oe \output_stage_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 - connect \logical_op__oe__ok \output_stage_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 - connect \logical_op__output_carry \output_stage_logical_op__output_carry - connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 - connect \logical_op__rc__ok \output_stage_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 - connect \logical_op__rc__rc \output_stage_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 - connect \logical_op__zero_a \output_stage_logical_op__zero_a - connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 - connect \muxid \output_stage_muxid - connect \muxid$1 \output_stage_muxid$21 - connect \o \output_stage_o - connect \o_ok \output_stage_o_ok - connect \quotient_root \output_stage_quotient_root - connect \remainder \output_stage_remainder - connect \xer_ov \output_stage_xer_ov - connect \xer_ov_ok \output_stage_xer_ov_ok - connect \xer_so \output_stage_xer_so - connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:160889.10-160892.4" - cell \p$81 \p + attribute \src "libresoc.v:168542.11-168545.4" + cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:159593.7-159593.20" - process $proc$libresoc.v:159593$9592 + attribute \src "libresoc.v:167623.7-167623.20" + process $proc$libresoc.v:167623$9617 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159602.13-159602.24" - process $proc$libresoc.v:159602$9593 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:159611.7-159611.21" - process $proc$libresoc.v:159611$9594 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:159634.13-159634.45" - process $proc$libresoc.v:159634$9595 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$9596 4'0000 - sync always - sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9596 - end - attribute \src "libresoc.v:159669.14-159669.47" - process $proc$libresoc.v:159669$9597 + attribute \src "libresoc.v:167634.13-167634.29" + process $proc$libresoc.v:167634$9618 assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$9598 12'000000000000 + assign $0\cr_a$21[3:0]$9619 4'0000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9598 + update \cr_a$21 $0\cr_a$21[3:0]$9619 end - attribute \src "libresoc.v:159691.14-159691.67" - process $proc$libresoc.v:159691$9599 + attribute \src "libresoc.v:167643.7-167643.26" + process $proc$libresoc.v:167643$9620 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9600 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\cr_a_ok$22[0:0]$9621 1'0 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9600 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9621 end - attribute \src "libresoc.v:159700.7-159700.42" - process $proc$libresoc.v:159700$9601 + attribute \src "libresoc.v:167654.13-167654.29" + process $proc$libresoc.v:167654$9622 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9602 1'0 + assign $0\muxid$1[1:0]$9623 2'00 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9602 + update \muxid$1 $0\muxid$1[1:0]$9623 end - attribute \src "libresoc.v:159717.13-159717.48" - process $proc$libresoc.v:159717$9603 + attribute \src "libresoc.v:167669.14-167669.43" + process $proc$libresoc.v:167669$9624 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9604 2'00 + assign $0\o$19[63:0]$9625 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9604 + update \o$19 $0\o$19[63:0]$9625 end - attribute \src "libresoc.v:159730.14-159730.43" - process $proc$libresoc.v:159730$9605 + attribute \src "libresoc.v:167678.7-167678.23" + process $proc$libresoc.v:167678$9626 assign { } { } - assign $0\logical_op__insn$19[31:0]$9606 0 + assign $0\o_ok$20[0:0]$9627 1'0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9606 + update \o_ok$20 $0\o_ok$20[0:0]$9627 end - attribute \src "libresoc.v:159887.13-159887.46" - process $proc$libresoc.v:159887$9607 + attribute \src "libresoc.v:167974.7-167974.20" + process $proc$libresoc.v:167974$9628 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9608 7'0000000 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9608 + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:159970.7-159970.40" - process $proc$libresoc.v:159970$9609 + attribute \src "libresoc.v:168011.14-168011.43" + process $proc$libresoc.v:168011$9629 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9610 1'0 + assign $0\sr_op__fn_unit$3[13:0]$9630 14'00000000000000 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9610 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9630 end - attribute \src "libresoc.v:159979.7-159979.41" - process $proc$libresoc.v:159979$9611 + attribute \src "libresoc.v:168035.14-168035.62" + process $proc$libresoc.v:168035$9631 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9612 1'0 + assign $0\sr_op__imm_data__data$4[63:0]$9632 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9612 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9632 end - attribute \src "libresoc.v:159988.7-159988.39" - process $proc$libresoc.v:159988$9613 + attribute \src "libresoc.v:168044.7-168044.37" + process $proc$libresoc.v:168044$9633 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9614 1'0 + assign $0\sr_op__imm_data__ok$5[0:0]$9634 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9614 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9634 end - attribute \src "libresoc.v:159997.7-159997.40" - process $proc$libresoc.v:159997$9615 + attribute \src "libresoc.v:168061.13-168061.43" + process $proc$libresoc.v:168061$9635 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9616 1'0 + assign $0\sr_op__input_carry$12[1:0]$9636 2'00 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9616 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9636 end - attribute \src "libresoc.v:160006.7-160006.36" - process $proc$libresoc.v:160006$9617 + attribute \src "libresoc.v:168074.7-168074.34" + process $proc$libresoc.v:168074$9637 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9618 1'0 + assign $0\sr_op__input_cr$14[0:0]$9638 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9618 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9638 end - attribute \src "libresoc.v:160017.7-160017.36" - process $proc$libresoc.v:160017$9619 + attribute \src "libresoc.v:168083.14-168083.38" + process $proc$libresoc.v:168083$9639 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9620 1'0 + assign $0\sr_op__insn$18[31:0]$9640 0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9620 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9640 end - attribute \src "libresoc.v:160024.7-160024.43" - process $proc$libresoc.v:160024$9621 + attribute \src "libresoc.v:168242.13-168242.41" + process $proc$libresoc.v:168242$9641 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9622 1'0 + assign $0\sr_op__insn_type$2[6:0]$9642 7'0000000 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9622 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9642 end - attribute \src "libresoc.v:160033.7-160033.36" - process $proc$libresoc.v:160033$9623 + attribute \src "libresoc.v:168326.7-168326.35" + process $proc$libresoc.v:168326$9643 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9624 1'0 + assign $0\sr_op__invert_in$11[0:0]$9644 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9624 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9644 end - attribute \src "libresoc.v:160042.7-160042.36" - process $proc$libresoc.v:160042$9625 + attribute \src "libresoc.v:168335.7-168335.34" + process $proc$libresoc.v:168335$9645 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9626 1'0 + assign $0\sr_op__is_32bit$16[0:0]$9646 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9626 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9646 end - attribute \src "libresoc.v:160051.7-160051.40" - process $proc$libresoc.v:160051$9627 + attribute \src "libresoc.v:168344.7-168344.35" + process $proc$libresoc.v:168344$9647 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9628 1'0 + assign $0\sr_op__is_signed$17[0:0]$9648 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9628 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9648 end - attribute \src "libresoc.v:160060.7-160060.37" - process $proc$libresoc.v:160060$9629 + attribute \src "libresoc.v:168355.7-168355.31" + process $proc$libresoc.v:168355$9649 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9630 1'0 + assign $0\sr_op__oe__oe$8[0:0]$9650 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9630 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9650 end - attribute \src "libresoc.v:160069.13-160069.29" - process $proc$libresoc.v:160069$9631 + attribute \src "libresoc.v:168364.7-168364.31" + process $proc$libresoc.v:168364$9651 assign { } { } - assign $0\muxid$1[1:0]$9632 2'00 + assign $0\sr_op__oe__ok$9[0:0]$9652 1'0 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9632 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9652 end - attribute \src "libresoc.v:160082.14-160082.38" - process $proc$libresoc.v:160082$9633 + attribute \src "libresoc.v:168371.7-168371.38" + process $proc$libresoc.v:168371$9653 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\sr_op__output_carry$13[0:0]$9654 1'0 sync always sync init - update \o $1\o[63:0] + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9654 end - attribute \src "libresoc.v:160089.7-160089.18" - process $proc$libresoc.v:160089$9634 + attribute \src "libresoc.v:168380.7-168380.35" + process $proc$libresoc.v:168380$9655 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $0\sr_op__output_cr$15[0:0]$9656 1'0 sync always sync init - update \o_ok $1\o_ok[0:0] + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9656 end - attribute \src "libresoc.v:160673.7-160673.20" - process $proc$libresoc.v:160673$9635 + attribute \src "libresoc.v:168391.7-168391.31" + process $proc$libresoc.v:168391$9657 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\sr_op__rc__ok$7[0:0]$9658 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9658 end - attribute \src "libresoc.v:160688.13-160688.26" - process $proc$libresoc.v:160688$9636 + attribute \src "libresoc.v:168400.7-168400.31" + process $proc$libresoc.v:168400$9659 assign { } { } - assign $1\xer_ov[1:0] 2'00 + assign $0\sr_op__rc__rc$6[0:0]$9660 1'0 sync always sync init - update \xer_ov $1\xer_ov[1:0] + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9660 end - attribute \src "libresoc.v:160695.7-160695.23" - process $proc$libresoc.v:160695$9637 + attribute \src "libresoc.v:168407.7-168407.35" + process $proc$libresoc.v:168407$9661 assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 + assign $0\sr_op__write_cr0$10[0:0]$9662 1'0 sync always sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9662 end - attribute \src "libresoc.v:160708.7-160708.25" - process $proc$libresoc.v:160708$9638 + attribute \src "libresoc.v:168416.13-168416.31" + process $proc$libresoc.v:168416$9663 assign { } { } - assign $0\xer_so$20[0:0]$9639 1'0 + assign $0\xer_ca$23[1:0]$9664 2'00 sync always sync init - update \xer_so$20 $0\xer_so$20[0:0]$9639 + update \xer_ca$23 $0\xer_ca$23[1:0]$9664 end - attribute \src "libresoc.v:160713.7-160713.23" - process $proc$libresoc.v:160713$9640 + attribute \src "libresoc.v:168425.7-168425.28" + process $proc$libresoc.v:168425$9665 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 + assign $0\xer_ca_ok$24[0:0]$9666 1'0 sync always sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:160723.3-160724.37" - process $proc$libresoc.v:160723$9470 - assign { } { } - assign $0\xer_so$20[0:0]$9471 \xer_so$20$next - sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9471 - end - attribute \src "libresoc.v:160725.3-160726.35" - process $proc$libresoc.v:160725$9472 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:160727.3-160728.29" - process $proc$libresoc.v:160727$9473 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9666 end - attribute \src "libresoc.v:160729.3-160730.35" - process $proc$libresoc.v:160729$9474 + attribute \src "libresoc.v:168439.3-168440.37" + process $proc$libresoc.v:168439$9502 assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + assign $0\xer_ca$23[1:0]$9503 \xer_ca$23$next sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \xer_ca$23 $0\xer_ca$23[1:0]$9503 end - attribute \src "libresoc.v:160731.3-160732.25" - process $proc$libresoc.v:160731$9475 + attribute \src "libresoc.v:168441.3-168442.43" + process $proc$libresoc.v:168441$9504 assign { } { } - assign $0\cr_a[3:0] \cr_a$next + assign $0\xer_ca_ok$24[0:0]$9505 \xer_ca_ok$24$next sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9505 end - attribute \src "libresoc.v:160733.3-160734.31" - process $proc$libresoc.v:160733$9476 + attribute \src "libresoc.v:168443.3-168444.33" + process $proc$libresoc.v:168443$9506 assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next + assign $0\cr_a$21[3:0]$9507 \cr_a$21$next sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] + update \cr_a$21 $0\cr_a$21[3:0]$9507 end - attribute \src "libresoc.v:160735.3-160736.19" - process $proc$libresoc.v:160735$9477 + attribute \src "libresoc.v:168445.3-168446.39" + process $proc$libresoc.v:168445$9508 assign { } { } - assign $0\o[63:0] \o$next + assign $0\cr_a_ok$22[0:0]$9509 \cr_a_ok$22$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9509 end - attribute \src "libresoc.v:160737.3-160738.25" - process $proc$libresoc.v:160737$9478 + attribute \src "libresoc.v:168447.3-168448.27" + process $proc$libresoc.v:168447$9510 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\o$19[63:0]$9511 \o$19$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \o$19 $0\o$19[63:0]$9511 end - attribute \src "libresoc.v:160739.3-160740.65" - process $proc$libresoc.v:160739$9479 + attribute \src "libresoc.v:168449.3-168450.33" + process $proc$libresoc.v:168449$9512 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9480 \logical_op__insn_type$2$next + assign $0\o_ok$20[0:0]$9513 \o_ok$20$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9480 + update \o_ok$20 $0\o_ok$20[0:0]$9513 end - attribute \src "libresoc.v:160741.3-160742.61" - process $proc$libresoc.v:160741$9481 + attribute \src "libresoc.v:168451.3-168452.55" + process $proc$libresoc.v:168451$9514 assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$9482 \logical_op__fn_unit$3$next + assign $0\sr_op__insn_type$2[6:0]$9515 \sr_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9482 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9515 end - attribute \src "libresoc.v:160743.3-160744.75" - process $proc$libresoc.v:160743$9483 + attribute \src "libresoc.v:168453.3-168454.51" + process $proc$libresoc.v:168453$9516 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9484 \logical_op__imm_data__data$4$next + assign $0\sr_op__fn_unit$3[13:0]$9517 \sr_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9484 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9517 end - attribute \src "libresoc.v:160745.3-160746.71" - process $proc$libresoc.v:160745$9485 + attribute \src "libresoc.v:168455.3-168456.65" + process $proc$libresoc.v:168455$9518 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9486 \logical_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__data$4[63:0]$9519 \sr_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9486 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9519 end - attribute \src "libresoc.v:160747.3-160748.59" - process $proc$libresoc.v:160747$9487 + attribute \src "libresoc.v:168457.3-168458.61" + process $proc$libresoc.v:168457$9520 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9488 \logical_op__rc__rc$6$next + assign $0\sr_op__imm_data__ok$5[0:0]$9521 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9488 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9521 end - attribute \src "libresoc.v:160749.3-160750.59" - process $proc$libresoc.v:160749$9489 + attribute \src "libresoc.v:168459.3-168460.49" + process $proc$libresoc.v:168459$9522 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9490 \logical_op__rc__ok$7$next + assign $0\sr_op__rc__rc$6[0:0]$9523 \sr_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9490 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9523 end - attribute \src "libresoc.v:160751.3-160752.59" - process $proc$libresoc.v:160751$9491 + attribute \src "libresoc.v:168461.3-168462.49" + process $proc$libresoc.v:168461$9524 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9492 \logical_op__oe__oe$8$next + assign $0\sr_op__rc__ok$7[0:0]$9525 \sr_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9492 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9525 end - attribute \src "libresoc.v:160753.3-160754.59" - process $proc$libresoc.v:160753$9493 + attribute \src "libresoc.v:168463.3-168464.49" + process $proc$libresoc.v:168463$9526 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9494 \logical_op__oe__ok$9$next + assign $0\sr_op__oe__oe$8[0:0]$9527 \sr_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9494 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9527 end - attribute \src "libresoc.v:160755.3-160756.67" - process $proc$libresoc.v:160755$9495 + attribute \src "libresoc.v:168465.3-168466.49" + process $proc$libresoc.v:168465$9528 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9496 \logical_op__invert_in$10$next + assign $0\sr_op__oe__ok$9[0:0]$9529 \sr_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9496 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9529 end - attribute \src "libresoc.v:160757.3-160758.61" - process $proc$libresoc.v:160757$9497 + attribute \src "libresoc.v:168467.3-168468.57" + process $proc$libresoc.v:168467$9530 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9498 \logical_op__zero_a$11$next + assign $0\sr_op__write_cr0$10[0:0]$9531 \sr_op__write_cr0$10$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9498 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9531 end - attribute \src "libresoc.v:160759.3-160760.71" - process $proc$libresoc.v:160759$9499 + attribute \src "libresoc.v:168469.3-168470.57" + process $proc$libresoc.v:168469$9532 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9500 \logical_op__input_carry$12$next + assign $0\sr_op__invert_in$11[0:0]$9533 \sr_op__invert_in$11$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9500 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9533 end - attribute \src "libresoc.v:160761.3-160762.69" - process $proc$libresoc.v:160761$9501 + attribute \src "libresoc.v:168471.3-168472.61" + process $proc$libresoc.v:168471$9534 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9502 \logical_op__invert_out$13$next + assign $0\sr_op__input_carry$12[1:0]$9535 \sr_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9502 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9535 end - attribute \src "libresoc.v:160763.3-160764.67" - process $proc$libresoc.v:160763$9503 + attribute \src "libresoc.v:168473.3-168474.63" + process $proc$libresoc.v:168473$9536 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9504 \logical_op__write_cr0$14$next + assign $0\sr_op__output_carry$13[0:0]$9537 \sr_op__output_carry$13$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9504 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9537 end - attribute \src "libresoc.v:160765.3-160766.73" - process $proc$libresoc.v:160765$9505 + attribute \src "libresoc.v:168475.3-168476.55" + process $proc$libresoc.v:168475$9538 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9506 \logical_op__output_carry$15$next + assign $0\sr_op__input_cr$14[0:0]$9539 \sr_op__input_cr$14$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9506 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9539 end - attribute \src "libresoc.v:160767.3-160768.65" - process $proc$libresoc.v:160767$9507 + attribute \src "libresoc.v:168477.3-168478.57" + process $proc$libresoc.v:168477$9540 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9508 \logical_op__is_32bit$16$next + assign $0\sr_op__output_cr$15[0:0]$9541 \sr_op__output_cr$15$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9508 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9541 end - attribute \src "libresoc.v:160769.3-160770.67" - process $proc$libresoc.v:160769$9509 + attribute \src "libresoc.v:168479.3-168480.55" + process $proc$libresoc.v:168479$9542 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9510 \logical_op__is_signed$17$next + assign $0\sr_op__is_32bit$16[0:0]$9543 \sr_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9510 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9543 end - attribute \src "libresoc.v:160771.3-160772.65" - process $proc$libresoc.v:160771$9511 + attribute \src "libresoc.v:168481.3-168482.57" + process $proc$libresoc.v:168481$9544 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9512 \logical_op__data_len$18$next + assign $0\sr_op__is_signed$17[0:0]$9545 \sr_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9512 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9545 end - attribute \src "libresoc.v:160773.3-160774.57" - process $proc$libresoc.v:160773$9513 + attribute \src "libresoc.v:168483.3-168484.47" + process $proc$libresoc.v:168483$9546 assign { } { } - assign $0\logical_op__insn$19[31:0]$9514 \logical_op__insn$19$next + assign $0\sr_op__insn$18[31:0]$9547 \sr_op__insn$18$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9514 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9547 end - attribute \src "libresoc.v:160775.3-160776.33" - process $proc$libresoc.v:160775$9515 + attribute \src "libresoc.v:168485.3-168486.33" + process $proc$libresoc.v:168485$9548 assign { } { } - assign $0\muxid$1[1:0]$9516 \muxid$1$next + assign $0\muxid$1[1:0]$9549 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9516 + update \muxid$1 $0\muxid$1[1:0]$9549 end - attribute \src "libresoc.v:160777.3-160778.29" - process $proc$libresoc.v:160777$9517 + attribute \src "libresoc.v:168487.3-168488.29" + process $proc$libresoc.v:168487$9550 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:160893.3-160911.6" - process $proc$libresoc.v:160893$9518 + attribute \src "libresoc.v:168546.3-168563.6" + process $proc$libresoc.v:168546$9551 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\o$next[63:0]$9519 $1\o$next[63:0]$9521 - assign { } { } - assign $0\o_ok$next[0:0]$9520 $2\o_ok$next[0:0]$9523 - attribute \src "libresoc.v:160894.5-160894.29" + assign $0\r_busy$next[0:0]$9552 $2\r_busy$next[0:0]$9554 + attribute \src "libresoc.v:168547.5-168547.29" switch \initial - attribute \src "libresoc.v:160894.9-160894.17" + attribute \src "libresoc.v:168547.9-168547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$9522 $1\o$next[63:0]$9521 } { \o_ok$96 \o$95 } + assign $1\r_busy$next[0:0]$9553 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$9522 $1\o$next[63:0]$9521 } { \o_ok$96 \o$95 } + assign $1\r_busy$next[0:0]$9553 1'0 case - assign $1\o$next[63:0]$9521 \o - assign $1\o_ok$next[0:0]$9522 \o_ok + assign $1\r_busy$next[0:0]$9553 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9523 1'0 + assign $2\r_busy$next[0:0]$9554 1'0 case - assign $2\o_ok$next[0:0]$9523 $1\o_ok$next[0:0]$9522 + assign $2\r_busy$next[0:0]$9554 $1\r_busy$next[0:0]$9553 end sync always - update \o$next $0\o$next[63:0]$9519 - update \o_ok$next $0\o_ok$next[0:0]$9520 + update \r_busy$next $0\r_busy$next[0:0]$9552 end - attribute \src "libresoc.v:160912.3-160930.6" - process $proc$libresoc.v:160912$9524 + attribute \src "libresoc.v:168564.3-168576.6" + process $proc$libresoc.v:168564$9555 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$9525 $1\cr_a$next[3:0]$9527 - assign { } { } - assign $0\cr_a_ok$next[0:0]$9526 $2\cr_a_ok$next[0:0]$9529 - attribute \src "libresoc.v:160913.5-160913.29" + assign $0\muxid$1$next[1:0]$9556 $1\muxid$1$next[1:0]$9557 + attribute \src "libresoc.v:168565.5-168565.29" switch \initial - attribute \src "libresoc.v:160913.9-160913.17" + attribute \src "libresoc.v:168565.9-168565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$9528 $1\cr_a$next[3:0]$9527 } { \cr_a_ok$98 \cr_a$97 } + assign $1\muxid$1$next[1:0]$9557 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$9528 $1\cr_a$next[3:0]$9527 } { \cr_a_ok$98 \cr_a$97 } - case - assign $1\cr_a$next[3:0]$9527 \cr_a - assign $1\cr_a_ok$next[0:0]$9528 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$9529 1'0 + assign $1\muxid$1$next[1:0]$9557 \muxid$53 case - assign $2\cr_a_ok$next[0:0]$9529 $1\cr_a_ok$next[0:0]$9528 + assign $1\muxid$1$next[1:0]$9557 \muxid$1 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9525 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9526 + update \muxid$1$next $0\muxid$1$next[1:0]$9556 end - attribute \src "libresoc.v:160931.3-160949.6" - process $proc$libresoc.v:160931$9530 + attribute \src "libresoc.v:168577.3-168617.6" + process $proc$libresoc.v:168577$9558 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9531 $1\xer_ov$next[1:0]$9533 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9532 $2\xer_ov_ok$next[0:0]$9535 - attribute \src "libresoc.v:160932.5-160932.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$3$next[13:0]$9559 $1\sr_op__fn_unit$3$next[13:0]$9576 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$12$next[1:0]$9562 $1\sr_op__input_carry$12$next[1:0]$9579 + assign $0\sr_op__input_cr$14$next[0:0]$9563 $1\sr_op__input_cr$14$next[0:0]$9580 + assign $0\sr_op__insn$18$next[31:0]$9564 $1\sr_op__insn$18$next[31:0]$9581 + assign $0\sr_op__insn_type$2$next[6:0]$9565 $1\sr_op__insn_type$2$next[6:0]$9582 + assign $0\sr_op__invert_in$11$next[0:0]$9566 $1\sr_op__invert_in$11$next[0:0]$9583 + assign $0\sr_op__is_32bit$16$next[0:0]$9567 $1\sr_op__is_32bit$16$next[0:0]$9584 + assign $0\sr_op__is_signed$17$next[0:0]$9568 $1\sr_op__is_signed$17$next[0:0]$9585 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$13$next[0:0]$9571 $1\sr_op__output_carry$13$next[0:0]$9588 + assign $0\sr_op__output_cr$15$next[0:0]$9572 $1\sr_op__output_cr$15$next[0:0]$9589 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$10$next[0:0]$9575 $1\sr_op__write_cr0$10$next[0:0]$9592 + assign $0\sr_op__imm_data__data$4$next[63:0]$9560 $2\sr_op__imm_data__data$4$next[63:0]$9593 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9561 $2\sr_op__imm_data__ok$5$next[0:0]$9594 + assign $0\sr_op__oe__oe$8$next[0:0]$9569 $2\sr_op__oe__oe$8$next[0:0]$9595 + assign $0\sr_op__oe__ok$9$next[0:0]$9570 $2\sr_op__oe__ok$9$next[0:0]$9596 + assign $0\sr_op__rc__ok$7$next[0:0]$9573 $2\sr_op__rc__ok$7$next[0:0]$9597 + assign $0\sr_op__rc__rc$6$next[0:0]$9574 $2\sr_op__rc__rc$6$next[0:0]$9598 + attribute \src "libresoc.v:168578.5-168578.29" switch \initial - attribute \src "libresoc.v:160932.9-160932.17" + attribute \src "libresoc.v:168578.9-168578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9534 $1\xer_ov$next[1:0]$9533 } { \xer_ov_ok$100 \xer_ov$99 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9581 $1\sr_op__is_signed$17$next[0:0]$9585 $1\sr_op__is_32bit$16$next[0:0]$9584 $1\sr_op__output_cr$15$next[0:0]$9589 $1\sr_op__input_cr$14$next[0:0]$9580 $1\sr_op__output_carry$13$next[0:0]$9588 $1\sr_op__input_carry$12$next[1:0]$9579 $1\sr_op__invert_in$11$next[0:0]$9583 $1\sr_op__write_cr0$10$next[0:0]$9592 $1\sr_op__oe__ok$9$next[0:0]$9587 $1\sr_op__oe__oe$8$next[0:0]$9586 $1\sr_op__rc__ok$7$next[0:0]$9590 $1\sr_op__rc__rc$6$next[0:0]$9591 $1\sr_op__imm_data__ok$5$next[0:0]$9578 $1\sr_op__imm_data__data$4$next[63:0]$9577 $1\sr_op__fn_unit$3$next[13:0]$9576 $1\sr_op__insn_type$2$next[6:0]$9582 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9534 $1\xer_ov$next[1:0]$9533 } { \xer_ov_ok$100 \xer_ov$99 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9581 $1\sr_op__is_signed$17$next[0:0]$9585 $1\sr_op__is_32bit$16$next[0:0]$9584 $1\sr_op__output_cr$15$next[0:0]$9589 $1\sr_op__input_cr$14$next[0:0]$9580 $1\sr_op__output_carry$13$next[0:0]$9588 $1\sr_op__input_carry$12$next[1:0]$9579 $1\sr_op__invert_in$11$next[0:0]$9583 $1\sr_op__write_cr0$10$next[0:0]$9592 $1\sr_op__oe__ok$9$next[0:0]$9587 $1\sr_op__oe__oe$8$next[0:0]$9586 $1\sr_op__rc__ok$7$next[0:0]$9590 $1\sr_op__rc__rc$6$next[0:0]$9591 $1\sr_op__imm_data__ok$5$next[0:0]$9578 $1\sr_op__imm_data__data$4$next[63:0]$9577 $1\sr_op__fn_unit$3$next[13:0]$9576 $1\sr_op__insn_type$2$next[6:0]$9582 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case - assign $1\xer_ov$next[1:0]$9533 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9534 \xer_ov_ok + assign $1\sr_op__fn_unit$3$next[13:0]$9576 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9577 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9578 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9579 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9580 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9581 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9582 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9583 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9584 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9585 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9586 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9587 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9588 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9589 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9590 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9591 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9592 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9535 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$4$next[63:0]$9593 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9594 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9598 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9597 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9595 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9596 1'0 case - assign $2\xer_ov_ok$next[0:0]$9535 $1\xer_ov_ok$next[0:0]$9534 + assign $2\sr_op__imm_data__data$4$next[63:0]$9593 $1\sr_op__imm_data__data$4$next[63:0]$9577 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9594 $1\sr_op__imm_data__ok$5$next[0:0]$9578 + assign $2\sr_op__oe__oe$8$next[0:0]$9595 $1\sr_op__oe__oe$8$next[0:0]$9586 + assign $2\sr_op__oe__ok$9$next[0:0]$9596 $1\sr_op__oe__ok$9$next[0:0]$9587 + assign $2\sr_op__rc__ok$7$next[0:0]$9597 $1\sr_op__rc__ok$7$next[0:0]$9590 + assign $2\sr_op__rc__rc$6$next[0:0]$9598 $1\sr_op__rc__rc$6$next[0:0]$9591 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9531 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9532 + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9559 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9560 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9561 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9562 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9563 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9564 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9565 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9566 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9567 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9568 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9569 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9570 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9571 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9572 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9573 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9574 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9575 end - attribute \src "libresoc.v:160950.3-160968.6" - process $proc$libresoc.v:160950$9536 + attribute \src "libresoc.v:168618.3-168636.6" + process $proc$libresoc.v:168618$9599 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\o$19$next[63:0]$9600 $1\o$19$next[63:0]$9602 assign { } { } - assign $0\xer_so$20$next[0:0]$9538 $1\xer_so$20$next[0:0]$9540 - assign $0\xer_so_ok$next[0:0]$9537 $2\xer_so_ok$next[0:0]$9541 - attribute \src "libresoc.v:160951.5-160951.29" + assign $0\o_ok$20$next[0:0]$9601 $2\o_ok$20$next[0:0]$9604 + attribute \src "libresoc.v:168619.5-168619.29" switch \initial - attribute \src "libresoc.v:160951.9-160951.17" + attribute \src "libresoc.v:168619.9-168619.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9539 $1\xer_so$20$next[0:0]$9540 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\o_ok$20$next[0:0]$9603 $1\o$19$next[63:0]$9602 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9539 $1\xer_so$20$next[0:0]$9540 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\o_ok$20$next[0:0]$9603 $1\o$19$next[63:0]$9602 } { \o_ok$72 \o$71 } case - assign $1\xer_so_ok$next[0:0]$9539 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9540 \xer_so$20 + assign $1\o$19$next[63:0]$9602 \o$19 + assign $1\o_ok$20$next[0:0]$9603 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9541 1'0 + assign $2\o_ok$20$next[0:0]$9604 1'0 case - assign $2\xer_so_ok$next[0:0]$9541 $1\xer_so_ok$next[0:0]$9539 + assign $2\o_ok$20$next[0:0]$9604 $1\o_ok$20$next[0:0]$9603 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9537 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9538 + update \o$19$next $0\o$19$next[63:0]$9600 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9601 end - attribute \src "libresoc.v:160969.3-160986.6" - process $proc$libresoc.v:160969$9542 + attribute \src "libresoc.v:168637.3-168655.6" + process $proc$libresoc.v:168637$9605 + assign { } { } + assign { } { } assign { } { } assign { } { } + assign $0\cr_a$21$next[3:0]$9606 $1\cr_a$21$next[3:0]$9608 assign { } { } - assign $0\r_busy$next[0:0]$9543 $2\r_busy$next[0:0]$9545 - attribute \src "libresoc.v:160970.5-160970.29" + assign $0\cr_a_ok$22$next[0:0]$9607 $2\cr_a_ok$22$next[0:0]$9610 + attribute \src "libresoc.v:168638.5-168638.29" switch \initial - attribute \src "libresoc.v:160970.9-160970.17" + attribute \src "libresoc.v:168638.9-168638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9544 1'1 + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9609 $1\cr_a$21$next[3:0]$9608 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9544 1'0 + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9609 $1\cr_a$21$next[3:0]$9608 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\r_busy$next[0:0]$9544 \r_busy + assign $1\cr_a$21$next[3:0]$9608 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9609 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9545 1'0 - case - assign $2\r_busy$next[0:0]$9545 $1\r_busy$next[0:0]$9544 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$9543 - end - attribute \src "libresoc.v:160987.3-160999.6" - process $proc$libresoc.v:160987$9546 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$9547 $1\muxid$1$next[1:0]$9548 - attribute \src "libresoc.v:160988.5-160988.29" - switch \initial - attribute \src "libresoc.v:160988.9-160988.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$9548 \muxid$76 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$9548 \muxid$76 + assign $2\cr_a_ok$22$next[0:0]$9610 1'0 case - assign $1\muxid$1$next[1:0]$9548 \muxid$1 + assign $2\cr_a_ok$22$next[0:0]$9610 $1\cr_a_ok$22$next[0:0]$9609 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9547 + update \cr_a$21$next $0\cr_a$21$next[3:0]$9606 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9607 end - attribute \src "libresoc.v:161000.3-161041.6" - process $proc$libresoc.v:161000$9549 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:168656.3-168674.6" + process $proc$libresoc.v:168656$9611 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\xer_ca$23$next[1:0]$9612 $1\xer_ca$23$next[1:0]$9614 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9550 $1\logical_op__data_len$18$next[3:0]$9568 - assign $0\logical_op__fn_unit$3$next[11:0]$9551 $1\logical_op__fn_unit$3$next[11:0]$9569 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9554 $1\logical_op__input_carry$12$next[1:0]$9572 - assign $0\logical_op__insn$19$next[31:0]$9555 $1\logical_op__insn$19$next[31:0]$9573 - assign $0\logical_op__insn_type$2$next[6:0]$9556 $1\logical_op__insn_type$2$next[6:0]$9574 - assign $0\logical_op__invert_in$10$next[0:0]$9557 $1\logical_op__invert_in$10$next[0:0]$9575 - assign $0\logical_op__invert_out$13$next[0:0]$9558 $1\logical_op__invert_out$13$next[0:0]$9576 - assign $0\logical_op__is_32bit$16$next[0:0]$9559 $1\logical_op__is_32bit$16$next[0:0]$9577 - assign $0\logical_op__is_signed$17$next[0:0]$9560 $1\logical_op__is_signed$17$next[0:0]$9578 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9563 $1\logical_op__output_carry$15$next[0:0]$9581 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9566 $1\logical_op__write_cr0$14$next[0:0]$9584 - assign $0\logical_op__zero_a$11$next[0:0]$9567 $1\logical_op__zero_a$11$next[0:0]$9585 - assign $0\logical_op__imm_data__data$4$next[63:0]$9552 $2\logical_op__imm_data__data$4$next[63:0]$9586 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9553 $2\logical_op__imm_data__ok$5$next[0:0]$9587 - assign $0\logical_op__oe__oe$8$next[0:0]$9561 $2\logical_op__oe__oe$8$next[0:0]$9588 - assign $0\logical_op__oe__ok$9$next[0:0]$9562 $2\logical_op__oe__ok$9$next[0:0]$9589 - assign $0\logical_op__rc__ok$7$next[0:0]$9564 $2\logical_op__rc__ok$7$next[0:0]$9590 - assign $0\logical_op__rc__rc$6$next[0:0]$9565 $2\logical_op__rc__rc$6$next[0:0]$9591 - attribute \src "libresoc.v:161001.5-161001.29" + assign $0\xer_ca_ok$24$next[0:0]$9613 $2\xer_ca_ok$24$next[0:0]$9616 + attribute \src "libresoc.v:168657.5-168657.29" switch \initial - attribute \src "libresoc.v:161001.9-161001.17" + attribute \src "libresoc.v:168657.9-168657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9573 $1\logical_op__data_len$18$next[3:0]$9568 $1\logical_op__is_signed$17$next[0:0]$9578 $1\logical_op__is_32bit$16$next[0:0]$9577 $1\logical_op__output_carry$15$next[0:0]$9581 $1\logical_op__write_cr0$14$next[0:0]$9584 $1\logical_op__invert_out$13$next[0:0]$9576 $1\logical_op__input_carry$12$next[1:0]$9572 $1\logical_op__zero_a$11$next[0:0]$9585 $1\logical_op__invert_in$10$next[0:0]$9575 $1\logical_op__oe__ok$9$next[0:0]$9580 $1\logical_op__oe__oe$8$next[0:0]$9579 $1\logical_op__rc__ok$7$next[0:0]$9582 $1\logical_op__rc__rc$6$next[0:0]$9583 $1\logical_op__imm_data__ok$5$next[0:0]$9571 $1\logical_op__imm_data__data$4$next[63:0]$9570 $1\logical_op__fn_unit$3$next[11:0]$9569 $1\logical_op__insn_type$2$next[6:0]$9574 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\xer_ca_ok$24$next[0:0]$9615 $1\xer_ca$23$next[1:0]$9614 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9573 $1\logical_op__data_len$18$next[3:0]$9568 $1\logical_op__is_signed$17$next[0:0]$9578 $1\logical_op__is_32bit$16$next[0:0]$9577 $1\logical_op__output_carry$15$next[0:0]$9581 $1\logical_op__write_cr0$14$next[0:0]$9584 $1\logical_op__invert_out$13$next[0:0]$9576 $1\logical_op__input_carry$12$next[1:0]$9572 $1\logical_op__zero_a$11$next[0:0]$9585 $1\logical_op__invert_in$10$next[0:0]$9575 $1\logical_op__oe__ok$9$next[0:0]$9580 $1\logical_op__oe__oe$8$next[0:0]$9579 $1\logical_op__rc__ok$7$next[0:0]$9582 $1\logical_op__rc__rc$6$next[0:0]$9583 $1\logical_op__imm_data__ok$5$next[0:0]$9571 $1\logical_op__imm_data__data$4$next[63:0]$9570 $1\logical_op__fn_unit$3$next[11:0]$9569 $1\logical_op__insn_type$2$next[6:0]$9574 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\xer_ca_ok$24$next[0:0]$9615 $1\xer_ca$23$next[1:0]$9614 } { \xer_ca_ok$76 \xer_ca$75 } case - assign $1\logical_op__data_len$18$next[3:0]$9568 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[11:0]$9569 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9570 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9571 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9572 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9573 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9574 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9575 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9576 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9577 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9578 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9579 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9580 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9581 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9582 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9583 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9584 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9585 \logical_op__zero_a$11 + assign $1\xer_ca$23$next[1:0]$9614 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9615 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9586 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9587 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9591 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9590 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9588 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9589 1'0 + assign $2\xer_ca_ok$24$next[0:0]$9616 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$9586 $1\logical_op__imm_data__data$4$next[63:0]$9570 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9587 $1\logical_op__imm_data__ok$5$next[0:0]$9571 - assign $2\logical_op__oe__oe$8$next[0:0]$9588 $1\logical_op__oe__oe$8$next[0:0]$9579 - assign $2\logical_op__oe__ok$9$next[0:0]$9589 $1\logical_op__oe__ok$9$next[0:0]$9580 - assign $2\logical_op__rc__ok$7$next[0:0]$9590 $1\logical_op__rc__ok$7$next[0:0]$9582 - assign $2\logical_op__rc__rc$6$next[0:0]$9591 $1\logical_op__rc__rc$6$next[0:0]$9583 + assign $2\xer_ca_ok$24$next[0:0]$9616 $1\xer_ca_ok$24$next[0:0]$9615 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9550 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$9551 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9552 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9553 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9554 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9555 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9556 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9557 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9558 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9559 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9560 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9561 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9562 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9563 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9564 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9565 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9566 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9567 + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9612 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9613 end - connect \$74 $and$libresoc.v:160722$9469_Y - connect \cr_a$68 4'0000 - connect \cr_a_ok$69 1'0 - connect \xer_so_ok$72 1'0 + connect \$51 $and$libresoc.v:168438$9501_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } - connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } - connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } - connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } - connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } - connect \muxid$76 \output_muxid$41 - connect \p_valid_i_p_ready_o \$74 + connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } + connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } + connect \muxid$53 \output_muxid$25 + connect \p_valid_i_p_ready_o \$51 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$73 \p_valid_i - connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } - connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } - connect { \cr_a_ok$67 \output_cr_a } 5'00000 - connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } - connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } - connect \output_muxid \output_stage_muxid$21 - connect \output_stage_remainder \remainder - connect \output_stage_quotient_root \quotient_root - connect \output_stage_div_by_zero \div_by_zero - connect \output_stage_dive_abs_ov64 \dive_abs_ov64 - connect \output_stage_dive_abs_ov32 \dive_abs_ov32 - connect \output_stage_dividend_neg \dividend_neg - connect \output_stage_divisor_neg \divisor_neg - connect \output_stage_xer_so \xer_so - connect \rb$66 \rb - connect \ra$65 \ra - connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \output_stage_muxid \muxid + connect \p_valid_i$50 \p_valid_i + connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \output_muxid \muxid end -attribute \src "libresoc.v:161078.1-162056.10" +attribute \src "libresoc.v:168695.1-169659.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" -module \pipe_middle_0 - attribute \src "libresoc.v:161981.3-161995.6" - wire $0\div_by_zero$54$next[0:0]$9820 - attribute \src "libresoc.v:161655.3-161656.47" - wire $0\div_by_zero$54[0:0]$9655 - attribute \src "libresoc.v:161101.7-161101.30" - wire $0\div_by_zero$54[0:0]$9837 - attribute \src "libresoc.v:161777.3-161788.6" - wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:161765.3-161776.6" - wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:161753.3-161764.6" - wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:161951.3-161965.6" - wire $0\dive_abs_ov32$52$next[0:0]$9812 - attribute \src "libresoc.v:161659.3-161660.51" - wire $0\dive_abs_ov32$52[0:0]$9659 - attribute \src "libresoc.v:161125.7-161125.32" - wire $0\dive_abs_ov32$52[0:0]$9839 - attribute \src "libresoc.v:161966.3-161980.6" - wire $0\dive_abs_ov64$53$next[0:0]$9816 - attribute \src "libresoc.v:161657.3-161658.51" - wire $0\dive_abs_ov64$53[0:0]$9657 - attribute \src "libresoc.v:161133.7-161133.32" - wire $0\dive_abs_ov64$53[0:0]$9841 - attribute \src "libresoc.v:161996.3-162010.6" - wire width 128 $0\dividend$68$next[127:0]$9824 - attribute \src "libresoc.v:161653.3-161654.41" - wire width 128 $0\dividend$68[127:0]$9653 - attribute \src "libresoc.v:161139.15-161139.68" - wire width 128 $0\dividend$68[127:0]$9843 - attribute \src "libresoc.v:161936.3-161950.6" - wire $0\dividend_neg$51$next[0:0]$9808 - attribute \src "libresoc.v:161661.3-161662.49" - wire $0\dividend_neg$51[0:0]$9661 - attribute \src "libresoc.v:161147.7-161147.31" - wire $0\dividend_neg$51[0:0]$9845 - attribute \src "libresoc.v:161921.3-161935.6" - wire $0\divisor_neg$50$next[0:0]$9804 - attribute \src "libresoc.v:161663.3-161664.47" - wire $0\divisor_neg$50[0:0]$9663 - attribute \src "libresoc.v:161155.7-161155.30" - wire $0\divisor_neg$50[0:0]$9847 - attribute \src "libresoc.v:162011.3-162025.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$9828 - attribute \src "libresoc.v:161651.3-161652.57" - wire width 64 $0\divisor_radicand$65[63:0]$9651 - attribute \src "libresoc.v:161161.14-161161.58" - wire width 64 $0\divisor_radicand$65[63:0]$9849 - attribute \src "libresoc.v:161789.3-161816.6" - wire $0\empty$next[0:0]$9721 - attribute \src "libresoc.v:161709.3-161710.27" - wire $0\empty[0:0] - attribute \src "libresoc.v:161079.7-161079.20" +module \pipe2$35 + attribute \src "libresoc.v:169565.3-169583.6" + wire width 64 $0\fast1$11$next[63:0]$9735 + attribute \src "libresoc.v:169414.3-169415.35" + wire width 64 $0\fast1$11[63:0]$9673 + attribute \src "libresoc.v:168707.14-168707.47" + wire width 64 $0\fast1$11[63:0]$9759 + attribute \src "libresoc.v:169565.3-169583.6" + wire $0\fast1_ok$next[0:0]$9734 + attribute \src "libresoc.v:169416.3-169417.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:169584.3-169602.6" + wire width 64 $0\fast2$12$next[63:0]$9741 + attribute \src "libresoc.v:169410.3-169411.35" + wire width 64 $0\fast2$12[63:0]$9670 + attribute \src "libresoc.v:168723.14-168723.47" + wire width 64 $0\fast2$12[63:0]$9762 + attribute \src "libresoc.v:169584.3-169602.6" + wire $0\fast2_ok$next[0:0]$9740 + attribute \src "libresoc.v:169412.3-169413.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:168696.7-168696.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161832.3-161875.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$9731 - attribute \src "libresoc.v:161703.3-161704.65" - wire width 4 $0\logical_op__data_len$45[3:0]$9703 - attribute \src "libresoc.v:161173.13-161173.45" - wire width 4 $0\logical_op__data_len$45[3:0]$9852 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 12 $0\logical_op__fn_unit$30$next[11:0]$9732 - attribute \src "libresoc.v:161673.3-161674.63" - wire width 12 $0\logical_op__fn_unit$30[11:0]$9673 - attribute \src "libresoc.v:161220.14-161220.48" - wire width 12 $0\logical_op__fn_unit$30[11:0]$9854 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$9733 - attribute \src "libresoc.v:161675.3-161676.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9675 - attribute \src "libresoc.v:161226.14-161226.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9856 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$9734 - attribute \src "libresoc.v:161677.3-161678.73" - wire $0\logical_op__imm_data__ok$32[0:0]$9677 - attribute \src "libresoc.v:161234.7-161234.43" - wire $0\logical_op__imm_data__ok$32[0:0]$9858 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$9735 - attribute \src "libresoc.v:161691.3-161692.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$9691 - attribute \src "libresoc.v:161256.13-161256.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$9860 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$9736 - attribute \src "libresoc.v:161705.3-161706.57" - wire width 32 $0\logical_op__insn$46[31:0]$9705 - attribute \src "libresoc.v:161264.14-161264.43" - wire width 32 $0\logical_op__insn$46[31:0]$9862 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$9737 - attribute \src "libresoc.v:161671.3-161672.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$9671 - attribute \src "libresoc.v:161494.13-161494.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$9864 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__invert_in$37$next[0:0]$9738 - attribute \src "libresoc.v:161687.3-161688.67" - wire $0\logical_op__invert_in$37[0:0]$9687 - attribute \src "libresoc.v:161502.7-161502.40" - wire $0\logical_op__invert_in$37[0:0]$9866 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__invert_out$40$next[0:0]$9739 - attribute \src "libresoc.v:161693.3-161694.69" - wire $0\logical_op__invert_out$40[0:0]$9693 - attribute \src "libresoc.v:161510.7-161510.41" - wire $0\logical_op__invert_out$40[0:0]$9868 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__is_32bit$43$next[0:0]$9740 - attribute \src "libresoc.v:161699.3-161700.65" - wire $0\logical_op__is_32bit$43[0:0]$9699 - attribute \src "libresoc.v:161518.7-161518.39" - wire $0\logical_op__is_32bit$43[0:0]$9870 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__is_signed$44$next[0:0]$9741 - attribute \src "libresoc.v:161701.3-161702.67" - wire $0\logical_op__is_signed$44[0:0]$9701 - attribute \src "libresoc.v:161526.7-161526.40" - wire $0\logical_op__is_signed$44[0:0]$9872 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__oe__oe$35$next[0:0]$9742 - attribute \src "libresoc.v:161683.3-161684.61" - wire $0\logical_op__oe__oe$35[0:0]$9683 - attribute \src "libresoc.v:161532.7-161532.37" - wire $0\logical_op__oe__oe$35[0:0]$9874 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__oe__ok$36$next[0:0]$9743 - attribute \src "libresoc.v:161685.3-161686.61" - wire $0\logical_op__oe__ok$36[0:0]$9685 - attribute \src "libresoc.v:161540.7-161540.37" - wire $0\logical_op__oe__ok$36[0:0]$9876 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__output_carry$42$next[0:0]$9744 - attribute \src "libresoc.v:161697.3-161698.73" - wire $0\logical_op__output_carry$42[0:0]$9697 - attribute \src "libresoc.v:161550.7-161550.43" - wire $0\logical_op__output_carry$42[0:0]$9878 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__rc__ok$34$next[0:0]$9745 - attribute \src "libresoc.v:161681.3-161682.61" - wire $0\logical_op__rc__ok$34[0:0]$9681 - attribute \src "libresoc.v:161556.7-161556.37" - wire $0\logical_op__rc__ok$34[0:0]$9880 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__rc__rc$33$next[0:0]$9746 - attribute \src "libresoc.v:161679.3-161680.61" - wire $0\logical_op__rc__rc$33[0:0]$9679 - attribute \src "libresoc.v:161564.7-161564.37" - wire $0\logical_op__rc__rc$33[0:0]$9882 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__write_cr0$41$next[0:0]$9747 - attribute \src "libresoc.v:161695.3-161696.67" - wire $0\logical_op__write_cr0$41[0:0]$9695 - attribute \src "libresoc.v:161574.7-161574.40" - wire $0\logical_op__write_cr0$41[0:0]$9884 - attribute \src "libresoc.v:161832.3-161875.6" - wire $0\logical_op__zero_a$38$next[0:0]$9748 - attribute \src "libresoc.v:161689.3-161690.61" - wire $0\logical_op__zero_a$38[0:0]$9689 - attribute \src "libresoc.v:161582.7-161582.37" - wire $0\logical_op__zero_a$38[0:0]$9886 - attribute \src "libresoc.v:161817.3-161831.6" - wire width 2 $0\muxid$28$next[1:0]$9727 - attribute \src "libresoc.v:161707.3-161708.35" - wire width 2 $0\muxid$28[1:0]$9707 - attribute \src "libresoc.v:161590.13-161590.30" - wire width 2 $0\muxid$28[1:0]$9888 - attribute \src "libresoc.v:162026.3-162040.6" - wire width 2 $0\operation$69$next[1:0]$9832 - attribute \src "libresoc.v:161649.3-161650.43" - wire width 2 $0\operation$69[1:0]$9649 - attribute \src "libresoc.v:161600.13-161600.34" - wire width 2 $0\operation$69[1:0]$9890 - attribute \src "libresoc.v:161876.3-161890.6" - wire width 64 $0\ra$47$next[63:0]$9792 - attribute \src "libresoc.v:161669.3-161670.29" - wire width 64 $0\ra$47[63:0]$9669 - attribute \src "libresoc.v:161614.14-161614.44" - wire width 64 $0\ra$47[63:0]$9892 - attribute \src "libresoc.v:161891.3-161905.6" - wire width 64 $0\rb$48$next[63:0]$9796 - attribute \src "libresoc.v:161667.3-161668.29" - wire width 64 $0\rb$48[63:0]$9667 - attribute \src "libresoc.v:161622.14-161622.44" - wire width 64 $0\rb$48[63:0]$9894 - attribute \src "libresoc.v:161744.3-161752.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$9715 - attribute \src "libresoc.v:161711.3-161712.75" - wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:161735.3-161743.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$9712 - attribute \src "libresoc.v:161713.3-161714.65" - wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:161906.3-161920.6" - wire $0\xer_so$49$next[0:0]$9800 - attribute \src "libresoc.v:161665.3-161666.37" - wire $0\xer_so$49[0:0]$9665 - attribute \src "libresoc.v:161640.7-161640.25" - wire $0\xer_so$49[0:0]$9898 - attribute \src "libresoc.v:161981.3-161995.6" - wire $1\div_by_zero$54$next[0:0]$9821 - attribute \src "libresoc.v:161777.3-161788.6" - wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:161765.3-161776.6" - wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:161753.3-161764.6" - wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:161951.3-161965.6" - wire $1\dive_abs_ov32$52$next[0:0]$9813 - attribute \src "libresoc.v:161966.3-161980.6" - wire $1\dive_abs_ov64$53$next[0:0]$9817 - attribute \src "libresoc.v:161996.3-162010.6" - wire width 128 $1\dividend$68$next[127:0]$9825 - attribute \src "libresoc.v:161936.3-161950.6" - wire $1\dividend_neg$51$next[0:0]$9809 - attribute \src "libresoc.v:161921.3-161935.6" - wire $1\divisor_neg$50$next[0:0]$9805 - attribute \src "libresoc.v:162011.3-162025.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$9829 - attribute \src "libresoc.v:161789.3-161816.6" - wire $1\empty$next[0:0]$9722 - attribute \src "libresoc.v:161165.7-161165.19" - wire $1\empty[0:0] - attribute \src "libresoc.v:161832.3-161875.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$9749 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 12 $1\logical_op__fn_unit$30$next[11:0]$9750 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$9751 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$9752 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$9753 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$9754 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$9755 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__invert_in$37$next[0:0]$9756 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__invert_out$40$next[0:0]$9757 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__is_32bit$43$next[0:0]$9758 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__is_signed$44$next[0:0]$9759 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__oe__oe$35$next[0:0]$9760 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__oe__ok$36$next[0:0]$9761 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__output_carry$42$next[0:0]$9762 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__rc__ok$34$next[0:0]$9763 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__rc__rc$33$next[0:0]$9764 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__write_cr0$41$next[0:0]$9765 - attribute \src "libresoc.v:161832.3-161875.6" - wire $1\logical_op__zero_a$38$next[0:0]$9766 - attribute \src "libresoc.v:161817.3-161831.6" - wire width 2 $1\muxid$28$next[1:0]$9728 - attribute \src "libresoc.v:162026.3-162040.6" - wire width 2 $1\operation$69$next[1:0]$9833 - attribute \src "libresoc.v:161876.3-161890.6" - wire width 64 $1\ra$47$next[63:0]$9793 - attribute \src "libresoc.v:161891.3-161905.6" - wire width 64 $1\rb$48$next[63:0]$9797 - attribute \src "libresoc.v:161744.3-161752.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$9716 - attribute \src "libresoc.v:161628.15-161628.84" - wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:161735.3-161743.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$9713 - attribute \src "libresoc.v:161632.13-161632.45" - wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:161906.3-161920.6" - wire $1\xer_so$49$next[0:0]$9801 - attribute \src "libresoc.v:161981.3-161995.6" - wire $2\div_by_zero$54$next[0:0]$9822 - attribute \src "libresoc.v:161951.3-161965.6" - wire $2\dive_abs_ov32$52$next[0:0]$9814 - attribute \src "libresoc.v:161966.3-161980.6" - wire $2\dive_abs_ov64$53$next[0:0]$9818 - attribute \src "libresoc.v:161996.3-162010.6" - wire width 128 $2\dividend$68$next[127:0]$9826 - attribute \src "libresoc.v:161936.3-161950.6" - wire $2\dividend_neg$51$next[0:0]$9810 - attribute \src "libresoc.v:161921.3-161935.6" - wire $2\divisor_neg$50$next[0:0]$9806 - attribute \src "libresoc.v:162011.3-162025.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$9830 - attribute \src "libresoc.v:161789.3-161816.6" - wire $2\empty$next[0:0]$9723 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$9767 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 12 $2\logical_op__fn_unit$30$next[11:0]$9768 - attribute \src "libresoc.v:161832.3-161875.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$9769 - attribute \src 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attribute \src "libresoc.v:161832.3-161875.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$9785 - attribute \src "libresoc.v:161832.3-161875.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$9786 - attribute \src "libresoc.v:161832.3-161875.6" - wire $3\logical_op__oe__oe$35$next[0:0]$9787 - attribute \src "libresoc.v:161832.3-161875.6" - wire $3\logical_op__oe__ok$36$next[0:0]$9788 - attribute \src "libresoc.v:161832.3-161875.6" - wire $3\logical_op__rc__ok$34$next[0:0]$9789 - attribute \src "libresoc.v:161832.3-161875.6" - wire $3\logical_op__rc__rc$33$next[0:0]$9790 - attribute \src "libresoc.v:161789.3-161816.6" - wire $4\empty$next[0:0]$9725 - attribute \src "libresoc.v:161647.18-161647.98" - wire $and$libresoc.v:161647$9646_Y - attribute \src "libresoc.v:161648.18-161648.107" - wire $and$libresoc.v:161648$9647_Y - attribute \src "libresoc.v:161644.18-161644.92" - wire width 192 $extend$libresoc.v:161644$9642_Y - attribute \src "libresoc.v:161646.18-161646.119" - wire $ge$libresoc.v:161646$9645_Y - attribute \src "libresoc.v:161645.18-161645.93" - wire $not$libresoc.v:161645$9644_Y - attribute \src "libresoc.v:161644.18-161644.92" - wire width 192 $pos$libresoc.v:161644$9643_Y - attribute \src "libresoc.v:161643.18-161643.138" - wire width 191 $sshl$libresoc.v:161643$9641_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - wire width 192 \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - wire width 191 \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "libresoc.v:169622.3-169640.6" + wire width 64 $0\msr$next[63:0]$9752 + attribute \src "libresoc.v:169444.3-169445.23" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:169622.3-169640.6" + wire $0\msr_ok$next[0:0]$9753 + attribute \src "libresoc.v:169446.3-169447.29" + wire $0\msr_ok[0:0] + attribute \src "libresoc.v:169512.3-169524.6" + wire width 2 $0\muxid$1$next[1:0]$9706 + attribute \src "libresoc.v:169440.3-169441.33" + wire width 2 $0\muxid$1[1:0]$9696 + attribute \src "libresoc.v:169001.13-169001.29" + wire width 2 $0\muxid$1[1:0]$9767 + attribute \src "libresoc.v:169603.3-169621.6" + wire width 64 $0\nia$next[63:0]$9746 + attribute \src "libresoc.v:169448.3-169449.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:169603.3-169621.6" + wire $0\nia_ok$next[0:0]$9747 + attribute \src "libresoc.v:169408.3-169409.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:169546.3-169564.6" + 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attribute \src "libresoc.v:169525.3-169545.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$9711 + attribute \src "libresoc.v:169426.3-169427.49" + wire width 32 $0\trap_op__insn$4[31:0]$9682 + attribute \src "libresoc.v:169125.14-169125.39" + wire width 32 $0\trap_op__insn$4[31:0]$9778 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$9712 + attribute \src "libresoc.v:169422.3-169423.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$9678 + attribute \src "libresoc.v:169282.13-169282.43" + wire width 7 $0\trap_op__insn_type$2[6:0]$9780 + attribute \src "libresoc.v:169525.3-169545.6" + wire $0\trap_op__is_32bit$7$next[0:0]$9713 + attribute \src "libresoc.v:169432.3-169433.57" + wire $0\trap_op__is_32bit$7[0:0]$9688 + attribute \src "libresoc.v:169368.7-169368.35" + wire $0\trap_op__is_32bit$7[0:0]$9782 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9714 + attribute \src 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" - wire width 128 \div_state_init_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_init_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_init_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" - wire width 64 \div_state_next_divisor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_next_i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_next_i_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_next_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_next_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 60 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$52$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 61 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$53$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 input 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 59 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$51$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 58 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$50$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 input 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" - wire \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" - wire \empty$next - attribute \src "libresoc.v:161079.7-161079.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 32 \fast1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 34 \fast2$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 35 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$next + attribute \src "libresoc.v:168696.7-168696.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast1$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast2$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast2_ok + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 53 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45 + wire width 64 \main_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit + wire width 64 \main_trap_op__cia$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 38 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$30$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_trap_op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data + wire width 32 \main_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31 + wire width 32 \main_trap_op__insn$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31$next + wire width 7 \main_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 39 \logical_op__imm_data__data$4 + wire width 7 \main_trap_op__insn_type$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok + wire \main_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$32 + wire \main_trap_op__is_32bit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$32$next + wire width 8 \main_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 8 \main_trap_op__ldst_exc$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 \main_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 47 \logical_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 \main_trap_op__msr$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39 + wire width 13 \main_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39$next + wire width 13 \main_trap_op__trapaddr$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn + wire width 8 \main_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 54 \logical_op__insn$19 + wire width 8 \main_trap_op__traptype$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 19 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 18 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 30 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46 + wire width 64 input 9 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46$next + wire width 64 \trap_op__cia$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$6$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 22 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 23 \trap_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -333229,8 +348347,9 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type + wire width 7 input 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -333305,8 +348424,11 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 37 \logical_op__insn_type$2 + wire width 7 output 21 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -333381,965 +348503,499 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$37$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$40$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$43$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 52 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$44$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$35$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$36$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__oe__ok$9 + wire width 7 \trap_op__insn_type$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry + wire input 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \logical_op__output_carry$15 + wire \trap_op__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$42 + wire output 26 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$42$next + wire \trap_op__is_32bit$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok + wire width 8 input 13 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$34 + wire width 8 output 29 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$34$next + wire width 8 \trap_op__ldst_exc$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__rc__ok$7 + wire width 8 \trap_op__ldst_exc$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc + wire width 64 input 8 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$33 + wire width 64 \trap_op__msr$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$33$next + wire width 64 output 24 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__rc__rc$6 + wire width 64 \trap_op__msr$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 + wire width 13 input 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \logical_op__write_cr0$14 + wire width 13 \trap_op__trapaddr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$41 + wire width 13 output 28 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$41$next + wire width 13 \trap_op__trapaddr$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a + wire width 8 input 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \logical_op__zero_a$11 + wire width 8 \trap_op__traptype$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$38 + wire width 8 output 27 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$38$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 36 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 35 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 34 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 input 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 output 63 \quotient_root - attribute \src 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parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \saved_state_q_bits_known - connect \B 6'111111 - connect \Y $ge$libresoc.v:161646$9645_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:161645$9644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \empty - connect \Y $not$libresoc.v:161645$9644_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:161644$9643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:161644$9642_Y - connect \Y $pos$libresoc.v:161644$9643_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:161643$9641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \div_state_next_o_dividend_quotient [127:64] - connect \B 7'1000000 - connect \Y $sshl$libresoc.v:161643$9641_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:161715.18-161719.4" - cell \div_state_init \div_state_init - connect \dividend \div_state_init_dividend - connect \o_dividend_quotient \div_state_init_o_dividend_quotient - connect \o_q_bits_known \div_state_init_o_q_bits_known + connect \A \p_valid_i$25 + connect \B \p_ready_o + connect \Y $and$libresoc.v:169407$9667_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:161720.18-161726.4" - cell \div_state_next \div_state_next - connect \divisor \div_state_next_divisor - connect \i_dividend_quotient \div_state_next_i_dividend_quotient - connect \i_q_bits_known \div_state_next_i_q_bits_known - connect \o_dividend_quotient \div_state_next_o_dividend_quotient - connect \o_q_bits_known \div_state_next_o_q_bits_known + attribute \src "libresoc.v:169450.13-169485.4" + cell \main$38 \main + connect \fast1 \main_fast1 + connect \fast1$11 \main_fast1$23 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$12 \main_fast2$24 + connect \fast2_ok \main_fast2_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$13 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__cia$6 \main_trap_op__cia$18 + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__insn$4 \main_trap_op__insn$16 + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 + connect \trap_op__ldst_exc \main_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__msr$5 \main_trap_op__msr$17 + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:161727.10-161730.4" - cell \n$80 \n + attribute \src "libresoc.v:169486.10-169489.4" + cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:161731.10-161734.4" - cell \p$79 \p + attribute \src "libresoc.v:169490.10-169493.4" + cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:161079.7-161079.20" - process $proc$libresoc.v:161079$9835 + attribute \src "libresoc.v:168696.7-168696.20" + process $proc$libresoc.v:168696$9757 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161101.7-161101.30" - process $proc$libresoc.v:161101$9836 - assign { } { } - assign $0\div_by_zero$54[0:0]$9837 1'0 - sync always - sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9837 - end - attribute \src "libresoc.v:161125.7-161125.32" - process $proc$libresoc.v:161125$9838 - assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9839 1'0 - sync always - sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9839 - end - attribute \src "libresoc.v:161133.7-161133.32" - process $proc$libresoc.v:161133$9840 - assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9841 1'0 - sync always - sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9841 - end - attribute \src "libresoc.v:161139.15-161139.68" - process $proc$libresoc.v:161139$9842 - assign { } { } - assign $0\dividend$68[127:0]$9843 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dividend$68 $0\dividend$68[127:0]$9843 - end - attribute \src "libresoc.v:161147.7-161147.31" - process $proc$libresoc.v:161147$9844 - assign { } { } - assign $0\dividend_neg$51[0:0]$9845 1'0 - sync always - sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9845 - end - attribute \src "libresoc.v:161155.7-161155.30" - process $proc$libresoc.v:161155$9846 - assign { } { } - assign $0\divisor_neg$50[0:0]$9847 1'0 - sync always - sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9847 - end - attribute \src "libresoc.v:161161.14-161161.58" - process $proc$libresoc.v:161161$9848 - assign { } { } - assign $0\divisor_radicand$65[63:0]$9849 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9849 - end - attribute \src "libresoc.v:161165.7-161165.19" - process $proc$libresoc.v:161165$9850 - assign { } { } - assign $1\empty[0:0] 1'1 - sync always - sync init - update \empty $1\empty[0:0] - end - attribute \src "libresoc.v:161173.13-161173.45" - process $proc$libresoc.v:161173$9851 - assign { } { } - assign $0\logical_op__data_len$45[3:0]$9852 4'0000 - sync always - sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9852 - end - attribute \src "libresoc.v:161220.14-161220.48" - process $proc$libresoc.v:161220$9853 + attribute \src "libresoc.v:168707.14-168707.47" + process $proc$libresoc.v:168707$9758 assign { } { } - assign $0\logical_op__fn_unit$30[11:0]$9854 12'000000000000 + assign $0\fast1$11[63:0]$9759 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9854 + update \fast1$11 $0\fast1$11[63:0]$9759 end - attribute \src "libresoc.v:161226.14-161226.68" - process $proc$libresoc.v:161226$9855 + attribute \src "libresoc.v:168714.7-168714.22" + process $proc$libresoc.v:168714$9760 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9856 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9856 - end - attribute \src "libresoc.v:161234.7-161234.43" - process $proc$libresoc.v:161234$9857 - assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9858 1'0 - sync always - sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9858 - end - attribute \src "libresoc.v:161256.13-161256.48" - process $proc$libresoc.v:161256$9859 - assign { } { } - assign $0\logical_op__input_carry$39[1:0]$9860 2'00 - sync always - sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9860 - end - attribute \src "libresoc.v:161264.14-161264.43" - process $proc$libresoc.v:161264$9861 - assign { } { } - assign $0\logical_op__insn$46[31:0]$9862 0 + assign $1\fast1_ok[0:0] 1'0 sync always sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9862 + update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:161494.13-161494.47" - process $proc$libresoc.v:161494$9863 + attribute \src "libresoc.v:168723.14-168723.47" + process $proc$libresoc.v:168723$9761 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9864 7'0000000 + assign $0\fast2$12[63:0]$9762 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9864 + update \fast2$12 $0\fast2$12[63:0]$9762 end - attribute \src "libresoc.v:161502.7-161502.40" - process $proc$libresoc.v:161502$9865 + attribute \src "libresoc.v:168730.7-168730.22" + process $proc$libresoc.v:168730$9763 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$9866 1'0 + assign $1\fast2_ok[0:0] 1'0 sync always sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9866 + update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:161510.7-161510.41" - process $proc$libresoc.v:161510$9867 + attribute \src "libresoc.v:168985.14-168985.40" + process $proc$libresoc.v:168985$9764 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$9868 1'0 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9868 + update \msr $1\msr[63:0] end - attribute \src "libresoc.v:161518.7-161518.39" - process $proc$libresoc.v:161518$9869 + attribute \src "libresoc.v:168992.7-168992.20" + process $proc$libresoc.v:168992$9765 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$9870 1'0 + assign $1\msr_ok[0:0] 1'0 sync always sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9870 + update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:161526.7-161526.40" - process $proc$libresoc.v:161526$9871 + attribute \src "libresoc.v:169001.13-169001.29" + process $proc$libresoc.v:169001$9766 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$9872 1'0 + assign $0\muxid$1[1:0]$9767 2'00 sync always sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9872 + update \muxid$1 $0\muxid$1[1:0]$9767 end - attribute \src "libresoc.v:161532.7-161532.37" - process $proc$libresoc.v:161532$9873 + attribute \src "libresoc.v:169014.14-169014.40" + process $proc$libresoc.v:169014$9768 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$9874 1'0 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9874 + update \nia $1\nia[63:0] end - attribute \src "libresoc.v:161540.7-161540.37" - process $proc$libresoc.v:161540$9875 + attribute \src "libresoc.v:169021.7-169021.20" + process $proc$libresoc.v:169021$9769 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$9876 1'0 + assign $1\nia_ok[0:0] 1'0 sync always sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9876 + update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:161550.7-161550.43" - process $proc$libresoc.v:161550$9877 + attribute \src "libresoc.v:169028.14-169028.38" + process $proc$libresoc.v:169028$9770 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$9878 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9878 + update \o $1\o[63:0] end - attribute \src "libresoc.v:161556.7-161556.37" - process $proc$libresoc.v:161556$9879 + attribute \src "libresoc.v:169035.7-169035.18" + process $proc$libresoc.v:169035$9771 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$9880 1'0 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9880 + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:161564.7-161564.37" - process $proc$libresoc.v:161564$9881 + attribute \src "libresoc.v:169049.7-169049.20" + process $proc$libresoc.v:169049$9772 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$9882 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9882 + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:161574.7-161574.40" - process $proc$libresoc.v:161574$9883 + attribute \src "libresoc.v:169062.14-169062.53" + process $proc$libresoc.v:169062$9773 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$9884 1'0 + assign $0\trap_op__cia$6[63:0]$9774 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9884 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9774 end - attribute \src "libresoc.v:161582.7-161582.37" - process $proc$libresoc.v:161582$9885 + attribute \src "libresoc.v:169099.14-169099.45" + process $proc$libresoc.v:169099$9775 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$9886 1'0 + assign $0\trap_op__fn_unit$3[13:0]$9776 14'00000000000000 sync always sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9886 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9776 end - attribute \src "libresoc.v:161590.13-161590.30" - process $proc$libresoc.v:161590$9887 + attribute \src "libresoc.v:169125.14-169125.39" + process $proc$libresoc.v:169125$9777 assign { } { } - assign $0\muxid$28[1:0]$9888 2'00 + assign $0\trap_op__insn$4[31:0]$9778 0 sync always sync init - update \muxid$28 $0\muxid$28[1:0]$9888 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9778 end - attribute \src "libresoc.v:161600.13-161600.34" - process $proc$libresoc.v:161600$9889 + attribute \src "libresoc.v:169282.13-169282.43" + process $proc$libresoc.v:169282$9779 assign { } { } - assign $0\operation$69[1:0]$9890 2'00 + assign $0\trap_op__insn_type$2[6:0]$9780 7'0000000 sync always sync init - update \operation$69 $0\operation$69[1:0]$9890 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9780 end - attribute \src "libresoc.v:161614.14-161614.44" - process $proc$libresoc.v:161614$9891 + attribute \src "libresoc.v:169368.7-169368.35" + process $proc$libresoc.v:169368$9781 assign { } { } - assign $0\ra$47[63:0]$9892 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__is_32bit$7[0:0]$9782 1'0 sync always sync init - update \ra$47 $0\ra$47[63:0]$9892 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9782 end - attribute \src "libresoc.v:161622.14-161622.44" - process $proc$libresoc.v:161622$9893 + attribute \src "libresoc.v:169375.13-169375.43" + process $proc$libresoc.v:169375$9783 assign { } { } - assign $0\rb$48[63:0]$9894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__ldst_exc$10[7:0]$9784 8'00000000 sync always sync init - update \rb$48 $0\rb$48[63:0]$9894 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9784 end - attribute \src "libresoc.v:161628.15-161628.84" - process $proc$libresoc.v:161628$9895 + attribute \src "libresoc.v:169386.14-169386.53" + process $proc$libresoc.v:169386$9785 assign { } { } - assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__msr$5[63:0]$9786 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9786 end - attribute \src "libresoc.v:161632.13-161632.45" - process $proc$libresoc.v:161632$9896 + attribute \src "libresoc.v:169395.14-169395.46" + process $proc$libresoc.v:169395$9787 assign { } { } - assign $1\saved_state_q_bits_known[6:0] 7'0000000 + assign $0\trap_op__trapaddr$9[12:0]$9788 13'0000000000000 sync always sync init - update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9788 end - attribute \src "libresoc.v:161640.7-161640.25" - process $proc$libresoc.v:161640$9897 + attribute \src "libresoc.v:169404.13-169404.42" + process $proc$libresoc.v:169404$9789 assign { } { } - assign $0\xer_so$49[0:0]$9898 1'0 + assign $0\trap_op__traptype$8[7:0]$9790 8'00000000 sync always sync init - update \xer_so$49 $0\xer_so$49[0:0]$9898 - end - attribute \src "libresoc.v:161649.3-161650.43" - process $proc$libresoc.v:161649$9648 - assign { } { } - assign $0\operation$69[1:0]$9649 \operation$69$next - sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$9649 - end - attribute \src "libresoc.v:161651.3-161652.57" - process $proc$libresoc.v:161651$9650 - assign { } { } - assign $0\divisor_radicand$65[63:0]$9651 \divisor_radicand$65$next - sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9651 - end - attribute \src "libresoc.v:161653.3-161654.41" - process $proc$libresoc.v:161653$9652 - assign { } { } - assign $0\dividend$68[127:0]$9653 \dividend$68$next - sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$9653 - end - attribute \src "libresoc.v:161655.3-161656.47" - process $proc$libresoc.v:161655$9654 - assign { } { } - assign $0\div_by_zero$54[0:0]$9655 \div_by_zero$54$next - sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9655 - end - attribute \src "libresoc.v:161657.3-161658.51" - process $proc$libresoc.v:161657$9656 - assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9657 \dive_abs_ov64$53$next - sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9657 - end - attribute \src "libresoc.v:161659.3-161660.51" - process $proc$libresoc.v:161659$9658 - assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9659 \dive_abs_ov32$52$next - sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9659 - end - attribute \src "libresoc.v:161661.3-161662.49" - process $proc$libresoc.v:161661$9660 - assign { } { } - assign $0\dividend_neg$51[0:0]$9661 \dividend_neg$51$next - sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9661 - end - attribute \src "libresoc.v:161663.3-161664.47" - process $proc$libresoc.v:161663$9662 - assign { } { } - assign $0\divisor_neg$50[0:0]$9663 \divisor_neg$50$next - sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9663 - end - attribute \src "libresoc.v:161665.3-161666.37" - process $proc$libresoc.v:161665$9664 - assign { } { } - assign $0\xer_so$49[0:0]$9665 \xer_so$49$next - sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$9665 - end - attribute \src "libresoc.v:161667.3-161668.29" - process $proc$libresoc.v:161667$9666 - assign { } { } - assign $0\rb$48[63:0]$9667 \rb$48$next - sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$9667 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9790 end - attribute \src "libresoc.v:161669.3-161670.29" - process $proc$libresoc.v:161669$9668 + attribute \src "libresoc.v:169408.3-169409.29" + process $proc$libresoc.v:169408$9668 assign { } { } - assign $0\ra$47[63:0]$9669 \ra$47$next - sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$9669 - end - attribute \src "libresoc.v:161671.3-161672.67" - process $proc$libresoc.v:161671$9670 - assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9671 \logical_op__insn_type$29$next - sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9671 - end - attribute \src "libresoc.v:161673.3-161674.63" - process $proc$libresoc.v:161673$9672 - assign { } { } - assign $0\logical_op__fn_unit$30[11:0]$9673 \logical_op__fn_unit$30$next + assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9673 + update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:161675.3-161676.77" - process $proc$libresoc.v:161675$9674 + attribute \src "libresoc.v:169410.3-169411.35" + process $proc$libresoc.v:169410$9669 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9675 \logical_op__imm_data__data$31$next + assign $0\fast2$12[63:0]$9670 \fast2$12$next sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9675 + update \fast2$12 $0\fast2$12[63:0]$9670 end - attribute \src "libresoc.v:161677.3-161678.73" - process $proc$libresoc.v:161677$9676 + attribute \src "libresoc.v:169412.3-169413.33" + process $proc$libresoc.v:169412$9671 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9677 \logical_op__imm_data__ok$32$next + assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9677 + update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:161679.3-161680.61" - process $proc$libresoc.v:161679$9678 + attribute \src "libresoc.v:169414.3-169415.35" + process $proc$libresoc.v:169414$9672 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$9679 \logical_op__rc__rc$33$next + assign $0\fast1$11[63:0]$9673 \fast1$11$next sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9679 + update \fast1$11 $0\fast1$11[63:0]$9673 end - attribute \src "libresoc.v:161681.3-161682.61" - process $proc$libresoc.v:161681$9680 + attribute \src "libresoc.v:169416.3-169417.33" + process $proc$libresoc.v:169416$9674 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$9681 \logical_op__rc__ok$34$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9681 + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:161683.3-161684.61" - process $proc$libresoc.v:161683$9682 + attribute \src "libresoc.v:169418.3-169419.19" + process $proc$libresoc.v:169418$9675 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$9683 \logical_op__oe__oe$35$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9683 + update \o $0\o[63:0] end - attribute \src "libresoc.v:161685.3-161686.61" - process $proc$libresoc.v:161685$9684 + attribute \src "libresoc.v:169420.3-169421.25" + process $proc$libresoc.v:169420$9676 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$9685 \logical_op__oe__ok$36$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9685 + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:161687.3-161688.67" - process $proc$libresoc.v:161687$9686 + attribute \src "libresoc.v:169422.3-169423.59" + process $proc$libresoc.v:169422$9677 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$9687 \logical_op__invert_in$37$next + assign $0\trap_op__insn_type$2[6:0]$9678 \trap_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9687 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9678 end - attribute \src "libresoc.v:161689.3-161690.61" - process $proc$libresoc.v:161689$9688 + attribute \src "libresoc.v:169424.3-169425.55" + process $proc$libresoc.v:169424$9679 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$9689 \logical_op__zero_a$38$next + assign $0\trap_op__fn_unit$3[13:0]$9680 \trap_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9689 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9680 end - attribute \src "libresoc.v:161691.3-161692.71" - process $proc$libresoc.v:161691$9690 + attribute \src "libresoc.v:169426.3-169427.49" + process $proc$libresoc.v:169426$9681 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$9691 \logical_op__input_carry$39$next + assign $0\trap_op__insn$4[31:0]$9682 \trap_op__insn$4$next sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9691 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9682 end - attribute \src "libresoc.v:161693.3-161694.69" - process $proc$libresoc.v:161693$9692 + attribute \src "libresoc.v:169428.3-169429.47" + process $proc$libresoc.v:169428$9683 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$9693 \logical_op__invert_out$40$next + assign $0\trap_op__msr$5[63:0]$9684 \trap_op__msr$5$next sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9693 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9684 end - attribute \src "libresoc.v:161695.3-161696.67" - process $proc$libresoc.v:161695$9694 + attribute \src "libresoc.v:169430.3-169431.47" + process $proc$libresoc.v:169430$9685 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$9695 \logical_op__write_cr0$41$next + assign $0\trap_op__cia$6[63:0]$9686 \trap_op__cia$6$next sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9695 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9686 end - attribute \src "libresoc.v:161697.3-161698.73" - process $proc$libresoc.v:161697$9696 + attribute \src "libresoc.v:169432.3-169433.57" + process $proc$libresoc.v:169432$9687 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$9697 \logical_op__output_carry$42$next + assign $0\trap_op__is_32bit$7[0:0]$9688 \trap_op__is_32bit$7$next sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9697 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9688 end - attribute \src "libresoc.v:161699.3-161700.65" - process $proc$libresoc.v:161699$9698 + attribute \src "libresoc.v:169434.3-169435.57" + process $proc$libresoc.v:169434$9689 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$9699 \logical_op__is_32bit$43$next + assign $0\trap_op__traptype$8[7:0]$9690 \trap_op__traptype$8$next sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9699 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9690 end - attribute \src "libresoc.v:161701.3-161702.67" - process $proc$libresoc.v:161701$9700 + attribute \src "libresoc.v:169436.3-169437.57" + process $proc$libresoc.v:169436$9691 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$9701 \logical_op__is_signed$44$next + assign $0\trap_op__trapaddr$9[12:0]$9692 \trap_op__trapaddr$9$next sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9701 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9692 end - attribute \src "libresoc.v:161703.3-161704.65" - process $proc$libresoc.v:161703$9702 + attribute \src "libresoc.v:169438.3-169439.59" + process $proc$libresoc.v:169438$9693 assign { } { } - assign $0\logical_op__data_len$45[3:0]$9703 \logical_op__data_len$45$next + assign $0\trap_op__ldst_exc$10[7:0]$9694 \trap_op__ldst_exc$10$next sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9703 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9694 end - attribute \src "libresoc.v:161705.3-161706.57" - process $proc$libresoc.v:161705$9704 + attribute \src "libresoc.v:169440.3-169441.33" + process $proc$libresoc.v:169440$9695 assign { } { } - assign $0\logical_op__insn$46[31:0]$9705 \logical_op__insn$46$next + assign $0\muxid$1[1:0]$9696 \muxid$1$next sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9705 + update \muxid$1 $0\muxid$1[1:0]$9696 end - attribute \src "libresoc.v:161707.3-161708.35" - process $proc$libresoc.v:161707$9706 + attribute \src "libresoc.v:169442.3-169443.29" + process $proc$libresoc.v:169442$9697 assign { } { } - assign $0\muxid$28[1:0]$9707 \muxid$28$next + assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$9707 + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:161709.3-161710.27" - process $proc$libresoc.v:161709$9708 + attribute \src "libresoc.v:169444.3-169445.23" + process $proc$libresoc.v:169444$9698 assign { } { } - assign $0\empty[0:0] \empty$next + assign $0\msr[63:0] \msr$next sync posedge \coresync_clk - update \empty $0\empty[0:0] + update \msr $0\msr[63:0] end - attribute \src "libresoc.v:161711.3-161712.75" - process $proc$libresoc.v:161711$9709 + attribute \src "libresoc.v:169446.3-169447.29" + process $proc$libresoc.v:169446$9699 assign { } { } - assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk - update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] + update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:161713.3-161714.65" - process $proc$libresoc.v:161713$9710 + attribute \src "libresoc.v:169448.3-169449.23" + process $proc$libresoc.v:169448$9700 assign { } { } - assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + assign $0\nia[63:0] \nia$next sync posedge \coresync_clk - update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] - end - attribute \src "libresoc.v:161735.3-161743.6" - process $proc$libresoc.v:161735$9711 - assign { } { } - assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$9712 $1\saved_state_q_bits_known$next[6:0]$9713 - attribute \src "libresoc.v:161736.5-161736.29" - switch \initial - attribute \src "libresoc.v:161736.9-161736.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$9713 7'0000000 - case - assign $1\saved_state_q_bits_known$next[6:0]$9713 \div_state_next_o_q_bits_known - end - sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$9712 - end - attribute \src "libresoc.v:161744.3-161752.6" - process $proc$libresoc.v:161744$9714 - assign { } { } - assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$9715 $1\saved_state_dividend_quotient$next[127:0]$9716 - attribute \src "libresoc.v:161745.5-161745.29" - switch \initial - attribute \src "libresoc.v:161745.9-161745.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$9716 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\saved_state_dividend_quotient$next[127:0]$9716 \div_state_next_o_dividend_quotient - end - sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$9715 + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:161753.3-161764.6" - process $proc$libresoc.v:161753$9717 + attribute \src "libresoc.v:169494.3-169511.6" + process $proc$libresoc.v:169494$9701 assign { } { } - assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:161754.5-161754.29" - switch \initial - attribute \src "libresoc.v:161754.9-161754.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known - end - sync always - update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] - end - attribute \src "libresoc.v:161765.3-161776.6" - process $proc$libresoc.v:161765$9718 assign { } { } - assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:161766.5-161766.29" - switch \initial - attribute \src "libresoc.v:161766.9-161766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient - end - sync always - update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] - end - attribute \src "libresoc.v:161777.3-161788.6" - process $proc$libresoc.v:161777$9719 assign { } { } - assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:161778.5-161778.29" + assign $0\r_busy$next[0:0]$9702 $2\r_busy$next[0:0]$9704 + attribute \src "libresoc.v:169495.5-169495.29" switch \initial - attribute \src "libresoc.v:161778.9-161778.17" + attribute \src "libresoc.v:169495.9-169495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case + case 2'-1 assign { } { } - assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 - end - sync always - update \div_state_next_divisor $0\div_state_next_divisor[63:0] - end - attribute \src "libresoc.v:161789.3-161816.6" - process $proc$libresoc.v:161789$9720 - assign { } { } - assign { } { } - assign { } { } - assign $0\empty$next[0:0]$9721 $4\empty$next[0:0]$9725 - attribute \src "libresoc.v:161790.5-161790.29" - switch \initial - attribute \src "libresoc.v:161790.9-161790.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + assign $1\r_busy$next[0:0]$9703 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'1- assign { } { } - assign $1\empty$next[0:0]$9722 $2\empty$next[0:0]$9723 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\empty$next[0:0]$9723 1'0 - case - assign $2\empty$next[0:0]$9723 \empty - end - attribute \src "libresoc.v:0.0-0.0" + assign $1\r_busy$next[0:0]$9703 1'0 case - assign { } { } - assign $1\empty$next[0:0]$9722 $3\empty$next[0:0]$9724 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch \$66 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\empty$next[0:0]$9724 1'1 - case - assign $3\empty$next[0:0]$9724 \empty - end + assign $1\r_busy$next[0:0]$9703 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\empty$next[0:0]$9725 1'1 + assign $2\r_busy$next[0:0]$9704 1'0 case - assign $4\empty$next[0:0]$9725 $1\empty$next[0:0]$9722 + assign $2\r_busy$next[0:0]$9704 $1\r_busy$next[0:0]$9703 end sync always - update \empty$next $0\empty$next[0:0]$9721 + update \r_busy$next $0\r_busy$next[0:0]$9702 end - attribute \src "libresoc.v:161817.3-161831.6" - process $proc$libresoc.v:161817$9726 + attribute \src "libresoc.v:169512.3-169524.6" + process $proc$libresoc.v:169512$9705 assign { } { } assign { } { } - assign $0\muxid$28$next[1:0]$9727 $1\muxid$28$next[1:0]$9728 - attribute \src "libresoc.v:161818.5-161818.29" + assign $0\muxid$1$next[1:0]$9706 $1\muxid$1$next[1:0]$9707 + attribute \src "libresoc.v:169513.5-169513.29" switch \initial - attribute \src "libresoc.v:161818.9-161818.17" + attribute \src "libresoc.v:169513.9-169513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\muxid$28$next[1:0]$9728 $2\muxid$28$next[1:0]$9729 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\muxid$28$next[1:0]$9729 \muxid - case - assign $2\muxid$28$next[1:0]$9729 \muxid$28 - end + assign $1\muxid$1$next[1:0]$9707 \muxid$28 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9707 \muxid$28 case - assign $1\muxid$28$next[1:0]$9728 \muxid$28 + assign $1\muxid$1$next[1:0]$9707 \muxid$1 end sync always - update \muxid$28$next $0\muxid$28$next[1:0]$9727 + update \muxid$1$next $0\muxid$1$next[1:0]$9706 end - attribute \src "libresoc.v:161832.3-161875.6" - process $proc$libresoc.v:161832$9730 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:169525.3-169545.6" + process $proc$libresoc.v:169525$9708 assign { } { } assign { } { } assign { } { } @@ -334358,59 +349014,25 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$9731 $1\logical_op__data_len$45$next[3:0]$9749 - assign $0\logical_op__fn_unit$30$next[11:0]$9732 $1\logical_op__fn_unit$30$next[11:0]$9750 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$9735 $1\logical_op__input_carry$39$next[1:0]$9753 - assign $0\logical_op__insn$46$next[31:0]$9736 $1\logical_op__insn$46$next[31:0]$9754 - assign $0\logical_op__insn_type$29$next[6:0]$9737 $1\logical_op__insn_type$29$next[6:0]$9755 - assign $0\logical_op__invert_in$37$next[0:0]$9738 $1\logical_op__invert_in$37$next[0:0]$9756 - assign $0\logical_op__invert_out$40$next[0:0]$9739 $1\logical_op__invert_out$40$next[0:0]$9757 - assign $0\logical_op__is_32bit$43$next[0:0]$9740 $1\logical_op__is_32bit$43$next[0:0]$9758 - assign $0\logical_op__is_signed$44$next[0:0]$9741 $1\logical_op__is_signed$44$next[0:0]$9759 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$9744 $1\logical_op__output_carry$42$next[0:0]$9762 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$9747 $1\logical_op__write_cr0$41$next[0:0]$9765 - assign $0\logical_op__zero_a$38$next[0:0]$9748 $1\logical_op__zero_a$38$next[0:0]$9766 - assign $0\logical_op__imm_data__data$31$next[63:0]$9733 $3\logical_op__imm_data__data$31$next[63:0]$9785 - assign $0\logical_op__imm_data__ok$32$next[0:0]$9734 $3\logical_op__imm_data__ok$32$next[0:0]$9786 - assign $0\logical_op__oe__oe$35$next[0:0]$9742 $3\logical_op__oe__oe$35$next[0:0]$9787 - assign $0\logical_op__oe__ok$36$next[0:0]$9743 $3\logical_op__oe__ok$36$next[0:0]$9788 - assign $0\logical_op__rc__ok$34$next[0:0]$9745 $3\logical_op__rc__ok$34$next[0:0]$9789 - assign $0\logical_op__rc__rc$33$next[0:0]$9746 $3\logical_op__rc__rc$33$next[0:0]$9790 - attribute \src "libresoc.v:161833.5-161833.29" + assign $0\trap_op__cia$6$next[63:0]$9709 $1\trap_op__cia$6$next[63:0]$9718 + assign $0\trap_op__fn_unit$3$next[13:0]$9710 $1\trap_op__fn_unit$3$next[13:0]$9719 + assign $0\trap_op__insn$4$next[31:0]$9711 $1\trap_op__insn$4$next[31:0]$9720 + assign $0\trap_op__insn_type$2$next[6:0]$9712 $1\trap_op__insn_type$2$next[6:0]$9721 + assign $0\trap_op__is_32bit$7$next[0:0]$9713 $1\trap_op__is_32bit$7$next[0:0]$9722 + assign $0\trap_op__ldst_exc$10$next[7:0]$9714 $1\trap_op__ldst_exc$10$next[7:0]$9723 + assign $0\trap_op__msr$5$next[63:0]$9715 $1\trap_op__msr$5$next[63:0]$9724 + assign $0\trap_op__trapaddr$9$next[12:0]$9716 $1\trap_op__trapaddr$9$next[12:0]$9725 + assign $0\trap_op__traptype$8$next[7:0]$9717 $1\trap_op__traptype$8$next[7:0]$9726 + attribute \src "libresoc.v:169526.5-169526.29" switch \initial - attribute \src "libresoc.v:161833.9-161833.17" + attribute \src "libresoc.v:169526.9-169526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 2'-1 assign { } { } assign { } { } assign { } { } @@ -334420,887 +349042,677 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9723 $1\trap_op__trapaddr$9$next[12:0]$9725 $1\trap_op__traptype$8$next[7:0]$9726 $1\trap_op__is_32bit$7$next[0:0]$9722 $1\trap_op__cia$6$next[63:0]$9718 $1\trap_op__msr$5$next[63:0]$9724 $1\trap_op__insn$4$next[31:0]$9720 $1\trap_op__fn_unit$3$next[13:0]$9719 $1\trap_op__insn_type$2$next[6:0]$9721 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$9749 $2\logical_op__data_len$45$next[3:0]$9767 - assign $1\logical_op__fn_unit$30$next[11:0]$9750 $2\logical_op__fn_unit$30$next[11:0]$9768 - assign $1\logical_op__imm_data__data$31$next[63:0]$9751 $2\logical_op__imm_data__data$31$next[63:0]$9769 - assign $1\logical_op__imm_data__ok$32$next[0:0]$9752 $2\logical_op__imm_data__ok$32$next[0:0]$9770 - assign $1\logical_op__input_carry$39$next[1:0]$9753 $2\logical_op__input_carry$39$next[1:0]$9771 - assign $1\logical_op__insn$46$next[31:0]$9754 $2\logical_op__insn$46$next[31:0]$9772 - assign $1\logical_op__insn_type$29$next[6:0]$9755 $2\logical_op__insn_type$29$next[6:0]$9773 - assign $1\logical_op__invert_in$37$next[0:0]$9756 $2\logical_op__invert_in$37$next[0:0]$9774 - assign $1\logical_op__invert_out$40$next[0:0]$9757 $2\logical_op__invert_out$40$next[0:0]$9775 - assign $1\logical_op__is_32bit$43$next[0:0]$9758 $2\logical_op__is_32bit$43$next[0:0]$9776 - assign $1\logical_op__is_signed$44$next[0:0]$9759 $2\logical_op__is_signed$44$next[0:0]$9777 - assign $1\logical_op__oe__oe$35$next[0:0]$9760 $2\logical_op__oe__oe$35$next[0:0]$9778 - assign $1\logical_op__oe__ok$36$next[0:0]$9761 $2\logical_op__oe__ok$36$next[0:0]$9779 - assign $1\logical_op__output_carry$42$next[0:0]$9762 $2\logical_op__output_carry$42$next[0:0]$9780 - assign $1\logical_op__rc__ok$34$next[0:0]$9763 $2\logical_op__rc__ok$34$next[0:0]$9781 - assign $1\logical_op__rc__rc$33$next[0:0]$9764 $2\logical_op__rc__rc$33$next[0:0]$9782 - assign $1\logical_op__write_cr0$41$next[0:0]$9765 $2\logical_op__write_cr0$41$next[0:0]$9783 - assign $1\logical_op__zero_a$38$next[0:0]$9766 $2\logical_op__zero_a$38$next[0:0]$9784 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$9772 $2\logical_op__data_len$45$next[3:0]$9767 $2\logical_op__is_signed$44$next[0:0]$9777 $2\logical_op__is_32bit$43$next[0:0]$9776 $2\logical_op__output_carry$42$next[0:0]$9780 $2\logical_op__write_cr0$41$next[0:0]$9783 $2\logical_op__invert_out$40$next[0:0]$9775 $2\logical_op__input_carry$39$next[1:0]$9771 $2\logical_op__zero_a$38$next[0:0]$9784 $2\logical_op__invert_in$37$next[0:0]$9774 $2\logical_op__oe__ok$36$next[0:0]$9779 $2\logical_op__oe__oe$35$next[0:0]$9778 $2\logical_op__rc__ok$34$next[0:0]$9781 $2\logical_op__rc__rc$33$next[0:0]$9782 $2\logical_op__imm_data__ok$32$next[0:0]$9770 $2\logical_op__imm_data__data$31$next[63:0]$9769 $2\logical_op__fn_unit$30$next[11:0]$9768 $2\logical_op__insn_type$29$next[6:0]$9773 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - case - assign $2\logical_op__data_len$45$next[3:0]$9767 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[11:0]$9768 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$9769 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$9770 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$9771 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$9772 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$9773 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$9774 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$9775 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$9776 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$9777 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$9778 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$9779 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$9780 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$9781 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$9782 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$9783 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$9784 \logical_op__zero_a$38 - end - case - assign $1\logical_op__data_len$45$next[3:0]$9749 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[11:0]$9750 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$9751 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$9752 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$9753 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$9754 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$9755 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$9756 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$9757 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$9758 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$9759 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$9760 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$9761 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$9762 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$9763 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$9764 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$9765 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$9766 \logical_op__zero_a$38 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$9785 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$9786 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$9790 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$9789 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$9787 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$9788 1'0 + assign { $1\trap_op__ldst_exc$10$next[7:0]$9723 $1\trap_op__trapaddr$9$next[12:0]$9725 $1\trap_op__traptype$8$next[7:0]$9726 $1\trap_op__is_32bit$7$next[0:0]$9722 $1\trap_op__cia$6$next[63:0]$9718 $1\trap_op__msr$5$next[63:0]$9724 $1\trap_op__insn$4$next[31:0]$9720 $1\trap_op__fn_unit$3$next[13:0]$9719 $1\trap_op__insn_type$2$next[6:0]$9721 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } case - assign $3\logical_op__imm_data__data$31$next[63:0]$9785 $1\logical_op__imm_data__data$31$next[63:0]$9751 - assign $3\logical_op__imm_data__ok$32$next[0:0]$9786 $1\logical_op__imm_data__ok$32$next[0:0]$9752 - assign $3\logical_op__oe__oe$35$next[0:0]$9787 $1\logical_op__oe__oe$35$next[0:0]$9760 - assign $3\logical_op__oe__ok$36$next[0:0]$9788 $1\logical_op__oe__ok$36$next[0:0]$9761 - assign $3\logical_op__rc__ok$34$next[0:0]$9789 $1\logical_op__rc__ok$34$next[0:0]$9763 - assign $3\logical_op__rc__rc$33$next[0:0]$9790 $1\logical_op__rc__rc$33$next[0:0]$9764 + assign $1\trap_op__cia$6$next[63:0]$9718 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[13:0]$9719 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9720 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9721 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9722 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9723 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9724 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9725 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9726 \trap_op__traptype$8 end sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$9731 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[11:0]$9732 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$9733 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$9734 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$9735 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$9736 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$9737 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$9738 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$9739 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$9740 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$9741 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$9742 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$9743 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$9744 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$9745 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$9746 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$9747 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$9748 + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9709 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9710 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9711 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9712 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9713 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9714 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9715 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9716 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9717 end - attribute \src "libresoc.v:161876.3-161890.6" - process $proc$libresoc.v:161876$9791 + attribute \src "libresoc.v:169546.3-169564.6" + process $proc$libresoc.v:169546$9727 assign { } { } assign { } { } - assign $0\ra$47$next[63:0]$9792 $1\ra$47$next[63:0]$9793 - attribute \src "libresoc.v:161877.5-161877.29" - switch \initial - attribute \src "libresoc.v:161877.9-161877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ra$47$next[63:0]$9793 $2\ra$47$next[63:0]$9794 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ra$47$next[63:0]$9794 \ra - case - assign $2\ra$47$next[63:0]$9794 \ra$47 - end - case - assign $1\ra$47$next[63:0]$9793 \ra$47 - end - sync always - update \ra$47$next $0\ra$47$next[63:0]$9792 - end - attribute \src "libresoc.v:161891.3-161905.6" - process $proc$libresoc.v:161891$9795 assign { } { } assign { } { } - assign $0\rb$48$next[63:0]$9796 $1\rb$48$next[63:0]$9797 - attribute \src "libresoc.v:161892.5-161892.29" + assign $0\o$next[63:0]$9728 $1\o$next[63:0]$9730 + assign { } { } + assign $0\o_ok$next[0:0]$9729 $2\o_ok$next[0:0]$9732 + attribute \src "libresoc.v:169547.5-169547.29" switch \initial - attribute \src "libresoc.v:161892.9-161892.17" + attribute \src "libresoc.v:169547.9-169547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\rb$48$next[63:0]$9797 $2\rb$48$next[63:0]$9798 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\rb$48$next[63:0]$9798 \rb - case - assign $2\rb$48$next[63:0]$9798 \rb$48 - end - case - assign $1\rb$48$next[63:0]$9797 \rb$48 - end - sync always - update \rb$48$next $0\rb$48$next[63:0]$9796 - end - attribute \src "libresoc.v:161906.3-161920.6" - process $proc$libresoc.v:161906$9799 - assign { } { } - assign { } { } - assign $0\xer_so$49$next[0:0]$9800 $1\xer_so$49$next[0:0]$9801 - attribute \src "libresoc.v:161907.5-161907.29" - switch \initial - attribute \src "libresoc.v:161907.9-161907.17" - case 1'1 + assign { } { } + assign { $1\o_ok$next[0:0]$9731 $1\o$next[63:0]$9730 } { \o_ok$39 \o$38 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9731 $1\o$next[63:0]$9730 } { \o_ok$39 \o$38 } case + assign $1\o$next[63:0]$9730 \o + assign $1\o_ok$next[0:0]$9731 \o_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$9801 $2\xer_so$49$next[0:0]$9802 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so$49$next[0:0]$9802 \xer_so - case - assign $2\xer_so$49$next[0:0]$9802 \xer_so$49 - end + assign $2\o_ok$next[0:0]$9732 1'0 case - assign $1\xer_so$49$next[0:0]$9801 \xer_so$49 + assign $2\o_ok$next[0:0]$9732 $1\o_ok$next[0:0]$9731 end sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$9800 + update \o$next $0\o$next[63:0]$9728 + update \o_ok$next $0\o_ok$next[0:0]$9729 end - attribute \src "libresoc.v:161921.3-161935.6" - process $proc$libresoc.v:161921$9803 + attribute \src "libresoc.v:169565.3-169583.6" + process $proc$libresoc.v:169565$9733 + assign { } { } assign { } { } assign { } { } - assign $0\divisor_neg$50$next[0:0]$9804 $1\divisor_neg$50$next[0:0]$9805 - attribute \src "libresoc.v:161922.5-161922.29" + assign { } { } + assign { } { } + assign $0\fast1$11$next[63:0]$9735 $1\fast1$11$next[63:0]$9737 + assign $0\fast1_ok$next[0:0]$9734 $2\fast1_ok$next[0:0]$9738 + attribute \src "libresoc.v:169566.5-169566.29" switch \initial - attribute \src "libresoc.v:161922.9-161922.17" + attribute \src "libresoc.v:169566.9-169566.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$9805 $2\divisor_neg$50$next[0:0]$9806 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\divisor_neg$50$next[0:0]$9806 \divisor_neg - case - assign $2\divisor_neg$50$next[0:0]$9806 \divisor_neg$50 - end - case - assign $1\divisor_neg$50$next[0:0]$9805 \divisor_neg$50 - end - sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$9804 - end - attribute \src "libresoc.v:161936.3-161950.6" - process $proc$libresoc.v:161936$9807 - assign { } { } - assign { } { } - assign $0\dividend_neg$51$next[0:0]$9808 $1\dividend_neg$51$next[0:0]$9809 - attribute \src "libresoc.v:161937.5-161937.29" - switch \initial - attribute \src "libresoc.v:161937.9-161937.17" - case 1'1 + assign { } { } + assign { $1\fast1_ok$next[0:0]$9736 $1\fast1$11$next[63:0]$9737 } { \fast1_ok$41 \fast1$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$9736 $1\fast1$11$next[63:0]$9737 } { \fast1_ok$41 \fast1$40 } case + assign $1\fast1_ok$next[0:0]$9736 \fast1_ok + assign $1\fast1$11$next[63:0]$9737 \fast1$11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$9809 $2\dividend_neg$51$next[0:0]$9810 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend_neg$51$next[0:0]$9810 \dividend_neg - case - assign $2\dividend_neg$51$next[0:0]$9810 \dividend_neg$51 - end + assign $2\fast1_ok$next[0:0]$9738 1'0 case - assign $1\dividend_neg$51$next[0:0]$9809 \dividend_neg$51 + assign $2\fast1_ok$next[0:0]$9738 $1\fast1_ok$next[0:0]$9736 end sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$9808 + update \fast1_ok$next $0\fast1_ok$next[0:0]$9734 + update \fast1$11$next $0\fast1$11$next[63:0]$9735 end - attribute \src "libresoc.v:161951.3-161965.6" - process $proc$libresoc.v:161951$9811 + attribute \src "libresoc.v:169584.3-169602.6" + process $proc$libresoc.v:169584$9739 + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$9812 $1\dive_abs_ov32$52$next[0:0]$9813 - attribute \src "libresoc.v:161952.5-161952.29" + assign { } { } + assign $0\fast2$12$next[63:0]$9741 $1\fast2$12$next[63:0]$9743 + assign $0\fast2_ok$next[0:0]$9740 $2\fast2_ok$next[0:0]$9744 + attribute \src "libresoc.v:169585.5-169585.29" switch \initial - attribute \src "libresoc.v:161952.9-161952.17" + attribute \src "libresoc.v:169585.9-169585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$9813 $2\dive_abs_ov32$52$next[0:0]$9814 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$9814 \dive_abs_ov32 - case - assign $2\dive_abs_ov32$52$next[0:0]$9814 \dive_abs_ov32$52 - end - case - assign $1\dive_abs_ov32$52$next[0:0]$9813 \dive_abs_ov32$52 - end - sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$9812 - end - attribute \src "libresoc.v:161966.3-161980.6" - process $proc$libresoc.v:161966$9815 - assign { } { } - assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$9816 $1\dive_abs_ov64$53$next[0:0]$9817 - attribute \src "libresoc.v:161967.5-161967.29" - switch \initial - attribute \src "libresoc.v:161967.9-161967.17" - case 1'1 + assign { } { } + assign { $1\fast2_ok$next[0:0]$9742 $1\fast2$12$next[63:0]$9743 } { \fast2_ok$43 \fast2$42 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$9742 $1\fast2$12$next[63:0]$9743 } { \fast2_ok$43 \fast2$42 } case + assign $1\fast2_ok$next[0:0]$9742 \fast2_ok + assign $1\fast2$12$next[63:0]$9743 \fast2$12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$9817 $2\dive_abs_ov64$53$next[0:0]$9818 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$9818 \dive_abs_ov64 - case - assign $2\dive_abs_ov64$53$next[0:0]$9818 \dive_abs_ov64$53 - end + assign $2\fast2_ok$next[0:0]$9744 1'0 case - assign $1\dive_abs_ov64$53$next[0:0]$9817 \dive_abs_ov64$53 + assign $2\fast2_ok$next[0:0]$9744 $1\fast2_ok$next[0:0]$9742 end sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$9816 + update \fast2_ok$next $0\fast2_ok$next[0:0]$9740 + update \fast2$12$next $0\fast2$12$next[63:0]$9741 end - attribute \src "libresoc.v:161981.3-161995.6" - process $proc$libresoc.v:161981$9819 + attribute \src "libresoc.v:169603.3-169621.6" + process $proc$libresoc.v:169603$9745 + assign { } { } + assign { } { } + assign { } { } assign { } { } + assign $0\nia$next[63:0]$9746 $1\nia$next[63:0]$9748 assign { } { } - assign $0\div_by_zero$54$next[0:0]$9820 $1\div_by_zero$54$next[0:0]$9821 - attribute \src "libresoc.v:161982.5-161982.29" + assign $0\nia_ok$next[0:0]$9747 $2\nia_ok$next[0:0]$9750 + attribute \src "libresoc.v:169604.5-169604.29" switch \initial - attribute \src "libresoc.v:161982.9-161982.17" + attribute \src "libresoc.v:169604.9-169604.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$9821 $2\div_by_zero$54$next[0:0]$9822 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\div_by_zero$54$next[0:0]$9822 \div_by_zero - case - assign $2\div_by_zero$54$next[0:0]$9822 \div_by_zero$54 - end - case - assign $1\div_by_zero$54$next[0:0]$9821 \div_by_zero$54 - end - sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$9820 - end - attribute \src "libresoc.v:161996.3-162010.6" - process $proc$libresoc.v:161996$9823 - assign { } { } - assign { } { } - assign $0\dividend$68$next[127:0]$9824 $1\dividend$68$next[127:0]$9825 - attribute \src "libresoc.v:161997.5-161997.29" - switch \initial - attribute \src "libresoc.v:161997.9-161997.17" - case 1'1 + assign { } { } + assign { $1\nia_ok$next[0:0]$9749 $1\nia$next[63:0]$9748 } { \nia_ok$45 \nia$44 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$9749 $1\nia$next[63:0]$9748 } { \nia_ok$45 \nia$44 } case + assign $1\nia$next[63:0]$9748 \nia + assign $1\nia_ok$next[0:0]$9749 \nia_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$9825 $2\dividend$68$next[127:0]$9826 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend$68$next[127:0]$9826 \dividend - case - assign $2\dividend$68$next[127:0]$9826 \dividend$68 - end + assign $2\nia_ok$next[0:0]$9750 1'0 case - assign $1\dividend$68$next[127:0]$9825 \dividend$68 + assign $2\nia_ok$next[0:0]$9750 $1\nia_ok$next[0:0]$9749 end sync always - update \dividend$68$next $0\dividend$68$next[127:0]$9824 + update \nia$next $0\nia$next[63:0]$9746 + update \nia_ok$next $0\nia_ok$next[0:0]$9747 end - attribute \src "libresoc.v:162011.3-162025.6" - process $proc$libresoc.v:162011$9827 + attribute \src "libresoc.v:169622.3-169640.6" + process $proc$libresoc.v:169622$9751 assign { } { } assign { } { } - assign $0\divisor_radicand$65$next[63:0]$9828 $1\divisor_radicand$65$next[63:0]$9829 - attribute \src "libresoc.v:162012.5-162012.29" + assign { } { } + assign { } { } + assign $0\msr$next[63:0]$9752 $1\msr$next[63:0]$9754 + assign { } { } + assign $0\msr_ok$next[0:0]$9753 $2\msr_ok$next[0:0]$9756 + attribute \src "libresoc.v:169623.5-169623.29" switch \initial - attribute \src "libresoc.v:162012.9-162012.17" + attribute \src "libresoc.v:169623.9-169623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$9829 $2\divisor_radicand$65$next[63:0]$9830 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\divisor_radicand$65$next[63:0]$9830 \divisor_radicand - case - assign $2\divisor_radicand$65$next[63:0]$9830 \divisor_radicand$65 - end - case - assign $1\divisor_radicand$65$next[63:0]$9829 \divisor_radicand$65 - end - sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$9828 - end - attribute \src "libresoc.v:162026.3-162040.6" - process $proc$libresoc.v:162026$9831 - assign { } { } - assign { } { } - assign $0\operation$69$next[1:0]$9832 $1\operation$69$next[1:0]$9833 - attribute \src "libresoc.v:162027.5-162027.29" - switch \initial - attribute \src "libresoc.v:162027.9-162027.17" - case 1'1 + assign { } { } + assign { $1\msr_ok$next[0:0]$9755 $1\msr$next[63:0]$9754 } { \msr_ok$47 \msr$46 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$9755 $1\msr$next[63:0]$9754 } { \msr_ok$47 \msr$46 } case + assign $1\msr$next[63:0]$9754 \msr + assign $1\msr_ok$next[0:0]$9755 \msr_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\operation$69$next[1:0]$9833 $2\operation$69$next[1:0]$9834 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\operation$69$next[1:0]$9834 \operation - case - assign $2\operation$69$next[1:0]$9834 \operation$69 - end + assign $2\msr_ok$next[0:0]$9756 1'0 case - assign $1\operation$69$next[1:0]$9833 \operation$69 + assign $2\msr_ok$next[0:0]$9756 $1\msr_ok$next[0:0]$9755 end sync always - update \operation$69$next $0\operation$69$next[1:0]$9832 + update \msr$next $0\msr$next[63:0]$9752 + update \msr_ok$next $0\msr_ok$next[0:0]$9753 end - connect \$56 $sshl$libresoc.v:161643$9641_Y - connect \$55 $pos$libresoc.v:161644$9643_Y - connect \$59 $not$libresoc.v:161645$9644_Y - connect \$61 $ge$libresoc.v:161646$9645_Y - connect \$63 $and$libresoc.v:161647$9646_Y - connect \$66 $and$libresoc.v:161648$9647_Y - connect \p_ready_o \empty - connect \n_valid_o \$63 - connect \remainder \$55 - connect \quotient_root \div_state_next_o_dividend_quotient [63:0] - connect \div_by_zero$27 \div_by_zero$54 - connect \dive_abs_ov64$26 \dive_abs_ov64$53 - connect \dive_abs_ov32$25 \dive_abs_ov32$52 - connect \dividend_neg$24 \dividend_neg$51 - connect \divisor_neg$23 \divisor_neg$50 - connect \xer_so$22 \xer_so$49 - connect \rb$21 \rb$48 - connect \ra$20 \ra$47 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } - connect \muxid$1 \muxid$28 - connect \div_state_init_dividend \dividend + connect \$26 $and$libresoc.v:169407$9667_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } + connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } + connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } + connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } + connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } + connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } + connect \muxid$28 \main_muxid$13 + connect \p_valid_i_p_ready_o \$26 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$25 \p_valid_i + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect \main_rb \rb + connect \main_ra \ra + connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \main_muxid \muxid end -attribute \src "libresoc.v:162060.1-163584.10" +attribute \src "libresoc.v:169663.1-171166.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" -module \pipe_start - attribute \src "libresoc.v:163390.3-163402.6" - wire $0\div_by_zero$next[0:0]$9944 - attribute \src "libresoc.v:163176.3-163177.39" - wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:163364.3-163376.6" - wire $0\dive_abs_ov32$next[0:0]$9938 - attribute \src "libresoc.v:163180.3-163181.43" - wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:163377.3-163389.6" - wire $0\dive_abs_ov64$next[0:0]$9941 - attribute \src "libresoc.v:163178.3-163179.43" - wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:163403.3-163415.6" - wire width 128 $0\dividend$next[127:0]$9947 - attribute \src "libresoc.v:163174.3-163175.33" - wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:163351.3-163363.6" - wire $0\dividend_neg$next[0:0]$9935 - attribute \src "libresoc.v:163182.3-163183.41" - wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:163338.3-163350.6" - wire $0\divisor_neg$next[0:0]$9932 - attribute \src "libresoc.v:163184.3-163185.39" - wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:163416.3-163428.6" - wire width 64 $0\divisor_radicand$next[63:0]$9950 - attribute \src "libresoc.v:163172.3-163173.49" - wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:162061.7-162061.20" +module \pipe_end + attribute \src "libresoc.v:171004.3-171022.6" + wire width 4 $0\cr_a$next[3:0]$9847 + attribute \src "libresoc.v:170823.3-170824.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:171004.3-171022.6" + wire $0\cr_a_ok$next[0:0]$9848 + attribute \src "libresoc.v:170825.3-170826.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:169664.7-169664.20" wire $0\initial[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 4 $0\logical_op__data_len$next[3:0]$9963 - attribute \src "libresoc.v:163224.3-163225.57" - wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 12 $0\logical_op__fn_unit$next[11:0]$9964 - attribute \src "libresoc.v:163194.3-163195.55" - wire width 12 $0\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$9965 - attribute \src "libresoc.v:163196.3-163197.69" - wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__imm_data__ok$next[0:0]$9966 - attribute \src "libresoc.v:163198.3-163199.65" - wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$9967 - attribute \src "libresoc.v:163212.3-163213.63" - wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 32 $0\logical_op__insn$next[31:0]$9968 - attribute \src "libresoc.v:163226.3-163227.49" - wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$9969 - attribute \src "libresoc.v:163192.3-163193.59" - wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__invert_in$next[0:0]$9970 - attribute \src "libresoc.v:163208.3-163209.59" - wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__invert_out$next[0:0]$9971 - attribute \src "libresoc.v:163214.3-163215.61" - wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__is_32bit$next[0:0]$9972 - attribute \src "libresoc.v:163220.3-163221.57" - wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__is_signed$next[0:0]$9973 - attribute \src "libresoc.v:163222.3-163223.59" - wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__oe__oe$next[0:0]$9974 - attribute \src "libresoc.v:163204.3-163205.53" - wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__oe__ok$next[0:0]$9975 - attribute \src "libresoc.v:163206.3-163207.53" - wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__output_carry$next[0:0]$9976 - attribute \src "libresoc.v:163218.3-163219.65" - wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__rc__ok$next[0:0]$9977 - attribute \src "libresoc.v:163202.3-163203.53" - wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__rc__rc$next[0:0]$9978 - attribute \src "libresoc.v:163200.3-163201.53" - wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__write_cr0$next[0:0]$9979 - attribute \src "libresoc.v:163216.3-163217.59" - wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $0\logical_op__zero_a$next[0:0]$9980 - attribute \src "libresoc.v:163210.3-163211.53" - wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:163460.3-163472.6" - wire width 2 $0\muxid$next[1:0]$9960 - attribute \src "libresoc.v:163228.3-163229.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:163429.3-163441.6" - wire width 2 $0\operation$next[1:0]$9953 - attribute \src "libresoc.v:163170.3-163171.35" - wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:163442.3-163459.6" - wire $0\r_busy$next[0:0]$9956 - attribute \src "libresoc.v:163230.3-163231.29" + attribute \src "libresoc.v:171092.3-171133.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9872 + attribute \src "libresoc.v:170863.3-170864.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9834 + attribute \src "libresoc.v:169705.13-169705.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9918 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9873 + attribute \src "libresoc.v:170833.3-170834.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9804 + attribute \src "libresoc.v:169744.14-169744.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9920 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9874 + attribute \src "libresoc.v:170835.3-170836.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9806 + attribute \src "libresoc.v:169768.14-169768.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9922 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9875 + attribute \src "libresoc.v:170837.3-170838.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9808 + attribute \src "libresoc.v:169777.7-169777.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9924 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9876 + attribute \src "libresoc.v:170851.3-170852.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9822 + attribute \src "libresoc.v:169794.13-169794.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9926 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9877 + attribute \src "libresoc.v:170865.3-170866.57" + wire width 32 $0\logical_op__insn$19[31:0]$9836 + attribute \src "libresoc.v:169807.14-169807.43" + wire width 32 $0\logical_op__insn$19[31:0]$9928 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9878 + attribute \src "libresoc.v:170831.3-170832.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9802 + attribute \src "libresoc.v:169966.13-169966.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9930 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__invert_in$10$next[0:0]$9879 + attribute \src "libresoc.v:170847.3-170848.67" + wire $0\logical_op__invert_in$10[0:0]$9818 + attribute \src "libresoc.v:170050.7-170050.40" + wire $0\logical_op__invert_in$10[0:0]$9932 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__invert_out$13$next[0:0]$9880 + attribute \src "libresoc.v:170853.3-170854.69" + wire $0\logical_op__invert_out$13[0:0]$9824 + attribute \src "libresoc.v:170059.7-170059.41" + wire $0\logical_op__invert_out$13[0:0]$9934 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9881 + attribute \src "libresoc.v:170859.3-170860.65" + wire $0\logical_op__is_32bit$16[0:0]$9830 + attribute \src "libresoc.v:170068.7-170068.39" + wire $0\logical_op__is_32bit$16[0:0]$9936 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__is_signed$17$next[0:0]$9882 + attribute \src "libresoc.v:170861.3-170862.67" + wire $0\logical_op__is_signed$17[0:0]$9832 + attribute \src "libresoc.v:170077.7-170077.40" + wire $0\logical_op__is_signed$17[0:0]$9938 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9883 + attribute \src "libresoc.v:170843.3-170844.59" + wire $0\logical_op__oe__oe$8[0:0]$9814 + attribute \src "libresoc.v:170086.7-170086.36" + wire $0\logical_op__oe__oe$8[0:0]$9940 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9884 + attribute \src "libresoc.v:170845.3-170846.59" + wire $0\logical_op__oe__ok$9[0:0]$9816 + attribute \src "libresoc.v:170097.7-170097.36" + wire $0\logical_op__oe__ok$9[0:0]$9942 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__output_carry$15$next[0:0]$9885 + attribute \src "libresoc.v:170857.3-170858.73" + wire $0\logical_op__output_carry$15[0:0]$9828 + attribute \src "libresoc.v:170104.7-170104.43" + wire $0\logical_op__output_carry$15[0:0]$9944 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9886 + attribute \src "libresoc.v:170841.3-170842.59" + wire $0\logical_op__rc__ok$7[0:0]$9812 + attribute \src "libresoc.v:170113.7-170113.36" + wire $0\logical_op__rc__ok$7[0:0]$9946 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9887 + attribute \src "libresoc.v:170839.3-170840.59" + wire $0\logical_op__rc__rc$6[0:0]$9810 + attribute \src "libresoc.v:170122.7-170122.36" + wire $0\logical_op__rc__rc$6[0:0]$9948 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9888 + attribute \src "libresoc.v:170855.3-170856.67" + wire $0\logical_op__write_cr0$14[0:0]$9826 + attribute \src "libresoc.v:170131.7-170131.40" + wire $0\logical_op__write_cr0$14[0:0]$9950 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__zero_a$11$next[0:0]$9889 + attribute \src "libresoc.v:170849.3-170850.61" + wire $0\logical_op__zero_a$11[0:0]$9820 + attribute \src "libresoc.v:170140.7-170140.37" + wire $0\logical_op__zero_a$11[0:0]$9952 + attribute \src "libresoc.v:171079.3-171091.6" + wire width 2 $0\muxid$1$next[1:0]$9869 + attribute \src "libresoc.v:170867.3-170868.33" + wire width 2 $0\muxid$1[1:0]$9838 + attribute \src "libresoc.v:170149.13-170149.29" + wire width 2 $0\muxid$1[1:0]$9954 + attribute \src "libresoc.v:170985.3-171003.6" + wire width 64 $0\o$next[63:0]$9841 + attribute \src "libresoc.v:170827.3-170828.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:170985.3-171003.6" + wire $0\o_ok$next[0:0]$9842 + attribute \src "libresoc.v:170829.3-170830.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:171061.3-171078.6" + wire $0\r_busy$next[0:0]$9865 + attribute \src "libresoc.v:170869.3-170870.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:163515.3-163527.6" - wire width 64 $0\ra$next[63:0]$10006 - attribute \src "libresoc.v:163190.3-163191.21" - wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:163528.3-163540.6" - wire width 64 $0\rb$next[63:0]$10009 - attribute \src "libresoc.v:163188.3-163189.21" - wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:163541.3-163553.6" - wire $0\xer_so$next[0:0]$10012 - attribute \src "libresoc.v:163186.3-163187.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:163390.3-163402.6" - wire $1\div_by_zero$next[0:0]$9945 - attribute \src "libresoc.v:162070.7-162070.25" - wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:163364.3-163376.6" - wire $1\dive_abs_ov32$next[0:0]$9939 - attribute \src "libresoc.v:162077.7-162077.27" - wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:163377.3-163389.6" - wire $1\dive_abs_ov64$next[0:0]$9942 - attribute \src "libresoc.v:162084.7-162084.27" - wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:163403.3-163415.6" - wire width 128 $1\dividend$next[127:0]$9948 - attribute \src "libresoc.v:162091.15-162091.63" - wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:163351.3-163363.6" - wire $1\dividend_neg$next[0:0]$9936 - attribute \src "libresoc.v:162098.7-162098.26" - wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:163338.3-163350.6" - wire $1\divisor_neg$next[0:0]$9933 - attribute \src "libresoc.v:162105.7-162105.25" - wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:163416.3-163428.6" - wire width 64 $1\divisor_radicand$next[63:0]$9951 - attribute \src "libresoc.v:162112.14-162112.53" - wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 4 $1\logical_op__data_len$next[3:0]$9981 - attribute \src "libresoc.v:162389.13-162389.40" - wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 12 $1\logical_op__fn_unit$next[11:0]$9982 - attribute \src "libresoc.v:162411.14-162411.43" - wire width 12 $1\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$9983 - attribute \src "libresoc.v:162446.14-162446.63" - wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__imm_data__ok$next[0:0]$9984 - attribute \src "libresoc.v:162455.7-162455.38" - wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$9985 - attribute \src "libresoc.v:162468.13-162468.43" - wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 32 $1\logical_op__insn$next[31:0]$9986 - attribute \src "libresoc.v:162485.14-162485.38" - wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$9987 - attribute \src "libresoc.v:162568.13-162568.42" - wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__invert_in$next[0:0]$9988 - attribute \src "libresoc.v:162725.7-162725.35" - wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__invert_out$next[0:0]$9989 - attribute \src "libresoc.v:162734.7-162734.36" - wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__is_32bit$next[0:0]$9990 - attribute \src "libresoc.v:162743.7-162743.34" - wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__is_signed$next[0:0]$9991 - attribute \src "libresoc.v:162752.7-162752.35" - wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__oe__oe$next[0:0]$9992 - attribute \src "libresoc.v:162761.7-162761.32" - wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__oe__ok$next[0:0]$9993 - attribute \src "libresoc.v:162770.7-162770.32" - wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__output_carry$next[0:0]$9994 - attribute \src "libresoc.v:162779.7-162779.38" - wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__rc__ok$next[0:0]$9995 - attribute \src "libresoc.v:162788.7-162788.32" - wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__rc__rc$next[0:0]$9996 - attribute \src "libresoc.v:162797.7-162797.32" - wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__write_cr0$next[0:0]$9997 - attribute \src "libresoc.v:162806.7-162806.35" - wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire $1\logical_op__zero_a$next[0:0]$9998 - attribute \src "libresoc.v:162815.7-162815.32" - wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:163460.3-163472.6" - wire width 2 $1\muxid$next[1:0]$9961 - attribute \src "libresoc.v:162824.13-162824.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:163429.3-163441.6" - wire width 2 $1\operation$next[1:0]$9954 - attribute \src "libresoc.v:162839.13-162839.29" - wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:163442.3-163459.6" - wire $1\r_busy$next[0:0]$9957 - attribute \src "libresoc.v:162853.7-162853.20" + attribute \src "libresoc.v:171023.3-171041.6" + wire width 2 $0\xer_ov$next[1:0]$9853 + attribute \src "libresoc.v:170819.3-170820.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:171023.3-171041.6" + wire $0\xer_ov_ok$next[0:0]$9854 + attribute \src "libresoc.v:170821.3-170822.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:171042.3-171060.6" + wire $0\xer_so$20$next[0:0]$9860 + attribute \src "libresoc.v:170815.3-170816.37" + wire $0\xer_so$20[0:0]$9793 + attribute \src "libresoc.v:170800.7-170800.25" + wire $0\xer_so$20[0:0]$9961 + attribute \src "libresoc.v:171042.3-171060.6" + wire $0\xer_so_ok$next[0:0]$9859 + attribute \src "libresoc.v:170817.3-170818.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:171004.3-171022.6" + wire width 4 $1\cr_a$next[3:0]$9849 + attribute \src "libresoc.v:169673.13-169673.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:171004.3-171022.6" + wire $1\cr_a_ok$next[0:0]$9850 + attribute \src "libresoc.v:169682.7-169682.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:171092.3-171133.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9890 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9891 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9892 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9893 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9894 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9895 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9896 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__invert_in$10$next[0:0]$9897 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__invert_out$13$next[0:0]$9898 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9899 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__is_signed$17$next[0:0]$9900 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9901 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9902 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__output_carry$15$next[0:0]$9903 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9904 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9905 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9906 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__zero_a$11$next[0:0]$9907 + attribute \src "libresoc.v:171079.3-171091.6" + wire width 2 $1\muxid$1$next[1:0]$9870 + attribute \src "libresoc.v:170985.3-171003.6" + wire width 64 $1\o$next[63:0]$9843 + attribute \src "libresoc.v:170162.14-170162.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:170985.3-171003.6" + wire $1\o_ok$next[0:0]$9844 + attribute \src "libresoc.v:170169.7-170169.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:171061.3-171078.6" + wire $1\r_busy$next[0:0]$9866 + attribute \src "libresoc.v:170765.7-170765.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:163515.3-163527.6" - wire width 64 $1\ra$next[63:0]$10007 - attribute \src "libresoc.v:162858.14-162858.39" - wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:163528.3-163540.6" - wire width 64 $1\rb$next[63:0]$10010 - attribute \src "libresoc.v:162869.14-162869.39" - wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:163541.3-163553.6" - wire $1\xer_so$next[0:0]$10013 - attribute \src "libresoc.v:163162.7-163162.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:163473.3-163514.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$9999 - attribute \src "libresoc.v:163473.3-163514.6" - wire $2\logical_op__imm_data__ok$next[0:0]$10000 - attribute \src "libresoc.v:163473.3-163514.6" - wire $2\logical_op__oe__oe$next[0:0]$10001 - attribute \src "libresoc.v:163473.3-163514.6" - wire $2\logical_op__oe__ok$next[0:0]$10002 - attribute \src "libresoc.v:163473.3-163514.6" - wire $2\logical_op__rc__ok$next[0:0]$10003 - attribute \src "libresoc.v:163473.3-163514.6" - wire $2\logical_op__rc__rc$next[0:0]$10004 - attribute \src "libresoc.v:163442.3-163459.6" - wire $2\r_busy$next[0:0]$9958 - attribute \src "libresoc.v:163169.18-163169.118" - wire $and$libresoc.v:163169$9899_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "libresoc.v:171023.3-171041.6" + wire width 2 $1\xer_ov$next[1:0]$9855 + attribute \src "libresoc.v:170780.13-170780.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:171023.3-171041.6" + wire $1\xer_ov_ok$next[0:0]$9856 + attribute \src "libresoc.v:170787.7-170787.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:171042.3-171060.6" + wire $1\xer_so$20$next[0:0]$9862 + attribute \src "libresoc.v:171042.3-171060.6" + wire $1\xer_so_ok$next[0:0]$9861 + attribute \src "libresoc.v:170805.7-170805.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:171004.3-171022.6" + wire $2\cr_a_ok$next[0:0]$9851 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9908 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9909 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9910 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9911 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9912 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9913 + attribute \src "libresoc.v:170985.3-171003.6" + wire $2\o_ok$next[0:0]$9845 + attribute \src "libresoc.v:171061.3-171078.6" + wire $2\r_busy$next[0:0]$9867 + attribute \src "libresoc.v:171023.3-171041.6" + wire $2\xer_ov_ok$next[0:0]$9857 + attribute \src "libresoc.v:171042.3-171060.6" + wire $2\xer_so_ok$next[0:0]$9863 + attribute \src "libresoc.v:170814.18-170814.118" + wire $and$libresoc.v:170814$9791_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 62 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire output 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$94 + wire input 30 \div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$95 + wire input 28 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$93 + wire input 29 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$92 + wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:162061.7-162061.15" + wire input 26 \divisor_neg + attribute \src "libresoc.v:169664.7-169664.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len + wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len$40 + wire width 4 output 52 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$93 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 37 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit$25 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data + wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data$26 + wire width 64 output 38 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok + wire width 64 \logical_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok$27 + wire width 64 \logical_op__imm_data__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$80 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry + wire width 2 input 15 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry$34 + wire width 2 output 46 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn$41 + wire width 2 \logical_op__input_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$94 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -335375,8 +349787,9 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -335386,232 +349799,76 @@ module \pipe_start attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_in$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_32bit$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_signed$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__oe$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__ok$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__output_carry$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__rc$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__write_cr0$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__zero_a$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 53 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 38 \logical_op__fn_unit$3 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 39 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 47 \logical_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 54 \logical_op__insn$19 + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$86 + wire width 7 output 36 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$next + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -335686,8 +349943,191 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \logical_op__insn_type + wire width 7 \logical_op__insn_type$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$58 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$45 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$59 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -335762,8 +350202,9 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 37 \logical_op__insn_type$2 + wire width 7 \output_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -335838,222 +350279,137 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 48 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 52 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$76 + wire width 7 \output_logical_op__insn_type$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \logical_op__oe__ok$9 + wire \output_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$next + wire \output_logical_op__invert_in$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \logical_op__output_carry + wire \output_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \logical_op__output_carry$15 + wire \output_logical_op__invert_out$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$82 + wire \output_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$next + wire \output_logical_op__is_32bit$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \logical_op__rc__ok + wire \output_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \logical_op__rc__ok$7 + wire \output_logical_op__is_signed$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$74 + wire \output_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$next + wire \output_logical_op__oe__oe$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \logical_op__rc__rc + wire \output_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \logical_op__rc__rc$6 + wire \output_logical_op__oe__ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$73 + wire \output_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$next + wire \output_logical_op__output_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \logical_op__write_cr0 + wire \output_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \logical_op__write_cr0$14 + wire \output_logical_op__rc__ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$81 + wire \output_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$next + wire \output_logical_op__rc__rc$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \logical_op__zero_a + wire \output_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \logical_op__zero_a$11 + wire \output_logical_op__write_cr0$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$78 + wire \output_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 36 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$68 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 35 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 34 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 56 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next + wire \output_logical_op__zero_a$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \setup_stage_div_by_zero + wire \output_stage_div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \setup_stage_dive_abs_ov32 + wire \output_stage_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \setup_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \setup_stage_dividend + wire \output_stage_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \setup_stage_dividend_neg + wire \output_stage_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \setup_stage_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \setup_stage_divisor_radicand + wire \output_stage_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len + wire width 4 \output_stage_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len$62 + wire width 4 \output_stage_logical_op__data_len$38 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \setup_stage_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_stage_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \setup_stage_logical_op__fn_unit$47 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_stage_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__data + wire width 64 \output_stage_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__data$48 + wire width 64 \output_stage_logical_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__imm_data__ok + wire \output_stage_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__imm_data__ok$49 + wire \output_stage_logical_op__imm_data__ok$25 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry + wire width 2 \output_stage_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry$56 + wire width 2 \output_stage_logical_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn + wire width 32 \output_stage_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn$63 + wire width 32 \output_stage_logical_op__insn$39 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -336128,8 +350484,9 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type + wire width 7 \output_stage_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -336204,7823 +350561,8130 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_out + wire width 7 \output_stage_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_out$57 + wire \output_stage_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_32bit + wire \output_stage_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_32bit$60 + wire \output_stage_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_signed + wire \output_stage_logical_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_signed$61 + wire \output_stage_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__oe + wire \output_stage_logical_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__oe$52 + wire \output_stage_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__ok + wire \output_stage_logical_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__ok$53 + wire \output_stage_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__output_carry + wire \output_stage_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__output_carry$59 + wire \output_stage_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__ok + wire \output_stage_logical_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__ok$51 + wire \output_stage_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__rc + wire \output_stage_logical_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__rc$50 + wire \output_stage_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__write_cr0 + wire \output_stage_logical_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__write_cr0$58 + wire \output_stage_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__zero_a + wire \output_stage_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__zero_a$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \setup_stage_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \setup_stage_muxid$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \setup_stage_operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \setup_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \setup_stage_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 57 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:163169$9899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$65 - connect \B \p_ready_o - connect \Y $and$libresoc.v:163169$9899_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:163232.14-163277.4" - cell \input$78 \input - connect \logical_op__data_len \input_logical_op__data_len - connect \logical_op__data_len$18 \input_logical_op__data_len$40 - connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 - connect \logical_op__imm_data__data \input_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 - connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 - connect \logical_op__input_carry \input_logical_op__input_carry - connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 - connect \logical_op__insn \input_logical_op__insn - connect \logical_op__insn$19 \input_logical_op__insn$41 - connect \logical_op__insn_type \input_logical_op__insn_type - connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 - connect \logical_op__invert_in \input_logical_op__invert_in - connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 - connect \logical_op__invert_out \input_logical_op__invert_out - connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 - connect \logical_op__is_32bit \input_logical_op__is_32bit - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 - connect \logical_op__is_signed \input_logical_op__is_signed - connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 - connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 - connect \logical_op__oe__ok \input_logical_op__oe__ok - connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 - connect \logical_op__output_carry \input_logical_op__output_carry - connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 - connect \logical_op__rc__ok \input_logical_op__rc__ok - connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 - connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 - connect \logical_op__write_cr0 \input_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 - connect \logical_op__zero_a \input_logical_op__zero_a - connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$23 - connect \ra \input_ra - connect \ra$20 \input_ra$42 - connect \rb \input_rb - connect \rb$21 \input_rb$43 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$44 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:163278.10-163281.4" - cell \n$77 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:163282.10-163285.4" - cell \p$76 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:163286.15-163337.4" - cell \setup_stage \setup_stage - connect \div_by_zero \setup_stage_div_by_zero - connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 - connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 - connect \dividend \setup_stage_dividend - connect \dividend_neg \setup_stage_dividend_neg - connect \divisor_neg \setup_stage_divisor_neg - connect \divisor_radicand \setup_stage_divisor_radicand - connect \logical_op__data_len \setup_stage_logical_op__data_len - connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 - connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit - connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 - connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 - connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 - connect \logical_op__input_carry \setup_stage_logical_op__input_carry - connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 - connect \logical_op__insn \setup_stage_logical_op__insn - connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 - connect \logical_op__insn_type \setup_stage_logical_op__insn_type - connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 - connect \logical_op__invert_in \setup_stage_logical_op__invert_in - connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 - connect \logical_op__invert_out \setup_stage_logical_op__invert_out - connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 - connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit - connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 - connect \logical_op__is_signed \setup_stage_logical_op__is_signed - connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 - connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe - connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 - connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok - connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 - connect \logical_op__output_carry \setup_stage_logical_op__output_carry - connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 - connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok - connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 - connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc - connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 - connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 - connect \logical_op__zero_a \setup_stage_logical_op__zero_a - connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 - connect \muxid \setup_stage_muxid - connect \muxid$1 \setup_stage_muxid$45 - connect \operation \setup_stage_operation - connect \ra \setup_stage_ra - connect \rb \setup_stage_rb - connect \xer_so \setup_stage_xer_so - connect \xer_so$20 \setup_stage_xer_so$64 - end - attribute \src "libresoc.v:162061.7-162061.20" - process $proc$libresoc.v:162061$10014 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:162070.7-162070.25" - process $proc$libresoc.v:162070$10015 - assign { } { } - assign $1\div_by_zero[0:0] 1'0 - sync always - sync init - update \div_by_zero $1\div_by_zero[0:0] - end - attribute \src "libresoc.v:162077.7-162077.27" - process $proc$libresoc.v:162077$10016 - assign { } { } - assign $1\dive_abs_ov32[0:0] 1'0 - sync always - sync init - update \dive_abs_ov32 $1\dive_abs_ov32[0:0] - end - attribute \src "libresoc.v:162084.7-162084.27" - process $proc$libresoc.v:162084$10017 - assign { } { } - assign $1\dive_abs_ov64[0:0] 1'0 - sync always - sync init - update \dive_abs_ov64 $1\dive_abs_ov64[0:0] - end - attribute \src "libresoc.v:162091.15-162091.63" - process $proc$libresoc.v:162091$10018 - assign { } { } - assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dividend $1\dividend[127:0] - end - attribute \src "libresoc.v:162098.7-162098.26" - process $proc$libresoc.v:162098$10019 - assign { } { } - assign $1\dividend_neg[0:0] 1'0 - sync always - sync init - update \dividend_neg $1\dividend_neg[0:0] - end - attribute \src "libresoc.v:162105.7-162105.25" - process $proc$libresoc.v:162105$10020 - assign { } { } - assign $1\divisor_neg[0:0] 1'0 - sync always - sync init - update \divisor_neg $1\divisor_neg[0:0] - end - attribute \src "libresoc.v:162112.14-162112.53" - process $proc$libresoc.v:162112$10021 - assign { } { } - assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \divisor_radicand $1\divisor_radicand[63:0] - end - attribute \src "libresoc.v:162389.13-162389.40" - process $proc$libresoc.v:162389$10022 - assign { } { } - assign $1\logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \logical_op__data_len $1\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:162411.14-162411.43" - process $proc$libresoc.v:162411$10023 - assign { } { } - assign $1\logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:162446.14-162446.63" - process $proc$libresoc.v:162446$10024 - assign { } { } - assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:162455.7-162455.38" - process $proc$libresoc.v:162455$10025 - assign { } { } - assign $1\logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:162468.13-162468.43" - process $proc$libresoc.v:162468$10026 - assign { } { } - assign $1\logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \logical_op__input_carry $1\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:162485.14-162485.38" - process $proc$libresoc.v:162485$10027 - assign { } { } - assign $1\logical_op__insn[31:0] 0 - sync always - sync init - update \logical_op__insn $1\logical_op__insn[31:0] - end - attribute \src "libresoc.v:162568.13-162568.42" - process $proc$libresoc.v:162568$10028 - assign { } { } - assign $1\logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \logical_op__insn_type $1\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:162725.7-162725.35" - process $proc$libresoc.v:162725$10029 - assign { } { } - assign $1\logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \logical_op__invert_in $1\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:162734.7-162734.36" - process $proc$libresoc.v:162734$10030 - assign { } { } - assign $1\logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \logical_op__invert_out $1\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:162743.7-162743.34" - process $proc$libresoc.v:162743$10031 - assign { } { } - assign $1\logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:162752.7-162752.35" - process $proc$libresoc.v:162752$10032 - assign { } { } - assign $1\logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \logical_op__is_signed $1\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:162761.7-162761.32" - process $proc$libresoc.v:162761$10033 - assign { } { } - assign $1\logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:162770.7-162770.32" - process $proc$libresoc.v:162770$10034 - assign { } { } - assign $1\logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:162779.7-162779.38" - process $proc$libresoc.v:162779$10035 - assign { } { } - assign $1\logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \logical_op__output_carry $1\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:162788.7-162788.32" - process $proc$libresoc.v:162788$10036 - assign { } { } - assign $1\logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:162797.7-162797.32" - process $proc$libresoc.v:162797$10037 - assign { } { } - assign $1\logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:162806.7-162806.35" - process $proc$libresoc.v:162806$10038 - assign { } { } - assign $1\logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:162815.7-162815.32" - process $proc$libresoc.v:162815$10039 - assign { } { } - assign $1\logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \logical_op__zero_a $1\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:162824.13-162824.25" - process $proc$libresoc.v:162824$10040 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:162839.13-162839.29" - process $proc$libresoc.v:162839$10041 - assign { } { } - assign $1\operation[1:0] 2'00 - sync always - sync init - update \operation $1\operation[1:0] - end - attribute \src "libresoc.v:162853.7-162853.20" - process $proc$libresoc.v:162853$10042 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:162858.14-162858.39" - process $proc$libresoc.v:162858$10043 - assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra $1\ra[63:0] - end - attribute \src "libresoc.v:162869.14-162869.39" - process $proc$libresoc.v:162869$10044 - assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb $1\rb[63:0] - end - attribute \src "libresoc.v:163162.7-163162.20" - process $proc$libresoc.v:163162$10045 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:163170.3-163171.35" - process $proc$libresoc.v:163170$9900 - assign { } { } - assign $0\operation[1:0] \operation$next - sync posedge \coresync_clk - update \operation $0\operation[1:0] - end - attribute \src "libresoc.v:163172.3-163173.49" - process $proc$libresoc.v:163172$9901 - assign { } { } - assign $0\divisor_radicand[63:0] \divisor_radicand$next - sync posedge \coresync_clk - update \divisor_radicand $0\divisor_radicand[63:0] - end - attribute \src "libresoc.v:163174.3-163175.33" - process $proc$libresoc.v:163174$9902 - assign { } { } - assign $0\dividend[127:0] \dividend$next - sync posedge \coresync_clk - update \dividend $0\dividend[127:0] - end - attribute \src "libresoc.v:163176.3-163177.39" - process $proc$libresoc.v:163176$9903 - assign { } { } - assign $0\div_by_zero[0:0] \div_by_zero$next - sync posedge \coresync_clk - update \div_by_zero $0\div_by_zero[0:0] - end - attribute \src "libresoc.v:163178.3-163179.43" - process $proc$libresoc.v:163178$9904 - assign { } { } - assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next - sync posedge \coresync_clk - update \dive_abs_ov64 $0\dive_abs_ov64[0:0] - end - attribute \src "libresoc.v:163180.3-163181.43" - process $proc$libresoc.v:163180$9905 - assign { } { } - assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next - sync posedge \coresync_clk - update \dive_abs_ov32 $0\dive_abs_ov32[0:0] - end - attribute \src "libresoc.v:163182.3-163183.41" - process $proc$libresoc.v:163182$9906 - assign { } { } - assign $0\dividend_neg[0:0] \dividend_neg$next - sync posedge \coresync_clk - update \dividend_neg $0\dividend_neg[0:0] - end - attribute \src "libresoc.v:163184.3-163185.39" - process $proc$libresoc.v:163184$9907 - assign { } { } - assign $0\divisor_neg[0:0] \divisor_neg$next - sync posedge \coresync_clk - update \divisor_neg $0\divisor_neg[0:0] - end - attribute \src "libresoc.v:163186.3-163187.29" - process $proc$libresoc.v:163186$9908 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:163188.3-163189.21" - process $proc$libresoc.v:163188$9909 - assign { } { } - assign $0\rb[63:0] \rb$next - sync posedge \coresync_clk - update \rb $0\rb[63:0] - end - attribute \src "libresoc.v:163190.3-163191.21" - process $proc$libresoc.v:163190$9910 - assign { } { } - assign $0\ra[63:0] \ra$next - sync posedge \coresync_clk - update \ra $0\ra[63:0] - end - attribute \src "libresoc.v:163192.3-163193.59" - process $proc$libresoc.v:163192$9911 - assign { } { } - assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next - sync posedge \coresync_clk - update \logical_op__insn_type $0\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:163194.3-163195.55" - process $proc$libresoc.v:163194$9912 - assign { } { } - assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next - sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:163196.3-163197.69" - process $proc$libresoc.v:163196$9913 - assign { } { } - assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next - sync posedge \coresync_clk - update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:163198.3-163199.65" - process $proc$libresoc.v:163198$9914 - assign { } { } - assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:163200.3-163201.53" - process $proc$libresoc.v:163200$9915 - assign { } { } - assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next - sync posedge \coresync_clk - update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:163202.3-163203.53" - process $proc$libresoc.v:163202$9916 - assign { } { } - assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next - sync posedge \coresync_clk - update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:163204.3-163205.53" - process $proc$libresoc.v:163204$9917 - assign { } { } - assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next - sync posedge \coresync_clk - update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:163206.3-163207.53" - process $proc$libresoc.v:163206$9918 - assign { } { } - assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next - sync posedge \coresync_clk - update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:163208.3-163209.59" - process $proc$libresoc.v:163208$9919 - assign { } { } - assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next - sync posedge \coresync_clk - update \logical_op__invert_in $0\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:163210.3-163211.53" - process $proc$libresoc.v:163210$9920 - assign { } { } - assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next - sync posedge \coresync_clk - update \logical_op__zero_a $0\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:163212.3-163213.63" - process $proc$libresoc.v:163212$9921 - assign { } { } - assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next - sync posedge \coresync_clk - update \logical_op__input_carry $0\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:163214.3-163215.61" - process $proc$libresoc.v:163214$9922 - assign { } { } - assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next - sync posedge \coresync_clk - update \logical_op__invert_out $0\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:163216.3-163217.59" - process $proc$libresoc.v:163216$9923 - assign { } { } - assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next - sync posedge \coresync_clk - update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:163218.3-163219.65" - process $proc$libresoc.v:163218$9924 - assign { } { } - assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next - sync posedge \coresync_clk - update \logical_op__output_carry $0\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:163220.3-163221.57" - process $proc$libresoc.v:163220$9925 - assign { } { } - assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next - sync posedge \coresync_clk - update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:163222.3-163223.59" - process $proc$libresoc.v:163222$9926 - assign { } { } - assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next - sync posedge \coresync_clk - update \logical_op__is_signed $0\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:163224.3-163225.57" - process $proc$libresoc.v:163224$9927 - assign { } { } - assign $0\logical_op__data_len[3:0] \logical_op__data_len$next - sync posedge \coresync_clk - update \logical_op__data_len $0\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:163226.3-163227.49" - process $proc$libresoc.v:163226$9928 - assign { } { } - assign $0\logical_op__insn[31:0] \logical_op__insn$next - sync posedge \coresync_clk - update \logical_op__insn $0\logical_op__insn[31:0] - end - attribute \src "libresoc.v:163228.3-163229.27" - process $proc$libresoc.v:163228$9929 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:163230.3-163231.29" - process $proc$libresoc.v:163230$9930 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:163338.3-163350.6" - process $proc$libresoc.v:163338$9931 - assign { } { } - assign { } { } - assign $0\divisor_neg$next[0:0]$9932 $1\divisor_neg$next[0:0]$9933 - attribute \src "libresoc.v:163339.5-163339.29" - switch \initial - attribute \src "libresoc.v:163339.9-163339.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\divisor_neg$next[0:0]$9933 \divisor_neg$92 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\divisor_neg$next[0:0]$9933 \divisor_neg$92 - case - assign $1\divisor_neg$next[0:0]$9933 \divisor_neg - end - sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$9932 - end - attribute \src "libresoc.v:163351.3-163363.6" - process $proc$libresoc.v:163351$9934 - assign { } { } - assign { } { } - assign $0\dividend_neg$next[0:0]$9935 $1\dividend_neg$next[0:0]$9936 - attribute \src "libresoc.v:163352.5-163352.29" - switch \initial - attribute \src "libresoc.v:163352.9-163352.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dividend_neg$next[0:0]$9936 \dividend_neg$93 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dividend_neg$next[0:0]$9936 \dividend_neg$93 - case - assign $1\dividend_neg$next[0:0]$9936 \dividend_neg - end - sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$9935 - end - attribute \src "libresoc.v:163364.3-163376.6" - process $proc$libresoc.v:163364$9937 - assign { } { } - assign { } { } - assign $0\dive_abs_ov32$next[0:0]$9938 $1\dive_abs_ov32$next[0:0]$9939 - attribute \src "libresoc.v:163365.5-163365.29" - switch \initial - attribute \src "libresoc.v:163365.9-163365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dive_abs_ov32$next[0:0]$9939 \dive_abs_ov32$94 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dive_abs_ov32$next[0:0]$9939 \dive_abs_ov32$94 - case - assign $1\dive_abs_ov32$next[0:0]$9939 \dive_abs_ov32 - end - sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$9938 - end - attribute \src "libresoc.v:163377.3-163389.6" - process $proc$libresoc.v:163377$9940 - assign { } { } - assign { } { } - assign $0\dive_abs_ov64$next[0:0]$9941 $1\dive_abs_ov64$next[0:0]$9942 - attribute \src "libresoc.v:163378.5-163378.29" - switch \initial - attribute \src "libresoc.v:163378.9-163378.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dive_abs_ov64$next[0:0]$9942 \dive_abs_ov64$95 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dive_abs_ov64$next[0:0]$9942 \dive_abs_ov64$95 - case - assign $1\dive_abs_ov64$next[0:0]$9942 \dive_abs_ov64 - end - sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$9941 - end - attribute \src "libresoc.v:163390.3-163402.6" - process $proc$libresoc.v:163390$9943 - assign { } { } - assign { } { } - assign $0\div_by_zero$next[0:0]$9944 $1\div_by_zero$next[0:0]$9945 - attribute \src "libresoc.v:163391.5-163391.29" - switch \initial - attribute \src "libresoc.v:163391.9-163391.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\div_by_zero$next[0:0]$9945 \div_by_zero$96 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\div_by_zero$next[0:0]$9945 \div_by_zero$96 - case - assign $1\div_by_zero$next[0:0]$9945 \div_by_zero - end - sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$9944 - end - attribute \src "libresoc.v:163403.3-163415.6" - process $proc$libresoc.v:163403$9946 - assign { } { } - assign { } { } - assign $0\dividend$next[127:0]$9947 $1\dividend$next[127:0]$9948 - attribute \src "libresoc.v:163404.5-163404.29" - switch \initial - attribute \src "libresoc.v:163404.9-163404.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dividend$next[127:0]$9948 \dividend$97 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dividend$next[127:0]$9948 \dividend$97 - case - assign $1\dividend$next[127:0]$9948 \dividend - end - sync always - update \dividend$next $0\dividend$next[127:0]$9947 + wire \output_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_stage_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_stage_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_stage_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_stage_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \output_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \output_stage_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_stage_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_stage_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \output_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_stage_xer_so$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 31 \quotient_root + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 32 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 58 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 59 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 60 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 61 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:170814$9791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$73 + connect \B \p_ready_o + connect \Y $and$libresoc.v:170814$9791_Y end - attribute \src "libresoc.v:163416.3-163428.6" - process $proc$libresoc.v:163416$9949 - assign { } { } - assign { } { } - assign $0\divisor_radicand$next[63:0]$9950 $1\divisor_radicand$next[63:0]$9951 - attribute \src "libresoc.v:163417.5-163417.29" - switch \initial - attribute \src "libresoc.v:163417.9-163417.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\divisor_radicand$next[63:0]$9951 \divisor_radicand$98 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\divisor_radicand$next[63:0]$9951 \divisor_radicand$98 - case - assign $1\divisor_radicand$next[63:0]$9951 \divisor_radicand - end - sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$9950 + attribute \module_not_derived 1 + attribute \src "libresoc.v:170871.10-170874.4" + cell \n$82 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end - attribute \src "libresoc.v:163429.3-163441.6" - process $proc$libresoc.v:163429$9952 - assign { } { } - assign { } { } - assign $0\operation$next[1:0]$9953 $1\operation$next[1:0]$9954 - attribute \src "libresoc.v:163430.5-163430.29" - switch \initial - attribute \src "libresoc.v:163430.9-163430.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\operation$next[1:0]$9954 \operation$99 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\operation$next[1:0]$9954 \operation$99 - case - assign $1\operation$next[1:0]$9954 \operation - end - sync always - update \operation$next $0\operation$next[1:0]$9953 + attribute \module_not_derived 1 + attribute \src "libresoc.v:170875.15-170927.4" + cell \output$83 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$62 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$58 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$59 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$41 + connect \o \output_o + connect \o$20 \output_o$60 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$61 + connect \xer_ov \output_xer_ov + connect \xer_ov$23 \output_xer_ov$63 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$24 \output_xer_so$64 + connect \xer_so_ok \output_xer_so_ok end - attribute \src "libresoc.v:163442.3-163459.6" - process $proc$libresoc.v:163442$9955 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$9956 $2\r_busy$next[0:0]$9958 - attribute \src "libresoc.v:163443.5-163443.29" - switch \initial - attribute \src "libresoc.v:163443.9-163443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$9957 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$9957 1'0 - case - assign $1\r_busy$next[0:0]$9957 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$9958 1'0 - case - assign $2\r_busy$next[0:0]$9958 $1\r_busy$next[0:0]$9957 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$9956 + attribute \module_not_derived 1 + attribute \src "libresoc.v:170928.16-170980.4" + cell \output_stage \output_stage + connect \div_by_zero \output_stage_div_by_zero + connect \dive_abs_ov32 \output_stage_dive_abs_ov32 + connect \dive_abs_ov64 \output_stage_dive_abs_ov64 + connect \dividend_neg \output_stage_dividend_neg + connect \divisor_neg \output_stage_divisor_neg + connect \logical_op__data_len \output_stage_logical_op__data_len + connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 + connect \logical_op__fn_unit \output_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 + connect \logical_op__insn \output_stage_logical_op__insn + connect \logical_op__insn$19 \output_stage_logical_op__insn$39 + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 + connect \logical_op__oe__ok \output_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 + connect \logical_op__rc__ok \output_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 + connect \logical_op__zero_a \output_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 + connect \muxid \output_stage_muxid + connect \muxid$1 \output_stage_muxid$21 + connect \o \output_stage_o + connect \o_ok \output_stage_o_ok + connect \quotient_root \output_stage_quotient_root + connect \remainder \output_stage_remainder + connect \xer_ov \output_stage_xer_ov + connect \xer_ov_ok \output_stage_xer_ov_ok + connect \xer_so \output_stage_xer_so + connect \xer_so$20 \output_stage_xer_so$40 end - attribute \src "libresoc.v:163460.3-163472.6" - process $proc$libresoc.v:163460$9959 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$9960 $1\muxid$next[1:0]$9961 - attribute \src "libresoc.v:163461.5-163461.29" - switch \initial - attribute \src "libresoc.v:163461.9-163461.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$9961 \muxid$68 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$9961 \muxid$68 - case - assign $1\muxid$next[1:0]$9961 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$9960 + attribute \module_not_derived 1 + attribute \src "libresoc.v:170981.10-170984.4" + cell \p$81 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:163473.3-163514.6" - process $proc$libresoc.v:163473$9962 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$next[3:0]$9963 $1\logical_op__data_len$next[3:0]$9981 - assign $0\logical_op__fn_unit$next[11:0]$9964 $1\logical_op__fn_unit$next[11:0]$9982 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$next[1:0]$9967 $1\logical_op__input_carry$next[1:0]$9985 - assign $0\logical_op__insn$next[31:0]$9968 $1\logical_op__insn$next[31:0]$9986 - assign $0\logical_op__insn_type$next[6:0]$9969 $1\logical_op__insn_type$next[6:0]$9987 - assign $0\logical_op__invert_in$next[0:0]$9970 $1\logical_op__invert_in$next[0:0]$9988 - assign $0\logical_op__invert_out$next[0:0]$9971 $1\logical_op__invert_out$next[0:0]$9989 - assign $0\logical_op__is_32bit$next[0:0]$9972 $1\logical_op__is_32bit$next[0:0]$9990 - assign $0\logical_op__is_signed$next[0:0]$9973 $1\logical_op__is_signed$next[0:0]$9991 - assign { } { } + attribute \src "libresoc.v:169664.7-169664.20" + process $proc$libresoc.v:169664$9914 assign { } { } - assign $0\logical_op__output_carry$next[0:0]$9976 $1\logical_op__output_carry$next[0:0]$9994 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$9979 $1\logical_op__write_cr0$next[0:0]$9997 - assign $0\logical_op__zero_a$next[0:0]$9980 $1\logical_op__zero_a$next[0:0]$9998 - assign $0\logical_op__imm_data__data$next[63:0]$9965 $2\logical_op__imm_data__data$next[63:0]$9999 - assign $0\logical_op__imm_data__ok$next[0:0]$9966 $2\logical_op__imm_data__ok$next[0:0]$10000 - assign $0\logical_op__oe__oe$next[0:0]$9974 $2\logical_op__oe__oe$next[0:0]$10001 - assign $0\logical_op__oe__ok$next[0:0]$9975 $2\logical_op__oe__ok$next[0:0]$10002 - assign $0\logical_op__rc__ok$next[0:0]$9977 $2\logical_op__rc__ok$next[0:0]$10003 - assign $0\logical_op__rc__rc$next[0:0]$9978 $2\logical_op__rc__rc$next[0:0]$10004 - attribute \src "libresoc.v:163474.5-163474.29" - switch \initial - attribute \src "libresoc.v:163474.9-163474.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$9986 $1\logical_op__data_len$next[3:0]$9981 $1\logical_op__is_signed$next[0:0]$9991 $1\logical_op__is_32bit$next[0:0]$9990 $1\logical_op__output_carry$next[0:0]$9994 $1\logical_op__write_cr0$next[0:0]$9997 $1\logical_op__invert_out$next[0:0]$9989 $1\logical_op__input_carry$next[1:0]$9985 $1\logical_op__zero_a$next[0:0]$9998 $1\logical_op__invert_in$next[0:0]$9988 $1\logical_op__oe__ok$next[0:0]$9993 $1\logical_op__oe__oe$next[0:0]$9992 $1\logical_op__rc__ok$next[0:0]$9995 $1\logical_op__rc__rc$next[0:0]$9996 $1\logical_op__imm_data__ok$next[0:0]$9984 $1\logical_op__imm_data__data$next[63:0]$9983 $1\logical_op__fn_unit$next[11:0]$9982 $1\logical_op__insn_type$next[6:0]$9987 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$9986 $1\logical_op__data_len$next[3:0]$9981 $1\logical_op__is_signed$next[0:0]$9991 $1\logical_op__is_32bit$next[0:0]$9990 $1\logical_op__output_carry$next[0:0]$9994 $1\logical_op__write_cr0$next[0:0]$9997 $1\logical_op__invert_out$next[0:0]$9989 $1\logical_op__input_carry$next[1:0]$9985 $1\logical_op__zero_a$next[0:0]$9998 $1\logical_op__invert_in$next[0:0]$9988 $1\logical_op__oe__ok$next[0:0]$9993 $1\logical_op__oe__oe$next[0:0]$9992 $1\logical_op__rc__ok$next[0:0]$9995 $1\logical_op__rc__rc$next[0:0]$9996 $1\logical_op__imm_data__ok$next[0:0]$9984 $1\logical_op__imm_data__data$next[63:0]$9983 $1\logical_op__fn_unit$next[11:0]$9982 $1\logical_op__insn_type$next[6:0]$9987 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } - case - assign $1\logical_op__data_len$next[3:0]$9981 \logical_op__data_len - assign $1\logical_op__fn_unit$next[11:0]$9982 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$9983 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$9984 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$9985 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$9986 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$9987 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$9988 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$9989 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$9990 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$9991 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$9992 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$9993 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$9994 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$9995 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$9996 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$9997 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$9998 \logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$9999 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$10000 1'0 - assign $2\logical_op__rc__rc$next[0:0]$10004 1'0 - assign $2\logical_op__rc__ok$next[0:0]$10003 1'0 - assign $2\logical_op__oe__oe$next[0:0]$10001 1'0 - assign $2\logical_op__oe__ok$next[0:0]$10002 1'0 - case - assign $2\logical_op__imm_data__data$next[63:0]$9999 $1\logical_op__imm_data__data$next[63:0]$9983 - assign $2\logical_op__imm_data__ok$next[0:0]$10000 $1\logical_op__imm_data__ok$next[0:0]$9984 - assign $2\logical_op__oe__oe$next[0:0]$10001 $1\logical_op__oe__oe$next[0:0]$9992 - assign $2\logical_op__oe__ok$next[0:0]$10002 $1\logical_op__oe__ok$next[0:0]$9993 - assign $2\logical_op__rc__ok$next[0:0]$10003 $1\logical_op__rc__ok$next[0:0]$9995 - assign $2\logical_op__rc__rc$next[0:0]$10004 $1\logical_op__rc__rc$next[0:0]$9996 - end + assign $0\initial[0:0] 1'0 sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$9963 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$9964 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$9965 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$9966 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$9967 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$9968 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$9969 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$9970 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$9971 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$9972 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$9973 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$9974 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$9975 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$9976 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$9977 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$9978 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$9979 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$9980 + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:163515.3-163527.6" - process $proc$libresoc.v:163515$10005 + attribute \src "libresoc.v:169673.13-169673.24" + process $proc$libresoc.v:169673$9915 assign { } { } - assign { } { } - assign $0\ra$next[63:0]$10006 $1\ra$next[63:0]$10007 - attribute \src "libresoc.v:163516.5-163516.29" - switch \initial - attribute \src "libresoc.v:163516.9-163516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ra$next[63:0]$10007 \ra$87 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ra$next[63:0]$10007 \ra$87 - case - assign $1\ra$next[63:0]$10007 \ra - end + assign $1\cr_a[3:0] 4'0000 sync always - update \ra$next $0\ra$next[63:0]$10006 + sync init + update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:163528.3-163540.6" - process $proc$libresoc.v:163528$10008 - assign { } { } + attribute \src "libresoc.v:169682.7-169682.21" + process $proc$libresoc.v:169682$9916 assign { } { } - assign $0\rb$next[63:0]$10009 $1\rb$next[63:0]$10010 - attribute \src "libresoc.v:163529.5-163529.29" - switch \initial - attribute \src "libresoc.v:163529.9-163529.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\rb$next[63:0]$10010 \rb$89 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\rb$next[63:0]$10010 \rb$89 - case - assign $1\rb$next[63:0]$10010 \rb - end + assign $1\cr_a_ok[0:0] 1'0 sync always - update \rb$next $0\rb$next[63:0]$10009 + sync init + update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:163541.3-163553.6" - process $proc$libresoc.v:163541$10011 + attribute \src "libresoc.v:169705.13-169705.45" + process $proc$libresoc.v:169705$9917 assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$10012 $1\xer_so$next[0:0]$10013 - attribute \src "libresoc.v:163542.5-163542.29" - switch \initial - attribute \src "libresoc.v:163542.9-163542.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\xer_so$next[0:0]$10013 \xer_so$91 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\xer_so$next[0:0]$10013 \xer_so$91 - case - assign $1\xer_so$next[0:0]$10013 \xer_so - end + assign $0\logical_op__data_len$18[3:0]$9918 4'0000 sync always - update \xer_so$next $0\xer_so$next[0:0]$10012 - end - connect \$66 $and$libresoc.v:163169$9899_Y - connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \operation$99 \setup_stage_operation - connect \divisor_radicand$98 \setup_stage_divisor_radicand - connect \dividend$97 \setup_stage_dividend - connect \div_by_zero$96 \setup_stage_div_by_zero - connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 - connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 - connect \dividend_neg$93 \setup_stage_dividend_neg - connect \divisor_neg$92 \setup_stage_divisor_neg - connect \xer_so$91 \setup_stage_xer_so$64 - connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 - connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } - connect \muxid$68 \setup_stage_muxid$45 - connect \p_valid_i_p_ready_o \$66 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$65 \p_valid_i - connect \setup_stage_xer_so \input_xer_so$44 - connect \setup_stage_rb \input_rb$43 - connect \setup_stage_ra \input_ra$42 - connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } - connect \setup_stage_muxid \input_muxid$23 - connect \input_xer_so \xer_so$22 - connect \input_rb \rb$21 - connect \input_ra \ra$20 - connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "libresoc.v:163588.1-163632.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.pll" -attribute \generator "nMigen" -module \pll - attribute \src "libresoc.v:163589.7-163589.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:163621.3-163630.6" - wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:163611.3-163620.6" - wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:163621.3-163630.6" - wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:163611.3-163620.6" - wire $1\pll_lck_o[0:0] - attribute \src "libresoc.v:163608.17-163608.105" - wire $eq$libresoc.v:163608$10046_Y - attribute \src "libresoc.v:163609.17-163609.105" - wire $eq$libresoc.v:163609$10047_Y - attribute \src "libresoc.v:163610.17-163610.98" - wire $not$libresoc.v:163610$10048_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" - wire input 1 \clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" - wire output 5 \clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:163589.7-163589.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" - wire output 2 \pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 4 \pll_lck_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:163608$10046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \clk_sel_i - connect \B 2'00 - connect \Y $eq$libresoc.v:163608$10046_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:163609$10047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \clk_sel_i - connect \B 2'00 - connect \Y $eq$libresoc.v:163609$10047_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:163610$10048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk_24_i - connect \Y $not$libresoc.v:163610$10048_Y + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9918 end - attribute \src "libresoc.v:163589.7-163589.20" - process $proc$libresoc.v:163589$10051 + attribute \src "libresoc.v:169744.14-169744.48" + process $proc$libresoc.v:169744$9919 assign { } { } - assign $0\initial[0:0] 1'0 + assign $0\logical_op__fn_unit$3[13:0]$9920 14'00000000000000 sync always - update \initial $0\initial[0:0] sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9920 end - attribute \src "libresoc.v:163611.3-163620.6" - process $proc$libresoc.v:163611$10049 + attribute \src "libresoc.v:169768.14-169768.67" + process $proc$libresoc.v:169768$9921 assign { } { } - assign { } { } - assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:163612.5-163612.29" - switch \initial - attribute \src "libresoc.v:163612.9-163612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pll_lck_o[0:0] \clk_24_i - case - assign $1\pll_lck_o[0:0] 1'0 - end + assign $0\logical_op__imm_data__data$4[63:0]$9922 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \pll_lck_o $0\pll_lck_o[0:0] + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9922 end - attribute \src "libresoc.v:163621.3-163630.6" - process $proc$libresoc.v:163621$10050 - assign { } { } + attribute \src "libresoc.v:169777.7-169777.42" + process $proc$libresoc.v:169777$9923 assign { } { } - assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:163622.5-163622.29" - switch \initial - attribute \src "libresoc.v:163622.9-163622.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pll_18_o[0:0] \$5 - case - assign $1\pll_18_o[0:0] 1'0 - end - sync always - update \pll_18_o $0\pll_18_o[0:0] - end - connect \$1 $eq$libresoc.v:163608$10046_Y - connect \$3 $eq$libresoc.v:163609$10047_Y - connect \$5 $not$libresoc.v:163610$10048_Y - connect \clk_pll_o \clk_24_i -end -attribute \src "libresoc.v:163636.1-164278.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" -attribute \generator "nMigen" -module \popcount - attribute \src "libresoc.v:163637.7-163637.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:164125.3-164151.6" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:164125.3-164151.6" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:164049.19-164049.132" - wire width 4 $add$libresoc.v:164049$10052_Y - attribute \src "libresoc.v:164050.19-164050.132" - wire width 4 $add$libresoc.v:164050$10053_Y - attribute \src "libresoc.v:164051.19-164051.132" - wire width 4 $add$libresoc.v:164051$10054_Y - attribute \src "libresoc.v:164052.19-164052.132" - wire width 4 $add$libresoc.v:164052$10055_Y - attribute \src "libresoc.v:164053.19-164053.134" - wire width 4 $add$libresoc.v:164053$10056_Y - attribute \src "libresoc.v:164054.19-164054.134" - wire width 4 $add$libresoc.v:164054$10057_Y - attribute \src "libresoc.v:164055.18-164055.125" - wire width 3 $add$libresoc.v:164055$10058_Y - attribute \src "libresoc.v:164056.19-164056.134" - wire width 4 $add$libresoc.v:164056$10059_Y - attribute \src "libresoc.v:164057.19-164057.134" - wire width 4 $add$libresoc.v:164057$10060_Y - attribute \src "libresoc.v:164058.19-164058.134" - wire width 4 $add$libresoc.v:164058$10061_Y - attribute \src "libresoc.v:164059.19-164059.134" - wire width 4 $add$libresoc.v:164059$10062_Y - attribute \src "libresoc.v:164060.19-164060.134" - wire width 4 $add$libresoc.v:164060$10063_Y - attribute \src "libresoc.v:164061.19-164061.134" - wire width 4 $add$libresoc.v:164061$10064_Y - attribute \src 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\B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_6 } - connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:164051$10054_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164052$10055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_8 } - connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:164052$10055_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164053$10056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_10 } - connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:164053$10056_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164054$10057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_12 } - connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:164054$10057_Y + assign $0\logical_op__imm_data__ok$5[0:0]$9924 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9924 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164055$10058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [6] } - connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:164055$10058_Y + attribute \src "libresoc.v:169794.13-169794.48" + process $proc$libresoc.v:169794$9925 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9926 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9926 end - attribute \src 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$proc$libresoc.v:169966$9929 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9930 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9930 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164058$10061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_18 } - connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:164058$10061_Y + attribute \src "libresoc.v:170050.7-170050.40" + process $proc$libresoc.v:170050$9931 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9932 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9932 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164059$10062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_20 } - connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:164059$10062_Y + attribute \src "libresoc.v:170059.7-170059.41" + process $proc$libresoc.v:170059$9933 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9934 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9934 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164060$10063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_22 } - connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:164060$10063_Y + attribute \src "libresoc.v:170068.7-170068.39" + process $proc$libresoc.v:170068$9935 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9936 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9936 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164061$10064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_24 } - connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:164061$10064_Y + attribute \src "libresoc.v:170077.7-170077.40" + process $proc$libresoc.v:170077$9937 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9938 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9938 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164062$10065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_26 } - connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:164062$10065_Y + attribute \src "libresoc.v:170086.7-170086.36" + process $proc$libresoc.v:170086$9939 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9940 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9940 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164063$10066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_28 } - connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:164063$10066_Y + attribute \src "libresoc.v:170097.7-170097.36" + process $proc$libresoc.v:170097$9941 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9942 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9942 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164064$10067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_30 } - connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:164064$10067_Y + attribute \src "libresoc.v:170104.7-170104.43" + process $proc$libresoc.v:170104$9943 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9944 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9944 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164065$10068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_0 } - connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:164065$10068_Y + attribute \src "libresoc.v:170113.7-170113.36" + process $proc$libresoc.v:170113$9945 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9946 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9946 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164066$10069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [8] } - connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:164066$10069_Y + attribute \src "libresoc.v:170122.7-170122.36" + process $proc$libresoc.v:170122$9947 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9948 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9948 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164067$10070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_2 } - connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:164067$10070_Y + attribute \src "libresoc.v:170131.7-170131.40" + process $proc$libresoc.v:170131$9949 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9950 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9950 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164068$10071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_4 } - connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:164068$10071_Y + attribute \src "libresoc.v:170140.7-170140.37" + process $proc$libresoc.v:170140$9951 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9952 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9952 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164069$10072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_6 } - connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:164069$10072_Y + attribute \src "libresoc.v:170149.13-170149.29" + process $proc$libresoc.v:170149$9953 + assign { } { } + assign $0\muxid$1[1:0]$9954 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9954 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164070$10073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_8 } - connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:164070$10073_Y + attribute \src "libresoc.v:170162.14-170162.38" + process $proc$libresoc.v:170162$9955 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164071$10074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_10 } - connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:164071$10074_Y + attribute \src "libresoc.v:170169.7-170169.18" + process $proc$libresoc.v:170169$9956 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164072$10075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_12 } - connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:164072$10075_Y + attribute \src "libresoc.v:170765.7-170765.20" + process $proc$libresoc.v:170765$9957 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164073$10076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_14 } - connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:164073$10076_Y + attribute \src "libresoc.v:170780.13-170780.26" + process $proc$libresoc.v:170780$9958 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164074$10077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_0 } - connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:164074$10077_Y + attribute \src "libresoc.v:170787.7-170787.23" + process $proc$libresoc.v:170787$9959 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164075$10078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_2 } - connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:164075$10078_Y + attribute \src "libresoc.v:170800.7-170800.25" + process $proc$libresoc.v:170800$9960 + assign { } { } + assign $0\xer_so$20[0:0]$9961 1'0 + sync always + sync init + update \xer_so$20 $0\xer_so$20[0:0]$9961 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164076$10079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_4 } - connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:164076$10079_Y + attribute \src "libresoc.v:170805.7-170805.23" + process $proc$libresoc.v:170805$9962 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164077$10080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [10] } - connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:164077$10080_Y + attribute \src "libresoc.v:170815.3-170816.37" + process $proc$libresoc.v:170815$9792 + assign { } { } + assign $0\xer_so$20[0:0]$9793 \xer_so$20$next + sync posedge \coresync_clk + update \xer_so$20 $0\xer_so$20[0:0]$9793 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164078$10081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_6 } - connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:164078$10081_Y + attribute \src "libresoc.v:170817.3-170818.35" + process $proc$libresoc.v:170817$9794 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164079$10082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'00 \pop_5_0 } - connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:164079$10082_Y + attribute \src "libresoc.v:170819.3-170820.29" + process $proc$libresoc.v:170819$9795 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164080$10083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'00 \pop_5_2 } - connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:164080$10083_Y + attribute \src "libresoc.v:170821.3-170822.35" + process $proc$libresoc.v:170821$9796 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164081$10084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { 2'00 \pop_6_0 } - connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:164081$10084_Y + attribute \src "libresoc.v:170823.3-170824.25" + process $proc$libresoc.v:170823$9797 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164092$10103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [12] } - connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:164092$10103_Y + attribute \src "libresoc.v:170825.3-170826.31" + process $proc$libresoc.v:170825$9798 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164096$10110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [14] } - connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:164096$10110_Y + attribute \src "libresoc.v:170827.3-170828.19" + process $proc$libresoc.v:170827$9799 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164097$10111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [16] } - connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:164097$10111_Y + attribute \src "libresoc.v:170829.3-170830.25" + process $proc$libresoc.v:170829$9800 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164098$10112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [0] } - connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:164098$10112_Y + attribute \src "libresoc.v:170831.3-170832.65" + process $proc$libresoc.v:170831$9801 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9802 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9802 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164099$10113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [18] } - connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:164099$10113_Y + attribute \src "libresoc.v:170833.3-170834.61" + process $proc$libresoc.v:170833$9803 + assign { } { } + assign $0\logical_op__fn_unit$3[13:0]$9804 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9804 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164100$10114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [20] } - connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:164100$10114_Y + attribute \src "libresoc.v:170835.3-170836.75" + process $proc$libresoc.v:170835$9805 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9806 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9806 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164101$10115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [22] } - connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:164101$10115_Y + attribute \src "libresoc.v:170837.3-170838.71" + process $proc$libresoc.v:170837$9807 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9808 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9808 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164102$10116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [24] } - connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:164102$10116_Y + attribute \src "libresoc.v:170839.3-170840.59" + process $proc$libresoc.v:170839$9809 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9810 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9810 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164103$10117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [26] } - connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:164103$10117_Y + attribute \src "libresoc.v:170841.3-170842.59" + process $proc$libresoc.v:170841$9811 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9812 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9812 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164104$10118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [28] } - connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:164104$10118_Y + attribute \src "libresoc.v:170843.3-170844.59" + process $proc$libresoc.v:170843$9813 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9814 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9814 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164105$10119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [30] } - connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:164105$10119_Y + attribute \src "libresoc.v:170845.3-170846.59" + process $proc$libresoc.v:170845$9815 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9816 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9816 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164106$10120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [32] } - connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:164106$10120_Y + attribute \src "libresoc.v:170847.3-170848.67" + process $proc$libresoc.v:170847$9817 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9818 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9818 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164107$10121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [34] } - connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:164107$10121_Y + attribute \src "libresoc.v:170849.3-170850.61" + process $proc$libresoc.v:170849$9819 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9820 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9820 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164108$10122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [36] } - connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:164108$10122_Y + attribute \src "libresoc.v:170851.3-170852.71" + process $proc$libresoc.v:170851$9821 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9822 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9822 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164109$10123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [2] } - connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:164109$10123_Y + attribute \src "libresoc.v:170853.3-170854.69" + process $proc$libresoc.v:170853$9823 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9824 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9824 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164110$10124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [38] } - connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:164110$10124_Y + attribute \src "libresoc.v:170855.3-170856.67" + process $proc$libresoc.v:170855$9825 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9826 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9826 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164111$10125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [40] } - connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:164111$10125_Y + attribute \src "libresoc.v:170857.3-170858.73" + process $proc$libresoc.v:170857$9827 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9828 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9828 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164112$10126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [42] } - connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:164112$10126_Y + attribute \src "libresoc.v:170859.3-170860.65" + process $proc$libresoc.v:170859$9829 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9830 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9830 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164113$10127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [44] } - connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:164113$10127_Y + attribute \src "libresoc.v:170861.3-170862.67" + process $proc$libresoc.v:170861$9831 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9832 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9832 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164114$10128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [46] } - connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:164114$10128_Y + attribute \src "libresoc.v:170863.3-170864.65" + process $proc$libresoc.v:170863$9833 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9834 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9834 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164115$10129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [48] } - connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:164115$10129_Y + attribute \src "libresoc.v:170865.3-170866.57" + process $proc$libresoc.v:170865$9835 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9836 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9836 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164116$10130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [50] } - connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:164116$10130_Y + attribute \src "libresoc.v:170867.3-170868.33" + process $proc$libresoc.v:170867$9837 + assign { } { } + assign $0\muxid$1[1:0]$9838 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9838 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164117$10131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [52] } - connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:164117$10131_Y + attribute \src "libresoc.v:170869.3-170870.29" + process $proc$libresoc.v:170869$9839 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164118$10132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [54] } - connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:164118$10132_Y + attribute \src "libresoc.v:170985.3-171003.6" + process $proc$libresoc.v:170985$9840 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9841 $1\o$next[63:0]$9843 + assign { } { } + assign $0\o_ok$next[0:0]$9842 $2\o_ok$next[0:0]$9845 + attribute \src "libresoc.v:170986.5-170986.29" + switch \initial + attribute \src "libresoc.v:170986.9-170986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9844 $1\o$next[63:0]$9843 } { \o_ok$96 \o$95 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9844 $1\o$next[63:0]$9843 } { \o_ok$96 \o$95 } + case + assign $1\o$next[63:0]$9843 \o + assign $1\o_ok$next[0:0]$9844 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9845 1'0 + case + assign $2\o_ok$next[0:0]$9845 $1\o_ok$next[0:0]$9844 + end + sync always + update \o$next $0\o$next[63:0]$9841 + update \o_ok$next $0\o_ok$next[0:0]$9842 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164119$10133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [56] } - connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:164119$10133_Y + attribute \src "libresoc.v:171004.3-171022.6" + process $proc$libresoc.v:171004$9846 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9847 $1\cr_a$next[3:0]$9849 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9848 $2\cr_a_ok$next[0:0]$9851 + attribute \src "libresoc.v:171005.5-171005.29" + switch \initial + attribute \src "libresoc.v:171005.9-171005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9850 $1\cr_a$next[3:0]$9849 } { \cr_a_ok$98 \cr_a$97 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9850 $1\cr_a$next[3:0]$9849 } { \cr_a_ok$98 \cr_a$97 } + case + assign $1\cr_a$next[3:0]$9849 \cr_a + assign $1\cr_a_ok$next[0:0]$9850 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9851 1'0 + case + assign $2\cr_a_ok$next[0:0]$9851 $1\cr_a_ok$next[0:0]$9850 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9847 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9848 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164120$10134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [4] } - connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:164120$10134_Y + attribute \src "libresoc.v:171023.3-171041.6" + process $proc$libresoc.v:171023$9852 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9853 $1\xer_ov$next[1:0]$9855 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9854 $2\xer_ov_ok$next[0:0]$9857 + attribute \src "libresoc.v:171024.5-171024.29" + switch \initial + attribute \src "libresoc.v:171024.9-171024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9856 $1\xer_ov$next[1:0]$9855 } { \xer_ov_ok$100 \xer_ov$99 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9856 $1\xer_ov$next[1:0]$9855 } { \xer_ov_ok$100 \xer_ov$99 } + case + assign $1\xer_ov$next[1:0]$9855 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9856 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9857 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9857 $1\xer_ov_ok$next[0:0]$9856 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9853 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9854 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164121$10135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [58] } - connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:164121$10135_Y + attribute \src "libresoc.v:171042.3-171060.6" + process $proc$libresoc.v:171042$9858 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$20$next[0:0]$9860 $1\xer_so$20$next[0:0]$9862 + assign $0\xer_so_ok$next[0:0]$9859 $2\xer_so_ok$next[0:0]$9863 + attribute \src "libresoc.v:171043.5-171043.29" + switch \initial + attribute \src "libresoc.v:171043.9-171043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9861 $1\xer_so$20$next[0:0]$9862 } { \xer_so_ok$102 \xer_so$101 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9861 $1\xer_so$20$next[0:0]$9862 } { \xer_so_ok$102 \xer_so$101 } + case + assign $1\xer_so_ok$next[0:0]$9861 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9862 \xer_so$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9863 1'0 + case + assign $2\xer_so_ok$next[0:0]$9863 $1\xer_so_ok$next[0:0]$9861 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9859 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9860 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164122$10136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [60] } - connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:164122$10136_Y + attribute \src "libresoc.v:171061.3-171078.6" + process $proc$libresoc.v:171061$9864 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9865 $2\r_busy$next[0:0]$9867 + attribute \src "libresoc.v:171062.5-171062.29" + switch \initial + attribute \src "libresoc.v:171062.9-171062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9866 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9866 1'0 + case + assign $1\r_busy$next[0:0]$9866 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9867 1'0 + case + assign $2\r_busy$next[0:0]$9867 $1\r_busy$next[0:0]$9866 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9865 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164123$10137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [62] } - connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:164123$10137_Y + attribute \src "libresoc.v:171079.3-171091.6" + process $proc$libresoc.v:171079$9868 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9869 $1\muxid$1$next[1:0]$9870 + attribute \src "libresoc.v:171080.5-171080.29" + switch \initial + attribute \src "libresoc.v:171080.9-171080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9870 \muxid$76 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9870 \muxid$76 + case + assign $1\muxid$1$next[1:0]$9870 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9869 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164124$10138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_0 } - connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:164124$10138_Y + attribute \src "libresoc.v:171092.3-171133.6" + process $proc$libresoc.v:171092$9871 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$9872 $1\logical_op__data_len$18$next[3:0]$9890 + assign $0\logical_op__fn_unit$3$next[13:0]$9873 $1\logical_op__fn_unit$3$next[13:0]$9891 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$9876 $1\logical_op__input_carry$12$next[1:0]$9894 + assign $0\logical_op__insn$19$next[31:0]$9877 $1\logical_op__insn$19$next[31:0]$9895 + assign $0\logical_op__insn_type$2$next[6:0]$9878 $1\logical_op__insn_type$2$next[6:0]$9896 + assign $0\logical_op__invert_in$10$next[0:0]$9879 $1\logical_op__invert_in$10$next[0:0]$9897 + assign $0\logical_op__invert_out$13$next[0:0]$9880 $1\logical_op__invert_out$13$next[0:0]$9898 + assign $0\logical_op__is_32bit$16$next[0:0]$9881 $1\logical_op__is_32bit$16$next[0:0]$9899 + assign $0\logical_op__is_signed$17$next[0:0]$9882 $1\logical_op__is_signed$17$next[0:0]$9900 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$9885 $1\logical_op__output_carry$15$next[0:0]$9903 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$9888 $1\logical_op__write_cr0$14$next[0:0]$9906 + assign $0\logical_op__zero_a$11$next[0:0]$9889 $1\logical_op__zero_a$11$next[0:0]$9907 + assign $0\logical_op__imm_data__data$4$next[63:0]$9874 $2\logical_op__imm_data__data$4$next[63:0]$9908 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9875 $2\logical_op__imm_data__ok$5$next[0:0]$9909 + assign $0\logical_op__oe__oe$8$next[0:0]$9883 $2\logical_op__oe__oe$8$next[0:0]$9910 + assign $0\logical_op__oe__ok$9$next[0:0]$9884 $2\logical_op__oe__ok$9$next[0:0]$9911 + assign $0\logical_op__rc__ok$7$next[0:0]$9886 $2\logical_op__rc__ok$7$next[0:0]$9912 + assign $0\logical_op__rc__rc$6$next[0:0]$9887 $2\logical_op__rc__rc$6$next[0:0]$9913 + attribute \src "libresoc.v:171093.5-171093.29" + switch \initial + attribute \src "libresoc.v:171093.9-171093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9895 $1\logical_op__data_len$18$next[3:0]$9890 $1\logical_op__is_signed$17$next[0:0]$9900 $1\logical_op__is_32bit$16$next[0:0]$9899 $1\logical_op__output_carry$15$next[0:0]$9903 $1\logical_op__write_cr0$14$next[0:0]$9906 $1\logical_op__invert_out$13$next[0:0]$9898 $1\logical_op__input_carry$12$next[1:0]$9894 $1\logical_op__zero_a$11$next[0:0]$9907 $1\logical_op__invert_in$10$next[0:0]$9897 $1\logical_op__oe__ok$9$next[0:0]$9902 $1\logical_op__oe__oe$8$next[0:0]$9901 $1\logical_op__rc__ok$7$next[0:0]$9904 $1\logical_op__rc__rc$6$next[0:0]$9905 $1\logical_op__imm_data__ok$5$next[0:0]$9893 $1\logical_op__imm_data__data$4$next[63:0]$9892 $1\logical_op__fn_unit$3$next[13:0]$9891 $1\logical_op__insn_type$2$next[6:0]$9896 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9895 $1\logical_op__data_len$18$next[3:0]$9890 $1\logical_op__is_signed$17$next[0:0]$9900 $1\logical_op__is_32bit$16$next[0:0]$9899 $1\logical_op__output_carry$15$next[0:0]$9903 $1\logical_op__write_cr0$14$next[0:0]$9906 $1\logical_op__invert_out$13$next[0:0]$9898 $1\logical_op__input_carry$12$next[1:0]$9894 $1\logical_op__zero_a$11$next[0:0]$9907 $1\logical_op__invert_in$10$next[0:0]$9897 $1\logical_op__oe__ok$9$next[0:0]$9902 $1\logical_op__oe__oe$8$next[0:0]$9901 $1\logical_op__rc__ok$7$next[0:0]$9904 $1\logical_op__rc__rc$6$next[0:0]$9905 $1\logical_op__imm_data__ok$5$next[0:0]$9893 $1\logical_op__imm_data__data$4$next[63:0]$9892 $1\logical_op__fn_unit$3$next[13:0]$9891 $1\logical_op__insn_type$2$next[6:0]$9896 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + case + assign $1\logical_op__data_len$18$next[3:0]$9890 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$9891 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9892 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9893 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9894 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9895 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9896 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9897 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9898 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9899 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9900 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9901 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9902 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9903 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9904 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9905 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9906 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9907 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$9908 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9909 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9913 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9912 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9910 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9911 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$9908 $1\logical_op__imm_data__data$4$next[63:0]$9892 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9909 $1\logical_op__imm_data__ok$5$next[0:0]$9893 + assign $2\logical_op__oe__oe$8$next[0:0]$9910 $1\logical_op__oe__oe$8$next[0:0]$9901 + assign $2\logical_op__oe__ok$9$next[0:0]$9911 $1\logical_op__oe__ok$9$next[0:0]$9902 + assign $2\logical_op__rc__ok$7$next[0:0]$9912 $1\logical_op__rc__ok$7$next[0:0]$9904 + assign $2\logical_op__rc__rc$6$next[0:0]$9913 $1\logical_op__rc__rc$6$next[0:0]$9905 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9872 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9873 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9874 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9875 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9876 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9877 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9878 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9879 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9880 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9881 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9882 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9883 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9884 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9885 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9886 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9887 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9888 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9889 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:164082$10085 + connect \$74 $and$libresoc.v:170814$9791_Y + connect \cr_a$68 4'0000 + connect \cr_a_ok$69 1'0 + connect \xer_so_ok$72 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } + connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } + connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } + connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } + connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + connect \muxid$76 \output_muxid$41 + connect \p_valid_i_p_ready_o \$74 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$73 \p_valid_i + connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } + connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + connect { \cr_a_ok$67 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + connect \output_muxid \output_stage_muxid$21 + connect \output_stage_remainder \remainder + connect \output_stage_quotient_root \quotient_root + connect \output_stage_div_by_zero \div_by_zero + connect \output_stage_dive_abs_ov64 \dive_abs_ov64 + connect \output_stage_dive_abs_ov32 \dive_abs_ov32 + connect \output_stage_dividend_neg \dividend_neg + connect \output_stage_divisor_neg \divisor_neg + connect \output_stage_xer_so \xer_so + connect \rb$66 \rb + connect \ra$65 \ra + connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_stage_muxid \muxid +end +attribute \src "libresoc.v:171170.1-172157.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" +attribute \generator "nMigen" +module \pipe_middle_0 + attribute \src "libresoc.v:172082.3-172096.6" + wire $0\div_by_zero$54$next[0:0]$10142 + attribute \src "libresoc.v:171193.7-171193.30" + wire $0\div_by_zero$54[0:0]$10159 + attribute \src "libresoc.v:171756.3-171757.47" + wire $0\div_by_zero$54[0:0]$9977 + attribute \src "libresoc.v:171878.3-171889.6" + wire width 64 $0\div_state_next_divisor[63:0] + attribute \src "libresoc.v:171866.3-171877.6" + wire width 128 $0\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:171854.3-171865.6" + wire width 7 $0\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:172052.3-172066.6" + wire $0\dive_abs_ov32$52$next[0:0]$10134 + attribute \src "libresoc.v:171217.7-171217.32" + wire $0\dive_abs_ov32$52[0:0]$10161 + attribute \src "libresoc.v:171760.3-171761.51" + wire $0\dive_abs_ov32$52[0:0]$9981 + attribute \src "libresoc.v:172067.3-172081.6" + wire $0\dive_abs_ov64$53$next[0:0]$10138 + attribute \src "libresoc.v:171225.7-171225.32" + wire $0\dive_abs_ov64$53[0:0]$10163 + attribute \src "libresoc.v:171758.3-171759.51" + wire $0\dive_abs_ov64$53[0:0]$9979 + attribute \src "libresoc.v:172097.3-172111.6" + wire width 128 $0\dividend$68$next[127:0]$10146 + attribute \src "libresoc.v:171231.15-171231.68" + wire width 128 $0\dividend$68[127:0]$10165 + attribute \src "libresoc.v:171754.3-171755.41" + wire width 128 $0\dividend$68[127:0]$9975 + attribute \src "libresoc.v:172037.3-172051.6" + wire $0\dividend_neg$51$next[0:0]$10130 + attribute \src "libresoc.v:171239.7-171239.31" + wire $0\dividend_neg$51[0:0]$10167 + attribute \src "libresoc.v:171762.3-171763.49" + wire $0\dividend_neg$51[0:0]$9983 + attribute \src "libresoc.v:172022.3-172036.6" + wire $0\divisor_neg$50$next[0:0]$10126 + attribute \src "libresoc.v:171247.7-171247.30" + wire $0\divisor_neg$50[0:0]$10169 + attribute \src "libresoc.v:171764.3-171765.47" + wire $0\divisor_neg$50[0:0]$9985 + attribute \src "libresoc.v:172112.3-172126.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10150 + attribute \src "libresoc.v:171253.14-171253.58" + wire width 64 $0\divisor_radicand$65[63:0]$10171 + attribute \src "libresoc.v:171752.3-171753.57" + wire width 64 $0\divisor_radicand$65[63:0]$9973 + attribute \src "libresoc.v:171890.3-171917.6" + wire $0\empty$next[0:0]$10043 + attribute \src "libresoc.v:171810.3-171811.27" + wire $0\empty[0:0] + attribute \src "libresoc.v:171171.7-171171.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171933.3-171976.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10053 + attribute \src "libresoc.v:171804.3-171805.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10025 + attribute \src "libresoc.v:171265.13-171265.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10174 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10054 + attribute \src "libresoc.v:171318.14-171318.49" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10176 + attribute \src "libresoc.v:171774.3-171775.63" + wire width 14 $0\logical_op__fn_unit$30[13:0]$9995 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10055 + attribute \src "libresoc.v:171324.14-171324.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10178 + attribute \src "libresoc.v:171776.3-171777.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9997 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10056 + attribute \src "libresoc.v:171332.7-171332.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10180 + attribute \src "libresoc.v:171778.3-171779.73" + wire $0\logical_op__imm_data__ok$32[0:0]$9999 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10057 + attribute \src "libresoc.v:171792.3-171793.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$10013 + attribute \src "libresoc.v:171354.13-171354.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10182 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10058 + attribute \src "libresoc.v:171806.3-171807.57" + wire width 32 $0\logical_op__insn$46[31:0]$10027 + attribute \src "libresoc.v:171362.14-171362.43" + wire width 32 $0\logical_op__insn$46[31:0]$10184 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10059 + attribute \src "libresoc.v:171595.13-171595.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10186 + attribute \src "libresoc.v:171772.3-171773.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$9993 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__invert_in$37$next[0:0]$10060 + attribute \src "libresoc.v:171788.3-171789.67" + wire $0\logical_op__invert_in$37[0:0]$10009 + attribute \src "libresoc.v:171603.7-171603.40" + wire $0\logical_op__invert_in$37[0:0]$10188 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__invert_out$40$next[0:0]$10061 + attribute \src "libresoc.v:171794.3-171795.69" + wire $0\logical_op__invert_out$40[0:0]$10015 + attribute \src "libresoc.v:171611.7-171611.41" + wire $0\logical_op__invert_out$40[0:0]$10190 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10062 + attribute \src "libresoc.v:171800.3-171801.65" + wire $0\logical_op__is_32bit$43[0:0]$10021 + attribute \src "libresoc.v:171619.7-171619.39" + wire $0\logical_op__is_32bit$43[0:0]$10192 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__is_signed$44$next[0:0]$10063 + attribute \src "libresoc.v:171802.3-171803.67" + wire $0\logical_op__is_signed$44[0:0]$10023 + attribute \src "libresoc.v:171627.7-171627.40" + wire $0\logical_op__is_signed$44[0:0]$10194 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10064 + attribute \src "libresoc.v:171784.3-171785.61" + wire $0\logical_op__oe__oe$35[0:0]$10005 + attribute \src "libresoc.v:171633.7-171633.37" + wire $0\logical_op__oe__oe$35[0:0]$10196 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10065 + attribute \src "libresoc.v:171786.3-171787.61" + wire $0\logical_op__oe__ok$36[0:0]$10007 + attribute \src "libresoc.v:171641.7-171641.37" + wire $0\logical_op__oe__ok$36[0:0]$10198 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__output_carry$42$next[0:0]$10066 + attribute \src "libresoc.v:171798.3-171799.73" + wire $0\logical_op__output_carry$42[0:0]$10019 + attribute \src "libresoc.v:171651.7-171651.43" + wire $0\logical_op__output_carry$42[0:0]$10200 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10067 + attribute \src "libresoc.v:171782.3-171783.61" + wire $0\logical_op__rc__ok$34[0:0]$10003 + attribute \src "libresoc.v:171657.7-171657.37" + wire $0\logical_op__rc__ok$34[0:0]$10202 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10068 + attribute \src "libresoc.v:171780.3-171781.61" + wire $0\logical_op__rc__rc$33[0:0]$10001 + attribute \src "libresoc.v:171665.7-171665.37" + wire $0\logical_op__rc__rc$33[0:0]$10204 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10069 + attribute \src "libresoc.v:171796.3-171797.67" + wire $0\logical_op__write_cr0$41[0:0]$10017 + attribute \src "libresoc.v:171675.7-171675.40" + wire $0\logical_op__write_cr0$41[0:0]$10206 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__zero_a$38$next[0:0]$10070 + attribute \src "libresoc.v:171790.3-171791.61" + wire $0\logical_op__zero_a$38[0:0]$10011 + attribute \src "libresoc.v:171683.7-171683.37" + wire $0\logical_op__zero_a$38[0:0]$10208 + attribute \src "libresoc.v:171918.3-171932.6" + wire width 2 $0\muxid$28$next[1:0]$10049 + attribute \src "libresoc.v:171808.3-171809.35" + wire width 2 $0\muxid$28[1:0]$10029 + attribute \src "libresoc.v:171691.13-171691.30" + wire width 2 $0\muxid$28[1:0]$10210 + attribute \src "libresoc.v:172127.3-172141.6" + wire width 2 $0\operation$69$next[1:0]$10154 + attribute \src "libresoc.v:171701.13-171701.34" + wire width 2 $0\operation$69[1:0]$10212 + attribute \src "libresoc.v:171750.3-171751.43" + wire width 2 $0\operation$69[1:0]$9971 + attribute \src "libresoc.v:171977.3-171991.6" + wire width 64 $0\ra$47$next[63:0]$10114 + attribute \src "libresoc.v:171715.14-171715.44" + wire width 64 $0\ra$47[63:0]$10214 + attribute \src "libresoc.v:171770.3-171771.29" + wire width 64 $0\ra$47[63:0]$9991 + attribute \src "libresoc.v:171992.3-172006.6" + wire width 64 $0\rb$48$next[63:0]$10118 + attribute \src "libresoc.v:171723.14-171723.44" + wire width 64 $0\rb$48[63:0]$10216 + attribute \src "libresoc.v:171768.3-171769.29" + wire width 64 $0\rb$48[63:0]$9989 + attribute \src "libresoc.v:171845.3-171853.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10037 + attribute \src "libresoc.v:171812.3-171813.75" + wire width 128 $0\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:171836.3-171844.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10034 + attribute \src "libresoc.v:171814.3-171815.65" + wire width 7 $0\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:172007.3-172021.6" + wire $0\xer_so$49$next[0:0]$10122 + attribute \src "libresoc.v:171741.7-171741.25" + wire $0\xer_so$49[0:0]$10220 + attribute \src "libresoc.v:171766.3-171767.37" + wire $0\xer_so$49[0:0]$9987 + attribute \src "libresoc.v:172082.3-172096.6" + wire $1\div_by_zero$54$next[0:0]$10143 + attribute \src "libresoc.v:171878.3-171889.6" + wire width 64 $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:171866.3-171877.6" + wire width 128 $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:171854.3-171865.6" + wire width 7 $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:172052.3-172066.6" + wire $1\dive_abs_ov32$52$next[0:0]$10135 + attribute \src "libresoc.v:172067.3-172081.6" + wire $1\dive_abs_ov64$53$next[0:0]$10139 + attribute \src "libresoc.v:172097.3-172111.6" + wire width 128 $1\dividend$68$next[127:0]$10147 + attribute \src "libresoc.v:172037.3-172051.6" + wire $1\dividend_neg$51$next[0:0]$10131 + attribute \src "libresoc.v:172022.3-172036.6" + wire $1\divisor_neg$50$next[0:0]$10127 + attribute \src "libresoc.v:172112.3-172126.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10151 + attribute \src "libresoc.v:171890.3-171917.6" + wire $1\empty$next[0:0]$10044 + attribute \src "libresoc.v:171257.7-171257.19" + wire $1\empty[0:0] + attribute \src "libresoc.v:171933.3-171976.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10071 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10072 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10073 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10074 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10075 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10076 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10077 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__invert_in$37$next[0:0]$10078 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__invert_out$40$next[0:0]$10079 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10080 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__is_signed$44$next[0:0]$10081 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10082 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10083 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__output_carry$42$next[0:0]$10084 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10085 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10086 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10087 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__zero_a$38$next[0:0]$10088 + attribute \src "libresoc.v:171918.3-171932.6" + wire width 2 $1\muxid$28$next[1:0]$10050 + attribute \src "libresoc.v:172127.3-172141.6" + wire width 2 $1\operation$69$next[1:0]$10155 + attribute \src "libresoc.v:171977.3-171991.6" + wire width 64 $1\ra$47$next[63:0]$10115 + attribute \src "libresoc.v:171992.3-172006.6" + wire width 64 $1\rb$48$next[63:0]$10119 + attribute \src "libresoc.v:171845.3-171853.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10038 + attribute \src "libresoc.v:171729.15-171729.84" + wire width 128 $1\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:171836.3-171844.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10035 + attribute \src "libresoc.v:171733.13-171733.45" + wire width 7 $1\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:172007.3-172021.6" + wire $1\xer_so$49$next[0:0]$10123 + attribute \src "libresoc.v:172082.3-172096.6" + wire $2\div_by_zero$54$next[0:0]$10144 + attribute \src "libresoc.v:172052.3-172066.6" + wire $2\dive_abs_ov32$52$next[0:0]$10136 + attribute \src "libresoc.v:172067.3-172081.6" + wire $2\dive_abs_ov64$53$next[0:0]$10140 + attribute \src "libresoc.v:172097.3-172111.6" + wire width 128 $2\dividend$68$next[127:0]$10148 + attribute \src "libresoc.v:172037.3-172051.6" + wire $2\dividend_neg$51$next[0:0]$10132 + attribute \src "libresoc.v:172022.3-172036.6" + wire $2\divisor_neg$50$next[0:0]$10128 + attribute \src "libresoc.v:172112.3-172126.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10152 + attribute \src "libresoc.v:171890.3-171917.6" + wire $2\empty$next[0:0]$10045 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10089 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10090 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10091 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10092 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10093 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10094 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10095 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__invert_in$37$next[0:0]$10096 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__invert_out$40$next[0:0]$10097 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10098 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__is_signed$44$next[0:0]$10099 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10100 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10101 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__output_carry$42$next[0:0]$10102 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10103 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10104 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10105 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__zero_a$38$next[0:0]$10106 + attribute \src "libresoc.v:171918.3-171932.6" + wire width 2 $2\muxid$28$next[1:0]$10051 + attribute \src "libresoc.v:172127.3-172141.6" + wire width 2 $2\operation$69$next[1:0]$10156 + attribute \src "libresoc.v:171977.3-171991.6" + wire width 64 $2\ra$47$next[63:0]$10116 + attribute \src "libresoc.v:171992.3-172006.6" + wire width 64 $2\rb$48$next[63:0]$10120 + attribute \src "libresoc.v:172007.3-172021.6" + wire $2\xer_so$49$next[0:0]$10124 + attribute \src "libresoc.v:171890.3-171917.6" + wire $3\empty$next[0:0]$10046 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10107 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10108 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10109 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10110 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10111 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10112 + attribute \src "libresoc.v:171890.3-171917.6" + wire $4\empty$next[0:0]$10047 + attribute \src "libresoc.v:171748.18-171748.98" + wire $and$libresoc.v:171748$9968_Y + attribute \src "libresoc.v:171749.18-171749.107" + wire $and$libresoc.v:171749$9969_Y + attribute \src "libresoc.v:171745.18-171745.92" + wire width 192 $extend$libresoc.v:171745$9964_Y + attribute \src "libresoc.v:171747.18-171747.119" + wire $ge$libresoc.v:171747$9967_Y + attribute \src "libresoc.v:171746.18-171746.93" + wire $not$libresoc.v:171746$9966_Y + attribute \src "libresoc.v:171745.18-171745.92" + wire width 192 $pos$libresoc.v:171745$9965_Y + attribute \src "libresoc.v:171744.18-171744.138" + wire width 191 $sshl$libresoc.v:171744$9963_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 192 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 191 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 65 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 62 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 \div_state_init_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_init_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 \div_state_next_divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 60 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 61 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 input 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 59 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 58 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 input 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty$next + attribute \src "libresoc.v:171171.7-171171.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$30$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 35 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 34 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 input 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 output 63 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 output 64 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $and $and$libresoc.v:171748$9968 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 1'1 - connect \Y $eq$libresoc.v:164082$10085_Y + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:171748$9968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:164083$10086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + cell $and $and$libresoc.v:171749$9969 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 3'100 - connect \Y $eq$libresoc.v:164083$10086_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164084$10087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_0 - connect \Y $extend$libresoc.v:164084$10087_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164085$10089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_1 - connect \Y $extend$libresoc.v:164085$10089_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164086$10091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_2 - connect \Y $extend$libresoc.v:164086$10091_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164087$10093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_3 - connect \Y $extend$libresoc.v:164087$10093_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164088$10095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_4 - connect \Y $extend$libresoc.v:164088$10095_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164089$10097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_5 - connect \Y $extend$libresoc.v:164089$10097_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164090$10099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_6 - connect \Y $extend$libresoc.v:164090$10099_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164091$10101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_7 - connect \Y $extend$libresoc.v:164091$10101_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164093$10104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_0 - connect \Y $extend$libresoc.v:164093$10104_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:171749$9969_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164094$10106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $extend$libresoc.v:171745$9964 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_1 - connect \Y $extend$libresoc.v:164094$10106_Y + parameter \A_WIDTH 191 + parameter \Y_WIDTH 192 + connect \A \$56 + connect \Y $extend$libresoc.v:171745$9964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164095$10108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:171747$9967 parameter \A_SIGNED 0 parameter \A_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \pop_7_0 - connect \Y $extend$libresoc.v:164095$10108_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \saved_state_q_bits_known + connect \B 6'111111 + connect \Y $ge$libresoc.v:171747$9967_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164084$10088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $not $not$libresoc.v:171746$9966 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164084$10087_Y - connect \Y $pos$libresoc.v:164084$10088_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \empty + connect \Y $not$libresoc.v:171746$9966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164085$10090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $pos$libresoc.v:171745$9965 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164085$10089_Y - connect \Y $pos$libresoc.v:164085$10090_Y + parameter \A_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $extend$libresoc.v:171745$9964_Y + connect \Y $pos$libresoc.v:171745$9965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164086$10092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $sshl $sshl$libresoc.v:171744$9963 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164086$10091_Y - connect \Y $pos$libresoc.v:164086$10092_Y + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \div_state_next_o_dividend_quotient [127:64] + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:171744$9963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164087$10094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164087$10093_Y - connect \Y $pos$libresoc.v:164087$10094_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:171816.18-171820.4" + cell \div_state_init \div_state_init + connect \dividend \div_state_init_dividend + connect \o_dividend_quotient \div_state_init_o_dividend_quotient + connect \o_q_bits_known \div_state_init_o_q_bits_known end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164088$10096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164088$10095_Y - connect \Y $pos$libresoc.v:164088$10096_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:171821.18-171827.4" + cell \div_state_next \div_state_next + connect \divisor \div_state_next_divisor + connect \i_dividend_quotient \div_state_next_i_dividend_quotient + connect \i_q_bits_known \div_state_next_i_q_bits_known + connect \o_dividend_quotient \div_state_next_o_dividend_quotient + connect \o_q_bits_known \div_state_next_o_q_bits_known end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164089$10098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164089$10097_Y - connect \Y $pos$libresoc.v:164089$10098_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:171828.10-171831.4" + cell \n$80 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164090$10100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164090$10099_Y - connect \Y $pos$libresoc.v:164090$10100_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:171832.10-171835.4" + cell \p$79 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164091$10102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164091$10101_Y - connect \Y $pos$libresoc.v:164091$10102_Y + attribute \src "libresoc.v:171171.7-171171.20" + process $proc$libresoc.v:171171$10157 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164093$10105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:164093$10104_Y - connect \Y $pos$libresoc.v:164093$10105_Y + attribute \src "libresoc.v:171193.7-171193.30" + process $proc$libresoc.v:171193$10158 + assign { } { } + assign $0\div_by_zero$54[0:0]$10159 1'0 + sync always + sync init + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10159 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164094$10107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:164094$10106_Y - connect \Y $pos$libresoc.v:164094$10107_Y + attribute \src "libresoc.v:171217.7-171217.32" + process $proc$libresoc.v:171217$10160 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$10161 1'0 + sync always + sync init + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10161 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164095$10109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:164095$10108_Y - connect \Y $pos$libresoc.v:164095$10109_Y + attribute \src "libresoc.v:171225.7-171225.32" + process $proc$libresoc.v:171225$10162 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$10163 1'0 + sync always + sync init + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10163 end - attribute \src "libresoc.v:163637.7-163637.20" - process $proc$libresoc.v:163637$10140 + attribute \src "libresoc.v:171231.15-171231.68" + process $proc$libresoc.v:171231$10164 assign { } { } - assign $0\initial[0:0] 1'0 + assign $0\dividend$68[127:0]$10165 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always - update \initial $0\initial[0:0] sync init + update \dividend$68 $0\dividend$68[127:0]$10165 end - attribute \src "libresoc.v:164125.3-164151.6" - process $proc$libresoc.v:164125$10139 + attribute \src "libresoc.v:171239.7-171239.31" + process $proc$libresoc.v:171239$10166 assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:164126.5-164126.29" - switch \initial - attribute \src "libresoc.v:164126.9-164126.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - switch { \$192 \$190 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\o[63:0] [7:0] \$194 - assign $1\o[63:0] [15:8] \$196 - assign $1\o[63:0] [23:16] \$198 - assign $1\o[63:0] [31:24] \$200 - assign $1\o[63:0] [39:32] \$202 - assign $1\o[63:0] [47:40] \$204 - assign $1\o[63:0] [55:48] \$206 - assign $1\o[63:0] [63:56] \$208 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\o[63:0] [31:0] \$210 - assign $1\o[63:0] [63:32] \$212 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o[63:0] \$214 - end + assign $0\dividend_neg$51[0:0]$10167 1'0 sync always - update \o $0\o[63:0] + sync init + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10167 end - connect \$101 $add$libresoc.v:164049$10052_Y - connect \$104 $add$libresoc.v:164050$10053_Y - connect \$107 $add$libresoc.v:164051$10054_Y - connect \$110 $add$libresoc.v:164052$10055_Y - connect \$113 $add$libresoc.v:164053$10056_Y - connect \$116 $add$libresoc.v:164054$10057_Y - connect \$11 $add$libresoc.v:164055$10058_Y - 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[3:0] - connect \pop_3_15 \$143 [2:0] - connect \pop_3_14 \$140 [2:0] - connect \pop_3_13 \$137 [2:0] - connect \pop_3_12 \$134 [2:0] - connect \pop_3_11 \$131 [2:0] - connect \pop_3_10 \$128 [2:0] - connect \pop_3_9 \$125 [2:0] - connect \pop_3_8 \$122 [2:0] - connect \pop_3_7 \$119 [2:0] - connect \pop_3_6 \$116 [2:0] - connect \pop_3_5 \$113 [2:0] - connect \pop_3_4 \$110 [2:0] - connect \pop_3_3 \$107 [2:0] - connect \pop_3_2 \$104 [2:0] - connect \pop_3_1 \$101 [2:0] - connect \pop_3_0 \$98 [2:0] - connect \pop_2_31 \$95 [1:0] - connect \pop_2_30 \$92 [1:0] - connect \pop_2_29 \$89 [1:0] - connect \pop_2_28 \$86 [1:0] - connect \pop_2_27 \$83 [1:0] - connect \pop_2_26 \$80 [1:0] - connect \pop_2_25 \$77 [1:0] - connect \pop_2_24 \$74 [1:0] - connect \pop_2_23 \$71 [1:0] - connect \pop_2_22 \$68 [1:0] - connect \pop_2_21 \$65 [1:0] - connect \pop_2_20 \$62 [1:0] - connect \pop_2_19 \$59 [1:0] - connect \pop_2_18 \$56 [1:0] - connect \pop_2_17 \$53 [1:0] - connect \pop_2_16 \$50 [1:0] - connect \pop_2_15 \$47 [1:0] - connect \pop_2_14 \$44 [1:0] - connect \pop_2_13 \$41 [1:0] - connect \pop_2_12 \$38 [1:0] - connect \pop_2_11 \$35 [1:0] - connect \pop_2_10 \$32 [1:0] - connect \pop_2_9 \$29 [1:0] - connect \pop_2_8 \$26 [1:0] - connect \pop_2_7 \$23 [1:0] - connect \pop_2_6 \$20 [1:0] - connect \pop_2_5 \$17 [1:0] - connect \pop_2_4 \$14 [1:0] - connect \pop_2_3 \$11 [1:0] - connect \pop_2_2 \$8 [1:0] - connect \pop_2_1 \$5 [1:0] - connect \pop_2_0 \$2 [1:0] -end -attribute \src "libresoc.v:164282.1-164366.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick - attribute \src "libresoc.v:164339.17-164339.91" - wire $not$libresoc.v:164339$10141_Y - attribute \src "libresoc.v:164341.18-164341.93" - wire $not$libresoc.v:164341$10143_Y - attribute \src "libresoc.v:164343.18-164343.93" - wire $not$libresoc.v:164343$10145_Y - attribute \src "libresoc.v:164344.17-164344.138" - wire width 8 $not$libresoc.v:164344$10146_Y - attribute \src "libresoc.v:164346.18-164346.93" - wire $not$libresoc.v:164346$10148_Y - attribute \src "libresoc.v:164348.18-164348.93" - wire $not$libresoc.v:164348$10150_Y - attribute \src "libresoc.v:164350.18-164350.93" - wire $not$libresoc.v:164350$10152_Y - attribute \src "libresoc.v:164353.17-164353.91" - wire $not$libresoc.v:164353$10155_Y - attribute \src "libresoc.v:164340.18-164340.116" - wire $reduce_or$libresoc.v:164340$10142_Y - attribute \src "libresoc.v:164342.18-164342.122" - wire $reduce_or$libresoc.v:164342$10144_Y - attribute \src "libresoc.v:164345.18-164345.128" - wire $reduce_or$libresoc.v:164345$10147_Y - attribute \src "libresoc.v:164347.18-164347.134" - wire $reduce_or$libresoc.v:164347$10149_Y - attribute \src "libresoc.v:164349.18-164349.140" - wire $reduce_or$libresoc.v:164349$10151_Y - attribute \src "libresoc.v:164351.18-164351.90" - wire $reduce_or$libresoc.v:164351$10153_Y - attribute \src "libresoc.v:164352.17-164352.103" - wire $reduce_or$libresoc.v:164352$10154_Y - attribute \src "libresoc.v:164354.17-164354.109" - wire $reduce_or$libresoc.v:164354$10156_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164339$10141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164339$10141_Y + attribute \src "libresoc.v:171247.7-171247.30" + process $proc$libresoc.v:171247$10168 + assign { } { } + assign $0\divisor_neg$50[0:0]$10169 1'0 + sync always + sync init + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10169 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164341$10143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164341$10143_Y + attribute \src "libresoc.v:171253.14-171253.58" + process $proc$libresoc.v:171253$10170 + assign { } { } + assign $0\divisor_radicand$65[63:0]$10171 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10171 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164343$10145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164343$10145_Y + attribute \src "libresoc.v:171257.7-171257.19" + process $proc$libresoc.v:171257$10172 + assign { } { } + assign $1\empty[0:0] 1'1 + sync always + sync init + update \empty $1\empty[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164344$10146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164344$10146_Y + attribute \src "libresoc.v:171265.13-171265.45" + process $proc$libresoc.v:171265$10173 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$10174 4'0000 + sync always + sync init + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10174 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164346$10148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164346$10148_Y + attribute \src "libresoc.v:171318.14-171318.49" + process $proc$libresoc.v:171318$10175 + assign { } { } + assign $0\logical_op__fn_unit$30[13:0]$10176 14'00000000000000 + sync always + sync init + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10176 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164348$10150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164348$10150_Y + attribute \src "libresoc.v:171324.14-171324.68" + process $proc$libresoc.v:171324$10177 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$10178 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10178 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164350$10152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164350$10152_Y + attribute \src "libresoc.v:171332.7-171332.43" + process $proc$libresoc.v:171332$10179 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$10180 1'0 + sync always + sync init + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10180 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164353$10155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164353$10155_Y + attribute \src "libresoc.v:171354.13-171354.48" + process $proc$libresoc.v:171354$10181 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$10182 2'00 + sync always + sync init + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10182 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164340$10142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164340$10142_Y + attribute \src "libresoc.v:171362.14-171362.43" + process $proc$libresoc.v:171362$10183 + assign { } { } + assign $0\logical_op__insn$46[31:0]$10184 0 + sync always + sync init + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10184 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164342$10144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164342$10144_Y + attribute \src "libresoc.v:171595.13-171595.47" + process $proc$libresoc.v:171595$10185 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$10186 7'0000000 + sync always + sync init + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10186 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164345$10147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164345$10147_Y + attribute \src "libresoc.v:171603.7-171603.40" + process $proc$libresoc.v:171603$10187 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$10188 1'0 + sync always + sync init + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10188 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164347$10149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164347$10149_Y + attribute \src "libresoc.v:171611.7-171611.41" + process $proc$libresoc.v:171611$10189 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$10190 1'0 + sync always + sync init + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10190 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164349$10151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164349$10151_Y + attribute \src "libresoc.v:171619.7-171619.39" + process $proc$libresoc.v:171619$10191 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$10192 1'0 + sync always + sync init + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10192 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164351$10153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164351$10153_Y + attribute \src "libresoc.v:171627.7-171627.40" + process $proc$libresoc.v:171627$10193 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$10194 1'0 + sync always + sync init + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10194 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164352$10154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164352$10154_Y + attribute \src "libresoc.v:171633.7-171633.37" + process $proc$libresoc.v:171633$10195 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$10196 1'0 + sync always + sync init + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10196 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164354$10156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164354$10156_Y - end - connect \$7 $not$libresoc.v:164339$10141_Y - connect \$12 $reduce_or$libresoc.v:164340$10142_Y - connect \$11 $not$libresoc.v:164341$10143_Y - connect \$16 $reduce_or$libresoc.v:164342$10144_Y - connect \$15 $not$libresoc.v:164343$10145_Y - connect \$1 $not$libresoc.v:164344$10146_Y - connect \$20 $reduce_or$libresoc.v:164345$10147_Y - connect \$19 $not$libresoc.v:164346$10148_Y - connect \$24 $reduce_or$libresoc.v:164347$10149_Y - connect \$23 $not$libresoc.v:164348$10150_Y - connect \$28 $reduce_or$libresoc.v:164349$10151_Y - connect \$27 $not$libresoc.v:164350$10152_Y - connect \$31 $reduce_or$libresoc.v:164351$10153_Y - connect \$4 $reduce_or$libresoc.v:164352$10154_Y - connect \$3 $not$libresoc.v:164353$10155_Y - connect \$8 $reduce_or$libresoc.v:164354$10156_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164370.1-164454.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$139 - attribute \src "libresoc.v:164427.17-164427.91" - wire $not$libresoc.v:164427$10157_Y - attribute \src "libresoc.v:164429.18-164429.93" - wire $not$libresoc.v:164429$10159_Y - attribute \src "libresoc.v:164431.18-164431.93" - wire $not$libresoc.v:164431$10161_Y - attribute \src "libresoc.v:164432.17-164432.138" - wire width 8 $not$libresoc.v:164432$10162_Y - attribute \src "libresoc.v:164434.18-164434.93" - wire $not$libresoc.v:164434$10164_Y - attribute \src "libresoc.v:164436.18-164436.93" - wire $not$libresoc.v:164436$10166_Y - attribute \src "libresoc.v:164438.18-164438.93" - wire $not$libresoc.v:164438$10168_Y - attribute \src "libresoc.v:164441.17-164441.91" - wire $not$libresoc.v:164441$10171_Y - attribute \src "libresoc.v:164428.18-164428.116" - wire $reduce_or$libresoc.v:164428$10158_Y - attribute \src "libresoc.v:164430.18-164430.122" - wire $reduce_or$libresoc.v:164430$10160_Y - attribute \src "libresoc.v:164433.18-164433.128" - wire $reduce_or$libresoc.v:164433$10163_Y - attribute \src "libresoc.v:164435.18-164435.134" - wire $reduce_or$libresoc.v:164435$10165_Y - attribute \src "libresoc.v:164437.18-164437.140" - wire $reduce_or$libresoc.v:164437$10167_Y - attribute \src "libresoc.v:164439.18-164439.90" - wire $reduce_or$libresoc.v:164439$10169_Y - attribute \src "libresoc.v:164440.17-164440.103" - wire $reduce_or$libresoc.v:164440$10170_Y - attribute \src "libresoc.v:164442.17-164442.109" - wire $reduce_or$libresoc.v:164442$10172_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164427$10157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164427$10157_Y + attribute \src "libresoc.v:171641.7-171641.37" + process $proc$libresoc.v:171641$10197 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$10198 1'0 + sync always + sync init + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10198 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164429$10159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164429$10159_Y + attribute \src "libresoc.v:171651.7-171651.43" + process $proc$libresoc.v:171651$10199 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$10200 1'0 + sync always + sync init + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10200 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164431$10161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164431$10161_Y + attribute \src "libresoc.v:171657.7-171657.37" + process $proc$libresoc.v:171657$10201 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$10202 1'0 + sync always + sync init + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10202 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164432$10162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164432$10162_Y + attribute \src "libresoc.v:171665.7-171665.37" + process $proc$libresoc.v:171665$10203 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$10204 1'0 + sync always + sync init + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10204 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164434$10164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164434$10164_Y + attribute \src "libresoc.v:171675.7-171675.40" + process $proc$libresoc.v:171675$10205 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$10206 1'0 + sync always + sync init + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10206 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164436$10166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164436$10166_Y + attribute \src "libresoc.v:171683.7-171683.37" + process $proc$libresoc.v:171683$10207 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$10208 1'0 + sync always + sync init + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10208 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164438$10168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164438$10168_Y + attribute \src "libresoc.v:171691.13-171691.30" + process $proc$libresoc.v:171691$10209 + assign { } { } + assign $0\muxid$28[1:0]$10210 2'00 + sync always + sync init + update \muxid$28 $0\muxid$28[1:0]$10210 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164441$10171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164441$10171_Y + attribute \src "libresoc.v:171701.13-171701.34" + process $proc$libresoc.v:171701$10211 + assign { } { } + assign $0\operation$69[1:0]$10212 2'00 + sync always + sync init + update \operation$69 $0\operation$69[1:0]$10212 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164428$10158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164428$10158_Y + attribute \src "libresoc.v:171715.14-171715.44" + process $proc$libresoc.v:171715$10213 + assign { } { } + assign $0\ra$47[63:0]$10214 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra$47 $0\ra$47[63:0]$10214 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164430$10160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164430$10160_Y + attribute \src "libresoc.v:171723.14-171723.44" + process $proc$libresoc.v:171723$10215 + assign { } { } + assign $0\rb$48[63:0]$10216 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb$48 $0\rb$48[63:0]$10216 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164433$10163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164433$10163_Y + attribute \src "libresoc.v:171729.15-171729.84" + process $proc$libresoc.v:171729$10217 + assign { } { } + assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164435$10165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164435$10165_Y + attribute \src "libresoc.v:171733.13-171733.45" + process $proc$libresoc.v:171733$10218 + assign { } { } + assign $1\saved_state_q_bits_known[6:0] 7'0000000 + sync always + sync init + update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164437$10167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164437$10167_Y + attribute \src "libresoc.v:171741.7-171741.25" + process $proc$libresoc.v:171741$10219 + assign { } { } + assign $0\xer_so$49[0:0]$10220 1'0 + sync always + sync init + update \xer_so$49 $0\xer_so$49[0:0]$10220 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164439$10169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164439$10169_Y + attribute \src "libresoc.v:171750.3-171751.43" + process $proc$libresoc.v:171750$9970 + assign { } { } + assign $0\operation$69[1:0]$9971 \operation$69$next + sync posedge \coresync_clk + update \operation$69 $0\operation$69[1:0]$9971 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164440$10170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164440$10170_Y + attribute \src "libresoc.v:171752.3-171753.57" + process $proc$libresoc.v:171752$9972 + assign { } { } + assign $0\divisor_radicand$65[63:0]$9973 \divisor_radicand$65$next + sync posedge \coresync_clk + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9973 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164442$10172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164442$10172_Y - end - connect \$7 $not$libresoc.v:164427$10157_Y - connect \$12 $reduce_or$libresoc.v:164428$10158_Y - connect \$11 $not$libresoc.v:164429$10159_Y - connect \$16 $reduce_or$libresoc.v:164430$10160_Y - connect \$15 $not$libresoc.v:164431$10161_Y - connect \$1 $not$libresoc.v:164432$10162_Y - connect \$20 $reduce_or$libresoc.v:164433$10163_Y - connect \$19 $not$libresoc.v:164434$10164_Y - connect \$24 $reduce_or$libresoc.v:164435$10165_Y - connect \$23 $not$libresoc.v:164436$10166_Y - connect \$28 $reduce_or$libresoc.v:164437$10167_Y - connect \$27 $not$libresoc.v:164438$10168_Y - connect \$31 $reduce_or$libresoc.v:164439$10169_Y - connect \$4 $reduce_or$libresoc.v:164440$10170_Y - connect \$3 $not$libresoc.v:164441$10171_Y - connect \$8 $reduce_or$libresoc.v:164442$10172_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164458.1-164542.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$144 - attribute \src "libresoc.v:164515.17-164515.91" - wire $not$libresoc.v:164515$10173_Y - attribute \src "libresoc.v:164517.18-164517.93" - wire $not$libresoc.v:164517$10175_Y - attribute \src "libresoc.v:164519.18-164519.93" - wire $not$libresoc.v:164519$10177_Y - attribute \src "libresoc.v:164520.17-164520.138" - wire width 8 $not$libresoc.v:164520$10178_Y - attribute \src "libresoc.v:164522.18-164522.93" - wire $not$libresoc.v:164522$10180_Y - attribute \src "libresoc.v:164524.18-164524.93" - wire $not$libresoc.v:164524$10182_Y - attribute \src "libresoc.v:164526.18-164526.93" - wire $not$libresoc.v:164526$10184_Y - attribute \src "libresoc.v:164529.17-164529.91" - wire $not$libresoc.v:164529$10187_Y - attribute \src "libresoc.v:164516.18-164516.116" - wire $reduce_or$libresoc.v:164516$10174_Y - attribute \src "libresoc.v:164518.18-164518.122" - wire $reduce_or$libresoc.v:164518$10176_Y - attribute \src "libresoc.v:164521.18-164521.128" - wire $reduce_or$libresoc.v:164521$10179_Y - attribute \src "libresoc.v:164523.18-164523.134" - wire $reduce_or$libresoc.v:164523$10181_Y - attribute \src "libresoc.v:164525.18-164525.140" - wire $reduce_or$libresoc.v:164525$10183_Y - attribute \src "libresoc.v:164527.18-164527.90" - wire $reduce_or$libresoc.v:164527$10185_Y - attribute \src "libresoc.v:164528.17-164528.103" - wire $reduce_or$libresoc.v:164528$10186_Y - attribute \src "libresoc.v:164530.17-164530.109" - wire $reduce_or$libresoc.v:164530$10188_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164515$10173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164515$10173_Y + attribute \src "libresoc.v:171754.3-171755.41" + process $proc$libresoc.v:171754$9974 + assign { } { } + assign $0\dividend$68[127:0]$9975 \dividend$68$next + sync posedge \coresync_clk + update \dividend$68 $0\dividend$68[127:0]$9975 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164517$10175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164517$10175_Y + attribute \src "libresoc.v:171756.3-171757.47" + process $proc$libresoc.v:171756$9976 + assign { } { } + assign $0\div_by_zero$54[0:0]$9977 \div_by_zero$54$next + sync posedge \coresync_clk + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9977 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164519$10177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164519$10177_Y + attribute \src "libresoc.v:171758.3-171759.51" + process $proc$libresoc.v:171758$9978 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$9979 \dive_abs_ov64$53$next + sync posedge \coresync_clk + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9979 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164520$10178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164520$10178_Y + attribute \src "libresoc.v:171760.3-171761.51" + process $proc$libresoc.v:171760$9980 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$9981 \dive_abs_ov32$52$next + sync posedge \coresync_clk + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9981 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164522$10180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164522$10180_Y + attribute \src "libresoc.v:171762.3-171763.49" + process $proc$libresoc.v:171762$9982 + assign { } { } + assign $0\dividend_neg$51[0:0]$9983 \dividend_neg$51$next + sync posedge \coresync_clk + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9983 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164524$10182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164524$10182_Y + attribute \src "libresoc.v:171764.3-171765.47" + process $proc$libresoc.v:171764$9984 + assign { } { } + assign $0\divisor_neg$50[0:0]$9985 \divisor_neg$50$next + sync posedge \coresync_clk + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9985 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164526$10184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164526$10184_Y + attribute \src "libresoc.v:171766.3-171767.37" + process $proc$libresoc.v:171766$9986 + assign { } { } + assign $0\xer_so$49[0:0]$9987 \xer_so$49$next + sync posedge \coresync_clk + update \xer_so$49 $0\xer_so$49[0:0]$9987 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164529$10187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164529$10187_Y + attribute \src "libresoc.v:171768.3-171769.29" + process $proc$libresoc.v:171768$9988 + assign { } { } + assign $0\rb$48[63:0]$9989 \rb$48$next + sync posedge \coresync_clk + update \rb$48 $0\rb$48[63:0]$9989 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164516$10174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164516$10174_Y + attribute \src "libresoc.v:171770.3-171771.29" + process $proc$libresoc.v:171770$9990 + assign { } { } + assign $0\ra$47[63:0]$9991 \ra$47$next + sync posedge \coresync_clk + update \ra$47 $0\ra$47[63:0]$9991 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164518$10176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164518$10176_Y + attribute \src "libresoc.v:171772.3-171773.67" + process $proc$libresoc.v:171772$9992 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$9993 \logical_op__insn_type$29$next + sync posedge \coresync_clk + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9993 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164521$10179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164521$10179_Y + attribute \src "libresoc.v:171774.3-171775.63" + process $proc$libresoc.v:171774$9994 + assign { } { } + assign $0\logical_op__fn_unit$30[13:0]$9995 \logical_op__fn_unit$30$next + sync posedge \coresync_clk + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$9995 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164523$10181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164523$10181_Y + attribute \src "libresoc.v:171776.3-171777.77" + process $proc$libresoc.v:171776$9996 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$9997 \logical_op__imm_data__data$31$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9997 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164525$10183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164525$10183_Y + attribute \src "libresoc.v:171778.3-171779.73" + process $proc$libresoc.v:171778$9998 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$9999 \logical_op__imm_data__ok$32$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9999 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164527$10185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164527$10185_Y + attribute \src "libresoc.v:171780.3-171781.61" + process $proc$libresoc.v:171780$10000 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$10001 \logical_op__rc__rc$33$next + sync posedge \coresync_clk + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10001 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164528$10186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164528$10186_Y + attribute \src "libresoc.v:171782.3-171783.61" + process $proc$libresoc.v:171782$10002 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$10003 \logical_op__rc__ok$34$next + sync posedge \coresync_clk + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10003 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164530$10188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164530$10188_Y - end - connect \$7 $not$libresoc.v:164515$10173_Y - connect \$12 $reduce_or$libresoc.v:164516$10174_Y - connect \$11 $not$libresoc.v:164517$10175_Y - connect \$16 $reduce_or$libresoc.v:164518$10176_Y - connect \$15 $not$libresoc.v:164519$10177_Y - connect \$1 $not$libresoc.v:164520$10178_Y - connect \$20 $reduce_or$libresoc.v:164521$10179_Y - connect \$19 $not$libresoc.v:164522$10180_Y - connect \$24 $reduce_or$libresoc.v:164523$10181_Y - connect \$23 $not$libresoc.v:164524$10182_Y - connect \$28 $reduce_or$libresoc.v:164525$10183_Y - connect \$27 $not$libresoc.v:164526$10184_Y - connect \$31 $reduce_or$libresoc.v:164527$10185_Y - connect \$4 $reduce_or$libresoc.v:164528$10186_Y - connect \$3 $not$libresoc.v:164529$10187_Y - connect \$8 $reduce_or$libresoc.v:164530$10188_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164546.1-164630.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$146 - attribute \src "libresoc.v:164603.17-164603.91" - wire $not$libresoc.v:164603$10189_Y - attribute \src "libresoc.v:164605.18-164605.93" - wire $not$libresoc.v:164605$10191_Y - attribute \src "libresoc.v:164607.18-164607.93" - wire $not$libresoc.v:164607$10193_Y - attribute \src "libresoc.v:164608.17-164608.138" - wire width 8 $not$libresoc.v:164608$10194_Y - attribute \src "libresoc.v:164610.18-164610.93" - wire $not$libresoc.v:164610$10196_Y - attribute \src "libresoc.v:164612.18-164612.93" - wire $not$libresoc.v:164612$10198_Y - attribute \src "libresoc.v:164614.18-164614.93" - wire $not$libresoc.v:164614$10200_Y - attribute \src "libresoc.v:164617.17-164617.91" - wire $not$libresoc.v:164617$10203_Y - attribute \src "libresoc.v:164604.18-164604.116" - wire $reduce_or$libresoc.v:164604$10190_Y - attribute \src "libresoc.v:164606.18-164606.122" - wire $reduce_or$libresoc.v:164606$10192_Y - attribute \src "libresoc.v:164609.18-164609.128" - wire $reduce_or$libresoc.v:164609$10195_Y - attribute \src "libresoc.v:164611.18-164611.134" - wire $reduce_or$libresoc.v:164611$10197_Y - attribute \src "libresoc.v:164613.18-164613.140" - wire $reduce_or$libresoc.v:164613$10199_Y - attribute \src "libresoc.v:164615.18-164615.90" - wire $reduce_or$libresoc.v:164615$10201_Y - attribute \src "libresoc.v:164616.17-164616.103" - wire $reduce_or$libresoc.v:164616$10202_Y - attribute \src "libresoc.v:164618.17-164618.109" - wire $reduce_or$libresoc.v:164618$10204_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164603$10189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164603$10189_Y + attribute \src "libresoc.v:171784.3-171785.61" + process $proc$libresoc.v:171784$10004 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$10005 \logical_op__oe__oe$35$next + sync posedge \coresync_clk + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10005 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164605$10191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164605$10191_Y + attribute \src "libresoc.v:171786.3-171787.61" + process $proc$libresoc.v:171786$10006 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$10007 \logical_op__oe__ok$36$next + sync posedge \coresync_clk + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10007 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164607$10193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164607$10193_Y + attribute \src "libresoc.v:171788.3-171789.67" + process $proc$libresoc.v:171788$10008 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$10009 \logical_op__invert_in$37$next + sync posedge \coresync_clk + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10009 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164608$10194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164608$10194_Y + attribute \src "libresoc.v:171790.3-171791.61" + process $proc$libresoc.v:171790$10010 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$10011 \logical_op__zero_a$38$next + sync posedge \coresync_clk + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10011 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164610$10196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164610$10196_Y + attribute \src "libresoc.v:171792.3-171793.71" + process $proc$libresoc.v:171792$10012 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$10013 \logical_op__input_carry$39$next + sync posedge \coresync_clk + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10013 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164612$10198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164612$10198_Y + attribute \src "libresoc.v:171794.3-171795.69" + process $proc$libresoc.v:171794$10014 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$10015 \logical_op__invert_out$40$next + sync posedge \coresync_clk + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10015 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164614$10200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164614$10200_Y + attribute \src "libresoc.v:171796.3-171797.67" + process $proc$libresoc.v:171796$10016 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$10017 \logical_op__write_cr0$41$next + sync posedge \coresync_clk + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10017 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164617$10203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164617$10203_Y + attribute \src "libresoc.v:171798.3-171799.73" + process $proc$libresoc.v:171798$10018 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$10019 \logical_op__output_carry$42$next + sync posedge \coresync_clk + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10019 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164604$10190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164604$10190_Y + attribute \src "libresoc.v:171800.3-171801.65" + process $proc$libresoc.v:171800$10020 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$10021 \logical_op__is_32bit$43$next + sync posedge \coresync_clk + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10021 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164606$10192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164606$10192_Y + attribute \src "libresoc.v:171802.3-171803.67" + process $proc$libresoc.v:171802$10022 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$10023 \logical_op__is_signed$44$next + sync posedge \coresync_clk + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10023 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164609$10195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164609$10195_Y + attribute \src "libresoc.v:171804.3-171805.65" + process $proc$libresoc.v:171804$10024 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$10025 \logical_op__data_len$45$next + sync posedge \coresync_clk + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10025 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164611$10197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164611$10197_Y + attribute \src "libresoc.v:171806.3-171807.57" + process $proc$libresoc.v:171806$10026 + assign { } { } + assign $0\logical_op__insn$46[31:0]$10027 \logical_op__insn$46$next + sync posedge \coresync_clk + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10027 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164613$10199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164613$10199_Y + attribute \src "libresoc.v:171808.3-171809.35" + process $proc$libresoc.v:171808$10028 + assign { } { } + assign $0\muxid$28[1:0]$10029 \muxid$28$next + sync posedge \coresync_clk + update \muxid$28 $0\muxid$28[1:0]$10029 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164615$10201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164615$10201_Y + attribute \src "libresoc.v:171810.3-171811.27" + process $proc$libresoc.v:171810$10030 + assign { } { } + assign $0\empty[0:0] \empty$next + sync posedge \coresync_clk + update \empty $0\empty[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164616$10202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164616$10202_Y + attribute \src "libresoc.v:171812.3-171813.75" + process $proc$libresoc.v:171812$10031 + assign { } { } + assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + sync posedge \coresync_clk + update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164618$10204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164618$10204_Y - end - connect \$7 $not$libresoc.v:164603$10189_Y - connect \$12 $reduce_or$libresoc.v:164604$10190_Y - connect \$11 $not$libresoc.v:164605$10191_Y - connect \$16 $reduce_or$libresoc.v:164606$10192_Y - connect \$15 $not$libresoc.v:164607$10193_Y - connect \$1 $not$libresoc.v:164608$10194_Y - connect \$20 $reduce_or$libresoc.v:164609$10195_Y - connect \$19 $not$libresoc.v:164610$10196_Y - connect \$24 $reduce_or$libresoc.v:164611$10197_Y - connect \$23 $not$libresoc.v:164612$10198_Y - connect \$28 $reduce_or$libresoc.v:164613$10199_Y - connect \$27 $not$libresoc.v:164614$10200_Y - connect \$31 $reduce_or$libresoc.v:164615$10201_Y - connect \$4 $reduce_or$libresoc.v:164616$10202_Y - connect \$3 $not$libresoc.v:164617$10203_Y - connect \$8 $reduce_or$libresoc.v:164618$10204_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164634.1-164718.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$151 - attribute \src "libresoc.v:164691.17-164691.91" - wire $not$libresoc.v:164691$10205_Y - attribute \src "libresoc.v:164693.18-164693.93" - wire $not$libresoc.v:164693$10207_Y - attribute \src "libresoc.v:164695.18-164695.93" - wire $not$libresoc.v:164695$10209_Y - attribute \src "libresoc.v:164696.17-164696.138" - wire width 8 $not$libresoc.v:164696$10210_Y - attribute \src "libresoc.v:164698.18-164698.93" - wire $not$libresoc.v:164698$10212_Y - attribute \src "libresoc.v:164700.18-164700.93" - wire $not$libresoc.v:164700$10214_Y - attribute \src "libresoc.v:164702.18-164702.93" - wire $not$libresoc.v:164702$10216_Y - attribute \src "libresoc.v:164705.17-164705.91" - wire $not$libresoc.v:164705$10219_Y - attribute \src "libresoc.v:164692.18-164692.116" - wire $reduce_or$libresoc.v:164692$10206_Y - attribute \src "libresoc.v:164694.18-164694.122" - wire $reduce_or$libresoc.v:164694$10208_Y - attribute \src "libresoc.v:164697.18-164697.128" - wire $reduce_or$libresoc.v:164697$10211_Y - attribute \src "libresoc.v:164699.18-164699.134" - wire $reduce_or$libresoc.v:164699$10213_Y - attribute \src "libresoc.v:164701.18-164701.140" - wire $reduce_or$libresoc.v:164701$10215_Y - attribute \src "libresoc.v:164703.18-164703.90" - wire $reduce_or$libresoc.v:164703$10217_Y - attribute \src "libresoc.v:164704.17-164704.103" - wire $reduce_or$libresoc.v:164704$10218_Y - attribute \src "libresoc.v:164706.17-164706.109" - wire $reduce_or$libresoc.v:164706$10220_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164691$10205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164691$10205_Y + attribute \src "libresoc.v:171814.3-171815.65" + process $proc$libresoc.v:171814$10032 + assign { } { } + assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + sync posedge \coresync_clk + update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164693$10207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164693$10207_Y + attribute \src "libresoc.v:171836.3-171844.6" + process $proc$libresoc.v:171836$10033 + assign { } { } + assign { } { } + assign $0\saved_state_q_bits_known$next[6:0]$10034 $1\saved_state_q_bits_known$next[6:0]$10035 + attribute \src "libresoc.v:171837.5-171837.29" + switch \initial + attribute \src "libresoc.v:171837.9-171837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_q_bits_known$next[6:0]$10035 7'0000000 + case + assign $1\saved_state_q_bits_known$next[6:0]$10035 \div_state_next_o_q_bits_known + end + sync always + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10034 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164695$10209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164695$10209_Y + attribute \src "libresoc.v:171845.3-171853.6" + process $proc$libresoc.v:171845$10036 + assign { } { } + assign { } { } + assign $0\saved_state_dividend_quotient$next[127:0]$10037 $1\saved_state_dividend_quotient$next[127:0]$10038 + attribute \src "libresoc.v:171846.5-171846.29" + switch \initial + attribute \src "libresoc.v:171846.9-171846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_dividend_quotient$next[127:0]$10038 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\saved_state_dividend_quotient$next[127:0]$10038 \div_state_next_o_dividend_quotient + end + sync always + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10037 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164696$10210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164696$10210_Y + attribute \src "libresoc.v:171854.3-171865.6" + process $proc$libresoc.v:171854$10039 + assign { } { } + assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:171855.5-171855.29" + switch \initial + attribute \src "libresoc.v:171855.9-171855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known + end + sync always + update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164698$10212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164698$10212_Y + attribute \src "libresoc.v:171866.3-171877.6" + process $proc$libresoc.v:171866$10040 + assign { } { } + assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:171867.5-171867.29" + switch \initial + attribute \src "libresoc.v:171867.9-171867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient + end + sync always + update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164700$10214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164700$10214_Y + attribute \src "libresoc.v:171878.3-171889.6" + process $proc$libresoc.v:171878$10041 + assign { } { } + assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:171879.5-171879.29" + switch \initial + attribute \src "libresoc.v:171879.9-171879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 + end + sync always + update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164702$10216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164702$10216_Y + attribute \src "libresoc.v:171890.3-171917.6" + process $proc$libresoc.v:171890$10042 + assign { } { } + assign { } { } + assign { } { } + assign $0\empty$next[0:0]$10043 $4\empty$next[0:0]$10047 + attribute \src "libresoc.v:171891.5-171891.29" + switch \initial + attribute \src "libresoc.v:171891.9-171891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\empty$next[0:0]$10044 $2\empty$next[0:0]$10045 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\empty$next[0:0]$10045 1'0 + case + assign $2\empty$next[0:0]$10045 \empty + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\empty$next[0:0]$10044 $3\empty$next[0:0]$10046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + switch \$66 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\empty$next[0:0]$10046 1'1 + case + assign $3\empty$next[0:0]$10046 \empty + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\empty$next[0:0]$10047 1'1 + case + assign $4\empty$next[0:0]$10047 $1\empty$next[0:0]$10044 + end + sync always + update \empty$next $0\empty$next[0:0]$10043 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164705$10219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164705$10219_Y + attribute \src "libresoc.v:171918.3-171932.6" + process $proc$libresoc.v:171918$10048 + assign { } { } + assign { } { } + assign $0\muxid$28$next[1:0]$10049 $1\muxid$28$next[1:0]$10050 + attribute \src "libresoc.v:171919.5-171919.29" + switch \initial + attribute \src "libresoc.v:171919.9-171919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\muxid$28$next[1:0]$10050 $2\muxid$28$next[1:0]$10051 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\muxid$28$next[1:0]$10051 \muxid + case + assign $2\muxid$28$next[1:0]$10051 \muxid$28 + end + case + assign $1\muxid$28$next[1:0]$10050 \muxid$28 + end + sync always + update \muxid$28$next $0\muxid$28$next[1:0]$10049 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164692$10206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164692$10206_Y + attribute \src "libresoc.v:171933.3-171976.6" + process $proc$libresoc.v:171933$10052 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$45$next[3:0]$10053 $1\logical_op__data_len$45$next[3:0]$10071 + assign $0\logical_op__fn_unit$30$next[13:0]$10054 $1\logical_op__fn_unit$30$next[13:0]$10072 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$39$next[1:0]$10057 $1\logical_op__input_carry$39$next[1:0]$10075 + assign $0\logical_op__insn$46$next[31:0]$10058 $1\logical_op__insn$46$next[31:0]$10076 + assign $0\logical_op__insn_type$29$next[6:0]$10059 $1\logical_op__insn_type$29$next[6:0]$10077 + assign $0\logical_op__invert_in$37$next[0:0]$10060 $1\logical_op__invert_in$37$next[0:0]$10078 + assign $0\logical_op__invert_out$40$next[0:0]$10061 $1\logical_op__invert_out$40$next[0:0]$10079 + assign $0\logical_op__is_32bit$43$next[0:0]$10062 $1\logical_op__is_32bit$43$next[0:0]$10080 + assign $0\logical_op__is_signed$44$next[0:0]$10063 $1\logical_op__is_signed$44$next[0:0]$10081 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$42$next[0:0]$10066 $1\logical_op__output_carry$42$next[0:0]$10084 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$41$next[0:0]$10069 $1\logical_op__write_cr0$41$next[0:0]$10087 + assign $0\logical_op__zero_a$38$next[0:0]$10070 $1\logical_op__zero_a$38$next[0:0]$10088 + assign $0\logical_op__imm_data__data$31$next[63:0]$10055 $3\logical_op__imm_data__data$31$next[63:0]$10107 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10056 $3\logical_op__imm_data__ok$32$next[0:0]$10108 + assign $0\logical_op__oe__oe$35$next[0:0]$10064 $3\logical_op__oe__oe$35$next[0:0]$10109 + assign $0\logical_op__oe__ok$36$next[0:0]$10065 $3\logical_op__oe__ok$36$next[0:0]$10110 + assign $0\logical_op__rc__ok$34$next[0:0]$10067 $3\logical_op__rc__ok$34$next[0:0]$10111 + assign $0\logical_op__rc__rc$33$next[0:0]$10068 $3\logical_op__rc__rc$33$next[0:0]$10112 + attribute \src "libresoc.v:171934.5-171934.29" + switch \initial + attribute \src "libresoc.v:171934.9-171934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\logical_op__data_len$45$next[3:0]$10071 $2\logical_op__data_len$45$next[3:0]$10089 + assign $1\logical_op__fn_unit$30$next[13:0]$10072 $2\logical_op__fn_unit$30$next[13:0]$10090 + assign $1\logical_op__imm_data__data$31$next[63:0]$10073 $2\logical_op__imm_data__data$31$next[63:0]$10091 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10074 $2\logical_op__imm_data__ok$32$next[0:0]$10092 + assign $1\logical_op__input_carry$39$next[1:0]$10075 $2\logical_op__input_carry$39$next[1:0]$10093 + assign $1\logical_op__insn$46$next[31:0]$10076 $2\logical_op__insn$46$next[31:0]$10094 + assign $1\logical_op__insn_type$29$next[6:0]$10077 $2\logical_op__insn_type$29$next[6:0]$10095 + assign $1\logical_op__invert_in$37$next[0:0]$10078 $2\logical_op__invert_in$37$next[0:0]$10096 + assign $1\logical_op__invert_out$40$next[0:0]$10079 $2\logical_op__invert_out$40$next[0:0]$10097 + assign $1\logical_op__is_32bit$43$next[0:0]$10080 $2\logical_op__is_32bit$43$next[0:0]$10098 + assign $1\logical_op__is_signed$44$next[0:0]$10081 $2\logical_op__is_signed$44$next[0:0]$10099 + assign $1\logical_op__oe__oe$35$next[0:0]$10082 $2\logical_op__oe__oe$35$next[0:0]$10100 + assign $1\logical_op__oe__ok$36$next[0:0]$10083 $2\logical_op__oe__ok$36$next[0:0]$10101 + assign $1\logical_op__output_carry$42$next[0:0]$10084 $2\logical_op__output_carry$42$next[0:0]$10102 + assign $1\logical_op__rc__ok$34$next[0:0]$10085 $2\logical_op__rc__ok$34$next[0:0]$10103 + assign $1\logical_op__rc__rc$33$next[0:0]$10086 $2\logical_op__rc__rc$33$next[0:0]$10104 + assign $1\logical_op__write_cr0$41$next[0:0]$10087 $2\logical_op__write_cr0$41$next[0:0]$10105 + assign $1\logical_op__zero_a$38$next[0:0]$10088 $2\logical_op__zero_a$38$next[0:0]$10106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\logical_op__insn$46$next[31:0]$10094 $2\logical_op__data_len$45$next[3:0]$10089 $2\logical_op__is_signed$44$next[0:0]$10099 $2\logical_op__is_32bit$43$next[0:0]$10098 $2\logical_op__output_carry$42$next[0:0]$10102 $2\logical_op__write_cr0$41$next[0:0]$10105 $2\logical_op__invert_out$40$next[0:0]$10097 $2\logical_op__input_carry$39$next[1:0]$10093 $2\logical_op__zero_a$38$next[0:0]$10106 $2\logical_op__invert_in$37$next[0:0]$10096 $2\logical_op__oe__ok$36$next[0:0]$10101 $2\logical_op__oe__oe$35$next[0:0]$10100 $2\logical_op__rc__ok$34$next[0:0]$10103 $2\logical_op__rc__rc$33$next[0:0]$10104 $2\logical_op__imm_data__ok$32$next[0:0]$10092 $2\logical_op__imm_data__data$31$next[63:0]$10091 $2\logical_op__fn_unit$30$next[13:0]$10090 $2\logical_op__insn_type$29$next[6:0]$10095 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + case + assign $2\logical_op__data_len$45$next[3:0]$10089 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[13:0]$10090 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10091 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10092 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10093 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10094 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10095 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10096 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10097 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10098 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10099 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10100 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10101 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10102 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10103 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10104 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10105 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10106 \logical_op__zero_a$38 + end + case + assign $1\logical_op__data_len$45$next[3:0]$10071 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[13:0]$10072 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10073 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10074 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10075 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10076 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10077 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10078 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10079 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10080 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10081 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10082 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10083 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10084 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10085 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10086 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10087 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10088 \logical_op__zero_a$38 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\logical_op__imm_data__data$31$next[63:0]$10107 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10108 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10112 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10111 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10109 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10110 1'0 + case + assign $3\logical_op__imm_data__data$31$next[63:0]$10107 $1\logical_op__imm_data__data$31$next[63:0]$10073 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10108 $1\logical_op__imm_data__ok$32$next[0:0]$10074 + assign $3\logical_op__oe__oe$35$next[0:0]$10109 $1\logical_op__oe__oe$35$next[0:0]$10082 + assign $3\logical_op__oe__ok$36$next[0:0]$10110 $1\logical_op__oe__ok$36$next[0:0]$10083 + assign $3\logical_op__rc__ok$34$next[0:0]$10111 $1\logical_op__rc__ok$34$next[0:0]$10085 + assign $3\logical_op__rc__rc$33$next[0:0]$10112 $1\logical_op__rc__rc$33$next[0:0]$10086 + end + sync always + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10053 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10054 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10055 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10056 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10057 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10058 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10059 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10060 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10061 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10062 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10063 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10064 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10065 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10066 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10067 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10068 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10069 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10070 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164694$10208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164694$10208_Y + attribute \src "libresoc.v:171977.3-171991.6" + process $proc$libresoc.v:171977$10113 + assign { } { } + assign { } { } + assign $0\ra$47$next[63:0]$10114 $1\ra$47$next[63:0]$10115 + attribute \src "libresoc.v:171978.5-171978.29" + switch \initial + attribute \src "libresoc.v:171978.9-171978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ra$47$next[63:0]$10115 $2\ra$47$next[63:0]$10116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ra$47$next[63:0]$10116 \ra + case + assign $2\ra$47$next[63:0]$10116 \ra$47 + end + case + assign $1\ra$47$next[63:0]$10115 \ra$47 + end + sync always + update \ra$47$next $0\ra$47$next[63:0]$10114 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164697$10211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164697$10211_Y + attribute \src "libresoc.v:171992.3-172006.6" + process $proc$libresoc.v:171992$10117 + assign { } { } + assign { } { } + assign $0\rb$48$next[63:0]$10118 $1\rb$48$next[63:0]$10119 + attribute \src "libresoc.v:171993.5-171993.29" + switch \initial + attribute \src "libresoc.v:171993.9-171993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rb$48$next[63:0]$10119 $2\rb$48$next[63:0]$10120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\rb$48$next[63:0]$10120 \rb + case + assign $2\rb$48$next[63:0]$10120 \rb$48 + end + case + assign $1\rb$48$next[63:0]$10119 \rb$48 + end + sync always + update \rb$48$next $0\rb$48$next[63:0]$10118 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164699$10213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164699$10213_Y + attribute \src "libresoc.v:172007.3-172021.6" + process $proc$libresoc.v:172007$10121 + assign { } { } + assign { } { } + assign $0\xer_so$49$next[0:0]$10122 $1\xer_so$49$next[0:0]$10123 + attribute \src "libresoc.v:172008.5-172008.29" + switch \initial + attribute \src "libresoc.v:172008.9-172008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$49$next[0:0]$10123 $2\xer_so$49$next[0:0]$10124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so$49$next[0:0]$10124 \xer_so + case + assign $2\xer_so$49$next[0:0]$10124 \xer_so$49 + end + case + assign $1\xer_so$49$next[0:0]$10123 \xer_so$49 + end + sync always + update \xer_so$49$next $0\xer_so$49$next[0:0]$10122 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164701$10215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164701$10215_Y + attribute \src "libresoc.v:172022.3-172036.6" + process $proc$libresoc.v:172022$10125 + assign { } { } + assign { } { } + assign $0\divisor_neg$50$next[0:0]$10126 $1\divisor_neg$50$next[0:0]$10127 + attribute \src "libresoc.v:172023.5-172023.29" + switch \initial + attribute \src "libresoc.v:172023.9-172023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_neg$50$next[0:0]$10127 $2\divisor_neg$50$next[0:0]$10128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_neg$50$next[0:0]$10128 \divisor_neg + case + assign $2\divisor_neg$50$next[0:0]$10128 \divisor_neg$50 + end + case + assign $1\divisor_neg$50$next[0:0]$10127 \divisor_neg$50 + end + sync always + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10126 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164703$10217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164703$10217_Y + attribute \src "libresoc.v:172037.3-172051.6" + process $proc$libresoc.v:172037$10129 + assign { } { } + assign { } { } + assign $0\dividend_neg$51$next[0:0]$10130 $1\dividend_neg$51$next[0:0]$10131 + attribute \src "libresoc.v:172038.5-172038.29" + switch \initial + attribute \src "libresoc.v:172038.9-172038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend_neg$51$next[0:0]$10131 $2\dividend_neg$51$next[0:0]$10132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend_neg$51$next[0:0]$10132 \dividend_neg + case + assign $2\dividend_neg$51$next[0:0]$10132 \dividend_neg$51 + end + case + assign $1\dividend_neg$51$next[0:0]$10131 \dividend_neg$51 + end + sync always + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10130 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164704$10218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164704$10218_Y + attribute \src "libresoc.v:172052.3-172066.6" + process $proc$libresoc.v:172052$10133 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$52$next[0:0]$10134 $1\dive_abs_ov32$52$next[0:0]$10135 + attribute \src "libresoc.v:172053.5-172053.29" + switch \initial + attribute \src "libresoc.v:172053.9-172053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov32$52$next[0:0]$10135 $2\dive_abs_ov32$52$next[0:0]$10136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov32$52$next[0:0]$10136 \dive_abs_ov32 + case + assign $2\dive_abs_ov32$52$next[0:0]$10136 \dive_abs_ov32$52 + end + case + assign $1\dive_abs_ov32$52$next[0:0]$10135 \dive_abs_ov32$52 + end + sync always + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10134 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164706$10220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164706$10220_Y - end - connect \$7 $not$libresoc.v:164691$10205_Y - connect \$12 $reduce_or$libresoc.v:164692$10206_Y - connect \$11 $not$libresoc.v:164693$10207_Y - connect \$16 $reduce_or$libresoc.v:164694$10208_Y - connect \$15 $not$libresoc.v:164695$10209_Y - connect \$1 $not$libresoc.v:164696$10210_Y - connect \$20 $reduce_or$libresoc.v:164697$10211_Y - connect \$19 $not$libresoc.v:164698$10212_Y - connect \$24 $reduce_or$libresoc.v:164699$10213_Y - connect \$23 $not$libresoc.v:164700$10214_Y - connect \$28 $reduce_or$libresoc.v:164701$10215_Y - connect \$27 $not$libresoc.v:164702$10216_Y - connect \$31 $reduce_or$libresoc.v:164703$10217_Y - connect \$4 $reduce_or$libresoc.v:164704$10218_Y - connect \$3 $not$libresoc.v:164705$10219_Y - connect \$8 $reduce_or$libresoc.v:164706$10220_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164722.1-164806.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$153 - attribute \src "libresoc.v:164779.17-164779.91" - wire $not$libresoc.v:164779$10221_Y - attribute \src "libresoc.v:164781.18-164781.93" - wire $not$libresoc.v:164781$10223_Y - attribute \src "libresoc.v:164783.18-164783.93" - wire $not$libresoc.v:164783$10225_Y - attribute \src "libresoc.v:164784.17-164784.138" - wire width 8 $not$libresoc.v:164784$10226_Y - attribute \src "libresoc.v:164786.18-164786.93" - wire $not$libresoc.v:164786$10228_Y - attribute \src "libresoc.v:164788.18-164788.93" - wire $not$libresoc.v:164788$10230_Y - attribute \src "libresoc.v:164790.18-164790.93" - wire $not$libresoc.v:164790$10232_Y - attribute \src "libresoc.v:164793.17-164793.91" - wire $not$libresoc.v:164793$10235_Y - attribute \src "libresoc.v:164780.18-164780.116" - wire $reduce_or$libresoc.v:164780$10222_Y - attribute \src "libresoc.v:164782.18-164782.122" - wire $reduce_or$libresoc.v:164782$10224_Y - attribute \src "libresoc.v:164785.18-164785.128" - wire $reduce_or$libresoc.v:164785$10227_Y - attribute \src "libresoc.v:164787.18-164787.134" - wire $reduce_or$libresoc.v:164787$10229_Y - attribute \src "libresoc.v:164789.18-164789.140" - wire $reduce_or$libresoc.v:164789$10231_Y - attribute \src "libresoc.v:164791.18-164791.90" - wire $reduce_or$libresoc.v:164791$10233_Y - attribute \src "libresoc.v:164792.17-164792.103" - wire $reduce_or$libresoc.v:164792$10234_Y - attribute \src "libresoc.v:164794.17-164794.109" - wire $reduce_or$libresoc.v:164794$10236_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164779$10221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164779$10221_Y + attribute \src "libresoc.v:172067.3-172081.6" + process $proc$libresoc.v:172067$10137 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$53$next[0:0]$10138 $1\dive_abs_ov64$53$next[0:0]$10139 + attribute \src "libresoc.v:172068.5-172068.29" + switch \initial + attribute \src "libresoc.v:172068.9-172068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov64$53$next[0:0]$10139 $2\dive_abs_ov64$53$next[0:0]$10140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov64$53$next[0:0]$10140 \dive_abs_ov64 + case + assign $2\dive_abs_ov64$53$next[0:0]$10140 \dive_abs_ov64$53 + end + case + assign $1\dive_abs_ov64$53$next[0:0]$10139 \dive_abs_ov64$53 + end + sync always + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10138 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164781$10223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164781$10223_Y + attribute \src "libresoc.v:172082.3-172096.6" + process $proc$libresoc.v:172082$10141 + assign { } { } + assign { } { } + assign $0\div_by_zero$54$next[0:0]$10142 $1\div_by_zero$54$next[0:0]$10143 + attribute \src "libresoc.v:172083.5-172083.29" + switch \initial + attribute \src "libresoc.v:172083.9-172083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_by_zero$54$next[0:0]$10143 $2\div_by_zero$54$next[0:0]$10144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\div_by_zero$54$next[0:0]$10144 \div_by_zero + case + assign $2\div_by_zero$54$next[0:0]$10144 \div_by_zero$54 + end + case + assign $1\div_by_zero$54$next[0:0]$10143 \div_by_zero$54 + end + sync always + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10142 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164783$10225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164783$10225_Y + attribute \src "libresoc.v:172097.3-172111.6" + process $proc$libresoc.v:172097$10145 + assign { } { } + assign { } { } + assign $0\dividend$68$next[127:0]$10146 $1\dividend$68$next[127:0]$10147 + attribute \src "libresoc.v:172098.5-172098.29" + switch \initial + attribute \src "libresoc.v:172098.9-172098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend$68$next[127:0]$10147 $2\dividend$68$next[127:0]$10148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend$68$next[127:0]$10148 \dividend + case + assign $2\dividend$68$next[127:0]$10148 \dividend$68 + end + case + assign $1\dividend$68$next[127:0]$10147 \dividend$68 + end + sync always + update \dividend$68$next $0\dividend$68$next[127:0]$10146 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164784$10226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164784$10226_Y + attribute \src "libresoc.v:172112.3-172126.6" + process $proc$libresoc.v:172112$10149 + assign { } { } + assign { } { } + assign $0\divisor_radicand$65$next[63:0]$10150 $1\divisor_radicand$65$next[63:0]$10151 + attribute \src "libresoc.v:172113.5-172113.29" + switch \initial + attribute \src "libresoc.v:172113.9-172113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_radicand$65$next[63:0]$10151 $2\divisor_radicand$65$next[63:0]$10152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_radicand$65$next[63:0]$10152 \divisor_radicand + case + assign $2\divisor_radicand$65$next[63:0]$10152 \divisor_radicand$65 + end + case + assign $1\divisor_radicand$65$next[63:0]$10151 \divisor_radicand$65 + end + sync always + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10150 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164786$10228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164786$10228_Y + attribute \src "libresoc.v:172127.3-172141.6" + process $proc$libresoc.v:172127$10153 + assign { } { } + assign { } { } + assign $0\operation$69$next[1:0]$10154 $1\operation$69$next[1:0]$10155 + attribute \src "libresoc.v:172128.5-172128.29" + switch \initial + attribute \src "libresoc.v:172128.9-172128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\operation$69$next[1:0]$10155 $2\operation$69$next[1:0]$10156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\operation$69$next[1:0]$10156 \operation + case + assign $2\operation$69$next[1:0]$10156 \operation$69 + end + case + assign $1\operation$69$next[1:0]$10155 \operation$69 + end + sync always + update \operation$69$next $0\operation$69$next[1:0]$10154 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164788$10230 + connect \$56 $sshl$libresoc.v:171744$9963_Y + connect \$55 $pos$libresoc.v:171745$9965_Y + connect \$59 $not$libresoc.v:171746$9966_Y + connect \$61 $ge$libresoc.v:171747$9967_Y + connect \$63 $and$libresoc.v:171748$9968_Y + connect \$66 $and$libresoc.v:171749$9969_Y + connect \p_ready_o \empty + connect \n_valid_o \$63 + connect \remainder \$55 + connect \quotient_root \div_state_next_o_dividend_quotient [63:0] + connect \div_by_zero$27 \div_by_zero$54 + connect \dive_abs_ov64$26 \dive_abs_ov64$53 + connect \dive_abs_ov32$25 \dive_abs_ov32$52 + connect \dividend_neg$24 \dividend_neg$51 + connect \divisor_neg$23 \divisor_neg$50 + connect \xer_so$22 \xer_so$49 + connect \rb$21 \rb$48 + connect \ra$20 \ra$47 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } + connect \muxid$1 \muxid$28 + connect \div_state_init_dividend \dividend +end +attribute \src "libresoc.v:172161.1-173706.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" +attribute \generator "nMigen" +module \pipe_start + attribute \src "libresoc.v:173512.3-173524.6" + wire $0\div_by_zero$next[0:0]$10266 + attribute \src "libresoc.v:173298.3-173299.39" + wire $0\div_by_zero[0:0] + attribute \src "libresoc.v:173486.3-173498.6" + wire $0\dive_abs_ov32$next[0:0]$10260 + attribute \src "libresoc.v:173302.3-173303.43" + wire $0\dive_abs_ov32[0:0] + attribute \src "libresoc.v:173499.3-173511.6" + wire $0\dive_abs_ov64$next[0:0]$10263 + attribute \src "libresoc.v:173300.3-173301.43" + wire $0\dive_abs_ov64[0:0] + attribute \src "libresoc.v:173525.3-173537.6" + wire width 128 $0\dividend$next[127:0]$10269 + attribute \src "libresoc.v:173296.3-173297.33" + wire width 128 $0\dividend[127:0] + attribute \src "libresoc.v:173473.3-173485.6" + wire $0\dividend_neg$next[0:0]$10257 + attribute \src "libresoc.v:173304.3-173305.41" + wire $0\dividend_neg[0:0] + attribute \src "libresoc.v:173460.3-173472.6" + wire $0\divisor_neg$next[0:0]$10254 + attribute \src "libresoc.v:173306.3-173307.39" + wire $0\divisor_neg[0:0] + attribute \src "libresoc.v:173538.3-173550.6" + wire width 64 $0\divisor_radicand$next[63:0]$10272 + attribute \src "libresoc.v:173294.3-173295.49" + wire width 64 $0\divisor_radicand[63:0] + attribute \src "libresoc.v:172162.7-172162.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10285 + attribute \src "libresoc.v:173346.3-173347.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$10286 + attribute \src "libresoc.v:173316.3-173317.55" + wire width 14 $0\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10287 + attribute \src "libresoc.v:173318.3-173319.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10288 + attribute \src "libresoc.v:173320.3-173321.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10289 + attribute \src "libresoc.v:173334.3-173335.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 32 $0\logical_op__insn$next[31:0]$10290 + attribute \src "libresoc.v:173348.3-173349.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10291 + attribute \src "libresoc.v:173314.3-173315.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__invert_in$next[0:0]$10292 + attribute \src "libresoc.v:173330.3-173331.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__invert_out$next[0:0]$10293 + attribute \src "libresoc.v:173336.3-173337.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__is_32bit$next[0:0]$10294 + attribute \src "libresoc.v:173342.3-173343.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__is_signed$next[0:0]$10295 + attribute \src "libresoc.v:173344.3-173345.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__oe__oe$next[0:0]$10296 + attribute \src "libresoc.v:173326.3-173327.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__oe__ok$next[0:0]$10297 + attribute \src "libresoc.v:173328.3-173329.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__output_carry$next[0:0]$10298 + attribute \src "libresoc.v:173340.3-173341.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__rc__ok$next[0:0]$10299 + attribute \src "libresoc.v:173324.3-173325.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__rc__rc$next[0:0]$10300 + attribute \src "libresoc.v:173322.3-173323.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__write_cr0$next[0:0]$10301 + attribute \src "libresoc.v:173338.3-173339.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__zero_a$next[0:0]$10302 + attribute \src "libresoc.v:173332.3-173333.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:173582.3-173594.6" + wire width 2 $0\muxid$next[1:0]$10282 + attribute \src "libresoc.v:173350.3-173351.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:173551.3-173563.6" + wire width 2 $0\operation$next[1:0]$10275 + attribute \src "libresoc.v:173292.3-173293.35" + wire width 2 $0\operation[1:0] + attribute \src "libresoc.v:173564.3-173581.6" + wire $0\r_busy$next[0:0]$10278 + attribute \src "libresoc.v:173352.3-173353.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:173637.3-173649.6" + wire width 64 $0\ra$next[63:0]$10328 + attribute \src "libresoc.v:173312.3-173313.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:173650.3-173662.6" + wire width 64 $0\rb$next[63:0]$10331 + attribute \src "libresoc.v:173310.3-173311.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:173663.3-173675.6" + wire $0\xer_so$next[0:0]$10334 + attribute \src "libresoc.v:173308.3-173309.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:173512.3-173524.6" + wire $1\div_by_zero$next[0:0]$10267 + attribute \src "libresoc.v:172171.7-172171.25" + wire $1\div_by_zero[0:0] + attribute \src "libresoc.v:173486.3-173498.6" + wire $1\dive_abs_ov32$next[0:0]$10261 + attribute \src "libresoc.v:172178.7-172178.27" + wire $1\dive_abs_ov32[0:0] + attribute \src "libresoc.v:173499.3-173511.6" + wire $1\dive_abs_ov64$next[0:0]$10264 + attribute \src "libresoc.v:172185.7-172185.27" + wire $1\dive_abs_ov64[0:0] + attribute \src "libresoc.v:173525.3-173537.6" + wire width 128 $1\dividend$next[127:0]$10270 + attribute \src "libresoc.v:172192.15-172192.63" + wire width 128 $1\dividend[127:0] + attribute \src "libresoc.v:173473.3-173485.6" + wire $1\dividend_neg$next[0:0]$10258 + attribute \src "libresoc.v:172199.7-172199.26" + wire $1\dividend_neg[0:0] + attribute \src "libresoc.v:173460.3-173472.6" + wire $1\divisor_neg$next[0:0]$10255 + attribute \src "libresoc.v:172206.7-172206.25" + wire $1\divisor_neg[0:0] + attribute \src "libresoc.v:173538.3-173550.6" + wire width 64 $1\divisor_radicand$next[63:0]$10273 + attribute \src "libresoc.v:172213.14-172213.53" + wire width 64 $1\divisor_radicand[63:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10303 + attribute \src "libresoc.v:172496.13-172496.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$10304 + attribute \src "libresoc.v:172520.14-172520.44" + wire width 14 $1\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10305 + attribute \src "libresoc.v:172559.14-172559.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10306 + attribute \src "libresoc.v:172568.7-172568.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10307 + attribute \src "libresoc.v:172581.13-172581.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 32 $1\logical_op__insn$next[31:0]$10308 + attribute \src "libresoc.v:172598.14-172598.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10309 + attribute \src "libresoc.v:172682.13-172682.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__invert_in$next[0:0]$10310 + attribute \src "libresoc.v:172841.7-172841.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__invert_out$next[0:0]$10311 + attribute \src "libresoc.v:172850.7-172850.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__is_32bit$next[0:0]$10312 + attribute \src "libresoc.v:172859.7-172859.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__is_signed$next[0:0]$10313 + attribute \src "libresoc.v:172868.7-172868.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__oe__oe$next[0:0]$10314 + attribute \src "libresoc.v:172877.7-172877.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__oe__ok$next[0:0]$10315 + attribute \src "libresoc.v:172886.7-172886.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__output_carry$next[0:0]$10316 + attribute \src "libresoc.v:172895.7-172895.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__rc__ok$next[0:0]$10317 + attribute \src "libresoc.v:172904.7-172904.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__rc__rc$next[0:0]$10318 + attribute \src "libresoc.v:172913.7-172913.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__write_cr0$next[0:0]$10319 + attribute \src "libresoc.v:172922.7-172922.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__zero_a$next[0:0]$10320 + attribute \src "libresoc.v:172931.7-172931.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "libresoc.v:173582.3-173594.6" + wire width 2 $1\muxid$next[1:0]$10283 + attribute \src "libresoc.v:172940.13-172940.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:173551.3-173563.6" + wire width 2 $1\operation$next[1:0]$10276 + attribute \src "libresoc.v:172955.13-172955.29" + wire width 2 $1\operation[1:0] + attribute \src "libresoc.v:173564.3-173581.6" + wire $1\r_busy$next[0:0]$10279 + attribute \src "libresoc.v:172969.7-172969.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:173637.3-173649.6" + wire width 64 $1\ra$next[63:0]$10329 + attribute \src "libresoc.v:172974.14-172974.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:173650.3-173662.6" + wire width 64 $1\rb$next[63:0]$10332 + attribute \src "libresoc.v:172985.14-172985.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:173663.3-173675.6" + wire $1\xer_so$next[0:0]$10335 + attribute \src "libresoc.v:173284.7-173284.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10321 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10322 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__oe__oe$next[0:0]$10323 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__oe__ok$next[0:0]$10324 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__rc__ok$next[0:0]$10325 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__rc__rc$next[0:0]$10326 + attribute \src "libresoc.v:173564.3-173581.6" + wire $2\r_busy$next[0:0]$10280 + attribute \src "libresoc.v:173291.18-173291.118" + wire $and$libresoc.v:173291$10221_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$next + attribute \src "libresoc.v:172162.7-172162.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$40 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$27 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 35 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 34 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \setup_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \setup_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \setup_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \setup_stage_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \setup_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \setup_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \setup_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \setup_stage_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \setup_stage_logical_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \setup_stage_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \setup_stage_logical_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \setup_stage_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \setup_stage_logical_op__input_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \setup_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \setup_stage_logical_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \setup_stage_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \setup_stage_logical_op__insn_type$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_out$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__write_cr0$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \setup_stage_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \setup_stage_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \setup_stage_operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \setup_stage_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \setup_stage_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \setup_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \setup_stage_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:173291$10221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164788$10230_Y + connect \A \p_valid_i$65 + connect \B \p_ready_o + connect \Y $and$libresoc.v:173291$10221_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164790$10232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164790$10232_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:173354.14-173399.4" + cell \input$78 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$40 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$41 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$23 + connect \ra \input_ra + connect \ra$20 \input_ra$42 + connect \rb \input_rb + connect \rb$21 \input_rb$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$44 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164793$10235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164793$10235_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:173400.10-173403.4" + cell \n$77 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164780$10222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164780$10222_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:173404.10-173407.4" + cell \p$76 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164782$10224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164782$10224_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:173408.15-173459.4" + cell \setup_stage \setup_stage + connect \div_by_zero \setup_stage_div_by_zero + connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 + connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 + connect \dividend \setup_stage_dividend + connect \dividend_neg \setup_stage_dividend_neg + connect \divisor_neg \setup_stage_divisor_neg + connect \divisor_radicand \setup_stage_divisor_radicand + connect \logical_op__data_len \setup_stage_logical_op__data_len + connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 + connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 + connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 + connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 + connect \logical_op__input_carry \setup_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 + connect \logical_op__insn \setup_stage_logical_op__insn + connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 + connect \logical_op__insn_type \setup_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 + connect \logical_op__invert_in \setup_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 + connect \logical_op__invert_out \setup_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 + connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 + connect \logical_op__is_signed \setup_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 + connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 + connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 + connect \logical_op__output_carry \setup_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 + connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 + connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 + connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 + connect \logical_op__zero_a \setup_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 + connect \muxid \setup_stage_muxid + connect \muxid$1 \setup_stage_muxid$45 + connect \operation \setup_stage_operation + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164785$10227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164785$10227_Y + attribute \src "libresoc.v:172162.7-172162.20" + process $proc$libresoc.v:172162$10336 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164787$10229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164787$10229_Y + attribute \src "libresoc.v:172171.7-172171.25" + process $proc$libresoc.v:172171$10337 + assign { } { } + assign $1\div_by_zero[0:0] 1'0 + sync always + sync init + update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164789$10231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164789$10231_Y + attribute \src "libresoc.v:172178.7-172178.27" + process $proc$libresoc.v:172178$10338 + assign { } { } + assign $1\dive_abs_ov32[0:0] 1'0 + sync always + sync init + update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164791$10233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164791$10233_Y + attribute \src "libresoc.v:172185.7-172185.27" + process $proc$libresoc.v:172185$10339 + assign { } { } + assign $1\dive_abs_ov64[0:0] 1'0 + sync always + sync init + update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164792$10234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164792$10234_Y + attribute \src "libresoc.v:172192.15-172192.63" + process $proc$libresoc.v:172192$10340 + assign { } { } + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend $1\dividend[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164794$10236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164794$10236_Y - end - connect \$7 $not$libresoc.v:164779$10221_Y - connect \$12 $reduce_or$libresoc.v:164780$10222_Y - connect \$11 $not$libresoc.v:164781$10223_Y - connect \$16 $reduce_or$libresoc.v:164782$10224_Y - connect \$15 $not$libresoc.v:164783$10225_Y - connect \$1 $not$libresoc.v:164784$10226_Y - connect \$20 $reduce_or$libresoc.v:164785$10227_Y - connect \$19 $not$libresoc.v:164786$10228_Y - connect \$24 $reduce_or$libresoc.v:164787$10229_Y - connect \$23 $not$libresoc.v:164788$10230_Y - connect \$28 $reduce_or$libresoc.v:164789$10231_Y - connect \$27 $not$libresoc.v:164790$10232_Y - connect \$31 $reduce_or$libresoc.v:164791$10233_Y - connect \$4 $reduce_or$libresoc.v:164792$10234_Y - connect \$3 $not$libresoc.v:164793$10235_Y - connect \$8 $reduce_or$libresoc.v:164794$10236_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164810.1-164894.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$159 - attribute \src "libresoc.v:164867.17-164867.91" - wire $not$libresoc.v:164867$10237_Y - attribute \src "libresoc.v:164869.18-164869.93" - wire $not$libresoc.v:164869$10239_Y - attribute \src "libresoc.v:164871.18-164871.93" - wire $not$libresoc.v:164871$10241_Y - attribute \src "libresoc.v:164872.17-164872.138" - wire width 8 $not$libresoc.v:164872$10242_Y - attribute \src "libresoc.v:164874.18-164874.93" - wire $not$libresoc.v:164874$10244_Y - attribute \src "libresoc.v:164876.18-164876.93" - wire $not$libresoc.v:164876$10246_Y - attribute \src "libresoc.v:164878.18-164878.93" - wire $not$libresoc.v:164878$10248_Y - attribute \src "libresoc.v:164881.17-164881.91" - wire $not$libresoc.v:164881$10251_Y - attribute \src "libresoc.v:164868.18-164868.116" - wire $reduce_or$libresoc.v:164868$10238_Y - attribute \src "libresoc.v:164870.18-164870.122" - wire $reduce_or$libresoc.v:164870$10240_Y - attribute \src "libresoc.v:164873.18-164873.128" - wire $reduce_or$libresoc.v:164873$10243_Y - attribute \src "libresoc.v:164875.18-164875.134" - wire $reduce_or$libresoc.v:164875$10245_Y - attribute \src "libresoc.v:164877.18-164877.140" - wire $reduce_or$libresoc.v:164877$10247_Y - attribute \src "libresoc.v:164879.18-164879.90" - wire $reduce_or$libresoc.v:164879$10249_Y - attribute \src "libresoc.v:164880.17-164880.103" - wire $reduce_or$libresoc.v:164880$10250_Y - attribute \src "libresoc.v:164882.17-164882.109" - wire $reduce_or$libresoc.v:164882$10252_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164867$10237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164867$10237_Y + attribute \src "libresoc.v:172199.7-172199.26" + process $proc$libresoc.v:172199$10341 + assign { } { } + assign $1\dividend_neg[0:0] 1'0 + sync always + sync init + update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164869$10239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164869$10239_Y + attribute \src "libresoc.v:172206.7-172206.25" + process $proc$libresoc.v:172206$10342 + assign { } { } + assign $1\divisor_neg[0:0] 1'0 + sync always + sync init + update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164871$10241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164871$10241_Y + attribute \src "libresoc.v:172213.14-172213.53" + process $proc$libresoc.v:172213$10343 + assign { } { } + assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164872$10242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164872$10242_Y + attribute \src "libresoc.v:172496.13-172496.40" + process $proc$libresoc.v:172496$10344 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164874$10244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164874$10244_Y + attribute \src "libresoc.v:172520.14-172520.44" + process $proc$libresoc.v:172520$10345 + assign { } { } + assign $1\logical_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164876$10246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164876$10246_Y + attribute \src "libresoc.v:172559.14-172559.63" + process $proc$libresoc.v:172559$10346 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164878$10248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164878$10248_Y + attribute \src "libresoc.v:172568.7-172568.38" + process $proc$libresoc.v:172568$10347 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164881$10251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164881$10251_Y + attribute \src "libresoc.v:172581.13-172581.43" + process $proc$libresoc.v:172581$10348 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164868$10238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164868$10238_Y + attribute \src "libresoc.v:172598.14-172598.38" + process $proc$libresoc.v:172598$10349 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164870$10240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164870$10240_Y + attribute \src "libresoc.v:172682.13-172682.42" + process $proc$libresoc.v:172682$10350 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164873$10243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164873$10243_Y + attribute \src "libresoc.v:172841.7-172841.35" + process $proc$libresoc.v:172841$10351 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164875$10245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164875$10245_Y + attribute \src "libresoc.v:172850.7-172850.36" + process $proc$libresoc.v:172850$10352 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164877$10247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164877$10247_Y + attribute \src "libresoc.v:172859.7-172859.34" + process $proc$libresoc.v:172859$10353 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164879$10249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164879$10249_Y + attribute \src "libresoc.v:172868.7-172868.35" + process $proc$libresoc.v:172868$10354 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164880$10250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164880$10250_Y + attribute \src "libresoc.v:172877.7-172877.32" + process $proc$libresoc.v:172877$10355 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164882$10252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164882$10252_Y - end - connect \$7 $not$libresoc.v:164867$10237_Y - connect \$12 $reduce_or$libresoc.v:164868$10238_Y - connect \$11 $not$libresoc.v:164869$10239_Y - connect \$16 $reduce_or$libresoc.v:164870$10240_Y - connect \$15 $not$libresoc.v:164871$10241_Y - connect \$1 $not$libresoc.v:164872$10242_Y - connect \$20 $reduce_or$libresoc.v:164873$10243_Y - connect \$19 $not$libresoc.v:164874$10244_Y - connect \$24 $reduce_or$libresoc.v:164875$10245_Y - connect \$23 $not$libresoc.v:164876$10246_Y - connect \$28 $reduce_or$libresoc.v:164877$10247_Y - connect \$27 $not$libresoc.v:164878$10248_Y - connect \$31 $reduce_or$libresoc.v:164879$10249_Y - connect \$4 $reduce_or$libresoc.v:164880$10250_Y - connect \$3 $not$libresoc.v:164881$10251_Y - connect \$8 $reduce_or$libresoc.v:164882$10252_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164898.1-164982.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$161 - attribute \src "libresoc.v:164955.17-164955.91" - wire $not$libresoc.v:164955$10253_Y - attribute \src "libresoc.v:164957.18-164957.93" - wire $not$libresoc.v:164957$10255_Y - attribute \src "libresoc.v:164959.18-164959.93" - wire $not$libresoc.v:164959$10257_Y - attribute \src "libresoc.v:164960.17-164960.138" - wire width 8 $not$libresoc.v:164960$10258_Y - attribute \src "libresoc.v:164962.18-164962.93" - wire $not$libresoc.v:164962$10260_Y - attribute \src "libresoc.v:164964.18-164964.93" - wire $not$libresoc.v:164964$10262_Y - attribute \src "libresoc.v:164966.18-164966.93" - wire $not$libresoc.v:164966$10264_Y - attribute \src "libresoc.v:164969.17-164969.91" - wire $not$libresoc.v:164969$10267_Y - attribute \src "libresoc.v:164956.18-164956.116" - wire $reduce_or$libresoc.v:164956$10254_Y - attribute \src "libresoc.v:164958.18-164958.122" - wire $reduce_or$libresoc.v:164958$10256_Y - attribute \src "libresoc.v:164961.18-164961.128" - wire $reduce_or$libresoc.v:164961$10259_Y - attribute \src "libresoc.v:164963.18-164963.134" - wire $reduce_or$libresoc.v:164963$10261_Y - attribute \src "libresoc.v:164965.18-164965.140" - wire $reduce_or$libresoc.v:164965$10263_Y - attribute \src "libresoc.v:164967.18-164967.90" - wire $reduce_or$libresoc.v:164967$10265_Y - attribute \src "libresoc.v:164968.17-164968.103" - wire $reduce_or$libresoc.v:164968$10266_Y - attribute \src "libresoc.v:164970.17-164970.109" - wire $reduce_or$libresoc.v:164970$10268_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164955$10253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164955$10253_Y + attribute \src "libresoc.v:172886.7-172886.32" + process $proc$libresoc.v:172886$10356 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164957$10255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164957$10255_Y + attribute \src "libresoc.v:172895.7-172895.38" + process $proc$libresoc.v:172895$10357 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164959$10257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164959$10257_Y + attribute \src "libresoc.v:172904.7-172904.32" + process $proc$libresoc.v:172904$10358 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164960$10258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164960$10258_Y + attribute \src "libresoc.v:172913.7-172913.32" + process $proc$libresoc.v:172913$10359 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164962$10260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164962$10260_Y + attribute \src "libresoc.v:172922.7-172922.35" + process $proc$libresoc.v:172922$10360 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164964$10262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164964$10262_Y + attribute \src "libresoc.v:172931.7-172931.32" + process $proc$libresoc.v:172931$10361 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164966$10264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164966$10264_Y + attribute \src "libresoc.v:172940.13-172940.25" + process $proc$libresoc.v:172940$10362 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164969$10267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164969$10267_Y + attribute \src "libresoc.v:172955.13-172955.29" + process $proc$libresoc.v:172955$10363 + assign { } { } + assign $1\operation[1:0] 2'00 + sync always + sync init + update \operation $1\operation[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164956$10254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164956$10254_Y + attribute \src "libresoc.v:172969.7-172969.20" + process $proc$libresoc.v:172969$10364 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164958$10256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164958$10256_Y + attribute \src "libresoc.v:172974.14-172974.39" + process $proc$libresoc.v:172974$10365 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164961$10259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164961$10259_Y + attribute \src "libresoc.v:172985.14-172985.39" + process $proc$libresoc.v:172985$10366 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164963$10261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164963$10261_Y + attribute \src "libresoc.v:173284.7-173284.20" + process $proc$libresoc.v:173284$10367 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164965$10263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164965$10263_Y + attribute \src "libresoc.v:173292.3-173293.35" + process $proc$libresoc.v:173292$10222 + assign { } { } + assign $0\operation[1:0] \operation$next + sync posedge \coresync_clk + update \operation $0\operation[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164967$10265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164967$10265_Y + attribute \src "libresoc.v:173294.3-173295.49" + process $proc$libresoc.v:173294$10223 + assign { } { } + assign $0\divisor_radicand[63:0] \divisor_radicand$next + sync posedge \coresync_clk + update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164968$10266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164968$10266_Y + attribute \src "libresoc.v:173296.3-173297.33" + process $proc$libresoc.v:173296$10224 + assign { } { } + assign $0\dividend[127:0] \dividend$next + sync posedge \coresync_clk + update \dividend $0\dividend[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164970$10268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164970$10268_Y - end - connect \$7 $not$libresoc.v:164955$10253_Y - connect \$12 $reduce_or$libresoc.v:164956$10254_Y - connect \$11 $not$libresoc.v:164957$10255_Y - connect \$16 $reduce_or$libresoc.v:164958$10256_Y - connect \$15 $not$libresoc.v:164959$10257_Y - connect \$1 $not$libresoc.v:164960$10258_Y - connect \$20 $reduce_or$libresoc.v:164961$10259_Y - connect \$19 $not$libresoc.v:164962$10260_Y - connect \$24 $reduce_or$libresoc.v:164963$10261_Y - connect \$23 $not$libresoc.v:164964$10262_Y - connect \$28 $reduce_or$libresoc.v:164965$10263_Y - connect \$27 $not$libresoc.v:164966$10264_Y - connect \$31 $reduce_or$libresoc.v:164967$10265_Y - connect \$4 $reduce_or$libresoc.v:164968$10266_Y - connect \$3 $not$libresoc.v:164969$10267_Y - connect \$8 $reduce_or$libresoc.v:164970$10268_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164986.1-165070.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$168 - attribute \src "libresoc.v:165043.17-165043.91" - wire $not$libresoc.v:165043$10269_Y - attribute \src "libresoc.v:165045.18-165045.93" - wire $not$libresoc.v:165045$10271_Y - attribute \src "libresoc.v:165047.18-165047.93" - wire $not$libresoc.v:165047$10273_Y - attribute \src "libresoc.v:165048.17-165048.138" - wire width 8 $not$libresoc.v:165048$10274_Y - attribute \src "libresoc.v:165050.18-165050.93" - wire $not$libresoc.v:165050$10276_Y - attribute \src "libresoc.v:165052.18-165052.93" - wire $not$libresoc.v:165052$10278_Y - attribute \src "libresoc.v:165054.18-165054.93" - wire $not$libresoc.v:165054$10280_Y - attribute \src "libresoc.v:165057.17-165057.91" - wire $not$libresoc.v:165057$10283_Y - attribute \src "libresoc.v:165044.18-165044.116" - wire $reduce_or$libresoc.v:165044$10270_Y - attribute \src "libresoc.v:165046.18-165046.122" - wire $reduce_or$libresoc.v:165046$10272_Y - attribute \src "libresoc.v:165049.18-165049.128" - wire $reduce_or$libresoc.v:165049$10275_Y - attribute \src "libresoc.v:165051.18-165051.134" - wire $reduce_or$libresoc.v:165051$10277_Y - attribute \src "libresoc.v:165053.18-165053.140" - wire $reduce_or$libresoc.v:165053$10279_Y - attribute \src "libresoc.v:165055.18-165055.90" - wire $reduce_or$libresoc.v:165055$10281_Y - attribute \src "libresoc.v:165056.17-165056.103" - wire $reduce_or$libresoc.v:165056$10282_Y - attribute \src "libresoc.v:165058.17-165058.109" - wire $reduce_or$libresoc.v:165058$10284_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165043$10269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165043$10269_Y + attribute \src "libresoc.v:173298.3-173299.39" + process $proc$libresoc.v:173298$10225 + assign { } { } + assign $0\div_by_zero[0:0] \div_by_zero$next + sync posedge \coresync_clk + update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165045$10271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165045$10271_Y + attribute \src "libresoc.v:173300.3-173301.43" + process $proc$libresoc.v:173300$10226 + assign { } { } + assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next + sync posedge \coresync_clk + update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165047$10273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165047$10273_Y + attribute \src "libresoc.v:173302.3-173303.43" + process $proc$libresoc.v:173302$10227 + assign { } { } + assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next + sync posedge \coresync_clk + update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165048$10274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165048$10274_Y + attribute \src "libresoc.v:173304.3-173305.41" + process $proc$libresoc.v:173304$10228 + assign { } { } + assign $0\dividend_neg[0:0] \dividend_neg$next + sync posedge \coresync_clk + update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165050$10276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165050$10276_Y + attribute \src "libresoc.v:173306.3-173307.39" + process $proc$libresoc.v:173306$10229 + assign { } { } + assign $0\divisor_neg[0:0] \divisor_neg$next + sync posedge \coresync_clk + update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165052$10278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165052$10278_Y + attribute \src "libresoc.v:173308.3-173309.29" + process $proc$libresoc.v:173308$10230 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165054$10280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165054$10280_Y + attribute \src "libresoc.v:173310.3-173311.21" + process $proc$libresoc.v:173310$10231 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165057$10283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165057$10283_Y + attribute \src "libresoc.v:173312.3-173313.21" + process $proc$libresoc.v:173312$10232 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165044$10270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165044$10270_Y + attribute \src "libresoc.v:173314.3-173315.59" + process $proc$libresoc.v:173314$10233 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165046$10272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165046$10272_Y + attribute \src "libresoc.v:173316.3-173317.55" + process $proc$libresoc.v:173316$10234 + assign { } { } + assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165049$10275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165049$10275_Y + attribute \src "libresoc.v:173318.3-173319.69" + process $proc$libresoc.v:173318$10235 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165051$10277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165051$10277_Y + attribute \src "libresoc.v:173320.3-173321.65" + process $proc$libresoc.v:173320$10236 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165053$10279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165053$10279_Y + attribute \src "libresoc.v:173322.3-173323.53" + process $proc$libresoc.v:173322$10237 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165055$10281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165055$10281_Y + attribute \src "libresoc.v:173324.3-173325.53" + process $proc$libresoc.v:173324$10238 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165056$10282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165056$10282_Y + attribute \src "libresoc.v:173326.3-173327.53" + process $proc$libresoc.v:173326$10239 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165058$10284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165058$10284_Y - end - connect \$7 $not$libresoc.v:165043$10269_Y - connect \$12 $reduce_or$libresoc.v:165044$10270_Y - connect \$11 $not$libresoc.v:165045$10271_Y - connect \$16 $reduce_or$libresoc.v:165046$10272_Y - connect \$15 $not$libresoc.v:165047$10273_Y - connect \$1 $not$libresoc.v:165048$10274_Y - connect \$20 $reduce_or$libresoc.v:165049$10275_Y - connect \$19 $not$libresoc.v:165050$10276_Y - connect \$24 $reduce_or$libresoc.v:165051$10277_Y - connect \$23 $not$libresoc.v:165052$10278_Y - connect \$28 $reduce_or$libresoc.v:165053$10279_Y - connect \$27 $not$libresoc.v:165054$10280_Y - connect \$31 $reduce_or$libresoc.v:165055$10281_Y - connect \$4 $reduce_or$libresoc.v:165056$10282_Y - connect \$3 $not$libresoc.v:165057$10283_Y - connect \$8 $reduce_or$libresoc.v:165058$10284_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165074.1-165158.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$170 - attribute \src "libresoc.v:165131.17-165131.91" - wire $not$libresoc.v:165131$10285_Y - attribute \src "libresoc.v:165133.18-165133.93" - wire $not$libresoc.v:165133$10287_Y - attribute \src "libresoc.v:165135.18-165135.93" - wire $not$libresoc.v:165135$10289_Y - attribute \src "libresoc.v:165136.17-165136.138" - wire width 8 $not$libresoc.v:165136$10290_Y - attribute \src "libresoc.v:165138.18-165138.93" - wire $not$libresoc.v:165138$10292_Y - attribute \src "libresoc.v:165140.18-165140.93" - wire $not$libresoc.v:165140$10294_Y - attribute \src "libresoc.v:165142.18-165142.93" - wire $not$libresoc.v:165142$10296_Y - attribute \src "libresoc.v:165145.17-165145.91" - wire $not$libresoc.v:165145$10299_Y - attribute \src "libresoc.v:165132.18-165132.116" - wire $reduce_or$libresoc.v:165132$10286_Y - attribute \src "libresoc.v:165134.18-165134.122" - wire $reduce_or$libresoc.v:165134$10288_Y - attribute \src "libresoc.v:165137.18-165137.128" - wire $reduce_or$libresoc.v:165137$10291_Y - attribute \src "libresoc.v:165139.18-165139.134" - wire $reduce_or$libresoc.v:165139$10293_Y - attribute \src "libresoc.v:165141.18-165141.140" - wire $reduce_or$libresoc.v:165141$10295_Y - attribute \src "libresoc.v:165143.18-165143.90" - wire $reduce_or$libresoc.v:165143$10297_Y - attribute \src "libresoc.v:165144.17-165144.103" - wire $reduce_or$libresoc.v:165144$10298_Y - attribute \src "libresoc.v:165146.17-165146.109" - wire $reduce_or$libresoc.v:165146$10300_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165131$10285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165131$10285_Y + attribute \src "libresoc.v:173328.3-173329.53" + process $proc$libresoc.v:173328$10240 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165133$10287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165133$10287_Y + attribute \src "libresoc.v:173330.3-173331.59" + process $proc$libresoc.v:173330$10241 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165135$10289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165135$10289_Y + attribute \src "libresoc.v:173332.3-173333.53" + process $proc$libresoc.v:173332$10242 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165136$10290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165136$10290_Y + attribute \src "libresoc.v:173334.3-173335.63" + process $proc$libresoc.v:173334$10243 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165138$10292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165138$10292_Y + attribute \src "libresoc.v:173336.3-173337.61" + process $proc$libresoc.v:173336$10244 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165140$10294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165140$10294_Y + attribute \src "libresoc.v:173338.3-173339.59" + process $proc$libresoc.v:173338$10245 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165142$10296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165142$10296_Y + attribute \src "libresoc.v:173340.3-173341.65" + process $proc$libresoc.v:173340$10246 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165145$10299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165145$10299_Y + attribute \src "libresoc.v:173342.3-173343.57" + process $proc$libresoc.v:173342$10247 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165132$10286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165132$10286_Y + attribute \src "libresoc.v:173344.3-173345.59" + process $proc$libresoc.v:173344$10248 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165134$10288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165134$10288_Y + attribute \src "libresoc.v:173346.3-173347.57" + process $proc$libresoc.v:173346$10249 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165137$10291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165137$10291_Y + attribute \src "libresoc.v:173348.3-173349.49" + process $proc$libresoc.v:173348$10250 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165139$10293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165139$10293_Y + attribute \src "libresoc.v:173350.3-173351.27" + process $proc$libresoc.v:173350$10251 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165141$10295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165141$10295_Y + attribute \src "libresoc.v:173352.3-173353.29" + process $proc$libresoc.v:173352$10252 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165143$10297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165143$10297_Y + attribute \src "libresoc.v:173460.3-173472.6" + process $proc$libresoc.v:173460$10253 + assign { } { } + assign { } { } + assign $0\divisor_neg$next[0:0]$10254 $1\divisor_neg$next[0:0]$10255 + attribute \src "libresoc.v:173461.5-173461.29" + switch \initial + attribute \src "libresoc.v:173461.9-173461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_neg$next[0:0]$10255 \divisor_neg$92 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_neg$next[0:0]$10255 \divisor_neg$92 + case + assign $1\divisor_neg$next[0:0]$10255 \divisor_neg + end + sync always + update \divisor_neg$next $0\divisor_neg$next[0:0]$10254 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165144$10298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165144$10298_Y + attribute \src "libresoc.v:173473.3-173485.6" + process $proc$libresoc.v:173473$10256 + assign { } { } + assign { } { } + assign $0\dividend_neg$next[0:0]$10257 $1\dividend_neg$next[0:0]$10258 + attribute \src "libresoc.v:173474.5-173474.29" + switch \initial + attribute \src "libresoc.v:173474.9-173474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend_neg$next[0:0]$10258 \dividend_neg$93 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend_neg$next[0:0]$10258 \dividend_neg$93 + case + assign $1\dividend_neg$next[0:0]$10258 \dividend_neg + end + sync always + update \dividend_neg$next $0\dividend_neg$next[0:0]$10257 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165146$10300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165146$10300_Y - end - connect \$7 $not$libresoc.v:165131$10285_Y - connect \$12 $reduce_or$libresoc.v:165132$10286_Y - connect \$11 $not$libresoc.v:165133$10287_Y - connect \$16 $reduce_or$libresoc.v:165134$10288_Y - connect \$15 $not$libresoc.v:165135$10289_Y - connect \$1 $not$libresoc.v:165136$10290_Y - connect \$20 $reduce_or$libresoc.v:165137$10291_Y - connect \$19 $not$libresoc.v:165138$10292_Y - connect \$24 $reduce_or$libresoc.v:165139$10293_Y - connect \$23 $not$libresoc.v:165140$10294_Y - connect \$28 $reduce_or$libresoc.v:165141$10295_Y - connect \$27 $not$libresoc.v:165142$10296_Y - connect \$31 $reduce_or$libresoc.v:165143$10297_Y - connect \$4 $reduce_or$libresoc.v:165144$10298_Y - connect \$3 $not$libresoc.v:165145$10299_Y - connect \$8 $reduce_or$libresoc.v:165146$10300_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + attribute \src "libresoc.v:173486.3-173498.6" + process $proc$libresoc.v:173486$10259 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$next[0:0]$10260 $1\dive_abs_ov32$next[0:0]$10261 + attribute \src "libresoc.v:173487.5-173487.29" + switch \initial + attribute \src "libresoc.v:173487.9-173487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32$94 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32$94 + case + assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32 + end + sync always + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10260 + end + attribute \src "libresoc.v:173499.3-173511.6" + process $proc$libresoc.v:173499$10262 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$next[0:0]$10263 $1\dive_abs_ov64$next[0:0]$10264 + attribute \src "libresoc.v:173500.5-173500.29" + switch \initial + attribute \src "libresoc.v:173500.9-173500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64$95 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64$95 + case + assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64 + end + sync always + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10263 + end + attribute \src "libresoc.v:173512.3-173524.6" + process $proc$libresoc.v:173512$10265 + assign { } { } + assign { } { } + assign $0\div_by_zero$next[0:0]$10266 $1\div_by_zero$next[0:0]$10267 + attribute \src "libresoc.v:173513.5-173513.29" + switch \initial + attribute \src "libresoc.v:173513.9-173513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\div_by_zero$next[0:0]$10267 \div_by_zero$96 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\div_by_zero$next[0:0]$10267 \div_by_zero$96 + case + assign $1\div_by_zero$next[0:0]$10267 \div_by_zero + end + sync always + update \div_by_zero$next $0\div_by_zero$next[0:0]$10266 + end + attribute \src "libresoc.v:173525.3-173537.6" + process $proc$libresoc.v:173525$10268 + assign { } { } + assign { } { } + assign $0\dividend$next[127:0]$10269 $1\dividend$next[127:0]$10270 + attribute \src "libresoc.v:173526.5-173526.29" + switch \initial + attribute \src "libresoc.v:173526.9-173526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend$next[127:0]$10270 \dividend$97 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend$next[127:0]$10270 \dividend$97 + case + assign $1\dividend$next[127:0]$10270 \dividend + end + sync always + update \dividend$next $0\dividend$next[127:0]$10269 + end + attribute \src "libresoc.v:173538.3-173550.6" + process $proc$libresoc.v:173538$10271 + assign { } { } + assign { } { } + assign $0\divisor_radicand$next[63:0]$10272 $1\divisor_radicand$next[63:0]$10273 + attribute \src "libresoc.v:173539.5-173539.29" + switch \initial + attribute \src "libresoc.v:173539.9-173539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand$98 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand$98 + case + assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand + end + sync always + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10272 + end + attribute \src "libresoc.v:173551.3-173563.6" + process $proc$libresoc.v:173551$10274 + assign { } { } + assign { } { } + assign $0\operation$next[1:0]$10275 $1\operation$next[1:0]$10276 + attribute \src "libresoc.v:173552.5-173552.29" + switch \initial + attribute \src "libresoc.v:173552.9-173552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\operation$next[1:0]$10276 \operation$99 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\operation$next[1:0]$10276 \operation$99 + case + assign $1\operation$next[1:0]$10276 \operation + end + sync always + update \operation$next $0\operation$next[1:0]$10275 + end + attribute \src "libresoc.v:173564.3-173581.6" + process $proc$libresoc.v:173564$10277 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$10278 $2\r_busy$next[0:0]$10280 + attribute \src "libresoc.v:173565.5-173565.29" + switch \initial + attribute \src "libresoc.v:173565.9-173565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$10279 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$10279 1'0 + case + assign $1\r_busy$next[0:0]$10279 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$10280 1'0 + case + assign $2\r_busy$next[0:0]$10280 $1\r_busy$next[0:0]$10279 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$10278 + end + attribute \src "libresoc.v:173582.3-173594.6" + process $proc$libresoc.v:173582$10281 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$10282 $1\muxid$next[1:0]$10283 + attribute \src "libresoc.v:173583.5-173583.29" + switch \initial + attribute \src "libresoc.v:173583.9-173583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$10283 \muxid$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$10283 \muxid$68 + case + assign $1\muxid$next[1:0]$10283 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$10282 + end + attribute \src "libresoc.v:173595.3-173636.6" + process $proc$libresoc.v:173595$10284 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$10285 $1\logical_op__data_len$next[3:0]$10303 + assign $0\logical_op__fn_unit$next[13:0]$10286 $1\logical_op__fn_unit$next[13:0]$10304 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$10289 $1\logical_op__input_carry$next[1:0]$10307 + assign $0\logical_op__insn$next[31:0]$10290 $1\logical_op__insn$next[31:0]$10308 + assign $0\logical_op__insn_type$next[6:0]$10291 $1\logical_op__insn_type$next[6:0]$10309 + assign $0\logical_op__invert_in$next[0:0]$10292 $1\logical_op__invert_in$next[0:0]$10310 + assign $0\logical_op__invert_out$next[0:0]$10293 $1\logical_op__invert_out$next[0:0]$10311 + assign $0\logical_op__is_32bit$next[0:0]$10294 $1\logical_op__is_32bit$next[0:0]$10312 + assign $0\logical_op__is_signed$next[0:0]$10295 $1\logical_op__is_signed$next[0:0]$10313 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$10298 $1\logical_op__output_carry$next[0:0]$10316 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$10301 $1\logical_op__write_cr0$next[0:0]$10319 + assign $0\logical_op__zero_a$next[0:0]$10302 $1\logical_op__zero_a$next[0:0]$10320 + assign $0\logical_op__imm_data__data$next[63:0]$10287 $2\logical_op__imm_data__data$next[63:0]$10321 + assign $0\logical_op__imm_data__ok$next[0:0]$10288 $2\logical_op__imm_data__ok$next[0:0]$10322 + assign $0\logical_op__oe__oe$next[0:0]$10296 $2\logical_op__oe__oe$next[0:0]$10323 + assign $0\logical_op__oe__ok$next[0:0]$10297 $2\logical_op__oe__ok$next[0:0]$10324 + assign $0\logical_op__rc__ok$next[0:0]$10299 $2\logical_op__rc__ok$next[0:0]$10325 + assign $0\logical_op__rc__rc$next[0:0]$10300 $2\logical_op__rc__rc$next[0:0]$10326 + attribute \src "libresoc.v:173596.5-173596.29" + switch \initial + attribute \src "libresoc.v:173596.9-173596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$10308 $1\logical_op__data_len$next[3:0]$10303 $1\logical_op__is_signed$next[0:0]$10313 $1\logical_op__is_32bit$next[0:0]$10312 $1\logical_op__output_carry$next[0:0]$10316 $1\logical_op__write_cr0$next[0:0]$10319 $1\logical_op__invert_out$next[0:0]$10311 $1\logical_op__input_carry$next[1:0]$10307 $1\logical_op__zero_a$next[0:0]$10320 $1\logical_op__invert_in$next[0:0]$10310 $1\logical_op__oe__ok$next[0:0]$10315 $1\logical_op__oe__oe$next[0:0]$10314 $1\logical_op__rc__ok$next[0:0]$10317 $1\logical_op__rc__rc$next[0:0]$10318 $1\logical_op__imm_data__ok$next[0:0]$10306 $1\logical_op__imm_data__data$next[63:0]$10305 $1\logical_op__fn_unit$next[13:0]$10304 $1\logical_op__insn_type$next[6:0]$10309 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$10308 $1\logical_op__data_len$next[3:0]$10303 $1\logical_op__is_signed$next[0:0]$10313 $1\logical_op__is_32bit$next[0:0]$10312 $1\logical_op__output_carry$next[0:0]$10316 $1\logical_op__write_cr0$next[0:0]$10319 $1\logical_op__invert_out$next[0:0]$10311 $1\logical_op__input_carry$next[1:0]$10307 $1\logical_op__zero_a$next[0:0]$10320 $1\logical_op__invert_in$next[0:0]$10310 $1\logical_op__oe__ok$next[0:0]$10315 $1\logical_op__oe__oe$next[0:0]$10314 $1\logical_op__rc__ok$next[0:0]$10317 $1\logical_op__rc__rc$next[0:0]$10318 $1\logical_op__imm_data__ok$next[0:0]$10306 $1\logical_op__imm_data__data$next[63:0]$10305 $1\logical_op__fn_unit$next[13:0]$10304 $1\logical_op__insn_type$next[6:0]$10309 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + case + assign $1\logical_op__data_len$next[3:0]$10303 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$10304 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10305 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10306 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10307 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10308 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10309 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10310 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10311 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10312 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10313 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10314 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10315 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10316 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10317 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10318 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10319 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10320 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$10321 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10322 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10326 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10325 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10323 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10324 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$10321 $1\logical_op__imm_data__data$next[63:0]$10305 + assign $2\logical_op__imm_data__ok$next[0:0]$10322 $1\logical_op__imm_data__ok$next[0:0]$10306 + assign $2\logical_op__oe__oe$next[0:0]$10323 $1\logical_op__oe__oe$next[0:0]$10314 + assign $2\logical_op__oe__ok$next[0:0]$10324 $1\logical_op__oe__ok$next[0:0]$10315 + assign $2\logical_op__rc__ok$next[0:0]$10325 $1\logical_op__rc__ok$next[0:0]$10317 + assign $2\logical_op__rc__rc$next[0:0]$10326 $1\logical_op__rc__rc$next[0:0]$10318 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10285 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10286 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10287 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10288 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10289 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10290 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10291 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10292 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10293 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10294 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10295 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10296 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10297 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10298 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10299 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10300 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10301 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10302 + end + attribute \src "libresoc.v:173637.3-173649.6" + process $proc$libresoc.v:173637$10327 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$10328 $1\ra$next[63:0]$10329 + attribute \src "libresoc.v:173638.5-173638.29" + switch \initial + attribute \src "libresoc.v:173638.9-173638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$10329 \ra$87 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$10329 \ra$87 + case + assign $1\ra$next[63:0]$10329 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$10328 + end + attribute \src "libresoc.v:173650.3-173662.6" + process $proc$libresoc.v:173650$10330 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$10331 $1\rb$next[63:0]$10332 + attribute \src "libresoc.v:173651.5-173651.29" + switch \initial + attribute \src "libresoc.v:173651.9-173651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$10332 \rb$89 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$10332 \rb$89 + case + assign $1\rb$next[63:0]$10332 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$10331 + end + attribute \src "libresoc.v:173663.3-173675.6" + process $proc$libresoc.v:173663$10333 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$10334 $1\xer_so$next[0:0]$10335 + attribute \src "libresoc.v:173664.5-173664.29" + switch \initial + attribute \src "libresoc.v:173664.9-173664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$10335 \xer_so$91 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$10335 \xer_so$91 + case + assign $1\xer_so$next[0:0]$10335 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$10334 + end + connect \$66 $and$libresoc.v:173291$10221_Y + connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \operation$99 \setup_stage_operation + connect \divisor_radicand$98 \setup_stage_divisor_radicand + connect \dividend$97 \setup_stage_dividend + connect \div_by_zero$96 \setup_stage_div_by_zero + connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 + connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 + connect \dividend_neg$93 \setup_stage_dividend_neg + connect \divisor_neg$92 \setup_stage_divisor_neg + connect \xer_so$91 \setup_stage_xer_so$64 + connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 + connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + connect \muxid$68 \setup_stage_muxid$45 + connect \p_valid_i_p_ready_o \$66 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$65 \p_valid_i + connect \setup_stage_xer_so \input_xer_so$44 + connect \setup_stage_rb \input_rb$43 + connect \setup_stage_ra \input_ra$42 + connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + connect \setup_stage_muxid \input_muxid$23 + connect \input_xer_so \xer_so$22 + connect \input_rb \rb$21 + connect \input_ra \ra$20 + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:165162.1-165246.10" +attribute \src "libresoc.v:173710.1-173754.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.pll" attribute \generator "nMigen" -module \ppick$175 - attribute \src "libresoc.v:165219.17-165219.91" - wire $not$libresoc.v:165219$10301_Y - attribute \src "libresoc.v:165221.18-165221.93" - wire $not$libresoc.v:165221$10303_Y - attribute \src "libresoc.v:165223.18-165223.93" - wire $not$libresoc.v:165223$10305_Y - attribute \src "libresoc.v:165224.17-165224.138" - wire width 8 $not$libresoc.v:165224$10306_Y - attribute \src "libresoc.v:165226.18-165226.93" - wire $not$libresoc.v:165226$10308_Y - attribute \src "libresoc.v:165228.18-165228.93" - wire $not$libresoc.v:165228$10310_Y - attribute \src "libresoc.v:165230.18-165230.93" - wire $not$libresoc.v:165230$10312_Y - attribute \src "libresoc.v:165233.17-165233.91" - wire $not$libresoc.v:165233$10315_Y - attribute \src "libresoc.v:165220.18-165220.116" - wire $reduce_or$libresoc.v:165220$10302_Y - attribute \src "libresoc.v:165222.18-165222.122" - wire $reduce_or$libresoc.v:165222$10304_Y - attribute \src "libresoc.v:165225.18-165225.128" - wire $reduce_or$libresoc.v:165225$10307_Y - attribute \src "libresoc.v:165227.18-165227.134" - wire $reduce_or$libresoc.v:165227$10309_Y - attribute \src "libresoc.v:165229.18-165229.140" - wire $reduce_or$libresoc.v:165229$10311_Y - attribute \src "libresoc.v:165231.18-165231.90" - wire $reduce_or$libresoc.v:165231$10313_Y - attribute \src "libresoc.v:165232.17-165232.103" - wire $reduce_or$libresoc.v:165232$10314_Y - attribute \src "libresoc.v:165234.17-165234.109" - wire $reduce_or$libresoc.v:165234$10316_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" +module \pll + attribute \src "libresoc.v:173711.7-173711.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173743.3-173752.6" + wire $0\pll_18_o[0:0] + attribute \src "libresoc.v:173733.3-173742.6" + wire $0\pll_lck_o[0:0] + attribute \src "libresoc.v:173743.3-173752.6" + wire $1\pll_18_o[0:0] + attribute \src "libresoc.v:173733.3-173742.6" + wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:173730.17-173730.105" + wire $eq$libresoc.v:173730$10368_Y + attribute \src "libresoc.v:173731.17-173731.105" + wire $eq$libresoc.v:173731$10369_Y + attribute \src "libresoc.v:173732.17-173732.98" + wire $not$libresoc.v:173732$10370_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165219$10301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165219$10301_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165221$10303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire output 5 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 3 \clk_sel_i + attribute \src "libresoc.v:173711.7-173711.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 2 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 4 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:173730$10368 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165221$10303_Y + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:173730$10368_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165223$10305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:173731$10369 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165223$10305_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165224$10306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165224$10306_Y + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:173731$10369_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165226$10308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + cell $not $not$libresoc.v:173732$10370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165226$10308_Y + connect \A \clk_24_i + connect \Y $not$libresoc.v:173732$10370_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165228$10310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165228$10310_Y + attribute \src "libresoc.v:173711.7-173711.20" + process $proc$libresoc.v:173711$10373 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165230$10312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165230$10312_Y + attribute \src "libresoc.v:173733.3-173742.6" + process $proc$libresoc.v:173733$10371 + assign { } { } + assign { } { } + assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] + attribute \src "libresoc.v:173734.5-173734.29" + switch \initial + attribute \src "libresoc.v:173734.9-173734.17" + case 1'1 + case + end + attribute \src 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64 input 3 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 input 1 \data_len + attribute \src "libresoc.v:173759.7-173759.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 output 2 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 6 \pop_6_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 6 \pop_6_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 7 \pop_7_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174171$10374 parameter \A_SIGNED 0 parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165220$10302_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165222$10304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165222$10304_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_2 } + connect \B { 2'00 \pop_2_3 } + connect \Y $add$libresoc.v:174171$10374_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165225$10307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174172$10375 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165225$10307_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_4 } + connect \B { 2'00 \pop_2_5 } + connect \Y $add$libresoc.v:174172$10375_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165227$10309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174173$10376 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165227$10309_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_6 } + connect \B { 2'00 \pop_2_7 } + connect \Y $add$libresoc.v:174173$10376_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165229$10311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174174$10377 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165229$10311_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_8 } + connect \B { 2'00 \pop_2_9 } + connect \Y $add$libresoc.v:174174$10377_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165231$10313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174175$10378 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165231$10313_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_10 } + connect \B { 2'00 \pop_2_11 } + connect \Y $add$libresoc.v:174175$10378_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165232$10314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174176$10379 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165232$10314_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_12 } + connect \B { 2'00 \pop_2_13 } + connect \Y $add$libresoc.v:174176$10379_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165234$10316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174177$10380 parameter \A_SIGNED 0 parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165234$10316_Y - end - connect \$7 $not$libresoc.v:165219$10301_Y - connect \$12 $reduce_or$libresoc.v:165220$10302_Y - connect \$11 $not$libresoc.v:165221$10303_Y - connect \$16 $reduce_or$libresoc.v:165222$10304_Y - connect \$15 $not$libresoc.v:165223$10305_Y - connect \$1 $not$libresoc.v:165224$10306_Y - connect \$20 $reduce_or$libresoc.v:165225$10307_Y - connect \$19 $not$libresoc.v:165226$10308_Y - connect \$24 $reduce_or$libresoc.v:165227$10309_Y - connect \$23 $not$libresoc.v:165228$10310_Y - connect \$28 $reduce_or$libresoc.v:165229$10311_Y - connect \$27 $not$libresoc.v:165230$10312_Y - connect \$31 $reduce_or$libresoc.v:165231$10313_Y - connect \$4 $reduce_or$libresoc.v:165232$10314_Y - connect \$3 $not$libresoc.v:165233$10315_Y - connect \$8 $reduce_or$libresoc.v:165234$10316_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165250.1-165334.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$177 - attribute \src "libresoc.v:165307.17-165307.91" - wire $not$libresoc.v:165307$10317_Y - attribute \src "libresoc.v:165309.18-165309.93" - wire $not$libresoc.v:165309$10319_Y - attribute \src "libresoc.v:165311.18-165311.93" - wire $not$libresoc.v:165311$10321_Y - attribute \src "libresoc.v:165312.17-165312.138" - wire width 8 $not$libresoc.v:165312$10322_Y - attribute \src "libresoc.v:165314.18-165314.93" - wire $not$libresoc.v:165314$10324_Y - attribute \src "libresoc.v:165316.18-165316.93" - wire $not$libresoc.v:165316$10326_Y - attribute \src "libresoc.v:165318.18-165318.93" - wire $not$libresoc.v:165318$10328_Y - attribute \src "libresoc.v:165321.17-165321.91" - wire $not$libresoc.v:165321$10331_Y - attribute \src "libresoc.v:165308.18-165308.116" - wire $reduce_or$libresoc.v:165308$10318_Y - attribute \src "libresoc.v:165310.18-165310.122" - wire $reduce_or$libresoc.v:165310$10320_Y - attribute \src "libresoc.v:165313.18-165313.128" - wire $reduce_or$libresoc.v:165313$10323_Y - attribute \src "libresoc.v:165315.18-165315.134" - wire $reduce_or$libresoc.v:165315$10325_Y - attribute \src "libresoc.v:165317.18-165317.140" - wire $reduce_or$libresoc.v:165317$10327_Y - attribute \src "libresoc.v:165319.18-165319.90" - wire $reduce_or$libresoc.v:165319$10329_Y - attribute \src "libresoc.v:165320.17-165320.103" - wire $reduce_or$libresoc.v:165320$10330_Y - attribute \src "libresoc.v:165322.17-165322.109" - wire $reduce_or$libresoc.v:165322$10332_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165307$10317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165307$10317_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165309$10319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165309$10319_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165311$10321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165311$10321_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165312$10322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165312$10322_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165314$10324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165314$10324_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [6] } + connect \B { 2'00 \a [7] } + connect \Y $add$libresoc.v:174177$10380_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165316$10326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174178$10381 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165316$10326_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_14 } + connect \B { 2'00 \pop_2_15 } + connect \Y $add$libresoc.v:174178$10381_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165318$10328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174179$10382 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165318$10328_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_16 } + connect \B { 2'00 \pop_2_17 } + connect \Y $add$libresoc.v:174179$10382_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165321$10331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174180$10383 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165321$10331_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_18 } + connect \B { 2'00 \pop_2_19 } + connect \Y $add$libresoc.v:174180$10383_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165308$10318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174181$10384 parameter \A_SIGNED 0 parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165308$10318_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_20 } + connect \B { 2'00 \pop_2_21 } + connect \Y $add$libresoc.v:174181$10384_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165310$10320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174182$10385 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165310$10320_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_22 } + connect \B { 2'00 \pop_2_23 } + connect \Y $add$libresoc.v:174182$10385_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165313$10323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174183$10386 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165313$10323_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_24 } + connect \B { 2'00 \pop_2_25 } + connect \Y $add$libresoc.v:174183$10386_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165315$10325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174184$10387 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165315$10325_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_26 } + connect \B { 2'00 \pop_2_27 } + connect \Y $add$libresoc.v:174184$10387_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165317$10327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174185$10388 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165317$10327_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_28 } + connect \B { 2'00 \pop_2_29 } + connect \Y $add$libresoc.v:174185$10388_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165319$10329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174186$10389 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165319$10329_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_30 } + connect \B { 2'00 \pop_2_31 } + connect \Y $add$libresoc.v:174186$10389_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165320$10330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174187$10390 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165320$10330_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_0 } + connect \B { 2'00 \pop_3_1 } + connect \Y $add$libresoc.v:174187$10390_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165322$10332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174188$10391 parameter \A_SIGNED 0 parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165322$10332_Y - end - connect \$7 $not$libresoc.v:165307$10317_Y - connect \$12 $reduce_or$libresoc.v:165308$10318_Y - connect \$11 $not$libresoc.v:165309$10319_Y - connect \$16 $reduce_or$libresoc.v:165310$10320_Y - connect \$15 $not$libresoc.v:165311$10321_Y - connect \$1 $not$libresoc.v:165312$10322_Y - connect \$20 $reduce_or$libresoc.v:165313$10323_Y - connect \$19 $not$libresoc.v:165314$10324_Y - connect \$24 $reduce_or$libresoc.v:165315$10325_Y - connect \$23 $not$libresoc.v:165316$10326_Y - connect \$28 $reduce_or$libresoc.v:165317$10327_Y - connect \$27 $not$libresoc.v:165318$10328_Y - connect \$31 $reduce_or$libresoc.v:165319$10329_Y - connect \$4 $reduce_or$libresoc.v:165320$10330_Y - connect \$3 $not$libresoc.v:165321$10331_Y - connect \$8 $reduce_or$libresoc.v:165322$10332_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165338.1-165422.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$184 - attribute \src "libresoc.v:165395.17-165395.91" - wire $not$libresoc.v:165395$10333_Y - attribute \src "libresoc.v:165397.18-165397.93" - wire $not$libresoc.v:165397$10335_Y - attribute \src "libresoc.v:165399.18-165399.93" - wire $not$libresoc.v:165399$10337_Y - attribute \src "libresoc.v:165400.17-165400.138" - wire width 8 $not$libresoc.v:165400$10338_Y - attribute \src "libresoc.v:165402.18-165402.93" - wire $not$libresoc.v:165402$10340_Y - attribute \src "libresoc.v:165404.18-165404.93" - wire $not$libresoc.v:165404$10342_Y - attribute \src "libresoc.v:165406.18-165406.93" - wire $not$libresoc.v:165406$10344_Y - attribute \src "libresoc.v:165409.17-165409.91" - wire $not$libresoc.v:165409$10347_Y - attribute \src "libresoc.v:165396.18-165396.116" - wire $reduce_or$libresoc.v:165396$10334_Y - attribute \src "libresoc.v:165398.18-165398.122" - wire $reduce_or$libresoc.v:165398$10336_Y - attribute \src "libresoc.v:165401.18-165401.128" - wire $reduce_or$libresoc.v:165401$10339_Y - attribute \src "libresoc.v:165403.18-165403.134" - wire $reduce_or$libresoc.v:165403$10341_Y - attribute \src "libresoc.v:165405.18-165405.140" - wire $reduce_or$libresoc.v:165405$10343_Y - attribute \src "libresoc.v:165407.18-165407.90" - wire $reduce_or$libresoc.v:165407$10345_Y - attribute \src "libresoc.v:165408.17-165408.103" - wire $reduce_or$libresoc.v:165408$10346_Y - attribute \src "libresoc.v:165410.17-165410.109" - wire $reduce_or$libresoc.v:165410$10348_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165395$10333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165395$10333_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165397$10335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165397$10335_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165399$10337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165399$10337_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [8] } + connect \B { 2'00 \a [9] } + connect \Y $add$libresoc.v:174188$10391_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165400$10338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174189$10392 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165400$10338_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_2 } + connect \B { 2'00 \pop_3_3 } + connect \Y $add$libresoc.v:174189$10392_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165402$10340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174190$10393 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165402$10340_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_4 } + connect \B { 2'00 \pop_3_5 } + connect \Y $add$libresoc.v:174190$10393_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165404$10342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174191$10394 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165404$10342_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_6 } + connect \B { 2'00 \pop_3_7 } + connect \Y $add$libresoc.v:174191$10394_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165406$10344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174192$10395 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165406$10344_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_8 } + connect \B { 2'00 \pop_3_9 } + connect \Y $add$libresoc.v:174192$10395_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165409$10347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174193$10396 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165409$10347_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_10 } + connect \B { 2'00 \pop_3_11 } + connect \Y $add$libresoc.v:174193$10396_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165396$10334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174194$10397 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165396$10334_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_12 } + connect \B { 2'00 \pop_3_13 } + connect \Y $add$libresoc.v:174194$10397_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165398$10336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174195$10398 parameter \A_SIGNED 0 parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165398$10336_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_14 } + connect \B { 2'00 \pop_3_15 } + connect \Y $add$libresoc.v:174195$10398_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165401$10339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174196$10399 parameter \A_SIGNED 0 parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165401$10339_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165403$10341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165403$10341_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165405$10343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165405$10343_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_0 } + connect \B { 2'00 \pop_4_1 } + connect \Y $add$libresoc.v:174196$10399_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165407$10345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174197$10400 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165407$10345_Y + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_2 } + connect \B { 2'00 \pop_4_3 } + connect \Y $add$libresoc.v:174197$10400_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165408$10346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174198$10401 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165408$10346_Y + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_4 } + connect \B { 2'00 \pop_4_5 } + connect \Y $add$libresoc.v:174198$10401_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165410$10348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174199$10402 parameter \A_SIGNED 0 parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165410$10348_Y - end - connect \$7 $not$libresoc.v:165395$10333_Y - connect \$12 $reduce_or$libresoc.v:165396$10334_Y - connect \$11 $not$libresoc.v:165397$10335_Y - connect \$16 $reduce_or$libresoc.v:165398$10336_Y - connect \$15 $not$libresoc.v:165399$10337_Y - connect \$1 $not$libresoc.v:165400$10338_Y - connect \$20 $reduce_or$libresoc.v:165401$10339_Y - connect \$19 $not$libresoc.v:165402$10340_Y - connect \$24 $reduce_or$libresoc.v:165403$10341_Y - connect \$23 $not$libresoc.v:165404$10342_Y - connect \$28 $reduce_or$libresoc.v:165405$10343_Y - connect \$27 $not$libresoc.v:165406$10344_Y - connect \$31 $reduce_or$libresoc.v:165407$10345_Y - connect \$4 $reduce_or$libresoc.v:165408$10346_Y - connect \$3 $not$libresoc.v:165409$10347_Y - connect \$8 $reduce_or$libresoc.v:165410$10348_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165426.1-165510.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$186 - attribute \src "libresoc.v:165483.17-165483.91" - wire $not$libresoc.v:165483$10349_Y - attribute \src "libresoc.v:165485.18-165485.93" - wire $not$libresoc.v:165485$10351_Y - attribute \src "libresoc.v:165487.18-165487.93" - wire $not$libresoc.v:165487$10353_Y - attribute \src "libresoc.v:165488.17-165488.138" - wire width 8 $not$libresoc.v:165488$10354_Y - attribute \src "libresoc.v:165490.18-165490.93" - wire $not$libresoc.v:165490$10356_Y - attribute \src "libresoc.v:165492.18-165492.93" - wire $not$libresoc.v:165492$10358_Y - attribute \src "libresoc.v:165494.18-165494.93" - wire $not$libresoc.v:165494$10360_Y - attribute \src "libresoc.v:165497.17-165497.91" - wire $not$libresoc.v:165497$10363_Y - attribute \src "libresoc.v:165484.18-165484.116" - wire $reduce_or$libresoc.v:165484$10350_Y - attribute \src "libresoc.v:165486.18-165486.122" - wire $reduce_or$libresoc.v:165486$10352_Y - attribute \src "libresoc.v:165489.18-165489.128" - wire $reduce_or$libresoc.v:165489$10355_Y - attribute \src "libresoc.v:165491.18-165491.134" - wire $reduce_or$libresoc.v:165491$10357_Y - attribute \src "libresoc.v:165493.18-165493.140" - wire $reduce_or$libresoc.v:165493$10359_Y - attribute \src "libresoc.v:165495.18-165495.90" - wire $reduce_or$libresoc.v:165495$10361_Y - attribute \src "libresoc.v:165496.17-165496.103" - wire $reduce_or$libresoc.v:165496$10362_Y - attribute \src "libresoc.v:165498.17-165498.109" - wire $reduce_or$libresoc.v:165498$10364_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165483$10349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165483$10349_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165485$10351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165485$10351_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165487$10353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165487$10353_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165488$10354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165488$10354_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165490$10356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165490$10356_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165492$10358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165492$10358_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165494$10360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165494$10360_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165497$10363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165497$10363_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165484$10350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165484$10350_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165486$10352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165486$10352_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [10] } + connect \B { 2'00 \a [11] } + connect \Y $add$libresoc.v:174199$10402_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165489$10355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174200$10403 parameter \A_SIGNED 0 parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165489$10355_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_6 } + connect \B { 2'00 \pop_4_7 } + connect \Y $add$libresoc.v:174200$10403_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165491$10357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174201$10404 parameter \A_SIGNED 0 parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165491$10357_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165493$10359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165493$10359_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165495$10361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165495$10361_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165496$10362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165496$10362_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165498$10364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165498$10364_Y - end - connect \$7 $not$libresoc.v:165483$10349_Y - connect \$12 $reduce_or$libresoc.v:165484$10350_Y - connect \$11 $not$libresoc.v:165485$10351_Y - connect \$16 $reduce_or$libresoc.v:165486$10352_Y - connect \$15 $not$libresoc.v:165487$10353_Y - connect \$1 $not$libresoc.v:165488$10354_Y - connect \$20 $reduce_or$libresoc.v:165489$10355_Y - connect \$19 $not$libresoc.v:165490$10356_Y - connect \$24 $reduce_or$libresoc.v:165491$10357_Y - connect \$23 $not$libresoc.v:165492$10358_Y - connect \$28 $reduce_or$libresoc.v:165493$10359_Y - connect \$27 $not$libresoc.v:165494$10360_Y - connect \$31 $reduce_or$libresoc.v:165495$10361_Y - connect \$4 $reduce_or$libresoc.v:165496$10362_Y - connect \$3 $not$libresoc.v:165497$10363_Y - connect \$8 $reduce_or$libresoc.v:165498$10364_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165514.1-165598.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$192 - attribute \src "libresoc.v:165571.17-165571.91" - wire $not$libresoc.v:165571$10365_Y - attribute \src "libresoc.v:165573.18-165573.93" - wire $not$libresoc.v:165573$10367_Y - attribute \src "libresoc.v:165575.18-165575.93" - wire $not$libresoc.v:165575$10369_Y - attribute \src "libresoc.v:165576.17-165576.138" - wire width 8 $not$libresoc.v:165576$10370_Y - attribute \src "libresoc.v:165578.18-165578.93" - wire $not$libresoc.v:165578$10372_Y - attribute \src "libresoc.v:165580.18-165580.93" - wire $not$libresoc.v:165580$10374_Y - attribute \src "libresoc.v:165582.18-165582.93" - wire $not$libresoc.v:165582$10376_Y - attribute \src "libresoc.v:165585.17-165585.91" - wire $not$libresoc.v:165585$10379_Y - attribute \src "libresoc.v:165572.18-165572.116" - wire $reduce_or$libresoc.v:165572$10366_Y - attribute \src "libresoc.v:165574.18-165574.122" - wire $reduce_or$libresoc.v:165574$10368_Y - attribute \src "libresoc.v:165577.18-165577.128" - wire $reduce_or$libresoc.v:165577$10371_Y - attribute \src "libresoc.v:165579.18-165579.134" - wire $reduce_or$libresoc.v:165579$10373_Y - attribute \src "libresoc.v:165581.18-165581.140" - wire $reduce_or$libresoc.v:165581$10375_Y - attribute \src "libresoc.v:165583.18-165583.90" - wire $reduce_or$libresoc.v:165583$10377_Y - attribute \src "libresoc.v:165584.17-165584.103" - wire $reduce_or$libresoc.v:165584$10378_Y - attribute \src "libresoc.v:165586.17-165586.109" - wire $reduce_or$libresoc.v:165586$10380_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165571$10365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165571$10365_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165573$10367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165573$10367_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_0 } + connect \B { 2'00 \pop_5_1 } + connect \Y $add$libresoc.v:174201$10404_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165575$10369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174202$10405 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165575$10369_Y + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_2 } + connect \B { 2'00 \pop_5_3 } + connect \Y $add$libresoc.v:174202$10405_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165576$10370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174203$10406 parameter \A_SIGNED 0 parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165576$10370_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165578$10372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165578$10372_Y + connect \A { 2'00 \pop_6_0 } + connect \B { 2'00 \pop_6_1 } + connect \Y $add$libresoc.v:174203$10406_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165580$10374 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174214$10425 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165580$10374_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [12] } + connect \B { 2'00 \a [13] } + connect \Y $add$libresoc.v:174214$10425_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165582$10376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174218$10432 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165582$10376_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [14] } + connect \B { 2'00 \a [15] } + connect \Y $add$libresoc.v:174218$10432_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165585$10379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174219$10433 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165585$10379_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [16] } + connect \B { 2'00 \a [17] } + connect \Y $add$libresoc.v:174219$10433_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165572$10366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174220$10434 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165572$10366_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [0] } + connect \B { 2'00 \a [1] } + connect \Y $add$libresoc.v:174220$10434_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165574$10368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174221$10435 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165574$10368_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [18] } + connect \B { 2'00 \a [19] } + connect \Y $add$libresoc.v:174221$10435_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165577$10371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174222$10436 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165577$10371_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [20] } + connect \B { 2'00 \a [21] } + connect \Y $add$libresoc.v:174222$10436_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165579$10373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174223$10437 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165579$10373_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [22] } + connect \B { 2'00 \a [23] } + connect \Y $add$libresoc.v:174223$10437_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165581$10375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174224$10438 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165581$10375_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [24] } + connect \B { 2'00 \a [25] } + connect \Y $add$libresoc.v:174224$10438_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165583$10377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174225$10439 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165583$10377_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [26] } + connect \B { 2'00 \a [27] } + connect \Y $add$libresoc.v:174225$10439_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165584$10378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174226$10440 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165584$10378_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [28] } + connect \B { 2'00 \a [29] } + connect \Y $add$libresoc.v:174226$10440_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165586$10380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174227$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165586$10380_Y - end - connect \$7 $not$libresoc.v:165571$10365_Y - connect \$12 $reduce_or$libresoc.v:165572$10366_Y - connect \$11 $not$libresoc.v:165573$10367_Y - connect \$16 $reduce_or$libresoc.v:165574$10368_Y - connect \$15 $not$libresoc.v:165575$10369_Y - connect \$1 $not$libresoc.v:165576$10370_Y - connect \$20 $reduce_or$libresoc.v:165577$10371_Y - connect \$19 $not$libresoc.v:165578$10372_Y - connect \$24 $reduce_or$libresoc.v:165579$10373_Y - connect \$23 $not$libresoc.v:165580$10374_Y - connect \$28 $reduce_or$libresoc.v:165581$10375_Y - connect \$27 $not$libresoc.v:165582$10376_Y - connect \$31 $reduce_or$libresoc.v:165583$10377_Y - connect \$4 $reduce_or$libresoc.v:165584$10378_Y - connect \$3 $not$libresoc.v:165585$10379_Y - connect \$8 $reduce_or$libresoc.v:165586$10380_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165602.1-165686.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$194 - attribute \src "libresoc.v:165659.17-165659.91" - wire $not$libresoc.v:165659$10381_Y - attribute \src "libresoc.v:165661.18-165661.93" - wire $not$libresoc.v:165661$10383_Y - attribute \src "libresoc.v:165663.18-165663.93" - wire $not$libresoc.v:165663$10385_Y - attribute \src "libresoc.v:165664.17-165664.138" - wire width 8 $not$libresoc.v:165664$10386_Y - attribute \src "libresoc.v:165666.18-165666.93" - wire $not$libresoc.v:165666$10388_Y - attribute \src "libresoc.v:165668.18-165668.93" - wire $not$libresoc.v:165668$10390_Y - attribute \src "libresoc.v:165670.18-165670.93" - wire $not$libresoc.v:165670$10392_Y - attribute \src "libresoc.v:165673.17-165673.91" - wire $not$libresoc.v:165673$10395_Y - attribute \src "libresoc.v:165660.18-165660.116" - wire $reduce_or$libresoc.v:165660$10382_Y - attribute \src "libresoc.v:165662.18-165662.122" - wire $reduce_or$libresoc.v:165662$10384_Y - attribute \src "libresoc.v:165665.18-165665.128" - wire $reduce_or$libresoc.v:165665$10387_Y - attribute \src "libresoc.v:165667.18-165667.134" - wire $reduce_or$libresoc.v:165667$10389_Y - attribute \src "libresoc.v:165669.18-165669.140" - wire $reduce_or$libresoc.v:165669$10391_Y - attribute \src "libresoc.v:165671.18-165671.90" - wire $reduce_or$libresoc.v:165671$10393_Y - attribute \src "libresoc.v:165672.17-165672.103" - wire $reduce_or$libresoc.v:165672$10394_Y - attribute \src "libresoc.v:165674.17-165674.109" - wire $reduce_or$libresoc.v:165674$10396_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165659$10381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165659$10381_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [30] } + connect \B { 2'00 \a [31] } + connect \Y $add$libresoc.v:174227$10441_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165661$10383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174228$10442 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165661$10383_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [32] } + connect \B { 2'00 \a [33] } + connect \Y $add$libresoc.v:174228$10442_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165663$10385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174229$10443 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165663$10385_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [34] } + connect \B { 2'00 \a [35] } + connect \Y $add$libresoc.v:174229$10443_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165664$10386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174230$10444 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165664$10386_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [36] } + connect \B { 2'00 \a [37] } + connect \Y $add$libresoc.v:174230$10444_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165666$10388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174231$10445 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165666$10388_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [2] } + connect \B { 2'00 \a [3] } + connect \Y $add$libresoc.v:174231$10445_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165668$10390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174232$10446 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165668$10390_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [38] } + connect \B { 2'00 \a [39] } + connect \Y $add$libresoc.v:174232$10446_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165670$10392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174233$10447 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165670$10392_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [40] } + connect \B { 2'00 \a [41] } + connect \Y $add$libresoc.v:174233$10447_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165673$10395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174234$10448 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165673$10395_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [42] } + connect \B { 2'00 \a [43] } + connect \Y $add$libresoc.v:174234$10448_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165660$10382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174235$10449 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165660$10382_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [44] } + connect \B { 2'00 \a [45] } + connect \Y $add$libresoc.v:174235$10449_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165662$10384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174236$10450 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165662$10384_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [46] } + connect \B { 2'00 \a [47] } + connect \Y $add$libresoc.v:174236$10450_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165665$10387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174237$10451 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165665$10387_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [48] } + connect \B { 2'00 \a [49] } + connect \Y $add$libresoc.v:174237$10451_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165667$10389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174238$10452 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165667$10389_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [50] } + connect \B { 2'00 \a [51] } + connect \Y $add$libresoc.v:174238$10452_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165669$10391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174239$10453 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165669$10391_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [52] } + connect \B { 2'00 \a [53] } + connect \Y $add$libresoc.v:174239$10453_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165671$10393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174240$10454 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165671$10393_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [54] } + connect \B { 2'00 \a [55] } + connect \Y $add$libresoc.v:174240$10454_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165672$10394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174241$10455 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165672$10394_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [56] } + connect \B { 2'00 \a [57] } + connect \Y $add$libresoc.v:174241$10455_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165674$10396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174242$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165674$10396_Y - end - connect \$7 $not$libresoc.v:165659$10381_Y - connect \$12 $reduce_or$libresoc.v:165660$10382_Y - connect \$11 $not$libresoc.v:165661$10383_Y - connect \$16 $reduce_or$libresoc.v:165662$10384_Y - connect \$15 $not$libresoc.v:165663$10385_Y - connect \$1 $not$libresoc.v:165664$10386_Y - connect \$20 $reduce_or$libresoc.v:165665$10387_Y - connect \$19 $not$libresoc.v:165666$10388_Y - connect \$24 $reduce_or$libresoc.v:165667$10389_Y - connect \$23 $not$libresoc.v:165668$10390_Y - connect \$28 $reduce_or$libresoc.v:165669$10391_Y - connect \$27 $not$libresoc.v:165670$10392_Y - connect \$31 $reduce_or$libresoc.v:165671$10393_Y - connect \$4 $reduce_or$libresoc.v:165672$10394_Y - connect \$3 $not$libresoc.v:165673$10395_Y - connect \$8 $reduce_or$libresoc.v:165674$10396_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165690.1-165774.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$200 - attribute \src "libresoc.v:165747.17-165747.91" - wire $not$libresoc.v:165747$10397_Y - attribute \src "libresoc.v:165749.18-165749.93" - wire $not$libresoc.v:165749$10399_Y - attribute \src "libresoc.v:165751.18-165751.93" - wire $not$libresoc.v:165751$10401_Y - attribute \src "libresoc.v:165752.17-165752.138" - wire width 8 $not$libresoc.v:165752$10402_Y - attribute \src "libresoc.v:165754.18-165754.93" - wire $not$libresoc.v:165754$10404_Y - attribute \src "libresoc.v:165756.18-165756.93" - wire $not$libresoc.v:165756$10406_Y - attribute \src "libresoc.v:165758.18-165758.93" - wire $not$libresoc.v:165758$10408_Y - attribute \src "libresoc.v:165761.17-165761.91" - wire $not$libresoc.v:165761$10411_Y - attribute \src "libresoc.v:165748.18-165748.116" - wire $reduce_or$libresoc.v:165748$10398_Y - attribute \src "libresoc.v:165750.18-165750.122" - wire $reduce_or$libresoc.v:165750$10400_Y - attribute \src "libresoc.v:165753.18-165753.128" - wire $reduce_or$libresoc.v:165753$10403_Y - attribute \src "libresoc.v:165755.18-165755.134" - wire $reduce_or$libresoc.v:165755$10405_Y - attribute \src "libresoc.v:165757.18-165757.140" - wire $reduce_or$libresoc.v:165757$10407_Y - attribute \src "libresoc.v:165759.18-165759.90" - wire $reduce_or$libresoc.v:165759$10409_Y - attribute \src "libresoc.v:165760.17-165760.103" - wire $reduce_or$libresoc.v:165760$10410_Y - attribute \src "libresoc.v:165762.17-165762.109" - wire $reduce_or$libresoc.v:165762$10412_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165747$10397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165747$10397_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [4] } + connect \B { 2'00 \a [5] } + connect \Y $add$libresoc.v:174242$10456_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165749$10399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174243$10457 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165749$10399_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [58] } + connect \B { 2'00 \a [59] } + connect \Y $add$libresoc.v:174243$10457_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165751$10401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174244$10458 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165751$10401_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [60] } + connect \B { 2'00 \a [61] } + connect \Y $add$libresoc.v:174244$10458_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165752$10402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174245$10459 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165752$10402_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [62] } + connect \B { 2'00 \a [63] } + connect \Y $add$libresoc.v:174245$10459_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165754$10404 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174246$10460 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165754$10404_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_0 } + connect \B { 2'00 \pop_2_1 } + connect \Y $add$libresoc.v:174246$10460_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165756$10406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + cell $eq $eq$libresoc.v:174204$10407 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165756$10406_Y + connect \A \data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:174204$10407_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165758$10408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + cell $eq $eq$libresoc.v:174205$10408 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165758$10408_Y + connect \A \data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:174205$10408_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165761$10411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174206$10409 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165761$10411_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_0 + connect \Y $extend$libresoc.v:174206$10409_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165748$10398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174207$10411 parameter \A_SIGNED 0 parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165748$10398_Y + parameter \Y_WIDTH 8 + connect \A \pop_4_1 + connect \Y $extend$libresoc.v:174207$10411_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165750$10400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174208$10413 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165750$10400_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_2 + connect \Y $extend$libresoc.v:174208$10413_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165753$10403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174209$10415 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165753$10403_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_3 + connect \Y $extend$libresoc.v:174209$10415_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165755$10405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174210$10417 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165755$10405_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_4 + connect \Y $extend$libresoc.v:174210$10417_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165757$10407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174211$10419 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165757$10407_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_5 + connect \Y $extend$libresoc.v:174211$10419_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165759$10409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174212$10421 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165759$10409_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_6 + connect \Y $extend$libresoc.v:174212$10421_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165760$10410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174213$10423 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165760$10410_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_7 + connect \Y $extend$libresoc.v:174213$10423_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165762$10412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165762$10412_Y - end - connect \$7 $not$libresoc.v:165747$10397_Y - connect \$12 $reduce_or$libresoc.v:165748$10398_Y - connect \$11 $not$libresoc.v:165749$10399_Y - connect \$16 $reduce_or$libresoc.v:165750$10400_Y - connect \$15 $not$libresoc.v:165751$10401_Y - connect \$1 $not$libresoc.v:165752$10402_Y - connect \$20 $reduce_or$libresoc.v:165753$10403_Y - connect \$19 $not$libresoc.v:165754$10404_Y - connect \$24 $reduce_or$libresoc.v:165755$10405_Y - connect \$23 $not$libresoc.v:165756$10406_Y - connect \$28 $reduce_or$libresoc.v:165757$10407_Y - connect \$27 $not$libresoc.v:165758$10408_Y - connect \$31 $reduce_or$libresoc.v:165759$10409_Y - connect \$4 $reduce_or$libresoc.v:165760$10410_Y - connect \$3 $not$libresoc.v:165761$10411_Y - connect \$8 $reduce_or$libresoc.v:165762$10412_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165778.1-165862.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$202 - attribute \src "libresoc.v:165835.17-165835.91" - wire $not$libresoc.v:165835$10413_Y - attribute \src "libresoc.v:165837.18-165837.93" - wire $not$libresoc.v:165837$10415_Y - attribute \src "libresoc.v:165839.18-165839.93" - wire $not$libresoc.v:165839$10417_Y - attribute \src "libresoc.v:165840.17-165840.138" - wire width 8 $not$libresoc.v:165840$10418_Y - attribute \src "libresoc.v:165842.18-165842.93" - wire $not$libresoc.v:165842$10420_Y - attribute \src "libresoc.v:165844.18-165844.93" - wire $not$libresoc.v:165844$10422_Y - attribute \src "libresoc.v:165846.18-165846.93" - wire $not$libresoc.v:165846$10424_Y - attribute \src "libresoc.v:165849.17-165849.91" - wire $not$libresoc.v:165849$10427_Y - attribute \src "libresoc.v:165836.18-165836.116" - wire $reduce_or$libresoc.v:165836$10414_Y - attribute \src "libresoc.v:165838.18-165838.122" - wire $reduce_or$libresoc.v:165838$10416_Y - attribute \src "libresoc.v:165841.18-165841.128" - wire $reduce_or$libresoc.v:165841$10419_Y - attribute \src "libresoc.v:165843.18-165843.134" - wire $reduce_or$libresoc.v:165843$10421_Y - attribute \src "libresoc.v:165845.18-165845.140" - wire $reduce_or$libresoc.v:165845$10423_Y - attribute \src "libresoc.v:165847.18-165847.90" - wire $reduce_or$libresoc.v:165847$10425_Y - attribute \src "libresoc.v:165848.17-165848.103" - wire $reduce_or$libresoc.v:165848$10426_Y - attribute \src "libresoc.v:165850.17-165850.109" - wire $reduce_or$libresoc.v:165850$10428_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165835$10413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174215$10426 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165835$10413_Y + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_0 + connect \Y $extend$libresoc.v:174215$10426_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165837$10415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174216$10428 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165837$10415_Y + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_1 + connect \Y $extend$libresoc.v:174216$10428_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165839$10417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174217$10430 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165839$10417_Y + parameter \A_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \pop_7_0 + connect \Y $extend$libresoc.v:174217$10430_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165840$10418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174206$10410 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165840$10418_Y + connect \A $extend$libresoc.v:174206$10409_Y + connect \Y $pos$libresoc.v:174206$10410_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165842$10420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174207$10412 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165842$10420_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174207$10411_Y + connect \Y $pos$libresoc.v:174207$10412_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165844$10422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174208$10414 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165844$10422_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174208$10413_Y + connect \Y $pos$libresoc.v:174208$10414_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165846$10424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174209$10416 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165846$10424_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174209$10415_Y + connect \Y $pos$libresoc.v:174209$10416_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165849$10427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174210$10418 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165849$10427_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174210$10417_Y + connect \Y $pos$libresoc.v:174210$10418_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165836$10414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174211$10420 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165836$10414_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174211$10419_Y + connect \Y $pos$libresoc.v:174211$10420_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165838$10416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174212$10422 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165838$10416_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174212$10421_Y + connect \Y $pos$libresoc.v:174212$10422_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165841$10419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174213$10424 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165841$10419_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174213$10423_Y + connect \Y $pos$libresoc.v:174213$10424_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165843$10421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174215$10427 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165843$10421_Y + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:174215$10426_Y + connect \Y $pos$libresoc.v:174215$10427_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165845$10423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174216$10429 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165845$10423_Y + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:174216$10428_Y + connect \Y $pos$libresoc.v:174216$10429_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165847$10425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174217$10431 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165847$10425_Y + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:174217$10430_Y + connect \Y $pos$libresoc.v:174217$10431_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165848$10426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165848$10426_Y + attribute \src "libresoc.v:173759.7-173759.20" + process $proc$libresoc.v:173759$10462 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165850$10428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165850$10428_Y - end - connect \$7 $not$libresoc.v:165835$10413_Y - connect \$12 $reduce_or$libresoc.v:165836$10414_Y - connect \$11 $not$libresoc.v:165837$10415_Y - connect \$16 $reduce_or$libresoc.v:165838$10416_Y - connect \$15 $not$libresoc.v:165839$10417_Y - connect \$1 $not$libresoc.v:165840$10418_Y - connect \$20 $reduce_or$libresoc.v:165841$10419_Y - connect \$19 $not$libresoc.v:165842$10420_Y - connect \$24 $reduce_or$libresoc.v:165843$10421_Y - connect \$23 $not$libresoc.v:165844$10422_Y - connect \$28 $reduce_or$libresoc.v:165845$10423_Y - connect \$27 $not$libresoc.v:165846$10424_Y - connect \$31 $reduce_or$libresoc.v:165847$10425_Y - connect \$4 $reduce_or$libresoc.v:165848$10426_Y - connect \$3 $not$libresoc.v:165849$10427_Y - connect \$8 $reduce_or$libresoc.v:165850$10428_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + attribute \src "libresoc.v:174247.3-174273.6" + process $proc$libresoc.v:174247$10461 + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:174248.5-174248.29" + switch \initial + attribute \src "libresoc.v:174248.9-174248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + switch { \$192 \$190 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o[63:0] [7:0] \$194 + assign $1\o[63:0] [15:8] \$196 + assign $1\o[63:0] [23:16] \$198 + assign $1\o[63:0] [31:24] \$200 + assign $1\o[63:0] [39:32] \$202 + assign $1\o[63:0] [47:40] \$204 + assign $1\o[63:0] [55:48] \$206 + assign $1\o[63:0] [63:56] \$208 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o[63:0] [31:0] \$210 + assign $1\o[63:0] [63:32] \$212 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] \$214 + end + sync always + update \o $0\o[63:0] + end + connect \$101 $add$libresoc.v:174171$10374_Y + connect \$104 $add$libresoc.v:174172$10375_Y + connect \$107 $add$libresoc.v:174173$10376_Y + connect \$110 $add$libresoc.v:174174$10377_Y + connect \$113 $add$libresoc.v:174175$10378_Y + connect \$116 $add$libresoc.v:174176$10379_Y + connect \$11 $add$libresoc.v:174177$10380_Y + connect \$119 $add$libresoc.v:174178$10381_Y + connect \$122 $add$libresoc.v:174179$10382_Y + connect \$125 $add$libresoc.v:174180$10383_Y + connect \$128 $add$libresoc.v:174181$10384_Y + connect \$131 $add$libresoc.v:174182$10385_Y + connect \$134 $add$libresoc.v:174183$10386_Y + connect \$137 $add$libresoc.v:174184$10387_Y + connect \$140 $add$libresoc.v:174185$10388_Y + connect \$143 $add$libresoc.v:174186$10389_Y + connect \$146 $add$libresoc.v:174187$10390_Y + connect \$14 $add$libresoc.v:174188$10391_Y + connect \$149 $add$libresoc.v:174189$10392_Y + connect \$152 $add$libresoc.v:174190$10393_Y + connect \$155 $add$libresoc.v:174191$10394_Y + connect \$158 $add$libresoc.v:174192$10395_Y + connect \$161 $add$libresoc.v:174193$10396_Y + connect \$164 $add$libresoc.v:174194$10397_Y + connect \$167 $add$libresoc.v:174195$10398_Y + connect \$170 $add$libresoc.v:174196$10399_Y + connect \$173 $add$libresoc.v:174197$10400_Y + connect \$176 $add$libresoc.v:174198$10401_Y + connect \$17 $add$libresoc.v:174199$10402_Y + connect \$179 $add$libresoc.v:174200$10403_Y + connect \$182 $add$libresoc.v:174201$10404_Y + connect \$185 $add$libresoc.v:174202$10405_Y + connect \$188 $add$libresoc.v:174203$10406_Y + connect \$190 $eq$libresoc.v:174204$10407_Y + connect \$192 $eq$libresoc.v:174205$10408_Y + connect \$194 $pos$libresoc.v:174206$10410_Y + connect \$196 $pos$libresoc.v:174207$10412_Y + connect \$198 $pos$libresoc.v:174208$10414_Y + connect \$200 $pos$libresoc.v:174209$10416_Y + connect \$202 $pos$libresoc.v:174210$10418_Y + connect \$204 $pos$libresoc.v:174211$10420_Y + connect \$206 $pos$libresoc.v:174212$10422_Y + connect \$208 $pos$libresoc.v:174213$10424_Y + connect \$20 $add$libresoc.v:174214$10425_Y + connect \$210 $pos$libresoc.v:174215$10427_Y + connect \$212 $pos$libresoc.v:174216$10429_Y + connect \$214 $pos$libresoc.v:174217$10431_Y + connect \$23 $add$libresoc.v:174218$10432_Y + connect \$26 $add$libresoc.v:174219$10433_Y + connect \$2 $add$libresoc.v:174220$10434_Y + connect \$29 $add$libresoc.v:174221$10435_Y + connect \$32 $add$libresoc.v:174222$10436_Y + connect \$35 $add$libresoc.v:174223$10437_Y + connect \$38 $add$libresoc.v:174224$10438_Y + connect \$41 $add$libresoc.v:174225$10439_Y + connect \$44 $add$libresoc.v:174226$10440_Y + connect \$47 $add$libresoc.v:174227$10441_Y + connect \$50 $add$libresoc.v:174228$10442_Y + connect \$53 $add$libresoc.v:174229$10443_Y + connect \$56 $add$libresoc.v:174230$10444_Y + connect \$5 $add$libresoc.v:174231$10445_Y + connect \$59 $add$libresoc.v:174232$10446_Y + connect \$62 $add$libresoc.v:174233$10447_Y + connect \$65 $add$libresoc.v:174234$10448_Y + connect \$68 $add$libresoc.v:174235$10449_Y + connect \$71 $add$libresoc.v:174236$10450_Y + connect \$74 $add$libresoc.v:174237$10451_Y + connect \$77 $add$libresoc.v:174238$10452_Y + connect \$80 $add$libresoc.v:174239$10453_Y + connect \$83 $add$libresoc.v:174240$10454_Y + connect \$86 $add$libresoc.v:174241$10455_Y + connect \$8 $add$libresoc.v:174242$10456_Y + connect \$89 $add$libresoc.v:174243$10457_Y + connect \$92 $add$libresoc.v:174244$10458_Y + connect \$95 $add$libresoc.v:174245$10459_Y + connect \$98 $add$libresoc.v:174246$10460_Y + connect \$1 \$2 + connect \$4 \$5 + connect \$7 \$8 + connect \$10 \$11 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 + connect \$25 \$26 + connect \$28 \$29 + connect \$31 \$32 + connect \$34 \$35 + connect \$37 \$38 + connect \$40 \$41 + connect \$43 \$44 + connect \$46 \$47 + connect \$49 \$50 + connect \$52 \$53 + connect \$55 \$56 + connect \$58 \$59 + connect \$61 \$62 + connect \$64 \$65 + connect \$67 \$68 + connect \$70 \$71 + connect \$73 \$74 + connect \$76 \$77 + connect \$79 \$80 + connect \$82 \$83 + connect \$85 \$86 + connect \$88 \$89 + connect \$91 \$92 + connect \$94 \$95 + connect \$97 \$98 + connect \$100 \$101 + connect \$103 \$104 + connect \$106 \$107 + connect \$109 \$110 + connect \$112 \$113 + connect \$115 \$116 + connect \$118 \$119 + connect \$121 \$122 + connect \$124 \$125 + connect \$127 \$128 + connect \$130 \$131 + connect \$133 \$134 + connect \$136 \$137 + connect \$139 \$140 + connect \$142 \$143 + connect \$145 \$146 + connect \$148 \$149 + connect \$151 \$152 + connect \$154 \$155 + connect \$157 \$158 + connect \$160 \$161 + connect \$163 \$164 + connect \$166 \$167 + connect \$169 \$170 + connect \$172 \$173 + connect \$175 \$176 + connect \$178 \$179 + connect \$181 \$182 + connect \$184 \$185 + connect \$187 \$188 + connect \pop_7_0 \$188 [6:0] + connect \pop_6_1 \$185 [5:0] + connect \pop_6_0 \$182 [5:0] + connect \pop_5_3 \$179 [4:0] + connect \pop_5_2 \$176 [4:0] + connect \pop_5_1 \$173 [4:0] + connect \pop_5_0 \$170 [4:0] + connect \pop_4_7 \$167 [3:0] + connect \pop_4_6 \$164 [3:0] + connect \pop_4_5 \$161 [3:0] + connect \pop_4_4 \$158 [3:0] + connect \pop_4_3 \$155 [3:0] + connect \pop_4_2 \$152 [3:0] + connect \pop_4_1 \$149 [3:0] + connect \pop_4_0 \$146 [3:0] + connect \pop_3_15 \$143 [2:0] + connect \pop_3_14 \$140 [2:0] + connect \pop_3_13 \$137 [2:0] + connect \pop_3_12 \$134 [2:0] + connect \pop_3_11 \$131 [2:0] + connect \pop_3_10 \$128 [2:0] + connect \pop_3_9 \$125 [2:0] + connect \pop_3_8 \$122 [2:0] + connect \pop_3_7 \$119 [2:0] + connect \pop_3_6 \$116 [2:0] + connect \pop_3_5 \$113 [2:0] + connect \pop_3_4 \$110 [2:0] + connect \pop_3_3 \$107 [2:0] + connect \pop_3_2 \$104 [2:0] + connect \pop_3_1 \$101 [2:0] + connect \pop_3_0 \$98 [2:0] + connect \pop_2_31 \$95 [1:0] + connect \pop_2_30 \$92 [1:0] + connect \pop_2_29 \$89 [1:0] + connect \pop_2_28 \$86 [1:0] + connect \pop_2_27 \$83 [1:0] + connect \pop_2_26 \$80 [1:0] + connect \pop_2_25 \$77 [1:0] + connect \pop_2_24 \$74 [1:0] + connect \pop_2_23 \$71 [1:0] + connect \pop_2_22 \$68 [1:0] + connect \pop_2_21 \$65 [1:0] + connect \pop_2_20 \$62 [1:0] + connect \pop_2_19 \$59 [1:0] + connect \pop_2_18 \$56 [1:0] + connect \pop_2_17 \$53 [1:0] + connect \pop_2_16 \$50 [1:0] + connect \pop_2_15 \$47 [1:0] + connect \pop_2_14 \$44 [1:0] + connect \pop_2_13 \$41 [1:0] + connect \pop_2_12 \$38 [1:0] + connect \pop_2_11 \$35 [1:0] + connect \pop_2_10 \$32 [1:0] + connect \pop_2_9 \$29 [1:0] + connect \pop_2_8 \$26 [1:0] + connect \pop_2_7 \$23 [1:0] + connect \pop_2_6 \$20 [1:0] + connect \pop_2_5 \$17 [1:0] + connect \pop_2_4 \$14 [1:0] + connect \pop_2_3 \$11 [1:0] + connect \pop_2_2 \$8 [1:0] + connect \pop_2_1 \$5 [1:0] + connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:165866.1-165950.10" +attribute \src "libresoc.v:174404.1-174488.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$209 - attribute \src "libresoc.v:165923.17-165923.91" - wire $not$libresoc.v:165923$10429_Y - attribute \src "libresoc.v:165925.18-165925.93" - wire $not$libresoc.v:165925$10431_Y - attribute \src "libresoc.v:165927.18-165927.93" - wire $not$libresoc.v:165927$10433_Y - attribute \src "libresoc.v:165928.17-165928.138" - wire width 8 $not$libresoc.v:165928$10434_Y - attribute \src "libresoc.v:165930.18-165930.93" - wire $not$libresoc.v:165930$10436_Y - attribute \src "libresoc.v:165932.18-165932.93" - wire $not$libresoc.v:165932$10438_Y - attribute \src "libresoc.v:165934.18-165934.93" - wire $not$libresoc.v:165934$10440_Y - attribute \src "libresoc.v:165937.17-165937.91" - wire $not$libresoc.v:165937$10443_Y - attribute \src "libresoc.v:165924.18-165924.116" - wire $reduce_or$libresoc.v:165924$10430_Y - attribute \src "libresoc.v:165926.18-165926.122" - wire $reduce_or$libresoc.v:165926$10432_Y - attribute \src "libresoc.v:165929.18-165929.128" - wire $reduce_or$libresoc.v:165929$10435_Y - attribute \src "libresoc.v:165931.18-165931.134" - wire $reduce_or$libresoc.v:165931$10437_Y - attribute \src "libresoc.v:165933.18-165933.140" - wire $reduce_or$libresoc.v:165933$10439_Y - attribute \src "libresoc.v:165935.18-165935.90" - wire $reduce_or$libresoc.v:165935$10441_Y - attribute \src "libresoc.v:165936.17-165936.103" - wire $reduce_or$libresoc.v:165936$10442_Y - attribute \src "libresoc.v:165938.17-165938.109" - wire $reduce_or$libresoc.v:165938$10444_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" +module \ppick + attribute \src "libresoc.v:174461.17-174461.91" + wire $not$libresoc.v:174461$10463_Y + attribute \src "libresoc.v:174463.18-174463.93" + wire $not$libresoc.v:174463$10465_Y + attribute \src "libresoc.v:174465.18-174465.93" + wire $not$libresoc.v:174465$10467_Y + attribute \src "libresoc.v:174466.17-174466.138" + wire width 8 $not$libresoc.v:174466$10468_Y + attribute \src "libresoc.v:174468.18-174468.93" + wire $not$libresoc.v:174468$10470_Y + attribute \src "libresoc.v:174470.18-174470.93" + wire $not$libresoc.v:174470$10472_Y + attribute \src "libresoc.v:174472.18-174472.93" + wire $not$libresoc.v:174472$10474_Y + attribute \src "libresoc.v:174475.17-174475.91" + wire $not$libresoc.v:174475$10477_Y + attribute \src "libresoc.v:174462.18-174462.116" + wire $reduce_or$libresoc.v:174462$10464_Y + attribute \src "libresoc.v:174464.18-174464.122" + wire $reduce_or$libresoc.v:174464$10466_Y + attribute \src "libresoc.v:174467.18-174467.128" + wire $reduce_or$libresoc.v:174467$10469_Y + attribute \src "libresoc.v:174469.18-174469.134" + wire $reduce_or$libresoc.v:174469$10471_Y + attribute \src "libresoc.v:174471.18-174471.140" + wire $reduce_or$libresoc.v:174471$10473_Y + attribute \src "libresoc.v:174473.18-174473.90" + wire $reduce_or$libresoc.v:174473$10475_Y + attribute \src "libresoc.v:174474.17-174474.103" + wire $reduce_or$libresoc.v:174474$10476_Y + attribute \src "libresoc.v:174476.17-174476.109" + wire $reduce_or$libresoc.v:174476$10478_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165923$10429 + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174461$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:165923$10429_Y + connect \Y $not$libresoc.v:174461$10463_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165925$10431 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174463$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:165925$10431_Y + connect \Y $not$libresoc.v:174463$10465_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165927$10433 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174465$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:165927$10433_Y + connect \Y $not$libresoc.v:174465$10467_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165928$10434 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174466$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165928$10434_Y + connect \Y $not$libresoc.v:174466$10468_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165930$10436 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174468$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:165930$10436_Y + connect \Y $not$libresoc.v:174468$10470_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165932$10438 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174470$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:165932$10438_Y + connect \Y $not$libresoc.v:174470$10472_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165934$10440 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174472$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:165934$10440_Y + connect \Y $not$libresoc.v:174472$10474_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165937$10443 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174475$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:165937$10443_Y + connect \Y $not$libresoc.v:174475$10477_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165924$10430 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174462$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165924$10430_Y + connect \Y $reduce_or$libresoc.v:174462$10464_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165926$10432 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174464$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165926$10432_Y + connect \Y $reduce_or$libresoc.v:174464$10466_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165929$10435 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174467$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165929$10435_Y + connect \Y $reduce_or$libresoc.v:174467$10469_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165931$10437 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174469$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165931$10437_Y + connect \Y $reduce_or$libresoc.v:174469$10471_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165933$10439 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174471$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165933$10439_Y + connect \Y $reduce_or$libresoc.v:174471$10473_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165935$10441 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174473$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:165935$10441_Y + connect \Y $reduce_or$libresoc.v:174473$10475_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165936$10442 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174474$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165936$10442_Y + connect \Y $reduce_or$libresoc.v:174474$10476_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165938$10444 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174476$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165938$10444_Y - end - connect \$7 $not$libresoc.v:165923$10429_Y - connect \$12 $reduce_or$libresoc.v:165924$10430_Y - connect \$11 $not$libresoc.v:165925$10431_Y - connect \$16 $reduce_or$libresoc.v:165926$10432_Y - connect \$15 $not$libresoc.v:165927$10433_Y - connect \$1 $not$libresoc.v:165928$10434_Y - connect \$20 $reduce_or$libresoc.v:165929$10435_Y - connect \$19 $not$libresoc.v:165930$10436_Y - connect \$24 $reduce_or$libresoc.v:165931$10437_Y - connect \$23 $not$libresoc.v:165932$10438_Y - connect \$28 $reduce_or$libresoc.v:165933$10439_Y - connect \$27 $not$libresoc.v:165934$10440_Y - connect \$31 $reduce_or$libresoc.v:165935$10441_Y - connect \$4 $reduce_or$libresoc.v:165936$10442_Y - connect \$3 $not$libresoc.v:165937$10443_Y - connect \$8 $reduce_or$libresoc.v:165938$10444_Y + connect \Y $reduce_or$libresoc.v:174476$10478_Y + end + connect \$7 $not$libresoc.v:174461$10463_Y + connect \$12 $reduce_or$libresoc.v:174462$10464_Y + connect \$11 $not$libresoc.v:174463$10465_Y + connect \$16 $reduce_or$libresoc.v:174464$10466_Y + connect \$15 $not$libresoc.v:174465$10467_Y + connect \$1 $not$libresoc.v:174466$10468_Y + connect \$20 $reduce_or$libresoc.v:174467$10469_Y + connect \$19 $not$libresoc.v:174468$10470_Y + connect \$24 $reduce_or$libresoc.v:174469$10471_Y + connect \$23 $not$libresoc.v:174470$10472_Y + connect \$28 $reduce_or$libresoc.v:174471$10473_Y + connect \$27 $not$libresoc.v:174472$10474_Y + connect \$31 $reduce_or$libresoc.v:174473$10475_Y + connect \$4 $reduce_or$libresoc.v:174474$10476_Y + connect \$3 $not$libresoc.v:174475$10477_Y + connect \$8 $reduce_or$libresoc.v:174476$10478_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -344033,243 +358697,243 @@ module \ppick$209 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:165954.1-166038.10" +attribute \src "libresoc.v:174492.1-174576.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$211 - attribute \src "libresoc.v:166011.17-166011.91" - wire $not$libresoc.v:166011$10445_Y - attribute \src "libresoc.v:166013.18-166013.93" - wire $not$libresoc.v:166013$10447_Y - attribute \src "libresoc.v:166015.18-166015.93" - wire $not$libresoc.v:166015$10449_Y - attribute \src "libresoc.v:166016.17-166016.138" - wire width 8 $not$libresoc.v:166016$10450_Y - attribute \src "libresoc.v:166018.18-166018.93" - wire $not$libresoc.v:166018$10452_Y - attribute \src "libresoc.v:166020.18-166020.93" - wire $not$libresoc.v:166020$10454_Y - attribute \src "libresoc.v:166022.18-166022.93" - wire $not$libresoc.v:166022$10456_Y - attribute \src "libresoc.v:166025.17-166025.91" - wire $not$libresoc.v:166025$10459_Y - attribute \src "libresoc.v:166012.18-166012.116" - wire $reduce_or$libresoc.v:166012$10446_Y - attribute \src "libresoc.v:166014.18-166014.122" - wire $reduce_or$libresoc.v:166014$10448_Y - attribute \src "libresoc.v:166017.18-166017.128" - wire $reduce_or$libresoc.v:166017$10451_Y - attribute \src "libresoc.v:166019.18-166019.134" - wire $reduce_or$libresoc.v:166019$10453_Y - attribute \src "libresoc.v:166021.18-166021.140" - wire $reduce_or$libresoc.v:166021$10455_Y - attribute \src "libresoc.v:166023.18-166023.90" - wire $reduce_or$libresoc.v:166023$10457_Y - attribute \src "libresoc.v:166024.17-166024.103" - wire $reduce_or$libresoc.v:166024$10458_Y - attribute \src "libresoc.v:166026.17-166026.109" - wire $reduce_or$libresoc.v:166026$10460_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" +module \ppick$175 + attribute \src "libresoc.v:174549.17-174549.91" + wire $not$libresoc.v:174549$10479_Y + attribute \src "libresoc.v:174551.18-174551.93" + wire $not$libresoc.v:174551$10481_Y + attribute \src "libresoc.v:174553.18-174553.93" + wire $not$libresoc.v:174553$10483_Y + attribute \src "libresoc.v:174554.17-174554.138" + wire width 8 $not$libresoc.v:174554$10484_Y + attribute \src "libresoc.v:174556.18-174556.93" + wire $not$libresoc.v:174556$10486_Y + attribute \src "libresoc.v:174558.18-174558.93" + wire $not$libresoc.v:174558$10488_Y + attribute \src "libresoc.v:174560.18-174560.93" + wire $not$libresoc.v:174560$10490_Y + attribute \src "libresoc.v:174563.17-174563.91" + wire $not$libresoc.v:174563$10493_Y + attribute \src "libresoc.v:174550.18-174550.116" + wire $reduce_or$libresoc.v:174550$10480_Y + attribute \src "libresoc.v:174552.18-174552.122" + wire $reduce_or$libresoc.v:174552$10482_Y + attribute \src "libresoc.v:174555.18-174555.128" + wire $reduce_or$libresoc.v:174555$10485_Y + attribute \src "libresoc.v:174557.18-174557.134" + wire $reduce_or$libresoc.v:174557$10487_Y + attribute \src "libresoc.v:174559.18-174559.140" + wire $reduce_or$libresoc.v:174559$10489_Y + attribute \src "libresoc.v:174561.18-174561.90" + wire $reduce_or$libresoc.v:174561$10491_Y + attribute \src "libresoc.v:174562.17-174562.103" + wire $reduce_or$libresoc.v:174562$10492_Y + attribute \src "libresoc.v:174564.17-174564.109" + wire $reduce_or$libresoc.v:174564$10494_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166011$10445 + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174549$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:166011$10445_Y + connect \Y $not$libresoc.v:174549$10479_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166013$10447 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174551$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:166013$10447_Y + connect \Y $not$libresoc.v:174551$10481_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166015$10449 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174553$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:166015$10449_Y + connect \Y $not$libresoc.v:174553$10483_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166016$10450 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174554$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:166016$10450_Y + connect \Y $not$libresoc.v:174554$10484_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166018$10452 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174556$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:166018$10452_Y + connect \Y $not$libresoc.v:174556$10486_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166020$10454 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174558$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:166020$10454_Y + connect \Y $not$libresoc.v:174558$10488_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166022$10456 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174560$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:166022$10456_Y + connect \Y $not$libresoc.v:174560$10490_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166025$10459 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174563$10493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166025$10459_Y + connect \Y $not$libresoc.v:174563$10493_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166012$10446 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174550$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:166012$10446_Y + connect \Y $reduce_or$libresoc.v:174550$10480_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166014$10448 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174552$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:166014$10448_Y + connect \Y $reduce_or$libresoc.v:174552$10482_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166017$10451 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174555$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:166017$10451_Y + connect \Y $reduce_or$libresoc.v:174555$10485_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166019$10453 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174557$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:166019$10453_Y + connect \Y $reduce_or$libresoc.v:174557$10487_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166021$10455 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174559$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:166021$10455_Y + connect \Y $reduce_or$libresoc.v:174559$10489_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166023$10457 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174561$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166023$10457_Y + connect \Y $reduce_or$libresoc.v:174561$10491_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166024$10458 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174562$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:166024$10458_Y + connect \Y $reduce_or$libresoc.v:174562$10492_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166026$10460 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174564$10494 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:166026$10460_Y - end - connect \$7 $not$libresoc.v:166011$10445_Y - connect \$12 $reduce_or$libresoc.v:166012$10446_Y - connect \$11 $not$libresoc.v:166013$10447_Y - connect \$16 $reduce_or$libresoc.v:166014$10448_Y - connect \$15 $not$libresoc.v:166015$10449_Y - connect \$1 $not$libresoc.v:166016$10450_Y - connect \$20 $reduce_or$libresoc.v:166017$10451_Y - connect \$19 $not$libresoc.v:166018$10452_Y - connect \$24 $reduce_or$libresoc.v:166019$10453_Y - connect \$23 $not$libresoc.v:166020$10454_Y - connect \$28 $reduce_or$libresoc.v:166021$10455_Y - connect \$27 $not$libresoc.v:166022$10456_Y - connect \$31 $reduce_or$libresoc.v:166023$10457_Y - connect \$4 $reduce_or$libresoc.v:166024$10458_Y - connect \$3 $not$libresoc.v:166025$10459_Y - connect \$8 $reduce_or$libresoc.v:166026$10460_Y + connect \Y $reduce_or$libresoc.v:174564$10494_Y + end + connect \$7 $not$libresoc.v:174549$10479_Y + connect \$12 $reduce_or$libresoc.v:174550$10480_Y + connect \$11 $not$libresoc.v:174551$10481_Y + connect \$16 $reduce_or$libresoc.v:174552$10482_Y + connect \$15 $not$libresoc.v:174553$10483_Y + connect \$1 $not$libresoc.v:174554$10484_Y + connect \$20 $reduce_or$libresoc.v:174555$10485_Y + connect \$19 $not$libresoc.v:174556$10486_Y + connect \$24 $reduce_or$libresoc.v:174557$10487_Y + connect \$23 $not$libresoc.v:174558$10488_Y + connect \$28 $reduce_or$libresoc.v:174559$10489_Y + connect \$27 $not$libresoc.v:174560$10490_Y + connect \$31 $reduce_or$libresoc.v:174561$10491_Y + connect \$4 $reduce_or$libresoc.v:174562$10492_Y + connect \$3 $not$libresoc.v:174563$10493_Y + connect \$8 $reduce_or$libresoc.v:174564$10494_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -344282,316 +358946,316 @@ module \ppick$211 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:166042.1-166072.10" +attribute \src "libresoc.v:174580.1-174610.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:166063.17-166063.89" - wire width 2 $not$libresoc.v:166063$10461_Y - attribute \src "libresoc.v:166065.17-166065.91" - wire $not$libresoc.v:166065$10463_Y - attribute \src "libresoc.v:166064.17-166064.103" - wire $reduce_or$libresoc.v:166064$10462_Y - attribute \src "libresoc.v:166066.17-166066.89" - wire $reduce_or$libresoc.v:166066$10464_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174601.17-174601.89" + wire width 2 $not$libresoc.v:174601$10495_Y + attribute \src "libresoc.v:174603.17-174603.91" + wire $not$libresoc.v:174603$10497_Y + attribute \src "libresoc.v:174602.17-174602.103" + wire $reduce_or$libresoc.v:174602$10496_Y + attribute \src "libresoc.v:174604.17-174604.89" + wire $reduce_or$libresoc.v:174604$10498_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166063$10461 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174601$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:166063$10461_Y + connect \Y $not$libresoc.v:174601$10495_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166065$10463 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174603$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166065$10463_Y + connect \Y $not$libresoc.v:174603$10497_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166064$10462 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174602$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166064$10462_Y + connect \Y $reduce_or$libresoc.v:174602$10496_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166066$10464 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174604$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166066$10464_Y + connect \Y $reduce_or$libresoc.v:174604$10498_Y end - connect \$1 $not$libresoc.v:166063$10461_Y - connect \$4 $reduce_or$libresoc.v:166064$10462_Y - connect \$3 $not$libresoc.v:166065$10463_Y - connect \$7 $reduce_or$libresoc.v:166066$10464_Y + connect \$1 $not$libresoc.v:174601$10495_Y + connect \$4 $reduce_or$libresoc.v:174602$10496_Y + connect \$3 $not$libresoc.v:174603$10497_Y + connect \$7 $reduce_or$libresoc.v:174604$10498_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:166076.1-166097.10" +attribute \src "libresoc.v:174614.1-174635.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:166091.17-166091.89" - wire $not$libresoc.v:166091$10465_Y - attribute \src "libresoc.v:166092.17-166092.89" - wire $reduce_or$libresoc.v:166092$10466_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174629.17-174629.89" + wire $not$libresoc.v:174629$10499_Y + attribute \src "libresoc.v:174630.17-174630.89" + wire $reduce_or$libresoc.v:174630$10500_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166091$10465 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174629$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:166091$10465_Y + connect \Y $not$libresoc.v:174629$10499_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166092$10466 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174630$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166092$10466_Y + connect \Y $reduce_or$libresoc.v:174630$10500_Y end - connect \$1 $not$libresoc.v:166091$10465_Y - connect \$3 $reduce_or$libresoc.v:166092$10466_Y + connect \$1 $not$libresoc.v:174629$10499_Y + connect \$3 $reduce_or$libresoc.v:174630$10500_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:166101.1-166122.10" +attribute \src "libresoc.v:174639.1-174660.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:166116.17-166116.89" - wire $not$libresoc.v:166116$10467_Y - attribute \src "libresoc.v:166117.17-166117.89" - wire $reduce_or$libresoc.v:166117$10468_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174654.17-174654.89" + wire $not$libresoc.v:174654$10501_Y + attribute \src "libresoc.v:174655.17-174655.89" + wire $reduce_or$libresoc.v:174655$10502_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166116$10467 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174654$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:166116$10467_Y + connect \Y $not$libresoc.v:174654$10501_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166117$10468 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174655$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166117$10468_Y + connect \Y $reduce_or$libresoc.v:174655$10502_Y end - connect \$1 $not$libresoc.v:166116$10467_Y - connect \$3 $reduce_or$libresoc.v:166117$10468_Y + connect \$1 $not$libresoc.v:174654$10501_Y + connect \$3 $reduce_or$libresoc.v:174655$10502_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:166126.1-166147.10" +attribute \src "libresoc.v:174664.1-174685.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:166141.17-166141.89" - wire $not$libresoc.v:166141$10469_Y - attribute \src "libresoc.v:166142.17-166142.89" - wire $reduce_or$libresoc.v:166142$10470_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174679.17-174679.89" + wire $not$libresoc.v:174679$10503_Y + attribute \src "libresoc.v:174680.17-174680.89" + wire $reduce_or$libresoc.v:174680$10504_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166141$10469 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174679$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:166141$10469_Y + connect \Y $not$libresoc.v:174679$10503_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166142$10470 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174680$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166142$10470_Y + connect \Y $reduce_or$libresoc.v:174680$10504_Y end - connect \$1 $not$libresoc.v:166141$10469_Y - connect \$3 $reduce_or$libresoc.v:166142$10470_Y + connect \$1 $not$libresoc.v:174679$10503_Y + connect \$3 $reduce_or$libresoc.v:174680$10504_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:166151.1-166190.10" +attribute \src "libresoc.v:174689.1-174728.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:166178.17-166178.91" - wire $not$libresoc.v:166178$10471_Y - attribute \src "libresoc.v:166180.17-166180.89" - wire width 3 $not$libresoc.v:166180$10473_Y - attribute \src "libresoc.v:166182.17-166182.91" - wire $not$libresoc.v:166182$10475_Y - attribute \src "libresoc.v:166179.18-166179.90" - wire $reduce_or$libresoc.v:166179$10472_Y - attribute \src "libresoc.v:166181.17-166181.103" - wire $reduce_or$libresoc.v:166181$10474_Y - attribute \src "libresoc.v:166183.17-166183.105" - wire $reduce_or$libresoc.v:166183$10476_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174716.17-174716.91" + wire $not$libresoc.v:174716$10505_Y + attribute \src "libresoc.v:174718.17-174718.89" + wire width 3 $not$libresoc.v:174718$10507_Y + attribute \src "libresoc.v:174720.17-174720.91" + wire $not$libresoc.v:174720$10509_Y + attribute \src "libresoc.v:174717.18-174717.90" + wire $reduce_or$libresoc.v:174717$10506_Y + attribute \src "libresoc.v:174719.17-174719.103" + wire $reduce_or$libresoc.v:174719$10508_Y + attribute \src "libresoc.v:174721.17-174721.105" + wire $reduce_or$libresoc.v:174721$10510_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166178$10471 + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174716$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:166178$10471_Y + connect \Y $not$libresoc.v:174716$10505_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166180$10473 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174718$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:166180$10473_Y + connect \Y $not$libresoc.v:174718$10507_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166182$10475 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174720$10509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166182$10475_Y + connect \Y $not$libresoc.v:174720$10509_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166179$10472 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174717$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166179$10472_Y + connect \Y $reduce_or$libresoc.v:174717$10506_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166181$10474 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174719$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166181$10474_Y + connect \Y $reduce_or$libresoc.v:174719$10508_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166183$10476 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174721$10510 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166183$10476_Y - end - connect \$7 $not$libresoc.v:166178$10471_Y - connect \$11 $reduce_or$libresoc.v:166179$10472_Y - connect \$1 $not$libresoc.v:166180$10473_Y - connect \$4 $reduce_or$libresoc.v:166181$10474_Y - connect \$3 $not$libresoc.v:166182$10475_Y - connect \$8 $reduce_or$libresoc.v:166183$10476_Y + connect \Y $reduce_or$libresoc.v:174721$10510_Y + end + connect \$7 $not$libresoc.v:174716$10505_Y + connect \$11 $reduce_or$libresoc.v:174717$10506_Y + connect \$1 $not$libresoc.v:174718$10507_Y + connect \$4 $reduce_or$libresoc.v:174719$10508_Y + connect \$3 $not$libresoc.v:174720$10509_Y + connect \$8 $reduce_or$libresoc.v:174721$10510_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -344599,346 +359263,346 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:166194.1-166224.10" +attribute \src "libresoc.v:174732.1-174762.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" attribute \generator "nMigen" module \rdpick_FAST_fast2 - attribute \src "libresoc.v:166215.17-166215.89" - wire width 2 $not$libresoc.v:166215$10477_Y - attribute \src "libresoc.v:166217.17-166217.91" - wire $not$libresoc.v:166217$10479_Y - attribute \src "libresoc.v:166216.17-166216.103" - wire $reduce_or$libresoc.v:166216$10478_Y - attribute \src "libresoc.v:166218.17-166218.89" - wire $reduce_or$libresoc.v:166218$10480_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174753.17-174753.89" + wire width 2 $not$libresoc.v:174753$10511_Y + attribute \src "libresoc.v:174755.17-174755.91" + wire $not$libresoc.v:174755$10513_Y + attribute \src "libresoc.v:174754.17-174754.103" + wire $reduce_or$libresoc.v:174754$10512_Y + attribute \src "libresoc.v:174756.17-174756.89" + wire $reduce_or$libresoc.v:174756$10514_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166215$10477 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174753$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:166215$10477_Y + connect \Y $not$libresoc.v:174753$10511_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166217$10479 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174755$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166217$10479_Y + connect \Y $not$libresoc.v:174755$10513_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166216$10478 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174754$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166216$10478_Y + connect \Y $reduce_or$libresoc.v:174754$10512_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166218$10480 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174756$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166218$10480_Y + connect \Y $reduce_or$libresoc.v:174756$10514_Y end - connect \$1 $not$libresoc.v:166215$10477_Y - connect \$4 $reduce_or$libresoc.v:166216$10478_Y - connect \$3 $not$libresoc.v:166217$10479_Y - connect \$7 $reduce_or$libresoc.v:166218$10480_Y + connect \$1 $not$libresoc.v:174753$10511_Y + connect \$4 $reduce_or$libresoc.v:174754$10512_Y + connect \$3 $not$libresoc.v:174755$10513_Y + connect \$7 $reduce_or$libresoc.v:174756$10514_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:166228.1-166321.10" +attribute \src "libresoc.v:174766.1-174859.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" attribute \generator "nMigen" module \rdpick_INT_ra - attribute \src "libresoc.v:166291.17-166291.91" - wire $not$libresoc.v:166291$10481_Y - attribute \src "libresoc.v:166293.18-166293.93" - wire $not$libresoc.v:166293$10483_Y - attribute \src "libresoc.v:166295.18-166295.93" - wire $not$libresoc.v:166295$10485_Y - attribute \src "libresoc.v:166296.17-166296.89" - wire width 9 $not$libresoc.v:166296$10486_Y - attribute \src "libresoc.v:166298.18-166298.93" - wire $not$libresoc.v:166298$10488_Y - attribute \src "libresoc.v:166300.18-166300.93" - wire $not$libresoc.v:166300$10490_Y - attribute \src "libresoc.v:166302.18-166302.93" - wire $not$libresoc.v:166302$10492_Y - attribute \src "libresoc.v:166304.18-166304.93" - wire $not$libresoc.v:166304$10494_Y - attribute \src "libresoc.v:166307.17-166307.91" - wire $not$libresoc.v:166307$10497_Y - attribute \src "libresoc.v:166292.18-166292.106" - wire $reduce_or$libresoc.v:166292$10482_Y - attribute \src "libresoc.v:166294.18-166294.106" - wire $reduce_or$libresoc.v:166294$10484_Y - attribute \src "libresoc.v:166297.18-166297.106" - wire $reduce_or$libresoc.v:166297$10487_Y - attribute \src "libresoc.v:166299.18-166299.106" - wire $reduce_or$libresoc.v:166299$10489_Y - attribute \src "libresoc.v:166301.18-166301.106" - wire $reduce_or$libresoc.v:166301$10491_Y - attribute \src "libresoc.v:166303.18-166303.106" - wire $reduce_or$libresoc.v:166303$10493_Y - attribute \src "libresoc.v:166305.18-166305.90" - wire $reduce_or$libresoc.v:166305$10495_Y - attribute \src "libresoc.v:166306.17-166306.103" - wire $reduce_or$libresoc.v:166306$10496_Y - attribute \src "libresoc.v:166308.17-166308.105" - wire $reduce_or$libresoc.v:166308$10498_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174829.17-174829.91" + wire $not$libresoc.v:174829$10515_Y + attribute \src "libresoc.v:174831.18-174831.93" + wire $not$libresoc.v:174831$10517_Y + attribute \src "libresoc.v:174833.18-174833.93" + wire $not$libresoc.v:174833$10519_Y + attribute \src "libresoc.v:174834.17-174834.89" + wire width 9 $not$libresoc.v:174834$10520_Y + attribute \src "libresoc.v:174836.18-174836.93" + wire $not$libresoc.v:174836$10522_Y + attribute \src "libresoc.v:174838.18-174838.93" + wire $not$libresoc.v:174838$10524_Y + attribute \src "libresoc.v:174840.18-174840.93" + wire $not$libresoc.v:174840$10526_Y + attribute \src "libresoc.v:174842.18-174842.93" + wire $not$libresoc.v:174842$10528_Y + attribute \src "libresoc.v:174845.17-174845.91" + wire $not$libresoc.v:174845$10531_Y + attribute \src "libresoc.v:174830.18-174830.106" + wire $reduce_or$libresoc.v:174830$10516_Y + attribute \src "libresoc.v:174832.18-174832.106" + wire $reduce_or$libresoc.v:174832$10518_Y + attribute \src "libresoc.v:174835.18-174835.106" + wire $reduce_or$libresoc.v:174835$10521_Y + attribute \src "libresoc.v:174837.18-174837.106" + wire $reduce_or$libresoc.v:174837$10523_Y + attribute \src "libresoc.v:174839.18-174839.106" + wire $reduce_or$libresoc.v:174839$10525_Y + attribute \src "libresoc.v:174841.18-174841.106" + wire $reduce_or$libresoc.v:174841$10527_Y + attribute \src "libresoc.v:174843.18-174843.90" + wire $reduce_or$libresoc.v:174843$10529_Y + attribute \src "libresoc.v:174844.17-174844.103" + wire $reduce_or$libresoc.v:174844$10530_Y + attribute \src "libresoc.v:174846.17-174846.105" + wire $reduce_or$libresoc.v:174846$10532_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 9 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 9 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 9 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 9 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166291$10481 + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174829$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:166291$10481_Y + connect \Y $not$libresoc.v:174829$10515_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166293$10483 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174831$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:166293$10483_Y + connect \Y $not$libresoc.v:174831$10517_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166295$10485 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174833$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:166295$10485_Y + connect \Y $not$libresoc.v:174833$10519_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166296$10486 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174834$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 9 connect \A \i - connect \Y $not$libresoc.v:166296$10486_Y + connect \Y $not$libresoc.v:174834$10520_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166298$10488 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174836$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:166298$10488_Y + connect \Y $not$libresoc.v:174836$10522_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166300$10490 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174838$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:166300$10490_Y + connect \Y $not$libresoc.v:174838$10524_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166302$10492 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174840$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:166302$10492_Y + connect \Y $not$libresoc.v:174840$10526_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166304$10494 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174842$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:166304$10494_Y + connect \Y $not$libresoc.v:174842$10528_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166307$10497 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174845$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166307$10497_Y + connect \Y $not$libresoc.v:174845$10531_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166292$10482 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174830$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:166292$10482_Y + connect \Y $reduce_or$libresoc.v:174830$10516_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166294$10484 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174832$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:166294$10484_Y + connect \Y $reduce_or$libresoc.v:174832$10518_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166297$10487 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174835$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:166297$10487_Y + connect \Y $reduce_or$libresoc.v:174835$10521_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166299$10489 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174837$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:166299$10489_Y + connect \Y $reduce_or$libresoc.v:174837$10523_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166301$10491 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174839$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:166301$10491_Y + connect \Y $reduce_or$libresoc.v:174839$10525_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166303$10493 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174841$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:166303$10493_Y + connect \Y $reduce_or$libresoc.v:174841$10527_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166305$10495 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174843$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166305$10495_Y + connect \Y $reduce_or$libresoc.v:174843$10529_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166306$10496 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174844$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166306$10496_Y + connect \Y $reduce_or$libresoc.v:174844$10530_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166308$10498 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174846$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166308$10498_Y - end - connect \$7 $not$libresoc.v:166291$10481_Y - connect \$12 $reduce_or$libresoc.v:166292$10482_Y - connect \$11 $not$libresoc.v:166293$10483_Y - connect \$16 $reduce_or$libresoc.v:166294$10484_Y - connect \$15 $not$libresoc.v:166295$10485_Y - connect \$1 $not$libresoc.v:166296$10486_Y - connect \$20 $reduce_or$libresoc.v:166297$10487_Y - connect \$19 $not$libresoc.v:166298$10488_Y - connect \$24 $reduce_or$libresoc.v:166299$10489_Y - connect \$23 $not$libresoc.v:166300$10490_Y - connect \$28 $reduce_or$libresoc.v:166301$10491_Y - connect \$27 $not$libresoc.v:166302$10492_Y - connect \$32 $reduce_or$libresoc.v:166303$10493_Y - connect \$31 $not$libresoc.v:166304$10494_Y - connect \$35 $reduce_or$libresoc.v:166305$10495_Y - connect \$4 $reduce_or$libresoc.v:166306$10496_Y - connect \$3 $not$libresoc.v:166307$10497_Y - connect \$8 $reduce_or$libresoc.v:166308$10498_Y + connect \Y $reduce_or$libresoc.v:174846$10532_Y + end + connect \$7 $not$libresoc.v:174829$10515_Y + connect \$12 $reduce_or$libresoc.v:174830$10516_Y + connect \$11 $not$libresoc.v:174831$10517_Y + connect \$16 $reduce_or$libresoc.v:174832$10518_Y + connect \$15 $not$libresoc.v:174833$10519_Y + connect \$1 $not$libresoc.v:174834$10520_Y + connect \$20 $reduce_or$libresoc.v:174835$10521_Y + connect \$19 $not$libresoc.v:174836$10522_Y + connect \$24 $reduce_or$libresoc.v:174837$10523_Y + connect \$23 $not$libresoc.v:174838$10524_Y + connect \$28 $reduce_or$libresoc.v:174839$10525_Y + connect \$27 $not$libresoc.v:174840$10526_Y + connect \$32 $reduce_or$libresoc.v:174841$10527_Y + connect \$31 $not$libresoc.v:174842$10528_Y + connect \$35 $reduce_or$libresoc.v:174843$10529_Y + connect \$4 $reduce_or$libresoc.v:174844$10530_Y + connect \$3 $not$libresoc.v:174845$10531_Y + connect \$8 $reduce_or$libresoc.v:174846$10532_Y connect \en_o \$35 connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t8 \$31 @@ -344952,243 +359616,243 @@ module \rdpick_INT_ra connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:166325.1-166409.10" +attribute \src "libresoc.v:174863.1-174947.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" attribute \generator "nMigen" module \rdpick_INT_rb - attribute \src "libresoc.v:166382.17-166382.91" - wire $not$libresoc.v:166382$10499_Y - attribute \src "libresoc.v:166384.18-166384.93" - wire $not$libresoc.v:166384$10501_Y - attribute \src "libresoc.v:166386.18-166386.93" - wire $not$libresoc.v:166386$10503_Y - attribute \src "libresoc.v:166387.17-166387.89" - wire width 8 $not$libresoc.v:166387$10504_Y - attribute \src "libresoc.v:166389.18-166389.93" - wire $not$libresoc.v:166389$10506_Y - attribute \src "libresoc.v:166391.18-166391.93" - wire $not$libresoc.v:166391$10508_Y - attribute \src "libresoc.v:166393.18-166393.93" - wire $not$libresoc.v:166393$10510_Y - attribute \src "libresoc.v:166396.17-166396.91" - wire $not$libresoc.v:166396$10513_Y - attribute \src "libresoc.v:166383.18-166383.106" - wire $reduce_or$libresoc.v:166383$10500_Y - attribute \src "libresoc.v:166385.18-166385.106" - wire $reduce_or$libresoc.v:166385$10502_Y - attribute \src "libresoc.v:166388.18-166388.106" - wire $reduce_or$libresoc.v:166388$10505_Y - attribute \src "libresoc.v:166390.18-166390.106" - wire $reduce_or$libresoc.v:166390$10507_Y - attribute \src "libresoc.v:166392.18-166392.106" - wire $reduce_or$libresoc.v:166392$10509_Y - attribute \src "libresoc.v:166394.18-166394.90" - wire $reduce_or$libresoc.v:166394$10511_Y - attribute \src "libresoc.v:166395.17-166395.103" - wire $reduce_or$libresoc.v:166395$10512_Y - attribute \src "libresoc.v:166397.17-166397.105" - wire $reduce_or$libresoc.v:166397$10514_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174920.17-174920.91" + wire $not$libresoc.v:174920$10533_Y + attribute \src "libresoc.v:174922.18-174922.93" + wire $not$libresoc.v:174922$10535_Y + attribute \src "libresoc.v:174924.18-174924.93" + wire $not$libresoc.v:174924$10537_Y + attribute \src "libresoc.v:174925.17-174925.89" + wire width 8 $not$libresoc.v:174925$10538_Y + attribute \src "libresoc.v:174927.18-174927.93" + wire $not$libresoc.v:174927$10540_Y + attribute \src "libresoc.v:174929.18-174929.93" + wire $not$libresoc.v:174929$10542_Y + attribute \src "libresoc.v:174931.18-174931.93" + wire $not$libresoc.v:174931$10544_Y + attribute \src "libresoc.v:174934.17-174934.91" + wire $not$libresoc.v:174934$10547_Y + attribute \src "libresoc.v:174921.18-174921.106" + wire $reduce_or$libresoc.v:174921$10534_Y + attribute \src "libresoc.v:174923.18-174923.106" + wire $reduce_or$libresoc.v:174923$10536_Y + attribute \src "libresoc.v:174926.18-174926.106" + wire $reduce_or$libresoc.v:174926$10539_Y + attribute \src "libresoc.v:174928.18-174928.106" + wire $reduce_or$libresoc.v:174928$10541_Y + attribute \src "libresoc.v:174930.18-174930.106" + wire $reduce_or$libresoc.v:174930$10543_Y + attribute \src "libresoc.v:174932.18-174932.90" + wire $reduce_or$libresoc.v:174932$10545_Y + attribute \src "libresoc.v:174933.17-174933.103" + wire $reduce_or$libresoc.v:174933$10546_Y + attribute \src "libresoc.v:174935.17-174935.105" + wire $reduce_or$libresoc.v:174935$10548_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166382$10499 + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174920$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:166382$10499_Y + connect \Y $not$libresoc.v:174920$10533_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166384$10501 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174922$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:166384$10501_Y + connect \Y $not$libresoc.v:174922$10535_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166386$10503 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174924$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:166386$10503_Y + connect \Y $not$libresoc.v:174924$10537_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166387$10504 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174925$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A \i - connect \Y $not$libresoc.v:166387$10504_Y + connect \Y $not$libresoc.v:174925$10538_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166389$10506 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174927$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:166389$10506_Y + connect \Y $not$libresoc.v:174927$10540_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166391$10508 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174929$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:166391$10508_Y + connect \Y $not$libresoc.v:174929$10542_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166393$10510 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174931$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:166393$10510_Y + connect \Y $not$libresoc.v:174931$10544_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166396$10513 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174934$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166396$10513_Y + connect \Y $not$libresoc.v:174934$10547_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166383$10500 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174921$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:166383$10500_Y + connect \Y $reduce_or$libresoc.v:174921$10534_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166385$10502 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174923$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:166385$10502_Y + connect \Y $reduce_or$libresoc.v:174923$10536_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166388$10505 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174926$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:166388$10505_Y + connect \Y $reduce_or$libresoc.v:174926$10539_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166390$10507 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174928$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:166390$10507_Y + connect \Y $reduce_or$libresoc.v:174928$10541_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166392$10509 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174930$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:166392$10509_Y + connect \Y $reduce_or$libresoc.v:174930$10543_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166394$10511 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174932$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166394$10511_Y + connect \Y $reduce_or$libresoc.v:174932$10545_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166395$10512 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174933$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166395$10512_Y + connect \Y $reduce_or$libresoc.v:174933$10546_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166397$10514 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174935$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166397$10514_Y - end - connect \$7 $not$libresoc.v:166382$10499_Y - connect \$12 $reduce_or$libresoc.v:166383$10500_Y - connect \$11 $not$libresoc.v:166384$10501_Y - connect \$16 $reduce_or$libresoc.v:166385$10502_Y - connect \$15 $not$libresoc.v:166386$10503_Y - connect \$1 $not$libresoc.v:166387$10504_Y - connect \$20 $reduce_or$libresoc.v:166388$10505_Y - connect \$19 $not$libresoc.v:166389$10506_Y - connect \$24 $reduce_or$libresoc.v:166390$10507_Y - connect \$23 $not$libresoc.v:166391$10508_Y - connect \$28 $reduce_or$libresoc.v:166392$10509_Y - connect \$27 $not$libresoc.v:166393$10510_Y - connect \$31 $reduce_or$libresoc.v:166394$10511_Y - connect \$4 $reduce_or$libresoc.v:166395$10512_Y - connect \$3 $not$libresoc.v:166396$10513_Y - connect \$8 $reduce_or$libresoc.v:166397$10514_Y + connect \Y $reduce_or$libresoc.v:174935$10548_Y + end + connect \$7 $not$libresoc.v:174920$10533_Y + connect \$12 $reduce_or$libresoc.v:174921$10534_Y + connect \$11 $not$libresoc.v:174922$10535_Y + connect \$16 $reduce_or$libresoc.v:174923$10536_Y + connect \$15 $not$libresoc.v:174924$10537_Y + connect \$1 $not$libresoc.v:174925$10538_Y + connect \$20 $reduce_or$libresoc.v:174926$10539_Y + connect \$19 $not$libresoc.v:174927$10540_Y + connect \$24 $reduce_or$libresoc.v:174928$10541_Y + connect \$23 $not$libresoc.v:174929$10542_Y + connect \$28 $reduce_or$libresoc.v:174930$10543_Y + connect \$27 $not$libresoc.v:174931$10544_Y + connect \$31 $reduce_or$libresoc.v:174932$10545_Y + connect \$4 $reduce_or$libresoc.v:174933$10546_Y + connect \$3 $not$libresoc.v:174934$10547_Y + connect \$8 $reduce_or$libresoc.v:174935$10548_Y connect \en_o \$31 connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t7 \$27 @@ -345201,224 +359865,224 @@ module \rdpick_INT_rb connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:166413.1-166443.10" +attribute \src "libresoc.v:174951.1-174981.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" attribute \generator "nMigen" module \rdpick_INT_rc - attribute \src "libresoc.v:166434.17-166434.89" - wire width 2 $not$libresoc.v:166434$10515_Y - attribute \src "libresoc.v:166436.17-166436.91" - wire $not$libresoc.v:166436$10517_Y - attribute \src "libresoc.v:166435.17-166435.103" - wire $reduce_or$libresoc.v:166435$10516_Y - attribute \src "libresoc.v:166437.17-166437.89" - wire $reduce_or$libresoc.v:166437$10518_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:174972.17-174972.89" + wire width 2 $not$libresoc.v:174972$10549_Y + attribute \src "libresoc.v:174974.17-174974.91" + wire $not$libresoc.v:174974$10551_Y + attribute \src "libresoc.v:174973.17-174973.103" + wire $reduce_or$libresoc.v:174973$10550_Y + attribute \src "libresoc.v:174975.17-174975.89" + wire $reduce_or$libresoc.v:174975$10552_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166434$10515 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:174972$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:166434$10515_Y + connect \Y $not$libresoc.v:174972$10549_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166436$10517 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:174974$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166436$10517_Y + connect \Y $not$libresoc.v:174974$10551_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166435$10516 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:174973$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166435$10516_Y + connect \Y $reduce_or$libresoc.v:174973$10550_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166437$10518 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:174975$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166437$10518_Y + connect \Y $reduce_or$libresoc.v:174975$10552_Y end - connect \$1 $not$libresoc.v:166434$10515_Y - connect \$4 $reduce_or$libresoc.v:166435$10516_Y - connect \$3 $not$libresoc.v:166436$10517_Y - connect \$7 $reduce_or$libresoc.v:166437$10518_Y + connect \$1 $not$libresoc.v:174972$10549_Y + connect \$4 $reduce_or$libresoc.v:174973$10550_Y + connect \$3 $not$libresoc.v:174974$10551_Y + connect \$7 $reduce_or$libresoc.v:174975$10552_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:166447.1-166468.10" +attribute \src "libresoc.v:174985.1-175006.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:166462.17-166462.89" - wire $not$libresoc.v:166462$10519_Y - attribute \src "libresoc.v:166463.17-166463.89" - wire $reduce_or$libresoc.v:166463$10520_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:175000.17-175000.89" + wire $not$libresoc.v:175000$10553_Y + attribute \src "libresoc.v:175001.17-175001.89" + wire $reduce_or$libresoc.v:175001$10554_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166462$10519 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:175000$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:166462$10519_Y + connect \Y $not$libresoc.v:175000$10553_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166463$10520 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:175001$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166463$10520_Y + connect \Y $reduce_or$libresoc.v:175001$10554_Y end - connect \$1 $not$libresoc.v:166462$10519_Y - connect \$3 $reduce_or$libresoc.v:166463$10520_Y + connect \$1 $not$libresoc.v:175000$10553_Y + connect \$3 $reduce_or$libresoc.v:175001$10554_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:166472.1-166511.10" +attribute \src "libresoc.v:175010.1-175049.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:166499.17-166499.91" - wire $not$libresoc.v:166499$10521_Y - attribute \src "libresoc.v:166501.17-166501.89" - wire width 3 $not$libresoc.v:166501$10523_Y - attribute \src "libresoc.v:166503.17-166503.91" - wire $not$libresoc.v:166503$10525_Y - attribute \src "libresoc.v:166500.18-166500.90" - wire $reduce_or$libresoc.v:166500$10522_Y - attribute \src "libresoc.v:166502.17-166502.103" - wire $reduce_or$libresoc.v:166502$10524_Y - attribute \src "libresoc.v:166504.17-166504.105" - wire $reduce_or$libresoc.v:166504$10526_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:175037.17-175037.91" + wire $not$libresoc.v:175037$10555_Y + attribute \src "libresoc.v:175039.17-175039.89" + wire width 3 $not$libresoc.v:175039$10557_Y + attribute \src "libresoc.v:175041.17-175041.91" + wire $not$libresoc.v:175041$10559_Y + attribute \src "libresoc.v:175038.18-175038.90" + wire $reduce_or$libresoc.v:175038$10556_Y + attribute \src "libresoc.v:175040.17-175040.103" + wire $reduce_or$libresoc.v:175040$10558_Y + attribute \src "libresoc.v:175042.17-175042.105" + wire $reduce_or$libresoc.v:175042$10560_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166499$10521 + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:175037$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:166499$10521_Y + connect \Y $not$libresoc.v:175037$10555_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166501$10523 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:175039$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:166501$10523_Y + connect \Y $not$libresoc.v:175039$10557_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166503$10525 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:175041$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166503$10525_Y + connect \Y $not$libresoc.v:175041$10559_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166500$10522 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:175038$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166500$10522_Y + connect \Y $reduce_or$libresoc.v:175038$10556_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166502$10524 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:175040$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166502$10524_Y + connect \Y $reduce_or$libresoc.v:175040$10558_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166504$10526 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:175042$10560 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166504$10526_Y - end - connect \$7 $not$libresoc.v:166499$10521_Y - connect \$11 $reduce_or$libresoc.v:166500$10522_Y - connect \$1 $not$libresoc.v:166501$10523_Y - connect \$4 $reduce_or$libresoc.v:166502$10524_Y - connect \$3 $not$libresoc.v:166503$10525_Y - connect \$8 $reduce_or$libresoc.v:166504$10526_Y + connect \Y $reduce_or$libresoc.v:175042$10560_Y + end + connect \$7 $not$libresoc.v:175037$10555_Y + connect \$11 $reduce_or$libresoc.v:175038$10556_Y + connect \$1 $not$libresoc.v:175039$10557_Y + connect \$4 $reduce_or$libresoc.v:175040$10558_Y + connect \$3 $not$libresoc.v:175041$10559_Y + connect \$8 $reduce_or$libresoc.v:175042$10560_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -345426,233 +360090,233 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:166515.1-166536.10" +attribute \src "libresoc.v:175053.1-175074.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:166530.17-166530.89" - wire $not$libresoc.v:166530$10527_Y - attribute \src "libresoc.v:166531.17-166531.89" - wire $reduce_or$libresoc.v:166531$10528_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:175068.17-175068.89" + wire $not$libresoc.v:175068$10561_Y + attribute \src "libresoc.v:175069.17-175069.89" + wire $reduce_or$libresoc.v:175069$10562_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166530$10527 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:175068$10561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:166530$10527_Y + connect \Y $not$libresoc.v:175068$10561_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166531$10528 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:175069$10562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166531$10528_Y + connect \Y $reduce_or$libresoc.v:175069$10562_Y end - connect \$1 $not$libresoc.v:166530$10527_Y - connect \$3 $reduce_or$libresoc.v:166531$10528_Y + connect \$1 $not$libresoc.v:175068$10561_Y + connect \$3 $reduce_or$libresoc.v:175069$10562_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:166540.1-166606.10" +attribute \src "libresoc.v:175078.1-175144.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:166585.17-166585.91" - wire $not$libresoc.v:166585$10529_Y - attribute \src "libresoc.v:166587.18-166587.93" - wire $not$libresoc.v:166587$10531_Y - attribute \src "libresoc.v:166589.18-166589.93" - wire $not$libresoc.v:166589$10533_Y - attribute \src "libresoc.v:166590.17-166590.89" - wire width 6 $not$libresoc.v:166590$10534_Y - attribute \src "libresoc.v:166592.18-166592.93" - wire $not$libresoc.v:166592$10536_Y - attribute \src "libresoc.v:166595.17-166595.91" - wire $not$libresoc.v:166595$10539_Y - attribute \src "libresoc.v:166586.18-166586.106" - wire $reduce_or$libresoc.v:166586$10530_Y - attribute \src "libresoc.v:166588.18-166588.106" - wire $reduce_or$libresoc.v:166588$10532_Y - attribute \src "libresoc.v:166591.18-166591.106" - wire $reduce_or$libresoc.v:166591$10535_Y - attribute \src "libresoc.v:166593.18-166593.90" - wire $reduce_or$libresoc.v:166593$10537_Y - attribute \src "libresoc.v:166594.17-166594.103" - wire $reduce_or$libresoc.v:166594$10538_Y - attribute \src "libresoc.v:166596.17-166596.105" - wire $reduce_or$libresoc.v:166596$10540_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:175123.17-175123.91" + wire $not$libresoc.v:175123$10563_Y + attribute \src "libresoc.v:175125.18-175125.93" + wire $not$libresoc.v:175125$10565_Y + attribute \src "libresoc.v:175127.18-175127.93" + wire $not$libresoc.v:175127$10567_Y + attribute \src "libresoc.v:175128.17-175128.89" + wire width 6 $not$libresoc.v:175128$10568_Y + attribute \src "libresoc.v:175130.18-175130.93" + wire $not$libresoc.v:175130$10570_Y + attribute \src "libresoc.v:175133.17-175133.91" + wire $not$libresoc.v:175133$10573_Y + attribute \src "libresoc.v:175124.18-175124.106" + wire $reduce_or$libresoc.v:175124$10564_Y + attribute \src "libresoc.v:175126.18-175126.106" + wire $reduce_or$libresoc.v:175126$10566_Y + attribute \src "libresoc.v:175129.18-175129.106" + wire $reduce_or$libresoc.v:175129$10569_Y + attribute \src "libresoc.v:175131.18-175131.90" + wire $reduce_or$libresoc.v:175131$10571_Y + attribute \src "libresoc.v:175132.17-175132.103" + wire $reduce_or$libresoc.v:175132$10572_Y + attribute \src "libresoc.v:175134.17-175134.105" + wire $reduce_or$libresoc.v:175134$10574_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 6 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166585$10529 + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:175123$10563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:166585$10529_Y + connect \Y $not$libresoc.v:175123$10563_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166587$10531 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:175125$10565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:166587$10531_Y + connect \Y $not$libresoc.v:175125$10565_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166589$10533 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:175127$10567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:166589$10533_Y + connect \Y $not$libresoc.v:175127$10567_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166590$10534 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:175128$10568 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:166590$10534_Y + connect \Y $not$libresoc.v:175128$10568_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166592$10536 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:175130$10570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:166592$10536_Y + connect \Y $not$libresoc.v:175130$10570_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166595$10539 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:175133$10573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:166595$10539_Y + connect \Y $not$libresoc.v:175133$10573_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166586$10530 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:175124$10564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:166586$10530_Y + connect \Y $reduce_or$libresoc.v:175124$10564_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166588$10532 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:175126$10566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:166588$10532_Y + connect \Y $reduce_or$libresoc.v:175126$10566_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166591$10535 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:175129$10569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:166591$10535_Y + connect \Y $reduce_or$libresoc.v:175129$10569_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166593$10537 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:175131$10571 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:166593$10537_Y + connect \Y $reduce_or$libresoc.v:175131$10571_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166594$10538 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:175132$10572 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166594$10538_Y + connect \Y $reduce_or$libresoc.v:175132$10572_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166596$10540 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:175134$10574 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166596$10540_Y - end - connect \$7 $not$libresoc.v:166585$10529_Y - connect \$12 $reduce_or$libresoc.v:166586$10530_Y - connect \$11 $not$libresoc.v:166587$10531_Y - connect \$16 $reduce_or$libresoc.v:166588$10532_Y - connect \$15 $not$libresoc.v:166589$10533_Y - connect \$1 $not$libresoc.v:166590$10534_Y - connect \$20 $reduce_or$libresoc.v:166591$10535_Y - connect \$19 $not$libresoc.v:166592$10536_Y - connect \$23 $reduce_or$libresoc.v:166593$10537_Y - connect \$4 $reduce_or$libresoc.v:166594$10538_Y - connect \$3 $not$libresoc.v:166595$10539_Y - connect \$8 $reduce_or$libresoc.v:166596$10540_Y + connect \Y $reduce_or$libresoc.v:175134$10574_Y + end + connect \$7 $not$libresoc.v:175123$10563_Y + connect \$12 $reduce_or$libresoc.v:175124$10564_Y + connect \$11 $not$libresoc.v:175125$10565_Y + connect \$16 $reduce_or$libresoc.v:175126$10566_Y + connect \$15 $not$libresoc.v:175127$10567_Y + connect \$1 $not$libresoc.v:175128$10568_Y + connect \$20 $reduce_or$libresoc.v:175129$10569_Y + connect \$19 $not$libresoc.v:175130$10570_Y + connect \$23 $reduce_or$libresoc.v:175131$10571_Y + connect \$4 $reduce_or$libresoc.v:175132$10572_Y + connect \$3 $not$libresoc.v:175133$10573_Y + connect \$8 $reduce_or$libresoc.v:175134$10574_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -345663,177 +360327,177 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:166610.1-167081.10" +attribute \src "libresoc.v:175148.1-175619.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:166611.7-166611.20" + attribute \src "libresoc.v:175149.7-175149.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166941.3-166980.6" - wire width 4 $0\r0__data_o$next[3:0]$10596 - attribute \src "libresoc.v:166696.3-166697.37" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $0\r0__data_o$next[3:0]$10630 + attribute \src "libresoc.v:175234.3-175235.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:167011.3-167050.6" - wire width 4 $0\r20__data_o$next[3:0]$10610 - attribute \src "libresoc.v:166694.3-166695.39" + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $0\r20__data_o$next[3:0]$10644 + attribute \src "libresoc.v:175232.3-175233.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:166774.3-166800.6" - wire width 4 $0\reg$next[3:0]$10562 - attribute \src "libresoc.v:166692.3-166693.25" + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $0\reg$next[3:0]$10596 + attribute \src "libresoc.v:175230.3-175231.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:166704.3-166743.6" - wire width 4 $0\src10__data_o$next[3:0]$10553 - attribute \src "libresoc.v:166702.3-166703.43" + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $0\src10__data_o$next[3:0]$10587 + attribute \src "libresoc.v:175240.3-175241.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:166801.3-166840.6" - wire width 4 $0\src20__data_o$next[3:0]$10568 - attribute \src "libresoc.v:166700.3-166701.43" + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $0\src20__data_o$next[3:0]$10602 + attribute \src "libresoc.v:175238.3-175239.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:166871.3-166910.6" - wire width 4 $0\src30__data_o$next[3:0]$10582 - attribute \src "libresoc.v:166698.3-166699.43" + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $0\src30__data_o$next[3:0]$10616 + attribute \src "libresoc.v:175236.3-175237.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:166981.3-167010.6" - wire $0\wr_detect$10[0:0]$10604 - attribute \src "libresoc.v:167051.3-167080.6" - wire $0\wr_detect$13[0:0]$10618 - attribute \src "libresoc.v:166841.3-166870.6" - wire $0\wr_detect$4[0:0]$10576 - attribute \src "libresoc.v:166911.3-166940.6" - wire $0\wr_detect$7[0:0]$10590 - attribute \src "libresoc.v:166744.3-166773.6" + attribute \src "libresoc.v:175519.3-175548.6" + wire $0\wr_detect$10[0:0]$10638 + attribute \src "libresoc.v:175589.3-175618.6" + wire $0\wr_detect$13[0:0]$10652 + attribute \src "libresoc.v:175379.3-175408.6" + wire $0\wr_detect$4[0:0]$10610 + attribute \src "libresoc.v:175449.3-175478.6" + wire $0\wr_detect$7[0:0]$10624 + attribute \src "libresoc.v:175282.3-175311.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:166941.3-166980.6" - wire width 4 $1\r0__data_o$next[3:0]$10597 - attribute \src "libresoc.v:166636.13-166636.30" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $1\r0__data_o$next[3:0]$10631 + attribute \src "libresoc.v:175174.13-175174.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:167011.3-167050.6" - wire width 4 $1\r20__data_o$next[3:0]$10611 - attribute \src "libresoc.v:166643.13-166643.31" + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $1\r20__data_o$next[3:0]$10645 + attribute \src "libresoc.v:175181.13-175181.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:166774.3-166800.6" - wire width 4 $1\reg$next[3:0]$10563 - attribute \src "libresoc.v:166649.13-166649.25" + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $1\reg$next[3:0]$10597 + attribute \src "libresoc.v:175187.13-175187.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:166704.3-166743.6" - wire width 4 $1\src10__data_o$next[3:0]$10554 - attribute \src "libresoc.v:166654.13-166654.33" + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $1\src10__data_o$next[3:0]$10588 + attribute \src "libresoc.v:175192.13-175192.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:166801.3-166840.6" - wire width 4 $1\src20__data_o$next[3:0]$10569 - attribute \src "libresoc.v:166661.13-166661.33" + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $1\src20__data_o$next[3:0]$10603 + attribute \src "libresoc.v:175199.13-175199.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:166871.3-166910.6" - wire width 4 $1\src30__data_o$next[3:0]$10583 - attribute \src "libresoc.v:166668.13-166668.33" + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $1\src30__data_o$next[3:0]$10617 + attribute \src "libresoc.v:175206.13-175206.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:166981.3-167010.6" - wire $1\wr_detect$10[0:0]$10605 - attribute \src "libresoc.v:167051.3-167080.6" - wire $1\wr_detect$13[0:0]$10619 - attribute \src "libresoc.v:166841.3-166870.6" - wire $1\wr_detect$4[0:0]$10577 - attribute \src "libresoc.v:166911.3-166940.6" - wire $1\wr_detect$7[0:0]$10591 - attribute \src "libresoc.v:166744.3-166773.6" + attribute \src "libresoc.v:175519.3-175548.6" + wire $1\wr_detect$10[0:0]$10639 + attribute \src "libresoc.v:175589.3-175618.6" + wire $1\wr_detect$13[0:0]$10653 + attribute \src "libresoc.v:175379.3-175408.6" + wire $1\wr_detect$4[0:0]$10611 + attribute \src "libresoc.v:175449.3-175478.6" + wire $1\wr_detect$7[0:0]$10625 + attribute \src "libresoc.v:175282.3-175311.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:166941.3-166980.6" - wire width 4 $2\r0__data_o$next[3:0]$10598 - attribute \src "libresoc.v:167011.3-167050.6" - wire width 4 $2\r20__data_o$next[3:0]$10612 - attribute \src "libresoc.v:166774.3-166800.6" - wire width 4 $2\reg$next[3:0]$10564 - attribute \src "libresoc.v:166704.3-166743.6" - wire width 4 $2\src10__data_o$next[3:0]$10555 - attribute \src "libresoc.v:166801.3-166840.6" - wire width 4 $2\src20__data_o$next[3:0]$10570 - attribute \src "libresoc.v:166871.3-166910.6" - wire width 4 $2\src30__data_o$next[3:0]$10584 - attribute \src "libresoc.v:166981.3-167010.6" - wire $2\wr_detect$10[0:0]$10606 - attribute \src "libresoc.v:167051.3-167080.6" - wire $2\wr_detect$13[0:0]$10620 - attribute \src "libresoc.v:166841.3-166870.6" - wire $2\wr_detect$4[0:0]$10578 - attribute \src "libresoc.v:166911.3-166940.6" - wire $2\wr_detect$7[0:0]$10592 - attribute \src "libresoc.v:166744.3-166773.6" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $2\r0__data_o$next[3:0]$10632 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $2\r20__data_o$next[3:0]$10646 + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $2\reg$next[3:0]$10598 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $2\src10__data_o$next[3:0]$10589 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $2\src20__data_o$next[3:0]$10604 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $2\src30__data_o$next[3:0]$10618 + attribute \src "libresoc.v:175519.3-175548.6" + wire $2\wr_detect$10[0:0]$10640 + attribute \src "libresoc.v:175589.3-175618.6" + wire $2\wr_detect$13[0:0]$10654 + attribute \src "libresoc.v:175379.3-175408.6" + wire $2\wr_detect$4[0:0]$10612 + attribute \src "libresoc.v:175449.3-175478.6" + wire $2\wr_detect$7[0:0]$10626 + attribute \src "libresoc.v:175282.3-175311.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:166941.3-166980.6" - wire width 4 $3\r0__data_o$next[3:0]$10599 - attribute \src "libresoc.v:167011.3-167050.6" - wire width 4 $3\r20__data_o$next[3:0]$10613 - attribute \src "libresoc.v:166774.3-166800.6" - wire width 4 $3\reg$next[3:0]$10565 - attribute \src "libresoc.v:166704.3-166743.6" - wire width 4 $3\src10__data_o$next[3:0]$10556 - attribute \src "libresoc.v:166801.3-166840.6" - wire width 4 $3\src20__data_o$next[3:0]$10571 - attribute \src "libresoc.v:166871.3-166910.6" - wire width 4 $3\src30__data_o$next[3:0]$10585 - attribute \src "libresoc.v:166981.3-167010.6" - wire $3\wr_detect$10[0:0]$10607 - attribute \src "libresoc.v:167051.3-167080.6" - wire $3\wr_detect$13[0:0]$10621 - attribute \src "libresoc.v:166841.3-166870.6" - wire $3\wr_detect$4[0:0]$10579 - attribute \src "libresoc.v:166911.3-166940.6" - wire $3\wr_detect$7[0:0]$10593 - attribute \src "libresoc.v:166744.3-166773.6" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $3\r0__data_o$next[3:0]$10633 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $3\r20__data_o$next[3:0]$10647 + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $3\reg$next[3:0]$10599 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $3\src10__data_o$next[3:0]$10590 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $3\src20__data_o$next[3:0]$10605 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $3\src30__data_o$next[3:0]$10619 + attribute \src "libresoc.v:175519.3-175548.6" + wire $3\wr_detect$10[0:0]$10641 + attribute \src "libresoc.v:175589.3-175618.6" + wire $3\wr_detect$13[0:0]$10655 + attribute \src "libresoc.v:175379.3-175408.6" + wire $3\wr_detect$4[0:0]$10613 + attribute \src "libresoc.v:175449.3-175478.6" + wire $3\wr_detect$7[0:0]$10627 + attribute \src "libresoc.v:175282.3-175311.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:166941.3-166980.6" - wire width 4 $4\r0__data_o$next[3:0]$10600 - attribute \src "libresoc.v:167011.3-167050.6" - wire width 4 $4\r20__data_o$next[3:0]$10614 - attribute \src "libresoc.v:166774.3-166800.6" - wire width 4 $4\reg$next[3:0]$10566 - attribute \src "libresoc.v:166704.3-166743.6" - wire width 4 $4\src10__data_o$next[3:0]$10557 - attribute \src "libresoc.v:166801.3-166840.6" - wire width 4 $4\src20__data_o$next[3:0]$10572 - attribute \src "libresoc.v:166871.3-166910.6" - wire width 4 $4\src30__data_o$next[3:0]$10586 - attribute \src "libresoc.v:166981.3-167010.6" - wire $4\wr_detect$10[0:0]$10608 - attribute \src "libresoc.v:167051.3-167080.6" - wire $4\wr_detect$13[0:0]$10622 - attribute \src "libresoc.v:166841.3-166870.6" - wire $4\wr_detect$4[0:0]$10580 - attribute \src "libresoc.v:166911.3-166940.6" - wire $4\wr_detect$7[0:0]$10594 - attribute \src "libresoc.v:166744.3-166773.6" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $4\r0__data_o$next[3:0]$10634 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $4\r20__data_o$next[3:0]$10648 + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $4\reg$next[3:0]$10600 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $4\src10__data_o$next[3:0]$10591 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $4\src20__data_o$next[3:0]$10606 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $4\src30__data_o$next[3:0]$10620 + attribute \src "libresoc.v:175519.3-175548.6" + wire $4\wr_detect$10[0:0]$10642 + attribute \src "libresoc.v:175589.3-175618.6" + wire $4\wr_detect$13[0:0]$10656 + attribute \src "libresoc.v:175379.3-175408.6" + wire $4\wr_detect$4[0:0]$10614 + attribute \src "libresoc.v:175449.3-175478.6" + wire $4\wr_detect$7[0:0]$10628 + attribute \src "libresoc.v:175282.3-175311.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:166941.3-166980.6" - wire width 4 $5\r0__data_o$next[3:0]$10601 - attribute \src "libresoc.v:167011.3-167050.6" - wire width 4 $5\r20__data_o$next[3:0]$10615 - attribute \src "libresoc.v:166704.3-166743.6" - wire width 4 $5\src10__data_o$next[3:0]$10558 - attribute \src "libresoc.v:166801.3-166840.6" - wire width 4 $5\src20__data_o$next[3:0]$10573 - attribute \src "libresoc.v:166871.3-166910.6" - wire width 4 $5\src30__data_o$next[3:0]$10587 - attribute \src "libresoc.v:166941.3-166980.6" - wire width 4 $6\r0__data_o$next[3:0]$10602 - attribute \src "libresoc.v:167011.3-167050.6" - wire width 4 $6\r20__data_o$next[3:0]$10616 - attribute \src "libresoc.v:166704.3-166743.6" - wire width 4 $6\src10__data_o$next[3:0]$10559 - attribute \src "libresoc.v:166801.3-166840.6" - wire width 4 $6\src20__data_o$next[3:0]$10574 - attribute \src "libresoc.v:166871.3-166910.6" - wire width 4 $6\src30__data_o$next[3:0]$10588 - attribute \src "libresoc.v:166687.17-166687.104" - wire $not$libresoc.v:166687$10541_Y - attribute \src "libresoc.v:166688.18-166688.105" - wire $not$libresoc.v:166688$10542_Y - attribute \src "libresoc.v:166689.17-166689.100" - wire $not$libresoc.v:166689$10543_Y - attribute \src "libresoc.v:166690.17-166690.103" - wire $not$libresoc.v:166690$10544_Y - attribute \src "libresoc.v:166691.17-166691.103" - wire $not$libresoc.v:166691$10545_Y + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $5\r0__data_o$next[3:0]$10635 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $5\r20__data_o$next[3:0]$10649 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $5\src10__data_o$next[3:0]$10592 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $5\src20__data_o$next[3:0]$10607 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $5\src30__data_o$next[3:0]$10621 + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $6\r0__data_o$next[3:0]$10636 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $6\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $6\src10__data_o$next[3:0]$10593 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $6\src20__data_o$next[3:0]$10608 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $6\src30__data_o$next[3:0]$10622 + attribute \src "libresoc.v:175225.17-175225.104" + wire $not$libresoc.v:175225$10575_Y + attribute \src "libresoc.v:175226.18-175226.105" + wire $not$libresoc.v:175226$10576_Y + attribute \src "libresoc.v:175227.17-175227.100" + wire $not$libresoc.v:175227$10577_Y + attribute \src "libresoc.v:175228.17-175228.103" + wire $not$libresoc.v:175228$10578_Y + attribute \src "libresoc.v:175229.17-175229.103" + wire $not$libresoc.v:175229$10579_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -345844,57 +360508,57 @@ module \reg_0 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest20__wen - attribute \src "libresoc.v:166611.7-166611.15" + attribute \src "libresoc.v:175149.7-175149.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r20__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src10__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src30__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -345907,152 +360571,152 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166687$10541 + cell $not $not$libresoc.v:175225$10575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:166687$10541_Y + connect \Y $not$libresoc.v:175225$10575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166688$10542 + cell $not $not$libresoc.v:175226$10576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:166688$10542_Y + connect \Y $not$libresoc.v:175226$10576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166689$10543 + cell $not $not$libresoc.v:175227$10577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:166689$10543_Y + connect \Y $not$libresoc.v:175227$10577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166690$10544 + cell $not $not$libresoc.v:175228$10578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:166690$10544_Y + connect \Y $not$libresoc.v:175228$10578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166691$10545 + cell $not $not$libresoc.v:175229$10579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:166691$10545_Y + connect \Y $not$libresoc.v:175229$10579_Y end - attribute \src "libresoc.v:166611.7-166611.20" - process $proc$libresoc.v:166611$10623 + attribute \src "libresoc.v:175149.7-175149.20" + process $proc$libresoc.v:175149$10657 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166636.13-166636.30" - process $proc$libresoc.v:166636$10624 + attribute \src "libresoc.v:175174.13-175174.30" + process $proc$libresoc.v:175174$10658 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:166643.13-166643.31" - process $proc$libresoc.v:166643$10625 + attribute \src "libresoc.v:175181.13-175181.31" + process $proc$libresoc.v:175181$10659 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:166649.13-166649.25" - process $proc$libresoc.v:166649$10626 + attribute \src "libresoc.v:175187.13-175187.25" + process $proc$libresoc.v:175187$10660 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:166654.13-166654.33" - process $proc$libresoc.v:166654$10627 + attribute \src "libresoc.v:175192.13-175192.33" + process $proc$libresoc.v:175192$10661 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:166661.13-166661.33" - process $proc$libresoc.v:166661$10628 + attribute \src "libresoc.v:175199.13-175199.33" + process $proc$libresoc.v:175199$10662 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:166668.13-166668.33" - process $proc$libresoc.v:166668$10629 + attribute \src "libresoc.v:175206.13-175206.33" + process $proc$libresoc.v:175206$10663 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:166692.3-166693.25" - process $proc$libresoc.v:166692$10546 + attribute \src "libresoc.v:175230.3-175231.25" + process $proc$libresoc.v:175230$10580 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:166694.3-166695.39" - process $proc$libresoc.v:166694$10547 + attribute \src "libresoc.v:175232.3-175233.39" + process $proc$libresoc.v:175232$10581 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:166696.3-166697.37" - process $proc$libresoc.v:166696$10548 + attribute \src "libresoc.v:175234.3-175235.37" + process $proc$libresoc.v:175234$10582 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:166698.3-166699.43" - process $proc$libresoc.v:166698$10549 + attribute \src "libresoc.v:175236.3-175237.43" + process $proc$libresoc.v:175236$10583 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:166700.3-166701.43" - process $proc$libresoc.v:166700$10550 + attribute \src "libresoc.v:175238.3-175239.43" + process $proc$libresoc.v:175238$10584 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:166702.3-166703.43" - process $proc$libresoc.v:166702$10551 + attribute \src "libresoc.v:175240.3-175241.43" + process $proc$libresoc.v:175240$10585 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:166704.3-166743.6" - process $proc$libresoc.v:166704$10552 + attribute \src "libresoc.v:175242.3-175281.6" + process $proc$libresoc.v:175242$10586 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10553 $6\src10__data_o$next[3:0]$10559 - attribute \src "libresoc.v:166705.5-166705.29" + assign $0\src10__data_o$next[3:0]$10587 $6\src10__data_o$next[3:0]$10593 + attribute \src "libresoc.v:175243.5-175243.29" switch \initial - attribute \src "libresoc.v:166705.9-166705.17" + attribute \src "libresoc.v:175243.9-175243.17" case 1'1 case end @@ -346064,66 +360728,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10554 $5\src10__data_o$next[3:0]$10558 + assign $1\src10__data_o$next[3:0]$10588 $5\src10__data_o$next[3:0]$10592 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10555 \dest10__data_i + assign $2\src10__data_o$next[3:0]$10589 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10555 4'0000 + assign $2\src10__data_o$next[3:0]$10589 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10556 \dest20__data_i + assign $3\src10__data_o$next[3:0]$10590 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10556 $2\src10__data_o$next[3:0]$10555 + assign $3\src10__data_o$next[3:0]$10590 $2\src10__data_o$next[3:0]$10589 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10557 \w0__data_i + assign $4\src10__data_o$next[3:0]$10591 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10557 $3\src10__data_o$next[3:0]$10556 + assign $4\src10__data_o$next[3:0]$10591 $3\src10__data_o$next[3:0]$10590 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10558 \reg + assign $5\src10__data_o$next[3:0]$10592 \reg case - assign $5\src10__data_o$next[3:0]$10558 $4\src10__data_o$next[3:0]$10557 + assign $5\src10__data_o$next[3:0]$10592 $4\src10__data_o$next[3:0]$10591 end case - assign $1\src10__data_o$next[3:0]$10554 4'0000 + assign $1\src10__data_o$next[3:0]$10588 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10559 4'0000 + assign $6\src10__data_o$next[3:0]$10593 4'0000 case - assign $6\src10__data_o$next[3:0]$10559 $1\src10__data_o$next[3:0]$10554 + assign $6\src10__data_o$next[3:0]$10593 $1\src10__data_o$next[3:0]$10588 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10553 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10587 end - attribute \src "libresoc.v:166744.3-166773.6" - process $proc$libresoc.v:166744$10560 + attribute \src "libresoc.v:175282.3-175311.6" + process $proc$libresoc.v:175282$10594 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:166745.5-166745.29" + attribute \src "libresoc.v:175283.5-175283.29" switch \initial - attribute \src "libresoc.v:166745.9-166745.17" + attribute \src "libresoc.v:175283.9-175283.17" case 1'1 case end @@ -346169,17 +360833,17 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:166774.3-166800.6" - process $proc$libresoc.v:166774$10561 + attribute \src "libresoc.v:175312.3-175338.6" + process $proc$libresoc.v:175312$10595 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10562 $4\reg$next[3:0]$10566 - attribute \src "libresoc.v:166775.5-166775.29" + assign $0\reg$next[3:0]$10596 $4\reg$next[3:0]$10600 + attribute \src "libresoc.v:175313.5-175313.29" switch \initial - attribute \src "libresoc.v:166775.9-166775.17" + attribute \src "libresoc.v:175313.9-175313.17" case 1'1 case end @@ -346188,49 +360852,49 @@ module \reg_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10563 \dest10__data_i + assign $1\reg$next[3:0]$10597 \dest10__data_i case - assign $1\reg$next[3:0]$10563 \reg + assign $1\reg$next[3:0]$10597 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10564 \dest20__data_i + assign $2\reg$next[3:0]$10598 \dest20__data_i case - assign $2\reg$next[3:0]$10564 $1\reg$next[3:0]$10563 + assign $2\reg$next[3:0]$10598 $1\reg$next[3:0]$10597 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10565 \w0__data_i + assign $3\reg$next[3:0]$10599 \w0__data_i case - assign $3\reg$next[3:0]$10565 $2\reg$next[3:0]$10564 + assign $3\reg$next[3:0]$10599 $2\reg$next[3:0]$10598 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10566 4'0000 + assign $4\reg$next[3:0]$10600 4'0000 case - assign $4\reg$next[3:0]$10566 $3\reg$next[3:0]$10565 + assign $4\reg$next[3:0]$10600 $3\reg$next[3:0]$10599 end sync always - update \reg$next $0\reg$next[3:0]$10562 + update \reg$next $0\reg$next[3:0]$10596 end - attribute \src "libresoc.v:166801.3-166840.6" - process $proc$libresoc.v:166801$10567 + attribute \src "libresoc.v:175339.3-175378.6" + process $proc$libresoc.v:175339$10601 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10568 $6\src20__data_o$next[3:0]$10574 - attribute \src "libresoc.v:166802.5-166802.29" + assign $0\src20__data_o$next[3:0]$10602 $6\src20__data_o$next[3:0]$10608 + attribute \src "libresoc.v:175340.5-175340.29" switch \initial - attribute \src "libresoc.v:166802.9-166802.17" + attribute \src "libresoc.v:175340.9-175340.17" case 1'1 case end @@ -346242,66 +360906,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10569 $5\src20__data_o$next[3:0]$10573 + assign $1\src20__data_o$next[3:0]$10603 $5\src20__data_o$next[3:0]$10607 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10570 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10604 \dest10__data_i case - assign $2\src20__data_o$next[3:0]$10570 4'0000 + assign $2\src20__data_o$next[3:0]$10604 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10571 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10605 \dest20__data_i case - assign $3\src20__data_o$next[3:0]$10571 $2\src20__data_o$next[3:0]$10570 + assign $3\src20__data_o$next[3:0]$10605 $2\src20__data_o$next[3:0]$10604 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10572 \w0__data_i + assign $4\src20__data_o$next[3:0]$10606 \w0__data_i case - assign $4\src20__data_o$next[3:0]$10572 $3\src20__data_o$next[3:0]$10571 + assign $4\src20__data_o$next[3:0]$10606 $3\src20__data_o$next[3:0]$10605 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10573 \reg + assign $5\src20__data_o$next[3:0]$10607 \reg case - assign $5\src20__data_o$next[3:0]$10573 $4\src20__data_o$next[3:0]$10572 + assign $5\src20__data_o$next[3:0]$10607 $4\src20__data_o$next[3:0]$10606 end case - assign $1\src20__data_o$next[3:0]$10569 4'0000 + assign $1\src20__data_o$next[3:0]$10603 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10574 4'0000 + assign $6\src20__data_o$next[3:0]$10608 4'0000 case - assign $6\src20__data_o$next[3:0]$10574 $1\src20__data_o$next[3:0]$10569 + assign $6\src20__data_o$next[3:0]$10608 $1\src20__data_o$next[3:0]$10603 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10568 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10602 end - attribute \src "libresoc.v:166841.3-166870.6" - process $proc$libresoc.v:166841$10575 + attribute \src "libresoc.v:175379.3-175408.6" + process $proc$libresoc.v:175379$10609 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10576 $1\wr_detect$4[0:0]$10577 - attribute \src "libresoc.v:166842.5-166842.29" + assign $0\wr_detect$4[0:0]$10610 $1\wr_detect$4[0:0]$10611 + attribute \src "libresoc.v:175380.5-175380.29" switch \initial - attribute \src "libresoc.v:166842.9-166842.17" + attribute \src "libresoc.v:175380.9-175380.17" case 1'1 case end @@ -346313,49 +360977,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10577 $4\wr_detect$4[0:0]$10580 + assign $1\wr_detect$4[0:0]$10611 $4\wr_detect$4[0:0]$10614 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10578 1'1 + assign $2\wr_detect$4[0:0]$10612 1'1 case - assign $2\wr_detect$4[0:0]$10578 1'0 + assign $2\wr_detect$4[0:0]$10612 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10579 1'1 + assign $3\wr_detect$4[0:0]$10613 1'1 case - assign $3\wr_detect$4[0:0]$10579 $2\wr_detect$4[0:0]$10578 + assign $3\wr_detect$4[0:0]$10613 $2\wr_detect$4[0:0]$10612 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10580 1'1 + assign $4\wr_detect$4[0:0]$10614 1'1 case - assign $4\wr_detect$4[0:0]$10580 $3\wr_detect$4[0:0]$10579 + assign $4\wr_detect$4[0:0]$10614 $3\wr_detect$4[0:0]$10613 end case - assign $1\wr_detect$4[0:0]$10577 1'0 + assign $1\wr_detect$4[0:0]$10611 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10576 + update \wr_detect$4 $0\wr_detect$4[0:0]$10610 end - attribute \src "libresoc.v:166871.3-166910.6" - process $proc$libresoc.v:166871$10581 + attribute \src "libresoc.v:175409.3-175448.6" + process $proc$libresoc.v:175409$10615 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10582 $6\src30__data_o$next[3:0]$10588 - attribute \src "libresoc.v:166872.5-166872.29" + assign $0\src30__data_o$next[3:0]$10616 $6\src30__data_o$next[3:0]$10622 + attribute \src "libresoc.v:175410.5-175410.29" switch \initial - attribute \src "libresoc.v:166872.9-166872.17" + attribute \src "libresoc.v:175410.9-175410.17" case 1'1 case end @@ -346367,66 +361031,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10583 $5\src30__data_o$next[3:0]$10587 + assign $1\src30__data_o$next[3:0]$10617 $5\src30__data_o$next[3:0]$10621 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10584 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10618 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10584 4'0000 + assign $2\src30__data_o$next[3:0]$10618 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10585 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10619 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10585 $2\src30__data_o$next[3:0]$10584 + assign $3\src30__data_o$next[3:0]$10619 $2\src30__data_o$next[3:0]$10618 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10586 \w0__data_i + assign $4\src30__data_o$next[3:0]$10620 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10586 $3\src30__data_o$next[3:0]$10585 + assign $4\src30__data_o$next[3:0]$10620 $3\src30__data_o$next[3:0]$10619 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10587 \reg + assign $5\src30__data_o$next[3:0]$10621 \reg case - assign $5\src30__data_o$next[3:0]$10587 $4\src30__data_o$next[3:0]$10586 + assign $5\src30__data_o$next[3:0]$10621 $4\src30__data_o$next[3:0]$10620 end case - assign $1\src30__data_o$next[3:0]$10583 4'0000 + assign $1\src30__data_o$next[3:0]$10617 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10588 4'0000 + assign $6\src30__data_o$next[3:0]$10622 4'0000 case - assign $6\src30__data_o$next[3:0]$10588 $1\src30__data_o$next[3:0]$10583 + assign $6\src30__data_o$next[3:0]$10622 $1\src30__data_o$next[3:0]$10617 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10582 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10616 end - attribute \src "libresoc.v:166911.3-166940.6" - process $proc$libresoc.v:166911$10589 + attribute \src "libresoc.v:175449.3-175478.6" + process $proc$libresoc.v:175449$10623 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10590 $1\wr_detect$7[0:0]$10591 - attribute \src "libresoc.v:166912.5-166912.29" + assign $0\wr_detect$7[0:0]$10624 $1\wr_detect$7[0:0]$10625 + attribute \src "libresoc.v:175450.5-175450.29" switch \initial - attribute \src "libresoc.v:166912.9-166912.17" + attribute \src "libresoc.v:175450.9-175450.17" case 1'1 case end @@ -346438,49 +361102,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10591 $4\wr_detect$7[0:0]$10594 + assign $1\wr_detect$7[0:0]$10625 $4\wr_detect$7[0:0]$10628 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10592 1'1 + assign $2\wr_detect$7[0:0]$10626 1'1 case - assign $2\wr_detect$7[0:0]$10592 1'0 + assign $2\wr_detect$7[0:0]$10626 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10593 1'1 + assign $3\wr_detect$7[0:0]$10627 1'1 case - assign $3\wr_detect$7[0:0]$10593 $2\wr_detect$7[0:0]$10592 + assign $3\wr_detect$7[0:0]$10627 $2\wr_detect$7[0:0]$10626 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10594 1'1 + assign $4\wr_detect$7[0:0]$10628 1'1 case - assign $4\wr_detect$7[0:0]$10594 $3\wr_detect$7[0:0]$10593 + assign $4\wr_detect$7[0:0]$10628 $3\wr_detect$7[0:0]$10627 end case - assign $1\wr_detect$7[0:0]$10591 1'0 + assign $1\wr_detect$7[0:0]$10625 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10590 + update \wr_detect$7 $0\wr_detect$7[0:0]$10624 end - attribute \src "libresoc.v:166941.3-166980.6" - process $proc$libresoc.v:166941$10595 + attribute \src "libresoc.v:175479.3-175518.6" + process $proc$libresoc.v:175479$10629 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10596 $6\r0__data_o$next[3:0]$10602 - attribute \src "libresoc.v:166942.5-166942.29" + assign $0\r0__data_o$next[3:0]$10630 $6\r0__data_o$next[3:0]$10636 + attribute \src "libresoc.v:175480.5-175480.29" switch \initial - attribute \src "libresoc.v:166942.9-166942.17" + attribute \src "libresoc.v:175480.9-175480.17" case 1'1 case end @@ -346492,66 +361156,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10597 $5\r0__data_o$next[3:0]$10601 + assign $1\r0__data_o$next[3:0]$10631 $5\r0__data_o$next[3:0]$10635 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10598 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10632 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10598 4'0000 + assign $2\r0__data_o$next[3:0]$10632 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10599 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10633 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10599 $2\r0__data_o$next[3:0]$10598 + assign $3\r0__data_o$next[3:0]$10633 $2\r0__data_o$next[3:0]$10632 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10600 \w0__data_i + assign $4\r0__data_o$next[3:0]$10634 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10600 $3\r0__data_o$next[3:0]$10599 + assign $4\r0__data_o$next[3:0]$10634 $3\r0__data_o$next[3:0]$10633 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10601 \reg + assign $5\r0__data_o$next[3:0]$10635 \reg case - assign $5\r0__data_o$next[3:0]$10601 $4\r0__data_o$next[3:0]$10600 + assign $5\r0__data_o$next[3:0]$10635 $4\r0__data_o$next[3:0]$10634 end case - assign $1\r0__data_o$next[3:0]$10597 4'0000 + assign $1\r0__data_o$next[3:0]$10631 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10602 4'0000 + assign $6\r0__data_o$next[3:0]$10636 4'0000 case - assign $6\r0__data_o$next[3:0]$10602 $1\r0__data_o$next[3:0]$10597 + assign $6\r0__data_o$next[3:0]$10636 $1\r0__data_o$next[3:0]$10631 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10596 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10630 end - attribute \src "libresoc.v:166981.3-167010.6" - process $proc$libresoc.v:166981$10603 + attribute \src "libresoc.v:175519.3-175548.6" + process $proc$libresoc.v:175519$10637 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10604 $1\wr_detect$10[0:0]$10605 - attribute \src "libresoc.v:166982.5-166982.29" + assign $0\wr_detect$10[0:0]$10638 $1\wr_detect$10[0:0]$10639 + attribute \src "libresoc.v:175520.5-175520.29" switch \initial - attribute \src "libresoc.v:166982.9-166982.17" + attribute \src "libresoc.v:175520.9-175520.17" case 1'1 case end @@ -346563,49 +361227,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10605 $4\wr_detect$10[0:0]$10608 + assign $1\wr_detect$10[0:0]$10639 $4\wr_detect$10[0:0]$10642 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10606 1'1 + assign $2\wr_detect$10[0:0]$10640 1'1 case - assign $2\wr_detect$10[0:0]$10606 1'0 + assign $2\wr_detect$10[0:0]$10640 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10607 1'1 + assign $3\wr_detect$10[0:0]$10641 1'1 case - assign $3\wr_detect$10[0:0]$10607 $2\wr_detect$10[0:0]$10606 + assign $3\wr_detect$10[0:0]$10641 $2\wr_detect$10[0:0]$10640 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10608 1'1 + assign $4\wr_detect$10[0:0]$10642 1'1 case - assign $4\wr_detect$10[0:0]$10608 $3\wr_detect$10[0:0]$10607 + assign $4\wr_detect$10[0:0]$10642 $3\wr_detect$10[0:0]$10641 end case - assign $1\wr_detect$10[0:0]$10605 1'0 + assign $1\wr_detect$10[0:0]$10639 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10604 + update \wr_detect$10 $0\wr_detect$10[0:0]$10638 end - attribute \src "libresoc.v:167011.3-167050.6" - process $proc$libresoc.v:167011$10609 + attribute \src "libresoc.v:175549.3-175588.6" + process $proc$libresoc.v:175549$10643 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10610 $6\r20__data_o$next[3:0]$10616 - attribute \src "libresoc.v:167012.5-167012.29" + assign $0\r20__data_o$next[3:0]$10644 $6\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:175550.5-175550.29" switch \initial - attribute \src "libresoc.v:167012.9-167012.17" + attribute \src "libresoc.v:175550.9-175550.17" case 1'1 case end @@ -346617,66 +361281,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r20__data_o$next[3:0]$10611 $5\r20__data_o$next[3:0]$10615 + assign $1\r20__data_o$next[3:0]$10645 $5\r20__data_o$next[3:0]$10649 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r20__data_o$next[3:0]$10612 \dest10__data_i + assign $2\r20__data_o$next[3:0]$10646 \dest10__data_i case - assign $2\r20__data_o$next[3:0]$10612 4'0000 + assign $2\r20__data_o$next[3:0]$10646 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r20__data_o$next[3:0]$10613 \dest20__data_i + assign $3\r20__data_o$next[3:0]$10647 \dest20__data_i case - assign $3\r20__data_o$next[3:0]$10613 $2\r20__data_o$next[3:0]$10612 + assign $3\r20__data_o$next[3:0]$10647 $2\r20__data_o$next[3:0]$10646 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r20__data_o$next[3:0]$10614 \w0__data_i + assign $4\r20__data_o$next[3:0]$10648 \w0__data_i case - assign $4\r20__data_o$next[3:0]$10614 $3\r20__data_o$next[3:0]$10613 + assign $4\r20__data_o$next[3:0]$10648 $3\r20__data_o$next[3:0]$10647 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r20__data_o$next[3:0]$10615 \reg + assign $5\r20__data_o$next[3:0]$10649 \reg case - assign $5\r20__data_o$next[3:0]$10615 $4\r20__data_o$next[3:0]$10614 + assign $5\r20__data_o$next[3:0]$10649 $4\r20__data_o$next[3:0]$10648 end case - assign $1\r20__data_o$next[3:0]$10611 4'0000 + assign $1\r20__data_o$next[3:0]$10645 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r20__data_o$next[3:0]$10616 4'0000 + assign $6\r20__data_o$next[3:0]$10650 4'0000 case - assign $6\r20__data_o$next[3:0]$10616 $1\r20__data_o$next[3:0]$10611 + assign $6\r20__data_o$next[3:0]$10650 $1\r20__data_o$next[3:0]$10645 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10610 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10644 end - attribute \src "libresoc.v:167051.3-167080.6" - process $proc$libresoc.v:167051$10617 + attribute \src "libresoc.v:175589.3-175618.6" + process $proc$libresoc.v:175589$10651 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10618 $1\wr_detect$13[0:0]$10619 - attribute \src "libresoc.v:167052.5-167052.29" + assign $0\wr_detect$13[0:0]$10652 $1\wr_detect$13[0:0]$10653 + attribute \src "libresoc.v:175590.5-175590.29" switch \initial - attribute \src "libresoc.v:167052.9-167052.17" + attribute \src "libresoc.v:175590.9-175590.17" case 1'1 case end @@ -346688,205 +361352,205 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10619 $4\wr_detect$13[0:0]$10622 + assign $1\wr_detect$13[0:0]$10653 $4\wr_detect$13[0:0]$10656 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10620 1'1 + assign $2\wr_detect$13[0:0]$10654 1'1 case - assign $2\wr_detect$13[0:0]$10620 1'0 + assign $2\wr_detect$13[0:0]$10654 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10621 1'1 + assign $3\wr_detect$13[0:0]$10655 1'1 case - assign $3\wr_detect$13[0:0]$10621 $2\wr_detect$13[0:0]$10620 + assign $3\wr_detect$13[0:0]$10655 $2\wr_detect$13[0:0]$10654 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10622 1'1 + assign $4\wr_detect$13[0:0]$10656 1'1 case - assign $4\wr_detect$13[0:0]$10622 $3\wr_detect$13[0:0]$10621 + assign $4\wr_detect$13[0:0]$10656 $3\wr_detect$13[0:0]$10655 end case - assign $1\wr_detect$13[0:0]$10619 1'0 + assign $1\wr_detect$13[0:0]$10653 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10618 + update \wr_detect$13 $0\wr_detect$13[0:0]$10652 end - connect \$9 $not$libresoc.v:166687$10541_Y - connect \$12 $not$libresoc.v:166688$10542_Y - connect \$1 $not$libresoc.v:166689$10543_Y - connect \$3 $not$libresoc.v:166690$10544_Y - connect \$6 $not$libresoc.v:166691$10545_Y + connect \$9 $not$libresoc.v:175225$10575_Y + connect \$12 $not$libresoc.v:175226$10576_Y + connect \$1 $not$libresoc.v:175227$10577_Y + connect \$3 $not$libresoc.v:175228$10578_Y + connect \$6 $not$libresoc.v:175229$10579_Y end -attribute \src "libresoc.v:167085.1-167530.10" +attribute \src "libresoc.v:175623.1-176068.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:167086.7-167086.20" + attribute \src "libresoc.v:175624.7-175624.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167415.3-167460.6" - wire width 2 $0\r0__data_o$next[1:0]$10682 - attribute \src "libresoc.v:167161.3-167162.37" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $0\r0__data_o$next[1:0]$10716 + attribute \src "libresoc.v:175699.3-175700.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:167497.3-167529.6" - wire width 2 $0\reg$next[1:0]$10698 - attribute \src "libresoc.v:167159.3-167160.25" + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $0\reg$next[1:0]$10732 + attribute \src "libresoc.v:175697.3-175698.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:167169.3-167214.6" - wire width 2 $0\src10__data_o$next[1:0]$10640 - attribute \src "libresoc.v:167167.3-167168.43" + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $0\src10__data_o$next[1:0]$10674 + attribute \src "libresoc.v:175705.3-175706.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:167251.3-167296.6" - wire width 2 $0\src20__data_o$next[1:0]$10650 - attribute \src "libresoc.v:167165.3-167166.43" + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $0\src20__data_o$next[1:0]$10684 + attribute \src "libresoc.v:175703.3-175704.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:167333.3-167378.6" - wire width 2 $0\src30__data_o$next[1:0]$10666 - attribute \src "libresoc.v:167163.3-167164.43" + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $0\src30__data_o$next[1:0]$10700 + attribute \src "libresoc.v:175701.3-175702.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:167461.3-167496.6" - wire $0\wr_detect$10[0:0]$10691 - attribute \src "libresoc.v:167297.3-167332.6" - wire $0\wr_detect$4[0:0]$10659 - attribute \src "libresoc.v:167379.3-167414.6" - wire $0\wr_detect$7[0:0]$10675 - attribute \src "libresoc.v:167215.3-167250.6" + attribute \src "libresoc.v:175999.3-176034.6" + wire $0\wr_detect$10[0:0]$10725 + attribute \src "libresoc.v:175835.3-175870.6" + wire $0\wr_detect$4[0:0]$10693 + attribute \src "libresoc.v:175917.3-175952.6" + wire $0\wr_detect$7[0:0]$10709 + attribute \src "libresoc.v:175753.3-175788.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:167415.3-167460.6" - wire width 2 $1\r0__data_o$next[1:0]$10683 - attribute \src "libresoc.v:167113.13-167113.30" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $1\r0__data_o$next[1:0]$10717 + attribute \src "libresoc.v:175651.13-175651.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:167497.3-167529.6" - wire width 2 $1\reg$next[1:0]$10699 - attribute \src "libresoc.v:167119.13-167119.25" + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $1\reg$next[1:0]$10733 + attribute \src "libresoc.v:175657.13-175657.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:167169.3-167214.6" - wire width 2 $1\src10__data_o$next[1:0]$10641 - attribute \src "libresoc.v:167124.13-167124.33" + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $1\src10__data_o$next[1:0]$10675 + attribute \src "libresoc.v:175662.13-175662.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:167251.3-167296.6" - wire width 2 $1\src20__data_o$next[1:0]$10651 - attribute \src "libresoc.v:167131.13-167131.33" + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $1\src20__data_o$next[1:0]$10685 + attribute \src "libresoc.v:175669.13-175669.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:167333.3-167378.6" - wire width 2 $1\src30__data_o$next[1:0]$10667 - attribute \src "libresoc.v:167138.13-167138.33" + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $1\src30__data_o$next[1:0]$10701 + attribute \src "libresoc.v:175676.13-175676.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:167461.3-167496.6" - wire $1\wr_detect$10[0:0]$10692 - attribute \src "libresoc.v:167297.3-167332.6" - wire $1\wr_detect$4[0:0]$10660 - attribute \src "libresoc.v:167379.3-167414.6" - wire $1\wr_detect$7[0:0]$10676 - attribute \src "libresoc.v:167215.3-167250.6" + attribute \src "libresoc.v:175999.3-176034.6" + wire $1\wr_detect$10[0:0]$10726 + attribute \src "libresoc.v:175835.3-175870.6" + wire $1\wr_detect$4[0:0]$10694 + attribute \src "libresoc.v:175917.3-175952.6" + wire $1\wr_detect$7[0:0]$10710 + attribute \src "libresoc.v:175753.3-175788.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:167415.3-167460.6" - wire width 2 $2\r0__data_o$next[1:0]$10684 - attribute \src "libresoc.v:167497.3-167529.6" - wire width 2 $2\reg$next[1:0]$10700 - attribute \src "libresoc.v:167169.3-167214.6" - wire width 2 $2\src10__data_o$next[1:0]$10642 - attribute \src "libresoc.v:167251.3-167296.6" - wire width 2 $2\src20__data_o$next[1:0]$10652 - attribute \src "libresoc.v:167333.3-167378.6" - wire width 2 $2\src30__data_o$next[1:0]$10668 - attribute \src "libresoc.v:167461.3-167496.6" - wire $2\wr_detect$10[0:0]$10693 - attribute \src "libresoc.v:167297.3-167332.6" - wire $2\wr_detect$4[0:0]$10661 - attribute \src "libresoc.v:167379.3-167414.6" - wire $2\wr_detect$7[0:0]$10677 - attribute \src "libresoc.v:167215.3-167250.6" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $2\r0__data_o$next[1:0]$10718 + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $2\reg$next[1:0]$10734 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $2\src10__data_o$next[1:0]$10676 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $2\src20__data_o$next[1:0]$10686 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $2\src30__data_o$next[1:0]$10702 + attribute \src "libresoc.v:175999.3-176034.6" + wire $2\wr_detect$10[0:0]$10727 + attribute \src "libresoc.v:175835.3-175870.6" + wire $2\wr_detect$4[0:0]$10695 + attribute \src "libresoc.v:175917.3-175952.6" + wire $2\wr_detect$7[0:0]$10711 + attribute \src "libresoc.v:175753.3-175788.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:167415.3-167460.6" - wire width 2 $3\r0__data_o$next[1:0]$10685 - attribute \src "libresoc.v:167497.3-167529.6" - wire width 2 $3\reg$next[1:0]$10701 - attribute \src "libresoc.v:167169.3-167214.6" - wire width 2 $3\src10__data_o$next[1:0]$10643 - attribute \src "libresoc.v:167251.3-167296.6" - wire width 2 $3\src20__data_o$next[1:0]$10653 - attribute \src "libresoc.v:167333.3-167378.6" - wire width 2 $3\src30__data_o$next[1:0]$10669 - attribute \src "libresoc.v:167461.3-167496.6" - wire $3\wr_detect$10[0:0]$10694 - attribute \src "libresoc.v:167297.3-167332.6" - wire $3\wr_detect$4[0:0]$10662 - attribute \src "libresoc.v:167379.3-167414.6" - wire $3\wr_detect$7[0:0]$10678 - attribute \src "libresoc.v:167215.3-167250.6" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $3\r0__data_o$next[1:0]$10719 + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $3\reg$next[1:0]$10735 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $3\src10__data_o$next[1:0]$10677 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $3\src20__data_o$next[1:0]$10687 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $3\src30__data_o$next[1:0]$10703 + attribute \src "libresoc.v:175999.3-176034.6" + wire $3\wr_detect$10[0:0]$10728 + attribute \src "libresoc.v:175835.3-175870.6" + wire $3\wr_detect$4[0:0]$10696 + attribute \src "libresoc.v:175917.3-175952.6" + wire $3\wr_detect$7[0:0]$10712 + attribute \src "libresoc.v:175753.3-175788.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:167415.3-167460.6" - wire width 2 $4\r0__data_o$next[1:0]$10686 - attribute \src "libresoc.v:167497.3-167529.6" - wire width 2 $4\reg$next[1:0]$10702 - attribute \src "libresoc.v:167169.3-167214.6" - wire width 2 $4\src10__data_o$next[1:0]$10644 - attribute \src "libresoc.v:167251.3-167296.6" - wire width 2 $4\src20__data_o$next[1:0]$10654 - attribute \src "libresoc.v:167333.3-167378.6" - wire width 2 $4\src30__data_o$next[1:0]$10670 - attribute \src "libresoc.v:167461.3-167496.6" - wire $4\wr_detect$10[0:0]$10695 - attribute \src "libresoc.v:167297.3-167332.6" - wire $4\wr_detect$4[0:0]$10663 - attribute \src "libresoc.v:167379.3-167414.6" - wire $4\wr_detect$7[0:0]$10679 - attribute \src "libresoc.v:167215.3-167250.6" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $4\r0__data_o$next[1:0]$10720 + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $4\reg$next[1:0]$10736 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $4\src10__data_o$next[1:0]$10678 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $4\src20__data_o$next[1:0]$10688 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $4\src30__data_o$next[1:0]$10704 + attribute \src "libresoc.v:175999.3-176034.6" + wire $4\wr_detect$10[0:0]$10729 + attribute \src "libresoc.v:175835.3-175870.6" + wire $4\wr_detect$4[0:0]$10697 + attribute \src "libresoc.v:175917.3-175952.6" + wire $4\wr_detect$7[0:0]$10713 + attribute \src "libresoc.v:175753.3-175788.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:167415.3-167460.6" - wire width 2 $5\r0__data_o$next[1:0]$10687 - attribute \src "libresoc.v:167497.3-167529.6" - wire width 2 $5\reg$next[1:0]$10703 - attribute \src "libresoc.v:167169.3-167214.6" - wire width 2 $5\src10__data_o$next[1:0]$10645 - attribute \src "libresoc.v:167251.3-167296.6" - wire width 2 $5\src20__data_o$next[1:0]$10655 - attribute \src "libresoc.v:167333.3-167378.6" - wire width 2 $5\src30__data_o$next[1:0]$10671 - attribute \src "libresoc.v:167461.3-167496.6" - wire $5\wr_detect$10[0:0]$10696 - attribute \src "libresoc.v:167297.3-167332.6" - wire $5\wr_detect$4[0:0]$10664 - attribute \src "libresoc.v:167379.3-167414.6" - wire $5\wr_detect$7[0:0]$10680 - attribute \src "libresoc.v:167215.3-167250.6" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $5\r0__data_o$next[1:0]$10721 + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $5\reg$next[1:0]$10737 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $5\src10__data_o$next[1:0]$10679 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $5\src20__data_o$next[1:0]$10689 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $5\src30__data_o$next[1:0]$10705 + attribute \src "libresoc.v:175999.3-176034.6" + wire $5\wr_detect$10[0:0]$10730 + attribute \src "libresoc.v:175835.3-175870.6" + wire $5\wr_detect$4[0:0]$10698 + attribute \src "libresoc.v:175917.3-175952.6" + wire $5\wr_detect$7[0:0]$10714 + attribute \src "libresoc.v:175753.3-175788.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:167415.3-167460.6" - wire width 2 $6\r0__data_o$next[1:0]$10688 - attribute \src "libresoc.v:167169.3-167214.6" - wire width 2 $6\src10__data_o$next[1:0]$10646 - attribute \src "libresoc.v:167251.3-167296.6" - wire width 2 $6\src20__data_o$next[1:0]$10656 - attribute \src "libresoc.v:167333.3-167378.6" - wire width 2 $6\src30__data_o$next[1:0]$10672 - attribute \src "libresoc.v:167415.3-167460.6" - wire width 2 $7\r0__data_o$next[1:0]$10689 - attribute \src "libresoc.v:167169.3-167214.6" - wire width 2 $7\src10__data_o$next[1:0]$10647 - attribute \src "libresoc.v:167251.3-167296.6" - wire width 2 $7\src20__data_o$next[1:0]$10657 - attribute \src "libresoc.v:167333.3-167378.6" - wire width 2 $7\src30__data_o$next[1:0]$10673 - attribute \src "libresoc.v:167155.17-167155.104" - wire $not$libresoc.v:167155$10630_Y - attribute \src "libresoc.v:167156.17-167156.100" - wire $not$libresoc.v:167156$10631_Y - attribute \src "libresoc.v:167157.17-167157.103" - wire $not$libresoc.v:167157$10632_Y - attribute \src "libresoc.v:167158.17-167158.103" - wire $not$libresoc.v:167158$10633_Y + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $6\r0__data_o$next[1:0]$10722 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $6\src10__data_o$next[1:0]$10680 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $6\src20__data_o$next[1:0]$10690 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $6\src30__data_o$next[1:0]$10706 + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $7\r0__data_o$next[1:0]$10723 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $7\src10__data_o$next[1:0]$10681 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $7\src20__data_o$next[1:0]$10691 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $7\src30__data_o$next[1:0]$10707 + attribute \src "libresoc.v:175693.17-175693.104" + wire $not$libresoc.v:175693$10664_Y + attribute \src "libresoc.v:175694.17-175694.100" + wire $not$libresoc.v:175694$10665_Y + attribute \src "libresoc.v:175695.17-175695.103" + wire $not$libresoc.v:175695$10666_Y + attribute \src "libresoc.v:175696.17-175696.103" + wire $not$libresoc.v:175696$10667_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -346895,55 +361559,55 @@ module \reg_0$132 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 11 \dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 13 \dest30__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:167086.7-167086.15" + attribute \src "libresoc.v:175624.7-175624.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \r0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r0__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src10__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src30__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -346954,129 +361618,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167155$10630 + cell $not $not$libresoc.v:175693$10664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:167155$10630_Y + connect \Y $not$libresoc.v:175693$10664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167156$10631 + cell $not $not$libresoc.v:175694$10665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:167156$10631_Y + connect \Y $not$libresoc.v:175694$10665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167157$10632 + cell $not $not$libresoc.v:175695$10666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:167157$10632_Y + connect \Y $not$libresoc.v:175695$10666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167158$10633 + cell $not $not$libresoc.v:175696$10667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:167158$10633_Y + connect \Y $not$libresoc.v:175696$10667_Y end - attribute \src "libresoc.v:167086.7-167086.20" - process $proc$libresoc.v:167086$10704 + attribute \src "libresoc.v:175624.7-175624.20" + process $proc$libresoc.v:175624$10738 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167113.13-167113.30" - process $proc$libresoc.v:167113$10705 + attribute \src "libresoc.v:175651.13-175651.30" + process $proc$libresoc.v:175651$10739 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:167119.13-167119.25" - process $proc$libresoc.v:167119$10706 + attribute \src "libresoc.v:175657.13-175657.25" + process $proc$libresoc.v:175657$10740 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:167124.13-167124.33" - process $proc$libresoc.v:167124$10707 + attribute \src "libresoc.v:175662.13-175662.33" + process $proc$libresoc.v:175662$10741 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:167131.13-167131.33" - process $proc$libresoc.v:167131$10708 + attribute \src "libresoc.v:175669.13-175669.33" + process $proc$libresoc.v:175669$10742 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:167138.13-167138.33" - process $proc$libresoc.v:167138$10709 + attribute \src "libresoc.v:175676.13-175676.33" + process $proc$libresoc.v:175676$10743 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:167159.3-167160.25" - process $proc$libresoc.v:167159$10634 + attribute \src "libresoc.v:175697.3-175698.25" + process $proc$libresoc.v:175697$10668 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:167161.3-167162.37" - process $proc$libresoc.v:167161$10635 + attribute \src "libresoc.v:175699.3-175700.37" + process $proc$libresoc.v:175699$10669 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:167163.3-167164.43" - process $proc$libresoc.v:167163$10636 + attribute \src "libresoc.v:175701.3-175702.43" + process $proc$libresoc.v:175701$10670 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:167165.3-167166.43" - process $proc$libresoc.v:167165$10637 + attribute \src "libresoc.v:175703.3-175704.43" + process $proc$libresoc.v:175703$10671 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:167167.3-167168.43" - process $proc$libresoc.v:167167$10638 + attribute \src "libresoc.v:175705.3-175706.43" + process $proc$libresoc.v:175705$10672 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:167169.3-167214.6" - process $proc$libresoc.v:167169$10639 + attribute \src "libresoc.v:175707.3-175752.6" + process $proc$libresoc.v:175707$10673 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$10640 $7\src10__data_o$next[1:0]$10647 - attribute \src "libresoc.v:167170.5-167170.29" + assign $0\src10__data_o$next[1:0]$10674 $7\src10__data_o$next[1:0]$10681 + attribute \src "libresoc.v:175708.5-175708.29" switch \initial - attribute \src "libresoc.v:167170.9-167170.17" + attribute \src "libresoc.v:175708.9-175708.17" case 1'1 case end @@ -347089,75 +361753,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$10641 $6\src10__data_o$next[1:0]$10646 + assign $1\src10__data_o$next[1:0]$10675 $6\src10__data_o$next[1:0]$10680 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$10642 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10676 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$10642 2'00 + assign $2\src10__data_o$next[1:0]$10676 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$10643 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10677 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$10643 $2\src10__data_o$next[1:0]$10642 + assign $3\src10__data_o$next[1:0]$10677 $2\src10__data_o$next[1:0]$10676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$10644 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10678 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$10644 $3\src10__data_o$next[1:0]$10643 + assign $4\src10__data_o$next[1:0]$10678 $3\src10__data_o$next[1:0]$10677 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$10645 \w0__data_i + assign $5\src10__data_o$next[1:0]$10679 \w0__data_i case - assign $5\src10__data_o$next[1:0]$10645 $4\src10__data_o$next[1:0]$10644 + assign $5\src10__data_o$next[1:0]$10679 $4\src10__data_o$next[1:0]$10678 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$10646 \reg + assign $6\src10__data_o$next[1:0]$10680 \reg case - assign $6\src10__data_o$next[1:0]$10646 $5\src10__data_o$next[1:0]$10645 + assign $6\src10__data_o$next[1:0]$10680 $5\src10__data_o$next[1:0]$10679 end case - assign $1\src10__data_o$next[1:0]$10641 2'00 + assign $1\src10__data_o$next[1:0]$10675 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$10647 2'00 + assign $7\src10__data_o$next[1:0]$10681 2'00 case - assign $7\src10__data_o$next[1:0]$10647 $1\src10__data_o$next[1:0]$10641 + assign $7\src10__data_o$next[1:0]$10681 $1\src10__data_o$next[1:0]$10675 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10640 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10674 end - attribute \src "libresoc.v:167215.3-167250.6" - process $proc$libresoc.v:167215$10648 + attribute \src "libresoc.v:175753.3-175788.6" + process $proc$libresoc.v:175753$10682 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:167216.5-167216.29" + attribute \src "libresoc.v:175754.5-175754.29" switch \initial - attribute \src "libresoc.v:167216.9-167216.17" + attribute \src "libresoc.v:175754.9-175754.17" case 1'1 case end @@ -347213,15 +361877,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:167251.3-167296.6" - process $proc$libresoc.v:167251$10649 + attribute \src "libresoc.v:175789.3-175834.6" + process $proc$libresoc.v:175789$10683 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$10650 $7\src20__data_o$next[1:0]$10657 - attribute \src "libresoc.v:167252.5-167252.29" + assign $0\src20__data_o$next[1:0]$10684 $7\src20__data_o$next[1:0]$10691 + attribute \src "libresoc.v:175790.5-175790.29" switch \initial - attribute \src "libresoc.v:167252.9-167252.17" + attribute \src "libresoc.v:175790.9-175790.17" case 1'1 case end @@ -347234,75 +361898,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$10651 $6\src20__data_o$next[1:0]$10656 + assign $1\src20__data_o$next[1:0]$10685 $6\src20__data_o$next[1:0]$10690 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$10652 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10686 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$10652 2'00 + assign $2\src20__data_o$next[1:0]$10686 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$10653 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10687 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$10653 $2\src20__data_o$next[1:0]$10652 + assign $3\src20__data_o$next[1:0]$10687 $2\src20__data_o$next[1:0]$10686 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$10654 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10688 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$10654 $3\src20__data_o$next[1:0]$10653 + assign $4\src20__data_o$next[1:0]$10688 $3\src20__data_o$next[1:0]$10687 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$10655 \w0__data_i + assign $5\src20__data_o$next[1:0]$10689 \w0__data_i case - assign $5\src20__data_o$next[1:0]$10655 $4\src20__data_o$next[1:0]$10654 + assign $5\src20__data_o$next[1:0]$10689 $4\src20__data_o$next[1:0]$10688 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$10656 \reg + assign $6\src20__data_o$next[1:0]$10690 \reg case - assign $6\src20__data_o$next[1:0]$10656 $5\src20__data_o$next[1:0]$10655 + assign $6\src20__data_o$next[1:0]$10690 $5\src20__data_o$next[1:0]$10689 end case - assign $1\src20__data_o$next[1:0]$10651 2'00 + assign $1\src20__data_o$next[1:0]$10685 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$10657 2'00 + assign $7\src20__data_o$next[1:0]$10691 2'00 case - assign $7\src20__data_o$next[1:0]$10657 $1\src20__data_o$next[1:0]$10651 + assign $7\src20__data_o$next[1:0]$10691 $1\src20__data_o$next[1:0]$10685 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10650 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10684 end - attribute \src "libresoc.v:167297.3-167332.6" - process $proc$libresoc.v:167297$10658 + attribute \src "libresoc.v:175835.3-175870.6" + process $proc$libresoc.v:175835$10692 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10659 $1\wr_detect$4[0:0]$10660 - attribute \src "libresoc.v:167298.5-167298.29" + assign $0\wr_detect$4[0:0]$10693 $1\wr_detect$4[0:0]$10694 + attribute \src "libresoc.v:175836.5-175836.29" switch \initial - attribute \src "libresoc.v:167298.9-167298.17" + attribute \src "libresoc.v:175836.9-175836.17" case 1'1 case end @@ -347315,58 +361979,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10660 $5\wr_detect$4[0:0]$10664 + assign $1\wr_detect$4[0:0]$10694 $5\wr_detect$4[0:0]$10698 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10661 1'1 + assign $2\wr_detect$4[0:0]$10695 1'1 case - assign $2\wr_detect$4[0:0]$10661 1'0 + assign $2\wr_detect$4[0:0]$10695 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10662 1'1 + assign $3\wr_detect$4[0:0]$10696 1'1 case - assign $3\wr_detect$4[0:0]$10662 $2\wr_detect$4[0:0]$10661 + assign $3\wr_detect$4[0:0]$10696 $2\wr_detect$4[0:0]$10695 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10663 1'1 + assign $4\wr_detect$4[0:0]$10697 1'1 case - assign $4\wr_detect$4[0:0]$10663 $3\wr_detect$4[0:0]$10662 + assign $4\wr_detect$4[0:0]$10697 $3\wr_detect$4[0:0]$10696 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10664 1'1 + assign $5\wr_detect$4[0:0]$10698 1'1 case - assign $5\wr_detect$4[0:0]$10664 $4\wr_detect$4[0:0]$10663 + assign $5\wr_detect$4[0:0]$10698 $4\wr_detect$4[0:0]$10697 end case - assign $1\wr_detect$4[0:0]$10660 1'0 + assign $1\wr_detect$4[0:0]$10694 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10659 + update \wr_detect$4 $0\wr_detect$4[0:0]$10693 end - attribute \src "libresoc.v:167333.3-167378.6" - process $proc$libresoc.v:167333$10665 + attribute \src "libresoc.v:175871.3-175916.6" + process $proc$libresoc.v:175871$10699 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$10666 $7\src30__data_o$next[1:0]$10673 - attribute \src "libresoc.v:167334.5-167334.29" + assign $0\src30__data_o$next[1:0]$10700 $7\src30__data_o$next[1:0]$10707 + attribute \src "libresoc.v:175872.5-175872.29" switch \initial - attribute \src "libresoc.v:167334.9-167334.17" + attribute \src "libresoc.v:175872.9-175872.17" case 1'1 case end @@ -347379,75 +362043,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$10667 $6\src30__data_o$next[1:0]$10672 + assign $1\src30__data_o$next[1:0]$10701 $6\src30__data_o$next[1:0]$10706 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$10668 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10702 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$10668 2'00 + assign $2\src30__data_o$next[1:0]$10702 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$10669 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10703 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$10669 $2\src30__data_o$next[1:0]$10668 + assign $3\src30__data_o$next[1:0]$10703 $2\src30__data_o$next[1:0]$10702 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$10670 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10704 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$10670 $3\src30__data_o$next[1:0]$10669 + assign $4\src30__data_o$next[1:0]$10704 $3\src30__data_o$next[1:0]$10703 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$10671 \w0__data_i + assign $5\src30__data_o$next[1:0]$10705 \w0__data_i case - assign $5\src30__data_o$next[1:0]$10671 $4\src30__data_o$next[1:0]$10670 + assign $5\src30__data_o$next[1:0]$10705 $4\src30__data_o$next[1:0]$10704 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$10672 \reg + assign $6\src30__data_o$next[1:0]$10706 \reg case - assign $6\src30__data_o$next[1:0]$10672 $5\src30__data_o$next[1:0]$10671 + assign $6\src30__data_o$next[1:0]$10706 $5\src30__data_o$next[1:0]$10705 end case - assign $1\src30__data_o$next[1:0]$10667 2'00 + assign $1\src30__data_o$next[1:0]$10701 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$10673 2'00 + assign $7\src30__data_o$next[1:0]$10707 2'00 case - assign $7\src30__data_o$next[1:0]$10673 $1\src30__data_o$next[1:0]$10667 + assign $7\src30__data_o$next[1:0]$10707 $1\src30__data_o$next[1:0]$10701 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10666 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10700 end - attribute \src "libresoc.v:167379.3-167414.6" - process $proc$libresoc.v:167379$10674 + attribute \src "libresoc.v:175917.3-175952.6" + process $proc$libresoc.v:175917$10708 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10675 $1\wr_detect$7[0:0]$10676 - attribute \src "libresoc.v:167380.5-167380.29" + assign $0\wr_detect$7[0:0]$10709 $1\wr_detect$7[0:0]$10710 + attribute \src "libresoc.v:175918.5-175918.29" switch \initial - attribute \src "libresoc.v:167380.9-167380.17" + attribute \src "libresoc.v:175918.9-175918.17" case 1'1 case end @@ -347460,58 +362124,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10676 $5\wr_detect$7[0:0]$10680 + assign $1\wr_detect$7[0:0]$10710 $5\wr_detect$7[0:0]$10714 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10677 1'1 + assign $2\wr_detect$7[0:0]$10711 1'1 case - assign $2\wr_detect$7[0:0]$10677 1'0 + assign $2\wr_detect$7[0:0]$10711 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10678 1'1 + assign $3\wr_detect$7[0:0]$10712 1'1 case - assign $3\wr_detect$7[0:0]$10678 $2\wr_detect$7[0:0]$10677 + assign $3\wr_detect$7[0:0]$10712 $2\wr_detect$7[0:0]$10711 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10679 1'1 + assign $4\wr_detect$7[0:0]$10713 1'1 case - assign $4\wr_detect$7[0:0]$10679 $3\wr_detect$7[0:0]$10678 + assign $4\wr_detect$7[0:0]$10713 $3\wr_detect$7[0:0]$10712 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10680 1'1 + assign $5\wr_detect$7[0:0]$10714 1'1 case - assign $5\wr_detect$7[0:0]$10680 $4\wr_detect$7[0:0]$10679 + assign $5\wr_detect$7[0:0]$10714 $4\wr_detect$7[0:0]$10713 end case - assign $1\wr_detect$7[0:0]$10676 1'0 + assign $1\wr_detect$7[0:0]$10710 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10675 + update \wr_detect$7 $0\wr_detect$7[0:0]$10709 end - attribute \src "libresoc.v:167415.3-167460.6" - process $proc$libresoc.v:167415$10681 + attribute \src "libresoc.v:175953.3-175998.6" + process $proc$libresoc.v:175953$10715 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$10682 $7\r0__data_o$next[1:0]$10689 - attribute \src "libresoc.v:167416.5-167416.29" + assign $0\r0__data_o$next[1:0]$10716 $7\r0__data_o$next[1:0]$10723 + attribute \src "libresoc.v:175954.5-175954.29" switch \initial - attribute \src "libresoc.v:167416.9-167416.17" + attribute \src "libresoc.v:175954.9-175954.17" case 1'1 case end @@ -347524,75 +362188,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$10683 $6\r0__data_o$next[1:0]$10688 + assign $1\r0__data_o$next[1:0]$10717 $6\r0__data_o$next[1:0]$10722 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$10684 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10718 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$10684 2'00 + assign $2\r0__data_o$next[1:0]$10718 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$10685 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10719 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$10685 $2\r0__data_o$next[1:0]$10684 + assign $3\r0__data_o$next[1:0]$10719 $2\r0__data_o$next[1:0]$10718 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$10686 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10720 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$10686 $3\r0__data_o$next[1:0]$10685 + assign $4\r0__data_o$next[1:0]$10720 $3\r0__data_o$next[1:0]$10719 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$10687 \w0__data_i + assign $5\r0__data_o$next[1:0]$10721 \w0__data_i case - assign $5\r0__data_o$next[1:0]$10687 $4\r0__data_o$next[1:0]$10686 + assign $5\r0__data_o$next[1:0]$10721 $4\r0__data_o$next[1:0]$10720 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$10688 \reg + assign $6\r0__data_o$next[1:0]$10722 \reg case - assign $6\r0__data_o$next[1:0]$10688 $5\r0__data_o$next[1:0]$10687 + assign $6\r0__data_o$next[1:0]$10722 $5\r0__data_o$next[1:0]$10721 end case - assign $1\r0__data_o$next[1:0]$10683 2'00 + assign $1\r0__data_o$next[1:0]$10717 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$10689 2'00 + assign $7\r0__data_o$next[1:0]$10723 2'00 case - assign $7\r0__data_o$next[1:0]$10689 $1\r0__data_o$next[1:0]$10683 + assign $7\r0__data_o$next[1:0]$10723 $1\r0__data_o$next[1:0]$10717 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10682 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10716 end - attribute \src "libresoc.v:167461.3-167496.6" - process $proc$libresoc.v:167461$10690 + attribute \src "libresoc.v:175999.3-176034.6" + process $proc$libresoc.v:175999$10724 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10691 $1\wr_detect$10[0:0]$10692 - attribute \src "libresoc.v:167462.5-167462.29" + assign $0\wr_detect$10[0:0]$10725 $1\wr_detect$10[0:0]$10726 + attribute \src "libresoc.v:176000.5-176000.29" switch \initial - attribute \src "libresoc.v:167462.9-167462.17" + attribute \src "libresoc.v:176000.9-176000.17" case 1'1 case end @@ -347605,61 +362269,61 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10692 $5\wr_detect$10[0:0]$10696 + assign $1\wr_detect$10[0:0]$10726 $5\wr_detect$10[0:0]$10730 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10693 1'1 + assign $2\wr_detect$10[0:0]$10727 1'1 case - assign $2\wr_detect$10[0:0]$10693 1'0 + assign $2\wr_detect$10[0:0]$10727 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10694 1'1 + assign $3\wr_detect$10[0:0]$10728 1'1 case - assign $3\wr_detect$10[0:0]$10694 $2\wr_detect$10[0:0]$10693 + assign $3\wr_detect$10[0:0]$10728 $2\wr_detect$10[0:0]$10727 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10695 1'1 + assign $4\wr_detect$10[0:0]$10729 1'1 case - assign $4\wr_detect$10[0:0]$10695 $3\wr_detect$10[0:0]$10694 + assign $4\wr_detect$10[0:0]$10729 $3\wr_detect$10[0:0]$10728 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10696 1'1 + assign $5\wr_detect$10[0:0]$10730 1'1 case - assign $5\wr_detect$10[0:0]$10696 $4\wr_detect$10[0:0]$10695 + assign $5\wr_detect$10[0:0]$10730 $4\wr_detect$10[0:0]$10729 end case - assign $1\wr_detect$10[0:0]$10692 1'0 + assign $1\wr_detect$10[0:0]$10726 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10691 + update \wr_detect$10 $0\wr_detect$10[0:0]$10725 end - attribute \src "libresoc.v:167497.3-167529.6" - process $proc$libresoc.v:167497$10697 + attribute \src "libresoc.v:176035.3-176067.6" + process $proc$libresoc.v:176035$10731 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10698 $5\reg$next[1:0]$10703 - attribute \src "libresoc.v:167498.5-167498.29" + assign $0\reg$next[1:0]$10732 $5\reg$next[1:0]$10737 + attribute \src "libresoc.v:176036.5-176036.29" switch \initial - attribute \src "libresoc.v:167498.9-167498.17" + attribute \src "libresoc.v:176036.9-176036.17" case 1'1 case end @@ -347668,255 +362332,336 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10699 \dest10__data_i + assign $1\reg$next[1:0]$10733 \dest10__data_i case - assign $1\reg$next[1:0]$10699 \reg + assign $1\reg$next[1:0]$10733 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10700 \dest20__data_i + assign $2\reg$next[1:0]$10734 \dest20__data_i case - assign $2\reg$next[1:0]$10700 $1\reg$next[1:0]$10699 + assign $2\reg$next[1:0]$10734 $1\reg$next[1:0]$10733 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10701 \dest30__data_i + assign $3\reg$next[1:0]$10735 \dest30__data_i case - assign $3\reg$next[1:0]$10701 $2\reg$next[1:0]$10700 + assign $3\reg$next[1:0]$10735 $2\reg$next[1:0]$10734 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10702 \w0__data_i + assign $4\reg$next[1:0]$10736 \w0__data_i case - assign $4\reg$next[1:0]$10702 $3\reg$next[1:0]$10701 + assign $4\reg$next[1:0]$10736 $3\reg$next[1:0]$10735 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10703 2'00 + assign $5\reg$next[1:0]$10737 2'00 case - assign $5\reg$next[1:0]$10703 $4\reg$next[1:0]$10702 + assign $5\reg$next[1:0]$10737 $4\reg$next[1:0]$10736 end sync always - update \reg$next $0\reg$next[1:0]$10698 + update \reg$next $0\reg$next[1:0]$10732 end - connect \$9 $not$libresoc.v:167155$10630_Y - connect \$1 $not$libresoc.v:167156$10631_Y - connect \$3 $not$libresoc.v:167157$10632_Y - connect \$6 $not$libresoc.v:167158$10633_Y + connect \$9 $not$libresoc.v:175693$10664_Y + connect \$1 $not$libresoc.v:175694$10665_Y + connect \$3 $not$libresoc.v:175695$10666_Y + connect \$6 $not$libresoc.v:175696$10667_Y end -attribute \src "libresoc.v:167534.1-167753.10" +attribute \src "libresoc.v:176072.1-176421.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:167586.3-167625.6" - wire width 64 $0\cia0__data_o$next[63:0]$10716 - attribute \src "libresoc.v:167584.3-167585.41" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $0\cia0__data_o$next[63:0]$10752 + attribute \src "libresoc.v:176140.3-176141.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:167535.7-167535.20" + attribute \src "libresoc.v:176073.7-176073.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167656.3-167695.6" - wire width 64 $0\msr0__data_o$next[63:0]$10725 - attribute \src "libresoc.v:167582.3-167583.41" + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $0\msr0__data_o$next[63:0]$10762 + attribute \src "libresoc.v:176138.3-176139.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:167726.3-167752.6" - wire width 64 $0\reg$next[63:0]$10739 - attribute \src "libresoc.v:167580.3-167581.25" + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $0\reg$next[63:0]$10794 + attribute \src "libresoc.v:176134.3-176135.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:167696.3-167725.6" - wire $0\wr_detect$4[0:0]$10733 - attribute \src "libresoc.v:167626.3-167655.6" + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $0\sv0__data_o$next[63:0]$10778 + attribute \src "libresoc.v:176136.3-176137.39" + wire width 64 $0\sv0__data_o[63:0] + attribute \src "libresoc.v:176270.3-176305.6" + wire $0\wr_detect$4[0:0]$10771 + attribute \src "libresoc.v:176352.3-176387.6" + wire $0\wr_detect$7[0:0]$10787 + attribute \src "libresoc.v:176188.3-176223.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:167586.3-167625.6" - wire width 64 $1\cia0__data_o$next[63:0]$10717 - attribute \src "libresoc.v:167542.14-167542.49" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $1\cia0__data_o$next[63:0]$10753 + attribute \src "libresoc.v:176082.14-176082.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:167656.3-167695.6" - wire width 64 $1\msr0__data_o$next[63:0]$10726 - attribute \src "libresoc.v:167559.14-167559.49" + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $1\msr0__data_o$next[63:0]$10763 + attribute \src "libresoc.v:176099.14-176099.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:167726.3-167752.6" - wire width 64 $1\reg$next[63:0]$10740 - attribute \src "libresoc.v:167571.14-167571.42" + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $1\reg$next[63:0]$10795 + attribute \src "libresoc.v:176111.14-176111.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:167696.3-167725.6" - wire $1\wr_detect$4[0:0]$10734 - attribute \src "libresoc.v:167626.3-167655.6" + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $1\sv0__data_o$next[63:0]$10779 + attribute \src "libresoc.v:176118.14-176118.48" + wire width 64 $1\sv0__data_o[63:0] + attribute \src "libresoc.v:176270.3-176305.6" + wire $1\wr_detect$4[0:0]$10772 + attribute \src "libresoc.v:176352.3-176387.6" + wire $1\wr_detect$7[0:0]$10788 + attribute \src "libresoc.v:176188.3-176223.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:167586.3-167625.6" - wire width 64 $2\cia0__data_o$next[63:0]$10718 - attribute \src "libresoc.v:167656.3-167695.6" - wire width 64 $2\msr0__data_o$next[63:0]$10727 - attribute \src "libresoc.v:167726.3-167752.6" - wire width 64 $2\reg$next[63:0]$10741 - attribute \src "libresoc.v:167696.3-167725.6" - wire $2\wr_detect$4[0:0]$10735 - attribute \src "libresoc.v:167626.3-167655.6" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $2\cia0__data_o$next[63:0]$10754 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $2\msr0__data_o$next[63:0]$10764 + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $2\reg$next[63:0]$10796 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $2\sv0__data_o$next[63:0]$10780 + attribute \src "libresoc.v:176270.3-176305.6" + wire $2\wr_detect$4[0:0]$10773 + attribute \src "libresoc.v:176352.3-176387.6" + wire $2\wr_detect$7[0:0]$10789 + attribute \src "libresoc.v:176188.3-176223.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:167586.3-167625.6" - wire width 64 $3\cia0__data_o$next[63:0]$10719 - attribute \src "libresoc.v:167656.3-167695.6" - wire width 64 $3\msr0__data_o$next[63:0]$10728 - attribute \src "libresoc.v:167726.3-167752.6" - wire width 64 $3\reg$next[63:0]$10742 - attribute \src "libresoc.v:167696.3-167725.6" - wire $3\wr_detect$4[0:0]$10736 - attribute \src "libresoc.v:167626.3-167655.6" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $3\cia0__data_o$next[63:0]$10755 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $3\msr0__data_o$next[63:0]$10765 + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $3\reg$next[63:0]$10797 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $3\sv0__data_o$next[63:0]$10781 + attribute \src "libresoc.v:176270.3-176305.6" + wire $3\wr_detect$4[0:0]$10774 + attribute \src "libresoc.v:176352.3-176387.6" + wire $3\wr_detect$7[0:0]$10790 + attribute \src "libresoc.v:176188.3-176223.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:167586.3-167625.6" - wire width 64 $4\cia0__data_o$next[63:0]$10720 - attribute \src "libresoc.v:167656.3-167695.6" - wire width 64 $4\msr0__data_o$next[63:0]$10729 - attribute \src "libresoc.v:167726.3-167752.6" - wire width 64 $4\reg$next[63:0]$10743 - attribute \src "libresoc.v:167696.3-167725.6" - wire $4\wr_detect$4[0:0]$10737 - attribute \src "libresoc.v:167626.3-167655.6" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $4\cia0__data_o$next[63:0]$10756 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $4\msr0__data_o$next[63:0]$10766 + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $4\reg$next[63:0]$10798 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $4\sv0__data_o$next[63:0]$10782 + attribute \src "libresoc.v:176270.3-176305.6" + wire $4\wr_detect$4[0:0]$10775 + attribute \src "libresoc.v:176352.3-176387.6" + wire $4\wr_detect$7[0:0]$10791 + attribute \src "libresoc.v:176188.3-176223.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:167586.3-167625.6" - wire width 64 $5\cia0__data_o$next[63:0]$10721 - attribute \src "libresoc.v:167656.3-167695.6" - wire width 64 $5\msr0__data_o$next[63:0]$10730 - attribute \src "libresoc.v:167586.3-167625.6" - wire width 64 $6\cia0__data_o$next[63:0]$10722 - attribute \src "libresoc.v:167656.3-167695.6" - wire width 64 $6\msr0__data_o$next[63:0]$10731 - attribute \src "libresoc.v:167578.17-167578.100" - wire $not$libresoc.v:167578$10710_Y - attribute \src "libresoc.v:167579.17-167579.103" - wire $not$libresoc.v:167579$10711_Y + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $5\cia0__data_o$next[63:0]$10757 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $5\msr0__data_o$next[63:0]$10767 + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $5\reg$next[63:0]$10799 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $5\sv0__data_o$next[63:0]$10783 + attribute \src "libresoc.v:176270.3-176305.6" + wire $5\wr_detect$4[0:0]$10776 + attribute \src "libresoc.v:176352.3-176387.6" + wire $5\wr_detect$7[0:0]$10792 + attribute \src "libresoc.v:176188.3-176223.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $6\cia0__data_o$next[63:0]$10758 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $6\msr0__data_o$next[63:0]$10768 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $6\sv0__data_o$next[63:0]$10784 + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $7\cia0__data_o$next[63:0]$10759 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $7\msr0__data_o$next[63:0]$10769 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $7\sv0__data_o$next[63:0]$10785 + attribute \src "libresoc.v:176131.17-176131.100" + wire $not$libresoc.v:176131$10744_Y + attribute \src "libresoc.v:176132.17-176132.103" + wire $not$libresoc.v:176132$10745_Y + attribute \src "libresoc.v:176133.17-176133.103" + wire $not$libresoc.v:176133$10746_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 3 \cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \cia0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr10__wen - attribute \src "libresoc.v:167535.7-167535.15" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr10__wen + attribute \src "libresoc.v:176073.7-176073.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 5 \msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \msr0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167578$10710 + cell $not $not$libresoc.v:176131$10744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:167578$10710_Y + connect \Y $not$libresoc.v:176131$10744_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167579$10711 + cell $not $not$libresoc.v:176132$10745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:167579$10711_Y + connect \Y $not$libresoc.v:176132$10745_Y end - attribute \src "libresoc.v:167535.7-167535.20" - process $proc$libresoc.v:167535$10744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176133$10746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:176133$10746_Y + end + attribute \src "libresoc.v:176073.7-176073.20" + process $proc$libresoc.v:176073$10800 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167542.14-167542.49" - process $proc$libresoc.v:167542$10745 + attribute \src "libresoc.v:176082.14-176082.49" + process $proc$libresoc.v:176082$10801 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:167559.14-167559.49" - process $proc$libresoc.v:167559$10746 + attribute \src "libresoc.v:176099.14-176099.49" + process $proc$libresoc.v:176099$10802 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:167571.14-167571.42" - process $proc$libresoc.v:167571$10747 + attribute \src "libresoc.v:176111.14-176111.42" + process $proc$libresoc.v:176111$10803 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:167580.3-167581.25" - process $proc$libresoc.v:167580$10712 + attribute \src "libresoc.v:176118.14-176118.48" + process $proc$libresoc.v:176118$10804 + assign { } { } + assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv0__data_o $1\sv0__data_o[63:0] + end + attribute \src "libresoc.v:176134.3-176135.25" + process $proc$libresoc.v:176134$10747 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:167582.3-167583.41" - process $proc$libresoc.v:167582$10713 + attribute \src "libresoc.v:176136.3-176137.39" + process $proc$libresoc.v:176136$10748 + assign { } { } + assign $0\sv0__data_o[63:0] \sv0__data_o$next + sync posedge \coresync_clk + update \sv0__data_o $0\sv0__data_o[63:0] + end + attribute \src "libresoc.v:176138.3-176139.41" + process $proc$libresoc.v:176138$10749 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:167584.3-167585.41" - process $proc$libresoc.v:167584$10714 + attribute \src "libresoc.v:176140.3-176141.41" + process $proc$libresoc.v:176140$10750 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:167586.3-167625.6" - process $proc$libresoc.v:167586$10715 + attribute \src "libresoc.v:176142.3-176187.6" + process $proc$libresoc.v:176142$10751 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10716 $6\cia0__data_o$next[63:0]$10722 - attribute \src "libresoc.v:167587.5-167587.29" + assign $0\cia0__data_o$next[63:0]$10752 $7\cia0__data_o$next[63:0]$10759 + attribute \src "libresoc.v:176143.5-176143.29" switch \initial - attribute \src "libresoc.v:167587.9-167587.17" + attribute \src "libresoc.v:176143.9-176143.17" case 1'1 case end @@ -347928,66 +362673,76 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$10717 $5\cia0__data_o$next[63:0]$10721 + assign { } { } + assign $1\cia0__data_o$next[63:0]$10753 $6\cia0__data_o$next[63:0]$10758 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$10718 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10754 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$10718 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10754 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$10719 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10755 \msr0__data_i + case + assign $3\cia0__data_o$next[63:0]$10755 $2\cia0__data_o$next[63:0]$10754 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia0__data_o$next[63:0]$10756 \sv0__data_i case - assign $3\cia0__data_o$next[63:0]$10719 $2\cia0__data_o$next[63:0]$10718 + assign $4\cia0__data_o$next[63:0]$10756 $3\cia0__data_o$next[63:0]$10755 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$10720 \d_wr10__data_i + assign $5\cia0__data_o$next[63:0]$10757 \d_wr10__data_i case - assign $4\cia0__data_o$next[63:0]$10720 $3\cia0__data_o$next[63:0]$10719 + assign $5\cia0__data_o$next[63:0]$10757 $4\cia0__data_o$next[63:0]$10756 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$10721 \reg + assign $6\cia0__data_o$next[63:0]$10758 \reg case - assign $5\cia0__data_o$next[63:0]$10721 $4\cia0__data_o$next[63:0]$10720 + assign $6\cia0__data_o$next[63:0]$10758 $5\cia0__data_o$next[63:0]$10757 end case - assign $1\cia0__data_o$next[63:0]$10717 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10753 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$10722 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\cia0__data_o$next[63:0]$10722 $1\cia0__data_o$next[63:0]$10717 + assign $7\cia0__data_o$next[63:0]$10759 $1\cia0__data_o$next[63:0]$10753 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10716 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10752 end - attribute \src "libresoc.v:167626.3-167655.6" - process $proc$libresoc.v:167626$10723 + attribute \src "libresoc.v:176188.3-176223.6" + process $proc$libresoc.v:176188$10760 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:167627.5-167627.29" + attribute \src "libresoc.v:176189.5-176189.29" switch \initial - attribute \src "libresoc.v:167627.9-167627.17" + attribute \src "libresoc.v:176189.9-176189.17" case 1'1 case end @@ -347999,7 +362754,8 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" @@ -348019,7 +362775,7 @@ module \reg_0$135 assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen + switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -348027,21 +362783,30 @@ module \reg_0$135 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:167656.3-167695.6" - process $proc$libresoc.v:167656$10724 + attribute \src "libresoc.v:176224.3-176269.6" + process $proc$libresoc.v:176224$10761 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10725 $6\msr0__data_o$next[63:0]$10731 - attribute \src "libresoc.v:167657.5-167657.29" + assign $0\msr0__data_o$next[63:0]$10762 $7\msr0__data_o$next[63:0]$10769 + attribute \src "libresoc.v:176225.5-176225.29" switch \initial - attribute \src "libresoc.v:167657.9-167657.17" + attribute \src "libresoc.v:176225.9-176225.17" case 1'1 case end @@ -348053,66 +362818,76 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$10726 $5\msr0__data_o$next[63:0]$10730 + assign { } { } + assign $1\msr0__data_o$next[63:0]$10763 $6\msr0__data_o$next[63:0]$10768 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$10727 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10764 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$10727 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10764 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$10728 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10765 \msr0__data_i + case + assign $3\msr0__data_o$next[63:0]$10765 $2\msr0__data_o$next[63:0]$10764 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr0__data_o$next[63:0]$10766 \sv0__data_i case - assign $3\msr0__data_o$next[63:0]$10728 $2\msr0__data_o$next[63:0]$10727 + assign $4\msr0__data_o$next[63:0]$10766 $3\msr0__data_o$next[63:0]$10765 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$10729 \d_wr10__data_i + assign $5\msr0__data_o$next[63:0]$10767 \d_wr10__data_i case - assign $4\msr0__data_o$next[63:0]$10729 $3\msr0__data_o$next[63:0]$10728 + assign $5\msr0__data_o$next[63:0]$10767 $4\msr0__data_o$next[63:0]$10766 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$10730 \reg + assign $6\msr0__data_o$next[63:0]$10768 \reg case - assign $5\msr0__data_o$next[63:0]$10730 $4\msr0__data_o$next[63:0]$10729 + assign $6\msr0__data_o$next[63:0]$10768 $5\msr0__data_o$next[63:0]$10767 end case - assign $1\msr0__data_o$next[63:0]$10726 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10763 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$10731 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr0__data_o$next[63:0]$10769 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\msr0__data_o$next[63:0]$10731 $1\msr0__data_o$next[63:0]$10726 + assign $7\msr0__data_o$next[63:0]$10769 $1\msr0__data_o$next[63:0]$10763 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10725 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10762 end - attribute \src "libresoc.v:167696.3-167725.6" - process $proc$libresoc.v:167696$10732 + attribute \src "libresoc.v:176270.3-176305.6" + process $proc$libresoc.v:176270$10770 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10733 $1\wr_detect$4[0:0]$10734 - attribute \src "libresoc.v:167697.5-167697.29" + assign $0\wr_detect$4[0:0]$10771 $1\wr_detect$4[0:0]$10772 + attribute \src "libresoc.v:176271.5-176271.29" switch \initial - attribute \src "libresoc.v:167697.9-167697.17" + attribute \src "libresoc.v:176271.9-176271.17" case 1'1 case end @@ -348124,51 +362899,207 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10734 $4\wr_detect$4[0:0]$10737 + assign { } { } + assign $1\wr_detect$4[0:0]$10772 $5\wr_detect$4[0:0]$10776 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10735 1'1 + assign $2\wr_detect$4[0:0]$10773 1'1 case - assign $2\wr_detect$4[0:0]$10735 1'0 + assign $2\wr_detect$4[0:0]$10773 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10736 1'1 + assign $3\wr_detect$4[0:0]$10774 1'1 case - assign $3\wr_detect$4[0:0]$10736 $2\wr_detect$4[0:0]$10735 + assign $3\wr_detect$4[0:0]$10774 $2\wr_detect$4[0:0]$10773 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10775 1'1 + case + assign $4\wr_detect$4[0:0]$10775 $3\wr_detect$4[0:0]$10774 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10737 1'1 + assign $5\wr_detect$4[0:0]$10776 1'1 case - assign $4\wr_detect$4[0:0]$10737 $3\wr_detect$4[0:0]$10736 + assign $5\wr_detect$4[0:0]$10776 $4\wr_detect$4[0:0]$10775 end case - assign $1\wr_detect$4[0:0]$10734 1'0 + assign $1\wr_detect$4[0:0]$10772 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10733 + update \wr_detect$4 $0\wr_detect$4[0:0]$10771 end - attribute \src "libresoc.v:167726.3-167752.6" - process $proc$libresoc.v:167726$10738 + attribute \src "libresoc.v:176306.3-176351.6" + process $proc$libresoc.v:176306$10777 assign { } { } assign { } { } assign { } { } + assign $0\sv0__data_o$next[63:0]$10778 $7\sv0__data_o$next[63:0]$10785 + attribute \src "libresoc.v:176307.5-176307.29" + switch \initial + attribute \src "libresoc.v:176307.9-176307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\sv0__data_o$next[63:0]$10779 $6\sv0__data_o$next[63:0]$10784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv0__data_o$next[63:0]$10780 \nia0__data_i + case + assign $2\sv0__data_o$next[63:0]$10780 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv0__data_o$next[63:0]$10781 \msr0__data_i + case + assign $3\sv0__data_o$next[63:0]$10781 $2\sv0__data_o$next[63:0]$10780 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv0__data_o$next[63:0]$10782 \sv0__data_i + case + assign $4\sv0__data_o$next[63:0]$10782 $3\sv0__data_o$next[63:0]$10781 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv0__data_o$next[63:0]$10783 \d_wr10__data_i + case + assign $5\sv0__data_o$next[63:0]$10783 $4\sv0__data_o$next[63:0]$10782 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv0__data_o$next[63:0]$10784 \reg + case + assign $6\sv0__data_o$next[63:0]$10784 $5\sv0__data_o$next[63:0]$10783 + end + case + assign $1\sv0__data_o$next[63:0]$10779 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv0__data_o$next[63:0]$10785 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\sv0__data_o$next[63:0]$10785 $1\sv0__data_o$next[63:0]$10779 + end + sync always + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10778 + end + attribute \src "libresoc.v:176352.3-176387.6" + process $proc$libresoc.v:176352$10786 assign { } { } assign { } { } - assign $0\reg$next[63:0]$10739 $4\reg$next[63:0]$10743 - attribute \src "libresoc.v:167727.5-167727.29" + assign $0\wr_detect$7[0:0]$10787 $1\wr_detect$7[0:0]$10788 + attribute \src "libresoc.v:176353.5-176353.29" switch \initial - attribute \src "libresoc.v:167727.9-167727.17" + attribute \src "libresoc.v:176353.9-176353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10788 $5\wr_detect$7[0:0]$10792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10789 1'1 + case + assign $2\wr_detect$7[0:0]$10789 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10790 1'1 + case + assign $3\wr_detect$7[0:0]$10790 $2\wr_detect$7[0:0]$10789 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10791 1'1 + case + assign $4\wr_detect$7[0:0]$10791 $3\wr_detect$7[0:0]$10790 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10792 1'1 + case + assign $5\wr_detect$7[0:0]$10792 $4\wr_detect$7[0:0]$10791 + end + case + assign $1\wr_detect$7[0:0]$10788 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10787 + end + attribute \src "libresoc.v:176388.3-176420.6" + process $proc$libresoc.v:176388$10793 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10794 $5\reg$next[63:0]$10799 + attribute \src "libresoc.v:176389.5-176389.29" + switch \initial + attribute \src "libresoc.v:176389.9-176389.17" case 1'1 case end @@ -348177,214 +363108,224 @@ module \reg_0$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10740 \nia0__data_i + assign $1\reg$next[63:0]$10795 \nia0__data_i case - assign $1\reg$next[63:0]$10740 \reg + assign $1\reg$next[63:0]$10795 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10741 \msr0__data_i + assign $2\reg$next[63:0]$10796 \msr0__data_i + case + assign $2\reg$next[63:0]$10796 $1\reg$next[63:0]$10795 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10797 \sv0__data_i case - assign $2\reg$next[63:0]$10741 $1\reg$next[63:0]$10740 + assign $3\reg$next[63:0]$10797 $2\reg$next[63:0]$10796 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10742 \d_wr10__data_i + assign $4\reg$next[63:0]$10798 \d_wr10__data_i case - assign $3\reg$next[63:0]$10742 $2\reg$next[63:0]$10741 + assign $4\reg$next[63:0]$10798 $3\reg$next[63:0]$10797 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10743 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$10799 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\reg$next[63:0]$10743 $3\reg$next[63:0]$10742 + assign $5\reg$next[63:0]$10799 $4\reg$next[63:0]$10798 end sync always - update \reg$next $0\reg$next[63:0]$10739 + update \reg$next $0\reg$next[63:0]$10794 end - connect \$1 $not$libresoc.v:167578$10710_Y - connect \$3 $not$libresoc.v:167579$10711_Y + connect \$1 $not$libresoc.v:176131$10744_Y + connect \$3 $not$libresoc.v:176132$10745_Y + connect \$6 $not$libresoc.v:176133$10746_Y end -attribute \src "libresoc.v:167757.1-168228.10" +attribute \src "libresoc.v:176425.1-176896.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:167758.7-167758.20" + attribute \src "libresoc.v:176426.7-176426.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168088.3-168127.6" - wire width 4 $0\r1__data_o$next[3:0]$10803 - attribute \src "libresoc.v:167843.3-167844.37" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $0\r1__data_o$next[3:0]$10860 + attribute \src "libresoc.v:176511.3-176512.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:168158.3-168197.6" - wire width 4 $0\r21__data_o$next[3:0]$10817 - attribute \src "libresoc.v:167841.3-167842.39" + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $0\r21__data_o$next[3:0]$10874 + attribute \src "libresoc.v:176509.3-176510.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:167921.3-167947.6" - wire width 4 $0\reg$next[3:0]$10769 - attribute \src "libresoc.v:167839.3-167840.25" + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $0\reg$next[3:0]$10826 + attribute \src "libresoc.v:176507.3-176508.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:167851.3-167890.6" - wire width 4 $0\src11__data_o$next[3:0]$10760 - attribute \src "libresoc.v:167849.3-167850.43" + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $0\src11__data_o$next[3:0]$10817 + attribute \src "libresoc.v:176517.3-176518.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:167948.3-167987.6" - wire width 4 $0\src21__data_o$next[3:0]$10775 - attribute \src "libresoc.v:167847.3-167848.43" + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $0\src21__data_o$next[3:0]$10832 + attribute \src "libresoc.v:176515.3-176516.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:168018.3-168057.6" - wire width 4 $0\src31__data_o$next[3:0]$10789 - attribute \src "libresoc.v:167845.3-167846.43" + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $0\src31__data_o$next[3:0]$10846 + attribute \src "libresoc.v:176513.3-176514.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:168128.3-168157.6" - wire $0\wr_detect$10[0:0]$10811 - attribute \src "libresoc.v:168198.3-168227.6" - wire $0\wr_detect$13[0:0]$10825 - attribute \src "libresoc.v:167988.3-168017.6" - wire $0\wr_detect$4[0:0]$10783 - attribute \src "libresoc.v:168058.3-168087.6" - wire $0\wr_detect$7[0:0]$10797 - attribute \src "libresoc.v:167891.3-167920.6" + attribute \src "libresoc.v:176796.3-176825.6" + wire $0\wr_detect$10[0:0]$10868 + attribute \src "libresoc.v:176866.3-176895.6" + wire $0\wr_detect$13[0:0]$10882 + attribute \src "libresoc.v:176656.3-176685.6" + wire $0\wr_detect$4[0:0]$10840 + attribute \src "libresoc.v:176726.3-176755.6" + wire $0\wr_detect$7[0:0]$10854 + attribute \src "libresoc.v:176559.3-176588.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:168088.3-168127.6" - wire width 4 $1\r1__data_o$next[3:0]$10804 - attribute \src "libresoc.v:167783.13-167783.30" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $1\r1__data_o$next[3:0]$10861 + attribute \src "libresoc.v:176451.13-176451.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:168158.3-168197.6" - wire width 4 $1\r21__data_o$next[3:0]$10818 - attribute \src "libresoc.v:167790.13-167790.31" + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $1\r21__data_o$next[3:0]$10875 + attribute \src "libresoc.v:176458.13-176458.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:167921.3-167947.6" - wire width 4 $1\reg$next[3:0]$10770 - attribute \src "libresoc.v:167796.13-167796.25" + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $1\reg$next[3:0]$10827 + attribute \src "libresoc.v:176464.13-176464.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:167851.3-167890.6" - wire width 4 $1\src11__data_o$next[3:0]$10761 - attribute \src "libresoc.v:167801.13-167801.33" + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $1\src11__data_o$next[3:0]$10818 + attribute \src "libresoc.v:176469.13-176469.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:167948.3-167987.6" - wire width 4 $1\src21__data_o$next[3:0]$10776 - attribute \src "libresoc.v:167808.13-167808.33" + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $1\src21__data_o$next[3:0]$10833 + attribute \src "libresoc.v:176476.13-176476.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:168018.3-168057.6" - wire width 4 $1\src31__data_o$next[3:0]$10790 - attribute \src "libresoc.v:167815.13-167815.33" + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $1\src31__data_o$next[3:0]$10847 + attribute \src "libresoc.v:176483.13-176483.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:168128.3-168157.6" - wire $1\wr_detect$10[0:0]$10812 - attribute \src "libresoc.v:168198.3-168227.6" - wire $1\wr_detect$13[0:0]$10826 - attribute \src "libresoc.v:167988.3-168017.6" - wire $1\wr_detect$4[0:0]$10784 - attribute \src "libresoc.v:168058.3-168087.6" - wire $1\wr_detect$7[0:0]$10798 - attribute \src "libresoc.v:167891.3-167920.6" + attribute \src "libresoc.v:176796.3-176825.6" + wire $1\wr_detect$10[0:0]$10869 + attribute \src "libresoc.v:176866.3-176895.6" + wire $1\wr_detect$13[0:0]$10883 + attribute \src "libresoc.v:176656.3-176685.6" + wire $1\wr_detect$4[0:0]$10841 + attribute \src "libresoc.v:176726.3-176755.6" + wire $1\wr_detect$7[0:0]$10855 + attribute \src "libresoc.v:176559.3-176588.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:168088.3-168127.6" - wire width 4 $2\r1__data_o$next[3:0]$10805 - attribute \src "libresoc.v:168158.3-168197.6" - wire width 4 $2\r21__data_o$next[3:0]$10819 - attribute \src "libresoc.v:167921.3-167947.6" - wire width 4 $2\reg$next[3:0]$10771 - attribute \src "libresoc.v:167851.3-167890.6" - wire width 4 $2\src11__data_o$next[3:0]$10762 - attribute \src "libresoc.v:167948.3-167987.6" - wire width 4 $2\src21__data_o$next[3:0]$10777 - attribute \src "libresoc.v:168018.3-168057.6" - wire width 4 $2\src31__data_o$next[3:0]$10791 - attribute \src "libresoc.v:168128.3-168157.6" - wire $2\wr_detect$10[0:0]$10813 - attribute \src "libresoc.v:168198.3-168227.6" - wire $2\wr_detect$13[0:0]$10827 - attribute \src "libresoc.v:167988.3-168017.6" - wire $2\wr_detect$4[0:0]$10785 - attribute \src "libresoc.v:168058.3-168087.6" - wire $2\wr_detect$7[0:0]$10799 - attribute \src "libresoc.v:167891.3-167920.6" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $2\r1__data_o$next[3:0]$10862 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $2\r21__data_o$next[3:0]$10876 + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $2\reg$next[3:0]$10828 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $2\src11__data_o$next[3:0]$10819 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $2\src21__data_o$next[3:0]$10834 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $2\src31__data_o$next[3:0]$10848 + attribute \src "libresoc.v:176796.3-176825.6" + wire $2\wr_detect$10[0:0]$10870 + attribute \src "libresoc.v:176866.3-176895.6" + wire $2\wr_detect$13[0:0]$10884 + attribute \src "libresoc.v:176656.3-176685.6" + wire $2\wr_detect$4[0:0]$10842 + attribute \src "libresoc.v:176726.3-176755.6" + wire $2\wr_detect$7[0:0]$10856 + attribute \src "libresoc.v:176559.3-176588.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:168088.3-168127.6" - wire width 4 $3\r1__data_o$next[3:0]$10806 - attribute \src "libresoc.v:168158.3-168197.6" - wire width 4 $3\r21__data_o$next[3:0]$10820 - attribute \src "libresoc.v:167921.3-167947.6" - wire width 4 $3\reg$next[3:0]$10772 - attribute \src "libresoc.v:167851.3-167890.6" - wire width 4 $3\src11__data_o$next[3:0]$10763 - attribute \src "libresoc.v:167948.3-167987.6" - wire width 4 $3\src21__data_o$next[3:0]$10778 - attribute \src "libresoc.v:168018.3-168057.6" - wire width 4 $3\src31__data_o$next[3:0]$10792 - attribute \src "libresoc.v:168128.3-168157.6" - wire $3\wr_detect$10[0:0]$10814 - attribute \src "libresoc.v:168198.3-168227.6" - wire $3\wr_detect$13[0:0]$10828 - attribute \src "libresoc.v:167988.3-168017.6" - wire $3\wr_detect$4[0:0]$10786 - attribute \src "libresoc.v:168058.3-168087.6" - wire $3\wr_detect$7[0:0]$10800 - attribute \src "libresoc.v:167891.3-167920.6" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $3\r1__data_o$next[3:0]$10863 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $3\r21__data_o$next[3:0]$10877 + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $3\reg$next[3:0]$10829 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $3\src11__data_o$next[3:0]$10820 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $3\src21__data_o$next[3:0]$10835 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $3\src31__data_o$next[3:0]$10849 + attribute \src "libresoc.v:176796.3-176825.6" + wire $3\wr_detect$10[0:0]$10871 + attribute \src "libresoc.v:176866.3-176895.6" + wire $3\wr_detect$13[0:0]$10885 + attribute \src "libresoc.v:176656.3-176685.6" + wire $3\wr_detect$4[0:0]$10843 + attribute \src "libresoc.v:176726.3-176755.6" + wire $3\wr_detect$7[0:0]$10857 + attribute \src "libresoc.v:176559.3-176588.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:168088.3-168127.6" - wire width 4 $4\r1__data_o$next[3:0]$10807 - attribute \src "libresoc.v:168158.3-168197.6" - wire width 4 $4\r21__data_o$next[3:0]$10821 - attribute \src "libresoc.v:167921.3-167947.6" - wire width 4 $4\reg$next[3:0]$10773 - attribute \src "libresoc.v:167851.3-167890.6" - wire width 4 $4\src11__data_o$next[3:0]$10764 - attribute \src "libresoc.v:167948.3-167987.6" - wire width 4 $4\src21__data_o$next[3:0]$10779 - attribute \src "libresoc.v:168018.3-168057.6" - wire width 4 $4\src31__data_o$next[3:0]$10793 - attribute \src "libresoc.v:168128.3-168157.6" - wire $4\wr_detect$10[0:0]$10815 - attribute \src "libresoc.v:168198.3-168227.6" - wire $4\wr_detect$13[0:0]$10829 - attribute \src "libresoc.v:167988.3-168017.6" - wire $4\wr_detect$4[0:0]$10787 - attribute \src "libresoc.v:168058.3-168087.6" - wire $4\wr_detect$7[0:0]$10801 - attribute \src "libresoc.v:167891.3-167920.6" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $4\r1__data_o$next[3:0]$10864 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $4\r21__data_o$next[3:0]$10878 + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $4\reg$next[3:0]$10830 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $4\src11__data_o$next[3:0]$10821 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $4\src21__data_o$next[3:0]$10836 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $4\src31__data_o$next[3:0]$10850 + attribute \src "libresoc.v:176796.3-176825.6" + wire $4\wr_detect$10[0:0]$10872 + attribute \src "libresoc.v:176866.3-176895.6" + wire $4\wr_detect$13[0:0]$10886 + attribute \src "libresoc.v:176656.3-176685.6" + wire $4\wr_detect$4[0:0]$10844 + attribute \src "libresoc.v:176726.3-176755.6" + wire $4\wr_detect$7[0:0]$10858 + attribute \src "libresoc.v:176559.3-176588.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:168088.3-168127.6" - wire width 4 $5\r1__data_o$next[3:0]$10808 - attribute \src "libresoc.v:168158.3-168197.6" - wire width 4 $5\r21__data_o$next[3:0]$10822 - attribute \src "libresoc.v:167851.3-167890.6" - wire width 4 $5\src11__data_o$next[3:0]$10765 - attribute \src "libresoc.v:167948.3-167987.6" - wire width 4 $5\src21__data_o$next[3:0]$10780 - attribute \src "libresoc.v:168018.3-168057.6" - wire width 4 $5\src31__data_o$next[3:0]$10794 - attribute \src "libresoc.v:168088.3-168127.6" - wire width 4 $6\r1__data_o$next[3:0]$10809 - attribute \src "libresoc.v:168158.3-168197.6" - wire width 4 $6\r21__data_o$next[3:0]$10823 - attribute \src "libresoc.v:167851.3-167890.6" - wire width 4 $6\src11__data_o$next[3:0]$10766 - attribute \src "libresoc.v:167948.3-167987.6" - wire width 4 $6\src21__data_o$next[3:0]$10781 - attribute \src "libresoc.v:168018.3-168057.6" - wire width 4 $6\src31__data_o$next[3:0]$10795 - attribute \src "libresoc.v:167834.17-167834.104" - wire $not$libresoc.v:167834$10748_Y - attribute \src "libresoc.v:167835.18-167835.105" - wire $not$libresoc.v:167835$10749_Y - attribute \src "libresoc.v:167836.17-167836.100" - wire $not$libresoc.v:167836$10750_Y - attribute \src "libresoc.v:167837.17-167837.103" - wire $not$libresoc.v:167837$10751_Y - attribute \src "libresoc.v:167838.17-167838.103" - wire $not$libresoc.v:167838$10752_Y + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $5\r1__data_o$next[3:0]$10865 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $5\r21__data_o$next[3:0]$10879 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $5\src11__data_o$next[3:0]$10822 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $5\src21__data_o$next[3:0]$10837 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $5\src31__data_o$next[3:0]$10851 + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $6\r1__data_o$next[3:0]$10866 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $6\r21__data_o$next[3:0]$10880 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $6\src11__data_o$next[3:0]$10823 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $6\src21__data_o$next[3:0]$10838 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $6\src31__data_o$next[3:0]$10852 + attribute \src "libresoc.v:176502.17-176502.104" + wire $not$libresoc.v:176502$10805_Y + attribute \src "libresoc.v:176503.18-176503.105" + wire $not$libresoc.v:176503$10806_Y + attribute \src "libresoc.v:176504.17-176504.100" + wire $not$libresoc.v:176504$10807_Y + attribute \src "libresoc.v:176505.17-176505.103" + wire $not$libresoc.v:176505$10808_Y + attribute \src "libresoc.v:176506.17-176506.103" + wire $not$libresoc.v:176506$10809_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -348395,57 +363336,57 @@ module \reg_1 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest21__wen - attribute \src "libresoc.v:167758.7-167758.15" + attribute \src "libresoc.v:176426.7-176426.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r21__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src11__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src31__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -348458,152 +363399,152 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167834$10748 + cell $not $not$libresoc.v:176502$10805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:167834$10748_Y + connect \Y $not$libresoc.v:176502$10805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167835$10749 + cell $not $not$libresoc.v:176503$10806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:167835$10749_Y + connect \Y $not$libresoc.v:176503$10806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167836$10750 + cell $not $not$libresoc.v:176504$10807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:167836$10750_Y + connect \Y $not$libresoc.v:176504$10807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167837$10751 + cell $not $not$libresoc.v:176505$10808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:167837$10751_Y + connect \Y $not$libresoc.v:176505$10808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167838$10752 + cell $not $not$libresoc.v:176506$10809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:167838$10752_Y + connect \Y $not$libresoc.v:176506$10809_Y end - attribute \src "libresoc.v:167758.7-167758.20" - process $proc$libresoc.v:167758$10830 + attribute \src "libresoc.v:176426.7-176426.20" + process $proc$libresoc.v:176426$10887 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167783.13-167783.30" - process $proc$libresoc.v:167783$10831 + attribute \src "libresoc.v:176451.13-176451.30" + process $proc$libresoc.v:176451$10888 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:167790.13-167790.31" - process $proc$libresoc.v:167790$10832 + attribute \src "libresoc.v:176458.13-176458.31" + process $proc$libresoc.v:176458$10889 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:167796.13-167796.25" - process $proc$libresoc.v:167796$10833 + attribute \src "libresoc.v:176464.13-176464.25" + process $proc$libresoc.v:176464$10890 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:167801.13-167801.33" - process $proc$libresoc.v:167801$10834 + attribute \src "libresoc.v:176469.13-176469.33" + process $proc$libresoc.v:176469$10891 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:167808.13-167808.33" - process $proc$libresoc.v:167808$10835 + attribute \src "libresoc.v:176476.13-176476.33" + process $proc$libresoc.v:176476$10892 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:167815.13-167815.33" - process $proc$libresoc.v:167815$10836 + attribute \src "libresoc.v:176483.13-176483.33" + process $proc$libresoc.v:176483$10893 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:167839.3-167840.25" - process $proc$libresoc.v:167839$10753 + attribute \src "libresoc.v:176507.3-176508.25" + process $proc$libresoc.v:176507$10810 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:167841.3-167842.39" - process $proc$libresoc.v:167841$10754 + attribute \src "libresoc.v:176509.3-176510.39" + process $proc$libresoc.v:176509$10811 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:167843.3-167844.37" - process $proc$libresoc.v:167843$10755 + attribute \src "libresoc.v:176511.3-176512.37" + process $proc$libresoc.v:176511$10812 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:167845.3-167846.43" - process $proc$libresoc.v:167845$10756 + attribute \src "libresoc.v:176513.3-176514.43" + process $proc$libresoc.v:176513$10813 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:167847.3-167848.43" - process $proc$libresoc.v:167847$10757 + attribute \src "libresoc.v:176515.3-176516.43" + process $proc$libresoc.v:176515$10814 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:167849.3-167850.43" - process $proc$libresoc.v:167849$10758 + attribute \src "libresoc.v:176517.3-176518.43" + process $proc$libresoc.v:176517$10815 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:167851.3-167890.6" - process $proc$libresoc.v:167851$10759 + attribute \src "libresoc.v:176519.3-176558.6" + process $proc$libresoc.v:176519$10816 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$10760 $6\src11__data_o$next[3:0]$10766 - attribute \src "libresoc.v:167852.5-167852.29" + assign $0\src11__data_o$next[3:0]$10817 $6\src11__data_o$next[3:0]$10823 + attribute \src "libresoc.v:176520.5-176520.29" switch \initial - attribute \src "libresoc.v:167852.9-167852.17" + attribute \src "libresoc.v:176520.9-176520.17" case 1'1 case end @@ -348615,66 +363556,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$10761 $5\src11__data_o$next[3:0]$10765 + assign $1\src11__data_o$next[3:0]$10818 $5\src11__data_o$next[3:0]$10822 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$10762 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10819 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$10762 4'0000 + assign $2\src11__data_o$next[3:0]$10819 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$10763 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10820 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$10763 $2\src11__data_o$next[3:0]$10762 + assign $3\src11__data_o$next[3:0]$10820 $2\src11__data_o$next[3:0]$10819 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$10764 \w1__data_i + assign $4\src11__data_o$next[3:0]$10821 \w1__data_i case - assign $4\src11__data_o$next[3:0]$10764 $3\src11__data_o$next[3:0]$10763 + assign $4\src11__data_o$next[3:0]$10821 $3\src11__data_o$next[3:0]$10820 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$10765 \reg + assign $5\src11__data_o$next[3:0]$10822 \reg case - assign $5\src11__data_o$next[3:0]$10765 $4\src11__data_o$next[3:0]$10764 + assign $5\src11__data_o$next[3:0]$10822 $4\src11__data_o$next[3:0]$10821 end case - assign $1\src11__data_o$next[3:0]$10761 4'0000 + assign $1\src11__data_o$next[3:0]$10818 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$10766 4'0000 + assign $6\src11__data_o$next[3:0]$10823 4'0000 case - assign $6\src11__data_o$next[3:0]$10766 $1\src11__data_o$next[3:0]$10761 + assign $6\src11__data_o$next[3:0]$10823 $1\src11__data_o$next[3:0]$10818 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10760 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10817 end - attribute \src "libresoc.v:167891.3-167920.6" - process $proc$libresoc.v:167891$10767 + attribute \src "libresoc.v:176559.3-176588.6" + process $proc$libresoc.v:176559$10824 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:167892.5-167892.29" + attribute \src "libresoc.v:176560.5-176560.29" switch \initial - attribute \src "libresoc.v:167892.9-167892.17" + attribute \src "libresoc.v:176560.9-176560.17" case 1'1 case end @@ -348720,17 +363661,17 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:167921.3-167947.6" - process $proc$libresoc.v:167921$10768 + attribute \src "libresoc.v:176589.3-176615.6" + process $proc$libresoc.v:176589$10825 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10769 $4\reg$next[3:0]$10773 - attribute \src "libresoc.v:167922.5-167922.29" + assign $0\reg$next[3:0]$10826 $4\reg$next[3:0]$10830 + attribute \src "libresoc.v:176590.5-176590.29" switch \initial - attribute \src "libresoc.v:167922.9-167922.17" + attribute \src "libresoc.v:176590.9-176590.17" case 1'1 case end @@ -348739,49 +363680,49 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10770 \dest11__data_i + assign $1\reg$next[3:0]$10827 \dest11__data_i case - assign $1\reg$next[3:0]$10770 \reg + assign $1\reg$next[3:0]$10827 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10771 \dest21__data_i + assign $2\reg$next[3:0]$10828 \dest21__data_i case - assign $2\reg$next[3:0]$10771 $1\reg$next[3:0]$10770 + assign $2\reg$next[3:0]$10828 $1\reg$next[3:0]$10827 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10772 \w1__data_i + assign $3\reg$next[3:0]$10829 \w1__data_i case - assign $3\reg$next[3:0]$10772 $2\reg$next[3:0]$10771 + assign $3\reg$next[3:0]$10829 $2\reg$next[3:0]$10828 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10773 4'0000 + assign $4\reg$next[3:0]$10830 4'0000 case - assign $4\reg$next[3:0]$10773 $3\reg$next[3:0]$10772 + assign $4\reg$next[3:0]$10830 $3\reg$next[3:0]$10829 end sync always - update \reg$next $0\reg$next[3:0]$10769 + update \reg$next $0\reg$next[3:0]$10826 end - attribute \src "libresoc.v:167948.3-167987.6" - process $proc$libresoc.v:167948$10774 + attribute \src "libresoc.v:176616.3-176655.6" + process $proc$libresoc.v:176616$10831 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$10775 $6\src21__data_o$next[3:0]$10781 - attribute \src "libresoc.v:167949.5-167949.29" + assign $0\src21__data_o$next[3:0]$10832 $6\src21__data_o$next[3:0]$10838 + attribute \src "libresoc.v:176617.5-176617.29" switch \initial - attribute \src "libresoc.v:167949.9-167949.17" + attribute \src "libresoc.v:176617.9-176617.17" case 1'1 case end @@ -348793,66 +363734,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$10776 $5\src21__data_o$next[3:0]$10780 + assign $1\src21__data_o$next[3:0]$10833 $5\src21__data_o$next[3:0]$10837 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$10777 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10834 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$10777 4'0000 + assign $2\src21__data_o$next[3:0]$10834 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$10778 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10835 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$10778 $2\src21__data_o$next[3:0]$10777 + assign $3\src21__data_o$next[3:0]$10835 $2\src21__data_o$next[3:0]$10834 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$10779 \w1__data_i + assign $4\src21__data_o$next[3:0]$10836 \w1__data_i case - assign $4\src21__data_o$next[3:0]$10779 $3\src21__data_o$next[3:0]$10778 + assign $4\src21__data_o$next[3:0]$10836 $3\src21__data_o$next[3:0]$10835 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$10780 \reg + assign $5\src21__data_o$next[3:0]$10837 \reg case - assign $5\src21__data_o$next[3:0]$10780 $4\src21__data_o$next[3:0]$10779 + assign $5\src21__data_o$next[3:0]$10837 $4\src21__data_o$next[3:0]$10836 end case - assign $1\src21__data_o$next[3:0]$10776 4'0000 + assign $1\src21__data_o$next[3:0]$10833 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$10781 4'0000 + assign $6\src21__data_o$next[3:0]$10838 4'0000 case - assign $6\src21__data_o$next[3:0]$10781 $1\src21__data_o$next[3:0]$10776 + assign $6\src21__data_o$next[3:0]$10838 $1\src21__data_o$next[3:0]$10833 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10775 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10832 end - attribute \src "libresoc.v:167988.3-168017.6" - process $proc$libresoc.v:167988$10782 + attribute \src "libresoc.v:176656.3-176685.6" + process $proc$libresoc.v:176656$10839 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10783 $1\wr_detect$4[0:0]$10784 - attribute \src "libresoc.v:167989.5-167989.29" + assign $0\wr_detect$4[0:0]$10840 $1\wr_detect$4[0:0]$10841 + attribute \src "libresoc.v:176657.5-176657.29" switch \initial - attribute \src "libresoc.v:167989.9-167989.17" + attribute \src "libresoc.v:176657.9-176657.17" case 1'1 case end @@ -348864,49 +363805,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10784 $4\wr_detect$4[0:0]$10787 + assign $1\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10844 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10785 1'1 + assign $2\wr_detect$4[0:0]$10842 1'1 case - assign $2\wr_detect$4[0:0]$10785 1'0 + assign $2\wr_detect$4[0:0]$10842 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10786 1'1 + assign $3\wr_detect$4[0:0]$10843 1'1 case - assign $3\wr_detect$4[0:0]$10786 $2\wr_detect$4[0:0]$10785 + assign $3\wr_detect$4[0:0]$10843 $2\wr_detect$4[0:0]$10842 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10787 1'1 + assign $4\wr_detect$4[0:0]$10844 1'1 case - assign $4\wr_detect$4[0:0]$10787 $3\wr_detect$4[0:0]$10786 + assign $4\wr_detect$4[0:0]$10844 $3\wr_detect$4[0:0]$10843 end case - assign $1\wr_detect$4[0:0]$10784 1'0 + assign $1\wr_detect$4[0:0]$10841 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10783 + update \wr_detect$4 $0\wr_detect$4[0:0]$10840 end - attribute \src "libresoc.v:168018.3-168057.6" - process $proc$libresoc.v:168018$10788 + attribute \src "libresoc.v:176686.3-176725.6" + process $proc$libresoc.v:176686$10845 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$10789 $6\src31__data_o$next[3:0]$10795 - attribute \src "libresoc.v:168019.5-168019.29" + assign $0\src31__data_o$next[3:0]$10846 $6\src31__data_o$next[3:0]$10852 + attribute \src "libresoc.v:176687.5-176687.29" switch \initial - attribute \src "libresoc.v:168019.9-168019.17" + attribute \src "libresoc.v:176687.9-176687.17" case 1'1 case end @@ -348918,66 +363859,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$10790 $5\src31__data_o$next[3:0]$10794 + assign $1\src31__data_o$next[3:0]$10847 $5\src31__data_o$next[3:0]$10851 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$10791 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10848 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$10791 4'0000 + assign $2\src31__data_o$next[3:0]$10848 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$10792 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10849 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$10792 $2\src31__data_o$next[3:0]$10791 + assign $3\src31__data_o$next[3:0]$10849 $2\src31__data_o$next[3:0]$10848 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$10793 \w1__data_i + assign $4\src31__data_o$next[3:0]$10850 \w1__data_i case - assign $4\src31__data_o$next[3:0]$10793 $3\src31__data_o$next[3:0]$10792 + assign $4\src31__data_o$next[3:0]$10850 $3\src31__data_o$next[3:0]$10849 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$10794 \reg + assign $5\src31__data_o$next[3:0]$10851 \reg case - assign $5\src31__data_o$next[3:0]$10794 $4\src31__data_o$next[3:0]$10793 + assign $5\src31__data_o$next[3:0]$10851 $4\src31__data_o$next[3:0]$10850 end case - assign $1\src31__data_o$next[3:0]$10790 4'0000 + assign $1\src31__data_o$next[3:0]$10847 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$10795 4'0000 + assign $6\src31__data_o$next[3:0]$10852 4'0000 case - assign $6\src31__data_o$next[3:0]$10795 $1\src31__data_o$next[3:0]$10790 + assign $6\src31__data_o$next[3:0]$10852 $1\src31__data_o$next[3:0]$10847 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10789 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10846 end - attribute \src "libresoc.v:168058.3-168087.6" - process $proc$libresoc.v:168058$10796 + attribute \src "libresoc.v:176726.3-176755.6" + process $proc$libresoc.v:176726$10853 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10797 $1\wr_detect$7[0:0]$10798 - attribute \src "libresoc.v:168059.5-168059.29" + assign $0\wr_detect$7[0:0]$10854 $1\wr_detect$7[0:0]$10855 + attribute \src "libresoc.v:176727.5-176727.29" switch \initial - attribute \src "libresoc.v:168059.9-168059.17" + attribute \src "libresoc.v:176727.9-176727.17" case 1'1 case end @@ -348989,49 +363930,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10798 $4\wr_detect$7[0:0]$10801 + assign $1\wr_detect$7[0:0]$10855 $4\wr_detect$7[0:0]$10858 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10799 1'1 + assign $2\wr_detect$7[0:0]$10856 1'1 case - assign $2\wr_detect$7[0:0]$10799 1'0 + assign $2\wr_detect$7[0:0]$10856 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10800 1'1 + assign $3\wr_detect$7[0:0]$10857 1'1 case - assign $3\wr_detect$7[0:0]$10800 $2\wr_detect$7[0:0]$10799 + assign $3\wr_detect$7[0:0]$10857 $2\wr_detect$7[0:0]$10856 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10801 1'1 + assign $4\wr_detect$7[0:0]$10858 1'1 case - assign $4\wr_detect$7[0:0]$10801 $3\wr_detect$7[0:0]$10800 + assign $4\wr_detect$7[0:0]$10858 $3\wr_detect$7[0:0]$10857 end case - assign $1\wr_detect$7[0:0]$10798 1'0 + assign $1\wr_detect$7[0:0]$10855 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10797 + update \wr_detect$7 $0\wr_detect$7[0:0]$10854 end - attribute \src "libresoc.v:168088.3-168127.6" - process $proc$libresoc.v:168088$10802 + attribute \src "libresoc.v:176756.3-176795.6" + process $proc$libresoc.v:176756$10859 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10803 $6\r1__data_o$next[3:0]$10809 - attribute \src "libresoc.v:168089.5-168089.29" + assign $0\r1__data_o$next[3:0]$10860 $6\r1__data_o$next[3:0]$10866 + attribute \src "libresoc.v:176757.5-176757.29" switch \initial - attribute \src "libresoc.v:168089.9-168089.17" + attribute \src "libresoc.v:176757.9-176757.17" case 1'1 case end @@ -349043,66 +363984,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$10804 $5\r1__data_o$next[3:0]$10808 + assign $1\r1__data_o$next[3:0]$10861 $5\r1__data_o$next[3:0]$10865 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$10805 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10862 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$10805 4'0000 + assign $2\r1__data_o$next[3:0]$10862 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$10806 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10863 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$10806 $2\r1__data_o$next[3:0]$10805 + assign $3\r1__data_o$next[3:0]$10863 $2\r1__data_o$next[3:0]$10862 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$10807 \w1__data_i + assign $4\r1__data_o$next[3:0]$10864 \w1__data_i case - assign $4\r1__data_o$next[3:0]$10807 $3\r1__data_o$next[3:0]$10806 + assign $4\r1__data_o$next[3:0]$10864 $3\r1__data_o$next[3:0]$10863 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$10808 \reg + assign $5\r1__data_o$next[3:0]$10865 \reg case - assign $5\r1__data_o$next[3:0]$10808 $4\r1__data_o$next[3:0]$10807 + assign $5\r1__data_o$next[3:0]$10865 $4\r1__data_o$next[3:0]$10864 end case - assign $1\r1__data_o$next[3:0]$10804 4'0000 + assign $1\r1__data_o$next[3:0]$10861 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$10809 4'0000 + assign $6\r1__data_o$next[3:0]$10866 4'0000 case - assign $6\r1__data_o$next[3:0]$10809 $1\r1__data_o$next[3:0]$10804 + assign $6\r1__data_o$next[3:0]$10866 $1\r1__data_o$next[3:0]$10861 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10803 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10860 end - attribute \src "libresoc.v:168128.3-168157.6" - process $proc$libresoc.v:168128$10810 + attribute \src "libresoc.v:176796.3-176825.6" + process $proc$libresoc.v:176796$10867 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10811 $1\wr_detect$10[0:0]$10812 - attribute \src "libresoc.v:168129.5-168129.29" + assign $0\wr_detect$10[0:0]$10868 $1\wr_detect$10[0:0]$10869 + attribute \src "libresoc.v:176797.5-176797.29" switch \initial - attribute \src "libresoc.v:168129.9-168129.17" + attribute \src "libresoc.v:176797.9-176797.17" case 1'1 case end @@ -349114,49 +364055,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10812 $4\wr_detect$10[0:0]$10815 + assign $1\wr_detect$10[0:0]$10869 $4\wr_detect$10[0:0]$10872 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10813 1'1 + assign $2\wr_detect$10[0:0]$10870 1'1 case - assign $2\wr_detect$10[0:0]$10813 1'0 + assign $2\wr_detect$10[0:0]$10870 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10814 1'1 + assign $3\wr_detect$10[0:0]$10871 1'1 case - assign $3\wr_detect$10[0:0]$10814 $2\wr_detect$10[0:0]$10813 + assign $3\wr_detect$10[0:0]$10871 $2\wr_detect$10[0:0]$10870 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10815 1'1 + assign $4\wr_detect$10[0:0]$10872 1'1 case - assign $4\wr_detect$10[0:0]$10815 $3\wr_detect$10[0:0]$10814 + assign $4\wr_detect$10[0:0]$10872 $3\wr_detect$10[0:0]$10871 end case - assign $1\wr_detect$10[0:0]$10812 1'0 + assign $1\wr_detect$10[0:0]$10869 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10811 + update \wr_detect$10 $0\wr_detect$10[0:0]$10868 end - attribute \src "libresoc.v:168158.3-168197.6" - process $proc$libresoc.v:168158$10816 + attribute \src "libresoc.v:176826.3-176865.6" + process $proc$libresoc.v:176826$10873 assign { } { } assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$10817 $6\r21__data_o$next[3:0]$10823 - attribute \src "libresoc.v:168159.5-168159.29" + assign $0\r21__data_o$next[3:0]$10874 $6\r21__data_o$next[3:0]$10880 + attribute \src "libresoc.v:176827.5-176827.29" switch \initial - attribute \src "libresoc.v:168159.9-168159.17" + attribute \src "libresoc.v:176827.9-176827.17" case 1'1 case end @@ -349168,66 +364109,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$10818 $5\r21__data_o$next[3:0]$10822 + assign $1\r21__data_o$next[3:0]$10875 $5\r21__data_o$next[3:0]$10879 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$10819 \dest11__data_i + assign $2\r21__data_o$next[3:0]$10876 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$10819 4'0000 + assign $2\r21__data_o$next[3:0]$10876 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$10820 \dest21__data_i + assign $3\r21__data_o$next[3:0]$10877 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$10820 $2\r21__data_o$next[3:0]$10819 + assign $3\r21__data_o$next[3:0]$10877 $2\r21__data_o$next[3:0]$10876 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$10821 \w1__data_i + assign $4\r21__data_o$next[3:0]$10878 \w1__data_i case - assign $4\r21__data_o$next[3:0]$10821 $3\r21__data_o$next[3:0]$10820 + assign $4\r21__data_o$next[3:0]$10878 $3\r21__data_o$next[3:0]$10877 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$10822 \reg + assign $5\r21__data_o$next[3:0]$10879 \reg case - assign $5\r21__data_o$next[3:0]$10822 $4\r21__data_o$next[3:0]$10821 + assign $5\r21__data_o$next[3:0]$10879 $4\r21__data_o$next[3:0]$10878 end case - assign $1\r21__data_o$next[3:0]$10818 4'0000 + assign $1\r21__data_o$next[3:0]$10875 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$10823 4'0000 + assign $6\r21__data_o$next[3:0]$10880 4'0000 case - assign $6\r21__data_o$next[3:0]$10823 $1\r21__data_o$next[3:0]$10818 + assign $6\r21__data_o$next[3:0]$10880 $1\r21__data_o$next[3:0]$10875 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10817 + update \r21__data_o$next $0\r21__data_o$next[3:0]$10874 end - attribute \src "libresoc.v:168198.3-168227.6" - process $proc$libresoc.v:168198$10824 + attribute \src "libresoc.v:176866.3-176895.6" + process $proc$libresoc.v:176866$10881 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10825 $1\wr_detect$13[0:0]$10826 - attribute \src "libresoc.v:168199.5-168199.29" + assign $0\wr_detect$13[0:0]$10882 $1\wr_detect$13[0:0]$10883 + attribute \src "libresoc.v:176867.5-176867.29" switch \initial - attribute \src "libresoc.v:168199.9-168199.17" + attribute \src "libresoc.v:176867.9-176867.17" case 1'1 case end @@ -349239,205 +364180,205 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10826 $4\wr_detect$13[0:0]$10829 + assign $1\wr_detect$13[0:0]$10883 $4\wr_detect$13[0:0]$10886 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10827 1'1 + assign $2\wr_detect$13[0:0]$10884 1'1 case - assign $2\wr_detect$13[0:0]$10827 1'0 + assign $2\wr_detect$13[0:0]$10884 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10828 1'1 + assign $3\wr_detect$13[0:0]$10885 1'1 case - assign $3\wr_detect$13[0:0]$10828 $2\wr_detect$13[0:0]$10827 + assign $3\wr_detect$13[0:0]$10885 $2\wr_detect$13[0:0]$10884 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10829 1'1 + assign $4\wr_detect$13[0:0]$10886 1'1 case - assign $4\wr_detect$13[0:0]$10829 $3\wr_detect$13[0:0]$10828 + assign $4\wr_detect$13[0:0]$10886 $3\wr_detect$13[0:0]$10885 end case - assign $1\wr_detect$13[0:0]$10826 1'0 + assign $1\wr_detect$13[0:0]$10883 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10825 + update \wr_detect$13 $0\wr_detect$13[0:0]$10882 end - connect \$9 $not$libresoc.v:167834$10748_Y - connect \$12 $not$libresoc.v:167835$10749_Y - connect \$1 $not$libresoc.v:167836$10750_Y - connect \$3 $not$libresoc.v:167837$10751_Y - connect \$6 $not$libresoc.v:167838$10752_Y + connect \$9 $not$libresoc.v:176502$10805_Y + connect \$12 $not$libresoc.v:176503$10806_Y + connect \$1 $not$libresoc.v:176504$10807_Y + connect \$3 $not$libresoc.v:176505$10808_Y + connect \$6 $not$libresoc.v:176506$10809_Y end -attribute \src "libresoc.v:168232.1-168677.10" +attribute \src "libresoc.v:176900.1-177345.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:168233.7-168233.20" + attribute \src "libresoc.v:176901.7-176901.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168562.3-168607.6" - wire width 2 $0\r1__data_o$next[1:0]$10889 - attribute \src "libresoc.v:168308.3-168309.37" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $0\r1__data_o$next[1:0]$10946 + attribute \src "libresoc.v:176976.3-176977.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:168644.3-168676.6" - wire width 2 $0\reg$next[1:0]$10905 - attribute \src "libresoc.v:168306.3-168307.25" + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $0\reg$next[1:0]$10962 + attribute \src "libresoc.v:176974.3-176975.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:168316.3-168361.6" - wire width 2 $0\src11__data_o$next[1:0]$10847 - attribute \src "libresoc.v:168314.3-168315.43" + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $0\src11__data_o$next[1:0]$10904 + attribute \src "libresoc.v:176982.3-176983.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:168398.3-168443.6" - wire width 2 $0\src21__data_o$next[1:0]$10857 - attribute \src "libresoc.v:168312.3-168313.43" + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $0\src21__data_o$next[1:0]$10914 + attribute \src "libresoc.v:176980.3-176981.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:168480.3-168525.6" - wire width 2 $0\src31__data_o$next[1:0]$10873 - attribute \src "libresoc.v:168310.3-168311.43" + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $0\src31__data_o$next[1:0]$10930 + attribute \src "libresoc.v:176978.3-176979.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:168608.3-168643.6" - wire $0\wr_detect$10[0:0]$10898 - attribute \src "libresoc.v:168444.3-168479.6" - wire $0\wr_detect$4[0:0]$10866 - attribute \src "libresoc.v:168526.3-168561.6" - wire $0\wr_detect$7[0:0]$10882 - attribute \src "libresoc.v:168362.3-168397.6" + attribute \src "libresoc.v:177276.3-177311.6" + wire $0\wr_detect$10[0:0]$10955 + attribute \src "libresoc.v:177112.3-177147.6" + wire $0\wr_detect$4[0:0]$10923 + attribute \src "libresoc.v:177194.3-177229.6" + wire $0\wr_detect$7[0:0]$10939 + attribute \src "libresoc.v:177030.3-177065.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:168562.3-168607.6" - wire width 2 $1\r1__data_o$next[1:0]$10890 - attribute \src "libresoc.v:168260.13-168260.30" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $1\r1__data_o$next[1:0]$10947 + attribute \src "libresoc.v:176928.13-176928.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:168644.3-168676.6" - wire width 2 $1\reg$next[1:0]$10906 - attribute \src "libresoc.v:168266.13-168266.25" + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $1\reg$next[1:0]$10963 + attribute \src "libresoc.v:176934.13-176934.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:168316.3-168361.6" - wire width 2 $1\src11__data_o$next[1:0]$10848 - attribute \src "libresoc.v:168271.13-168271.33" + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $1\src11__data_o$next[1:0]$10905 + attribute \src "libresoc.v:176939.13-176939.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:168398.3-168443.6" - wire width 2 $1\src21__data_o$next[1:0]$10858 - attribute \src "libresoc.v:168278.13-168278.33" + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $1\src21__data_o$next[1:0]$10915 + attribute \src "libresoc.v:176946.13-176946.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:168480.3-168525.6" - wire width 2 $1\src31__data_o$next[1:0]$10874 - attribute \src "libresoc.v:168285.13-168285.33" + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $1\src31__data_o$next[1:0]$10931 + attribute \src "libresoc.v:176953.13-176953.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:168608.3-168643.6" - wire $1\wr_detect$10[0:0]$10899 - attribute \src "libresoc.v:168444.3-168479.6" - wire $1\wr_detect$4[0:0]$10867 - attribute \src "libresoc.v:168526.3-168561.6" - wire $1\wr_detect$7[0:0]$10883 - attribute \src "libresoc.v:168362.3-168397.6" + attribute \src "libresoc.v:177276.3-177311.6" + wire $1\wr_detect$10[0:0]$10956 + attribute \src "libresoc.v:177112.3-177147.6" + wire $1\wr_detect$4[0:0]$10924 + attribute \src "libresoc.v:177194.3-177229.6" + wire $1\wr_detect$7[0:0]$10940 + attribute \src "libresoc.v:177030.3-177065.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:168562.3-168607.6" - wire width 2 $2\r1__data_o$next[1:0]$10891 - attribute \src "libresoc.v:168644.3-168676.6" - wire width 2 $2\reg$next[1:0]$10907 - attribute \src "libresoc.v:168316.3-168361.6" - wire width 2 $2\src11__data_o$next[1:0]$10849 - attribute \src "libresoc.v:168398.3-168443.6" - wire width 2 $2\src21__data_o$next[1:0]$10859 - attribute \src "libresoc.v:168480.3-168525.6" - wire width 2 $2\src31__data_o$next[1:0]$10875 - attribute \src "libresoc.v:168608.3-168643.6" - wire $2\wr_detect$10[0:0]$10900 - attribute \src "libresoc.v:168444.3-168479.6" - wire $2\wr_detect$4[0:0]$10868 - attribute \src "libresoc.v:168526.3-168561.6" - wire $2\wr_detect$7[0:0]$10884 - attribute \src "libresoc.v:168362.3-168397.6" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $2\r1__data_o$next[1:0]$10948 + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $2\reg$next[1:0]$10964 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $2\src11__data_o$next[1:0]$10906 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $2\src21__data_o$next[1:0]$10916 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $2\src31__data_o$next[1:0]$10932 + attribute \src "libresoc.v:177276.3-177311.6" + wire $2\wr_detect$10[0:0]$10957 + attribute \src "libresoc.v:177112.3-177147.6" + wire $2\wr_detect$4[0:0]$10925 + attribute \src "libresoc.v:177194.3-177229.6" + wire $2\wr_detect$7[0:0]$10941 + attribute \src "libresoc.v:177030.3-177065.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:168562.3-168607.6" - wire width 2 $3\r1__data_o$next[1:0]$10892 - attribute \src "libresoc.v:168644.3-168676.6" - wire width 2 $3\reg$next[1:0]$10908 - attribute \src "libresoc.v:168316.3-168361.6" - wire width 2 $3\src11__data_o$next[1:0]$10850 - attribute \src "libresoc.v:168398.3-168443.6" - wire width 2 $3\src21__data_o$next[1:0]$10860 - attribute \src "libresoc.v:168480.3-168525.6" - wire width 2 $3\src31__data_o$next[1:0]$10876 - attribute \src "libresoc.v:168608.3-168643.6" - wire $3\wr_detect$10[0:0]$10901 - attribute \src "libresoc.v:168444.3-168479.6" - wire $3\wr_detect$4[0:0]$10869 - attribute \src "libresoc.v:168526.3-168561.6" - wire $3\wr_detect$7[0:0]$10885 - attribute \src "libresoc.v:168362.3-168397.6" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $3\r1__data_o$next[1:0]$10949 + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $3\reg$next[1:0]$10965 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $3\src11__data_o$next[1:0]$10907 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $3\src21__data_o$next[1:0]$10917 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $3\src31__data_o$next[1:0]$10933 + attribute \src "libresoc.v:177276.3-177311.6" + wire $3\wr_detect$10[0:0]$10958 + attribute \src "libresoc.v:177112.3-177147.6" + wire $3\wr_detect$4[0:0]$10926 + attribute \src "libresoc.v:177194.3-177229.6" + wire $3\wr_detect$7[0:0]$10942 + attribute \src "libresoc.v:177030.3-177065.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:168562.3-168607.6" - wire width 2 $4\r1__data_o$next[1:0]$10893 - attribute \src "libresoc.v:168644.3-168676.6" - wire width 2 $4\reg$next[1:0]$10909 - attribute \src "libresoc.v:168316.3-168361.6" - wire width 2 $4\src11__data_o$next[1:0]$10851 - attribute \src "libresoc.v:168398.3-168443.6" - wire width 2 $4\src21__data_o$next[1:0]$10861 - attribute \src "libresoc.v:168480.3-168525.6" - wire width 2 $4\src31__data_o$next[1:0]$10877 - attribute \src "libresoc.v:168608.3-168643.6" - wire $4\wr_detect$10[0:0]$10902 - attribute \src "libresoc.v:168444.3-168479.6" - wire $4\wr_detect$4[0:0]$10870 - attribute \src "libresoc.v:168526.3-168561.6" - wire $4\wr_detect$7[0:0]$10886 - attribute \src "libresoc.v:168362.3-168397.6" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $4\r1__data_o$next[1:0]$10950 + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $4\reg$next[1:0]$10966 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $4\src11__data_o$next[1:0]$10908 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $4\src21__data_o$next[1:0]$10918 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $4\src31__data_o$next[1:0]$10934 + attribute \src "libresoc.v:177276.3-177311.6" + wire $4\wr_detect$10[0:0]$10959 + attribute \src "libresoc.v:177112.3-177147.6" + wire $4\wr_detect$4[0:0]$10927 + attribute \src "libresoc.v:177194.3-177229.6" + wire $4\wr_detect$7[0:0]$10943 + attribute \src "libresoc.v:177030.3-177065.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:168562.3-168607.6" - wire width 2 $5\r1__data_o$next[1:0]$10894 - attribute \src "libresoc.v:168644.3-168676.6" - wire width 2 $5\reg$next[1:0]$10910 - attribute \src "libresoc.v:168316.3-168361.6" - wire width 2 $5\src11__data_o$next[1:0]$10852 - attribute \src "libresoc.v:168398.3-168443.6" - wire width 2 $5\src21__data_o$next[1:0]$10862 - attribute \src "libresoc.v:168480.3-168525.6" - wire width 2 $5\src31__data_o$next[1:0]$10878 - attribute \src "libresoc.v:168608.3-168643.6" - wire $5\wr_detect$10[0:0]$10903 - attribute \src "libresoc.v:168444.3-168479.6" - wire $5\wr_detect$4[0:0]$10871 - attribute \src "libresoc.v:168526.3-168561.6" - wire $5\wr_detect$7[0:0]$10887 - attribute \src "libresoc.v:168362.3-168397.6" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $5\r1__data_o$next[1:0]$10951 + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $5\reg$next[1:0]$10967 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $5\src11__data_o$next[1:0]$10909 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $5\src21__data_o$next[1:0]$10919 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $5\src31__data_o$next[1:0]$10935 + attribute \src "libresoc.v:177276.3-177311.6" + wire $5\wr_detect$10[0:0]$10960 + attribute \src "libresoc.v:177112.3-177147.6" + wire $5\wr_detect$4[0:0]$10928 + attribute \src "libresoc.v:177194.3-177229.6" + wire $5\wr_detect$7[0:0]$10944 + attribute \src "libresoc.v:177030.3-177065.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:168562.3-168607.6" - wire width 2 $6\r1__data_o$next[1:0]$10895 - attribute \src "libresoc.v:168316.3-168361.6" - wire width 2 $6\src11__data_o$next[1:0]$10853 - attribute \src "libresoc.v:168398.3-168443.6" - wire width 2 $6\src21__data_o$next[1:0]$10863 - attribute \src "libresoc.v:168480.3-168525.6" - wire width 2 $6\src31__data_o$next[1:0]$10879 - attribute \src "libresoc.v:168562.3-168607.6" - wire width 2 $7\r1__data_o$next[1:0]$10896 - attribute \src "libresoc.v:168316.3-168361.6" - wire width 2 $7\src11__data_o$next[1:0]$10854 - attribute \src "libresoc.v:168398.3-168443.6" - wire width 2 $7\src21__data_o$next[1:0]$10864 - attribute \src "libresoc.v:168480.3-168525.6" - wire width 2 $7\src31__data_o$next[1:0]$10880 - attribute \src "libresoc.v:168302.17-168302.104" - wire $not$libresoc.v:168302$10837_Y - attribute \src "libresoc.v:168303.17-168303.100" - wire $not$libresoc.v:168303$10838_Y - attribute \src "libresoc.v:168304.17-168304.103" - wire $not$libresoc.v:168304$10839_Y - attribute \src "libresoc.v:168305.17-168305.103" - wire $not$libresoc.v:168305$10840_Y + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $6\r1__data_o$next[1:0]$10952 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $6\src11__data_o$next[1:0]$10910 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $6\src21__data_o$next[1:0]$10920 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $6\src31__data_o$next[1:0]$10936 + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $7\r1__data_o$next[1:0]$10953 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $7\src11__data_o$next[1:0]$10911 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $7\src21__data_o$next[1:0]$10921 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $7\src31__data_o$next[1:0]$10937 + attribute \src "libresoc.v:176970.17-176970.104" + wire $not$libresoc.v:176970$10894_Y + attribute \src "libresoc.v:176971.17-176971.100" + wire $not$libresoc.v:176971$10895_Y + attribute \src "libresoc.v:176972.17-176972.103" + wire $not$libresoc.v:176972$10896_Y + attribute \src "libresoc.v:176973.17-176973.103" + wire $not$libresoc.v:176973$10897_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -349446,55 +364387,55 @@ module \reg_1$133 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 13 \dest31__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:168233.7-168233.15" + attribute \src "libresoc.v:176901.7-176901.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \r1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r1__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src11__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src31__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -349505,129 +364446,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168302$10837 + cell $not $not$libresoc.v:176970$10894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:168302$10837_Y + connect \Y $not$libresoc.v:176970$10894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168303$10838 + cell $not $not$libresoc.v:176971$10895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:168303$10838_Y + connect \Y $not$libresoc.v:176971$10895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168304$10839 + cell $not $not$libresoc.v:176972$10896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:168304$10839_Y + connect \Y $not$libresoc.v:176972$10896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168305$10840 + cell $not $not$libresoc.v:176973$10897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:168305$10840_Y + connect \Y $not$libresoc.v:176973$10897_Y end - attribute \src "libresoc.v:168233.7-168233.20" - process $proc$libresoc.v:168233$10911 + attribute \src "libresoc.v:176901.7-176901.20" + process $proc$libresoc.v:176901$10968 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168260.13-168260.30" - process $proc$libresoc.v:168260$10912 + attribute \src "libresoc.v:176928.13-176928.30" + process $proc$libresoc.v:176928$10969 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:168266.13-168266.25" - process $proc$libresoc.v:168266$10913 + attribute \src "libresoc.v:176934.13-176934.25" + process $proc$libresoc.v:176934$10970 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:168271.13-168271.33" - process $proc$libresoc.v:168271$10914 + attribute \src "libresoc.v:176939.13-176939.33" + process $proc$libresoc.v:176939$10971 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:168278.13-168278.33" - process $proc$libresoc.v:168278$10915 + attribute \src "libresoc.v:176946.13-176946.33" + process $proc$libresoc.v:176946$10972 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:168285.13-168285.33" - process $proc$libresoc.v:168285$10916 + attribute \src "libresoc.v:176953.13-176953.33" + process $proc$libresoc.v:176953$10973 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:168306.3-168307.25" - process $proc$libresoc.v:168306$10841 + attribute \src "libresoc.v:176974.3-176975.25" + process $proc$libresoc.v:176974$10898 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:168308.3-168309.37" - process $proc$libresoc.v:168308$10842 + attribute \src "libresoc.v:176976.3-176977.37" + process $proc$libresoc.v:176976$10899 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:168310.3-168311.43" - process $proc$libresoc.v:168310$10843 + attribute \src "libresoc.v:176978.3-176979.43" + process $proc$libresoc.v:176978$10900 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:168312.3-168313.43" - process $proc$libresoc.v:168312$10844 + attribute \src "libresoc.v:176980.3-176981.43" + process $proc$libresoc.v:176980$10901 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:168314.3-168315.43" - process $proc$libresoc.v:168314$10845 + attribute \src "libresoc.v:176982.3-176983.43" + process $proc$libresoc.v:176982$10902 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:168316.3-168361.6" - process $proc$libresoc.v:168316$10846 + attribute \src "libresoc.v:176984.3-177029.6" + process $proc$libresoc.v:176984$10903 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$10847 $7\src11__data_o$next[1:0]$10854 - attribute \src "libresoc.v:168317.5-168317.29" + assign $0\src11__data_o$next[1:0]$10904 $7\src11__data_o$next[1:0]$10911 + attribute \src "libresoc.v:176985.5-176985.29" switch \initial - attribute \src "libresoc.v:168317.9-168317.17" + attribute \src "libresoc.v:176985.9-176985.17" case 1'1 case end @@ -349640,75 +364581,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$10848 $6\src11__data_o$next[1:0]$10853 + assign $1\src11__data_o$next[1:0]$10905 $6\src11__data_o$next[1:0]$10910 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$10849 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10906 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$10849 2'00 + assign $2\src11__data_o$next[1:0]$10906 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$10850 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10907 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$10850 $2\src11__data_o$next[1:0]$10849 + assign $3\src11__data_o$next[1:0]$10907 $2\src11__data_o$next[1:0]$10906 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$10851 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10908 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$10851 $3\src11__data_o$next[1:0]$10850 + assign $4\src11__data_o$next[1:0]$10908 $3\src11__data_o$next[1:0]$10907 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$10852 \w1__data_i + assign $5\src11__data_o$next[1:0]$10909 \w1__data_i case - assign $5\src11__data_o$next[1:0]$10852 $4\src11__data_o$next[1:0]$10851 + assign $5\src11__data_o$next[1:0]$10909 $4\src11__data_o$next[1:0]$10908 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$10853 \reg + assign $6\src11__data_o$next[1:0]$10910 \reg case - assign $6\src11__data_o$next[1:0]$10853 $5\src11__data_o$next[1:0]$10852 + assign $6\src11__data_o$next[1:0]$10910 $5\src11__data_o$next[1:0]$10909 end case - assign $1\src11__data_o$next[1:0]$10848 2'00 + assign $1\src11__data_o$next[1:0]$10905 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$10854 2'00 + assign $7\src11__data_o$next[1:0]$10911 2'00 case - assign $7\src11__data_o$next[1:0]$10854 $1\src11__data_o$next[1:0]$10848 + assign $7\src11__data_o$next[1:0]$10911 $1\src11__data_o$next[1:0]$10905 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10847 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10904 end - attribute \src "libresoc.v:168362.3-168397.6" - process $proc$libresoc.v:168362$10855 + attribute \src "libresoc.v:177030.3-177065.6" + process $proc$libresoc.v:177030$10912 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:168363.5-168363.29" + attribute \src "libresoc.v:177031.5-177031.29" switch \initial - attribute \src "libresoc.v:168363.9-168363.17" + attribute \src "libresoc.v:177031.9-177031.17" case 1'1 case end @@ -349764,15 +364705,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:168398.3-168443.6" - process $proc$libresoc.v:168398$10856 + attribute \src "libresoc.v:177066.3-177111.6" + process $proc$libresoc.v:177066$10913 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$10857 $7\src21__data_o$next[1:0]$10864 - attribute \src "libresoc.v:168399.5-168399.29" + assign $0\src21__data_o$next[1:0]$10914 $7\src21__data_o$next[1:0]$10921 + attribute \src "libresoc.v:177067.5-177067.29" switch \initial - attribute \src "libresoc.v:168399.9-168399.17" + attribute \src "libresoc.v:177067.9-177067.17" case 1'1 case end @@ -349785,75 +364726,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$10858 $6\src21__data_o$next[1:0]$10863 + assign $1\src21__data_o$next[1:0]$10915 $6\src21__data_o$next[1:0]$10920 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$10859 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10916 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$10859 2'00 + assign $2\src21__data_o$next[1:0]$10916 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$10860 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10917 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$10860 $2\src21__data_o$next[1:0]$10859 + assign $3\src21__data_o$next[1:0]$10917 $2\src21__data_o$next[1:0]$10916 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$10861 \dest31__data_i + assign $4\src21__data_o$next[1:0]$10918 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$10861 $3\src21__data_o$next[1:0]$10860 + assign $4\src21__data_o$next[1:0]$10918 $3\src21__data_o$next[1:0]$10917 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$10862 \w1__data_i + assign $5\src21__data_o$next[1:0]$10919 \w1__data_i case - assign $5\src21__data_o$next[1:0]$10862 $4\src21__data_o$next[1:0]$10861 + assign $5\src21__data_o$next[1:0]$10919 $4\src21__data_o$next[1:0]$10918 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$10863 \reg + assign $6\src21__data_o$next[1:0]$10920 \reg case - assign $6\src21__data_o$next[1:0]$10863 $5\src21__data_o$next[1:0]$10862 + assign $6\src21__data_o$next[1:0]$10920 $5\src21__data_o$next[1:0]$10919 end case - assign $1\src21__data_o$next[1:0]$10858 2'00 + assign $1\src21__data_o$next[1:0]$10915 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$10864 2'00 + assign $7\src21__data_o$next[1:0]$10921 2'00 case - assign $7\src21__data_o$next[1:0]$10864 $1\src21__data_o$next[1:0]$10858 + assign $7\src21__data_o$next[1:0]$10921 $1\src21__data_o$next[1:0]$10915 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10857 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10914 end - attribute \src "libresoc.v:168444.3-168479.6" - process $proc$libresoc.v:168444$10865 + attribute \src "libresoc.v:177112.3-177147.6" + process $proc$libresoc.v:177112$10922 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10866 $1\wr_detect$4[0:0]$10867 - attribute \src "libresoc.v:168445.5-168445.29" + assign $0\wr_detect$4[0:0]$10923 $1\wr_detect$4[0:0]$10924 + attribute \src "libresoc.v:177113.5-177113.29" switch \initial - attribute \src "libresoc.v:168445.9-168445.17" + attribute \src "libresoc.v:177113.9-177113.17" case 1'1 case end @@ -349866,58 +364807,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10867 $5\wr_detect$4[0:0]$10871 + assign $1\wr_detect$4[0:0]$10924 $5\wr_detect$4[0:0]$10928 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10868 1'1 + assign $2\wr_detect$4[0:0]$10925 1'1 case - assign $2\wr_detect$4[0:0]$10868 1'0 + assign $2\wr_detect$4[0:0]$10925 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10869 1'1 + assign $3\wr_detect$4[0:0]$10926 1'1 case - assign $3\wr_detect$4[0:0]$10869 $2\wr_detect$4[0:0]$10868 + assign $3\wr_detect$4[0:0]$10926 $2\wr_detect$4[0:0]$10925 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10870 1'1 + assign $4\wr_detect$4[0:0]$10927 1'1 case - assign $4\wr_detect$4[0:0]$10870 $3\wr_detect$4[0:0]$10869 + assign $4\wr_detect$4[0:0]$10927 $3\wr_detect$4[0:0]$10926 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10871 1'1 + assign $5\wr_detect$4[0:0]$10928 1'1 case - assign $5\wr_detect$4[0:0]$10871 $4\wr_detect$4[0:0]$10870 + assign $5\wr_detect$4[0:0]$10928 $4\wr_detect$4[0:0]$10927 end case - assign $1\wr_detect$4[0:0]$10867 1'0 + assign $1\wr_detect$4[0:0]$10924 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10866 + update \wr_detect$4 $0\wr_detect$4[0:0]$10923 end - attribute \src "libresoc.v:168480.3-168525.6" - process $proc$libresoc.v:168480$10872 + attribute \src "libresoc.v:177148.3-177193.6" + process $proc$libresoc.v:177148$10929 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$10873 $7\src31__data_o$next[1:0]$10880 - attribute \src "libresoc.v:168481.5-168481.29" + assign $0\src31__data_o$next[1:0]$10930 $7\src31__data_o$next[1:0]$10937 + attribute \src "libresoc.v:177149.5-177149.29" switch \initial - attribute \src "libresoc.v:168481.9-168481.17" + attribute \src "libresoc.v:177149.9-177149.17" case 1'1 case end @@ -349930,75 +364871,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$10874 $6\src31__data_o$next[1:0]$10879 + assign $1\src31__data_o$next[1:0]$10931 $6\src31__data_o$next[1:0]$10936 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$10875 \dest11__data_i + assign $2\src31__data_o$next[1:0]$10932 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$10875 2'00 + assign $2\src31__data_o$next[1:0]$10932 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$10876 \dest21__data_i + assign $3\src31__data_o$next[1:0]$10933 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$10876 $2\src31__data_o$next[1:0]$10875 + assign $3\src31__data_o$next[1:0]$10933 $2\src31__data_o$next[1:0]$10932 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$10877 \dest31__data_i + assign $4\src31__data_o$next[1:0]$10934 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$10877 $3\src31__data_o$next[1:0]$10876 + assign $4\src31__data_o$next[1:0]$10934 $3\src31__data_o$next[1:0]$10933 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$10878 \w1__data_i + assign $5\src31__data_o$next[1:0]$10935 \w1__data_i case - assign $5\src31__data_o$next[1:0]$10878 $4\src31__data_o$next[1:0]$10877 + assign $5\src31__data_o$next[1:0]$10935 $4\src31__data_o$next[1:0]$10934 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$10879 \reg + assign $6\src31__data_o$next[1:0]$10936 \reg case - assign $6\src31__data_o$next[1:0]$10879 $5\src31__data_o$next[1:0]$10878 + assign $6\src31__data_o$next[1:0]$10936 $5\src31__data_o$next[1:0]$10935 end case - assign $1\src31__data_o$next[1:0]$10874 2'00 + assign $1\src31__data_o$next[1:0]$10931 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$10880 2'00 + assign $7\src31__data_o$next[1:0]$10937 2'00 case - assign $7\src31__data_o$next[1:0]$10880 $1\src31__data_o$next[1:0]$10874 + assign $7\src31__data_o$next[1:0]$10937 $1\src31__data_o$next[1:0]$10931 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$10873 + update \src31__data_o$next $0\src31__data_o$next[1:0]$10930 end - attribute \src "libresoc.v:168526.3-168561.6" - process $proc$libresoc.v:168526$10881 + attribute \src "libresoc.v:177194.3-177229.6" + process $proc$libresoc.v:177194$10938 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10882 $1\wr_detect$7[0:0]$10883 - attribute \src "libresoc.v:168527.5-168527.29" + assign $0\wr_detect$7[0:0]$10939 $1\wr_detect$7[0:0]$10940 + attribute \src "libresoc.v:177195.5-177195.29" switch \initial - attribute \src "libresoc.v:168527.9-168527.17" + attribute \src "libresoc.v:177195.9-177195.17" case 1'1 case end @@ -350011,58 +364952,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10883 $5\wr_detect$7[0:0]$10887 + assign $1\wr_detect$7[0:0]$10940 $5\wr_detect$7[0:0]$10944 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10884 1'1 + assign $2\wr_detect$7[0:0]$10941 1'1 case - assign $2\wr_detect$7[0:0]$10884 1'0 + assign $2\wr_detect$7[0:0]$10941 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10885 1'1 + assign $3\wr_detect$7[0:0]$10942 1'1 case - assign $3\wr_detect$7[0:0]$10885 $2\wr_detect$7[0:0]$10884 + assign $3\wr_detect$7[0:0]$10942 $2\wr_detect$7[0:0]$10941 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10886 1'1 + assign $4\wr_detect$7[0:0]$10943 1'1 case - assign $4\wr_detect$7[0:0]$10886 $3\wr_detect$7[0:0]$10885 + assign $4\wr_detect$7[0:0]$10943 $3\wr_detect$7[0:0]$10942 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10887 1'1 + assign $5\wr_detect$7[0:0]$10944 1'1 case - assign $5\wr_detect$7[0:0]$10887 $4\wr_detect$7[0:0]$10886 + assign $5\wr_detect$7[0:0]$10944 $4\wr_detect$7[0:0]$10943 end case - assign $1\wr_detect$7[0:0]$10883 1'0 + assign $1\wr_detect$7[0:0]$10940 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10882 + update \wr_detect$7 $0\wr_detect$7[0:0]$10939 end - attribute \src "libresoc.v:168562.3-168607.6" - process $proc$libresoc.v:168562$10888 + attribute \src "libresoc.v:177230.3-177275.6" + process $proc$libresoc.v:177230$10945 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$10889 $7\r1__data_o$next[1:0]$10896 - attribute \src "libresoc.v:168563.5-168563.29" + assign $0\r1__data_o$next[1:0]$10946 $7\r1__data_o$next[1:0]$10953 + attribute \src "libresoc.v:177231.5-177231.29" switch \initial - attribute \src "libresoc.v:168563.9-168563.17" + attribute \src "libresoc.v:177231.9-177231.17" case 1'1 case end @@ -350075,75 +365016,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$10890 $6\r1__data_o$next[1:0]$10895 + assign $1\r1__data_o$next[1:0]$10947 $6\r1__data_o$next[1:0]$10952 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$10891 \dest11__data_i + assign $2\r1__data_o$next[1:0]$10948 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$10891 2'00 + assign $2\r1__data_o$next[1:0]$10948 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$10892 \dest21__data_i + assign $3\r1__data_o$next[1:0]$10949 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$10892 $2\r1__data_o$next[1:0]$10891 + assign $3\r1__data_o$next[1:0]$10949 $2\r1__data_o$next[1:0]$10948 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$10893 \dest31__data_i + assign $4\r1__data_o$next[1:0]$10950 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$10893 $3\r1__data_o$next[1:0]$10892 + assign $4\r1__data_o$next[1:0]$10950 $3\r1__data_o$next[1:0]$10949 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$10894 \w1__data_i + assign $5\r1__data_o$next[1:0]$10951 \w1__data_i case - assign $5\r1__data_o$next[1:0]$10894 $4\r1__data_o$next[1:0]$10893 + assign $5\r1__data_o$next[1:0]$10951 $4\r1__data_o$next[1:0]$10950 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$10895 \reg + assign $6\r1__data_o$next[1:0]$10952 \reg case - assign $6\r1__data_o$next[1:0]$10895 $5\r1__data_o$next[1:0]$10894 + assign $6\r1__data_o$next[1:0]$10952 $5\r1__data_o$next[1:0]$10951 end case - assign $1\r1__data_o$next[1:0]$10890 2'00 + assign $1\r1__data_o$next[1:0]$10947 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$10896 2'00 + assign $7\r1__data_o$next[1:0]$10953 2'00 case - assign $7\r1__data_o$next[1:0]$10896 $1\r1__data_o$next[1:0]$10890 + assign $7\r1__data_o$next[1:0]$10953 $1\r1__data_o$next[1:0]$10947 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$10889 + update \r1__data_o$next $0\r1__data_o$next[1:0]$10946 end - attribute \src "libresoc.v:168608.3-168643.6" - process $proc$libresoc.v:168608$10897 + attribute \src "libresoc.v:177276.3-177311.6" + process $proc$libresoc.v:177276$10954 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10898 $1\wr_detect$10[0:0]$10899 - attribute \src "libresoc.v:168609.5-168609.29" + assign $0\wr_detect$10[0:0]$10955 $1\wr_detect$10[0:0]$10956 + attribute \src "libresoc.v:177277.5-177277.29" switch \initial - attribute \src "libresoc.v:168609.9-168609.17" + attribute \src "libresoc.v:177277.9-177277.17" case 1'1 case end @@ -350156,61 +365097,61 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10899 $5\wr_detect$10[0:0]$10903 + assign $1\wr_detect$10[0:0]$10956 $5\wr_detect$10[0:0]$10960 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10900 1'1 + assign $2\wr_detect$10[0:0]$10957 1'1 case - assign $2\wr_detect$10[0:0]$10900 1'0 + assign $2\wr_detect$10[0:0]$10957 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10901 1'1 + assign $3\wr_detect$10[0:0]$10958 1'1 case - assign $3\wr_detect$10[0:0]$10901 $2\wr_detect$10[0:0]$10900 + assign $3\wr_detect$10[0:0]$10958 $2\wr_detect$10[0:0]$10957 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10902 1'1 + assign $4\wr_detect$10[0:0]$10959 1'1 case - assign $4\wr_detect$10[0:0]$10902 $3\wr_detect$10[0:0]$10901 + assign $4\wr_detect$10[0:0]$10959 $3\wr_detect$10[0:0]$10958 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10903 1'1 + assign $5\wr_detect$10[0:0]$10960 1'1 case - assign $5\wr_detect$10[0:0]$10903 $4\wr_detect$10[0:0]$10902 + assign $5\wr_detect$10[0:0]$10960 $4\wr_detect$10[0:0]$10959 end case - assign $1\wr_detect$10[0:0]$10899 1'0 + assign $1\wr_detect$10[0:0]$10956 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10898 + update \wr_detect$10 $0\wr_detect$10[0:0]$10955 end - attribute \src "libresoc.v:168644.3-168676.6" - process $proc$libresoc.v:168644$10904 + attribute \src "libresoc.v:177312.3-177344.6" + process $proc$libresoc.v:177312$10961 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10905 $5\reg$next[1:0]$10910 - attribute \src "libresoc.v:168645.5-168645.29" + assign $0\reg$next[1:0]$10962 $5\reg$next[1:0]$10967 + attribute \src "libresoc.v:177313.5-177313.29" switch \initial - attribute \src "libresoc.v:168645.9-168645.17" + attribute \src "libresoc.v:177313.9-177313.17" case 1'1 case end @@ -350219,255 +365160,336 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10906 \dest11__data_i + assign $1\reg$next[1:0]$10963 \dest11__data_i case - assign $1\reg$next[1:0]$10906 \reg + assign $1\reg$next[1:0]$10963 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10907 \dest21__data_i + assign $2\reg$next[1:0]$10964 \dest21__data_i case - assign $2\reg$next[1:0]$10907 $1\reg$next[1:0]$10906 + assign $2\reg$next[1:0]$10964 $1\reg$next[1:0]$10963 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10908 \dest31__data_i + assign $3\reg$next[1:0]$10965 \dest31__data_i case - assign $3\reg$next[1:0]$10908 $2\reg$next[1:0]$10907 + assign $3\reg$next[1:0]$10965 $2\reg$next[1:0]$10964 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10909 \w1__data_i + assign $4\reg$next[1:0]$10966 \w1__data_i case - assign $4\reg$next[1:0]$10909 $3\reg$next[1:0]$10908 + assign $4\reg$next[1:0]$10966 $3\reg$next[1:0]$10965 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10910 2'00 + assign $5\reg$next[1:0]$10967 2'00 case - assign $5\reg$next[1:0]$10910 $4\reg$next[1:0]$10909 + assign $5\reg$next[1:0]$10967 $4\reg$next[1:0]$10966 end sync always - update \reg$next $0\reg$next[1:0]$10905 + update \reg$next $0\reg$next[1:0]$10962 end - connect \$9 $not$libresoc.v:168302$10837_Y - connect \$1 $not$libresoc.v:168303$10838_Y - connect \$3 $not$libresoc.v:168304$10839_Y - connect \$6 $not$libresoc.v:168305$10840_Y + connect \$9 $not$libresoc.v:176970$10894_Y + connect \$1 $not$libresoc.v:176971$10895_Y + connect \$3 $not$libresoc.v:176972$10896_Y + connect \$6 $not$libresoc.v:176973$10897_Y end -attribute \src "libresoc.v:168681.1-168900.10" +attribute \src "libresoc.v:177349.1-177698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:168733.3-168772.6" - wire width 64 $0\cia1__data_o$next[63:0]$10923 - attribute \src "libresoc.v:168731.3-168732.41" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $0\cia1__data_o$next[63:0]$10982 + attribute \src "libresoc.v:177417.3-177418.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:168682.7-168682.20" + attribute \src "libresoc.v:177350.7-177350.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168803.3-168842.6" - wire width 64 $0\msr1__data_o$next[63:0]$10932 - attribute \src "libresoc.v:168729.3-168730.41" + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $0\msr1__data_o$next[63:0]$10992 + attribute \src "libresoc.v:177415.3-177416.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:168873.3-168899.6" - wire width 64 $0\reg$next[63:0]$10946 - attribute \src "libresoc.v:168727.3-168728.25" + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $0\reg$next[63:0]$11024 + attribute \src "libresoc.v:177411.3-177412.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:168843.3-168872.6" - wire $0\wr_detect$4[0:0]$10940 - attribute \src "libresoc.v:168773.3-168802.6" + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $0\sv1__data_o$next[63:0]$11008 + attribute \src "libresoc.v:177413.3-177414.39" + wire width 64 $0\sv1__data_o[63:0] + attribute \src "libresoc.v:177547.3-177582.6" + wire $0\wr_detect$4[0:0]$11001 + attribute \src "libresoc.v:177629.3-177664.6" + wire $0\wr_detect$7[0:0]$11017 + attribute \src "libresoc.v:177465.3-177500.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:168733.3-168772.6" - wire width 64 $1\cia1__data_o$next[63:0]$10924 - attribute \src "libresoc.v:168689.14-168689.49" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $1\cia1__data_o$next[63:0]$10983 + attribute \src "libresoc.v:177359.14-177359.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:168803.3-168842.6" - wire width 64 $1\msr1__data_o$next[63:0]$10933 - attribute \src "libresoc.v:168706.14-168706.49" + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $1\msr1__data_o$next[63:0]$10993 + attribute \src "libresoc.v:177376.14-177376.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:168873.3-168899.6" - wire width 64 $1\reg$next[63:0]$10947 - attribute \src "libresoc.v:168718.14-168718.42" + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $1\reg$next[63:0]$11025 + attribute \src "libresoc.v:177388.14-177388.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:168843.3-168872.6" - wire $1\wr_detect$4[0:0]$10941 - attribute \src "libresoc.v:168773.3-168802.6" + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $1\sv1__data_o$next[63:0]$11009 + attribute \src "libresoc.v:177395.14-177395.48" + wire width 64 $1\sv1__data_o[63:0] + attribute \src "libresoc.v:177547.3-177582.6" + wire $1\wr_detect$4[0:0]$11002 + attribute \src "libresoc.v:177629.3-177664.6" + wire $1\wr_detect$7[0:0]$11018 + attribute \src "libresoc.v:177465.3-177500.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:168733.3-168772.6" - wire width 64 $2\cia1__data_o$next[63:0]$10925 - attribute \src "libresoc.v:168803.3-168842.6" - wire width 64 $2\msr1__data_o$next[63:0]$10934 - attribute \src "libresoc.v:168873.3-168899.6" - wire width 64 $2\reg$next[63:0]$10948 - attribute \src "libresoc.v:168843.3-168872.6" - wire $2\wr_detect$4[0:0]$10942 - attribute \src "libresoc.v:168773.3-168802.6" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $2\cia1__data_o$next[63:0]$10984 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $2\msr1__data_o$next[63:0]$10994 + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $2\reg$next[63:0]$11026 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $2\sv1__data_o$next[63:0]$11010 + attribute \src "libresoc.v:177547.3-177582.6" + wire $2\wr_detect$4[0:0]$11003 + attribute \src "libresoc.v:177629.3-177664.6" + wire $2\wr_detect$7[0:0]$11019 + attribute \src "libresoc.v:177465.3-177500.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:168733.3-168772.6" - wire width 64 $3\cia1__data_o$next[63:0]$10926 - attribute \src "libresoc.v:168803.3-168842.6" - wire width 64 $3\msr1__data_o$next[63:0]$10935 - attribute \src "libresoc.v:168873.3-168899.6" - wire width 64 $3\reg$next[63:0]$10949 - attribute \src "libresoc.v:168843.3-168872.6" - wire $3\wr_detect$4[0:0]$10943 - attribute \src "libresoc.v:168773.3-168802.6" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $3\cia1__data_o$next[63:0]$10985 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $3\msr1__data_o$next[63:0]$10995 + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $3\reg$next[63:0]$11027 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $3\sv1__data_o$next[63:0]$11011 + attribute \src "libresoc.v:177547.3-177582.6" + wire $3\wr_detect$4[0:0]$11004 + attribute \src "libresoc.v:177629.3-177664.6" + wire $3\wr_detect$7[0:0]$11020 + attribute \src "libresoc.v:177465.3-177500.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:168733.3-168772.6" - wire width 64 $4\cia1__data_o$next[63:0]$10927 - attribute \src "libresoc.v:168803.3-168842.6" - wire width 64 $4\msr1__data_o$next[63:0]$10936 - attribute \src "libresoc.v:168873.3-168899.6" - wire width 64 $4\reg$next[63:0]$10950 - attribute \src "libresoc.v:168843.3-168872.6" - wire $4\wr_detect$4[0:0]$10944 - attribute \src "libresoc.v:168773.3-168802.6" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $4\cia1__data_o$next[63:0]$10986 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $4\msr1__data_o$next[63:0]$10996 + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $4\reg$next[63:0]$11028 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $4\sv1__data_o$next[63:0]$11012 + attribute \src "libresoc.v:177547.3-177582.6" + wire $4\wr_detect$4[0:0]$11005 + attribute \src "libresoc.v:177629.3-177664.6" + wire $4\wr_detect$7[0:0]$11021 + attribute \src "libresoc.v:177465.3-177500.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:168733.3-168772.6" - wire width 64 $5\cia1__data_o$next[63:0]$10928 - attribute \src "libresoc.v:168803.3-168842.6" - wire width 64 $5\msr1__data_o$next[63:0]$10937 - attribute \src "libresoc.v:168733.3-168772.6" - wire width 64 $6\cia1__data_o$next[63:0]$10929 - attribute \src "libresoc.v:168803.3-168842.6" - wire width 64 $6\msr1__data_o$next[63:0]$10938 - attribute \src "libresoc.v:168725.17-168725.100" - wire $not$libresoc.v:168725$10917_Y - attribute \src "libresoc.v:168726.17-168726.103" - wire $not$libresoc.v:168726$10918_Y + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $5\cia1__data_o$next[63:0]$10987 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $5\msr1__data_o$next[63:0]$10997 + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $5\reg$next[63:0]$11029 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $5\sv1__data_o$next[63:0]$11013 + attribute \src "libresoc.v:177547.3-177582.6" + wire $5\wr_detect$4[0:0]$11006 + attribute \src "libresoc.v:177629.3-177664.6" + wire $5\wr_detect$7[0:0]$11022 + attribute \src "libresoc.v:177465.3-177500.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $6\cia1__data_o$next[63:0]$10988 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $6\msr1__data_o$next[63:0]$10998 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $6\sv1__data_o$next[63:0]$11014 + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $7\cia1__data_o$next[63:0]$10989 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $7\msr1__data_o$next[63:0]$10999 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $7\sv1__data_o$next[63:0]$11015 + attribute \src "libresoc.v:177408.17-177408.100" + wire $not$libresoc.v:177408$10974_Y + attribute \src "libresoc.v:177409.17-177409.103" + wire $not$libresoc.v:177409$10975_Y + attribute \src "libresoc.v:177410.17-177410.103" + wire $not$libresoc.v:177410$10976_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 3 \cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \cia1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr11__wen - attribute \src "libresoc.v:168682.7-168682.15" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr11__wen + attribute \src "libresoc.v:177350.7-177350.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 5 \msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \msr1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168725$10917 + cell $not $not$libresoc.v:177408$10974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:168725$10917_Y + connect \Y $not$libresoc.v:177408$10974_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168726$10918 + cell $not $not$libresoc.v:177409$10975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:168726$10918_Y + connect \Y $not$libresoc.v:177409$10975_Y end - attribute \src "libresoc.v:168682.7-168682.20" - process $proc$libresoc.v:168682$10951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:177410$10976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:177410$10976_Y + end + attribute \src "libresoc.v:177350.7-177350.20" + process $proc$libresoc.v:177350$11030 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168689.14-168689.49" - process $proc$libresoc.v:168689$10952 + attribute \src "libresoc.v:177359.14-177359.49" + process $proc$libresoc.v:177359$11031 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:168706.14-168706.49" - process $proc$libresoc.v:168706$10953 + attribute \src "libresoc.v:177376.14-177376.49" + process $proc$libresoc.v:177376$11032 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:168718.14-168718.42" - process $proc$libresoc.v:168718$10954 + attribute \src "libresoc.v:177388.14-177388.42" + process $proc$libresoc.v:177388$11033 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:168727.3-168728.25" - process $proc$libresoc.v:168727$10919 + attribute \src "libresoc.v:177395.14-177395.48" + process $proc$libresoc.v:177395$11034 + assign { } { } + assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv1__data_o $1\sv1__data_o[63:0] + end + attribute \src "libresoc.v:177411.3-177412.25" + process $proc$libresoc.v:177411$10977 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:168729.3-168730.41" - process $proc$libresoc.v:168729$10920 + attribute \src "libresoc.v:177413.3-177414.39" + process $proc$libresoc.v:177413$10978 + assign { } { } + assign $0\sv1__data_o[63:0] \sv1__data_o$next + sync posedge \coresync_clk + update \sv1__data_o $0\sv1__data_o[63:0] + end + attribute \src "libresoc.v:177415.3-177416.41" + process $proc$libresoc.v:177415$10979 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:168731.3-168732.41" - process $proc$libresoc.v:168731$10921 + attribute \src "libresoc.v:177417.3-177418.41" + process $proc$libresoc.v:177417$10980 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:168733.3-168772.6" - process $proc$libresoc.v:168733$10922 + attribute \src "libresoc.v:177419.3-177464.6" + process $proc$libresoc.v:177419$10981 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$10923 $6\cia1__data_o$next[63:0]$10929 - attribute \src "libresoc.v:168734.5-168734.29" + assign $0\cia1__data_o$next[63:0]$10982 $7\cia1__data_o$next[63:0]$10989 + attribute \src "libresoc.v:177420.5-177420.29" switch \initial - attribute \src "libresoc.v:168734.9-168734.17" + attribute \src "libresoc.v:177420.9-177420.17" case 1'1 case end @@ -350479,66 +365501,76 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$10924 $5\cia1__data_o$next[63:0]$10928 + assign { } { } + assign $1\cia1__data_o$next[63:0]$10983 $6\cia1__data_o$next[63:0]$10988 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$10925 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$10984 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$10925 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$10984 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$10926 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$10985 \msr1__data_i + case + assign $3\cia1__data_o$next[63:0]$10985 $2\cia1__data_o$next[63:0]$10984 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia1__data_o$next[63:0]$10986 \sv1__data_i case - assign $3\cia1__data_o$next[63:0]$10926 $2\cia1__data_o$next[63:0]$10925 + assign $4\cia1__data_o$next[63:0]$10986 $3\cia1__data_o$next[63:0]$10985 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$10927 \d_wr11__data_i + assign $5\cia1__data_o$next[63:0]$10987 \d_wr11__data_i case - assign $4\cia1__data_o$next[63:0]$10927 $3\cia1__data_o$next[63:0]$10926 + assign $5\cia1__data_o$next[63:0]$10987 $4\cia1__data_o$next[63:0]$10986 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$10928 \reg + assign $6\cia1__data_o$next[63:0]$10988 \reg case - assign $5\cia1__data_o$next[63:0]$10928 $4\cia1__data_o$next[63:0]$10927 + assign $6\cia1__data_o$next[63:0]$10988 $5\cia1__data_o$next[63:0]$10987 end case - assign $1\cia1__data_o$next[63:0]$10924 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$10983 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$10929 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\cia1__data_o$next[63:0]$10929 $1\cia1__data_o$next[63:0]$10924 + assign $7\cia1__data_o$next[63:0]$10989 $1\cia1__data_o$next[63:0]$10983 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10923 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10982 end - attribute \src "libresoc.v:168773.3-168802.6" - process $proc$libresoc.v:168773$10930 + attribute \src "libresoc.v:177465.3-177500.6" + process $proc$libresoc.v:177465$10990 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:168774.5-168774.29" + attribute \src "libresoc.v:177466.5-177466.29" switch \initial - attribute \src "libresoc.v:168774.9-168774.17" + attribute \src "libresoc.v:177466.9-177466.17" case 1'1 case end @@ -350550,7 +365582,8 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" @@ -350570,7 +365603,7 @@ module \reg_1$136 assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen + switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -350578,21 +365611,30 @@ module \reg_1$136 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:168803.3-168842.6" - process $proc$libresoc.v:168803$10931 + attribute \src "libresoc.v:177501.3-177546.6" + process $proc$libresoc.v:177501$10991 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$10932 $6\msr1__data_o$next[63:0]$10938 - attribute \src "libresoc.v:168804.5-168804.29" + assign $0\msr1__data_o$next[63:0]$10992 $7\msr1__data_o$next[63:0]$10999 + attribute \src "libresoc.v:177502.5-177502.29" switch \initial - attribute \src "libresoc.v:168804.9-168804.17" + attribute \src "libresoc.v:177502.9-177502.17" case 1'1 case end @@ -350604,66 +365646,76 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$10933 $5\msr1__data_o$next[63:0]$10937 + assign { } { } + assign $1\msr1__data_o$next[63:0]$10993 $6\msr1__data_o$next[63:0]$10998 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$10934 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$10994 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$10934 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$10994 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$10935 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$10995 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$10935 $2\msr1__data_o$next[63:0]$10934 + assign $3\msr1__data_o$next[63:0]$10995 $2\msr1__data_o$next[63:0]$10994 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr1__data_o$next[63:0]$10996 \sv1__data_i + case + assign $4\msr1__data_o$next[63:0]$10996 $3\msr1__data_o$next[63:0]$10995 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$10936 \d_wr11__data_i + assign $5\msr1__data_o$next[63:0]$10997 \d_wr11__data_i case - assign $4\msr1__data_o$next[63:0]$10936 $3\msr1__data_o$next[63:0]$10935 + assign $5\msr1__data_o$next[63:0]$10997 $4\msr1__data_o$next[63:0]$10996 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$10937 \reg + assign $6\msr1__data_o$next[63:0]$10998 \reg case - assign $5\msr1__data_o$next[63:0]$10937 $4\msr1__data_o$next[63:0]$10936 + assign $6\msr1__data_o$next[63:0]$10998 $5\msr1__data_o$next[63:0]$10997 end case - assign $1\msr1__data_o$next[63:0]$10933 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$10993 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$10938 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr1__data_o$next[63:0]$10999 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\msr1__data_o$next[63:0]$10938 $1\msr1__data_o$next[63:0]$10933 + assign $7\msr1__data_o$next[63:0]$10999 $1\msr1__data_o$next[63:0]$10993 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10932 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10992 end - attribute \src "libresoc.v:168843.3-168872.6" - process $proc$libresoc.v:168843$10939 + attribute \src "libresoc.v:177547.3-177582.6" + process $proc$libresoc.v:177547$11000 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10940 $1\wr_detect$4[0:0]$10941 - attribute \src "libresoc.v:168844.5-168844.29" + assign $0\wr_detect$4[0:0]$11001 $1\wr_detect$4[0:0]$11002 + attribute \src "libresoc.v:177548.5-177548.29" switch \initial - attribute \src "libresoc.v:168844.9-168844.17" + attribute \src "libresoc.v:177548.9-177548.17" case 1'1 case end @@ -350675,51 +365727,207 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10941 $4\wr_detect$4[0:0]$10944 + assign { } { } + assign $1\wr_detect$4[0:0]$11002 $5\wr_detect$4[0:0]$11006 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10942 1'1 + assign $2\wr_detect$4[0:0]$11003 1'1 case - assign $2\wr_detect$4[0:0]$10942 1'0 + assign $2\wr_detect$4[0:0]$11003 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10943 1'1 + assign $3\wr_detect$4[0:0]$11004 1'1 + case + assign $3\wr_detect$4[0:0]$11004 $2\wr_detect$4[0:0]$11003 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11005 1'1 case - assign $3\wr_detect$4[0:0]$10943 $2\wr_detect$4[0:0]$10942 + assign $4\wr_detect$4[0:0]$11005 $3\wr_detect$4[0:0]$11004 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10944 1'1 + assign $5\wr_detect$4[0:0]$11006 1'1 case - assign $4\wr_detect$4[0:0]$10944 $3\wr_detect$4[0:0]$10943 + assign $5\wr_detect$4[0:0]$11006 $4\wr_detect$4[0:0]$11005 end case - assign $1\wr_detect$4[0:0]$10941 1'0 + assign $1\wr_detect$4[0:0]$11002 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10940 + update \wr_detect$4 $0\wr_detect$4[0:0]$11001 end - attribute \src "libresoc.v:168873.3-168899.6" - process $proc$libresoc.v:168873$10945 + attribute \src "libresoc.v:177583.3-177628.6" + process $proc$libresoc.v:177583$11007 assign { } { } assign { } { } assign { } { } + assign $0\sv1__data_o$next[63:0]$11008 $7\sv1__data_o$next[63:0]$11015 + attribute \src "libresoc.v:177584.5-177584.29" + switch \initial + attribute \src "libresoc.v:177584.9-177584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\sv1__data_o$next[63:0]$11009 $6\sv1__data_o$next[63:0]$11014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv1__data_o$next[63:0]$11010 \nia1__data_i + case + assign $2\sv1__data_o$next[63:0]$11010 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv1__data_o$next[63:0]$11011 \msr1__data_i + case + assign $3\sv1__data_o$next[63:0]$11011 $2\sv1__data_o$next[63:0]$11010 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv1__data_o$next[63:0]$11012 \sv1__data_i + case + assign $4\sv1__data_o$next[63:0]$11012 $3\sv1__data_o$next[63:0]$11011 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv1__data_o$next[63:0]$11013 \d_wr11__data_i + case + assign $5\sv1__data_o$next[63:0]$11013 $4\sv1__data_o$next[63:0]$11012 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv1__data_o$next[63:0]$11014 \reg + case + assign $6\sv1__data_o$next[63:0]$11014 $5\sv1__data_o$next[63:0]$11013 + end + case + assign $1\sv1__data_o$next[63:0]$11009 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv1__data_o$next[63:0]$11015 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\sv1__data_o$next[63:0]$11015 $1\sv1__data_o$next[63:0]$11009 + end + sync always + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11008 + end + attribute \src "libresoc.v:177629.3-177664.6" + process $proc$libresoc.v:177629$11016 assign { } { } assign { } { } - assign $0\reg$next[63:0]$10946 $4\reg$next[63:0]$10950 - attribute \src "libresoc.v:168874.5-168874.29" + assign $0\wr_detect$7[0:0]$11017 $1\wr_detect$7[0:0]$11018 + attribute \src "libresoc.v:177630.5-177630.29" switch \initial - attribute \src "libresoc.v:168874.9-168874.17" + attribute \src "libresoc.v:177630.9-177630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11018 $5\wr_detect$7[0:0]$11022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11019 1'1 + case + assign $2\wr_detect$7[0:0]$11019 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11020 1'1 + case + assign $3\wr_detect$7[0:0]$11020 $2\wr_detect$7[0:0]$11019 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11021 1'1 + case + assign $4\wr_detect$7[0:0]$11021 $3\wr_detect$7[0:0]$11020 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11022 1'1 + case + assign $5\wr_detect$7[0:0]$11022 $4\wr_detect$7[0:0]$11021 + end + case + assign $1\wr_detect$7[0:0]$11018 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11017 + end + attribute \src "libresoc.v:177665.3-177697.6" + process $proc$libresoc.v:177665$11023 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$11024 $5\reg$next[63:0]$11029 + attribute \src "libresoc.v:177666.5-177666.29" + switch \initial + attribute \src "libresoc.v:177666.9-177666.17" case 1'1 case end @@ -350728,214 +365936,224 @@ module \reg_1$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10947 \nia1__data_i + assign $1\reg$next[63:0]$11025 \nia1__data_i case - assign $1\reg$next[63:0]$10947 \reg + assign $1\reg$next[63:0]$11025 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10948 \msr1__data_i + assign $2\reg$next[63:0]$11026 \msr1__data_i + case + assign $2\reg$next[63:0]$11026 $1\reg$next[63:0]$11025 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11027 \sv1__data_i case - assign $2\reg$next[63:0]$10948 $1\reg$next[63:0]$10947 + assign $3\reg$next[63:0]$11027 $2\reg$next[63:0]$11026 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10949 \d_wr11__data_i + assign $4\reg$next[63:0]$11028 \d_wr11__data_i case - assign $3\reg$next[63:0]$10949 $2\reg$next[63:0]$10948 + assign $4\reg$next[63:0]$11028 $3\reg$next[63:0]$11027 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10950 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11029 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\reg$next[63:0]$10950 $3\reg$next[63:0]$10949 + assign $5\reg$next[63:0]$11029 $4\reg$next[63:0]$11028 end sync always - update \reg$next $0\reg$next[63:0]$10946 + update \reg$next $0\reg$next[63:0]$11024 end - connect \$1 $not$libresoc.v:168725$10917_Y - connect \$3 $not$libresoc.v:168726$10918_Y + connect \$1 $not$libresoc.v:177408$10974_Y + connect \$3 $not$libresoc.v:177409$10975_Y + connect \$6 $not$libresoc.v:177410$10976_Y end -attribute \src "libresoc.v:168904.1-169375.10" +attribute \src "libresoc.v:177702.1-178173.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:168905.7-168905.20" + attribute \src "libresoc.v:177703.7-177703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169305.3-169344.6" - wire width 4 $0\r22__data_o$next[3:0]$11024 - attribute \src "libresoc.v:168988.3-168989.39" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $0\r22__data_o$next[3:0]$11104 + attribute \src "libresoc.v:177786.3-177787.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:169235.3-169274.6" - wire width 4 $0\r2__data_o$next[3:0]$11010 - attribute \src "libresoc.v:168990.3-168991.37" + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $0\r2__data_o$next[3:0]$11090 + attribute \src "libresoc.v:177788.3-177789.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:169068.3-169094.6" - wire width 4 $0\reg$next[3:0]$10976 - attribute \src "libresoc.v:168986.3-168987.25" + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $0\reg$next[3:0]$11056 + attribute \src "libresoc.v:177784.3-177785.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:168998.3-169037.6" - wire width 4 $0\src12__data_o$next[3:0]$10967 - attribute \src "libresoc.v:168996.3-168997.43" + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $0\src12__data_o$next[3:0]$11047 + attribute \src "libresoc.v:177794.3-177795.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:169095.3-169134.6" - wire width 4 $0\src22__data_o$next[3:0]$10982 - attribute \src "libresoc.v:168994.3-168995.43" + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $0\src22__data_o$next[3:0]$11062 + attribute \src "libresoc.v:177792.3-177793.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:169165.3-169204.6" - wire width 4 $0\src32__data_o$next[3:0]$10996 - attribute \src "libresoc.v:168992.3-168993.43" + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $0\src32__data_o$next[3:0]$11076 + attribute \src "libresoc.v:177790.3-177791.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:169275.3-169304.6" - wire $0\wr_detect$10[0:0]$11018 - attribute \src "libresoc.v:169345.3-169374.6" - wire $0\wr_detect$13[0:0]$11032 - attribute \src "libresoc.v:169135.3-169164.6" - wire $0\wr_detect$4[0:0]$10990 - attribute \src "libresoc.v:169205.3-169234.6" - wire $0\wr_detect$7[0:0]$11004 - attribute \src "libresoc.v:169038.3-169067.6" + attribute \src "libresoc.v:178073.3-178102.6" + wire $0\wr_detect$10[0:0]$11098 + attribute \src "libresoc.v:178143.3-178172.6" + wire $0\wr_detect$13[0:0]$11112 + attribute \src "libresoc.v:177933.3-177962.6" + wire $0\wr_detect$4[0:0]$11070 + attribute \src "libresoc.v:178003.3-178032.6" + wire $0\wr_detect$7[0:0]$11084 + attribute \src "libresoc.v:177836.3-177865.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:169305.3-169344.6" - wire width 4 $1\r22__data_o$next[3:0]$11025 - attribute \src "libresoc.v:168930.13-168930.31" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $1\r22__data_o$next[3:0]$11105 + attribute \src "libresoc.v:177728.13-177728.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:169235.3-169274.6" - wire width 4 $1\r2__data_o$next[3:0]$11011 - attribute \src "libresoc.v:168937.13-168937.30" + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $1\r2__data_o$next[3:0]$11091 + attribute \src "libresoc.v:177735.13-177735.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:169068.3-169094.6" - wire width 4 $1\reg$next[3:0]$10977 - attribute \src "libresoc.v:168943.13-168943.25" + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $1\reg$next[3:0]$11057 + attribute \src "libresoc.v:177741.13-177741.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:168998.3-169037.6" - wire width 4 $1\src12__data_o$next[3:0]$10968 - attribute \src "libresoc.v:168948.13-168948.33" + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $1\src12__data_o$next[3:0]$11048 + attribute \src "libresoc.v:177746.13-177746.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:169095.3-169134.6" - wire width 4 $1\src22__data_o$next[3:0]$10983 - attribute \src "libresoc.v:168955.13-168955.33" + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $1\src22__data_o$next[3:0]$11063 + attribute \src "libresoc.v:177753.13-177753.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:169165.3-169204.6" - wire width 4 $1\src32__data_o$next[3:0]$10997 - attribute \src "libresoc.v:168962.13-168962.33" + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $1\src32__data_o$next[3:0]$11077 + attribute \src "libresoc.v:177760.13-177760.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:169275.3-169304.6" - wire $1\wr_detect$10[0:0]$11019 - attribute \src "libresoc.v:169345.3-169374.6" - wire $1\wr_detect$13[0:0]$11033 - attribute \src "libresoc.v:169135.3-169164.6" - wire $1\wr_detect$4[0:0]$10991 - attribute \src "libresoc.v:169205.3-169234.6" - wire $1\wr_detect$7[0:0]$11005 - attribute \src "libresoc.v:169038.3-169067.6" + attribute \src "libresoc.v:178073.3-178102.6" + wire $1\wr_detect$10[0:0]$11099 + attribute \src "libresoc.v:178143.3-178172.6" + wire $1\wr_detect$13[0:0]$11113 + attribute \src "libresoc.v:177933.3-177962.6" + wire $1\wr_detect$4[0:0]$11071 + attribute \src "libresoc.v:178003.3-178032.6" + wire $1\wr_detect$7[0:0]$11085 + attribute \src "libresoc.v:177836.3-177865.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:169305.3-169344.6" - wire width 4 $2\r22__data_o$next[3:0]$11026 - attribute \src "libresoc.v:169235.3-169274.6" - wire width 4 $2\r2__data_o$next[3:0]$11012 - attribute \src "libresoc.v:169068.3-169094.6" - wire width 4 $2\reg$next[3:0]$10978 - attribute \src "libresoc.v:168998.3-169037.6" - wire width 4 $2\src12__data_o$next[3:0]$10969 - attribute \src "libresoc.v:169095.3-169134.6" - wire width 4 $2\src22__data_o$next[3:0]$10984 - attribute \src "libresoc.v:169165.3-169204.6" - wire width 4 $2\src32__data_o$next[3:0]$10998 - attribute \src "libresoc.v:169275.3-169304.6" - wire $2\wr_detect$10[0:0]$11020 - attribute \src "libresoc.v:169345.3-169374.6" - wire $2\wr_detect$13[0:0]$11034 - attribute \src "libresoc.v:169135.3-169164.6" - wire $2\wr_detect$4[0:0]$10992 - attribute \src "libresoc.v:169205.3-169234.6" - wire $2\wr_detect$7[0:0]$11006 - attribute \src "libresoc.v:169038.3-169067.6" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $2\r22__data_o$next[3:0]$11106 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $2\r2__data_o$next[3:0]$11092 + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $2\reg$next[3:0]$11058 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $2\src12__data_o$next[3:0]$11049 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $2\src22__data_o$next[3:0]$11064 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $2\src32__data_o$next[3:0]$11078 + attribute \src "libresoc.v:178073.3-178102.6" + wire $2\wr_detect$10[0:0]$11100 + attribute \src "libresoc.v:178143.3-178172.6" + wire $2\wr_detect$13[0:0]$11114 + attribute \src "libresoc.v:177933.3-177962.6" + wire $2\wr_detect$4[0:0]$11072 + attribute \src "libresoc.v:178003.3-178032.6" + wire $2\wr_detect$7[0:0]$11086 + attribute \src "libresoc.v:177836.3-177865.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:169305.3-169344.6" - wire width 4 $3\r22__data_o$next[3:0]$11027 - attribute \src "libresoc.v:169235.3-169274.6" - wire width 4 $3\r2__data_o$next[3:0]$11013 - attribute \src "libresoc.v:169068.3-169094.6" - wire width 4 $3\reg$next[3:0]$10979 - attribute \src "libresoc.v:168998.3-169037.6" - wire width 4 $3\src12__data_o$next[3:0]$10970 - attribute \src "libresoc.v:169095.3-169134.6" - wire width 4 $3\src22__data_o$next[3:0]$10985 - attribute \src "libresoc.v:169165.3-169204.6" - wire width 4 $3\src32__data_o$next[3:0]$10999 - attribute \src "libresoc.v:169275.3-169304.6" - wire $3\wr_detect$10[0:0]$11021 - attribute \src "libresoc.v:169345.3-169374.6" - wire $3\wr_detect$13[0:0]$11035 - attribute \src "libresoc.v:169135.3-169164.6" - wire $3\wr_detect$4[0:0]$10993 - attribute \src "libresoc.v:169205.3-169234.6" - wire $3\wr_detect$7[0:0]$11007 - attribute \src "libresoc.v:169038.3-169067.6" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $3\r22__data_o$next[3:0]$11107 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $3\r2__data_o$next[3:0]$11093 + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $3\reg$next[3:0]$11059 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $3\src12__data_o$next[3:0]$11050 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $3\src22__data_o$next[3:0]$11065 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $3\src32__data_o$next[3:0]$11079 + attribute \src "libresoc.v:178073.3-178102.6" + wire $3\wr_detect$10[0:0]$11101 + attribute \src "libresoc.v:178143.3-178172.6" + wire $3\wr_detect$13[0:0]$11115 + attribute \src "libresoc.v:177933.3-177962.6" + wire $3\wr_detect$4[0:0]$11073 + attribute \src "libresoc.v:178003.3-178032.6" + wire $3\wr_detect$7[0:0]$11087 + attribute \src "libresoc.v:177836.3-177865.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:169305.3-169344.6" - wire width 4 $4\r22__data_o$next[3:0]$11028 - attribute \src "libresoc.v:169235.3-169274.6" - wire width 4 $4\r2__data_o$next[3:0]$11014 - attribute \src "libresoc.v:169068.3-169094.6" - wire width 4 $4\reg$next[3:0]$10980 - attribute \src "libresoc.v:168998.3-169037.6" - wire width 4 $4\src12__data_o$next[3:0]$10971 - attribute \src "libresoc.v:169095.3-169134.6" - wire width 4 $4\src22__data_o$next[3:0]$10986 - attribute \src "libresoc.v:169165.3-169204.6" - wire width 4 $4\src32__data_o$next[3:0]$11000 - attribute \src "libresoc.v:169275.3-169304.6" - wire $4\wr_detect$10[0:0]$11022 - attribute \src "libresoc.v:169345.3-169374.6" - wire $4\wr_detect$13[0:0]$11036 - attribute \src "libresoc.v:169135.3-169164.6" - wire $4\wr_detect$4[0:0]$10994 - attribute \src "libresoc.v:169205.3-169234.6" - wire $4\wr_detect$7[0:0]$11008 - attribute \src "libresoc.v:169038.3-169067.6" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $4\r22__data_o$next[3:0]$11108 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $4\r2__data_o$next[3:0]$11094 + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $4\reg$next[3:0]$11060 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $4\src12__data_o$next[3:0]$11051 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $4\src22__data_o$next[3:0]$11066 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $4\src32__data_o$next[3:0]$11080 + attribute \src "libresoc.v:178073.3-178102.6" + wire $4\wr_detect$10[0:0]$11102 + attribute \src "libresoc.v:178143.3-178172.6" + wire $4\wr_detect$13[0:0]$11116 + attribute \src "libresoc.v:177933.3-177962.6" + wire $4\wr_detect$4[0:0]$11074 + attribute \src "libresoc.v:178003.3-178032.6" + wire $4\wr_detect$7[0:0]$11088 + attribute \src "libresoc.v:177836.3-177865.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:169305.3-169344.6" - wire width 4 $5\r22__data_o$next[3:0]$11029 - attribute \src "libresoc.v:169235.3-169274.6" - wire width 4 $5\r2__data_o$next[3:0]$11015 - attribute \src "libresoc.v:168998.3-169037.6" - wire width 4 $5\src12__data_o$next[3:0]$10972 - attribute \src "libresoc.v:169095.3-169134.6" - wire width 4 $5\src22__data_o$next[3:0]$10987 - attribute \src "libresoc.v:169165.3-169204.6" - wire width 4 $5\src32__data_o$next[3:0]$11001 - attribute \src "libresoc.v:169305.3-169344.6" - wire width 4 $6\r22__data_o$next[3:0]$11030 - attribute \src "libresoc.v:169235.3-169274.6" - wire width 4 $6\r2__data_o$next[3:0]$11016 - attribute \src "libresoc.v:168998.3-169037.6" - wire width 4 $6\src12__data_o$next[3:0]$10973 - attribute \src "libresoc.v:169095.3-169134.6" - wire width 4 $6\src22__data_o$next[3:0]$10988 - attribute \src "libresoc.v:169165.3-169204.6" - wire width 4 $6\src32__data_o$next[3:0]$11002 - attribute \src "libresoc.v:168981.17-168981.104" - wire $not$libresoc.v:168981$10955_Y - attribute \src "libresoc.v:168982.18-168982.105" - wire $not$libresoc.v:168982$10956_Y - attribute \src "libresoc.v:168983.17-168983.100" - wire $not$libresoc.v:168983$10957_Y - attribute \src "libresoc.v:168984.17-168984.103" - wire $not$libresoc.v:168984$10958_Y - attribute \src "libresoc.v:168985.17-168985.103" - wire $not$libresoc.v:168985$10959_Y + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $5\r22__data_o$next[3:0]$11109 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $5\r2__data_o$next[3:0]$11095 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $5\src12__data_o$next[3:0]$11052 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $5\src22__data_o$next[3:0]$11067 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $5\src32__data_o$next[3:0]$11081 + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $6\r22__data_o$next[3:0]$11110 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $6\r2__data_o$next[3:0]$11096 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $6\src12__data_o$next[3:0]$11053 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $6\src22__data_o$next[3:0]$11068 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $6\src32__data_o$next[3:0]$11082 + attribute \src "libresoc.v:177779.17-177779.104" + wire $not$libresoc.v:177779$11035_Y + attribute \src "libresoc.v:177780.18-177780.105" + wire $not$libresoc.v:177780$11036_Y + attribute \src "libresoc.v:177781.17-177781.100" + wire $not$libresoc.v:177781$11037_Y + attribute \src "libresoc.v:177782.17-177782.103" + wire $not$libresoc.v:177782$11038_Y + attribute \src "libresoc.v:177783.17-177783.103" + wire $not$libresoc.v:177783$11039_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -350946,57 +366164,57 @@ module \reg_2 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest22__wen - attribute \src "libresoc.v:168905.7-168905.15" + attribute \src "libresoc.v:177703.7-177703.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r2__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src12__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src32__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -351009,152 +366227,152 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168981$10955 + cell $not $not$libresoc.v:177779$11035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:168981$10955_Y + connect \Y $not$libresoc.v:177779$11035_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168982$10956 + cell $not $not$libresoc.v:177780$11036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:168982$10956_Y + connect \Y $not$libresoc.v:177780$11036_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168983$10957 + cell $not $not$libresoc.v:177781$11037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:168983$10957_Y + connect \Y $not$libresoc.v:177781$11037_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168984$10958 + cell $not $not$libresoc.v:177782$11038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:168984$10958_Y + connect \Y $not$libresoc.v:177782$11038_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168985$10959 + cell $not $not$libresoc.v:177783$11039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:168985$10959_Y + connect \Y $not$libresoc.v:177783$11039_Y end - attribute \src "libresoc.v:168905.7-168905.20" - process $proc$libresoc.v:168905$11037 + attribute \src "libresoc.v:177703.7-177703.20" + process $proc$libresoc.v:177703$11117 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168930.13-168930.31" - process $proc$libresoc.v:168930$11038 + attribute \src "libresoc.v:177728.13-177728.31" + process $proc$libresoc.v:177728$11118 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:168937.13-168937.30" - process $proc$libresoc.v:168937$11039 + attribute \src "libresoc.v:177735.13-177735.30" + process $proc$libresoc.v:177735$11119 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:168943.13-168943.25" - process $proc$libresoc.v:168943$11040 + attribute \src "libresoc.v:177741.13-177741.25" + process $proc$libresoc.v:177741$11120 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:168948.13-168948.33" - process $proc$libresoc.v:168948$11041 + attribute \src "libresoc.v:177746.13-177746.33" + process $proc$libresoc.v:177746$11121 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:168955.13-168955.33" - process $proc$libresoc.v:168955$11042 + attribute \src "libresoc.v:177753.13-177753.33" + process $proc$libresoc.v:177753$11122 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:168962.13-168962.33" - process $proc$libresoc.v:168962$11043 + attribute \src "libresoc.v:177760.13-177760.33" + process $proc$libresoc.v:177760$11123 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:168986.3-168987.25" - process $proc$libresoc.v:168986$10960 + attribute \src "libresoc.v:177784.3-177785.25" + process $proc$libresoc.v:177784$11040 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:168988.3-168989.39" - process $proc$libresoc.v:168988$10961 + attribute \src "libresoc.v:177786.3-177787.39" + process $proc$libresoc.v:177786$11041 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:168990.3-168991.37" - process $proc$libresoc.v:168990$10962 + attribute \src "libresoc.v:177788.3-177789.37" + process $proc$libresoc.v:177788$11042 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:168992.3-168993.43" - process $proc$libresoc.v:168992$10963 + attribute \src "libresoc.v:177790.3-177791.43" + process $proc$libresoc.v:177790$11043 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:168994.3-168995.43" - process $proc$libresoc.v:168994$10964 + attribute \src "libresoc.v:177792.3-177793.43" + process $proc$libresoc.v:177792$11044 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:168996.3-168997.43" - process $proc$libresoc.v:168996$10965 + attribute \src "libresoc.v:177794.3-177795.43" + process $proc$libresoc.v:177794$11045 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:168998.3-169037.6" - process $proc$libresoc.v:168998$10966 + attribute \src "libresoc.v:177796.3-177835.6" + process $proc$libresoc.v:177796$11046 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[3:0]$10967 $6\src12__data_o$next[3:0]$10973 - attribute \src "libresoc.v:168999.5-168999.29" + assign $0\src12__data_o$next[3:0]$11047 $6\src12__data_o$next[3:0]$11053 + attribute \src "libresoc.v:177797.5-177797.29" switch \initial - attribute \src "libresoc.v:168999.9-168999.17" + attribute \src "libresoc.v:177797.9-177797.17" case 1'1 case end @@ -351166,66 +366384,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[3:0]$10968 $5\src12__data_o$next[3:0]$10972 + assign $1\src12__data_o$next[3:0]$11048 $5\src12__data_o$next[3:0]$11052 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[3:0]$10969 \dest12__data_i + assign $2\src12__data_o$next[3:0]$11049 \dest12__data_i case - assign $2\src12__data_o$next[3:0]$10969 4'0000 + assign $2\src12__data_o$next[3:0]$11049 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[3:0]$10970 \dest22__data_i + assign $3\src12__data_o$next[3:0]$11050 \dest22__data_i case - assign $3\src12__data_o$next[3:0]$10970 $2\src12__data_o$next[3:0]$10969 + assign $3\src12__data_o$next[3:0]$11050 $2\src12__data_o$next[3:0]$11049 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[3:0]$10971 \w2__data_i + assign $4\src12__data_o$next[3:0]$11051 \w2__data_i case - assign $4\src12__data_o$next[3:0]$10971 $3\src12__data_o$next[3:0]$10970 + assign $4\src12__data_o$next[3:0]$11051 $3\src12__data_o$next[3:0]$11050 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[3:0]$10972 \reg + assign $5\src12__data_o$next[3:0]$11052 \reg case - assign $5\src12__data_o$next[3:0]$10972 $4\src12__data_o$next[3:0]$10971 + assign $5\src12__data_o$next[3:0]$11052 $4\src12__data_o$next[3:0]$11051 end case - assign $1\src12__data_o$next[3:0]$10968 4'0000 + assign $1\src12__data_o$next[3:0]$11048 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$10973 4'0000 + assign $6\src12__data_o$next[3:0]$11053 4'0000 case - assign $6\src12__data_o$next[3:0]$10973 $1\src12__data_o$next[3:0]$10968 + assign $6\src12__data_o$next[3:0]$11053 $1\src12__data_o$next[3:0]$11048 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$10967 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11047 end - attribute \src "libresoc.v:169038.3-169067.6" - process $proc$libresoc.v:169038$10974 + attribute \src "libresoc.v:177836.3-177865.6" + process $proc$libresoc.v:177836$11054 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:169039.5-169039.29" + attribute \src "libresoc.v:177837.5-177837.29" switch \initial - attribute \src "libresoc.v:169039.9-169039.17" + attribute \src "libresoc.v:177837.9-177837.17" case 1'1 case end @@ -351271,17 +366489,17 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:169068.3-169094.6" - process $proc$libresoc.v:169068$10975 + attribute \src "libresoc.v:177866.3-177892.6" + process $proc$libresoc.v:177866$11055 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10976 $4\reg$next[3:0]$10980 - attribute \src "libresoc.v:169069.5-169069.29" + assign $0\reg$next[3:0]$11056 $4\reg$next[3:0]$11060 + attribute \src "libresoc.v:177867.5-177867.29" switch \initial - attribute \src "libresoc.v:169069.9-169069.17" + attribute \src "libresoc.v:177867.9-177867.17" case 1'1 case end @@ -351290,49 +366508,49 @@ module \reg_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10977 \dest12__data_i + assign $1\reg$next[3:0]$11057 \dest12__data_i case - assign $1\reg$next[3:0]$10977 \reg + assign $1\reg$next[3:0]$11057 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10978 \dest22__data_i + assign $2\reg$next[3:0]$11058 \dest22__data_i case - assign $2\reg$next[3:0]$10978 $1\reg$next[3:0]$10977 + assign $2\reg$next[3:0]$11058 $1\reg$next[3:0]$11057 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10979 \w2__data_i + assign $3\reg$next[3:0]$11059 \w2__data_i case - assign $3\reg$next[3:0]$10979 $2\reg$next[3:0]$10978 + assign $3\reg$next[3:0]$11059 $2\reg$next[3:0]$11058 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10980 4'0000 + assign $4\reg$next[3:0]$11060 4'0000 case - assign $4\reg$next[3:0]$10980 $3\reg$next[3:0]$10979 + assign $4\reg$next[3:0]$11060 $3\reg$next[3:0]$11059 end sync always - update \reg$next $0\reg$next[3:0]$10976 + update \reg$next $0\reg$next[3:0]$11056 end - attribute \src "libresoc.v:169095.3-169134.6" - process $proc$libresoc.v:169095$10981 + attribute \src "libresoc.v:177893.3-177932.6" + process $proc$libresoc.v:177893$11061 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$10982 $6\src22__data_o$next[3:0]$10988 - attribute \src "libresoc.v:169096.5-169096.29" + assign $0\src22__data_o$next[3:0]$11062 $6\src22__data_o$next[3:0]$11068 + attribute \src "libresoc.v:177894.5-177894.29" switch \initial - attribute \src "libresoc.v:169096.9-169096.17" + attribute \src "libresoc.v:177894.9-177894.17" case 1'1 case end @@ -351344,66 +366562,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$10983 $5\src22__data_o$next[3:0]$10987 + assign $1\src22__data_o$next[3:0]$11063 $5\src22__data_o$next[3:0]$11067 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$10984 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11064 \dest12__data_i case - assign $2\src22__data_o$next[3:0]$10984 4'0000 + assign $2\src22__data_o$next[3:0]$11064 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$10985 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11065 \dest22__data_i case - assign $3\src22__data_o$next[3:0]$10985 $2\src22__data_o$next[3:0]$10984 + assign $3\src22__data_o$next[3:0]$11065 $2\src22__data_o$next[3:0]$11064 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$10986 \w2__data_i + assign $4\src22__data_o$next[3:0]$11066 \w2__data_i case - assign $4\src22__data_o$next[3:0]$10986 $3\src22__data_o$next[3:0]$10985 + assign $4\src22__data_o$next[3:0]$11066 $3\src22__data_o$next[3:0]$11065 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$10987 \reg + assign $5\src22__data_o$next[3:0]$11067 \reg case - assign $5\src22__data_o$next[3:0]$10987 $4\src22__data_o$next[3:0]$10986 + assign $5\src22__data_o$next[3:0]$11067 $4\src22__data_o$next[3:0]$11066 end case - assign $1\src22__data_o$next[3:0]$10983 4'0000 + assign $1\src22__data_o$next[3:0]$11063 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$10988 4'0000 + assign $6\src22__data_o$next[3:0]$11068 4'0000 case - assign $6\src22__data_o$next[3:0]$10988 $1\src22__data_o$next[3:0]$10983 + assign $6\src22__data_o$next[3:0]$11068 $1\src22__data_o$next[3:0]$11063 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$10982 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11062 end - attribute \src "libresoc.v:169135.3-169164.6" - process $proc$libresoc.v:169135$10989 + attribute \src "libresoc.v:177933.3-177962.6" + process $proc$libresoc.v:177933$11069 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10990 $1\wr_detect$4[0:0]$10991 - attribute \src "libresoc.v:169136.5-169136.29" + assign $0\wr_detect$4[0:0]$11070 $1\wr_detect$4[0:0]$11071 + attribute \src "libresoc.v:177934.5-177934.29" switch \initial - attribute \src "libresoc.v:169136.9-169136.17" + attribute \src "libresoc.v:177934.9-177934.17" case 1'1 case end @@ -351415,49 +366633,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10991 $4\wr_detect$4[0:0]$10994 + assign $1\wr_detect$4[0:0]$11071 $4\wr_detect$4[0:0]$11074 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10992 1'1 + assign $2\wr_detect$4[0:0]$11072 1'1 case - assign $2\wr_detect$4[0:0]$10992 1'0 + assign $2\wr_detect$4[0:0]$11072 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10993 1'1 + assign $3\wr_detect$4[0:0]$11073 1'1 case - assign $3\wr_detect$4[0:0]$10993 $2\wr_detect$4[0:0]$10992 + assign $3\wr_detect$4[0:0]$11073 $2\wr_detect$4[0:0]$11072 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10994 1'1 + assign $4\wr_detect$4[0:0]$11074 1'1 case - assign $4\wr_detect$4[0:0]$10994 $3\wr_detect$4[0:0]$10993 + assign $4\wr_detect$4[0:0]$11074 $3\wr_detect$4[0:0]$11073 end case - assign $1\wr_detect$4[0:0]$10991 1'0 + assign $1\wr_detect$4[0:0]$11071 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10990 + update \wr_detect$4 $0\wr_detect$4[0:0]$11070 end - attribute \src "libresoc.v:169165.3-169204.6" - process $proc$libresoc.v:169165$10995 + attribute \src "libresoc.v:177963.3-178002.6" + process $proc$libresoc.v:177963$11075 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$10996 $6\src32__data_o$next[3:0]$11002 - attribute \src "libresoc.v:169166.5-169166.29" + assign $0\src32__data_o$next[3:0]$11076 $6\src32__data_o$next[3:0]$11082 + attribute \src "libresoc.v:177964.5-177964.29" switch \initial - attribute \src "libresoc.v:169166.9-169166.17" + attribute \src "libresoc.v:177964.9-177964.17" case 1'1 case end @@ -351469,66 +366687,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$10997 $5\src32__data_o$next[3:0]$11001 + assign $1\src32__data_o$next[3:0]$11077 $5\src32__data_o$next[3:0]$11081 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$10998 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11078 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$10998 4'0000 + assign $2\src32__data_o$next[3:0]$11078 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$10999 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11079 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$10999 $2\src32__data_o$next[3:0]$10998 + assign $3\src32__data_o$next[3:0]$11079 $2\src32__data_o$next[3:0]$11078 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$11000 \w2__data_i + assign $4\src32__data_o$next[3:0]$11080 \w2__data_i case - assign $4\src32__data_o$next[3:0]$11000 $3\src32__data_o$next[3:0]$10999 + assign $4\src32__data_o$next[3:0]$11080 $3\src32__data_o$next[3:0]$11079 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$11001 \reg + assign $5\src32__data_o$next[3:0]$11081 \reg case - assign $5\src32__data_o$next[3:0]$11001 $4\src32__data_o$next[3:0]$11000 + assign $5\src32__data_o$next[3:0]$11081 $4\src32__data_o$next[3:0]$11080 end case - assign $1\src32__data_o$next[3:0]$10997 4'0000 + assign $1\src32__data_o$next[3:0]$11077 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$11002 4'0000 + assign $6\src32__data_o$next[3:0]$11082 4'0000 case - assign $6\src32__data_o$next[3:0]$11002 $1\src32__data_o$next[3:0]$10997 + assign $6\src32__data_o$next[3:0]$11082 $1\src32__data_o$next[3:0]$11077 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$10996 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11076 end - attribute \src "libresoc.v:169205.3-169234.6" - process $proc$libresoc.v:169205$11003 + attribute \src "libresoc.v:178003.3-178032.6" + process $proc$libresoc.v:178003$11083 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11004 $1\wr_detect$7[0:0]$11005 - attribute \src "libresoc.v:169206.5-169206.29" + assign $0\wr_detect$7[0:0]$11084 $1\wr_detect$7[0:0]$11085 + attribute \src "libresoc.v:178004.5-178004.29" switch \initial - attribute \src "libresoc.v:169206.9-169206.17" + attribute \src "libresoc.v:178004.9-178004.17" case 1'1 case end @@ -351540,49 +366758,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11005 $4\wr_detect$7[0:0]$11008 + assign $1\wr_detect$7[0:0]$11085 $4\wr_detect$7[0:0]$11088 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11006 1'1 + assign $2\wr_detect$7[0:0]$11086 1'1 case - assign $2\wr_detect$7[0:0]$11006 1'0 + assign $2\wr_detect$7[0:0]$11086 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11007 1'1 + assign $3\wr_detect$7[0:0]$11087 1'1 case - assign $3\wr_detect$7[0:0]$11007 $2\wr_detect$7[0:0]$11006 + assign $3\wr_detect$7[0:0]$11087 $2\wr_detect$7[0:0]$11086 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11008 1'1 + assign $4\wr_detect$7[0:0]$11088 1'1 case - assign $4\wr_detect$7[0:0]$11008 $3\wr_detect$7[0:0]$11007 + assign $4\wr_detect$7[0:0]$11088 $3\wr_detect$7[0:0]$11087 end case - assign $1\wr_detect$7[0:0]$11005 1'0 + assign $1\wr_detect$7[0:0]$11085 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11004 + update \wr_detect$7 $0\wr_detect$7[0:0]$11084 end - attribute \src "libresoc.v:169235.3-169274.6" - process $proc$libresoc.v:169235$11009 + attribute \src "libresoc.v:178033.3-178072.6" + process $proc$libresoc.v:178033$11089 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11010 $6\r2__data_o$next[3:0]$11016 - attribute \src "libresoc.v:169236.5-169236.29" + assign $0\r2__data_o$next[3:0]$11090 $6\r2__data_o$next[3:0]$11096 + attribute \src "libresoc.v:178034.5-178034.29" switch \initial - attribute \src "libresoc.v:169236.9-169236.17" + attribute \src "libresoc.v:178034.9-178034.17" case 1'1 case end @@ -351594,66 +366812,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$11011 $5\r2__data_o$next[3:0]$11015 + assign $1\r2__data_o$next[3:0]$11091 $5\r2__data_o$next[3:0]$11095 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$11012 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11092 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$11012 4'0000 + assign $2\r2__data_o$next[3:0]$11092 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$11013 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11093 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$11013 $2\r2__data_o$next[3:0]$11012 + assign $3\r2__data_o$next[3:0]$11093 $2\r2__data_o$next[3:0]$11092 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$11014 \w2__data_i + assign $4\r2__data_o$next[3:0]$11094 \w2__data_i case - assign $4\r2__data_o$next[3:0]$11014 $3\r2__data_o$next[3:0]$11013 + assign $4\r2__data_o$next[3:0]$11094 $3\r2__data_o$next[3:0]$11093 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$11015 \reg + assign $5\r2__data_o$next[3:0]$11095 \reg case - assign $5\r2__data_o$next[3:0]$11015 $4\r2__data_o$next[3:0]$11014 + assign $5\r2__data_o$next[3:0]$11095 $4\r2__data_o$next[3:0]$11094 end case - assign $1\r2__data_o$next[3:0]$11011 4'0000 + assign $1\r2__data_o$next[3:0]$11091 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$11016 4'0000 + assign $6\r2__data_o$next[3:0]$11096 4'0000 case - assign $6\r2__data_o$next[3:0]$11016 $1\r2__data_o$next[3:0]$11011 + assign $6\r2__data_o$next[3:0]$11096 $1\r2__data_o$next[3:0]$11091 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11010 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11090 end - attribute \src "libresoc.v:169275.3-169304.6" - process $proc$libresoc.v:169275$11017 + attribute \src "libresoc.v:178073.3-178102.6" + process $proc$libresoc.v:178073$11097 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11018 $1\wr_detect$10[0:0]$11019 - attribute \src "libresoc.v:169276.5-169276.29" + assign $0\wr_detect$10[0:0]$11098 $1\wr_detect$10[0:0]$11099 + attribute \src "libresoc.v:178074.5-178074.29" switch \initial - attribute \src "libresoc.v:169276.9-169276.17" + attribute \src "libresoc.v:178074.9-178074.17" case 1'1 case end @@ -351665,49 +366883,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11019 $4\wr_detect$10[0:0]$11022 + assign $1\wr_detect$10[0:0]$11099 $4\wr_detect$10[0:0]$11102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11020 1'1 + assign $2\wr_detect$10[0:0]$11100 1'1 case - assign $2\wr_detect$10[0:0]$11020 1'0 + assign $2\wr_detect$10[0:0]$11100 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11021 1'1 + assign $3\wr_detect$10[0:0]$11101 1'1 case - assign $3\wr_detect$10[0:0]$11021 $2\wr_detect$10[0:0]$11020 + assign $3\wr_detect$10[0:0]$11101 $2\wr_detect$10[0:0]$11100 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11022 1'1 + assign $4\wr_detect$10[0:0]$11102 1'1 case - assign $4\wr_detect$10[0:0]$11022 $3\wr_detect$10[0:0]$11021 + assign $4\wr_detect$10[0:0]$11102 $3\wr_detect$10[0:0]$11101 end case - assign $1\wr_detect$10[0:0]$11019 1'0 + assign $1\wr_detect$10[0:0]$11099 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11018 + update \wr_detect$10 $0\wr_detect$10[0:0]$11098 end - attribute \src "libresoc.v:169305.3-169344.6" - process $proc$libresoc.v:169305$11023 + attribute \src "libresoc.v:178103.3-178142.6" + process $proc$libresoc.v:178103$11103 assign { } { } assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$11024 $6\r22__data_o$next[3:0]$11030 - attribute \src "libresoc.v:169306.5-169306.29" + assign $0\r22__data_o$next[3:0]$11104 $6\r22__data_o$next[3:0]$11110 + attribute \src "libresoc.v:178104.5-178104.29" switch \initial - attribute \src "libresoc.v:169306.9-169306.17" + attribute \src "libresoc.v:178104.9-178104.17" case 1'1 case end @@ -351719,66 +366937,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r22__data_o$next[3:0]$11025 $5\r22__data_o$next[3:0]$11029 + assign $1\r22__data_o$next[3:0]$11105 $5\r22__data_o$next[3:0]$11109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r22__data_o$next[3:0]$11026 \dest12__data_i + assign $2\r22__data_o$next[3:0]$11106 \dest12__data_i case - assign $2\r22__data_o$next[3:0]$11026 4'0000 + assign $2\r22__data_o$next[3:0]$11106 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r22__data_o$next[3:0]$11027 \dest22__data_i + assign $3\r22__data_o$next[3:0]$11107 \dest22__data_i case - assign $3\r22__data_o$next[3:0]$11027 $2\r22__data_o$next[3:0]$11026 + assign $3\r22__data_o$next[3:0]$11107 $2\r22__data_o$next[3:0]$11106 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r22__data_o$next[3:0]$11028 \w2__data_i + assign $4\r22__data_o$next[3:0]$11108 \w2__data_i case - assign $4\r22__data_o$next[3:0]$11028 $3\r22__data_o$next[3:0]$11027 + assign $4\r22__data_o$next[3:0]$11108 $3\r22__data_o$next[3:0]$11107 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r22__data_o$next[3:0]$11029 \reg + assign $5\r22__data_o$next[3:0]$11109 \reg case - assign $5\r22__data_o$next[3:0]$11029 $4\r22__data_o$next[3:0]$11028 + assign $5\r22__data_o$next[3:0]$11109 $4\r22__data_o$next[3:0]$11108 end case - assign $1\r22__data_o$next[3:0]$11025 4'0000 + assign $1\r22__data_o$next[3:0]$11105 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r22__data_o$next[3:0]$11030 4'0000 + assign $6\r22__data_o$next[3:0]$11110 4'0000 case - assign $6\r22__data_o$next[3:0]$11030 $1\r22__data_o$next[3:0]$11025 + assign $6\r22__data_o$next[3:0]$11110 $1\r22__data_o$next[3:0]$11105 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11024 + update \r22__data_o$next $0\r22__data_o$next[3:0]$11104 end - attribute \src "libresoc.v:169345.3-169374.6" - process $proc$libresoc.v:169345$11031 + attribute \src "libresoc.v:178143.3-178172.6" + process $proc$libresoc.v:178143$11111 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11032 $1\wr_detect$13[0:0]$11033 - attribute \src "libresoc.v:169346.5-169346.29" + assign $0\wr_detect$13[0:0]$11112 $1\wr_detect$13[0:0]$11113 + attribute \src "libresoc.v:178144.5-178144.29" switch \initial - attribute \src "libresoc.v:169346.9-169346.17" + attribute \src "libresoc.v:178144.9-178144.17" case 1'1 case end @@ -351790,205 +367008,205 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11033 $4\wr_detect$13[0:0]$11036 + assign $1\wr_detect$13[0:0]$11113 $4\wr_detect$13[0:0]$11116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11034 1'1 + assign $2\wr_detect$13[0:0]$11114 1'1 case - assign $2\wr_detect$13[0:0]$11034 1'0 + assign $2\wr_detect$13[0:0]$11114 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11035 1'1 + assign $3\wr_detect$13[0:0]$11115 1'1 case - assign $3\wr_detect$13[0:0]$11035 $2\wr_detect$13[0:0]$11034 + assign $3\wr_detect$13[0:0]$11115 $2\wr_detect$13[0:0]$11114 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11036 1'1 + assign $4\wr_detect$13[0:0]$11116 1'1 case - assign $4\wr_detect$13[0:0]$11036 $3\wr_detect$13[0:0]$11035 + assign $4\wr_detect$13[0:0]$11116 $3\wr_detect$13[0:0]$11115 end case - assign $1\wr_detect$13[0:0]$11033 1'0 + assign $1\wr_detect$13[0:0]$11113 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11032 + update \wr_detect$13 $0\wr_detect$13[0:0]$11112 end - connect \$9 $not$libresoc.v:168981$10955_Y - connect \$12 $not$libresoc.v:168982$10956_Y - connect \$1 $not$libresoc.v:168983$10957_Y - connect \$3 $not$libresoc.v:168984$10958_Y - connect \$6 $not$libresoc.v:168985$10959_Y + connect \$9 $not$libresoc.v:177779$11035_Y + connect \$12 $not$libresoc.v:177780$11036_Y + connect \$1 $not$libresoc.v:177781$11037_Y + connect \$3 $not$libresoc.v:177782$11038_Y + connect \$6 $not$libresoc.v:177783$11039_Y end -attribute \src "libresoc.v:169379.1-169824.10" +attribute \src "libresoc.v:178177.1-178622.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:169380.7-169380.20" + attribute \src "libresoc.v:178178.7-178178.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169709.3-169754.6" - wire width 2 $0\r2__data_o$next[1:0]$11096 - attribute \src "libresoc.v:169455.3-169456.37" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $0\r2__data_o$next[1:0]$11176 + attribute \src "libresoc.v:178253.3-178254.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:169791.3-169823.6" - wire width 2 $0\reg$next[1:0]$11112 - attribute \src "libresoc.v:169453.3-169454.25" + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $0\reg$next[1:0]$11192 + attribute \src "libresoc.v:178251.3-178252.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:169463.3-169508.6" - wire width 2 $0\src12__data_o$next[1:0]$11054 - attribute \src "libresoc.v:169461.3-169462.43" + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $0\src12__data_o$next[1:0]$11134 + attribute \src "libresoc.v:178259.3-178260.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:169545.3-169590.6" - wire width 2 $0\src22__data_o$next[1:0]$11064 - attribute \src "libresoc.v:169459.3-169460.43" + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $0\src22__data_o$next[1:0]$11144 + attribute \src "libresoc.v:178257.3-178258.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:169627.3-169672.6" - wire width 2 $0\src32__data_o$next[1:0]$11080 - attribute \src "libresoc.v:169457.3-169458.43" + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $0\src32__data_o$next[1:0]$11160 + attribute \src "libresoc.v:178255.3-178256.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:169755.3-169790.6" - wire $0\wr_detect$10[0:0]$11105 - attribute \src "libresoc.v:169591.3-169626.6" - wire $0\wr_detect$4[0:0]$11073 - attribute \src "libresoc.v:169673.3-169708.6" - wire $0\wr_detect$7[0:0]$11089 - attribute \src "libresoc.v:169509.3-169544.6" + attribute \src "libresoc.v:178553.3-178588.6" + wire $0\wr_detect$10[0:0]$11185 + attribute \src "libresoc.v:178389.3-178424.6" + wire $0\wr_detect$4[0:0]$11153 + attribute \src "libresoc.v:178471.3-178506.6" + wire $0\wr_detect$7[0:0]$11169 + attribute \src "libresoc.v:178307.3-178342.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:169709.3-169754.6" - wire width 2 $1\r2__data_o$next[1:0]$11097 - attribute \src "libresoc.v:169407.13-169407.30" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $1\r2__data_o$next[1:0]$11177 + attribute \src "libresoc.v:178205.13-178205.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:169791.3-169823.6" - wire width 2 $1\reg$next[1:0]$11113 - attribute \src "libresoc.v:169413.13-169413.25" + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $1\reg$next[1:0]$11193 + attribute \src "libresoc.v:178211.13-178211.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:169463.3-169508.6" - wire width 2 $1\src12__data_o$next[1:0]$11055 - attribute \src "libresoc.v:169418.13-169418.33" + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $1\src12__data_o$next[1:0]$11135 + attribute \src "libresoc.v:178216.13-178216.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:169545.3-169590.6" - wire width 2 $1\src22__data_o$next[1:0]$11065 - attribute \src "libresoc.v:169425.13-169425.33" + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $1\src22__data_o$next[1:0]$11145 + attribute \src "libresoc.v:178223.13-178223.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:169627.3-169672.6" - wire width 2 $1\src32__data_o$next[1:0]$11081 - attribute \src "libresoc.v:169432.13-169432.33" + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $1\src32__data_o$next[1:0]$11161 + attribute \src "libresoc.v:178230.13-178230.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:169755.3-169790.6" - wire $1\wr_detect$10[0:0]$11106 - attribute \src "libresoc.v:169591.3-169626.6" - wire $1\wr_detect$4[0:0]$11074 - attribute \src "libresoc.v:169673.3-169708.6" - wire $1\wr_detect$7[0:0]$11090 - attribute \src "libresoc.v:169509.3-169544.6" + attribute \src "libresoc.v:178553.3-178588.6" + wire $1\wr_detect$10[0:0]$11186 + attribute \src "libresoc.v:178389.3-178424.6" + wire $1\wr_detect$4[0:0]$11154 + attribute \src "libresoc.v:178471.3-178506.6" + wire $1\wr_detect$7[0:0]$11170 + attribute \src "libresoc.v:178307.3-178342.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:169709.3-169754.6" - wire width 2 $2\r2__data_o$next[1:0]$11098 - attribute \src "libresoc.v:169791.3-169823.6" - wire width 2 $2\reg$next[1:0]$11114 - attribute \src "libresoc.v:169463.3-169508.6" - wire width 2 $2\src12__data_o$next[1:0]$11056 - attribute \src "libresoc.v:169545.3-169590.6" - wire width 2 $2\src22__data_o$next[1:0]$11066 - attribute \src "libresoc.v:169627.3-169672.6" - wire width 2 $2\src32__data_o$next[1:0]$11082 - attribute \src "libresoc.v:169755.3-169790.6" - wire $2\wr_detect$10[0:0]$11107 - attribute \src "libresoc.v:169591.3-169626.6" - wire $2\wr_detect$4[0:0]$11075 - attribute \src "libresoc.v:169673.3-169708.6" - wire $2\wr_detect$7[0:0]$11091 - attribute \src "libresoc.v:169509.3-169544.6" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $2\r2__data_o$next[1:0]$11178 + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $2\reg$next[1:0]$11194 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $2\src12__data_o$next[1:0]$11136 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $2\src22__data_o$next[1:0]$11146 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $2\src32__data_o$next[1:0]$11162 + attribute \src "libresoc.v:178553.3-178588.6" + wire $2\wr_detect$10[0:0]$11187 + attribute \src "libresoc.v:178389.3-178424.6" + wire $2\wr_detect$4[0:0]$11155 + attribute \src "libresoc.v:178471.3-178506.6" + wire $2\wr_detect$7[0:0]$11171 + attribute \src "libresoc.v:178307.3-178342.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:169709.3-169754.6" - wire width 2 $3\r2__data_o$next[1:0]$11099 - attribute \src "libresoc.v:169791.3-169823.6" - wire width 2 $3\reg$next[1:0]$11115 - attribute \src "libresoc.v:169463.3-169508.6" - wire width 2 $3\src12__data_o$next[1:0]$11057 - attribute \src "libresoc.v:169545.3-169590.6" - wire width 2 $3\src22__data_o$next[1:0]$11067 - attribute \src "libresoc.v:169627.3-169672.6" - wire width 2 $3\src32__data_o$next[1:0]$11083 - attribute \src "libresoc.v:169755.3-169790.6" - wire $3\wr_detect$10[0:0]$11108 - attribute \src "libresoc.v:169591.3-169626.6" - wire $3\wr_detect$4[0:0]$11076 - attribute \src "libresoc.v:169673.3-169708.6" - wire $3\wr_detect$7[0:0]$11092 - attribute \src "libresoc.v:169509.3-169544.6" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $3\r2__data_o$next[1:0]$11179 + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $3\reg$next[1:0]$11195 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $3\src12__data_o$next[1:0]$11137 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $3\src22__data_o$next[1:0]$11147 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $3\src32__data_o$next[1:0]$11163 + attribute \src "libresoc.v:178553.3-178588.6" + wire $3\wr_detect$10[0:0]$11188 + attribute \src "libresoc.v:178389.3-178424.6" + wire $3\wr_detect$4[0:0]$11156 + attribute \src "libresoc.v:178471.3-178506.6" + wire $3\wr_detect$7[0:0]$11172 + attribute \src "libresoc.v:178307.3-178342.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:169709.3-169754.6" - wire width 2 $4\r2__data_o$next[1:0]$11100 - attribute \src "libresoc.v:169791.3-169823.6" - wire width 2 $4\reg$next[1:0]$11116 - attribute \src "libresoc.v:169463.3-169508.6" - wire width 2 $4\src12__data_o$next[1:0]$11058 - attribute \src "libresoc.v:169545.3-169590.6" - wire width 2 $4\src22__data_o$next[1:0]$11068 - attribute \src "libresoc.v:169627.3-169672.6" - wire width 2 $4\src32__data_o$next[1:0]$11084 - attribute \src "libresoc.v:169755.3-169790.6" - wire $4\wr_detect$10[0:0]$11109 - attribute \src "libresoc.v:169591.3-169626.6" - wire $4\wr_detect$4[0:0]$11077 - attribute \src "libresoc.v:169673.3-169708.6" - wire $4\wr_detect$7[0:0]$11093 - attribute \src "libresoc.v:169509.3-169544.6" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $4\r2__data_o$next[1:0]$11180 + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $4\reg$next[1:0]$11196 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $4\src12__data_o$next[1:0]$11138 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $4\src22__data_o$next[1:0]$11148 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $4\src32__data_o$next[1:0]$11164 + attribute \src "libresoc.v:178553.3-178588.6" + wire $4\wr_detect$10[0:0]$11189 + attribute \src "libresoc.v:178389.3-178424.6" + wire $4\wr_detect$4[0:0]$11157 + attribute \src "libresoc.v:178471.3-178506.6" + wire $4\wr_detect$7[0:0]$11173 + attribute \src "libresoc.v:178307.3-178342.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:169709.3-169754.6" - wire width 2 $5\r2__data_o$next[1:0]$11101 - attribute \src "libresoc.v:169791.3-169823.6" - wire width 2 $5\reg$next[1:0]$11117 - attribute \src "libresoc.v:169463.3-169508.6" - wire width 2 $5\src12__data_o$next[1:0]$11059 - attribute \src "libresoc.v:169545.3-169590.6" - wire width 2 $5\src22__data_o$next[1:0]$11069 - attribute \src "libresoc.v:169627.3-169672.6" - wire width 2 $5\src32__data_o$next[1:0]$11085 - attribute \src "libresoc.v:169755.3-169790.6" - wire $5\wr_detect$10[0:0]$11110 - attribute \src "libresoc.v:169591.3-169626.6" - wire $5\wr_detect$4[0:0]$11078 - attribute \src "libresoc.v:169673.3-169708.6" - wire $5\wr_detect$7[0:0]$11094 - attribute \src "libresoc.v:169509.3-169544.6" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $5\r2__data_o$next[1:0]$11181 + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $5\reg$next[1:0]$11197 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $5\src12__data_o$next[1:0]$11139 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $5\src22__data_o$next[1:0]$11149 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $5\src32__data_o$next[1:0]$11165 + attribute \src "libresoc.v:178553.3-178588.6" + wire $5\wr_detect$10[0:0]$11190 + attribute \src "libresoc.v:178389.3-178424.6" + wire $5\wr_detect$4[0:0]$11158 + attribute \src "libresoc.v:178471.3-178506.6" + wire $5\wr_detect$7[0:0]$11174 + attribute \src "libresoc.v:178307.3-178342.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:169709.3-169754.6" - wire width 2 $6\r2__data_o$next[1:0]$11102 - attribute \src "libresoc.v:169463.3-169508.6" - wire width 2 $6\src12__data_o$next[1:0]$11060 - attribute \src "libresoc.v:169545.3-169590.6" - wire width 2 $6\src22__data_o$next[1:0]$11070 - attribute \src "libresoc.v:169627.3-169672.6" - wire width 2 $6\src32__data_o$next[1:0]$11086 - attribute \src "libresoc.v:169709.3-169754.6" - wire width 2 $7\r2__data_o$next[1:0]$11103 - attribute \src "libresoc.v:169463.3-169508.6" - wire width 2 $7\src12__data_o$next[1:0]$11061 - attribute \src "libresoc.v:169545.3-169590.6" - wire width 2 $7\src22__data_o$next[1:0]$11071 - attribute \src "libresoc.v:169627.3-169672.6" - wire width 2 $7\src32__data_o$next[1:0]$11087 - attribute \src "libresoc.v:169449.17-169449.104" - wire $not$libresoc.v:169449$11044_Y - attribute \src "libresoc.v:169450.17-169450.100" - wire $not$libresoc.v:169450$11045_Y - attribute \src "libresoc.v:169451.17-169451.103" - wire $not$libresoc.v:169451$11046_Y - attribute \src "libresoc.v:169452.17-169452.103" - wire $not$libresoc.v:169452$11047_Y + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $6\r2__data_o$next[1:0]$11182 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $6\src12__data_o$next[1:0]$11140 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $6\src22__data_o$next[1:0]$11150 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $6\src32__data_o$next[1:0]$11166 + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $7\r2__data_o$next[1:0]$11183 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $7\src12__data_o$next[1:0]$11141 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $7\src22__data_o$next[1:0]$11151 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $7\src32__data_o$next[1:0]$11167 + attribute \src "libresoc.v:178247.17-178247.104" + wire $not$libresoc.v:178247$11124_Y + attribute \src "libresoc.v:178248.17-178248.100" + wire $not$libresoc.v:178248$11125_Y + attribute \src "libresoc.v:178249.17-178249.103" + wire $not$libresoc.v:178249$11126_Y + attribute \src "libresoc.v:178250.17-178250.103" + wire $not$libresoc.v:178250$11127_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -351997,55 +367215,55 @@ module \reg_2$134 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 13 \dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:169380.7-169380.15" + attribute \src "libresoc.v:178178.7-178178.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \r2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r2__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src12__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src32__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -352056,129 +367274,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169449$11044 + cell $not $not$libresoc.v:178247$11124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:169449$11044_Y + connect \Y $not$libresoc.v:178247$11124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169450$11045 + cell $not $not$libresoc.v:178248$11125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:169450$11045_Y + connect \Y $not$libresoc.v:178248$11125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169451$11046 + cell $not $not$libresoc.v:178249$11126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:169451$11046_Y + connect \Y $not$libresoc.v:178249$11126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169452$11047 + cell $not $not$libresoc.v:178250$11127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:169452$11047_Y + connect \Y $not$libresoc.v:178250$11127_Y end - attribute \src "libresoc.v:169380.7-169380.20" - process $proc$libresoc.v:169380$11118 + attribute \src "libresoc.v:178178.7-178178.20" + process $proc$libresoc.v:178178$11198 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169407.13-169407.30" - process $proc$libresoc.v:169407$11119 + attribute \src "libresoc.v:178205.13-178205.30" + process $proc$libresoc.v:178205$11199 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:169413.13-169413.25" - process $proc$libresoc.v:169413$11120 + attribute \src "libresoc.v:178211.13-178211.25" + process $proc$libresoc.v:178211$11200 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:169418.13-169418.33" - process $proc$libresoc.v:169418$11121 + attribute \src "libresoc.v:178216.13-178216.33" + process $proc$libresoc.v:178216$11201 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:169425.13-169425.33" - process $proc$libresoc.v:169425$11122 + attribute \src "libresoc.v:178223.13-178223.33" + process $proc$libresoc.v:178223$11202 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:169432.13-169432.33" - process $proc$libresoc.v:169432$11123 + attribute \src "libresoc.v:178230.13-178230.33" + process $proc$libresoc.v:178230$11203 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:169453.3-169454.25" - process $proc$libresoc.v:169453$11048 + attribute \src "libresoc.v:178251.3-178252.25" + process $proc$libresoc.v:178251$11128 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:169455.3-169456.37" - process $proc$libresoc.v:169455$11049 + attribute \src "libresoc.v:178253.3-178254.37" + process $proc$libresoc.v:178253$11129 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:169457.3-169458.43" - process $proc$libresoc.v:169457$11050 + attribute \src "libresoc.v:178255.3-178256.43" + process $proc$libresoc.v:178255$11130 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:169459.3-169460.43" - process $proc$libresoc.v:169459$11051 + attribute \src "libresoc.v:178257.3-178258.43" + process $proc$libresoc.v:178257$11131 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:169461.3-169462.43" - process $proc$libresoc.v:169461$11052 + attribute \src "libresoc.v:178259.3-178260.43" + process $proc$libresoc.v:178259$11132 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:169463.3-169508.6" - process $proc$libresoc.v:169463$11053 + attribute \src "libresoc.v:178261.3-178306.6" + process $proc$libresoc.v:178261$11133 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$11054 $7\src12__data_o$next[1:0]$11061 - attribute \src "libresoc.v:169464.5-169464.29" + assign $0\src12__data_o$next[1:0]$11134 $7\src12__data_o$next[1:0]$11141 + attribute \src "libresoc.v:178262.5-178262.29" switch \initial - attribute \src "libresoc.v:169464.9-169464.17" + attribute \src "libresoc.v:178262.9-178262.17" case 1'1 case end @@ -352191,75 +367409,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$11055 $6\src12__data_o$next[1:0]$11060 + assign $1\src12__data_o$next[1:0]$11135 $6\src12__data_o$next[1:0]$11140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$11056 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11136 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$11056 2'00 + assign $2\src12__data_o$next[1:0]$11136 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$11057 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11137 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$11057 $2\src12__data_o$next[1:0]$11056 + assign $3\src12__data_o$next[1:0]$11137 $2\src12__data_o$next[1:0]$11136 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$11058 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11138 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$11058 $3\src12__data_o$next[1:0]$11057 + assign $4\src12__data_o$next[1:0]$11138 $3\src12__data_o$next[1:0]$11137 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$11059 \w2__data_i + assign $5\src12__data_o$next[1:0]$11139 \w2__data_i case - assign $5\src12__data_o$next[1:0]$11059 $4\src12__data_o$next[1:0]$11058 + assign $5\src12__data_o$next[1:0]$11139 $4\src12__data_o$next[1:0]$11138 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$11060 \reg + assign $6\src12__data_o$next[1:0]$11140 \reg case - assign $6\src12__data_o$next[1:0]$11060 $5\src12__data_o$next[1:0]$11059 + assign $6\src12__data_o$next[1:0]$11140 $5\src12__data_o$next[1:0]$11139 end case - assign $1\src12__data_o$next[1:0]$11055 2'00 + assign $1\src12__data_o$next[1:0]$11135 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$11061 2'00 + assign $7\src12__data_o$next[1:0]$11141 2'00 case - assign $7\src12__data_o$next[1:0]$11061 $1\src12__data_o$next[1:0]$11055 + assign $7\src12__data_o$next[1:0]$11141 $1\src12__data_o$next[1:0]$11135 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11054 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11134 end - attribute \src "libresoc.v:169509.3-169544.6" - process $proc$libresoc.v:169509$11062 + attribute \src "libresoc.v:178307.3-178342.6" + process $proc$libresoc.v:178307$11142 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:169510.5-169510.29" + attribute \src "libresoc.v:178308.5-178308.29" switch \initial - attribute \src "libresoc.v:169510.9-169510.17" + attribute \src "libresoc.v:178308.9-178308.17" case 1'1 case end @@ -352315,15 +367533,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:169545.3-169590.6" - process $proc$libresoc.v:169545$11063 + attribute \src "libresoc.v:178343.3-178388.6" + process $proc$libresoc.v:178343$11143 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$11064 $7\src22__data_o$next[1:0]$11071 - attribute \src "libresoc.v:169546.5-169546.29" + assign $0\src22__data_o$next[1:0]$11144 $7\src22__data_o$next[1:0]$11151 + attribute \src "libresoc.v:178344.5-178344.29" switch \initial - attribute \src "libresoc.v:169546.9-169546.17" + attribute \src "libresoc.v:178344.9-178344.17" case 1'1 case end @@ -352336,75 +367554,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$11065 $6\src22__data_o$next[1:0]$11070 + assign $1\src22__data_o$next[1:0]$11145 $6\src22__data_o$next[1:0]$11150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$11066 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11146 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$11066 2'00 + assign $2\src22__data_o$next[1:0]$11146 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$11067 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11147 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$11067 $2\src22__data_o$next[1:0]$11066 + assign $3\src22__data_o$next[1:0]$11147 $2\src22__data_o$next[1:0]$11146 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$11068 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11148 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$11068 $3\src22__data_o$next[1:0]$11067 + assign $4\src22__data_o$next[1:0]$11148 $3\src22__data_o$next[1:0]$11147 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$11069 \w2__data_i + assign $5\src22__data_o$next[1:0]$11149 \w2__data_i case - assign $5\src22__data_o$next[1:0]$11069 $4\src22__data_o$next[1:0]$11068 + assign $5\src22__data_o$next[1:0]$11149 $4\src22__data_o$next[1:0]$11148 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$11070 \reg + assign $6\src22__data_o$next[1:0]$11150 \reg case - assign $6\src22__data_o$next[1:0]$11070 $5\src22__data_o$next[1:0]$11069 + assign $6\src22__data_o$next[1:0]$11150 $5\src22__data_o$next[1:0]$11149 end case - assign $1\src22__data_o$next[1:0]$11065 2'00 + assign $1\src22__data_o$next[1:0]$11145 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$11071 2'00 + assign $7\src22__data_o$next[1:0]$11151 2'00 case - assign $7\src22__data_o$next[1:0]$11071 $1\src22__data_o$next[1:0]$11065 + assign $7\src22__data_o$next[1:0]$11151 $1\src22__data_o$next[1:0]$11145 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11064 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11144 end - attribute \src "libresoc.v:169591.3-169626.6" - process $proc$libresoc.v:169591$11072 + attribute \src "libresoc.v:178389.3-178424.6" + process $proc$libresoc.v:178389$11152 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11073 $1\wr_detect$4[0:0]$11074 - attribute \src "libresoc.v:169592.5-169592.29" + assign $0\wr_detect$4[0:0]$11153 $1\wr_detect$4[0:0]$11154 + attribute \src "libresoc.v:178390.5-178390.29" switch \initial - attribute \src "libresoc.v:169592.9-169592.17" + attribute \src "libresoc.v:178390.9-178390.17" case 1'1 case end @@ -352417,58 +367635,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11074 $5\wr_detect$4[0:0]$11078 + assign $1\wr_detect$4[0:0]$11154 $5\wr_detect$4[0:0]$11158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11075 1'1 + assign $2\wr_detect$4[0:0]$11155 1'1 case - assign $2\wr_detect$4[0:0]$11075 1'0 + assign $2\wr_detect$4[0:0]$11155 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11076 1'1 + assign $3\wr_detect$4[0:0]$11156 1'1 case - assign $3\wr_detect$4[0:0]$11076 $2\wr_detect$4[0:0]$11075 + assign $3\wr_detect$4[0:0]$11156 $2\wr_detect$4[0:0]$11155 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11077 1'1 + assign $4\wr_detect$4[0:0]$11157 1'1 case - assign $4\wr_detect$4[0:0]$11077 $3\wr_detect$4[0:0]$11076 + assign $4\wr_detect$4[0:0]$11157 $3\wr_detect$4[0:0]$11156 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11078 1'1 + assign $5\wr_detect$4[0:0]$11158 1'1 case - assign $5\wr_detect$4[0:0]$11078 $4\wr_detect$4[0:0]$11077 + assign $5\wr_detect$4[0:0]$11158 $4\wr_detect$4[0:0]$11157 end case - assign $1\wr_detect$4[0:0]$11074 1'0 + assign $1\wr_detect$4[0:0]$11154 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11073 + update \wr_detect$4 $0\wr_detect$4[0:0]$11153 end - attribute \src "libresoc.v:169627.3-169672.6" - process $proc$libresoc.v:169627$11079 + attribute \src "libresoc.v:178425.3-178470.6" + process $proc$libresoc.v:178425$11159 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$11080 $7\src32__data_o$next[1:0]$11087 - attribute \src "libresoc.v:169628.5-169628.29" + assign $0\src32__data_o$next[1:0]$11160 $7\src32__data_o$next[1:0]$11167 + attribute \src "libresoc.v:178426.5-178426.29" switch \initial - attribute \src "libresoc.v:169628.9-169628.17" + attribute \src "libresoc.v:178426.9-178426.17" case 1'1 case end @@ -352481,75 +367699,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$11081 $6\src32__data_o$next[1:0]$11086 + assign $1\src32__data_o$next[1:0]$11161 $6\src32__data_o$next[1:0]$11166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$11082 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11162 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$11082 2'00 + assign $2\src32__data_o$next[1:0]$11162 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$11083 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11163 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$11083 $2\src32__data_o$next[1:0]$11082 + assign $3\src32__data_o$next[1:0]$11163 $2\src32__data_o$next[1:0]$11162 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$11084 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11164 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$11084 $3\src32__data_o$next[1:0]$11083 + assign $4\src32__data_o$next[1:0]$11164 $3\src32__data_o$next[1:0]$11163 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$11085 \w2__data_i + assign $5\src32__data_o$next[1:0]$11165 \w2__data_i case - assign $5\src32__data_o$next[1:0]$11085 $4\src32__data_o$next[1:0]$11084 + assign $5\src32__data_o$next[1:0]$11165 $4\src32__data_o$next[1:0]$11164 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$11086 \reg + assign $6\src32__data_o$next[1:0]$11166 \reg case - assign $6\src32__data_o$next[1:0]$11086 $5\src32__data_o$next[1:0]$11085 + assign $6\src32__data_o$next[1:0]$11166 $5\src32__data_o$next[1:0]$11165 end case - assign $1\src32__data_o$next[1:0]$11081 2'00 + assign $1\src32__data_o$next[1:0]$11161 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$11087 2'00 + assign $7\src32__data_o$next[1:0]$11167 2'00 case - assign $7\src32__data_o$next[1:0]$11087 $1\src32__data_o$next[1:0]$11081 + assign $7\src32__data_o$next[1:0]$11167 $1\src32__data_o$next[1:0]$11161 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11080 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11160 end - attribute \src "libresoc.v:169673.3-169708.6" - process $proc$libresoc.v:169673$11088 + attribute \src "libresoc.v:178471.3-178506.6" + process $proc$libresoc.v:178471$11168 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11089 $1\wr_detect$7[0:0]$11090 - attribute \src "libresoc.v:169674.5-169674.29" + assign $0\wr_detect$7[0:0]$11169 $1\wr_detect$7[0:0]$11170 + attribute \src "libresoc.v:178472.5-178472.29" switch \initial - attribute \src "libresoc.v:169674.9-169674.17" + attribute \src "libresoc.v:178472.9-178472.17" case 1'1 case end @@ -352562,58 +367780,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11090 $5\wr_detect$7[0:0]$11094 + assign $1\wr_detect$7[0:0]$11170 $5\wr_detect$7[0:0]$11174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11091 1'1 + assign $2\wr_detect$7[0:0]$11171 1'1 case - assign $2\wr_detect$7[0:0]$11091 1'0 + assign $2\wr_detect$7[0:0]$11171 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11092 1'1 + assign $3\wr_detect$7[0:0]$11172 1'1 case - assign $3\wr_detect$7[0:0]$11092 $2\wr_detect$7[0:0]$11091 + assign $3\wr_detect$7[0:0]$11172 $2\wr_detect$7[0:0]$11171 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11093 1'1 + assign $4\wr_detect$7[0:0]$11173 1'1 case - assign $4\wr_detect$7[0:0]$11093 $3\wr_detect$7[0:0]$11092 + assign $4\wr_detect$7[0:0]$11173 $3\wr_detect$7[0:0]$11172 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11094 1'1 + assign $5\wr_detect$7[0:0]$11174 1'1 case - assign $5\wr_detect$7[0:0]$11094 $4\wr_detect$7[0:0]$11093 + assign $5\wr_detect$7[0:0]$11174 $4\wr_detect$7[0:0]$11173 end case - assign $1\wr_detect$7[0:0]$11090 1'0 + assign $1\wr_detect$7[0:0]$11170 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11089 + update \wr_detect$7 $0\wr_detect$7[0:0]$11169 end - attribute \src "libresoc.v:169709.3-169754.6" - process $proc$libresoc.v:169709$11095 + attribute \src "libresoc.v:178507.3-178552.6" + process $proc$libresoc.v:178507$11175 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$11096 $7\r2__data_o$next[1:0]$11103 - attribute \src "libresoc.v:169710.5-169710.29" + assign $0\r2__data_o$next[1:0]$11176 $7\r2__data_o$next[1:0]$11183 + attribute \src "libresoc.v:178508.5-178508.29" switch \initial - attribute \src "libresoc.v:169710.9-169710.17" + attribute \src "libresoc.v:178508.9-178508.17" case 1'1 case end @@ -352626,80 +367844,711 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$11097 $6\r2__data_o$next[1:0]$11102 + assign $1\r2__data_o$next[1:0]$11177 $6\r2__data_o$next[1:0]$11182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$11098 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11178 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$11098 2'00 + assign $2\r2__data_o$next[1:0]$11178 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$11099 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11179 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$11099 $2\r2__data_o$next[1:0]$11098 + assign $3\r2__data_o$next[1:0]$11179 $2\r2__data_o$next[1:0]$11178 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$11100 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11180 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$11100 $3\r2__data_o$next[1:0]$11099 + assign $4\r2__data_o$next[1:0]$11180 $3\r2__data_o$next[1:0]$11179 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$11101 \w2__data_i + assign $5\r2__data_o$next[1:0]$11181 \w2__data_i case - assign $5\r2__data_o$next[1:0]$11101 $4\r2__data_o$next[1:0]$11100 + assign $5\r2__data_o$next[1:0]$11181 $4\r2__data_o$next[1:0]$11180 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$11102 \reg + assign $6\r2__data_o$next[1:0]$11182 \reg + case + assign $6\r2__data_o$next[1:0]$11182 $5\r2__data_o$next[1:0]$11181 + end + case + assign $1\r2__data_o$next[1:0]$11177 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r2__data_o$next[1:0]$11183 2'00 + case + assign $7\r2__data_o$next[1:0]$11183 $1\r2__data_o$next[1:0]$11177 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[1:0]$11176 + end + attribute \src "libresoc.v:178553.3-178588.6" + process $proc$libresoc.v:178553$11184 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11185 $1\wr_detect$10[0:0]$11186 + attribute \src "libresoc.v:178554.5-178554.29" + switch \initial + attribute \src "libresoc.v:178554.9-178554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11186 $5\wr_detect$10[0:0]$11190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11187 1'1 + case + assign $2\wr_detect$10[0:0]$11187 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11188 1'1 + case + assign $3\wr_detect$10[0:0]$11188 $2\wr_detect$10[0:0]$11187 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11189 1'1 + case + assign $4\wr_detect$10[0:0]$11189 $3\wr_detect$10[0:0]$11188 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$11190 1'1 + case + assign $5\wr_detect$10[0:0]$11190 $4\wr_detect$10[0:0]$11189 + end + case + assign $1\wr_detect$10[0:0]$11186 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11185 + end + attribute \src "libresoc.v:178589.3-178621.6" + process $proc$libresoc.v:178589$11191 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$11192 $5\reg$next[1:0]$11197 + attribute \src "libresoc.v:178590.5-178590.29" + switch \initial + attribute \src "libresoc.v:178590.9-178590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$11193 \dest12__data_i + case + assign $1\reg$next[1:0]$11193 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$11194 \dest22__data_i + case + assign $2\reg$next[1:0]$11194 $1\reg$next[1:0]$11193 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$11195 \dest32__data_i + case + assign $3\reg$next[1:0]$11195 $2\reg$next[1:0]$11194 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$11196 \w2__data_i + case + assign $4\reg$next[1:0]$11196 $3\reg$next[1:0]$11195 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$11197 2'00 + case + assign $5\reg$next[1:0]$11197 $4\reg$next[1:0]$11196 + end + sync always + update \reg$next $0\reg$next[1:0]$11192 + end + connect \$9 $not$libresoc.v:178247$11124_Y + connect \$1 $not$libresoc.v:178248$11125_Y + connect \$3 $not$libresoc.v:178249$11126_Y + connect \$6 $not$libresoc.v:178250$11127_Y +end +attribute \src "libresoc.v:178626.1-178975.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" +attribute \generator "nMigen" +module \reg_2$137 + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $0\cia2__data_o$next[63:0]$11212 + attribute \src "libresoc.v:178694.3-178695.41" + wire width 64 $0\cia2__data_o[63:0] + attribute \src "libresoc.v:178627.7-178627.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $0\msr2__data_o$next[63:0]$11222 + attribute \src "libresoc.v:178692.3-178693.41" + wire width 64 $0\msr2__data_o[63:0] + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $0\reg$next[63:0]$11254 + attribute \src "libresoc.v:178688.3-178689.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $0\sv2__data_o$next[63:0]$11238 + attribute \src "libresoc.v:178690.3-178691.39" + wire width 64 $0\sv2__data_o[63:0] + attribute \src "libresoc.v:178824.3-178859.6" + wire $0\wr_detect$4[0:0]$11231 + attribute \src "libresoc.v:178906.3-178941.6" + wire $0\wr_detect$7[0:0]$11247 + attribute \src "libresoc.v:178742.3-178777.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $1\cia2__data_o$next[63:0]$11213 + attribute \src "libresoc.v:178636.14-178636.49" + wire width 64 $1\cia2__data_o[63:0] + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $1\msr2__data_o$next[63:0]$11223 + attribute \src "libresoc.v:178653.14-178653.49" + wire width 64 $1\msr2__data_o[63:0] + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $1\reg$next[63:0]$11255 + attribute \src "libresoc.v:178665.14-178665.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $1\sv2__data_o$next[63:0]$11239 + attribute \src "libresoc.v:178672.14-178672.48" + wire width 64 $1\sv2__data_o[63:0] + attribute \src "libresoc.v:178824.3-178859.6" + wire $1\wr_detect$4[0:0]$11232 + attribute \src "libresoc.v:178906.3-178941.6" + wire $1\wr_detect$7[0:0]$11248 + attribute \src "libresoc.v:178742.3-178777.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $2\cia2__data_o$next[63:0]$11214 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $2\msr2__data_o$next[63:0]$11224 + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $2\reg$next[63:0]$11256 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $2\sv2__data_o$next[63:0]$11240 + attribute \src "libresoc.v:178824.3-178859.6" + wire $2\wr_detect$4[0:0]$11233 + attribute \src "libresoc.v:178906.3-178941.6" + wire $2\wr_detect$7[0:0]$11249 + attribute \src "libresoc.v:178742.3-178777.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $3\cia2__data_o$next[63:0]$11215 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $3\msr2__data_o$next[63:0]$11225 + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $3\reg$next[63:0]$11257 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $3\sv2__data_o$next[63:0]$11241 + attribute \src "libresoc.v:178824.3-178859.6" + wire $3\wr_detect$4[0:0]$11234 + attribute \src "libresoc.v:178906.3-178941.6" + wire $3\wr_detect$7[0:0]$11250 + attribute \src "libresoc.v:178742.3-178777.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $4\cia2__data_o$next[63:0]$11216 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $4\msr2__data_o$next[63:0]$11226 + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $4\reg$next[63:0]$11258 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $4\sv2__data_o$next[63:0]$11242 + attribute \src "libresoc.v:178824.3-178859.6" + wire $4\wr_detect$4[0:0]$11235 + attribute \src "libresoc.v:178906.3-178941.6" + wire $4\wr_detect$7[0:0]$11251 + attribute \src "libresoc.v:178742.3-178777.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $5\cia2__data_o$next[63:0]$11217 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $5\msr2__data_o$next[63:0]$11227 + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $5\reg$next[63:0]$11259 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $5\sv2__data_o$next[63:0]$11243 + attribute \src "libresoc.v:178824.3-178859.6" + wire $5\wr_detect$4[0:0]$11236 + attribute \src "libresoc.v:178906.3-178941.6" + wire $5\wr_detect$7[0:0]$11252 + attribute \src "libresoc.v:178742.3-178777.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $6\cia2__data_o$next[63:0]$11218 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $6\msr2__data_o$next[63:0]$11228 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $6\sv2__data_o$next[63:0]$11244 + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $7\cia2__data_o$next[63:0]$11219 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $7\msr2__data_o$next[63:0]$11229 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $7\sv2__data_o$next[63:0]$11245 + attribute \src "libresoc.v:178685.17-178685.100" + wire $not$libresoc.v:178685$11204_Y + attribute \src "libresoc.v:178686.17-178686.103" + wire $not$libresoc.v:178686$11205_Y + attribute \src "libresoc.v:178687.17-178687.103" + wire $not$libresoc.v:178687$11206_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 3 \cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \cia2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cia2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr12__wen + attribute \src "libresoc.v:178627.7-178627.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \msr2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178685$11204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:178685$11204_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178686$11205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:178686$11205_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178687$11206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:178687$11206_Y + end + attribute \src "libresoc.v:178627.7-178627.20" + process $proc$libresoc.v:178627$11260 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178636.14-178636.49" + process $proc$libresoc.v:178636$11261 + assign { } { } + assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia2__data_o $1\cia2__data_o[63:0] + end + attribute \src "libresoc.v:178653.14-178653.49" + process $proc$libresoc.v:178653$11262 + assign { } { } + assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr2__data_o $1\msr2__data_o[63:0] + end + attribute \src "libresoc.v:178665.14-178665.42" + process $proc$libresoc.v:178665$11263 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:178672.14-178672.48" + process $proc$libresoc.v:178672$11264 + assign { } { } + assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv2__data_o $1\sv2__data_o[63:0] + end + attribute \src "libresoc.v:178688.3-178689.25" + process $proc$libresoc.v:178688$11207 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:178690.3-178691.39" + process $proc$libresoc.v:178690$11208 + assign { } { } + assign $0\sv2__data_o[63:0] \sv2__data_o$next + sync posedge \coresync_clk + update \sv2__data_o $0\sv2__data_o[63:0] + end + attribute \src "libresoc.v:178692.3-178693.41" + process $proc$libresoc.v:178692$11209 + assign { } { } + assign $0\msr2__data_o[63:0] \msr2__data_o$next + sync posedge \coresync_clk + update \msr2__data_o $0\msr2__data_o[63:0] + end + attribute \src "libresoc.v:178694.3-178695.41" + process $proc$libresoc.v:178694$11210 + assign { } { } + assign $0\cia2__data_o[63:0] \cia2__data_o$next + sync posedge \coresync_clk + update \cia2__data_o $0\cia2__data_o[63:0] + end + attribute \src "libresoc.v:178696.3-178741.6" + process $proc$libresoc.v:178696$11211 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia2__data_o$next[63:0]$11212 $7\cia2__data_o$next[63:0]$11219 + attribute \src "libresoc.v:178697.5-178697.29" + switch \initial + attribute \src "libresoc.v:178697.9-178697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia2__data_o$next[63:0]$11213 $6\cia2__data_o$next[63:0]$11218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia2__data_o$next[63:0]$11214 \nia2__data_i + case + assign $2\cia2__data_o$next[63:0]$11214 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia2__data_o$next[63:0]$11215 \msr2__data_i + case + assign $3\cia2__data_o$next[63:0]$11215 $2\cia2__data_o$next[63:0]$11214 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia2__data_o$next[63:0]$11216 \sv2__data_i + case + assign $4\cia2__data_o$next[63:0]$11216 $3\cia2__data_o$next[63:0]$11215 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia2__data_o$next[63:0]$11217 \d_wr12__data_i + case + assign $5\cia2__data_o$next[63:0]$11217 $4\cia2__data_o$next[63:0]$11216 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia2__data_o$next[63:0]$11218 \reg + case + assign $6\cia2__data_o$next[63:0]$11218 $5\cia2__data_o$next[63:0]$11217 + end + case + assign $1\cia2__data_o$next[63:0]$11213 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\cia2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\cia2__data_o$next[63:0]$11219 $1\cia2__data_o$next[63:0]$11213 + end + sync always + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11212 + end + attribute \src "libresoc.v:178742.3-178777.6" + process $proc$libresoc.v:178742$11220 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:178743.5-178743.29" + switch \initial + attribute \src "libresoc.v:178743.9-178743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:178778.3-178823.6" + process $proc$libresoc.v:178778$11221 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr2__data_o$next[63:0]$11222 $7\msr2__data_o$next[63:0]$11229 + attribute \src "libresoc.v:178779.5-178779.29" + switch \initial + attribute \src "libresoc.v:178779.9-178779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr2__data_o$next[63:0]$11223 $6\msr2__data_o$next[63:0]$11228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr2__data_o$next[63:0]$11224 \nia2__data_i + case + assign $2\msr2__data_o$next[63:0]$11224 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr2__data_o$next[63:0]$11225 \msr2__data_i + case + assign $3\msr2__data_o$next[63:0]$11225 $2\msr2__data_o$next[63:0]$11224 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr2__data_o$next[63:0]$11226 \sv2__data_i + case + assign $4\msr2__data_o$next[63:0]$11226 $3\msr2__data_o$next[63:0]$11225 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr2__data_o$next[63:0]$11227 \d_wr12__data_i + case + assign $5\msr2__data_o$next[63:0]$11227 $4\msr2__data_o$next[63:0]$11226 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr2__data_o$next[63:0]$11228 \reg case - assign $6\r2__data_o$next[1:0]$11102 $5\r2__data_o$next[1:0]$11101 + assign $6\msr2__data_o$next[63:0]$11228 $5\msr2__data_o$next[63:0]$11227 end case - assign $1\r2__data_o$next[1:0]$11097 2'00 + assign $1\msr2__data_o$next[63:0]$11223 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$11103 2'00 + assign $7\msr2__data_o$next[63:0]$11229 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\r2__data_o$next[1:0]$11103 $1\r2__data_o$next[1:0]$11097 + assign $7\msr2__data_o$next[63:0]$11229 $1\msr2__data_o$next[63:0]$11223 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11096 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11222 end - attribute \src "libresoc.v:169755.3-169790.6" - process $proc$libresoc.v:169755$11104 + attribute \src "libresoc.v:178824.3-178859.6" + process $proc$libresoc.v:178824$11230 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11105 $1\wr_detect$10[0:0]$11106 - attribute \src "libresoc.v:169756.5-169756.29" + assign $0\wr_detect$4[0:0]$11231 $1\wr_detect$4[0:0]$11232 + attribute \src "libresoc.v:178825.5-178825.29" switch \initial - attribute \src "libresoc.v:169756.9-169756.17" + attribute \src "libresoc.v:178825.9-178825.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + switch \msr2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -352707,570 +368556,206 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11106 $5\wr_detect$10[0:0]$11110 + assign $1\wr_detect$4[0:0]$11232 $5\wr_detect$4[0:0]$11236 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen + switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11107 1'1 + assign $2\wr_detect$4[0:0]$11233 1'1 case - assign $2\wr_detect$10[0:0]$11107 1'0 + assign $2\wr_detect$4[0:0]$11233 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen + switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11108 1'1 + assign $3\wr_detect$4[0:0]$11234 1'1 case - assign $3\wr_detect$10[0:0]$11108 $2\wr_detect$10[0:0]$11107 + assign $3\wr_detect$4[0:0]$11234 $2\wr_detect$4[0:0]$11233 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen + switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11109 1'1 + assign $4\wr_detect$4[0:0]$11235 1'1 case - assign $4\wr_detect$10[0:0]$11109 $3\wr_detect$10[0:0]$11108 + assign $4\wr_detect$4[0:0]$11235 $3\wr_detect$4[0:0]$11234 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen + switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11110 1'1 + assign $5\wr_detect$4[0:0]$11236 1'1 case - assign $5\wr_detect$10[0:0]$11110 $4\wr_detect$10[0:0]$11109 + assign $5\wr_detect$4[0:0]$11236 $4\wr_detect$4[0:0]$11235 end case - assign $1\wr_detect$10[0:0]$11106 1'0 + assign $1\wr_detect$4[0:0]$11232 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11105 + update \wr_detect$4 $0\wr_detect$4[0:0]$11231 end - attribute \src "libresoc.v:169791.3-169823.6" - process $proc$libresoc.v:169791$11111 - assign { } { } + attribute \src "libresoc.v:178860.3-178905.6" + process $proc$libresoc.v:178860$11237 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[1:0]$11112 $5\reg$next[1:0]$11117 - attribute \src "libresoc.v:169792.5-169792.29" + assign $0\sv2__data_o$next[63:0]$11238 $7\sv2__data_o$next[63:0]$11245 + attribute \src "libresoc.v:178861.5-178861.29" switch \initial - attribute \src "libresoc.v:169792.9-169792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[1:0]$11113 \dest12__data_i - case - assign $1\reg$next[1:0]$11113 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[1:0]$11114 \dest22__data_i - case - assign $2\reg$next[1:0]$11114 $1\reg$next[1:0]$11113 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[1:0]$11115 \dest32__data_i - case - assign $3\reg$next[1:0]$11115 $2\reg$next[1:0]$11114 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[1:0]$11116 \w2__data_i - case - assign $4\reg$next[1:0]$11116 $3\reg$next[1:0]$11115 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\reg$next[1:0]$11117 2'00 - case - assign $5\reg$next[1:0]$11117 $4\reg$next[1:0]$11116 - end - sync always - update \reg$next $0\reg$next[1:0]$11112 - end - connect \$9 $not$libresoc.v:169449$11044_Y - connect \$1 $not$libresoc.v:169450$11045_Y - connect \$3 $not$libresoc.v:169451$11046_Y - connect \$6 $not$libresoc.v:169452$11047_Y -end -attribute \src "libresoc.v:169828.1-170047.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" -attribute \generator "nMigen" -module \reg_2$137 - attribute \src "libresoc.v:169880.3-169919.6" - wire width 64 $0\cia2__data_o$next[63:0]$11130 - attribute \src "libresoc.v:169878.3-169879.41" - wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:169829.7-169829.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:169950.3-169989.6" - wire width 64 $0\msr2__data_o$next[63:0]$11139 - attribute \src "libresoc.v:169876.3-169877.41" - wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:170020.3-170046.6" - wire width 64 $0\reg$next[63:0]$11153 - attribute \src "libresoc.v:169874.3-169875.25" - wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:169990.3-170019.6" - wire $0\wr_detect$4[0:0]$11147 - attribute \src "libresoc.v:169920.3-169949.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:169880.3-169919.6" - wire width 64 $1\cia2__data_o$next[63:0]$11131 - attribute \src "libresoc.v:169836.14-169836.49" - wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:169950.3-169989.6" - wire width 64 $1\msr2__data_o$next[63:0]$11140 - attribute \src "libresoc.v:169853.14-169853.49" - wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:170020.3-170046.6" - wire width 64 $1\reg$next[63:0]$11154 - attribute \src "libresoc.v:169865.14-169865.42" - wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:169990.3-170019.6" - wire $1\wr_detect$4[0:0]$11148 - attribute \src "libresoc.v:169920.3-169949.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:169880.3-169919.6" - wire width 64 $2\cia2__data_o$next[63:0]$11132 - attribute \src "libresoc.v:169950.3-169989.6" - wire width 64 $2\msr2__data_o$next[63:0]$11141 - attribute \src "libresoc.v:170020.3-170046.6" - wire width 64 $2\reg$next[63:0]$11155 - attribute \src "libresoc.v:169990.3-170019.6" - wire $2\wr_detect$4[0:0]$11149 - attribute \src "libresoc.v:169920.3-169949.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:169880.3-169919.6" - wire width 64 $3\cia2__data_o$next[63:0]$11133 - attribute \src "libresoc.v:169950.3-169989.6" - wire width 64 $3\msr2__data_o$next[63:0]$11142 - attribute \src "libresoc.v:170020.3-170046.6" - wire width 64 $3\reg$next[63:0]$11156 - attribute \src "libresoc.v:169990.3-170019.6" - wire $3\wr_detect$4[0:0]$11150 - attribute \src "libresoc.v:169920.3-169949.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:169880.3-169919.6" - wire width 64 $4\cia2__data_o$next[63:0]$11134 - attribute \src "libresoc.v:169950.3-169989.6" - wire width 64 $4\msr2__data_o$next[63:0]$11143 - attribute \src "libresoc.v:170020.3-170046.6" - wire width 64 $4\reg$next[63:0]$11157 - attribute \src "libresoc.v:169990.3-170019.6" - wire $4\wr_detect$4[0:0]$11151 - attribute \src "libresoc.v:169920.3-169949.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:169880.3-169919.6" - wire width 64 $5\cia2__data_o$next[63:0]$11135 - attribute \src "libresoc.v:169950.3-169989.6" - wire width 64 $5\msr2__data_o$next[63:0]$11144 - attribute \src "libresoc.v:169880.3-169919.6" - wire width 64 $6\cia2__data_o$next[63:0]$11136 - attribute \src "libresoc.v:169950.3-169989.6" - wire width 64 $6\msr2__data_o$next[63:0]$11145 - attribute \src "libresoc.v:169872.17-169872.100" - wire $not$libresoc.v:169872$11124_Y - attribute \src "libresoc.v:169873.17-169873.103" - wire $not$libresoc.v:169873$11125_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr12__wen - attribute \src "libresoc.v:169829.7-169829.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169872$11124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:169872$11124_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169873$11125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:169873$11125_Y - end - attribute \src "libresoc.v:169829.7-169829.20" - process $proc$libresoc.v:169829$11158 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:169836.14-169836.49" - process $proc$libresoc.v:169836$11159 - assign { } { } - assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia2__data_o $1\cia2__data_o[63:0] - end - attribute \src "libresoc.v:169853.14-169853.49" - process $proc$libresoc.v:169853$11160 - assign { } { } - assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr2__data_o $1\msr2__data_o[63:0] - end - attribute \src "libresoc.v:169865.14-169865.42" - process $proc$libresoc.v:169865$11161 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "libresoc.v:169874.3-169875.25" - process $proc$libresoc.v:169874$11126 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "libresoc.v:169876.3-169877.41" - process $proc$libresoc.v:169876$11127 - assign { } { } - assign $0\msr2__data_o[63:0] \msr2__data_o$next - sync posedge \coresync_clk - update \msr2__data_o $0\msr2__data_o[63:0] - end - attribute \src "libresoc.v:169878.3-169879.41" - process $proc$libresoc.v:169878$11128 - assign { } { } - assign $0\cia2__data_o[63:0] \cia2__data_o$next - sync posedge \coresync_clk - update \cia2__data_o $0\cia2__data_o[63:0] - end - attribute \src "libresoc.v:169880.3-169919.6" - process $proc$libresoc.v:169880$11129 - assign { } { } - assign { } { } - assign { } { } - assign $0\cia2__data_o$next[63:0]$11130 $6\cia2__data_o$next[63:0]$11136 - attribute \src "libresoc.v:169881.5-169881.29" - switch \initial - attribute \src "libresoc.v:169881.9-169881.17" + attribute \src "libresoc.v:178861.9-178861.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia2__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\cia2__data_o$next[63:0]$11131 $5\cia2__data_o$next[63:0]$11135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia2__data_o$next[63:0]$11132 \nia2__data_i - case - assign $2\cia2__data_o$next[63:0]$11132 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia2__data_o$next[63:0]$11133 \msr2__data_i - case - assign $3\cia2__data_o$next[63:0]$11133 $2\cia2__data_o$next[63:0]$11132 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia2__data_o$next[63:0]$11134 \d_wr12__data_i - case - assign $4\cia2__data_o$next[63:0]$11134 $3\cia2__data_o$next[63:0]$11133 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia2__data_o$next[63:0]$11135 \reg - case - assign $5\cia2__data_o$next[63:0]$11135 $4\cia2__data_o$next[63:0]$11134 - end - case - assign $1\cia2__data_o$next[63:0]$11131 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \sv2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$11136 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\cia2__data_o$next[63:0]$11136 $1\cia2__data_o$next[63:0]$11131 - end - sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11130 - end - attribute \src "libresoc.v:169920.3-169949.6" - process $proc$libresoc.v:169920$11137 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:169921.5-169921.29" - switch \initial - attribute \src "libresoc.v:169921.9-169921.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia2__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] + assign $1\sv2__data_o$next[63:0]$11239 $6\sv2__data_o$next[63:0]$11244 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect[0:0] 1'1 + assign $2\sv2__data_o$next[63:0]$11240 \nia2__data_i case - assign $2\wr_detect[0:0] 1'0 + assign $2\sv2__data_o$next[63:0]$11240 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect[0:0] 1'1 + assign $3\sv2__data_o$next[63:0]$11241 \msr2__data_i case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] + assign $3\sv2__data_o$next[63:0]$11241 $2\sv2__data_o$next[63:0]$11240 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen + switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect[0:0] 1'1 + assign $4\sv2__data_o$next[63:0]$11242 \sv2__data_i case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "libresoc.v:169950.3-169989.6" - process $proc$libresoc.v:169950$11138 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr2__data_o$next[63:0]$11139 $6\msr2__data_o$next[63:0]$11145 - attribute \src "libresoc.v:169951.5-169951.29" - switch \initial - attribute \src "libresoc.v:169951.9-169951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr2__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\msr2__data_o$next[63:0]$11140 $5\msr2__data_o$next[63:0]$11144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr2__data_o$next[63:0]$11141 \nia2__data_i - case - assign $2\msr2__data_o$next[63:0]$11141 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr2__data_o$next[63:0]$11142 \msr2__data_i - case - assign $3\msr2__data_o$next[63:0]$11142 $2\msr2__data_o$next[63:0]$11141 + assign $4\sv2__data_o$next[63:0]$11242 $3\sv2__data_o$next[63:0]$11241 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$11143 \d_wr12__data_i + assign $5\sv2__data_o$next[63:0]$11243 \d_wr12__data_i case - assign $4\msr2__data_o$next[63:0]$11143 $3\msr2__data_o$next[63:0]$11142 + assign $5\sv2__data_o$next[63:0]$11243 $4\sv2__data_o$next[63:0]$11242 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 + switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$11144 \reg + assign $6\sv2__data_o$next[63:0]$11244 \reg case - assign $5\msr2__data_o$next[63:0]$11144 $4\msr2__data_o$next[63:0]$11143 + assign $6\sv2__data_o$next[63:0]$11244 $5\sv2__data_o$next[63:0]$11243 end case - assign $1\msr2__data_o$next[63:0]$11140 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv2__data_o$next[63:0]$11239 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$11145 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv2__data_o$next[63:0]$11245 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\msr2__data_o$next[63:0]$11145 $1\msr2__data_o$next[63:0]$11140 + assign $7\sv2__data_o$next[63:0]$11245 $1\sv2__data_o$next[63:0]$11239 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11139 + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11238 end - attribute \src "libresoc.v:169990.3-170019.6" - process $proc$libresoc.v:169990$11146 + attribute \src "libresoc.v:178906.3-178941.6" + process $proc$libresoc.v:178906$11246 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11147 $1\wr_detect$4[0:0]$11148 - attribute \src "libresoc.v:169991.5-169991.29" + assign $0\wr_detect$7[0:0]$11247 $1\wr_detect$7[0:0]$11248 + attribute \src "libresoc.v:178907.5-178907.29" switch \initial - attribute \src "libresoc.v:169991.9-169991.17" + attribute \src "libresoc.v:178907.9-178907.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr2__ren + switch \sv2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11148 $4\wr_detect$4[0:0]$11151 + assign { } { } + assign $1\wr_detect$7[0:0]$11248 $5\wr_detect$7[0:0]$11252 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11149 1'1 + assign $2\wr_detect$7[0:0]$11249 1'1 case - assign $2\wr_detect$4[0:0]$11149 1'0 + assign $2\wr_detect$7[0:0]$11249 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11150 1'1 + assign $3\wr_detect$7[0:0]$11250 1'1 case - assign $3\wr_detect$4[0:0]$11150 $2\wr_detect$4[0:0]$11149 + assign $3\wr_detect$7[0:0]$11250 $2\wr_detect$7[0:0]$11249 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11251 1'1 + case + assign $4\wr_detect$7[0:0]$11251 $3\wr_detect$7[0:0]$11250 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11151 1'1 + assign $5\wr_detect$7[0:0]$11252 1'1 case - assign $4\wr_detect$4[0:0]$11151 $3\wr_detect$4[0:0]$11150 + assign $5\wr_detect$7[0:0]$11252 $4\wr_detect$7[0:0]$11251 end case - assign $1\wr_detect$4[0:0]$11148 1'0 + assign $1\wr_detect$7[0:0]$11248 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11147 + update \wr_detect$7 $0\wr_detect$7[0:0]$11247 end - attribute \src "libresoc.v:170020.3-170046.6" - process $proc$libresoc.v:170020$11152 + attribute \src "libresoc.v:178942.3-178974.6" + process $proc$libresoc.v:178942$11253 + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11153 $4\reg$next[63:0]$11157 - attribute \src "libresoc.v:170021.5-170021.29" + assign $0\reg$next[63:0]$11254 $5\reg$next[63:0]$11259 + attribute \src "libresoc.v:178943.5-178943.29" switch \initial - attribute \src "libresoc.v:170021.9-170021.17" + attribute \src "libresoc.v:178943.9-178943.17" case 1'1 case end @@ -353279,214 +368764,224 @@ module \reg_2$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11154 \nia2__data_i + assign $1\reg$next[63:0]$11255 \nia2__data_i case - assign $1\reg$next[63:0]$11154 \reg + assign $1\reg$next[63:0]$11255 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11155 \msr2__data_i + assign $2\reg$next[63:0]$11256 \msr2__data_i case - assign $2\reg$next[63:0]$11155 $1\reg$next[63:0]$11154 + assign $2\reg$next[63:0]$11256 $1\reg$next[63:0]$11255 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11257 \sv2__data_i + case + assign $3\reg$next[63:0]$11257 $2\reg$next[63:0]$11256 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11156 \d_wr12__data_i + assign $4\reg$next[63:0]$11258 \d_wr12__data_i case - assign $3\reg$next[63:0]$11156 $2\reg$next[63:0]$11155 + assign $4\reg$next[63:0]$11258 $3\reg$next[63:0]$11257 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11157 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11259 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\reg$next[63:0]$11157 $3\reg$next[63:0]$11156 + assign $5\reg$next[63:0]$11259 $4\reg$next[63:0]$11258 end sync always - update \reg$next $0\reg$next[63:0]$11153 + update \reg$next $0\reg$next[63:0]$11254 end - connect \$1 $not$libresoc.v:169872$11124_Y - connect \$3 $not$libresoc.v:169873$11125_Y + connect \$1 $not$libresoc.v:178685$11204_Y + connect \$3 $not$libresoc.v:178686$11205_Y + connect \$6 $not$libresoc.v:178687$11206_Y end -attribute \src "libresoc.v:170051.1-170522.10" +attribute \src "libresoc.v:178979.1-179450.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:170052.7-170052.20" + attribute \src "libresoc.v:178980.7-178980.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170452.3-170491.6" - wire width 4 $0\r23__data_o$next[3:0]$11231 - attribute \src "libresoc.v:170135.3-170136.39" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $0\r23__data_o$next[3:0]$11334 + attribute \src "libresoc.v:179063.3-179064.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:170382.3-170421.6" - wire width 4 $0\r3__data_o$next[3:0]$11217 - attribute \src "libresoc.v:170137.3-170138.37" + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $0\r3__data_o$next[3:0]$11320 + attribute \src "libresoc.v:179065.3-179066.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:170215.3-170241.6" - wire width 4 $0\reg$next[3:0]$11183 - attribute \src "libresoc.v:170133.3-170134.25" + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $0\reg$next[3:0]$11286 + attribute \src "libresoc.v:179061.3-179062.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:170145.3-170184.6" - wire width 4 $0\src13__data_o$next[3:0]$11174 - attribute \src "libresoc.v:170143.3-170144.43" + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $0\src13__data_o$next[3:0]$11277 + attribute \src "libresoc.v:179071.3-179072.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:170242.3-170281.6" - wire width 4 $0\src23__data_o$next[3:0]$11189 - attribute \src "libresoc.v:170141.3-170142.43" + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $0\src23__data_o$next[3:0]$11292 + attribute \src "libresoc.v:179069.3-179070.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:170312.3-170351.6" - wire width 4 $0\src33__data_o$next[3:0]$11203 - attribute \src "libresoc.v:170139.3-170140.43" + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $0\src33__data_o$next[3:0]$11306 + attribute \src "libresoc.v:179067.3-179068.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:170422.3-170451.6" - wire $0\wr_detect$10[0:0]$11225 - attribute \src "libresoc.v:170492.3-170521.6" - wire $0\wr_detect$13[0:0]$11239 - attribute \src "libresoc.v:170282.3-170311.6" - wire $0\wr_detect$4[0:0]$11197 - attribute \src "libresoc.v:170352.3-170381.6" - wire $0\wr_detect$7[0:0]$11211 - attribute \src "libresoc.v:170185.3-170214.6" + attribute \src "libresoc.v:179350.3-179379.6" + wire $0\wr_detect$10[0:0]$11328 + attribute \src "libresoc.v:179420.3-179449.6" + wire $0\wr_detect$13[0:0]$11342 + attribute \src "libresoc.v:179210.3-179239.6" + wire $0\wr_detect$4[0:0]$11300 + attribute \src "libresoc.v:179280.3-179309.6" + wire $0\wr_detect$7[0:0]$11314 + attribute \src "libresoc.v:179113.3-179142.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:170452.3-170491.6" - wire width 4 $1\r23__data_o$next[3:0]$11232 - attribute \src "libresoc.v:170077.13-170077.31" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $1\r23__data_o$next[3:0]$11335 + attribute \src "libresoc.v:179005.13-179005.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:170382.3-170421.6" - wire width 4 $1\r3__data_o$next[3:0]$11218 - attribute \src "libresoc.v:170084.13-170084.30" + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $1\r3__data_o$next[3:0]$11321 + attribute \src "libresoc.v:179012.13-179012.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:170215.3-170241.6" - wire width 4 $1\reg$next[3:0]$11184 - attribute \src "libresoc.v:170090.13-170090.25" + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $1\reg$next[3:0]$11287 + attribute \src "libresoc.v:179018.13-179018.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:170145.3-170184.6" - wire width 4 $1\src13__data_o$next[3:0]$11175 - attribute \src "libresoc.v:170095.13-170095.33" + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $1\src13__data_o$next[3:0]$11278 + attribute \src "libresoc.v:179023.13-179023.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:170242.3-170281.6" - wire width 4 $1\src23__data_o$next[3:0]$11190 - attribute \src "libresoc.v:170102.13-170102.33" + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $1\src23__data_o$next[3:0]$11293 + attribute \src "libresoc.v:179030.13-179030.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:170312.3-170351.6" - wire width 4 $1\src33__data_o$next[3:0]$11204 - attribute \src "libresoc.v:170109.13-170109.33" + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $1\src33__data_o$next[3:0]$11307 + attribute \src "libresoc.v:179037.13-179037.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:170422.3-170451.6" - wire $1\wr_detect$10[0:0]$11226 - attribute \src "libresoc.v:170492.3-170521.6" - wire $1\wr_detect$13[0:0]$11240 - attribute \src "libresoc.v:170282.3-170311.6" - wire $1\wr_detect$4[0:0]$11198 - attribute \src "libresoc.v:170352.3-170381.6" - wire $1\wr_detect$7[0:0]$11212 - attribute \src "libresoc.v:170185.3-170214.6" + attribute \src "libresoc.v:179350.3-179379.6" + wire $1\wr_detect$10[0:0]$11329 + attribute \src "libresoc.v:179420.3-179449.6" + wire $1\wr_detect$13[0:0]$11343 + attribute \src "libresoc.v:179210.3-179239.6" + wire $1\wr_detect$4[0:0]$11301 + attribute \src "libresoc.v:179280.3-179309.6" + wire $1\wr_detect$7[0:0]$11315 + attribute \src "libresoc.v:179113.3-179142.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:170452.3-170491.6" - wire width 4 $2\r23__data_o$next[3:0]$11233 - attribute \src "libresoc.v:170382.3-170421.6" - wire width 4 $2\r3__data_o$next[3:0]$11219 - attribute \src "libresoc.v:170215.3-170241.6" - wire width 4 $2\reg$next[3:0]$11185 - attribute \src "libresoc.v:170145.3-170184.6" - wire width 4 $2\src13__data_o$next[3:0]$11176 - attribute \src "libresoc.v:170242.3-170281.6" - wire width 4 $2\src23__data_o$next[3:0]$11191 - attribute \src "libresoc.v:170312.3-170351.6" - wire width 4 $2\src33__data_o$next[3:0]$11205 - attribute \src "libresoc.v:170422.3-170451.6" - wire $2\wr_detect$10[0:0]$11227 - attribute \src "libresoc.v:170492.3-170521.6" - wire $2\wr_detect$13[0:0]$11241 - attribute \src "libresoc.v:170282.3-170311.6" - wire $2\wr_detect$4[0:0]$11199 - attribute \src "libresoc.v:170352.3-170381.6" - wire $2\wr_detect$7[0:0]$11213 - attribute \src "libresoc.v:170185.3-170214.6" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $2\r23__data_o$next[3:0]$11336 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $2\r3__data_o$next[3:0]$11322 + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $2\reg$next[3:0]$11288 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $2\src13__data_o$next[3:0]$11279 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $2\src23__data_o$next[3:0]$11294 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $2\src33__data_o$next[3:0]$11308 + attribute \src "libresoc.v:179350.3-179379.6" + wire $2\wr_detect$10[0:0]$11330 + attribute \src "libresoc.v:179420.3-179449.6" + wire $2\wr_detect$13[0:0]$11344 + attribute \src "libresoc.v:179210.3-179239.6" + wire $2\wr_detect$4[0:0]$11302 + attribute \src "libresoc.v:179280.3-179309.6" + wire $2\wr_detect$7[0:0]$11316 + attribute \src "libresoc.v:179113.3-179142.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:170452.3-170491.6" - wire width 4 $3\r23__data_o$next[3:0]$11234 - attribute \src "libresoc.v:170382.3-170421.6" - wire width 4 $3\r3__data_o$next[3:0]$11220 - attribute \src "libresoc.v:170215.3-170241.6" - wire width 4 $3\reg$next[3:0]$11186 - attribute \src "libresoc.v:170145.3-170184.6" - wire width 4 $3\src13__data_o$next[3:0]$11177 - attribute \src "libresoc.v:170242.3-170281.6" - wire width 4 $3\src23__data_o$next[3:0]$11192 - attribute \src "libresoc.v:170312.3-170351.6" - wire width 4 $3\src33__data_o$next[3:0]$11206 - attribute \src "libresoc.v:170422.3-170451.6" - wire $3\wr_detect$10[0:0]$11228 - attribute \src "libresoc.v:170492.3-170521.6" - wire $3\wr_detect$13[0:0]$11242 - attribute \src "libresoc.v:170282.3-170311.6" - wire $3\wr_detect$4[0:0]$11200 - attribute \src "libresoc.v:170352.3-170381.6" - wire $3\wr_detect$7[0:0]$11214 - attribute \src "libresoc.v:170185.3-170214.6" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $3\r23__data_o$next[3:0]$11337 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $3\r3__data_o$next[3:0]$11323 + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $3\reg$next[3:0]$11289 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $3\src13__data_o$next[3:0]$11280 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $3\src23__data_o$next[3:0]$11295 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $3\src33__data_o$next[3:0]$11309 + attribute \src "libresoc.v:179350.3-179379.6" + wire $3\wr_detect$10[0:0]$11331 + attribute \src "libresoc.v:179420.3-179449.6" + wire $3\wr_detect$13[0:0]$11345 + attribute \src "libresoc.v:179210.3-179239.6" + wire $3\wr_detect$4[0:0]$11303 + attribute \src "libresoc.v:179280.3-179309.6" + wire $3\wr_detect$7[0:0]$11317 + attribute \src "libresoc.v:179113.3-179142.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:170452.3-170491.6" - wire width 4 $4\r23__data_o$next[3:0]$11235 - attribute \src "libresoc.v:170382.3-170421.6" - wire width 4 $4\r3__data_o$next[3:0]$11221 - attribute \src "libresoc.v:170215.3-170241.6" - wire width 4 $4\reg$next[3:0]$11187 - attribute \src "libresoc.v:170145.3-170184.6" - wire width 4 $4\src13__data_o$next[3:0]$11178 - attribute \src "libresoc.v:170242.3-170281.6" - wire width 4 $4\src23__data_o$next[3:0]$11193 - attribute \src "libresoc.v:170312.3-170351.6" - wire width 4 $4\src33__data_o$next[3:0]$11207 - attribute \src "libresoc.v:170422.3-170451.6" - wire $4\wr_detect$10[0:0]$11229 - attribute \src "libresoc.v:170492.3-170521.6" - wire $4\wr_detect$13[0:0]$11243 - attribute \src "libresoc.v:170282.3-170311.6" - wire $4\wr_detect$4[0:0]$11201 - attribute \src "libresoc.v:170352.3-170381.6" - wire $4\wr_detect$7[0:0]$11215 - attribute \src "libresoc.v:170185.3-170214.6" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $4\r23__data_o$next[3:0]$11338 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $4\r3__data_o$next[3:0]$11324 + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $4\reg$next[3:0]$11290 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $4\src13__data_o$next[3:0]$11281 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $4\src23__data_o$next[3:0]$11296 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $4\src33__data_o$next[3:0]$11310 + attribute \src "libresoc.v:179350.3-179379.6" + wire $4\wr_detect$10[0:0]$11332 + attribute \src "libresoc.v:179420.3-179449.6" + wire $4\wr_detect$13[0:0]$11346 + attribute \src "libresoc.v:179210.3-179239.6" + wire $4\wr_detect$4[0:0]$11304 + attribute \src "libresoc.v:179280.3-179309.6" + wire $4\wr_detect$7[0:0]$11318 + attribute \src "libresoc.v:179113.3-179142.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:170452.3-170491.6" - wire width 4 $5\r23__data_o$next[3:0]$11236 - attribute \src "libresoc.v:170382.3-170421.6" - wire width 4 $5\r3__data_o$next[3:0]$11222 - attribute \src "libresoc.v:170145.3-170184.6" - wire width 4 $5\src13__data_o$next[3:0]$11179 - attribute \src "libresoc.v:170242.3-170281.6" - wire width 4 $5\src23__data_o$next[3:0]$11194 - attribute \src "libresoc.v:170312.3-170351.6" - wire width 4 $5\src33__data_o$next[3:0]$11208 - attribute \src "libresoc.v:170452.3-170491.6" - wire width 4 $6\r23__data_o$next[3:0]$11237 - attribute \src "libresoc.v:170382.3-170421.6" - wire width 4 $6\r3__data_o$next[3:0]$11223 - attribute \src "libresoc.v:170145.3-170184.6" - wire width 4 $6\src13__data_o$next[3:0]$11180 - attribute \src "libresoc.v:170242.3-170281.6" - wire width 4 $6\src23__data_o$next[3:0]$11195 - attribute \src "libresoc.v:170312.3-170351.6" - wire width 4 $6\src33__data_o$next[3:0]$11209 - attribute \src "libresoc.v:170128.17-170128.104" - wire $not$libresoc.v:170128$11162_Y - attribute \src "libresoc.v:170129.18-170129.105" - wire $not$libresoc.v:170129$11163_Y - attribute \src "libresoc.v:170130.17-170130.100" - wire $not$libresoc.v:170130$11164_Y - attribute \src "libresoc.v:170131.17-170131.103" - wire $not$libresoc.v:170131$11165_Y - attribute \src "libresoc.v:170132.17-170132.103" - wire $not$libresoc.v:170132$11166_Y + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $5\r23__data_o$next[3:0]$11339 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $5\r3__data_o$next[3:0]$11325 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $5\src13__data_o$next[3:0]$11282 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $5\src23__data_o$next[3:0]$11297 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $5\src33__data_o$next[3:0]$11311 + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $6\r23__data_o$next[3:0]$11340 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $6\r3__data_o$next[3:0]$11326 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $6\src13__data_o$next[3:0]$11283 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $6\src23__data_o$next[3:0]$11298 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $6\src33__data_o$next[3:0]$11312 + attribute \src "libresoc.v:179056.17-179056.104" + wire $not$libresoc.v:179056$11265_Y + attribute \src "libresoc.v:179057.18-179057.105" + wire $not$libresoc.v:179057$11266_Y + attribute \src "libresoc.v:179058.17-179058.100" + wire $not$libresoc.v:179058$11267_Y + attribute \src "libresoc.v:179059.17-179059.103" + wire $not$libresoc.v:179059$11268_Y + attribute \src "libresoc.v:179060.17-179060.103" + wire $not$libresoc.v:179060$11269_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -353497,57 +368992,57 @@ module \reg_3 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest23__wen - attribute \src "libresoc.v:170052.7-170052.15" + attribute \src "libresoc.v:178980.7-178980.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r23__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r3__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src13__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src23__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src33__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src33__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src33__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w3__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -353560,152 +369055,152 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170128$11162 + cell $not $not$libresoc.v:179056$11265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:170128$11162_Y + connect \Y $not$libresoc.v:179056$11265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170129$11163 + cell $not $not$libresoc.v:179057$11266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:170129$11163_Y + connect \Y $not$libresoc.v:179057$11266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170130$11164 + cell $not $not$libresoc.v:179058$11267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:170130$11164_Y + connect \Y $not$libresoc.v:179058$11267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170131$11165 + cell $not $not$libresoc.v:179059$11268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:170131$11165_Y + connect \Y $not$libresoc.v:179059$11268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170132$11166 + cell $not $not$libresoc.v:179060$11269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:170132$11166_Y + connect \Y $not$libresoc.v:179060$11269_Y end - attribute \src "libresoc.v:170052.7-170052.20" - process $proc$libresoc.v:170052$11244 + attribute \src "libresoc.v:178980.7-178980.20" + process $proc$libresoc.v:178980$11347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170077.13-170077.31" - process $proc$libresoc.v:170077$11245 + attribute \src "libresoc.v:179005.13-179005.31" + process $proc$libresoc.v:179005$11348 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:170084.13-170084.30" - process $proc$libresoc.v:170084$11246 + attribute \src "libresoc.v:179012.13-179012.30" + process $proc$libresoc.v:179012$11349 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:170090.13-170090.25" - process $proc$libresoc.v:170090$11247 + attribute \src "libresoc.v:179018.13-179018.25" + process $proc$libresoc.v:179018$11350 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:170095.13-170095.33" - process $proc$libresoc.v:170095$11248 + attribute \src "libresoc.v:179023.13-179023.33" + process $proc$libresoc.v:179023$11351 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:170102.13-170102.33" - process $proc$libresoc.v:170102$11249 + attribute \src "libresoc.v:179030.13-179030.33" + process $proc$libresoc.v:179030$11352 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:170109.13-170109.33" - process $proc$libresoc.v:170109$11250 + attribute \src "libresoc.v:179037.13-179037.33" + process $proc$libresoc.v:179037$11353 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:170133.3-170134.25" - process $proc$libresoc.v:170133$11167 + attribute \src "libresoc.v:179061.3-179062.25" + process $proc$libresoc.v:179061$11270 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:170135.3-170136.39" - process $proc$libresoc.v:170135$11168 + attribute \src "libresoc.v:179063.3-179064.39" + process $proc$libresoc.v:179063$11271 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:170137.3-170138.37" - process $proc$libresoc.v:170137$11169 + attribute \src "libresoc.v:179065.3-179066.37" + process $proc$libresoc.v:179065$11272 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:170139.3-170140.43" - process $proc$libresoc.v:170139$11170 + attribute \src "libresoc.v:179067.3-179068.43" + process $proc$libresoc.v:179067$11273 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:170141.3-170142.43" - process $proc$libresoc.v:170141$11171 + attribute \src "libresoc.v:179069.3-179070.43" + process $proc$libresoc.v:179069$11274 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:170143.3-170144.43" - process $proc$libresoc.v:170143$11172 + attribute \src "libresoc.v:179071.3-179072.43" + process $proc$libresoc.v:179071$11275 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:170145.3-170184.6" - process $proc$libresoc.v:170145$11173 + attribute \src "libresoc.v:179073.3-179112.6" + process $proc$libresoc.v:179073$11276 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$11174 $6\src13__data_o$next[3:0]$11180 - attribute \src "libresoc.v:170146.5-170146.29" + assign $0\src13__data_o$next[3:0]$11277 $6\src13__data_o$next[3:0]$11283 + attribute \src "libresoc.v:179074.5-179074.29" switch \initial - attribute \src "libresoc.v:170146.9-170146.17" + attribute \src "libresoc.v:179074.9-179074.17" case 1'1 case end @@ -353717,66 +369212,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$11175 $5\src13__data_o$next[3:0]$11179 + assign $1\src13__data_o$next[3:0]$11278 $5\src13__data_o$next[3:0]$11282 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$11176 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11279 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$11176 4'0000 + assign $2\src13__data_o$next[3:0]$11279 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$11177 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11280 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$11177 $2\src13__data_o$next[3:0]$11176 + assign $3\src13__data_o$next[3:0]$11280 $2\src13__data_o$next[3:0]$11279 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$11178 \w3__data_i + assign $4\src13__data_o$next[3:0]$11281 \w3__data_i case - assign $4\src13__data_o$next[3:0]$11178 $3\src13__data_o$next[3:0]$11177 + assign $4\src13__data_o$next[3:0]$11281 $3\src13__data_o$next[3:0]$11280 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$11179 \reg + assign $5\src13__data_o$next[3:0]$11282 \reg case - assign $5\src13__data_o$next[3:0]$11179 $4\src13__data_o$next[3:0]$11178 + assign $5\src13__data_o$next[3:0]$11282 $4\src13__data_o$next[3:0]$11281 end case - assign $1\src13__data_o$next[3:0]$11175 4'0000 + assign $1\src13__data_o$next[3:0]$11278 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$11180 4'0000 + assign $6\src13__data_o$next[3:0]$11283 4'0000 case - assign $6\src13__data_o$next[3:0]$11180 $1\src13__data_o$next[3:0]$11175 + assign $6\src13__data_o$next[3:0]$11283 $1\src13__data_o$next[3:0]$11278 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11174 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11277 end - attribute \src "libresoc.v:170185.3-170214.6" - process $proc$libresoc.v:170185$11181 + attribute \src "libresoc.v:179113.3-179142.6" + process $proc$libresoc.v:179113$11284 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:170186.5-170186.29" + attribute \src "libresoc.v:179114.5-179114.29" switch \initial - attribute \src "libresoc.v:170186.9-170186.17" + attribute \src "libresoc.v:179114.9-179114.17" case 1'1 case end @@ -353822,17 +369317,17 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:170215.3-170241.6" - process $proc$libresoc.v:170215$11182 + attribute \src "libresoc.v:179143.3-179169.6" + process $proc$libresoc.v:179143$11285 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11183 $4\reg$next[3:0]$11187 - attribute \src "libresoc.v:170216.5-170216.29" + assign $0\reg$next[3:0]$11286 $4\reg$next[3:0]$11290 + attribute \src "libresoc.v:179144.5-179144.29" switch \initial - attribute \src "libresoc.v:170216.9-170216.17" + attribute \src "libresoc.v:179144.9-179144.17" case 1'1 case end @@ -353841,49 +369336,49 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11184 \dest13__data_i + assign $1\reg$next[3:0]$11287 \dest13__data_i case - assign $1\reg$next[3:0]$11184 \reg + assign $1\reg$next[3:0]$11287 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11185 \dest23__data_i + assign $2\reg$next[3:0]$11288 \dest23__data_i case - assign $2\reg$next[3:0]$11185 $1\reg$next[3:0]$11184 + assign $2\reg$next[3:0]$11288 $1\reg$next[3:0]$11287 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11186 \w3__data_i + assign $3\reg$next[3:0]$11289 \w3__data_i case - assign $3\reg$next[3:0]$11186 $2\reg$next[3:0]$11185 + assign $3\reg$next[3:0]$11289 $2\reg$next[3:0]$11288 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11187 4'0000 + assign $4\reg$next[3:0]$11290 4'0000 case - assign $4\reg$next[3:0]$11187 $3\reg$next[3:0]$11186 + assign $4\reg$next[3:0]$11290 $3\reg$next[3:0]$11289 end sync always - update \reg$next $0\reg$next[3:0]$11183 + update \reg$next $0\reg$next[3:0]$11286 end - attribute \src "libresoc.v:170242.3-170281.6" - process $proc$libresoc.v:170242$11188 + attribute \src "libresoc.v:179170.3-179209.6" + process $proc$libresoc.v:179170$11291 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$11189 $6\src23__data_o$next[3:0]$11195 - attribute \src "libresoc.v:170243.5-170243.29" + assign $0\src23__data_o$next[3:0]$11292 $6\src23__data_o$next[3:0]$11298 + attribute \src "libresoc.v:179171.5-179171.29" switch \initial - attribute \src "libresoc.v:170243.9-170243.17" + attribute \src "libresoc.v:179171.9-179171.17" case 1'1 case end @@ -353895,66 +369390,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$11190 $5\src23__data_o$next[3:0]$11194 + assign $1\src23__data_o$next[3:0]$11293 $5\src23__data_o$next[3:0]$11297 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$11191 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11294 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$11191 4'0000 + assign $2\src23__data_o$next[3:0]$11294 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$11192 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11295 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$11192 $2\src23__data_o$next[3:0]$11191 + assign $3\src23__data_o$next[3:0]$11295 $2\src23__data_o$next[3:0]$11294 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$11193 \w3__data_i + assign $4\src23__data_o$next[3:0]$11296 \w3__data_i case - assign $4\src23__data_o$next[3:0]$11193 $3\src23__data_o$next[3:0]$11192 + assign $4\src23__data_o$next[3:0]$11296 $3\src23__data_o$next[3:0]$11295 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$11194 \reg + assign $5\src23__data_o$next[3:0]$11297 \reg case - assign $5\src23__data_o$next[3:0]$11194 $4\src23__data_o$next[3:0]$11193 + assign $5\src23__data_o$next[3:0]$11297 $4\src23__data_o$next[3:0]$11296 end case - assign $1\src23__data_o$next[3:0]$11190 4'0000 + assign $1\src23__data_o$next[3:0]$11293 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$11195 4'0000 + assign $6\src23__data_o$next[3:0]$11298 4'0000 case - assign $6\src23__data_o$next[3:0]$11195 $1\src23__data_o$next[3:0]$11190 + assign $6\src23__data_o$next[3:0]$11298 $1\src23__data_o$next[3:0]$11293 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11189 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11292 end - attribute \src "libresoc.v:170282.3-170311.6" - process $proc$libresoc.v:170282$11196 + attribute \src "libresoc.v:179210.3-179239.6" + process $proc$libresoc.v:179210$11299 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11197 $1\wr_detect$4[0:0]$11198 - attribute \src "libresoc.v:170283.5-170283.29" + assign $0\wr_detect$4[0:0]$11300 $1\wr_detect$4[0:0]$11301 + attribute \src "libresoc.v:179211.5-179211.29" switch \initial - attribute \src "libresoc.v:170283.9-170283.17" + attribute \src "libresoc.v:179211.9-179211.17" case 1'1 case end @@ -353966,49 +369461,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11198 $4\wr_detect$4[0:0]$11201 + assign $1\wr_detect$4[0:0]$11301 $4\wr_detect$4[0:0]$11304 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11199 1'1 + assign $2\wr_detect$4[0:0]$11302 1'1 case - assign $2\wr_detect$4[0:0]$11199 1'0 + assign $2\wr_detect$4[0:0]$11302 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11200 1'1 + assign $3\wr_detect$4[0:0]$11303 1'1 case - assign $3\wr_detect$4[0:0]$11200 $2\wr_detect$4[0:0]$11199 + assign $3\wr_detect$4[0:0]$11303 $2\wr_detect$4[0:0]$11302 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11201 1'1 + assign $4\wr_detect$4[0:0]$11304 1'1 case - assign $4\wr_detect$4[0:0]$11201 $3\wr_detect$4[0:0]$11200 + assign $4\wr_detect$4[0:0]$11304 $3\wr_detect$4[0:0]$11303 end case - assign $1\wr_detect$4[0:0]$11198 1'0 + assign $1\wr_detect$4[0:0]$11301 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11197 + update \wr_detect$4 $0\wr_detect$4[0:0]$11300 end - attribute \src "libresoc.v:170312.3-170351.6" - process $proc$libresoc.v:170312$11202 + attribute \src "libresoc.v:179240.3-179279.6" + process $proc$libresoc.v:179240$11305 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11203 $6\src33__data_o$next[3:0]$11209 - attribute \src "libresoc.v:170313.5-170313.29" + assign $0\src33__data_o$next[3:0]$11306 $6\src33__data_o$next[3:0]$11312 + attribute \src "libresoc.v:179241.5-179241.29" switch \initial - attribute \src "libresoc.v:170313.9-170313.17" + attribute \src "libresoc.v:179241.9-179241.17" case 1'1 case end @@ -354020,66 +369515,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$11204 $5\src33__data_o$next[3:0]$11208 + assign $1\src33__data_o$next[3:0]$11307 $5\src33__data_o$next[3:0]$11311 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$11205 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11308 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$11205 4'0000 + assign $2\src33__data_o$next[3:0]$11308 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$11206 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11309 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$11206 $2\src33__data_o$next[3:0]$11205 + assign $3\src33__data_o$next[3:0]$11309 $2\src33__data_o$next[3:0]$11308 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$11207 \w3__data_i + assign $4\src33__data_o$next[3:0]$11310 \w3__data_i case - assign $4\src33__data_o$next[3:0]$11207 $3\src33__data_o$next[3:0]$11206 + assign $4\src33__data_o$next[3:0]$11310 $3\src33__data_o$next[3:0]$11309 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$11208 \reg + assign $5\src33__data_o$next[3:0]$11311 \reg case - assign $5\src33__data_o$next[3:0]$11208 $4\src33__data_o$next[3:0]$11207 + assign $5\src33__data_o$next[3:0]$11311 $4\src33__data_o$next[3:0]$11310 end case - assign $1\src33__data_o$next[3:0]$11204 4'0000 + assign $1\src33__data_o$next[3:0]$11307 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$11209 4'0000 + assign $6\src33__data_o$next[3:0]$11312 4'0000 case - assign $6\src33__data_o$next[3:0]$11209 $1\src33__data_o$next[3:0]$11204 + assign $6\src33__data_o$next[3:0]$11312 $1\src33__data_o$next[3:0]$11307 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11203 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11306 end - attribute \src "libresoc.v:170352.3-170381.6" - process $proc$libresoc.v:170352$11210 + attribute \src "libresoc.v:179280.3-179309.6" + process $proc$libresoc.v:179280$11313 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11211 $1\wr_detect$7[0:0]$11212 - attribute \src "libresoc.v:170353.5-170353.29" + assign $0\wr_detect$7[0:0]$11314 $1\wr_detect$7[0:0]$11315 + attribute \src "libresoc.v:179281.5-179281.29" switch \initial - attribute \src "libresoc.v:170353.9-170353.17" + attribute \src "libresoc.v:179281.9-179281.17" case 1'1 case end @@ -354091,49 +369586,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11212 $4\wr_detect$7[0:0]$11215 + assign $1\wr_detect$7[0:0]$11315 $4\wr_detect$7[0:0]$11318 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11213 1'1 + assign $2\wr_detect$7[0:0]$11316 1'1 case - assign $2\wr_detect$7[0:0]$11213 1'0 + assign $2\wr_detect$7[0:0]$11316 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11214 1'1 + assign $3\wr_detect$7[0:0]$11317 1'1 case - assign $3\wr_detect$7[0:0]$11214 $2\wr_detect$7[0:0]$11213 + assign $3\wr_detect$7[0:0]$11317 $2\wr_detect$7[0:0]$11316 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11215 1'1 + assign $4\wr_detect$7[0:0]$11318 1'1 case - assign $4\wr_detect$7[0:0]$11215 $3\wr_detect$7[0:0]$11214 + assign $4\wr_detect$7[0:0]$11318 $3\wr_detect$7[0:0]$11317 end case - assign $1\wr_detect$7[0:0]$11212 1'0 + assign $1\wr_detect$7[0:0]$11315 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11211 + update \wr_detect$7 $0\wr_detect$7[0:0]$11314 end - attribute \src "libresoc.v:170382.3-170421.6" - process $proc$libresoc.v:170382$11216 + attribute \src "libresoc.v:179310.3-179349.6" + process $proc$libresoc.v:179310$11319 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$11217 $6\r3__data_o$next[3:0]$11223 - attribute \src "libresoc.v:170383.5-170383.29" + assign $0\r3__data_o$next[3:0]$11320 $6\r3__data_o$next[3:0]$11326 + attribute \src "libresoc.v:179311.5-179311.29" switch \initial - attribute \src "libresoc.v:170383.9-170383.17" + attribute \src "libresoc.v:179311.9-179311.17" case 1'1 case end @@ -354145,66 +369640,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$11218 $5\r3__data_o$next[3:0]$11222 + assign $1\r3__data_o$next[3:0]$11321 $5\r3__data_o$next[3:0]$11325 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$11219 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11322 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$11219 4'0000 + assign $2\r3__data_o$next[3:0]$11322 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$11220 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11323 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$11220 $2\r3__data_o$next[3:0]$11219 + assign $3\r3__data_o$next[3:0]$11323 $2\r3__data_o$next[3:0]$11322 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$11221 \w3__data_i + assign $4\r3__data_o$next[3:0]$11324 \w3__data_i case - assign $4\r3__data_o$next[3:0]$11221 $3\r3__data_o$next[3:0]$11220 + assign $4\r3__data_o$next[3:0]$11324 $3\r3__data_o$next[3:0]$11323 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$11222 \reg + assign $5\r3__data_o$next[3:0]$11325 \reg case - assign $5\r3__data_o$next[3:0]$11222 $4\r3__data_o$next[3:0]$11221 + assign $5\r3__data_o$next[3:0]$11325 $4\r3__data_o$next[3:0]$11324 end case - assign $1\r3__data_o$next[3:0]$11218 4'0000 + assign $1\r3__data_o$next[3:0]$11321 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$11223 4'0000 + assign $6\r3__data_o$next[3:0]$11326 4'0000 case - assign $6\r3__data_o$next[3:0]$11223 $1\r3__data_o$next[3:0]$11218 + assign $6\r3__data_o$next[3:0]$11326 $1\r3__data_o$next[3:0]$11321 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11217 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11320 end - attribute \src "libresoc.v:170422.3-170451.6" - process $proc$libresoc.v:170422$11224 + attribute \src "libresoc.v:179350.3-179379.6" + process $proc$libresoc.v:179350$11327 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11225 $1\wr_detect$10[0:0]$11226 - attribute \src "libresoc.v:170423.5-170423.29" + assign $0\wr_detect$10[0:0]$11328 $1\wr_detect$10[0:0]$11329 + attribute \src "libresoc.v:179351.5-179351.29" switch \initial - attribute \src "libresoc.v:170423.9-170423.17" + attribute \src "libresoc.v:179351.9-179351.17" case 1'1 case end @@ -354216,120 +369711,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11226 $4\wr_detect$10[0:0]$11229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$11227 1'1 - case - assign $2\wr_detect$10[0:0]$11227 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$11228 1'1 - case - assign $3\wr_detect$10[0:0]$11228 $2\wr_detect$10[0:0]$11227 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$11229 1'1 - case - assign $4\wr_detect$10[0:0]$11229 $3\wr_detect$10[0:0]$11228 - end - case - assign $1\wr_detect$10[0:0]$11226 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11225 - end - attribute \src "libresoc.v:170452.3-170491.6" - process $proc$libresoc.v:170452$11230 - assign { } { } - assign { } { } - assign { } { } - assign $0\r23__data_o$next[3:0]$11231 $6\r23__data_o$next[3:0]$11237 - attribute \src "libresoc.v:170453.5-170453.29" - switch \initial - attribute \src "libresoc.v:170453.9-170453.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r23__data_o$next[3:0]$11232 $5\r23__data_o$next[3:0]$11236 + assign $1\wr_detect$10[0:0]$11329 $4\wr_detect$10[0:0]$11332 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r23__data_o$next[3:0]$11233 \dest13__data_i + assign $2\wr_detect$10[0:0]$11330 1'1 case - assign $2\r23__data_o$next[3:0]$11233 4'0000 + assign $2\wr_detect$10[0:0]$11330 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r23__data_o$next[3:0]$11234 \dest23__data_i + assign $3\wr_detect$10[0:0]$11331 1'1 case - assign $3\r23__data_o$next[3:0]$11234 $2\r23__data_o$next[3:0]$11233 + assign $3\wr_detect$10[0:0]$11331 $2\wr_detect$10[0:0]$11330 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r23__data_o$next[3:0]$11235 \w3__data_i + assign $4\wr_detect$10[0:0]$11332 1'1 case - assign $4\r23__data_o$next[3:0]$11235 $3\r23__data_o$next[3:0]$11234 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r23__data_o$next[3:0]$11236 \reg - case - assign $5\r23__data_o$next[3:0]$11236 $4\r23__data_o$next[3:0]$11235 + assign $4\wr_detect$10[0:0]$11332 $3\wr_detect$10[0:0]$11331 end case - assign $1\r23__data_o$next[3:0]$11232 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r23__data_o$next[3:0]$11237 4'0000 - case - assign $6\r23__data_o$next[3:0]$11237 $1\r23__data_o$next[3:0]$11232 + assign $1\wr_detect$10[0:0]$11329 1'0 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11231 + update \wr_detect$10 $0\wr_detect$10[0:0]$11328 end - attribute \src "libresoc.v:170492.3-170521.6" - process $proc$libresoc.v:170492$11238 + attribute \src "libresoc.v:179380.3-179419.6" + process $proc$libresoc.v:179380$11333 + assign { } { } assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11239 $1\wr_detect$13[0:0]$11240 - attribute \src "libresoc.v:170493.5-170493.29" + assign $0\r23__data_o$next[3:0]$11334 $6\r23__data_o$next[3:0]$11340 + attribute \src "libresoc.v:179381.5-179381.29" switch \initial - attribute \src "libresoc.v:170493.9-170493.17" + attribute \src "libresoc.v:179381.9-179381.17" case 1'1 case end @@ -354341,715 +369765,288 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11240 $4\wr_detect$13[0:0]$11243 + assign $1\r23__data_o$next[3:0]$11335 $5\r23__data_o$next[3:0]$11339 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11241 1'1 + assign $2\r23__data_o$next[3:0]$11336 \dest13__data_i case - assign $2\wr_detect$13[0:0]$11241 1'0 + assign $2\r23__data_o$next[3:0]$11336 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11242 1'1 + assign $3\r23__data_o$next[3:0]$11337 \dest23__data_i case - assign $3\wr_detect$13[0:0]$11242 $2\wr_detect$13[0:0]$11241 + assign $3\r23__data_o$next[3:0]$11337 $2\r23__data_o$next[3:0]$11336 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11243 1'1 - case - assign $4\wr_detect$13[0:0]$11243 $3\wr_detect$13[0:0]$11242 - end - case - assign $1\wr_detect$13[0:0]$11240 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11239 - end - connect \$9 $not$libresoc.v:170128$11162_Y - connect \$12 $not$libresoc.v:170129$11163_Y - connect \$1 $not$libresoc.v:170130$11164_Y - connect \$3 $not$libresoc.v:170131$11165_Y - connect \$6 $not$libresoc.v:170132$11166_Y -end -attribute \src "libresoc.v:170526.1-170745.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_3" -attribute \generator "nMigen" -module \reg_3$138 - attribute \src "libresoc.v:170578.3-170617.6" - wire width 64 $0\cia3__data_o$next[63:0]$11257 - attribute \src "libresoc.v:170576.3-170577.41" - wire width 64 $0\cia3__data_o[63:0] - attribute \src "libresoc.v:170527.7-170527.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:170648.3-170687.6" - wire width 64 $0\msr3__data_o$next[63:0]$11266 - attribute \src "libresoc.v:170574.3-170575.41" - wire width 64 $0\msr3__data_o[63:0] - attribute \src "libresoc.v:170718.3-170744.6" - wire width 64 $0\reg$next[63:0]$11280 - attribute \src "libresoc.v:170572.3-170573.25" - wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:170688.3-170717.6" - wire $0\wr_detect$4[0:0]$11274 - attribute \src "libresoc.v:170618.3-170647.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:170578.3-170617.6" - wire width 64 $1\cia3__data_o$next[63:0]$11258 - attribute \src "libresoc.v:170534.14-170534.49" - wire width 64 $1\cia3__data_o[63:0] - attribute \src "libresoc.v:170648.3-170687.6" - wire width 64 $1\msr3__data_o$next[63:0]$11267 - attribute \src "libresoc.v:170551.14-170551.49" - wire width 64 $1\msr3__data_o[63:0] - attribute \src "libresoc.v:170718.3-170744.6" - wire width 64 $1\reg$next[63:0]$11281 - attribute \src "libresoc.v:170563.14-170563.42" - wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:170688.3-170717.6" - wire $1\wr_detect$4[0:0]$11275 - attribute \src "libresoc.v:170618.3-170647.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:170578.3-170617.6" - wire width 64 $2\cia3__data_o$next[63:0]$11259 - attribute \src "libresoc.v:170648.3-170687.6" - wire width 64 $2\msr3__data_o$next[63:0]$11268 - attribute \src "libresoc.v:170718.3-170744.6" - wire width 64 $2\reg$next[63:0]$11282 - attribute \src "libresoc.v:170688.3-170717.6" - wire $2\wr_detect$4[0:0]$11276 - attribute \src "libresoc.v:170618.3-170647.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:170578.3-170617.6" - wire width 64 $3\cia3__data_o$next[63:0]$11260 - attribute \src "libresoc.v:170648.3-170687.6" - wire width 64 $3\msr3__data_o$next[63:0]$11269 - attribute \src "libresoc.v:170718.3-170744.6" - wire width 64 $3\reg$next[63:0]$11283 - attribute \src "libresoc.v:170688.3-170717.6" - wire $3\wr_detect$4[0:0]$11277 - attribute \src "libresoc.v:170618.3-170647.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:170578.3-170617.6" - wire width 64 $4\cia3__data_o$next[63:0]$11261 - attribute \src "libresoc.v:170648.3-170687.6" - wire width 64 $4\msr3__data_o$next[63:0]$11270 - attribute \src "libresoc.v:170718.3-170744.6" - wire width 64 $4\reg$next[63:0]$11284 - attribute \src "libresoc.v:170688.3-170717.6" - wire $4\wr_detect$4[0:0]$11278 - attribute \src "libresoc.v:170618.3-170647.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:170578.3-170617.6" - wire width 64 $5\cia3__data_o$next[63:0]$11262 - attribute \src "libresoc.v:170648.3-170687.6" - wire width 64 $5\msr3__data_o$next[63:0]$11271 - attribute \src "libresoc.v:170578.3-170617.6" - wire width 64 $6\cia3__data_o$next[63:0]$11263 - attribute \src "libresoc.v:170648.3-170687.6" - wire width 64 $6\msr3__data_o$next[63:0]$11272 - attribute \src "libresoc.v:170570.17-170570.100" - wire $not$libresoc.v:170570$11251_Y - attribute \src "libresoc.v:170571.17-170571.103" - wire $not$libresoc.v:170571$11252_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia3__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr13__wen - attribute \src "libresoc.v:170527.7-170527.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170570$11251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:170570$11251_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170571$11252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:170571$11252_Y - end - attribute \src "libresoc.v:170527.7-170527.20" - process $proc$libresoc.v:170527$11285 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:170534.14-170534.49" - process $proc$libresoc.v:170534$11286 - assign { } { } - assign $1\cia3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia3__data_o $1\cia3__data_o[63:0] - end - attribute \src "libresoc.v:170551.14-170551.49" - process $proc$libresoc.v:170551$11287 - assign { } { } - assign $1\msr3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr3__data_o $1\msr3__data_o[63:0] - end - attribute \src "libresoc.v:170563.14-170563.42" - process $proc$libresoc.v:170563$11288 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "libresoc.v:170572.3-170573.25" - process $proc$libresoc.v:170572$11253 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "libresoc.v:170574.3-170575.41" - process $proc$libresoc.v:170574$11254 - assign { } { } - assign $0\msr3__data_o[63:0] \msr3__data_o$next - sync posedge \coresync_clk - update \msr3__data_o $0\msr3__data_o[63:0] - end - attribute \src "libresoc.v:170576.3-170577.41" - process $proc$libresoc.v:170576$11255 - assign { } { } - assign $0\cia3__data_o[63:0] \cia3__data_o$next - sync posedge \coresync_clk - update \cia3__data_o $0\cia3__data_o[63:0] - end - attribute \src "libresoc.v:170578.3-170617.6" - process $proc$libresoc.v:170578$11256 - assign { } { } - assign { } { } - assign { } { } - assign $0\cia3__data_o$next[63:0]$11257 $6\cia3__data_o$next[63:0]$11263 - attribute \src "libresoc.v:170579.5-170579.29" - switch \initial - attribute \src "libresoc.v:170579.9-170579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia3__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\cia3__data_o$next[63:0]$11258 $5\cia3__data_o$next[63:0]$11262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia3__data_o$next[63:0]$11259 \nia3__data_i - case - assign $2\cia3__data_o$next[63:0]$11259 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia3__data_o$next[63:0]$11260 \msr3__data_i - case - assign $3\cia3__data_o$next[63:0]$11260 $2\cia3__data_o$next[63:0]$11259 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia3__data_o$next[63:0]$11261 \d_wr13__data_i - case - assign $4\cia3__data_o$next[63:0]$11261 $3\cia3__data_o$next[63:0]$11260 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia3__data_o$next[63:0]$11262 \reg - case - assign $5\cia3__data_o$next[63:0]$11262 $4\cia3__data_o$next[63:0]$11261 - end - case - assign $1\cia3__data_o$next[63:0]$11258 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\cia3__data_o$next[63:0]$11263 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\cia3__data_o$next[63:0]$11263 $1\cia3__data_o$next[63:0]$11258 - end - sync always - update \cia3__data_o$next $0\cia3__data_o$next[63:0]$11257 - end - attribute \src "libresoc.v:170618.3-170647.6" - process $proc$libresoc.v:170618$11264 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:170619.5-170619.29" - switch \initial - attribute \src "libresoc.v:170619.9-170619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia3__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 + assign $4\r23__data_o$next[3:0]$11338 \w3__data_i case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "libresoc.v:170648.3-170687.6" - process $proc$libresoc.v:170648$11265 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr3__data_o$next[63:0]$11266 $6\msr3__data_o$next[63:0]$11272 - attribute \src "libresoc.v:170649.5-170649.29" - switch \initial - attribute \src "libresoc.v:170649.9-170649.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr3__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\msr3__data_o$next[63:0]$11267 $5\msr3__data_o$next[63:0]$11271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr3__data_o$next[63:0]$11268 \nia3__data_i - case - assign $2\msr3__data_o$next[63:0]$11268 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr3__data_o$next[63:0]$11269 \msr3__data_i - case - assign $3\msr3__data_o$next[63:0]$11269 $2\msr3__data_o$next[63:0]$11268 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr3__data_o$next[63:0]$11270 \d_wr13__data_i - case - assign $4\msr3__data_o$next[63:0]$11270 $3\msr3__data_o$next[63:0]$11269 + assign $4\r23__data_o$next[3:0]$11338 $3\r23__data_o$next[3:0]$11337 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 + switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr3__data_o$next[63:0]$11271 \reg + assign $5\r23__data_o$next[3:0]$11339 \reg case - assign $5\msr3__data_o$next[63:0]$11271 $4\msr3__data_o$next[63:0]$11270 + assign $5\r23__data_o$next[3:0]$11339 $4\r23__data_o$next[3:0]$11338 end case - assign $1\msr3__data_o$next[63:0]$11267 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\r23__data_o$next[3:0]$11335 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr3__data_o$next[63:0]$11272 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\r23__data_o$next[3:0]$11340 4'0000 case - assign $6\msr3__data_o$next[63:0]$11272 $1\msr3__data_o$next[63:0]$11267 + assign $6\r23__data_o$next[3:0]$11340 $1\r23__data_o$next[3:0]$11335 end sync always - update \msr3__data_o$next $0\msr3__data_o$next[63:0]$11266 + update \r23__data_o$next $0\r23__data_o$next[3:0]$11334 end - attribute \src "libresoc.v:170688.3-170717.6" - process $proc$libresoc.v:170688$11273 + attribute \src "libresoc.v:179420.3-179449.6" + process $proc$libresoc.v:179420$11341 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11274 $1\wr_detect$4[0:0]$11275 - attribute \src "libresoc.v:170689.5-170689.29" + assign $0\wr_detect$13[0:0]$11342 $1\wr_detect$13[0:0]$11343 + attribute \src "libresoc.v:179421.5-179421.29" switch \initial - attribute \src "libresoc.v:170689.9-170689.17" + attribute \src "libresoc.v:179421.9-179421.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr3__ren + switch \r23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11275 $4\wr_detect$4[0:0]$11278 + assign $1\wr_detect$13[0:0]$11343 $4\wr_detect$13[0:0]$11346 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen + switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11276 1'1 + assign $2\wr_detect$13[0:0]$11344 1'1 case - assign $2\wr_detect$4[0:0]$11276 1'0 + assign $2\wr_detect$13[0:0]$11344 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen + switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11277 1'1 + assign $3\wr_detect$13[0:0]$11345 1'1 case - assign $3\wr_detect$4[0:0]$11277 $2\wr_detect$4[0:0]$11276 + assign $3\wr_detect$13[0:0]$11345 $2\wr_detect$13[0:0]$11344 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen + switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11278 1'1 + assign $4\wr_detect$13[0:0]$11346 1'1 case - assign $4\wr_detect$4[0:0]$11278 $3\wr_detect$4[0:0]$11277 + assign $4\wr_detect$13[0:0]$11346 $3\wr_detect$13[0:0]$11345 end case - assign $1\wr_detect$4[0:0]$11275 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11274 - end - attribute \src "libresoc.v:170718.3-170744.6" - process $proc$libresoc.v:170718$11279 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$11280 $4\reg$next[63:0]$11284 - attribute \src "libresoc.v:170719.5-170719.29" - switch \initial - attribute \src "libresoc.v:170719.9-170719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[63:0]$11281 \nia3__data_i - case - assign $1\reg$next[63:0]$11281 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[63:0]$11282 \msr3__data_i - case - assign $2\reg$next[63:0]$11282 $1\reg$next[63:0]$11281 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[63:0]$11283 \d_wr13__data_i - case - assign $3\reg$next[63:0]$11283 $2\reg$next[63:0]$11282 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[63:0]$11284 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\reg$next[63:0]$11284 $3\reg$next[63:0]$11283 + assign $1\wr_detect$13[0:0]$11343 1'0 end sync always - update \reg$next $0\reg$next[63:0]$11280 + update \wr_detect$13 $0\wr_detect$13[0:0]$11342 end - connect \$1 $not$libresoc.v:170570$11251_Y - connect \$3 $not$libresoc.v:170571$11252_Y + connect \$9 $not$libresoc.v:179056$11265_Y + connect \$12 $not$libresoc.v:179057$11266_Y + connect \$1 $not$libresoc.v:179058$11267_Y + connect \$3 $not$libresoc.v:179059$11268_Y + connect \$6 $not$libresoc.v:179060$11269_Y end -attribute \src "libresoc.v:170749.1-171220.10" +attribute \src "libresoc.v:179454.1-179925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:170750.7-170750.20" + attribute \src "libresoc.v:179455.7-179455.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171150.3-171189.6" - wire width 4 $0\r24__data_o$next[3:0]$11358 - attribute \src "libresoc.v:170833.3-170834.39" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $0\r24__data_o$next[3:0]$11423 + attribute \src "libresoc.v:179538.3-179539.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:171080.3-171119.6" - wire width 4 $0\r4__data_o$next[3:0]$11344 - attribute \src "libresoc.v:170835.3-170836.37" + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $0\r4__data_o$next[3:0]$11409 + attribute \src "libresoc.v:179540.3-179541.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:170913.3-170939.6" - wire width 4 $0\reg$next[3:0]$11310 - attribute \src "libresoc.v:170831.3-170832.25" + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $0\reg$next[3:0]$11375 + attribute \src "libresoc.v:179536.3-179537.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:170843.3-170882.6" - wire width 4 $0\src14__data_o$next[3:0]$11301 - attribute \src "libresoc.v:170841.3-170842.43" + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $0\src14__data_o$next[3:0]$11366 + attribute \src "libresoc.v:179546.3-179547.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:170940.3-170979.6" - wire width 4 $0\src24__data_o$next[3:0]$11316 - attribute \src "libresoc.v:170839.3-170840.43" + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $0\src24__data_o$next[3:0]$11381 + attribute \src "libresoc.v:179544.3-179545.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:171010.3-171049.6" - wire width 4 $0\src34__data_o$next[3:0]$11330 - attribute \src "libresoc.v:170837.3-170838.43" + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $0\src34__data_o$next[3:0]$11395 + attribute \src "libresoc.v:179542.3-179543.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:171120.3-171149.6" - wire $0\wr_detect$10[0:0]$11352 - attribute \src "libresoc.v:171190.3-171219.6" - wire $0\wr_detect$13[0:0]$11366 - attribute \src "libresoc.v:170980.3-171009.6" - wire $0\wr_detect$4[0:0]$11324 - attribute \src "libresoc.v:171050.3-171079.6" - wire $0\wr_detect$7[0:0]$11338 - attribute \src "libresoc.v:170883.3-170912.6" + attribute \src "libresoc.v:179825.3-179854.6" + wire $0\wr_detect$10[0:0]$11417 + attribute \src "libresoc.v:179895.3-179924.6" + wire $0\wr_detect$13[0:0]$11431 + attribute \src "libresoc.v:179685.3-179714.6" + wire $0\wr_detect$4[0:0]$11389 + attribute \src "libresoc.v:179755.3-179784.6" + wire $0\wr_detect$7[0:0]$11403 + attribute \src "libresoc.v:179588.3-179617.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:171150.3-171189.6" - wire width 4 $1\r24__data_o$next[3:0]$11359 - attribute \src "libresoc.v:170775.13-170775.31" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $1\r24__data_o$next[3:0]$11424 + attribute \src "libresoc.v:179480.13-179480.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:171080.3-171119.6" - wire width 4 $1\r4__data_o$next[3:0]$11345 - attribute \src "libresoc.v:170782.13-170782.30" + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $1\r4__data_o$next[3:0]$11410 + attribute \src "libresoc.v:179487.13-179487.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:170913.3-170939.6" - wire width 4 $1\reg$next[3:0]$11311 - attribute \src "libresoc.v:170788.13-170788.25" + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $1\reg$next[3:0]$11376 + attribute \src "libresoc.v:179493.13-179493.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:170843.3-170882.6" - wire width 4 $1\src14__data_o$next[3:0]$11302 - attribute \src "libresoc.v:170793.13-170793.33" + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $1\src14__data_o$next[3:0]$11367 + attribute \src "libresoc.v:179498.13-179498.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:170940.3-170979.6" - wire width 4 $1\src24__data_o$next[3:0]$11317 - attribute \src "libresoc.v:170800.13-170800.33" + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $1\src24__data_o$next[3:0]$11382 + attribute \src "libresoc.v:179505.13-179505.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:171010.3-171049.6" - wire width 4 $1\src34__data_o$next[3:0]$11331 - attribute \src "libresoc.v:170807.13-170807.33" + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $1\src34__data_o$next[3:0]$11396 + attribute \src "libresoc.v:179512.13-179512.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:171120.3-171149.6" - wire $1\wr_detect$10[0:0]$11353 - attribute \src "libresoc.v:171190.3-171219.6" - wire $1\wr_detect$13[0:0]$11367 - attribute \src "libresoc.v:170980.3-171009.6" - wire $1\wr_detect$4[0:0]$11325 - attribute \src "libresoc.v:171050.3-171079.6" - wire $1\wr_detect$7[0:0]$11339 - attribute \src "libresoc.v:170883.3-170912.6" + attribute \src "libresoc.v:179825.3-179854.6" + wire $1\wr_detect$10[0:0]$11418 + attribute \src "libresoc.v:179895.3-179924.6" + wire $1\wr_detect$13[0:0]$11432 + attribute \src "libresoc.v:179685.3-179714.6" + wire $1\wr_detect$4[0:0]$11390 + attribute \src "libresoc.v:179755.3-179784.6" + wire $1\wr_detect$7[0:0]$11404 + attribute \src "libresoc.v:179588.3-179617.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:171150.3-171189.6" - wire width 4 $2\r24__data_o$next[3:0]$11360 - attribute \src "libresoc.v:171080.3-171119.6" - wire width 4 $2\r4__data_o$next[3:0]$11346 - attribute \src "libresoc.v:170913.3-170939.6" - wire width 4 $2\reg$next[3:0]$11312 - attribute \src "libresoc.v:170843.3-170882.6" - wire width 4 $2\src14__data_o$next[3:0]$11303 - attribute \src "libresoc.v:170940.3-170979.6" - wire width 4 $2\src24__data_o$next[3:0]$11318 - attribute \src "libresoc.v:171010.3-171049.6" - wire width 4 $2\src34__data_o$next[3:0]$11332 - attribute \src "libresoc.v:171120.3-171149.6" - wire $2\wr_detect$10[0:0]$11354 - attribute \src "libresoc.v:171190.3-171219.6" - wire $2\wr_detect$13[0:0]$11368 - attribute \src "libresoc.v:170980.3-171009.6" - wire $2\wr_detect$4[0:0]$11326 - attribute \src "libresoc.v:171050.3-171079.6" - wire $2\wr_detect$7[0:0]$11340 - attribute \src "libresoc.v:170883.3-170912.6" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $2\r24__data_o$next[3:0]$11425 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $2\r4__data_o$next[3:0]$11411 + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $2\reg$next[3:0]$11377 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $2\src14__data_o$next[3:0]$11368 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $2\src24__data_o$next[3:0]$11383 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $2\src34__data_o$next[3:0]$11397 + attribute \src "libresoc.v:179825.3-179854.6" + wire $2\wr_detect$10[0:0]$11419 + attribute \src "libresoc.v:179895.3-179924.6" + wire $2\wr_detect$13[0:0]$11433 + attribute \src "libresoc.v:179685.3-179714.6" + wire $2\wr_detect$4[0:0]$11391 + attribute \src "libresoc.v:179755.3-179784.6" + wire $2\wr_detect$7[0:0]$11405 + attribute \src "libresoc.v:179588.3-179617.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:171150.3-171189.6" - wire width 4 $3\r24__data_o$next[3:0]$11361 - attribute \src "libresoc.v:171080.3-171119.6" - wire width 4 $3\r4__data_o$next[3:0]$11347 - attribute \src "libresoc.v:170913.3-170939.6" - wire width 4 $3\reg$next[3:0]$11313 - attribute \src "libresoc.v:170843.3-170882.6" - wire width 4 $3\src14__data_o$next[3:0]$11304 - attribute \src "libresoc.v:170940.3-170979.6" - wire width 4 $3\src24__data_o$next[3:0]$11319 - attribute \src "libresoc.v:171010.3-171049.6" - wire width 4 $3\src34__data_o$next[3:0]$11333 - attribute \src "libresoc.v:171120.3-171149.6" - wire $3\wr_detect$10[0:0]$11355 - attribute \src "libresoc.v:171190.3-171219.6" - wire $3\wr_detect$13[0:0]$11369 - attribute \src "libresoc.v:170980.3-171009.6" - wire $3\wr_detect$4[0:0]$11327 - attribute \src "libresoc.v:171050.3-171079.6" - wire $3\wr_detect$7[0:0]$11341 - attribute \src "libresoc.v:170883.3-170912.6" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $3\r24__data_o$next[3:0]$11426 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $3\r4__data_o$next[3:0]$11412 + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $3\reg$next[3:0]$11378 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $3\src14__data_o$next[3:0]$11369 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $3\src24__data_o$next[3:0]$11384 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $3\src34__data_o$next[3:0]$11398 + attribute \src "libresoc.v:179825.3-179854.6" + wire $3\wr_detect$10[0:0]$11420 + attribute \src "libresoc.v:179895.3-179924.6" + wire $3\wr_detect$13[0:0]$11434 + attribute \src "libresoc.v:179685.3-179714.6" + wire $3\wr_detect$4[0:0]$11392 + attribute \src "libresoc.v:179755.3-179784.6" + wire $3\wr_detect$7[0:0]$11406 + attribute \src "libresoc.v:179588.3-179617.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:171150.3-171189.6" - wire width 4 $4\r24__data_o$next[3:0]$11362 - attribute \src "libresoc.v:171080.3-171119.6" - wire width 4 $4\r4__data_o$next[3:0]$11348 - attribute \src "libresoc.v:170913.3-170939.6" - wire width 4 $4\reg$next[3:0]$11314 - attribute \src "libresoc.v:170843.3-170882.6" - wire width 4 $4\src14__data_o$next[3:0]$11305 - attribute \src "libresoc.v:170940.3-170979.6" - wire width 4 $4\src24__data_o$next[3:0]$11320 - attribute \src "libresoc.v:171010.3-171049.6" - wire width 4 $4\src34__data_o$next[3:0]$11334 - attribute \src "libresoc.v:171120.3-171149.6" - wire $4\wr_detect$10[0:0]$11356 - attribute \src "libresoc.v:171190.3-171219.6" - wire $4\wr_detect$13[0:0]$11370 - attribute \src "libresoc.v:170980.3-171009.6" - wire $4\wr_detect$4[0:0]$11328 - attribute \src "libresoc.v:171050.3-171079.6" - wire $4\wr_detect$7[0:0]$11342 - attribute \src "libresoc.v:170883.3-170912.6" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $4\r24__data_o$next[3:0]$11427 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $4\r4__data_o$next[3:0]$11413 + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $4\reg$next[3:0]$11379 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $4\src14__data_o$next[3:0]$11370 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $4\src24__data_o$next[3:0]$11385 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $4\src34__data_o$next[3:0]$11399 + attribute \src "libresoc.v:179825.3-179854.6" + wire $4\wr_detect$10[0:0]$11421 + attribute \src "libresoc.v:179895.3-179924.6" + wire $4\wr_detect$13[0:0]$11435 + attribute \src "libresoc.v:179685.3-179714.6" + wire $4\wr_detect$4[0:0]$11393 + attribute \src "libresoc.v:179755.3-179784.6" + wire $4\wr_detect$7[0:0]$11407 + attribute \src "libresoc.v:179588.3-179617.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:171150.3-171189.6" - wire width 4 $5\r24__data_o$next[3:0]$11363 - attribute \src "libresoc.v:171080.3-171119.6" - wire width 4 $5\r4__data_o$next[3:0]$11349 - attribute \src "libresoc.v:170843.3-170882.6" - wire width 4 $5\src14__data_o$next[3:0]$11306 - attribute \src "libresoc.v:170940.3-170979.6" - wire width 4 $5\src24__data_o$next[3:0]$11321 - attribute \src "libresoc.v:171010.3-171049.6" - wire width 4 $5\src34__data_o$next[3:0]$11335 - attribute \src "libresoc.v:171150.3-171189.6" - wire width 4 $6\r24__data_o$next[3:0]$11364 - attribute \src "libresoc.v:171080.3-171119.6" - wire width 4 $6\r4__data_o$next[3:0]$11350 - attribute \src "libresoc.v:170843.3-170882.6" - wire width 4 $6\src14__data_o$next[3:0]$11307 - attribute \src "libresoc.v:170940.3-170979.6" - wire width 4 $6\src24__data_o$next[3:0]$11322 - attribute \src "libresoc.v:171010.3-171049.6" - wire width 4 $6\src34__data_o$next[3:0]$11336 - attribute \src "libresoc.v:170826.17-170826.104" - wire $not$libresoc.v:170826$11289_Y - attribute \src "libresoc.v:170827.18-170827.105" - wire $not$libresoc.v:170827$11290_Y - attribute \src "libresoc.v:170828.17-170828.100" - wire $not$libresoc.v:170828$11291_Y - attribute \src "libresoc.v:170829.17-170829.103" - wire $not$libresoc.v:170829$11292_Y - attribute \src "libresoc.v:170830.17-170830.103" - wire $not$libresoc.v:170830$11293_Y + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $5\r24__data_o$next[3:0]$11428 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $5\r4__data_o$next[3:0]$11414 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $5\src14__data_o$next[3:0]$11371 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $5\src24__data_o$next[3:0]$11386 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $5\src34__data_o$next[3:0]$11400 + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $6\r24__data_o$next[3:0]$11429 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $6\r4__data_o$next[3:0]$11415 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $6\src14__data_o$next[3:0]$11372 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $6\src24__data_o$next[3:0]$11387 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $6\src34__data_o$next[3:0]$11401 + attribute \src "libresoc.v:179531.17-179531.104" + wire $not$libresoc.v:179531$11354_Y + attribute \src "libresoc.v:179532.18-179532.105" + wire $not$libresoc.v:179532$11355_Y + attribute \src "libresoc.v:179533.17-179533.100" + wire $not$libresoc.v:179533$11356_Y + attribute \src "libresoc.v:179534.17-179534.103" + wire $not$libresoc.v:179534$11357_Y + attribute \src "libresoc.v:179535.17-179535.103" + wire $not$libresoc.v:179535$11358_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -355060,57 +370057,57 @@ module \reg_4 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest14__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest14__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest24__wen - attribute \src "libresoc.v:170750.7-170750.15" + attribute \src "libresoc.v:179455.7-179455.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r24__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r4__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r4__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src14__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src24__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src34__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src34__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src34__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w4__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w4__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -355123,152 +370120,152 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170826$11289 + cell $not $not$libresoc.v:179531$11354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:170826$11289_Y + connect \Y $not$libresoc.v:179531$11354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170827$11290 + cell $not $not$libresoc.v:179532$11355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:170827$11290_Y + connect \Y $not$libresoc.v:179532$11355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170828$11291 + cell $not $not$libresoc.v:179533$11356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:170828$11291_Y + connect \Y $not$libresoc.v:179533$11356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170829$11292 + cell $not $not$libresoc.v:179534$11357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:170829$11292_Y + connect \Y $not$libresoc.v:179534$11357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170830$11293 + cell $not $not$libresoc.v:179535$11358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:170830$11293_Y + connect \Y $not$libresoc.v:179535$11358_Y end - attribute \src "libresoc.v:170750.7-170750.20" - process $proc$libresoc.v:170750$11371 + attribute \src "libresoc.v:179455.7-179455.20" + process $proc$libresoc.v:179455$11436 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170775.13-170775.31" - process $proc$libresoc.v:170775$11372 + attribute \src "libresoc.v:179480.13-179480.31" + process $proc$libresoc.v:179480$11437 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:170782.13-170782.30" - process $proc$libresoc.v:170782$11373 + attribute \src "libresoc.v:179487.13-179487.30" + process $proc$libresoc.v:179487$11438 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:170788.13-170788.25" - process $proc$libresoc.v:170788$11374 + attribute \src "libresoc.v:179493.13-179493.25" + process $proc$libresoc.v:179493$11439 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:170793.13-170793.33" - process $proc$libresoc.v:170793$11375 + attribute \src "libresoc.v:179498.13-179498.33" + process $proc$libresoc.v:179498$11440 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:170800.13-170800.33" - process $proc$libresoc.v:170800$11376 + attribute \src "libresoc.v:179505.13-179505.33" + process $proc$libresoc.v:179505$11441 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:170807.13-170807.33" - process $proc$libresoc.v:170807$11377 + attribute \src "libresoc.v:179512.13-179512.33" + process $proc$libresoc.v:179512$11442 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:170831.3-170832.25" - process $proc$libresoc.v:170831$11294 + attribute \src "libresoc.v:179536.3-179537.25" + process $proc$libresoc.v:179536$11359 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:170833.3-170834.39" - process $proc$libresoc.v:170833$11295 + attribute \src "libresoc.v:179538.3-179539.39" + process $proc$libresoc.v:179538$11360 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:170835.3-170836.37" - process $proc$libresoc.v:170835$11296 + attribute \src "libresoc.v:179540.3-179541.37" + process $proc$libresoc.v:179540$11361 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:170837.3-170838.43" - process $proc$libresoc.v:170837$11297 + attribute \src "libresoc.v:179542.3-179543.43" + process $proc$libresoc.v:179542$11362 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:170839.3-170840.43" - process $proc$libresoc.v:170839$11298 + attribute \src "libresoc.v:179544.3-179545.43" + process $proc$libresoc.v:179544$11363 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:170841.3-170842.43" - process $proc$libresoc.v:170841$11299 + attribute \src "libresoc.v:179546.3-179547.43" + process $proc$libresoc.v:179546$11364 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:170843.3-170882.6" - process $proc$libresoc.v:170843$11300 + attribute \src "libresoc.v:179548.3-179587.6" + process $proc$libresoc.v:179548$11365 assign { } { } assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$11301 $6\src14__data_o$next[3:0]$11307 - attribute \src "libresoc.v:170844.5-170844.29" + assign $0\src14__data_o$next[3:0]$11366 $6\src14__data_o$next[3:0]$11372 + attribute \src "libresoc.v:179549.5-179549.29" switch \initial - attribute \src "libresoc.v:170844.9-170844.17" + attribute \src "libresoc.v:179549.9-179549.17" case 1'1 case end @@ -355280,66 +370277,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src14__data_o$next[3:0]$11302 $5\src14__data_o$next[3:0]$11306 + assign $1\src14__data_o$next[3:0]$11367 $5\src14__data_o$next[3:0]$11371 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src14__data_o$next[3:0]$11303 \dest14__data_i + assign $2\src14__data_o$next[3:0]$11368 \dest14__data_i case - assign $2\src14__data_o$next[3:0]$11303 4'0000 + assign $2\src14__data_o$next[3:0]$11368 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src14__data_o$next[3:0]$11304 \dest24__data_i + assign $3\src14__data_o$next[3:0]$11369 \dest24__data_i case - assign $3\src14__data_o$next[3:0]$11304 $2\src14__data_o$next[3:0]$11303 + assign $3\src14__data_o$next[3:0]$11369 $2\src14__data_o$next[3:0]$11368 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src14__data_o$next[3:0]$11305 \w4__data_i + assign $4\src14__data_o$next[3:0]$11370 \w4__data_i case - assign $4\src14__data_o$next[3:0]$11305 $3\src14__data_o$next[3:0]$11304 + assign $4\src14__data_o$next[3:0]$11370 $3\src14__data_o$next[3:0]$11369 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$11306 \reg + assign $5\src14__data_o$next[3:0]$11371 \reg case - assign $5\src14__data_o$next[3:0]$11306 $4\src14__data_o$next[3:0]$11305 + assign $5\src14__data_o$next[3:0]$11371 $4\src14__data_o$next[3:0]$11370 end case - assign $1\src14__data_o$next[3:0]$11302 4'0000 + assign $1\src14__data_o$next[3:0]$11367 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$11307 4'0000 + assign $6\src14__data_o$next[3:0]$11372 4'0000 case - assign $6\src14__data_o$next[3:0]$11307 $1\src14__data_o$next[3:0]$11302 + assign $6\src14__data_o$next[3:0]$11372 $1\src14__data_o$next[3:0]$11367 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11301 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11366 end - attribute \src "libresoc.v:170883.3-170912.6" - process $proc$libresoc.v:170883$11308 + attribute \src "libresoc.v:179588.3-179617.6" + process $proc$libresoc.v:179588$11373 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:170884.5-170884.29" + attribute \src "libresoc.v:179589.5-179589.29" switch \initial - attribute \src "libresoc.v:170884.9-170884.17" + attribute \src "libresoc.v:179589.9-179589.17" case 1'1 case end @@ -355385,17 +370382,17 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:170913.3-170939.6" - process $proc$libresoc.v:170913$11309 + attribute \src "libresoc.v:179618.3-179644.6" + process $proc$libresoc.v:179618$11374 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11310 $4\reg$next[3:0]$11314 - attribute \src "libresoc.v:170914.5-170914.29" + assign $0\reg$next[3:0]$11375 $4\reg$next[3:0]$11379 + attribute \src "libresoc.v:179619.5-179619.29" switch \initial - attribute \src "libresoc.v:170914.9-170914.17" + attribute \src "libresoc.v:179619.9-179619.17" case 1'1 case end @@ -355404,49 +370401,49 @@ module \reg_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11311 \dest14__data_i + assign $1\reg$next[3:0]$11376 \dest14__data_i case - assign $1\reg$next[3:0]$11311 \reg + assign $1\reg$next[3:0]$11376 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11312 \dest24__data_i + assign $2\reg$next[3:0]$11377 \dest24__data_i case - assign $2\reg$next[3:0]$11312 $1\reg$next[3:0]$11311 + assign $2\reg$next[3:0]$11377 $1\reg$next[3:0]$11376 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11313 \w4__data_i + assign $3\reg$next[3:0]$11378 \w4__data_i case - assign $3\reg$next[3:0]$11313 $2\reg$next[3:0]$11312 + assign $3\reg$next[3:0]$11378 $2\reg$next[3:0]$11377 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11314 4'0000 + assign $4\reg$next[3:0]$11379 4'0000 case - assign $4\reg$next[3:0]$11314 $3\reg$next[3:0]$11313 + assign $4\reg$next[3:0]$11379 $3\reg$next[3:0]$11378 end sync always - update \reg$next $0\reg$next[3:0]$11310 + update \reg$next $0\reg$next[3:0]$11375 end - attribute \src "libresoc.v:170940.3-170979.6" - process $proc$libresoc.v:170940$11315 + attribute \src "libresoc.v:179645.3-179684.6" + process $proc$libresoc.v:179645$11380 assign { } { } assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11316 $6\src24__data_o$next[3:0]$11322 - attribute \src "libresoc.v:170941.5-170941.29" + assign $0\src24__data_o$next[3:0]$11381 $6\src24__data_o$next[3:0]$11387 + attribute \src "libresoc.v:179646.5-179646.29" switch \initial - attribute \src "libresoc.v:170941.9-170941.17" + attribute \src "libresoc.v:179646.9-179646.17" case 1'1 case end @@ -355458,66 +370455,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$11317 $5\src24__data_o$next[3:0]$11321 + assign $1\src24__data_o$next[3:0]$11382 $5\src24__data_o$next[3:0]$11386 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$11318 \dest14__data_i + assign $2\src24__data_o$next[3:0]$11383 \dest14__data_i case - assign $2\src24__data_o$next[3:0]$11318 4'0000 + assign $2\src24__data_o$next[3:0]$11383 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$11319 \dest24__data_i + assign $3\src24__data_o$next[3:0]$11384 \dest24__data_i case - assign $3\src24__data_o$next[3:0]$11319 $2\src24__data_o$next[3:0]$11318 + assign $3\src24__data_o$next[3:0]$11384 $2\src24__data_o$next[3:0]$11383 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$11320 \w4__data_i + assign $4\src24__data_o$next[3:0]$11385 \w4__data_i case - assign $4\src24__data_o$next[3:0]$11320 $3\src24__data_o$next[3:0]$11319 + assign $4\src24__data_o$next[3:0]$11385 $3\src24__data_o$next[3:0]$11384 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$11321 \reg + assign $5\src24__data_o$next[3:0]$11386 \reg case - assign $5\src24__data_o$next[3:0]$11321 $4\src24__data_o$next[3:0]$11320 + assign $5\src24__data_o$next[3:0]$11386 $4\src24__data_o$next[3:0]$11385 end case - assign $1\src24__data_o$next[3:0]$11317 4'0000 + assign $1\src24__data_o$next[3:0]$11382 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$11322 4'0000 + assign $6\src24__data_o$next[3:0]$11387 4'0000 case - assign $6\src24__data_o$next[3:0]$11322 $1\src24__data_o$next[3:0]$11317 + assign $6\src24__data_o$next[3:0]$11387 $1\src24__data_o$next[3:0]$11382 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11316 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11381 end - attribute \src "libresoc.v:170980.3-171009.6" - process $proc$libresoc.v:170980$11323 + attribute \src "libresoc.v:179685.3-179714.6" + process $proc$libresoc.v:179685$11388 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11324 $1\wr_detect$4[0:0]$11325 - attribute \src "libresoc.v:170981.5-170981.29" + assign $0\wr_detect$4[0:0]$11389 $1\wr_detect$4[0:0]$11390 + attribute \src "libresoc.v:179686.5-179686.29" switch \initial - attribute \src "libresoc.v:170981.9-170981.17" + attribute \src "libresoc.v:179686.9-179686.17" case 1'1 case end @@ -355529,49 +370526,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11325 $4\wr_detect$4[0:0]$11328 + assign $1\wr_detect$4[0:0]$11390 $4\wr_detect$4[0:0]$11393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11326 1'1 + assign $2\wr_detect$4[0:0]$11391 1'1 case - assign $2\wr_detect$4[0:0]$11326 1'0 + assign $2\wr_detect$4[0:0]$11391 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11327 1'1 + assign $3\wr_detect$4[0:0]$11392 1'1 case - assign $3\wr_detect$4[0:0]$11327 $2\wr_detect$4[0:0]$11326 + assign $3\wr_detect$4[0:0]$11392 $2\wr_detect$4[0:0]$11391 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11328 1'1 + assign $4\wr_detect$4[0:0]$11393 1'1 case - assign $4\wr_detect$4[0:0]$11328 $3\wr_detect$4[0:0]$11327 + assign $4\wr_detect$4[0:0]$11393 $3\wr_detect$4[0:0]$11392 end case - assign $1\wr_detect$4[0:0]$11325 1'0 + assign $1\wr_detect$4[0:0]$11390 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11324 + update \wr_detect$4 $0\wr_detect$4[0:0]$11389 end - attribute \src "libresoc.v:171010.3-171049.6" - process $proc$libresoc.v:171010$11329 + attribute \src "libresoc.v:179715.3-179754.6" + process $proc$libresoc.v:179715$11394 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11330 $6\src34__data_o$next[3:0]$11336 - attribute \src "libresoc.v:171011.5-171011.29" + assign $0\src34__data_o$next[3:0]$11395 $6\src34__data_o$next[3:0]$11401 + attribute \src "libresoc.v:179716.5-179716.29" switch \initial - attribute \src "libresoc.v:171011.9-171011.17" + attribute \src "libresoc.v:179716.9-179716.17" case 1'1 case end @@ -355583,66 +370580,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$11331 $5\src34__data_o$next[3:0]$11335 + assign $1\src34__data_o$next[3:0]$11396 $5\src34__data_o$next[3:0]$11400 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$11332 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11397 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$11332 4'0000 + assign $2\src34__data_o$next[3:0]$11397 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$11333 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11398 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$11333 $2\src34__data_o$next[3:0]$11332 + assign $3\src34__data_o$next[3:0]$11398 $2\src34__data_o$next[3:0]$11397 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$11334 \w4__data_i + assign $4\src34__data_o$next[3:0]$11399 \w4__data_i case - assign $4\src34__data_o$next[3:0]$11334 $3\src34__data_o$next[3:0]$11333 + assign $4\src34__data_o$next[3:0]$11399 $3\src34__data_o$next[3:0]$11398 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$11335 \reg + assign $5\src34__data_o$next[3:0]$11400 \reg case - assign $5\src34__data_o$next[3:0]$11335 $4\src34__data_o$next[3:0]$11334 + assign $5\src34__data_o$next[3:0]$11400 $4\src34__data_o$next[3:0]$11399 end case - assign $1\src34__data_o$next[3:0]$11331 4'0000 + assign $1\src34__data_o$next[3:0]$11396 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$11336 4'0000 + assign $6\src34__data_o$next[3:0]$11401 4'0000 case - assign $6\src34__data_o$next[3:0]$11336 $1\src34__data_o$next[3:0]$11331 + assign $6\src34__data_o$next[3:0]$11401 $1\src34__data_o$next[3:0]$11396 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11330 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11395 end - attribute \src "libresoc.v:171050.3-171079.6" - process $proc$libresoc.v:171050$11337 + attribute \src "libresoc.v:179755.3-179784.6" + process $proc$libresoc.v:179755$11402 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11338 $1\wr_detect$7[0:0]$11339 - attribute \src "libresoc.v:171051.5-171051.29" + assign $0\wr_detect$7[0:0]$11403 $1\wr_detect$7[0:0]$11404 + attribute \src "libresoc.v:179756.5-179756.29" switch \initial - attribute \src "libresoc.v:171051.9-171051.17" + attribute \src "libresoc.v:179756.9-179756.17" case 1'1 case end @@ -355654,49 +370651,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11339 $4\wr_detect$7[0:0]$11342 + assign $1\wr_detect$7[0:0]$11404 $4\wr_detect$7[0:0]$11407 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11340 1'1 + assign $2\wr_detect$7[0:0]$11405 1'1 case - assign $2\wr_detect$7[0:0]$11340 1'0 + assign $2\wr_detect$7[0:0]$11405 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11341 1'1 + assign $3\wr_detect$7[0:0]$11406 1'1 case - assign $3\wr_detect$7[0:0]$11341 $2\wr_detect$7[0:0]$11340 + assign $3\wr_detect$7[0:0]$11406 $2\wr_detect$7[0:0]$11405 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11342 1'1 + assign $4\wr_detect$7[0:0]$11407 1'1 case - assign $4\wr_detect$7[0:0]$11342 $3\wr_detect$7[0:0]$11341 + assign $4\wr_detect$7[0:0]$11407 $3\wr_detect$7[0:0]$11406 end case - assign $1\wr_detect$7[0:0]$11339 1'0 + assign $1\wr_detect$7[0:0]$11404 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11338 + update \wr_detect$7 $0\wr_detect$7[0:0]$11403 end - attribute \src "libresoc.v:171080.3-171119.6" - process $proc$libresoc.v:171080$11343 + attribute \src "libresoc.v:179785.3-179824.6" + process $proc$libresoc.v:179785$11408 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11344 $6\r4__data_o$next[3:0]$11350 - attribute \src "libresoc.v:171081.5-171081.29" + assign $0\r4__data_o$next[3:0]$11409 $6\r4__data_o$next[3:0]$11415 + attribute \src "libresoc.v:179786.5-179786.29" switch \initial - attribute \src "libresoc.v:171081.9-171081.17" + attribute \src "libresoc.v:179786.9-179786.17" case 1'1 case end @@ -355708,66 +370705,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$11345 $5\r4__data_o$next[3:0]$11349 + assign $1\r4__data_o$next[3:0]$11410 $5\r4__data_o$next[3:0]$11414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$11346 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11411 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$11346 4'0000 + assign $2\r4__data_o$next[3:0]$11411 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$11347 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11412 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$11347 $2\r4__data_o$next[3:0]$11346 + assign $3\r4__data_o$next[3:0]$11412 $2\r4__data_o$next[3:0]$11411 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$11348 \w4__data_i + assign $4\r4__data_o$next[3:0]$11413 \w4__data_i case - assign $4\r4__data_o$next[3:0]$11348 $3\r4__data_o$next[3:0]$11347 + assign $4\r4__data_o$next[3:0]$11413 $3\r4__data_o$next[3:0]$11412 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$11349 \reg + assign $5\r4__data_o$next[3:0]$11414 \reg case - assign $5\r4__data_o$next[3:0]$11349 $4\r4__data_o$next[3:0]$11348 + assign $5\r4__data_o$next[3:0]$11414 $4\r4__data_o$next[3:0]$11413 end case - assign $1\r4__data_o$next[3:0]$11345 4'0000 + assign $1\r4__data_o$next[3:0]$11410 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$11350 4'0000 + assign $6\r4__data_o$next[3:0]$11415 4'0000 case - assign $6\r4__data_o$next[3:0]$11350 $1\r4__data_o$next[3:0]$11345 + assign $6\r4__data_o$next[3:0]$11415 $1\r4__data_o$next[3:0]$11410 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11344 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11409 end - attribute \src "libresoc.v:171120.3-171149.6" - process $proc$libresoc.v:171120$11351 + attribute \src "libresoc.v:179825.3-179854.6" + process $proc$libresoc.v:179825$11416 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11352 $1\wr_detect$10[0:0]$11353 - attribute \src "libresoc.v:171121.5-171121.29" + assign $0\wr_detect$10[0:0]$11417 $1\wr_detect$10[0:0]$11418 + attribute \src "libresoc.v:179826.5-179826.29" switch \initial - attribute \src "libresoc.v:171121.9-171121.17" + attribute \src "libresoc.v:179826.9-179826.17" case 1'1 case end @@ -355779,49 +370776,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11353 $4\wr_detect$10[0:0]$11356 + assign $1\wr_detect$10[0:0]$11418 $4\wr_detect$10[0:0]$11421 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11354 1'1 + assign $2\wr_detect$10[0:0]$11419 1'1 case - assign $2\wr_detect$10[0:0]$11354 1'0 + assign $2\wr_detect$10[0:0]$11419 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11355 1'1 + assign $3\wr_detect$10[0:0]$11420 1'1 case - assign $3\wr_detect$10[0:0]$11355 $2\wr_detect$10[0:0]$11354 + assign $3\wr_detect$10[0:0]$11420 $2\wr_detect$10[0:0]$11419 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11356 1'1 + assign $4\wr_detect$10[0:0]$11421 1'1 case - assign $4\wr_detect$10[0:0]$11356 $3\wr_detect$10[0:0]$11355 + assign $4\wr_detect$10[0:0]$11421 $3\wr_detect$10[0:0]$11420 end case - assign $1\wr_detect$10[0:0]$11353 1'0 + assign $1\wr_detect$10[0:0]$11418 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11352 + update \wr_detect$10 $0\wr_detect$10[0:0]$11417 end - attribute \src "libresoc.v:171150.3-171189.6" - process $proc$libresoc.v:171150$11357 + attribute \src "libresoc.v:179855.3-179894.6" + process $proc$libresoc.v:179855$11422 assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$11358 $6\r24__data_o$next[3:0]$11364 - attribute \src "libresoc.v:171151.5-171151.29" + assign $0\r24__data_o$next[3:0]$11423 $6\r24__data_o$next[3:0]$11429 + attribute \src "libresoc.v:179856.5-179856.29" switch \initial - attribute \src "libresoc.v:171151.9-171151.17" + attribute \src "libresoc.v:179856.9-179856.17" case 1'1 case end @@ -355833,66 +370830,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r24__data_o$next[3:0]$11359 $5\r24__data_o$next[3:0]$11363 + assign $1\r24__data_o$next[3:0]$11424 $5\r24__data_o$next[3:0]$11428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r24__data_o$next[3:0]$11360 \dest14__data_i + assign $2\r24__data_o$next[3:0]$11425 \dest14__data_i case - assign $2\r24__data_o$next[3:0]$11360 4'0000 + assign $2\r24__data_o$next[3:0]$11425 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r24__data_o$next[3:0]$11361 \dest24__data_i + assign $3\r24__data_o$next[3:0]$11426 \dest24__data_i case - assign $3\r24__data_o$next[3:0]$11361 $2\r24__data_o$next[3:0]$11360 + assign $3\r24__data_o$next[3:0]$11426 $2\r24__data_o$next[3:0]$11425 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r24__data_o$next[3:0]$11362 \w4__data_i + assign $4\r24__data_o$next[3:0]$11427 \w4__data_i case - assign $4\r24__data_o$next[3:0]$11362 $3\r24__data_o$next[3:0]$11361 + assign $4\r24__data_o$next[3:0]$11427 $3\r24__data_o$next[3:0]$11426 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r24__data_o$next[3:0]$11363 \reg + assign $5\r24__data_o$next[3:0]$11428 \reg case - assign $5\r24__data_o$next[3:0]$11363 $4\r24__data_o$next[3:0]$11362 + assign $5\r24__data_o$next[3:0]$11428 $4\r24__data_o$next[3:0]$11427 end case - assign $1\r24__data_o$next[3:0]$11359 4'0000 + assign $1\r24__data_o$next[3:0]$11424 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11364 4'0000 + assign $6\r24__data_o$next[3:0]$11429 4'0000 case - assign $6\r24__data_o$next[3:0]$11364 $1\r24__data_o$next[3:0]$11359 + assign $6\r24__data_o$next[3:0]$11429 $1\r24__data_o$next[3:0]$11424 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11358 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11423 end - attribute \src "libresoc.v:171190.3-171219.6" - process $proc$libresoc.v:171190$11365 + attribute \src "libresoc.v:179895.3-179924.6" + process $proc$libresoc.v:179895$11430 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11366 $1\wr_detect$13[0:0]$11367 - attribute \src "libresoc.v:171191.5-171191.29" + assign $0\wr_detect$13[0:0]$11431 $1\wr_detect$13[0:0]$11432 + attribute \src "libresoc.v:179896.5-179896.29" switch \initial - attribute \src "libresoc.v:171191.9-171191.17" + attribute \src "libresoc.v:179896.9-179896.17" case 1'1 case end @@ -355904,217 +370901,217 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11367 $4\wr_detect$13[0:0]$11370 + assign $1\wr_detect$13[0:0]$11432 $4\wr_detect$13[0:0]$11435 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11368 1'1 + assign $2\wr_detect$13[0:0]$11433 1'1 case - assign $2\wr_detect$13[0:0]$11368 1'0 + assign $2\wr_detect$13[0:0]$11433 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11369 1'1 + assign $3\wr_detect$13[0:0]$11434 1'1 case - assign $3\wr_detect$13[0:0]$11369 $2\wr_detect$13[0:0]$11368 + assign $3\wr_detect$13[0:0]$11434 $2\wr_detect$13[0:0]$11433 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11370 1'1 + assign $4\wr_detect$13[0:0]$11435 1'1 case - assign $4\wr_detect$13[0:0]$11370 $3\wr_detect$13[0:0]$11369 + assign $4\wr_detect$13[0:0]$11435 $3\wr_detect$13[0:0]$11434 end case - assign $1\wr_detect$13[0:0]$11367 1'0 + assign $1\wr_detect$13[0:0]$11432 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11366 + update \wr_detect$13 $0\wr_detect$13[0:0]$11431 end - connect \$9 $not$libresoc.v:170826$11289_Y - connect \$12 $not$libresoc.v:170827$11290_Y - connect \$1 $not$libresoc.v:170828$11291_Y - connect \$3 $not$libresoc.v:170829$11292_Y - connect \$6 $not$libresoc.v:170830$11293_Y + connect \$9 $not$libresoc.v:179531$11354_Y + connect \$12 $not$libresoc.v:179532$11355_Y + connect \$1 $not$libresoc.v:179533$11356_Y + connect \$3 $not$libresoc.v:179534$11357_Y + connect \$6 $not$libresoc.v:179535$11358_Y end -attribute \src "libresoc.v:171224.1-171695.10" +attribute \src "libresoc.v:179929.1-180400.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:171225.7-171225.20" + attribute \src "libresoc.v:179930.7-179930.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171625.3-171664.6" - wire width 4 $0\r25__data_o$next[3:0]$11447 - attribute \src "libresoc.v:171308.3-171309.39" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $0\r25__data_o$next[3:0]$11512 + attribute \src "libresoc.v:180013.3-180014.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:171555.3-171594.6" - wire width 4 $0\r5__data_o$next[3:0]$11433 - attribute \src "libresoc.v:171310.3-171311.37" + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $0\r5__data_o$next[3:0]$11498 + attribute \src "libresoc.v:180015.3-180016.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:171388.3-171414.6" - wire width 4 $0\reg$next[3:0]$11399 - attribute \src "libresoc.v:171306.3-171307.25" + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $0\reg$next[3:0]$11464 + attribute \src "libresoc.v:180011.3-180012.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:171318.3-171357.6" - wire width 4 $0\src15__data_o$next[3:0]$11390 - attribute \src "libresoc.v:171316.3-171317.43" + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $0\src15__data_o$next[3:0]$11455 + attribute \src "libresoc.v:180021.3-180022.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:171415.3-171454.6" - wire width 4 $0\src25__data_o$next[3:0]$11405 - attribute \src "libresoc.v:171314.3-171315.43" + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $0\src25__data_o$next[3:0]$11470 + attribute \src "libresoc.v:180019.3-180020.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:171485.3-171524.6" - wire width 4 $0\src35__data_o$next[3:0]$11419 - attribute \src "libresoc.v:171312.3-171313.43" + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $0\src35__data_o$next[3:0]$11484 + attribute \src "libresoc.v:180017.3-180018.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:171595.3-171624.6" - wire $0\wr_detect$10[0:0]$11441 - attribute \src "libresoc.v:171665.3-171694.6" - wire $0\wr_detect$13[0:0]$11455 - attribute \src "libresoc.v:171455.3-171484.6" - wire $0\wr_detect$4[0:0]$11413 - attribute \src "libresoc.v:171525.3-171554.6" - wire $0\wr_detect$7[0:0]$11427 - attribute \src "libresoc.v:171358.3-171387.6" + attribute \src "libresoc.v:180300.3-180329.6" + wire $0\wr_detect$10[0:0]$11506 + attribute \src "libresoc.v:180370.3-180399.6" + wire $0\wr_detect$13[0:0]$11520 + attribute \src "libresoc.v:180160.3-180189.6" + wire $0\wr_detect$4[0:0]$11478 + attribute \src "libresoc.v:180230.3-180259.6" + wire $0\wr_detect$7[0:0]$11492 + attribute \src "libresoc.v:180063.3-180092.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:171625.3-171664.6" - wire width 4 $1\r25__data_o$next[3:0]$11448 - attribute \src "libresoc.v:171250.13-171250.31" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $1\r25__data_o$next[3:0]$11513 + attribute \src "libresoc.v:179955.13-179955.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:171555.3-171594.6" - wire width 4 $1\r5__data_o$next[3:0]$11434 - attribute \src "libresoc.v:171257.13-171257.30" + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $1\r5__data_o$next[3:0]$11499 + attribute \src "libresoc.v:179962.13-179962.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:171388.3-171414.6" - wire width 4 $1\reg$next[3:0]$11400 - attribute \src "libresoc.v:171263.13-171263.25" + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $1\reg$next[3:0]$11465 + attribute \src "libresoc.v:179968.13-179968.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:171318.3-171357.6" - wire width 4 $1\src15__data_o$next[3:0]$11391 - attribute \src "libresoc.v:171268.13-171268.33" + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $1\src15__data_o$next[3:0]$11456 + attribute \src "libresoc.v:179973.13-179973.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:171415.3-171454.6" - wire width 4 $1\src25__data_o$next[3:0]$11406 - attribute \src "libresoc.v:171275.13-171275.33" + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $1\src25__data_o$next[3:0]$11471 + attribute \src "libresoc.v:179980.13-179980.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:171485.3-171524.6" - wire width 4 $1\src35__data_o$next[3:0]$11420 - attribute \src "libresoc.v:171282.13-171282.33" + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $1\src35__data_o$next[3:0]$11485 + attribute \src "libresoc.v:179987.13-179987.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:171595.3-171624.6" - wire $1\wr_detect$10[0:0]$11442 - attribute \src "libresoc.v:171665.3-171694.6" - wire $1\wr_detect$13[0:0]$11456 - attribute \src "libresoc.v:171455.3-171484.6" - wire $1\wr_detect$4[0:0]$11414 - attribute \src "libresoc.v:171525.3-171554.6" - wire $1\wr_detect$7[0:0]$11428 - attribute \src "libresoc.v:171358.3-171387.6" + attribute \src "libresoc.v:180300.3-180329.6" + wire $1\wr_detect$10[0:0]$11507 + attribute \src "libresoc.v:180370.3-180399.6" + wire $1\wr_detect$13[0:0]$11521 + attribute \src "libresoc.v:180160.3-180189.6" + wire $1\wr_detect$4[0:0]$11479 + attribute \src "libresoc.v:180230.3-180259.6" + wire $1\wr_detect$7[0:0]$11493 + attribute \src "libresoc.v:180063.3-180092.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:171625.3-171664.6" - wire width 4 $2\r25__data_o$next[3:0]$11449 - attribute \src "libresoc.v:171555.3-171594.6" - wire width 4 $2\r5__data_o$next[3:0]$11435 - attribute \src "libresoc.v:171388.3-171414.6" - wire width 4 $2\reg$next[3:0]$11401 - attribute \src "libresoc.v:171318.3-171357.6" - wire width 4 $2\src15__data_o$next[3:0]$11392 - attribute \src "libresoc.v:171415.3-171454.6" - wire width 4 $2\src25__data_o$next[3:0]$11407 - attribute \src "libresoc.v:171485.3-171524.6" - wire width 4 $2\src35__data_o$next[3:0]$11421 - attribute \src "libresoc.v:171595.3-171624.6" - wire $2\wr_detect$10[0:0]$11443 - attribute \src "libresoc.v:171665.3-171694.6" - wire $2\wr_detect$13[0:0]$11457 - attribute \src "libresoc.v:171455.3-171484.6" - wire $2\wr_detect$4[0:0]$11415 - attribute \src "libresoc.v:171525.3-171554.6" - wire $2\wr_detect$7[0:0]$11429 - attribute \src "libresoc.v:171358.3-171387.6" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $2\r25__data_o$next[3:0]$11514 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $2\r5__data_o$next[3:0]$11500 + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $2\reg$next[3:0]$11466 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $2\src15__data_o$next[3:0]$11457 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $2\src25__data_o$next[3:0]$11472 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $2\src35__data_o$next[3:0]$11486 + attribute \src "libresoc.v:180300.3-180329.6" + wire $2\wr_detect$10[0:0]$11508 + attribute \src "libresoc.v:180370.3-180399.6" + wire $2\wr_detect$13[0:0]$11522 + attribute \src "libresoc.v:180160.3-180189.6" + wire $2\wr_detect$4[0:0]$11480 + attribute \src "libresoc.v:180230.3-180259.6" + wire $2\wr_detect$7[0:0]$11494 + attribute \src "libresoc.v:180063.3-180092.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:171625.3-171664.6" - wire width 4 $3\r25__data_o$next[3:0]$11450 - attribute \src "libresoc.v:171555.3-171594.6" - wire width 4 $3\r5__data_o$next[3:0]$11436 - attribute \src "libresoc.v:171388.3-171414.6" - wire width 4 $3\reg$next[3:0]$11402 - attribute \src "libresoc.v:171318.3-171357.6" - wire width 4 $3\src15__data_o$next[3:0]$11393 - attribute \src "libresoc.v:171415.3-171454.6" - wire width 4 $3\src25__data_o$next[3:0]$11408 - attribute \src "libresoc.v:171485.3-171524.6" - wire width 4 $3\src35__data_o$next[3:0]$11422 - attribute \src "libresoc.v:171595.3-171624.6" - wire $3\wr_detect$10[0:0]$11444 - attribute \src "libresoc.v:171665.3-171694.6" - wire $3\wr_detect$13[0:0]$11458 - attribute \src "libresoc.v:171455.3-171484.6" - wire $3\wr_detect$4[0:0]$11416 - attribute \src "libresoc.v:171525.3-171554.6" - wire $3\wr_detect$7[0:0]$11430 - attribute \src "libresoc.v:171358.3-171387.6" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $3\r25__data_o$next[3:0]$11515 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $3\r5__data_o$next[3:0]$11501 + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $3\reg$next[3:0]$11467 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $3\src15__data_o$next[3:0]$11458 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $3\src25__data_o$next[3:0]$11473 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $3\src35__data_o$next[3:0]$11487 + attribute \src "libresoc.v:180300.3-180329.6" + wire $3\wr_detect$10[0:0]$11509 + attribute \src "libresoc.v:180370.3-180399.6" + wire $3\wr_detect$13[0:0]$11523 + attribute \src "libresoc.v:180160.3-180189.6" + wire $3\wr_detect$4[0:0]$11481 + attribute \src "libresoc.v:180230.3-180259.6" + wire $3\wr_detect$7[0:0]$11495 + attribute \src "libresoc.v:180063.3-180092.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:171625.3-171664.6" - wire width 4 $4\r25__data_o$next[3:0]$11451 - attribute \src "libresoc.v:171555.3-171594.6" - wire width 4 $4\r5__data_o$next[3:0]$11437 - attribute \src "libresoc.v:171388.3-171414.6" - wire width 4 $4\reg$next[3:0]$11403 - attribute \src "libresoc.v:171318.3-171357.6" - wire width 4 $4\src15__data_o$next[3:0]$11394 - attribute \src "libresoc.v:171415.3-171454.6" - wire width 4 $4\src25__data_o$next[3:0]$11409 - attribute \src "libresoc.v:171485.3-171524.6" - wire width 4 $4\src35__data_o$next[3:0]$11423 - attribute \src "libresoc.v:171595.3-171624.6" - wire $4\wr_detect$10[0:0]$11445 - attribute \src "libresoc.v:171665.3-171694.6" - wire $4\wr_detect$13[0:0]$11459 - attribute \src "libresoc.v:171455.3-171484.6" - wire $4\wr_detect$4[0:0]$11417 - attribute \src "libresoc.v:171525.3-171554.6" - wire $4\wr_detect$7[0:0]$11431 - attribute \src "libresoc.v:171358.3-171387.6" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $4\r25__data_o$next[3:0]$11516 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $4\r5__data_o$next[3:0]$11502 + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $4\reg$next[3:0]$11468 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $4\src15__data_o$next[3:0]$11459 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $4\src25__data_o$next[3:0]$11474 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $4\src35__data_o$next[3:0]$11488 + attribute \src "libresoc.v:180300.3-180329.6" + wire $4\wr_detect$10[0:0]$11510 + attribute \src "libresoc.v:180370.3-180399.6" + wire $4\wr_detect$13[0:0]$11524 + attribute \src "libresoc.v:180160.3-180189.6" + wire $4\wr_detect$4[0:0]$11482 + attribute \src "libresoc.v:180230.3-180259.6" + wire $4\wr_detect$7[0:0]$11496 + attribute \src "libresoc.v:180063.3-180092.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:171625.3-171664.6" - wire width 4 $5\r25__data_o$next[3:0]$11452 - attribute \src "libresoc.v:171555.3-171594.6" - wire width 4 $5\r5__data_o$next[3:0]$11438 - attribute \src "libresoc.v:171318.3-171357.6" - wire width 4 $5\src15__data_o$next[3:0]$11395 - attribute \src "libresoc.v:171415.3-171454.6" - wire width 4 $5\src25__data_o$next[3:0]$11410 - attribute \src "libresoc.v:171485.3-171524.6" - wire width 4 $5\src35__data_o$next[3:0]$11424 - attribute \src "libresoc.v:171625.3-171664.6" - wire width 4 $6\r25__data_o$next[3:0]$11453 - attribute \src "libresoc.v:171555.3-171594.6" - wire width 4 $6\r5__data_o$next[3:0]$11439 - attribute \src "libresoc.v:171318.3-171357.6" - wire width 4 $6\src15__data_o$next[3:0]$11396 - attribute \src "libresoc.v:171415.3-171454.6" - wire width 4 $6\src25__data_o$next[3:0]$11411 - attribute \src "libresoc.v:171485.3-171524.6" - wire width 4 $6\src35__data_o$next[3:0]$11425 - attribute \src "libresoc.v:171301.17-171301.104" - wire $not$libresoc.v:171301$11378_Y - attribute \src "libresoc.v:171302.18-171302.105" - wire $not$libresoc.v:171302$11379_Y - attribute \src "libresoc.v:171303.17-171303.100" - wire $not$libresoc.v:171303$11380_Y - attribute \src "libresoc.v:171304.17-171304.103" - wire $not$libresoc.v:171304$11381_Y - attribute \src "libresoc.v:171305.17-171305.103" - wire $not$libresoc.v:171305$11382_Y + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $5\r25__data_o$next[3:0]$11517 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $5\r5__data_o$next[3:0]$11503 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $5\src15__data_o$next[3:0]$11460 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $5\src25__data_o$next[3:0]$11475 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $5\src35__data_o$next[3:0]$11489 + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $6\r25__data_o$next[3:0]$11518 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $6\r5__data_o$next[3:0]$11504 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $6\src15__data_o$next[3:0]$11461 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $6\src25__data_o$next[3:0]$11476 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $6\src35__data_o$next[3:0]$11490 + attribute \src "libresoc.v:180006.17-180006.104" + wire $not$libresoc.v:180006$11443_Y + attribute \src "libresoc.v:180007.18-180007.105" + wire $not$libresoc.v:180007$11444_Y + attribute \src "libresoc.v:180008.17-180008.100" + wire $not$libresoc.v:180008$11445_Y + attribute \src "libresoc.v:180009.17-180009.103" + wire $not$libresoc.v:180009$11446_Y + attribute \src "libresoc.v:180010.17-180010.103" + wire $not$libresoc.v:180010$11447_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -356125,57 +371122,57 @@ module \reg_5 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest15__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest25__wen - attribute \src "libresoc.v:171225.7-171225.15" + attribute \src "libresoc.v:179930.7-179930.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r25__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r5__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r5__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src15__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src15__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src15__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src25__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src35__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src35__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src35__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w5__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w5__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -356188,152 +371185,152 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171301$11378 + cell $not $not$libresoc.v:180006$11443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:171301$11378_Y + connect \Y $not$libresoc.v:180006$11443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171302$11379 + cell $not $not$libresoc.v:180007$11444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:171302$11379_Y + connect \Y $not$libresoc.v:180007$11444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171303$11380 + cell $not $not$libresoc.v:180008$11445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:171303$11380_Y + connect \Y $not$libresoc.v:180008$11445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171304$11381 + cell $not $not$libresoc.v:180009$11446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:171304$11381_Y + connect \Y $not$libresoc.v:180009$11446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171305$11382 + cell $not $not$libresoc.v:180010$11447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:171305$11382_Y + connect \Y $not$libresoc.v:180010$11447_Y end - attribute \src "libresoc.v:171225.7-171225.20" - process $proc$libresoc.v:171225$11460 + attribute \src "libresoc.v:179930.7-179930.20" + process $proc$libresoc.v:179930$11525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171250.13-171250.31" - process $proc$libresoc.v:171250$11461 + attribute \src "libresoc.v:179955.13-179955.31" + process $proc$libresoc.v:179955$11526 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:171257.13-171257.30" - process $proc$libresoc.v:171257$11462 + attribute \src "libresoc.v:179962.13-179962.30" + process $proc$libresoc.v:179962$11527 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:171263.13-171263.25" - process $proc$libresoc.v:171263$11463 + attribute \src "libresoc.v:179968.13-179968.25" + process $proc$libresoc.v:179968$11528 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:171268.13-171268.33" - process $proc$libresoc.v:171268$11464 + attribute \src "libresoc.v:179973.13-179973.33" + process $proc$libresoc.v:179973$11529 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:171275.13-171275.33" - process $proc$libresoc.v:171275$11465 + attribute \src "libresoc.v:179980.13-179980.33" + process $proc$libresoc.v:179980$11530 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:171282.13-171282.33" - process $proc$libresoc.v:171282$11466 + attribute \src "libresoc.v:179987.13-179987.33" + process $proc$libresoc.v:179987$11531 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:171306.3-171307.25" - process $proc$libresoc.v:171306$11383 + attribute \src "libresoc.v:180011.3-180012.25" + process $proc$libresoc.v:180011$11448 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:171308.3-171309.39" - process $proc$libresoc.v:171308$11384 + attribute \src "libresoc.v:180013.3-180014.39" + process $proc$libresoc.v:180013$11449 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:171310.3-171311.37" - process $proc$libresoc.v:171310$11385 + attribute \src "libresoc.v:180015.3-180016.37" + process $proc$libresoc.v:180015$11450 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:171312.3-171313.43" - process $proc$libresoc.v:171312$11386 + attribute \src "libresoc.v:180017.3-180018.43" + process $proc$libresoc.v:180017$11451 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:171314.3-171315.43" - process $proc$libresoc.v:171314$11387 + attribute \src "libresoc.v:180019.3-180020.43" + process $proc$libresoc.v:180019$11452 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:171316.3-171317.43" - process $proc$libresoc.v:171316$11388 + attribute \src "libresoc.v:180021.3-180022.43" + process $proc$libresoc.v:180021$11453 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:171318.3-171357.6" - process $proc$libresoc.v:171318$11389 + attribute \src "libresoc.v:180023.3-180062.6" + process $proc$libresoc.v:180023$11454 assign { } { } assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11390 $6\src15__data_o$next[3:0]$11396 - attribute \src "libresoc.v:171319.5-171319.29" + assign $0\src15__data_o$next[3:0]$11455 $6\src15__data_o$next[3:0]$11461 + attribute \src "libresoc.v:180024.5-180024.29" switch \initial - attribute \src "libresoc.v:171319.9-171319.17" + attribute \src "libresoc.v:180024.9-180024.17" case 1'1 case end @@ -356345,66 +371342,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11391 $5\src15__data_o$next[3:0]$11395 + assign $1\src15__data_o$next[3:0]$11456 $5\src15__data_o$next[3:0]$11460 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11392 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11457 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11392 4'0000 + assign $2\src15__data_o$next[3:0]$11457 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11393 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11458 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11393 $2\src15__data_o$next[3:0]$11392 + assign $3\src15__data_o$next[3:0]$11458 $2\src15__data_o$next[3:0]$11457 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11394 \w5__data_i + assign $4\src15__data_o$next[3:0]$11459 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11394 $3\src15__data_o$next[3:0]$11393 + assign $4\src15__data_o$next[3:0]$11459 $3\src15__data_o$next[3:0]$11458 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11395 \reg + assign $5\src15__data_o$next[3:0]$11460 \reg case - assign $5\src15__data_o$next[3:0]$11395 $4\src15__data_o$next[3:0]$11394 + assign $5\src15__data_o$next[3:0]$11460 $4\src15__data_o$next[3:0]$11459 end case - assign $1\src15__data_o$next[3:0]$11391 4'0000 + assign $1\src15__data_o$next[3:0]$11456 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11396 4'0000 + assign $6\src15__data_o$next[3:0]$11461 4'0000 case - assign $6\src15__data_o$next[3:0]$11396 $1\src15__data_o$next[3:0]$11391 + assign $6\src15__data_o$next[3:0]$11461 $1\src15__data_o$next[3:0]$11456 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11390 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11455 end - attribute \src "libresoc.v:171358.3-171387.6" - process $proc$libresoc.v:171358$11397 + attribute \src "libresoc.v:180063.3-180092.6" + process $proc$libresoc.v:180063$11462 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:171359.5-171359.29" + attribute \src "libresoc.v:180064.5-180064.29" switch \initial - attribute \src "libresoc.v:171359.9-171359.17" + attribute \src "libresoc.v:180064.9-180064.17" case 1'1 case end @@ -356450,17 +371447,17 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:171388.3-171414.6" - process $proc$libresoc.v:171388$11398 + attribute \src "libresoc.v:180093.3-180119.6" + process $proc$libresoc.v:180093$11463 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11399 $4\reg$next[3:0]$11403 - attribute \src "libresoc.v:171389.5-171389.29" + assign $0\reg$next[3:0]$11464 $4\reg$next[3:0]$11468 + attribute \src "libresoc.v:180094.5-180094.29" switch \initial - attribute \src "libresoc.v:171389.9-171389.17" + attribute \src "libresoc.v:180094.9-180094.17" case 1'1 case end @@ -356469,49 +371466,49 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11400 \dest15__data_i + assign $1\reg$next[3:0]$11465 \dest15__data_i case - assign $1\reg$next[3:0]$11400 \reg + assign $1\reg$next[3:0]$11465 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11401 \dest25__data_i + assign $2\reg$next[3:0]$11466 \dest25__data_i case - assign $2\reg$next[3:0]$11401 $1\reg$next[3:0]$11400 + assign $2\reg$next[3:0]$11466 $1\reg$next[3:0]$11465 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11402 \w5__data_i + assign $3\reg$next[3:0]$11467 \w5__data_i case - assign $3\reg$next[3:0]$11402 $2\reg$next[3:0]$11401 + assign $3\reg$next[3:0]$11467 $2\reg$next[3:0]$11466 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11403 4'0000 + assign $4\reg$next[3:0]$11468 4'0000 case - assign $4\reg$next[3:0]$11403 $3\reg$next[3:0]$11402 + assign $4\reg$next[3:0]$11468 $3\reg$next[3:0]$11467 end sync always - update \reg$next $0\reg$next[3:0]$11399 + update \reg$next $0\reg$next[3:0]$11464 end - attribute \src "libresoc.v:171415.3-171454.6" - process $proc$libresoc.v:171415$11404 + attribute \src "libresoc.v:180120.3-180159.6" + process $proc$libresoc.v:180120$11469 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11405 $6\src25__data_o$next[3:0]$11411 - attribute \src "libresoc.v:171416.5-171416.29" + assign $0\src25__data_o$next[3:0]$11470 $6\src25__data_o$next[3:0]$11476 + attribute \src "libresoc.v:180121.5-180121.29" switch \initial - attribute \src "libresoc.v:171416.9-171416.17" + attribute \src "libresoc.v:180121.9-180121.17" case 1'1 case end @@ -356523,66 +371520,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11406 $5\src25__data_o$next[3:0]$11410 + assign $1\src25__data_o$next[3:0]$11471 $5\src25__data_o$next[3:0]$11475 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11407 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11472 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11407 4'0000 + assign $2\src25__data_o$next[3:0]$11472 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11408 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11473 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11408 $2\src25__data_o$next[3:0]$11407 + assign $3\src25__data_o$next[3:0]$11473 $2\src25__data_o$next[3:0]$11472 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11409 \w5__data_i + assign $4\src25__data_o$next[3:0]$11474 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11409 $3\src25__data_o$next[3:0]$11408 + assign $4\src25__data_o$next[3:0]$11474 $3\src25__data_o$next[3:0]$11473 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11410 \reg + assign $5\src25__data_o$next[3:0]$11475 \reg case - assign $5\src25__data_o$next[3:0]$11410 $4\src25__data_o$next[3:0]$11409 + assign $5\src25__data_o$next[3:0]$11475 $4\src25__data_o$next[3:0]$11474 end case - assign $1\src25__data_o$next[3:0]$11406 4'0000 + assign $1\src25__data_o$next[3:0]$11471 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11411 4'0000 + assign $6\src25__data_o$next[3:0]$11476 4'0000 case - assign $6\src25__data_o$next[3:0]$11411 $1\src25__data_o$next[3:0]$11406 + assign $6\src25__data_o$next[3:0]$11476 $1\src25__data_o$next[3:0]$11471 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11405 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11470 end - attribute \src "libresoc.v:171455.3-171484.6" - process $proc$libresoc.v:171455$11412 + attribute \src "libresoc.v:180160.3-180189.6" + process $proc$libresoc.v:180160$11477 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11413 $1\wr_detect$4[0:0]$11414 - attribute \src "libresoc.v:171456.5-171456.29" + assign $0\wr_detect$4[0:0]$11478 $1\wr_detect$4[0:0]$11479 + attribute \src "libresoc.v:180161.5-180161.29" switch \initial - attribute \src "libresoc.v:171456.9-171456.17" + attribute \src "libresoc.v:180161.9-180161.17" case 1'1 case end @@ -356594,49 +371591,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11414 $4\wr_detect$4[0:0]$11417 + assign $1\wr_detect$4[0:0]$11479 $4\wr_detect$4[0:0]$11482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11415 1'1 + assign $2\wr_detect$4[0:0]$11480 1'1 case - assign $2\wr_detect$4[0:0]$11415 1'0 + assign $2\wr_detect$4[0:0]$11480 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11416 1'1 + assign $3\wr_detect$4[0:0]$11481 1'1 case - assign $3\wr_detect$4[0:0]$11416 $2\wr_detect$4[0:0]$11415 + assign $3\wr_detect$4[0:0]$11481 $2\wr_detect$4[0:0]$11480 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11417 1'1 + assign $4\wr_detect$4[0:0]$11482 1'1 case - assign $4\wr_detect$4[0:0]$11417 $3\wr_detect$4[0:0]$11416 + assign $4\wr_detect$4[0:0]$11482 $3\wr_detect$4[0:0]$11481 end case - assign $1\wr_detect$4[0:0]$11414 1'0 + assign $1\wr_detect$4[0:0]$11479 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11413 + update \wr_detect$4 $0\wr_detect$4[0:0]$11478 end - attribute \src "libresoc.v:171485.3-171524.6" - process $proc$libresoc.v:171485$11418 + attribute \src "libresoc.v:180190.3-180229.6" + process $proc$libresoc.v:180190$11483 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11419 $6\src35__data_o$next[3:0]$11425 - attribute \src "libresoc.v:171486.5-171486.29" + assign $0\src35__data_o$next[3:0]$11484 $6\src35__data_o$next[3:0]$11490 + attribute \src "libresoc.v:180191.5-180191.29" switch \initial - attribute \src "libresoc.v:171486.9-171486.17" + attribute \src "libresoc.v:180191.9-180191.17" case 1'1 case end @@ -356648,66 +371645,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11420 $5\src35__data_o$next[3:0]$11424 + assign $1\src35__data_o$next[3:0]$11485 $5\src35__data_o$next[3:0]$11489 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11421 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11486 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11421 4'0000 + assign $2\src35__data_o$next[3:0]$11486 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11422 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11487 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11422 $2\src35__data_o$next[3:0]$11421 + assign $3\src35__data_o$next[3:0]$11487 $2\src35__data_o$next[3:0]$11486 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11423 \w5__data_i + assign $4\src35__data_o$next[3:0]$11488 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11423 $3\src35__data_o$next[3:0]$11422 + assign $4\src35__data_o$next[3:0]$11488 $3\src35__data_o$next[3:0]$11487 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11424 \reg + assign $5\src35__data_o$next[3:0]$11489 \reg case - assign $5\src35__data_o$next[3:0]$11424 $4\src35__data_o$next[3:0]$11423 + assign $5\src35__data_o$next[3:0]$11489 $4\src35__data_o$next[3:0]$11488 end case - assign $1\src35__data_o$next[3:0]$11420 4'0000 + assign $1\src35__data_o$next[3:0]$11485 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11425 4'0000 + assign $6\src35__data_o$next[3:0]$11490 4'0000 case - assign $6\src35__data_o$next[3:0]$11425 $1\src35__data_o$next[3:0]$11420 + assign $6\src35__data_o$next[3:0]$11490 $1\src35__data_o$next[3:0]$11485 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11419 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11484 end - attribute \src "libresoc.v:171525.3-171554.6" - process $proc$libresoc.v:171525$11426 + attribute \src "libresoc.v:180230.3-180259.6" + process $proc$libresoc.v:180230$11491 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11427 $1\wr_detect$7[0:0]$11428 - attribute \src "libresoc.v:171526.5-171526.29" + assign $0\wr_detect$7[0:0]$11492 $1\wr_detect$7[0:0]$11493 + attribute \src "libresoc.v:180231.5-180231.29" switch \initial - attribute \src "libresoc.v:171526.9-171526.17" + attribute \src "libresoc.v:180231.9-180231.17" case 1'1 case end @@ -356719,49 +371716,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11428 $4\wr_detect$7[0:0]$11431 + assign $1\wr_detect$7[0:0]$11493 $4\wr_detect$7[0:0]$11496 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11429 1'1 + assign $2\wr_detect$7[0:0]$11494 1'1 case - assign $2\wr_detect$7[0:0]$11429 1'0 + assign $2\wr_detect$7[0:0]$11494 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11430 1'1 + assign $3\wr_detect$7[0:0]$11495 1'1 case - assign $3\wr_detect$7[0:0]$11430 $2\wr_detect$7[0:0]$11429 + assign $3\wr_detect$7[0:0]$11495 $2\wr_detect$7[0:0]$11494 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11431 1'1 + assign $4\wr_detect$7[0:0]$11496 1'1 case - assign $4\wr_detect$7[0:0]$11431 $3\wr_detect$7[0:0]$11430 + assign $4\wr_detect$7[0:0]$11496 $3\wr_detect$7[0:0]$11495 end case - assign $1\wr_detect$7[0:0]$11428 1'0 + assign $1\wr_detect$7[0:0]$11493 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11427 + update \wr_detect$7 $0\wr_detect$7[0:0]$11492 end - attribute \src "libresoc.v:171555.3-171594.6" - process $proc$libresoc.v:171555$11432 + attribute \src "libresoc.v:180260.3-180299.6" + process $proc$libresoc.v:180260$11497 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11433 $6\r5__data_o$next[3:0]$11439 - attribute \src "libresoc.v:171556.5-171556.29" + assign $0\r5__data_o$next[3:0]$11498 $6\r5__data_o$next[3:0]$11504 + attribute \src "libresoc.v:180261.5-180261.29" switch \initial - attribute \src "libresoc.v:171556.9-171556.17" + attribute \src "libresoc.v:180261.9-180261.17" case 1'1 case end @@ -356773,66 +371770,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11434 $5\r5__data_o$next[3:0]$11438 + assign $1\r5__data_o$next[3:0]$11499 $5\r5__data_o$next[3:0]$11503 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11435 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11500 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11435 4'0000 + assign $2\r5__data_o$next[3:0]$11500 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11436 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11501 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11436 $2\r5__data_o$next[3:0]$11435 + assign $3\r5__data_o$next[3:0]$11501 $2\r5__data_o$next[3:0]$11500 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11437 \w5__data_i + assign $4\r5__data_o$next[3:0]$11502 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11437 $3\r5__data_o$next[3:0]$11436 + assign $4\r5__data_o$next[3:0]$11502 $3\r5__data_o$next[3:0]$11501 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11438 \reg + assign $5\r5__data_o$next[3:0]$11503 \reg case - assign $5\r5__data_o$next[3:0]$11438 $4\r5__data_o$next[3:0]$11437 + assign $5\r5__data_o$next[3:0]$11503 $4\r5__data_o$next[3:0]$11502 end case - assign $1\r5__data_o$next[3:0]$11434 4'0000 + assign $1\r5__data_o$next[3:0]$11499 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11439 4'0000 + assign $6\r5__data_o$next[3:0]$11504 4'0000 case - assign $6\r5__data_o$next[3:0]$11439 $1\r5__data_o$next[3:0]$11434 + assign $6\r5__data_o$next[3:0]$11504 $1\r5__data_o$next[3:0]$11499 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11433 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11498 end - attribute \src "libresoc.v:171595.3-171624.6" - process $proc$libresoc.v:171595$11440 + attribute \src "libresoc.v:180300.3-180329.6" + process $proc$libresoc.v:180300$11505 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11441 $1\wr_detect$10[0:0]$11442 - attribute \src "libresoc.v:171596.5-171596.29" + assign $0\wr_detect$10[0:0]$11506 $1\wr_detect$10[0:0]$11507 + attribute \src "libresoc.v:180301.5-180301.29" switch \initial - attribute \src "libresoc.v:171596.9-171596.17" + attribute \src "libresoc.v:180301.9-180301.17" case 1'1 case end @@ -356844,49 +371841,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11442 $4\wr_detect$10[0:0]$11445 + assign $1\wr_detect$10[0:0]$11507 $4\wr_detect$10[0:0]$11510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11443 1'1 + assign $2\wr_detect$10[0:0]$11508 1'1 case - assign $2\wr_detect$10[0:0]$11443 1'0 + assign $2\wr_detect$10[0:0]$11508 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11444 1'1 + assign $3\wr_detect$10[0:0]$11509 1'1 case - assign $3\wr_detect$10[0:0]$11444 $2\wr_detect$10[0:0]$11443 + assign $3\wr_detect$10[0:0]$11509 $2\wr_detect$10[0:0]$11508 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11445 1'1 + assign $4\wr_detect$10[0:0]$11510 1'1 case - assign $4\wr_detect$10[0:0]$11445 $3\wr_detect$10[0:0]$11444 + assign $4\wr_detect$10[0:0]$11510 $3\wr_detect$10[0:0]$11509 end case - assign $1\wr_detect$10[0:0]$11442 1'0 + assign $1\wr_detect$10[0:0]$11507 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11441 + update \wr_detect$10 $0\wr_detect$10[0:0]$11506 end - attribute \src "libresoc.v:171625.3-171664.6" - process $proc$libresoc.v:171625$11446 + attribute \src "libresoc.v:180330.3-180369.6" + process $proc$libresoc.v:180330$11511 assign { } { } assign { } { } assign { } { } - assign $0\r25__data_o$next[3:0]$11447 $6\r25__data_o$next[3:0]$11453 - attribute \src "libresoc.v:171626.5-171626.29" + assign $0\r25__data_o$next[3:0]$11512 $6\r25__data_o$next[3:0]$11518 + attribute \src "libresoc.v:180331.5-180331.29" switch \initial - attribute \src "libresoc.v:171626.9-171626.17" + attribute \src "libresoc.v:180331.9-180331.17" case 1'1 case end @@ -356898,66 +371895,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r25__data_o$next[3:0]$11448 $5\r25__data_o$next[3:0]$11452 + assign $1\r25__data_o$next[3:0]$11513 $5\r25__data_o$next[3:0]$11517 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r25__data_o$next[3:0]$11449 \dest15__data_i + assign $2\r25__data_o$next[3:0]$11514 \dest15__data_i case - assign $2\r25__data_o$next[3:0]$11449 4'0000 + assign $2\r25__data_o$next[3:0]$11514 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r25__data_o$next[3:0]$11450 \dest25__data_i + assign $3\r25__data_o$next[3:0]$11515 \dest25__data_i case - assign $3\r25__data_o$next[3:0]$11450 $2\r25__data_o$next[3:0]$11449 + assign $3\r25__data_o$next[3:0]$11515 $2\r25__data_o$next[3:0]$11514 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r25__data_o$next[3:0]$11451 \w5__data_i + assign $4\r25__data_o$next[3:0]$11516 \w5__data_i case - assign $4\r25__data_o$next[3:0]$11451 $3\r25__data_o$next[3:0]$11450 + assign $4\r25__data_o$next[3:0]$11516 $3\r25__data_o$next[3:0]$11515 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r25__data_o$next[3:0]$11452 \reg + assign $5\r25__data_o$next[3:0]$11517 \reg case - assign $5\r25__data_o$next[3:0]$11452 $4\r25__data_o$next[3:0]$11451 + assign $5\r25__data_o$next[3:0]$11517 $4\r25__data_o$next[3:0]$11516 end case - assign $1\r25__data_o$next[3:0]$11448 4'0000 + assign $1\r25__data_o$next[3:0]$11513 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r25__data_o$next[3:0]$11453 4'0000 + assign $6\r25__data_o$next[3:0]$11518 4'0000 case - assign $6\r25__data_o$next[3:0]$11453 $1\r25__data_o$next[3:0]$11448 + assign $6\r25__data_o$next[3:0]$11518 $1\r25__data_o$next[3:0]$11513 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11447 + update \r25__data_o$next $0\r25__data_o$next[3:0]$11512 end - attribute \src "libresoc.v:171665.3-171694.6" - process $proc$libresoc.v:171665$11454 + attribute \src "libresoc.v:180370.3-180399.6" + process $proc$libresoc.v:180370$11519 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11455 $1\wr_detect$13[0:0]$11456 - attribute \src "libresoc.v:171666.5-171666.29" + assign $0\wr_detect$13[0:0]$11520 $1\wr_detect$13[0:0]$11521 + attribute \src "libresoc.v:180371.5-180371.29" switch \initial - attribute \src "libresoc.v:171666.9-171666.17" + attribute \src "libresoc.v:180371.9-180371.17" case 1'1 case end @@ -356969,217 +371966,217 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11456 $4\wr_detect$13[0:0]$11459 + assign $1\wr_detect$13[0:0]$11521 $4\wr_detect$13[0:0]$11524 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11457 1'1 + assign $2\wr_detect$13[0:0]$11522 1'1 case - assign $2\wr_detect$13[0:0]$11457 1'0 + assign $2\wr_detect$13[0:0]$11522 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11458 1'1 + assign $3\wr_detect$13[0:0]$11523 1'1 case - assign $3\wr_detect$13[0:0]$11458 $2\wr_detect$13[0:0]$11457 + assign $3\wr_detect$13[0:0]$11523 $2\wr_detect$13[0:0]$11522 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11459 1'1 + assign $4\wr_detect$13[0:0]$11524 1'1 case - assign $4\wr_detect$13[0:0]$11459 $3\wr_detect$13[0:0]$11458 + assign $4\wr_detect$13[0:0]$11524 $3\wr_detect$13[0:0]$11523 end case - assign $1\wr_detect$13[0:0]$11456 1'0 + assign $1\wr_detect$13[0:0]$11521 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11455 + update \wr_detect$13 $0\wr_detect$13[0:0]$11520 end - connect \$9 $not$libresoc.v:171301$11378_Y - connect \$12 $not$libresoc.v:171302$11379_Y - connect \$1 $not$libresoc.v:171303$11380_Y - connect \$3 $not$libresoc.v:171304$11381_Y - connect \$6 $not$libresoc.v:171305$11382_Y + connect \$9 $not$libresoc.v:180006$11443_Y + connect \$12 $not$libresoc.v:180007$11444_Y + connect \$1 $not$libresoc.v:180008$11445_Y + connect \$3 $not$libresoc.v:180009$11446_Y + connect \$6 $not$libresoc.v:180010$11447_Y end -attribute \src "libresoc.v:171699.1-172170.10" +attribute \src "libresoc.v:180404.1-180875.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:171700.7-171700.20" + attribute \src "libresoc.v:180405.7-180405.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172100.3-172139.6" - wire width 4 $0\r26__data_o$next[3:0]$11536 - attribute \src "libresoc.v:171783.3-171784.39" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $0\r26__data_o$next[3:0]$11601 + attribute \src "libresoc.v:180488.3-180489.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:172030.3-172069.6" - wire width 4 $0\r6__data_o$next[3:0]$11522 - attribute \src "libresoc.v:171785.3-171786.37" + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $0\r6__data_o$next[3:0]$11587 + attribute \src "libresoc.v:180490.3-180491.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:171863.3-171889.6" - wire width 4 $0\reg$next[3:0]$11488 - attribute \src "libresoc.v:171781.3-171782.25" + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $0\reg$next[3:0]$11553 + attribute \src "libresoc.v:180486.3-180487.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:171793.3-171832.6" - wire width 4 $0\src16__data_o$next[3:0]$11479 - attribute \src "libresoc.v:171791.3-171792.43" + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $0\src16__data_o$next[3:0]$11544 + attribute \src "libresoc.v:180496.3-180497.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:171890.3-171929.6" - wire width 4 $0\src26__data_o$next[3:0]$11494 - attribute \src "libresoc.v:171789.3-171790.43" + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $0\src26__data_o$next[3:0]$11559 + attribute \src "libresoc.v:180494.3-180495.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:171960.3-171999.6" - wire width 4 $0\src36__data_o$next[3:0]$11508 - attribute \src "libresoc.v:171787.3-171788.43" + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $0\src36__data_o$next[3:0]$11573 + attribute \src "libresoc.v:180492.3-180493.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:172070.3-172099.6" - wire $0\wr_detect$10[0:0]$11530 - attribute \src "libresoc.v:172140.3-172169.6" - wire $0\wr_detect$13[0:0]$11544 - attribute \src "libresoc.v:171930.3-171959.6" - wire $0\wr_detect$4[0:0]$11502 - attribute \src "libresoc.v:172000.3-172029.6" - wire $0\wr_detect$7[0:0]$11516 - attribute \src "libresoc.v:171833.3-171862.6" + attribute \src "libresoc.v:180775.3-180804.6" + wire $0\wr_detect$10[0:0]$11595 + attribute \src "libresoc.v:180845.3-180874.6" + wire $0\wr_detect$13[0:0]$11609 + attribute \src "libresoc.v:180635.3-180664.6" + wire $0\wr_detect$4[0:0]$11567 + attribute \src "libresoc.v:180705.3-180734.6" + wire $0\wr_detect$7[0:0]$11581 + attribute \src "libresoc.v:180538.3-180567.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:172100.3-172139.6" - wire width 4 $1\r26__data_o$next[3:0]$11537 - attribute \src "libresoc.v:171725.13-171725.31" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $1\r26__data_o$next[3:0]$11602 + attribute \src "libresoc.v:180430.13-180430.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:172030.3-172069.6" - wire width 4 $1\r6__data_o$next[3:0]$11523 - attribute \src "libresoc.v:171732.13-171732.30" + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $1\r6__data_o$next[3:0]$11588 + attribute \src "libresoc.v:180437.13-180437.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:171863.3-171889.6" - wire width 4 $1\reg$next[3:0]$11489 - attribute \src "libresoc.v:171738.13-171738.25" + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $1\reg$next[3:0]$11554 + attribute \src "libresoc.v:180443.13-180443.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:171793.3-171832.6" - wire width 4 $1\src16__data_o$next[3:0]$11480 - attribute \src "libresoc.v:171743.13-171743.33" + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $1\src16__data_o$next[3:0]$11545 + attribute \src "libresoc.v:180448.13-180448.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:171890.3-171929.6" - wire width 4 $1\src26__data_o$next[3:0]$11495 - attribute \src "libresoc.v:171750.13-171750.33" + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $1\src26__data_o$next[3:0]$11560 + attribute \src "libresoc.v:180455.13-180455.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:171960.3-171999.6" - wire width 4 $1\src36__data_o$next[3:0]$11509 - attribute \src "libresoc.v:171757.13-171757.33" + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $1\src36__data_o$next[3:0]$11574 + attribute \src "libresoc.v:180462.13-180462.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:172070.3-172099.6" - wire $1\wr_detect$10[0:0]$11531 - attribute \src "libresoc.v:172140.3-172169.6" - wire $1\wr_detect$13[0:0]$11545 - attribute \src "libresoc.v:171930.3-171959.6" - wire $1\wr_detect$4[0:0]$11503 - attribute \src "libresoc.v:172000.3-172029.6" - wire $1\wr_detect$7[0:0]$11517 - attribute \src "libresoc.v:171833.3-171862.6" + attribute \src "libresoc.v:180775.3-180804.6" + wire $1\wr_detect$10[0:0]$11596 + attribute \src "libresoc.v:180845.3-180874.6" + wire $1\wr_detect$13[0:0]$11610 + attribute \src "libresoc.v:180635.3-180664.6" + wire $1\wr_detect$4[0:0]$11568 + attribute \src "libresoc.v:180705.3-180734.6" + wire $1\wr_detect$7[0:0]$11582 + attribute \src "libresoc.v:180538.3-180567.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:172100.3-172139.6" - wire width 4 $2\r26__data_o$next[3:0]$11538 - attribute \src "libresoc.v:172030.3-172069.6" - wire width 4 $2\r6__data_o$next[3:0]$11524 - attribute \src "libresoc.v:171863.3-171889.6" - wire width 4 $2\reg$next[3:0]$11490 - attribute \src "libresoc.v:171793.3-171832.6" - wire width 4 $2\src16__data_o$next[3:0]$11481 - attribute \src "libresoc.v:171890.3-171929.6" - wire width 4 $2\src26__data_o$next[3:0]$11496 - attribute \src "libresoc.v:171960.3-171999.6" - wire width 4 $2\src36__data_o$next[3:0]$11510 - attribute \src "libresoc.v:172070.3-172099.6" - wire $2\wr_detect$10[0:0]$11532 - attribute \src "libresoc.v:172140.3-172169.6" - wire $2\wr_detect$13[0:0]$11546 - attribute \src "libresoc.v:171930.3-171959.6" - wire $2\wr_detect$4[0:0]$11504 - attribute \src "libresoc.v:172000.3-172029.6" - wire $2\wr_detect$7[0:0]$11518 - attribute \src "libresoc.v:171833.3-171862.6" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $2\r26__data_o$next[3:0]$11603 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $2\r6__data_o$next[3:0]$11589 + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $2\reg$next[3:0]$11555 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $2\src16__data_o$next[3:0]$11546 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $2\src26__data_o$next[3:0]$11561 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $2\src36__data_o$next[3:0]$11575 + attribute \src "libresoc.v:180775.3-180804.6" + wire $2\wr_detect$10[0:0]$11597 + attribute \src "libresoc.v:180845.3-180874.6" + wire $2\wr_detect$13[0:0]$11611 + attribute \src "libresoc.v:180635.3-180664.6" + wire $2\wr_detect$4[0:0]$11569 + attribute \src "libresoc.v:180705.3-180734.6" + wire $2\wr_detect$7[0:0]$11583 + attribute \src "libresoc.v:180538.3-180567.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:172100.3-172139.6" - wire width 4 $3\r26__data_o$next[3:0]$11539 - attribute \src "libresoc.v:172030.3-172069.6" - wire width 4 $3\r6__data_o$next[3:0]$11525 - attribute \src "libresoc.v:171863.3-171889.6" - wire width 4 $3\reg$next[3:0]$11491 - attribute \src "libresoc.v:171793.3-171832.6" - wire width 4 $3\src16__data_o$next[3:0]$11482 - attribute \src "libresoc.v:171890.3-171929.6" - wire width 4 $3\src26__data_o$next[3:0]$11497 - attribute \src "libresoc.v:171960.3-171999.6" - wire width 4 $3\src36__data_o$next[3:0]$11511 - attribute \src "libresoc.v:172070.3-172099.6" - wire $3\wr_detect$10[0:0]$11533 - attribute \src "libresoc.v:172140.3-172169.6" - wire $3\wr_detect$13[0:0]$11547 - attribute \src "libresoc.v:171930.3-171959.6" - wire $3\wr_detect$4[0:0]$11505 - attribute \src "libresoc.v:172000.3-172029.6" - wire $3\wr_detect$7[0:0]$11519 - attribute \src "libresoc.v:171833.3-171862.6" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $3\r26__data_o$next[3:0]$11604 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $3\r6__data_o$next[3:0]$11590 + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $3\reg$next[3:0]$11556 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $3\src16__data_o$next[3:0]$11547 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $3\src26__data_o$next[3:0]$11562 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $3\src36__data_o$next[3:0]$11576 + attribute \src "libresoc.v:180775.3-180804.6" + wire $3\wr_detect$10[0:0]$11598 + attribute \src "libresoc.v:180845.3-180874.6" + wire $3\wr_detect$13[0:0]$11612 + attribute \src "libresoc.v:180635.3-180664.6" + wire $3\wr_detect$4[0:0]$11570 + attribute \src "libresoc.v:180705.3-180734.6" + wire $3\wr_detect$7[0:0]$11584 + attribute \src "libresoc.v:180538.3-180567.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:172100.3-172139.6" - wire width 4 $4\r26__data_o$next[3:0]$11540 - attribute \src "libresoc.v:172030.3-172069.6" - wire width 4 $4\r6__data_o$next[3:0]$11526 - attribute \src "libresoc.v:171863.3-171889.6" - wire width 4 $4\reg$next[3:0]$11492 - attribute \src "libresoc.v:171793.3-171832.6" - wire width 4 $4\src16__data_o$next[3:0]$11483 - attribute \src "libresoc.v:171890.3-171929.6" - wire width 4 $4\src26__data_o$next[3:0]$11498 - attribute \src "libresoc.v:171960.3-171999.6" - wire width 4 $4\src36__data_o$next[3:0]$11512 - attribute \src "libresoc.v:172070.3-172099.6" - wire $4\wr_detect$10[0:0]$11534 - attribute \src "libresoc.v:172140.3-172169.6" - wire $4\wr_detect$13[0:0]$11548 - attribute \src "libresoc.v:171930.3-171959.6" - wire $4\wr_detect$4[0:0]$11506 - attribute \src "libresoc.v:172000.3-172029.6" - wire $4\wr_detect$7[0:0]$11520 - attribute \src "libresoc.v:171833.3-171862.6" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $4\r26__data_o$next[3:0]$11605 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $4\r6__data_o$next[3:0]$11591 + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $4\reg$next[3:0]$11557 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $4\src16__data_o$next[3:0]$11548 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $4\src26__data_o$next[3:0]$11563 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $4\src36__data_o$next[3:0]$11577 + attribute \src "libresoc.v:180775.3-180804.6" + wire $4\wr_detect$10[0:0]$11599 + attribute \src "libresoc.v:180845.3-180874.6" + wire $4\wr_detect$13[0:0]$11613 + attribute \src "libresoc.v:180635.3-180664.6" + wire $4\wr_detect$4[0:0]$11571 + attribute \src "libresoc.v:180705.3-180734.6" + wire $4\wr_detect$7[0:0]$11585 + attribute \src "libresoc.v:180538.3-180567.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:172100.3-172139.6" - wire width 4 $5\r26__data_o$next[3:0]$11541 - attribute \src "libresoc.v:172030.3-172069.6" - wire width 4 $5\r6__data_o$next[3:0]$11527 - attribute \src "libresoc.v:171793.3-171832.6" - wire width 4 $5\src16__data_o$next[3:0]$11484 - attribute \src "libresoc.v:171890.3-171929.6" - wire width 4 $5\src26__data_o$next[3:0]$11499 - attribute \src "libresoc.v:171960.3-171999.6" - wire width 4 $5\src36__data_o$next[3:0]$11513 - attribute \src "libresoc.v:172100.3-172139.6" - wire width 4 $6\r26__data_o$next[3:0]$11542 - attribute \src "libresoc.v:172030.3-172069.6" - wire width 4 $6\r6__data_o$next[3:0]$11528 - attribute \src "libresoc.v:171793.3-171832.6" - wire width 4 $6\src16__data_o$next[3:0]$11485 - attribute \src "libresoc.v:171890.3-171929.6" - wire width 4 $6\src26__data_o$next[3:0]$11500 - attribute \src "libresoc.v:171960.3-171999.6" - wire width 4 $6\src36__data_o$next[3:0]$11514 - attribute \src "libresoc.v:171776.17-171776.104" - wire $not$libresoc.v:171776$11467_Y - attribute \src "libresoc.v:171777.18-171777.105" - wire $not$libresoc.v:171777$11468_Y - attribute \src "libresoc.v:171778.17-171778.100" - wire $not$libresoc.v:171778$11469_Y - attribute \src "libresoc.v:171779.17-171779.103" - wire $not$libresoc.v:171779$11470_Y - attribute \src "libresoc.v:171780.17-171780.103" - wire $not$libresoc.v:171780$11471_Y + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $5\r26__data_o$next[3:0]$11606 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $5\r6__data_o$next[3:0]$11592 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $5\src16__data_o$next[3:0]$11549 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $5\src26__data_o$next[3:0]$11564 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $5\src36__data_o$next[3:0]$11578 + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $6\r26__data_o$next[3:0]$11607 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $6\r6__data_o$next[3:0]$11593 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $6\src16__data_o$next[3:0]$11550 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $6\src26__data_o$next[3:0]$11565 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $6\src36__data_o$next[3:0]$11579 + attribute \src "libresoc.v:180481.17-180481.104" + wire $not$libresoc.v:180481$11532_Y + attribute \src "libresoc.v:180482.18-180482.105" + wire $not$libresoc.v:180482$11533_Y + attribute \src "libresoc.v:180483.17-180483.100" + wire $not$libresoc.v:180483$11534_Y + attribute \src "libresoc.v:180484.17-180484.103" + wire $not$libresoc.v:180484$11535_Y + attribute \src "libresoc.v:180485.17-180485.103" + wire $not$libresoc.v:180485$11536_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -357190,57 +372187,57 @@ module \reg_6 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest16__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest16__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest26__wen - attribute \src "libresoc.v:171700.7-171700.15" + attribute \src "libresoc.v:180405.7-180405.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r26__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r6__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r6__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src16__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src16__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src16__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src26__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src36__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w6__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -357253,152 +372250,152 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171776$11467 + cell $not $not$libresoc.v:180481$11532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:171776$11467_Y + connect \Y $not$libresoc.v:180481$11532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171777$11468 + cell $not $not$libresoc.v:180482$11533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:171777$11468_Y + connect \Y $not$libresoc.v:180482$11533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171778$11469 + cell $not $not$libresoc.v:180483$11534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:171778$11469_Y + connect \Y $not$libresoc.v:180483$11534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171779$11470 + cell $not $not$libresoc.v:180484$11535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:171779$11470_Y + connect \Y $not$libresoc.v:180484$11535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171780$11471 + cell $not $not$libresoc.v:180485$11536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:171780$11471_Y + connect \Y $not$libresoc.v:180485$11536_Y end - attribute \src "libresoc.v:171700.7-171700.20" - process $proc$libresoc.v:171700$11549 + attribute \src "libresoc.v:180405.7-180405.20" + process $proc$libresoc.v:180405$11614 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171725.13-171725.31" - process $proc$libresoc.v:171725$11550 + attribute \src "libresoc.v:180430.13-180430.31" + process $proc$libresoc.v:180430$11615 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:171732.13-171732.30" - process $proc$libresoc.v:171732$11551 + attribute \src "libresoc.v:180437.13-180437.30" + process $proc$libresoc.v:180437$11616 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:171738.13-171738.25" - process $proc$libresoc.v:171738$11552 + attribute \src "libresoc.v:180443.13-180443.25" + process $proc$libresoc.v:180443$11617 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:171743.13-171743.33" - process $proc$libresoc.v:171743$11553 + attribute \src "libresoc.v:180448.13-180448.33" + process $proc$libresoc.v:180448$11618 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:171750.13-171750.33" - process $proc$libresoc.v:171750$11554 + attribute \src "libresoc.v:180455.13-180455.33" + process $proc$libresoc.v:180455$11619 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:171757.13-171757.33" - process $proc$libresoc.v:171757$11555 + attribute \src "libresoc.v:180462.13-180462.33" + process $proc$libresoc.v:180462$11620 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:171781.3-171782.25" - process $proc$libresoc.v:171781$11472 + attribute \src "libresoc.v:180486.3-180487.25" + process $proc$libresoc.v:180486$11537 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:171783.3-171784.39" - process $proc$libresoc.v:171783$11473 + attribute \src "libresoc.v:180488.3-180489.39" + process $proc$libresoc.v:180488$11538 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:171785.3-171786.37" - process $proc$libresoc.v:171785$11474 + attribute \src "libresoc.v:180490.3-180491.37" + process $proc$libresoc.v:180490$11539 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:171787.3-171788.43" - process $proc$libresoc.v:171787$11475 + attribute \src "libresoc.v:180492.3-180493.43" + process $proc$libresoc.v:180492$11540 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:171789.3-171790.43" - process $proc$libresoc.v:171789$11476 + attribute \src "libresoc.v:180494.3-180495.43" + process $proc$libresoc.v:180494$11541 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:171791.3-171792.43" - process $proc$libresoc.v:171791$11477 + attribute \src "libresoc.v:180496.3-180497.43" + process $proc$libresoc.v:180496$11542 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:171793.3-171832.6" - process $proc$libresoc.v:171793$11478 + attribute \src "libresoc.v:180498.3-180537.6" + process $proc$libresoc.v:180498$11543 assign { } { } assign { } { } assign { } { } - assign $0\src16__data_o$next[3:0]$11479 $6\src16__data_o$next[3:0]$11485 - attribute \src "libresoc.v:171794.5-171794.29" + assign $0\src16__data_o$next[3:0]$11544 $6\src16__data_o$next[3:0]$11550 + attribute \src "libresoc.v:180499.5-180499.29" switch \initial - attribute \src "libresoc.v:171794.9-171794.17" + attribute \src "libresoc.v:180499.9-180499.17" case 1'1 case end @@ -357410,66 +372407,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src16__data_o$next[3:0]$11480 $5\src16__data_o$next[3:0]$11484 + assign $1\src16__data_o$next[3:0]$11545 $5\src16__data_o$next[3:0]$11549 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src16__data_o$next[3:0]$11481 \dest16__data_i + assign $2\src16__data_o$next[3:0]$11546 \dest16__data_i case - assign $2\src16__data_o$next[3:0]$11481 4'0000 + assign $2\src16__data_o$next[3:0]$11546 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src16__data_o$next[3:0]$11482 \dest26__data_i + assign $3\src16__data_o$next[3:0]$11547 \dest26__data_i case - assign $3\src16__data_o$next[3:0]$11482 $2\src16__data_o$next[3:0]$11481 + assign $3\src16__data_o$next[3:0]$11547 $2\src16__data_o$next[3:0]$11546 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src16__data_o$next[3:0]$11483 \w6__data_i + assign $4\src16__data_o$next[3:0]$11548 \w6__data_i case - assign $4\src16__data_o$next[3:0]$11483 $3\src16__data_o$next[3:0]$11482 + assign $4\src16__data_o$next[3:0]$11548 $3\src16__data_o$next[3:0]$11547 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11484 \reg + assign $5\src16__data_o$next[3:0]$11549 \reg case - assign $5\src16__data_o$next[3:0]$11484 $4\src16__data_o$next[3:0]$11483 + assign $5\src16__data_o$next[3:0]$11549 $4\src16__data_o$next[3:0]$11548 end case - assign $1\src16__data_o$next[3:0]$11480 4'0000 + assign $1\src16__data_o$next[3:0]$11545 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11485 4'0000 + assign $6\src16__data_o$next[3:0]$11550 4'0000 case - assign $6\src16__data_o$next[3:0]$11485 $1\src16__data_o$next[3:0]$11480 + assign $6\src16__data_o$next[3:0]$11550 $1\src16__data_o$next[3:0]$11545 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11479 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11544 end - attribute \src "libresoc.v:171833.3-171862.6" - process $proc$libresoc.v:171833$11486 + attribute \src "libresoc.v:180538.3-180567.6" + process $proc$libresoc.v:180538$11551 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:171834.5-171834.29" + attribute \src "libresoc.v:180539.5-180539.29" switch \initial - attribute \src "libresoc.v:171834.9-171834.17" + attribute \src "libresoc.v:180539.9-180539.17" case 1'1 case end @@ -357515,17 +372512,17 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:171863.3-171889.6" - process $proc$libresoc.v:171863$11487 + attribute \src "libresoc.v:180568.3-180594.6" + process $proc$libresoc.v:180568$11552 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11488 $4\reg$next[3:0]$11492 - attribute \src "libresoc.v:171864.5-171864.29" + assign $0\reg$next[3:0]$11553 $4\reg$next[3:0]$11557 + attribute \src "libresoc.v:180569.5-180569.29" switch \initial - attribute \src "libresoc.v:171864.9-171864.17" + attribute \src "libresoc.v:180569.9-180569.17" case 1'1 case end @@ -357534,49 +372531,49 @@ module \reg_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11489 \dest16__data_i + assign $1\reg$next[3:0]$11554 \dest16__data_i case - assign $1\reg$next[3:0]$11489 \reg + assign $1\reg$next[3:0]$11554 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11490 \dest26__data_i + assign $2\reg$next[3:0]$11555 \dest26__data_i case - assign $2\reg$next[3:0]$11490 $1\reg$next[3:0]$11489 + assign $2\reg$next[3:0]$11555 $1\reg$next[3:0]$11554 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11491 \w6__data_i + assign $3\reg$next[3:0]$11556 \w6__data_i case - assign $3\reg$next[3:0]$11491 $2\reg$next[3:0]$11490 + assign $3\reg$next[3:0]$11556 $2\reg$next[3:0]$11555 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11492 4'0000 + assign $4\reg$next[3:0]$11557 4'0000 case - assign $4\reg$next[3:0]$11492 $3\reg$next[3:0]$11491 + assign $4\reg$next[3:0]$11557 $3\reg$next[3:0]$11556 end sync always - update \reg$next $0\reg$next[3:0]$11488 + update \reg$next $0\reg$next[3:0]$11553 end - attribute \src "libresoc.v:171890.3-171929.6" - process $proc$libresoc.v:171890$11493 + attribute \src "libresoc.v:180595.3-180634.6" + process $proc$libresoc.v:180595$11558 assign { } { } assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11494 $6\src26__data_o$next[3:0]$11500 - attribute \src "libresoc.v:171891.5-171891.29" + assign $0\src26__data_o$next[3:0]$11559 $6\src26__data_o$next[3:0]$11565 + attribute \src "libresoc.v:180596.5-180596.29" switch \initial - attribute \src "libresoc.v:171891.9-171891.17" + attribute \src "libresoc.v:180596.9-180596.17" case 1'1 case end @@ -357588,66 +372585,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11495 $5\src26__data_o$next[3:0]$11499 + assign $1\src26__data_o$next[3:0]$11560 $5\src26__data_o$next[3:0]$11564 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11496 \dest16__data_i + assign $2\src26__data_o$next[3:0]$11561 \dest16__data_i case - assign $2\src26__data_o$next[3:0]$11496 4'0000 + assign $2\src26__data_o$next[3:0]$11561 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11497 \dest26__data_i + assign $3\src26__data_o$next[3:0]$11562 \dest26__data_i case - assign $3\src26__data_o$next[3:0]$11497 $2\src26__data_o$next[3:0]$11496 + assign $3\src26__data_o$next[3:0]$11562 $2\src26__data_o$next[3:0]$11561 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11498 \w6__data_i + assign $4\src26__data_o$next[3:0]$11563 \w6__data_i case - assign $4\src26__data_o$next[3:0]$11498 $3\src26__data_o$next[3:0]$11497 + assign $4\src26__data_o$next[3:0]$11563 $3\src26__data_o$next[3:0]$11562 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11499 \reg + assign $5\src26__data_o$next[3:0]$11564 \reg case - assign $5\src26__data_o$next[3:0]$11499 $4\src26__data_o$next[3:0]$11498 + assign $5\src26__data_o$next[3:0]$11564 $4\src26__data_o$next[3:0]$11563 end case - assign $1\src26__data_o$next[3:0]$11495 4'0000 + assign $1\src26__data_o$next[3:0]$11560 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11500 4'0000 + assign $6\src26__data_o$next[3:0]$11565 4'0000 case - assign $6\src26__data_o$next[3:0]$11500 $1\src26__data_o$next[3:0]$11495 + assign $6\src26__data_o$next[3:0]$11565 $1\src26__data_o$next[3:0]$11560 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11494 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11559 end - attribute \src "libresoc.v:171930.3-171959.6" - process $proc$libresoc.v:171930$11501 + attribute \src "libresoc.v:180635.3-180664.6" + process $proc$libresoc.v:180635$11566 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11502 $1\wr_detect$4[0:0]$11503 - attribute \src "libresoc.v:171931.5-171931.29" + assign $0\wr_detect$4[0:0]$11567 $1\wr_detect$4[0:0]$11568 + attribute \src "libresoc.v:180636.5-180636.29" switch \initial - attribute \src "libresoc.v:171931.9-171931.17" + attribute \src "libresoc.v:180636.9-180636.17" case 1'1 case end @@ -357659,49 +372656,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11503 $4\wr_detect$4[0:0]$11506 + assign $1\wr_detect$4[0:0]$11568 $4\wr_detect$4[0:0]$11571 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11504 1'1 + assign $2\wr_detect$4[0:0]$11569 1'1 case - assign $2\wr_detect$4[0:0]$11504 1'0 + assign $2\wr_detect$4[0:0]$11569 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11505 1'1 + assign $3\wr_detect$4[0:0]$11570 1'1 case - assign $3\wr_detect$4[0:0]$11505 $2\wr_detect$4[0:0]$11504 + assign $3\wr_detect$4[0:0]$11570 $2\wr_detect$4[0:0]$11569 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11506 1'1 + assign $4\wr_detect$4[0:0]$11571 1'1 case - assign $4\wr_detect$4[0:0]$11506 $3\wr_detect$4[0:0]$11505 + assign $4\wr_detect$4[0:0]$11571 $3\wr_detect$4[0:0]$11570 end case - assign $1\wr_detect$4[0:0]$11503 1'0 + assign $1\wr_detect$4[0:0]$11568 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11502 + update \wr_detect$4 $0\wr_detect$4[0:0]$11567 end - attribute \src "libresoc.v:171960.3-171999.6" - process $proc$libresoc.v:171960$11507 + attribute \src "libresoc.v:180665.3-180704.6" + process $proc$libresoc.v:180665$11572 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11508 $6\src36__data_o$next[3:0]$11514 - attribute \src "libresoc.v:171961.5-171961.29" + assign $0\src36__data_o$next[3:0]$11573 $6\src36__data_o$next[3:0]$11579 + attribute \src "libresoc.v:180666.5-180666.29" switch \initial - attribute \src "libresoc.v:171961.9-171961.17" + attribute \src "libresoc.v:180666.9-180666.17" case 1'1 case end @@ -357713,66 +372710,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11509 $5\src36__data_o$next[3:0]$11513 + assign $1\src36__data_o$next[3:0]$11574 $5\src36__data_o$next[3:0]$11578 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11510 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11575 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11510 4'0000 + assign $2\src36__data_o$next[3:0]$11575 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11511 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11576 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11511 $2\src36__data_o$next[3:0]$11510 + assign $3\src36__data_o$next[3:0]$11576 $2\src36__data_o$next[3:0]$11575 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11512 \w6__data_i + assign $4\src36__data_o$next[3:0]$11577 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11512 $3\src36__data_o$next[3:0]$11511 + assign $4\src36__data_o$next[3:0]$11577 $3\src36__data_o$next[3:0]$11576 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11513 \reg + assign $5\src36__data_o$next[3:0]$11578 \reg case - assign $5\src36__data_o$next[3:0]$11513 $4\src36__data_o$next[3:0]$11512 + assign $5\src36__data_o$next[3:0]$11578 $4\src36__data_o$next[3:0]$11577 end case - assign $1\src36__data_o$next[3:0]$11509 4'0000 + assign $1\src36__data_o$next[3:0]$11574 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11514 4'0000 + assign $6\src36__data_o$next[3:0]$11579 4'0000 case - assign $6\src36__data_o$next[3:0]$11514 $1\src36__data_o$next[3:0]$11509 + assign $6\src36__data_o$next[3:0]$11579 $1\src36__data_o$next[3:0]$11574 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11508 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11573 end - attribute \src "libresoc.v:172000.3-172029.6" - process $proc$libresoc.v:172000$11515 + attribute \src "libresoc.v:180705.3-180734.6" + process $proc$libresoc.v:180705$11580 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11516 $1\wr_detect$7[0:0]$11517 - attribute \src "libresoc.v:172001.5-172001.29" + assign $0\wr_detect$7[0:0]$11581 $1\wr_detect$7[0:0]$11582 + attribute \src "libresoc.v:180706.5-180706.29" switch \initial - attribute \src "libresoc.v:172001.9-172001.17" + attribute \src "libresoc.v:180706.9-180706.17" case 1'1 case end @@ -357784,49 +372781,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11517 $4\wr_detect$7[0:0]$11520 + assign $1\wr_detect$7[0:0]$11582 $4\wr_detect$7[0:0]$11585 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11518 1'1 + assign $2\wr_detect$7[0:0]$11583 1'1 case - assign $2\wr_detect$7[0:0]$11518 1'0 + assign $2\wr_detect$7[0:0]$11583 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11519 1'1 + assign $3\wr_detect$7[0:0]$11584 1'1 case - assign $3\wr_detect$7[0:0]$11519 $2\wr_detect$7[0:0]$11518 + assign $3\wr_detect$7[0:0]$11584 $2\wr_detect$7[0:0]$11583 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11520 1'1 + assign $4\wr_detect$7[0:0]$11585 1'1 case - assign $4\wr_detect$7[0:0]$11520 $3\wr_detect$7[0:0]$11519 + assign $4\wr_detect$7[0:0]$11585 $3\wr_detect$7[0:0]$11584 end case - assign $1\wr_detect$7[0:0]$11517 1'0 + assign $1\wr_detect$7[0:0]$11582 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11516 + update \wr_detect$7 $0\wr_detect$7[0:0]$11581 end - attribute \src "libresoc.v:172030.3-172069.6" - process $proc$libresoc.v:172030$11521 + attribute \src "libresoc.v:180735.3-180774.6" + process $proc$libresoc.v:180735$11586 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11522 $6\r6__data_o$next[3:0]$11528 - attribute \src "libresoc.v:172031.5-172031.29" + assign $0\r6__data_o$next[3:0]$11587 $6\r6__data_o$next[3:0]$11593 + attribute \src "libresoc.v:180736.5-180736.29" switch \initial - attribute \src "libresoc.v:172031.9-172031.17" + attribute \src "libresoc.v:180736.9-180736.17" case 1'1 case end @@ -357838,66 +372835,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11523 $5\r6__data_o$next[3:0]$11527 + assign $1\r6__data_o$next[3:0]$11588 $5\r6__data_o$next[3:0]$11592 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11524 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11589 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11524 4'0000 + assign $2\r6__data_o$next[3:0]$11589 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11525 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11590 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11525 $2\r6__data_o$next[3:0]$11524 + assign $3\r6__data_o$next[3:0]$11590 $2\r6__data_o$next[3:0]$11589 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11526 \w6__data_i + assign $4\r6__data_o$next[3:0]$11591 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11526 $3\r6__data_o$next[3:0]$11525 + assign $4\r6__data_o$next[3:0]$11591 $3\r6__data_o$next[3:0]$11590 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11527 \reg + assign $5\r6__data_o$next[3:0]$11592 \reg case - assign $5\r6__data_o$next[3:0]$11527 $4\r6__data_o$next[3:0]$11526 + assign $5\r6__data_o$next[3:0]$11592 $4\r6__data_o$next[3:0]$11591 end case - assign $1\r6__data_o$next[3:0]$11523 4'0000 + assign $1\r6__data_o$next[3:0]$11588 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11528 4'0000 + assign $6\r6__data_o$next[3:0]$11593 4'0000 case - assign $6\r6__data_o$next[3:0]$11528 $1\r6__data_o$next[3:0]$11523 + assign $6\r6__data_o$next[3:0]$11593 $1\r6__data_o$next[3:0]$11588 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11522 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11587 end - attribute \src "libresoc.v:172070.3-172099.6" - process $proc$libresoc.v:172070$11529 + attribute \src "libresoc.v:180775.3-180804.6" + process $proc$libresoc.v:180775$11594 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11530 $1\wr_detect$10[0:0]$11531 - attribute \src "libresoc.v:172071.5-172071.29" + assign $0\wr_detect$10[0:0]$11595 $1\wr_detect$10[0:0]$11596 + attribute \src "libresoc.v:180776.5-180776.29" switch \initial - attribute \src "libresoc.v:172071.9-172071.17" + attribute \src "libresoc.v:180776.9-180776.17" case 1'1 case end @@ -357909,49 +372906,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11531 $4\wr_detect$10[0:0]$11534 + assign $1\wr_detect$10[0:0]$11596 $4\wr_detect$10[0:0]$11599 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11532 1'1 + assign $2\wr_detect$10[0:0]$11597 1'1 case - assign $2\wr_detect$10[0:0]$11532 1'0 + assign $2\wr_detect$10[0:0]$11597 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11533 1'1 + assign $3\wr_detect$10[0:0]$11598 1'1 case - assign $3\wr_detect$10[0:0]$11533 $2\wr_detect$10[0:0]$11532 + assign $3\wr_detect$10[0:0]$11598 $2\wr_detect$10[0:0]$11597 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11534 1'1 + assign $4\wr_detect$10[0:0]$11599 1'1 case - assign $4\wr_detect$10[0:0]$11534 $3\wr_detect$10[0:0]$11533 + assign $4\wr_detect$10[0:0]$11599 $3\wr_detect$10[0:0]$11598 end case - assign $1\wr_detect$10[0:0]$11531 1'0 + assign $1\wr_detect$10[0:0]$11596 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11530 + update \wr_detect$10 $0\wr_detect$10[0:0]$11595 end - attribute \src "libresoc.v:172100.3-172139.6" - process $proc$libresoc.v:172100$11535 + attribute \src "libresoc.v:180805.3-180844.6" + process $proc$libresoc.v:180805$11600 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11536 $6\r26__data_o$next[3:0]$11542 - attribute \src "libresoc.v:172101.5-172101.29" + assign $0\r26__data_o$next[3:0]$11601 $6\r26__data_o$next[3:0]$11607 + attribute \src "libresoc.v:180806.5-180806.29" switch \initial - attribute \src "libresoc.v:172101.9-172101.17" + attribute \src "libresoc.v:180806.9-180806.17" case 1'1 case end @@ -357963,66 +372960,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r26__data_o$next[3:0]$11537 $5\r26__data_o$next[3:0]$11541 + assign $1\r26__data_o$next[3:0]$11602 $5\r26__data_o$next[3:0]$11606 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r26__data_o$next[3:0]$11538 \dest16__data_i + assign $2\r26__data_o$next[3:0]$11603 \dest16__data_i case - assign $2\r26__data_o$next[3:0]$11538 4'0000 + assign $2\r26__data_o$next[3:0]$11603 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r26__data_o$next[3:0]$11539 \dest26__data_i + assign $3\r26__data_o$next[3:0]$11604 \dest26__data_i case - assign $3\r26__data_o$next[3:0]$11539 $2\r26__data_o$next[3:0]$11538 + assign $3\r26__data_o$next[3:0]$11604 $2\r26__data_o$next[3:0]$11603 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r26__data_o$next[3:0]$11540 \w6__data_i + assign $4\r26__data_o$next[3:0]$11605 \w6__data_i case - assign $4\r26__data_o$next[3:0]$11540 $3\r26__data_o$next[3:0]$11539 + assign $4\r26__data_o$next[3:0]$11605 $3\r26__data_o$next[3:0]$11604 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r26__data_o$next[3:0]$11541 \reg + assign $5\r26__data_o$next[3:0]$11606 \reg case - assign $5\r26__data_o$next[3:0]$11541 $4\r26__data_o$next[3:0]$11540 + assign $5\r26__data_o$next[3:0]$11606 $4\r26__data_o$next[3:0]$11605 end case - assign $1\r26__data_o$next[3:0]$11537 4'0000 + assign $1\r26__data_o$next[3:0]$11602 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11542 4'0000 + assign $6\r26__data_o$next[3:0]$11607 4'0000 case - assign $6\r26__data_o$next[3:0]$11542 $1\r26__data_o$next[3:0]$11537 + assign $6\r26__data_o$next[3:0]$11607 $1\r26__data_o$next[3:0]$11602 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11536 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11601 end - attribute \src "libresoc.v:172140.3-172169.6" - process $proc$libresoc.v:172140$11543 + attribute \src "libresoc.v:180845.3-180874.6" + process $proc$libresoc.v:180845$11608 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11544 $1\wr_detect$13[0:0]$11545 - attribute \src "libresoc.v:172141.5-172141.29" + assign $0\wr_detect$13[0:0]$11609 $1\wr_detect$13[0:0]$11610 + attribute \src "libresoc.v:180846.5-180846.29" switch \initial - attribute \src "libresoc.v:172141.9-172141.17" + attribute \src "libresoc.v:180846.9-180846.17" case 1'1 case end @@ -358034,217 +373031,217 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11545 $4\wr_detect$13[0:0]$11548 + assign $1\wr_detect$13[0:0]$11610 $4\wr_detect$13[0:0]$11613 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11546 1'1 + assign $2\wr_detect$13[0:0]$11611 1'1 case - assign $2\wr_detect$13[0:0]$11546 1'0 + assign $2\wr_detect$13[0:0]$11611 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11547 1'1 + assign $3\wr_detect$13[0:0]$11612 1'1 case - assign $3\wr_detect$13[0:0]$11547 $2\wr_detect$13[0:0]$11546 + assign $3\wr_detect$13[0:0]$11612 $2\wr_detect$13[0:0]$11611 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11548 1'1 + assign $4\wr_detect$13[0:0]$11613 1'1 case - assign $4\wr_detect$13[0:0]$11548 $3\wr_detect$13[0:0]$11547 + assign $4\wr_detect$13[0:0]$11613 $3\wr_detect$13[0:0]$11612 end case - assign $1\wr_detect$13[0:0]$11545 1'0 + assign $1\wr_detect$13[0:0]$11610 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11544 + update \wr_detect$13 $0\wr_detect$13[0:0]$11609 end - connect \$9 $not$libresoc.v:171776$11467_Y - connect \$12 $not$libresoc.v:171777$11468_Y - connect \$1 $not$libresoc.v:171778$11469_Y - connect \$3 $not$libresoc.v:171779$11470_Y - connect \$6 $not$libresoc.v:171780$11471_Y + connect \$9 $not$libresoc.v:180481$11532_Y + connect \$12 $not$libresoc.v:180482$11533_Y + connect \$1 $not$libresoc.v:180483$11534_Y + connect \$3 $not$libresoc.v:180484$11535_Y + connect \$6 $not$libresoc.v:180485$11536_Y end -attribute \src "libresoc.v:172174.1-172645.10" +attribute \src "libresoc.v:180879.1-181350.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:172175.7-172175.20" + attribute \src "libresoc.v:180880.7-180880.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172575.3-172614.6" - wire width 4 $0\r27__data_o$next[3:0]$11625 - attribute \src "libresoc.v:172258.3-172259.39" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $0\r27__data_o$next[3:0]$11690 + attribute \src "libresoc.v:180963.3-180964.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:172505.3-172544.6" - wire width 4 $0\r7__data_o$next[3:0]$11611 - attribute \src "libresoc.v:172260.3-172261.37" + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $0\r7__data_o$next[3:0]$11676 + attribute \src "libresoc.v:180965.3-180966.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:172338.3-172364.6" - wire width 4 $0\reg$next[3:0]$11577 - attribute \src "libresoc.v:172256.3-172257.25" + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $0\reg$next[3:0]$11642 + attribute \src "libresoc.v:180961.3-180962.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:172268.3-172307.6" - wire width 4 $0\src17__data_o$next[3:0]$11568 - attribute \src "libresoc.v:172266.3-172267.43" + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $0\src17__data_o$next[3:0]$11633 + attribute \src "libresoc.v:180971.3-180972.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:172365.3-172404.6" - wire width 4 $0\src27__data_o$next[3:0]$11583 - attribute \src "libresoc.v:172264.3-172265.43" + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $0\src27__data_o$next[3:0]$11648 + attribute \src "libresoc.v:180969.3-180970.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:172435.3-172474.6" - wire width 4 $0\src37__data_o$next[3:0]$11597 - attribute \src "libresoc.v:172262.3-172263.43" + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $0\src37__data_o$next[3:0]$11662 + attribute \src "libresoc.v:180967.3-180968.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:172545.3-172574.6" - wire $0\wr_detect$10[0:0]$11619 - attribute \src "libresoc.v:172615.3-172644.6" - wire $0\wr_detect$13[0:0]$11633 - attribute \src "libresoc.v:172405.3-172434.6" - wire $0\wr_detect$4[0:0]$11591 - attribute \src "libresoc.v:172475.3-172504.6" - wire $0\wr_detect$7[0:0]$11605 - attribute \src "libresoc.v:172308.3-172337.6" + attribute \src "libresoc.v:181250.3-181279.6" + wire $0\wr_detect$10[0:0]$11684 + attribute \src "libresoc.v:181320.3-181349.6" + wire $0\wr_detect$13[0:0]$11698 + attribute \src "libresoc.v:181110.3-181139.6" + wire $0\wr_detect$4[0:0]$11656 + attribute \src "libresoc.v:181180.3-181209.6" + wire $0\wr_detect$7[0:0]$11670 + attribute \src "libresoc.v:181013.3-181042.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:172575.3-172614.6" - wire width 4 $1\r27__data_o$next[3:0]$11626 - attribute \src "libresoc.v:172200.13-172200.31" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $1\r27__data_o$next[3:0]$11691 + attribute \src "libresoc.v:180905.13-180905.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:172505.3-172544.6" - wire width 4 $1\r7__data_o$next[3:0]$11612 - attribute \src "libresoc.v:172207.13-172207.30" + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $1\r7__data_o$next[3:0]$11677 + attribute \src "libresoc.v:180912.13-180912.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:172338.3-172364.6" - wire width 4 $1\reg$next[3:0]$11578 - attribute \src "libresoc.v:172213.13-172213.25" + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $1\reg$next[3:0]$11643 + attribute \src "libresoc.v:180918.13-180918.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:172268.3-172307.6" - wire width 4 $1\src17__data_o$next[3:0]$11569 - attribute \src "libresoc.v:172218.13-172218.33" + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $1\src17__data_o$next[3:0]$11634 + attribute \src "libresoc.v:180923.13-180923.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:172365.3-172404.6" - wire width 4 $1\src27__data_o$next[3:0]$11584 - attribute \src "libresoc.v:172225.13-172225.33" + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $1\src27__data_o$next[3:0]$11649 + attribute \src "libresoc.v:180930.13-180930.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:172435.3-172474.6" - wire width 4 $1\src37__data_o$next[3:0]$11598 - attribute \src "libresoc.v:172232.13-172232.33" + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $1\src37__data_o$next[3:0]$11663 + attribute \src "libresoc.v:180937.13-180937.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:172545.3-172574.6" - wire $1\wr_detect$10[0:0]$11620 - attribute \src "libresoc.v:172615.3-172644.6" - wire $1\wr_detect$13[0:0]$11634 - attribute \src "libresoc.v:172405.3-172434.6" - wire $1\wr_detect$4[0:0]$11592 - attribute \src "libresoc.v:172475.3-172504.6" - wire $1\wr_detect$7[0:0]$11606 - attribute \src "libresoc.v:172308.3-172337.6" + attribute \src "libresoc.v:181250.3-181279.6" + wire $1\wr_detect$10[0:0]$11685 + attribute \src "libresoc.v:181320.3-181349.6" + wire $1\wr_detect$13[0:0]$11699 + attribute \src "libresoc.v:181110.3-181139.6" + wire $1\wr_detect$4[0:0]$11657 + attribute \src "libresoc.v:181180.3-181209.6" + wire $1\wr_detect$7[0:0]$11671 + attribute \src "libresoc.v:181013.3-181042.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:172575.3-172614.6" - wire width 4 $2\r27__data_o$next[3:0]$11627 - attribute \src "libresoc.v:172505.3-172544.6" - wire width 4 $2\r7__data_o$next[3:0]$11613 - attribute \src "libresoc.v:172338.3-172364.6" - wire width 4 $2\reg$next[3:0]$11579 - attribute \src "libresoc.v:172268.3-172307.6" - wire width 4 $2\src17__data_o$next[3:0]$11570 - attribute \src "libresoc.v:172365.3-172404.6" - wire width 4 $2\src27__data_o$next[3:0]$11585 - attribute \src "libresoc.v:172435.3-172474.6" - wire width 4 $2\src37__data_o$next[3:0]$11599 - attribute \src "libresoc.v:172545.3-172574.6" - wire $2\wr_detect$10[0:0]$11621 - attribute \src "libresoc.v:172615.3-172644.6" - wire $2\wr_detect$13[0:0]$11635 - attribute \src "libresoc.v:172405.3-172434.6" - wire $2\wr_detect$4[0:0]$11593 - attribute \src "libresoc.v:172475.3-172504.6" - wire $2\wr_detect$7[0:0]$11607 - attribute \src "libresoc.v:172308.3-172337.6" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $2\r27__data_o$next[3:0]$11692 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $2\r7__data_o$next[3:0]$11678 + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $2\reg$next[3:0]$11644 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $2\src17__data_o$next[3:0]$11635 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $2\src27__data_o$next[3:0]$11650 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $2\src37__data_o$next[3:0]$11664 + attribute \src "libresoc.v:181250.3-181279.6" + wire $2\wr_detect$10[0:0]$11686 + attribute \src "libresoc.v:181320.3-181349.6" + wire $2\wr_detect$13[0:0]$11700 + attribute \src "libresoc.v:181110.3-181139.6" + wire $2\wr_detect$4[0:0]$11658 + attribute \src "libresoc.v:181180.3-181209.6" + wire $2\wr_detect$7[0:0]$11672 + attribute \src "libresoc.v:181013.3-181042.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:172575.3-172614.6" - wire width 4 $3\r27__data_o$next[3:0]$11628 - attribute \src "libresoc.v:172505.3-172544.6" - wire width 4 $3\r7__data_o$next[3:0]$11614 - attribute \src "libresoc.v:172338.3-172364.6" - wire width 4 $3\reg$next[3:0]$11580 - attribute \src "libresoc.v:172268.3-172307.6" - wire width 4 $3\src17__data_o$next[3:0]$11571 - attribute \src "libresoc.v:172365.3-172404.6" - wire width 4 $3\src27__data_o$next[3:0]$11586 - attribute \src "libresoc.v:172435.3-172474.6" - wire width 4 $3\src37__data_o$next[3:0]$11600 - attribute \src "libresoc.v:172545.3-172574.6" - wire $3\wr_detect$10[0:0]$11622 - attribute \src "libresoc.v:172615.3-172644.6" - wire $3\wr_detect$13[0:0]$11636 - attribute \src "libresoc.v:172405.3-172434.6" - wire $3\wr_detect$4[0:0]$11594 - attribute \src "libresoc.v:172475.3-172504.6" - wire $3\wr_detect$7[0:0]$11608 - attribute \src "libresoc.v:172308.3-172337.6" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $3\r27__data_o$next[3:0]$11693 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $3\r7__data_o$next[3:0]$11679 + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $3\reg$next[3:0]$11645 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $3\src17__data_o$next[3:0]$11636 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $3\src27__data_o$next[3:0]$11651 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $3\src37__data_o$next[3:0]$11665 + attribute \src "libresoc.v:181250.3-181279.6" + wire $3\wr_detect$10[0:0]$11687 + attribute \src "libresoc.v:181320.3-181349.6" + wire $3\wr_detect$13[0:0]$11701 + attribute \src "libresoc.v:181110.3-181139.6" + wire $3\wr_detect$4[0:0]$11659 + attribute \src "libresoc.v:181180.3-181209.6" + wire $3\wr_detect$7[0:0]$11673 + attribute \src "libresoc.v:181013.3-181042.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:172575.3-172614.6" - wire width 4 $4\r27__data_o$next[3:0]$11629 - attribute \src "libresoc.v:172505.3-172544.6" - wire width 4 $4\r7__data_o$next[3:0]$11615 - attribute \src "libresoc.v:172338.3-172364.6" - wire width 4 $4\reg$next[3:0]$11581 - attribute \src "libresoc.v:172268.3-172307.6" - wire width 4 $4\src17__data_o$next[3:0]$11572 - attribute \src "libresoc.v:172365.3-172404.6" - wire width 4 $4\src27__data_o$next[3:0]$11587 - attribute \src "libresoc.v:172435.3-172474.6" - wire width 4 $4\src37__data_o$next[3:0]$11601 - attribute \src "libresoc.v:172545.3-172574.6" - wire $4\wr_detect$10[0:0]$11623 - attribute \src "libresoc.v:172615.3-172644.6" - wire $4\wr_detect$13[0:0]$11637 - attribute \src "libresoc.v:172405.3-172434.6" - wire $4\wr_detect$4[0:0]$11595 - attribute \src "libresoc.v:172475.3-172504.6" - wire $4\wr_detect$7[0:0]$11609 - attribute \src "libresoc.v:172308.3-172337.6" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $4\r27__data_o$next[3:0]$11694 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $4\r7__data_o$next[3:0]$11680 + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $4\reg$next[3:0]$11646 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $4\src17__data_o$next[3:0]$11637 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $4\src27__data_o$next[3:0]$11652 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $4\src37__data_o$next[3:0]$11666 + attribute \src "libresoc.v:181250.3-181279.6" + wire $4\wr_detect$10[0:0]$11688 + attribute \src "libresoc.v:181320.3-181349.6" + wire $4\wr_detect$13[0:0]$11702 + attribute \src "libresoc.v:181110.3-181139.6" + wire $4\wr_detect$4[0:0]$11660 + attribute \src "libresoc.v:181180.3-181209.6" + wire $4\wr_detect$7[0:0]$11674 + attribute \src "libresoc.v:181013.3-181042.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:172575.3-172614.6" - wire width 4 $5\r27__data_o$next[3:0]$11630 - attribute \src "libresoc.v:172505.3-172544.6" - wire width 4 $5\r7__data_o$next[3:0]$11616 - attribute \src "libresoc.v:172268.3-172307.6" - wire width 4 $5\src17__data_o$next[3:0]$11573 - attribute \src "libresoc.v:172365.3-172404.6" - wire width 4 $5\src27__data_o$next[3:0]$11588 - attribute \src "libresoc.v:172435.3-172474.6" - wire width 4 $5\src37__data_o$next[3:0]$11602 - attribute \src "libresoc.v:172575.3-172614.6" - wire width 4 $6\r27__data_o$next[3:0]$11631 - attribute \src "libresoc.v:172505.3-172544.6" - wire width 4 $6\r7__data_o$next[3:0]$11617 - attribute \src "libresoc.v:172268.3-172307.6" - wire width 4 $6\src17__data_o$next[3:0]$11574 - attribute \src "libresoc.v:172365.3-172404.6" - wire width 4 $6\src27__data_o$next[3:0]$11589 - attribute \src "libresoc.v:172435.3-172474.6" - wire width 4 $6\src37__data_o$next[3:0]$11603 - attribute \src "libresoc.v:172251.17-172251.104" - wire $not$libresoc.v:172251$11556_Y - attribute \src "libresoc.v:172252.18-172252.105" - wire $not$libresoc.v:172252$11557_Y - attribute \src "libresoc.v:172253.17-172253.100" - wire $not$libresoc.v:172253$11558_Y - attribute \src "libresoc.v:172254.17-172254.103" - wire $not$libresoc.v:172254$11559_Y - attribute \src "libresoc.v:172255.17-172255.103" - wire $not$libresoc.v:172255$11560_Y + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $5\r27__data_o$next[3:0]$11695 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $5\r7__data_o$next[3:0]$11681 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $5\src17__data_o$next[3:0]$11638 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $5\src27__data_o$next[3:0]$11653 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $5\src37__data_o$next[3:0]$11667 + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $6\r27__data_o$next[3:0]$11696 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $6\r7__data_o$next[3:0]$11682 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $6\src17__data_o$next[3:0]$11639 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $6\src27__data_o$next[3:0]$11654 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $6\src37__data_o$next[3:0]$11668 + attribute \src "libresoc.v:180956.17-180956.104" + wire $not$libresoc.v:180956$11621_Y + attribute \src "libresoc.v:180957.18-180957.105" + wire $not$libresoc.v:180957$11622_Y + attribute \src "libresoc.v:180958.17-180958.100" + wire $not$libresoc.v:180958$11623_Y + attribute \src "libresoc.v:180959.17-180959.103" + wire $not$libresoc.v:180959$11624_Y + attribute \src "libresoc.v:180960.17-180960.103" + wire $not$libresoc.v:180960$11625_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -358255,57 +373252,57 @@ module \reg_7 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest27__wen - attribute \src "libresoc.v:172175.7-172175.15" + attribute \src "libresoc.v:180880.7-180880.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r27__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r7__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r7__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src17__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src27__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src37__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w7__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect @@ -358318,152 +373315,152 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172251$11556 + cell $not $not$libresoc.v:180956$11621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:172251$11556_Y + connect \Y $not$libresoc.v:180956$11621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172252$11557 + cell $not $not$libresoc.v:180957$11622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:172252$11557_Y + connect \Y $not$libresoc.v:180957$11622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172253$11558 + cell $not $not$libresoc.v:180958$11623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:172253$11558_Y + connect \Y $not$libresoc.v:180958$11623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172254$11559 + cell $not $not$libresoc.v:180959$11624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:172254$11559_Y + connect \Y $not$libresoc.v:180959$11624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172255$11560 + cell $not $not$libresoc.v:180960$11625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:172255$11560_Y + connect \Y $not$libresoc.v:180960$11625_Y end - attribute \src "libresoc.v:172175.7-172175.20" - process $proc$libresoc.v:172175$11638 + attribute \src "libresoc.v:180880.7-180880.20" + process $proc$libresoc.v:180880$11703 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172200.13-172200.31" - process $proc$libresoc.v:172200$11639 + attribute \src "libresoc.v:180905.13-180905.31" + process $proc$libresoc.v:180905$11704 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:172207.13-172207.30" - process $proc$libresoc.v:172207$11640 + attribute \src "libresoc.v:180912.13-180912.30" + process $proc$libresoc.v:180912$11705 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:172213.13-172213.25" - process $proc$libresoc.v:172213$11641 + attribute \src "libresoc.v:180918.13-180918.25" + process $proc$libresoc.v:180918$11706 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:172218.13-172218.33" - process $proc$libresoc.v:172218$11642 + attribute \src "libresoc.v:180923.13-180923.33" + process $proc$libresoc.v:180923$11707 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:172225.13-172225.33" - process $proc$libresoc.v:172225$11643 + attribute \src "libresoc.v:180930.13-180930.33" + process $proc$libresoc.v:180930$11708 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:172232.13-172232.33" - process $proc$libresoc.v:172232$11644 + attribute \src "libresoc.v:180937.13-180937.33" + process $proc$libresoc.v:180937$11709 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:172256.3-172257.25" - process $proc$libresoc.v:172256$11561 + attribute \src "libresoc.v:180961.3-180962.25" + process $proc$libresoc.v:180961$11626 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:172258.3-172259.39" - process $proc$libresoc.v:172258$11562 + attribute \src "libresoc.v:180963.3-180964.39" + process $proc$libresoc.v:180963$11627 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:172260.3-172261.37" - process $proc$libresoc.v:172260$11563 + attribute \src "libresoc.v:180965.3-180966.37" + process $proc$libresoc.v:180965$11628 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:172262.3-172263.43" - process $proc$libresoc.v:172262$11564 + attribute \src "libresoc.v:180967.3-180968.43" + process $proc$libresoc.v:180967$11629 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:172264.3-172265.43" - process $proc$libresoc.v:172264$11565 + attribute \src "libresoc.v:180969.3-180970.43" + process $proc$libresoc.v:180969$11630 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:172266.3-172267.43" - process $proc$libresoc.v:172266$11566 + attribute \src "libresoc.v:180971.3-180972.43" + process $proc$libresoc.v:180971$11631 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:172268.3-172307.6" - process $proc$libresoc.v:172268$11567 + attribute \src "libresoc.v:180973.3-181012.6" + process $proc$libresoc.v:180973$11632 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11568 $6\src17__data_o$next[3:0]$11574 - attribute \src "libresoc.v:172269.5-172269.29" + assign $0\src17__data_o$next[3:0]$11633 $6\src17__data_o$next[3:0]$11639 + attribute \src "libresoc.v:180974.5-180974.29" switch \initial - attribute \src "libresoc.v:172269.9-172269.17" + attribute \src "libresoc.v:180974.9-180974.17" case 1'1 case end @@ -358475,66 +373472,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11569 $5\src17__data_o$next[3:0]$11573 + assign $1\src17__data_o$next[3:0]$11634 $5\src17__data_o$next[3:0]$11638 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11570 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11635 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11570 4'0000 + assign $2\src17__data_o$next[3:0]$11635 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11571 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11636 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11571 $2\src17__data_o$next[3:0]$11570 + assign $3\src17__data_o$next[3:0]$11636 $2\src17__data_o$next[3:0]$11635 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11572 \w7__data_i + assign $4\src17__data_o$next[3:0]$11637 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11572 $3\src17__data_o$next[3:0]$11571 + assign $4\src17__data_o$next[3:0]$11637 $3\src17__data_o$next[3:0]$11636 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11573 \reg + assign $5\src17__data_o$next[3:0]$11638 \reg case - assign $5\src17__data_o$next[3:0]$11573 $4\src17__data_o$next[3:0]$11572 + assign $5\src17__data_o$next[3:0]$11638 $4\src17__data_o$next[3:0]$11637 end case - assign $1\src17__data_o$next[3:0]$11569 4'0000 + assign $1\src17__data_o$next[3:0]$11634 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11574 4'0000 + assign $6\src17__data_o$next[3:0]$11639 4'0000 case - assign $6\src17__data_o$next[3:0]$11574 $1\src17__data_o$next[3:0]$11569 + assign $6\src17__data_o$next[3:0]$11639 $1\src17__data_o$next[3:0]$11634 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11568 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11633 end - attribute \src "libresoc.v:172308.3-172337.6" - process $proc$libresoc.v:172308$11575 + attribute \src "libresoc.v:181013.3-181042.6" + process $proc$libresoc.v:181013$11640 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:172309.5-172309.29" + attribute \src "libresoc.v:181014.5-181014.29" switch \initial - attribute \src "libresoc.v:172309.9-172309.17" + attribute \src "libresoc.v:181014.9-181014.17" case 1'1 case end @@ -358580,17 +373577,17 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:172338.3-172364.6" - process $proc$libresoc.v:172338$11576 + attribute \src "libresoc.v:181043.3-181069.6" + process $proc$libresoc.v:181043$11641 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11577 $4\reg$next[3:0]$11581 - attribute \src "libresoc.v:172339.5-172339.29" + assign $0\reg$next[3:0]$11642 $4\reg$next[3:0]$11646 + attribute \src "libresoc.v:181044.5-181044.29" switch \initial - attribute \src "libresoc.v:172339.9-172339.17" + attribute \src "libresoc.v:181044.9-181044.17" case 1'1 case end @@ -358599,49 +373596,49 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11578 \dest17__data_i + assign $1\reg$next[3:0]$11643 \dest17__data_i case - assign $1\reg$next[3:0]$11578 \reg + assign $1\reg$next[3:0]$11643 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11579 \dest27__data_i + assign $2\reg$next[3:0]$11644 \dest27__data_i case - assign $2\reg$next[3:0]$11579 $1\reg$next[3:0]$11578 + assign $2\reg$next[3:0]$11644 $1\reg$next[3:0]$11643 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11580 \w7__data_i + assign $3\reg$next[3:0]$11645 \w7__data_i case - assign $3\reg$next[3:0]$11580 $2\reg$next[3:0]$11579 + assign $3\reg$next[3:0]$11645 $2\reg$next[3:0]$11644 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11581 4'0000 + assign $4\reg$next[3:0]$11646 4'0000 case - assign $4\reg$next[3:0]$11581 $3\reg$next[3:0]$11580 + assign $4\reg$next[3:0]$11646 $3\reg$next[3:0]$11645 end sync always - update \reg$next $0\reg$next[3:0]$11577 + update \reg$next $0\reg$next[3:0]$11642 end - attribute \src "libresoc.v:172365.3-172404.6" - process $proc$libresoc.v:172365$11582 + attribute \src "libresoc.v:181070.3-181109.6" + process $proc$libresoc.v:181070$11647 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11583 $6\src27__data_o$next[3:0]$11589 - attribute \src "libresoc.v:172366.5-172366.29" + assign $0\src27__data_o$next[3:0]$11648 $6\src27__data_o$next[3:0]$11654 + attribute \src "libresoc.v:181071.5-181071.29" switch \initial - attribute \src "libresoc.v:172366.9-172366.17" + attribute \src "libresoc.v:181071.9-181071.17" case 1'1 case end @@ -358653,66 +373650,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11584 $5\src27__data_o$next[3:0]$11588 + assign $1\src27__data_o$next[3:0]$11649 $5\src27__data_o$next[3:0]$11653 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11585 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11650 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11585 4'0000 + assign $2\src27__data_o$next[3:0]$11650 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11586 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11651 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11586 $2\src27__data_o$next[3:0]$11585 + assign $3\src27__data_o$next[3:0]$11651 $2\src27__data_o$next[3:0]$11650 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11587 \w7__data_i + assign $4\src27__data_o$next[3:0]$11652 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11587 $3\src27__data_o$next[3:0]$11586 + assign $4\src27__data_o$next[3:0]$11652 $3\src27__data_o$next[3:0]$11651 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11588 \reg + assign $5\src27__data_o$next[3:0]$11653 \reg case - assign $5\src27__data_o$next[3:0]$11588 $4\src27__data_o$next[3:0]$11587 + assign $5\src27__data_o$next[3:0]$11653 $4\src27__data_o$next[3:0]$11652 end case - assign $1\src27__data_o$next[3:0]$11584 4'0000 + assign $1\src27__data_o$next[3:0]$11649 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11589 4'0000 + assign $6\src27__data_o$next[3:0]$11654 4'0000 case - assign $6\src27__data_o$next[3:0]$11589 $1\src27__data_o$next[3:0]$11584 + assign $6\src27__data_o$next[3:0]$11654 $1\src27__data_o$next[3:0]$11649 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11583 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11648 end - attribute \src "libresoc.v:172405.3-172434.6" - process $proc$libresoc.v:172405$11590 + attribute \src "libresoc.v:181110.3-181139.6" + process $proc$libresoc.v:181110$11655 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11591 $1\wr_detect$4[0:0]$11592 - attribute \src "libresoc.v:172406.5-172406.29" + assign $0\wr_detect$4[0:0]$11656 $1\wr_detect$4[0:0]$11657 + attribute \src "libresoc.v:181111.5-181111.29" switch \initial - attribute \src "libresoc.v:172406.9-172406.17" + attribute \src "libresoc.v:181111.9-181111.17" case 1'1 case end @@ -358724,49 +373721,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11592 $4\wr_detect$4[0:0]$11595 + assign $1\wr_detect$4[0:0]$11657 $4\wr_detect$4[0:0]$11660 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11593 1'1 + assign $2\wr_detect$4[0:0]$11658 1'1 case - assign $2\wr_detect$4[0:0]$11593 1'0 + assign $2\wr_detect$4[0:0]$11658 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11594 1'1 + assign $3\wr_detect$4[0:0]$11659 1'1 case - assign $3\wr_detect$4[0:0]$11594 $2\wr_detect$4[0:0]$11593 + assign $3\wr_detect$4[0:0]$11659 $2\wr_detect$4[0:0]$11658 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11595 1'1 + assign $4\wr_detect$4[0:0]$11660 1'1 case - assign $4\wr_detect$4[0:0]$11595 $3\wr_detect$4[0:0]$11594 + assign $4\wr_detect$4[0:0]$11660 $3\wr_detect$4[0:0]$11659 end case - assign $1\wr_detect$4[0:0]$11592 1'0 + assign $1\wr_detect$4[0:0]$11657 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11591 + update \wr_detect$4 $0\wr_detect$4[0:0]$11656 end - attribute \src "libresoc.v:172435.3-172474.6" - process $proc$libresoc.v:172435$11596 + attribute \src "libresoc.v:181140.3-181179.6" + process $proc$libresoc.v:181140$11661 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11597 $6\src37__data_o$next[3:0]$11603 - attribute \src "libresoc.v:172436.5-172436.29" + assign $0\src37__data_o$next[3:0]$11662 $6\src37__data_o$next[3:0]$11668 + attribute \src "libresoc.v:181141.5-181141.29" switch \initial - attribute \src "libresoc.v:172436.9-172436.17" + attribute \src "libresoc.v:181141.9-181141.17" case 1'1 case end @@ -358778,66 +373775,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$11598 $5\src37__data_o$next[3:0]$11602 + assign $1\src37__data_o$next[3:0]$11663 $5\src37__data_o$next[3:0]$11667 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$11599 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11664 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$11599 4'0000 + assign $2\src37__data_o$next[3:0]$11664 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$11600 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11665 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$11600 $2\src37__data_o$next[3:0]$11599 + assign $3\src37__data_o$next[3:0]$11665 $2\src37__data_o$next[3:0]$11664 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$11601 \w7__data_i + assign $4\src37__data_o$next[3:0]$11666 \w7__data_i case - assign $4\src37__data_o$next[3:0]$11601 $3\src37__data_o$next[3:0]$11600 + assign $4\src37__data_o$next[3:0]$11666 $3\src37__data_o$next[3:0]$11665 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$11602 \reg + assign $5\src37__data_o$next[3:0]$11667 \reg case - assign $5\src37__data_o$next[3:0]$11602 $4\src37__data_o$next[3:0]$11601 + assign $5\src37__data_o$next[3:0]$11667 $4\src37__data_o$next[3:0]$11666 end case - assign $1\src37__data_o$next[3:0]$11598 4'0000 + assign $1\src37__data_o$next[3:0]$11663 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$11603 4'0000 + assign $6\src37__data_o$next[3:0]$11668 4'0000 case - assign $6\src37__data_o$next[3:0]$11603 $1\src37__data_o$next[3:0]$11598 + assign $6\src37__data_o$next[3:0]$11668 $1\src37__data_o$next[3:0]$11663 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11597 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11662 end - attribute \src "libresoc.v:172475.3-172504.6" - process $proc$libresoc.v:172475$11604 + attribute \src "libresoc.v:181180.3-181209.6" + process $proc$libresoc.v:181180$11669 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11605 $1\wr_detect$7[0:0]$11606 - attribute \src "libresoc.v:172476.5-172476.29" + assign $0\wr_detect$7[0:0]$11670 $1\wr_detect$7[0:0]$11671 + attribute \src "libresoc.v:181181.5-181181.29" switch \initial - attribute \src "libresoc.v:172476.9-172476.17" + attribute \src "libresoc.v:181181.9-181181.17" case 1'1 case end @@ -358849,49 +373846,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11606 $4\wr_detect$7[0:0]$11609 + assign $1\wr_detect$7[0:0]$11671 $4\wr_detect$7[0:0]$11674 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11607 1'1 + assign $2\wr_detect$7[0:0]$11672 1'1 case - assign $2\wr_detect$7[0:0]$11607 1'0 + assign $2\wr_detect$7[0:0]$11672 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11608 1'1 + assign $3\wr_detect$7[0:0]$11673 1'1 case - assign $3\wr_detect$7[0:0]$11608 $2\wr_detect$7[0:0]$11607 + assign $3\wr_detect$7[0:0]$11673 $2\wr_detect$7[0:0]$11672 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11609 1'1 + assign $4\wr_detect$7[0:0]$11674 1'1 case - assign $4\wr_detect$7[0:0]$11609 $3\wr_detect$7[0:0]$11608 + assign $4\wr_detect$7[0:0]$11674 $3\wr_detect$7[0:0]$11673 end case - assign $1\wr_detect$7[0:0]$11606 1'0 + assign $1\wr_detect$7[0:0]$11671 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11605 + update \wr_detect$7 $0\wr_detect$7[0:0]$11670 end - attribute \src "libresoc.v:172505.3-172544.6" - process $proc$libresoc.v:172505$11610 + attribute \src "libresoc.v:181210.3-181249.6" + process $proc$libresoc.v:181210$11675 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$11611 $6\r7__data_o$next[3:0]$11617 - attribute \src "libresoc.v:172506.5-172506.29" + assign $0\r7__data_o$next[3:0]$11676 $6\r7__data_o$next[3:0]$11682 + attribute \src "libresoc.v:181211.5-181211.29" switch \initial - attribute \src "libresoc.v:172506.9-172506.17" + attribute \src "libresoc.v:181211.9-181211.17" case 1'1 case end @@ -358903,66 +373900,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$11612 $5\r7__data_o$next[3:0]$11616 + assign $1\r7__data_o$next[3:0]$11677 $5\r7__data_o$next[3:0]$11681 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$11613 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11678 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$11613 4'0000 + assign $2\r7__data_o$next[3:0]$11678 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$11614 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11679 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$11614 $2\r7__data_o$next[3:0]$11613 + assign $3\r7__data_o$next[3:0]$11679 $2\r7__data_o$next[3:0]$11678 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$11615 \w7__data_i + assign $4\r7__data_o$next[3:0]$11680 \w7__data_i case - assign $4\r7__data_o$next[3:0]$11615 $3\r7__data_o$next[3:0]$11614 + assign $4\r7__data_o$next[3:0]$11680 $3\r7__data_o$next[3:0]$11679 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$11616 \reg + assign $5\r7__data_o$next[3:0]$11681 \reg case - assign $5\r7__data_o$next[3:0]$11616 $4\r7__data_o$next[3:0]$11615 + assign $5\r7__data_o$next[3:0]$11681 $4\r7__data_o$next[3:0]$11680 end case - assign $1\r7__data_o$next[3:0]$11612 4'0000 + assign $1\r7__data_o$next[3:0]$11677 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$11617 4'0000 + assign $6\r7__data_o$next[3:0]$11682 4'0000 case - assign $6\r7__data_o$next[3:0]$11617 $1\r7__data_o$next[3:0]$11612 + assign $6\r7__data_o$next[3:0]$11682 $1\r7__data_o$next[3:0]$11677 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11611 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11676 end - attribute \src "libresoc.v:172545.3-172574.6" - process $proc$libresoc.v:172545$11618 + attribute \src "libresoc.v:181250.3-181279.6" + process $proc$libresoc.v:181250$11683 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11619 $1\wr_detect$10[0:0]$11620 - attribute \src "libresoc.v:172546.5-172546.29" + assign $0\wr_detect$10[0:0]$11684 $1\wr_detect$10[0:0]$11685 + attribute \src "libresoc.v:181251.5-181251.29" switch \initial - attribute \src "libresoc.v:172546.9-172546.17" + attribute \src "libresoc.v:181251.9-181251.17" case 1'1 case end @@ -358974,49 +373971,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11620 $4\wr_detect$10[0:0]$11623 + assign $1\wr_detect$10[0:0]$11685 $4\wr_detect$10[0:0]$11688 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11621 1'1 + assign $2\wr_detect$10[0:0]$11686 1'1 case - assign $2\wr_detect$10[0:0]$11621 1'0 + assign $2\wr_detect$10[0:0]$11686 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11622 1'1 + assign $3\wr_detect$10[0:0]$11687 1'1 case - assign $3\wr_detect$10[0:0]$11622 $2\wr_detect$10[0:0]$11621 + assign $3\wr_detect$10[0:0]$11687 $2\wr_detect$10[0:0]$11686 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11623 1'1 + assign $4\wr_detect$10[0:0]$11688 1'1 case - assign $4\wr_detect$10[0:0]$11623 $3\wr_detect$10[0:0]$11622 + assign $4\wr_detect$10[0:0]$11688 $3\wr_detect$10[0:0]$11687 end case - assign $1\wr_detect$10[0:0]$11620 1'0 + assign $1\wr_detect$10[0:0]$11685 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11619 + update \wr_detect$10 $0\wr_detect$10[0:0]$11684 end - attribute \src "libresoc.v:172575.3-172614.6" - process $proc$libresoc.v:172575$11624 + attribute \src "libresoc.v:181280.3-181319.6" + process $proc$libresoc.v:181280$11689 assign { } { } assign { } { } assign { } { } - assign $0\r27__data_o$next[3:0]$11625 $6\r27__data_o$next[3:0]$11631 - attribute \src "libresoc.v:172576.5-172576.29" + assign $0\r27__data_o$next[3:0]$11690 $6\r27__data_o$next[3:0]$11696 + attribute \src "libresoc.v:181281.5-181281.29" switch \initial - attribute \src "libresoc.v:172576.9-172576.17" + attribute \src "libresoc.v:181281.9-181281.17" case 1'1 case end @@ -359028,66 +374025,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r27__data_o$next[3:0]$11626 $5\r27__data_o$next[3:0]$11630 + assign $1\r27__data_o$next[3:0]$11691 $5\r27__data_o$next[3:0]$11695 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r27__data_o$next[3:0]$11627 \dest17__data_i + assign $2\r27__data_o$next[3:0]$11692 \dest17__data_i case - assign $2\r27__data_o$next[3:0]$11627 4'0000 + assign $2\r27__data_o$next[3:0]$11692 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r27__data_o$next[3:0]$11628 \dest27__data_i + assign $3\r27__data_o$next[3:0]$11693 \dest27__data_i case - assign $3\r27__data_o$next[3:0]$11628 $2\r27__data_o$next[3:0]$11627 + assign $3\r27__data_o$next[3:0]$11693 $2\r27__data_o$next[3:0]$11692 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r27__data_o$next[3:0]$11629 \w7__data_i + assign $4\r27__data_o$next[3:0]$11694 \w7__data_i case - assign $4\r27__data_o$next[3:0]$11629 $3\r27__data_o$next[3:0]$11628 + assign $4\r27__data_o$next[3:0]$11694 $3\r27__data_o$next[3:0]$11693 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r27__data_o$next[3:0]$11630 \reg + assign $5\r27__data_o$next[3:0]$11695 \reg case - assign $5\r27__data_o$next[3:0]$11630 $4\r27__data_o$next[3:0]$11629 + assign $5\r27__data_o$next[3:0]$11695 $4\r27__data_o$next[3:0]$11694 end case - assign $1\r27__data_o$next[3:0]$11626 4'0000 + assign $1\r27__data_o$next[3:0]$11691 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r27__data_o$next[3:0]$11631 4'0000 + assign $6\r27__data_o$next[3:0]$11696 4'0000 case - assign $6\r27__data_o$next[3:0]$11631 $1\r27__data_o$next[3:0]$11626 + assign $6\r27__data_o$next[3:0]$11696 $1\r27__data_o$next[3:0]$11691 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11625 + update \r27__data_o$next $0\r27__data_o$next[3:0]$11690 end - attribute \src "libresoc.v:172615.3-172644.6" - process $proc$libresoc.v:172615$11632 + attribute \src "libresoc.v:181320.3-181349.6" + process $proc$libresoc.v:181320$11697 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11633 $1\wr_detect$13[0:0]$11634 - attribute \src "libresoc.v:172616.5-172616.29" + assign $0\wr_detect$13[0:0]$11698 $1\wr_detect$13[0:0]$11699 + attribute \src "libresoc.v:181321.5-181321.29" switch \initial - attribute \src "libresoc.v:172616.9-172616.17" + attribute \src "libresoc.v:181321.9-181321.17" case 1'1 case end @@ -359099,115 +374096,115 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11634 $4\wr_detect$13[0:0]$11637 + assign $1\wr_detect$13[0:0]$11699 $4\wr_detect$13[0:0]$11702 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11635 1'1 + assign $2\wr_detect$13[0:0]$11700 1'1 case - assign $2\wr_detect$13[0:0]$11635 1'0 + assign $2\wr_detect$13[0:0]$11700 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11636 1'1 + assign $3\wr_detect$13[0:0]$11701 1'1 case - assign $3\wr_detect$13[0:0]$11636 $2\wr_detect$13[0:0]$11635 + assign $3\wr_detect$13[0:0]$11701 $2\wr_detect$13[0:0]$11700 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11637 1'1 + assign $4\wr_detect$13[0:0]$11702 1'1 case - assign $4\wr_detect$13[0:0]$11637 $3\wr_detect$13[0:0]$11636 + assign $4\wr_detect$13[0:0]$11702 $3\wr_detect$13[0:0]$11701 end case - assign $1\wr_detect$13[0:0]$11634 1'0 + assign $1\wr_detect$13[0:0]$11699 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11633 + update \wr_detect$13 $0\wr_detect$13[0:0]$11698 end - connect \$9 $not$libresoc.v:172251$11556_Y - connect \$12 $not$libresoc.v:172252$11557_Y - connect \$1 $not$libresoc.v:172253$11558_Y - connect \$3 $not$libresoc.v:172254$11559_Y - connect \$6 $not$libresoc.v:172255$11560_Y + connect \$9 $not$libresoc.v:180956$11621_Y + connect \$12 $not$libresoc.v:180957$11622_Y + connect \$1 $not$libresoc.v:180958$11623_Y + connect \$3 $not$libresoc.v:180959$11624_Y + connect \$6 $not$libresoc.v:180960$11625_Y end -attribute \src "libresoc.v:172649.1-172707.10" +attribute \src "libresoc.v:181354.1-181412.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:172650.7-172650.20" + attribute \src "libresoc.v:181355.7-181355.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172695.3-172703.6" - wire width 5 $0\q_int$next[4:0]$11655 - attribute \src "libresoc.v:172693.3-172694.27" + attribute \src "libresoc.v:181400.3-181408.6" + wire width 5 $0\q_int$next[4:0]$11720 + attribute \src "libresoc.v:181398.3-181399.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:172695.3-172703.6" - wire width 5 $1\q_int$next[4:0]$11656 - attribute \src "libresoc.v:172672.13-172672.26" + attribute \src "libresoc.v:181400.3-181408.6" + wire width 5 $1\q_int$next[4:0]$11721 + attribute \src "libresoc.v:181377.13-181377.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:172685.17-172685.96" - wire width 5 $and$libresoc.v:172685$11645_Y - attribute \src "libresoc.v:172690.17-172690.96" - wire width 5 $and$libresoc.v:172690$11650_Y - attribute \src "libresoc.v:172687.18-172687.93" - wire width 5 $not$libresoc.v:172687$11647_Y - attribute \src "libresoc.v:172689.17-172689.92" - wire width 5 $not$libresoc.v:172689$11649_Y - attribute \src "libresoc.v:172692.17-172692.92" - wire width 5 $not$libresoc.v:172692$11652_Y - attribute \src "libresoc.v:172686.18-172686.98" - wire width 5 $or$libresoc.v:172686$11646_Y - attribute \src "libresoc.v:172688.18-172688.99" - wire width 5 $or$libresoc.v:172688$11648_Y - attribute \src "libresoc.v:172691.17-172691.97" - wire width 5 $or$libresoc.v:172691$11651_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181390.17-181390.96" + wire width 5 $and$libresoc.v:181390$11710_Y + attribute \src "libresoc.v:181395.17-181395.96" + wire width 5 $and$libresoc.v:181395$11715_Y + attribute \src "libresoc.v:181392.18-181392.93" + wire width 5 $not$libresoc.v:181392$11712_Y + attribute \src "libresoc.v:181394.17-181394.92" + wire width 5 $not$libresoc.v:181394$11714_Y + attribute \src "libresoc.v:181397.17-181397.92" + wire width 5 $not$libresoc.v:181397$11717_Y + attribute \src "libresoc.v:181391.18-181391.98" + wire width 5 $or$libresoc.v:181391$11711_Y + attribute \src "libresoc.v:181393.18-181393.99" + wire width 5 $or$libresoc.v:181393$11713_Y + attribute \src "libresoc.v:181396.17-181396.97" + wire width 5 $or$libresoc.v:181396$11716_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:172650.7-172650.15" + attribute \src "libresoc.v:181355.7-181355.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172685$11645 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181390$11710 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -359215,10 +374212,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172685$11645_Y + connect \Y $and$libresoc.v:181390$11710_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172690$11650 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181395$11715 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -359226,34 +374223,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:172690$11650_Y + connect \Y $and$libresoc.v:181395$11715_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172687$11647 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181392$11712 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:172687$11647_Y + connect \Y $not$libresoc.v:181392$11712_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172689$11649 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181394$11714 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:172689$11649_Y + connect \Y $not$libresoc.v:181394$11714_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172692$11652 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181397$11717 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:172692$11652_Y + connect \Y $not$libresoc.v:181397$11717_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172686$11646 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181391$11711 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -359261,10 +374258,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:172686$11646_Y + connect \Y $or$libresoc.v:181391$11711_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172688$11648 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181393$11713 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -359272,10 +374269,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:172688$11648_Y + connect \Y $or$libresoc.v:181393$11713_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172691$11651 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181396$11716 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -359283,39 +374280,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:172691$11651_Y + connect \Y $or$libresoc.v:181396$11716_Y end - attribute \src "libresoc.v:172650.7-172650.20" - process $proc$libresoc.v:172650$11657 + attribute \src "libresoc.v:181355.7-181355.20" + process $proc$libresoc.v:181355$11722 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172672.13-172672.26" - process $proc$libresoc.v:172672$11658 + attribute \src "libresoc.v:181377.13-181377.26" + process $proc$libresoc.v:181377$11723 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:172693.3-172694.27" - process $proc$libresoc.v:172693$11653 + attribute \src "libresoc.v:181398.3-181399.27" + process $proc$libresoc.v:181398$11718 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:172695.3-172703.6" - process $proc$libresoc.v:172695$11654 + attribute \src "libresoc.v:181400.3-181408.6" + process $proc$libresoc.v:181400$11719 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11655 $1\q_int$next[4:0]$11656 - attribute \src "libresoc.v:172696.5-172696.29" + assign $0\q_int$next[4:0]$11720 $1\q_int$next[4:0]$11721 + attribute \src "libresoc.v:181401.5-181401.29" switch \initial - attribute \src "libresoc.v:172696.9-172696.17" + attribute \src "libresoc.v:181401.9-181401.17" case 1'1 case end @@ -359324,94 +374321,94 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11656 5'00000 + assign $1\q_int$next[4:0]$11721 5'00000 case - assign $1\q_int$next[4:0]$11656 \$5 + assign $1\q_int$next[4:0]$11721 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11655 + update \q_int$next $0\q_int$next[4:0]$11720 end - connect \$9 $and$libresoc.v:172685$11645_Y - connect \$11 $or$libresoc.v:172686$11646_Y - connect \$13 $not$libresoc.v:172687$11647_Y - connect \$15 $or$libresoc.v:172688$11648_Y - connect \$1 $not$libresoc.v:172689$11649_Y - connect \$3 $and$libresoc.v:172690$11650_Y - connect \$5 $or$libresoc.v:172691$11651_Y - connect \$7 $not$libresoc.v:172692$11652_Y + connect \$9 $and$libresoc.v:181390$11710_Y + connect \$11 $or$libresoc.v:181391$11711_Y + connect \$13 $not$libresoc.v:181392$11712_Y + connect \$15 $or$libresoc.v:181393$11713_Y + connect \$1 $not$libresoc.v:181394$11714_Y + connect \$3 $and$libresoc.v:181395$11715_Y + connect \$5 $or$libresoc.v:181396$11716_Y + connect \$7 $not$libresoc.v:181397$11717_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:172711.1-172769.10" +attribute \src "libresoc.v:181416.1-181474.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:172712.7-172712.20" + attribute \src "libresoc.v:181417.7-181417.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172757.3-172765.6" - wire width 4 $0\q_int$next[3:0]$11669 - attribute \src "libresoc.v:172755.3-172756.27" + attribute \src "libresoc.v:181462.3-181470.6" + wire width 4 $0\q_int$next[3:0]$11734 + attribute \src "libresoc.v:181460.3-181461.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:172757.3-172765.6" - wire width 4 $1\q_int$next[3:0]$11670 - attribute \src "libresoc.v:172734.13-172734.25" + attribute \src "libresoc.v:181462.3-181470.6" + wire width 4 $1\q_int$next[3:0]$11735 + attribute \src "libresoc.v:181439.13-181439.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:172747.17-172747.96" - wire width 4 $and$libresoc.v:172747$11659_Y - attribute \src "libresoc.v:172752.17-172752.96" - wire width 4 $and$libresoc.v:172752$11664_Y - attribute \src "libresoc.v:172749.18-172749.93" - wire width 4 $not$libresoc.v:172749$11661_Y - attribute \src "libresoc.v:172751.17-172751.92" - wire width 4 $not$libresoc.v:172751$11663_Y - attribute \src "libresoc.v:172754.17-172754.92" - wire width 4 $not$libresoc.v:172754$11666_Y - attribute \src "libresoc.v:172748.18-172748.98" - wire width 4 $or$libresoc.v:172748$11660_Y - attribute \src "libresoc.v:172750.18-172750.99" - wire width 4 $or$libresoc.v:172750$11662_Y - attribute \src "libresoc.v:172753.17-172753.97" - wire width 4 $or$libresoc.v:172753$11665_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181452.17-181452.96" + wire width 4 $and$libresoc.v:181452$11724_Y + attribute \src "libresoc.v:181457.17-181457.96" + wire width 4 $and$libresoc.v:181457$11729_Y + attribute \src "libresoc.v:181454.18-181454.93" + wire width 4 $not$libresoc.v:181454$11726_Y + attribute \src "libresoc.v:181456.17-181456.92" + wire width 4 $not$libresoc.v:181456$11728_Y + attribute \src "libresoc.v:181459.17-181459.92" + wire width 4 $not$libresoc.v:181459$11731_Y + attribute \src "libresoc.v:181453.18-181453.98" + wire width 4 $or$libresoc.v:181453$11725_Y + attribute \src "libresoc.v:181455.18-181455.99" + wire width 4 $or$libresoc.v:181455$11727_Y + attribute \src "libresoc.v:181458.17-181458.97" + wire width 4 $or$libresoc.v:181458$11730_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:172712.7-172712.15" + attribute \src "libresoc.v:181417.7-181417.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172747$11659 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181452$11724 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359419,10 +374416,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172747$11659_Y + connect \Y $and$libresoc.v:181452$11724_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172752$11664 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181457$11729 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359430,34 +374427,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:172752$11664_Y + connect \Y $and$libresoc.v:181457$11729_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172749$11661 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181454$11726 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:172749$11661_Y + connect \Y $not$libresoc.v:181454$11726_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172751$11663 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181456$11728 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:172751$11663_Y + connect \Y $not$libresoc.v:181456$11728_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172754$11666 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181459$11731 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:172754$11666_Y + connect \Y $not$libresoc.v:181459$11731_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172748$11660 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181453$11725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359465,10 +374462,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:172748$11660_Y + connect \Y $or$libresoc.v:181453$11725_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172750$11662 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181455$11727 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359476,10 +374473,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:172750$11662_Y + connect \Y $or$libresoc.v:181455$11727_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172753$11665 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181458$11730 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359487,39 +374484,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:172753$11665_Y + connect \Y $or$libresoc.v:181458$11730_Y end - attribute \src "libresoc.v:172712.7-172712.20" - process $proc$libresoc.v:172712$11671 + attribute \src "libresoc.v:181417.7-181417.20" + process $proc$libresoc.v:181417$11736 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172734.13-172734.25" - process $proc$libresoc.v:172734$11672 + attribute \src "libresoc.v:181439.13-181439.25" + process $proc$libresoc.v:181439$11737 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:172755.3-172756.27" - process $proc$libresoc.v:172755$11667 + attribute \src "libresoc.v:181460.3-181461.27" + process $proc$libresoc.v:181460$11732 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:172757.3-172765.6" - process $proc$libresoc.v:172757$11668 + attribute \src "libresoc.v:181462.3-181470.6" + process $proc$libresoc.v:181462$11733 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11669 $1\q_int$next[3:0]$11670 - attribute \src "libresoc.v:172758.5-172758.29" + assign $0\q_int$next[3:0]$11734 $1\q_int$next[3:0]$11735 + attribute \src "libresoc.v:181463.5-181463.29" switch \initial - attribute \src "libresoc.v:172758.9-172758.17" + attribute \src "libresoc.v:181463.9-181463.17" case 1'1 case end @@ -359528,94 +374525,94 @@ module \req_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11670 4'0000 + assign $1\q_int$next[3:0]$11735 4'0000 case - assign $1\q_int$next[3:0]$11670 \$5 + assign $1\q_int$next[3:0]$11735 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11669 + update \q_int$next $0\q_int$next[3:0]$11734 end - connect \$9 $and$libresoc.v:172747$11659_Y - connect \$11 $or$libresoc.v:172748$11660_Y - connect \$13 $not$libresoc.v:172749$11661_Y - connect \$15 $or$libresoc.v:172750$11662_Y - connect \$1 $not$libresoc.v:172751$11663_Y - connect \$3 $and$libresoc.v:172752$11664_Y - connect \$5 $or$libresoc.v:172753$11665_Y - connect \$7 $not$libresoc.v:172754$11666_Y + connect \$9 $and$libresoc.v:181452$11724_Y + connect \$11 $or$libresoc.v:181453$11725_Y + connect \$13 $not$libresoc.v:181454$11726_Y + connect \$15 $or$libresoc.v:181455$11727_Y + connect \$1 $not$libresoc.v:181456$11728_Y + connect \$3 $and$libresoc.v:181457$11729_Y + connect \$5 $or$libresoc.v:181458$11730_Y + connect \$7 $not$libresoc.v:181459$11731_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:172773.1-172831.10" +attribute \src "libresoc.v:181478.1-181536.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:172774.7-172774.20" + attribute \src "libresoc.v:181479.7-181479.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172819.3-172827.6" - wire width 3 $0\q_int$next[2:0]$11683 - attribute \src "libresoc.v:172817.3-172818.27" + attribute \src "libresoc.v:181524.3-181532.6" + wire width 3 $0\q_int$next[2:0]$11748 + attribute \src "libresoc.v:181522.3-181523.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:172819.3-172827.6" - wire width 3 $1\q_int$next[2:0]$11684 - attribute \src "libresoc.v:172796.13-172796.25" + attribute \src "libresoc.v:181524.3-181532.6" + wire width 3 $1\q_int$next[2:0]$11749 + attribute \src "libresoc.v:181501.13-181501.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:172809.17-172809.96" - wire width 3 $and$libresoc.v:172809$11673_Y - attribute \src "libresoc.v:172814.17-172814.96" - wire width 3 $and$libresoc.v:172814$11678_Y - attribute \src "libresoc.v:172811.18-172811.93" - wire width 3 $not$libresoc.v:172811$11675_Y - attribute \src "libresoc.v:172813.17-172813.92" - wire width 3 $not$libresoc.v:172813$11677_Y - attribute \src "libresoc.v:172816.17-172816.92" - wire width 3 $not$libresoc.v:172816$11680_Y - attribute \src "libresoc.v:172810.18-172810.98" - wire width 3 $or$libresoc.v:172810$11674_Y - attribute \src "libresoc.v:172812.18-172812.99" - wire width 3 $or$libresoc.v:172812$11676_Y - attribute \src "libresoc.v:172815.17-172815.97" - wire width 3 $or$libresoc.v:172815$11679_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181514.17-181514.96" + wire width 3 $and$libresoc.v:181514$11738_Y + attribute \src "libresoc.v:181519.17-181519.96" + wire width 3 $and$libresoc.v:181519$11743_Y + attribute \src "libresoc.v:181516.18-181516.93" + wire width 3 $not$libresoc.v:181516$11740_Y + attribute \src "libresoc.v:181518.17-181518.92" + wire width 3 $not$libresoc.v:181518$11742_Y + attribute \src "libresoc.v:181521.17-181521.92" + wire width 3 $not$libresoc.v:181521$11745_Y + attribute \src "libresoc.v:181515.18-181515.98" + wire width 3 $or$libresoc.v:181515$11739_Y + attribute \src "libresoc.v:181517.18-181517.99" + wire width 3 $or$libresoc.v:181517$11741_Y + attribute \src "libresoc.v:181520.17-181520.97" + wire width 3 $or$libresoc.v:181520$11744_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:172774.7-172774.15" + attribute \src "libresoc.v:181479.7-181479.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172809$11673 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181514$11738 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359623,10 +374620,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172809$11673_Y + connect \Y $and$libresoc.v:181514$11738_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172814$11678 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181519$11743 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359634,34 +374631,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:172814$11678_Y + connect \Y $and$libresoc.v:181519$11743_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172811$11675 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181516$11740 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:172811$11675_Y + connect \Y $not$libresoc.v:181516$11740_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172813$11677 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181518$11742 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:172813$11677_Y + connect \Y $not$libresoc.v:181518$11742_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172816$11680 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181521$11745 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:172816$11680_Y + connect \Y $not$libresoc.v:181521$11745_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172810$11674 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181515$11739 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359669,10 +374666,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:172810$11674_Y + connect \Y $or$libresoc.v:181515$11739_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172812$11676 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181517$11741 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359680,10 +374677,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:172812$11676_Y + connect \Y $or$libresoc.v:181517$11741_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172815$11679 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181520$11744 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359691,39 +374688,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:172815$11679_Y + connect \Y $or$libresoc.v:181520$11744_Y end - attribute \src "libresoc.v:172774.7-172774.20" - process $proc$libresoc.v:172774$11685 + attribute \src "libresoc.v:181479.7-181479.20" + process $proc$libresoc.v:181479$11750 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172796.13-172796.25" - process $proc$libresoc.v:172796$11686 + attribute \src "libresoc.v:181501.13-181501.25" + process $proc$libresoc.v:181501$11751 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:172817.3-172818.27" - process $proc$libresoc.v:172817$11681 + attribute \src "libresoc.v:181522.3-181523.27" + process $proc$libresoc.v:181522$11746 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:172819.3-172827.6" - process $proc$libresoc.v:172819$11682 + attribute \src "libresoc.v:181524.3-181532.6" + process $proc$libresoc.v:181524$11747 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11683 $1\q_int$next[2:0]$11684 - attribute \src "libresoc.v:172820.5-172820.29" + assign $0\q_int$next[2:0]$11748 $1\q_int$next[2:0]$11749 + attribute \src "libresoc.v:181525.5-181525.29" switch \initial - attribute \src "libresoc.v:172820.9-172820.17" + attribute \src "libresoc.v:181525.9-181525.17" case 1'1 case end @@ -359732,94 +374729,94 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11684 3'000 + assign $1\q_int$next[2:0]$11749 3'000 case - assign $1\q_int$next[2:0]$11684 \$5 + assign $1\q_int$next[2:0]$11749 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11683 + update \q_int$next $0\q_int$next[2:0]$11748 end - connect \$9 $and$libresoc.v:172809$11673_Y - connect \$11 $or$libresoc.v:172810$11674_Y - connect \$13 $not$libresoc.v:172811$11675_Y - connect \$15 $or$libresoc.v:172812$11676_Y - connect \$1 $not$libresoc.v:172813$11677_Y - connect \$3 $and$libresoc.v:172814$11678_Y - connect \$5 $or$libresoc.v:172815$11679_Y - connect \$7 $not$libresoc.v:172816$11680_Y + connect \$9 $and$libresoc.v:181514$11738_Y + connect \$11 $or$libresoc.v:181515$11739_Y + connect \$13 $not$libresoc.v:181516$11740_Y + connect \$15 $or$libresoc.v:181517$11741_Y + connect \$1 $not$libresoc.v:181518$11742_Y + connect \$3 $and$libresoc.v:181519$11743_Y + connect \$5 $or$libresoc.v:181520$11744_Y + connect \$7 $not$libresoc.v:181521$11745_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:172835.1-172893.10" +attribute \src "libresoc.v:181540.1-181598.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:172836.7-172836.20" + attribute \src "libresoc.v:181541.7-181541.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172881.3-172889.6" - wire width 3 $0\q_int$next[2:0]$11697 - attribute \src "libresoc.v:172879.3-172880.27" + attribute \src "libresoc.v:181586.3-181594.6" + wire width 3 $0\q_int$next[2:0]$11762 + attribute \src "libresoc.v:181584.3-181585.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:172881.3-172889.6" - wire width 3 $1\q_int$next[2:0]$11698 - attribute \src "libresoc.v:172858.13-172858.25" + attribute \src "libresoc.v:181586.3-181594.6" + wire width 3 $1\q_int$next[2:0]$11763 + attribute \src "libresoc.v:181563.13-181563.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:172871.17-172871.96" - wire width 3 $and$libresoc.v:172871$11687_Y - attribute \src "libresoc.v:172876.17-172876.96" - wire width 3 $and$libresoc.v:172876$11692_Y - attribute \src "libresoc.v:172873.18-172873.93" - wire width 3 $not$libresoc.v:172873$11689_Y - attribute \src "libresoc.v:172875.17-172875.92" - wire width 3 $not$libresoc.v:172875$11691_Y - attribute \src "libresoc.v:172878.17-172878.92" - wire width 3 $not$libresoc.v:172878$11694_Y - attribute \src "libresoc.v:172872.18-172872.98" - wire width 3 $or$libresoc.v:172872$11688_Y - attribute \src "libresoc.v:172874.18-172874.99" - wire width 3 $or$libresoc.v:172874$11690_Y - attribute \src "libresoc.v:172877.17-172877.97" - wire width 3 $or$libresoc.v:172877$11693_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181576.17-181576.96" + wire width 3 $and$libresoc.v:181576$11752_Y + attribute \src "libresoc.v:181581.17-181581.96" + wire width 3 $and$libresoc.v:181581$11757_Y + attribute \src "libresoc.v:181578.18-181578.93" + wire width 3 $not$libresoc.v:181578$11754_Y + attribute \src "libresoc.v:181580.17-181580.92" + wire width 3 $not$libresoc.v:181580$11756_Y + attribute \src "libresoc.v:181583.17-181583.92" + wire width 3 $not$libresoc.v:181583$11759_Y + attribute \src "libresoc.v:181577.18-181577.98" + wire width 3 $or$libresoc.v:181577$11753_Y + attribute \src "libresoc.v:181579.18-181579.99" + wire width 3 $or$libresoc.v:181579$11755_Y + attribute \src "libresoc.v:181582.17-181582.97" + wire width 3 $or$libresoc.v:181582$11758_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:172836.7-172836.15" + attribute \src "libresoc.v:181541.7-181541.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172871$11687 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181576$11752 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359827,10 +374824,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172871$11687_Y + connect \Y $and$libresoc.v:181576$11752_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172876$11692 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181581$11757 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359838,34 +374835,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:172876$11692_Y + connect \Y $and$libresoc.v:181581$11757_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172873$11689 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181578$11754 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:172873$11689_Y + connect \Y $not$libresoc.v:181578$11754_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172875$11691 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181580$11756 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:172875$11691_Y + connect \Y $not$libresoc.v:181580$11756_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172878$11694 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181583$11759 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:172878$11694_Y + connect \Y $not$libresoc.v:181583$11759_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172872$11688 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181577$11753 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359873,10 +374870,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:172872$11688_Y + connect \Y $or$libresoc.v:181577$11753_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172874$11690 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181579$11755 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359884,10 +374881,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:172874$11690_Y + connect \Y $or$libresoc.v:181579$11755_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172877$11693 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181582$11758 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359895,39 +374892,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:172877$11693_Y + connect \Y $or$libresoc.v:181582$11758_Y end - attribute \src "libresoc.v:172836.7-172836.20" - process $proc$libresoc.v:172836$11699 + attribute \src "libresoc.v:181541.7-181541.20" + process $proc$libresoc.v:181541$11764 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172858.13-172858.25" - process $proc$libresoc.v:172858$11700 + attribute \src "libresoc.v:181563.13-181563.25" + process $proc$libresoc.v:181563$11765 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:172879.3-172880.27" - process $proc$libresoc.v:172879$11695 + attribute \src "libresoc.v:181584.3-181585.27" + process $proc$libresoc.v:181584$11760 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:172881.3-172889.6" - process $proc$libresoc.v:172881$11696 + attribute \src "libresoc.v:181586.3-181594.6" + process $proc$libresoc.v:181586$11761 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11697 $1\q_int$next[2:0]$11698 - attribute \src "libresoc.v:172882.5-172882.29" + assign $0\q_int$next[2:0]$11762 $1\q_int$next[2:0]$11763 + attribute \src "libresoc.v:181587.5-181587.29" switch \initial - attribute \src "libresoc.v:172882.9-172882.17" + attribute \src "libresoc.v:181587.9-181587.17" case 1'1 case end @@ -359936,94 +374933,94 @@ module \req_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11698 3'000 + assign $1\q_int$next[2:0]$11763 3'000 case - assign $1\q_int$next[2:0]$11698 \$5 + assign $1\q_int$next[2:0]$11763 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11697 + update \q_int$next $0\q_int$next[2:0]$11762 end - connect \$9 $and$libresoc.v:172871$11687_Y - connect \$11 $or$libresoc.v:172872$11688_Y - connect \$13 $not$libresoc.v:172873$11689_Y - connect \$15 $or$libresoc.v:172874$11690_Y - connect \$1 $not$libresoc.v:172875$11691_Y - connect \$3 $and$libresoc.v:172876$11692_Y - connect \$5 $or$libresoc.v:172877$11693_Y - connect \$7 $not$libresoc.v:172878$11694_Y + connect \$9 $and$libresoc.v:181576$11752_Y + connect \$11 $or$libresoc.v:181577$11753_Y + connect \$13 $not$libresoc.v:181578$11754_Y + connect \$15 $or$libresoc.v:181579$11755_Y + connect \$1 $not$libresoc.v:181580$11756_Y + connect \$3 $and$libresoc.v:181581$11757_Y + connect \$5 $or$libresoc.v:181582$11758_Y + connect \$7 $not$libresoc.v:181583$11759_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:172897.1-172955.10" +attribute \src "libresoc.v:181602.1-181660.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:172898.7-172898.20" + attribute \src "libresoc.v:181603.7-181603.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172943.3-172951.6" - wire width 3 $0\q_int$next[2:0]$11711 - attribute \src "libresoc.v:172941.3-172942.27" + attribute \src "libresoc.v:181648.3-181656.6" + wire width 3 $0\q_int$next[2:0]$11776 + attribute \src "libresoc.v:181646.3-181647.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:172943.3-172951.6" - wire width 3 $1\q_int$next[2:0]$11712 - attribute \src "libresoc.v:172920.13-172920.25" + attribute \src "libresoc.v:181648.3-181656.6" + wire width 3 $1\q_int$next[2:0]$11777 + attribute \src "libresoc.v:181625.13-181625.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:172933.17-172933.96" - wire width 3 $and$libresoc.v:172933$11701_Y - attribute \src "libresoc.v:172938.17-172938.96" - wire width 3 $and$libresoc.v:172938$11706_Y - attribute \src "libresoc.v:172935.18-172935.93" - wire width 3 $not$libresoc.v:172935$11703_Y - attribute \src "libresoc.v:172937.17-172937.92" - wire width 3 $not$libresoc.v:172937$11705_Y - attribute \src "libresoc.v:172940.17-172940.92" - wire width 3 $not$libresoc.v:172940$11708_Y - attribute \src "libresoc.v:172934.18-172934.98" - wire width 3 $or$libresoc.v:172934$11702_Y - attribute \src "libresoc.v:172936.18-172936.99" - wire width 3 $or$libresoc.v:172936$11704_Y - attribute \src "libresoc.v:172939.17-172939.97" - wire width 3 $or$libresoc.v:172939$11707_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181638.17-181638.96" + wire width 3 $and$libresoc.v:181638$11766_Y + attribute \src "libresoc.v:181643.17-181643.96" + wire width 3 $and$libresoc.v:181643$11771_Y + attribute \src "libresoc.v:181640.18-181640.93" + wire width 3 $not$libresoc.v:181640$11768_Y + attribute \src "libresoc.v:181642.17-181642.92" + wire width 3 $not$libresoc.v:181642$11770_Y + attribute \src "libresoc.v:181645.17-181645.92" + wire width 3 $not$libresoc.v:181645$11773_Y + attribute \src "libresoc.v:181639.18-181639.98" + wire width 3 $or$libresoc.v:181639$11767_Y + attribute \src "libresoc.v:181641.18-181641.99" + wire width 3 $or$libresoc.v:181641$11769_Y + attribute \src "libresoc.v:181644.17-181644.97" + wire width 3 $or$libresoc.v:181644$11772_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:172898.7-172898.15" + attribute \src "libresoc.v:181603.7-181603.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172933$11701 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181638$11766 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360031,10 +375028,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172933$11701_Y + connect \Y $and$libresoc.v:181638$11766_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172938$11706 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181643$11771 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360042,34 +375039,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:172938$11706_Y + connect \Y $and$libresoc.v:181643$11771_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172935$11703 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181640$11768 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:172935$11703_Y + connect \Y $not$libresoc.v:181640$11768_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172937$11705 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181642$11770 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:172937$11705_Y + connect \Y $not$libresoc.v:181642$11770_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172940$11708 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181645$11773 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:172940$11708_Y + connect \Y $not$libresoc.v:181645$11773_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172934$11702 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181639$11767 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360077,10 +375074,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:172934$11702_Y + connect \Y $or$libresoc.v:181639$11767_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172936$11704 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181641$11769 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360088,10 +375085,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:172936$11704_Y + connect \Y $or$libresoc.v:181641$11769_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172939$11707 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181644$11772 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360099,39 +375096,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:172939$11707_Y + connect \Y $or$libresoc.v:181644$11772_Y end - attribute \src "libresoc.v:172898.7-172898.20" - process $proc$libresoc.v:172898$11713 + attribute \src "libresoc.v:181603.7-181603.20" + process $proc$libresoc.v:181603$11778 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172920.13-172920.25" - process $proc$libresoc.v:172920$11714 + attribute \src "libresoc.v:181625.13-181625.25" + process $proc$libresoc.v:181625$11779 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:172941.3-172942.27" - process $proc$libresoc.v:172941$11709 + attribute \src "libresoc.v:181646.3-181647.27" + process $proc$libresoc.v:181646$11774 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:172943.3-172951.6" - process $proc$libresoc.v:172943$11710 + attribute \src "libresoc.v:181648.3-181656.6" + process $proc$libresoc.v:181648$11775 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11711 $1\q_int$next[2:0]$11712 - attribute \src "libresoc.v:172944.5-172944.29" + assign $0\q_int$next[2:0]$11776 $1\q_int$next[2:0]$11777 + attribute \src "libresoc.v:181649.5-181649.29" switch \initial - attribute \src "libresoc.v:172944.9-172944.17" + attribute \src "libresoc.v:181649.9-181649.17" case 1'1 case end @@ -360140,94 +375137,94 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11712 3'000 + assign $1\q_int$next[2:0]$11777 3'000 case - assign $1\q_int$next[2:0]$11712 \$5 + assign $1\q_int$next[2:0]$11777 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11711 + update \q_int$next $0\q_int$next[2:0]$11776 end - connect \$9 $and$libresoc.v:172933$11701_Y - connect \$11 $or$libresoc.v:172934$11702_Y - connect \$13 $not$libresoc.v:172935$11703_Y - connect \$15 $or$libresoc.v:172936$11704_Y - connect \$1 $not$libresoc.v:172937$11705_Y - connect \$3 $and$libresoc.v:172938$11706_Y - connect \$5 $or$libresoc.v:172939$11707_Y - connect \$7 $not$libresoc.v:172940$11708_Y + connect \$9 $and$libresoc.v:181638$11766_Y + connect \$11 $or$libresoc.v:181639$11767_Y + connect \$13 $not$libresoc.v:181640$11768_Y + connect \$15 $or$libresoc.v:181641$11769_Y + connect \$1 $not$libresoc.v:181642$11770_Y + connect \$3 $and$libresoc.v:181643$11771_Y + connect \$5 $or$libresoc.v:181644$11772_Y + connect \$7 $not$libresoc.v:181645$11773_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:172959.1-173017.10" +attribute \src "libresoc.v:181664.1-181722.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:172960.7-172960.20" + attribute \src "libresoc.v:181665.7-181665.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173005.3-173013.6" - wire width 5 $0\q_int$next[4:0]$11725 - attribute \src "libresoc.v:173003.3-173004.27" + attribute \src "libresoc.v:181710.3-181718.6" + wire width 5 $0\q_int$next[4:0]$11790 + attribute \src "libresoc.v:181708.3-181709.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:173005.3-173013.6" - wire width 5 $1\q_int$next[4:0]$11726 - attribute \src "libresoc.v:172982.13-172982.26" + attribute \src "libresoc.v:181710.3-181718.6" + wire width 5 $1\q_int$next[4:0]$11791 + attribute \src "libresoc.v:181687.13-181687.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:172995.17-172995.96" - wire width 5 $and$libresoc.v:172995$11715_Y - attribute \src "libresoc.v:173000.17-173000.96" - wire width 5 $and$libresoc.v:173000$11720_Y - attribute \src "libresoc.v:172997.18-172997.93" - wire width 5 $not$libresoc.v:172997$11717_Y - attribute \src "libresoc.v:172999.17-172999.92" - wire width 5 $not$libresoc.v:172999$11719_Y - attribute \src "libresoc.v:173002.17-173002.92" - wire width 5 $not$libresoc.v:173002$11722_Y - attribute \src "libresoc.v:172996.18-172996.98" - wire width 5 $or$libresoc.v:172996$11716_Y - attribute \src "libresoc.v:172998.18-172998.99" - wire width 5 $or$libresoc.v:172998$11718_Y - attribute \src "libresoc.v:173001.17-173001.97" - wire width 5 $or$libresoc.v:173001$11721_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181700.17-181700.96" + wire width 5 $and$libresoc.v:181700$11780_Y + attribute \src "libresoc.v:181705.17-181705.96" + wire width 5 $and$libresoc.v:181705$11785_Y + attribute \src "libresoc.v:181702.18-181702.93" + wire width 5 $not$libresoc.v:181702$11782_Y + attribute \src "libresoc.v:181704.17-181704.92" + wire width 5 $not$libresoc.v:181704$11784_Y + attribute \src "libresoc.v:181707.17-181707.92" + wire width 5 $not$libresoc.v:181707$11787_Y + attribute \src "libresoc.v:181701.18-181701.98" + wire width 5 $or$libresoc.v:181701$11781_Y + attribute \src "libresoc.v:181703.18-181703.99" + wire width 5 $or$libresoc.v:181703$11783_Y + attribute \src "libresoc.v:181706.17-181706.97" + wire width 5 $or$libresoc.v:181706$11786_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:172960.7-172960.15" + attribute \src "libresoc.v:181665.7-181665.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172995$11715 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181700$11780 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360235,10 +375232,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172995$11715_Y + connect \Y $and$libresoc.v:181700$11780_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173000$11720 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181705$11785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360246,34 +375243,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:173000$11720_Y + connect \Y $and$libresoc.v:181705$11785_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172997$11717 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181702$11782 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:172997$11717_Y + connect \Y $not$libresoc.v:181702$11782_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172999$11719 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181704$11784 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:172999$11719_Y + connect \Y $not$libresoc.v:181704$11784_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173002$11722 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181707$11787 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:173002$11722_Y + connect \Y $not$libresoc.v:181707$11787_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172996$11716 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181701$11781 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360281,10 +375278,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:172996$11716_Y + connect \Y $or$libresoc.v:181701$11781_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172998$11718 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181703$11783 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360292,10 +375289,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:172998$11718_Y + connect \Y $or$libresoc.v:181703$11783_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173001$11721 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181706$11786 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360303,39 +375300,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:173001$11721_Y + connect \Y $or$libresoc.v:181706$11786_Y end - attribute \src "libresoc.v:172960.7-172960.20" - process $proc$libresoc.v:172960$11727 + attribute \src "libresoc.v:181665.7-181665.20" + process $proc$libresoc.v:181665$11792 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172982.13-172982.26" - process $proc$libresoc.v:172982$11728 + attribute \src "libresoc.v:181687.13-181687.26" + process $proc$libresoc.v:181687$11793 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:173003.3-173004.27" - process $proc$libresoc.v:173003$11723 + attribute \src "libresoc.v:181708.3-181709.27" + process $proc$libresoc.v:181708$11788 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:173005.3-173013.6" - process $proc$libresoc.v:173005$11724 + attribute \src "libresoc.v:181710.3-181718.6" + process $proc$libresoc.v:181710$11789 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11725 $1\q_int$next[4:0]$11726 - attribute \src "libresoc.v:173006.5-173006.29" + assign $0\q_int$next[4:0]$11790 $1\q_int$next[4:0]$11791 + attribute \src "libresoc.v:181711.5-181711.29" switch \initial - attribute \src "libresoc.v:173006.9-173006.17" + attribute \src "libresoc.v:181711.9-181711.17" case 1'1 case end @@ -360344,94 +375341,94 @@ module \req_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11726 5'00000 + assign $1\q_int$next[4:0]$11791 5'00000 case - assign $1\q_int$next[4:0]$11726 \$5 + assign $1\q_int$next[4:0]$11791 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11725 + update \q_int$next $0\q_int$next[4:0]$11790 end - connect \$9 $and$libresoc.v:172995$11715_Y - connect \$11 $or$libresoc.v:172996$11716_Y - connect \$13 $not$libresoc.v:172997$11717_Y - connect \$15 $or$libresoc.v:172998$11718_Y - connect \$1 $not$libresoc.v:172999$11719_Y - connect \$3 $and$libresoc.v:173000$11720_Y - connect \$5 $or$libresoc.v:173001$11721_Y - connect \$7 $not$libresoc.v:173002$11722_Y + connect \$9 $and$libresoc.v:181700$11780_Y + connect \$11 $or$libresoc.v:181701$11781_Y + connect \$13 $not$libresoc.v:181702$11782_Y + connect \$15 $or$libresoc.v:181703$11783_Y + connect \$1 $not$libresoc.v:181704$11784_Y + connect \$3 $and$libresoc.v:181705$11785_Y + connect \$5 $or$libresoc.v:181706$11786_Y + connect \$7 $not$libresoc.v:181707$11787_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:173021.1-173079.10" +attribute \src "libresoc.v:181726.1-181784.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:173022.7-173022.20" + attribute \src "libresoc.v:181727.7-181727.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173067.3-173075.6" - wire width 2 $0\q_int$next[1:0]$11739 - attribute \src "libresoc.v:173065.3-173066.27" + attribute \src "libresoc.v:181772.3-181780.6" + wire width 2 $0\q_int$next[1:0]$11804 + attribute \src "libresoc.v:181770.3-181771.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:173067.3-173075.6" - wire width 2 $1\q_int$next[1:0]$11740 - attribute \src "libresoc.v:173044.13-173044.25" + attribute \src "libresoc.v:181772.3-181780.6" + wire width 2 $1\q_int$next[1:0]$11805 + attribute \src "libresoc.v:181749.13-181749.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:173057.17-173057.96" - wire width 2 $and$libresoc.v:173057$11729_Y - attribute \src "libresoc.v:173062.17-173062.96" - wire width 2 $and$libresoc.v:173062$11734_Y - attribute \src "libresoc.v:173059.18-173059.93" - wire width 2 $not$libresoc.v:173059$11731_Y - attribute \src "libresoc.v:173061.17-173061.92" - wire width 2 $not$libresoc.v:173061$11733_Y - attribute \src "libresoc.v:173064.17-173064.92" - wire width 2 $not$libresoc.v:173064$11736_Y - attribute \src "libresoc.v:173058.18-173058.98" - wire width 2 $or$libresoc.v:173058$11730_Y - attribute \src "libresoc.v:173060.18-173060.99" - wire width 2 $or$libresoc.v:173060$11732_Y - attribute \src "libresoc.v:173063.17-173063.97" - wire width 2 $or$libresoc.v:173063$11735_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181762.17-181762.96" + wire width 2 $and$libresoc.v:181762$11794_Y + attribute \src "libresoc.v:181767.17-181767.96" + wire width 2 $and$libresoc.v:181767$11799_Y + attribute \src "libresoc.v:181764.18-181764.93" + wire width 2 $not$libresoc.v:181764$11796_Y + attribute \src "libresoc.v:181766.17-181766.92" + wire width 2 $not$libresoc.v:181766$11798_Y + attribute \src "libresoc.v:181769.17-181769.92" + wire width 2 $not$libresoc.v:181769$11801_Y + attribute \src "libresoc.v:181763.18-181763.98" + wire width 2 $or$libresoc.v:181763$11795_Y + attribute \src "libresoc.v:181765.18-181765.99" + wire width 2 $or$libresoc.v:181765$11797_Y + attribute \src "libresoc.v:181768.17-181768.97" + wire width 2 $or$libresoc.v:181768$11800_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 2 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 2 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:173022.7-173022.15" + attribute \src "libresoc.v:181727.7-181727.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 2 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 2 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 2 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173057$11729 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181762$11794 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -360439,10 +375436,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:173057$11729_Y + connect \Y $and$libresoc.v:181762$11794_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173062$11734 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181767$11799 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -360450,34 +375447,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:173062$11734_Y + connect \Y $and$libresoc.v:181767$11799_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173059$11731 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181764$11796 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:173059$11731_Y + connect \Y $not$libresoc.v:181764$11796_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173061$11733 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181766$11798 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:173061$11733_Y + connect \Y $not$libresoc.v:181766$11798_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173064$11736 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181769$11801 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:173064$11736_Y + connect \Y $not$libresoc.v:181769$11801_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173058$11730 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181763$11795 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -360485,10 +375482,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:173058$11730_Y + connect \Y $or$libresoc.v:181763$11795_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173060$11732 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181765$11797 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -360496,10 +375493,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:173060$11732_Y + connect \Y $or$libresoc.v:181765$11797_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173063$11735 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181768$11800 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -360507,39 +375504,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:173063$11735_Y + connect \Y $or$libresoc.v:181768$11800_Y end - attribute \src "libresoc.v:173022.7-173022.20" - process $proc$libresoc.v:173022$11741 + attribute \src "libresoc.v:181727.7-181727.20" + process $proc$libresoc.v:181727$11806 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173044.13-173044.25" - process $proc$libresoc.v:173044$11742 + attribute \src "libresoc.v:181749.13-181749.25" + process $proc$libresoc.v:181749$11807 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:173065.3-173066.27" - process $proc$libresoc.v:173065$11737 + attribute \src "libresoc.v:181770.3-181771.27" + process $proc$libresoc.v:181770$11802 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:173067.3-173075.6" - process $proc$libresoc.v:173067$11738 + attribute \src "libresoc.v:181772.3-181780.6" + process $proc$libresoc.v:181772$11803 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11739 $1\q_int$next[1:0]$11740 - attribute \src "libresoc.v:173068.5-173068.29" + assign $0\q_int$next[1:0]$11804 $1\q_int$next[1:0]$11805 + attribute \src "libresoc.v:181773.5-181773.29" switch \initial - attribute \src "libresoc.v:173068.9-173068.17" + attribute \src "libresoc.v:181773.9-181773.17" case 1'1 case end @@ -360548,94 +375545,94 @@ module \req_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$11740 2'00 + assign $1\q_int$next[1:0]$11805 2'00 case - assign $1\q_int$next[1:0]$11740 \$5 + assign $1\q_int$next[1:0]$11805 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$11739 + update \q_int$next $0\q_int$next[1:0]$11804 end - connect \$9 $and$libresoc.v:173057$11729_Y - connect \$11 $or$libresoc.v:173058$11730_Y - connect \$13 $not$libresoc.v:173059$11731_Y - connect \$15 $or$libresoc.v:173060$11732_Y - connect \$1 $not$libresoc.v:173061$11733_Y - connect \$3 $and$libresoc.v:173062$11734_Y - connect \$5 $or$libresoc.v:173063$11735_Y - connect \$7 $not$libresoc.v:173064$11736_Y + connect \$9 $and$libresoc.v:181762$11794_Y + connect \$11 $or$libresoc.v:181763$11795_Y + connect \$13 $not$libresoc.v:181764$11796_Y + connect \$15 $or$libresoc.v:181765$11797_Y + connect \$1 $not$libresoc.v:181766$11798_Y + connect \$3 $and$libresoc.v:181767$11799_Y + connect \$5 $or$libresoc.v:181768$11800_Y + connect \$7 $not$libresoc.v:181769$11801_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:173083.1-173141.10" +attribute \src "libresoc.v:181788.1-181846.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:173084.7-173084.20" + attribute \src "libresoc.v:181789.7-181789.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173129.3-173137.6" - wire width 6 $0\q_int$next[5:0]$11753 - attribute \src "libresoc.v:173127.3-173128.27" + attribute \src "libresoc.v:181834.3-181842.6" + wire width 6 $0\q_int$next[5:0]$11818 + attribute \src "libresoc.v:181832.3-181833.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:173129.3-173137.6" - wire width 6 $1\q_int$next[5:0]$11754 - attribute \src "libresoc.v:173106.13-173106.26" + attribute \src "libresoc.v:181834.3-181842.6" + wire width 6 $1\q_int$next[5:0]$11819 + attribute \src "libresoc.v:181811.13-181811.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:173119.17-173119.96" - wire width 6 $and$libresoc.v:173119$11743_Y - attribute \src "libresoc.v:173124.17-173124.96" - wire width 6 $and$libresoc.v:173124$11748_Y - attribute \src "libresoc.v:173121.18-173121.93" - wire width 6 $not$libresoc.v:173121$11745_Y - attribute \src "libresoc.v:173123.17-173123.92" - wire width 6 $not$libresoc.v:173123$11747_Y - attribute \src "libresoc.v:173126.17-173126.92" - wire width 6 $not$libresoc.v:173126$11750_Y - attribute \src "libresoc.v:173120.18-173120.98" - wire width 6 $or$libresoc.v:173120$11744_Y - attribute \src "libresoc.v:173122.18-173122.99" - wire width 6 $or$libresoc.v:173122$11746_Y - attribute \src "libresoc.v:173125.17-173125.97" - wire width 6 $or$libresoc.v:173125$11749_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181824.17-181824.96" + wire width 6 $and$libresoc.v:181824$11808_Y + attribute \src "libresoc.v:181829.17-181829.96" + wire width 6 $and$libresoc.v:181829$11813_Y + attribute \src "libresoc.v:181826.18-181826.93" + wire width 6 $not$libresoc.v:181826$11810_Y + attribute \src "libresoc.v:181828.17-181828.92" + wire width 6 $not$libresoc.v:181828$11812_Y + attribute \src "libresoc.v:181831.17-181831.92" + wire width 6 $not$libresoc.v:181831$11815_Y + attribute \src "libresoc.v:181825.18-181825.98" + wire width 6 $or$libresoc.v:181825$11809_Y + attribute \src "libresoc.v:181827.18-181827.99" + wire width 6 $or$libresoc.v:181827$11811_Y + attribute \src "libresoc.v:181830.17-181830.97" + wire width 6 $or$libresoc.v:181830$11814_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:173084.7-173084.15" + attribute \src "libresoc.v:181789.7-181789.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 6 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173119$11743 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181824$11808 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360643,10 +375640,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:173119$11743_Y + connect \Y $and$libresoc.v:181824$11808_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173124$11748 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181829$11813 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360654,34 +375651,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:173124$11748_Y + connect \Y $and$libresoc.v:181829$11813_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173121$11745 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181826$11810 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:173121$11745_Y + connect \Y $not$libresoc.v:181826$11810_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173123$11747 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181828$11812 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:173123$11747_Y + connect \Y $not$libresoc.v:181828$11812_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173126$11750 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181831$11815 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:173126$11750_Y + connect \Y $not$libresoc.v:181831$11815_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173120$11744 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181825$11809 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360689,10 +375686,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:173120$11744_Y + connect \Y $or$libresoc.v:181825$11809_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173122$11746 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181827$11811 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360700,10 +375697,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:173122$11746_Y + connect \Y $or$libresoc.v:181827$11811_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173125$11749 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181830$11814 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360711,39 +375708,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:173125$11749_Y + connect \Y $or$libresoc.v:181830$11814_Y end - attribute \src "libresoc.v:173084.7-173084.20" - process $proc$libresoc.v:173084$11755 + attribute \src "libresoc.v:181789.7-181789.20" + process $proc$libresoc.v:181789$11820 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173106.13-173106.26" - process $proc$libresoc.v:173106$11756 + attribute \src "libresoc.v:181811.13-181811.26" + process $proc$libresoc.v:181811$11821 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:173127.3-173128.27" - process $proc$libresoc.v:173127$11751 + attribute \src "libresoc.v:181832.3-181833.27" + process $proc$libresoc.v:181832$11816 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:173129.3-173137.6" - process $proc$libresoc.v:173129$11752 + attribute \src "libresoc.v:181834.3-181842.6" + process $proc$libresoc.v:181834$11817 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$11753 $1\q_int$next[5:0]$11754 - attribute \src "libresoc.v:173130.5-173130.29" + assign $0\q_int$next[5:0]$11818 $1\q_int$next[5:0]$11819 + attribute \src "libresoc.v:181835.5-181835.29" switch \initial - attribute \src "libresoc.v:173130.9-173130.17" + attribute \src "libresoc.v:181835.9-181835.17" case 1'1 case end @@ -360752,94 +375749,94 @@ module \req_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$11754 6'000000 + assign $1\q_int$next[5:0]$11819 6'000000 case - assign $1\q_int$next[5:0]$11754 \$5 + assign $1\q_int$next[5:0]$11819 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$11753 + update \q_int$next $0\q_int$next[5:0]$11818 end - connect \$9 $and$libresoc.v:173119$11743_Y - connect \$11 $or$libresoc.v:173120$11744_Y - connect \$13 $not$libresoc.v:173121$11745_Y - connect \$15 $or$libresoc.v:173122$11746_Y - connect \$1 $not$libresoc.v:173123$11747_Y - connect \$3 $and$libresoc.v:173124$11748_Y - connect \$5 $or$libresoc.v:173125$11749_Y - connect \$7 $not$libresoc.v:173126$11750_Y + connect \$9 $and$libresoc.v:181824$11808_Y + connect \$11 $or$libresoc.v:181825$11809_Y + connect \$13 $not$libresoc.v:181826$11810_Y + connect \$15 $or$libresoc.v:181827$11811_Y + connect \$1 $not$libresoc.v:181828$11812_Y + connect \$3 $and$libresoc.v:181829$11813_Y + connect \$5 $or$libresoc.v:181830$11814_Y + connect \$7 $not$libresoc.v:181831$11815_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:173145.1-173203.10" +attribute \src "libresoc.v:181850.1-181908.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:173146.7-173146.20" + attribute \src "libresoc.v:181851.7-181851.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173191.3-173199.6" - wire width 4 $0\q_int$next[3:0]$11767 - attribute \src "libresoc.v:173189.3-173190.27" + attribute \src "libresoc.v:181896.3-181904.6" + wire width 4 $0\q_int$next[3:0]$11832 + attribute \src "libresoc.v:181894.3-181895.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:173191.3-173199.6" - wire width 4 $1\q_int$next[3:0]$11768 - attribute \src "libresoc.v:173168.13-173168.25" + attribute \src "libresoc.v:181896.3-181904.6" + wire width 4 $1\q_int$next[3:0]$11833 + attribute \src "libresoc.v:181873.13-181873.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:173181.17-173181.96" - wire width 4 $and$libresoc.v:173181$11757_Y - attribute \src "libresoc.v:173186.17-173186.96" - wire width 4 $and$libresoc.v:173186$11762_Y - attribute \src "libresoc.v:173183.18-173183.93" - wire width 4 $not$libresoc.v:173183$11759_Y - attribute \src "libresoc.v:173185.17-173185.92" - wire width 4 $not$libresoc.v:173185$11761_Y - attribute \src "libresoc.v:173188.17-173188.92" - wire width 4 $not$libresoc.v:173188$11764_Y - attribute \src "libresoc.v:173182.18-173182.98" - wire width 4 $or$libresoc.v:173182$11758_Y - attribute \src "libresoc.v:173184.18-173184.99" - wire width 4 $or$libresoc.v:173184$11760_Y - attribute \src "libresoc.v:173187.17-173187.97" - wire width 4 $or$libresoc.v:173187$11763_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181886.17-181886.96" + wire width 4 $and$libresoc.v:181886$11822_Y + attribute \src "libresoc.v:181891.17-181891.96" + wire width 4 $and$libresoc.v:181891$11827_Y + attribute \src "libresoc.v:181888.18-181888.93" + wire width 4 $not$libresoc.v:181888$11824_Y + attribute \src "libresoc.v:181890.17-181890.92" + wire width 4 $not$libresoc.v:181890$11826_Y + attribute \src "libresoc.v:181893.17-181893.92" + wire width 4 $not$libresoc.v:181893$11829_Y + attribute \src "libresoc.v:181887.18-181887.98" + wire width 4 $or$libresoc.v:181887$11823_Y + attribute \src "libresoc.v:181889.18-181889.99" + wire width 4 $or$libresoc.v:181889$11825_Y + attribute \src "libresoc.v:181892.17-181892.97" + wire width 4 $or$libresoc.v:181892$11828_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:173146.7-173146.15" + attribute \src "libresoc.v:181851.7-181851.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173181$11757 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:181886$11822 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360847,10 +375844,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:173181$11757_Y + connect \Y $and$libresoc.v:181886$11822_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173186$11762 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181891$11827 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360858,34 +375855,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:173186$11762_Y + connect \Y $and$libresoc.v:181891$11827_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173183$11759 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181888$11824 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:173183$11759_Y + connect \Y $not$libresoc.v:181888$11824_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173185$11761 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181890$11826 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:173185$11761_Y + connect \Y $not$libresoc.v:181890$11826_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173188$11764 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:181893$11829 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:173188$11764_Y + connect \Y $not$libresoc.v:181893$11829_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173182$11758 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:181887$11823 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360893,10 +375890,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:173182$11758_Y + connect \Y $or$libresoc.v:181887$11823_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173184$11760 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181889$11825 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360904,10 +375901,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:173184$11760_Y + connect \Y $or$libresoc.v:181889$11825_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173187$11763 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181892$11828 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360915,39 +375912,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:173187$11763_Y + connect \Y $or$libresoc.v:181892$11828_Y end - attribute \src "libresoc.v:173146.7-173146.20" - process $proc$libresoc.v:173146$11769 + attribute \src "libresoc.v:181851.7-181851.20" + process $proc$libresoc.v:181851$11834 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173168.13-173168.25" - process $proc$libresoc.v:173168$11770 + attribute \src "libresoc.v:181873.13-181873.25" + process $proc$libresoc.v:181873$11835 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:173189.3-173190.27" - process $proc$libresoc.v:173189$11765 + attribute \src "libresoc.v:181894.3-181895.27" + process $proc$libresoc.v:181894$11830 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:173191.3-173199.6" - process $proc$libresoc.v:173191$11766 + attribute \src "libresoc.v:181896.3-181904.6" + process $proc$libresoc.v:181896$11831 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11767 $1\q_int$next[3:0]$11768 - attribute \src "libresoc.v:173192.5-173192.29" + assign $0\q_int$next[3:0]$11832 $1\q_int$next[3:0]$11833 + attribute \src "libresoc.v:181897.5-181897.29" switch \initial - attribute \src "libresoc.v:173192.9-173192.17" + attribute \src "libresoc.v:181897.9-181897.17" case 1'1 case end @@ -360956,82 +375953,82 @@ module \req_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11768 4'0000 + assign $1\q_int$next[3:0]$11833 4'0000 case - assign $1\q_int$next[3:0]$11768 \$5 + assign $1\q_int$next[3:0]$11833 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11767 + update \q_int$next $0\q_int$next[3:0]$11832 end - connect \$9 $and$libresoc.v:173181$11757_Y - connect \$11 $or$libresoc.v:173182$11758_Y - connect \$13 $not$libresoc.v:173183$11759_Y - connect \$15 $or$libresoc.v:173184$11760_Y - connect \$1 $not$libresoc.v:173185$11761_Y - connect \$3 $and$libresoc.v:173186$11762_Y - connect \$5 $or$libresoc.v:173187$11763_Y - connect \$7 $not$libresoc.v:173188$11764_Y + connect \$9 $and$libresoc.v:181886$11822_Y + connect \$11 $or$libresoc.v:181887$11823_Y + connect \$13 $not$libresoc.v:181888$11824_Y + connect \$15 $or$libresoc.v:181889$11825_Y + connect \$1 $not$libresoc.v:181890$11826_Y + connect \$3 $and$libresoc.v:181891$11827_Y + connect \$5 $or$libresoc.v:181892$11828_Y + connect \$7 $not$libresoc.v:181893$11829_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:173207.1-173256.10" +attribute \src "libresoc.v:181912.1-181961.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:173208.7-173208.20" + attribute \src "libresoc.v:181913.7-181913.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173244.3-173252.6" - wire $0\q_int$next[0:0]$11778 - attribute \src "libresoc.v:173242.3-173243.27" + attribute \src "libresoc.v:181949.3-181957.6" + wire $0\q_int$next[0:0]$11843 + attribute \src "libresoc.v:181947.3-181948.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:173244.3-173252.6" - wire $1\q_int$next[0:0]$11779 - attribute \src "libresoc.v:173224.7-173224.19" + attribute \src "libresoc.v:181949.3-181957.6" + wire $1\q_int$next[0:0]$11844 + attribute \src "libresoc.v:181929.7-181929.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:173239.17-173239.96" - wire $and$libresoc.v:173239$11773_Y - attribute \src "libresoc.v:173238.17-173238.94" - wire $not$libresoc.v:173238$11772_Y - attribute \src "libresoc.v:173241.17-173241.94" - wire $not$libresoc.v:173241$11775_Y - attribute \src "libresoc.v:173237.17-173237.100" - wire $or$libresoc.v:173237$11771_Y - attribute \src "libresoc.v:173240.17-173240.99" - wire $or$libresoc.v:173240$11774_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181944.17-181944.96" + wire $and$libresoc.v:181944$11838_Y + attribute \src "libresoc.v:181943.17-181943.94" + wire $not$libresoc.v:181943$11837_Y + attribute \src "libresoc.v:181946.17-181946.94" + wire $not$libresoc.v:181946$11840_Y + attribute \src "libresoc.v:181942.17-181942.100" + wire $or$libresoc.v:181942$11836_Y + attribute \src "libresoc.v:181945.17-181945.99" + wire $or$libresoc.v:181945$11839_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:173208.7-173208.15" + attribute \src "libresoc.v:181913.7-181913.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173239$11773 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181944$11838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361039,26 +376036,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:173239$11773_Y + connect \Y $and$libresoc.v:181944$11838_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173238$11772 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181943$11837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:173238$11772_Y + connect \Y $not$libresoc.v:181943$11837_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173241$11775 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181946$11840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:173241$11775_Y + connect \Y $not$libresoc.v:181946$11840_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173237$11771 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181942$11836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361066,10 +376063,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:173237$11771_Y + connect \Y $or$libresoc.v:181942$11836_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173240$11774 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181945$11839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361077,39 +376074,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:173240$11774_Y + connect \Y $or$libresoc.v:181945$11839_Y end - attribute \src "libresoc.v:173208.7-173208.20" - process $proc$libresoc.v:173208$11780 + attribute \src "libresoc.v:181913.7-181913.20" + process $proc$libresoc.v:181913$11845 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173224.7-173224.19" - process $proc$libresoc.v:173224$11781 + attribute \src "libresoc.v:181929.7-181929.19" + process $proc$libresoc.v:181929$11846 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:173242.3-173243.27" - process $proc$libresoc.v:173242$11776 + attribute \src "libresoc.v:181947.3-181948.27" + process $proc$libresoc.v:181947$11841 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:173244.3-173252.6" - process $proc$libresoc.v:173244$11777 + attribute \src "libresoc.v:181949.3-181957.6" + process $proc$libresoc.v:181949$11842 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11778 $1\q_int$next[0:0]$11779 - attribute \src "libresoc.v:173245.5-173245.29" + assign $0\q_int$next[0:0]$11843 $1\q_int$next[0:0]$11844 + attribute \src "libresoc.v:181950.5-181950.29" switch \initial - attribute \src "libresoc.v:173245.9-173245.17" + attribute \src "libresoc.v:181950.9-181950.17" case 1'1 case end @@ -361118,79 +376115,79 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11779 1'0 + assign $1\q_int$next[0:0]$11844 1'0 case - assign $1\q_int$next[0:0]$11779 \$5 + assign $1\q_int$next[0:0]$11844 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11778 + update \q_int$next $0\q_int$next[0:0]$11843 end - connect \$9 $or$libresoc.v:173237$11771_Y - connect \$1 $not$libresoc.v:173238$11772_Y - connect \$3 $and$libresoc.v:173239$11773_Y - connect \$5 $or$libresoc.v:173240$11774_Y - connect \$7 $not$libresoc.v:173241$11775_Y + connect \$9 $or$libresoc.v:181942$11836_Y + connect \$1 $not$libresoc.v:181943$11837_Y + connect \$3 $and$libresoc.v:181944$11838_Y + connect \$5 $or$libresoc.v:181945$11839_Y + connect \$7 $not$libresoc.v:181946$11840_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:173260.1-173309.10" +attribute \src "libresoc.v:181965.1-182014.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:173261.7-173261.20" + attribute \src "libresoc.v:181966.7-181966.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173297.3-173305.6" - wire $0\q_int$next[0:0]$11789 - attribute \src "libresoc.v:173295.3-173296.27" + attribute \src "libresoc.v:182002.3-182010.6" + wire $0\q_int$next[0:0]$11854 + attribute \src "libresoc.v:182000.3-182001.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:173297.3-173305.6" - wire $1\q_int$next[0:0]$11790 - attribute \src "libresoc.v:173277.7-173277.19" + attribute \src "libresoc.v:182002.3-182010.6" + wire $1\q_int$next[0:0]$11855 + attribute \src "libresoc.v:181982.7-181982.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:173292.17-173292.96" - wire $and$libresoc.v:173292$11784_Y - attribute \src "libresoc.v:173291.17-173291.94" - wire $not$libresoc.v:173291$11783_Y - attribute \src "libresoc.v:173294.17-173294.94" - wire $not$libresoc.v:173294$11786_Y - attribute \src "libresoc.v:173290.17-173290.100" - wire $or$libresoc.v:173290$11782_Y - attribute \src "libresoc.v:173293.17-173293.99" - wire $or$libresoc.v:173293$11785_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:181997.17-181997.96" + wire $and$libresoc.v:181997$11849_Y + attribute \src "libresoc.v:181996.17-181996.94" + wire $not$libresoc.v:181996$11848_Y + attribute \src "libresoc.v:181999.17-181999.94" + wire $not$libresoc.v:181999$11851_Y + attribute \src "libresoc.v:181995.17-181995.100" + wire $or$libresoc.v:181995$11847_Y + attribute \src "libresoc.v:181998.17-181998.99" + wire $or$libresoc.v:181998$11850_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:173261.7-173261.15" + attribute \src "libresoc.v:181966.7-181966.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173292$11784 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:181997$11849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361198,26 +376195,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:173292$11784_Y + connect \Y $and$libresoc.v:181997$11849_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173291$11783 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:181996$11848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:173291$11783_Y + connect \Y $not$libresoc.v:181996$11848_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173294$11786 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:181999$11851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:173294$11786_Y + connect \Y $not$libresoc.v:181999$11851_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173290$11782 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:181995$11847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361225,10 +376222,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:173290$11782_Y + connect \Y $or$libresoc.v:181995$11847_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173293$11785 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:181998$11850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361236,39 +376233,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:173293$11785_Y + connect \Y $or$libresoc.v:181998$11850_Y end - attribute \src "libresoc.v:173261.7-173261.20" - process $proc$libresoc.v:173261$11791 + attribute \src "libresoc.v:181966.7-181966.20" + process $proc$libresoc.v:181966$11856 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173277.7-173277.19" - process $proc$libresoc.v:173277$11792 + attribute \src "libresoc.v:181982.7-181982.19" + process $proc$libresoc.v:181982$11857 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:173295.3-173296.27" - process $proc$libresoc.v:173295$11787 + attribute \src "libresoc.v:182000.3-182001.27" + process $proc$libresoc.v:182000$11852 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:173297.3-173305.6" - process $proc$libresoc.v:173297$11788 + attribute \src "libresoc.v:182002.3-182010.6" + process $proc$libresoc.v:182002$11853 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11789 $1\q_int$next[0:0]$11790 - attribute \src "libresoc.v:173298.5-173298.29" + assign $0\q_int$next[0:0]$11854 $1\q_int$next[0:0]$11855 + attribute \src "libresoc.v:182003.5-182003.29" switch \initial - attribute \src "libresoc.v:173298.9-173298.17" + attribute \src "libresoc.v:182003.9-182003.17" case 1'1 case end @@ -361277,423 +376274,423 @@ module \reset_l$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11790 1'0 + assign $1\q_int$next[0:0]$11855 1'0 case - assign $1\q_int$next[0:0]$11790 \$5 + assign $1\q_int$next[0:0]$11855 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11789 + update \q_int$next $0\q_int$next[0:0]$11854 end - connect \$9 $or$libresoc.v:173290$11782_Y - connect \$1 $not$libresoc.v:173291$11783_Y - connect \$3 $and$libresoc.v:173292$11784_Y - connect \$5 $or$libresoc.v:173293$11785_Y - connect \$7 $not$libresoc.v:173294$11786_Y + connect \$9 $or$libresoc.v:181995$11847_Y + connect \$1 $not$libresoc.v:181996$11848_Y + connect \$3 $and$libresoc.v:181997$11849_Y + connect \$5 $or$libresoc.v:181998$11850_Y + connect \$7 $not$libresoc.v:181999$11851_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:173313.1-173900.10" +attribute \src "libresoc.v:182018.1-182605.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:173314.7-173314.20" + attribute \src "libresoc.v:182019.7-182019.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $10\mask[9:9] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $11\mask[10:10] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $12\mask[11:11] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $13\mask[12:12] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $14\mask[13:13] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $15\mask[14:14] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $16\mask[15:15] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $17\mask[16:16] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $18\mask[17:17] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $19\mask[18:18] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $1\mask[0:0] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $20\mask[19:19] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $21\mask[20:20] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $22\mask[21:21] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $23\mask[22:22] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $24\mask[23:23] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $25\mask[24:24] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $26\mask[25:25] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $27\mask[26:26] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $28\mask[27:27] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $29\mask[28:28] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $2\mask[1:1] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $30\mask[29:29] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $31\mask[30:30] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $32\mask[31:31] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $33\mask[32:32] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $34\mask[33:33] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $35\mask[34:34] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $36\mask[35:35] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $37\mask[36:36] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $38\mask[37:37] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $39\mask[38:38] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $3\mask[2:2] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $40\mask[39:39] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $41\mask[40:40] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $42\mask[41:41] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $43\mask[42:42] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $44\mask[43:43] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $45\mask[44:44] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $46\mask[45:45] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $47\mask[46:46] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $48\mask[47:47] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $49\mask[48:48] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $4\mask[3:3] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $50\mask[49:49] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $51\mask[50:50] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $52\mask[51:51] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $53\mask[52:52] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $54\mask[53:53] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $55\mask[54:54] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $56\mask[55:55] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $57\mask[56:56] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $58\mask[57:57] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $59\mask[58:58] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $5\mask[4:4] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $60\mask[59:59] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $61\mask[60:60] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $62\mask[61:61] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $63\mask[62:62] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $64\mask[63:63] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $6\mask[5:5] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $7\mask[6:6] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $8\mask[7:7] - attribute \src "libresoc.v:173512.3-173899.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $9\mask[8:8] - attribute \src "libresoc.v:173448.17-173448.96" - wire $gt$libresoc.v:173448$11793_Y - attribute \src "libresoc.v:173449.18-173449.98" - wire $gt$libresoc.v:173449$11794_Y - attribute \src "libresoc.v:173450.19-173450.99" - wire $gt$libresoc.v:173450$11795_Y - attribute \src "libresoc.v:173451.19-173451.99" - wire $gt$libresoc.v:173451$11796_Y - attribute \src "libresoc.v:173452.19-173452.99" - wire $gt$libresoc.v:173452$11797_Y - attribute \src "libresoc.v:173453.19-173453.99" - wire $gt$libresoc.v:173453$11798_Y - attribute \src "libresoc.v:173454.19-173454.99" - wire $gt$libresoc.v:173454$11799_Y - attribute \src "libresoc.v:173455.19-173455.99" - wire $gt$libresoc.v:173455$11800_Y - attribute \src "libresoc.v:173456.19-173456.99" - wire $gt$libresoc.v:173456$11801_Y - attribute \src "libresoc.v:173457.19-173457.99" - wire $gt$libresoc.v:173457$11802_Y - attribute \src "libresoc.v:173458.19-173458.99" - wire $gt$libresoc.v:173458$11803_Y - attribute \src "libresoc.v:173459.18-173459.97" - wire $gt$libresoc.v:173459$11804_Y - attribute \src "libresoc.v:173460.19-173460.99" - wire $gt$libresoc.v:173460$11805_Y - attribute \src "libresoc.v:173461.19-173461.99" - wire $gt$libresoc.v:173461$11806_Y - attribute \src "libresoc.v:173462.19-173462.99" - wire $gt$libresoc.v:173462$11807_Y - attribute \src "libresoc.v:173463.19-173463.99" - wire $gt$libresoc.v:173463$11808_Y - attribute \src "libresoc.v:173464.19-173464.99" - wire $gt$libresoc.v:173464$11809_Y - attribute \src "libresoc.v:173465.18-173465.97" - wire $gt$libresoc.v:173465$11810_Y - attribute \src "libresoc.v:173466.18-173466.97" - wire $gt$libresoc.v:173466$11811_Y - attribute \src "libresoc.v:173467.18-173467.97" - wire $gt$libresoc.v:173467$11812_Y - attribute \src "libresoc.v:173468.17-173468.96" - wire $gt$libresoc.v:173468$11813_Y - attribute \src "libresoc.v:173469.18-173469.97" - wire $gt$libresoc.v:173469$11814_Y - attribute \src "libresoc.v:173470.18-173470.97" - wire $gt$libresoc.v:173470$11815_Y - attribute \src "libresoc.v:173471.18-173471.97" - wire $gt$libresoc.v:173471$11816_Y - attribute \src "libresoc.v:173472.18-173472.97" - wire $gt$libresoc.v:173472$11817_Y - attribute \src "libresoc.v:173473.18-173473.97" - wire $gt$libresoc.v:173473$11818_Y - attribute \src "libresoc.v:173474.18-173474.97" - wire $gt$libresoc.v:173474$11819_Y - attribute \src "libresoc.v:173475.18-173475.97" - wire $gt$libresoc.v:173475$11820_Y - attribute \src "libresoc.v:173476.18-173476.98" - wire $gt$libresoc.v:173476$11821_Y - attribute \src "libresoc.v:173477.18-173477.98" - wire $gt$libresoc.v:173477$11822_Y - attribute \src "libresoc.v:173478.18-173478.98" - wire $gt$libresoc.v:173478$11823_Y - attribute \src "libresoc.v:173479.17-173479.96" - wire $gt$libresoc.v:173479$11824_Y - attribute \src "libresoc.v:173480.18-173480.98" - wire $gt$libresoc.v:173480$11825_Y - attribute \src "libresoc.v:173481.18-173481.98" - wire $gt$libresoc.v:173481$11826_Y - attribute \src "libresoc.v:173482.18-173482.98" - wire $gt$libresoc.v:173482$11827_Y - attribute \src "libresoc.v:173483.18-173483.98" - wire $gt$libresoc.v:173483$11828_Y - attribute \src "libresoc.v:173484.18-173484.98" - wire $gt$libresoc.v:173484$11829_Y - attribute \src "libresoc.v:173485.18-173485.98" - wire $gt$libresoc.v:173485$11830_Y - attribute \src "libresoc.v:173486.18-173486.98" - wire $gt$libresoc.v:173486$11831_Y - attribute \src "libresoc.v:173487.18-173487.98" - wire $gt$libresoc.v:173487$11832_Y - attribute \src "libresoc.v:173488.18-173488.98" - wire $gt$libresoc.v:173488$11833_Y - attribute \src "libresoc.v:173489.18-173489.98" - wire $gt$libresoc.v:173489$11834_Y - attribute \src "libresoc.v:173490.17-173490.96" - wire $gt$libresoc.v:173490$11835_Y - attribute \src "libresoc.v:173491.18-173491.98" - wire $gt$libresoc.v:173491$11836_Y - attribute \src "libresoc.v:173492.18-173492.98" - wire $gt$libresoc.v:173492$11837_Y - attribute \src "libresoc.v:173493.18-173493.98" - wire $gt$libresoc.v:173493$11838_Y - attribute \src "libresoc.v:173494.18-173494.98" - wire $gt$libresoc.v:173494$11839_Y - attribute \src "libresoc.v:173495.18-173495.98" - wire $gt$libresoc.v:173495$11840_Y - attribute \src "libresoc.v:173496.18-173496.98" - wire $gt$libresoc.v:173496$11841_Y - attribute \src "libresoc.v:173497.18-173497.98" - wire $gt$libresoc.v:173497$11842_Y - attribute \src "libresoc.v:173498.18-173498.98" - wire $gt$libresoc.v:173498$11843_Y - attribute \src "libresoc.v:173499.18-173499.98" - wire $gt$libresoc.v:173499$11844_Y - attribute \src "libresoc.v:173500.18-173500.98" - wire $gt$libresoc.v:173500$11845_Y - attribute \src "libresoc.v:173501.17-173501.96" - wire $gt$libresoc.v:173501$11846_Y - attribute \src "libresoc.v:173502.18-173502.98" - wire $gt$libresoc.v:173502$11847_Y - attribute \src "libresoc.v:173503.18-173503.98" - wire $gt$libresoc.v:173503$11848_Y - attribute \src "libresoc.v:173504.18-173504.98" - wire $gt$libresoc.v:173504$11849_Y - attribute \src "libresoc.v:173505.18-173505.98" - wire $gt$libresoc.v:173505$11850_Y - attribute \src "libresoc.v:173506.18-173506.98" - wire $gt$libresoc.v:173506$11851_Y - attribute \src "libresoc.v:173507.18-173507.98" - wire $gt$libresoc.v:173507$11852_Y - attribute \src "libresoc.v:173508.18-173508.98" - wire $gt$libresoc.v:173508$11853_Y - attribute \src "libresoc.v:173509.18-173509.98" - wire $gt$libresoc.v:173509$11854_Y - attribute \src "libresoc.v:173510.18-173510.98" - wire $gt$libresoc.v:173510$11855_Y - attribute \src "libresoc.v:173511.18-173511.98" - wire $gt$libresoc.v:173511$11856_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "libresoc.v:182153.17-182153.96" + wire $gt$libresoc.v:182153$11858_Y + attribute \src "libresoc.v:182154.18-182154.98" + wire $gt$libresoc.v:182154$11859_Y + attribute \src "libresoc.v:182155.19-182155.99" + wire $gt$libresoc.v:182155$11860_Y + attribute \src "libresoc.v:182156.19-182156.99" + wire $gt$libresoc.v:182156$11861_Y + attribute \src "libresoc.v:182157.19-182157.99" + wire $gt$libresoc.v:182157$11862_Y + attribute \src "libresoc.v:182158.19-182158.99" + wire $gt$libresoc.v:182158$11863_Y + attribute \src "libresoc.v:182159.19-182159.99" + wire $gt$libresoc.v:182159$11864_Y + attribute \src "libresoc.v:182160.19-182160.99" + wire $gt$libresoc.v:182160$11865_Y + attribute \src "libresoc.v:182161.19-182161.99" + wire $gt$libresoc.v:182161$11866_Y + attribute \src "libresoc.v:182162.19-182162.99" + wire $gt$libresoc.v:182162$11867_Y + attribute \src "libresoc.v:182163.19-182163.99" + wire $gt$libresoc.v:182163$11868_Y + attribute \src "libresoc.v:182164.18-182164.97" + wire $gt$libresoc.v:182164$11869_Y + attribute \src "libresoc.v:182165.19-182165.99" + wire $gt$libresoc.v:182165$11870_Y + attribute \src "libresoc.v:182166.19-182166.99" + wire $gt$libresoc.v:182166$11871_Y + attribute \src "libresoc.v:182167.19-182167.99" + wire $gt$libresoc.v:182167$11872_Y + attribute \src "libresoc.v:182168.19-182168.99" + wire $gt$libresoc.v:182168$11873_Y + attribute \src "libresoc.v:182169.19-182169.99" + wire $gt$libresoc.v:182169$11874_Y + attribute \src "libresoc.v:182170.18-182170.97" + wire $gt$libresoc.v:182170$11875_Y + attribute \src "libresoc.v:182171.18-182171.97" + wire $gt$libresoc.v:182171$11876_Y + attribute \src "libresoc.v:182172.18-182172.97" + wire $gt$libresoc.v:182172$11877_Y + attribute \src "libresoc.v:182173.17-182173.96" + wire $gt$libresoc.v:182173$11878_Y + attribute \src "libresoc.v:182174.18-182174.97" + wire $gt$libresoc.v:182174$11879_Y + attribute \src "libresoc.v:182175.18-182175.97" + wire $gt$libresoc.v:182175$11880_Y + attribute \src "libresoc.v:182176.18-182176.97" + wire $gt$libresoc.v:182176$11881_Y + attribute \src "libresoc.v:182177.18-182177.97" + wire $gt$libresoc.v:182177$11882_Y + attribute \src "libresoc.v:182178.18-182178.97" + wire $gt$libresoc.v:182178$11883_Y + attribute \src "libresoc.v:182179.18-182179.97" + wire $gt$libresoc.v:182179$11884_Y + attribute \src "libresoc.v:182180.18-182180.97" + wire $gt$libresoc.v:182180$11885_Y + attribute \src "libresoc.v:182181.18-182181.98" + wire $gt$libresoc.v:182181$11886_Y + attribute \src "libresoc.v:182182.18-182182.98" + wire $gt$libresoc.v:182182$11887_Y + attribute \src "libresoc.v:182183.18-182183.98" + wire $gt$libresoc.v:182183$11888_Y + attribute \src "libresoc.v:182184.17-182184.96" + wire $gt$libresoc.v:182184$11889_Y + attribute \src "libresoc.v:182185.18-182185.98" + wire $gt$libresoc.v:182185$11890_Y + attribute \src "libresoc.v:182186.18-182186.98" + wire $gt$libresoc.v:182186$11891_Y + attribute \src "libresoc.v:182187.18-182187.98" + wire $gt$libresoc.v:182187$11892_Y + attribute \src "libresoc.v:182188.18-182188.98" + wire $gt$libresoc.v:182188$11893_Y + attribute \src "libresoc.v:182189.18-182189.98" + wire $gt$libresoc.v:182189$11894_Y + attribute \src "libresoc.v:182190.18-182190.98" + wire $gt$libresoc.v:182190$11895_Y + attribute \src "libresoc.v:182191.18-182191.98" + wire $gt$libresoc.v:182191$11896_Y + attribute \src "libresoc.v:182192.18-182192.98" + wire $gt$libresoc.v:182192$11897_Y + attribute \src "libresoc.v:182193.18-182193.98" + wire $gt$libresoc.v:182193$11898_Y + attribute \src "libresoc.v:182194.18-182194.98" + wire $gt$libresoc.v:182194$11899_Y + attribute \src "libresoc.v:182195.17-182195.96" + wire $gt$libresoc.v:182195$11900_Y + attribute \src "libresoc.v:182196.18-182196.98" + wire $gt$libresoc.v:182196$11901_Y + attribute \src "libresoc.v:182197.18-182197.98" + wire $gt$libresoc.v:182197$11902_Y + attribute \src "libresoc.v:182198.18-182198.98" + wire $gt$libresoc.v:182198$11903_Y + attribute \src "libresoc.v:182199.18-182199.98" + wire $gt$libresoc.v:182199$11904_Y + attribute \src "libresoc.v:182200.18-182200.98" + wire $gt$libresoc.v:182200$11905_Y + attribute \src "libresoc.v:182201.18-182201.98" + wire $gt$libresoc.v:182201$11906_Y + attribute \src "libresoc.v:182202.18-182202.98" + wire $gt$libresoc.v:182202$11907_Y + attribute \src "libresoc.v:182203.18-182203.98" + wire $gt$libresoc.v:182203$11908_Y + attribute \src "libresoc.v:182204.18-182204.98" + wire $gt$libresoc.v:182204$11909_Y + attribute \src "libresoc.v:182205.18-182205.98" + wire $gt$libresoc.v:182205$11910_Y + attribute \src "libresoc.v:182206.17-182206.96" + wire $gt$libresoc.v:182206$11911_Y + attribute \src "libresoc.v:182207.18-182207.98" + wire $gt$libresoc.v:182207$11912_Y + attribute \src "libresoc.v:182208.18-182208.98" + wire $gt$libresoc.v:182208$11913_Y + attribute \src "libresoc.v:182209.18-182209.98" + wire $gt$libresoc.v:182209$11914_Y + attribute \src "libresoc.v:182210.18-182210.98" + wire $gt$libresoc.v:182210$11915_Y + attribute \src "libresoc.v:182211.18-182211.98" + wire $gt$libresoc.v:182211$11916_Y + attribute \src "libresoc.v:182212.18-182212.98" + wire $gt$libresoc.v:182212$11917_Y + attribute \src "libresoc.v:182213.18-182213.98" + wire $gt$libresoc.v:182213$11918_Y + attribute \src "libresoc.v:182214.18-182214.98" + wire $gt$libresoc.v:182214$11919_Y + attribute \src "libresoc.v:182215.18-182215.98" + wire $gt$libresoc.v:182215$11920_Y + attribute \src "libresoc.v:182216.18-182216.98" + wire $gt$libresoc.v:182216$11921_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:173314.7-173314.15" + attribute \src "libresoc.v:182019.7-182019.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173448$11793 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182153$11858 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361701,10 +376698,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:173448$11793_Y + connect \Y $gt$libresoc.v:182153$11858_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173449$11794 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182154$11859 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361712,10 +376709,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:173449$11794_Y + connect \Y $gt$libresoc.v:182154$11859_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173450$11795 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182155$11860 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361723,10 +376720,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:173450$11795_Y + connect \Y $gt$libresoc.v:182155$11860_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173451$11796 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182156$11861 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361734,10 +376731,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:173451$11796_Y + connect \Y $gt$libresoc.v:182156$11861_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173452$11797 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182157$11862 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361745,10 +376742,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:173452$11797_Y + connect \Y $gt$libresoc.v:182157$11862_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173453$11798 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182158$11863 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361756,10 +376753,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:173453$11798_Y + connect \Y $gt$libresoc.v:182158$11863_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173454$11799 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182159$11864 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361767,10 +376764,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:173454$11799_Y + connect \Y $gt$libresoc.v:182159$11864_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173455$11800 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182160$11865 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361778,10 +376775,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:173455$11800_Y + connect \Y $gt$libresoc.v:182160$11865_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173456$11801 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182161$11866 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361789,10 +376786,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:173456$11801_Y + connect \Y $gt$libresoc.v:182161$11866_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173457$11802 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182162$11867 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361800,10 +376797,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:173457$11802_Y + connect \Y $gt$libresoc.v:182162$11867_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173458$11803 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182163$11868 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361811,10 +376808,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:173458$11803_Y + connect \Y $gt$libresoc.v:182163$11868_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173459$11804 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182164$11869 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361822,10 +376819,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:173459$11804_Y + connect \Y $gt$libresoc.v:182164$11869_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173460$11805 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182165$11870 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361833,10 +376830,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:173460$11805_Y + connect \Y $gt$libresoc.v:182165$11870_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173461$11806 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182166$11871 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361844,10 +376841,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:173461$11806_Y + connect \Y $gt$libresoc.v:182166$11871_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173462$11807 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182167$11872 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361855,10 +376852,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:173462$11807_Y + connect \Y $gt$libresoc.v:182167$11872_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173463$11808 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182168$11873 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361866,10 +376863,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:173463$11808_Y + connect \Y $gt$libresoc.v:182168$11873_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173464$11809 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182169$11874 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361877,10 +376874,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:173464$11809_Y + connect \Y $gt$libresoc.v:182169$11874_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173465$11810 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182170$11875 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361888,10 +376885,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:173465$11810_Y + connect \Y $gt$libresoc.v:182170$11875_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173466$11811 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182171$11876 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361899,10 +376896,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:173466$11811_Y + connect \Y $gt$libresoc.v:182171$11876_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173467$11812 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182172$11877 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361910,10 +376907,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:173467$11812_Y + connect \Y $gt$libresoc.v:182172$11877_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173468$11813 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182173$11878 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361921,10 +376918,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:173468$11813_Y + connect \Y $gt$libresoc.v:182173$11878_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173469$11814 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182174$11879 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361932,10 +376929,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:173469$11814_Y + connect \Y $gt$libresoc.v:182174$11879_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173470$11815 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182175$11880 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361943,10 +376940,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:173470$11815_Y + connect \Y $gt$libresoc.v:182175$11880_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173471$11816 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182176$11881 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361954,10 +376951,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:173471$11816_Y + connect \Y $gt$libresoc.v:182176$11881_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173472$11817 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182177$11882 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361965,10 +376962,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:173472$11817_Y + connect \Y $gt$libresoc.v:182177$11882_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173473$11818 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182178$11883 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361976,10 +376973,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:173473$11818_Y + connect \Y $gt$libresoc.v:182178$11883_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173474$11819 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182179$11884 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361987,10 +376984,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:173474$11819_Y + connect \Y $gt$libresoc.v:182179$11884_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173475$11820 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182180$11885 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -361998,10 +376995,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:173475$11820_Y + connect \Y $gt$libresoc.v:182180$11885_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173476$11821 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182181$11886 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362009,10 +377006,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:173476$11821_Y + connect \Y $gt$libresoc.v:182181$11886_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173477$11822 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182182$11887 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362020,10 +377017,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:173477$11822_Y + connect \Y $gt$libresoc.v:182182$11887_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173478$11823 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182183$11888 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362031,10 +377028,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:173478$11823_Y + connect \Y $gt$libresoc.v:182183$11888_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173479$11824 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182184$11889 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362042,10 +377039,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:173479$11824_Y + connect \Y $gt$libresoc.v:182184$11889_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173480$11825 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182185$11890 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362053,10 +377050,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:173480$11825_Y + connect \Y $gt$libresoc.v:182185$11890_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173481$11826 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182186$11891 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362064,10 +377061,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:173481$11826_Y + connect \Y $gt$libresoc.v:182186$11891_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173482$11827 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182187$11892 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362075,10 +377072,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:173482$11827_Y + connect \Y $gt$libresoc.v:182187$11892_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173483$11828 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182188$11893 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362086,10 +377083,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:173483$11828_Y + connect \Y $gt$libresoc.v:182188$11893_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173484$11829 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182189$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362097,10 +377094,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:173484$11829_Y + connect \Y $gt$libresoc.v:182189$11894_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173485$11830 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182190$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362108,10 +377105,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:173485$11830_Y + connect \Y $gt$libresoc.v:182190$11895_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173486$11831 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182191$11896 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362119,10 +377116,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:173486$11831_Y + connect \Y $gt$libresoc.v:182191$11896_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173487$11832 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182192$11897 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362130,10 +377127,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:173487$11832_Y + connect \Y $gt$libresoc.v:182192$11897_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173488$11833 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182193$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362141,10 +377138,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:173488$11833_Y + connect \Y $gt$libresoc.v:182193$11898_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173489$11834 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182194$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362152,10 +377149,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:173489$11834_Y + connect \Y $gt$libresoc.v:182194$11899_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173490$11835 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182195$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362163,10 +377160,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:173490$11835_Y + connect \Y $gt$libresoc.v:182195$11900_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173491$11836 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182196$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362174,10 +377171,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:173491$11836_Y + connect \Y $gt$libresoc.v:182196$11901_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173492$11837 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182197$11902 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362185,10 +377182,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:173492$11837_Y + connect \Y $gt$libresoc.v:182197$11902_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173493$11838 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182198$11903 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362196,10 +377193,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:173493$11838_Y + connect \Y $gt$libresoc.v:182198$11903_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173494$11839 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182199$11904 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362207,10 +377204,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:173494$11839_Y + connect \Y $gt$libresoc.v:182199$11904_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173495$11840 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182200$11905 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362218,10 +377215,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:173495$11840_Y + connect \Y $gt$libresoc.v:182200$11905_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173496$11841 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182201$11906 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362229,10 +377226,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:173496$11841_Y + connect \Y $gt$libresoc.v:182201$11906_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173497$11842 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182202$11907 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362240,10 +377237,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:173497$11842_Y + connect \Y $gt$libresoc.v:182202$11907_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173498$11843 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182203$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362251,10 +377248,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:173498$11843_Y + connect \Y $gt$libresoc.v:182203$11908_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173499$11844 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182204$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362262,10 +377259,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:173499$11844_Y + connect \Y $gt$libresoc.v:182204$11909_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173500$11845 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182205$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362273,10 +377270,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:173500$11845_Y + connect \Y $gt$libresoc.v:182205$11910_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173501$11846 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182206$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362284,10 +377281,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:173501$11846_Y + connect \Y $gt$libresoc.v:182206$11911_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173502$11847 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182207$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362295,10 +377292,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:173502$11847_Y + connect \Y $gt$libresoc.v:182207$11912_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173503$11848 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182208$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362306,10 +377303,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:173503$11848_Y + connect \Y $gt$libresoc.v:182208$11913_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173504$11849 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182209$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362317,10 +377314,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:173504$11849_Y + connect \Y $gt$libresoc.v:182209$11914_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173505$11850 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182210$11915 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362328,10 +377325,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:173505$11850_Y + connect \Y $gt$libresoc.v:182210$11915_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173506$11851 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182211$11916 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362339,10 +377336,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:173506$11851_Y + connect \Y $gt$libresoc.v:182211$11916_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173507$11852 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182212$11917 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362350,10 +377347,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:173507$11852_Y + connect \Y $gt$libresoc.v:182212$11917_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173508$11853 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182213$11918 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362361,10 +377358,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:173508$11853_Y + connect \Y $gt$libresoc.v:182213$11918_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173509$11854 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182214$11919 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362372,10 +377369,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:173509$11854_Y + connect \Y $gt$libresoc.v:182214$11919_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173510$11855 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182215$11920 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362383,10 +377380,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:173510$11855_Y + connect \Y $gt$libresoc.v:182215$11920_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173511$11856 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:182216$11921 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -362394,18 +377391,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:173511$11856_Y + connect \Y $gt$libresoc.v:182216$11921_Y end - attribute \src "libresoc.v:173314.7-173314.20" - process $proc$libresoc.v:173314$11858 + attribute \src "libresoc.v:182019.7-182019.20" + process $proc$libresoc.v:182019$11923 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173512.3-173899.6" - process $proc$libresoc.v:173512$11857 + attribute \src "libresoc.v:182217.3-182604.6" + process $proc$libresoc.v:182217$11922 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -362472,13 +377469,13 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:173513.5-173513.29" + attribute \src "libresoc.v:182218.5-182218.29" switch \initial - attribute \src "libresoc.v:173513.9-173513.17" + attribute \src "libresoc.v:182218.9-182218.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362487,7 +377484,7 @@ module \right_mask case assign $1\mask[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362496,7 +377493,7 @@ module \right_mask case assign $2\mask[1:1] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362505,7 +377502,7 @@ module \right_mask case assign $3\mask[2:2] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362514,7 +377511,7 @@ module \right_mask case assign $4\mask[3:3] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362523,7 +377520,7 @@ module \right_mask case assign $5\mask[4:4] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362532,7 +377529,7 @@ module \right_mask case assign $6\mask[5:5] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362541,7 +377538,7 @@ module \right_mask case assign $7\mask[6:6] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362550,7 +377547,7 @@ module \right_mask case assign $8\mask[7:7] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362559,7 +377556,7 @@ module \right_mask case assign $9\mask[8:8] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362568,7 +377565,7 @@ module \right_mask case assign $10\mask[9:9] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362577,7 +377574,7 @@ module \right_mask case assign $11\mask[10:10] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362586,7 +377583,7 @@ module \right_mask case assign $12\mask[11:11] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362595,7 +377592,7 @@ module \right_mask case assign $13\mask[12:12] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362604,7 +377601,7 @@ module \right_mask case assign $14\mask[13:13] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362613,7 +377610,7 @@ module \right_mask case assign $15\mask[14:14] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362622,7 +377619,7 @@ module \right_mask case assign $16\mask[15:15] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362631,7 +377628,7 @@ module \right_mask case assign $17\mask[16:16] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$35 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362640,7 +377637,7 @@ module \right_mask case assign $18\mask[17:17] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362649,7 +377646,7 @@ module \right_mask case assign $19\mask[18:18] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362658,7 +377655,7 @@ module \right_mask case assign $20\mask[19:19] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362667,7 +377664,7 @@ module \right_mask case assign $21\mask[20:20] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362676,7 +377673,7 @@ module \right_mask case assign $22\mask[21:21] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362685,7 +377682,7 @@ module \right_mask case assign $23\mask[22:22] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$47 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362694,7 +377691,7 @@ module \right_mask case assign $24\mask[23:23] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362703,7 +377700,7 @@ module \right_mask case assign $25\mask[24:24] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$51 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362712,7 +377709,7 @@ module \right_mask case assign $26\mask[25:25] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$53 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362721,7 +377718,7 @@ module \right_mask case assign $27\mask[26:26] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362730,7 +377727,7 @@ module \right_mask case assign $28\mask[27:27] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362739,7 +377736,7 @@ module \right_mask case assign $29\mask[28:28] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362748,7 +377745,7 @@ module \right_mask case assign $30\mask[29:29] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362757,7 +377754,7 @@ module \right_mask case assign $31\mask[30:30] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362766,7 +377763,7 @@ module \right_mask case assign $32\mask[31:31] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$65 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362775,7 +377772,7 @@ module \right_mask case assign $33\mask[32:32] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362784,7 +377781,7 @@ module \right_mask case assign $34\mask[33:33] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362793,7 +377790,7 @@ module \right_mask case assign $35\mask[34:34] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362802,7 +377799,7 @@ module \right_mask case assign $36\mask[35:35] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362811,7 +377808,7 @@ module \right_mask case assign $37\mask[36:36] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$75 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362820,7 +377817,7 @@ module \right_mask case assign $38\mask[37:37] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362829,7 +377826,7 @@ module \right_mask case assign $39\mask[38:38] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$79 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362838,7 +377835,7 @@ module \right_mask case assign $40\mask[39:39] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362847,7 +377844,7 @@ module \right_mask case assign $41\mask[40:40] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362856,7 +377853,7 @@ module \right_mask case assign $42\mask[41:41] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362865,7 +377862,7 @@ module \right_mask case assign $43\mask[42:42] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362874,7 +377871,7 @@ module \right_mask case assign $44\mask[43:43] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$89 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362883,7 +377880,7 @@ module \right_mask case assign $45\mask[44:44] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$91 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362892,7 +377889,7 @@ module \right_mask case assign $46\mask[45:45] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362901,7 +377898,7 @@ module \right_mask case assign $47\mask[46:46] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362910,7 +377907,7 @@ module \right_mask case assign $48\mask[47:47] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$97 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362919,7 +377916,7 @@ module \right_mask case assign $49\mask[48:48] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$99 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362928,7 +377925,7 @@ module \right_mask case assign $50\mask[49:49] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362937,7 +377934,7 @@ module \right_mask case assign $51\mask[50:50] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362946,7 +377943,7 @@ module \right_mask case assign $52\mask[51:51] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362955,7 +377952,7 @@ module \right_mask case assign $53\mask[52:52] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$107 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362964,7 +377961,7 @@ module \right_mask case assign $54\mask[53:53] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$109 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362973,7 +377970,7 @@ module \right_mask case assign $55\mask[54:54] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$111 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362982,7 +377979,7 @@ module \right_mask case assign $56\mask[55:55] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -362991,7 +377988,7 @@ module \right_mask case assign $57\mask[56:56] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -363000,7 +377997,7 @@ module \right_mask case assign $58\mask[57:57] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -363009,7 +378006,7 @@ module \right_mask case assign $59\mask[58:58] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -363018,7 +378015,7 @@ module \right_mask case assign $60\mask[59:59] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -363027,7 +378024,7 @@ module \right_mask case assign $61\mask[60:60] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -363036,7 +378033,7 @@ module \right_mask case assign $62\mask[61:61] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$125 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -363045,7 +378042,7 @@ module \right_mask case assign $63\mask[62:62] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -363057,140 +378054,140 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:173448$11793_Y - connect \$99 $gt$libresoc.v:173449$11794_Y - connect \$101 $gt$libresoc.v:173450$11795_Y - connect \$103 $gt$libresoc.v:173451$11796_Y - connect \$105 $gt$libresoc.v:173452$11797_Y - connect \$107 $gt$libresoc.v:173453$11798_Y - connect \$109 $gt$libresoc.v:173454$11799_Y - connect \$111 $gt$libresoc.v:173455$11800_Y - connect \$113 $gt$libresoc.v:173456$11801_Y - connect \$115 $gt$libresoc.v:173457$11802_Y - connect \$117 $gt$libresoc.v:173458$11803_Y - connect \$11 $gt$libresoc.v:173459$11804_Y - connect \$119 $gt$libresoc.v:173460$11805_Y - connect \$121 $gt$libresoc.v:173461$11806_Y - connect \$123 $gt$libresoc.v:173462$11807_Y - connect \$125 $gt$libresoc.v:173463$11808_Y - connect \$127 $gt$libresoc.v:173464$11809_Y - connect \$13 $gt$libresoc.v:173465$11810_Y - connect \$15 $gt$libresoc.v:173466$11811_Y - connect \$17 $gt$libresoc.v:173467$11812_Y - connect \$1 $gt$libresoc.v:173468$11813_Y - connect \$19 $gt$libresoc.v:173469$11814_Y - connect \$21 $gt$libresoc.v:173470$11815_Y - connect \$23 $gt$libresoc.v:173471$11816_Y - connect \$25 $gt$libresoc.v:173472$11817_Y - connect \$27 $gt$libresoc.v:173473$11818_Y - connect \$29 $gt$libresoc.v:173474$11819_Y - connect \$31 $gt$libresoc.v:173475$11820_Y - connect \$33 $gt$libresoc.v:173476$11821_Y - connect \$35 $gt$libresoc.v:173477$11822_Y - connect \$37 $gt$libresoc.v:173478$11823_Y - connect \$3 $gt$libresoc.v:173479$11824_Y - connect \$39 $gt$libresoc.v:173480$11825_Y - connect \$41 $gt$libresoc.v:173481$11826_Y - connect \$43 $gt$libresoc.v:173482$11827_Y - connect \$45 $gt$libresoc.v:173483$11828_Y - connect \$47 $gt$libresoc.v:173484$11829_Y - connect \$49 $gt$libresoc.v:173485$11830_Y - connect \$51 $gt$libresoc.v:173486$11831_Y - connect \$53 $gt$libresoc.v:173487$11832_Y - connect \$55 $gt$libresoc.v:173488$11833_Y - connect \$57 $gt$libresoc.v:173489$11834_Y - connect \$5 $gt$libresoc.v:173490$11835_Y - connect \$59 $gt$libresoc.v:173491$11836_Y - connect \$61 $gt$libresoc.v:173492$11837_Y - connect \$63 $gt$libresoc.v:173493$11838_Y - connect \$65 $gt$libresoc.v:173494$11839_Y - connect \$67 $gt$libresoc.v:173495$11840_Y - connect \$69 $gt$libresoc.v:173496$11841_Y - connect \$71 $gt$libresoc.v:173497$11842_Y - connect \$73 $gt$libresoc.v:173498$11843_Y - connect \$75 $gt$libresoc.v:173499$11844_Y - connect \$77 $gt$libresoc.v:173500$11845_Y - connect \$7 $gt$libresoc.v:173501$11846_Y - connect \$79 $gt$libresoc.v:173502$11847_Y - connect \$81 $gt$libresoc.v:173503$11848_Y - connect \$83 $gt$libresoc.v:173504$11849_Y - connect \$85 $gt$libresoc.v:173505$11850_Y - connect \$87 $gt$libresoc.v:173506$11851_Y - connect \$89 $gt$libresoc.v:173507$11852_Y - connect \$91 $gt$libresoc.v:173508$11853_Y - connect \$93 $gt$libresoc.v:173509$11854_Y - connect \$95 $gt$libresoc.v:173510$11855_Y - connect \$97 $gt$libresoc.v:173511$11856_Y + connect \$9 $gt$libresoc.v:182153$11858_Y + connect \$99 $gt$libresoc.v:182154$11859_Y + connect \$101 $gt$libresoc.v:182155$11860_Y + connect \$103 $gt$libresoc.v:182156$11861_Y + connect \$105 $gt$libresoc.v:182157$11862_Y + connect \$107 $gt$libresoc.v:182158$11863_Y + connect \$109 $gt$libresoc.v:182159$11864_Y + connect \$111 $gt$libresoc.v:182160$11865_Y + connect \$113 $gt$libresoc.v:182161$11866_Y + connect \$115 $gt$libresoc.v:182162$11867_Y + connect \$117 $gt$libresoc.v:182163$11868_Y + connect \$11 $gt$libresoc.v:182164$11869_Y + connect \$119 $gt$libresoc.v:182165$11870_Y + connect \$121 $gt$libresoc.v:182166$11871_Y + connect \$123 $gt$libresoc.v:182167$11872_Y + connect \$125 $gt$libresoc.v:182168$11873_Y + connect \$127 $gt$libresoc.v:182169$11874_Y + connect \$13 $gt$libresoc.v:182170$11875_Y + connect \$15 $gt$libresoc.v:182171$11876_Y + connect \$17 $gt$libresoc.v:182172$11877_Y + connect \$1 $gt$libresoc.v:182173$11878_Y + connect \$19 $gt$libresoc.v:182174$11879_Y + connect \$21 $gt$libresoc.v:182175$11880_Y + connect \$23 $gt$libresoc.v:182176$11881_Y + connect \$25 $gt$libresoc.v:182177$11882_Y + connect \$27 $gt$libresoc.v:182178$11883_Y + connect \$29 $gt$libresoc.v:182179$11884_Y + connect \$31 $gt$libresoc.v:182180$11885_Y + connect \$33 $gt$libresoc.v:182181$11886_Y + connect \$35 $gt$libresoc.v:182182$11887_Y + connect \$37 $gt$libresoc.v:182183$11888_Y + connect \$3 $gt$libresoc.v:182184$11889_Y + connect \$39 $gt$libresoc.v:182185$11890_Y + connect \$41 $gt$libresoc.v:182186$11891_Y + connect \$43 $gt$libresoc.v:182187$11892_Y + connect \$45 $gt$libresoc.v:182188$11893_Y + connect \$47 $gt$libresoc.v:182189$11894_Y + connect \$49 $gt$libresoc.v:182190$11895_Y + connect \$51 $gt$libresoc.v:182191$11896_Y + connect \$53 $gt$libresoc.v:182192$11897_Y + connect \$55 $gt$libresoc.v:182193$11898_Y + connect \$57 $gt$libresoc.v:182194$11899_Y + connect \$5 $gt$libresoc.v:182195$11900_Y + connect \$59 $gt$libresoc.v:182196$11901_Y + connect \$61 $gt$libresoc.v:182197$11902_Y + connect \$63 $gt$libresoc.v:182198$11903_Y + connect \$65 $gt$libresoc.v:182199$11904_Y + connect \$67 $gt$libresoc.v:182200$11905_Y + connect \$69 $gt$libresoc.v:182201$11906_Y + connect \$71 $gt$libresoc.v:182202$11907_Y + connect \$73 $gt$libresoc.v:182203$11908_Y + connect \$75 $gt$libresoc.v:182204$11909_Y + connect \$77 $gt$libresoc.v:182205$11910_Y + connect \$7 $gt$libresoc.v:182206$11911_Y + connect \$79 $gt$libresoc.v:182207$11912_Y + connect \$81 $gt$libresoc.v:182208$11913_Y + connect \$83 $gt$libresoc.v:182209$11914_Y + connect \$85 $gt$libresoc.v:182210$11915_Y + connect \$87 $gt$libresoc.v:182211$11916_Y + connect \$89 $gt$libresoc.v:182212$11917_Y + connect \$91 $gt$libresoc.v:182213$11918_Y + connect \$93 $gt$libresoc.v:182214$11919_Y + connect \$95 $gt$libresoc.v:182215$11920_Y + connect \$97 $gt$libresoc.v:182216$11921_Y end -attribute \src "libresoc.v:173904.1-173962.10" +attribute \src "libresoc.v:182609.1-182667.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:173905.7-173905.20" + attribute \src "libresoc.v:182610.7-182610.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173950.3-173958.6" - wire $0\q_int$next[0:0]$11869 - attribute \src "libresoc.v:173948.3-173949.27" + attribute \src "libresoc.v:182655.3-182663.6" + wire $0\q_int$next[0:0]$11934 + attribute \src "libresoc.v:182653.3-182654.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:173950.3-173958.6" - wire $1\q_int$next[0:0]$11870 - attribute \src "libresoc.v:173927.7-173927.19" + attribute \src "libresoc.v:182655.3-182663.6" + wire $1\q_int$next[0:0]$11935 + attribute \src "libresoc.v:182632.7-182632.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:173940.17-173940.96" - wire $and$libresoc.v:173940$11859_Y - attribute \src "libresoc.v:173945.17-173945.96" - wire $and$libresoc.v:173945$11864_Y - attribute \src "libresoc.v:173942.18-173942.94" - wire $not$libresoc.v:173942$11861_Y - attribute \src "libresoc.v:173944.17-173944.93" - wire $not$libresoc.v:173944$11863_Y - attribute \src "libresoc.v:173947.17-173947.93" - wire $not$libresoc.v:173947$11866_Y - attribute \src "libresoc.v:173941.18-173941.99" - wire $or$libresoc.v:173941$11860_Y - attribute \src "libresoc.v:173943.18-173943.100" - wire $or$libresoc.v:173943$11862_Y - attribute \src "libresoc.v:173946.17-173946.98" - wire $or$libresoc.v:173946$11865_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:182645.17-182645.96" + wire $and$libresoc.v:182645$11924_Y + attribute \src "libresoc.v:182650.17-182650.96" + wire $and$libresoc.v:182650$11929_Y + attribute \src "libresoc.v:182647.18-182647.94" + wire $not$libresoc.v:182647$11926_Y + attribute \src "libresoc.v:182649.17-182649.93" + wire $not$libresoc.v:182649$11928_Y + attribute \src "libresoc.v:182652.17-182652.93" + wire $not$libresoc.v:182652$11931_Y + attribute \src "libresoc.v:182646.18-182646.99" + wire $or$libresoc.v:182646$11925_Y + attribute \src "libresoc.v:182648.18-182648.100" + wire $or$libresoc.v:182648$11927_Y + attribute \src "libresoc.v:182651.17-182651.98" + wire $or$libresoc.v:182651$11930_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:173905.7-173905.15" + attribute \src "libresoc.v:182610.7-182610.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173940$11859 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:182645$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363198,10 +378195,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:173940$11859_Y + connect \Y $and$libresoc.v:182645$11924_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173945$11864 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:182650$11929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363209,34 +378206,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:173945$11864_Y + connect \Y $and$libresoc.v:182650$11929_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173942$11861 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:182647$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:173942$11861_Y + connect \Y $not$libresoc.v:182647$11926_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173944$11863 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:182649$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:173944$11863_Y + connect \Y $not$libresoc.v:182649$11928_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173947$11866 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:182652$11931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:173947$11866_Y + connect \Y $not$libresoc.v:182652$11931_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173941$11860 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:182646$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363244,10 +378241,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:173941$11860_Y + connect \Y $or$libresoc.v:182646$11925_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173943$11862 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:182648$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363255,10 +378252,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:173943$11862_Y + connect \Y $or$libresoc.v:182648$11927_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173946$11865 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:182651$11930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363266,39 +378263,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:173946$11865_Y + connect \Y $or$libresoc.v:182651$11930_Y end - attribute \src "libresoc.v:173905.7-173905.20" - process $proc$libresoc.v:173905$11871 + attribute \src "libresoc.v:182610.7-182610.20" + process $proc$libresoc.v:182610$11936 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173927.7-173927.19" - process $proc$libresoc.v:173927$11872 + attribute \src "libresoc.v:182632.7-182632.19" + process $proc$libresoc.v:182632$11937 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:173948.3-173949.27" - process $proc$libresoc.v:173948$11867 + attribute \src "libresoc.v:182653.3-182654.27" + process $proc$libresoc.v:182653$11932 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:173950.3-173958.6" - process $proc$libresoc.v:173950$11868 + attribute \src "libresoc.v:182655.3-182663.6" + process $proc$libresoc.v:182655$11933 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11869 $1\q_int$next[0:0]$11870 - attribute \src "libresoc.v:173951.5-173951.29" + assign $0\q_int$next[0:0]$11934 $1\q_int$next[0:0]$11935 + attribute \src "libresoc.v:182656.5-182656.29" switch \initial - attribute \src "libresoc.v:173951.9-173951.17" + attribute \src "libresoc.v:182656.9-182656.17" case 1'1 case end @@ -363307,94 +378304,94 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11870 1'0 + assign $1\q_int$next[0:0]$11935 1'0 case - assign $1\q_int$next[0:0]$11870 \$5 + assign $1\q_int$next[0:0]$11935 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11869 + update \q_int$next $0\q_int$next[0:0]$11934 end - connect \$9 $and$libresoc.v:173940$11859_Y - connect \$11 $or$libresoc.v:173941$11860_Y - connect \$13 $not$libresoc.v:173942$11861_Y - connect \$15 $or$libresoc.v:173943$11862_Y - connect \$1 $not$libresoc.v:173944$11863_Y - connect \$3 $and$libresoc.v:173945$11864_Y - connect \$5 $or$libresoc.v:173946$11865_Y - connect \$7 $not$libresoc.v:173947$11866_Y + connect \$9 $and$libresoc.v:182645$11924_Y + connect \$11 $or$libresoc.v:182646$11925_Y + connect \$13 $not$libresoc.v:182647$11926_Y + connect \$15 $or$libresoc.v:182648$11927_Y + connect \$1 $not$libresoc.v:182649$11928_Y + connect \$3 $and$libresoc.v:182650$11929_Y + connect \$5 $or$libresoc.v:182651$11930_Y + connect \$7 $not$libresoc.v:182652$11931_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:173966.1-174024.10" +attribute \src "libresoc.v:182671.1-182729.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:173967.7-173967.20" + attribute \src "libresoc.v:182672.7-182672.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174012.3-174020.6" - wire $0\q_int$next[0:0]$11883 - attribute \src "libresoc.v:174010.3-174011.27" + attribute \src "libresoc.v:182717.3-182725.6" + wire $0\q_int$next[0:0]$11948 + attribute \src "libresoc.v:182715.3-182716.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174012.3-174020.6" - wire $1\q_int$next[0:0]$11884 - attribute \src "libresoc.v:173989.7-173989.19" + attribute \src "libresoc.v:182717.3-182725.6" + wire $1\q_int$next[0:0]$11949 + attribute \src "libresoc.v:182694.7-182694.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174002.17-174002.96" - wire $and$libresoc.v:174002$11873_Y - attribute \src "libresoc.v:174007.17-174007.96" - wire $and$libresoc.v:174007$11878_Y - attribute \src "libresoc.v:174004.18-174004.94" - wire $not$libresoc.v:174004$11875_Y - attribute \src "libresoc.v:174006.17-174006.93" - wire $not$libresoc.v:174006$11877_Y - attribute \src "libresoc.v:174009.17-174009.93" - wire $not$libresoc.v:174009$11880_Y - attribute \src "libresoc.v:174003.18-174003.99" - wire $or$libresoc.v:174003$11874_Y - attribute \src "libresoc.v:174005.18-174005.100" - wire $or$libresoc.v:174005$11876_Y - attribute \src "libresoc.v:174008.17-174008.98" - wire $or$libresoc.v:174008$11879_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:182707.17-182707.96" + wire $and$libresoc.v:182707$11938_Y + attribute \src "libresoc.v:182712.17-182712.96" + wire $and$libresoc.v:182712$11943_Y + attribute \src "libresoc.v:182709.18-182709.94" + wire $not$libresoc.v:182709$11940_Y + attribute \src "libresoc.v:182711.17-182711.93" + wire $not$libresoc.v:182711$11942_Y + attribute \src "libresoc.v:182714.17-182714.93" + wire $not$libresoc.v:182714$11945_Y + attribute \src "libresoc.v:182708.18-182708.99" + wire $or$libresoc.v:182708$11939_Y + attribute \src "libresoc.v:182710.18-182710.100" + wire $or$libresoc.v:182710$11941_Y + attribute \src "libresoc.v:182713.17-182713.98" + wire $or$libresoc.v:182713$11944_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:173967.7-173967.15" + attribute \src "libresoc.v:182672.7-182672.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174002$11873 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:182707$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363402,10 +378399,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174002$11873_Y + connect \Y $and$libresoc.v:182707$11938_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174007$11878 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:182712$11943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363413,34 +378410,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174007$11878_Y + connect \Y $and$libresoc.v:182712$11943_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174004$11875 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:182709$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:174004$11875_Y + connect \Y $not$libresoc.v:182709$11940_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174006$11877 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:182711$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174006$11877_Y + connect \Y $not$libresoc.v:182711$11942_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174009$11880 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:182714$11945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174009$11880_Y + connect \Y $not$libresoc.v:182714$11945_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174003$11874 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:182708$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363448,10 +378445,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:174003$11874_Y + connect \Y $or$libresoc.v:182708$11939_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174005$11876 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:182710$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363459,10 +378456,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:174005$11876_Y + connect \Y $or$libresoc.v:182710$11941_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174008$11879 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:182713$11944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363470,39 +378467,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:174008$11879_Y + connect \Y $or$libresoc.v:182713$11944_Y end - attribute \src "libresoc.v:173967.7-173967.20" - process $proc$libresoc.v:173967$11885 + attribute \src "libresoc.v:182672.7-182672.20" + process $proc$libresoc.v:182672$11950 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173989.7-173989.19" - process $proc$libresoc.v:173989$11886 + attribute \src "libresoc.v:182694.7-182694.19" + process $proc$libresoc.v:182694$11951 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174010.3-174011.27" - process $proc$libresoc.v:174010$11881 + attribute \src "libresoc.v:182715.3-182716.27" + process $proc$libresoc.v:182715$11946 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174012.3-174020.6" - process $proc$libresoc.v:174012$11882 + attribute \src "libresoc.v:182717.3-182725.6" + process $proc$libresoc.v:182717$11947 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11883 $1\q_int$next[0:0]$11884 - attribute \src "libresoc.v:174013.5-174013.29" + assign $0\q_int$next[0:0]$11948 $1\q_int$next[0:0]$11949 + attribute \src "libresoc.v:182718.5-182718.29" switch \initial - attribute \src "libresoc.v:174013.9-174013.17" + attribute \src "libresoc.v:182718.9-182718.17" case 1'1 case end @@ -363511,94 +378508,94 @@ module \rok_l$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11884 1'0 + assign $1\q_int$next[0:0]$11949 1'0 case - assign $1\q_int$next[0:0]$11884 \$5 + assign $1\q_int$next[0:0]$11949 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11883 + update \q_int$next $0\q_int$next[0:0]$11948 end - connect \$9 $and$libresoc.v:174002$11873_Y - connect \$11 $or$libresoc.v:174003$11874_Y - connect \$13 $not$libresoc.v:174004$11875_Y - connect \$15 $or$libresoc.v:174005$11876_Y - connect \$1 $not$libresoc.v:174006$11877_Y - connect \$3 $and$libresoc.v:174007$11878_Y - connect \$5 $or$libresoc.v:174008$11879_Y - connect \$7 $not$libresoc.v:174009$11880_Y + connect \$9 $and$libresoc.v:182707$11938_Y + connect \$11 $or$libresoc.v:182708$11939_Y + connect \$13 $not$libresoc.v:182709$11940_Y + connect \$15 $or$libresoc.v:182710$11941_Y + connect \$1 $not$libresoc.v:182711$11942_Y + connect \$3 $and$libresoc.v:182712$11943_Y + connect \$5 $or$libresoc.v:182713$11944_Y + connect \$7 $not$libresoc.v:182714$11945_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:174028.1-174086.10" +attribute \src "libresoc.v:182733.1-182791.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:174029.7-174029.20" + attribute \src "libresoc.v:182734.7-182734.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174074.3-174082.6" - wire $0\q_int$next[0:0]$11897 - attribute \src "libresoc.v:174072.3-174073.27" + attribute \src "libresoc.v:182779.3-182787.6" + wire $0\q_int$next[0:0]$11962 + attribute \src "libresoc.v:182777.3-182778.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174074.3-174082.6" - wire $1\q_int$next[0:0]$11898 - attribute \src "libresoc.v:174051.7-174051.19" + attribute \src "libresoc.v:182779.3-182787.6" + wire $1\q_int$next[0:0]$11963 + attribute \src "libresoc.v:182756.7-182756.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174064.17-174064.96" - wire $and$libresoc.v:174064$11887_Y - attribute \src "libresoc.v:174069.17-174069.96" - wire $and$libresoc.v:174069$11892_Y - attribute \src "libresoc.v:174066.18-174066.94" - wire $not$libresoc.v:174066$11889_Y - attribute \src "libresoc.v:174068.17-174068.93" - wire $not$libresoc.v:174068$11891_Y - attribute \src "libresoc.v:174071.17-174071.93" - wire $not$libresoc.v:174071$11894_Y - attribute \src "libresoc.v:174065.18-174065.99" - wire $or$libresoc.v:174065$11888_Y - attribute \src "libresoc.v:174067.18-174067.100" - wire $or$libresoc.v:174067$11890_Y - attribute \src "libresoc.v:174070.17-174070.98" - wire $or$libresoc.v:174070$11893_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:182769.17-182769.96" + wire $and$libresoc.v:182769$11952_Y + attribute \src "libresoc.v:182774.17-182774.96" + wire $and$libresoc.v:182774$11957_Y + attribute \src "libresoc.v:182771.18-182771.94" + wire $not$libresoc.v:182771$11954_Y + attribute \src "libresoc.v:182773.17-182773.93" + wire $not$libresoc.v:182773$11956_Y + attribute \src "libresoc.v:182776.17-182776.93" + wire $not$libresoc.v:182776$11959_Y + attribute \src "libresoc.v:182770.18-182770.99" + wire $or$libresoc.v:182770$11953_Y + attribute \src "libresoc.v:182772.18-182772.100" + wire $or$libresoc.v:182772$11955_Y + attribute \src "libresoc.v:182775.17-182775.98" + wire $or$libresoc.v:182775$11958_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174029.7-174029.15" + attribute \src "libresoc.v:182734.7-182734.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174064$11887 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:182769$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363606,10 +378603,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174064$11887_Y + connect \Y $and$libresoc.v:182769$11952_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174069$11892 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:182774$11957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363617,34 +378614,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174069$11892_Y + connect \Y $and$libresoc.v:182774$11957_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174066$11889 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:182771$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:174066$11889_Y + connect \Y $not$libresoc.v:182771$11954_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174068$11891 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:182773$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174068$11891_Y + connect \Y $not$libresoc.v:182773$11956_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174071$11894 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:182776$11959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174071$11894_Y + connect \Y $not$libresoc.v:182776$11959_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174065$11888 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:182770$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363652,10 +378649,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:174065$11888_Y + connect \Y $or$libresoc.v:182770$11953_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174067$11890 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:182772$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363663,10 +378660,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:174067$11890_Y + connect \Y $or$libresoc.v:182772$11955_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174070$11893 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:182775$11958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363674,39 +378671,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:174070$11893_Y + connect \Y $or$libresoc.v:182775$11958_Y end - attribute \src "libresoc.v:174029.7-174029.20" - process $proc$libresoc.v:174029$11899 + attribute \src "libresoc.v:182734.7-182734.20" + process $proc$libresoc.v:182734$11964 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174051.7-174051.19" - process $proc$libresoc.v:174051$11900 + attribute \src "libresoc.v:182756.7-182756.19" + process $proc$libresoc.v:182756$11965 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174072.3-174073.27" - process $proc$libresoc.v:174072$11895 + attribute \src "libresoc.v:182777.3-182778.27" + process $proc$libresoc.v:182777$11960 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174074.3-174082.6" - process $proc$libresoc.v:174074$11896 + attribute \src "libresoc.v:182779.3-182787.6" + process $proc$libresoc.v:182779$11961 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11897 $1\q_int$next[0:0]$11898 - attribute \src "libresoc.v:174075.5-174075.29" + assign $0\q_int$next[0:0]$11962 $1\q_int$next[0:0]$11963 + attribute \src "libresoc.v:182780.5-182780.29" switch \initial - attribute \src "libresoc.v:174075.9-174075.17" + attribute \src "libresoc.v:182780.9-182780.17" case 1'1 case end @@ -363715,94 +378712,94 @@ module \rok_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11898 1'0 + assign $1\q_int$next[0:0]$11963 1'0 case - assign $1\q_int$next[0:0]$11898 \$5 + assign $1\q_int$next[0:0]$11963 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11897 + update \q_int$next $0\q_int$next[0:0]$11962 end - connect \$9 $and$libresoc.v:174064$11887_Y - connect \$11 $or$libresoc.v:174065$11888_Y - connect \$13 $not$libresoc.v:174066$11889_Y - connect \$15 $or$libresoc.v:174067$11890_Y - connect \$1 $not$libresoc.v:174068$11891_Y - connect \$3 $and$libresoc.v:174069$11892_Y - connect \$5 $or$libresoc.v:174070$11893_Y - connect \$7 $not$libresoc.v:174071$11894_Y + connect \$9 $and$libresoc.v:182769$11952_Y + connect \$11 $or$libresoc.v:182770$11953_Y + connect \$13 $not$libresoc.v:182771$11954_Y + connect \$15 $or$libresoc.v:182772$11955_Y + connect \$1 $not$libresoc.v:182773$11956_Y + connect \$3 $and$libresoc.v:182774$11957_Y + connect \$5 $or$libresoc.v:182775$11958_Y + connect \$7 $not$libresoc.v:182776$11959_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:174090.1-174148.10" +attribute \src "libresoc.v:182795.1-182853.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:174091.7-174091.20" + attribute \src "libresoc.v:182796.7-182796.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174136.3-174144.6" - wire $0\q_int$next[0:0]$11911 - attribute \src "libresoc.v:174134.3-174135.27" + attribute \src "libresoc.v:182841.3-182849.6" + wire $0\q_int$next[0:0]$11976 + attribute \src "libresoc.v:182839.3-182840.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174136.3-174144.6" - wire $1\q_int$next[0:0]$11912 - attribute \src "libresoc.v:174113.7-174113.19" + attribute \src "libresoc.v:182841.3-182849.6" + wire $1\q_int$next[0:0]$11977 + attribute \src "libresoc.v:182818.7-182818.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174126.17-174126.96" - wire $and$libresoc.v:174126$11901_Y - attribute \src "libresoc.v:174131.17-174131.96" - wire $and$libresoc.v:174131$11906_Y - attribute \src "libresoc.v:174128.18-174128.94" - wire $not$libresoc.v:174128$11903_Y - attribute \src "libresoc.v:174130.17-174130.93" - wire $not$libresoc.v:174130$11905_Y - attribute \src "libresoc.v:174133.17-174133.93" - wire $not$libresoc.v:174133$11908_Y - attribute \src "libresoc.v:174127.18-174127.99" - wire $or$libresoc.v:174127$11902_Y - attribute \src "libresoc.v:174129.18-174129.100" - wire $or$libresoc.v:174129$11904_Y - attribute \src "libresoc.v:174132.17-174132.98" - wire $or$libresoc.v:174132$11907_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:182831.17-182831.96" + wire $and$libresoc.v:182831$11966_Y + attribute \src "libresoc.v:182836.17-182836.96" + wire $and$libresoc.v:182836$11971_Y + attribute \src "libresoc.v:182833.18-182833.94" + wire $not$libresoc.v:182833$11968_Y + attribute \src "libresoc.v:182835.17-182835.93" + wire $not$libresoc.v:182835$11970_Y + attribute \src "libresoc.v:182838.17-182838.93" + wire $not$libresoc.v:182838$11973_Y + attribute \src "libresoc.v:182832.18-182832.99" + wire $or$libresoc.v:182832$11967_Y + attribute \src "libresoc.v:182834.18-182834.100" + wire $or$libresoc.v:182834$11969_Y + attribute \src "libresoc.v:182837.17-182837.98" + wire $or$libresoc.v:182837$11972_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174091.7-174091.15" + attribute \src "libresoc.v:182796.7-182796.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174126$11901 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:182831$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363810,10 +378807,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174126$11901_Y + connect \Y $and$libresoc.v:182831$11966_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174131$11906 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:182836$11971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363821,34 +378818,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174131$11906_Y + connect \Y $and$libresoc.v:182836$11971_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174128$11903 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:182833$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:174128$11903_Y + connect \Y $not$libresoc.v:182833$11968_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174130$11905 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:182835$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174130$11905_Y + connect \Y $not$libresoc.v:182835$11970_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174133$11908 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:182838$11973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174133$11908_Y + connect \Y $not$libresoc.v:182838$11973_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174127$11902 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:182832$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363856,10 +378853,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:174127$11902_Y + connect \Y $or$libresoc.v:182832$11967_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174129$11904 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:182834$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363867,10 +378864,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:174129$11904_Y + connect \Y $or$libresoc.v:182834$11969_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174132$11907 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:182837$11972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -363878,39 +378875,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:174132$11907_Y + connect \Y $or$libresoc.v:182837$11972_Y end - attribute \src "libresoc.v:174091.7-174091.20" - process $proc$libresoc.v:174091$11913 + attribute \src "libresoc.v:182796.7-182796.20" + process $proc$libresoc.v:182796$11978 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174113.7-174113.19" - process $proc$libresoc.v:174113$11914 + attribute \src "libresoc.v:182818.7-182818.19" + process $proc$libresoc.v:182818$11979 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174134.3-174135.27" - process $proc$libresoc.v:174134$11909 + attribute \src "libresoc.v:182839.3-182840.27" + process $proc$libresoc.v:182839$11974 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174136.3-174144.6" - process $proc$libresoc.v:174136$11910 + attribute \src "libresoc.v:182841.3-182849.6" + process $proc$libresoc.v:182841$11975 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11911 $1\q_int$next[0:0]$11912 - attribute \src "libresoc.v:174137.5-174137.29" + assign $0\q_int$next[0:0]$11976 $1\q_int$next[0:0]$11977 + attribute \src "libresoc.v:182842.5-182842.29" switch \initial - attribute \src "libresoc.v:174137.9-174137.17" + attribute \src "libresoc.v:182842.9-182842.17" case 1'1 case end @@ -363919,94 +378916,94 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11912 1'0 + assign $1\q_int$next[0:0]$11977 1'0 case - assign $1\q_int$next[0:0]$11912 \$5 + assign $1\q_int$next[0:0]$11977 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11911 + update \q_int$next $0\q_int$next[0:0]$11976 end - connect \$9 $and$libresoc.v:174126$11901_Y - connect \$11 $or$libresoc.v:174127$11902_Y - connect \$13 $not$libresoc.v:174128$11903_Y - connect \$15 $or$libresoc.v:174129$11904_Y - connect \$1 $not$libresoc.v:174130$11905_Y - connect \$3 $and$libresoc.v:174131$11906_Y - connect \$5 $or$libresoc.v:174132$11907_Y - connect \$7 $not$libresoc.v:174133$11908_Y + connect \$9 $and$libresoc.v:182831$11966_Y + connect \$11 $or$libresoc.v:182832$11967_Y + connect \$13 $not$libresoc.v:182833$11968_Y + connect \$15 $or$libresoc.v:182834$11969_Y + connect \$1 $not$libresoc.v:182835$11970_Y + connect \$3 $and$libresoc.v:182836$11971_Y + connect \$5 $or$libresoc.v:182837$11972_Y + connect \$7 $not$libresoc.v:182838$11973_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:174152.1-174210.10" +attribute \src "libresoc.v:182857.1-182915.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:174153.7-174153.20" + attribute \src "libresoc.v:182858.7-182858.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174198.3-174206.6" - wire $0\q_int$next[0:0]$11925 - attribute \src "libresoc.v:174196.3-174197.27" + attribute \src "libresoc.v:182903.3-182911.6" + wire $0\q_int$next[0:0]$11990 + attribute \src "libresoc.v:182901.3-182902.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174198.3-174206.6" - wire $1\q_int$next[0:0]$11926 - attribute \src "libresoc.v:174175.7-174175.19" + attribute \src "libresoc.v:182903.3-182911.6" + wire $1\q_int$next[0:0]$11991 + attribute \src "libresoc.v:182880.7-182880.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174188.17-174188.96" - wire $and$libresoc.v:174188$11915_Y - attribute \src "libresoc.v:174193.17-174193.96" - wire $and$libresoc.v:174193$11920_Y - attribute \src "libresoc.v:174190.18-174190.94" - wire $not$libresoc.v:174190$11917_Y - attribute \src "libresoc.v:174192.17-174192.93" - wire $not$libresoc.v:174192$11919_Y - attribute \src "libresoc.v:174195.17-174195.93" - wire $not$libresoc.v:174195$11922_Y - attribute \src "libresoc.v:174189.18-174189.99" - wire $or$libresoc.v:174189$11916_Y - attribute \src "libresoc.v:174191.18-174191.100" - wire $or$libresoc.v:174191$11918_Y - attribute \src "libresoc.v:174194.17-174194.98" - wire $or$libresoc.v:174194$11921_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:182893.17-182893.96" + wire $and$libresoc.v:182893$11980_Y + attribute \src "libresoc.v:182898.17-182898.96" + wire $and$libresoc.v:182898$11985_Y + attribute \src "libresoc.v:182895.18-182895.94" + wire $not$libresoc.v:182895$11982_Y + attribute \src "libresoc.v:182897.17-182897.93" + wire $not$libresoc.v:182897$11984_Y + attribute \src "libresoc.v:182900.17-182900.93" + wire $not$libresoc.v:182900$11987_Y + attribute \src "libresoc.v:182894.18-182894.99" + wire $or$libresoc.v:182894$11981_Y + attribute \src "libresoc.v:182896.18-182896.100" + wire $or$libresoc.v:182896$11983_Y + attribute \src "libresoc.v:182899.17-182899.98" + wire $or$libresoc.v:182899$11986_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174153.7-174153.15" + attribute \src "libresoc.v:182858.7-182858.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174188$11915 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:182893$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364014,10 +379011,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174188$11915_Y + connect \Y $and$libresoc.v:182893$11980_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174193$11920 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:182898$11985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364025,34 +379022,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174193$11920_Y + connect \Y $and$libresoc.v:182898$11985_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174190$11917 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:182895$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:174190$11917_Y + connect \Y $not$libresoc.v:182895$11982_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174192$11919 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:182897$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174192$11919_Y + connect \Y $not$libresoc.v:182897$11984_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174195$11922 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:182900$11987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174195$11922_Y + connect \Y $not$libresoc.v:182900$11987_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174189$11916 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:182894$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364060,10 +379057,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:174189$11916_Y + connect \Y $or$libresoc.v:182894$11981_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174191$11918 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:182896$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364071,10 +379068,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:174191$11918_Y + connect \Y $or$libresoc.v:182896$11983_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174194$11921 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:182899$11986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364082,39 +379079,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:174194$11921_Y + connect \Y $or$libresoc.v:182899$11986_Y end - attribute \src "libresoc.v:174153.7-174153.20" - process $proc$libresoc.v:174153$11927 + attribute \src "libresoc.v:182858.7-182858.20" + process $proc$libresoc.v:182858$11992 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174175.7-174175.19" - process $proc$libresoc.v:174175$11928 + attribute \src "libresoc.v:182880.7-182880.19" + process $proc$libresoc.v:182880$11993 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174196.3-174197.27" - process $proc$libresoc.v:174196$11923 + attribute \src "libresoc.v:182901.3-182902.27" + process $proc$libresoc.v:182901$11988 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174198.3-174206.6" - process $proc$libresoc.v:174198$11924 + attribute \src "libresoc.v:182903.3-182911.6" + process $proc$libresoc.v:182903$11989 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11925 $1\q_int$next[0:0]$11926 - attribute \src "libresoc.v:174199.5-174199.29" + assign $0\q_int$next[0:0]$11990 $1\q_int$next[0:0]$11991 + attribute \src "libresoc.v:182904.5-182904.29" switch \initial - attribute \src "libresoc.v:174199.9-174199.17" + attribute \src "libresoc.v:182904.9-182904.17" case 1'1 case end @@ -364123,94 +379120,94 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11926 1'0 + assign $1\q_int$next[0:0]$11991 1'0 case - assign $1\q_int$next[0:0]$11926 \$5 + assign $1\q_int$next[0:0]$11991 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11925 + update \q_int$next $0\q_int$next[0:0]$11990 end - connect \$9 $and$libresoc.v:174188$11915_Y - connect \$11 $or$libresoc.v:174189$11916_Y - connect \$13 $not$libresoc.v:174190$11917_Y - connect \$15 $or$libresoc.v:174191$11918_Y - connect \$1 $not$libresoc.v:174192$11919_Y - connect \$3 $and$libresoc.v:174193$11920_Y - connect \$5 $or$libresoc.v:174194$11921_Y - connect \$7 $not$libresoc.v:174195$11922_Y + connect \$9 $and$libresoc.v:182893$11980_Y + connect \$11 $or$libresoc.v:182894$11981_Y + connect \$13 $not$libresoc.v:182895$11982_Y + connect \$15 $or$libresoc.v:182896$11983_Y + connect \$1 $not$libresoc.v:182897$11984_Y + connect \$3 $and$libresoc.v:182898$11985_Y + connect \$5 $or$libresoc.v:182899$11986_Y + connect \$7 $not$libresoc.v:182900$11987_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:174214.1-174272.10" +attribute \src "libresoc.v:182919.1-182977.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:174215.7-174215.20" + attribute \src "libresoc.v:182920.7-182920.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174260.3-174268.6" - wire $0\q_int$next[0:0]$11939 - attribute \src "libresoc.v:174258.3-174259.27" + attribute \src "libresoc.v:182965.3-182973.6" + wire $0\q_int$next[0:0]$12004 + attribute \src "libresoc.v:182963.3-182964.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174260.3-174268.6" - wire $1\q_int$next[0:0]$11940 - attribute \src "libresoc.v:174237.7-174237.19" + attribute \src "libresoc.v:182965.3-182973.6" + wire $1\q_int$next[0:0]$12005 + attribute \src "libresoc.v:182942.7-182942.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174250.17-174250.96" - wire $and$libresoc.v:174250$11929_Y - attribute \src "libresoc.v:174255.17-174255.96" - wire $and$libresoc.v:174255$11934_Y - attribute \src "libresoc.v:174252.18-174252.94" - wire $not$libresoc.v:174252$11931_Y - attribute \src "libresoc.v:174254.17-174254.93" - wire $not$libresoc.v:174254$11933_Y - attribute \src "libresoc.v:174257.17-174257.93" - wire $not$libresoc.v:174257$11936_Y - attribute \src "libresoc.v:174251.18-174251.99" - wire $or$libresoc.v:174251$11930_Y - attribute \src "libresoc.v:174253.18-174253.100" - wire $or$libresoc.v:174253$11932_Y - attribute \src "libresoc.v:174256.17-174256.98" - wire $or$libresoc.v:174256$11935_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:182955.17-182955.96" + wire $and$libresoc.v:182955$11994_Y + attribute \src "libresoc.v:182960.17-182960.96" + wire $and$libresoc.v:182960$11999_Y + attribute \src "libresoc.v:182957.18-182957.94" + wire $not$libresoc.v:182957$11996_Y + attribute \src "libresoc.v:182959.17-182959.93" + wire $not$libresoc.v:182959$11998_Y + attribute \src "libresoc.v:182962.17-182962.93" + wire $not$libresoc.v:182962$12001_Y + attribute \src "libresoc.v:182956.18-182956.99" + wire $or$libresoc.v:182956$11995_Y + attribute \src "libresoc.v:182958.18-182958.100" + wire $or$libresoc.v:182958$11997_Y + attribute \src "libresoc.v:182961.17-182961.98" + wire $or$libresoc.v:182961$12000_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174215.7-174215.15" + attribute \src "libresoc.v:182920.7-182920.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174250$11929 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:182955$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364218,10 +379215,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174250$11929_Y + connect \Y $and$libresoc.v:182955$11994_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174255$11934 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:182960$11999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364229,34 +379226,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174255$11934_Y + connect \Y $and$libresoc.v:182960$11999_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174252$11931 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:182957$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:174252$11931_Y + connect \Y $not$libresoc.v:182957$11996_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174254$11933 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:182959$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174254$11933_Y + connect \Y $not$libresoc.v:182959$11998_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174257$11936 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:182962$12001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174257$11936_Y + connect \Y $not$libresoc.v:182962$12001_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174251$11930 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:182956$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364264,10 +379261,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:174251$11930_Y + connect \Y $or$libresoc.v:182956$11995_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174253$11932 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:182958$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364275,10 +379272,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:174253$11932_Y + connect \Y $or$libresoc.v:182958$11997_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174256$11935 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:182961$12000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364286,39 +379283,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:174256$11935_Y + connect \Y $or$libresoc.v:182961$12000_Y end - attribute \src "libresoc.v:174215.7-174215.20" - process $proc$libresoc.v:174215$11941 + attribute \src "libresoc.v:182920.7-182920.20" + process $proc$libresoc.v:182920$12006 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174237.7-174237.19" - process $proc$libresoc.v:174237$11942 + attribute \src "libresoc.v:182942.7-182942.19" + process $proc$libresoc.v:182942$12007 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174258.3-174259.27" - process $proc$libresoc.v:174258$11937 + attribute \src "libresoc.v:182963.3-182964.27" + process $proc$libresoc.v:182963$12002 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174260.3-174268.6" - process $proc$libresoc.v:174260$11938 + attribute \src "libresoc.v:182965.3-182973.6" + process $proc$libresoc.v:182965$12003 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11939 $1\q_int$next[0:0]$11940 - attribute \src "libresoc.v:174261.5-174261.29" + assign $0\q_int$next[0:0]$12004 $1\q_int$next[0:0]$12005 + attribute \src "libresoc.v:182966.5-182966.29" switch \initial - attribute \src "libresoc.v:174261.9-174261.17" + attribute \src "libresoc.v:182966.9-182966.17" case 1'1 case end @@ -364327,94 +379324,94 @@ module \rok_l$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11940 1'0 + assign $1\q_int$next[0:0]$12005 1'0 case - assign $1\q_int$next[0:0]$11940 \$5 + assign $1\q_int$next[0:0]$12005 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11939 + update \q_int$next $0\q_int$next[0:0]$12004 end - connect \$9 $and$libresoc.v:174250$11929_Y - connect \$11 $or$libresoc.v:174251$11930_Y - connect \$13 $not$libresoc.v:174252$11931_Y - connect \$15 $or$libresoc.v:174253$11932_Y - connect \$1 $not$libresoc.v:174254$11933_Y - connect \$3 $and$libresoc.v:174255$11934_Y - connect \$5 $or$libresoc.v:174256$11935_Y - connect \$7 $not$libresoc.v:174257$11936_Y + connect \$9 $and$libresoc.v:182955$11994_Y + connect \$11 $or$libresoc.v:182956$11995_Y + connect \$13 $not$libresoc.v:182957$11996_Y + connect \$15 $or$libresoc.v:182958$11997_Y + connect \$1 $not$libresoc.v:182959$11998_Y + connect \$3 $and$libresoc.v:182960$11999_Y + connect \$5 $or$libresoc.v:182961$12000_Y + connect \$7 $not$libresoc.v:182962$12001_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:174276.1-174334.10" +attribute \src "libresoc.v:182981.1-183039.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:174277.7-174277.20" + attribute \src "libresoc.v:182982.7-182982.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174322.3-174330.6" - wire $0\q_int$next[0:0]$11953 - attribute \src "libresoc.v:174320.3-174321.27" + attribute \src "libresoc.v:183027.3-183035.6" + wire $0\q_int$next[0:0]$12018 + attribute \src "libresoc.v:183025.3-183026.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174322.3-174330.6" - wire $1\q_int$next[0:0]$11954 - attribute \src "libresoc.v:174299.7-174299.19" + attribute \src "libresoc.v:183027.3-183035.6" + wire $1\q_int$next[0:0]$12019 + attribute \src "libresoc.v:183004.7-183004.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174312.17-174312.96" - wire $and$libresoc.v:174312$11943_Y - attribute \src "libresoc.v:174317.17-174317.96" - wire $and$libresoc.v:174317$11948_Y - attribute \src "libresoc.v:174314.18-174314.94" - wire $not$libresoc.v:174314$11945_Y - attribute \src "libresoc.v:174316.17-174316.93" - wire $not$libresoc.v:174316$11947_Y - attribute \src "libresoc.v:174319.17-174319.93" - wire $not$libresoc.v:174319$11950_Y - attribute \src "libresoc.v:174313.18-174313.99" - wire $or$libresoc.v:174313$11944_Y - attribute \src "libresoc.v:174315.18-174315.100" - wire $or$libresoc.v:174315$11946_Y - attribute \src "libresoc.v:174318.17-174318.98" - wire $or$libresoc.v:174318$11949_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183017.17-183017.96" + wire $and$libresoc.v:183017$12008_Y + attribute \src "libresoc.v:183022.17-183022.96" + wire $and$libresoc.v:183022$12013_Y + attribute \src "libresoc.v:183019.18-183019.94" + wire $not$libresoc.v:183019$12010_Y + attribute \src "libresoc.v:183021.17-183021.93" + wire $not$libresoc.v:183021$12012_Y + attribute \src "libresoc.v:183024.17-183024.93" + wire $not$libresoc.v:183024$12015_Y + attribute \src "libresoc.v:183018.18-183018.99" + wire $or$libresoc.v:183018$12009_Y + attribute \src "libresoc.v:183020.18-183020.100" + wire $or$libresoc.v:183020$12011_Y + attribute \src "libresoc.v:183023.17-183023.98" + wire $or$libresoc.v:183023$12014_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174277.7-174277.15" + attribute \src "libresoc.v:182982.7-182982.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174312$11943 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183017$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364422,10 +379419,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174312$11943_Y + connect \Y $and$libresoc.v:183017$12008_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174317$11948 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183022$12013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364433,34 +379430,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174317$11948_Y + connect \Y $and$libresoc.v:183022$12013_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174314$11945 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183019$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:174314$11945_Y + connect \Y $not$libresoc.v:183019$12010_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174316$11947 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183021$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174316$11947_Y + connect \Y $not$libresoc.v:183021$12012_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174319$11950 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183024$12015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174319$11950_Y + connect \Y $not$libresoc.v:183024$12015_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174313$11944 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183018$12009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364468,10 +379465,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:174313$11944_Y + connect \Y $or$libresoc.v:183018$12009_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174315$11946 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183020$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364479,10 +379476,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:174315$11946_Y + connect \Y $or$libresoc.v:183020$12011_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174318$11949 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183023$12014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364490,39 +379487,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:174318$11949_Y + connect \Y $or$libresoc.v:183023$12014_Y end - attribute \src "libresoc.v:174277.7-174277.20" - process $proc$libresoc.v:174277$11955 + attribute \src "libresoc.v:182982.7-182982.20" + process $proc$libresoc.v:182982$12020 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174299.7-174299.19" - process $proc$libresoc.v:174299$11956 + attribute \src "libresoc.v:183004.7-183004.19" + process $proc$libresoc.v:183004$12021 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174320.3-174321.27" - process $proc$libresoc.v:174320$11951 + attribute \src "libresoc.v:183025.3-183026.27" + process $proc$libresoc.v:183025$12016 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174322.3-174330.6" - process $proc$libresoc.v:174322$11952 + attribute \src "libresoc.v:183027.3-183035.6" + process $proc$libresoc.v:183027$12017 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11953 $1\q_int$next[0:0]$11954 - attribute \src "libresoc.v:174323.5-174323.29" + assign $0\q_int$next[0:0]$12018 $1\q_int$next[0:0]$12019 + attribute \src "libresoc.v:183028.5-183028.29" switch \initial - attribute \src "libresoc.v:174323.9-174323.17" + attribute \src "libresoc.v:183028.9-183028.17" case 1'1 case end @@ -364531,94 +379528,94 @@ module \rok_l$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11954 1'0 + assign $1\q_int$next[0:0]$12019 1'0 case - assign $1\q_int$next[0:0]$11954 \$5 + assign $1\q_int$next[0:0]$12019 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11953 + update \q_int$next $0\q_int$next[0:0]$12018 end - connect \$9 $and$libresoc.v:174312$11943_Y - connect \$11 $or$libresoc.v:174313$11944_Y - connect \$13 $not$libresoc.v:174314$11945_Y - connect \$15 $or$libresoc.v:174315$11946_Y - connect \$1 $not$libresoc.v:174316$11947_Y - connect \$3 $and$libresoc.v:174317$11948_Y - connect \$5 $or$libresoc.v:174318$11949_Y - connect \$7 $not$libresoc.v:174319$11950_Y + connect \$9 $and$libresoc.v:183017$12008_Y + connect \$11 $or$libresoc.v:183018$12009_Y + connect \$13 $not$libresoc.v:183019$12010_Y + connect \$15 $or$libresoc.v:183020$12011_Y + connect \$1 $not$libresoc.v:183021$12012_Y + connect \$3 $and$libresoc.v:183022$12013_Y + connect \$5 $or$libresoc.v:183023$12014_Y + connect \$7 $not$libresoc.v:183024$12015_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:174338.1-174396.10" +attribute \src "libresoc.v:183043.1-183101.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:174339.7-174339.20" + attribute \src "libresoc.v:183044.7-183044.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174384.3-174392.6" - wire $0\q_int$next[0:0]$11967 - attribute \src "libresoc.v:174382.3-174383.27" + attribute \src "libresoc.v:183089.3-183097.6" + wire $0\q_int$next[0:0]$12032 + attribute \src "libresoc.v:183087.3-183088.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174384.3-174392.6" - wire $1\q_int$next[0:0]$11968 - attribute \src "libresoc.v:174361.7-174361.19" + attribute \src "libresoc.v:183089.3-183097.6" + wire $1\q_int$next[0:0]$12033 + attribute \src "libresoc.v:183066.7-183066.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174374.17-174374.96" - wire $and$libresoc.v:174374$11957_Y - attribute \src "libresoc.v:174379.17-174379.96" - wire $and$libresoc.v:174379$11962_Y - attribute \src "libresoc.v:174376.18-174376.94" - wire $not$libresoc.v:174376$11959_Y - attribute \src "libresoc.v:174378.17-174378.93" - wire $not$libresoc.v:174378$11961_Y - attribute \src "libresoc.v:174381.17-174381.93" - wire $not$libresoc.v:174381$11964_Y - attribute \src "libresoc.v:174375.18-174375.99" - wire $or$libresoc.v:174375$11958_Y - attribute \src "libresoc.v:174377.18-174377.100" - wire $or$libresoc.v:174377$11960_Y - attribute \src "libresoc.v:174380.17-174380.98" - wire $or$libresoc.v:174380$11963_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183079.17-183079.96" + wire $and$libresoc.v:183079$12022_Y + attribute \src "libresoc.v:183084.17-183084.96" + wire $and$libresoc.v:183084$12027_Y + attribute \src "libresoc.v:183081.18-183081.94" + wire $not$libresoc.v:183081$12024_Y + attribute \src "libresoc.v:183083.17-183083.93" + wire $not$libresoc.v:183083$12026_Y + attribute \src "libresoc.v:183086.17-183086.93" + wire $not$libresoc.v:183086$12029_Y + attribute \src "libresoc.v:183080.18-183080.99" + wire $or$libresoc.v:183080$12023_Y + attribute \src "libresoc.v:183082.18-183082.100" + wire $or$libresoc.v:183082$12025_Y + attribute \src "libresoc.v:183085.17-183085.98" + wire $or$libresoc.v:183085$12028_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174339.7-174339.15" + attribute \src "libresoc.v:183044.7-183044.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174374$11957 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183079$12022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364626,10 +379623,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174374$11957_Y + connect \Y $and$libresoc.v:183079$12022_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174379$11962 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183084$12027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364637,34 +379634,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174379$11962_Y + connect \Y $and$libresoc.v:183084$12027_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174376$11959 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183081$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:174376$11959_Y + connect \Y $not$libresoc.v:183081$12024_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174378$11961 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183083$12026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174378$11961_Y + connect \Y $not$libresoc.v:183083$12026_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174381$11964 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183086$12029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174381$11964_Y + connect \Y $not$libresoc.v:183086$12029_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174375$11958 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183080$12023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364672,10 +379669,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:174375$11958_Y + connect \Y $or$libresoc.v:183080$12023_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174377$11960 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183082$12025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364683,10 +379680,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:174377$11960_Y + connect \Y $or$libresoc.v:183082$12025_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174380$11963 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183085$12028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364694,39 +379691,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:174380$11963_Y + connect \Y $or$libresoc.v:183085$12028_Y end - attribute \src "libresoc.v:174339.7-174339.20" - process $proc$libresoc.v:174339$11969 + attribute \src "libresoc.v:183044.7-183044.20" + process $proc$libresoc.v:183044$12034 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174361.7-174361.19" - process $proc$libresoc.v:174361$11970 + attribute \src "libresoc.v:183066.7-183066.19" + process $proc$libresoc.v:183066$12035 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174382.3-174383.27" - process $proc$libresoc.v:174382$11965 + attribute \src "libresoc.v:183087.3-183088.27" + process $proc$libresoc.v:183087$12030 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174384.3-174392.6" - process $proc$libresoc.v:174384$11966 + attribute \src "libresoc.v:183089.3-183097.6" + process $proc$libresoc.v:183089$12031 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11967 $1\q_int$next[0:0]$11968 - attribute \src "libresoc.v:174385.5-174385.29" + assign $0\q_int$next[0:0]$12032 $1\q_int$next[0:0]$12033 + attribute \src "libresoc.v:183090.5-183090.29" switch \initial - attribute \src "libresoc.v:174385.9-174385.17" + attribute \src "libresoc.v:183090.9-183090.17" case 1'1 case end @@ -364735,94 +379732,94 @@ module \rok_l$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11968 1'0 + assign $1\q_int$next[0:0]$12033 1'0 case - assign $1\q_int$next[0:0]$11968 \$5 + assign $1\q_int$next[0:0]$12033 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11967 + update \q_int$next $0\q_int$next[0:0]$12032 end - connect \$9 $and$libresoc.v:174374$11957_Y - connect \$11 $or$libresoc.v:174375$11958_Y - connect \$13 $not$libresoc.v:174376$11959_Y - connect \$15 $or$libresoc.v:174377$11960_Y - connect \$1 $not$libresoc.v:174378$11961_Y - connect \$3 $and$libresoc.v:174379$11962_Y - connect \$5 $or$libresoc.v:174380$11963_Y - connect \$7 $not$libresoc.v:174381$11964_Y + connect \$9 $and$libresoc.v:183079$12022_Y + connect \$11 $or$libresoc.v:183080$12023_Y + connect \$13 $not$libresoc.v:183081$12024_Y + connect \$15 $or$libresoc.v:183082$12025_Y + connect \$1 $not$libresoc.v:183083$12026_Y + connect \$3 $and$libresoc.v:183084$12027_Y + connect \$5 $or$libresoc.v:183085$12028_Y + connect \$7 $not$libresoc.v:183086$12029_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:174400.1-174458.10" +attribute \src "libresoc.v:183105.1-183163.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:174401.7-174401.20" + attribute \src "libresoc.v:183106.7-183106.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174446.3-174454.6" - wire $0\q_int$next[0:0]$11981 - attribute \src "libresoc.v:174444.3-174445.27" + attribute \src "libresoc.v:183151.3-183159.6" + wire $0\q_int$next[0:0]$12046 + attribute \src "libresoc.v:183149.3-183150.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174446.3-174454.6" - wire $1\q_int$next[0:0]$11982 - attribute \src "libresoc.v:174423.7-174423.19" + attribute \src "libresoc.v:183151.3-183159.6" + wire $1\q_int$next[0:0]$12047 + attribute \src "libresoc.v:183128.7-183128.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174436.17-174436.96" - wire $and$libresoc.v:174436$11971_Y - attribute \src "libresoc.v:174441.17-174441.96" - wire $and$libresoc.v:174441$11976_Y - attribute \src "libresoc.v:174438.18-174438.94" - wire $not$libresoc.v:174438$11973_Y - attribute \src "libresoc.v:174440.17-174440.93" - wire $not$libresoc.v:174440$11975_Y - attribute \src "libresoc.v:174443.17-174443.93" - wire $not$libresoc.v:174443$11978_Y - attribute \src "libresoc.v:174437.18-174437.99" - wire $or$libresoc.v:174437$11972_Y - attribute \src "libresoc.v:174439.18-174439.100" - wire $or$libresoc.v:174439$11974_Y - attribute \src "libresoc.v:174442.17-174442.98" - wire $or$libresoc.v:174442$11977_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183141.17-183141.96" + wire $and$libresoc.v:183141$12036_Y + attribute \src "libresoc.v:183146.17-183146.96" + wire $and$libresoc.v:183146$12041_Y + attribute \src "libresoc.v:183143.18-183143.94" + wire $not$libresoc.v:183143$12038_Y + attribute \src "libresoc.v:183145.17-183145.93" + wire $not$libresoc.v:183145$12040_Y + attribute \src "libresoc.v:183148.17-183148.93" + wire $not$libresoc.v:183148$12043_Y + attribute \src "libresoc.v:183142.18-183142.99" + wire $or$libresoc.v:183142$12037_Y + attribute \src "libresoc.v:183144.18-183144.100" + wire $or$libresoc.v:183144$12039_Y + attribute \src "libresoc.v:183147.17-183147.98" + wire $or$libresoc.v:183147$12042_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174401.7-174401.15" + attribute \src "libresoc.v:183106.7-183106.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174436$11971 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183141$12036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364830,10 +379827,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174436$11971_Y + connect \Y $and$libresoc.v:183141$12036_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174441$11976 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183146$12041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364841,34 +379838,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174441$11976_Y + connect \Y $and$libresoc.v:183146$12041_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174438$11973 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183143$12038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:174438$11973_Y + connect \Y $not$libresoc.v:183143$12038_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174440$11975 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183145$12040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174440$11975_Y + connect \Y $not$libresoc.v:183145$12040_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174443$11978 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183148$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:174443$11978_Y + connect \Y $not$libresoc.v:183148$12043_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174437$11972 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183142$12037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364876,10 +379873,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:174437$11972_Y + connect \Y $or$libresoc.v:183142$12037_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174439$11974 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183144$12039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364887,10 +379884,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:174439$11974_Y + connect \Y $or$libresoc.v:183144$12039_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174442$11977 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183147$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -364898,39 +379895,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:174442$11977_Y + connect \Y $or$libresoc.v:183147$12042_Y end - attribute \src "libresoc.v:174401.7-174401.20" - process $proc$libresoc.v:174401$11983 + attribute \src "libresoc.v:183106.7-183106.20" + process $proc$libresoc.v:183106$12048 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174423.7-174423.19" - process $proc$libresoc.v:174423$11984 + attribute \src "libresoc.v:183128.7-183128.19" + process $proc$libresoc.v:183128$12049 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174444.3-174445.27" - process $proc$libresoc.v:174444$11979 + attribute \src "libresoc.v:183149.3-183150.27" + process $proc$libresoc.v:183149$12044 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174446.3-174454.6" - process $proc$libresoc.v:174446$11980 + attribute \src "libresoc.v:183151.3-183159.6" + process $proc$libresoc.v:183151$12045 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11981 $1\q_int$next[0:0]$11982 - attribute \src "libresoc.v:174447.5-174447.29" + assign $0\q_int$next[0:0]$12046 $1\q_int$next[0:0]$12047 + attribute \src "libresoc.v:183152.5-183152.29" switch \initial - attribute \src "libresoc.v:174447.9-174447.17" + attribute \src "libresoc.v:183152.9-183152.17" case 1'1 case end @@ -364939,150 +379936,150 @@ module \rok_l$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11982 1'0 + assign $1\q_int$next[0:0]$12047 1'0 case - assign $1\q_int$next[0:0]$11982 \$5 + assign $1\q_int$next[0:0]$12047 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11981 + update \q_int$next $0\q_int$next[0:0]$12046 end - connect \$9 $and$libresoc.v:174436$11971_Y - connect \$11 $or$libresoc.v:174437$11972_Y - connect \$13 $not$libresoc.v:174438$11973_Y - connect \$15 $or$libresoc.v:174439$11974_Y - connect \$1 $not$libresoc.v:174440$11975_Y - connect \$3 $and$libresoc.v:174441$11976_Y - connect \$5 $or$libresoc.v:174442$11977_Y - connect \$7 $not$libresoc.v:174443$11978_Y + connect \$9 $and$libresoc.v:183141$12036_Y + connect \$11 $or$libresoc.v:183142$12037_Y + connect \$13 $not$libresoc.v:183143$12038_Y + connect \$15 $or$libresoc.v:183144$12039_Y + connect \$1 $not$libresoc.v:183145$12040_Y + connect \$3 $and$libresoc.v:183146$12041_Y + connect \$5 $or$libresoc.v:183147$12042_Y + connect \$7 $not$libresoc.v:183148$12043_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:174462.1-174813.10" +attribute \src "libresoc.v:183167.1-183518.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:174731.3-174740.6" + attribute \src "libresoc.v:183436.3-183445.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:174663.3-174677.6" + attribute \src "libresoc.v:183368.3-183382.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:174463.7-174463.20" + attribute \src "libresoc.v:183168.7-183168.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174753.3-174786.6" - wire width 7 $0\mb$8[6:0]$12032 - attribute \src "libresoc.v:174787.3-174801.6" - wire width 7 $0\me$13[6:0]$12037 - attribute \src "libresoc.v:174688.3-174699.6" + attribute \src "libresoc.v:183458.3-183491.6" + wire width 7 $0\mb$8[6:0]$12097 + attribute \src "libresoc.v:183492.3-183506.6" + wire width 7 $0\me$13[6:0]$12102 + attribute \src "libresoc.v:183393.3-183404.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:174700.3-174711.6" + attribute \src "libresoc.v:183405.3-183416.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:174712.3-174730.6" + attribute \src "libresoc.v:183417.3-183435.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:174678.3-174687.6" + attribute \src "libresoc.v:183383.3-183392.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:174741.3-174752.6" + attribute \src "libresoc.v:183446.3-183457.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:174731.3-174740.6" + attribute \src "libresoc.v:183436.3-183445.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:174663.3-174677.6" + attribute \src "libresoc.v:183368.3-183382.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:174753.3-174786.6" - wire width 7 $1\mb$8[6:0]$12033 - attribute \src "libresoc.v:174787.3-174801.6" - wire width 7 $1\me$13[6:0]$12038 - attribute \src "libresoc.v:174688.3-174699.6" + attribute \src "libresoc.v:183458.3-183491.6" + wire width 7 $1\mb$8[6:0]$12098 + attribute \src "libresoc.v:183492.3-183506.6" + wire width 7 $1\me$13[6:0]$12103 + attribute \src "libresoc.v:183393.3-183404.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:174700.3-174711.6" + attribute \src "libresoc.v:183405.3-183416.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:174712.3-174730.6" + attribute \src "libresoc.v:183417.3-183435.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:174678.3-174687.6" + attribute \src "libresoc.v:183383.3-183392.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:174741.3-174752.6" + attribute \src "libresoc.v:183446.3-183457.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:174753.3-174786.6" - wire width 2 $2\mb$8[6:5]$12034 - attribute \src "libresoc.v:174753.3-174786.6" - wire width 2 $3\mb$8[6:5]$12035 - attribute \src "libresoc.v:174614.18-174614.118" - wire $and$libresoc.v:174614$11988_Y - attribute \src "libresoc.v:174616.18-174616.114" - wire $and$libresoc.v:174616$11990_Y - attribute \src "libresoc.v:174625.18-174625.113" - wire $and$libresoc.v:174625$11999_Y - attribute \src "libresoc.v:174627.18-174627.114" - wire $and$libresoc.v:174627$12001_Y - attribute \src "libresoc.v:174629.18-174629.114" - wire $and$libresoc.v:174629$12003_Y - attribute \src "libresoc.v:174630.18-174630.103" - wire width 64 $and$libresoc.v:174630$12004_Y - attribute \src "libresoc.v:174631.18-174631.106" - wire width 64 $and$libresoc.v:174631$12005_Y - attribute \src "libresoc.v:174633.18-174633.103" - wire width 64 $and$libresoc.v:174633$12007_Y - attribute \src "libresoc.v:174635.18-174635.105" - wire width 64 $and$libresoc.v:174635$12009_Y - attribute \src "libresoc.v:174638.18-174638.106" - wire width 64 $and$libresoc.v:174638$12012_Y - attribute \src "libresoc.v:174641.18-174641.105" - wire width 64 $and$libresoc.v:174641$12015_Y - attribute \src "libresoc.v:174643.17-174643.109" - wire $and$libresoc.v:174643$12017_Y - attribute \src "libresoc.v:174644.18-174644.104" - wire width 64 $and$libresoc.v:174644$12018_Y - attribute \src "libresoc.v:174648.18-174648.105" - wire width 64 $and$libresoc.v:174648$12022_Y - attribute \src "libresoc.v:174612.17-174612.98" - wire width 7 $extend$libresoc.v:174612$11985_Y - attribute \src "libresoc.v:174628.18-174628.122" - wire $gt$libresoc.v:174628$12002_Y - attribute \src "libresoc.v:174618.18-174618.111" - wire $le$libresoc.v:174618$11992_Y - attribute \src "libresoc.v:174620.18-174620.111" - wire $le$libresoc.v:174620$11994_Y - attribute \src "libresoc.v:174621.17-174621.117" - wire width 7 $neg$libresoc.v:174621$11995_Y - attribute \src "libresoc.v:174613.18-174613.103" - wire $not$libresoc.v:174613$11987_Y - attribute \src "libresoc.v:174615.18-174615.108" - wire $not$libresoc.v:174615$11989_Y - attribute \src "libresoc.v:174617.18-174617.105" - wire width 6 $not$libresoc.v:174617$11991_Y - attribute \src "libresoc.v:174623.18-174623.112" - wire width 64 $not$libresoc.v:174623$11997_Y - attribute \src "libresoc.v:174624.18-174624.109" - wire $not$libresoc.v:174624$11998_Y - attribute \src "libresoc.v:174632.17-174632.105" - wire $not$libresoc.v:174632$12006_Y - attribute \src "libresoc.v:174634.18-174634.102" - wire width 64 $not$libresoc.v:174634$12008_Y - attribute \src "libresoc.v:174640.18-174640.102" - wire width 64 $not$libresoc.v:174640$12014_Y - attribute \src "libresoc.v:174645.18-174645.100" - wire width 64 $not$libresoc.v:174645$12019_Y - attribute \src "libresoc.v:174647.18-174647.100" - wire width 64 $not$libresoc.v:174647$12021_Y - attribute \src "libresoc.v:174626.18-174626.115" - wire $or$libresoc.v:174626$12000_Y - attribute \src "libresoc.v:174636.18-174636.108" - wire width 64 $or$libresoc.v:174636$12010_Y - attribute \src "libresoc.v:174637.18-174637.103" - wire width 64 $or$libresoc.v:174637$12011_Y - attribute \src "libresoc.v:174639.18-174639.103" - wire width 64 $or$libresoc.v:174639$12013_Y - attribute \src "libresoc.v:174642.18-174642.108" - wire width 64 $or$libresoc.v:174642$12016_Y - attribute \src "libresoc.v:174646.18-174646.106" - wire width 64 $or$libresoc.v:174646$12020_Y - attribute \src "libresoc.v:174612.17-174612.98" - wire width 7 $pos$libresoc.v:174612$11986_Y - attribute \src "libresoc.v:174649.18-174649.102" - wire $reduce_or$libresoc.v:174649$12023_Y - attribute \src "libresoc.v:174619.18-174619.109" - wire width 8 $sub$libresoc.v:174619$11993_Y - attribute \src "libresoc.v:174622.18-174622.110" - wire width 8 $sub$libresoc.v:174622$11996_Y + attribute \src "libresoc.v:183458.3-183491.6" + wire width 2 $2\mb$8[6:5]$12099 + attribute \src "libresoc.v:183458.3-183491.6" + wire width 2 $3\mb$8[6:5]$12100 + attribute \src "libresoc.v:183319.18-183319.118" + wire $and$libresoc.v:183319$12053_Y + attribute \src "libresoc.v:183321.18-183321.114" + wire $and$libresoc.v:183321$12055_Y + attribute \src "libresoc.v:183330.18-183330.113" + wire $and$libresoc.v:183330$12064_Y + attribute \src "libresoc.v:183332.18-183332.114" + wire $and$libresoc.v:183332$12066_Y + attribute \src "libresoc.v:183334.18-183334.114" + wire $and$libresoc.v:183334$12068_Y + attribute \src "libresoc.v:183335.18-183335.103" + wire width 64 $and$libresoc.v:183335$12069_Y + attribute \src "libresoc.v:183336.18-183336.106" + wire width 64 $and$libresoc.v:183336$12070_Y + attribute \src "libresoc.v:183338.18-183338.103" + wire width 64 $and$libresoc.v:183338$12072_Y + attribute \src "libresoc.v:183340.18-183340.105" + wire width 64 $and$libresoc.v:183340$12074_Y + attribute \src "libresoc.v:183343.18-183343.106" + wire width 64 $and$libresoc.v:183343$12077_Y + attribute \src "libresoc.v:183346.18-183346.105" + wire width 64 $and$libresoc.v:183346$12080_Y + attribute \src "libresoc.v:183348.17-183348.109" + wire $and$libresoc.v:183348$12082_Y + attribute \src "libresoc.v:183349.18-183349.104" + wire width 64 $and$libresoc.v:183349$12083_Y + attribute \src "libresoc.v:183353.18-183353.105" + wire width 64 $and$libresoc.v:183353$12087_Y + attribute \src "libresoc.v:183317.17-183317.98" + wire width 7 $extend$libresoc.v:183317$12050_Y + attribute \src "libresoc.v:183333.18-183333.122" + wire $gt$libresoc.v:183333$12067_Y + attribute \src "libresoc.v:183323.18-183323.111" + wire $le$libresoc.v:183323$12057_Y + attribute \src "libresoc.v:183325.18-183325.111" + wire $le$libresoc.v:183325$12059_Y + attribute \src "libresoc.v:183326.17-183326.117" + wire width 7 $neg$libresoc.v:183326$12060_Y + attribute \src "libresoc.v:183318.18-183318.103" + wire $not$libresoc.v:183318$12052_Y + attribute \src "libresoc.v:183320.18-183320.108" + wire $not$libresoc.v:183320$12054_Y + attribute \src "libresoc.v:183322.18-183322.105" + wire width 6 $not$libresoc.v:183322$12056_Y + attribute \src "libresoc.v:183328.18-183328.112" + wire width 64 $not$libresoc.v:183328$12062_Y + attribute \src "libresoc.v:183329.18-183329.109" + wire $not$libresoc.v:183329$12063_Y + attribute \src "libresoc.v:183337.17-183337.105" + wire $not$libresoc.v:183337$12071_Y + attribute \src "libresoc.v:183339.18-183339.102" + wire width 64 $not$libresoc.v:183339$12073_Y + attribute \src "libresoc.v:183345.18-183345.102" + wire width 64 $not$libresoc.v:183345$12079_Y + attribute \src "libresoc.v:183350.18-183350.100" + wire width 64 $not$libresoc.v:183350$12084_Y + attribute \src "libresoc.v:183352.18-183352.100" + wire width 64 $not$libresoc.v:183352$12086_Y + attribute \src "libresoc.v:183331.18-183331.115" + wire $or$libresoc.v:183331$12065_Y + attribute \src "libresoc.v:183341.18-183341.108" + wire width 64 $or$libresoc.v:183341$12075_Y + attribute \src "libresoc.v:183342.18-183342.103" + wire width 64 $or$libresoc.v:183342$12076_Y + attribute \src "libresoc.v:183344.18-183344.103" + wire width 64 $or$libresoc.v:183344$12078_Y + attribute \src "libresoc.v:183347.18-183347.108" + wire width 64 $or$libresoc.v:183347$12081_Y + attribute \src "libresoc.v:183351.18-183351.106" + wire width 64 $or$libresoc.v:183351$12085_Y + attribute \src "libresoc.v:183317.17-183317.98" + wire width 7 $pos$libresoc.v:183317$12051_Y + attribute \src "libresoc.v:183354.18-183354.102" + wire $reduce_or$libresoc.v:183354$12088_Y + attribute \src "libresoc.v:183324.18-183324.109" + wire width 8 $sub$libresoc.v:183324$12058_Y + attribute \src "libresoc.v:183327.18-183327.110" + wire width 8 $sub$libresoc.v:183327$12061_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -365175,13 +380172,13 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:174463.7-174463.15" + attribute \src "libresoc.v:183168.7-183168.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 \left_mask_mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 \left_mask_shift attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" wire width 5 input 1 \mb @@ -365205,9 +380202,9 @@ module \rotator wire width 64 \repl32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" wire width 64 output 12 \result_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 \right_mask_mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 \right_mask_shift attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" wire input 8 \right_shift @@ -365232,7 +380229,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:174614$11988 + cell $and $and$libresoc.v:183319$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365240,10 +380237,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:174614$11988_Y + connect \Y $and$libresoc.v:183319$12053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:174616$11990 + cell $and $and$libresoc.v:183321$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365251,10 +380248,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:174616$11990_Y + connect \Y $and$libresoc.v:183321$12055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:174625$11999 + cell $and $and$libresoc.v:183330$12064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365262,10 +380259,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:174625$11999_Y + connect \Y $and$libresoc.v:183330$12064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:174627$12001 + cell $and $and$libresoc.v:183332$12066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365273,10 +380270,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:174627$12001_Y + connect \Y $and$libresoc.v:183332$12066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:174629$12003 + cell $and $and$libresoc.v:183334$12068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365284,10 +380281,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:174629$12003_Y + connect \Y $and$libresoc.v:183334$12068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:174630$12004 + cell $and $and$libresoc.v:183335$12069 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365295,10 +380292,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:174630$12004_Y + connect \Y $and$libresoc.v:183335$12069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:174631$12005 + cell $and $and$libresoc.v:183336$12070 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365306,10 +380303,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:174631$12005_Y + connect \Y $and$libresoc.v:183336$12070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:174633$12007 + cell $and $and$libresoc.v:183338$12072 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365317,10 +380314,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:174633$12007_Y + connect \Y $and$libresoc.v:183338$12072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:174635$12009 + cell $and $and$libresoc.v:183340$12074 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365328,10 +380325,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:174635$12009_Y + connect \Y $and$libresoc.v:183340$12074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:174638$12012 + cell $and $and$libresoc.v:183343$12077 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365339,10 +380336,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:174638$12012_Y + connect \Y $and$libresoc.v:183343$12077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:174641$12015 + cell $and $and$libresoc.v:183346$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365350,10 +380347,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:174641$12015_Y + connect \Y $and$libresoc.v:183346$12080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:174643$12017 + cell $and $and$libresoc.v:183348$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365361,10 +380358,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:174643$12017_Y + connect \Y $and$libresoc.v:183348$12082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:174644$12018 + cell $and $and$libresoc.v:183349$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365372,10 +380369,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:174644$12018_Y + connect \Y $and$libresoc.v:183349$12083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:174648$12022 + cell $and $and$libresoc.v:183353$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365383,18 +380380,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:174648$12022_Y + connect \Y $and$libresoc.v:183353$12087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:174612$11985 + cell $pos $extend$libresoc.v:183317$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:174612$11985_Y + connect \Y $extend$libresoc.v:183317$12050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:174628$12002 + cell $gt $gt$libresoc.v:183333$12067 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365402,10 +380399,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:174628$12002_Y + connect \Y $gt$libresoc.v:183333$12067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:174618$11992 + cell $le $le$libresoc.v:183323$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -365413,10 +380410,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:174618$11992_Y + connect \Y $le$libresoc.v:183323$12057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:174620$11994 + cell $le $le$libresoc.v:183325$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -365424,98 +380421,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:174620$11994_Y + connect \Y $le$libresoc.v:183325$12059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:174621$11995 + cell $neg $neg$libresoc.v:183326$12060 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:174621$11995_Y + connect \Y $neg$libresoc.v:183326$12060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:174613$11987 + cell $not $not$libresoc.v:183318$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:174613$11987_Y + connect \Y $not$libresoc.v:183318$12052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:174615$11989 + cell $not $not$libresoc.v:183320$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:174615$11989_Y + connect \Y $not$libresoc.v:183320$12054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:174617$11991 + cell $not $not$libresoc.v:183322$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:174617$11991_Y + connect \Y $not$libresoc.v:183322$12056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:174623$11997 + cell $not $not$libresoc.v:183328$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:174623$11997_Y + connect \Y $not$libresoc.v:183328$12062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:174624$11998 + cell $not $not$libresoc.v:183329$12063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:174624$11998_Y + connect \Y $not$libresoc.v:183329$12063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:174632$12006 + cell $not $not$libresoc.v:183337$12071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:174632$12006_Y + connect \Y $not$libresoc.v:183337$12071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:174634$12008 + cell $not $not$libresoc.v:183339$12073 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:174634$12008_Y + connect \Y $not$libresoc.v:183339$12073_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:174640$12014 + cell $not $not$libresoc.v:183345$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:174640$12014_Y + connect \Y $not$libresoc.v:183345$12079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:174645$12019 + cell $not $not$libresoc.v:183350$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:174645$12019_Y + connect \Y $not$libresoc.v:183350$12084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:174647$12021 + cell $not $not$libresoc.v:183352$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:174647$12021_Y + connect \Y $not$libresoc.v:183352$12086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:174626$12000 + cell $or $or$libresoc.v:183331$12065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365523,10 +380520,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:174626$12000_Y + connect \Y $or$libresoc.v:183331$12065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:174636$12010 + cell $or $or$libresoc.v:183341$12075 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365534,10 +380531,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:174636$12010_Y + connect \Y $or$libresoc.v:183341$12075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:174637$12011 + cell $or $or$libresoc.v:183342$12076 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365545,10 +380542,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:174637$12011_Y + connect \Y $or$libresoc.v:183342$12076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:174639$12013 + cell $or $or$libresoc.v:183344$12078 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365556,10 +380553,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:174639$12013_Y + connect \Y $or$libresoc.v:183344$12078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:174642$12016 + cell $or $or$libresoc.v:183347$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365567,10 +380564,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:174642$12016_Y + connect \Y $or$libresoc.v:183347$12081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:174646$12020 + cell $or $or$libresoc.v:183351$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -365578,26 +380575,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:174646$12020_Y + connect \Y $or$libresoc.v:183351$12085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:174612$11986 + cell $pos $pos$libresoc.v:183317$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:174612$11985_Y - connect \Y $pos$libresoc.v:174612$11986_Y + connect \A $extend$libresoc.v:183317$12050_Y + connect \Y $pos$libresoc.v:183317$12051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:174649$12023 + cell $reduce_or $reduce_or$libresoc.v:183354$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:174649$12023_Y + connect \Y $reduce_or$libresoc.v:183354$12088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:174619$11993 + cell $sub $sub$libresoc.v:183324$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -365605,10 +380602,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:174619$11993_Y + connect \Y $sub$libresoc.v:183324$12058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:174622$11996 + cell $sub $sub$libresoc.v:183327$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365616,42 +380613,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:174622$11996_Y + connect \Y $sub$libresoc.v:183327$12061_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:174650.13-174653.4" + attribute \src "libresoc.v:183355.13-183358.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:174654.14-174657.4" + attribute \src "libresoc.v:183359.14-183362.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:174658.8-174662.4" + attribute \src "libresoc.v:183363.8-183367.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:174463.7-174463.20" - process $proc$libresoc.v:174463$12039 + attribute \src "libresoc.v:183168.7-183168.20" + process $proc$libresoc.v:183168$12104 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174663.3-174677.6" - process $proc$libresoc.v:174663$12024 + attribute \src "libresoc.v:183368.3-183382.6" + process $proc$libresoc.v:183368$12089 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:174664.5-174664.29" + attribute \src "libresoc.v:183369.5-183369.29" switch \initial - attribute \src "libresoc.v:174664.9-174664.17" + attribute \src "libresoc.v:183369.9-183369.17" case 1'1 case end @@ -365673,14 +380670,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:174678.3-174687.6" - process $proc$libresoc.v:174678$12025 + attribute \src "libresoc.v:183383.3-183392.6" + process $proc$libresoc.v:183383$12090 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:174679.5-174679.29" + attribute \src "libresoc.v:183384.5-183384.29" switch \initial - attribute \src "libresoc.v:174679.9-174679.17" + attribute \src "libresoc.v:183384.9-183384.17" case 1'1 case end @@ -365696,13 +380693,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:174688.3-174699.6" - process $proc$libresoc.v:174688$12026 + attribute \src "libresoc.v:183393.3-183404.6" + process $proc$libresoc.v:183393$12091 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:174689.5-174689.29" + attribute \src "libresoc.v:183394.5-183394.29" switch \initial - attribute \src "libresoc.v:174689.9-174689.17" + attribute \src "libresoc.v:183394.9-183394.17" case 1'1 case end @@ -365720,13 +380717,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:174700.3-174711.6" - process $proc$libresoc.v:174700$12027 + attribute \src "libresoc.v:183405.3-183416.6" + process $proc$libresoc.v:183405$12092 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:174701.5-174701.29" + attribute \src "libresoc.v:183406.5-183406.29" switch \initial - attribute \src "libresoc.v:174701.9-174701.17" + attribute \src "libresoc.v:183406.9-183406.17" case 1'1 case end @@ -365744,14 +380741,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:174712.3-174730.6" - process $proc$libresoc.v:174712$12028 + attribute \src "libresoc.v:183417.3-183435.6" + process $proc$libresoc.v:183417$12093 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:174713.5-174713.29" + attribute \src "libresoc.v:183418.5-183418.29" switch \initial - attribute \src "libresoc.v:174713.9-174713.17" + attribute \src "libresoc.v:183418.9-183418.17" case 1'1 case end @@ -365779,14 +380776,14 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:174731.3-174740.6" - process $proc$libresoc.v:174731$12029 + attribute \src "libresoc.v:183436.3-183445.6" + process $proc$libresoc.v:183436$12094 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:174732.5-174732.29" + attribute \src "libresoc.v:183437.5-183437.29" switch \initial - attribute \src "libresoc.v:174732.9-174732.17" + attribute \src "libresoc.v:183437.9-183437.17" case 1'1 case end @@ -365802,13 +380799,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:174741.3-174752.6" - process $proc$libresoc.v:174741$12030 + attribute \src "libresoc.v:183446.3-183457.6" + process $proc$libresoc.v:183446$12095 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:174742.5-174742.29" + attribute \src "libresoc.v:183447.5-183447.29" switch \initial - attribute \src "libresoc.v:174742.9-174742.17" + attribute \src "libresoc.v:183447.9-183447.17" case 1'1 case end @@ -365826,13 +380823,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:174753.3-174786.6" - process $proc$libresoc.v:174753$12031 + attribute \src "libresoc.v:183458.3-183491.6" + process $proc$libresoc.v:183458$12096 assign { } { } - assign $0\mb$8[6:0]$12032 $1\mb$8[6:0]$12033 - attribute \src "libresoc.v:174754.5-174754.29" + assign $0\mb$8[6:0]$12097 $1\mb$8[6:0]$12098 + attribute \src "libresoc.v:183459.5-183459.29" switch \initial - attribute \src "libresoc.v:174754.9-174754.17" + attribute \src "libresoc.v:183459.9-183459.17" case 1'1 case end @@ -365841,48 +380838,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$12033 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12033 [6:5] $2\mb$8[6:5]$12034 + assign $1\mb$8[6:0]$12098 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12098 [6:5] $2\mb$8[6:5]$12099 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$12034 2'01 + assign $2\mb$8[6:5]$12099 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$12034 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12099 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$12033 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12033 [6:5] $3\mb$8[6:5]$12035 + assign $1\mb$8[6:0]$12098 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12098 [6:5] $3\mb$8[6:5]$12100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$12035 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12100 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$12035 \sh [6:5] + assign $3\mb$8[6:5]$12100 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$12033 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12098 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$12032 + update \mb$8 $0\mb$8[6:0]$12097 end - attribute \src "libresoc.v:174787.3-174801.6" - process $proc$libresoc.v:174787$12036 + attribute \src "libresoc.v:183492.3-183506.6" + process $proc$libresoc.v:183492$12101 assign { } { } - assign $0\me$13[6:0]$12037 $1\me$13[6:0]$12038 - attribute \src "libresoc.v:174788.5-174788.29" + assign $0\me$13[6:0]$12102 $1\me$13[6:0]$12103 + attribute \src "libresoc.v:183493.5-183493.29" switch \initial - attribute \src "libresoc.v:174788.9-174788.17" + attribute \src "libresoc.v:183493.9-183493.17" case 1'1 case end @@ -365891,57 +380888,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$12038 { 2'01 \me } + assign $1\me$13[6:0]$12103 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$12038 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12038 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12037 - end - connect \$9 $pos$libresoc.v:174612$11986_Y - connect \$11 $not$libresoc.v:174613$11987_Y - connect \$14 $and$libresoc.v:174614$11988_Y - connect \$16 $not$libresoc.v:174615$11989_Y - connect \$18 $and$libresoc.v:174616$11990_Y - connect \$20 $not$libresoc.v:174617$11991_Y - connect \$22 $le$libresoc.v:174618$11992_Y - connect \$25 $sub$libresoc.v:174619$11993_Y - connect \$27 $le$libresoc.v:174620$11994_Y - connect \$2 $neg$libresoc.v:174621$11995_Y - connect \$30 $sub$libresoc.v:174622$11996_Y - connect \$32 $not$libresoc.v:174623$11997_Y - connect \$34 $not$libresoc.v:174624$11998_Y - connect \$36 $and$libresoc.v:174625$11999_Y - connect \$38 $or$libresoc.v:174626$12000_Y - connect \$40 $and$libresoc.v:174627$12001_Y - connect \$42 $gt$libresoc.v:174628$12002_Y - connect \$44 $and$libresoc.v:174629$12003_Y - connect \$46 $and$libresoc.v:174630$12004_Y - connect \$48 $and$libresoc.v:174631$12005_Y - connect \$4 $not$libresoc.v:174632$12006_Y - connect \$51 $and$libresoc.v:174633$12007_Y - connect \$50 $not$libresoc.v:174634$12008_Y - connect \$54 $and$libresoc.v:174635$12009_Y - connect \$56 $or$libresoc.v:174636$12010_Y - connect \$58 $or$libresoc.v:174637$12011_Y - connect \$60 $and$libresoc.v:174638$12012_Y - connect \$63 $or$libresoc.v:174639$12013_Y - connect \$62 $not$libresoc.v:174640$12014_Y - connect \$66 $and$libresoc.v:174641$12015_Y - connect \$68 $or$libresoc.v:174642$12016_Y - connect \$6 $and$libresoc.v:174643$12017_Y - connect \$70 $and$libresoc.v:174644$12018_Y - connect \$72 $not$libresoc.v:174645$12019_Y - connect \$74 $or$libresoc.v:174646$12020_Y - connect \$77 $not$libresoc.v:174647$12021_Y - connect \$79 $and$libresoc.v:174648$12022_Y - connect \$76 $reduce_or$libresoc.v:174649$12023_Y + assign $1\me$13[6:0]$12103 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12103 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12102 + end + connect \$9 $pos$libresoc.v:183317$12051_Y + connect \$11 $not$libresoc.v:183318$12052_Y + connect \$14 $and$libresoc.v:183319$12053_Y + connect \$16 $not$libresoc.v:183320$12054_Y + connect \$18 $and$libresoc.v:183321$12055_Y + connect \$20 $not$libresoc.v:183322$12056_Y + connect \$22 $le$libresoc.v:183323$12057_Y + connect \$25 $sub$libresoc.v:183324$12058_Y + connect \$27 $le$libresoc.v:183325$12059_Y + connect \$2 $neg$libresoc.v:183326$12060_Y + connect \$30 $sub$libresoc.v:183327$12061_Y + connect \$32 $not$libresoc.v:183328$12062_Y + connect \$34 $not$libresoc.v:183329$12063_Y + connect \$36 $and$libresoc.v:183330$12064_Y + connect \$38 $or$libresoc.v:183331$12065_Y + connect \$40 $and$libresoc.v:183332$12066_Y + connect \$42 $gt$libresoc.v:183333$12067_Y + connect \$44 $and$libresoc.v:183334$12068_Y + connect \$46 $and$libresoc.v:183335$12069_Y + connect \$48 $and$libresoc.v:183336$12070_Y + connect \$4 $not$libresoc.v:183337$12071_Y + connect \$51 $and$libresoc.v:183338$12072_Y + connect \$50 $not$libresoc.v:183339$12073_Y + connect \$54 $and$libresoc.v:183340$12074_Y + connect \$56 $or$libresoc.v:183341$12075_Y + connect \$58 $or$libresoc.v:183342$12076_Y + connect \$60 $and$libresoc.v:183343$12077_Y + connect \$63 $or$libresoc.v:183344$12078_Y + connect \$62 $not$libresoc.v:183345$12079_Y + connect \$66 $and$libresoc.v:183346$12080_Y + connect \$68 $or$libresoc.v:183347$12081_Y + connect \$6 $and$libresoc.v:183348$12082_Y + connect \$70 $and$libresoc.v:183349$12083_Y + connect \$72 $not$libresoc.v:183350$12084_Y + connect \$74 $or$libresoc.v:183351$12085_Y + connect \$77 $not$libresoc.v:183352$12086_Y + connect \$79 $and$libresoc.v:183353$12087_Y + connect \$76 $reduce_or$libresoc.v:183354$12088_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -365954,15 +380951,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:174817.1-174831.10" +attribute \src "libresoc.v:183522.1-183536.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:174829.17-174829.32" - wire width 128 $shr$libresoc.v:174829$12041_Y - attribute \src "libresoc.v:174828.17-174828.100" - wire width 8 $sub$libresoc.v:174828$12040_Y + attribute \src "libresoc.v:183534.17-183534.32" + wire width 128 $shr$libresoc.v:183534$12106_Y + attribute \src "libresoc.v:183533.17-183533.100" + wire width 8 $sub$libresoc.v:183533$12105_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -365973,8 +380970,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:174829.17-174829.32" - cell $shr $shr$libresoc.v:174829$12041 + attribute \src "libresoc.v:183534.17-183534.32" + cell $shr $shr$libresoc.v:183534$12106 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -365982,10 +380979,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:174829$12041_Y + connect \Y $shr$libresoc.v:183534$12106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:174828$12040 + cell $sub $sub$libresoc.v:183533$12105 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -365993,81 +380990,81 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:174828$12040_Y + connect \Y $sub$libresoc.v:183533$12105_Y end - connect \$2 $sub$libresoc.v:174828$12040_Y - connect \$1 $shr$libresoc.v:174829$12041_Y [63:0] + connect \$2 $sub$libresoc.v:183533$12105_Y + connect \$1 $shr$libresoc.v:183534$12106_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:174835.1-174893.10" +attribute \src "libresoc.v:183540.1-183598.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:174836.7-174836.20" + attribute \src "libresoc.v:183541.7-183541.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174881.3-174889.6" - wire $0\q_int$next[0:0]$12052 - attribute \src "libresoc.v:174879.3-174880.27" + attribute \src "libresoc.v:183586.3-183594.6" + wire $0\q_int$next[0:0]$12117 + attribute \src "libresoc.v:183584.3-183585.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174881.3-174889.6" - wire $1\q_int$next[0:0]$12053 - attribute \src "libresoc.v:174858.7-174858.19" + attribute \src "libresoc.v:183586.3-183594.6" + wire $1\q_int$next[0:0]$12118 + attribute \src "libresoc.v:183563.7-183563.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174871.17-174871.96" - wire $and$libresoc.v:174871$12042_Y - attribute \src "libresoc.v:174876.17-174876.96" - wire $and$libresoc.v:174876$12047_Y - attribute \src "libresoc.v:174873.18-174873.93" - wire $not$libresoc.v:174873$12044_Y - attribute \src "libresoc.v:174875.17-174875.92" - wire $not$libresoc.v:174875$12046_Y - attribute \src "libresoc.v:174878.17-174878.92" - wire $not$libresoc.v:174878$12049_Y - attribute \src "libresoc.v:174872.18-174872.98" - wire $or$libresoc.v:174872$12043_Y - attribute \src "libresoc.v:174874.18-174874.99" - wire $or$libresoc.v:174874$12045_Y - attribute \src "libresoc.v:174877.17-174877.97" - wire $or$libresoc.v:174877$12048_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183576.17-183576.96" + wire $and$libresoc.v:183576$12107_Y + attribute \src "libresoc.v:183581.17-183581.96" + wire $and$libresoc.v:183581$12112_Y + attribute \src "libresoc.v:183578.18-183578.93" + wire $not$libresoc.v:183578$12109_Y + attribute \src "libresoc.v:183580.17-183580.92" + wire $not$libresoc.v:183580$12111_Y + attribute \src "libresoc.v:183583.17-183583.92" + wire $not$libresoc.v:183583$12114_Y + attribute \src "libresoc.v:183577.18-183577.98" + wire $or$libresoc.v:183577$12108_Y + attribute \src "libresoc.v:183579.18-183579.99" + wire $or$libresoc.v:183579$12110_Y + attribute \src "libresoc.v:183582.17-183582.97" + wire $or$libresoc.v:183582$12113_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174836.7-174836.15" + attribute \src "libresoc.v:183541.7-183541.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174871$12042 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183576$12107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366075,10 +381072,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174871$12042_Y + connect \Y $and$libresoc.v:183576$12107_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174876$12047 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183581$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366086,34 +381083,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174876$12047_Y + connect \Y $and$libresoc.v:183581$12112_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174873$12044 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183578$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:174873$12044_Y + connect \Y $not$libresoc.v:183578$12109_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174875$12046 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183580$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:174875$12046_Y + connect \Y $not$libresoc.v:183580$12111_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174878$12049 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183583$12114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:174878$12049_Y + connect \Y $not$libresoc.v:183583$12114_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174872$12043 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183577$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366121,10 +381118,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:174872$12043_Y + connect \Y $or$libresoc.v:183577$12108_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174874$12045 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183579$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366132,10 +381129,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:174874$12045_Y + connect \Y $or$libresoc.v:183579$12110_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174877$12048 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183582$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366143,39 +381140,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:174877$12048_Y + connect \Y $or$libresoc.v:183582$12113_Y end - attribute \src "libresoc.v:174836.7-174836.20" - process $proc$libresoc.v:174836$12054 + attribute \src "libresoc.v:183541.7-183541.20" + process $proc$libresoc.v:183541$12119 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174858.7-174858.19" - process $proc$libresoc.v:174858$12055 + attribute \src "libresoc.v:183563.7-183563.19" + process $proc$libresoc.v:183563$12120 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174879.3-174880.27" - process $proc$libresoc.v:174879$12050 + attribute \src "libresoc.v:183584.3-183585.27" + process $proc$libresoc.v:183584$12115 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174881.3-174889.6" - process $proc$libresoc.v:174881$12051 + attribute \src "libresoc.v:183586.3-183594.6" + process $proc$libresoc.v:183586$12116 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12052 $1\q_int$next[0:0]$12053 - attribute \src "libresoc.v:174882.5-174882.29" + assign $0\q_int$next[0:0]$12117 $1\q_int$next[0:0]$12118 + attribute \src "libresoc.v:183587.5-183587.29" switch \initial - attribute \src "libresoc.v:174882.9-174882.17" + attribute \src "libresoc.v:183587.9-183587.17" case 1'1 case end @@ -366184,94 +381181,94 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12053 1'0 + assign $1\q_int$next[0:0]$12118 1'0 case - assign $1\q_int$next[0:0]$12053 \$5 + assign $1\q_int$next[0:0]$12118 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12052 + update \q_int$next $0\q_int$next[0:0]$12117 end - connect \$9 $and$libresoc.v:174871$12042_Y - connect \$11 $or$libresoc.v:174872$12043_Y - connect \$13 $not$libresoc.v:174873$12044_Y - connect \$15 $or$libresoc.v:174874$12045_Y - connect \$1 $not$libresoc.v:174875$12046_Y - connect \$3 $and$libresoc.v:174876$12047_Y - connect \$5 $or$libresoc.v:174877$12048_Y - connect \$7 $not$libresoc.v:174878$12049_Y + connect \$9 $and$libresoc.v:183576$12107_Y + connect \$11 $or$libresoc.v:183577$12108_Y + connect \$13 $not$libresoc.v:183578$12109_Y + connect \$15 $or$libresoc.v:183579$12110_Y + connect \$1 $not$libresoc.v:183580$12111_Y + connect \$3 $and$libresoc.v:183581$12112_Y + connect \$5 $or$libresoc.v:183582$12113_Y + connect \$7 $not$libresoc.v:183583$12114_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:174897.1-174955.10" +attribute \src "libresoc.v:183602.1-183660.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:174898.7-174898.20" + attribute \src "libresoc.v:183603.7-183603.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174943.3-174951.6" - wire $0\q_int$next[0:0]$12066 - attribute \src "libresoc.v:174941.3-174942.27" + attribute \src "libresoc.v:183648.3-183656.6" + wire $0\q_int$next[0:0]$12131 + attribute \src "libresoc.v:183646.3-183647.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:174943.3-174951.6" - wire $1\q_int$next[0:0]$12067 - attribute \src "libresoc.v:174920.7-174920.19" + attribute \src "libresoc.v:183648.3-183656.6" + wire $1\q_int$next[0:0]$12132 + attribute \src "libresoc.v:183625.7-183625.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174933.17-174933.96" - wire $and$libresoc.v:174933$12056_Y - attribute \src "libresoc.v:174938.17-174938.96" - wire $and$libresoc.v:174938$12061_Y - attribute \src "libresoc.v:174935.18-174935.93" - wire $not$libresoc.v:174935$12058_Y - attribute \src "libresoc.v:174937.17-174937.92" - wire $not$libresoc.v:174937$12060_Y - attribute \src "libresoc.v:174940.17-174940.92" - wire $not$libresoc.v:174940$12063_Y - attribute \src "libresoc.v:174934.18-174934.98" - wire $or$libresoc.v:174934$12057_Y - attribute \src "libresoc.v:174936.18-174936.99" - wire $or$libresoc.v:174936$12059_Y - attribute \src "libresoc.v:174939.17-174939.97" - wire $or$libresoc.v:174939$12062_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183638.17-183638.96" + wire $and$libresoc.v:183638$12121_Y + attribute \src "libresoc.v:183643.17-183643.96" + wire $and$libresoc.v:183643$12126_Y + attribute \src "libresoc.v:183640.18-183640.93" + wire $not$libresoc.v:183640$12123_Y + attribute \src "libresoc.v:183642.17-183642.92" + wire $not$libresoc.v:183642$12125_Y + attribute \src "libresoc.v:183645.17-183645.92" + wire $not$libresoc.v:183645$12128_Y + attribute \src "libresoc.v:183639.18-183639.98" + wire $or$libresoc.v:183639$12122_Y + attribute \src "libresoc.v:183641.18-183641.99" + wire $or$libresoc.v:183641$12124_Y + attribute \src "libresoc.v:183644.17-183644.97" + wire $or$libresoc.v:183644$12127_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174898.7-174898.15" + attribute \src "libresoc.v:183603.7-183603.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174933$12056 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183638$12121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366279,10 +381276,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174933$12056_Y + connect \Y $and$libresoc.v:183638$12121_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174938$12061 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183643$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366290,34 +381287,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:174938$12061_Y + connect \Y $and$libresoc.v:183643$12126_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174935$12058 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183640$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:174935$12058_Y + connect \Y $not$libresoc.v:183640$12123_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174937$12060 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183642$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:174937$12060_Y + connect \Y $not$libresoc.v:183642$12125_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174940$12063 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183645$12128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:174940$12063_Y + connect \Y $not$libresoc.v:183645$12128_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174934$12057 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183639$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366325,10 +381322,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:174934$12057_Y + connect \Y $or$libresoc.v:183639$12122_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174936$12059 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183641$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366336,10 +381333,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:174936$12059_Y + connect \Y $or$libresoc.v:183641$12124_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174939$12062 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183644$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366347,39 +381344,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:174939$12062_Y + connect \Y $or$libresoc.v:183644$12127_Y end - attribute \src "libresoc.v:174898.7-174898.20" - process $proc$libresoc.v:174898$12068 + attribute \src "libresoc.v:183603.7-183603.20" + process $proc$libresoc.v:183603$12133 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174920.7-174920.19" - process $proc$libresoc.v:174920$12069 + attribute \src "libresoc.v:183625.7-183625.19" + process $proc$libresoc.v:183625$12134 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:174941.3-174942.27" - process $proc$libresoc.v:174941$12064 + attribute \src "libresoc.v:183646.3-183647.27" + process $proc$libresoc.v:183646$12129 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:174943.3-174951.6" - process $proc$libresoc.v:174943$12065 + attribute \src "libresoc.v:183648.3-183656.6" + process $proc$libresoc.v:183648$12130 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12066 $1\q_int$next[0:0]$12067 - attribute \src "libresoc.v:174944.5-174944.29" + assign $0\q_int$next[0:0]$12131 $1\q_int$next[0:0]$12132 + attribute \src "libresoc.v:183649.5-183649.29" switch \initial - attribute \src "libresoc.v:174944.9-174944.17" + attribute \src "libresoc.v:183649.9-183649.17" case 1'1 case end @@ -366388,94 +381385,94 @@ module \rst_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12067 1'0 + assign $1\q_int$next[0:0]$12132 1'0 case - assign $1\q_int$next[0:0]$12067 \$5 + assign $1\q_int$next[0:0]$12132 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12066 + update \q_int$next $0\q_int$next[0:0]$12131 end - connect \$9 $and$libresoc.v:174933$12056_Y - connect \$11 $or$libresoc.v:174934$12057_Y - connect \$13 $not$libresoc.v:174935$12058_Y - connect \$15 $or$libresoc.v:174936$12059_Y - connect \$1 $not$libresoc.v:174937$12060_Y - connect \$3 $and$libresoc.v:174938$12061_Y - connect \$5 $or$libresoc.v:174939$12062_Y - connect \$7 $not$libresoc.v:174940$12063_Y + connect \$9 $and$libresoc.v:183638$12121_Y + connect \$11 $or$libresoc.v:183639$12122_Y + connect \$13 $not$libresoc.v:183640$12123_Y + connect \$15 $or$libresoc.v:183641$12124_Y + connect \$1 $not$libresoc.v:183642$12125_Y + connect \$3 $and$libresoc.v:183643$12126_Y + connect \$5 $or$libresoc.v:183644$12127_Y + connect \$7 $not$libresoc.v:183645$12128_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:174959.1-175017.10" +attribute \src "libresoc.v:183664.1-183722.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:174960.7-174960.20" + attribute \src "libresoc.v:183665.7-183665.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175005.3-175013.6" - wire $0\q_int$next[0:0]$12080 - attribute \src "libresoc.v:175003.3-175004.27" + attribute \src "libresoc.v:183710.3-183718.6" + wire $0\q_int$next[0:0]$12145 + attribute \src "libresoc.v:183708.3-183709.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:175005.3-175013.6" - wire $1\q_int$next[0:0]$12081 - attribute \src "libresoc.v:174982.7-174982.19" + attribute \src "libresoc.v:183710.3-183718.6" + wire $1\q_int$next[0:0]$12146 + attribute \src "libresoc.v:183687.7-183687.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:174995.17-174995.96" - wire $and$libresoc.v:174995$12070_Y - attribute \src "libresoc.v:175000.17-175000.96" - wire $and$libresoc.v:175000$12075_Y - attribute \src "libresoc.v:174997.18-174997.93" - wire $not$libresoc.v:174997$12072_Y - attribute \src "libresoc.v:174999.17-174999.92" - wire $not$libresoc.v:174999$12074_Y - attribute \src "libresoc.v:175002.17-175002.92" - wire $not$libresoc.v:175002$12077_Y - attribute \src "libresoc.v:174996.18-174996.98" - wire $or$libresoc.v:174996$12071_Y - attribute \src "libresoc.v:174998.18-174998.99" - wire $or$libresoc.v:174998$12073_Y - attribute \src "libresoc.v:175001.17-175001.97" - wire $or$libresoc.v:175001$12076_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183700.17-183700.96" + wire $and$libresoc.v:183700$12135_Y + attribute \src "libresoc.v:183705.17-183705.96" + wire $and$libresoc.v:183705$12140_Y + attribute \src "libresoc.v:183702.18-183702.93" + wire $not$libresoc.v:183702$12137_Y + attribute \src "libresoc.v:183704.17-183704.92" + wire $not$libresoc.v:183704$12139_Y + attribute \src "libresoc.v:183707.17-183707.92" + wire $not$libresoc.v:183707$12142_Y + attribute \src "libresoc.v:183701.18-183701.98" + wire $or$libresoc.v:183701$12136_Y + attribute \src "libresoc.v:183703.18-183703.99" + wire $or$libresoc.v:183703$12138_Y + attribute \src "libresoc.v:183706.17-183706.97" + wire $or$libresoc.v:183706$12141_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:174960.7-174960.15" + attribute \src "libresoc.v:183665.7-183665.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174995$12070 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183700$12135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366483,10 +381480,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:174995$12070_Y + connect \Y $and$libresoc.v:183700$12135_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175000$12075 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183705$12140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366494,34 +381491,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:175000$12075_Y + connect \Y $and$libresoc.v:183705$12140_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174997$12072 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183702$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:174997$12072_Y + connect \Y $not$libresoc.v:183702$12137_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174999$12074 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183704$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:174999$12074_Y + connect \Y $not$libresoc.v:183704$12139_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175002$12077 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183707$12142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175002$12077_Y + connect \Y $not$libresoc.v:183707$12142_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174996$12071 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183701$12136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366529,10 +381526,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:174996$12071_Y + connect \Y $or$libresoc.v:183701$12136_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174998$12073 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183703$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366540,10 +381537,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:174998$12073_Y + connect \Y $or$libresoc.v:183703$12138_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175001$12076 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183706$12141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366551,39 +381548,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:175001$12076_Y + connect \Y $or$libresoc.v:183706$12141_Y end - attribute \src "libresoc.v:174960.7-174960.20" - process $proc$libresoc.v:174960$12082 + attribute \src "libresoc.v:183665.7-183665.20" + process $proc$libresoc.v:183665$12147 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174982.7-174982.19" - process $proc$libresoc.v:174982$12083 + attribute \src "libresoc.v:183687.7-183687.19" + process $proc$libresoc.v:183687$12148 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:175003.3-175004.27" - process $proc$libresoc.v:175003$12078 + attribute \src "libresoc.v:183708.3-183709.27" + process $proc$libresoc.v:183708$12143 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:175005.3-175013.6" - process $proc$libresoc.v:175005$12079 + attribute \src "libresoc.v:183710.3-183718.6" + process $proc$libresoc.v:183710$12144 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12080 $1\q_int$next[0:0]$12081 - attribute \src "libresoc.v:175006.5-175006.29" + assign $0\q_int$next[0:0]$12145 $1\q_int$next[0:0]$12146 + attribute \src "libresoc.v:183711.5-183711.29" switch \initial - attribute \src "libresoc.v:175006.9-175006.17" + attribute \src "libresoc.v:183711.9-183711.17" case 1'1 case end @@ -366592,94 +381589,94 @@ module \rst_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12081 1'0 + assign $1\q_int$next[0:0]$12146 1'0 case - assign $1\q_int$next[0:0]$12081 \$5 + assign $1\q_int$next[0:0]$12146 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12080 + update \q_int$next $0\q_int$next[0:0]$12145 end - connect \$9 $and$libresoc.v:174995$12070_Y - connect \$11 $or$libresoc.v:174996$12071_Y - connect \$13 $not$libresoc.v:174997$12072_Y - connect \$15 $or$libresoc.v:174998$12073_Y - connect \$1 $not$libresoc.v:174999$12074_Y - connect \$3 $and$libresoc.v:175000$12075_Y - connect \$5 $or$libresoc.v:175001$12076_Y - connect \$7 $not$libresoc.v:175002$12077_Y + connect \$9 $and$libresoc.v:183700$12135_Y + connect \$11 $or$libresoc.v:183701$12136_Y + connect \$13 $not$libresoc.v:183702$12137_Y + connect \$15 $or$libresoc.v:183703$12138_Y + connect \$1 $not$libresoc.v:183704$12139_Y + connect \$3 $and$libresoc.v:183705$12140_Y + connect \$5 $or$libresoc.v:183706$12141_Y + connect \$7 $not$libresoc.v:183707$12142_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:175021.1-175079.10" +attribute \src "libresoc.v:183726.1-183784.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:175022.7-175022.20" + attribute \src "libresoc.v:183727.7-183727.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175067.3-175075.6" - wire $0\q_int$next[0:0]$12094 - attribute \src "libresoc.v:175065.3-175066.27" + attribute \src "libresoc.v:183772.3-183780.6" + wire $0\q_int$next[0:0]$12159 + attribute \src "libresoc.v:183770.3-183771.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:175067.3-175075.6" - wire $1\q_int$next[0:0]$12095 - attribute \src "libresoc.v:175044.7-175044.19" + attribute \src "libresoc.v:183772.3-183780.6" + wire $1\q_int$next[0:0]$12160 + attribute \src "libresoc.v:183749.7-183749.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:175057.17-175057.96" - wire $and$libresoc.v:175057$12084_Y - attribute \src "libresoc.v:175062.17-175062.96" - wire $and$libresoc.v:175062$12089_Y - attribute \src "libresoc.v:175059.18-175059.93" - wire $not$libresoc.v:175059$12086_Y - attribute \src "libresoc.v:175061.17-175061.92" - wire $not$libresoc.v:175061$12088_Y - attribute \src "libresoc.v:175064.17-175064.92" - wire $not$libresoc.v:175064$12091_Y - attribute \src "libresoc.v:175058.18-175058.98" - wire $or$libresoc.v:175058$12085_Y - attribute \src "libresoc.v:175060.18-175060.99" - wire $or$libresoc.v:175060$12087_Y - attribute \src "libresoc.v:175063.17-175063.97" - wire $or$libresoc.v:175063$12090_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183762.17-183762.96" + wire $and$libresoc.v:183762$12149_Y + attribute \src "libresoc.v:183767.17-183767.96" + wire $and$libresoc.v:183767$12154_Y + attribute \src "libresoc.v:183764.18-183764.93" + wire $not$libresoc.v:183764$12151_Y + attribute \src "libresoc.v:183766.17-183766.92" + wire $not$libresoc.v:183766$12153_Y + attribute \src "libresoc.v:183769.17-183769.92" + wire $not$libresoc.v:183769$12156_Y + attribute \src "libresoc.v:183763.18-183763.98" + wire $or$libresoc.v:183763$12150_Y + attribute \src "libresoc.v:183765.18-183765.99" + wire $or$libresoc.v:183765$12152_Y + attribute \src "libresoc.v:183768.17-183768.97" + wire $or$libresoc.v:183768$12155_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:175022.7-175022.15" + attribute \src "libresoc.v:183727.7-183727.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175057$12084 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183762$12149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366687,10 +381684,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:175057$12084_Y + connect \Y $and$libresoc.v:183762$12149_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175062$12089 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183767$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366698,34 +381695,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:175062$12089_Y + connect \Y $and$libresoc.v:183767$12154_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175059$12086 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183764$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:175059$12086_Y + connect \Y $not$libresoc.v:183764$12151_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175061$12088 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183766$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175061$12088_Y + connect \Y $not$libresoc.v:183766$12153_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175064$12091 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183769$12156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175064$12091_Y + connect \Y $not$libresoc.v:183769$12156_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175058$12085 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183763$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366733,10 +381730,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:175058$12085_Y + connect \Y $or$libresoc.v:183763$12150_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175060$12087 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183765$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366744,10 +381741,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:175060$12087_Y + connect \Y $or$libresoc.v:183765$12152_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175063$12090 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183768$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366755,39 +381752,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:175063$12090_Y + connect \Y $or$libresoc.v:183768$12155_Y end - attribute \src "libresoc.v:175022.7-175022.20" - process $proc$libresoc.v:175022$12096 + attribute \src "libresoc.v:183727.7-183727.20" + process $proc$libresoc.v:183727$12161 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175044.7-175044.19" - process $proc$libresoc.v:175044$12097 + attribute \src "libresoc.v:183749.7-183749.19" + process $proc$libresoc.v:183749$12162 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:175065.3-175066.27" - process $proc$libresoc.v:175065$12092 + attribute \src "libresoc.v:183770.3-183771.27" + process $proc$libresoc.v:183770$12157 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:175067.3-175075.6" - process $proc$libresoc.v:175067$12093 + attribute \src "libresoc.v:183772.3-183780.6" + process $proc$libresoc.v:183772$12158 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12094 $1\q_int$next[0:0]$12095 - attribute \src "libresoc.v:175068.5-175068.29" + assign $0\q_int$next[0:0]$12159 $1\q_int$next[0:0]$12160 + attribute \src "libresoc.v:183773.5-183773.29" switch \initial - attribute \src "libresoc.v:175068.9-175068.17" + attribute \src "libresoc.v:183773.9-183773.17" case 1'1 case end @@ -366796,94 +381793,94 @@ module \rst_l$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12095 1'0 + assign $1\q_int$next[0:0]$12160 1'0 case - assign $1\q_int$next[0:0]$12095 \$5 + assign $1\q_int$next[0:0]$12160 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12094 + update \q_int$next $0\q_int$next[0:0]$12159 end - connect \$9 $and$libresoc.v:175057$12084_Y - connect \$11 $or$libresoc.v:175058$12085_Y - connect \$13 $not$libresoc.v:175059$12086_Y - connect \$15 $or$libresoc.v:175060$12087_Y - connect \$1 $not$libresoc.v:175061$12088_Y - connect \$3 $and$libresoc.v:175062$12089_Y - connect \$5 $or$libresoc.v:175063$12090_Y - connect \$7 $not$libresoc.v:175064$12091_Y + connect \$9 $and$libresoc.v:183762$12149_Y + connect \$11 $or$libresoc.v:183763$12150_Y + connect \$13 $not$libresoc.v:183764$12151_Y + connect \$15 $or$libresoc.v:183765$12152_Y + connect \$1 $not$libresoc.v:183766$12153_Y + connect \$3 $and$libresoc.v:183767$12154_Y + connect \$5 $or$libresoc.v:183768$12155_Y + connect \$7 $not$libresoc.v:183769$12156_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:175083.1-175141.10" +attribute \src "libresoc.v:183788.1-183846.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:175084.7-175084.20" + attribute \src "libresoc.v:183789.7-183789.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175129.3-175137.6" - wire $0\q_int$next[0:0]$12108 - attribute \src "libresoc.v:175127.3-175128.27" + attribute \src "libresoc.v:183834.3-183842.6" + wire $0\q_int$next[0:0]$12173 + attribute \src "libresoc.v:183832.3-183833.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:175129.3-175137.6" - wire $1\q_int$next[0:0]$12109 - attribute \src "libresoc.v:175106.7-175106.19" + attribute \src "libresoc.v:183834.3-183842.6" + wire $1\q_int$next[0:0]$12174 + attribute \src "libresoc.v:183811.7-183811.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:175119.17-175119.96" - wire $and$libresoc.v:175119$12098_Y - attribute \src "libresoc.v:175124.17-175124.96" - wire $and$libresoc.v:175124$12103_Y - attribute \src "libresoc.v:175121.18-175121.93" - wire $not$libresoc.v:175121$12100_Y - attribute \src "libresoc.v:175123.17-175123.92" - wire $not$libresoc.v:175123$12102_Y - attribute \src "libresoc.v:175126.17-175126.92" - wire $not$libresoc.v:175126$12105_Y - attribute \src "libresoc.v:175120.18-175120.98" - wire $or$libresoc.v:175120$12099_Y - attribute \src "libresoc.v:175122.18-175122.99" - wire $or$libresoc.v:175122$12101_Y - attribute \src "libresoc.v:175125.17-175125.97" - wire $or$libresoc.v:175125$12104_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183824.17-183824.96" + wire $and$libresoc.v:183824$12163_Y + attribute \src "libresoc.v:183829.17-183829.96" + wire $and$libresoc.v:183829$12168_Y + attribute \src "libresoc.v:183826.18-183826.93" + wire $not$libresoc.v:183826$12165_Y + attribute \src "libresoc.v:183828.17-183828.92" + wire $not$libresoc.v:183828$12167_Y + attribute \src "libresoc.v:183831.17-183831.92" + wire $not$libresoc.v:183831$12170_Y + attribute \src "libresoc.v:183825.18-183825.98" + wire $or$libresoc.v:183825$12164_Y + attribute \src "libresoc.v:183827.18-183827.99" + wire $or$libresoc.v:183827$12166_Y + attribute \src "libresoc.v:183830.17-183830.97" + wire $or$libresoc.v:183830$12169_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:175084.7-175084.15" + attribute \src "libresoc.v:183789.7-183789.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175119$12098 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183824$12163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366891,10 +381888,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:175119$12098_Y + connect \Y $and$libresoc.v:183824$12163_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175124$12103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183829$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366902,34 +381899,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:175124$12103_Y + connect \Y $and$libresoc.v:183829$12168_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175121$12100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183826$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:175121$12100_Y + connect \Y $not$libresoc.v:183826$12165_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175123$12102 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183828$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175123$12102_Y + connect \Y $not$libresoc.v:183828$12167_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175126$12105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183831$12170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175126$12105_Y + connect \Y $not$libresoc.v:183831$12170_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175120$12099 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183825$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366937,10 +381934,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:175120$12099_Y + connect \Y $or$libresoc.v:183825$12164_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175122$12101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183827$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366948,10 +381945,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:175122$12101_Y + connect \Y $or$libresoc.v:183827$12166_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175125$12104 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183830$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366959,39 +381956,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:175125$12104_Y + connect \Y $or$libresoc.v:183830$12169_Y end - attribute \src "libresoc.v:175084.7-175084.20" - process $proc$libresoc.v:175084$12110 + attribute \src "libresoc.v:183789.7-183789.20" + process $proc$libresoc.v:183789$12175 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175106.7-175106.19" - process $proc$libresoc.v:175106$12111 + attribute \src "libresoc.v:183811.7-183811.19" + process $proc$libresoc.v:183811$12176 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:175127.3-175128.27" - process $proc$libresoc.v:175127$12106 + attribute \src "libresoc.v:183832.3-183833.27" + process $proc$libresoc.v:183832$12171 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:175129.3-175137.6" - process $proc$libresoc.v:175129$12107 + attribute \src "libresoc.v:183834.3-183842.6" + process $proc$libresoc.v:183834$12172 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12108 $1\q_int$next[0:0]$12109 - attribute \src "libresoc.v:175130.5-175130.29" + assign $0\q_int$next[0:0]$12173 $1\q_int$next[0:0]$12174 + attribute \src "libresoc.v:183835.5-183835.29" switch \initial - attribute \src "libresoc.v:175130.9-175130.17" + attribute \src "libresoc.v:183835.9-183835.17" case 1'1 case end @@ -367000,94 +381997,94 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12109 1'0 + assign $1\q_int$next[0:0]$12174 1'0 case - assign $1\q_int$next[0:0]$12109 \$5 + assign $1\q_int$next[0:0]$12174 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12108 + update \q_int$next $0\q_int$next[0:0]$12173 end - connect \$9 $and$libresoc.v:175119$12098_Y - connect \$11 $or$libresoc.v:175120$12099_Y - connect \$13 $not$libresoc.v:175121$12100_Y - connect \$15 $or$libresoc.v:175122$12101_Y - connect \$1 $not$libresoc.v:175123$12102_Y - connect \$3 $and$libresoc.v:175124$12103_Y - connect \$5 $or$libresoc.v:175125$12104_Y - connect \$7 $not$libresoc.v:175126$12105_Y + connect \$9 $and$libresoc.v:183824$12163_Y + connect \$11 $or$libresoc.v:183825$12164_Y + connect \$13 $not$libresoc.v:183826$12165_Y + connect \$15 $or$libresoc.v:183827$12166_Y + connect \$1 $not$libresoc.v:183828$12167_Y + connect \$3 $and$libresoc.v:183829$12168_Y + connect \$5 $or$libresoc.v:183830$12169_Y + connect \$7 $not$libresoc.v:183831$12170_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:175145.1-175203.10" +attribute \src "libresoc.v:183850.1-183908.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:175146.7-175146.20" + attribute \src "libresoc.v:183851.7-183851.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175191.3-175199.6" - wire $0\q_int$next[0:0]$12122 - attribute \src "libresoc.v:175189.3-175190.27" + attribute \src "libresoc.v:183896.3-183904.6" + wire $0\q_int$next[0:0]$12187 + attribute \src "libresoc.v:183894.3-183895.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:175191.3-175199.6" - wire $1\q_int$next[0:0]$12123 - attribute \src "libresoc.v:175168.7-175168.19" + attribute \src "libresoc.v:183896.3-183904.6" + wire $1\q_int$next[0:0]$12188 + attribute \src "libresoc.v:183873.7-183873.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:175181.17-175181.96" - wire $and$libresoc.v:175181$12112_Y - attribute \src "libresoc.v:175186.17-175186.96" - wire $and$libresoc.v:175186$12117_Y - attribute \src "libresoc.v:175183.18-175183.93" - wire $not$libresoc.v:175183$12114_Y - attribute \src "libresoc.v:175185.17-175185.92" - wire $not$libresoc.v:175185$12116_Y - attribute \src "libresoc.v:175188.17-175188.92" - wire $not$libresoc.v:175188$12119_Y - attribute \src "libresoc.v:175182.18-175182.98" - wire $or$libresoc.v:175182$12113_Y - attribute \src "libresoc.v:175184.18-175184.99" - wire $or$libresoc.v:175184$12115_Y - attribute \src "libresoc.v:175187.17-175187.97" - wire $or$libresoc.v:175187$12118_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183886.17-183886.96" + wire $and$libresoc.v:183886$12177_Y + attribute \src "libresoc.v:183891.17-183891.96" + wire $and$libresoc.v:183891$12182_Y + attribute \src "libresoc.v:183888.18-183888.93" + wire $not$libresoc.v:183888$12179_Y + attribute \src "libresoc.v:183890.17-183890.92" + wire $not$libresoc.v:183890$12181_Y + attribute \src "libresoc.v:183893.17-183893.92" + wire $not$libresoc.v:183893$12184_Y + attribute \src "libresoc.v:183887.18-183887.98" + wire $or$libresoc.v:183887$12178_Y + attribute \src "libresoc.v:183889.18-183889.99" + wire $or$libresoc.v:183889$12180_Y + attribute \src "libresoc.v:183892.17-183892.97" + wire $or$libresoc.v:183892$12183_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:175146.7-175146.15" + attribute \src "libresoc.v:183851.7-183851.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175181$12112 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183886$12177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367095,10 +382092,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:175181$12112_Y + connect \Y $and$libresoc.v:183886$12177_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175186$12117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183891$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367106,34 +382103,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:175186$12117_Y + connect \Y $and$libresoc.v:183891$12182_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175183$12114 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183888$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:175183$12114_Y + connect \Y $not$libresoc.v:183888$12179_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175185$12116 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183890$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175185$12116_Y + connect \Y $not$libresoc.v:183890$12181_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175188$12119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183893$12184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175188$12119_Y + connect \Y $not$libresoc.v:183893$12184_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175182$12113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183887$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367141,10 +382138,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:175182$12113_Y + connect \Y $or$libresoc.v:183887$12178_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175184$12115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183889$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367152,10 +382149,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:175184$12115_Y + connect \Y $or$libresoc.v:183889$12180_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175187$12118 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183892$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367163,39 +382160,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:175187$12118_Y + connect \Y $or$libresoc.v:183892$12183_Y end - attribute \src "libresoc.v:175146.7-175146.20" - process $proc$libresoc.v:175146$12124 + attribute \src "libresoc.v:183851.7-183851.20" + process $proc$libresoc.v:183851$12189 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175168.7-175168.19" - process $proc$libresoc.v:175168$12125 + attribute \src "libresoc.v:183873.7-183873.19" + process $proc$libresoc.v:183873$12190 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:175189.3-175190.27" - process $proc$libresoc.v:175189$12120 + attribute \src "libresoc.v:183894.3-183895.27" + process $proc$libresoc.v:183894$12185 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:175191.3-175199.6" - process $proc$libresoc.v:175191$12121 + attribute \src "libresoc.v:183896.3-183904.6" + process $proc$libresoc.v:183896$12186 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12122 $1\q_int$next[0:0]$12123 - attribute \src "libresoc.v:175192.5-175192.29" + assign $0\q_int$next[0:0]$12187 $1\q_int$next[0:0]$12188 + attribute \src "libresoc.v:183897.5-183897.29" switch \initial - attribute \src "libresoc.v:175192.9-175192.17" + attribute \src "libresoc.v:183897.9-183897.17" case 1'1 case end @@ -367204,94 +382201,94 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12123 1'0 + assign $1\q_int$next[0:0]$12188 1'0 case - assign $1\q_int$next[0:0]$12123 \$5 + assign $1\q_int$next[0:0]$12188 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12122 + update \q_int$next $0\q_int$next[0:0]$12187 end - connect \$9 $and$libresoc.v:175181$12112_Y - connect \$11 $or$libresoc.v:175182$12113_Y - connect \$13 $not$libresoc.v:175183$12114_Y - connect \$15 $or$libresoc.v:175184$12115_Y - connect \$1 $not$libresoc.v:175185$12116_Y - connect \$3 $and$libresoc.v:175186$12117_Y - connect \$5 $or$libresoc.v:175187$12118_Y - connect \$7 $not$libresoc.v:175188$12119_Y + connect \$9 $and$libresoc.v:183886$12177_Y + connect \$11 $or$libresoc.v:183887$12178_Y + connect \$13 $not$libresoc.v:183888$12179_Y + connect \$15 $or$libresoc.v:183889$12180_Y + connect \$1 $not$libresoc.v:183890$12181_Y + connect \$3 $and$libresoc.v:183891$12182_Y + connect \$5 $or$libresoc.v:183892$12183_Y + connect \$7 $not$libresoc.v:183893$12184_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:175207.1-175265.10" +attribute \src "libresoc.v:183912.1-183970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:175208.7-175208.20" + attribute \src "libresoc.v:183913.7-183913.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175253.3-175261.6" - wire $0\q_int$next[0:0]$12136 - attribute \src "libresoc.v:175251.3-175252.27" + attribute \src "libresoc.v:183958.3-183966.6" + wire $0\q_int$next[0:0]$12201 + attribute \src "libresoc.v:183956.3-183957.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:175253.3-175261.6" - wire $1\q_int$next[0:0]$12137 - attribute \src "libresoc.v:175230.7-175230.19" + attribute \src "libresoc.v:183958.3-183966.6" + wire $1\q_int$next[0:0]$12202 + attribute \src "libresoc.v:183935.7-183935.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:175243.17-175243.96" - wire $and$libresoc.v:175243$12126_Y - attribute \src "libresoc.v:175248.17-175248.96" - wire $and$libresoc.v:175248$12131_Y - attribute \src "libresoc.v:175245.18-175245.93" - wire $not$libresoc.v:175245$12128_Y - attribute \src "libresoc.v:175247.17-175247.92" - wire $not$libresoc.v:175247$12130_Y - attribute \src "libresoc.v:175250.17-175250.92" - wire $not$libresoc.v:175250$12133_Y - attribute \src "libresoc.v:175244.18-175244.98" - wire $or$libresoc.v:175244$12127_Y - attribute \src "libresoc.v:175246.18-175246.99" - wire $or$libresoc.v:175246$12129_Y - attribute \src "libresoc.v:175249.17-175249.97" - wire $or$libresoc.v:175249$12132_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:183948.17-183948.96" + wire $and$libresoc.v:183948$12191_Y + attribute \src "libresoc.v:183953.17-183953.96" + wire $and$libresoc.v:183953$12196_Y + attribute \src "libresoc.v:183950.18-183950.93" + wire $not$libresoc.v:183950$12193_Y + attribute \src "libresoc.v:183952.17-183952.92" + wire $not$libresoc.v:183952$12195_Y + attribute \src "libresoc.v:183955.17-183955.92" + wire $not$libresoc.v:183955$12198_Y + attribute \src "libresoc.v:183949.18-183949.98" + wire $or$libresoc.v:183949$12192_Y + attribute \src "libresoc.v:183951.18-183951.99" + wire $or$libresoc.v:183951$12194_Y + attribute \src "libresoc.v:183954.17-183954.97" + wire $or$libresoc.v:183954$12197_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:175208.7-175208.15" + attribute \src "libresoc.v:183913.7-183913.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175243$12126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183948$12191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367299,10 +382296,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:175243$12126_Y + connect \Y $and$libresoc.v:183948$12191_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175248$12131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183953$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367310,34 +382307,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:175248$12131_Y + connect \Y $and$libresoc.v:183953$12196_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175245$12128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183950$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:175245$12128_Y + connect \Y $not$libresoc.v:183950$12193_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175247$12130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183952$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175247$12130_Y + connect \Y $not$libresoc.v:183952$12195_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175250$12133 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183955$12198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175250$12133_Y + connect \Y $not$libresoc.v:183955$12198_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175244$12127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183949$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367345,10 +382342,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:175244$12127_Y + connect \Y $or$libresoc.v:183949$12192_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175246$12129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183951$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367356,10 +382353,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:175246$12129_Y + connect \Y $or$libresoc.v:183951$12194_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175249$12132 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183954$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367367,39 +382364,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:175249$12132_Y + connect \Y $or$libresoc.v:183954$12197_Y end - attribute \src "libresoc.v:175208.7-175208.20" - process $proc$libresoc.v:175208$12138 + attribute \src "libresoc.v:183913.7-183913.20" + process $proc$libresoc.v:183913$12203 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175230.7-175230.19" - process $proc$libresoc.v:175230$12139 + attribute \src "libresoc.v:183935.7-183935.19" + process $proc$libresoc.v:183935$12204 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:175251.3-175252.27" - process $proc$libresoc.v:175251$12134 + attribute \src "libresoc.v:183956.3-183957.27" + process $proc$libresoc.v:183956$12199 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:175253.3-175261.6" - process $proc$libresoc.v:175253$12135 + attribute \src "libresoc.v:183958.3-183966.6" + process $proc$libresoc.v:183958$12200 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12136 $1\q_int$next[0:0]$12137 - attribute \src "libresoc.v:175254.5-175254.29" + assign $0\q_int$next[0:0]$12201 $1\q_int$next[0:0]$12202 + attribute \src "libresoc.v:183959.5-183959.29" switch \initial - attribute \src "libresoc.v:175254.9-175254.17" + attribute \src "libresoc.v:183959.9-183959.17" case 1'1 case end @@ -367408,94 +382405,94 @@ module \rst_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12137 1'0 + assign $1\q_int$next[0:0]$12202 1'0 case - assign $1\q_int$next[0:0]$12137 \$5 + assign $1\q_int$next[0:0]$12202 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12136 + update \q_int$next $0\q_int$next[0:0]$12201 end - connect \$9 $and$libresoc.v:175243$12126_Y - connect \$11 $or$libresoc.v:175244$12127_Y - connect \$13 $not$libresoc.v:175245$12128_Y - connect \$15 $or$libresoc.v:175246$12129_Y - connect \$1 $not$libresoc.v:175247$12130_Y - connect \$3 $and$libresoc.v:175248$12131_Y - connect \$5 $or$libresoc.v:175249$12132_Y - connect \$7 $not$libresoc.v:175250$12133_Y + connect \$9 $and$libresoc.v:183948$12191_Y + connect \$11 $or$libresoc.v:183949$12192_Y + connect \$13 $not$libresoc.v:183950$12193_Y + connect \$15 $or$libresoc.v:183951$12194_Y + connect \$1 $not$libresoc.v:183952$12195_Y + connect \$3 $and$libresoc.v:183953$12196_Y + connect \$5 $or$libresoc.v:183954$12197_Y + connect \$7 $not$libresoc.v:183955$12198_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:175269.1-175327.10" +attribute \src "libresoc.v:183974.1-184032.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:175270.7-175270.20" + attribute \src "libresoc.v:183975.7-183975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175315.3-175323.6" - wire $0\q_int$next[0:0]$12150 - attribute \src "libresoc.v:175313.3-175314.27" + attribute \src "libresoc.v:184020.3-184028.6" + wire $0\q_int$next[0:0]$12215 + attribute \src "libresoc.v:184018.3-184019.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:175315.3-175323.6" - wire $1\q_int$next[0:0]$12151 - attribute \src "libresoc.v:175292.7-175292.19" + attribute \src "libresoc.v:184020.3-184028.6" + wire $1\q_int$next[0:0]$12216 + attribute \src "libresoc.v:183997.7-183997.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:175305.17-175305.96" - wire $and$libresoc.v:175305$12140_Y - attribute \src "libresoc.v:175310.17-175310.96" - wire $and$libresoc.v:175310$12145_Y - attribute \src "libresoc.v:175307.18-175307.93" - wire $not$libresoc.v:175307$12142_Y - attribute \src "libresoc.v:175309.17-175309.92" - wire $not$libresoc.v:175309$12144_Y - attribute \src "libresoc.v:175312.17-175312.92" - wire $not$libresoc.v:175312$12147_Y - attribute \src "libresoc.v:175306.18-175306.98" - wire $or$libresoc.v:175306$12141_Y - attribute \src "libresoc.v:175308.18-175308.99" - wire $or$libresoc.v:175308$12143_Y - attribute \src "libresoc.v:175311.17-175311.97" - wire $or$libresoc.v:175311$12146_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:184010.17-184010.96" + wire $and$libresoc.v:184010$12205_Y + attribute \src "libresoc.v:184015.17-184015.96" + wire $and$libresoc.v:184015$12210_Y + attribute \src "libresoc.v:184012.18-184012.93" + wire $not$libresoc.v:184012$12207_Y + attribute \src "libresoc.v:184014.17-184014.92" + wire $not$libresoc.v:184014$12209_Y + attribute \src "libresoc.v:184017.17-184017.92" + wire $not$libresoc.v:184017$12212_Y + attribute \src "libresoc.v:184011.18-184011.98" + wire $or$libresoc.v:184011$12206_Y + attribute \src "libresoc.v:184013.18-184013.99" + wire $or$libresoc.v:184013$12208_Y + attribute \src "libresoc.v:184016.17-184016.97" + wire $or$libresoc.v:184016$12211_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:175270.7-175270.15" + attribute \src "libresoc.v:183975.7-183975.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175305$12140 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:184010$12205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367503,10 +382500,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:175305$12140_Y + connect \Y $and$libresoc.v:184010$12205_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175310$12145 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:184015$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367514,34 +382511,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:175310$12145_Y + connect \Y $and$libresoc.v:184015$12210_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175307$12142 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:184012$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:175307$12142_Y + connect \Y $not$libresoc.v:184012$12207_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175309$12144 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:184014$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175309$12144_Y + connect \Y $not$libresoc.v:184014$12209_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175312$12147 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:184017$12212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175312$12147_Y + connect \Y $not$libresoc.v:184017$12212_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175306$12141 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:184011$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367549,10 +382546,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:175306$12141_Y + connect \Y $or$libresoc.v:184011$12206_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175308$12143 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:184013$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367560,10 +382557,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:175308$12143_Y + connect \Y $or$libresoc.v:184013$12208_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175311$12146 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:184016$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367571,39 +382568,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:175311$12146_Y + connect \Y $or$libresoc.v:184016$12211_Y end - attribute \src "libresoc.v:175270.7-175270.20" - process $proc$libresoc.v:175270$12152 + attribute \src "libresoc.v:183975.7-183975.20" + process $proc$libresoc.v:183975$12217 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175292.7-175292.19" - process $proc$libresoc.v:175292$12153 + attribute \src "libresoc.v:183997.7-183997.19" + process $proc$libresoc.v:183997$12218 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:175313.3-175314.27" - process $proc$libresoc.v:175313$12148 + attribute \src "libresoc.v:184018.3-184019.27" + process $proc$libresoc.v:184018$12213 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:175315.3-175323.6" - process $proc$libresoc.v:175315$12149 + attribute \src "libresoc.v:184020.3-184028.6" + process $proc$libresoc.v:184020$12214 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12150 $1\q_int$next[0:0]$12151 - attribute \src "libresoc.v:175316.5-175316.29" + assign $0\q_int$next[0:0]$12215 $1\q_int$next[0:0]$12216 + attribute \src "libresoc.v:184021.5-184021.29" switch \initial - attribute \src "libresoc.v:175316.9-175316.17" + attribute \src "libresoc.v:184021.9-184021.17" case 1'1 case end @@ -367612,94 +382609,94 @@ module \rst_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12151 1'0 + assign $1\q_int$next[0:0]$12216 1'0 case - assign $1\q_int$next[0:0]$12151 \$5 + assign $1\q_int$next[0:0]$12216 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12150 + update \q_int$next $0\q_int$next[0:0]$12215 end - connect \$9 $and$libresoc.v:175305$12140_Y - connect \$11 $or$libresoc.v:175306$12141_Y - connect \$13 $not$libresoc.v:175307$12142_Y - connect \$15 $or$libresoc.v:175308$12143_Y - connect \$1 $not$libresoc.v:175309$12144_Y - connect \$3 $and$libresoc.v:175310$12145_Y - connect \$5 $or$libresoc.v:175311$12146_Y - connect \$7 $not$libresoc.v:175312$12147_Y + connect \$9 $and$libresoc.v:184010$12205_Y + connect \$11 $or$libresoc.v:184011$12206_Y + connect \$13 $not$libresoc.v:184012$12207_Y + connect \$15 $or$libresoc.v:184013$12208_Y + connect \$1 $not$libresoc.v:184014$12209_Y + connect \$3 $and$libresoc.v:184015$12210_Y + connect \$5 $or$libresoc.v:184016$12211_Y + connect \$7 $not$libresoc.v:184017$12212_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:175331.1-175389.10" +attribute \src "libresoc.v:184036.1-184094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:175332.7-175332.20" + attribute \src "libresoc.v:184037.7-184037.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175377.3-175385.6" - wire $0\q_int$next[0:0]$12164 - attribute \src "libresoc.v:175375.3-175376.27" + attribute \src "libresoc.v:184082.3-184090.6" + wire $0\q_int$next[0:0]$12229 + attribute \src "libresoc.v:184080.3-184081.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:175377.3-175385.6" - wire $1\q_int$next[0:0]$12165 - attribute \src "libresoc.v:175354.7-175354.19" + attribute \src "libresoc.v:184082.3-184090.6" + wire $1\q_int$next[0:0]$12230 + attribute \src "libresoc.v:184059.7-184059.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:175367.17-175367.96" - wire $and$libresoc.v:175367$12154_Y - attribute \src "libresoc.v:175372.17-175372.96" - wire $and$libresoc.v:175372$12159_Y - attribute \src "libresoc.v:175369.18-175369.93" - wire $not$libresoc.v:175369$12156_Y - attribute \src "libresoc.v:175371.17-175371.92" - wire $not$libresoc.v:175371$12158_Y - attribute \src "libresoc.v:175374.17-175374.92" - wire $not$libresoc.v:175374$12161_Y - attribute \src "libresoc.v:175368.18-175368.98" - wire $or$libresoc.v:175368$12155_Y - attribute \src "libresoc.v:175370.18-175370.99" - wire $or$libresoc.v:175370$12157_Y - attribute \src "libresoc.v:175373.17-175373.97" - wire $or$libresoc.v:175373$12160_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:184072.17-184072.96" + wire $and$libresoc.v:184072$12219_Y + attribute \src "libresoc.v:184077.17-184077.96" + wire $and$libresoc.v:184077$12224_Y + attribute \src "libresoc.v:184074.18-184074.93" + wire $not$libresoc.v:184074$12221_Y + attribute \src "libresoc.v:184076.17-184076.92" + wire $not$libresoc.v:184076$12223_Y + attribute \src "libresoc.v:184079.17-184079.92" + wire $not$libresoc.v:184079$12226_Y + attribute \src "libresoc.v:184073.18-184073.98" + wire $or$libresoc.v:184073$12220_Y + attribute \src "libresoc.v:184075.18-184075.99" + wire $or$libresoc.v:184075$12222_Y + attribute \src "libresoc.v:184078.17-184078.97" + wire $or$libresoc.v:184078$12225_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:175332.7-175332.15" + attribute \src "libresoc.v:184037.7-184037.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175367$12154 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:184072$12219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367707,10 +382704,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:175367$12154_Y + connect \Y $and$libresoc.v:184072$12219_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175372$12159 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:184077$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367718,34 +382715,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:175372$12159_Y + connect \Y $and$libresoc.v:184077$12224_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175369$12156 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:184074$12221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:175369$12156_Y + connect \Y $not$libresoc.v:184074$12221_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175371$12158 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:184076$12223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175371$12158_Y + connect \Y $not$libresoc.v:184076$12223_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175374$12161 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:184079$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175374$12161_Y + connect \Y $not$libresoc.v:184079$12226_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175368$12155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:184073$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367753,10 +382750,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:175368$12155_Y + connect \Y $or$libresoc.v:184073$12220_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175370$12157 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:184075$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367764,10 +382761,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:175370$12157_Y + connect \Y $or$libresoc.v:184075$12222_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175373$12160 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:184078$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367775,39 +382772,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:175373$12160_Y + connect \Y $or$libresoc.v:184078$12225_Y end - attribute \src "libresoc.v:175332.7-175332.20" - process $proc$libresoc.v:175332$12166 + attribute \src "libresoc.v:184037.7-184037.20" + process $proc$libresoc.v:184037$12231 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175354.7-175354.19" - process $proc$libresoc.v:175354$12167 + attribute \src "libresoc.v:184059.7-184059.19" + process $proc$libresoc.v:184059$12232 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:175375.3-175376.27" - process $proc$libresoc.v:175375$12162 + attribute \src "libresoc.v:184080.3-184081.27" + process $proc$libresoc.v:184080$12227 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:175377.3-175385.6" - process $proc$libresoc.v:175377$12163 + attribute \src "libresoc.v:184082.3-184090.6" + process $proc$libresoc.v:184082$12228 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12164 $1\q_int$next[0:0]$12165 - attribute \src "libresoc.v:175378.5-175378.29" + assign $0\q_int$next[0:0]$12229 $1\q_int$next[0:0]$12230 + attribute \src "libresoc.v:184083.5-184083.29" switch \initial - attribute \src "libresoc.v:175378.9-175378.17" + attribute \src "libresoc.v:184083.9-184083.17" case 1'1 case end @@ -367816,94 +382813,94 @@ module \rst_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12165 1'0 + assign $1\q_int$next[0:0]$12230 1'0 case - assign $1\q_int$next[0:0]$12165 \$5 + assign $1\q_int$next[0:0]$12230 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12164 + update \q_int$next $0\q_int$next[0:0]$12229 end - connect \$9 $and$libresoc.v:175367$12154_Y - connect \$11 $or$libresoc.v:175368$12155_Y - connect \$13 $not$libresoc.v:175369$12156_Y - connect \$15 $or$libresoc.v:175370$12157_Y - connect \$1 $not$libresoc.v:175371$12158_Y - connect \$3 $and$libresoc.v:175372$12159_Y - connect \$5 $or$libresoc.v:175373$12160_Y - connect \$7 $not$libresoc.v:175374$12161_Y + connect \$9 $and$libresoc.v:184072$12219_Y + connect \$11 $or$libresoc.v:184073$12220_Y + connect \$13 $not$libresoc.v:184074$12221_Y + connect \$15 $or$libresoc.v:184075$12222_Y + connect \$1 $not$libresoc.v:184076$12223_Y + connect \$3 $and$libresoc.v:184077$12224_Y + connect \$5 $or$libresoc.v:184078$12225_Y + connect \$7 $not$libresoc.v:184079$12226_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:175393.1-175451.10" +attribute \src "libresoc.v:184098.1-184156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:175394.7-175394.20" + attribute \src "libresoc.v:184099.7-184099.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175439.3-175447.6" - wire $0\q_int$next[0:0]$12178 - attribute \src "libresoc.v:175437.3-175438.27" + attribute \src "libresoc.v:184144.3-184152.6" + wire $0\q_int$next[0:0]$12243 + attribute \src "libresoc.v:184142.3-184143.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:175439.3-175447.6" - wire $1\q_int$next[0:0]$12179 - attribute \src "libresoc.v:175416.7-175416.19" + attribute \src "libresoc.v:184144.3-184152.6" + wire $1\q_int$next[0:0]$12244 + attribute \src "libresoc.v:184121.7-184121.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:175429.17-175429.96" - wire $and$libresoc.v:175429$12168_Y - attribute \src "libresoc.v:175434.17-175434.96" - wire $and$libresoc.v:175434$12173_Y - attribute \src "libresoc.v:175431.18-175431.93" - wire $not$libresoc.v:175431$12170_Y - attribute \src "libresoc.v:175433.17-175433.92" - wire $not$libresoc.v:175433$12172_Y - attribute \src "libresoc.v:175436.17-175436.92" - wire $not$libresoc.v:175436$12175_Y - attribute \src "libresoc.v:175430.18-175430.98" - wire $or$libresoc.v:175430$12169_Y - attribute \src "libresoc.v:175432.18-175432.99" - wire $or$libresoc.v:175432$12171_Y - attribute \src "libresoc.v:175435.17-175435.97" - wire $or$libresoc.v:175435$12174_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:184134.17-184134.96" + wire $and$libresoc.v:184134$12233_Y + attribute \src "libresoc.v:184139.17-184139.96" + wire $and$libresoc.v:184139$12238_Y + attribute \src "libresoc.v:184136.18-184136.93" + wire $not$libresoc.v:184136$12235_Y + attribute \src "libresoc.v:184138.17-184138.92" + wire $not$libresoc.v:184138$12237_Y + attribute \src "libresoc.v:184141.17-184141.92" + wire $not$libresoc.v:184141$12240_Y + attribute \src "libresoc.v:184135.18-184135.98" + wire $or$libresoc.v:184135$12234_Y + attribute \src "libresoc.v:184137.18-184137.99" + wire $or$libresoc.v:184137$12236_Y + attribute \src "libresoc.v:184140.17-184140.97" + wire $or$libresoc.v:184140$12239_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:175394.7-175394.15" + attribute \src "libresoc.v:184099.7-184099.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175429$12168 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:184134$12233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367911,10 +382908,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:175429$12168_Y + connect \Y $and$libresoc.v:184134$12233_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175434$12173 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:184139$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367922,34 +382919,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:175434$12173_Y + connect \Y $and$libresoc.v:184139$12238_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175431$12170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:184136$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:175431$12170_Y + connect \Y $not$libresoc.v:184136$12235_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175433$12172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:184138$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175433$12172_Y + connect \Y $not$libresoc.v:184138$12237_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175436$12175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:184141$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:175436$12175_Y + connect \Y $not$libresoc.v:184141$12240_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175430$12169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:184135$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367957,10 +382954,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:175430$12169_Y + connect \Y $or$libresoc.v:184135$12234_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175432$12171 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:184137$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367968,10 +382965,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:175432$12171_Y + connect \Y $or$libresoc.v:184137$12236_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175435$12174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:184140$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367979,39 +382976,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:175435$12174_Y + connect \Y $or$libresoc.v:184140$12239_Y end - attribute \src "libresoc.v:175394.7-175394.20" - process $proc$libresoc.v:175394$12180 + attribute \src "libresoc.v:184099.7-184099.20" + process $proc$libresoc.v:184099$12245 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175416.7-175416.19" - process $proc$libresoc.v:175416$12181 + attribute \src "libresoc.v:184121.7-184121.19" + process $proc$libresoc.v:184121$12246 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:175437.3-175438.27" - process $proc$libresoc.v:175437$12176 + attribute \src "libresoc.v:184142.3-184143.27" + process $proc$libresoc.v:184142$12241 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:175439.3-175447.6" - process $proc$libresoc.v:175439$12177 + attribute \src "libresoc.v:184144.3-184152.6" + process $proc$libresoc.v:184144$12242 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12178 $1\q_int$next[0:0]$12179 - attribute \src "libresoc.v:175440.5-175440.29" + assign $0\q_int$next[0:0]$12243 $1\q_int$next[0:0]$12244 + attribute \src "libresoc.v:184145.5-184145.29" switch \initial - attribute \src "libresoc.v:175440.9-175440.17" + attribute \src "libresoc.v:184145.9-184145.17" case 1'1 case end @@ -368020,92 +383017,92 @@ module \rst_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12179 1'0 + assign $1\q_int$next[0:0]$12244 1'0 case - assign $1\q_int$next[0:0]$12179 \$5 + assign $1\q_int$next[0:0]$12244 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12178 + update \q_int$next $0\q_int$next[0:0]$12243 end - connect \$9 $and$libresoc.v:175429$12168_Y - connect \$11 $or$libresoc.v:175430$12169_Y - connect \$13 $not$libresoc.v:175431$12170_Y - connect \$15 $or$libresoc.v:175432$12171_Y - connect \$1 $not$libresoc.v:175433$12172_Y - connect \$3 $and$libresoc.v:175434$12173_Y - connect \$5 $or$libresoc.v:175435$12174_Y - connect \$7 $not$libresoc.v:175436$12175_Y + connect \$9 $and$libresoc.v:184134$12233_Y + connect \$11 $or$libresoc.v:184135$12234_Y + connect \$13 $not$libresoc.v:184136$12235_Y + connect \$15 $or$libresoc.v:184137$12236_Y + connect \$1 $not$libresoc.v:184138$12237_Y + connect \$3 $and$libresoc.v:184139$12238_Y + connect \$5 $or$libresoc.v:184140$12239_Y + connect \$7 $not$libresoc.v:184141$12240_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:175455.1-175858.10" +attribute \src "libresoc.v:184160.1-184569.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:175816.3-175841.6" + attribute \src "libresoc.v:184527.3-184552.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:175456.7-175456.20" + attribute \src "libresoc.v:184161.7-184161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175816.3-175841.6" + attribute \src "libresoc.v:184527.3-184552.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:175816.3-175841.6" + attribute \src "libresoc.v:184527.3-184552.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:175795.18-175795.122" - wire $and$libresoc.v:175795$12183_Y - attribute \src "libresoc.v:175797.18-175797.122" - wire $and$libresoc.v:175797$12185_Y - attribute \src "libresoc.v:175806.18-175806.105" - wire $and$libresoc.v:175806$12198_Y - attribute \src "libresoc.v:175809.18-175809.105" - wire $and$libresoc.v:175809$12201_Y - attribute \src "libresoc.v:175805.18-175805.123" - wire $eq$libresoc.v:175805$12197_Y - attribute \src "libresoc.v:175808.18-175808.123" - wire $eq$libresoc.v:175808$12200_Y - attribute \src "libresoc.v:175811.18-175811.117" - wire $eq$libresoc.v:175811$12203_Y - attribute \src "libresoc.v:175798.18-175798.97" - wire width 65 $extend$libresoc.v:175798$12186_Y - attribute \src "libresoc.v:175799.18-175799.91" - wire width 65 $extend$libresoc.v:175799$12188_Y - attribute \src "libresoc.v:175801.18-175801.97" - wire width 65 $extend$libresoc.v:175801$12191_Y - attribute \src "libresoc.v:175802.18-175802.91" - wire width 65 $extend$libresoc.v:175802$12193_Y - attribute \src "libresoc.v:175814.18-175814.99" - wire width 128 $extend$libresoc.v:175814$12206_Y - attribute \src "libresoc.v:175804.18-175804.112" - wire $ge$libresoc.v:175804$12196_Y - attribute \src "libresoc.v:175807.18-175807.124" - wire $ge$libresoc.v:175807$12199_Y - attribute \src "libresoc.v:175798.18-175798.97" - wire width 65 $neg$libresoc.v:175798$12187_Y - attribute \src "libresoc.v:175801.18-175801.97" - wire width 65 $neg$libresoc.v:175801$12192_Y - attribute \src "libresoc.v:175799.18-175799.91" - wire width 65 $pos$libresoc.v:175799$12189_Y - attribute \src "libresoc.v:175802.18-175802.91" - wire width 65 $pos$libresoc.v:175802$12194_Y - attribute \src "libresoc.v:175814.18-175814.99" - wire width 128 $pos$libresoc.v:175814$12207_Y - attribute \src "libresoc.v:175813.18-175813.117" - wire width 95 $sshl$libresoc.v:175813$12205_Y - attribute \src "libresoc.v:175815.18-175815.111" - wire width 191 $sshl$libresoc.v:175815$12208_Y - attribute \src "libresoc.v:175794.18-175794.131" - wire $ternary$libresoc.v:175794$12182_Y - attribute \src "libresoc.v:175796.18-175796.131" - wire $ternary$libresoc.v:175796$12184_Y - attribute \src "libresoc.v:175800.18-175800.119" - wire width 65 $ternary$libresoc.v:175800$12190_Y - attribute \src "libresoc.v:175803.18-175803.120" - wire width 65 $ternary$libresoc.v:175803$12195_Y - attribute \src "libresoc.v:175810.18-175810.130" - wire width 32 $ternary$libresoc.v:175810$12202_Y - attribute \src "libresoc.v:175812.18-175812.131" - wire width 32 $ternary$libresoc.v:175812$12204_Y + attribute \src "libresoc.v:184506.18-184506.122" + wire $and$libresoc.v:184506$12248_Y + attribute \src "libresoc.v:184508.18-184508.122" + wire $and$libresoc.v:184508$12250_Y + attribute \src "libresoc.v:184517.18-184517.105" + wire $and$libresoc.v:184517$12263_Y + attribute \src "libresoc.v:184520.18-184520.105" + wire $and$libresoc.v:184520$12266_Y + attribute \src "libresoc.v:184516.18-184516.123" + wire $eq$libresoc.v:184516$12262_Y + attribute \src "libresoc.v:184519.18-184519.123" + wire $eq$libresoc.v:184519$12265_Y + attribute \src "libresoc.v:184522.18-184522.117" + wire $eq$libresoc.v:184522$12268_Y + attribute \src "libresoc.v:184509.18-184509.97" + wire width 65 $extend$libresoc.v:184509$12251_Y + attribute \src "libresoc.v:184510.18-184510.91" + wire width 65 $extend$libresoc.v:184510$12253_Y + attribute \src "libresoc.v:184512.18-184512.97" + wire width 65 $extend$libresoc.v:184512$12256_Y + attribute \src "libresoc.v:184513.18-184513.91" + wire width 65 $extend$libresoc.v:184513$12258_Y + attribute \src "libresoc.v:184525.18-184525.99" + wire width 128 $extend$libresoc.v:184525$12271_Y + attribute \src "libresoc.v:184515.18-184515.112" + wire $ge$libresoc.v:184515$12261_Y + attribute \src "libresoc.v:184518.18-184518.124" + wire $ge$libresoc.v:184518$12264_Y + attribute \src "libresoc.v:184509.18-184509.97" + wire width 65 $neg$libresoc.v:184509$12252_Y + attribute \src "libresoc.v:184512.18-184512.97" + wire width 65 $neg$libresoc.v:184512$12257_Y + attribute \src "libresoc.v:184510.18-184510.91" + wire width 65 $pos$libresoc.v:184510$12254_Y + attribute \src "libresoc.v:184513.18-184513.91" + wire width 65 $pos$libresoc.v:184513$12259_Y + attribute \src "libresoc.v:184525.18-184525.99" + wire width 128 $pos$libresoc.v:184525$12272_Y + attribute \src "libresoc.v:184524.18-184524.117" + wire width 95 $sshl$libresoc.v:184524$12270_Y + attribute \src "libresoc.v:184526.18-184526.111" + wire width 191 $sshl$libresoc.v:184526$12273_Y + attribute \src "libresoc.v:184505.18-184505.131" + wire $ternary$libresoc.v:184505$12247_Y + attribute \src "libresoc.v:184507.18-184507.131" + wire $ternary$libresoc.v:184507$12249_Y + attribute \src "libresoc.v:184511.18-184511.119" + wire width 65 $ternary$libresoc.v:184511$12255_Y + attribute \src "libresoc.v:184514.18-184514.120" + wire width 65 $ternary$libresoc.v:184514$12260_Y + attribute \src "libresoc.v:184521.18-184521.130" + wire width 32 $ternary$libresoc.v:184521$12267_Y + attribute \src "libresoc.v:184523.18-184523.131" + wire width 32 $ternary$libresoc.v:184523$12269_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -368142,11 +383139,11 @@ module \setup_stage wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" wire width 32 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" wire width 32 \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" wire width 128 \$61 @@ -368174,42 +383171,46 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:175456.7-175456.15" + attribute \src "libresoc.v:184161.7-184161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -368308,6 +383309,7 @@ module \setup_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -368384,6 +383386,7 @@ module \setup_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -368430,9 +383433,9 @@ module \setup_stage wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 50 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 output 49 \operation @@ -368445,7 +383448,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:175795$12183 + cell $and $and$libresoc.v:184506$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -368453,10 +383456,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:175795$12183_Y + connect \Y $and$libresoc.v:184506$12248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:175797$12185 + cell $and $and$libresoc.v:184508$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -368464,10 +383467,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:175797$12185_Y + connect \Y $and$libresoc.v:184508$12250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:175806$12198 + cell $and $and$libresoc.v:184517$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -368475,10 +383478,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:175806$12198_Y + connect \Y $and$libresoc.v:184517$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:175809$12201 + cell $and $and$libresoc.v:184520$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -368486,10 +383489,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:175809$12201_Y + connect \Y $and$libresoc.v:184520$12266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:175805$12197 + cell $eq $eq$libresoc.v:184516$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -368497,10 +383500,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:175805$12197_Y + connect \Y $eq$libresoc.v:184516$12262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:175808$12200 + cell $eq $eq$libresoc.v:184519$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -368508,10 +383511,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:175808$12200_Y + connect \Y $eq$libresoc.v:184519$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:175811$12203 + cell $eq $eq$libresoc.v:184522$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -368519,50 +383522,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:175811$12203_Y + connect \Y $eq$libresoc.v:184522$12268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:175798$12186 + cell $pos $extend$libresoc.v:184509$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:175798$12186_Y + connect \Y $extend$libresoc.v:184509$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:175799$12188 + cell $pos $extend$libresoc.v:184510$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:175799$12188_Y + connect \Y $extend$libresoc.v:184510$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:175801$12191 + cell $pos $extend$libresoc.v:184512$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:175801$12191_Y + connect \Y $extend$libresoc.v:184512$12256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:175802$12193 + cell $pos $extend$libresoc.v:184513$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:175802$12193_Y + connect \Y $extend$libresoc.v:184513$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:175814$12206 + cell $pos $extend$libresoc.v:184525$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:175814$12206_Y + connect \Y $extend$libresoc.v:184525$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:175804$12196 + cell $ge $ge$libresoc.v:184515$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -368570,10 +383573,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:175804$12196_Y + connect \Y $ge$libresoc.v:184515$12261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:175807$12199 + cell $ge $ge$libresoc.v:184518$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -368581,50 +383584,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:175807$12199_Y + connect \Y $ge$libresoc.v:184518$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:175798$12187 + cell $neg $neg$libresoc.v:184509$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:175798$12186_Y - connect \Y $neg$libresoc.v:175798$12187_Y + connect \A $extend$libresoc.v:184509$12251_Y + connect \Y $neg$libresoc.v:184509$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:175801$12192 + cell $neg $neg$libresoc.v:184512$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:175801$12191_Y - connect \Y $neg$libresoc.v:175801$12192_Y + connect \A $extend$libresoc.v:184512$12256_Y + connect \Y $neg$libresoc.v:184512$12257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:175799$12189 + cell $pos $pos$libresoc.v:184510$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:175799$12188_Y - connect \Y $pos$libresoc.v:175799$12189_Y + connect \A $extend$libresoc.v:184510$12253_Y + connect \Y $pos$libresoc.v:184510$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:175802$12194 + cell $pos $pos$libresoc.v:184513$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:175802$12193_Y - connect \Y $pos$libresoc.v:175802$12194_Y + connect \A $extend$libresoc.v:184513$12258_Y + connect \Y $pos$libresoc.v:184513$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:175814$12207 + cell $pos $pos$libresoc.v:184525$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:175814$12206_Y - connect \Y $pos$libresoc.v:175814$12207_Y + connect \A $extend$libresoc.v:184525$12271_Y + connect \Y $pos$libresoc.v:184525$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:175813$12205 + cell $sshl $sshl$libresoc.v:184524$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -368632,10 +383635,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:175813$12205_Y + connect \Y $sshl$libresoc.v:184524$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:175815$12208 + cell $sshl $sshl$libresoc.v:184526$12273 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -368643,72 +383646,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:175815$12208_Y + connect \Y $sshl$libresoc.v:184526$12273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:175794$12182 + cell $mux $ternary$libresoc.v:184505$12247 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:175794$12182_Y + connect \Y $ternary$libresoc.v:184505$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:175796$12184 + cell $mux $ternary$libresoc.v:184507$12249 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:175796$12184_Y + connect \Y $ternary$libresoc.v:184507$12249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:175800$12190 + cell $mux $ternary$libresoc.v:184511$12255 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:175800$12190_Y + connect \Y $ternary$libresoc.v:184511$12255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:175803$12195 + cell $mux $ternary$libresoc.v:184514$12260 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:175803$12195_Y + connect \Y $ternary$libresoc.v:184514$12260_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:175810$12202 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:184521$12267 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:175810$12202_Y + connect \Y $ternary$libresoc.v:184521$12267_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:175812$12204 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:184523$12269 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:175812$12204_Y + connect \Y $ternary$libresoc.v:184523$12269_Y end - attribute \src "libresoc.v:175456.7-175456.20" - process $proc$libresoc.v:175456$12210 + attribute \src "libresoc.v:184161.7-184161.20" + process $proc$libresoc.v:184161$12275 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175816.3-175841.6" - process $proc$libresoc.v:175816$12209 + attribute \src "libresoc.v:184527.3-184552.6" + process $proc$libresoc.v:184527$12274 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:175817.5-175817.29" + attribute \src "libresoc.v:184528.5-184528.29" switch \initial - attribute \src "libresoc.v:175817.9-175817.17" + attribute \src "libresoc.v:184528.9-184528.17" case 1'1 case end @@ -368740,28 +383743,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:175794$12182_Y - connect \$23 $and$libresoc.v:175795$12183_Y - connect \$25 $ternary$libresoc.v:175796$12184_Y - connect \$27 $and$libresoc.v:175797$12185_Y - connect \$30 $neg$libresoc.v:175798$12187_Y - connect \$32 $pos$libresoc.v:175799$12189_Y - connect \$34 $ternary$libresoc.v:175800$12190_Y - connect \$37 $neg$libresoc.v:175801$12192_Y - connect \$39 $pos$libresoc.v:175802$12194_Y - connect \$41 $ternary$libresoc.v:175803$12195_Y - connect \$43 $ge$libresoc.v:175804$12196_Y - connect \$45 $eq$libresoc.v:175805$12197_Y - connect \$47 $and$libresoc.v:175806$12198_Y - connect \$49 $ge$libresoc.v:175807$12199_Y - connect \$51 $eq$libresoc.v:175808$12200_Y - connect \$53 $and$libresoc.v:175809$12201_Y - connect \$55 $ternary$libresoc.v:175810$12202_Y - connect \$57 $eq$libresoc.v:175811$12203_Y - connect \$59 $ternary$libresoc.v:175812$12204_Y - connect \$62 $sshl$libresoc.v:175813$12205_Y - connect \$61 $pos$libresoc.v:175814$12207_Y - connect \$66 $sshl$libresoc.v:175815$12208_Y + connect \$21 $ternary$libresoc.v:184505$12247_Y + connect \$23 $and$libresoc.v:184506$12248_Y + connect \$25 $ternary$libresoc.v:184507$12249_Y + connect \$27 $and$libresoc.v:184508$12250_Y + connect \$30 $neg$libresoc.v:184509$12252_Y + connect \$32 $pos$libresoc.v:184510$12254_Y + connect \$34 $ternary$libresoc.v:184511$12255_Y + connect \$37 $neg$libresoc.v:184512$12257_Y + connect \$39 $pos$libresoc.v:184513$12259_Y + connect \$41 $ternary$libresoc.v:184514$12260_Y + connect \$43 $ge$libresoc.v:184515$12261_Y + connect \$45 $eq$libresoc.v:184516$12262_Y + connect \$47 $and$libresoc.v:184517$12263_Y + connect \$49 $ge$libresoc.v:184518$12264_Y + connect \$51 $eq$libresoc.v:184519$12265_Y + connect \$53 $and$libresoc.v:184520$12266_Y + connect \$55 $ternary$libresoc.v:184521$12267_Y + connect \$57 $eq$libresoc.v:184522$12268_Y + connect \$59 $ternary$libresoc.v:184523$12269_Y + connect \$62 $sshl$libresoc.v:184524$12270_Y + connect \$61 $pos$libresoc.v:184525$12272_Y + connect \$66 $sshl$libresoc.v:184526$12273_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -368779,513 +383782,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:175862.1-177063.10" +attribute \src "libresoc.v:184573.1-185780.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:176634.3-176635.25" + attribute \src "libresoc.v:185351.3-185352.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:176632.3-176633.46" + attribute \src "libresoc.v:185349.3-185350.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:176983.3-176991.6" - wire $0\alu_l_r_alu$next[0:0]$12428 - attribute \src "libresoc.v:176550.3-176551.39" + attribute \src "libresoc.v:185700.3-185708.6" + wire $0\alu_l_r_alu$next[0:0]$12493 + attribute \src "libresoc.v:185267.3-185268.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 12 $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12345 - attribute \src "libresoc.v:176578.3-176579.75" - wire width 12 $0\alu_shift_rot0_sr_op__fn_unit[11:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12346 - attribute \src "libresoc.v:176580.3-176581.89" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 + attribute \src "libresoc.v:185295.3-185296.75" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] + attribute \src "libresoc.v:185537.3-185574.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 + attribute \src "libresoc.v:185297.3-185298.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12347 - attribute \src "libresoc.v:176582.3-176583.85" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 + attribute \src "libresoc.v:185299.3-185300.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12348 - attribute \src "libresoc.v:176596.3-176597.83" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 + attribute \src "libresoc.v:185313.3-185314.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12349 - attribute \src "libresoc.v:176600.3-176601.77" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 + attribute \src "libresoc.v:185317.3-185318.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12350 - attribute \src "libresoc.v:176608.3-176609.69" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 + attribute \src "libresoc.v:185325.3-185326.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12351 - attribute \src "libresoc.v:176576.3-176577.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 + attribute \src "libresoc.v:185293.3-185294.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12352 - attribute \src "libresoc.v:176594.3-176595.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 + attribute \src "libresoc.v:185311.3-185312.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12353 - attribute \src "libresoc.v:176604.3-176605.77" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 + attribute \src "libresoc.v:185321.3-185322.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12354 - attribute \src "libresoc.v:176606.3-176607.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 + attribute \src "libresoc.v:185323.3-185324.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12355 - attribute \src "libresoc.v:176588.3-176589.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 + attribute \src "libresoc.v:185305.3-185306.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12356 - attribute \src "libresoc.v:176590.3-176591.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 + attribute \src "libresoc.v:185307.3-185308.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12357 - attribute \src "libresoc.v:176598.3-176599.85" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 + attribute \src "libresoc.v:185315.3-185316.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12358 - attribute \src "libresoc.v:176602.3-176603.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 + attribute \src "libresoc.v:185319.3-185320.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12359 - attribute \src "libresoc.v:176586.3-176587.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 + attribute \src "libresoc.v:185303.3-185304.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12360 - attribute \src "libresoc.v:176584.3-176585.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 + attribute \src "libresoc.v:185301.3-185302.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12361 - attribute \src "libresoc.v:176592.3-176593.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 + attribute \src "libresoc.v:185309.3-185310.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:176974.3-176982.6" - wire $0\alui_l_r_alui$next[0:0]$12425 - attribute \src "libresoc.v:176552.3-176553.43" + attribute \src "libresoc.v:185691.3-185699.6" + wire $0\alui_l_r_alui$next[0:0]$12490 + attribute \src "libresoc.v:185269.3-185270.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:176858.3-176879.6" - wire width 64 $0\data_r0__o$next[63:0]$12386 - attribute \src "libresoc.v:176572.3-176573.37" + attribute \src "libresoc.v:185575.3-185596.6" + wire width 64 $0\data_r0__o$next[63:0]$12451 + attribute \src "libresoc.v:185289.3-185290.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:176858.3-176879.6" - wire $0\data_r0__o_ok$next[0:0]$12387 - attribute \src "libresoc.v:176574.3-176575.43" + attribute \src "libresoc.v:185575.3-185596.6" + wire $0\data_r0__o_ok$next[0:0]$12452 + attribute \src "libresoc.v:185291.3-185292.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:176880.3-176901.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12394 - attribute \src "libresoc.v:176568.3-176569.43" + attribute \src "libresoc.v:185597.3-185618.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12459 + attribute \src "libresoc.v:185285.3-185286.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:176880.3-176901.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12395 - attribute \src "libresoc.v:176570.3-176571.49" + attribute \src "libresoc.v:185597.3-185618.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12460 + attribute \src "libresoc.v:185287.3-185288.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:176902.3-176923.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12402 - attribute \src "libresoc.v:176564.3-176565.47" + attribute \src "libresoc.v:185619.3-185640.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12467 + attribute \src "libresoc.v:185281.3-185282.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:176902.3-176923.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12403 - attribute \src "libresoc.v:176566.3-176567.53" + attribute \src "libresoc.v:185619.3-185640.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12468 + attribute \src "libresoc.v:185283.3-185284.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:176992.3-177001.6" + attribute \src "libresoc.v:185709.3-185718.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:177002.3-177011.6" + attribute \src "libresoc.v:185719.3-185728.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:177012.3-177021.6" + attribute \src "libresoc.v:185729.3-185738.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:175863.7-175863.20" + attribute \src "libresoc.v:184574.7-184574.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176775.3-176783.6" - wire $0\opc_l_r_opc$next[0:0]$12330 - attribute \src "libresoc.v:176618.3-176619.39" + attribute \src "libresoc.v:185492.3-185500.6" + wire $0\opc_l_r_opc$next[0:0]$12395 + attribute \src "libresoc.v:185335.3-185336.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:176766.3-176774.6" - wire $0\opc_l_s_opc$next[0:0]$12327 - attribute \src "libresoc.v:176620.3-176621.39" + attribute \src "libresoc.v:185483.3-185491.6" + wire $0\opc_l_s_opc$next[0:0]$12392 + attribute \src "libresoc.v:185337.3-185338.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:177022.3-177030.6" - wire width 3 $0\prev_wr_go$next[2:0]$12434 - attribute \src "libresoc.v:176630.3-176631.37" + attribute \src "libresoc.v:185739.3-185747.6" + wire width 3 $0\prev_wr_go$next[2:0]$12499 + attribute \src "libresoc.v:185347.3-185348.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:176720.3-176729.6" + attribute \src "libresoc.v:185437.3-185446.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:176811.3-176819.6" - wire width 3 $0\req_l_r_req$next[2:0]$12342 - attribute \src "libresoc.v:176610.3-176611.39" + attribute \src "libresoc.v:185528.3-185536.6" + wire width 3 $0\req_l_r_req$next[2:0]$12407 + attribute \src "libresoc.v:185327.3-185328.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:176802.3-176810.6" - wire width 3 $0\req_l_s_req$next[2:0]$12339 - attribute \src "libresoc.v:176612.3-176613.39" + attribute \src "libresoc.v:185519.3-185527.6" + wire width 3 $0\req_l_s_req$next[2:0]$12404 + attribute \src "libresoc.v:185329.3-185330.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:176739.3-176747.6" - wire $0\rok_l_r_rdok$next[0:0]$12318 - attribute \src "libresoc.v:176626.3-176627.41" + attribute \src "libresoc.v:185456.3-185464.6" + wire $0\rok_l_r_rdok$next[0:0]$12383 + attribute \src "libresoc.v:185343.3-185344.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:176730.3-176738.6" - wire $0\rok_l_s_rdok$next[0:0]$12315 - attribute \src "libresoc.v:176628.3-176629.41" + attribute \src "libresoc.v:185447.3-185455.6" + wire $0\rok_l_s_rdok$next[0:0]$12380 + attribute \src "libresoc.v:185345.3-185346.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:176757.3-176765.6" - wire $0\rst_l_r_rst$next[0:0]$12324 - attribute \src "libresoc.v:176622.3-176623.39" + attribute \src "libresoc.v:185474.3-185482.6" + wire $0\rst_l_r_rst$next[0:0]$12389 + attribute \src "libresoc.v:185339.3-185340.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:176748.3-176756.6" - wire $0\rst_l_s_rst$next[0:0]$12321 - attribute \src "libresoc.v:176624.3-176625.39" + attribute \src "libresoc.v:185465.3-185473.6" + wire $0\rst_l_s_rst$next[0:0]$12386 + attribute \src "libresoc.v:185341.3-185342.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:176793.3-176801.6" - wire width 5 $0\src_l_r_src$next[4:0]$12336 - attribute \src "libresoc.v:176614.3-176615.39" + attribute \src "libresoc.v:185510.3-185518.6" + wire width 5 $0\src_l_r_src$next[4:0]$12401 + attribute \src "libresoc.v:185331.3-185332.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:176784.3-176792.6" - wire width 5 $0\src_l_s_src$next[4:0]$12333 - attribute \src "libresoc.v:176616.3-176617.39" + attribute \src "libresoc.v:185501.3-185509.6" + wire width 5 $0\src_l_s_src$next[4:0]$12398 + attribute \src "libresoc.v:185333.3-185334.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:176924.3-176933.6" - wire width 64 $0\src_r0$next[63:0]$12410 - attribute \src "libresoc.v:176562.3-176563.29" + attribute \src "libresoc.v:185641.3-185650.6" + wire width 64 $0\src_r0$next[63:0]$12475 + attribute \src "libresoc.v:185279.3-185280.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:176934.3-176943.6" - wire width 64 $0\src_r1$next[63:0]$12413 - attribute \src "libresoc.v:176560.3-176561.29" + attribute \src "libresoc.v:185651.3-185660.6" + wire width 64 $0\src_r1$next[63:0]$12478 + attribute \src "libresoc.v:185277.3-185278.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:176944.3-176953.6" - wire width 64 $0\src_r2$next[63:0]$12416 - attribute \src "libresoc.v:176558.3-176559.29" + attribute \src "libresoc.v:185661.3-185670.6" + wire width 64 $0\src_r2$next[63:0]$12481 + attribute \src "libresoc.v:185275.3-185276.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:176954.3-176963.6" - wire $0\src_r3$next[0:0]$12419 - attribute \src "libresoc.v:176556.3-176557.29" + attribute \src "libresoc.v:185671.3-185680.6" + wire $0\src_r3$next[0:0]$12484 + attribute \src "libresoc.v:185273.3-185274.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:176964.3-176973.6" - wire width 2 $0\src_r4$next[1:0]$12422 - attribute \src "libresoc.v:176554.3-176555.29" + attribute \src "libresoc.v:185681.3-185690.6" + wire width 2 $0\src_r4$next[1:0]$12487 + attribute \src "libresoc.v:185271.3-185272.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:175985.7-175985.24" + attribute \src "libresoc.v:184696.7-184696.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:175995.7-175995.26" + attribute \src "libresoc.v:184706.7-184706.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:176983.3-176991.6" - wire $1\alu_l_r_alu$next[0:0]$12429 - attribute \src "libresoc.v:176003.7-176003.25" + attribute \src "libresoc.v:185700.3-185708.6" + wire $1\alu_l_r_alu$next[0:0]$12494 + attribute \src "libresoc.v:184714.7-184714.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 12 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12362 - attribute \src "libresoc.v:176044.14-176044.53" - wire width 12 $1\alu_shift_rot0_sr_op__fn_unit[11:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12363 - attribute \src "libresoc.v:176048.14-176048.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 + attribute \src "libresoc.v:184757.14-184757.54" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] + attribute \src "libresoc.v:185537.3-185574.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 + attribute \src "libresoc.v:184761.14-184761.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12364 - attribute \src "libresoc.v:176052.7-176052.48" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 + attribute \src "libresoc.v:184765.7-184765.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12365 - attribute \src "libresoc.v:176060.13-176060.53" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 + attribute \src "libresoc.v:184773.13-184773.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12366 - attribute \src "libresoc.v:176064.7-176064.44" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 + attribute \src "libresoc.v:184777.7-184777.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12367 - attribute \src "libresoc.v:176068.14-176068.48" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 + attribute \src "libresoc.v:184781.14-184781.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12368 - attribute \src "libresoc.v:176146.13-176146.52" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 + attribute \src "libresoc.v:184860.13-184860.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12369 - attribute \src "libresoc.v:176150.7-176150.45" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 + attribute \src "libresoc.v:184864.7-184864.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12370 - attribute \src "libresoc.v:176154.7-176154.44" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 + attribute \src "libresoc.v:184868.7-184868.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12371 - attribute \src "libresoc.v:176158.7-176158.45" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 + attribute \src "libresoc.v:184872.7-184872.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12372 - attribute \src "libresoc.v:176162.7-176162.42" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 + attribute \src "libresoc.v:184876.7-184876.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12373 - attribute \src "libresoc.v:176166.7-176166.42" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 + attribute \src "libresoc.v:184880.7-184880.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12374 - attribute \src "libresoc.v:176170.7-176170.48" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 + attribute \src "libresoc.v:184884.7-184884.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12375 - attribute \src "libresoc.v:176174.7-176174.45" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 + attribute \src "libresoc.v:184888.7-184888.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12376 - attribute \src "libresoc.v:176178.7-176178.42" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 + attribute \src "libresoc.v:184892.7-184892.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12377 - attribute \src "libresoc.v:176182.7-176182.42" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 + attribute \src "libresoc.v:184896.7-184896.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12378 - attribute \src "libresoc.v:176186.7-176186.45" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 + attribute \src "libresoc.v:184900.7-184900.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:176974.3-176982.6" - wire $1\alui_l_r_alui$next[0:0]$12426 - attribute \src "libresoc.v:176198.7-176198.27" + attribute \src "libresoc.v:185691.3-185699.6" + wire $1\alui_l_r_alui$next[0:0]$12491 + attribute \src "libresoc.v:184912.7-184912.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:176858.3-176879.6" - wire width 64 $1\data_r0__o$next[63:0]$12388 - attribute \src "libresoc.v:176232.14-176232.47" + attribute \src "libresoc.v:185575.3-185596.6" + wire width 64 $1\data_r0__o$next[63:0]$12453 + attribute \src "libresoc.v:184946.14-184946.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:176858.3-176879.6" - wire $1\data_r0__o_ok$next[0:0]$12389 - attribute \src "libresoc.v:176236.7-176236.27" + attribute \src "libresoc.v:185575.3-185596.6" + wire $1\data_r0__o_ok$next[0:0]$12454 + attribute \src "libresoc.v:184950.7-184950.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:176880.3-176901.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12396 - attribute \src "libresoc.v:176240.13-176240.33" + attribute \src "libresoc.v:185597.3-185618.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12461 + attribute \src "libresoc.v:184954.13-184954.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:176880.3-176901.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12397 - attribute \src "libresoc.v:176244.7-176244.30" + attribute \src "libresoc.v:185597.3-185618.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12462 + attribute \src "libresoc.v:184958.7-184958.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:176902.3-176923.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12404 - attribute \src "libresoc.v:176248.13-176248.35" + attribute \src "libresoc.v:185619.3-185640.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12469 + attribute \src "libresoc.v:184962.13-184962.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:176902.3-176923.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12405 - attribute \src "libresoc.v:176252.7-176252.32" + attribute \src "libresoc.v:185619.3-185640.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12470 + attribute \src "libresoc.v:184966.7-184966.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:176992.3-177001.6" + attribute \src "libresoc.v:185709.3-185718.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:177002.3-177011.6" + attribute \src "libresoc.v:185719.3-185728.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:177012.3-177021.6" + attribute \src "libresoc.v:185729.3-185738.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:176775.3-176783.6" - wire $1\opc_l_r_opc$next[0:0]$12331 - attribute \src "libresoc.v:176269.7-176269.25" + attribute \src "libresoc.v:185492.3-185500.6" + wire $1\opc_l_r_opc$next[0:0]$12396 + attribute \src "libresoc.v:184983.7-184983.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:176766.3-176774.6" - wire $1\opc_l_s_opc$next[0:0]$12328 - attribute \src "libresoc.v:176273.7-176273.25" + attribute \src "libresoc.v:185483.3-185491.6" + wire $1\opc_l_s_opc$next[0:0]$12393 + attribute \src "libresoc.v:184987.7-184987.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:177022.3-177030.6" - wire width 3 $1\prev_wr_go$next[2:0]$12435 - attribute \src "libresoc.v:176402.13-176402.30" + attribute \src "libresoc.v:185739.3-185747.6" + wire width 3 $1\prev_wr_go$next[2:0]$12500 + attribute \src "libresoc.v:185119.13-185119.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:176720.3-176729.6" + attribute \src "libresoc.v:185437.3-185446.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:176811.3-176819.6" - wire width 3 $1\req_l_r_req$next[2:0]$12343 - attribute \src "libresoc.v:176410.13-176410.31" + attribute \src "libresoc.v:185528.3-185536.6" + wire width 3 $1\req_l_r_req$next[2:0]$12408 + attribute \src "libresoc.v:185127.13-185127.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:176802.3-176810.6" - wire width 3 $1\req_l_s_req$next[2:0]$12340 - attribute \src "libresoc.v:176414.13-176414.31" + attribute \src "libresoc.v:185519.3-185527.6" + wire width 3 $1\req_l_s_req$next[2:0]$12405 + attribute \src "libresoc.v:185131.13-185131.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:176739.3-176747.6" - wire $1\rok_l_r_rdok$next[0:0]$12319 - attribute \src "libresoc.v:176426.7-176426.26" + attribute \src "libresoc.v:185456.3-185464.6" + wire $1\rok_l_r_rdok$next[0:0]$12384 + attribute \src "libresoc.v:185143.7-185143.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:176730.3-176738.6" - wire $1\rok_l_s_rdok$next[0:0]$12316 - attribute \src "libresoc.v:176430.7-176430.26" + attribute \src "libresoc.v:185447.3-185455.6" + wire $1\rok_l_s_rdok$next[0:0]$12381 + attribute \src "libresoc.v:185147.7-185147.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:176757.3-176765.6" - wire $1\rst_l_r_rst$next[0:0]$12325 - attribute \src "libresoc.v:176434.7-176434.25" + attribute \src "libresoc.v:185474.3-185482.6" + wire $1\rst_l_r_rst$next[0:0]$12390 + attribute \src "libresoc.v:185151.7-185151.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:176748.3-176756.6" - wire $1\rst_l_s_rst$next[0:0]$12322 - attribute \src "libresoc.v:176438.7-176438.25" + attribute \src "libresoc.v:185465.3-185473.6" + wire $1\rst_l_s_rst$next[0:0]$12387 + attribute \src "libresoc.v:185155.7-185155.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:176793.3-176801.6" - wire width 5 $1\src_l_r_src$next[4:0]$12337 - attribute \src "libresoc.v:176456.13-176456.32" + attribute \src "libresoc.v:185510.3-185518.6" + wire width 5 $1\src_l_r_src$next[4:0]$12402 + attribute \src "libresoc.v:185173.13-185173.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:176784.3-176792.6" - wire width 5 $1\src_l_s_src$next[4:0]$12334 - attribute \src "libresoc.v:176460.13-176460.32" + attribute \src "libresoc.v:185501.3-185509.6" + wire width 5 $1\src_l_s_src$next[4:0]$12399 + attribute \src "libresoc.v:185177.13-185177.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:176924.3-176933.6" - wire width 64 $1\src_r0$next[63:0]$12411 - attribute \src "libresoc.v:176466.14-176466.43" + attribute \src "libresoc.v:185641.3-185650.6" + wire width 64 $1\src_r0$next[63:0]$12476 + attribute \src "libresoc.v:185183.14-185183.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:176934.3-176943.6" - wire width 64 $1\src_r1$next[63:0]$12414 - attribute \src "libresoc.v:176470.14-176470.43" + attribute \src "libresoc.v:185651.3-185660.6" + wire width 64 $1\src_r1$next[63:0]$12479 + attribute \src "libresoc.v:185187.14-185187.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:176944.3-176953.6" - wire width 64 $1\src_r2$next[63:0]$12417 - attribute \src "libresoc.v:176474.14-176474.43" + attribute \src "libresoc.v:185661.3-185670.6" + wire width 64 $1\src_r2$next[63:0]$12482 + attribute \src "libresoc.v:185191.14-185191.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:176954.3-176963.6" - wire $1\src_r3$next[0:0]$12420 - attribute \src "libresoc.v:176478.7-176478.20" + attribute \src "libresoc.v:185671.3-185680.6" + wire $1\src_r3$next[0:0]$12485 + attribute \src "libresoc.v:185195.7-185195.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:176964.3-176973.6" - wire width 2 $1\src_r4$next[1:0]$12423 - attribute \src "libresoc.v:176482.13-176482.26" + attribute \src "libresoc.v:185681.3-185690.6" + wire width 2 $1\src_r4$next[1:0]$12488 + attribute \src "libresoc.v:185199.13-185199.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:176820.3-176857.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12379 - attribute \src "libresoc.v:176820.3-176857.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12380 - attribute \src "libresoc.v:176820.3-176857.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12381 - attribute \src "libresoc.v:176820.3-176857.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12382 - attribute \src "libresoc.v:176820.3-176857.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12383 - attribute \src "libresoc.v:176820.3-176857.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12384 - attribute \src "libresoc.v:176858.3-176879.6" - wire width 64 $2\data_r0__o$next[63:0]$12390 - attribute \src "libresoc.v:176858.3-176879.6" - wire $2\data_r0__o_ok$next[0:0]$12391 - attribute \src "libresoc.v:176880.3-176901.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12398 - attribute \src "libresoc.v:176880.3-176901.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12399 - attribute \src "libresoc.v:176902.3-176923.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12406 - attribute \src "libresoc.v:176902.3-176923.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12407 - attribute \src "libresoc.v:176858.3-176879.6" - wire $3\data_r0__o_ok$next[0:0]$12392 - attribute \src "libresoc.v:176880.3-176901.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12400 - attribute \src "libresoc.v:176902.3-176923.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12408 - attribute \src "libresoc.v:176492.19-176492.114" - wire width 5 $and$libresoc.v:176492$12212_Y - attribute \src "libresoc.v:176493.19-176493.125" - wire $and$libresoc.v:176493$12213_Y - attribute \src "libresoc.v:176494.19-176494.125" - wire $and$libresoc.v:176494$12214_Y - attribute \src "libresoc.v:176495.19-176495.125" - wire $and$libresoc.v:176495$12215_Y - attribute \src "libresoc.v:176496.18-176496.110" - wire $and$libresoc.v:176496$12216_Y - attribute \src "libresoc.v:176497.19-176497.141" - wire width 3 $and$libresoc.v:176497$12217_Y - attribute \src "libresoc.v:176498.19-176498.121" - wire width 3 $and$libresoc.v:176498$12218_Y - attribute \src "libresoc.v:176499.19-176499.127" - wire $and$libresoc.v:176499$12219_Y - attribute \src "libresoc.v:176500.19-176500.127" - wire $and$libresoc.v:176500$12220_Y - attribute \src "libresoc.v:176501.19-176501.127" - wire $and$libresoc.v:176501$12221_Y - attribute \src "libresoc.v:176503.18-176503.98" - wire $and$libresoc.v:176503$12223_Y - attribute \src "libresoc.v:176505.18-176505.100" - wire $and$libresoc.v:176505$12225_Y - attribute \src "libresoc.v:176506.18-176506.149" - wire width 3 $and$libresoc.v:176506$12226_Y - attribute \src "libresoc.v:176508.18-176508.119" - wire width 3 $and$libresoc.v:176508$12228_Y - attribute \src "libresoc.v:176511.17-176511.123" - wire $and$libresoc.v:176511$12231_Y - attribute \src "libresoc.v:176512.18-176512.116" - wire $and$libresoc.v:176512$12232_Y - attribute \src "libresoc.v:176517.18-176517.113" - wire $and$libresoc.v:176517$12237_Y - attribute \src "libresoc.v:176518.18-176518.125" - wire width 3 $and$libresoc.v:176518$12238_Y - attribute \src "libresoc.v:176520.18-176520.112" - wire $and$libresoc.v:176520$12240_Y - attribute \src "libresoc.v:176522.18-176522.132" - wire $and$libresoc.v:176522$12242_Y - attribute \src "libresoc.v:176523.18-176523.132" - wire $and$libresoc.v:176523$12243_Y - attribute \src "libresoc.v:176524.18-176524.117" - wire $and$libresoc.v:176524$12244_Y - attribute \src "libresoc.v:176530.18-176530.136" - wire $and$libresoc.v:176530$12250_Y - attribute \src "libresoc.v:176531.18-176531.124" - wire width 3 $and$libresoc.v:176531$12251_Y - attribute \src "libresoc.v:176533.18-176533.116" - wire $and$libresoc.v:176533$12253_Y - attribute \src "libresoc.v:176534.18-176534.119" - wire $and$libresoc.v:176534$12254_Y - attribute \src "libresoc.v:176535.18-176535.121" - wire $and$libresoc.v:176535$12255_Y - attribute \src "libresoc.v:176545.18-176545.140" - wire $and$libresoc.v:176545$12265_Y - attribute \src "libresoc.v:176546.18-176546.138" - wire $and$libresoc.v:176546$12266_Y - attribute \src "libresoc.v:176547.18-176547.171" - wire width 5 $and$libresoc.v:176547$12267_Y - attribute \src "libresoc.v:176549.18-176549.129" - wire width 5 $and$libresoc.v:176549$12269_Y - attribute \src "libresoc.v:176519.18-176519.113" - wire $eq$libresoc.v:176519$12239_Y - attribute \src "libresoc.v:176521.18-176521.119" - wire $eq$libresoc.v:176521$12241_Y - attribute \src "libresoc.v:176491.19-176491.115" - wire width 5 $not$libresoc.v:176491$12211_Y - attribute \src "libresoc.v:176502.18-176502.97" - wire $not$libresoc.v:176502$12222_Y - attribute \src "libresoc.v:176504.18-176504.99" - wire $not$libresoc.v:176504$12224_Y - attribute \src "libresoc.v:176507.18-176507.113" - wire width 3 $not$libresoc.v:176507$12227_Y - attribute \src "libresoc.v:176510.18-176510.106" - wire $not$libresoc.v:176510$12230_Y - attribute \src "libresoc.v:176516.18-176516.126" - wire $not$libresoc.v:176516$12236_Y - attribute \src "libresoc.v:176527.17-176527.113" - wire width 5 $not$libresoc.v:176527$12247_Y - attribute \src "libresoc.v:176548.18-176548.136" - wire $not$libresoc.v:176548$12268_Y - attribute \src "libresoc.v:176515.18-176515.112" - wire $or$libresoc.v:176515$12235_Y - attribute \src "libresoc.v:176525.18-176525.122" - wire $or$libresoc.v:176525$12245_Y - attribute \src "libresoc.v:176526.18-176526.124" - wire $or$libresoc.v:176526$12246_Y - attribute \src "libresoc.v:176528.18-176528.155" - wire width 3 $or$libresoc.v:176528$12248_Y - attribute \src "libresoc.v:176529.18-176529.181" - wire width 5 $or$libresoc.v:176529$12249_Y - attribute \src "libresoc.v:176532.18-176532.120" - wire width 3 $or$libresoc.v:176532$12252_Y - attribute \src "libresoc.v:176538.17-176538.117" - wire width 5 $or$libresoc.v:176538$12258_Y - attribute \src "libresoc.v:176544.17-176544.104" - wire $reduce_and$libresoc.v:176544$12264_Y - attribute \src "libresoc.v:176509.18-176509.106" - wire $reduce_or$libresoc.v:176509$12229_Y - attribute \src "libresoc.v:176513.18-176513.113" - wire $reduce_or$libresoc.v:176513$12233_Y - attribute \src "libresoc.v:176514.18-176514.112" - wire $reduce_or$libresoc.v:176514$12234_Y - attribute \src "libresoc.v:176536.18-176536.165" - wire $ternary$libresoc.v:176536$12256_Y - attribute \src "libresoc.v:176537.18-176537.182" - wire width 64 $ternary$libresoc.v:176537$12257_Y - attribute \src "libresoc.v:176539.18-176539.118" - wire width 64 $ternary$libresoc.v:176539$12259_Y - attribute \src "libresoc.v:176540.18-176540.115" - wire width 64 $ternary$libresoc.v:176540$12260_Y - attribute \src "libresoc.v:176541.18-176541.118" - wire width 64 $ternary$libresoc.v:176541$12261_Y - attribute \src "libresoc.v:176542.18-176542.118" - wire $ternary$libresoc.v:176542$12262_Y - attribute \src "libresoc.v:176543.18-176543.118" - wire width 2 $ternary$libresoc.v:176543$12263_Y + attribute \src "libresoc.v:185537.3-185574.6" + wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 + attribute \src "libresoc.v:185575.3-185596.6" + wire width 64 $2\data_r0__o$next[63:0]$12455 + attribute \src "libresoc.v:185575.3-185596.6" + wire $2\data_r0__o_ok$next[0:0]$12456 + attribute \src "libresoc.v:185597.3-185618.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12463 + attribute \src "libresoc.v:185597.3-185618.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12464 + attribute \src "libresoc.v:185619.3-185640.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12471 + attribute \src "libresoc.v:185619.3-185640.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12472 + attribute \src "libresoc.v:185575.3-185596.6" + wire $3\data_r0__o_ok$next[0:0]$12457 + attribute \src "libresoc.v:185597.3-185618.6" + wire $3\data_r1__cr_a_ok$next[0:0]$12465 + attribute \src "libresoc.v:185619.3-185640.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$12473 + attribute \src "libresoc.v:185209.19-185209.114" + wire width 5 $and$libresoc.v:185209$12277_Y + attribute \src "libresoc.v:185210.19-185210.125" + wire $and$libresoc.v:185210$12278_Y + attribute \src "libresoc.v:185211.19-185211.125" + wire $and$libresoc.v:185211$12279_Y + attribute \src "libresoc.v:185212.19-185212.125" + wire $and$libresoc.v:185212$12280_Y + attribute \src "libresoc.v:185213.18-185213.110" + wire $and$libresoc.v:185213$12281_Y + attribute \src "libresoc.v:185214.19-185214.141" + wire width 3 $and$libresoc.v:185214$12282_Y + attribute \src "libresoc.v:185215.19-185215.121" + wire width 3 $and$libresoc.v:185215$12283_Y + attribute \src "libresoc.v:185216.19-185216.127" + wire $and$libresoc.v:185216$12284_Y + attribute \src "libresoc.v:185217.19-185217.127" + wire $and$libresoc.v:185217$12285_Y + attribute \src "libresoc.v:185218.19-185218.127" + wire $and$libresoc.v:185218$12286_Y + attribute \src "libresoc.v:185220.18-185220.98" + wire $and$libresoc.v:185220$12288_Y + attribute \src "libresoc.v:185222.18-185222.100" + wire $and$libresoc.v:185222$12290_Y + attribute \src "libresoc.v:185223.18-185223.149" + wire width 3 $and$libresoc.v:185223$12291_Y + attribute \src "libresoc.v:185225.18-185225.119" + wire width 3 $and$libresoc.v:185225$12293_Y + attribute \src "libresoc.v:185228.17-185228.123" + wire $and$libresoc.v:185228$12296_Y + attribute \src "libresoc.v:185229.18-185229.116" + wire $and$libresoc.v:185229$12297_Y + attribute \src "libresoc.v:185234.18-185234.113" + wire $and$libresoc.v:185234$12302_Y + attribute \src "libresoc.v:185235.18-185235.125" + wire width 3 $and$libresoc.v:185235$12303_Y + attribute \src "libresoc.v:185237.18-185237.112" + wire $and$libresoc.v:185237$12305_Y + attribute \src "libresoc.v:185239.18-185239.132" + wire $and$libresoc.v:185239$12307_Y + attribute \src "libresoc.v:185240.18-185240.132" + wire $and$libresoc.v:185240$12308_Y + attribute \src "libresoc.v:185241.18-185241.117" + wire $and$libresoc.v:185241$12309_Y + attribute \src "libresoc.v:185247.18-185247.136" + wire $and$libresoc.v:185247$12315_Y + attribute \src "libresoc.v:185248.18-185248.124" + wire width 3 $and$libresoc.v:185248$12316_Y + attribute \src "libresoc.v:185250.18-185250.116" + wire $and$libresoc.v:185250$12318_Y + attribute \src "libresoc.v:185251.18-185251.119" + wire $and$libresoc.v:185251$12319_Y + attribute \src "libresoc.v:185252.18-185252.121" + wire $and$libresoc.v:185252$12320_Y + attribute \src "libresoc.v:185262.18-185262.140" + wire $and$libresoc.v:185262$12330_Y + attribute \src "libresoc.v:185263.18-185263.138" + wire $and$libresoc.v:185263$12331_Y + attribute \src "libresoc.v:185264.18-185264.171" + wire width 5 $and$libresoc.v:185264$12332_Y + attribute \src "libresoc.v:185266.18-185266.129" + wire width 5 $and$libresoc.v:185266$12334_Y + attribute \src "libresoc.v:185236.18-185236.113" + wire $eq$libresoc.v:185236$12304_Y + attribute \src "libresoc.v:185238.18-185238.119" + wire $eq$libresoc.v:185238$12306_Y + attribute \src "libresoc.v:185208.19-185208.115" + wire width 5 $not$libresoc.v:185208$12276_Y + attribute \src "libresoc.v:185219.18-185219.97" + wire $not$libresoc.v:185219$12287_Y + attribute \src "libresoc.v:185221.18-185221.99" + wire $not$libresoc.v:185221$12289_Y + attribute \src "libresoc.v:185224.18-185224.113" + wire width 3 $not$libresoc.v:185224$12292_Y + attribute \src "libresoc.v:185227.18-185227.106" + wire $not$libresoc.v:185227$12295_Y + attribute \src "libresoc.v:185233.18-185233.126" + wire $not$libresoc.v:185233$12301_Y + attribute \src "libresoc.v:185244.17-185244.113" + wire width 5 $not$libresoc.v:185244$12312_Y + attribute \src "libresoc.v:185265.18-185265.136" + wire $not$libresoc.v:185265$12333_Y + attribute \src "libresoc.v:185232.18-185232.112" + wire $or$libresoc.v:185232$12300_Y + attribute \src "libresoc.v:185242.18-185242.122" + wire $or$libresoc.v:185242$12310_Y + attribute \src "libresoc.v:185243.18-185243.124" + wire $or$libresoc.v:185243$12311_Y + attribute \src "libresoc.v:185245.18-185245.155" + wire width 3 $or$libresoc.v:185245$12313_Y + attribute \src "libresoc.v:185246.18-185246.181" + wire width 5 $or$libresoc.v:185246$12314_Y + attribute \src "libresoc.v:185249.18-185249.120" + wire width 3 $or$libresoc.v:185249$12317_Y + attribute \src "libresoc.v:185255.17-185255.117" + wire width 5 $or$libresoc.v:185255$12323_Y + attribute \src "libresoc.v:185261.17-185261.104" + wire $reduce_and$libresoc.v:185261$12329_Y + attribute \src "libresoc.v:185226.18-185226.106" + wire $reduce_or$libresoc.v:185226$12294_Y + attribute \src "libresoc.v:185230.18-185230.113" + wire $reduce_or$libresoc.v:185230$12298_Y + attribute \src "libresoc.v:185231.18-185231.112" + wire $reduce_or$libresoc.v:185231$12299_Y + attribute \src "libresoc.v:185253.18-185253.165" + wire $ternary$libresoc.v:185253$12321_Y + attribute \src "libresoc.v:185254.18-185254.182" + wire width 64 $ternary$libresoc.v:185254$12322_Y + attribute \src "libresoc.v:185256.18-185256.118" + wire width 64 $ternary$libresoc.v:185256$12324_Y + attribute \src "libresoc.v:185257.18-185257.115" + wire width 64 $ternary$libresoc.v:185257$12325_Y + attribute \src "libresoc.v:185258.18-185258.118" + wire width 64 $ternary$libresoc.v:185258$12326_Y + attribute \src "libresoc.v:185259.18-185259.118" + wire $ternary$libresoc.v:185259$12327_Y + attribute \src "libresoc.v:185260.18-185260.118" + wire width 2 $ternary$libresoc.v:185260$12328_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -369308,13 +384311,13 @@ module \shiftrot0 wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$118 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$2 @@ -369384,15 +384387,15 @@ module \shiftrot0 wire \$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$78 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$80 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$82 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$84 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 2 \$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$90 @@ -369406,29 +384409,29 @@ module \shiftrot0 wire width 5 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse @@ -369436,15 +384439,15 @@ module \shiftrot0 wire width 3 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_shift_rot0_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_shift_rot0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_shift_rot0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_shift_rot0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_shift_rot0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_shift_rot0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_shift_rot0_ra @@ -369453,22 +384456,24 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_shift_rot0_rc attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_shift_rot0_sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_shift_rot0_sr_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_shift_rot0_sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_shift_rot0_sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_shift_rot0_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -369567,6 +384572,7 @@ module \shiftrot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_shift_rot0_sr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -369617,17 +384623,17 @@ module \shiftrot0 wire width 2 \alu_shift_rot0_xer_ca$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_shift_rot0_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -369683,35 +384689,37 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:175863.7-175863.15" + attribute \src "libresoc.v:184574.7-184574.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_shift_rot0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -369800,6 +384808,7 @@ module \shiftrot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -369828,15 +384837,15 @@ module \shiftrot0 wire width 3 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -369844,23 +384853,23 @@ module \shiftrot0 wire width 5 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -369874,37 +384883,37 @@ module \shiftrot0 wire input 27 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 28 \src5_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel @@ -369913,7 +384922,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:176492$12212 + cell $and $and$libresoc.v:185209$12277 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -369921,10 +384930,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:176492$12212_Y + connect \Y $and$libresoc.v:185209$12277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:176493$12213 + cell $and $and$libresoc.v:185210$12278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -369932,10 +384941,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:176493$12213_Y + connect \Y $and$libresoc.v:185210$12278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:176494$12214 + cell $and $and$libresoc.v:185211$12279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -369943,10 +384952,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:176494$12214_Y + connect \Y $and$libresoc.v:185211$12279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:176495$12215 + cell $and $and$libresoc.v:185212$12280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -369954,10 +384963,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:176495$12215_Y + connect \Y $and$libresoc.v:185212$12280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:176496$12216 + cell $and $and$libresoc.v:185213$12281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -369965,10 +384974,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:176496$12216_Y + connect \Y $and$libresoc.v:185213$12281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:176497$12217 + cell $and $and$libresoc.v:185214$12282 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -369976,10 +384985,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:176497$12217_Y + connect \Y $and$libresoc.v:185214$12282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:176498$12218 + cell $and $and$libresoc.v:185215$12283 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -369987,10 +384996,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:176498$12218_Y + connect \Y $and$libresoc.v:185215$12283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:176499$12219 + cell $and $and$libresoc.v:185216$12284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -369998,10 +385007,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:176499$12219_Y + connect \Y $and$libresoc.v:185216$12284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:176500$12220 + cell $and $and$libresoc.v:185217$12285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370009,10 +385018,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:176500$12220_Y + connect \Y $and$libresoc.v:185217$12285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:176501$12221 + cell $and $and$libresoc.v:185218$12286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370020,10 +385029,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:176501$12221_Y + connect \Y $and$libresoc.v:185218$12286_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:176503$12223 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:185220$12288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370031,10 +385040,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:176503$12223_Y + connect \Y $and$libresoc.v:185220$12288_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:176505$12225 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:185222$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370042,10 +385051,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:176505$12225_Y + connect \Y $and$libresoc.v:185222$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:176506$12226 + cell $and $and$libresoc.v:185223$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -370053,10 +385062,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:176506$12226_Y + connect \Y $and$libresoc.v:185223$12291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:176508$12228 + cell $and $and$libresoc.v:185225$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -370064,10 +385073,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:176508$12228_Y + connect \Y $and$libresoc.v:185225$12293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:176511$12231 + cell $and $and$libresoc.v:185228$12296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370075,10 +385084,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:176511$12231_Y + connect \Y $and$libresoc.v:185228$12296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:176512$12232 + cell $and $and$libresoc.v:185229$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370086,10 +385095,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:176512$12232_Y + connect \Y $and$libresoc.v:185229$12297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:176517$12237 + cell $and $and$libresoc.v:185234$12302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370097,10 +385106,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:176517$12237_Y + connect \Y $and$libresoc.v:185234$12302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:176518$12238 + cell $and $and$libresoc.v:185235$12303 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -370108,10 +385117,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:176518$12238_Y + connect \Y $and$libresoc.v:185235$12303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:176520$12240 + cell $and $and$libresoc.v:185237$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370119,10 +385128,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:176520$12240_Y + connect \Y $and$libresoc.v:185237$12305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:176522$12242 + cell $and $and$libresoc.v:185239$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370130,10 +385139,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:176522$12242_Y + connect \Y $and$libresoc.v:185239$12307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:176523$12243 + cell $and $and$libresoc.v:185240$12308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370141,10 +385150,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:176523$12243_Y + connect \Y $and$libresoc.v:185240$12308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:176524$12244 + cell $and $and$libresoc.v:185241$12309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370152,10 +385161,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:176524$12244_Y + connect \Y $and$libresoc.v:185241$12309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:176530$12250 + cell $and $and$libresoc.v:185247$12315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370163,10 +385172,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:176530$12250_Y + connect \Y $and$libresoc.v:185247$12315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:176531$12251 + cell $and $and$libresoc.v:185248$12316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -370174,10 +385183,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:176531$12251_Y + connect \Y $and$libresoc.v:185248$12316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:176533$12253 + cell $and $and$libresoc.v:185250$12318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370185,10 +385194,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:176533$12253_Y + connect \Y $and$libresoc.v:185250$12318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:176534$12254 + cell $and $and$libresoc.v:185251$12319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370196,10 +385205,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:176534$12254_Y + connect \Y $and$libresoc.v:185251$12319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:176535$12255 + cell $and $and$libresoc.v:185252$12320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370207,10 +385216,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:176535$12255_Y + connect \Y $and$libresoc.v:185252$12320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:176545$12265 + cell $and $and$libresoc.v:185262$12330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370218,10 +385227,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:176545$12265_Y + connect \Y $and$libresoc.v:185262$12330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:176546$12266 + cell $and $and$libresoc.v:185263$12331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370229,10 +385238,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:176546$12266_Y + connect \Y $and$libresoc.v:185263$12331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:176547$12267 + cell $and $and$libresoc.v:185264$12332 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -370240,10 +385249,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:176547$12267_Y + connect \Y $and$libresoc.v:185264$12332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:176549$12269 + cell $and $and$libresoc.v:185266$12334 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -370251,10 +385260,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:176549$12269_Y + connect \Y $and$libresoc.v:185266$12334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:176519$12239 + cell $eq $eq$libresoc.v:185236$12304 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -370262,10 +385271,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:176519$12239_Y + connect \Y $eq$libresoc.v:185236$12304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:176521$12241 + cell $eq $eq$libresoc.v:185238$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -370273,74 +385282,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:176521$12241_Y + connect \Y $eq$libresoc.v:185238$12306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:176491$12211 + cell $not $not$libresoc.v:185208$12276 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:176491$12211_Y + connect \Y $not$libresoc.v:185208$12276_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:176502$12222 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:185219$12287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:176502$12222_Y + connect \Y $not$libresoc.v:185219$12287_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:176504$12224 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:185221$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:176504$12224_Y + connect \Y $not$libresoc.v:185221$12289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:176507$12227 + cell $not $not$libresoc.v:185224$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:176507$12227_Y + connect \Y $not$libresoc.v:185224$12292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:176510$12230 + cell $not $not$libresoc.v:185227$12295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:176510$12230_Y + connect \Y $not$libresoc.v:185227$12295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:176516$12236 + cell $not $not$libresoc.v:185233$12301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:176516$12236_Y + connect \Y $not$libresoc.v:185233$12301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:176527$12247 + cell $not $not$libresoc.v:185244$12312 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:176527$12247_Y + connect \Y $not$libresoc.v:185244$12312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:176548$12268 + cell $not $not$libresoc.v:185265$12333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:176548$12268_Y + connect \Y $not$libresoc.v:185265$12333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:176515$12235 + cell $or $or$libresoc.v:185232$12300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370348,10 +385357,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:176515$12235_Y + connect \Y $or$libresoc.v:185232$12300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:176525$12245 + cell $or $or$libresoc.v:185242$12310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370359,10 +385368,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:176525$12245_Y + connect \Y $or$libresoc.v:185242$12310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:176526$12246 + cell $or $or$libresoc.v:185243$12311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -370370,10 +385379,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:176526$12246_Y + connect \Y $or$libresoc.v:185243$12311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:176528$12248 + cell $or $or$libresoc.v:185245$12313 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -370381,10 +385390,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:176528$12248_Y + connect \Y $or$libresoc.v:185245$12313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:176529$12249 + cell $or $or$libresoc.v:185246$12314 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -370392,10 +385401,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:176529$12249_Y + connect \Y $or$libresoc.v:185246$12314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:176532$12252 + cell $or $or$libresoc.v:185249$12317 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -370403,10 +385412,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:176532$12252_Y + connect \Y $or$libresoc.v:185249$12317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:176538$12258 + cell $or $or$libresoc.v:185255$12323 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -370414,98 +385423,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:176538$12258_Y + connect \Y $or$libresoc.v:185255$12323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:176544$12264 + cell $reduce_and $reduce_and$libresoc.v:185261$12329 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:176544$12264_Y + connect \Y $reduce_and$libresoc.v:185261$12329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:176509$12229 + cell $reduce_or $reduce_or$libresoc.v:185226$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:176509$12229_Y + connect \Y $reduce_or$libresoc.v:185226$12294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:176513$12233 + cell $reduce_or $reduce_or$libresoc.v:185230$12298 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:176513$12233_Y + connect \Y $reduce_or$libresoc.v:185230$12298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:176514$12234 + cell $reduce_or $reduce_or$libresoc.v:185231$12299 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:176514$12234_Y + connect \Y $reduce_or$libresoc.v:185231$12299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:176536$12256 + cell $mux $ternary$libresoc.v:185253$12321 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:176536$12256_Y + connect \Y $ternary$libresoc.v:185253$12321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:176537$12257 + cell $mux $ternary$libresoc.v:185254$12322 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:176537$12257_Y + connect \Y $ternary$libresoc.v:185254$12322_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176539$12259 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:185256$12324 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:176539$12259_Y + connect \Y $ternary$libresoc.v:185256$12324_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176540$12260 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:185257$12325 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:176540$12260_Y + connect \Y $ternary$libresoc.v:185257$12325_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176541$12261 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:185258$12326 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:176541$12261_Y + connect \Y $ternary$libresoc.v:185258$12326_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176542$12262 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:185259$12327 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:176542$12262_Y + connect \Y $ternary$libresoc.v:185259$12327_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176543$12263 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:185260$12328 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:176543$12263_Y + connect \Y $ternary$libresoc.v:185260$12328_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:176636.15-176642.4" + attribute \src "libresoc.v:185353.15-185359.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -370514,7 +385523,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:176643.18-176678.4" + attribute \src "libresoc.v:185360.18-185395.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -370552,7 +385561,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:176679.16-176685.4" + attribute \src "libresoc.v:185396.16-185402.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -370561,7 +385570,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:176686.15-176692.4" + attribute \src "libresoc.v:185403.15-185409.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -370570,7 +385579,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:176693.15-176699.4" + attribute \src "libresoc.v:185410.15-185416.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -370579,7 +385588,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:176700.15-176706.4" + attribute \src "libresoc.v:185417.15-185423.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -370588,7 +385597,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:176707.15-176712.4" + attribute \src "libresoc.v:185424.15-185429.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -370596,7 +385605,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:176713.15-176719.4" + attribute \src "libresoc.v:185430.15-185436.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -370604,667 +385613,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:175863.7-175863.20" - process $proc$libresoc.v:175863$12436 + attribute \src "libresoc.v:184574.7-184574.20" + process $proc$libresoc.v:184574$12501 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175985.7-175985.24" - process $proc$libresoc.v:175985$12437 + attribute \src "libresoc.v:184696.7-184696.24" + process $proc$libresoc.v:184696$12502 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:175995.7-175995.26" - process $proc$libresoc.v:175995$12438 + attribute \src "libresoc.v:184706.7-184706.26" + process $proc$libresoc.v:184706$12503 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:176003.7-176003.25" - process $proc$libresoc.v:176003$12439 + attribute \src "libresoc.v:184714.7-184714.25" + process $proc$libresoc.v:184714$12504 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:176044.14-176044.53" - process $proc$libresoc.v:176044$12440 + attribute \src "libresoc.v:184757.14-184757.54" + process $proc$libresoc.v:184757$12505 assign { } { } - assign $1\alu_shift_rot0_sr_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[11:0] + update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:176048.14-176048.73" - process $proc$libresoc.v:176048$12441 + attribute \src "libresoc.v:184761.14-184761.73" + process $proc$libresoc.v:184761$12506 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:176052.7-176052.48" - process $proc$libresoc.v:176052$12442 + attribute \src "libresoc.v:184765.7-184765.48" + process $proc$libresoc.v:184765$12507 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:176060.13-176060.53" - process $proc$libresoc.v:176060$12443 + attribute \src "libresoc.v:184773.13-184773.53" + process $proc$libresoc.v:184773$12508 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:176064.7-176064.44" - process $proc$libresoc.v:176064$12444 + attribute \src "libresoc.v:184777.7-184777.44" + process $proc$libresoc.v:184777$12509 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:176068.14-176068.48" - process $proc$libresoc.v:176068$12445 + attribute \src "libresoc.v:184781.14-184781.48" + process $proc$libresoc.v:184781$12510 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:176146.13-176146.52" - process $proc$libresoc.v:176146$12446 + attribute \src "libresoc.v:184860.13-184860.52" + process $proc$libresoc.v:184860$12511 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:176150.7-176150.45" - process $proc$libresoc.v:176150$12447 + attribute \src "libresoc.v:184864.7-184864.45" + process $proc$libresoc.v:184864$12512 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:176154.7-176154.44" - process $proc$libresoc.v:176154$12448 + attribute \src "libresoc.v:184868.7-184868.44" + process $proc$libresoc.v:184868$12513 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:176158.7-176158.45" - process $proc$libresoc.v:176158$12449 + attribute \src "libresoc.v:184872.7-184872.45" + process $proc$libresoc.v:184872$12514 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:176162.7-176162.42" - process $proc$libresoc.v:176162$12450 + attribute \src "libresoc.v:184876.7-184876.42" + process $proc$libresoc.v:184876$12515 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:176166.7-176166.42" - process $proc$libresoc.v:176166$12451 + attribute \src "libresoc.v:184880.7-184880.42" + process $proc$libresoc.v:184880$12516 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:176170.7-176170.48" - process $proc$libresoc.v:176170$12452 + attribute \src "libresoc.v:184884.7-184884.48" + process $proc$libresoc.v:184884$12517 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:176174.7-176174.45" - process $proc$libresoc.v:176174$12453 + attribute \src "libresoc.v:184888.7-184888.45" + process $proc$libresoc.v:184888$12518 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:176178.7-176178.42" - process $proc$libresoc.v:176178$12454 + attribute \src "libresoc.v:184892.7-184892.42" + process $proc$libresoc.v:184892$12519 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:176182.7-176182.42" - process $proc$libresoc.v:176182$12455 + attribute \src "libresoc.v:184896.7-184896.42" + process $proc$libresoc.v:184896$12520 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:176186.7-176186.45" - process $proc$libresoc.v:176186$12456 + attribute \src "libresoc.v:184900.7-184900.45" + process $proc$libresoc.v:184900$12521 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:176198.7-176198.27" - process $proc$libresoc.v:176198$12457 + attribute \src "libresoc.v:184912.7-184912.27" + process $proc$libresoc.v:184912$12522 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:176232.14-176232.47" - process $proc$libresoc.v:176232$12458 + attribute \src "libresoc.v:184946.14-184946.47" + process $proc$libresoc.v:184946$12523 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:176236.7-176236.27" - process $proc$libresoc.v:176236$12459 + attribute \src "libresoc.v:184950.7-184950.27" + process $proc$libresoc.v:184950$12524 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:176240.13-176240.33" - process $proc$libresoc.v:176240$12460 + attribute \src "libresoc.v:184954.13-184954.33" + process $proc$libresoc.v:184954$12525 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:176244.7-176244.30" - process $proc$libresoc.v:176244$12461 + attribute \src "libresoc.v:184958.7-184958.30" + process $proc$libresoc.v:184958$12526 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:176248.13-176248.35" - process $proc$libresoc.v:176248$12462 + attribute \src "libresoc.v:184962.13-184962.35" + process $proc$libresoc.v:184962$12527 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:176252.7-176252.32" - process $proc$libresoc.v:176252$12463 + attribute \src "libresoc.v:184966.7-184966.32" + process $proc$libresoc.v:184966$12528 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:176269.7-176269.25" - process $proc$libresoc.v:176269$12464 + attribute \src "libresoc.v:184983.7-184983.25" + process $proc$libresoc.v:184983$12529 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:176273.7-176273.25" - process $proc$libresoc.v:176273$12465 + attribute \src "libresoc.v:184987.7-184987.25" + process $proc$libresoc.v:184987$12530 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:176402.13-176402.30" - process $proc$libresoc.v:176402$12466 + attribute \src "libresoc.v:185119.13-185119.30" + process $proc$libresoc.v:185119$12531 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:176410.13-176410.31" - process $proc$libresoc.v:176410$12467 + attribute \src "libresoc.v:185127.13-185127.31" + process $proc$libresoc.v:185127$12532 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:176414.13-176414.31" - process $proc$libresoc.v:176414$12468 + attribute \src "libresoc.v:185131.13-185131.31" + process $proc$libresoc.v:185131$12533 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:176426.7-176426.26" - process $proc$libresoc.v:176426$12469 + attribute \src "libresoc.v:185143.7-185143.26" + process $proc$libresoc.v:185143$12534 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:176430.7-176430.26" - process $proc$libresoc.v:176430$12470 + attribute \src "libresoc.v:185147.7-185147.26" + process $proc$libresoc.v:185147$12535 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:176434.7-176434.25" - process $proc$libresoc.v:176434$12471 + attribute \src "libresoc.v:185151.7-185151.25" + process $proc$libresoc.v:185151$12536 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:176438.7-176438.25" - process $proc$libresoc.v:176438$12472 + attribute \src "libresoc.v:185155.7-185155.25" + process $proc$libresoc.v:185155$12537 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:176456.13-176456.32" - process $proc$libresoc.v:176456$12473 + attribute \src "libresoc.v:185173.13-185173.32" + process $proc$libresoc.v:185173$12538 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:176460.13-176460.32" - process $proc$libresoc.v:176460$12474 + attribute \src "libresoc.v:185177.13-185177.32" + process $proc$libresoc.v:185177$12539 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:176466.14-176466.43" - process $proc$libresoc.v:176466$12475 + attribute \src "libresoc.v:185183.14-185183.43" + process $proc$libresoc.v:185183$12540 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:176470.14-176470.43" - process $proc$libresoc.v:176470$12476 + attribute \src "libresoc.v:185187.14-185187.43" + process $proc$libresoc.v:185187$12541 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:176474.14-176474.43" - process $proc$libresoc.v:176474$12477 + attribute \src "libresoc.v:185191.14-185191.43" + process $proc$libresoc.v:185191$12542 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:176478.7-176478.20" - process $proc$libresoc.v:176478$12478 + attribute \src "libresoc.v:185195.7-185195.20" + process $proc$libresoc.v:185195$12543 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:176482.13-176482.26" - process $proc$libresoc.v:176482$12479 + attribute \src "libresoc.v:185199.13-185199.26" + process $proc$libresoc.v:185199$12544 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:176550.3-176551.39" - process $proc$libresoc.v:176550$12270 + attribute \src "libresoc.v:185267.3-185268.39" + process $proc$libresoc.v:185267$12335 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:176552.3-176553.43" - process $proc$libresoc.v:176552$12271 + attribute \src "libresoc.v:185269.3-185270.43" + process $proc$libresoc.v:185269$12336 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:176554.3-176555.29" - process $proc$libresoc.v:176554$12272 + attribute \src "libresoc.v:185271.3-185272.29" + process $proc$libresoc.v:185271$12337 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:176556.3-176557.29" - process $proc$libresoc.v:176556$12273 + attribute \src "libresoc.v:185273.3-185274.29" + process $proc$libresoc.v:185273$12338 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:176558.3-176559.29" - process $proc$libresoc.v:176558$12274 + attribute \src "libresoc.v:185275.3-185276.29" + process $proc$libresoc.v:185275$12339 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:176560.3-176561.29" - process $proc$libresoc.v:176560$12275 + attribute \src "libresoc.v:185277.3-185278.29" + process $proc$libresoc.v:185277$12340 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:176562.3-176563.29" - process $proc$libresoc.v:176562$12276 + attribute \src "libresoc.v:185279.3-185280.29" + process $proc$libresoc.v:185279$12341 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:176564.3-176565.47" - process $proc$libresoc.v:176564$12277 + attribute \src "libresoc.v:185281.3-185282.47" + process $proc$libresoc.v:185281$12342 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:176566.3-176567.53" - process $proc$libresoc.v:176566$12278 + attribute \src "libresoc.v:185283.3-185284.53" + process $proc$libresoc.v:185283$12343 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:176568.3-176569.43" - process $proc$libresoc.v:176568$12279 + attribute \src "libresoc.v:185285.3-185286.43" + process $proc$libresoc.v:185285$12344 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:176570.3-176571.49" - process $proc$libresoc.v:176570$12280 + attribute \src "libresoc.v:185287.3-185288.49" + process $proc$libresoc.v:185287$12345 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:176572.3-176573.37" - process $proc$libresoc.v:176572$12281 + attribute \src "libresoc.v:185289.3-185290.37" + process $proc$libresoc.v:185289$12346 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:176574.3-176575.43" - process $proc$libresoc.v:176574$12282 + attribute \src "libresoc.v:185291.3-185292.43" + process $proc$libresoc.v:185291$12347 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:176576.3-176577.79" - process $proc$libresoc.v:176576$12283 + attribute \src "libresoc.v:185293.3-185294.79" + process $proc$libresoc.v:185293$12348 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:176578.3-176579.75" - process $proc$libresoc.v:176578$12284 + attribute \src "libresoc.v:185295.3-185296.75" + process $proc$libresoc.v:185295$12349 assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit[11:0] \alu_shift_rot0_sr_op__fn_unit$next + assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[11:0] + update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:176580.3-176581.89" - process $proc$libresoc.v:176580$12285 + attribute \src "libresoc.v:185297.3-185298.89" + process $proc$libresoc.v:185297$12350 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:176582.3-176583.85" - process $proc$libresoc.v:176582$12286 + attribute \src "libresoc.v:185299.3-185300.85" + process $proc$libresoc.v:185299$12351 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:176584.3-176585.73" - process $proc$libresoc.v:176584$12287 + attribute \src "libresoc.v:185301.3-185302.73" + process $proc$libresoc.v:185301$12352 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:176586.3-176587.73" - process $proc$libresoc.v:176586$12288 + attribute \src "libresoc.v:185303.3-185304.73" + process $proc$libresoc.v:185303$12353 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:176588.3-176589.73" - process $proc$libresoc.v:176588$12289 + attribute \src "libresoc.v:185305.3-185306.73" + process $proc$libresoc.v:185305$12354 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:176590.3-176591.73" - process $proc$libresoc.v:176590$12290 + attribute \src "libresoc.v:185307.3-185308.73" + process $proc$libresoc.v:185307$12355 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:176592.3-176593.79" - process $proc$libresoc.v:176592$12291 + attribute \src "libresoc.v:185309.3-185310.79" + process $proc$libresoc.v:185309$12356 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:176594.3-176595.79" - process $proc$libresoc.v:176594$12292 + attribute \src "libresoc.v:185311.3-185312.79" + process $proc$libresoc.v:185311$12357 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:176596.3-176597.83" - process $proc$libresoc.v:176596$12293 + attribute \src "libresoc.v:185313.3-185314.83" + process $proc$libresoc.v:185313$12358 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:176598.3-176599.85" - process $proc$libresoc.v:176598$12294 + attribute \src "libresoc.v:185315.3-185316.85" + process $proc$libresoc.v:185315$12359 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:176600.3-176601.77" - process $proc$libresoc.v:176600$12295 + attribute \src "libresoc.v:185317.3-185318.77" + process $proc$libresoc.v:185317$12360 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:176602.3-176603.79" - process $proc$libresoc.v:176602$12296 + attribute \src "libresoc.v:185319.3-185320.79" + process $proc$libresoc.v:185319$12361 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:176604.3-176605.77" - process $proc$libresoc.v:176604$12297 + attribute \src "libresoc.v:185321.3-185322.77" + process $proc$libresoc.v:185321$12362 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:176606.3-176607.79" - process $proc$libresoc.v:176606$12298 + attribute \src "libresoc.v:185323.3-185324.79" + process $proc$libresoc.v:185323$12363 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:176608.3-176609.69" - process $proc$libresoc.v:176608$12299 + attribute \src "libresoc.v:185325.3-185326.69" + process $proc$libresoc.v:185325$12364 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:176610.3-176611.39" - process $proc$libresoc.v:176610$12300 + attribute \src "libresoc.v:185327.3-185328.39" + process $proc$libresoc.v:185327$12365 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:176612.3-176613.39" - process $proc$libresoc.v:176612$12301 + attribute \src "libresoc.v:185329.3-185330.39" + process $proc$libresoc.v:185329$12366 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:176614.3-176615.39" - process $proc$libresoc.v:176614$12302 + attribute \src "libresoc.v:185331.3-185332.39" + process $proc$libresoc.v:185331$12367 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:176616.3-176617.39" - process $proc$libresoc.v:176616$12303 + attribute \src "libresoc.v:185333.3-185334.39" + process $proc$libresoc.v:185333$12368 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:176618.3-176619.39" - process $proc$libresoc.v:176618$12304 + attribute \src "libresoc.v:185335.3-185336.39" + process $proc$libresoc.v:185335$12369 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:176620.3-176621.39" - process $proc$libresoc.v:176620$12305 + attribute \src "libresoc.v:185337.3-185338.39" + process $proc$libresoc.v:185337$12370 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:176622.3-176623.39" - process $proc$libresoc.v:176622$12306 + attribute \src "libresoc.v:185339.3-185340.39" + process $proc$libresoc.v:185339$12371 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:176624.3-176625.39" - process $proc$libresoc.v:176624$12307 + attribute \src "libresoc.v:185341.3-185342.39" + process $proc$libresoc.v:185341$12372 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:176626.3-176627.41" - process $proc$libresoc.v:176626$12308 + attribute \src "libresoc.v:185343.3-185344.41" + process $proc$libresoc.v:185343$12373 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:176628.3-176629.41" - process $proc$libresoc.v:176628$12309 + attribute \src "libresoc.v:185345.3-185346.41" + process $proc$libresoc.v:185345$12374 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:176630.3-176631.37" - process $proc$libresoc.v:176630$12310 + attribute \src "libresoc.v:185347.3-185348.37" + process $proc$libresoc.v:185347$12375 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:176632.3-176633.46" - process $proc$libresoc.v:176632$12311 + attribute \src "libresoc.v:185349.3-185350.46" + process $proc$libresoc.v:185349$12376 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:176634.3-176635.25" - process $proc$libresoc.v:176634$12312 + attribute \src "libresoc.v:185351.3-185352.25" + process $proc$libresoc.v:185351$12377 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:176720.3-176729.6" - process $proc$libresoc.v:176720$12313 + attribute \src "libresoc.v:185437.3-185446.6" + process $proc$libresoc.v:185437$12378 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:176721.5-176721.29" + attribute \src "libresoc.v:185438.5-185438.29" switch \initial - attribute \src "libresoc.v:176721.9-176721.17" + attribute \src "libresoc.v:185438.9-185438.17" case 1'1 case end @@ -371280,14 +386289,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:176730.3-176738.6" - process $proc$libresoc.v:176730$12314 + attribute \src "libresoc.v:185447.3-185455.6" + process $proc$libresoc.v:185447$12379 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12315 $1\rok_l_s_rdok$next[0:0]$12316 - attribute \src "libresoc.v:176731.5-176731.29" + assign $0\rok_l_s_rdok$next[0:0]$12380 $1\rok_l_s_rdok$next[0:0]$12381 + attribute \src "libresoc.v:185448.5-185448.29" switch \initial - attribute \src "libresoc.v:176731.9-176731.17" + attribute \src "libresoc.v:185448.9-185448.17" case 1'1 case end @@ -371296,21 +386305,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12316 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12381 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12316 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12381 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12315 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12380 end - attribute \src "libresoc.v:176739.3-176747.6" - process $proc$libresoc.v:176739$12317 + attribute \src "libresoc.v:185456.3-185464.6" + process $proc$libresoc.v:185456$12382 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12318 $1\rok_l_r_rdok$next[0:0]$12319 - attribute \src "libresoc.v:176740.5-176740.29" + assign $0\rok_l_r_rdok$next[0:0]$12383 $1\rok_l_r_rdok$next[0:0]$12384 + attribute \src "libresoc.v:185457.5-185457.29" switch \initial - attribute \src "libresoc.v:176740.9-176740.17" + attribute \src "libresoc.v:185457.9-185457.17" case 1'1 case end @@ -371319,21 +386328,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12319 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12384 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12319 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12384 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12318 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12383 end - attribute \src "libresoc.v:176748.3-176756.6" - process $proc$libresoc.v:176748$12320 + attribute \src "libresoc.v:185465.3-185473.6" + process $proc$libresoc.v:185465$12385 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12321 $1\rst_l_s_rst$next[0:0]$12322 - attribute \src "libresoc.v:176749.5-176749.29" + assign $0\rst_l_s_rst$next[0:0]$12386 $1\rst_l_s_rst$next[0:0]$12387 + attribute \src "libresoc.v:185466.5-185466.29" switch \initial - attribute \src "libresoc.v:176749.9-176749.17" + attribute \src "libresoc.v:185466.9-185466.17" case 1'1 case end @@ -371342,21 +386351,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12322 1'0 + assign $1\rst_l_s_rst$next[0:0]$12387 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12322 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12387 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12321 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12386 end - attribute \src "libresoc.v:176757.3-176765.6" - process $proc$libresoc.v:176757$12323 + attribute \src "libresoc.v:185474.3-185482.6" + process $proc$libresoc.v:185474$12388 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12324 $1\rst_l_r_rst$next[0:0]$12325 - attribute \src "libresoc.v:176758.5-176758.29" + assign $0\rst_l_r_rst$next[0:0]$12389 $1\rst_l_r_rst$next[0:0]$12390 + attribute \src "libresoc.v:185475.5-185475.29" switch \initial - attribute \src "libresoc.v:176758.9-176758.17" + attribute \src "libresoc.v:185475.9-185475.17" case 1'1 case end @@ -371365,21 +386374,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12325 1'1 + assign $1\rst_l_r_rst$next[0:0]$12390 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12325 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12390 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12324 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12389 end - attribute \src "libresoc.v:176766.3-176774.6" - process $proc$libresoc.v:176766$12326 + attribute \src "libresoc.v:185483.3-185491.6" + process $proc$libresoc.v:185483$12391 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12327 $1\opc_l_s_opc$next[0:0]$12328 - attribute \src "libresoc.v:176767.5-176767.29" + assign $0\opc_l_s_opc$next[0:0]$12392 $1\opc_l_s_opc$next[0:0]$12393 + attribute \src "libresoc.v:185484.5-185484.29" switch \initial - attribute \src "libresoc.v:176767.9-176767.17" + attribute \src "libresoc.v:185484.9-185484.17" case 1'1 case end @@ -371388,21 +386397,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12328 1'0 + assign $1\opc_l_s_opc$next[0:0]$12393 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12328 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12393 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12327 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12392 end - attribute \src "libresoc.v:176775.3-176783.6" - process $proc$libresoc.v:176775$12329 + attribute \src "libresoc.v:185492.3-185500.6" + process $proc$libresoc.v:185492$12394 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12330 $1\opc_l_r_opc$next[0:0]$12331 - attribute \src "libresoc.v:176776.5-176776.29" + assign $0\opc_l_r_opc$next[0:0]$12395 $1\opc_l_r_opc$next[0:0]$12396 + attribute \src "libresoc.v:185493.5-185493.29" switch \initial - attribute \src "libresoc.v:176776.9-176776.17" + attribute \src "libresoc.v:185493.9-185493.17" case 1'1 case end @@ -371411,21 +386420,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12331 1'1 + assign $1\opc_l_r_opc$next[0:0]$12396 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12331 \req_done + assign $1\opc_l_r_opc$next[0:0]$12396 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12330 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12395 end - attribute \src "libresoc.v:176784.3-176792.6" - process $proc$libresoc.v:176784$12332 + attribute \src "libresoc.v:185501.3-185509.6" + process $proc$libresoc.v:185501$12397 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12333 $1\src_l_s_src$next[4:0]$12334 - attribute \src "libresoc.v:176785.5-176785.29" + assign $0\src_l_s_src$next[4:0]$12398 $1\src_l_s_src$next[4:0]$12399 + attribute \src "libresoc.v:185502.5-185502.29" switch \initial - attribute \src "libresoc.v:176785.9-176785.17" + attribute \src "libresoc.v:185502.9-185502.17" case 1'1 case end @@ -371434,21 +386443,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$12334 5'00000 + assign $1\src_l_s_src$next[4:0]$12399 5'00000 case - assign $1\src_l_s_src$next[4:0]$12334 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12399 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12333 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12398 end - attribute \src "libresoc.v:176793.3-176801.6" - process $proc$libresoc.v:176793$12335 + attribute \src "libresoc.v:185510.3-185518.6" + process $proc$libresoc.v:185510$12400 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12336 $1\src_l_r_src$next[4:0]$12337 - attribute \src "libresoc.v:176794.5-176794.29" + assign $0\src_l_r_src$next[4:0]$12401 $1\src_l_r_src$next[4:0]$12402 + attribute \src "libresoc.v:185511.5-185511.29" switch \initial - attribute \src "libresoc.v:176794.9-176794.17" + attribute \src "libresoc.v:185511.9-185511.17" case 1'1 case end @@ -371457,21 +386466,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$12337 5'11111 + assign $1\src_l_r_src$next[4:0]$12402 5'11111 case - assign $1\src_l_r_src$next[4:0]$12337 \reset_r + assign $1\src_l_r_src$next[4:0]$12402 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12336 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12401 end - attribute \src "libresoc.v:176802.3-176810.6" - process $proc$libresoc.v:176802$12338 + attribute \src "libresoc.v:185519.3-185527.6" + process $proc$libresoc.v:185519$12403 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12339 $1\req_l_s_req$next[2:0]$12340 - attribute \src "libresoc.v:176803.5-176803.29" + assign $0\req_l_s_req$next[2:0]$12404 $1\req_l_s_req$next[2:0]$12405 + attribute \src "libresoc.v:185520.5-185520.29" switch \initial - attribute \src "libresoc.v:176803.9-176803.17" + attribute \src "libresoc.v:185520.9-185520.17" case 1'1 case end @@ -371480,21 +386489,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$12340 3'000 + assign $1\req_l_s_req$next[2:0]$12405 3'000 case - assign $1\req_l_s_req$next[2:0]$12340 \$66 + assign $1\req_l_s_req$next[2:0]$12405 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12339 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12404 end - attribute \src "libresoc.v:176811.3-176819.6" - process $proc$libresoc.v:176811$12341 + attribute \src "libresoc.v:185528.3-185536.6" + process $proc$libresoc.v:185528$12406 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12342 $1\req_l_r_req$next[2:0]$12343 - attribute \src "libresoc.v:176812.5-176812.29" + assign $0\req_l_r_req$next[2:0]$12407 $1\req_l_r_req$next[2:0]$12408 + attribute \src "libresoc.v:185529.5-185529.29" switch \initial - attribute \src "libresoc.v:176812.9-176812.17" + attribute \src "libresoc.v:185529.9-185529.17" case 1'1 case end @@ -371503,15 +386512,15 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$12343 3'111 + assign $1\req_l_r_req$next[2:0]$12408 3'111 case - assign $1\req_l_r_req$next[2:0]$12343 \$68 + assign $1\req_l_r_req$next[2:0]$12408 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12342 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12407 end - attribute \src "libresoc.v:176820.3-176857.6" - process $proc$libresoc.v:176820$12344 + attribute \src "libresoc.v:185537.3-185574.6" + process $proc$libresoc.v:185537$12409 assign { } { } assign { } { } assign { } { } @@ -371546,32 +386555,32 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12345 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12362 + assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12348 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12365 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12349 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12366 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12350 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12367 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12351 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12368 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12352 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12369 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12353 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12370 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12354 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12371 + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12357 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12374 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12358 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12375 + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12361 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12378 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12346 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12379 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12347 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12380 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12355 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12381 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12356 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12382 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12359 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12383 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12360 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12384 - attribute \src "libresoc.v:176821.5-176821.29" + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 + attribute \src "libresoc.v:185538.5-185538.29" switch \initial - attribute \src "libresoc.v:176821.9-176821.17" + attribute \src "libresoc.v:185538.9-185538.17" case 1'1 case end @@ -371596,25 +386605,25 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12367 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12371 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12370 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12375 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12366 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12374 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12365 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12369 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12378 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12373 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12372 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12376 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12377 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12364 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12363 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12362 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12368 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12362 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12363 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12364 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12365 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12366 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12367 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12368 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12369 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12370 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12371 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12372 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12373 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12374 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12375 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12376 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12377 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12378 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -371626,53 +386635,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12379 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12380 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12384 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12383 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12381 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12382 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12379 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12363 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12380 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12364 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12381 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12372 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12382 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12373 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12383 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12376 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12384 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12377 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12345 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12346 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12347 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12348 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12349 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12350 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12351 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12352 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12353 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12354 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12355 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12356 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12357 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12358 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12359 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12360 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12361 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 end - attribute \src "libresoc.v:176858.3-176879.6" - process $proc$libresoc.v:176858$12385 + attribute \src "libresoc.v:185575.3-185596.6" + process $proc$libresoc.v:185575$12450 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12386 $2\data_r0__o$next[63:0]$12390 + assign $0\data_r0__o$next[63:0]$12451 $2\data_r0__o$next[63:0]$12455 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12387 $3\data_r0__o_ok$next[0:0]$12392 - attribute \src "libresoc.v:176859.5-176859.29" + assign $0\data_r0__o_ok$next[0:0]$12452 $3\data_r0__o_ok$next[0:0]$12457 + attribute \src "libresoc.v:185576.5-185576.29" switch \initial - attribute \src "libresoc.v:176859.9-176859.17" + attribute \src "libresoc.v:185576.9-185576.17" case 1'1 case end @@ -371682,10 +386691,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12389 $1\data_r0__o$next[63:0]$12388 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12454 $1\data_r0__o$next[63:0]$12453 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12388 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12389 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12453 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12454 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -371693,38 +386702,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12391 $2\data_r0__o$next[63:0]$12390 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12456 $2\data_r0__o$next[63:0]$12455 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12390 $1\data_r0__o$next[63:0]$12388 - assign $2\data_r0__o_ok$next[0:0]$12391 $1\data_r0__o_ok$next[0:0]$12389 + assign $2\data_r0__o$next[63:0]$12455 $1\data_r0__o$next[63:0]$12453 + assign $2\data_r0__o_ok$next[0:0]$12456 $1\data_r0__o_ok$next[0:0]$12454 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12392 1'0 + assign $3\data_r0__o_ok$next[0:0]$12457 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12392 $2\data_r0__o_ok$next[0:0]$12391 + assign $3\data_r0__o_ok$next[0:0]$12457 $2\data_r0__o_ok$next[0:0]$12456 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12386 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12387 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12451 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12452 end - attribute \src "libresoc.v:176880.3-176901.6" - process $proc$libresoc.v:176880$12393 + attribute \src "libresoc.v:185597.3-185618.6" + process $proc$libresoc.v:185597$12458 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12394 $2\data_r1__cr_a$next[3:0]$12398 + assign $0\data_r1__cr_a$next[3:0]$12459 $2\data_r1__cr_a$next[3:0]$12463 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12395 $3\data_r1__cr_a_ok$next[0:0]$12400 - attribute \src "libresoc.v:176881.5-176881.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12460 $3\data_r1__cr_a_ok$next[0:0]$12465 + attribute \src "libresoc.v:185598.5-185598.29" switch \initial - attribute \src "libresoc.v:176881.9-176881.17" + attribute \src "libresoc.v:185598.9-185598.17" case 1'1 case end @@ -371734,10 +386743,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12397 $1\data_r1__cr_a$next[3:0]$12396 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12462 $1\data_r1__cr_a$next[3:0]$12461 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12396 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12397 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12461 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12462 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -371745,38 +386754,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12399 $2\data_r1__cr_a$next[3:0]$12398 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12464 $2\data_r1__cr_a$next[3:0]$12463 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12398 $1\data_r1__cr_a$next[3:0]$12396 - assign $2\data_r1__cr_a_ok$next[0:0]$12399 $1\data_r1__cr_a_ok$next[0:0]$12397 + assign $2\data_r1__cr_a$next[3:0]$12463 $1\data_r1__cr_a$next[3:0]$12461 + assign $2\data_r1__cr_a_ok$next[0:0]$12464 $1\data_r1__cr_a_ok$next[0:0]$12462 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12400 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12465 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12400 $2\data_r1__cr_a_ok$next[0:0]$12399 + assign $3\data_r1__cr_a_ok$next[0:0]$12465 $2\data_r1__cr_a_ok$next[0:0]$12464 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12394 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12395 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12459 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12460 end - attribute \src "libresoc.v:176902.3-176923.6" - process $proc$libresoc.v:176902$12401 + attribute \src "libresoc.v:185619.3-185640.6" + process $proc$libresoc.v:185619$12466 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12402 $2\data_r2__xer_ca$next[1:0]$12406 + assign $0\data_r2__xer_ca$next[1:0]$12467 $2\data_r2__xer_ca$next[1:0]$12471 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12403 $3\data_r2__xer_ca_ok$next[0:0]$12408 - attribute \src "libresoc.v:176903.5-176903.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12468 $3\data_r2__xer_ca_ok$next[0:0]$12473 + attribute \src "libresoc.v:185620.5-185620.29" switch \initial - attribute \src "libresoc.v:176903.9-176903.17" + attribute \src "libresoc.v:185620.9-185620.17" case 1'1 case end @@ -371786,10 +386795,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12405 $1\data_r2__xer_ca$next[1:0]$12404 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12470 $1\data_r2__xer_ca$next[1:0]$12469 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12404 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12405 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12469 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12470 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -371797,147 +386806,147 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12407 $2\data_r2__xer_ca$next[1:0]$12406 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12472 $2\data_r2__xer_ca$next[1:0]$12471 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12406 $1\data_r2__xer_ca$next[1:0]$12404 - assign $2\data_r2__xer_ca_ok$next[0:0]$12407 $1\data_r2__xer_ca_ok$next[0:0]$12405 + assign $2\data_r2__xer_ca$next[1:0]$12471 $1\data_r2__xer_ca$next[1:0]$12469 + assign $2\data_r2__xer_ca_ok$next[0:0]$12472 $1\data_r2__xer_ca_ok$next[0:0]$12470 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12408 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12473 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12408 $2\data_r2__xer_ca_ok$next[0:0]$12407 + assign $3\data_r2__xer_ca_ok$next[0:0]$12473 $2\data_r2__xer_ca_ok$next[0:0]$12472 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12402 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12403 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12467 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12468 end - attribute \src "libresoc.v:176924.3-176933.6" - process $proc$libresoc.v:176924$12409 + attribute \src "libresoc.v:185641.3-185650.6" + process $proc$libresoc.v:185641$12474 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12410 $1\src_r0$next[63:0]$12411 - attribute \src "libresoc.v:176925.5-176925.29" + assign $0\src_r0$next[63:0]$12475 $1\src_r0$next[63:0]$12476 + attribute \src "libresoc.v:185642.5-185642.29" switch \initial - attribute \src "libresoc.v:176925.9-176925.17" + attribute \src "libresoc.v:185642.9-185642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12411 \src1_i + assign $1\src_r0$next[63:0]$12476 \src1_i case - assign $1\src_r0$next[63:0]$12411 \src_r0 + assign $1\src_r0$next[63:0]$12476 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12410 + update \src_r0$next $0\src_r0$next[63:0]$12475 end - attribute \src "libresoc.v:176934.3-176943.6" - process $proc$libresoc.v:176934$12412 + attribute \src "libresoc.v:185651.3-185660.6" + process $proc$libresoc.v:185651$12477 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12413 $1\src_r1$next[63:0]$12414 - attribute \src "libresoc.v:176935.5-176935.29" + assign $0\src_r1$next[63:0]$12478 $1\src_r1$next[63:0]$12479 + attribute \src "libresoc.v:185652.5-185652.29" switch \initial - attribute \src "libresoc.v:176935.9-176935.17" + attribute \src "libresoc.v:185652.9-185652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12414 \src_or_imm + assign $1\src_r1$next[63:0]$12479 \src_or_imm case - assign $1\src_r1$next[63:0]$12414 \src_r1 + assign $1\src_r1$next[63:0]$12479 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12413 + update \src_r1$next $0\src_r1$next[63:0]$12478 end - attribute \src "libresoc.v:176944.3-176953.6" - process $proc$libresoc.v:176944$12415 + attribute \src "libresoc.v:185661.3-185670.6" + process $proc$libresoc.v:185661$12480 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12416 $1\src_r2$next[63:0]$12417 - attribute \src "libresoc.v:176945.5-176945.29" + assign $0\src_r2$next[63:0]$12481 $1\src_r2$next[63:0]$12482 + attribute \src "libresoc.v:185662.5-185662.29" switch \initial - attribute \src "libresoc.v:176945.9-176945.17" + attribute \src "libresoc.v:185662.9-185662.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12417 \src3_i + assign $1\src_r2$next[63:0]$12482 \src3_i case - assign $1\src_r2$next[63:0]$12417 \src_r2 + assign $1\src_r2$next[63:0]$12482 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12416 + update \src_r2$next $0\src_r2$next[63:0]$12481 end - attribute \src "libresoc.v:176954.3-176963.6" - process $proc$libresoc.v:176954$12418 + attribute \src "libresoc.v:185671.3-185680.6" + process $proc$libresoc.v:185671$12483 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12419 $1\src_r3$next[0:0]$12420 - attribute \src "libresoc.v:176955.5-176955.29" + assign $0\src_r3$next[0:0]$12484 $1\src_r3$next[0:0]$12485 + attribute \src "libresoc.v:185672.5-185672.29" switch \initial - attribute \src "libresoc.v:176955.9-176955.17" + attribute \src "libresoc.v:185672.9-185672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12420 \src4_i + assign $1\src_r3$next[0:0]$12485 \src4_i case - assign $1\src_r3$next[0:0]$12420 \src_r3 + assign $1\src_r3$next[0:0]$12485 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12419 + update \src_r3$next $0\src_r3$next[0:0]$12484 end - attribute \src "libresoc.v:176964.3-176973.6" - process $proc$libresoc.v:176964$12421 + attribute \src "libresoc.v:185681.3-185690.6" + process $proc$libresoc.v:185681$12486 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12422 $1\src_r4$next[1:0]$12423 - attribute \src "libresoc.v:176965.5-176965.29" + assign $0\src_r4$next[1:0]$12487 $1\src_r4$next[1:0]$12488 + attribute \src "libresoc.v:185682.5-185682.29" switch \initial - attribute \src "libresoc.v:176965.9-176965.17" + attribute \src "libresoc.v:185682.9-185682.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12423 \src5_i + assign $1\src_r4$next[1:0]$12488 \src5_i case - assign $1\src_r4$next[1:0]$12423 \src_r4 + assign $1\src_r4$next[1:0]$12488 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12422 + update \src_r4$next $0\src_r4$next[1:0]$12487 end - attribute \src "libresoc.v:176974.3-176982.6" - process $proc$libresoc.v:176974$12424 + attribute \src "libresoc.v:185691.3-185699.6" + process $proc$libresoc.v:185691$12489 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12425 $1\alui_l_r_alui$next[0:0]$12426 - attribute \src "libresoc.v:176975.5-176975.29" + assign $0\alui_l_r_alui$next[0:0]$12490 $1\alui_l_r_alui$next[0:0]$12491 + attribute \src "libresoc.v:185692.5-185692.29" switch \initial - attribute \src "libresoc.v:176975.9-176975.17" + attribute \src "libresoc.v:185692.9-185692.17" case 1'1 case end @@ -371946,21 +386955,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12426 1'1 + assign $1\alui_l_r_alui$next[0:0]$12491 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12426 \$90 + assign $1\alui_l_r_alui$next[0:0]$12491 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12425 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12490 end - attribute \src "libresoc.v:176983.3-176991.6" - process $proc$libresoc.v:176983$12427 + attribute \src "libresoc.v:185700.3-185708.6" + process $proc$libresoc.v:185700$12492 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12428 $1\alu_l_r_alu$next[0:0]$12429 - attribute \src "libresoc.v:176984.5-176984.29" + assign $0\alu_l_r_alu$next[0:0]$12493 $1\alu_l_r_alu$next[0:0]$12494 + attribute \src "libresoc.v:185701.5-185701.29" switch \initial - attribute \src "libresoc.v:176984.9-176984.17" + attribute \src "libresoc.v:185701.9-185701.17" case 1'1 case end @@ -371969,21 +386978,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12429 1'1 + assign $1\alu_l_r_alu$next[0:0]$12494 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12429 \$92 + assign $1\alu_l_r_alu$next[0:0]$12494 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12428 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12493 end - attribute \src "libresoc.v:176992.3-177001.6" - process $proc$libresoc.v:176992$12430 + attribute \src "libresoc.v:185709.3-185718.6" + process $proc$libresoc.v:185709$12495 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:176993.5-176993.29" + attribute \src "libresoc.v:185710.5-185710.29" switch \initial - attribute \src "libresoc.v:176993.9-176993.17" + attribute \src "libresoc.v:185710.9-185710.17" case 1'1 case end @@ -371999,14 +387008,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:177002.3-177011.6" - process $proc$libresoc.v:177002$12431 + attribute \src "libresoc.v:185719.3-185728.6" + process $proc$libresoc.v:185719$12496 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:177003.5-177003.29" + attribute \src "libresoc.v:185720.5-185720.29" switch \initial - attribute \src "libresoc.v:177003.9-177003.17" + attribute \src "libresoc.v:185720.9-185720.17" case 1'1 case end @@ -372022,14 +387031,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:177012.3-177021.6" - process $proc$libresoc.v:177012$12432 + attribute \src "libresoc.v:185729.3-185738.6" + process $proc$libresoc.v:185729$12497 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:177013.5-177013.29" + attribute \src "libresoc.v:185730.5-185730.29" switch \initial - attribute \src "libresoc.v:177013.9-177013.17" + attribute \src "libresoc.v:185730.9-185730.17" case 1'1 case end @@ -372045,14 +387054,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:177022.3-177030.6" - process $proc$libresoc.v:177022$12433 + attribute \src "libresoc.v:185739.3-185747.6" + process $proc$libresoc.v:185739$12498 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12434 $1\prev_wr_go$next[2:0]$12435 - attribute \src "libresoc.v:177023.5-177023.29" + assign $0\prev_wr_go$next[2:0]$12499 $1\prev_wr_go$next[2:0]$12500 + attribute \src "libresoc.v:185740.5-185740.29" switch \initial - attribute \src "libresoc.v:177023.9-177023.17" + attribute \src "libresoc.v:185740.9-185740.17" case 1'1 case end @@ -372061,72 +387070,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12435 3'000 - case - assign $1\prev_wr_go$next[2:0]$12435 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12434 - end - connect \$100 $not$libresoc.v:176491$12211_Y - connect \$102 $and$libresoc.v:176492$12212_Y - connect \$104 $and$libresoc.v:176493$12213_Y - connect \$106 $and$libresoc.v:176494$12214_Y - connect \$108 $and$libresoc.v:176495$12215_Y - connect \$10 $and$libresoc.v:176496$12216_Y - connect \$110 $and$libresoc.v:176497$12217_Y - connect \$112 $and$libresoc.v:176498$12218_Y - connect \$114 $and$libresoc.v:176499$12219_Y - connect \$116 $and$libresoc.v:176500$12220_Y - connect \$118 $and$libresoc.v:176501$12221_Y - connect \$12 $not$libresoc.v:176502$12222_Y - connect \$14 $and$libresoc.v:176503$12223_Y - connect \$16 $not$libresoc.v:176504$12224_Y - connect \$18 $and$libresoc.v:176505$12225_Y - connect \$20 $and$libresoc.v:176506$12226_Y - connect \$24 $not$libresoc.v:176507$12227_Y - connect \$26 $and$libresoc.v:176508$12228_Y - connect \$23 $reduce_or$libresoc.v:176509$12229_Y - connect \$22 $not$libresoc.v:176510$12230_Y - connect \$2 $and$libresoc.v:176511$12231_Y - connect \$30 $and$libresoc.v:176512$12232_Y - connect \$32 $reduce_or$libresoc.v:176513$12233_Y - connect \$34 $reduce_or$libresoc.v:176514$12234_Y - connect \$36 $or$libresoc.v:176515$12235_Y - connect \$38 $not$libresoc.v:176516$12236_Y - connect \$40 $and$libresoc.v:176517$12237_Y - connect \$42 $and$libresoc.v:176518$12238_Y - connect \$44 $eq$libresoc.v:176519$12239_Y - connect \$46 $and$libresoc.v:176520$12240_Y - connect \$48 $eq$libresoc.v:176521$12241_Y - connect \$50 $and$libresoc.v:176522$12242_Y - connect \$52 $and$libresoc.v:176523$12243_Y - connect \$54 $and$libresoc.v:176524$12244_Y - connect \$56 $or$libresoc.v:176525$12245_Y - connect \$58 $or$libresoc.v:176526$12246_Y - connect \$5 $not$libresoc.v:176527$12247_Y - connect \$60 $or$libresoc.v:176528$12248_Y - connect \$62 $or$libresoc.v:176529$12249_Y - connect \$64 $and$libresoc.v:176530$12250_Y - connect \$66 $and$libresoc.v:176531$12251_Y - connect \$68 $or$libresoc.v:176532$12252_Y - connect \$70 $and$libresoc.v:176533$12253_Y - connect \$72 $and$libresoc.v:176534$12254_Y - connect \$74 $and$libresoc.v:176535$12255_Y - connect \$76 $ternary$libresoc.v:176536$12256_Y - connect \$78 $ternary$libresoc.v:176537$12257_Y - connect \$7 $or$libresoc.v:176538$12258_Y - connect \$80 $ternary$libresoc.v:176539$12259_Y - connect \$82 $ternary$libresoc.v:176540$12260_Y - connect \$84 $ternary$libresoc.v:176541$12261_Y - connect \$86 $ternary$libresoc.v:176542$12262_Y - connect \$88 $ternary$libresoc.v:176543$12263_Y - connect \$4 $reduce_and$libresoc.v:176544$12264_Y - connect \$90 $and$libresoc.v:176545$12265_Y - connect \$92 $and$libresoc.v:176546$12266_Y - connect \$94 $and$libresoc.v:176547$12267_Y - connect \$96 $not$libresoc.v:176548$12268_Y - connect \$98 $and$libresoc.v:176549$12269_Y + assign $1\prev_wr_go$next[2:0]$12500 3'000 + case + assign $1\prev_wr_go$next[2:0]$12500 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12499 + end + connect \$100 $not$libresoc.v:185208$12276_Y + connect \$102 $and$libresoc.v:185209$12277_Y + connect \$104 $and$libresoc.v:185210$12278_Y + connect \$106 $and$libresoc.v:185211$12279_Y + connect \$108 $and$libresoc.v:185212$12280_Y + connect \$10 $and$libresoc.v:185213$12281_Y + connect \$110 $and$libresoc.v:185214$12282_Y + connect \$112 $and$libresoc.v:185215$12283_Y + connect \$114 $and$libresoc.v:185216$12284_Y + connect \$116 $and$libresoc.v:185217$12285_Y + connect \$118 $and$libresoc.v:185218$12286_Y + connect \$12 $not$libresoc.v:185219$12287_Y + connect \$14 $and$libresoc.v:185220$12288_Y + connect \$16 $not$libresoc.v:185221$12289_Y + connect \$18 $and$libresoc.v:185222$12290_Y + connect \$20 $and$libresoc.v:185223$12291_Y + connect \$24 $not$libresoc.v:185224$12292_Y + connect \$26 $and$libresoc.v:185225$12293_Y + connect \$23 $reduce_or$libresoc.v:185226$12294_Y + connect \$22 $not$libresoc.v:185227$12295_Y + connect \$2 $and$libresoc.v:185228$12296_Y + connect \$30 $and$libresoc.v:185229$12297_Y + connect \$32 $reduce_or$libresoc.v:185230$12298_Y + connect \$34 $reduce_or$libresoc.v:185231$12299_Y + connect \$36 $or$libresoc.v:185232$12300_Y + connect \$38 $not$libresoc.v:185233$12301_Y + connect \$40 $and$libresoc.v:185234$12302_Y + connect \$42 $and$libresoc.v:185235$12303_Y + connect \$44 $eq$libresoc.v:185236$12304_Y + connect \$46 $and$libresoc.v:185237$12305_Y + connect \$48 $eq$libresoc.v:185238$12306_Y + connect \$50 $and$libresoc.v:185239$12307_Y + connect \$52 $and$libresoc.v:185240$12308_Y + connect \$54 $and$libresoc.v:185241$12309_Y + connect \$56 $or$libresoc.v:185242$12310_Y + connect \$58 $or$libresoc.v:185243$12311_Y + connect \$5 $not$libresoc.v:185244$12312_Y + connect \$60 $or$libresoc.v:185245$12313_Y + connect \$62 $or$libresoc.v:185246$12314_Y + connect \$64 $and$libresoc.v:185247$12315_Y + connect \$66 $and$libresoc.v:185248$12316_Y + connect \$68 $or$libresoc.v:185249$12317_Y + connect \$70 $and$libresoc.v:185250$12318_Y + connect \$72 $and$libresoc.v:185251$12319_Y + connect \$74 $and$libresoc.v:185252$12320_Y + connect \$76 $ternary$libresoc.v:185253$12321_Y + connect \$78 $ternary$libresoc.v:185254$12322_Y + connect \$7 $or$libresoc.v:185255$12323_Y + connect \$80 $ternary$libresoc.v:185256$12324_Y + connect \$82 $ternary$libresoc.v:185257$12325_Y + connect \$84 $ternary$libresoc.v:185258$12326_Y + connect \$86 $ternary$libresoc.v:185259$12327_Y + connect \$88 $ternary$libresoc.v:185260$12328_Y + connect \$4 $reduce_and$libresoc.v:185261$12329_Y + connect \$90 $and$libresoc.v:185262$12330_Y + connect \$92 $and$libresoc.v:185263$12331_Y + connect \$94 $and$libresoc.v:185264$12332_Y + connect \$96 $not$libresoc.v:185265$12333_Y + connect \$98 $and$libresoc.v:185266$12334_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -372160,48 +387169,48 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:177067.1-177244.10" +attribute \src "libresoc.v:185784.1-185964.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:177216.3-177219.6" - wire width 7 $0$memwr$\memory$libresoc.v:177218$12590_ADDR[6:0]$12593 - attribute \src "libresoc.v:177216.3-177219.6" - wire width 64 $0$memwr$\memory$libresoc.v:177218$12590_DATA[63:0]$12594 - attribute \src "libresoc.v:177216.3-177219.6" - wire width 64 $0$memwr$\memory$libresoc.v:177218$12590_EN[63:0]$12595 - attribute \src "libresoc.v:177216.3-177219.6" + attribute \src "libresoc.v:185936.3-185939.6" + wire width 7 $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 + attribute \src "libresoc.v:185936.3-185939.6" + wire width 64 $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 + attribute \src "libresoc.v:185936.3-185939.6" + wire width 64 $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 + attribute \src "libresoc.v:185936.3-185939.6" wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:177068.7-177068.20" + attribute \src "libresoc.v:185785.7-185785.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177221.3-177229.6" - wire $0\ren_delay$next[0:0]$12598 - attribute \src "libresoc.v:177100.3-177101.35" + attribute \src "libresoc.v:185941.3-185949.6" + wire $0\ren_delay$next[0:0]$12666 + attribute \src "libresoc.v:185817.3-185818.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:177230.3-177239.6" + attribute \src "libresoc.v:185950.3-185959.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:177221.3-177229.6" - wire $1\ren_delay$next[0:0]$12599 - attribute \src "libresoc.v:177084.7-177084.23" + attribute \src "libresoc.v:185941.3-185949.6" + wire $1\ren_delay$next[0:0]$12667 + attribute \src "libresoc.v:185801.7-185801.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:177230.3-177239.6" + attribute \src "libresoc.v:185950.3-185959.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:177220.26-177220.32" - wire width 64 $memrd$\memory$libresoc.v:177220$12596_DATA + attribute \src "libresoc.v:185940.26-185940.32" + wire width 64 $memrd$\memory$libresoc.v:185940$12664_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:177218$12590_ADDR + wire width 7 $memwr$\memory$libresoc.v:185938$12658_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:177218$12590_DATA + wire width 64 $memwr$\memory$libresoc.v:185938$12658_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:177218$12590_EN - attribute \src "libresoc.v:177215.13-177215.16" + wire width 64 $memwr$\memory$libresoc.v:185938$12658_EN + attribute \src "libresoc.v:185935.13-185935.16" wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:177068.7-177068.15" + attribute \src "libresoc.v:185785.7-185785.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr @@ -372217,1122 +387226,1152 @@ module \spr wire \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 7 input 3 \spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 7 input 6 \spr1__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 5 \spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 2 \spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:177102.14-177102.20" - memory width 64 size 110 \memory + attribute \src "libresoc.v:185819.14-185819.20" + memory width 64 size 113 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12601 + cell $meminit $meminit$\memory$libresoc.v:0$12669 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12601 + parameter \PRIORITY 12669 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12602 + cell $meminit $meminit$\memory$libresoc.v:0$12670 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12602 + parameter \PRIORITY 12670 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12603 + cell $meminit $meminit$\memory$libresoc.v:0$12671 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12603 + parameter \PRIORITY 12671 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12604 + cell $meminit $meminit$\memory$libresoc.v:0$12672 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12604 + parameter \PRIORITY 12672 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12605 + cell $meminit $meminit$\memory$libresoc.v:0$12673 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12605 + parameter \PRIORITY 12673 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12606 + cell $meminit $meminit$\memory$libresoc.v:0$12674 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12606 + parameter \PRIORITY 12674 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12607 + cell $meminit $meminit$\memory$libresoc.v:0$12675 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12607 + parameter \PRIORITY 12675 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12608 + cell $meminit $meminit$\memory$libresoc.v:0$12676 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12608 + parameter \PRIORITY 12676 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12609 + cell $meminit $meminit$\memory$libresoc.v:0$12677 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12609 + parameter \PRIORITY 12677 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12610 + cell $meminit $meminit$\memory$libresoc.v:0$12678 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12610 + parameter \PRIORITY 12678 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12611 + cell $meminit $meminit$\memory$libresoc.v:0$12679 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12611 + parameter \PRIORITY 12679 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12612 + cell $meminit $meminit$\memory$libresoc.v:0$12680 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12612 + parameter \PRIORITY 12680 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12613 + cell $meminit $meminit$\memory$libresoc.v:0$12681 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12613 + parameter \PRIORITY 12681 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12614 + cell $meminit $meminit$\memory$libresoc.v:0$12682 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12614 + parameter \PRIORITY 12682 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12615 + cell $meminit $meminit$\memory$libresoc.v:0$12683 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12615 + parameter \PRIORITY 12683 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12616 + cell $meminit $meminit$\memory$libresoc.v:0$12684 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12616 + parameter \PRIORITY 12684 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12617 + cell $meminit $meminit$\memory$libresoc.v:0$12685 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12617 + parameter \PRIORITY 12685 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12618 + cell $meminit $meminit$\memory$libresoc.v:0$12686 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12618 + parameter \PRIORITY 12686 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12619 + cell $meminit $meminit$\memory$libresoc.v:0$12687 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12619 + parameter \PRIORITY 12687 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12620 + cell $meminit $meminit$\memory$libresoc.v:0$12688 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12620 + parameter \PRIORITY 12688 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12621 + cell $meminit $meminit$\memory$libresoc.v:0$12689 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12621 + parameter \PRIORITY 12689 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12622 + cell $meminit $meminit$\memory$libresoc.v:0$12690 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12622 + parameter \PRIORITY 12690 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12623 + cell $meminit $meminit$\memory$libresoc.v:0$12691 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12623 + parameter \PRIORITY 12691 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12624 + cell $meminit $meminit$\memory$libresoc.v:0$12692 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12624 + parameter \PRIORITY 12692 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12625 + cell $meminit $meminit$\memory$libresoc.v:0$12693 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12625 + parameter \PRIORITY 12693 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12626 + cell $meminit $meminit$\memory$libresoc.v:0$12694 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12626 + parameter \PRIORITY 12694 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12627 + cell $meminit $meminit$\memory$libresoc.v:0$12695 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12627 + parameter \PRIORITY 12695 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12628 + cell $meminit $meminit$\memory$libresoc.v:0$12696 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12628 + parameter \PRIORITY 12696 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12629 + cell $meminit $meminit$\memory$libresoc.v:0$12697 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12629 + parameter \PRIORITY 12697 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12630 + cell $meminit $meminit$\memory$libresoc.v:0$12698 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12630 + parameter \PRIORITY 12698 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12631 + cell $meminit $meminit$\memory$libresoc.v:0$12699 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12631 + parameter \PRIORITY 12699 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12632 + cell $meminit $meminit$\memory$libresoc.v:0$12700 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12632 + parameter \PRIORITY 12700 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12633 + cell $meminit $meminit$\memory$libresoc.v:0$12701 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12633 + parameter \PRIORITY 12701 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 32 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12634 + cell $meminit $meminit$\memory$libresoc.v:0$12702 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12634 + parameter \PRIORITY 12702 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 33 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12635 + cell $meminit $meminit$\memory$libresoc.v:0$12703 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12635 + parameter \PRIORITY 12703 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 34 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12636 + cell $meminit $meminit$\memory$libresoc.v:0$12704 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12636 + parameter \PRIORITY 12704 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 35 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12637 + cell $meminit $meminit$\memory$libresoc.v:0$12705 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12637 + parameter \PRIORITY 12705 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 36 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12638 + cell $meminit $meminit$\memory$libresoc.v:0$12706 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12638 + parameter \PRIORITY 12706 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 37 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12639 + cell $meminit $meminit$\memory$libresoc.v:0$12707 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12639 + parameter \PRIORITY 12707 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 38 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12640 + cell $meminit $meminit$\memory$libresoc.v:0$12708 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12640 + parameter \PRIORITY 12708 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 39 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12641 + cell $meminit $meminit$\memory$libresoc.v:0$12709 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12641 + parameter \PRIORITY 12709 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 40 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12642 + cell $meminit $meminit$\memory$libresoc.v:0$12710 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12642 + parameter \PRIORITY 12710 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 41 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12643 + cell $meminit $meminit$\memory$libresoc.v:0$12711 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12643 + parameter \PRIORITY 12711 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 42 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12644 + cell $meminit $meminit$\memory$libresoc.v:0$12712 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12644 + parameter \PRIORITY 12712 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 43 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12645 + cell $meminit $meminit$\memory$libresoc.v:0$12713 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12645 + parameter \PRIORITY 12713 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 44 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12646 + cell $meminit $meminit$\memory$libresoc.v:0$12714 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12646 + parameter \PRIORITY 12714 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 45 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12647 + cell $meminit $meminit$\memory$libresoc.v:0$12715 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12647 + parameter \PRIORITY 12715 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 46 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12648 + cell $meminit $meminit$\memory$libresoc.v:0$12716 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12648 + parameter \PRIORITY 12716 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 47 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12649 + cell $meminit $meminit$\memory$libresoc.v:0$12717 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12649 + parameter \PRIORITY 12717 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 48 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12650 + cell $meminit $meminit$\memory$libresoc.v:0$12718 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12650 + parameter \PRIORITY 12718 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 49 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12651 + cell $meminit $meminit$\memory$libresoc.v:0$12719 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12651 + parameter \PRIORITY 12719 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 50 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12652 + cell $meminit $meminit$\memory$libresoc.v:0$12720 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12652 + parameter \PRIORITY 12720 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 51 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12653 + cell $meminit $meminit$\memory$libresoc.v:0$12721 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12653 + parameter \PRIORITY 12721 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 52 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12654 + cell $meminit $meminit$\memory$libresoc.v:0$12722 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12654 + parameter \PRIORITY 12722 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 53 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12655 + cell $meminit $meminit$\memory$libresoc.v:0$12723 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12655 + parameter \PRIORITY 12723 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 54 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12656 + cell $meminit $meminit$\memory$libresoc.v:0$12724 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12656 + parameter \PRIORITY 12724 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 55 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12657 + cell $meminit $meminit$\memory$libresoc.v:0$12725 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12657 + parameter \PRIORITY 12725 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 56 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12658 + cell $meminit $meminit$\memory$libresoc.v:0$12726 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12658 + parameter \PRIORITY 12726 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 57 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12659 + cell $meminit $meminit$\memory$libresoc.v:0$12727 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12659 + parameter \PRIORITY 12727 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 58 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12660 + cell $meminit $meminit$\memory$libresoc.v:0$12728 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12660 + parameter \PRIORITY 12728 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 59 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12661 + cell $meminit $meminit$\memory$libresoc.v:0$12729 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12661 + parameter \PRIORITY 12729 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 60 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12662 + cell $meminit $meminit$\memory$libresoc.v:0$12730 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12662 + parameter \PRIORITY 12730 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 61 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12663 + cell $meminit $meminit$\memory$libresoc.v:0$12731 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12663 + parameter \PRIORITY 12731 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 62 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12664 + cell $meminit $meminit$\memory$libresoc.v:0$12732 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12664 + parameter \PRIORITY 12732 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 63 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12665 + cell $meminit $meminit$\memory$libresoc.v:0$12733 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12665 + parameter \PRIORITY 12733 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 64 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12666 + cell $meminit $meminit$\memory$libresoc.v:0$12734 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12666 + parameter \PRIORITY 12734 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 65 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12667 + cell $meminit $meminit$\memory$libresoc.v:0$12735 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12667 + parameter \PRIORITY 12735 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 66 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12668 + cell $meminit $meminit$\memory$libresoc.v:0$12736 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12668 + parameter \PRIORITY 12736 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 67 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12669 + cell $meminit $meminit$\memory$libresoc.v:0$12737 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12669 + parameter \PRIORITY 12737 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 68 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12670 + cell $meminit $meminit$\memory$libresoc.v:0$12738 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12670 + parameter \PRIORITY 12738 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 69 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12671 + cell $meminit $meminit$\memory$libresoc.v:0$12739 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12671 + parameter \PRIORITY 12739 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 70 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12672 + cell $meminit $meminit$\memory$libresoc.v:0$12740 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12672 + parameter \PRIORITY 12740 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 71 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12673 + cell $meminit $meminit$\memory$libresoc.v:0$12741 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12673 + parameter \PRIORITY 12741 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 72 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12674 + cell $meminit $meminit$\memory$libresoc.v:0$12742 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12674 + parameter \PRIORITY 12742 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 73 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12675 + cell $meminit $meminit$\memory$libresoc.v:0$12743 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12675 + parameter \PRIORITY 12743 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 74 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12676 + cell $meminit $meminit$\memory$libresoc.v:0$12744 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12676 + parameter \PRIORITY 12744 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 75 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12677 + cell $meminit $meminit$\memory$libresoc.v:0$12745 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12677 + parameter \PRIORITY 12745 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 76 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12678 + cell $meminit $meminit$\memory$libresoc.v:0$12746 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12678 + parameter \PRIORITY 12746 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 77 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12679 + cell $meminit $meminit$\memory$libresoc.v:0$12747 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12679 + parameter \PRIORITY 12747 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 78 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12680 + cell $meminit $meminit$\memory$libresoc.v:0$12748 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12680 + parameter \PRIORITY 12748 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 79 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12681 + cell $meminit $meminit$\memory$libresoc.v:0$12749 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12681 + parameter \PRIORITY 12749 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 80 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12682 + cell $meminit $meminit$\memory$libresoc.v:0$12750 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12682 + parameter \PRIORITY 12750 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 81 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12683 + cell $meminit $meminit$\memory$libresoc.v:0$12751 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12683 + parameter \PRIORITY 12751 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 82 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12684 + cell $meminit $meminit$\memory$libresoc.v:0$12752 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12684 + parameter \PRIORITY 12752 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 83 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12685 + cell $meminit $meminit$\memory$libresoc.v:0$12753 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12685 + parameter \PRIORITY 12753 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 84 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12686 + cell $meminit $meminit$\memory$libresoc.v:0$12754 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12686 + parameter \PRIORITY 12754 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 85 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12687 + cell $meminit $meminit$\memory$libresoc.v:0$12755 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12687 + parameter \PRIORITY 12755 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 86 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12688 + cell $meminit $meminit$\memory$libresoc.v:0$12756 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12688 + parameter \PRIORITY 12756 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 87 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12689 + cell $meminit $meminit$\memory$libresoc.v:0$12757 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12689 + parameter \PRIORITY 12757 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 88 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12690 + cell $meminit $meminit$\memory$libresoc.v:0$12758 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12690 + parameter \PRIORITY 12758 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 89 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12691 + cell $meminit $meminit$\memory$libresoc.v:0$12759 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12691 + parameter \PRIORITY 12759 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 90 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12692 + cell $meminit $meminit$\memory$libresoc.v:0$12760 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12692 + parameter \PRIORITY 12760 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 91 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12693 + cell $meminit $meminit$\memory$libresoc.v:0$12761 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12693 + parameter \PRIORITY 12761 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 92 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12694 + cell $meminit $meminit$\memory$libresoc.v:0$12762 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12694 + parameter \PRIORITY 12762 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 93 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12695 + cell $meminit $meminit$\memory$libresoc.v:0$12763 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12695 + parameter \PRIORITY 12763 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 94 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12696 + cell $meminit $meminit$\memory$libresoc.v:0$12764 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12696 + parameter \PRIORITY 12764 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 95 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12697 + cell $meminit $meminit$\memory$libresoc.v:0$12765 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12697 + parameter \PRIORITY 12765 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 96 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12698 + cell $meminit $meminit$\memory$libresoc.v:0$12766 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12698 + parameter \PRIORITY 12766 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 97 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12699 + cell $meminit $meminit$\memory$libresoc.v:0$12767 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12699 + parameter \PRIORITY 12767 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 98 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12700 + cell $meminit $meminit$\memory$libresoc.v:0$12768 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12700 + parameter \PRIORITY 12768 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 99 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12701 + cell $meminit $meminit$\memory$libresoc.v:0$12769 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12701 + parameter \PRIORITY 12769 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 100 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12702 + cell $meminit $meminit$\memory$libresoc.v:0$12770 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12702 + parameter \PRIORITY 12770 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 101 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12703 + cell $meminit $meminit$\memory$libresoc.v:0$12771 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12703 + parameter \PRIORITY 12771 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 102 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12704 + cell $meminit $meminit$\memory$libresoc.v:0$12772 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12704 + parameter \PRIORITY 12772 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 103 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12705 + cell $meminit $meminit$\memory$libresoc.v:0$12773 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12705 + parameter \PRIORITY 12773 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 104 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12706 + cell $meminit $meminit$\memory$libresoc.v:0$12774 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12706 + parameter \PRIORITY 12774 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 105 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12707 + cell $meminit $meminit$\memory$libresoc.v:0$12775 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12707 + parameter \PRIORITY 12775 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 106 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12708 + cell $meminit $meminit$\memory$libresoc.v:0$12776 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12708 + parameter \PRIORITY 12776 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 107 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12709 + cell $meminit $meminit$\memory$libresoc.v:0$12777 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12709 + parameter \PRIORITY 12777 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 108 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12710 + cell $meminit $meminit$\memory$libresoc.v:0$12778 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12710 + parameter \PRIORITY 12778 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 109 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:177220.26-177220.32" - cell $memrd $memrd$\memory$libresoc.v:177220$12596 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12779 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12779 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 110 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12780 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12780 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 111 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12781 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12781 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 112 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:185940.26-185940.32" + cell $memrd $memrd$\memory$libresoc.v:185940$12664 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -373341,83 +388380,83 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:177220$12596_DATA + connect \DATA $memrd$\memory$libresoc.v:185940$12664_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$12711 + cell $memwr $memwr$\memory$libresoc.v:0$12782 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 12711 + parameter \PRIORITY 12782 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:177218$12590_ADDR + connect \ADDR $memwr$\memory$libresoc.v:185938$12658_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:177218$12590_DATA - connect \EN $memwr$\memory$libresoc.v:177218$12590_EN + connect \DATA $memwr$\memory$libresoc.v:185938$12658_DATA + connect \EN $memwr$\memory$libresoc.v:185938$12658_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12714 + process $proc$libresoc.v:0$12785 sync always sync init end - attribute \src "libresoc.v:177068.7-177068.20" - process $proc$libresoc.v:177068$12712 + attribute \src "libresoc.v:185785.7-185785.20" + process $proc$libresoc.v:185785$12783 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177084.7-177084.23" - process $proc$libresoc.v:177084$12713 + attribute \src "libresoc.v:185801.7-185801.23" + process $proc$libresoc.v:185801$12784 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:177100.3-177101.35" - process $proc$libresoc.v:177100$12591 + attribute \src "libresoc.v:185817.3-185818.35" + process $proc$libresoc.v:185817$12659 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:177216.3-177219.6" - process $proc$libresoc.v:177216$12592 + attribute \src "libresoc.v:185936.3-185939.6" + process $proc$libresoc.v:185936$12660 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:177218$12590_ADDR[6:0]$12593 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:177218$12590_DATA[63:0]$12594 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:177218$12590_EN[63:0]$12595 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:177218.5-177218.59" + attribute \src "libresoc.v:185938.5-185938.59" switch \spr1__wen - attribute \src "libresoc.v:177218.9-177218.18" + attribute \src "libresoc.v:185938.9-185938.18" case 1'1 - assign $0$memwr$\memory$libresoc.v:177218$12590_ADDR[6:0]$12593 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:177218$12590_DATA[63:0]$12594 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:177218$12590_EN[63:0]$12595 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:177218$12590_ADDR $0$memwr$\memory$libresoc.v:177218$12590_ADDR[6:0]$12593 - update $memwr$\memory$libresoc.v:177218$12590_DATA $0$memwr$\memory$libresoc.v:177218$12590_DATA[63:0]$12594 - update $memwr$\memory$libresoc.v:177218$12590_EN $0$memwr$\memory$libresoc.v:177218$12590_EN[63:0]$12595 + update $memwr$\memory$libresoc.v:185938$12658_ADDR $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 + update $memwr$\memory$libresoc.v:185938$12658_DATA $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 + update $memwr$\memory$libresoc.v:185938$12658_EN $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 end - attribute \src "libresoc.v:177221.3-177229.6" - process $proc$libresoc.v:177221$12597 + attribute \src "libresoc.v:185941.3-185949.6" + process $proc$libresoc.v:185941$12665 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$12598 $1\ren_delay$next[0:0]$12599 - attribute \src "libresoc.v:177222.5-177222.29" + assign $0\ren_delay$next[0:0]$12666 $1\ren_delay$next[0:0]$12667 + attribute \src "libresoc.v:185942.5-185942.29" switch \initial - attribute \src "libresoc.v:177222.9-177222.17" + attribute \src "libresoc.v:185942.9-185942.17" case 1'1 case end @@ -373426,21 +388465,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$12599 1'0 + assign $1\ren_delay$next[0:0]$12667 1'0 case - assign $1\ren_delay$next[0:0]$12599 \spr1__ren + assign $1\ren_delay$next[0:0]$12667 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12598 + update \ren_delay$next $0\ren_delay$next[0:0]$12666 end - attribute \src "libresoc.v:177230.3-177239.6" - process $proc$libresoc.v:177230$12600 + attribute \src "libresoc.v:185950.3-185959.6" + process $proc$libresoc.v:185950$12668 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:177231.5-177231.29" + attribute \src "libresoc.v:185951.5-185951.29" switch \initial - attribute \src "libresoc.v:177231.9-177231.17" + attribute \src "libresoc.v:185951.9-185951.17" case 1'1 case end @@ -373456,503 +388495,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:177220$12596_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:185940$12664_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:177248.1-178495.10" +attribute \src "libresoc.v:185968.1-187221.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:177992.3-177993.25" + attribute \src "libresoc.v:186718.3-186719.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:177990.3-177991.40" + attribute \src "libresoc.v:186716.3-186717.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:178386.3-178394.6" - wire $0\alu_l_r_alu$next[0:0]$12928 - attribute \src "libresoc.v:177920.3-177921.39" + attribute \src "libresoc.v:187112.3-187120.6" + wire $0\alu_l_r_alu$next[0:0]$12999 + attribute \src "libresoc.v:186646.3-186647.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:178172.3-178184.6" - wire width 12 $0\alu_spr0_spr_op__fn_unit$next[11:0]$12850 - attribute \src "libresoc.v:177962.3-177963.65" - wire width 12 $0\alu_spr0_spr_op__fn_unit[11:0] - attribute \src "libresoc.v:178172.3-178184.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12851 - attribute \src "libresoc.v:177964.3-177965.59" + attribute \src "libresoc.v:186898.3-186910.6" + wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 + attribute \src "libresoc.v:186688.3-186689.65" + wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] + attribute \src "libresoc.v:186898.3-186910.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12922 + attribute \src "libresoc.v:186690.3-186691.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:178172.3-178184.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12852 - attribute \src "libresoc.v:177960.3-177961.69" + attribute \src "libresoc.v:186898.3-186910.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 + attribute \src "libresoc.v:186686.3-186687.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:178172.3-178184.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12853 - attribute \src "libresoc.v:177966.3-177967.67" + attribute \src "libresoc.v:186898.3-186910.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 + attribute \src "libresoc.v:186692.3-186693.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:178377.3-178385.6" - wire $0\alui_l_r_alui$next[0:0]$12925 - attribute \src "libresoc.v:177922.3-177923.43" + attribute \src "libresoc.v:187103.3-187111.6" + wire $0\alui_l_r_alui$next[0:0]$12996 + attribute \src "libresoc.v:186648.3-186649.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:178185.3-178206.6" - wire width 64 $0\data_r0__o$next[63:0]$12859 - attribute \src "libresoc.v:177956.3-177957.37" + attribute \src "libresoc.v:186911.3-186932.6" + wire width 64 $0\data_r0__o$next[63:0]$12930 + attribute \src "libresoc.v:186682.3-186683.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:178185.3-178206.6" - wire $0\data_r0__o_ok$next[0:0]$12860 - attribute \src "libresoc.v:177958.3-177959.43" + attribute \src "libresoc.v:186911.3-186932.6" + wire $0\data_r0__o_ok$next[0:0]$12931 + attribute \src "libresoc.v:186684.3-186685.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:178207.3-178228.6" - wire width 64 $0\data_r1__spr1$next[63:0]$12867 - attribute \src "libresoc.v:177952.3-177953.43" + attribute \src "libresoc.v:186933.3-186954.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12938 + attribute \src "libresoc.v:186678.3-186679.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:178207.3-178228.6" - wire $0\data_r1__spr1_ok$next[0:0]$12868 - attribute \src "libresoc.v:177954.3-177955.49" + attribute \src "libresoc.v:186933.3-186954.6" + wire $0\data_r1__spr1_ok$next[0:0]$12939 + attribute \src "libresoc.v:186680.3-186681.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:178229.3-178250.6" - wire width 64 $0\data_r2__fast1$next[63:0]$12875 - attribute \src "libresoc.v:177948.3-177949.45" + attribute \src "libresoc.v:186955.3-186976.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12946 + attribute \src "libresoc.v:186674.3-186675.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:178229.3-178250.6" - wire $0\data_r2__fast1_ok$next[0:0]$12876 - attribute \src "libresoc.v:177950.3-177951.51" + attribute \src "libresoc.v:186955.3-186976.6" + wire $0\data_r2__fast1_ok$next[0:0]$12947 + attribute \src "libresoc.v:186676.3-186677.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:178251.3-178272.6" - wire $0\data_r3__xer_so$next[0:0]$12883 - attribute \src "libresoc.v:177944.3-177945.47" + attribute \src "libresoc.v:186977.3-186998.6" + wire $0\data_r3__xer_so$next[0:0]$12954 + attribute \src "libresoc.v:186670.3-186671.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:178251.3-178272.6" - wire $0\data_r3__xer_so_ok$next[0:0]$12884 - attribute \src "libresoc.v:177946.3-177947.53" + attribute \src "libresoc.v:186977.3-186998.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12955 + attribute \src "libresoc.v:186672.3-186673.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:178273.3-178294.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$12891 - attribute \src "libresoc.v:177940.3-177941.47" + attribute \src "libresoc.v:186999.3-187020.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$12962 + attribute \src "libresoc.v:186666.3-186667.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:178273.3-178294.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$12892 - attribute \src "libresoc.v:177942.3-177943.53" + attribute \src "libresoc.v:186999.3-187020.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$12963 + attribute \src "libresoc.v:186668.3-186669.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:178295.3-178316.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$12899 - attribute \src "libresoc.v:177936.3-177937.47" + attribute \src "libresoc.v:187021.3-187042.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$12970 + attribute \src "libresoc.v:186662.3-186663.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:178295.3-178316.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$12900 - attribute \src "libresoc.v:177938.3-177939.53" + attribute \src "libresoc.v:187021.3-187042.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$12971 + attribute \src "libresoc.v:186664.3-186665.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:178395.3-178404.6" + attribute \src "libresoc.v:187121.3-187130.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:178405.3-178414.6" + attribute \src "libresoc.v:187131.3-187140.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:178415.3-178424.6" + attribute \src "libresoc.v:187141.3-187150.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:178425.3-178434.6" + attribute \src "libresoc.v:187151.3-187160.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:178435.3-178444.6" + attribute \src "libresoc.v:187161.3-187170.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:178445.3-178454.6" + attribute \src "libresoc.v:187171.3-187180.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:177249.7-177249.20" + attribute \src "libresoc.v:185969.7-185969.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178127.3-178135.6" - wire $0\opc_l_r_opc$next[0:0]$12835 - attribute \src "libresoc.v:177976.3-177977.39" + attribute \src "libresoc.v:186853.3-186861.6" + wire $0\opc_l_r_opc$next[0:0]$12906 + attribute \src "libresoc.v:186702.3-186703.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:178118.3-178126.6" - wire $0\opc_l_s_opc$next[0:0]$12832 - attribute \src "libresoc.v:177978.3-177979.39" + attribute \src "libresoc.v:186844.3-186852.6" + wire $0\opc_l_s_opc$next[0:0]$12903 + attribute \src "libresoc.v:186704.3-186705.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:178455.3-178463.6" - wire width 6 $0\prev_wr_go$next[5:0]$12937 - attribute \src "libresoc.v:177988.3-177989.37" + attribute \src "libresoc.v:187181.3-187189.6" + wire width 6 $0\prev_wr_go$next[5:0]$13008 + attribute \src "libresoc.v:186714.3-186715.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:178072.3-178081.6" + attribute \src "libresoc.v:186798.3-186807.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:178163.3-178171.6" - wire width 6 $0\req_l_r_req$next[5:0]$12847 - attribute \src "libresoc.v:177968.3-177969.39" + attribute \src "libresoc.v:186889.3-186897.6" + wire width 6 $0\req_l_r_req$next[5:0]$12918 + attribute \src "libresoc.v:186694.3-186695.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:178154.3-178162.6" - wire width 6 $0\req_l_s_req$next[5:0]$12844 - attribute \src "libresoc.v:177970.3-177971.39" + attribute \src "libresoc.v:186880.3-186888.6" + wire width 6 $0\req_l_s_req$next[5:0]$12915 + attribute \src "libresoc.v:186696.3-186697.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:178091.3-178099.6" - wire $0\rok_l_r_rdok$next[0:0]$12823 - attribute \src "libresoc.v:177984.3-177985.41" + attribute \src "libresoc.v:186817.3-186825.6" + wire $0\rok_l_r_rdok$next[0:0]$12894 + attribute \src "libresoc.v:186710.3-186711.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:178082.3-178090.6" - wire $0\rok_l_s_rdok$next[0:0]$12820 - attribute \src "libresoc.v:177986.3-177987.41" + attribute \src "libresoc.v:186808.3-186816.6" + wire $0\rok_l_s_rdok$next[0:0]$12891 + attribute \src "libresoc.v:186712.3-186713.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:178109.3-178117.6" - wire $0\rst_l_r_rst$next[0:0]$12829 - attribute \src "libresoc.v:177980.3-177981.39" + attribute \src "libresoc.v:186835.3-186843.6" + wire $0\rst_l_r_rst$next[0:0]$12900 + attribute \src "libresoc.v:186706.3-186707.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:178100.3-178108.6" - wire $0\rst_l_s_rst$next[0:0]$12826 - attribute \src "libresoc.v:177982.3-177983.39" + attribute \src "libresoc.v:186826.3-186834.6" + wire $0\rst_l_s_rst$next[0:0]$12897 + attribute \src "libresoc.v:186708.3-186709.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:178145.3-178153.6" - wire width 6 $0\src_l_r_src$next[5:0]$12841 - attribute \src "libresoc.v:177972.3-177973.39" + attribute \src "libresoc.v:186871.3-186879.6" + wire width 6 $0\src_l_r_src$next[5:0]$12912 + attribute \src "libresoc.v:186698.3-186699.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:178136.3-178144.6" - wire width 6 $0\src_l_s_src$next[5:0]$12838 - attribute \src "libresoc.v:177974.3-177975.39" + attribute \src "libresoc.v:186862.3-186870.6" + wire width 6 $0\src_l_s_src$next[5:0]$12909 + attribute \src "libresoc.v:186700.3-186701.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:178317.3-178326.6" - wire width 64 $0\src_r0$next[63:0]$12907 - attribute \src "libresoc.v:177934.3-177935.29" + attribute \src "libresoc.v:187043.3-187052.6" + wire width 64 $0\src_r0$next[63:0]$12978 + attribute \src "libresoc.v:186660.3-186661.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:178327.3-178336.6" - wire width 64 $0\src_r1$next[63:0]$12910 - attribute \src "libresoc.v:177932.3-177933.29" + attribute \src "libresoc.v:187053.3-187062.6" + wire width 64 $0\src_r1$next[63:0]$12981 + attribute \src "libresoc.v:186658.3-186659.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:178337.3-178346.6" - wire width 64 $0\src_r2$next[63:0]$12913 - attribute \src "libresoc.v:177930.3-177931.29" + attribute \src "libresoc.v:187063.3-187072.6" + wire width 64 $0\src_r2$next[63:0]$12984 + attribute \src "libresoc.v:186656.3-186657.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:178347.3-178356.6" - wire $0\src_r3$next[0:0]$12916 - attribute \src "libresoc.v:177928.3-177929.29" + attribute \src "libresoc.v:187073.3-187082.6" + wire $0\src_r3$next[0:0]$12987 + attribute \src "libresoc.v:186654.3-186655.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:178357.3-178366.6" - wire width 2 $0\src_r4$next[1:0]$12919 - attribute \src "libresoc.v:177926.3-177927.29" + attribute \src "libresoc.v:187083.3-187092.6" + wire width 2 $0\src_r4$next[1:0]$12990 + attribute \src "libresoc.v:186652.3-186653.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:178367.3-178376.6" - wire width 2 $0\src_r5$next[1:0]$12922 - attribute \src "libresoc.v:177924.3-177925.29" + attribute \src "libresoc.v:187093.3-187102.6" + wire width 2 $0\src_r5$next[1:0]$12993 + attribute \src "libresoc.v:186650.3-186651.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:177385.7-177385.24" + attribute \src "libresoc.v:186105.7-186105.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:177395.7-177395.26" + attribute \src "libresoc.v:186115.7-186115.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:178386.3-178394.6" - wire $1\alu_l_r_alu$next[0:0]$12929 - attribute \src "libresoc.v:177403.7-177403.25" + attribute \src "libresoc.v:187112.3-187120.6" + wire $1\alu_l_r_alu$next[0:0]$13000 + attribute \src "libresoc.v:186123.7-186123.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:178172.3-178184.6" - wire width 12 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12854 - attribute \src "libresoc.v:177446.14-177446.48" - wire width 12 $1\alu_spr0_spr_op__fn_unit[11:0] - attribute \src "libresoc.v:178172.3-178184.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12855 - attribute \src "libresoc.v:177450.14-177450.43" + attribute \src "libresoc.v:186898.3-186910.6" + wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 + attribute \src "libresoc.v:186168.14-186168.49" + wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] + attribute \src "libresoc.v:186898.3-186910.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12926 + attribute \src "libresoc.v:186172.14-186172.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:178172.3-178184.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12856 - attribute \src "libresoc.v:177528.13-177528.47" + attribute \src "libresoc.v:186898.3-186910.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 + attribute \src "libresoc.v:186251.13-186251.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:178172.3-178184.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12857 - attribute \src "libresoc.v:177532.7-177532.39" + attribute \src "libresoc.v:186898.3-186910.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 + attribute \src "libresoc.v:186255.7-186255.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:178377.3-178385.6" - wire $1\alui_l_r_alui$next[0:0]$12926 - attribute \src "libresoc.v:177550.7-177550.27" + attribute \src "libresoc.v:187103.3-187111.6" + wire $1\alui_l_r_alui$next[0:0]$12997 + attribute \src "libresoc.v:186273.7-186273.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:178185.3-178206.6" - wire width 64 $1\data_r0__o$next[63:0]$12861 - attribute \src "libresoc.v:177582.14-177582.47" + attribute \src "libresoc.v:186911.3-186932.6" + wire width 64 $1\data_r0__o$next[63:0]$12932 + attribute \src "libresoc.v:186305.14-186305.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:178185.3-178206.6" - wire $1\data_r0__o_ok$next[0:0]$12862 - attribute \src "libresoc.v:177586.7-177586.27" + attribute \src "libresoc.v:186911.3-186932.6" + wire $1\data_r0__o_ok$next[0:0]$12933 + attribute \src "libresoc.v:186309.7-186309.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:178207.3-178228.6" - wire width 64 $1\data_r1__spr1$next[63:0]$12869 - attribute \src "libresoc.v:177590.14-177590.50" + attribute \src "libresoc.v:186933.3-186954.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12940 + attribute \src "libresoc.v:186313.14-186313.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:178207.3-178228.6" - wire $1\data_r1__spr1_ok$next[0:0]$12870 - attribute \src "libresoc.v:177594.7-177594.30" + attribute \src "libresoc.v:186933.3-186954.6" + wire $1\data_r1__spr1_ok$next[0:0]$12941 + attribute \src "libresoc.v:186317.7-186317.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:178229.3-178250.6" - wire width 64 $1\data_r2__fast1$next[63:0]$12877 - attribute \src "libresoc.v:177598.14-177598.51" + attribute \src "libresoc.v:186955.3-186976.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12948 + attribute \src "libresoc.v:186321.14-186321.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:178229.3-178250.6" - wire $1\data_r2__fast1_ok$next[0:0]$12878 - attribute \src "libresoc.v:177602.7-177602.31" + attribute \src "libresoc.v:186955.3-186976.6" + wire $1\data_r2__fast1_ok$next[0:0]$12949 + attribute \src "libresoc.v:186325.7-186325.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:178251.3-178272.6" - wire $1\data_r3__xer_so$next[0:0]$12885 - attribute \src "libresoc.v:177606.7-177606.29" + attribute \src "libresoc.v:186977.3-186998.6" + wire $1\data_r3__xer_so$next[0:0]$12956 + attribute \src "libresoc.v:186329.7-186329.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:178251.3-178272.6" - wire $1\data_r3__xer_so_ok$next[0:0]$12886 - attribute \src "libresoc.v:177610.7-177610.32" + attribute \src "libresoc.v:186977.3-186998.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12957 + attribute \src "libresoc.v:186333.7-186333.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:178273.3-178294.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$12893 - attribute \src "libresoc.v:177614.13-177614.35" + attribute \src "libresoc.v:186999.3-187020.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$12964 + attribute \src "libresoc.v:186337.13-186337.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:178273.3-178294.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$12894 - attribute \src "libresoc.v:177618.7-177618.32" + attribute \src "libresoc.v:186999.3-187020.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$12965 + attribute \src "libresoc.v:186341.7-186341.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:178295.3-178316.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$12901 - attribute \src "libresoc.v:177622.13-177622.35" + attribute \src "libresoc.v:187021.3-187042.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$12972 + attribute \src "libresoc.v:186345.13-186345.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:178295.3-178316.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$12902 - attribute \src "libresoc.v:177626.7-177626.32" + attribute \src "libresoc.v:187021.3-187042.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$12973 + attribute \src "libresoc.v:186349.7-186349.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:178395.3-178404.6" + attribute \src "libresoc.v:187121.3-187130.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:178405.3-178414.6" + attribute \src "libresoc.v:187131.3-187140.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:178415.3-178424.6" + attribute \src "libresoc.v:187141.3-187150.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:178425.3-178434.6" + attribute \src "libresoc.v:187151.3-187160.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:178435.3-178444.6" + attribute \src "libresoc.v:187161.3-187170.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:178445.3-178454.6" + attribute \src "libresoc.v:187171.3-187180.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:178127.3-178135.6" - wire $1\opc_l_r_opc$next[0:0]$12836 - attribute \src "libresoc.v:177654.7-177654.25" + attribute \src "libresoc.v:186853.3-186861.6" + wire $1\opc_l_r_opc$next[0:0]$12907 + attribute \src "libresoc.v:186377.7-186377.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:178118.3-178126.6" - wire $1\opc_l_s_opc$next[0:0]$12833 - attribute \src "libresoc.v:177658.7-177658.25" + attribute \src "libresoc.v:186844.3-186852.6" + wire $1\opc_l_s_opc$next[0:0]$12904 + attribute \src "libresoc.v:186381.7-186381.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:178455.3-178463.6" - wire width 6 $1\prev_wr_go$next[5:0]$12938 - attribute \src "libresoc.v:177757.13-177757.31" + attribute \src "libresoc.v:187181.3-187189.6" + wire width 6 $1\prev_wr_go$next[5:0]$13009 + attribute \src "libresoc.v:186483.13-186483.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:178072.3-178081.6" + attribute \src "libresoc.v:186798.3-186807.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:178163.3-178171.6" - wire width 6 $1\req_l_r_req$next[5:0]$12848 - attribute \src "libresoc.v:177765.13-177765.32" + attribute \src "libresoc.v:186889.3-186897.6" + wire width 6 $1\req_l_r_req$next[5:0]$12919 + attribute \src "libresoc.v:186491.13-186491.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:178154.3-178162.6" - wire width 6 $1\req_l_s_req$next[5:0]$12845 - attribute \src "libresoc.v:177769.13-177769.32" + attribute \src "libresoc.v:186880.3-186888.6" + wire width 6 $1\req_l_s_req$next[5:0]$12916 + attribute \src "libresoc.v:186495.13-186495.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:178091.3-178099.6" - wire $1\rok_l_r_rdok$next[0:0]$12824 - attribute \src "libresoc.v:177781.7-177781.26" + attribute \src "libresoc.v:186817.3-186825.6" + wire $1\rok_l_r_rdok$next[0:0]$12895 + attribute \src "libresoc.v:186507.7-186507.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:178082.3-178090.6" - wire $1\rok_l_s_rdok$next[0:0]$12821 - attribute \src "libresoc.v:177785.7-177785.26" + attribute \src "libresoc.v:186808.3-186816.6" + wire $1\rok_l_s_rdok$next[0:0]$12892 + attribute \src "libresoc.v:186511.7-186511.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:178109.3-178117.6" - wire $1\rst_l_r_rst$next[0:0]$12830 - attribute \src "libresoc.v:177789.7-177789.25" + attribute \src "libresoc.v:186835.3-186843.6" + wire $1\rst_l_r_rst$next[0:0]$12901 + attribute \src "libresoc.v:186515.7-186515.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:178100.3-178108.6" - wire $1\rst_l_s_rst$next[0:0]$12827 - attribute \src "libresoc.v:177793.7-177793.25" + attribute \src "libresoc.v:186826.3-186834.6" + wire $1\rst_l_s_rst$next[0:0]$12898 + attribute \src "libresoc.v:186519.7-186519.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:178145.3-178153.6" - wire width 6 $1\src_l_r_src$next[5:0]$12842 - attribute \src "libresoc.v:177815.13-177815.32" + attribute \src "libresoc.v:186871.3-186879.6" + wire width 6 $1\src_l_r_src$next[5:0]$12913 + attribute \src "libresoc.v:186541.13-186541.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:178136.3-178144.6" - wire width 6 $1\src_l_s_src$next[5:0]$12839 - attribute \src "libresoc.v:177819.13-177819.32" + attribute \src "libresoc.v:186862.3-186870.6" + wire width 6 $1\src_l_s_src$next[5:0]$12910 + attribute \src "libresoc.v:186545.13-186545.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:178317.3-178326.6" - wire width 64 $1\src_r0$next[63:0]$12908 - attribute \src "libresoc.v:177823.14-177823.43" + attribute \src "libresoc.v:187043.3-187052.6" + wire width 64 $1\src_r0$next[63:0]$12979 + attribute \src "libresoc.v:186549.14-186549.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:178327.3-178336.6" - wire width 64 $1\src_r1$next[63:0]$12911 - attribute \src "libresoc.v:177827.14-177827.43" + attribute \src "libresoc.v:187053.3-187062.6" + wire width 64 $1\src_r1$next[63:0]$12982 + attribute \src "libresoc.v:186553.14-186553.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:178337.3-178346.6" - wire width 64 $1\src_r2$next[63:0]$12914 - attribute \src "libresoc.v:177831.14-177831.43" + attribute \src "libresoc.v:187063.3-187072.6" + wire width 64 $1\src_r2$next[63:0]$12985 + attribute \src "libresoc.v:186557.14-186557.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:178347.3-178356.6" - wire $1\src_r3$next[0:0]$12917 - attribute \src "libresoc.v:177835.7-177835.20" + attribute \src "libresoc.v:187073.3-187082.6" + wire $1\src_r3$next[0:0]$12988 + attribute \src "libresoc.v:186561.7-186561.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:178357.3-178366.6" - wire width 2 $1\src_r4$next[1:0]$12920 - attribute \src "libresoc.v:177839.13-177839.26" + attribute \src "libresoc.v:187083.3-187092.6" + wire width 2 $1\src_r4$next[1:0]$12991 + attribute \src "libresoc.v:186565.13-186565.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:178367.3-178376.6" - wire width 2 $1\src_r5$next[1:0]$12923 - attribute \src "libresoc.v:177843.13-177843.26" + attribute \src "libresoc.v:187093.3-187102.6" + wire width 2 $1\src_r5$next[1:0]$12994 + attribute \src "libresoc.v:186569.13-186569.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:178185.3-178206.6" - wire width 64 $2\data_r0__o$next[63:0]$12863 - attribute \src "libresoc.v:178185.3-178206.6" - wire $2\data_r0__o_ok$next[0:0]$12864 - attribute \src "libresoc.v:178207.3-178228.6" - wire width 64 $2\data_r1__spr1$next[63:0]$12871 - attribute \src "libresoc.v:178207.3-178228.6" - wire $2\data_r1__spr1_ok$next[0:0]$12872 - attribute \src "libresoc.v:178229.3-178250.6" - wire width 64 $2\data_r2__fast1$next[63:0]$12879 - attribute \src "libresoc.v:178229.3-178250.6" - wire $2\data_r2__fast1_ok$next[0:0]$12880 - attribute \src "libresoc.v:178251.3-178272.6" - wire $2\data_r3__xer_so$next[0:0]$12887 - attribute \src "libresoc.v:178251.3-178272.6" - wire $2\data_r3__xer_so_ok$next[0:0]$12888 - attribute \src "libresoc.v:178273.3-178294.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$12895 - attribute \src "libresoc.v:178273.3-178294.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$12896 - attribute \src "libresoc.v:178295.3-178316.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$12903 - attribute \src "libresoc.v:178295.3-178316.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$12904 - attribute \src "libresoc.v:178185.3-178206.6" - wire $3\data_r0__o_ok$next[0:0]$12865 - attribute \src "libresoc.v:178207.3-178228.6" - wire $3\data_r1__spr1_ok$next[0:0]$12873 - attribute \src "libresoc.v:178229.3-178250.6" - wire $3\data_r2__fast1_ok$next[0:0]$12881 - attribute \src "libresoc.v:178251.3-178272.6" - wire $3\data_r3__xer_so_ok$next[0:0]$12889 - attribute \src "libresoc.v:178273.3-178294.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$12897 - attribute \src "libresoc.v:178295.3-178316.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$12905 - attribute \src "libresoc.v:177855.19-177855.133" - wire $and$libresoc.v:177855$12716_Y - attribute \src "libresoc.v:177856.19-177856.183" - wire width 6 $and$libresoc.v:177856$12717_Y - attribute \src "libresoc.v:177857.19-177857.115" - wire width 6 $and$libresoc.v:177857$12718_Y - attribute \src "libresoc.v:177859.19-177859.115" - wire width 6 $and$libresoc.v:177859$12720_Y - attribute \src "libresoc.v:177860.19-177860.125" - wire $and$libresoc.v:177860$12721_Y - attribute \src "libresoc.v:177861.19-177861.125" - wire $and$libresoc.v:177861$12722_Y - attribute \src "libresoc.v:177862.19-177862.125" - wire $and$libresoc.v:177862$12723_Y - attribute \src "libresoc.v:177863.19-177863.125" - wire $and$libresoc.v:177863$12724_Y - attribute \src "libresoc.v:177864.19-177864.125" - wire $and$libresoc.v:177864$12725_Y - attribute \src "libresoc.v:177866.19-177866.125" - wire $and$libresoc.v:177866$12727_Y - attribute \src "libresoc.v:177867.19-177867.165" - wire width 6 $and$libresoc.v:177867$12728_Y - attribute \src "libresoc.v:177868.19-177868.121" - wire width 6 $and$libresoc.v:177868$12729_Y - attribute \src "libresoc.v:177869.19-177869.127" - wire $and$libresoc.v:177869$12730_Y - attribute \src "libresoc.v:177870.19-177870.127" - wire $and$libresoc.v:177870$12731_Y - attribute \src "libresoc.v:177872.19-177872.127" - wire $and$libresoc.v:177872$12733_Y - attribute \src "libresoc.v:177873.19-177873.127" - wire $and$libresoc.v:177873$12734_Y - attribute \src "libresoc.v:177874.19-177874.127" - wire $and$libresoc.v:177874$12735_Y - attribute \src "libresoc.v:177875.19-177875.127" - wire $and$libresoc.v:177875$12736_Y - attribute \src "libresoc.v:177876.18-177876.110" - wire $and$libresoc.v:177876$12737_Y - attribute \src "libresoc.v:177878.18-177878.98" - wire $and$libresoc.v:177878$12739_Y - attribute \src "libresoc.v:177880.18-177880.100" - wire $and$libresoc.v:177880$12741_Y - attribute \src "libresoc.v:177881.18-177881.182" - wire width 6 $and$libresoc.v:177881$12742_Y - attribute \src "libresoc.v:177883.18-177883.119" - wire width 6 $and$libresoc.v:177883$12744_Y - attribute \src "libresoc.v:177886.18-177886.116" - wire $and$libresoc.v:177886$12747_Y - attribute \src "libresoc.v:177891.18-177891.113" - wire $and$libresoc.v:177891$12752_Y - attribute \src "libresoc.v:177892.18-177892.125" - wire width 6 $and$libresoc.v:177892$12753_Y - attribute \src "libresoc.v:177894.18-177894.112" - wire $and$libresoc.v:177894$12755_Y - attribute \src "libresoc.v:177896.18-177896.126" - wire $and$libresoc.v:177896$12757_Y - attribute \src "libresoc.v:177897.18-177897.126" - wire $and$libresoc.v:177897$12758_Y - attribute \src "libresoc.v:177898.18-177898.117" - wire $and$libresoc.v:177898$12759_Y - attribute \src "libresoc.v:177903.18-177903.130" - wire $and$libresoc.v:177903$12764_Y - attribute \src "libresoc.v:177904.17-177904.123" - wire $and$libresoc.v:177904$12765_Y - attribute \src "libresoc.v:177905.18-177905.124" - wire width 6 $and$libresoc.v:177905$12766_Y - attribute \src "libresoc.v:177907.18-177907.116" - wire $and$libresoc.v:177907$12768_Y - attribute \src "libresoc.v:177908.18-177908.119" - wire $and$libresoc.v:177908$12769_Y - attribute \src "libresoc.v:177909.18-177909.120" - wire $and$libresoc.v:177909$12770_Y - attribute \src "libresoc.v:177910.18-177910.121" - wire $and$libresoc.v:177910$12771_Y - attribute \src "libresoc.v:177911.18-177911.121" - wire $and$libresoc.v:177911$12772_Y - attribute \src "libresoc.v:177912.18-177912.121" - wire $and$libresoc.v:177912$12773_Y - attribute \src "libresoc.v:177919.18-177919.134" - wire $and$libresoc.v:177919$12780_Y - attribute \src "libresoc.v:177893.18-177893.113" - wire $eq$libresoc.v:177893$12754_Y - attribute \src "libresoc.v:177895.18-177895.119" - wire $eq$libresoc.v:177895$12756_Y - attribute \src "libresoc.v:177854.17-177854.113" - wire width 6 $not$libresoc.v:177854$12715_Y - attribute \src "libresoc.v:177858.19-177858.115" - wire width 6 $not$libresoc.v:177858$12719_Y - attribute \src "libresoc.v:177877.18-177877.97" - wire $not$libresoc.v:177877$12738_Y - attribute \src "libresoc.v:177879.18-177879.99" - wire $not$libresoc.v:177879$12740_Y - attribute \src "libresoc.v:177882.18-177882.113" - wire width 6 $not$libresoc.v:177882$12743_Y - attribute \src "libresoc.v:177885.18-177885.106" - wire $not$libresoc.v:177885$12746_Y - attribute \src "libresoc.v:177890.18-177890.120" - wire $not$libresoc.v:177890$12751_Y - attribute \src "libresoc.v:177865.18-177865.118" - wire width 6 $or$libresoc.v:177865$12726_Y - attribute \src "libresoc.v:177889.18-177889.112" - wire $or$libresoc.v:177889$12750_Y - attribute \src "libresoc.v:177899.18-177899.122" - wire $or$libresoc.v:177899$12760_Y - attribute \src "libresoc.v:177900.18-177900.124" - wire $or$libresoc.v:177900$12761_Y - attribute \src "libresoc.v:177901.18-177901.194" - wire width 6 $or$libresoc.v:177901$12762_Y - attribute \src "libresoc.v:177902.18-177902.194" - wire width 6 $or$libresoc.v:177902$12763_Y - attribute \src "libresoc.v:177906.18-177906.120" - wire width 6 $or$libresoc.v:177906$12767_Y - attribute \src "libresoc.v:177871.17-177871.105" - wire $reduce_and$libresoc.v:177871$12732_Y - attribute \src "libresoc.v:177884.18-177884.106" - wire $reduce_or$libresoc.v:177884$12745_Y - attribute \src "libresoc.v:177887.18-177887.113" - wire $reduce_or$libresoc.v:177887$12748_Y - attribute \src "libresoc.v:177888.18-177888.112" - wire $reduce_or$libresoc.v:177888$12749_Y - attribute \src "libresoc.v:177913.18-177913.118" - wire width 64 $ternary$libresoc.v:177913$12774_Y - attribute \src "libresoc.v:177914.18-177914.118" - wire width 64 $ternary$libresoc.v:177914$12775_Y - attribute \src "libresoc.v:177915.18-177915.118" - wire width 64 $ternary$libresoc.v:177915$12776_Y - attribute \src "libresoc.v:177916.18-177916.118" - wire $ternary$libresoc.v:177916$12777_Y - attribute \src "libresoc.v:177917.18-177917.118" - wire width 2 $ternary$libresoc.v:177917$12778_Y - attribute \src "libresoc.v:177918.18-177918.118" - wire width 2 $ternary$libresoc.v:177918$12779_Y + attribute \src "libresoc.v:186911.3-186932.6" + wire width 64 $2\data_r0__o$next[63:0]$12934 + attribute \src "libresoc.v:186911.3-186932.6" + wire $2\data_r0__o_ok$next[0:0]$12935 + attribute \src "libresoc.v:186933.3-186954.6" + wire width 64 $2\data_r1__spr1$next[63:0]$12942 + attribute \src "libresoc.v:186933.3-186954.6" + wire $2\data_r1__spr1_ok$next[0:0]$12943 + attribute \src "libresoc.v:186955.3-186976.6" + wire width 64 $2\data_r2__fast1$next[63:0]$12950 + attribute \src "libresoc.v:186955.3-186976.6" + wire $2\data_r2__fast1_ok$next[0:0]$12951 + attribute \src "libresoc.v:186977.3-186998.6" + wire $2\data_r3__xer_so$next[0:0]$12958 + attribute \src "libresoc.v:186977.3-186998.6" + wire $2\data_r3__xer_so_ok$next[0:0]$12959 + attribute \src "libresoc.v:186999.3-187020.6" + wire width 2 $2\data_r4__xer_ov$next[1:0]$12966 + attribute \src "libresoc.v:186999.3-187020.6" + wire $2\data_r4__xer_ov_ok$next[0:0]$12967 + attribute \src "libresoc.v:187021.3-187042.6" + wire width 2 $2\data_r5__xer_ca$next[1:0]$12974 + attribute \src "libresoc.v:187021.3-187042.6" + wire $2\data_r5__xer_ca_ok$next[0:0]$12975 + attribute \src "libresoc.v:186911.3-186932.6" + wire $3\data_r0__o_ok$next[0:0]$12936 + attribute \src "libresoc.v:186933.3-186954.6" + wire $3\data_r1__spr1_ok$next[0:0]$12944 + attribute \src "libresoc.v:186955.3-186976.6" + wire $3\data_r2__fast1_ok$next[0:0]$12952 + attribute \src "libresoc.v:186977.3-186998.6" + wire $3\data_r3__xer_so_ok$next[0:0]$12960 + attribute \src "libresoc.v:186999.3-187020.6" + wire $3\data_r4__xer_ov_ok$next[0:0]$12968 + attribute \src "libresoc.v:187021.3-187042.6" + wire $3\data_r5__xer_ca_ok$next[0:0]$12976 + attribute \src "libresoc.v:186581.19-186581.133" + wire $and$libresoc.v:186581$12787_Y + attribute \src "libresoc.v:186582.19-186582.183" + wire width 6 $and$libresoc.v:186582$12788_Y + attribute \src "libresoc.v:186583.19-186583.115" + wire width 6 $and$libresoc.v:186583$12789_Y + attribute \src "libresoc.v:186585.19-186585.115" + wire width 6 $and$libresoc.v:186585$12791_Y + attribute \src "libresoc.v:186586.19-186586.125" + wire $and$libresoc.v:186586$12792_Y + attribute \src "libresoc.v:186587.19-186587.125" + wire $and$libresoc.v:186587$12793_Y + attribute \src "libresoc.v:186588.19-186588.125" + wire $and$libresoc.v:186588$12794_Y + attribute \src "libresoc.v:186589.19-186589.125" + wire $and$libresoc.v:186589$12795_Y + attribute \src "libresoc.v:186590.19-186590.125" + wire $and$libresoc.v:186590$12796_Y + attribute \src "libresoc.v:186592.19-186592.125" + wire $and$libresoc.v:186592$12798_Y + attribute \src "libresoc.v:186593.19-186593.165" + wire width 6 $and$libresoc.v:186593$12799_Y + attribute \src "libresoc.v:186594.19-186594.121" + wire width 6 $and$libresoc.v:186594$12800_Y + attribute \src "libresoc.v:186595.19-186595.127" + wire $and$libresoc.v:186595$12801_Y + attribute \src "libresoc.v:186596.19-186596.127" + wire $and$libresoc.v:186596$12802_Y + attribute \src "libresoc.v:186598.19-186598.127" + wire $and$libresoc.v:186598$12804_Y + attribute \src "libresoc.v:186599.19-186599.127" + wire $and$libresoc.v:186599$12805_Y + attribute \src "libresoc.v:186600.19-186600.127" + wire $and$libresoc.v:186600$12806_Y + attribute \src "libresoc.v:186601.19-186601.127" + wire $and$libresoc.v:186601$12807_Y + attribute \src "libresoc.v:186602.18-186602.110" + wire $and$libresoc.v:186602$12808_Y + attribute \src "libresoc.v:186604.18-186604.98" + wire $and$libresoc.v:186604$12810_Y + attribute \src "libresoc.v:186606.18-186606.100" + wire $and$libresoc.v:186606$12812_Y + attribute \src "libresoc.v:186607.18-186607.182" + wire width 6 $and$libresoc.v:186607$12813_Y + attribute \src "libresoc.v:186609.18-186609.119" + wire width 6 $and$libresoc.v:186609$12815_Y + attribute \src "libresoc.v:186612.18-186612.116" + wire $and$libresoc.v:186612$12818_Y + attribute \src "libresoc.v:186617.18-186617.113" + wire $and$libresoc.v:186617$12823_Y + attribute \src "libresoc.v:186618.18-186618.125" + wire width 6 $and$libresoc.v:186618$12824_Y + attribute \src "libresoc.v:186620.18-186620.112" + wire $and$libresoc.v:186620$12826_Y + attribute \src "libresoc.v:186622.18-186622.126" + wire $and$libresoc.v:186622$12828_Y + attribute \src "libresoc.v:186623.18-186623.126" + wire $and$libresoc.v:186623$12829_Y + attribute \src "libresoc.v:186624.18-186624.117" + wire $and$libresoc.v:186624$12830_Y + attribute \src "libresoc.v:186629.18-186629.130" + wire $and$libresoc.v:186629$12835_Y + attribute \src "libresoc.v:186630.17-186630.123" + wire $and$libresoc.v:186630$12836_Y + attribute \src "libresoc.v:186631.18-186631.124" + wire width 6 $and$libresoc.v:186631$12837_Y + attribute \src "libresoc.v:186633.18-186633.116" + wire $and$libresoc.v:186633$12839_Y + attribute \src "libresoc.v:186634.18-186634.119" + wire $and$libresoc.v:186634$12840_Y + attribute \src "libresoc.v:186635.18-186635.120" + wire $and$libresoc.v:186635$12841_Y + attribute \src "libresoc.v:186636.18-186636.121" + wire $and$libresoc.v:186636$12842_Y + attribute \src "libresoc.v:186637.18-186637.121" + wire $and$libresoc.v:186637$12843_Y + attribute \src "libresoc.v:186638.18-186638.121" + wire $and$libresoc.v:186638$12844_Y + attribute \src "libresoc.v:186645.18-186645.134" + wire $and$libresoc.v:186645$12851_Y + attribute \src "libresoc.v:186619.18-186619.113" + wire $eq$libresoc.v:186619$12825_Y + attribute \src "libresoc.v:186621.18-186621.119" + wire $eq$libresoc.v:186621$12827_Y + attribute \src "libresoc.v:186580.17-186580.113" + wire width 6 $not$libresoc.v:186580$12786_Y + attribute \src "libresoc.v:186584.19-186584.115" + wire width 6 $not$libresoc.v:186584$12790_Y + attribute \src "libresoc.v:186603.18-186603.97" + wire $not$libresoc.v:186603$12809_Y + attribute \src "libresoc.v:186605.18-186605.99" + wire $not$libresoc.v:186605$12811_Y + attribute \src "libresoc.v:186608.18-186608.113" + wire width 6 $not$libresoc.v:186608$12814_Y + attribute \src "libresoc.v:186611.18-186611.106" + wire $not$libresoc.v:186611$12817_Y + attribute \src "libresoc.v:186616.18-186616.120" + wire $not$libresoc.v:186616$12822_Y + attribute \src "libresoc.v:186591.18-186591.118" + wire width 6 $or$libresoc.v:186591$12797_Y + attribute \src "libresoc.v:186615.18-186615.112" + wire $or$libresoc.v:186615$12821_Y + attribute \src "libresoc.v:186625.18-186625.122" + wire $or$libresoc.v:186625$12831_Y + attribute \src "libresoc.v:186626.18-186626.124" + wire $or$libresoc.v:186626$12832_Y + attribute \src "libresoc.v:186627.18-186627.194" + wire width 6 $or$libresoc.v:186627$12833_Y + attribute \src "libresoc.v:186628.18-186628.194" + wire width 6 $or$libresoc.v:186628$12834_Y + attribute \src "libresoc.v:186632.18-186632.120" + wire width 6 $or$libresoc.v:186632$12838_Y + attribute \src "libresoc.v:186597.17-186597.105" + wire $reduce_and$libresoc.v:186597$12803_Y + attribute \src "libresoc.v:186610.18-186610.106" + wire $reduce_or$libresoc.v:186610$12816_Y + attribute \src "libresoc.v:186613.18-186613.113" + wire $reduce_or$libresoc.v:186613$12819_Y + attribute \src "libresoc.v:186614.18-186614.112" + wire $reduce_or$libresoc.v:186614$12820_Y + attribute \src "libresoc.v:186639.18-186639.118" + wire width 64 $ternary$libresoc.v:186639$12845_Y + attribute \src "libresoc.v:186640.18-186640.118" + wire width 64 $ternary$libresoc.v:186640$12846_Y + attribute \src "libresoc.v:186641.18-186641.118" + wire width 64 $ternary$libresoc.v:186641$12847_Y + attribute \src "libresoc.v:186642.18-186642.118" + wire $ternary$libresoc.v:186642$12848_Y + attribute \src "libresoc.v:186643.18-186643.118" + wire width 2 $ternary$libresoc.v:186643$12849_Y + attribute \src "libresoc.v:186644.18-186644.118" + wire width 2 $ternary$libresoc.v:186644$12850_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -373995,13 +389034,13 @@ module \spr0 wire \$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 6 \$24 @@ -374069,47 +389108,47 @@ module \spr0 wire \$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$84 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$90 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$92 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 2 \$94 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 2 \$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse @@ -374119,15 +389158,15 @@ module \spr0 wire width 64 \alu_spr0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_fast1$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_spr0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_spr0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_spr0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_spr0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_spr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_ra @@ -374136,22 +389175,24 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_spr1$1 attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_spr0_spr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_spr0_spr_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_spr0_spr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_spr0_spr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_spr0_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -374230,6 +389271,7 @@ module \spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_spr0_spr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -374250,17 +389292,17 @@ module \spr0 wire \alu_spr0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_spr0_xer_so$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o @@ -374346,35 +389388,37 @@ module \spr0 wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \fast1_ok - attribute \src "libresoc.v:177249.7-177249.15" + attribute \src "libresoc.v:185969.7-185969.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_spr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" @@ -374451,6 +389495,7 @@ module \spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -374461,15 +389506,15 @@ module \spr0 wire width 6 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -374477,23 +389522,23 @@ module \spr0 wire width 6 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 6 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -374511,39 +389556,39 @@ module \spr0 wire width 2 input 14 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 13 \src6_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any @@ -374554,7 +389599,7 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:177855$12716 + cell $and $and$libresoc.v:186581$12787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374562,10 +389607,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:177855$12716_Y + connect \Y $and$libresoc.v:186581$12787_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:177856$12717 + cell $and $and$libresoc.v:186582$12788 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374573,10 +389618,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:177856$12717_Y + connect \Y $and$libresoc.v:186582$12788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:177857$12718 + cell $and $and$libresoc.v:186583$12789 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374584,10 +389629,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:177857$12718_Y + connect \Y $and$libresoc.v:186583$12789_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:177859$12720 + cell $and $and$libresoc.v:186585$12791 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374595,10 +389640,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:177859$12720_Y + connect \Y $and$libresoc.v:186585$12791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:177860$12721 + cell $and $and$libresoc.v:186586$12792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374606,10 +389651,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:177860$12721_Y + connect \Y $and$libresoc.v:186586$12792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:177861$12722 + cell $and $and$libresoc.v:186587$12793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374617,10 +389662,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:177861$12722_Y + connect \Y $and$libresoc.v:186587$12793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:177862$12723 + cell $and $and$libresoc.v:186588$12794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374628,10 +389673,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:177862$12723_Y + connect \Y $and$libresoc.v:186588$12794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:177863$12724 + cell $and $and$libresoc.v:186589$12795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374639,10 +389684,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:177863$12724_Y + connect \Y $and$libresoc.v:186589$12795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:177864$12725 + cell $and $and$libresoc.v:186590$12796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374650,10 +389695,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:177864$12725_Y + connect \Y $and$libresoc.v:186590$12796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:177866$12727 + cell $and $and$libresoc.v:186592$12798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374661,10 +389706,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:177866$12727_Y + connect \Y $and$libresoc.v:186592$12798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:177867$12728 + cell $and $and$libresoc.v:186593$12799 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374672,10 +389717,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:177867$12728_Y + connect \Y $and$libresoc.v:186593$12799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:177868$12729 + cell $and $and$libresoc.v:186594$12800 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374683,10 +389728,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:177868$12729_Y + connect \Y $and$libresoc.v:186594$12800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:177869$12730 + cell $and $and$libresoc.v:186595$12801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374694,10 +389739,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:177869$12730_Y + connect \Y $and$libresoc.v:186595$12801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:177870$12731 + cell $and $and$libresoc.v:186596$12802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374705,10 +389750,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:177870$12731_Y + connect \Y $and$libresoc.v:186596$12802_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:177872$12733 + cell $and $and$libresoc.v:186598$12804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374716,10 +389761,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:177872$12733_Y + connect \Y $and$libresoc.v:186598$12804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:177873$12734 + cell $and $and$libresoc.v:186599$12805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374727,10 +389772,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:177873$12734_Y + connect \Y $and$libresoc.v:186599$12805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:177874$12735 + cell $and $and$libresoc.v:186600$12806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374738,10 +389783,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:177874$12735_Y + connect \Y $and$libresoc.v:186600$12806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:177875$12736 + cell $and $and$libresoc.v:186601$12807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374749,10 +389794,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:177875$12736_Y + connect \Y $and$libresoc.v:186601$12807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:177876$12737 + cell $and $and$libresoc.v:186602$12808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374760,10 +389805,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:177876$12737_Y + connect \Y $and$libresoc.v:186602$12808_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:177878$12739 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:186604$12810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374771,10 +389816,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:177878$12739_Y + connect \Y $and$libresoc.v:186604$12810_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:177880$12741 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:186606$12812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374782,10 +389827,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:177880$12741_Y + connect \Y $and$libresoc.v:186606$12812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:177881$12742 + cell $and $and$libresoc.v:186607$12813 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374793,10 +389838,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:177881$12742_Y + connect \Y $and$libresoc.v:186607$12813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:177883$12744 + cell $and $and$libresoc.v:186609$12815 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374804,10 +389849,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:177883$12744_Y + connect \Y $and$libresoc.v:186609$12815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:177886$12747 + cell $and $and$libresoc.v:186612$12818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374815,10 +389860,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:177886$12747_Y + connect \Y $and$libresoc.v:186612$12818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:177891$12752 + cell $and $and$libresoc.v:186617$12823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374826,10 +389871,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:177891$12752_Y + connect \Y $and$libresoc.v:186617$12823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:177892$12753 + cell $and $and$libresoc.v:186618$12824 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374837,10 +389882,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:177892$12753_Y + connect \Y $and$libresoc.v:186618$12824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:177894$12755 + cell $and $and$libresoc.v:186620$12826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374848,10 +389893,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:177894$12755_Y + connect \Y $and$libresoc.v:186620$12826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:177896$12757 + cell $and $and$libresoc.v:186622$12828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374859,10 +389904,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:177896$12757_Y + connect \Y $and$libresoc.v:186622$12828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:177897$12758 + cell $and $and$libresoc.v:186623$12829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374870,10 +389915,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:177897$12758_Y + connect \Y $and$libresoc.v:186623$12829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:177898$12759 + cell $and $and$libresoc.v:186624$12830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374881,10 +389926,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:177898$12759_Y + connect \Y $and$libresoc.v:186624$12830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:177903$12764 + cell $and $and$libresoc.v:186629$12835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374892,10 +389937,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:177903$12764_Y + connect \Y $and$libresoc.v:186629$12835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:177904$12765 + cell $and $and$libresoc.v:186630$12836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374903,10 +389948,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:177904$12765_Y + connect \Y $and$libresoc.v:186630$12836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:177905$12766 + cell $and $and$libresoc.v:186631$12837 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -374914,10 +389959,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:177905$12766_Y + connect \Y $and$libresoc.v:186631$12837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:177907$12768 + cell $and $and$libresoc.v:186633$12839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374925,10 +389970,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:177907$12768_Y + connect \Y $and$libresoc.v:186633$12839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:177908$12769 + cell $and $and$libresoc.v:186634$12840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374936,10 +389981,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:177908$12769_Y + connect \Y $and$libresoc.v:186634$12840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:177909$12770 + cell $and $and$libresoc.v:186635$12841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374947,10 +389992,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:177909$12770_Y + connect \Y $and$libresoc.v:186635$12841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:177910$12771 + cell $and $and$libresoc.v:186636$12842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374958,10 +390003,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:177910$12771_Y + connect \Y $and$libresoc.v:186636$12842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:177911$12772 + cell $and $and$libresoc.v:186637$12843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374969,10 +390014,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:177911$12772_Y + connect \Y $and$libresoc.v:186637$12843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:177912$12773 + cell $and $and$libresoc.v:186638$12844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374980,10 +390025,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:177912$12773_Y + connect \Y $and$libresoc.v:186638$12844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:177919$12780 + cell $and $and$libresoc.v:186645$12851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374991,10 +390036,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:177919$12780_Y + connect \Y $and$libresoc.v:186645$12851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:177893$12754 + cell $eq $eq$libresoc.v:186619$12825 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375002,10 +390047,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:177893$12754_Y + connect \Y $eq$libresoc.v:186619$12825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:177895$12756 + cell $eq $eq$libresoc.v:186621$12827 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375013,66 +390058,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:177895$12756_Y + connect \Y $eq$libresoc.v:186621$12827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:177854$12715 + cell $not $not$libresoc.v:186580$12786 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:177854$12715_Y + connect \Y $not$libresoc.v:186580$12786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:177858$12719 + cell $not $not$libresoc.v:186584$12790 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:177858$12719_Y + connect \Y $not$libresoc.v:186584$12790_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:177877$12738 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:186603$12809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:177877$12738_Y + connect \Y $not$libresoc.v:186603$12809_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:177879$12740 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:186605$12811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:177879$12740_Y + connect \Y $not$libresoc.v:186605$12811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:177882$12743 + cell $not $not$libresoc.v:186608$12814 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:177882$12743_Y + connect \Y $not$libresoc.v:186608$12814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:177885$12746 + cell $not $not$libresoc.v:186611$12817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:177885$12746_Y + connect \Y $not$libresoc.v:186611$12817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:177890$12751 + cell $not $not$libresoc.v:186616$12822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:177890$12751_Y + connect \Y $not$libresoc.v:186616$12822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:177865$12726 + cell $or $or$libresoc.v:186591$12797 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375080,10 +390125,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:177865$12726_Y + connect \Y $or$libresoc.v:186591$12797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:177889$12750 + cell $or $or$libresoc.v:186615$12821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375091,10 +390136,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:177889$12750_Y + connect \Y $or$libresoc.v:186615$12821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:177899$12760 + cell $or $or$libresoc.v:186625$12831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375102,10 +390147,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:177899$12760_Y + connect \Y $or$libresoc.v:186625$12831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:177900$12761 + cell $or $or$libresoc.v:186626$12832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375113,10 +390158,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:177900$12761_Y + connect \Y $or$libresoc.v:186626$12832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:177901$12762 + cell $or $or$libresoc.v:186627$12833 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375124,10 +390169,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:177901$12762_Y + connect \Y $or$libresoc.v:186627$12833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:177902$12763 + cell $or $or$libresoc.v:186628$12834 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375135,10 +390180,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:177902$12763_Y + connect \Y $or$libresoc.v:186628$12834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:177906$12767 + cell $or $or$libresoc.v:186632$12838 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375146,90 +390191,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:177906$12767_Y + connect \Y $or$libresoc.v:186632$12838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:177871$12732 + cell $reduce_and $reduce_and$libresoc.v:186597$12803 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:177871$12732_Y + connect \Y $reduce_and$libresoc.v:186597$12803_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:177884$12745 + cell $reduce_or $reduce_or$libresoc.v:186610$12816 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:177884$12745_Y + connect \Y $reduce_or$libresoc.v:186610$12816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:177887$12748 + cell $reduce_or $reduce_or$libresoc.v:186613$12819 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:177887$12748_Y + connect \Y $reduce_or$libresoc.v:186613$12819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:177888$12749 + cell $reduce_or $reduce_or$libresoc.v:186614$12820 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:177888$12749_Y + connect \Y $reduce_or$libresoc.v:186614$12820_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:177913$12774 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:186639$12845 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:177913$12774_Y + connect \Y $ternary$libresoc.v:186639$12845_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:177914$12775 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:186640$12846 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:177914$12775_Y + connect \Y $ternary$libresoc.v:186640$12846_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:177915$12776 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:186641$12847 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:177915$12776_Y + connect \Y $ternary$libresoc.v:186641$12847_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:177916$12777 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:186642$12848 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:177916$12777_Y + connect \Y $ternary$libresoc.v:186642$12848_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:177917$12778 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:186643$12849 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:177917$12778_Y + connect \Y $ternary$libresoc.v:186643$12849_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:177918$12779 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:186644$12850 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:177918$12779_Y + connect \Y $ternary$libresoc.v:186644$12850_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:177994.14-178000.4" + attribute \src "libresoc.v:186720.14-186726.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -375238,7 +390283,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:178001.12-178030.4" + attribute \src "libresoc.v:186727.12-186756.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -375270,7 +390315,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:178031.15-178037.4" + attribute \src "libresoc.v:186757.15-186763.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -375279,7 +390324,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:178038.14-178044.4" + attribute \src "libresoc.v:186764.14-186770.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -375288,7 +390333,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:178045.14-178051.4" + attribute \src "libresoc.v:186771.14-186777.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -375297,7 +390342,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:178052.14-178058.4" + attribute \src "libresoc.v:186778.14-186784.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -375306,7 +390351,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:178059.14-178064.4" + attribute \src "libresoc.v:186785.14-186790.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -375314,7 +390359,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:178065.14-178071.4" + attribute \src "libresoc.v:186791.14-186797.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -375322,577 +390367,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:177249.7-177249.20" - process $proc$libresoc.v:177249$12939 + attribute \src "libresoc.v:185969.7-185969.20" + process $proc$libresoc.v:185969$13010 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177385.7-177385.24" - process $proc$libresoc.v:177385$12940 + attribute \src "libresoc.v:186105.7-186105.24" + process $proc$libresoc.v:186105$13011 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:177395.7-177395.26" - process $proc$libresoc.v:177395$12941 + attribute \src "libresoc.v:186115.7-186115.26" + process $proc$libresoc.v:186115$13012 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:177403.7-177403.25" - process $proc$libresoc.v:177403$12942 + attribute \src "libresoc.v:186123.7-186123.25" + process $proc$libresoc.v:186123$13013 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:177446.14-177446.48" - process $proc$libresoc.v:177446$12943 + attribute \src "libresoc.v:186168.14-186168.49" + process $proc$libresoc.v:186168$13014 assign { } { } - assign $1\alu_spr0_spr_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[11:0] + update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:177450.14-177450.43" - process $proc$libresoc.v:177450$12944 + attribute \src "libresoc.v:186172.14-186172.43" + process $proc$libresoc.v:186172$13015 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:177528.13-177528.47" - process $proc$libresoc.v:177528$12945 + attribute \src "libresoc.v:186251.13-186251.47" + process $proc$libresoc.v:186251$13016 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:177532.7-177532.39" - process $proc$libresoc.v:177532$12946 + attribute \src "libresoc.v:186255.7-186255.39" + process $proc$libresoc.v:186255$13017 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:177550.7-177550.27" - process $proc$libresoc.v:177550$12947 + attribute \src "libresoc.v:186273.7-186273.27" + process $proc$libresoc.v:186273$13018 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:177582.14-177582.47" - process $proc$libresoc.v:177582$12948 + attribute \src "libresoc.v:186305.14-186305.47" + process $proc$libresoc.v:186305$13019 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:177586.7-177586.27" - process $proc$libresoc.v:177586$12949 + attribute \src "libresoc.v:186309.7-186309.27" + process $proc$libresoc.v:186309$13020 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:177590.14-177590.50" - process $proc$libresoc.v:177590$12950 + attribute \src "libresoc.v:186313.14-186313.50" + process $proc$libresoc.v:186313$13021 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:177594.7-177594.30" - process $proc$libresoc.v:177594$12951 + attribute \src "libresoc.v:186317.7-186317.30" + process $proc$libresoc.v:186317$13022 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:177598.14-177598.51" - process $proc$libresoc.v:177598$12952 + attribute \src "libresoc.v:186321.14-186321.51" + process $proc$libresoc.v:186321$13023 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:177602.7-177602.31" - process $proc$libresoc.v:177602$12953 + attribute \src "libresoc.v:186325.7-186325.31" + process $proc$libresoc.v:186325$13024 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:177606.7-177606.29" - process $proc$libresoc.v:177606$12954 + attribute \src "libresoc.v:186329.7-186329.29" + process $proc$libresoc.v:186329$13025 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:177610.7-177610.32" - process $proc$libresoc.v:177610$12955 + attribute \src "libresoc.v:186333.7-186333.32" + process $proc$libresoc.v:186333$13026 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:177614.13-177614.35" - process $proc$libresoc.v:177614$12956 + attribute \src "libresoc.v:186337.13-186337.35" + process $proc$libresoc.v:186337$13027 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:177618.7-177618.32" - process $proc$libresoc.v:177618$12957 + attribute \src "libresoc.v:186341.7-186341.32" + process $proc$libresoc.v:186341$13028 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:177622.13-177622.35" - process $proc$libresoc.v:177622$12958 + attribute \src "libresoc.v:186345.13-186345.35" + process $proc$libresoc.v:186345$13029 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:177626.7-177626.32" - process $proc$libresoc.v:177626$12959 + attribute \src "libresoc.v:186349.7-186349.32" + process $proc$libresoc.v:186349$13030 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:177654.7-177654.25" - process $proc$libresoc.v:177654$12960 + attribute \src "libresoc.v:186377.7-186377.25" + process $proc$libresoc.v:186377$13031 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:177658.7-177658.25" - process $proc$libresoc.v:177658$12961 + attribute \src "libresoc.v:186381.7-186381.25" + process $proc$libresoc.v:186381$13032 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:177757.13-177757.31" - process $proc$libresoc.v:177757$12962 + attribute \src "libresoc.v:186483.13-186483.31" + process $proc$libresoc.v:186483$13033 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:177765.13-177765.32" - process $proc$libresoc.v:177765$12963 + attribute \src "libresoc.v:186491.13-186491.32" + process $proc$libresoc.v:186491$13034 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:177769.13-177769.32" - process $proc$libresoc.v:177769$12964 + attribute \src "libresoc.v:186495.13-186495.32" + process $proc$libresoc.v:186495$13035 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:177781.7-177781.26" - process $proc$libresoc.v:177781$12965 + attribute \src "libresoc.v:186507.7-186507.26" + process $proc$libresoc.v:186507$13036 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:177785.7-177785.26" - process $proc$libresoc.v:177785$12966 + attribute \src "libresoc.v:186511.7-186511.26" + process $proc$libresoc.v:186511$13037 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:177789.7-177789.25" - process $proc$libresoc.v:177789$12967 + attribute \src "libresoc.v:186515.7-186515.25" + process $proc$libresoc.v:186515$13038 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:177793.7-177793.25" - process $proc$libresoc.v:177793$12968 + attribute \src "libresoc.v:186519.7-186519.25" + process $proc$libresoc.v:186519$13039 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:177815.13-177815.32" - process $proc$libresoc.v:177815$12969 + attribute \src "libresoc.v:186541.13-186541.32" + process $proc$libresoc.v:186541$13040 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:177819.13-177819.32" - process $proc$libresoc.v:177819$12970 + attribute \src "libresoc.v:186545.13-186545.32" + process $proc$libresoc.v:186545$13041 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:177823.14-177823.43" - process $proc$libresoc.v:177823$12971 + attribute \src "libresoc.v:186549.14-186549.43" + process $proc$libresoc.v:186549$13042 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:177827.14-177827.43" - process $proc$libresoc.v:177827$12972 + attribute \src "libresoc.v:186553.14-186553.43" + process $proc$libresoc.v:186553$13043 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:177831.14-177831.43" - process $proc$libresoc.v:177831$12973 + attribute \src "libresoc.v:186557.14-186557.43" + process $proc$libresoc.v:186557$13044 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:177835.7-177835.20" - process $proc$libresoc.v:177835$12974 + attribute \src "libresoc.v:186561.7-186561.20" + process $proc$libresoc.v:186561$13045 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:177839.13-177839.26" - process $proc$libresoc.v:177839$12975 + attribute \src "libresoc.v:186565.13-186565.26" + process $proc$libresoc.v:186565$13046 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:177843.13-177843.26" - process $proc$libresoc.v:177843$12976 + attribute \src "libresoc.v:186569.13-186569.26" + process $proc$libresoc.v:186569$13047 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:177920.3-177921.39" - process $proc$libresoc.v:177920$12781 + attribute \src "libresoc.v:186646.3-186647.39" + process $proc$libresoc.v:186646$12852 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:177922.3-177923.43" - process $proc$libresoc.v:177922$12782 + attribute \src "libresoc.v:186648.3-186649.43" + process $proc$libresoc.v:186648$12853 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:177924.3-177925.29" - process $proc$libresoc.v:177924$12783 + attribute \src "libresoc.v:186650.3-186651.29" + process $proc$libresoc.v:186650$12854 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:177926.3-177927.29" - process $proc$libresoc.v:177926$12784 + attribute \src "libresoc.v:186652.3-186653.29" + process $proc$libresoc.v:186652$12855 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:177928.3-177929.29" - process $proc$libresoc.v:177928$12785 + attribute \src "libresoc.v:186654.3-186655.29" + process $proc$libresoc.v:186654$12856 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:177930.3-177931.29" - process $proc$libresoc.v:177930$12786 + attribute \src "libresoc.v:186656.3-186657.29" + process $proc$libresoc.v:186656$12857 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:177932.3-177933.29" - process $proc$libresoc.v:177932$12787 + attribute \src "libresoc.v:186658.3-186659.29" + process $proc$libresoc.v:186658$12858 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:177934.3-177935.29" - process $proc$libresoc.v:177934$12788 + attribute \src "libresoc.v:186660.3-186661.29" + process $proc$libresoc.v:186660$12859 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:177936.3-177937.47" - process $proc$libresoc.v:177936$12789 + attribute \src "libresoc.v:186662.3-186663.47" + process $proc$libresoc.v:186662$12860 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:177938.3-177939.53" - process $proc$libresoc.v:177938$12790 + attribute \src "libresoc.v:186664.3-186665.53" + process $proc$libresoc.v:186664$12861 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:177940.3-177941.47" - process $proc$libresoc.v:177940$12791 + attribute \src "libresoc.v:186666.3-186667.47" + process $proc$libresoc.v:186666$12862 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:177942.3-177943.53" - process $proc$libresoc.v:177942$12792 + attribute \src "libresoc.v:186668.3-186669.53" + process $proc$libresoc.v:186668$12863 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:177944.3-177945.47" - process $proc$libresoc.v:177944$12793 + attribute \src "libresoc.v:186670.3-186671.47" + process $proc$libresoc.v:186670$12864 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:177946.3-177947.53" - process $proc$libresoc.v:177946$12794 + attribute \src "libresoc.v:186672.3-186673.53" + process $proc$libresoc.v:186672$12865 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:177948.3-177949.45" - process $proc$libresoc.v:177948$12795 + attribute \src "libresoc.v:186674.3-186675.45" + process $proc$libresoc.v:186674$12866 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:177950.3-177951.51" - process $proc$libresoc.v:177950$12796 + attribute \src "libresoc.v:186676.3-186677.51" + process $proc$libresoc.v:186676$12867 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:177952.3-177953.43" - process $proc$libresoc.v:177952$12797 + attribute \src "libresoc.v:186678.3-186679.43" + process $proc$libresoc.v:186678$12868 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:177954.3-177955.49" - process $proc$libresoc.v:177954$12798 + attribute \src "libresoc.v:186680.3-186681.49" + process $proc$libresoc.v:186680$12869 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:177956.3-177957.37" - process $proc$libresoc.v:177956$12799 + attribute \src "libresoc.v:186682.3-186683.37" + process $proc$libresoc.v:186682$12870 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:177958.3-177959.43" - process $proc$libresoc.v:177958$12800 + attribute \src "libresoc.v:186684.3-186685.43" + process $proc$libresoc.v:186684$12871 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:177960.3-177961.69" - process $proc$libresoc.v:177960$12801 + attribute \src "libresoc.v:186686.3-186687.69" + process $proc$libresoc.v:186686$12872 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:177962.3-177963.65" - process $proc$libresoc.v:177962$12802 + attribute \src "libresoc.v:186688.3-186689.65" + process $proc$libresoc.v:186688$12873 assign { } { } - assign $0\alu_spr0_spr_op__fn_unit[11:0] \alu_spr0_spr_op__fn_unit$next + assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk - update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[11:0] + update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:177964.3-177965.59" - process $proc$libresoc.v:177964$12803 + attribute \src "libresoc.v:186690.3-186691.59" + process $proc$libresoc.v:186690$12874 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:177966.3-177967.67" - process $proc$libresoc.v:177966$12804 + attribute \src "libresoc.v:186692.3-186693.67" + process $proc$libresoc.v:186692$12875 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:177968.3-177969.39" - process $proc$libresoc.v:177968$12805 + attribute \src "libresoc.v:186694.3-186695.39" + process $proc$libresoc.v:186694$12876 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:177970.3-177971.39" - process $proc$libresoc.v:177970$12806 + attribute \src "libresoc.v:186696.3-186697.39" + process $proc$libresoc.v:186696$12877 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:177972.3-177973.39" - process $proc$libresoc.v:177972$12807 + attribute \src "libresoc.v:186698.3-186699.39" + process $proc$libresoc.v:186698$12878 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:177974.3-177975.39" - process $proc$libresoc.v:177974$12808 + attribute \src "libresoc.v:186700.3-186701.39" + process $proc$libresoc.v:186700$12879 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:177976.3-177977.39" - process $proc$libresoc.v:177976$12809 + attribute \src "libresoc.v:186702.3-186703.39" + process $proc$libresoc.v:186702$12880 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:177978.3-177979.39" - process $proc$libresoc.v:177978$12810 + attribute \src "libresoc.v:186704.3-186705.39" + process $proc$libresoc.v:186704$12881 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:177980.3-177981.39" - process $proc$libresoc.v:177980$12811 + attribute \src "libresoc.v:186706.3-186707.39" + process $proc$libresoc.v:186706$12882 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:177982.3-177983.39" - process $proc$libresoc.v:177982$12812 + attribute \src "libresoc.v:186708.3-186709.39" + process $proc$libresoc.v:186708$12883 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:177984.3-177985.41" - process $proc$libresoc.v:177984$12813 + attribute \src "libresoc.v:186710.3-186711.41" + process $proc$libresoc.v:186710$12884 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:177986.3-177987.41" - process $proc$libresoc.v:177986$12814 + attribute \src "libresoc.v:186712.3-186713.41" + process $proc$libresoc.v:186712$12885 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:177988.3-177989.37" - process $proc$libresoc.v:177988$12815 + attribute \src "libresoc.v:186714.3-186715.37" + process $proc$libresoc.v:186714$12886 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:177990.3-177991.40" - process $proc$libresoc.v:177990$12816 + attribute \src "libresoc.v:186716.3-186717.40" + process $proc$libresoc.v:186716$12887 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:177992.3-177993.25" - process $proc$libresoc.v:177992$12817 + attribute \src "libresoc.v:186718.3-186719.25" + process $proc$libresoc.v:186718$12888 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:178072.3-178081.6" - process $proc$libresoc.v:178072$12818 + attribute \src "libresoc.v:186798.3-186807.6" + process $proc$libresoc.v:186798$12889 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:178073.5-178073.29" + attribute \src "libresoc.v:186799.5-186799.29" switch \initial - attribute \src "libresoc.v:178073.9-178073.17" + attribute \src "libresoc.v:186799.9-186799.17" case 1'1 case end @@ -375908,14 +390953,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:178082.3-178090.6" - process $proc$libresoc.v:178082$12819 + attribute \src "libresoc.v:186808.3-186816.6" + process $proc$libresoc.v:186808$12890 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12820 $1\rok_l_s_rdok$next[0:0]$12821 - attribute \src "libresoc.v:178083.5-178083.29" + assign $0\rok_l_s_rdok$next[0:0]$12891 $1\rok_l_s_rdok$next[0:0]$12892 + attribute \src "libresoc.v:186809.5-186809.29" switch \initial - attribute \src "libresoc.v:178083.9-178083.17" + attribute \src "libresoc.v:186809.9-186809.17" case 1'1 case end @@ -375924,21 +390969,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12821 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12892 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12821 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12892 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12820 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12891 end - attribute \src "libresoc.v:178091.3-178099.6" - process $proc$libresoc.v:178091$12822 + attribute \src "libresoc.v:186817.3-186825.6" + process $proc$libresoc.v:186817$12893 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12823 $1\rok_l_r_rdok$next[0:0]$12824 - attribute \src "libresoc.v:178092.5-178092.29" + assign $0\rok_l_r_rdok$next[0:0]$12894 $1\rok_l_r_rdok$next[0:0]$12895 + attribute \src "libresoc.v:186818.5-186818.29" switch \initial - attribute \src "libresoc.v:178092.9-178092.17" + attribute \src "libresoc.v:186818.9-186818.17" case 1'1 case end @@ -375947,21 +390992,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12824 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12895 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12824 \$68 + assign $1\rok_l_r_rdok$next[0:0]$12895 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12823 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12894 end - attribute \src "libresoc.v:178100.3-178108.6" - process $proc$libresoc.v:178100$12825 + attribute \src "libresoc.v:186826.3-186834.6" + process $proc$libresoc.v:186826$12896 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12826 $1\rst_l_s_rst$next[0:0]$12827 - attribute \src "libresoc.v:178101.5-178101.29" + assign $0\rst_l_s_rst$next[0:0]$12897 $1\rst_l_s_rst$next[0:0]$12898 + attribute \src "libresoc.v:186827.5-186827.29" switch \initial - attribute \src "libresoc.v:178101.9-178101.17" + attribute \src "libresoc.v:186827.9-186827.17" case 1'1 case end @@ -375970,21 +391015,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12827 1'0 + assign $1\rst_l_s_rst$next[0:0]$12898 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12827 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12898 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12826 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12897 end - attribute \src "libresoc.v:178109.3-178117.6" - process $proc$libresoc.v:178109$12828 + attribute \src "libresoc.v:186835.3-186843.6" + process $proc$libresoc.v:186835$12899 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12829 $1\rst_l_r_rst$next[0:0]$12830 - attribute \src "libresoc.v:178110.5-178110.29" + assign $0\rst_l_r_rst$next[0:0]$12900 $1\rst_l_r_rst$next[0:0]$12901 + attribute \src "libresoc.v:186836.5-186836.29" switch \initial - attribute \src "libresoc.v:178110.9-178110.17" + attribute \src "libresoc.v:186836.9-186836.17" case 1'1 case end @@ -375993,21 +391038,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12830 1'1 + assign $1\rst_l_r_rst$next[0:0]$12901 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12830 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12901 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12829 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12900 end - attribute \src "libresoc.v:178118.3-178126.6" - process $proc$libresoc.v:178118$12831 + attribute \src "libresoc.v:186844.3-186852.6" + process $proc$libresoc.v:186844$12902 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12832 $1\opc_l_s_opc$next[0:0]$12833 - attribute \src "libresoc.v:178119.5-178119.29" + assign $0\opc_l_s_opc$next[0:0]$12903 $1\opc_l_s_opc$next[0:0]$12904 + attribute \src "libresoc.v:186845.5-186845.29" switch \initial - attribute \src "libresoc.v:178119.9-178119.17" + attribute \src "libresoc.v:186845.9-186845.17" case 1'1 case end @@ -376016,21 +391061,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12833 1'0 + assign $1\opc_l_s_opc$next[0:0]$12904 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12833 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12904 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12832 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12903 end - attribute \src "libresoc.v:178127.3-178135.6" - process $proc$libresoc.v:178127$12834 + attribute \src "libresoc.v:186853.3-186861.6" + process $proc$libresoc.v:186853$12905 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12835 $1\opc_l_r_opc$next[0:0]$12836 - attribute \src "libresoc.v:178128.5-178128.29" + assign $0\opc_l_r_opc$next[0:0]$12906 $1\opc_l_r_opc$next[0:0]$12907 + attribute \src "libresoc.v:186854.5-186854.29" switch \initial - attribute \src "libresoc.v:178128.9-178128.17" + attribute \src "libresoc.v:186854.9-186854.17" case 1'1 case end @@ -376039,21 +391084,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12836 1'1 + assign $1\opc_l_r_opc$next[0:0]$12907 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12836 \req_done + assign $1\opc_l_r_opc$next[0:0]$12907 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12835 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12906 end - attribute \src "libresoc.v:178136.3-178144.6" - process $proc$libresoc.v:178136$12837 + attribute \src "libresoc.v:186862.3-186870.6" + process $proc$libresoc.v:186862$12908 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$12838 $1\src_l_s_src$next[5:0]$12839 - attribute \src "libresoc.v:178137.5-178137.29" + assign $0\src_l_s_src$next[5:0]$12909 $1\src_l_s_src$next[5:0]$12910 + attribute \src "libresoc.v:186863.5-186863.29" switch \initial - attribute \src "libresoc.v:178137.9-178137.17" + attribute \src "libresoc.v:186863.9-186863.17" case 1'1 case end @@ -376062,21 +391107,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$12839 6'000000 + assign $1\src_l_s_src$next[5:0]$12910 6'000000 case - assign $1\src_l_s_src$next[5:0]$12839 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$12910 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12838 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12909 end - attribute \src "libresoc.v:178145.3-178153.6" - process $proc$libresoc.v:178145$12840 + attribute \src "libresoc.v:186871.3-186879.6" + process $proc$libresoc.v:186871$12911 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$12841 $1\src_l_r_src$next[5:0]$12842 - attribute \src "libresoc.v:178146.5-178146.29" + assign $0\src_l_r_src$next[5:0]$12912 $1\src_l_r_src$next[5:0]$12913 + attribute \src "libresoc.v:186872.5-186872.29" switch \initial - attribute \src "libresoc.v:178146.9-178146.17" + attribute \src "libresoc.v:186872.9-186872.17" case 1'1 case end @@ -376085,21 +391130,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$12842 6'111111 + assign $1\src_l_r_src$next[5:0]$12913 6'111111 case - assign $1\src_l_r_src$next[5:0]$12842 \reset_r + assign $1\src_l_r_src$next[5:0]$12913 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12841 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12912 end - attribute \src "libresoc.v:178154.3-178162.6" - process $proc$libresoc.v:178154$12843 + attribute \src "libresoc.v:186880.3-186888.6" + process $proc$libresoc.v:186880$12914 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$12844 $1\req_l_s_req$next[5:0]$12845 - attribute \src "libresoc.v:178155.5-178155.29" + assign $0\req_l_s_req$next[5:0]$12915 $1\req_l_s_req$next[5:0]$12916 + attribute \src "libresoc.v:186881.5-186881.29" switch \initial - attribute \src "libresoc.v:178155.9-178155.17" + attribute \src "libresoc.v:186881.9-186881.17" case 1'1 case end @@ -376108,21 +391153,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$12845 6'000000 + assign $1\req_l_s_req$next[5:0]$12916 6'000000 case - assign $1\req_l_s_req$next[5:0]$12845 \$70 + assign $1\req_l_s_req$next[5:0]$12916 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12844 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12915 end - attribute \src "libresoc.v:178163.3-178171.6" - process $proc$libresoc.v:178163$12846 + attribute \src "libresoc.v:186889.3-186897.6" + process $proc$libresoc.v:186889$12917 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$12847 $1\req_l_r_req$next[5:0]$12848 - attribute \src "libresoc.v:178164.5-178164.29" + assign $0\req_l_r_req$next[5:0]$12918 $1\req_l_r_req$next[5:0]$12919 + attribute \src "libresoc.v:186890.5-186890.29" switch \initial - attribute \src "libresoc.v:178164.9-178164.17" + attribute \src "libresoc.v:186890.9-186890.17" case 1'1 case end @@ -376131,15 +391176,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$12848 6'111111 + assign $1\req_l_r_req$next[5:0]$12919 6'111111 case - assign $1\req_l_r_req$next[5:0]$12848 \$72 + assign $1\req_l_r_req$next[5:0]$12919 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12847 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12918 end - attribute \src "libresoc.v:178172.3-178184.6" - process $proc$libresoc.v:178172$12849 + attribute \src "libresoc.v:186898.3-186910.6" + process $proc$libresoc.v:186898$12920 assign { } { } assign { } { } assign { } { } @@ -376148,13 +391193,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[11:0]$12850 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12854 - assign $0\alu_spr0_spr_op__insn$next[31:0]$12851 $1\alu_spr0_spr_op__insn$next[31:0]$12855 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12852 $1\alu_spr0_spr_op__insn_type$next[6:0]$12856 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12853 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12857 - attribute \src "libresoc.v:178173.5-178173.29" + assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12922 $1\alu_spr0_spr_op__insn$next[31:0]$12926 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 + attribute \src "libresoc.v:186899.5-186899.29" switch \initial - attribute \src "libresoc.v:178173.9-178173.17" + attribute \src "libresoc.v:186899.9-186899.17" case 1'1 case end @@ -376166,33 +391211,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12857 $1\alu_spr0_spr_op__insn$next[31:0]$12855 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12854 $1\alu_spr0_spr_op__insn_type$next[6:0]$12856 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 $1\alu_spr0_spr_op__insn$next[31:0]$12926 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[11:0]$12854 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$12855 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12856 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12857 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12926 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[11:0]$12850 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12851 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12852 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12853 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12922 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 end - attribute \src "libresoc.v:178185.3-178206.6" - process $proc$libresoc.v:178185$12858 + attribute \src "libresoc.v:186911.3-186932.6" + process $proc$libresoc.v:186911$12929 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12859 $2\data_r0__o$next[63:0]$12863 + assign $0\data_r0__o$next[63:0]$12930 $2\data_r0__o$next[63:0]$12934 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12860 $3\data_r0__o_ok$next[0:0]$12865 - attribute \src "libresoc.v:178186.5-178186.29" + assign $0\data_r0__o_ok$next[0:0]$12931 $3\data_r0__o_ok$next[0:0]$12936 + attribute \src "libresoc.v:186912.5-186912.29" switch \initial - attribute \src "libresoc.v:178186.9-178186.17" + attribute \src "libresoc.v:186912.9-186912.17" case 1'1 case end @@ -376202,10 +391247,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12862 $1\data_r0__o$next[63:0]$12861 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$12933 $1\data_r0__o$next[63:0]$12932 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$12861 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12862 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12932 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12933 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -376213,38 +391258,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12864 $2\data_r0__o$next[63:0]$12863 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12935 $2\data_r0__o$next[63:0]$12934 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12863 $1\data_r0__o$next[63:0]$12861 - assign $2\data_r0__o_ok$next[0:0]$12864 $1\data_r0__o_ok$next[0:0]$12862 + assign $2\data_r0__o$next[63:0]$12934 $1\data_r0__o$next[63:0]$12932 + assign $2\data_r0__o_ok$next[0:0]$12935 $1\data_r0__o_ok$next[0:0]$12933 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12865 1'0 + assign $3\data_r0__o_ok$next[0:0]$12936 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12865 $2\data_r0__o_ok$next[0:0]$12864 + assign $3\data_r0__o_ok$next[0:0]$12936 $2\data_r0__o_ok$next[0:0]$12935 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12859 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12860 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12930 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12931 end - attribute \src "libresoc.v:178207.3-178228.6" - process $proc$libresoc.v:178207$12866 + attribute \src "libresoc.v:186933.3-186954.6" + process $proc$libresoc.v:186933$12937 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$12867 $2\data_r1__spr1$next[63:0]$12871 + assign $0\data_r1__spr1$next[63:0]$12938 $2\data_r1__spr1$next[63:0]$12942 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$12868 $3\data_r1__spr1_ok$next[0:0]$12873 - attribute \src "libresoc.v:178208.5-178208.29" + assign $0\data_r1__spr1_ok$next[0:0]$12939 $3\data_r1__spr1_ok$next[0:0]$12944 + attribute \src "libresoc.v:186934.5-186934.29" switch \initial - attribute \src "libresoc.v:178208.9-178208.17" + attribute \src "libresoc.v:186934.9-186934.17" case 1'1 case end @@ -376254,10 +391299,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$12870 $1\data_r1__spr1$next[63:0]$12869 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$12941 $1\data_r1__spr1$next[63:0]$12940 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$12869 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$12870 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$12940 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12941 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -376265,38 +391310,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$12872 $2\data_r1__spr1$next[63:0]$12871 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$12943 $2\data_r1__spr1$next[63:0]$12942 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$12871 $1\data_r1__spr1$next[63:0]$12869 - assign $2\data_r1__spr1_ok$next[0:0]$12872 $1\data_r1__spr1_ok$next[0:0]$12870 + assign $2\data_r1__spr1$next[63:0]$12942 $1\data_r1__spr1$next[63:0]$12940 + assign $2\data_r1__spr1_ok$next[0:0]$12943 $1\data_r1__spr1_ok$next[0:0]$12941 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$12873 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$12944 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$12873 $2\data_r1__spr1_ok$next[0:0]$12872 + assign $3\data_r1__spr1_ok$next[0:0]$12944 $2\data_r1__spr1_ok$next[0:0]$12943 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12867 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12868 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12938 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12939 end - attribute \src "libresoc.v:178229.3-178250.6" - process $proc$libresoc.v:178229$12874 + attribute \src "libresoc.v:186955.3-186976.6" + process $proc$libresoc.v:186955$12945 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$12875 $2\data_r2__fast1$next[63:0]$12879 + assign $0\data_r2__fast1$next[63:0]$12946 $2\data_r2__fast1$next[63:0]$12950 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$12876 $3\data_r2__fast1_ok$next[0:0]$12881 - attribute \src "libresoc.v:178230.5-178230.29" + assign $0\data_r2__fast1_ok$next[0:0]$12947 $3\data_r2__fast1_ok$next[0:0]$12952 + attribute \src "libresoc.v:186956.5-186956.29" switch \initial - attribute \src "libresoc.v:178230.9-178230.17" + attribute \src "libresoc.v:186956.9-186956.17" case 1'1 case end @@ -376306,10 +391351,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$12878 $1\data_r2__fast1$next[63:0]$12877 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$12949 $1\data_r2__fast1$next[63:0]$12948 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$12877 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$12878 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$12948 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12949 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -376317,38 +391362,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$12880 $2\data_r2__fast1$next[63:0]$12879 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$12951 $2\data_r2__fast1$next[63:0]$12950 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$12879 $1\data_r2__fast1$next[63:0]$12877 - assign $2\data_r2__fast1_ok$next[0:0]$12880 $1\data_r2__fast1_ok$next[0:0]$12878 + assign $2\data_r2__fast1$next[63:0]$12950 $1\data_r2__fast1$next[63:0]$12948 + assign $2\data_r2__fast1_ok$next[0:0]$12951 $1\data_r2__fast1_ok$next[0:0]$12949 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$12881 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$12952 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$12881 $2\data_r2__fast1_ok$next[0:0]$12880 + assign $3\data_r2__fast1_ok$next[0:0]$12952 $2\data_r2__fast1_ok$next[0:0]$12951 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12875 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12876 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12946 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12947 end - attribute \src "libresoc.v:178251.3-178272.6" - process $proc$libresoc.v:178251$12882 + attribute \src "libresoc.v:186977.3-186998.6" + process $proc$libresoc.v:186977$12953 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$12883 $2\data_r3__xer_so$next[0:0]$12887 + assign $0\data_r3__xer_so$next[0:0]$12954 $2\data_r3__xer_so$next[0:0]$12958 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$12884 $3\data_r3__xer_so_ok$next[0:0]$12889 - attribute \src "libresoc.v:178252.5-178252.29" + assign $0\data_r3__xer_so_ok$next[0:0]$12955 $3\data_r3__xer_so_ok$next[0:0]$12960 + attribute \src "libresoc.v:186978.5-186978.29" switch \initial - attribute \src "libresoc.v:178252.9-178252.17" + attribute \src "libresoc.v:186978.9-186978.17" case 1'1 case end @@ -376358,10 +391403,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$12886 $1\data_r3__xer_so$next[0:0]$12885 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$12957 $1\data_r3__xer_so$next[0:0]$12956 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$12885 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$12886 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$12956 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12957 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -376369,38 +391414,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$12888 $2\data_r3__xer_so$next[0:0]$12887 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$12959 $2\data_r3__xer_so$next[0:0]$12958 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$12887 $1\data_r3__xer_so$next[0:0]$12885 - assign $2\data_r3__xer_so_ok$next[0:0]$12888 $1\data_r3__xer_so_ok$next[0:0]$12886 + assign $2\data_r3__xer_so$next[0:0]$12958 $1\data_r3__xer_so$next[0:0]$12956 + assign $2\data_r3__xer_so_ok$next[0:0]$12959 $1\data_r3__xer_so_ok$next[0:0]$12957 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$12889 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$12960 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$12889 $2\data_r3__xer_so_ok$next[0:0]$12888 + assign $3\data_r3__xer_so_ok$next[0:0]$12960 $2\data_r3__xer_so_ok$next[0:0]$12959 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12883 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12884 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12954 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12955 end - attribute \src "libresoc.v:178273.3-178294.6" - process $proc$libresoc.v:178273$12890 + attribute \src "libresoc.v:186999.3-187020.6" + process $proc$libresoc.v:186999$12961 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$12891 $2\data_r4__xer_ov$next[1:0]$12895 + assign $0\data_r4__xer_ov$next[1:0]$12962 $2\data_r4__xer_ov$next[1:0]$12966 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$12892 $3\data_r4__xer_ov_ok$next[0:0]$12897 - attribute \src "libresoc.v:178274.5-178274.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$12963 $3\data_r4__xer_ov_ok$next[0:0]$12968 + attribute \src "libresoc.v:187000.5-187000.29" switch \initial - attribute \src "libresoc.v:178274.9-178274.17" + attribute \src "libresoc.v:187000.9-187000.17" case 1'1 case end @@ -376410,10 +391455,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$12894 $1\data_r4__xer_ov$next[1:0]$12893 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$12965 $1\data_r4__xer_ov$next[1:0]$12964 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$12893 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$12894 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$12964 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$12965 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -376421,38 +391466,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$12896 $2\data_r4__xer_ov$next[1:0]$12895 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$12967 $2\data_r4__xer_ov$next[1:0]$12966 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$12895 $1\data_r4__xer_ov$next[1:0]$12893 - assign $2\data_r4__xer_ov_ok$next[0:0]$12896 $1\data_r4__xer_ov_ok$next[0:0]$12894 + assign $2\data_r4__xer_ov$next[1:0]$12966 $1\data_r4__xer_ov$next[1:0]$12964 + assign $2\data_r4__xer_ov_ok$next[0:0]$12967 $1\data_r4__xer_ov_ok$next[0:0]$12965 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$12897 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$12968 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$12897 $2\data_r4__xer_ov_ok$next[0:0]$12896 + assign $3\data_r4__xer_ov_ok$next[0:0]$12968 $2\data_r4__xer_ov_ok$next[0:0]$12967 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12891 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12892 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12962 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12963 end - attribute \src "libresoc.v:178295.3-178316.6" - process $proc$libresoc.v:178295$12898 + attribute \src "libresoc.v:187021.3-187042.6" + process $proc$libresoc.v:187021$12969 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$12899 $2\data_r5__xer_ca$next[1:0]$12903 + assign $0\data_r5__xer_ca$next[1:0]$12970 $2\data_r5__xer_ca$next[1:0]$12974 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$12900 $3\data_r5__xer_ca_ok$next[0:0]$12905 - attribute \src "libresoc.v:178296.5-178296.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$12971 $3\data_r5__xer_ca_ok$next[0:0]$12976 + attribute \src "libresoc.v:187022.5-187022.29" switch \initial - attribute \src "libresoc.v:178296.9-178296.17" + attribute \src "libresoc.v:187022.9-187022.17" case 1'1 case end @@ -376462,10 +391507,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$12902 $1\data_r5__xer_ca$next[1:0]$12901 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$12973 $1\data_r5__xer_ca$next[1:0]$12972 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$12901 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$12902 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$12972 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$12973 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -376473,170 +391518,170 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$12904 $2\data_r5__xer_ca$next[1:0]$12903 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$12975 $2\data_r5__xer_ca$next[1:0]$12974 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$12903 $1\data_r5__xer_ca$next[1:0]$12901 - assign $2\data_r5__xer_ca_ok$next[0:0]$12904 $1\data_r5__xer_ca_ok$next[0:0]$12902 + assign $2\data_r5__xer_ca$next[1:0]$12974 $1\data_r5__xer_ca$next[1:0]$12972 + assign $2\data_r5__xer_ca_ok$next[0:0]$12975 $1\data_r5__xer_ca_ok$next[0:0]$12973 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$12905 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$12976 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$12905 $2\data_r5__xer_ca_ok$next[0:0]$12904 + assign $3\data_r5__xer_ca_ok$next[0:0]$12976 $2\data_r5__xer_ca_ok$next[0:0]$12975 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12899 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12900 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12970 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12971 end - attribute \src "libresoc.v:178317.3-178326.6" - process $proc$libresoc.v:178317$12906 + attribute \src "libresoc.v:187043.3-187052.6" + process $proc$libresoc.v:187043$12977 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12907 $1\src_r0$next[63:0]$12908 - attribute \src "libresoc.v:178318.5-178318.29" + assign $0\src_r0$next[63:0]$12978 $1\src_r0$next[63:0]$12979 + attribute \src "libresoc.v:187044.5-187044.29" switch \initial - attribute \src "libresoc.v:178318.9-178318.17" + attribute \src "libresoc.v:187044.9-187044.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12908 \src1_i + assign $1\src_r0$next[63:0]$12979 \src1_i case - assign $1\src_r0$next[63:0]$12908 \src_r0 + assign $1\src_r0$next[63:0]$12979 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12907 + update \src_r0$next $0\src_r0$next[63:0]$12978 end - attribute \src "libresoc.v:178327.3-178336.6" - process $proc$libresoc.v:178327$12909 + attribute \src "libresoc.v:187053.3-187062.6" + process $proc$libresoc.v:187053$12980 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12910 $1\src_r1$next[63:0]$12911 - attribute \src "libresoc.v:178328.5-178328.29" + assign $0\src_r1$next[63:0]$12981 $1\src_r1$next[63:0]$12982 + attribute \src "libresoc.v:187054.5-187054.29" switch \initial - attribute \src "libresoc.v:178328.9-178328.17" + attribute \src "libresoc.v:187054.9-187054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12911 \src2_i + assign $1\src_r1$next[63:0]$12982 \src2_i case - assign $1\src_r1$next[63:0]$12911 \src_r1 + assign $1\src_r1$next[63:0]$12982 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12910 + update \src_r1$next $0\src_r1$next[63:0]$12981 end - attribute \src "libresoc.v:178337.3-178346.6" - process $proc$libresoc.v:178337$12912 + attribute \src "libresoc.v:187063.3-187072.6" + process $proc$libresoc.v:187063$12983 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12913 $1\src_r2$next[63:0]$12914 - attribute \src "libresoc.v:178338.5-178338.29" + assign $0\src_r2$next[63:0]$12984 $1\src_r2$next[63:0]$12985 + attribute \src "libresoc.v:187064.5-187064.29" switch \initial - attribute \src "libresoc.v:178338.9-178338.17" + attribute \src "libresoc.v:187064.9-187064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12914 \src3_i + assign $1\src_r2$next[63:0]$12985 \src3_i case - assign $1\src_r2$next[63:0]$12914 \src_r2 + assign $1\src_r2$next[63:0]$12985 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12913 + update \src_r2$next $0\src_r2$next[63:0]$12984 end - attribute \src "libresoc.v:178347.3-178356.6" - process $proc$libresoc.v:178347$12915 + attribute \src "libresoc.v:187073.3-187082.6" + process $proc$libresoc.v:187073$12986 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12916 $1\src_r3$next[0:0]$12917 - attribute \src "libresoc.v:178348.5-178348.29" + assign $0\src_r3$next[0:0]$12987 $1\src_r3$next[0:0]$12988 + attribute \src "libresoc.v:187074.5-187074.29" switch \initial - attribute \src "libresoc.v:178348.9-178348.17" + attribute \src "libresoc.v:187074.9-187074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12917 \src4_i + assign $1\src_r3$next[0:0]$12988 \src4_i case - assign $1\src_r3$next[0:0]$12917 \src_r3 + assign $1\src_r3$next[0:0]$12988 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12916 + update \src_r3$next $0\src_r3$next[0:0]$12987 end - attribute \src "libresoc.v:178357.3-178366.6" - process $proc$libresoc.v:178357$12918 + attribute \src "libresoc.v:187083.3-187092.6" + process $proc$libresoc.v:187083$12989 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12919 $1\src_r4$next[1:0]$12920 - attribute \src "libresoc.v:178358.5-178358.29" + assign $0\src_r4$next[1:0]$12990 $1\src_r4$next[1:0]$12991 + attribute \src "libresoc.v:187084.5-187084.29" switch \initial - attribute \src "libresoc.v:178358.9-178358.17" + attribute \src "libresoc.v:187084.9-187084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12920 \src5_i + assign $1\src_r4$next[1:0]$12991 \src5_i case - assign $1\src_r4$next[1:0]$12920 \src_r4 + assign $1\src_r4$next[1:0]$12991 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12919 + update \src_r4$next $0\src_r4$next[1:0]$12990 end - attribute \src "libresoc.v:178367.3-178376.6" - process $proc$libresoc.v:178367$12921 + attribute \src "libresoc.v:187093.3-187102.6" + process $proc$libresoc.v:187093$12992 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$12922 $1\src_r5$next[1:0]$12923 - attribute \src "libresoc.v:178368.5-178368.29" + assign $0\src_r5$next[1:0]$12993 $1\src_r5$next[1:0]$12994 + attribute \src "libresoc.v:187094.5-187094.29" switch \initial - attribute \src "libresoc.v:178368.9-178368.17" + attribute \src "libresoc.v:187094.9-187094.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$12923 \src6_i + assign $1\src_r5$next[1:0]$12994 \src6_i case - assign $1\src_r5$next[1:0]$12923 \src_r5 + assign $1\src_r5$next[1:0]$12994 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$12922 + update \src_r5$next $0\src_r5$next[1:0]$12993 end - attribute \src "libresoc.v:178377.3-178385.6" - process $proc$libresoc.v:178377$12924 + attribute \src "libresoc.v:187103.3-187111.6" + process $proc$libresoc.v:187103$12995 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12925 $1\alui_l_r_alui$next[0:0]$12926 - attribute \src "libresoc.v:178378.5-178378.29" + assign $0\alui_l_r_alui$next[0:0]$12996 $1\alui_l_r_alui$next[0:0]$12997 + attribute \src "libresoc.v:187104.5-187104.29" switch \initial - attribute \src "libresoc.v:178378.9-178378.17" + attribute \src "libresoc.v:187104.9-187104.17" case 1'1 case end @@ -376645,21 +391690,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12926 1'1 + assign $1\alui_l_r_alui$next[0:0]$12997 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12926 \$98 + assign $1\alui_l_r_alui$next[0:0]$12997 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12925 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12996 end - attribute \src "libresoc.v:178386.3-178394.6" - process $proc$libresoc.v:178386$12927 + attribute \src "libresoc.v:187112.3-187120.6" + process $proc$libresoc.v:187112$12998 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12928 $1\alu_l_r_alu$next[0:0]$12929 - attribute \src "libresoc.v:178387.5-178387.29" + assign $0\alu_l_r_alu$next[0:0]$12999 $1\alu_l_r_alu$next[0:0]$13000 + attribute \src "libresoc.v:187113.5-187113.29" switch \initial - attribute \src "libresoc.v:178387.9-178387.17" + attribute \src "libresoc.v:187113.9-187113.17" case 1'1 case end @@ -376668,21 +391713,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12929 1'1 + assign $1\alu_l_r_alu$next[0:0]$13000 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12929 \$100 + assign $1\alu_l_r_alu$next[0:0]$13000 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12928 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12999 end - attribute \src "libresoc.v:178395.3-178404.6" - process $proc$libresoc.v:178395$12930 + attribute \src "libresoc.v:187121.3-187130.6" + process $proc$libresoc.v:187121$13001 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:178396.5-178396.29" + attribute \src "libresoc.v:187122.5-187122.29" switch \initial - attribute \src "libresoc.v:178396.9-178396.17" + attribute \src "libresoc.v:187122.9-187122.17" case 1'1 case end @@ -376698,14 +391743,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:178405.3-178414.6" - process $proc$libresoc.v:178405$12931 + attribute \src "libresoc.v:187131.3-187140.6" + process $proc$libresoc.v:187131$13002 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:178406.5-178406.29" + attribute \src "libresoc.v:187132.5-187132.29" switch \initial - attribute \src "libresoc.v:178406.9-178406.17" + attribute \src "libresoc.v:187132.9-187132.17" case 1'1 case end @@ -376721,14 +391766,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:178415.3-178424.6" - process $proc$libresoc.v:178415$12932 + attribute \src "libresoc.v:187141.3-187150.6" + process $proc$libresoc.v:187141$13003 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:178416.5-178416.29" + attribute \src "libresoc.v:187142.5-187142.29" switch \initial - attribute \src "libresoc.v:178416.9-178416.17" + attribute \src "libresoc.v:187142.9-187142.17" case 1'1 case end @@ -376744,14 +391789,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:178425.3-178434.6" - process $proc$libresoc.v:178425$12933 + attribute \src "libresoc.v:187151.3-187160.6" + process $proc$libresoc.v:187151$13004 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:178426.5-178426.29" + attribute \src "libresoc.v:187152.5-187152.29" switch \initial - attribute \src "libresoc.v:178426.9-178426.17" + attribute \src "libresoc.v:187152.9-187152.17" case 1'1 case end @@ -376767,14 +391812,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:178435.3-178444.6" - process $proc$libresoc.v:178435$12934 + attribute \src "libresoc.v:187161.3-187170.6" + process $proc$libresoc.v:187161$13005 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:178436.5-178436.29" + attribute \src "libresoc.v:187162.5-187162.29" switch \initial - attribute \src "libresoc.v:178436.9-178436.17" + attribute \src "libresoc.v:187162.9-187162.17" case 1'1 case end @@ -376790,14 +391835,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:178445.3-178454.6" - process $proc$libresoc.v:178445$12935 + attribute \src "libresoc.v:187171.3-187180.6" + process $proc$libresoc.v:187171$13006 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:178446.5-178446.29" + attribute \src "libresoc.v:187172.5-187172.29" switch \initial - attribute \src "libresoc.v:178446.9-178446.17" + attribute \src "libresoc.v:187172.9-187172.17" case 1'1 case end @@ -376813,14 +391858,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:178455.3-178463.6" - process $proc$libresoc.v:178455$12936 + attribute \src "libresoc.v:187181.3-187189.6" + process $proc$libresoc.v:187181$13007 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$12937 $1\prev_wr_go$next[5:0]$12938 - attribute \src "libresoc.v:178456.5-178456.29" + assign $0\prev_wr_go$next[5:0]$13008 $1\prev_wr_go$next[5:0]$13009 + attribute \src "libresoc.v:187182.5-187182.29" switch \initial - attribute \src "libresoc.v:178456.9-178456.17" + attribute \src "libresoc.v:187182.9-187182.17" case 1'1 case end @@ -376829,79 +391874,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$12938 6'000000 - case - assign $1\prev_wr_go$next[5:0]$12938 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12937 - end - connect \$9 $not$libresoc.v:177854$12715_Y - connect \$100 $and$libresoc.v:177855$12716_Y - connect \$102 $and$libresoc.v:177856$12717_Y - connect \$104 $and$libresoc.v:177857$12718_Y - connect \$106 $not$libresoc.v:177858$12719_Y - connect \$108 $and$libresoc.v:177859$12720_Y - connect \$110 $and$libresoc.v:177860$12721_Y - connect \$112 $and$libresoc.v:177861$12722_Y - connect \$114 $and$libresoc.v:177862$12723_Y - connect \$116 $and$libresoc.v:177863$12724_Y - connect \$118 $and$libresoc.v:177864$12725_Y - connect \$11 $or$libresoc.v:177865$12726_Y - connect \$120 $and$libresoc.v:177866$12727_Y - connect \$122 $and$libresoc.v:177867$12728_Y - connect \$124 $and$libresoc.v:177868$12729_Y - connect \$126 $and$libresoc.v:177869$12730_Y - connect \$128 $and$libresoc.v:177870$12731_Y - connect \$8 $reduce_and$libresoc.v:177871$12732_Y - connect \$130 $and$libresoc.v:177872$12733_Y - connect \$132 $and$libresoc.v:177873$12734_Y - connect \$134 $and$libresoc.v:177874$12735_Y - connect \$136 $and$libresoc.v:177875$12736_Y - connect \$14 $and$libresoc.v:177876$12737_Y - connect \$16 $not$libresoc.v:177877$12738_Y - connect \$18 $and$libresoc.v:177878$12739_Y - connect \$20 $not$libresoc.v:177879$12740_Y - connect \$22 $and$libresoc.v:177880$12741_Y - connect \$24 $and$libresoc.v:177881$12742_Y - connect \$28 $not$libresoc.v:177882$12743_Y - connect \$30 $and$libresoc.v:177883$12744_Y - connect \$27 $reduce_or$libresoc.v:177884$12745_Y - connect \$26 $not$libresoc.v:177885$12746_Y - connect \$34 $and$libresoc.v:177886$12747_Y - connect \$36 $reduce_or$libresoc.v:177887$12748_Y - connect \$38 $reduce_or$libresoc.v:177888$12749_Y - connect \$40 $or$libresoc.v:177889$12750_Y - connect \$42 $not$libresoc.v:177890$12751_Y - connect \$44 $and$libresoc.v:177891$12752_Y - connect \$46 $and$libresoc.v:177892$12753_Y - connect \$48 $eq$libresoc.v:177893$12754_Y - connect \$50 $and$libresoc.v:177894$12755_Y - connect \$52 $eq$libresoc.v:177895$12756_Y - connect \$54 $and$libresoc.v:177896$12757_Y - connect \$56 $and$libresoc.v:177897$12758_Y - connect \$58 $and$libresoc.v:177898$12759_Y - connect \$60 $or$libresoc.v:177899$12760_Y - connect \$62 $or$libresoc.v:177900$12761_Y - connect \$64 $or$libresoc.v:177901$12762_Y - connect \$66 $or$libresoc.v:177902$12763_Y - connect \$68 $and$libresoc.v:177903$12764_Y - connect \$6 $and$libresoc.v:177904$12765_Y - connect \$70 $and$libresoc.v:177905$12766_Y - connect \$72 $or$libresoc.v:177906$12767_Y - connect \$74 $and$libresoc.v:177907$12768_Y - connect \$76 $and$libresoc.v:177908$12769_Y - connect \$78 $and$libresoc.v:177909$12770_Y - connect \$80 $and$libresoc.v:177910$12771_Y - connect \$82 $and$libresoc.v:177911$12772_Y - connect \$84 $and$libresoc.v:177912$12773_Y - connect \$86 $ternary$libresoc.v:177913$12774_Y - connect \$88 $ternary$libresoc.v:177914$12775_Y - connect \$90 $ternary$libresoc.v:177915$12776_Y - connect \$92 $ternary$libresoc.v:177916$12777_Y - connect \$94 $ternary$libresoc.v:177917$12778_Y - connect \$96 $ternary$libresoc.v:177918$12779_Y - connect \$98 $and$libresoc.v:177919$12780_Y + assign $1\prev_wr_go$next[5:0]$13009 6'000000 + case + assign $1\prev_wr_go$next[5:0]$13009 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13008 + end + connect \$9 $not$libresoc.v:186580$12786_Y + connect \$100 $and$libresoc.v:186581$12787_Y + connect \$102 $and$libresoc.v:186582$12788_Y + connect \$104 $and$libresoc.v:186583$12789_Y + connect \$106 $not$libresoc.v:186584$12790_Y + connect \$108 $and$libresoc.v:186585$12791_Y + connect \$110 $and$libresoc.v:186586$12792_Y + connect \$112 $and$libresoc.v:186587$12793_Y + connect \$114 $and$libresoc.v:186588$12794_Y + connect \$116 $and$libresoc.v:186589$12795_Y + connect \$118 $and$libresoc.v:186590$12796_Y + connect \$11 $or$libresoc.v:186591$12797_Y + connect \$120 $and$libresoc.v:186592$12798_Y + connect \$122 $and$libresoc.v:186593$12799_Y + connect \$124 $and$libresoc.v:186594$12800_Y + connect \$126 $and$libresoc.v:186595$12801_Y + connect \$128 $and$libresoc.v:186596$12802_Y + connect \$8 $reduce_and$libresoc.v:186597$12803_Y + connect \$130 $and$libresoc.v:186598$12804_Y + connect \$132 $and$libresoc.v:186599$12805_Y + connect \$134 $and$libresoc.v:186600$12806_Y + connect \$136 $and$libresoc.v:186601$12807_Y + connect \$14 $and$libresoc.v:186602$12808_Y + connect \$16 $not$libresoc.v:186603$12809_Y + connect \$18 $and$libresoc.v:186604$12810_Y + connect \$20 $not$libresoc.v:186605$12811_Y + connect \$22 $and$libresoc.v:186606$12812_Y + connect \$24 $and$libresoc.v:186607$12813_Y + connect \$28 $not$libresoc.v:186608$12814_Y + connect \$30 $and$libresoc.v:186609$12815_Y + connect \$27 $reduce_or$libresoc.v:186610$12816_Y + connect \$26 $not$libresoc.v:186611$12817_Y + connect \$34 $and$libresoc.v:186612$12818_Y + connect \$36 $reduce_or$libresoc.v:186613$12819_Y + connect \$38 $reduce_or$libresoc.v:186614$12820_Y + connect \$40 $or$libresoc.v:186615$12821_Y + connect \$42 $not$libresoc.v:186616$12822_Y + connect \$44 $and$libresoc.v:186617$12823_Y + connect \$46 $and$libresoc.v:186618$12824_Y + connect \$48 $eq$libresoc.v:186619$12825_Y + connect \$50 $and$libresoc.v:186620$12826_Y + connect \$52 $eq$libresoc.v:186621$12827_Y + connect \$54 $and$libresoc.v:186622$12828_Y + connect \$56 $and$libresoc.v:186623$12829_Y + connect \$58 $and$libresoc.v:186624$12830_Y + connect \$60 $or$libresoc.v:186625$12831_Y + connect \$62 $or$libresoc.v:186626$12832_Y + connect \$64 $or$libresoc.v:186627$12833_Y + connect \$66 $or$libresoc.v:186628$12834_Y + connect \$68 $and$libresoc.v:186629$12835_Y + connect \$6 $and$libresoc.v:186630$12836_Y + connect \$70 $and$libresoc.v:186631$12837_Y + connect \$72 $or$libresoc.v:186632$12838_Y + connect \$74 $and$libresoc.v:186633$12839_Y + connect \$76 $and$libresoc.v:186634$12840_Y + connect \$78 $and$libresoc.v:186635$12841_Y + connect \$80 $and$libresoc.v:186636$12842_Y + connect \$82 $and$libresoc.v:186637$12843_Y + connect \$84 $and$libresoc.v:186638$12844_Y + connect \$86 $ternary$libresoc.v:186639$12845_Y + connect \$88 $ternary$libresoc.v:186640$12846_Y + connect \$90 $ternary$libresoc.v:186641$12847_Y + connect \$92 $ternary$libresoc.v:186642$12848_Y + connect \$94 $ternary$libresoc.v:186643$12849_Y + connect \$96 $ternary$libresoc.v:186644$12850_Y + connect \$98 $and$libresoc.v:186645$12851_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -376934,111 +391979,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:178499.1-179013.10" +attribute \src "libresoc.v:187225.1-187745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:178766.3-178781.6" - wire width 64 $0\fast1$7[63:0]$12985 - attribute \src "libresoc.v:178843.3-178858.6" + attribute \src "libresoc.v:187498.3-187513.6" + wire width 64 $0\fast1$7[63:0]$13056 + attribute \src "libresoc.v:187575.3-187590.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:178500.7-178500.20" + attribute \src "libresoc.v:187226.7-187226.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178801.3-178842.6" + attribute \src "libresoc.v:187533.3-187574.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:178801.3-178842.6" + attribute \src "libresoc.v:187533.3-187574.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:178991.3-179009.6" - wire width 64 $0\spr1$6[63:0]$13010 - attribute \src "libresoc.v:178782.3-178800.6" + attribute \src "libresoc.v:187723.3-187741.6" + wire width 64 $0\spr1$6[63:0]$13081 + attribute \src "libresoc.v:187514.3-187532.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:178946.3-178969.6" - wire width 2 $0\xer_ca$10[1:0]$13004 - attribute \src "libresoc.v:178970.3-178990.6" + attribute \src "libresoc.v:187678.3-187701.6" + wire width 2 $0\xer_ca$10[1:0]$13075 + attribute \src "libresoc.v:187702.3-187722.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:178901.3-178924.6" - wire width 2 $0\xer_ov$9[1:0]$12998 - attribute \src "libresoc.v:178925.3-178945.6" + attribute \src "libresoc.v:187633.3-187656.6" + wire width 2 $0\xer_ov$9[1:0]$13069 + attribute \src "libresoc.v:187657.3-187677.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:178859.3-178879.6" - wire $0\xer_so$8[0:0]$12992 - attribute \src "libresoc.v:178880.3-178900.6" + attribute \src "libresoc.v:187591.3-187611.6" + wire $0\xer_so$8[0:0]$13063 + attribute \src "libresoc.v:187612.3-187632.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:178766.3-178781.6" - wire width 64 $1\fast1$7[63:0]$12986 - attribute \src "libresoc.v:178843.3-178858.6" + attribute \src "libresoc.v:187498.3-187513.6" + wire width 64 $1\fast1$7[63:0]$13057 + attribute \src "libresoc.v:187575.3-187590.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:178801.3-178842.6" + attribute \src "libresoc.v:187533.3-187574.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:178801.3-178842.6" + attribute \src "libresoc.v:187533.3-187574.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:178991.3-179009.6" - wire width 64 $1\spr1$6[63:0]$13011 - attribute \src "libresoc.v:178782.3-178800.6" + attribute \src "libresoc.v:187723.3-187741.6" + wire width 64 $1\spr1$6[63:0]$13082 + attribute \src "libresoc.v:187514.3-187532.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:178946.3-178969.6" - wire width 2 $1\xer_ca$10[1:0]$13005 - attribute \src "libresoc.v:178970.3-178990.6" + attribute \src "libresoc.v:187678.3-187701.6" + wire width 2 $1\xer_ca$10[1:0]$13076 + attribute \src "libresoc.v:187702.3-187722.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:178901.3-178924.6" - wire width 2 $1\xer_ov$9[1:0]$12999 - attribute \src "libresoc.v:178925.3-178945.6" + attribute \src "libresoc.v:187633.3-187656.6" + wire width 2 $1\xer_ov$9[1:0]$13070 + attribute \src "libresoc.v:187657.3-187677.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:178859.3-178879.6" - wire $1\xer_so$8[0:0]$12993 - attribute \src "libresoc.v:178880.3-178900.6" + attribute \src "libresoc.v:187591.3-187611.6" + wire $1\xer_so$8[0:0]$13064 + attribute \src "libresoc.v:187612.3-187632.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:178766.3-178781.6" - wire width 64 $2\fast1$7[63:0]$12987 - attribute \src "libresoc.v:178843.3-178858.6" + attribute \src "libresoc.v:187498.3-187513.6" + wire width 64 $2\fast1$7[63:0]$13058 + attribute \src "libresoc.v:187575.3-187590.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:178801.3-178842.6" + attribute \src "libresoc.v:187533.3-187574.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:178991.3-179009.6" - wire width 64 $2\spr1$6[63:0]$13012 - attribute \src "libresoc.v:178782.3-178800.6" + attribute \src "libresoc.v:187723.3-187741.6" + wire width 64 $2\spr1$6[63:0]$13083 + attribute \src "libresoc.v:187514.3-187532.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:178946.3-178969.6" - wire width 2 $2\xer_ca$10[1:0]$13006 - attribute \src "libresoc.v:178970.3-178990.6" + attribute \src "libresoc.v:187678.3-187701.6" + wire width 2 $2\xer_ca$10[1:0]$13077 + attribute \src "libresoc.v:187702.3-187722.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:178901.3-178924.6" - wire width 2 $2\xer_ov$9[1:0]$13000 - attribute \src "libresoc.v:178925.3-178945.6" + attribute \src "libresoc.v:187633.3-187656.6" + wire width 2 $2\xer_ov$9[1:0]$13071 + attribute \src "libresoc.v:187657.3-187677.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:178859.3-178879.6" - wire $2\xer_so$8[0:0]$12994 - attribute \src "libresoc.v:178880.3-178900.6" + attribute \src "libresoc.v:187591.3-187611.6" + wire $2\xer_so$8[0:0]$13065 + attribute \src "libresoc.v:187612.3-187632.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:178801.3-178842.6" + attribute \src "libresoc.v:187533.3-187574.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:178946.3-178969.6" - wire width 2 $3\xer_ca$10[1:0]$13007 - attribute \src "libresoc.v:178970.3-178990.6" + attribute \src "libresoc.v:187678.3-187701.6" + wire width 2 $3\xer_ca$10[1:0]$13078 + attribute \src "libresoc.v:187702.3-187722.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:178901.3-178924.6" - wire width 2 $3\xer_ov$9[1:0]$13001 - attribute \src "libresoc.v:178925.3-178945.6" + attribute \src "libresoc.v:187633.3-187656.6" + wire width 2 $3\xer_ov$9[1:0]$13072 + attribute \src "libresoc.v:187657.3-187677.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:178859.3-178879.6" - wire $3\xer_so$8[0:0]$12995 - attribute \src "libresoc.v:178880.3-178900.6" + attribute \src "libresoc.v:187591.3-187611.6" + wire $3\xer_so$8[0:0]$13066 + attribute \src "libresoc.v:187612.3-187632.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:178759.18-178759.106" - wire $eq$libresoc.v:178759$12977_Y - attribute \src "libresoc.v:178760.18-178760.106" - wire $eq$libresoc.v:178760$12978_Y - attribute \src "libresoc.v:178761.18-178761.106" - wire $eq$libresoc.v:178761$12979_Y - attribute \src "libresoc.v:178762.18-178762.106" - wire $eq$libresoc.v:178762$12980_Y - attribute \src "libresoc.v:178763.18-178763.106" - wire $eq$libresoc.v:178763$12981_Y - attribute \src "libresoc.v:178764.18-178764.106" - wire $eq$libresoc.v:178764$12982_Y - attribute \src "libresoc.v:178765.18-178765.106" - wire $eq$libresoc.v:178765$12983_Y + attribute \src "libresoc.v:187491.18-187491.106" + wire $eq$libresoc.v:187491$13048_Y + attribute \src "libresoc.v:187492.18-187492.106" + wire $eq$libresoc.v:187492$13049_Y + attribute \src "libresoc.v:187493.18-187493.106" + wire $eq$libresoc.v:187493$13050_Y + attribute \src "libresoc.v:187494.18-187494.106" + wire $eq$libresoc.v:187494$13051_Y + attribute \src "libresoc.v:187495.18-187495.106" + wire $eq$libresoc.v:187495$13052_Y + attribute \src "libresoc.v:187496.18-187496.106" + wire $eq$libresoc.v:187496$13053_Y + attribute \src "libresoc.v:187497.18-187497.106" + wire $eq$libresoc.v:187497$13054_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" @@ -377059,11 +392104,11 @@ module \spr_main wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast1_ok - attribute \src "libresoc.v:178500.7-178500.15" + attribute \src "libresoc.v:187226.7-187226.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 11 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \o @@ -377080,35 +392125,39 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 19 \spr1_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 13 \spr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 13 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -377187,6 +392236,7 @@ module \spr_main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \spr_op__insn_type attribute \enum_base_type "MicrOp" @@ -377263,6 +392313,7 @@ module \spr_main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 12 \spr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -377288,7 +392339,7 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178759$12977 + cell $eq $eq$libresoc.v:187491$13048 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -377296,10 +392347,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178759$12977_Y + connect \Y $eq$libresoc.v:187491$13048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178760$12978 + cell $eq $eq$libresoc.v:187492$13049 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -377307,10 +392358,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178760$12978_Y + connect \Y $eq$libresoc.v:187492$13049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178761$12979 + cell $eq $eq$libresoc.v:187493$13050 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -377318,10 +392369,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178761$12979_Y + connect \Y $eq$libresoc.v:187493$13050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178762$12980 + cell $eq $eq$libresoc.v:187494$13051 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -377329,10 +392380,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178762$12980_Y + connect \Y $eq$libresoc.v:187494$13051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178763$12981 + cell $eq $eq$libresoc.v:187495$13052 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -377340,10 +392391,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178763$12981_Y + connect \Y $eq$libresoc.v:187495$13052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178764$12982 + cell $eq $eq$libresoc.v:187496$13053 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -377351,10 +392402,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178764$12982_Y + connect \Y $eq$libresoc.v:187496$13053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:178765$12983 + cell $eq $eq$libresoc.v:187497$13054 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -377362,24 +392413,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178765$12983_Y + connect \Y $eq$libresoc.v:187497$13054_Y end - attribute \src "libresoc.v:178500.7-178500.20" - process $proc$libresoc.v:178500$13013 + attribute \src "libresoc.v:187226.7-187226.20" + process $proc$libresoc.v:187226$13084 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178766.3-178781.6" - process $proc$libresoc.v:178766$12984 + attribute \src "libresoc.v:187498.3-187513.6" + process $proc$libresoc.v:187498$13055 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$12985 $1\fast1$7[63:0]$12986 - attribute \src "libresoc.v:178767.5-178767.29" + assign $0\fast1$7[63:0]$13056 $1\fast1$7[63:0]$13057 + attribute \src "libresoc.v:187499.5-187499.29" switch \initial - attribute \src "libresoc.v:178767.9-178767.17" + attribute \src "libresoc.v:187499.9-187499.17" case 1'1 case end @@ -377388,30 +392439,30 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$12986 $2\fast1$7[63:0]$12987 + assign $1\fast1$7[63:0]$13057 $2\fast1$7[63:0]$13058 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$12987 \ra + assign $2\fast1$7[63:0]$13058 \ra case - assign $2\fast1$7[63:0]$12987 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$13058 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$12986 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$13057 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$12985 + update \fast1$7 $0\fast1$7[63:0]$13056 end - attribute \src "libresoc.v:178782.3-178800.6" - process $proc$libresoc.v:178782$12988 + attribute \src "libresoc.v:187514.3-187532.6" + process $proc$libresoc.v:187514$13059 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:178783.5-178783.29" + attribute \src "libresoc.v:187515.5-187515.29" switch \initial - attribute \src "libresoc.v:178783.9-178783.17" + attribute \src "libresoc.v:187515.9-187515.17" case 1'1 case end @@ -377437,17 +392488,17 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:178801.3-178842.6" - process $proc$libresoc.v:178801$12989 + attribute \src "libresoc.v:187533.3-187574.6" + process $proc$libresoc.v:187533$13060 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:178802.5-178802.29" + attribute \src "libresoc.v:187534.5-187534.29" switch \initial - attribute \src "libresoc.v:178802.9-178802.17" + attribute \src "libresoc.v:187534.9-187534.17" case 1'1 case end @@ -377498,14 +392549,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:178843.3-178858.6" - process $proc$libresoc.v:178843$12990 + attribute \src "libresoc.v:187575.3-187590.6" + process $proc$libresoc.v:187575$13061 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:178844.5-178844.29" + attribute \src "libresoc.v:187576.5-187576.29" switch \initial - attribute \src "libresoc.v:178844.9-178844.17" + attribute \src "libresoc.v:187576.9-187576.17" case 1'1 case end @@ -377530,14 +392581,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:178859.3-178879.6" - process $proc$libresoc.v:178859$12991 + attribute \src "libresoc.v:187591.3-187611.6" + process $proc$libresoc.v:187591$13062 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$12992 $1\xer_so$8[0:0]$12993 - attribute \src "libresoc.v:178860.5-178860.29" + assign $0\xer_so$8[0:0]$13063 $1\xer_so$8[0:0]$13064 + attribute \src "libresoc.v:187592.5-187592.29" switch \initial - attribute \src "libresoc.v:178860.9-178860.17" + attribute \src "libresoc.v:187592.9-187592.17" case 1'1 case end @@ -377546,39 +392597,39 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$12993 $2\xer_so$8[0:0]$12994 + assign $1\xer_so$8[0:0]$13064 $2\xer_so$8[0:0]$13065 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$12994 $3\xer_so$8[0:0]$12995 + assign $2\xer_so$8[0:0]$13065 $3\xer_so$8[0:0]$13066 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$12995 \ra [31] + assign $3\xer_so$8[0:0]$13066 \ra [31] case - assign $3\xer_so$8[0:0]$12995 1'0 + assign $3\xer_so$8[0:0]$13066 1'0 end case - assign $2\xer_so$8[0:0]$12994 1'0 + assign $2\xer_so$8[0:0]$13065 1'0 end case - assign $1\xer_so$8[0:0]$12993 1'0 + assign $1\xer_so$8[0:0]$13064 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$12992 + update \xer_so$8 $0\xer_so$8[0:0]$13063 end - attribute \src "libresoc.v:178880.3-178900.6" - process $proc$libresoc.v:178880$12996 + attribute \src "libresoc.v:187612.3-187632.6" + process $proc$libresoc.v:187612$13067 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:178881.5-178881.29" + attribute \src "libresoc.v:187613.5-187613.29" switch \initial - attribute \src "libresoc.v:178881.9-178881.17" + attribute \src "libresoc.v:187613.9-187613.17" case 1'1 case end @@ -377612,14 +392663,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:178901.3-178924.6" - process $proc$libresoc.v:178901$12997 + attribute \src "libresoc.v:187633.3-187656.6" + process $proc$libresoc.v:187633$13068 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$12998 $1\xer_ov$9[1:0]$12999 - attribute \src "libresoc.v:178902.5-178902.29" + assign $0\xer_ov$9[1:0]$13069 $1\xer_ov$9[1:0]$13070 + attribute \src "libresoc.v:187634.5-187634.29" switch \initial - attribute \src "libresoc.v:178902.9-178902.17" + attribute \src "libresoc.v:187634.9-187634.17" case 1'1 case end @@ -377628,40 +392679,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$12999 $2\xer_ov$9[1:0]$13000 + assign $1\xer_ov$9[1:0]$13070 $2\xer_ov$9[1:0]$13071 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$13000 $3\xer_ov$9[1:0]$13001 + assign $2\xer_ov$9[1:0]$13071 $3\xer_ov$9[1:0]$13072 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$13001 [0] \ra [30] - assign $3\xer_ov$9[1:0]$13001 [1] \ra [19] + assign $3\xer_ov$9[1:0]$13072 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13072 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$13001 2'00 + assign $3\xer_ov$9[1:0]$13072 2'00 end case - assign $2\xer_ov$9[1:0]$13000 2'00 + assign $2\xer_ov$9[1:0]$13071 2'00 end case - assign $1\xer_ov$9[1:0]$12999 2'00 + assign $1\xer_ov$9[1:0]$13070 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$12998 + update \xer_ov$9 $0\xer_ov$9[1:0]$13069 end - attribute \src "libresoc.v:178925.3-178945.6" - process $proc$libresoc.v:178925$13002 + attribute \src "libresoc.v:187657.3-187677.6" + process $proc$libresoc.v:187657$13073 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:178926.5-178926.29" + attribute \src "libresoc.v:187658.5-187658.29" switch \initial - attribute \src "libresoc.v:178926.9-178926.17" + attribute \src "libresoc.v:187658.9-187658.17" case 1'1 case end @@ -377695,14 +392746,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:178946.3-178969.6" - process $proc$libresoc.v:178946$13003 + attribute \src "libresoc.v:187678.3-187701.6" + process $proc$libresoc.v:187678$13074 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$13004 $1\xer_ca$10[1:0]$13005 - attribute \src "libresoc.v:178947.5-178947.29" + assign $0\xer_ca$10[1:0]$13075 $1\xer_ca$10[1:0]$13076 + attribute \src "libresoc.v:187679.5-187679.29" switch \initial - attribute \src "libresoc.v:178947.9-178947.17" + attribute \src "libresoc.v:187679.9-187679.17" case 1'1 case end @@ -377711,40 +392762,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$13005 $2\xer_ca$10[1:0]$13006 + assign $1\xer_ca$10[1:0]$13076 $2\xer_ca$10[1:0]$13077 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$13006 $3\xer_ca$10[1:0]$13007 + assign $2\xer_ca$10[1:0]$13077 $3\xer_ca$10[1:0]$13078 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$13007 [0] \ra [29] - assign $3\xer_ca$10[1:0]$13007 [1] \ra [18] + assign $3\xer_ca$10[1:0]$13078 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13078 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$13007 2'00 + assign $3\xer_ca$10[1:0]$13078 2'00 end case - assign $2\xer_ca$10[1:0]$13006 2'00 + assign $2\xer_ca$10[1:0]$13077 2'00 end case - assign $1\xer_ca$10[1:0]$13005 2'00 + assign $1\xer_ca$10[1:0]$13076 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$13004 + update \xer_ca$10 $0\xer_ca$10[1:0]$13075 end - attribute \src "libresoc.v:178970.3-178990.6" - process $proc$libresoc.v:178970$13008 + attribute \src "libresoc.v:187702.3-187722.6" + process $proc$libresoc.v:187702$13079 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:178971.5-178971.29" + attribute \src "libresoc.v:187703.5-187703.29" switch \initial - attribute \src "libresoc.v:178971.9-178971.17" + attribute \src "libresoc.v:187703.9-187703.17" case 1'1 case end @@ -377778,14 +392829,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:178991.3-179009.6" - process $proc$libresoc.v:178991$13009 + attribute \src "libresoc.v:187723.3-187741.6" + process $proc$libresoc.v:187723$13080 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$13010 $1\spr1$6[63:0]$13011 - attribute \src "libresoc.v:178992.5-178992.29" + assign $0\spr1$6[63:0]$13081 $1\spr1$6[63:0]$13082 + attribute \src "libresoc.v:187724.5-187724.29" switch \initial - attribute \src "libresoc.v:178992.9-178992.17" + attribute \src "libresoc.v:187724.9-187724.17" case 1'1 case end @@ -377794,64 +392845,64 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$13011 $2\spr1$6[63:0]$13012 + assign $1\spr1$6[63:0]$13082 $2\spr1$6[63:0]$13083 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$13012 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$13083 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$13012 \ra + assign $2\spr1$6[63:0]$13083 \ra end case - assign $1\spr1$6[63:0]$13011 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$13082 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$13010 + update \spr1$6 $0\spr1$6[63:0]$13081 end - connect \$11 $eq$libresoc.v:178759$12977_Y - connect \$13 $eq$libresoc.v:178760$12978_Y - connect \$15 $eq$libresoc.v:178761$12979_Y - connect \$17 $eq$libresoc.v:178762$12980_Y - connect \$19 $eq$libresoc.v:178763$12981_Y - connect \$21 $eq$libresoc.v:178764$12982_Y - connect \$23 $eq$libresoc.v:178765$12983_Y + connect \$11 $eq$libresoc.v:187491$13048_Y + connect \$13 $eq$libresoc.v:187492$13049_Y + connect \$15 $eq$libresoc.v:187493$13050_Y + connect \$17 $eq$libresoc.v:187494$13051_Y + connect \$19 $eq$libresoc.v:187495$13052_Y + connect \$21 $eq$libresoc.v:187496$13053_Y + connect \$23 $eq$libresoc.v:187497$13054_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:179017.1-179832.10" +attribute \src "libresoc.v:187749.1-188585.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:179144.3-179174.6" + attribute \src "libresoc.v:187879.3-187909.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:179175.3-179205.6" + attribute \src "libresoc.v:187910.3-187940.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:179018.7-179018.20" + attribute \src "libresoc.v:187750.7-187750.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179206.3-179518.6" + attribute \src "libresoc.v:187941.3-188262.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:179519.3-179831.6" + attribute \src "libresoc.v:188263.3-188584.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:179144.3-179174.6" + attribute \src "libresoc.v:187879.3-187909.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:179175.3-179205.6" + attribute \src "libresoc.v:187910.3-187940.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:179206.3-179518.6" + attribute \src "libresoc.v:187941.3-188262.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:179519.3-179831.6" + attribute \src "libresoc.v:188263.3-188584.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:179018.7-179018.15" + attribute \src "libresoc.v:187750.7-187750.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -377918,6 +392969,9 @@ module \sprmap attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -377968,26 +393022,26 @@ module \sprmap wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:179018.7-179018.20" - process $proc$libresoc.v:179018$13018 + attribute \src "libresoc.v:187750.7-187750.20" + process $proc$libresoc.v:187750$13089 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179144.3-179174.6" - process $proc$libresoc.v:179144$13014 + attribute \src "libresoc.v:187879.3-187909.6" + process $proc$libresoc.v:187879$13085 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:179145.5-179145.29" + attribute \src "libresoc.v:187880.5-187880.29" switch \initial - attribute \src "libresoc.v:179145.9-179145.17" + attribute \src "libresoc.v:187880.9-187880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -378027,18 +393081,18 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:179175.3-179205.6" - process $proc$libresoc.v:179175$13015 + attribute \src "libresoc.v:187910.3-187940.6" + process $proc$libresoc.v:187910$13086 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:179176.5-179176.29" + attribute \src "libresoc.v:187911.5-187911.29" switch \initial - attribute \src "libresoc.v:179176.9-179176.17" + attribute \src "libresoc.v:187911.9-187911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -378078,18 +393132,18 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:179206.3-179518.6" - process $proc$libresoc.v:179206$13016 + attribute \src "libresoc.v:187941.3-188262.6" + process $proc$libresoc.v:187941$13087 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:179207.5-179207.29" + attribute \src "libresoc.v:187942.5-187942.29" switch \initial - attribute \src "libresoc.v:179207.9-179207.17" + attribute \src "libresoc.v:187942.9-187942.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -378320,203 +393374,215 @@ module \sprmap assign { } { } assign $1\spr_o[9:0] 10'0000111111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 + case 10'1011000000 assign { } { } assign $1\spr_o[9:0] 10'0001000000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 + case 10'1011010000 assign { } { } assign $1\spr_o[9:0] 10'0001000001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 + case 10'1011010001 assign { } { } assign $1\spr_o[9:0] 10'0001000010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 + case 10'1100000000 assign { } { } assign $1\spr_o[9:0] 10'0001000011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 + case 10'1100000001 assign { } { } assign $1\spr_o[9:0] 10'0001000100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 + case 10'1100000010 assign { } { } assign $1\spr_o[9:0] 10'0001000101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 + case 10'1100000011 assign { } { } assign $1\spr_o[9:0] 10'0001000110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 + case 10'1100000100 assign { } { } assign $1\spr_o[9:0] 10'0001000111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 + case 10'1100000101 assign { } { } assign $1\spr_o[9:0] 10'0001001000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 + case 10'1100000110 assign { } { } assign $1\spr_o[9:0] 10'0001001001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 + case 10'1100000111 assign { } { } assign $1\spr_o[9:0] 10'0001001010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 + case 10'1100001000 assign { } { } assign $1\spr_o[9:0] 10'0001001011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 + case 10'1100001011 assign { } { } assign $1\spr_o[9:0] 10'0001001100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 + case 10'1100001100 assign { } { } assign $1\spr_o[9:0] 10'0001001101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 + case 10'1100001101 assign { } { } assign $1\spr_o[9:0] 10'0001001110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 + case 10'1100001110 assign { } { } assign $1\spr_o[9:0] 10'0001001111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 + case 10'1100010000 assign { } { } assign $1\spr_o[9:0] 10'0001010000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 + case 10'1100010001 assign { } { } assign $1\spr_o[9:0] 10'0001010001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 + case 10'1100010010 assign { } { } assign $1\spr_o[9:0] 10'0001010010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 + case 10'1100010011 assign { } { } assign $1\spr_o[9:0] 10'0001010011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 + case 10'1100010100 assign { } { } assign $1\spr_o[9:0] 10'0001010100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 + case 10'1100010101 assign { } { } assign $1\spr_o[9:0] 10'0001010101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 + case 10'1100010110 assign { } { } assign $1\spr_o[9:0] 10'0001010110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 + case 10'1100010111 assign { } { } assign $1\spr_o[9:0] 10'0001010111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 + case 10'1100011000 assign { } { } assign $1\spr_o[9:0] 10'0001011000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 + case 10'1100011011 assign { } { } assign $1\spr_o[9:0] 10'0001011001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 + case 10'1100011100 assign { } { } assign $1\spr_o[9:0] 10'0001011010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 + case 10'1100011101 assign { } { } assign $1\spr_o[9:0] 10'0001011011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 + case 10'1100011110 assign { } { } assign $1\spr_o[9:0] 10'0001011100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 + case 10'1100100000 assign { } { } assign $1\spr_o[9:0] 10'0001011101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 + case 10'1100100001 assign { } { } assign $1\spr_o[9:0] 10'0001011110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 + case 10'1100100010 assign { } { } assign $1\spr_o[9:0] 10'0001011111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 + case 10'1100100011 assign { } { } assign $1\spr_o[9:0] 10'0001100000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 + case 10'1100100100 assign { } { } assign $1\spr_o[9:0] 10'0001100001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 + case 10'1100100101 assign { } { } assign $1\spr_o[9:0] 10'0001100010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 + case 10'1100100110 assign { } { } assign $1\spr_o[9:0] 10'0001100011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 + case 10'1100101000 assign { } { } assign $1\spr_o[9:0] 10'0001100100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 assign { } { } assign $1\spr_o[9:0] 10'0001100110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 + case 10'1100101011 assign { } { } assign $1\spr_o[9:0] 10'0001100111 attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" case 10'1101010000 assign { } { } - assign $1\spr_o[9:0] 10'0001101000 + assign $1\spr_o[9:0] 10'0001101011 attribute \src "libresoc.v:0.0-0.0" case 10'1101010001 assign { } { } - assign $1\spr_o[9:0] 10'0001101001 + assign $1\spr_o[9:0] 10'0001101100 attribute \src "libresoc.v:0.0-0.0" case 10'1101010111 assign { } { } - assign $1\spr_o[9:0] 10'0001101010 + assign $1\spr_o[9:0] 10'0001101101 attribute \src "libresoc.v:0.0-0.0" case 10'1110000000 assign { } { } - assign $1\spr_o[9:0] 10'0001101011 + assign $1\spr_o[9:0] 10'0001101110 attribute \src "libresoc.v:0.0-0.0" case 10'1110000010 assign { } { } - assign $1\spr_o[9:0] 10'0001101100 + assign $1\spr_o[9:0] 10'0001101111 attribute \src "libresoc.v:0.0-0.0" case 10'1111111111 assign { } { } - assign $1\spr_o[9:0] 10'0001101101 + assign $1\spr_o[9:0] 10'0001110000 case assign $1\spr_o[9:0] 10'0000000000 end sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:179519.3-179831.6" - process $proc$libresoc.v:179519$13017 + attribute \src "libresoc.v:188263.3-188584.6" + process $proc$libresoc.v:188263$13088 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:179520.5-179520.29" + attribute \src "libresoc.v:188264.5-188264.29" switch \initial - attribute \src "libresoc.v:179520.9-179520.17" + attribute \src "libresoc.v:188264.9-188264.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -378747,6 +393813,18 @@ module \sprmap assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -378933,36 +394011,36 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:179836.1-180651.10" +attribute \src "libresoc.v:188589.1-189425.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" -module \sprmap$212 - attribute \src "libresoc.v:179963.3-179993.6" +module \sprmap$174 + attribute \src "libresoc.v:188719.3-188749.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:179994.3-180024.6" + attribute \src "libresoc.v:188750.3-188780.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:179837.7-179837.20" + attribute \src "libresoc.v:188590.7-188590.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180025.3-180337.6" + attribute \src "libresoc.v:188781.3-189102.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:180338.3-180650.6" + attribute \src "libresoc.v:189103.3-189424.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:179963.3-179993.6" + attribute \src "libresoc.v:188719.3-188749.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:179994.3-180024.6" + attribute \src "libresoc.v:188750.3-188780.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:180025.3-180337.6" + attribute \src "libresoc.v:188781.3-189102.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:180338.3-180650.6" + attribute \src "libresoc.v:189103.3-189424.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:179837.7-179837.15" + attribute \src "libresoc.v:188590.7-188590.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -379029,6 +394107,9 @@ module \sprmap$212 attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -379079,26 +394160,26 @@ module \sprmap$212 wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:179837.7-179837.20" - process $proc$libresoc.v:179837$13023 + attribute \src "libresoc.v:188590.7-188590.20" + process $proc$libresoc.v:188590$13094 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179963.3-179993.6" - process $proc$libresoc.v:179963$13019 + attribute \src "libresoc.v:188719.3-188749.6" + process $proc$libresoc.v:188719$13090 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:179964.5-179964.29" + attribute \src "libresoc.v:188720.5-188720.29" switch \initial - attribute \src "libresoc.v:179964.9-179964.17" + attribute \src "libresoc.v:188720.9-188720.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -379138,18 +394219,18 @@ module \sprmap$212 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:179994.3-180024.6" - process $proc$libresoc.v:179994$13020 + attribute \src "libresoc.v:188750.3-188780.6" + process $proc$libresoc.v:188750$13091 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:179995.5-179995.29" + attribute \src "libresoc.v:188751.5-188751.29" switch \initial - attribute \src "libresoc.v:179995.9-179995.17" + attribute \src "libresoc.v:188751.9-188751.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -379189,18 +394270,18 @@ module \sprmap$212 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:180025.3-180337.6" - process $proc$libresoc.v:180025$13021 + attribute \src "libresoc.v:188781.3-189102.6" + process $proc$libresoc.v:188781$13092 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:180026.5-180026.29" + attribute \src "libresoc.v:188782.5-188782.29" switch \initial - attribute \src "libresoc.v:180026.9-180026.17" + attribute \src "libresoc.v:188782.9-188782.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -379431,203 +394512,215 @@ module \sprmap$212 assign { } { } assign $1\spr_o[9:0] 10'0000111111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 + case 10'1011000000 assign { } { } assign $1\spr_o[9:0] 10'0001000000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 + case 10'1011010000 assign { } { } assign $1\spr_o[9:0] 10'0001000001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 + case 10'1011010001 assign { } { } assign $1\spr_o[9:0] 10'0001000010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 + case 10'1100000000 assign { } { } assign $1\spr_o[9:0] 10'0001000011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 + case 10'1100000001 assign { } { } assign $1\spr_o[9:0] 10'0001000100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 + case 10'1100000010 assign { } { } assign $1\spr_o[9:0] 10'0001000101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 + case 10'1100000011 assign { } { } assign $1\spr_o[9:0] 10'0001000110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 + case 10'1100000100 assign { } { } assign $1\spr_o[9:0] 10'0001000111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 + case 10'1100000101 assign { } { } assign $1\spr_o[9:0] 10'0001001000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 + case 10'1100000110 assign { } { } assign $1\spr_o[9:0] 10'0001001001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 + case 10'1100000111 assign { } { } assign $1\spr_o[9:0] 10'0001001010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 + case 10'1100001000 assign { } { } assign $1\spr_o[9:0] 10'0001001011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 + case 10'1100001011 assign { } { } assign $1\spr_o[9:0] 10'0001001100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 + case 10'1100001100 assign { } { } assign $1\spr_o[9:0] 10'0001001101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 + case 10'1100001101 assign { } { } assign $1\spr_o[9:0] 10'0001001110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 + case 10'1100001110 assign { } { } assign $1\spr_o[9:0] 10'0001001111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 + case 10'1100010000 assign { } { } assign $1\spr_o[9:0] 10'0001010000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 + case 10'1100010001 assign { } { } assign $1\spr_o[9:0] 10'0001010001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 + case 10'1100010010 assign { } { } assign $1\spr_o[9:0] 10'0001010010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 + case 10'1100010011 assign { } { } assign $1\spr_o[9:0] 10'0001010011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 + case 10'1100010100 assign { } { } assign $1\spr_o[9:0] 10'0001010100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 + case 10'1100010101 assign { } { } assign $1\spr_o[9:0] 10'0001010101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 + case 10'1100010110 assign { } { } assign $1\spr_o[9:0] 10'0001010110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 + case 10'1100010111 assign { } { } assign $1\spr_o[9:0] 10'0001010111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 + case 10'1100011000 assign { } { } assign $1\spr_o[9:0] 10'0001011000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 + case 10'1100011011 assign { } { } assign $1\spr_o[9:0] 10'0001011001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 + case 10'1100011100 assign { } { } assign $1\spr_o[9:0] 10'0001011010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 + case 10'1100011101 assign { } { } assign $1\spr_o[9:0] 10'0001011011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 + case 10'1100011110 assign { } { } assign $1\spr_o[9:0] 10'0001011100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 + case 10'1100100000 assign { } { } assign $1\spr_o[9:0] 10'0001011101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 + case 10'1100100001 assign { } { } assign $1\spr_o[9:0] 10'0001011110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 + case 10'1100100010 assign { } { } assign $1\spr_o[9:0] 10'0001011111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 + case 10'1100100011 assign { } { } assign $1\spr_o[9:0] 10'0001100000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 + case 10'1100100100 assign { } { } assign $1\spr_o[9:0] 10'0001100001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 + case 10'1100100101 assign { } { } assign $1\spr_o[9:0] 10'0001100010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 + case 10'1100100110 assign { } { } assign $1\spr_o[9:0] 10'0001100011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 + case 10'1100101000 assign { } { } assign $1\spr_o[9:0] 10'0001100100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 assign { } { } assign $1\spr_o[9:0] 10'0001100110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 + case 10'1100101011 assign { } { } assign $1\spr_o[9:0] 10'0001100111 attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" case 10'1101010000 assign { } { } - assign $1\spr_o[9:0] 10'0001101000 + assign $1\spr_o[9:0] 10'0001101011 attribute \src "libresoc.v:0.0-0.0" case 10'1101010001 assign { } { } - assign $1\spr_o[9:0] 10'0001101001 + assign $1\spr_o[9:0] 10'0001101100 attribute \src "libresoc.v:0.0-0.0" case 10'1101010111 assign { } { } - assign $1\spr_o[9:0] 10'0001101010 + assign $1\spr_o[9:0] 10'0001101101 attribute \src "libresoc.v:0.0-0.0" case 10'1110000000 assign { } { } - assign $1\spr_o[9:0] 10'0001101011 + assign $1\spr_o[9:0] 10'0001101110 attribute \src "libresoc.v:0.0-0.0" case 10'1110000010 assign { } { } - assign $1\spr_o[9:0] 10'0001101100 + assign $1\spr_o[9:0] 10'0001101111 attribute \src "libresoc.v:0.0-0.0" case 10'1111111111 assign { } { } - assign $1\spr_o[9:0] 10'0001101101 + assign $1\spr_o[9:0] 10'0001110000 case assign $1\spr_o[9:0] 10'0000000000 end sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:180338.3-180650.6" - process $proc$libresoc.v:180338$13022 + attribute \src "libresoc.v:189103.3-189424.6" + process $proc$libresoc.v:189103$13093 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:180339.5-180339.29" + attribute \src "libresoc.v:189104.5-189104.29" switch \initial - attribute \src "libresoc.v:180339.9-180339.17" + attribute \src "libresoc.v:189104.9-189104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -379858,6 +394951,18 @@ module \sprmap$212 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -380044,75 +395149,1375 @@ module \sprmap$212 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:180655.1-180713.10" +attribute \src "libresoc.v:189429.1-189569.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" +attribute \generator "nMigen" +module \sram4k_0 + attribute \src "libresoc.v:189504.3-189518.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:189534.3-189548.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:189430.7-189430.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189489.3-189503.6" + wire $0\sram4k_0_wb__ack$next[0:0]$13099 + attribute \src "libresoc.v:189470.3-189471.49" + wire $0\sram4k_0_wb__ack[0:0] + attribute \src "libresoc.v:189519.3-189533.6" + wire width 64 $0\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189479.3-189488.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189549.3-189568.6" + wire $0\we[0:0] + attribute \src "libresoc.v:189504.3-189518.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:189534.3-189548.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:189489.3-189503.6" + wire $1\sram4k_0_wb__ack$next[0:0]$13100 + attribute \src "libresoc.v:189447.7-189447.30" + wire $1\sram4k_0_wb__ack[0:0] + attribute \src "libresoc.v:189519.3-189533.6" + wire width 64 $1\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189479.3-189488.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189549.3-189568.6" + wire $1\we[0:0] + attribute \src "libresoc.v:189504.3-189518.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189534.3-189548.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189489.3-189503.6" + wire $2\sram4k_0_wb__ack$next[0:0]$13101 + attribute \src "libresoc.v:189519.3-189533.6" + wire width 64 $2\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189549.3-189568.6" + wire $2\we[0:0] + attribute \src "libresoc.v:189549.3-189568.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189469.17-189469.129" + wire $and$libresoc.v:189469$13095_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189430.7-189430.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_0_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:189469$13095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_0_wb__cyc + connect \B \sram4k_0_wb__stb + connect \Y $and$libresoc.v:189469$13095_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189472.21-189478.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:189430.7-189430.20" + process $proc$libresoc.v:189430$13106 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189447.7-189447.30" + process $proc$libresoc.v:189447$13107 + assign { } { } + assign $1\sram4k_0_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0] + end + attribute \src "libresoc.v:189470.3-189471.49" + process $proc$libresoc.v:189470$13096 + assign { } { } + assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next + sync posedge \clk + update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0] + end + attribute \src "libresoc.v:189479.3-189488.6" + process $proc$libresoc.v:189479$13097 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189480.5-189480.29" + switch \initial + attribute \src "libresoc.v:189480.9-189480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:189489.3-189503.6" + process $proc$libresoc.v:189489$13098 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_0_wb__ack$next[0:0]$13099 $2\sram4k_0_wb__ack$next[0:0]$13101 + attribute \src "libresoc.v:189490.5-189490.29" + switch \initial + attribute \src "libresoc.v:189490.9-189490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_0_wb__ack$next[0:0]$13100 \wb_active + case + assign $1\sram4k_0_wb__ack$next[0:0]$13100 \sram4k_0_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_0_wb__ack$next[0:0]$13101 1'0 + case + assign $2\sram4k_0_wb__ack$next[0:0]$13101 $1\sram4k_0_wb__ack$next[0:0]$13100 + end + sync always + update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13099 + end + attribute \src "libresoc.v:189504.3-189518.6" + process $proc$libresoc.v:189504$13102 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189505.5-189505.29" + switch \initial + attribute \src "libresoc.v:189505.9-189505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_0_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:189519.3-189533.6" + process $proc$libresoc.v:189519$13103 + assign { } { } + assign { } { } + assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189520.5-189520.29" + switch \initial + attribute \src "libresoc.v:189520.9-189520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_0_wb__dat_r[63:0] $2\sram4k_0_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_0_wb__dat_r[63:0] \q + case + assign $2\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0] + end + attribute \src "libresoc.v:189534.3-189548.6" + process $proc$libresoc.v:189534$13104 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189535.5-189535.29" + switch \initial + attribute \src "libresoc.v:189535.9-189535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_0_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189549.3-189568.6" + process $proc$libresoc.v:189549$13105 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189550.5-189550.29" + switch \initial + attribute \src "libresoc.v:189550.9-189550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_0_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_0_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:189469$13095_Y +end +attribute \src "libresoc.v:189573.1-189713.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" +attribute \generator "nMigen" +module \sram4k_1 + attribute \src "libresoc.v:189648.3-189662.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:189678.3-189692.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:189574.7-189574.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189633.3-189647.6" + wire $0\sram4k_1_wb__ack$next[0:0]$13112 + attribute \src "libresoc.v:189614.3-189615.49" + wire $0\sram4k_1_wb__ack[0:0] + attribute \src "libresoc.v:189663.3-189677.6" + wire width 64 $0\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189623.3-189632.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189693.3-189712.6" + wire $0\we[0:0] + attribute \src "libresoc.v:189648.3-189662.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:189678.3-189692.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:189633.3-189647.6" + wire $1\sram4k_1_wb__ack$next[0:0]$13113 + attribute \src "libresoc.v:189591.7-189591.30" + wire $1\sram4k_1_wb__ack[0:0] + attribute \src "libresoc.v:189663.3-189677.6" + wire width 64 $1\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189623.3-189632.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189693.3-189712.6" + wire $1\we[0:0] + attribute \src "libresoc.v:189648.3-189662.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189678.3-189692.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189633.3-189647.6" + wire $2\sram4k_1_wb__ack$next[0:0]$13114 + attribute \src "libresoc.v:189663.3-189677.6" + wire width 64 $2\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189693.3-189712.6" + wire $2\we[0:0] + attribute \src "libresoc.v:189693.3-189712.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189613.17-189613.129" + wire $and$libresoc.v:189613$13108_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189574.7-189574.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_1_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:189613$13108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_1_wb__cyc + connect \B \sram4k_1_wb__stb + connect \Y $and$libresoc.v:189613$13108_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189616.21-189622.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:189574.7-189574.20" + process $proc$libresoc.v:189574$13119 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189591.7-189591.30" + process $proc$libresoc.v:189591$13120 + assign { } { } + assign $1\sram4k_1_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0] + end + attribute \src "libresoc.v:189614.3-189615.49" + process $proc$libresoc.v:189614$13109 + assign { } { } + assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next + sync posedge \clk + update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0] + end + attribute \src "libresoc.v:189623.3-189632.6" + process $proc$libresoc.v:189623$13110 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189624.5-189624.29" + switch \initial + attribute \src "libresoc.v:189624.9-189624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:189633.3-189647.6" + process $proc$libresoc.v:189633$13111 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_1_wb__ack$next[0:0]$13112 $2\sram4k_1_wb__ack$next[0:0]$13114 + attribute \src "libresoc.v:189634.5-189634.29" + switch \initial + attribute \src "libresoc.v:189634.9-189634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_1_wb__ack$next[0:0]$13113 \wb_active + case + assign $1\sram4k_1_wb__ack$next[0:0]$13113 \sram4k_1_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_1_wb__ack$next[0:0]$13114 1'0 + case + assign $2\sram4k_1_wb__ack$next[0:0]$13114 $1\sram4k_1_wb__ack$next[0:0]$13113 + end + sync always + update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13112 + end + attribute \src "libresoc.v:189648.3-189662.6" + process $proc$libresoc.v:189648$13115 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189649.5-189649.29" + switch \initial + attribute \src "libresoc.v:189649.9-189649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_1_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:189663.3-189677.6" + process $proc$libresoc.v:189663$13116 + assign { } { } + assign { } { } + assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189664.5-189664.29" + switch \initial + attribute \src "libresoc.v:189664.9-189664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_1_wb__dat_r[63:0] $2\sram4k_1_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_1_wb__dat_r[63:0] \q + case + assign $2\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0] + end + attribute \src "libresoc.v:189678.3-189692.6" + process $proc$libresoc.v:189678$13117 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189679.5-189679.29" + switch \initial + attribute \src "libresoc.v:189679.9-189679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_1_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189693.3-189712.6" + process $proc$libresoc.v:189693$13118 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189694.5-189694.29" + switch \initial + attribute \src "libresoc.v:189694.9-189694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_1_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_1_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:189613$13108_Y +end +attribute \src "libresoc.v:189717.1-189857.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" +attribute \generator "nMigen" +module \sram4k_2 + attribute \src "libresoc.v:189792.3-189806.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:189822.3-189836.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:189718.7-189718.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189777.3-189791.6" + wire $0\sram4k_2_wb__ack$next[0:0]$13125 + attribute \src "libresoc.v:189758.3-189759.49" + wire $0\sram4k_2_wb__ack[0:0] + attribute \src "libresoc.v:189807.3-189821.6" + wire width 64 $0\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189767.3-189776.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189837.3-189856.6" + wire $0\we[0:0] + attribute \src "libresoc.v:189792.3-189806.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:189822.3-189836.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:189777.3-189791.6" + wire $1\sram4k_2_wb__ack$next[0:0]$13126 + attribute \src "libresoc.v:189735.7-189735.30" + wire $1\sram4k_2_wb__ack[0:0] + attribute \src "libresoc.v:189807.3-189821.6" + wire width 64 $1\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189767.3-189776.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189837.3-189856.6" + wire $1\we[0:0] + attribute \src "libresoc.v:189792.3-189806.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189822.3-189836.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189777.3-189791.6" + wire $2\sram4k_2_wb__ack$next[0:0]$13127 + attribute \src "libresoc.v:189807.3-189821.6" + wire width 64 $2\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189837.3-189856.6" + wire $2\we[0:0] + attribute \src "libresoc.v:189837.3-189856.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189757.17-189757.129" + wire $and$libresoc.v:189757$13121_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189718.7-189718.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_2_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:189757$13121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_2_wb__cyc + connect \B \sram4k_2_wb__stb + connect \Y $and$libresoc.v:189757$13121_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189760.21-189766.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:189718.7-189718.20" + process $proc$libresoc.v:189718$13132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189735.7-189735.30" + process $proc$libresoc.v:189735$13133 + assign { } { } + assign $1\sram4k_2_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0] + end + attribute \src "libresoc.v:189758.3-189759.49" + process $proc$libresoc.v:189758$13122 + assign { } { } + assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next + sync posedge \clk + update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0] + end + attribute \src "libresoc.v:189767.3-189776.6" + process $proc$libresoc.v:189767$13123 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189768.5-189768.29" + switch \initial + attribute \src "libresoc.v:189768.9-189768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:189777.3-189791.6" + process $proc$libresoc.v:189777$13124 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_2_wb__ack$next[0:0]$13125 $2\sram4k_2_wb__ack$next[0:0]$13127 + attribute \src "libresoc.v:189778.5-189778.29" + switch \initial + attribute \src "libresoc.v:189778.9-189778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_2_wb__ack$next[0:0]$13126 \wb_active + case + assign $1\sram4k_2_wb__ack$next[0:0]$13126 \sram4k_2_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_2_wb__ack$next[0:0]$13127 1'0 + case + assign $2\sram4k_2_wb__ack$next[0:0]$13127 $1\sram4k_2_wb__ack$next[0:0]$13126 + end + sync always + update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13125 + end + attribute \src "libresoc.v:189792.3-189806.6" + process $proc$libresoc.v:189792$13128 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189793.5-189793.29" + switch \initial + attribute \src "libresoc.v:189793.9-189793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_2_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:189807.3-189821.6" + process $proc$libresoc.v:189807$13129 + assign { } { } + assign { } { } + assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189808.5-189808.29" + switch \initial + attribute \src "libresoc.v:189808.9-189808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_2_wb__dat_r[63:0] $2\sram4k_2_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_2_wb__dat_r[63:0] \q + case + assign $2\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0] + end + attribute \src "libresoc.v:189822.3-189836.6" + process $proc$libresoc.v:189822$13130 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189823.5-189823.29" + switch \initial + attribute \src "libresoc.v:189823.9-189823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_2_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189837.3-189856.6" + process $proc$libresoc.v:189837$13131 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189838.5-189838.29" + switch \initial + attribute \src "libresoc.v:189838.9-189838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_2_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_2_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:189757$13121_Y +end +attribute \src "libresoc.v:189861.1-190001.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" +attribute \generator "nMigen" +module \sram4k_3 + attribute \src "libresoc.v:189936.3-189950.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:189966.3-189980.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:189862.7-189862.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189921.3-189935.6" + wire $0\sram4k_3_wb__ack$next[0:0]$13138 + attribute \src "libresoc.v:189902.3-189903.49" + wire $0\sram4k_3_wb__ack[0:0] + attribute \src "libresoc.v:189951.3-189965.6" + wire width 64 $0\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:189911.3-189920.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189981.3-190000.6" + wire $0\we[0:0] + attribute \src "libresoc.v:189936.3-189950.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:189966.3-189980.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:189921.3-189935.6" + wire $1\sram4k_3_wb__ack$next[0:0]$13139 + attribute \src "libresoc.v:189879.7-189879.30" + wire $1\sram4k_3_wb__ack[0:0] + attribute \src "libresoc.v:189951.3-189965.6" + wire width 64 $1\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:189911.3-189920.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189981.3-190000.6" + wire $1\we[0:0] + attribute \src "libresoc.v:189936.3-189950.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189966.3-189980.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189921.3-189935.6" + wire $2\sram4k_3_wb__ack$next[0:0]$13140 + attribute \src "libresoc.v:189951.3-189965.6" + wire width 64 $2\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:189981.3-190000.6" + wire $2\we[0:0] + attribute \src "libresoc.v:189981.3-190000.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189901.17-189901.129" + wire $and$libresoc.v:189901$13134_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189862.7-189862.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_3_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:189901$13134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_3_wb__cyc + connect \B \sram4k_3_wb__stb + connect \Y $and$libresoc.v:189901$13134_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189904.21-189910.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:189862.7-189862.20" + process $proc$libresoc.v:189862$13145 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189879.7-189879.30" + process $proc$libresoc.v:189879$13146 + assign { } { } + assign $1\sram4k_3_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0] + end + attribute \src "libresoc.v:189902.3-189903.49" + process $proc$libresoc.v:189902$13135 + assign { } { } + assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next + sync posedge \clk + update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0] + end + attribute \src "libresoc.v:189911.3-189920.6" + process $proc$libresoc.v:189911$13136 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189912.5-189912.29" + switch \initial + attribute \src "libresoc.v:189912.9-189912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:189921.3-189935.6" + process $proc$libresoc.v:189921$13137 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_3_wb__ack$next[0:0]$13138 $2\sram4k_3_wb__ack$next[0:0]$13140 + attribute \src "libresoc.v:189922.5-189922.29" + switch \initial + attribute \src "libresoc.v:189922.9-189922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_3_wb__ack$next[0:0]$13139 \wb_active + case + assign $1\sram4k_3_wb__ack$next[0:0]$13139 \sram4k_3_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_3_wb__ack$next[0:0]$13140 1'0 + case + assign $2\sram4k_3_wb__ack$next[0:0]$13140 $1\sram4k_3_wb__ack$next[0:0]$13139 + end + sync always + update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13138 + end + attribute \src "libresoc.v:189936.3-189950.6" + process $proc$libresoc.v:189936$13141 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189937.5-189937.29" + switch \initial + attribute \src "libresoc.v:189937.9-189937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_3_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:189951.3-189965.6" + process $proc$libresoc.v:189951$13142 + assign { } { } + assign { } { } + assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:189952.5-189952.29" + switch \initial + attribute \src "libresoc.v:189952.9-189952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_3_wb__dat_r[63:0] $2\sram4k_3_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_3_wb__dat_r[63:0] \q + case + assign $2\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0] + end + attribute \src "libresoc.v:189966.3-189980.6" + process $proc$libresoc.v:189966$13143 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189967.5-189967.29" + switch \initial + attribute \src "libresoc.v:189967.9-189967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_3_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189981.3-190000.6" + process $proc$libresoc.v:189981$13144 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189982.5-189982.29" + switch \initial + attribute \src "libresoc.v:189982.9-189982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_3_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_3_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:189901$13134_Y +end +attribute \src "libresoc.v:190005.1-190063.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:180656.7-180656.20" + attribute \src "libresoc.v:190006.7-190006.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180701.3-180709.6" - wire width 4 $0\q_int$next[3:0]$13034 - attribute \src "libresoc.v:180699.3-180700.27" + attribute \src "libresoc.v:190051.3-190059.6" + wire width 4 $0\q_int$next[3:0]$13157 + attribute \src "libresoc.v:190049.3-190050.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:180701.3-180709.6" - wire width 4 $1\q_int$next[3:0]$13035 - attribute \src "libresoc.v:180678.13-180678.25" + attribute \src "libresoc.v:190051.3-190059.6" + wire width 4 $1\q_int$next[3:0]$13158 + attribute \src "libresoc.v:190028.13-190028.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:180691.17-180691.96" - wire width 4 $and$libresoc.v:180691$13024_Y - attribute \src "libresoc.v:180696.17-180696.96" - wire width 4 $and$libresoc.v:180696$13029_Y - attribute \src "libresoc.v:180693.18-180693.93" - wire width 4 $not$libresoc.v:180693$13026_Y - attribute \src "libresoc.v:180695.17-180695.92" - wire width 4 $not$libresoc.v:180695$13028_Y - attribute \src "libresoc.v:180698.17-180698.92" - wire width 4 $not$libresoc.v:180698$13031_Y - attribute \src "libresoc.v:180692.18-180692.98" - wire width 4 $or$libresoc.v:180692$13025_Y - attribute \src "libresoc.v:180694.18-180694.99" - wire width 4 $or$libresoc.v:180694$13027_Y - attribute \src "libresoc.v:180697.17-180697.97" - wire width 4 $or$libresoc.v:180697$13030_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190041.17-190041.96" + wire width 4 $and$libresoc.v:190041$13147_Y + attribute \src "libresoc.v:190046.17-190046.96" + wire width 4 $and$libresoc.v:190046$13152_Y + attribute \src "libresoc.v:190043.18-190043.93" + wire width 4 $not$libresoc.v:190043$13149_Y + attribute \src "libresoc.v:190045.17-190045.92" + wire width 4 $not$libresoc.v:190045$13151_Y + attribute \src "libresoc.v:190048.17-190048.92" + wire width 4 $not$libresoc.v:190048$13154_Y + attribute \src "libresoc.v:190042.18-190042.98" + wire width 4 $or$libresoc.v:190042$13148_Y + attribute \src "libresoc.v:190044.18-190044.99" + wire width 4 $or$libresoc.v:190044$13150_Y + attribute \src "libresoc.v:190047.17-190047.97" + wire width 4 $or$libresoc.v:190047$13153_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180656.7-180656.15" + attribute \src "libresoc.v:190006.7-190006.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:180691$13024 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190041$13147 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -380120,10 +396525,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180691$13024_Y + connect \Y $and$libresoc.v:190041$13147_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:180696$13029 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190046$13152 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -380131,34 +396536,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180696$13029_Y + connect \Y $and$libresoc.v:190046$13152_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:180693$13026 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190043$13149 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:180693$13026_Y + connect \Y $not$libresoc.v:190043$13149_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:180695$13028 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190045$13151 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:180695$13028_Y + connect \Y $not$libresoc.v:190045$13151_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:180698$13031 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190048$13154 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:180698$13031_Y + connect \Y $not$libresoc.v:190048$13154_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:180692$13025 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190042$13148 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -380166,10 +396571,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:180692$13025_Y + connect \Y $or$libresoc.v:190042$13148_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:180694$13027 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190044$13150 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -380177,10 +396582,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:180694$13027_Y + connect \Y $or$libresoc.v:190044$13150_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:180697$13030 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190047$13153 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -380188,39 +396593,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:180697$13030_Y + connect \Y $or$libresoc.v:190047$13153_Y end - attribute \src "libresoc.v:180656.7-180656.20" - process $proc$libresoc.v:180656$13036 + attribute \src "libresoc.v:190006.7-190006.20" + process $proc$libresoc.v:190006$13159 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180678.13-180678.25" - process $proc$libresoc.v:180678$13037 + attribute \src "libresoc.v:190028.13-190028.25" + process $proc$libresoc.v:190028$13160 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:180699.3-180700.27" - process $proc$libresoc.v:180699$13032 + attribute \src "libresoc.v:190049.3-190050.27" + process $proc$libresoc.v:190049$13155 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:180701.3-180709.6" - process $proc$libresoc.v:180701$13033 + attribute \src "libresoc.v:190051.3-190059.6" + process $proc$libresoc.v:190051$13156 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13034 $1\q_int$next[3:0]$13035 - attribute \src "libresoc.v:180702.5-180702.29" + assign $0\q_int$next[3:0]$13157 $1\q_int$next[3:0]$13158 + attribute \src "libresoc.v:190052.5-190052.29" switch \initial - attribute \src "libresoc.v:180702.9-180702.17" + attribute \src "libresoc.v:190052.9-190052.17" case 1'1 case end @@ -380229,94 +396634,94 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13035 4'0000 + assign $1\q_int$next[3:0]$13158 4'0000 case - assign $1\q_int$next[3:0]$13035 \$5 + assign $1\q_int$next[3:0]$13158 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13034 + update \q_int$next $0\q_int$next[3:0]$13157 end - connect \$9 $and$libresoc.v:180691$13024_Y - connect \$11 $or$libresoc.v:180692$13025_Y - connect \$13 $not$libresoc.v:180693$13026_Y - connect \$15 $or$libresoc.v:180694$13027_Y - connect \$1 $not$libresoc.v:180695$13028_Y - connect \$3 $and$libresoc.v:180696$13029_Y - connect \$5 $or$libresoc.v:180697$13030_Y - connect \$7 $not$libresoc.v:180698$13031_Y + connect \$9 $and$libresoc.v:190041$13147_Y + connect \$11 $or$libresoc.v:190042$13148_Y + connect \$13 $not$libresoc.v:190043$13149_Y + connect \$15 $or$libresoc.v:190044$13150_Y + connect \$1 $not$libresoc.v:190045$13151_Y + connect \$3 $and$libresoc.v:190046$13152_Y + connect \$5 $or$libresoc.v:190047$13153_Y + connect \$7 $not$libresoc.v:190048$13154_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:180717.1-180775.10" +attribute \src "libresoc.v:190067.1-190125.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:180718.7-180718.20" + attribute \src "libresoc.v:190068.7-190068.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180763.3-180771.6" - wire width 6 $0\q_int$next[5:0]$13048 - attribute \src "libresoc.v:180761.3-180762.27" + attribute \src "libresoc.v:190113.3-190121.6" + wire width 6 $0\q_int$next[5:0]$13171 + attribute \src "libresoc.v:190111.3-190112.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:180763.3-180771.6" - wire width 6 $1\q_int$next[5:0]$13049 - attribute \src "libresoc.v:180740.13-180740.26" + attribute \src "libresoc.v:190113.3-190121.6" + wire width 6 $1\q_int$next[5:0]$13172 + attribute \src "libresoc.v:190090.13-190090.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:180753.17-180753.96" - wire width 6 $and$libresoc.v:180753$13038_Y - attribute \src "libresoc.v:180758.17-180758.96" - wire width 6 $and$libresoc.v:180758$13043_Y - attribute \src "libresoc.v:180755.18-180755.93" - wire width 6 $not$libresoc.v:180755$13040_Y - attribute \src "libresoc.v:180757.17-180757.92" - wire width 6 $not$libresoc.v:180757$13042_Y - attribute \src "libresoc.v:180760.17-180760.92" - wire width 6 $not$libresoc.v:180760$13045_Y - attribute \src "libresoc.v:180754.18-180754.98" - wire width 6 $or$libresoc.v:180754$13039_Y - attribute \src "libresoc.v:180756.18-180756.99" - wire width 6 $or$libresoc.v:180756$13041_Y - attribute \src "libresoc.v:180759.17-180759.97" - wire width 6 $or$libresoc.v:180759$13044_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190103.17-190103.96" + wire width 6 $and$libresoc.v:190103$13161_Y + attribute \src "libresoc.v:190108.17-190108.96" + wire width 6 $and$libresoc.v:190108$13166_Y + attribute \src "libresoc.v:190105.18-190105.93" + wire width 6 $not$libresoc.v:190105$13163_Y + attribute \src "libresoc.v:190107.17-190107.92" + wire width 6 $not$libresoc.v:190107$13165_Y + attribute \src "libresoc.v:190110.17-190110.92" + wire width 6 $not$libresoc.v:190110$13168_Y + attribute \src "libresoc.v:190104.18-190104.98" + wire width 6 $or$libresoc.v:190104$13162_Y + attribute \src "libresoc.v:190106.18-190106.99" + wire width 6 $or$libresoc.v:190106$13164_Y + attribute \src "libresoc.v:190109.17-190109.97" + wire width 6 $or$libresoc.v:190109$13167_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180718.7-180718.15" + attribute \src "libresoc.v:190068.7-190068.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:180753$13038 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190103$13161 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380324,10 +396729,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180753$13038_Y + connect \Y $and$libresoc.v:190103$13161_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:180758$13043 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190108$13166 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380335,34 +396740,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180758$13043_Y + connect \Y $and$libresoc.v:190108$13166_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:180755$13040 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190105$13163 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:180755$13040_Y + connect \Y $not$libresoc.v:190105$13163_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:180757$13042 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190107$13165 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:180757$13042_Y + connect \Y $not$libresoc.v:190107$13165_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:180760$13045 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190110$13168 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:180760$13045_Y + connect \Y $not$libresoc.v:190110$13168_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:180754$13039 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190104$13162 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380370,10 +396775,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:180754$13039_Y + connect \Y $or$libresoc.v:190104$13162_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:180756$13041 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190106$13164 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380381,10 +396786,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:180756$13041_Y + connect \Y $or$libresoc.v:190106$13164_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:180759$13044 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190109$13167 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380392,39 +396797,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:180759$13044_Y + connect \Y $or$libresoc.v:190109$13167_Y end - attribute \src "libresoc.v:180718.7-180718.20" - process $proc$libresoc.v:180718$13050 + attribute \src "libresoc.v:190068.7-190068.20" + process $proc$libresoc.v:190068$13173 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180740.13-180740.26" - process $proc$libresoc.v:180740$13051 + attribute \src "libresoc.v:190090.13-190090.26" + process $proc$libresoc.v:190090$13174 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:180761.3-180762.27" - process $proc$libresoc.v:180761$13046 + attribute \src "libresoc.v:190111.3-190112.27" + process $proc$libresoc.v:190111$13169 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:180763.3-180771.6" - process $proc$libresoc.v:180763$13047 + attribute \src "libresoc.v:190113.3-190121.6" + process $proc$libresoc.v:190113$13170 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13048 $1\q_int$next[5:0]$13049 - attribute \src "libresoc.v:180764.5-180764.29" + assign $0\q_int$next[5:0]$13171 $1\q_int$next[5:0]$13172 + attribute \src "libresoc.v:190114.5-190114.29" switch \initial - attribute \src "libresoc.v:180764.9-180764.17" + attribute \src "libresoc.v:190114.9-190114.17" case 1'1 case end @@ -380433,94 +396838,94 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13049 6'000000 + assign $1\q_int$next[5:0]$13172 6'000000 case - assign $1\q_int$next[5:0]$13049 \$5 + assign $1\q_int$next[5:0]$13172 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13048 + update \q_int$next $0\q_int$next[5:0]$13171 end - connect \$9 $and$libresoc.v:180753$13038_Y - connect \$11 $or$libresoc.v:180754$13039_Y - connect \$13 $not$libresoc.v:180755$13040_Y - connect \$15 $or$libresoc.v:180756$13041_Y - connect \$1 $not$libresoc.v:180757$13042_Y - connect \$3 $and$libresoc.v:180758$13043_Y - connect \$5 $or$libresoc.v:180759$13044_Y - connect \$7 $not$libresoc.v:180760$13045_Y + connect \$9 $and$libresoc.v:190103$13161_Y + connect \$11 $or$libresoc.v:190104$13162_Y + connect \$13 $not$libresoc.v:190105$13163_Y + connect \$15 $or$libresoc.v:190106$13164_Y + connect \$1 $not$libresoc.v:190107$13165_Y + connect \$3 $and$libresoc.v:190108$13166_Y + connect \$5 $or$libresoc.v:190109$13167_Y + connect \$7 $not$libresoc.v:190110$13168_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:180779.1-180837.10" +attribute \src "libresoc.v:190129.1-190187.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:180780.7-180780.20" + attribute \src "libresoc.v:190130.7-190130.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180825.3-180833.6" - wire width 3 $0\q_int$next[2:0]$13062 - attribute \src "libresoc.v:180823.3-180824.27" + attribute \src "libresoc.v:190175.3-190183.6" + wire width 3 $0\q_int$next[2:0]$13185 + attribute \src "libresoc.v:190173.3-190174.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:180825.3-180833.6" - wire width 3 $1\q_int$next[2:0]$13063 - attribute \src "libresoc.v:180802.13-180802.25" + attribute \src "libresoc.v:190175.3-190183.6" + wire width 3 $1\q_int$next[2:0]$13186 + attribute \src "libresoc.v:190152.13-190152.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:180815.17-180815.96" - wire width 3 $and$libresoc.v:180815$13052_Y - attribute \src "libresoc.v:180820.17-180820.96" - wire width 3 $and$libresoc.v:180820$13057_Y - attribute \src "libresoc.v:180817.18-180817.93" - wire width 3 $not$libresoc.v:180817$13054_Y - attribute \src "libresoc.v:180819.17-180819.92" - wire width 3 $not$libresoc.v:180819$13056_Y - attribute \src "libresoc.v:180822.17-180822.92" - wire width 3 $not$libresoc.v:180822$13059_Y - attribute \src "libresoc.v:180816.18-180816.98" - wire width 3 $or$libresoc.v:180816$13053_Y - attribute \src "libresoc.v:180818.18-180818.99" - wire width 3 $or$libresoc.v:180818$13055_Y - attribute \src "libresoc.v:180821.17-180821.97" - wire width 3 $or$libresoc.v:180821$13058_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190165.17-190165.96" + wire width 3 $and$libresoc.v:190165$13175_Y + attribute \src "libresoc.v:190170.17-190170.96" + wire width 3 $and$libresoc.v:190170$13180_Y + attribute \src "libresoc.v:190167.18-190167.93" + wire width 3 $not$libresoc.v:190167$13177_Y + attribute \src "libresoc.v:190169.17-190169.92" + wire width 3 $not$libresoc.v:190169$13179_Y + attribute \src "libresoc.v:190172.17-190172.92" + wire width 3 $not$libresoc.v:190172$13182_Y + attribute \src "libresoc.v:190166.18-190166.98" + wire width 3 $or$libresoc.v:190166$13176_Y + attribute \src "libresoc.v:190168.18-190168.99" + wire width 3 $or$libresoc.v:190168$13178_Y + attribute \src "libresoc.v:190171.17-190171.97" + wire width 3 $or$libresoc.v:190171$13181_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180780.7-180780.15" + attribute \src "libresoc.v:190130.7-190130.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:180815$13052 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190165$13175 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380528,10 +396933,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180815$13052_Y + connect \Y $and$libresoc.v:190165$13175_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:180820$13057 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190170$13180 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380539,34 +396944,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180820$13057_Y + connect \Y $and$libresoc.v:190170$13180_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:180817$13054 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190167$13177 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:180817$13054_Y + connect \Y $not$libresoc.v:190167$13177_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:180819$13056 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190169$13179 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:180819$13056_Y + connect \Y $not$libresoc.v:190169$13179_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:180822$13059 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190172$13182 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:180822$13059_Y + connect \Y $not$libresoc.v:190172$13182_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:180816$13053 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190166$13176 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380574,10 +396979,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:180816$13053_Y + connect \Y $or$libresoc.v:190166$13176_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:180818$13055 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190168$13178 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380585,10 +396990,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:180818$13055_Y + connect \Y $or$libresoc.v:190168$13178_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:180821$13058 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190171$13181 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380596,39 +397001,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:180821$13058_Y + connect \Y $or$libresoc.v:190171$13181_Y end - attribute \src "libresoc.v:180780.7-180780.20" - process $proc$libresoc.v:180780$13064 + attribute \src "libresoc.v:190130.7-190130.20" + process $proc$libresoc.v:190130$13187 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180802.13-180802.25" - process $proc$libresoc.v:180802$13065 + attribute \src "libresoc.v:190152.13-190152.25" + process $proc$libresoc.v:190152$13188 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:180823.3-180824.27" - process $proc$libresoc.v:180823$13060 + attribute \src "libresoc.v:190173.3-190174.27" + process $proc$libresoc.v:190173$13183 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:180825.3-180833.6" - process $proc$libresoc.v:180825$13061 + attribute \src "libresoc.v:190175.3-190183.6" + process $proc$libresoc.v:190175$13184 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13062 $1\q_int$next[2:0]$13063 - attribute \src "libresoc.v:180826.5-180826.29" + assign $0\q_int$next[2:0]$13185 $1\q_int$next[2:0]$13186 + attribute \src "libresoc.v:190176.5-190176.29" switch \initial - attribute \src "libresoc.v:180826.9-180826.17" + attribute \src "libresoc.v:190176.9-190176.17" case 1'1 case end @@ -380637,94 +397042,94 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13063 3'000 + assign $1\q_int$next[2:0]$13186 3'000 case - assign $1\q_int$next[2:0]$13063 \$5 + assign $1\q_int$next[2:0]$13186 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13062 + update \q_int$next $0\q_int$next[2:0]$13185 end - connect \$9 $and$libresoc.v:180815$13052_Y - connect \$11 $or$libresoc.v:180816$13053_Y - connect \$13 $not$libresoc.v:180817$13054_Y - connect \$15 $or$libresoc.v:180818$13055_Y - connect \$1 $not$libresoc.v:180819$13056_Y - connect \$3 $and$libresoc.v:180820$13057_Y - connect \$5 $or$libresoc.v:180821$13058_Y - connect \$7 $not$libresoc.v:180822$13059_Y + connect \$9 $and$libresoc.v:190165$13175_Y + connect \$11 $or$libresoc.v:190166$13176_Y + connect \$13 $not$libresoc.v:190167$13177_Y + connect \$15 $or$libresoc.v:190168$13178_Y + connect \$1 $not$libresoc.v:190169$13179_Y + connect \$3 $and$libresoc.v:190170$13180_Y + connect \$5 $or$libresoc.v:190171$13181_Y + connect \$7 $not$libresoc.v:190172$13182_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:180841.1-180899.10" +attribute \src "libresoc.v:190191.1-190249.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:180842.7-180842.20" + attribute \src "libresoc.v:190192.7-190192.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180887.3-180895.6" - wire width 5 $0\q_int$next[4:0]$13076 - attribute \src "libresoc.v:180885.3-180886.27" + attribute \src "libresoc.v:190237.3-190245.6" + wire width 5 $0\q_int$next[4:0]$13199 + attribute \src "libresoc.v:190235.3-190236.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:180887.3-180895.6" - wire width 5 $1\q_int$next[4:0]$13077 - attribute \src "libresoc.v:180864.13-180864.26" + attribute \src "libresoc.v:190237.3-190245.6" + wire width 5 $1\q_int$next[4:0]$13200 + attribute \src "libresoc.v:190214.13-190214.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:180877.17-180877.96" - wire width 5 $and$libresoc.v:180877$13066_Y - attribute \src "libresoc.v:180882.17-180882.96" - wire width 5 $and$libresoc.v:180882$13071_Y - attribute \src "libresoc.v:180879.18-180879.93" - wire width 5 $not$libresoc.v:180879$13068_Y - attribute \src "libresoc.v:180881.17-180881.92" - wire width 5 $not$libresoc.v:180881$13070_Y - attribute \src "libresoc.v:180884.17-180884.92" - wire width 5 $not$libresoc.v:180884$13073_Y - attribute \src "libresoc.v:180878.18-180878.98" - wire width 5 $or$libresoc.v:180878$13067_Y - attribute \src "libresoc.v:180880.18-180880.99" - wire width 5 $or$libresoc.v:180880$13069_Y - attribute \src "libresoc.v:180883.17-180883.97" - wire width 5 $or$libresoc.v:180883$13072_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190227.17-190227.96" + wire width 5 $and$libresoc.v:190227$13189_Y + attribute \src "libresoc.v:190232.17-190232.96" + wire width 5 $and$libresoc.v:190232$13194_Y + attribute \src "libresoc.v:190229.18-190229.93" + wire width 5 $not$libresoc.v:190229$13191_Y + attribute \src "libresoc.v:190231.17-190231.92" + wire width 5 $not$libresoc.v:190231$13193_Y + attribute \src "libresoc.v:190234.17-190234.92" + wire width 5 $not$libresoc.v:190234$13196_Y + attribute \src "libresoc.v:190228.18-190228.98" + wire width 5 $or$libresoc.v:190228$13190_Y + attribute \src "libresoc.v:190230.18-190230.99" + wire width 5 $or$libresoc.v:190230$13192_Y + attribute \src "libresoc.v:190233.17-190233.97" + wire width 5 $or$libresoc.v:190233$13195_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180842.7-180842.15" + attribute \src "libresoc.v:190192.7-190192.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 5 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:180877$13066 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190227$13189 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -380732,10 +397137,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180877$13066_Y + connect \Y $and$libresoc.v:190227$13189_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:180882$13071 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190232$13194 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -380743,34 +397148,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180882$13071_Y + connect \Y $and$libresoc.v:190232$13194_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:180879$13068 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190229$13191 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:180879$13068_Y + connect \Y $not$libresoc.v:190229$13191_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:180881$13070 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190231$13193 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:180881$13070_Y + connect \Y $not$libresoc.v:190231$13193_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:180884$13073 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190234$13196 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:180884$13073_Y + connect \Y $not$libresoc.v:190234$13196_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:180878$13067 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190228$13190 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -380778,10 +397183,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:180878$13067_Y + connect \Y $or$libresoc.v:190228$13190_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:180880$13069 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190230$13192 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -380789,10 +397194,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:180880$13069_Y + connect \Y $or$libresoc.v:190230$13192_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:180883$13072 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190233$13195 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -380800,39 +397205,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:180883$13072_Y + connect \Y $or$libresoc.v:190233$13195_Y end - attribute \src "libresoc.v:180842.7-180842.20" - process $proc$libresoc.v:180842$13078 + attribute \src "libresoc.v:190192.7-190192.20" + process $proc$libresoc.v:190192$13201 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180864.13-180864.26" - process $proc$libresoc.v:180864$13079 + attribute \src "libresoc.v:190214.13-190214.26" + process $proc$libresoc.v:190214$13202 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:180885.3-180886.27" - process $proc$libresoc.v:180885$13074 + attribute \src "libresoc.v:190235.3-190236.27" + process $proc$libresoc.v:190235$13197 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:180887.3-180895.6" - process $proc$libresoc.v:180887$13075 + attribute \src "libresoc.v:190237.3-190245.6" + process $proc$libresoc.v:190237$13198 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13076 $1\q_int$next[4:0]$13077 - attribute \src "libresoc.v:180888.5-180888.29" + assign $0\q_int$next[4:0]$13199 $1\q_int$next[4:0]$13200 + attribute \src "libresoc.v:190238.5-190238.29" switch \initial - attribute \src "libresoc.v:180888.9-180888.17" + attribute \src "libresoc.v:190238.9-190238.17" case 1'1 case end @@ -380841,94 +397246,94 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$13077 5'00000 + assign $1\q_int$next[4:0]$13200 5'00000 case - assign $1\q_int$next[4:0]$13077 \$5 + assign $1\q_int$next[4:0]$13200 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$13076 + update \q_int$next $0\q_int$next[4:0]$13199 end - connect \$9 $and$libresoc.v:180877$13066_Y - connect \$11 $or$libresoc.v:180878$13067_Y - connect \$13 $not$libresoc.v:180879$13068_Y - connect \$15 $or$libresoc.v:180880$13069_Y - connect \$1 $not$libresoc.v:180881$13070_Y - connect \$3 $and$libresoc.v:180882$13071_Y - connect \$5 $or$libresoc.v:180883$13072_Y - connect \$7 $not$libresoc.v:180884$13073_Y + connect \$9 $and$libresoc.v:190227$13189_Y + connect \$11 $or$libresoc.v:190228$13190_Y + connect \$13 $not$libresoc.v:190229$13191_Y + connect \$15 $or$libresoc.v:190230$13192_Y + connect \$1 $not$libresoc.v:190231$13193_Y + connect \$3 $and$libresoc.v:190232$13194_Y + connect \$5 $or$libresoc.v:190233$13195_Y + connect \$7 $not$libresoc.v:190234$13196_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:180903.1-180961.10" +attribute \src "libresoc.v:190253.1-190311.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:180904.7-180904.20" + attribute \src "libresoc.v:190254.7-190254.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180949.3-180957.6" - wire width 3 $0\q_int$next[2:0]$13090 - attribute \src "libresoc.v:180947.3-180948.27" + attribute \src "libresoc.v:190299.3-190307.6" + wire width 3 $0\q_int$next[2:0]$13213 + attribute \src "libresoc.v:190297.3-190298.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:180949.3-180957.6" - wire width 3 $1\q_int$next[2:0]$13091 - attribute \src "libresoc.v:180926.13-180926.25" + attribute \src "libresoc.v:190299.3-190307.6" + wire width 3 $1\q_int$next[2:0]$13214 + attribute \src "libresoc.v:190276.13-190276.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:180939.17-180939.96" - wire width 3 $and$libresoc.v:180939$13080_Y - attribute \src "libresoc.v:180944.17-180944.96" - wire width 3 $and$libresoc.v:180944$13085_Y - attribute \src "libresoc.v:180941.18-180941.93" - wire width 3 $not$libresoc.v:180941$13082_Y - attribute \src "libresoc.v:180943.17-180943.92" - wire width 3 $not$libresoc.v:180943$13084_Y - attribute \src "libresoc.v:180946.17-180946.92" - wire width 3 $not$libresoc.v:180946$13087_Y - attribute \src "libresoc.v:180940.18-180940.98" - wire width 3 $or$libresoc.v:180940$13081_Y - attribute \src "libresoc.v:180942.18-180942.99" - wire width 3 $or$libresoc.v:180942$13083_Y - attribute \src "libresoc.v:180945.17-180945.97" - wire width 3 $or$libresoc.v:180945$13086_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190289.17-190289.96" + wire width 3 $and$libresoc.v:190289$13203_Y + attribute \src "libresoc.v:190294.17-190294.96" + wire width 3 $and$libresoc.v:190294$13208_Y + attribute \src "libresoc.v:190291.18-190291.93" + wire width 3 $not$libresoc.v:190291$13205_Y + attribute \src "libresoc.v:190293.17-190293.92" + wire width 3 $not$libresoc.v:190293$13207_Y + attribute \src "libresoc.v:190296.17-190296.92" + wire width 3 $not$libresoc.v:190296$13210_Y + attribute \src "libresoc.v:190290.18-190290.98" + wire width 3 $or$libresoc.v:190290$13204_Y + attribute \src "libresoc.v:190292.18-190292.99" + wire width 3 $or$libresoc.v:190292$13206_Y + attribute \src "libresoc.v:190295.17-190295.97" + wire width 3 $or$libresoc.v:190295$13209_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180904.7-180904.15" + attribute \src "libresoc.v:190254.7-190254.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:180939$13080 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190289$13203 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380936,10 +397341,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180939$13080_Y + connect \Y $and$libresoc.v:190289$13203_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:180944$13085 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190294$13208 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380947,34 +397352,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180944$13085_Y + connect \Y $and$libresoc.v:190294$13208_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:180941$13082 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190291$13205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:180941$13082_Y + connect \Y $not$libresoc.v:190291$13205_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:180943$13084 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190293$13207 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:180943$13084_Y + connect \Y $not$libresoc.v:190293$13207_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:180946$13087 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190296$13210 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:180946$13087_Y + connect \Y $not$libresoc.v:190296$13210_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:180940$13081 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190290$13204 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380982,10 +397387,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:180940$13081_Y + connect \Y $or$libresoc.v:190290$13204_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:180942$13083 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190292$13206 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -380993,10 +397398,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:180942$13083_Y + connect \Y $or$libresoc.v:190292$13206_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:180945$13086 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190295$13209 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381004,39 +397409,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:180945$13086_Y + connect \Y $or$libresoc.v:190295$13209_Y end - attribute \src "libresoc.v:180904.7-180904.20" - process $proc$libresoc.v:180904$13092 + attribute \src "libresoc.v:190254.7-190254.20" + process $proc$libresoc.v:190254$13215 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180926.13-180926.25" - process $proc$libresoc.v:180926$13093 + attribute \src "libresoc.v:190276.13-190276.25" + process $proc$libresoc.v:190276$13216 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:180947.3-180948.27" - process $proc$libresoc.v:180947$13088 + attribute \src "libresoc.v:190297.3-190298.27" + process $proc$libresoc.v:190297$13211 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:180949.3-180957.6" - process $proc$libresoc.v:180949$13089 + attribute \src "libresoc.v:190299.3-190307.6" + process $proc$libresoc.v:190299$13212 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13090 $1\q_int$next[2:0]$13091 - attribute \src "libresoc.v:180950.5-180950.29" + assign $0\q_int$next[2:0]$13213 $1\q_int$next[2:0]$13214 + attribute \src "libresoc.v:190300.5-190300.29" switch \initial - attribute \src "libresoc.v:180950.9-180950.17" + attribute \src "libresoc.v:190300.9-190300.17" case 1'1 case end @@ -381045,94 +397450,94 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13091 3'000 + assign $1\q_int$next[2:0]$13214 3'000 case - assign $1\q_int$next[2:0]$13091 \$5 + assign $1\q_int$next[2:0]$13214 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13090 + update \q_int$next $0\q_int$next[2:0]$13213 end - connect \$9 $and$libresoc.v:180939$13080_Y - connect \$11 $or$libresoc.v:180940$13081_Y - connect \$13 $not$libresoc.v:180941$13082_Y - connect \$15 $or$libresoc.v:180942$13083_Y - connect \$1 $not$libresoc.v:180943$13084_Y - connect \$3 $and$libresoc.v:180944$13085_Y - connect \$5 $or$libresoc.v:180945$13086_Y - connect \$7 $not$libresoc.v:180946$13087_Y + connect \$9 $and$libresoc.v:190289$13203_Y + connect \$11 $or$libresoc.v:190290$13204_Y + connect \$13 $not$libresoc.v:190291$13205_Y + connect \$15 $or$libresoc.v:190292$13206_Y + connect \$1 $not$libresoc.v:190293$13207_Y + connect \$3 $and$libresoc.v:190294$13208_Y + connect \$5 $or$libresoc.v:190295$13209_Y + connect \$7 $not$libresoc.v:190296$13210_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:180965.1-181023.10" +attribute \src "libresoc.v:190315.1-190373.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:180966.7-180966.20" + attribute \src "libresoc.v:190316.7-190316.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181011.3-181019.6" - wire width 3 $0\q_int$next[2:0]$13104 - attribute \src "libresoc.v:181009.3-181010.27" + attribute \src "libresoc.v:190361.3-190369.6" + wire width 3 $0\q_int$next[2:0]$13227 + attribute \src "libresoc.v:190359.3-190360.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181011.3-181019.6" - wire width 3 $1\q_int$next[2:0]$13105 - attribute \src "libresoc.v:180988.13-180988.25" + attribute \src "libresoc.v:190361.3-190369.6" + wire width 3 $1\q_int$next[2:0]$13228 + attribute \src "libresoc.v:190338.13-190338.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181001.17-181001.96" - wire width 3 $and$libresoc.v:181001$13094_Y - attribute \src "libresoc.v:181006.17-181006.96" - wire width 3 $and$libresoc.v:181006$13099_Y - attribute \src "libresoc.v:181003.18-181003.93" - wire width 3 $not$libresoc.v:181003$13096_Y - attribute \src "libresoc.v:181005.17-181005.92" - wire width 3 $not$libresoc.v:181005$13098_Y - attribute \src "libresoc.v:181008.17-181008.92" - wire width 3 $not$libresoc.v:181008$13101_Y - attribute \src "libresoc.v:181002.18-181002.98" - wire width 3 $or$libresoc.v:181002$13095_Y - attribute \src "libresoc.v:181004.18-181004.99" - wire width 3 $or$libresoc.v:181004$13097_Y - attribute \src "libresoc.v:181007.17-181007.97" - wire width 3 $or$libresoc.v:181007$13100_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190351.17-190351.96" + wire width 3 $and$libresoc.v:190351$13217_Y + attribute \src "libresoc.v:190356.17-190356.96" + wire width 3 $and$libresoc.v:190356$13222_Y + attribute \src "libresoc.v:190353.18-190353.93" + wire width 3 $not$libresoc.v:190353$13219_Y + attribute \src "libresoc.v:190355.17-190355.92" + wire width 3 $not$libresoc.v:190355$13221_Y + attribute \src "libresoc.v:190358.17-190358.92" + wire width 3 $not$libresoc.v:190358$13224_Y + attribute \src "libresoc.v:190352.18-190352.98" + wire width 3 $or$libresoc.v:190352$13218_Y + attribute \src "libresoc.v:190354.18-190354.99" + wire width 3 $or$libresoc.v:190354$13220_Y + attribute \src "libresoc.v:190357.17-190357.97" + wire width 3 $or$libresoc.v:190357$13223_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180966.7-180966.15" + attribute \src "libresoc.v:190316.7-190316.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181001$13094 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190351$13217 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381140,10 +397545,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181001$13094_Y + connect \Y $and$libresoc.v:190351$13217_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181006$13099 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190356$13222 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381151,34 +397556,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181006$13099_Y + connect \Y $and$libresoc.v:190356$13222_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181003$13096 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190353$13219 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:181003$13096_Y + connect \Y $not$libresoc.v:190353$13219_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181005$13098 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190355$13221 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:181005$13098_Y + connect \Y $not$libresoc.v:190355$13221_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181008$13101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190358$13224 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:181008$13101_Y + connect \Y $not$libresoc.v:190358$13224_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181002$13095 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190352$13218 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381186,10 +397591,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:181002$13095_Y + connect \Y $or$libresoc.v:190352$13218_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181004$13097 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190354$13220 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381197,10 +397602,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:181004$13097_Y + connect \Y $or$libresoc.v:190354$13220_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181007$13100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190357$13223 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381208,39 +397613,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:181007$13100_Y + connect \Y $or$libresoc.v:190357$13223_Y end - attribute \src "libresoc.v:180966.7-180966.20" - process $proc$libresoc.v:180966$13106 + attribute \src "libresoc.v:190316.7-190316.20" + process $proc$libresoc.v:190316$13229 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180988.13-180988.25" - process $proc$libresoc.v:180988$13107 + attribute \src "libresoc.v:190338.13-190338.25" + process $proc$libresoc.v:190338$13230 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181009.3-181010.27" - process $proc$libresoc.v:181009$13102 + attribute \src "libresoc.v:190359.3-190360.27" + process $proc$libresoc.v:190359$13225 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181011.3-181019.6" - process $proc$libresoc.v:181011$13103 + attribute \src "libresoc.v:190361.3-190369.6" + process $proc$libresoc.v:190361$13226 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13104 $1\q_int$next[2:0]$13105 - attribute \src "libresoc.v:181012.5-181012.29" + assign $0\q_int$next[2:0]$13227 $1\q_int$next[2:0]$13228 + attribute \src "libresoc.v:190362.5-190362.29" switch \initial - attribute \src "libresoc.v:181012.9-181012.17" + attribute \src "libresoc.v:190362.9-190362.17" case 1'1 case end @@ -381249,94 +397654,94 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13105 3'000 + assign $1\q_int$next[2:0]$13228 3'000 case - assign $1\q_int$next[2:0]$13105 \$5 + assign $1\q_int$next[2:0]$13228 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13104 + update \q_int$next $0\q_int$next[2:0]$13227 end - connect \$9 $and$libresoc.v:181001$13094_Y - connect \$11 $or$libresoc.v:181002$13095_Y - connect \$13 $not$libresoc.v:181003$13096_Y - connect \$15 $or$libresoc.v:181004$13097_Y - connect \$1 $not$libresoc.v:181005$13098_Y - connect \$3 $and$libresoc.v:181006$13099_Y - connect \$5 $or$libresoc.v:181007$13100_Y - connect \$7 $not$libresoc.v:181008$13101_Y + connect \$9 $and$libresoc.v:190351$13217_Y + connect \$11 $or$libresoc.v:190352$13218_Y + connect \$13 $not$libresoc.v:190353$13219_Y + connect \$15 $or$libresoc.v:190354$13220_Y + connect \$1 $not$libresoc.v:190355$13221_Y + connect \$3 $and$libresoc.v:190356$13222_Y + connect \$5 $or$libresoc.v:190357$13223_Y + connect \$7 $not$libresoc.v:190358$13224_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:181027.1-181085.10" +attribute \src "libresoc.v:190377.1-190435.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:181028.7-181028.20" + attribute \src "libresoc.v:190378.7-190378.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181073.3-181081.6" - wire width 4 $0\q_int$next[3:0]$13118 - attribute \src "libresoc.v:181071.3-181072.27" + attribute \src "libresoc.v:190423.3-190431.6" + wire width 4 $0\q_int$next[3:0]$13241 + attribute \src "libresoc.v:190421.3-190422.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:181073.3-181081.6" - wire width 4 $1\q_int$next[3:0]$13119 - attribute \src "libresoc.v:181050.13-181050.25" + attribute \src "libresoc.v:190423.3-190431.6" + wire width 4 $1\q_int$next[3:0]$13242 + attribute \src "libresoc.v:190400.13-190400.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:181063.17-181063.96" - wire width 4 $and$libresoc.v:181063$13108_Y - attribute \src "libresoc.v:181068.17-181068.96" - wire width 4 $and$libresoc.v:181068$13113_Y - attribute \src "libresoc.v:181065.18-181065.93" - wire width 4 $not$libresoc.v:181065$13110_Y - attribute \src "libresoc.v:181067.17-181067.92" - wire width 4 $not$libresoc.v:181067$13112_Y - attribute \src "libresoc.v:181070.17-181070.92" - wire width 4 $not$libresoc.v:181070$13115_Y - attribute \src "libresoc.v:181064.18-181064.98" - wire width 4 $or$libresoc.v:181064$13109_Y - attribute \src "libresoc.v:181066.18-181066.99" - wire width 4 $or$libresoc.v:181066$13111_Y - attribute \src "libresoc.v:181069.17-181069.97" - wire width 4 $or$libresoc.v:181069$13114_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190413.17-190413.96" + wire width 4 $and$libresoc.v:190413$13231_Y + attribute \src "libresoc.v:190418.17-190418.96" + wire width 4 $and$libresoc.v:190418$13236_Y + attribute \src "libresoc.v:190415.18-190415.93" + wire width 4 $not$libresoc.v:190415$13233_Y + attribute \src "libresoc.v:190417.17-190417.92" + wire width 4 $not$libresoc.v:190417$13235_Y + attribute \src "libresoc.v:190420.17-190420.92" + wire width 4 $not$libresoc.v:190420$13238_Y + attribute \src "libresoc.v:190414.18-190414.98" + wire width 4 $or$libresoc.v:190414$13232_Y + attribute \src "libresoc.v:190416.18-190416.99" + wire width 4 $or$libresoc.v:190416$13234_Y + attribute \src "libresoc.v:190419.17-190419.97" + wire width 4 $or$libresoc.v:190419$13237_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181028.7-181028.15" + attribute \src "libresoc.v:190378.7-190378.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181063$13108 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190413$13231 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -381344,10 +397749,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181063$13108_Y + connect \Y $and$libresoc.v:190413$13231_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181068$13113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190418$13236 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -381355,34 +397760,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181068$13113_Y + connect \Y $and$libresoc.v:190418$13236_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181065$13110 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190415$13233 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:181065$13110_Y + connect \Y $not$libresoc.v:190415$13233_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181067$13112 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190417$13235 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:181067$13112_Y + connect \Y $not$libresoc.v:190417$13235_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181070$13115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190420$13238 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:181070$13115_Y + connect \Y $not$libresoc.v:190420$13238_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181064$13109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190414$13232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -381390,10 +397795,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:181064$13109_Y + connect \Y $or$libresoc.v:190414$13232_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181066$13111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190416$13234 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -381401,10 +397806,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:181066$13111_Y + connect \Y $or$libresoc.v:190416$13234_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181069$13114 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190419$13237 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -381412,39 +397817,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:181069$13114_Y + connect \Y $or$libresoc.v:190419$13237_Y end - attribute \src "libresoc.v:181028.7-181028.20" - process $proc$libresoc.v:181028$13120 + attribute \src "libresoc.v:190378.7-190378.20" + process $proc$libresoc.v:190378$13243 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181050.13-181050.25" - process $proc$libresoc.v:181050$13121 + attribute \src "libresoc.v:190400.13-190400.25" + process $proc$libresoc.v:190400$13244 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:181071.3-181072.27" - process $proc$libresoc.v:181071$13116 + attribute \src "libresoc.v:190421.3-190422.27" + process $proc$libresoc.v:190421$13239 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:181073.3-181081.6" - process $proc$libresoc.v:181073$13117 + attribute \src "libresoc.v:190423.3-190431.6" + process $proc$libresoc.v:190423$13240 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13118 $1\q_int$next[3:0]$13119 - attribute \src "libresoc.v:181074.5-181074.29" + assign $0\q_int$next[3:0]$13241 $1\q_int$next[3:0]$13242 + attribute \src "libresoc.v:190424.5-190424.29" switch \initial - attribute \src "libresoc.v:181074.9-181074.17" + attribute \src "libresoc.v:190424.9-190424.17" case 1'1 case end @@ -381453,94 +397858,94 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13119 4'0000 + assign $1\q_int$next[3:0]$13242 4'0000 case - assign $1\q_int$next[3:0]$13119 \$5 + assign $1\q_int$next[3:0]$13242 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13118 + update \q_int$next $0\q_int$next[3:0]$13241 end - connect \$9 $and$libresoc.v:181063$13108_Y - connect \$11 $or$libresoc.v:181064$13109_Y - connect \$13 $not$libresoc.v:181065$13110_Y - connect \$15 $or$libresoc.v:181066$13111_Y - connect \$1 $not$libresoc.v:181067$13112_Y - connect \$3 $and$libresoc.v:181068$13113_Y - connect \$5 $or$libresoc.v:181069$13114_Y - connect \$7 $not$libresoc.v:181070$13115_Y + connect \$9 $and$libresoc.v:190413$13231_Y + connect \$11 $or$libresoc.v:190414$13232_Y + connect \$13 $not$libresoc.v:190415$13233_Y + connect \$15 $or$libresoc.v:190416$13234_Y + connect \$1 $not$libresoc.v:190417$13235_Y + connect \$3 $and$libresoc.v:190418$13236_Y + connect \$5 $or$libresoc.v:190419$13237_Y + connect \$7 $not$libresoc.v:190420$13238_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:181089.1-181147.10" +attribute \src "libresoc.v:190439.1-190497.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:181090.7-181090.20" + attribute \src "libresoc.v:190440.7-190440.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181135.3-181143.6" - wire width 3 $0\q_int$next[2:0]$13132 - attribute \src "libresoc.v:181133.3-181134.27" + attribute \src "libresoc.v:190485.3-190493.6" + wire width 3 $0\q_int$next[2:0]$13255 + attribute \src "libresoc.v:190483.3-190484.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181135.3-181143.6" - wire width 3 $1\q_int$next[2:0]$13133 - attribute \src "libresoc.v:181112.13-181112.25" + attribute \src "libresoc.v:190485.3-190493.6" + wire width 3 $1\q_int$next[2:0]$13256 + attribute \src "libresoc.v:190462.13-190462.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181125.17-181125.96" - wire width 3 $and$libresoc.v:181125$13122_Y - attribute \src "libresoc.v:181130.17-181130.96" - wire width 3 $and$libresoc.v:181130$13127_Y - attribute \src "libresoc.v:181127.18-181127.93" - wire width 3 $not$libresoc.v:181127$13124_Y - attribute \src "libresoc.v:181129.17-181129.92" - wire width 3 $not$libresoc.v:181129$13126_Y - attribute \src "libresoc.v:181132.17-181132.92" - wire width 3 $not$libresoc.v:181132$13129_Y - attribute \src "libresoc.v:181126.18-181126.98" - wire width 3 $or$libresoc.v:181126$13123_Y - attribute \src "libresoc.v:181128.18-181128.99" - wire width 3 $or$libresoc.v:181128$13125_Y - attribute \src "libresoc.v:181131.17-181131.97" - wire width 3 $or$libresoc.v:181131$13128_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190475.17-190475.96" + wire width 3 $and$libresoc.v:190475$13245_Y + attribute \src "libresoc.v:190480.17-190480.96" + wire width 3 $and$libresoc.v:190480$13250_Y + attribute \src "libresoc.v:190477.18-190477.93" + wire width 3 $not$libresoc.v:190477$13247_Y + attribute \src "libresoc.v:190479.17-190479.92" + wire width 3 $not$libresoc.v:190479$13249_Y + attribute \src "libresoc.v:190482.17-190482.92" + wire width 3 $not$libresoc.v:190482$13252_Y + attribute \src "libresoc.v:190476.18-190476.98" + wire width 3 $or$libresoc.v:190476$13246_Y + attribute \src "libresoc.v:190478.18-190478.99" + wire width 3 $or$libresoc.v:190478$13248_Y + attribute \src "libresoc.v:190481.17-190481.97" + wire width 3 $or$libresoc.v:190481$13251_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181090.7-181090.15" + attribute \src "libresoc.v:190440.7-190440.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181125$13122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190475$13245 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381548,10 +397953,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181125$13122_Y + connect \Y $and$libresoc.v:190475$13245_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181130$13127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190480$13250 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381559,34 +397964,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181130$13127_Y + connect \Y $and$libresoc.v:190480$13250_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181127$13124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190477$13247 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:181127$13124_Y + connect \Y $not$libresoc.v:190477$13247_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181129$13126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190479$13249 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:181129$13126_Y + connect \Y $not$libresoc.v:190479$13249_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181132$13129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190482$13252 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:181132$13129_Y + connect \Y $not$libresoc.v:190482$13252_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181126$13123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190476$13246 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381594,10 +397999,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:181126$13123_Y + connect \Y $or$libresoc.v:190476$13246_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181128$13125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190478$13248 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381605,10 +398010,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:181128$13125_Y + connect \Y $or$libresoc.v:190478$13248_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181131$13128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190481$13251 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381616,39 +398021,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:181131$13128_Y + connect \Y $or$libresoc.v:190481$13251_Y end - attribute \src "libresoc.v:181090.7-181090.20" - process $proc$libresoc.v:181090$13134 + attribute \src "libresoc.v:190440.7-190440.20" + process $proc$libresoc.v:190440$13257 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181112.13-181112.25" - process $proc$libresoc.v:181112$13135 + attribute \src "libresoc.v:190462.13-190462.25" + process $proc$libresoc.v:190462$13258 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181133.3-181134.27" - process $proc$libresoc.v:181133$13130 + attribute \src "libresoc.v:190483.3-190484.27" + process $proc$libresoc.v:190483$13253 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181135.3-181143.6" - process $proc$libresoc.v:181135$13131 + attribute \src "libresoc.v:190485.3-190493.6" + process $proc$libresoc.v:190485$13254 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13132 $1\q_int$next[2:0]$13133 - attribute \src "libresoc.v:181136.5-181136.29" + assign $0\q_int$next[2:0]$13255 $1\q_int$next[2:0]$13256 + attribute \src "libresoc.v:190486.5-190486.29" switch \initial - attribute \src "libresoc.v:181136.9-181136.17" + attribute \src "libresoc.v:190486.9-190486.17" case 1'1 case end @@ -381657,94 +398062,94 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13133 3'000 + assign $1\q_int$next[2:0]$13256 3'000 case - assign $1\q_int$next[2:0]$13133 \$5 + assign $1\q_int$next[2:0]$13256 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13132 + update \q_int$next $0\q_int$next[2:0]$13255 end - connect \$9 $and$libresoc.v:181125$13122_Y - connect \$11 $or$libresoc.v:181126$13123_Y - connect \$13 $not$libresoc.v:181127$13124_Y - connect \$15 $or$libresoc.v:181128$13125_Y - connect \$1 $not$libresoc.v:181129$13126_Y - connect \$3 $and$libresoc.v:181130$13127_Y - connect \$5 $or$libresoc.v:181131$13128_Y - connect \$7 $not$libresoc.v:181132$13129_Y + connect \$9 $and$libresoc.v:190475$13245_Y + connect \$11 $or$libresoc.v:190476$13246_Y + connect \$13 $not$libresoc.v:190477$13247_Y + connect \$15 $or$libresoc.v:190478$13248_Y + connect \$1 $not$libresoc.v:190479$13249_Y + connect \$3 $and$libresoc.v:190480$13250_Y + connect \$5 $or$libresoc.v:190481$13251_Y + connect \$7 $not$libresoc.v:190482$13252_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:181151.1-181209.10" +attribute \src "libresoc.v:190501.1-190559.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:181152.7-181152.20" + attribute \src "libresoc.v:190502.7-190502.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181197.3-181205.6" - wire width 6 $0\q_int$next[5:0]$13146 - attribute \src "libresoc.v:181195.3-181196.27" + attribute \src "libresoc.v:190547.3-190555.6" + wire width 6 $0\q_int$next[5:0]$13269 + attribute \src "libresoc.v:190545.3-190546.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:181197.3-181205.6" - wire width 6 $1\q_int$next[5:0]$13147 - attribute \src "libresoc.v:181174.13-181174.26" + attribute \src "libresoc.v:190547.3-190555.6" + wire width 6 $1\q_int$next[5:0]$13270 + attribute \src "libresoc.v:190524.13-190524.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:181187.17-181187.96" - wire width 6 $and$libresoc.v:181187$13136_Y - attribute \src "libresoc.v:181192.17-181192.96" - wire width 6 $and$libresoc.v:181192$13141_Y - attribute \src "libresoc.v:181189.18-181189.93" - wire width 6 $not$libresoc.v:181189$13138_Y - attribute \src "libresoc.v:181191.17-181191.92" - wire width 6 $not$libresoc.v:181191$13140_Y - attribute \src "libresoc.v:181194.17-181194.92" - wire width 6 $not$libresoc.v:181194$13143_Y - attribute \src "libresoc.v:181188.18-181188.98" - wire width 6 $or$libresoc.v:181188$13137_Y - attribute \src "libresoc.v:181190.18-181190.99" - wire width 6 $or$libresoc.v:181190$13139_Y - attribute \src "libresoc.v:181193.17-181193.97" - wire width 6 $or$libresoc.v:181193$13142_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190537.17-190537.96" + wire width 6 $and$libresoc.v:190537$13259_Y + attribute \src "libresoc.v:190542.17-190542.96" + wire width 6 $and$libresoc.v:190542$13264_Y + attribute \src "libresoc.v:190539.18-190539.93" + wire width 6 $not$libresoc.v:190539$13261_Y + attribute \src "libresoc.v:190541.17-190541.92" + wire width 6 $not$libresoc.v:190541$13263_Y + attribute \src "libresoc.v:190544.17-190544.92" + wire width 6 $not$libresoc.v:190544$13266_Y + attribute \src "libresoc.v:190538.18-190538.98" + wire width 6 $or$libresoc.v:190538$13260_Y + attribute \src "libresoc.v:190540.18-190540.99" + wire width 6 $or$libresoc.v:190540$13262_Y + attribute \src "libresoc.v:190543.17-190543.97" + wire width 6 $or$libresoc.v:190543$13265_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181152.7-181152.15" + attribute \src "libresoc.v:190502.7-190502.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181187$13136 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190537$13259 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -381752,10 +398157,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181187$13136_Y + connect \Y $and$libresoc.v:190537$13259_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181192$13141 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190542$13264 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -381763,34 +398168,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181192$13141_Y + connect \Y $and$libresoc.v:190542$13264_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181189$13138 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190539$13261 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:181189$13138_Y + connect \Y $not$libresoc.v:190539$13261_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181191$13140 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190541$13263 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:181191$13140_Y + connect \Y $not$libresoc.v:190541$13263_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181194$13143 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190544$13266 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:181194$13143_Y + connect \Y $not$libresoc.v:190544$13266_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181188$13137 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190538$13260 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -381798,10 +398203,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:181188$13137_Y + connect \Y $or$libresoc.v:190538$13260_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181190$13139 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190540$13262 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -381809,10 +398214,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:181190$13139_Y + connect \Y $or$libresoc.v:190540$13262_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181193$13142 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190543$13265 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -381820,39 +398225,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:181193$13142_Y + connect \Y $or$libresoc.v:190543$13265_Y end - attribute \src "libresoc.v:181152.7-181152.20" - process $proc$libresoc.v:181152$13148 + attribute \src "libresoc.v:190502.7-190502.20" + process $proc$libresoc.v:190502$13271 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181174.13-181174.26" - process $proc$libresoc.v:181174$13149 + attribute \src "libresoc.v:190524.13-190524.26" + process $proc$libresoc.v:190524$13272 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:181195.3-181196.27" - process $proc$libresoc.v:181195$13144 + attribute \src "libresoc.v:190545.3-190546.27" + process $proc$libresoc.v:190545$13267 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:181197.3-181205.6" - process $proc$libresoc.v:181197$13145 + attribute \src "libresoc.v:190547.3-190555.6" + process $proc$libresoc.v:190547$13268 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13146 $1\q_int$next[5:0]$13147 - attribute \src "libresoc.v:181198.5-181198.29" + assign $0\q_int$next[5:0]$13269 $1\q_int$next[5:0]$13270 + attribute \src "libresoc.v:190548.5-190548.29" switch \initial - attribute \src "libresoc.v:181198.9-181198.17" + attribute \src "libresoc.v:190548.9-190548.17" case 1'1 case end @@ -381861,94 +398266,94 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13147 6'000000 + assign $1\q_int$next[5:0]$13270 6'000000 case - assign $1\q_int$next[5:0]$13147 \$5 + assign $1\q_int$next[5:0]$13270 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13146 + update \q_int$next $0\q_int$next[5:0]$13269 end - connect \$9 $and$libresoc.v:181187$13136_Y - connect \$11 $or$libresoc.v:181188$13137_Y - connect \$13 $not$libresoc.v:181189$13138_Y - connect \$15 $or$libresoc.v:181190$13139_Y - connect \$1 $not$libresoc.v:181191$13140_Y - connect \$3 $and$libresoc.v:181192$13141_Y - connect \$5 $or$libresoc.v:181193$13142_Y - connect \$7 $not$libresoc.v:181194$13143_Y + connect \$9 $and$libresoc.v:190537$13259_Y + connect \$11 $or$libresoc.v:190538$13260_Y + connect \$13 $not$libresoc.v:190539$13261_Y + connect \$15 $or$libresoc.v:190540$13262_Y + connect \$1 $not$libresoc.v:190541$13263_Y + connect \$3 $and$libresoc.v:190542$13264_Y + connect \$5 $or$libresoc.v:190543$13265_Y + connect \$7 $not$libresoc.v:190544$13266_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:181213.1-181271.10" +attribute \src "libresoc.v:190563.1-190621.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:181214.7-181214.20" + attribute \src "libresoc.v:190564.7-190564.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181259.3-181267.6" - wire width 3 $0\q_int$next[2:0]$13160 - attribute \src "libresoc.v:181257.3-181258.27" + attribute \src "libresoc.v:190609.3-190617.6" + wire width 3 $0\q_int$next[2:0]$13283 + attribute \src "libresoc.v:190607.3-190608.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181259.3-181267.6" - wire width 3 $1\q_int$next[2:0]$13161 - attribute \src "libresoc.v:181236.13-181236.25" + attribute \src "libresoc.v:190609.3-190617.6" + wire width 3 $1\q_int$next[2:0]$13284 + attribute \src "libresoc.v:190586.13-190586.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181249.17-181249.96" - wire width 3 $and$libresoc.v:181249$13150_Y - attribute \src "libresoc.v:181254.17-181254.96" - wire width 3 $and$libresoc.v:181254$13155_Y - attribute \src "libresoc.v:181251.18-181251.93" - wire width 3 $not$libresoc.v:181251$13152_Y - attribute \src "libresoc.v:181253.17-181253.92" - wire width 3 $not$libresoc.v:181253$13154_Y - attribute \src "libresoc.v:181256.17-181256.92" - wire width 3 $not$libresoc.v:181256$13157_Y - attribute \src "libresoc.v:181250.18-181250.98" - wire width 3 $or$libresoc.v:181250$13151_Y - attribute \src "libresoc.v:181252.18-181252.99" - wire width 3 $or$libresoc.v:181252$13153_Y - attribute \src "libresoc.v:181255.17-181255.97" - wire width 3 $or$libresoc.v:181255$13156_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190599.17-190599.96" + wire width 3 $and$libresoc.v:190599$13273_Y + attribute \src "libresoc.v:190604.17-190604.96" + wire width 3 $and$libresoc.v:190604$13278_Y + attribute \src "libresoc.v:190601.18-190601.93" + wire width 3 $not$libresoc.v:190601$13275_Y + attribute \src "libresoc.v:190603.17-190603.92" + wire width 3 $not$libresoc.v:190603$13277_Y + attribute \src "libresoc.v:190606.17-190606.92" + wire width 3 $not$libresoc.v:190606$13280_Y + attribute \src "libresoc.v:190600.18-190600.98" + wire width 3 $or$libresoc.v:190600$13274_Y + attribute \src "libresoc.v:190602.18-190602.99" + wire width 3 $or$libresoc.v:190602$13276_Y + attribute \src "libresoc.v:190605.17-190605.97" + wire width 3 $or$libresoc.v:190605$13279_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181214.7-181214.15" + attribute \src "libresoc.v:190564.7-190564.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181249$13150 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190599$13273 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381956,10 +398361,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181249$13150_Y + connect \Y $and$libresoc.v:190599$13273_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181254$13155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190604$13278 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -381967,34 +398372,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181254$13155_Y + connect \Y $and$libresoc.v:190604$13278_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181251$13152 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190601$13275 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:181251$13152_Y + connect \Y $not$libresoc.v:190601$13275_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181253$13154 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190603$13277 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:181253$13154_Y + connect \Y $not$libresoc.v:190603$13277_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181256$13157 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190606$13280 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:181256$13157_Y + connect \Y $not$libresoc.v:190606$13280_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181250$13151 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190600$13274 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382002,10 +398407,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:181250$13151_Y + connect \Y $or$libresoc.v:190600$13274_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181252$13153 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190602$13276 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382013,10 +398418,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:181252$13153_Y + connect \Y $or$libresoc.v:190602$13276_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181255$13156 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190605$13279 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382024,39 +398429,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:181255$13156_Y + connect \Y $or$libresoc.v:190605$13279_Y end - attribute \src "libresoc.v:181214.7-181214.20" - process $proc$libresoc.v:181214$13162 + attribute \src "libresoc.v:190564.7-190564.20" + process $proc$libresoc.v:190564$13285 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181236.13-181236.25" - process $proc$libresoc.v:181236$13163 + attribute \src "libresoc.v:190586.13-190586.25" + process $proc$libresoc.v:190586$13286 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181257.3-181258.27" - process $proc$libresoc.v:181257$13158 + attribute \src "libresoc.v:190607.3-190608.27" + process $proc$libresoc.v:190607$13281 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181259.3-181267.6" - process $proc$libresoc.v:181259$13159 + attribute \src "libresoc.v:190609.3-190617.6" + process $proc$libresoc.v:190609$13282 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13160 $1\q_int$next[2:0]$13161 - attribute \src "libresoc.v:181260.5-181260.29" + assign $0\q_int$next[2:0]$13283 $1\q_int$next[2:0]$13284 + attribute \src "libresoc.v:190610.5-190610.29" switch \initial - attribute \src "libresoc.v:181260.9-181260.17" + attribute \src "libresoc.v:190610.9-190610.17" case 1'1 case end @@ -382065,94 +398470,94 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13161 3'000 + assign $1\q_int$next[2:0]$13284 3'000 case - assign $1\q_int$next[2:0]$13161 \$5 + assign $1\q_int$next[2:0]$13284 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13160 + update \q_int$next $0\q_int$next[2:0]$13283 end - connect \$9 $and$libresoc.v:181249$13150_Y - connect \$11 $or$libresoc.v:181250$13151_Y - connect \$13 $not$libresoc.v:181251$13152_Y - connect \$15 $or$libresoc.v:181252$13153_Y - connect \$1 $not$libresoc.v:181253$13154_Y - connect \$3 $and$libresoc.v:181254$13155_Y - connect \$5 $or$libresoc.v:181255$13156_Y - connect \$7 $not$libresoc.v:181256$13157_Y + connect \$9 $and$libresoc.v:190599$13273_Y + connect \$11 $or$libresoc.v:190600$13274_Y + connect \$13 $not$libresoc.v:190601$13275_Y + connect \$15 $or$libresoc.v:190602$13276_Y + connect \$1 $not$libresoc.v:190603$13277_Y + connect \$3 $and$libresoc.v:190604$13278_Y + connect \$5 $or$libresoc.v:190605$13279_Y + connect \$7 $not$libresoc.v:190606$13280_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:181275.1-181333.10" +attribute \src "libresoc.v:190625.1-190683.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:181276.7-181276.20" + attribute \src "libresoc.v:190626.7-190626.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181321.3-181329.6" - wire $0\q_int$next[0:0]$13174 - attribute \src "libresoc.v:181319.3-181320.27" + attribute \src "libresoc.v:190671.3-190679.6" + wire $0\q_int$next[0:0]$13297 + attribute \src "libresoc.v:190669.3-190670.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181321.3-181329.6" - wire $1\q_int$next[0:0]$13175 - attribute \src "libresoc.v:181298.7-181298.19" + attribute \src "libresoc.v:190671.3-190679.6" + wire $1\q_int$next[0:0]$13298 + attribute \src "libresoc.v:190648.7-190648.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181311.17-181311.96" - wire $and$libresoc.v:181311$13164_Y - attribute \src "libresoc.v:181316.17-181316.96" - wire $and$libresoc.v:181316$13169_Y - attribute \src "libresoc.v:181313.18-181313.99" - wire $not$libresoc.v:181313$13166_Y - attribute \src "libresoc.v:181315.17-181315.98" - wire $not$libresoc.v:181315$13168_Y - attribute \src "libresoc.v:181318.17-181318.98" - wire $not$libresoc.v:181318$13171_Y - attribute \src "libresoc.v:181312.18-181312.104" - wire $or$libresoc.v:181312$13165_Y - attribute \src "libresoc.v:181314.18-181314.105" - wire $or$libresoc.v:181314$13167_Y - attribute \src "libresoc.v:181317.17-181317.103" - wire $or$libresoc.v:181317$13170_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190661.17-190661.96" + wire $and$libresoc.v:190661$13287_Y + attribute \src "libresoc.v:190666.17-190666.96" + wire $and$libresoc.v:190666$13292_Y + attribute \src "libresoc.v:190663.18-190663.99" + wire $not$libresoc.v:190663$13289_Y + attribute \src "libresoc.v:190665.17-190665.98" + wire $not$libresoc.v:190665$13291_Y + attribute \src "libresoc.v:190668.17-190668.98" + wire $not$libresoc.v:190668$13294_Y + attribute \src "libresoc.v:190662.18-190662.104" + wire $or$libresoc.v:190662$13288_Y + attribute \src "libresoc.v:190664.18-190664.105" + wire $or$libresoc.v:190664$13290_Y + attribute \src "libresoc.v:190667.17-190667.103" + wire $or$libresoc.v:190667$13293_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181276.7-181276.15" + attribute \src "libresoc.v:190626.7-190626.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 2 \r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181311$13164 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190661$13287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382160,10 +398565,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181311$13164_Y + connect \Y $and$libresoc.v:190661$13287_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181316$13169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190666$13292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382171,34 +398576,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181316$13169_Y + connect \Y $and$libresoc.v:190666$13292_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181313$13166 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190663$13289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:181313$13166_Y + connect \Y $not$libresoc.v:190663$13289_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181315$13168 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190665$13291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:181315$13168_Y + connect \Y $not$libresoc.v:190665$13291_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181318$13171 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190668$13294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:181318$13171_Y + connect \Y $not$libresoc.v:190668$13294_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181312$13165 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190662$13288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382206,10 +398611,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:181312$13165_Y + connect \Y $or$libresoc.v:190662$13288_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181314$13167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190664$13290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382217,10 +398622,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:181314$13167_Y + connect \Y $or$libresoc.v:190664$13290_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181317$13170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190667$13293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382228,39 +398633,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:181317$13170_Y + connect \Y $or$libresoc.v:190667$13293_Y end - attribute \src "libresoc.v:181276.7-181276.20" - process $proc$libresoc.v:181276$13176 + attribute \src "libresoc.v:190626.7-190626.20" + process $proc$libresoc.v:190626$13299 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181298.7-181298.19" - process $proc$libresoc.v:181298$13177 + attribute \src "libresoc.v:190648.7-190648.19" + process $proc$libresoc.v:190648$13300 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181319.3-181320.27" - process $proc$libresoc.v:181319$13172 + attribute \src "libresoc.v:190669.3-190670.27" + process $proc$libresoc.v:190669$13295 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181321.3-181329.6" - process $proc$libresoc.v:181321$13173 + attribute \src "libresoc.v:190671.3-190679.6" + process $proc$libresoc.v:190671$13296 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13174 $1\q_int$next[0:0]$13175 - attribute \src "libresoc.v:181322.5-181322.29" + assign $0\q_int$next[0:0]$13297 $1\q_int$next[0:0]$13298 + attribute \src "libresoc.v:190672.5-190672.29" switch \initial - attribute \src "libresoc.v:181322.9-181322.17" + attribute \src "libresoc.v:190672.9-190672.17" case 1'1 case end @@ -382269,94 +398674,94 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13175 1'0 + assign $1\q_int$next[0:0]$13298 1'0 case - assign $1\q_int$next[0:0]$13175 \$5 + assign $1\q_int$next[0:0]$13298 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13174 + update \q_int$next $0\q_int$next[0:0]$13297 end - connect \$9 $and$libresoc.v:181311$13164_Y - connect \$11 $or$libresoc.v:181312$13165_Y - connect \$13 $not$libresoc.v:181313$13166_Y - connect \$15 $or$libresoc.v:181314$13167_Y - connect \$1 $not$libresoc.v:181315$13168_Y - connect \$3 $and$libresoc.v:181316$13169_Y - connect \$5 $or$libresoc.v:181317$13170_Y - connect \$7 $not$libresoc.v:181318$13171_Y + connect \$9 $and$libresoc.v:190661$13287_Y + connect \$11 $or$libresoc.v:190662$13288_Y + connect \$13 $not$libresoc.v:190663$13289_Y + connect \$15 $or$libresoc.v:190664$13290_Y + connect \$1 $not$libresoc.v:190665$13291_Y + connect \$3 $and$libresoc.v:190666$13292_Y + connect \$5 $or$libresoc.v:190667$13293_Y + connect \$7 $not$libresoc.v:190668$13294_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:181337.1-181395.10" +attribute \src "libresoc.v:190687.1-190745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:181338.7-181338.20" + attribute \src "libresoc.v:190688.7-190688.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181383.3-181391.6" - wire $0\q_int$next[0:0]$13188 - attribute \src "libresoc.v:181381.3-181382.27" + attribute \src "libresoc.v:190733.3-190741.6" + wire $0\q_int$next[0:0]$13311 + attribute \src "libresoc.v:190731.3-190732.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181383.3-181391.6" - wire $1\q_int$next[0:0]$13189 - attribute \src "libresoc.v:181360.7-181360.19" + attribute \src "libresoc.v:190733.3-190741.6" + wire $1\q_int$next[0:0]$13312 + attribute \src "libresoc.v:190710.7-190710.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181373.17-181373.96" - wire $and$libresoc.v:181373$13178_Y - attribute \src "libresoc.v:181378.17-181378.96" - wire $and$libresoc.v:181378$13183_Y - attribute \src "libresoc.v:181375.18-181375.97" - wire $not$libresoc.v:181375$13180_Y - attribute \src "libresoc.v:181377.17-181377.96" - wire $not$libresoc.v:181377$13182_Y - attribute \src "libresoc.v:181380.17-181380.96" - wire $not$libresoc.v:181380$13185_Y - attribute \src "libresoc.v:181374.18-181374.102" - wire $or$libresoc.v:181374$13179_Y - attribute \src "libresoc.v:181376.18-181376.103" - wire $or$libresoc.v:181376$13181_Y - attribute \src "libresoc.v:181379.17-181379.101" - wire $or$libresoc.v:181379$13184_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:190723.17-190723.96" + wire $and$libresoc.v:190723$13301_Y + attribute \src "libresoc.v:190728.17-190728.96" + wire $and$libresoc.v:190728$13306_Y + attribute \src "libresoc.v:190725.18-190725.97" + wire $not$libresoc.v:190725$13303_Y + attribute \src "libresoc.v:190727.17-190727.96" + wire $not$libresoc.v:190727$13305_Y + attribute \src "libresoc.v:190730.17-190730.96" + wire $not$libresoc.v:190730$13308_Y + attribute \src "libresoc.v:190724.18-190724.102" + wire $or$libresoc.v:190724$13302_Y + attribute \src "libresoc.v:190726.18-190726.103" + wire $or$libresoc.v:190726$13304_Y + attribute \src "libresoc.v:190729.17-190729.101" + wire $or$libresoc.v:190729$13307_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181338.7-181338.15" + attribute \src "libresoc.v:190688.7-190688.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181373$13178 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:190723$13301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382364,10 +398769,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181373$13178_Y + connect \Y $and$libresoc.v:190723$13301_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181378$13183 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190728$13306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382375,34 +398780,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181378$13183_Y + connect \Y $and$libresoc.v:190728$13306_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181375$13180 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190725$13303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:181375$13180_Y + connect \Y $not$libresoc.v:190725$13303_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181377$13182 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190727$13305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:181377$13182_Y + connect \Y $not$libresoc.v:190727$13305_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181380$13185 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190730$13308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:181380$13185_Y + connect \Y $not$libresoc.v:190730$13308_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181374$13179 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190724$13302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382410,10 +398815,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:181374$13179_Y + connect \Y $or$libresoc.v:190724$13302_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181376$13181 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190726$13304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382421,10 +398826,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:181376$13181_Y + connect \Y $or$libresoc.v:190726$13304_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181379$13184 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:190729$13307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382432,39 +398837,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:181379$13184_Y + connect \Y $or$libresoc.v:190729$13307_Y end - attribute \src "libresoc.v:181338.7-181338.20" - process $proc$libresoc.v:181338$13190 + attribute \src "libresoc.v:190688.7-190688.20" + process $proc$libresoc.v:190688$13313 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181360.7-181360.19" - process $proc$libresoc.v:181360$13191 + attribute \src "libresoc.v:190710.7-190710.19" + process $proc$libresoc.v:190710$13314 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181381.3-181382.27" - process $proc$libresoc.v:181381$13186 + attribute \src "libresoc.v:190731.3-190732.27" + process $proc$libresoc.v:190731$13309 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181383.3-181391.6" - process $proc$libresoc.v:181383$13187 + attribute \src "libresoc.v:190733.3-190741.6" + process $proc$libresoc.v:190733$13310 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13188 $1\q_int$next[0:0]$13189 - attribute \src "libresoc.v:181384.5-181384.29" + assign $0\q_int$next[0:0]$13311 $1\q_int$next[0:0]$13312 + attribute \src "libresoc.v:190734.5-190734.29" switch \initial - attribute \src "libresoc.v:181384.9-181384.17" + attribute \src "libresoc.v:190734.9-190734.17" case 1'1 case end @@ -382473,286 +398878,326 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13189 1'0 + assign $1\q_int$next[0:0]$13312 1'0 case - assign $1\q_int$next[0:0]$13189 \$5 + assign $1\q_int$next[0:0]$13312 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13188 + update \q_int$next $0\q_int$next[0:0]$13311 end - connect \$9 $and$libresoc.v:181373$13178_Y - connect \$11 $or$libresoc.v:181374$13179_Y - connect \$13 $not$libresoc.v:181375$13180_Y - connect \$15 $or$libresoc.v:181376$13181_Y - connect \$1 $not$libresoc.v:181377$13182_Y - connect \$3 $and$libresoc.v:181378$13183_Y - connect \$5 $or$libresoc.v:181379$13184_Y - connect \$7 $not$libresoc.v:181380$13185_Y + connect \$9 $and$libresoc.v:190723$13301_Y + connect \$11 $or$libresoc.v:190724$13302_Y + connect \$13 $not$libresoc.v:190725$13303_Y + connect \$15 $or$libresoc.v:190726$13304_Y + connect \$1 $not$libresoc.v:190727$13305_Y + connect \$3 $and$libresoc.v:190728$13306_Y + connect \$5 $or$libresoc.v:190729$13307_Y + connect \$7 $not$libresoc.v:190730$13308_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:181399.1-181654.10" +attribute \src "libresoc.v:190749.1-191045.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:181627.3-181636.6" + attribute \src "libresoc.v:190997.3-191006.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:181400.7-181400.20" + attribute \src "libresoc.v:190750.7-190750.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181608.3-181617.6" + attribute \src "libresoc.v:191016.3-191025.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:181599.3-181607.6" - wire width 4 $0\ren_delay$12$next[3:0]$13204 - attribute \src "libresoc.v:181539.3-181540.43" - wire width 4 $0\ren_delay$12[3:0]$13201 - attribute \src "libresoc.v:181520.13-181520.34" - wire width 4 $0\ren_delay$12[3:0]$13214 - attribute \src "libresoc.v:181618.3-181626.6" - wire width 4 $0\ren_delay$next[3:0]$13208 - attribute \src "libresoc.v:181541.3-181542.35" - wire width 4 $0\ren_delay[3:0] - attribute \src "libresoc.v:181627.3-181636.6" + attribute \src "libresoc.v:191007.3-191015.6" + wire width 3 $0\ren_delay$12$next[2:0]$13338 + attribute \src "libresoc.v:190911.3-190912.43" + wire width 3 $0\ren_delay$12[2:0]$13327 + attribute \src "libresoc.v:190878.13-190878.34" + wire width 3 $0\ren_delay$12[2:0]$13344 + attribute \src "libresoc.v:190969.3-190977.6" + wire width 3 $0\ren_delay$19$next[2:0]$13330 + attribute \src "libresoc.v:190909.3-190910.43" + wire width 3 $0\ren_delay$19[2:0]$13325 + attribute \src "libresoc.v:190882.13-190882.34" + wire width 3 $0\ren_delay$19[2:0]$13346 + attribute \src "libresoc.v:190988.3-190996.6" + wire width 3 $0\ren_delay$next[2:0]$13334 + attribute \src "libresoc.v:190913.3-190914.35" + wire width 3 $0\ren_delay[2:0] + attribute \src "libresoc.v:190978.3-190987.6" + wire width 64 $0\sv__data_o[63:0] + attribute \src "libresoc.v:190997.3-191006.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:181608.3-181617.6" + attribute \src "libresoc.v:191016.3-191025.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:181599.3-181607.6" - wire width 4 $1\ren_delay$12$next[3:0]$13205 - attribute \src "libresoc.v:181618.3-181626.6" - wire width 4 $1\ren_delay$next[3:0]$13209 - attribute \src "libresoc.v:181518.13-181518.29" - wire width 4 $1\ren_delay[3:0] - attribute \src "libresoc.v:181531.18-181531.95" - wire width 64 $or$libresoc.v:181531$13192_Y - attribute \src "libresoc.v:181533.18-181533.124" - wire width 64 $or$libresoc.v:181533$13194_Y - attribute \src "libresoc.v:181534.18-181534.124" - wire width 64 $or$libresoc.v:181534$13195_Y - attribute \src "libresoc.v:181535.18-181535.97" - wire width 64 $or$libresoc.v:181535$13196_Y - attribute \src "libresoc.v:181537.17-181537.123" - wire width 64 $or$libresoc.v:181537$13198_Y - attribute \src "libresoc.v:181538.17-181538.123" - wire width 64 $or$libresoc.v:181538$13199_Y - attribute \src "libresoc.v:181532.18-181532.100" - wire $reduce_or$libresoc.v:181532$13193_Y - attribute \src "libresoc.v:181536.17-181536.95" - wire $reduce_or$libresoc.v:181536$13197_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + attribute \src "libresoc.v:191007.3-191015.6" + wire width 3 $1\ren_delay$12$next[2:0]$13339 + attribute \src "libresoc.v:190969.3-190977.6" + wire width 3 $1\ren_delay$19$next[2:0]$13331 + attribute \src "libresoc.v:190988.3-190996.6" + wire width 3 $1\ren_delay$next[2:0]$13335 + attribute \src "libresoc.v:190876.13-190876.29" + wire width 3 $1\ren_delay[2:0] + attribute \src "libresoc.v:190978.3-190987.6" + wire width 64 $1\sv__data_o[63:0] + attribute \src "libresoc.v:190900.18-190900.109" + wire width 64 $or$libresoc.v:190900$13315_Y + attribute \src "libresoc.v:190902.18-190902.124" + wire width 64 $or$libresoc.v:190902$13317_Y + attribute \src "libresoc.v:190903.18-190903.110" + wire width 64 $or$libresoc.v:190903$13318_Y + attribute \src "libresoc.v:190905.18-190905.122" + wire width 64 $or$libresoc.v:190905$13320_Y + attribute \src "libresoc.v:190906.18-190906.109" + wire width 64 $or$libresoc.v:190906$13321_Y + attribute \src "libresoc.v:190908.17-190908.123" + wire width 64 $or$libresoc.v:190908$13323_Y + attribute \src "libresoc.v:190901.18-190901.100" + wire $reduce_or$libresoc.v:190901$13316_Y + attribute \src "libresoc.v:190904.18-190904.100" + wire $reduce_or$libresoc.v:190904$13319_Y + attribute \src "libresoc.v:190907.17-190907.95" + wire $reduce_or$libresoc.v:190907$13322_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 \$19 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 64 \$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 3 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 2 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 5 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \data_i$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 10 \data_i$2 - attribute \src "libresoc.v:181400.7-181400.15" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 7 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \data_i$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \data_i$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 14 \data_i$4 + attribute \src "libresoc.v:190750.7-190750.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 7 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 6 \msr__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 9 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 8 \msr__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_cia0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_d_wr10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_nia0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_sv0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_sv0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_sv0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_sv0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_cia1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_d_wr11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_nia1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_sv1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_sv1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_sv1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_sv1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_cia2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_cia2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_d_wr12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_d_wr12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_msr2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_msr2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_msr2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_msr2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_nia2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_nia2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_cia3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_cia3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_d_wr13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_d_wr13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_msr3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_msr3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_msr3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_msr3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_nia3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_nia3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_sv2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_sv2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_sv2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_sv2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay + wire width 3 \ren_delay$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$12 + wire width 3 \ren_delay$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$12$next + wire width 3 \ren_delay$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 8 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 4 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \wen$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:181531$13192 + wire width 3 \ren_delay$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 12 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \sv__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 4 \sv__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 6 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 10 \wen$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 15 \wen$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:190900$13315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$6 + connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:181531$13192_Y + connect \Y $or$libresoc.v:190900$13315_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:181533$13194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:190902$13317 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \reg_0_msr0__data_o - connect \B \reg_1_msr1__data_o - connect \Y $or$libresoc.v:181533$13194_Y + connect \A \reg_1_msr1__data_o + connect \B \reg_2_msr2__data_o + connect \Y $or$libresoc.v:190902$13317_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:181534$13195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:190903$13318 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \reg_2_msr2__data_o - connect \B \reg_3_msr3__data_o - connect \Y $or$libresoc.v:181534$13195_Y + connect \A \reg_0_msr0__data_o + connect \B \$15 + connect \Y $or$libresoc.v:190903$13318_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:181535$13196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:190905$13320 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$15 - connect \B \$17 - connect \Y $or$libresoc.v:181535$13196_Y + connect \A \reg_1_sv1__data_o + connect \B \reg_2_sv2__data_o + connect \Y $or$libresoc.v:190905$13320_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:181537$13198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:190906$13321 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \reg_0_cia0__data_o - connect \B \reg_1_cia1__data_o - connect \Y $or$libresoc.v:181537$13198_Y + connect \A \reg_0_sv0__data_o + connect \B \$22 + connect \Y $or$libresoc.v:190906$13321_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:181538$13199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:190908$13323 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \reg_2_cia2__data_o - connect \B \reg_3_cia3__data_o - connect \Y $or$libresoc.v:181538$13199_Y + connect \A \reg_1_cia1__data_o + connect \B \reg_2_cia2__data_o + connect \Y $or$libresoc.v:190908$13323_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:181532$13193 + cell $reduce_or $reduce_or$libresoc.v:190901$13316 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:181532$13193_Y + connect \Y $reduce_or$libresoc.v:190901$13316_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:181536$13197 + cell $reduce_or $reduce_or$libresoc.v:190904$13319 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$19 + connect \Y $reduce_or$libresoc.v:190904$13319_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:190907$13322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:181536$13197_Y + connect \Y $reduce_or$libresoc.v:190907$13322_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:181543.15-181556.4" + attribute \src "libresoc.v:190915.15-190932.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -382766,9 +399211,13 @@ module \state connect \msr0__wen \reg_0_msr0__wen connect \nia0__data_i \reg_0_nia0__data_i connect \nia0__wen \reg_0_nia0__wen + connect \sv0__data_i \reg_0_sv0__data_i + connect \sv0__data_o \reg_0_sv0__data_o + connect \sv0__ren \reg_0_sv0__ren + connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:181557.15-181570.4" + attribute \src "libresoc.v:190933.15-190950.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -382782,9 +399231,13 @@ module \state connect \msr1__wen \reg_1_msr1__wen connect \nia1__data_i \reg_1_nia1__data_i connect \nia1__wen \reg_1_nia1__wen + connect \sv1__data_i \reg_1_sv1__data_i + connect \sv1__data_o \reg_1_sv1__data_o + connect \sv1__ren \reg_1_sv1__ren + connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:181571.15-181584.4" + attribute \src "libresoc.v:190951.15-190968.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -382798,69 +399251,72 @@ module \state connect \msr2__wen \reg_2_msr2__wen connect \nia2__data_i \reg_2_nia2__data_i connect \nia2__wen \reg_2_nia2__wen + connect \sv2__data_i \reg_2_sv2__data_i + connect \sv2__data_o \reg_2_sv2__data_o + connect \sv2__ren \reg_2_sv2__ren + connect \sv2__wen \reg_2_sv2__wen end - attribute \module_not_derived 1 - attribute \src "libresoc.v:181585.15-181598.4" - cell \reg_3$138 \reg_3 - connect \cia3__data_o \reg_3_cia3__data_o - connect \cia3__ren \reg_3_cia3__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr13__data_i \reg_3_d_wr13__data_i - connect \d_wr13__wen \reg_3_d_wr13__wen - connect \msr3__data_i \reg_3_msr3__data_i - connect \msr3__data_o \reg_3_msr3__data_o - connect \msr3__ren \reg_3_msr3__ren - connect \msr3__wen \reg_3_msr3__wen - connect \nia3__data_i \reg_3_nia3__data_i - connect \nia3__wen \reg_3_nia3__wen - end - attribute \src "libresoc.v:181400.7-181400.20" - process $proc$libresoc.v:181400$13211 + attribute \src "libresoc.v:190750.7-190750.20" + process $proc$libresoc.v:190750$13341 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181518.13-181518.29" - process $proc$libresoc.v:181518$13212 + attribute \src "libresoc.v:190876.13-190876.29" + process $proc$libresoc.v:190876$13342 + assign { } { } + assign $1\ren_delay[2:0] 3'000 + sync always + sync init + update \ren_delay $1\ren_delay[2:0] + end + attribute \src "libresoc.v:190878.13-190878.34" + process $proc$libresoc.v:190878$13343 assign { } { } - assign $1\ren_delay[3:0] 4'0000 + assign $0\ren_delay$12[2:0]$13344 3'000 sync always sync init - update \ren_delay $1\ren_delay[3:0] + update \ren_delay$12 $0\ren_delay$12[2:0]$13344 end - attribute \src "libresoc.v:181520.13-181520.34" - process $proc$libresoc.v:181520$13213 + attribute \src "libresoc.v:190882.13-190882.34" + process $proc$libresoc.v:190882$13345 assign { } { } - assign $0\ren_delay$12[3:0]$13214 4'0000 + assign $0\ren_delay$19[2:0]$13346 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[3:0]$13214 + update \ren_delay$19 $0\ren_delay$19[2:0]$13346 end - attribute \src "libresoc.v:181539.3-181540.43" - process $proc$libresoc.v:181539$13200 + attribute \src "libresoc.v:190909.3-190910.43" + process $proc$libresoc.v:190909$13324 assign { } { } - assign $0\ren_delay$12[3:0]$13201 \ren_delay$12$next + assign $0\ren_delay$19[2:0]$13325 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[3:0]$13201 + update \ren_delay$19 $0\ren_delay$19[2:0]$13325 end - attribute \src "libresoc.v:181541.3-181542.35" - process $proc$libresoc.v:181541$13202 + attribute \src "libresoc.v:190911.3-190912.43" + process $proc$libresoc.v:190911$13326 assign { } { } - assign $0\ren_delay[3:0] \ren_delay$next + assign $0\ren_delay$12[2:0]$13327 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay $0\ren_delay[3:0] + update \ren_delay$12 $0\ren_delay$12[2:0]$13327 end - attribute \src "libresoc.v:181599.3-181607.6" - process $proc$libresoc.v:181599$13203 + attribute \src "libresoc.v:190913.3-190914.35" + process $proc$libresoc.v:190913$13328 assign { } { } + assign $0\ren_delay[2:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[2:0] + end + attribute \src "libresoc.v:190969.3-190977.6" + process $proc$libresoc.v:190969$13329 assign { } { } - assign $0\ren_delay$12$next[3:0]$13204 $1\ren_delay$12$next[3:0]$13205 - attribute \src "libresoc.v:181600.5-181600.29" + assign { } { } + assign $0\ren_delay$19$next[2:0]$13330 $1\ren_delay$19$next[2:0]$13331 + attribute \src "libresoc.v:190970.5-190970.29" switch \initial - attribute \src "libresoc.v:181600.9-181600.17" + attribute \src "libresoc.v:190970.9-190970.17" case 1'1 case end @@ -382869,44 +399325,44 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[3:0]$13205 4'0000 + assign $1\ren_delay$19$next[2:0]$13331 3'000 case - assign $1\ren_delay$12$next[3:0]$13205 \msr__ren + assign $1\ren_delay$19$next[2:0]$13331 \sv__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[3:0]$13204 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13330 end - attribute \src "libresoc.v:181608.3-181617.6" - process $proc$libresoc.v:181608$13206 + attribute \src "libresoc.v:190978.3-190987.6" + process $proc$libresoc.v:190978$13332 assign { } { } assign { } { } - assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:181609.5-181609.29" + assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] + attribute \src "libresoc.v:190979.5-190979.29" switch \initial - attribute \src "libresoc.v:181609.9-181609.17" + attribute \src "libresoc.v:190979.9-190979.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$13 + switch \$20 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\msr__data_o[63:0] \$19 + assign $1\sv__data_o[63:0] \$24 case - assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \msr__data_o $0\msr__data_o[63:0] + update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:181618.3-181626.6" - process $proc$libresoc.v:181618$13207 + attribute \src "libresoc.v:190988.3-190996.6" + process $proc$libresoc.v:190988$13333 assign { } { } assign { } { } - assign $0\ren_delay$next[3:0]$13208 $1\ren_delay$next[3:0]$13209 - attribute \src "libresoc.v:181619.5-181619.29" + assign $0\ren_delay$next[2:0]$13334 $1\ren_delay$next[2:0]$13335 + attribute \src "libresoc.v:190989.5-190989.29" switch \initial - attribute \src "libresoc.v:181619.9-181619.17" + attribute \src "libresoc.v:190989.9-190989.17" case 1'1 case end @@ -382915,26 +399371,26 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[3:0]$13209 4'0000 + assign $1\ren_delay$next[2:0]$13335 3'000 case - assign $1\ren_delay$next[3:0]$13209 \cia__ren + assign $1\ren_delay$next[2:0]$13335 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[3:0]$13208 + update \ren_delay$next $0\ren_delay$next[2:0]$13334 end - attribute \src "libresoc.v:181627.3-181636.6" - process $proc$libresoc.v:181627$13210 + attribute \src "libresoc.v:190997.3-191006.6" + process $proc$libresoc.v:190997$13336 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:181628.5-181628.29" + attribute \src "libresoc.v:190998.5-190998.29" switch \initial - attribute \src "libresoc.v:181628.9-181628.17" + attribute \src "libresoc.v:190998.9-190998.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$4 + switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -382945,101 +399401,150 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - connect \$10 $or$libresoc.v:181531$13192_Y - connect \$13 $reduce_or$libresoc.v:181532$13193_Y - connect \$15 $or$libresoc.v:181533$13194_Y - connect \$17 $or$libresoc.v:181534$13195_Y - connect \$19 $or$libresoc.v:181535$13196_Y - connect \$4 $reduce_or$libresoc.v:181536$13197_Y - connect \$6 $or$libresoc.v:181537$13198_Y - connect \$8 $or$libresoc.v:181538$13199_Y - connect \reg_3_d_wr13__data_i \data_i + attribute \src "libresoc.v:191007.3-191015.6" + process $proc$libresoc.v:191007$13337 + assign { } { } + assign { } { } + assign $0\ren_delay$12$next[2:0]$13338 $1\ren_delay$12$next[2:0]$13339 + attribute \src "libresoc.v:191008.5-191008.29" + switch \initial + attribute \src "libresoc.v:191008.9-191008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$12$next[2:0]$13339 3'000 + case + assign $1\ren_delay$12$next[2:0]$13339 \msr__ren + end + sync always + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13338 + end + attribute \src "libresoc.v:191016.3-191025.6" + process $proc$libresoc.v:191016$13340 + assign { } { } + assign { } { } + assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] + attribute \src "libresoc.v:191017.5-191017.29" + switch \initial + attribute \src "libresoc.v:191017.9-191017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\msr__data_o[63:0] \$17 + case + assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \msr__data_o $0\msr__data_o[63:0] + end + connect \$10 $or$libresoc.v:190900$13315_Y + connect \$13 $reduce_or$libresoc.v:190901$13316_Y + connect \$15 $or$libresoc.v:190902$13317_Y + connect \$17 $or$libresoc.v:190903$13318_Y + connect \$20 $reduce_or$libresoc.v:190904$13319_Y + connect \$22 $or$libresoc.v:190905$13320_Y + connect \$24 $or$libresoc.v:190906$13321_Y + connect \$6 $reduce_or$libresoc.v:190907$13322_Y + connect \$8 $or$libresoc.v:190908$13323_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i - connect { \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen - connect \reg_3_msr3__data_i \data_i$2 - connect \reg_2_msr2__data_i \data_i$2 - connect \reg_1_msr1__data_i \data_i$2 - connect \reg_0_msr0__data_i \data_i$2 - connect { \reg_3_msr3__wen \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 - connect \reg_3_nia3__data_i \data_i$1 - connect \reg_2_nia2__data_i \data_i$1 - connect \reg_1_nia1__data_i \data_i$1 - connect \reg_0_nia0__data_i \data_i$1 - connect { \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen - connect { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren - connect { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren + connect { \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + connect \reg_2_sv2__data_i \data_i$2 + connect \reg_1_sv1__data_i \data_i$2 + connect \reg_0_sv0__data_i \data_i$2 + connect { \reg_2_sv2__wen \reg_1_sv1__wen \reg_0_sv0__wen } \wen$1 + connect \reg_2_msr2__data_i \data_i$4 + connect \reg_1_msr1__data_i \data_i$4 + connect \reg_0_msr0__data_i \data_i$4 + connect { \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$5 + connect \reg_2_nia2__data_i \data_i$3 + connect \reg_1_nia1__data_i \data_i$3 + connect \reg_0_nia0__data_i \data_i$3 + connect { \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + connect { \reg_2_sv2__ren \reg_1_sv1__ren \reg_0_sv0__ren } \sv__ren + connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:181658.1-181716.10" +attribute \src "libresoc.v:191049.1-191107.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:181659.7-181659.20" + attribute \src "libresoc.v:191050.7-191050.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181704.3-181712.6" - wire $0\q_int$next[0:0]$13225 - attribute \src "libresoc.v:181702.3-181703.27" + attribute \src "libresoc.v:191095.3-191103.6" + wire $0\q_int$next[0:0]$13357 + attribute \src "libresoc.v:191093.3-191094.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181704.3-181712.6" - wire $1\q_int$next[0:0]$13226 - attribute \src "libresoc.v:181681.7-181681.19" + attribute \src "libresoc.v:191095.3-191103.6" + wire $1\q_int$next[0:0]$13358 + attribute \src "libresoc.v:191072.7-191072.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181694.17-181694.96" - wire $and$libresoc.v:181694$13215_Y - attribute \src "libresoc.v:181699.17-181699.96" - wire $and$libresoc.v:181699$13220_Y - attribute \src "libresoc.v:181696.18-181696.93" - wire $not$libresoc.v:181696$13217_Y - attribute \src "libresoc.v:181698.17-181698.92" - wire $not$libresoc.v:181698$13219_Y - attribute \src "libresoc.v:181701.17-181701.92" - wire $not$libresoc.v:181701$13222_Y - attribute \src "libresoc.v:181695.18-181695.98" - wire $or$libresoc.v:181695$13216_Y - attribute \src "libresoc.v:181697.18-181697.99" - wire $or$libresoc.v:181697$13218_Y - attribute \src "libresoc.v:181700.17-181700.97" - wire $or$libresoc.v:181700$13221_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:191085.17-191085.96" + wire $and$libresoc.v:191085$13347_Y + attribute \src "libresoc.v:191090.17-191090.96" + wire $and$libresoc.v:191090$13352_Y + attribute \src "libresoc.v:191087.18-191087.93" + wire $not$libresoc.v:191087$13349_Y + attribute \src "libresoc.v:191089.17-191089.92" + wire $not$libresoc.v:191089$13351_Y + attribute \src "libresoc.v:191092.17-191092.92" + wire $not$libresoc.v:191092$13354_Y + attribute \src "libresoc.v:191086.18-191086.98" + wire $or$libresoc.v:191086$13348_Y + attribute \src "libresoc.v:191088.18-191088.99" + wire $or$libresoc.v:191088$13350_Y + attribute \src "libresoc.v:191091.17-191091.97" + wire $or$libresoc.v:191091$13353_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181659.7-181659.15" + attribute \src "libresoc.v:191050.7-191050.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181694$13215 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:191085$13347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383047,10 +399552,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181694$13215_Y + connect \Y $and$libresoc.v:191085$13347_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181699$13220 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:191090$13352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383058,34 +399563,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181699$13220_Y + connect \Y $and$libresoc.v:191090$13352_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181696$13217 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:191087$13349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:181696$13217_Y + connect \Y $not$libresoc.v:191087$13349_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181698$13219 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:191089$13351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:181698$13219_Y + connect \Y $not$libresoc.v:191089$13351_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181701$13222 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:191092$13354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:181701$13222_Y + connect \Y $not$libresoc.v:191092$13354_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181695$13216 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:191086$13348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383093,10 +399598,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:181695$13216_Y + connect \Y $or$libresoc.v:191086$13348_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181697$13218 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:191088$13350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383104,10 +399609,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:181697$13218_Y + connect \Y $or$libresoc.v:191088$13350_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181700$13221 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:191091$13353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383115,39 +399620,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:181700$13221_Y + connect \Y $or$libresoc.v:191091$13353_Y end - attribute \src "libresoc.v:181659.7-181659.20" - process $proc$libresoc.v:181659$13227 + attribute \src "libresoc.v:191050.7-191050.20" + process $proc$libresoc.v:191050$13359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181681.7-181681.19" - process $proc$libresoc.v:181681$13228 + attribute \src "libresoc.v:191072.7-191072.19" + process $proc$libresoc.v:191072$13360 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181702.3-181703.27" - process $proc$libresoc.v:181702$13223 + attribute \src "libresoc.v:191093.3-191094.27" + process $proc$libresoc.v:191093$13355 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181704.3-181712.6" - process $proc$libresoc.v:181704$13224 + attribute \src "libresoc.v:191095.3-191103.6" + process $proc$libresoc.v:191095$13356 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13225 $1\q_int$next[0:0]$13226 - attribute \src "libresoc.v:181705.5-181705.29" + assign $0\q_int$next[0:0]$13357 $1\q_int$next[0:0]$13358 + attribute \src "libresoc.v:191096.5-191096.29" switch \initial - attribute \src "libresoc.v:181705.9-181705.17" + attribute \src "libresoc.v:191096.9-191096.17" case 1'1 case end @@ -383156,26 +399661,26 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13226 1'0 + assign $1\q_int$next[0:0]$13358 1'0 case - assign $1\q_int$next[0:0]$13226 \$5 + assign $1\q_int$next[0:0]$13358 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13225 + update \q_int$next $0\q_int$next[0:0]$13357 end - connect \$9 $and$libresoc.v:181694$13215_Y - connect \$11 $or$libresoc.v:181695$13216_Y - connect \$13 $not$libresoc.v:181696$13217_Y - connect \$15 $or$libresoc.v:181697$13218_Y - connect \$1 $not$libresoc.v:181698$13219_Y - connect \$3 $and$libresoc.v:181699$13220_Y - connect \$5 $or$libresoc.v:181700$13221_Y - connect \$7 $not$libresoc.v:181701$13222_Y + connect \$9 $and$libresoc.v:191085$13347_Y + connect \$11 $or$libresoc.v:191086$13348_Y + connect \$13 $not$libresoc.v:191087$13349_Y + connect \$15 $or$libresoc.v:191088$13350_Y + connect \$1 $not$libresoc.v:191089$13351_Y + connect \$3 $and$libresoc.v:191090$13352_Y + connect \$5 $or$libresoc.v:191091$13353_Y + connect \$7 $not$libresoc.v:191092$13354_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:181721.1-182854.10" +attribute \src "libresoc.v:191112.1-192349.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -383189,13 +399694,13 @@ module \test_issuer wire output 6 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133" wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 368 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 404 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 370 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" + wire width 2 input 406 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 344 \dbus__ack @@ -383446,43 +399951,43 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 334 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 355 \icp_wb__ack + wire output 391 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 349 \icp_wb__adr + wire width 28 input 385 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 353 \icp_wb__cyc + wire input 389 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 351 \icp_wb__dat_r + wire width 32 output 387 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 350 \icp_wb__dat_w + wire width 32 input 386 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 357 \icp_wb__err + wire input 393 \icp_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 352 \icp_wb__sel + wire width 4 input 388 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 354 \icp_wb__stb + wire input 390 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 356 \icp_wb__we + wire input 392 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 364 \ics_wb__ack + wire output 400 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 358 \ics_wb__adr + wire width 28 input 394 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 362 \ics_wb__cyc + wire input 398 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 360 \ics_wb__dat_r + wire width 32 output 396 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 359 \ics_wb__dat_w + wire width 32 input 395 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 366 \ics_wb__err + wire input 402 \ics_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 361 \ics_wb__sel + wire width 4 input 397 \ics_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 363 \ics_wb__stb + wire input 399 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 365 \ics_wb__we + wire input 401 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 367 \int_level_i + wire width 16 input 403 \int_level_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 17 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" @@ -383501,7 +400006,7 @@ module \test_issuer wire output 15 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:134" wire input 3 \memerr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \mspi0_clk__core__o @@ -383552,24 +400057,24 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 142 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 373 \pc_i + wire width 64 input 409 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129" wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:467" - wire output 371 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + wire output 407 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" wire \pll_clk_24_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" wire \pll_clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 372 \pll_lck_o + wire output 408 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire \pll_pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:810" wire \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:810" wire \pllclk_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 145 \pwm_0__core__o @@ -383579,8 +400084,8 @@ module \test_issuer wire input 147 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 369 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 405 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 155 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -383937,10 +400442,82 @@ module \test_issuer wire input 263 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 356 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 349 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 353 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 351 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 350 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 357 \sram4k_0_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 352 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 354 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 355 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 365 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 358 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 362 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 360 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 359 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 366 \sram4k_1_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 361 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 363 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 364 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 374 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 367 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 371 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 369 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 368 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 375 \sram4k_2_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 370 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 372 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 373 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 383 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 376 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 380 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 378 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 377 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 384 \sram4k_3_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 379 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 381 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 382 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:182480.7-182486.4" + attribute \src "libresoc.v:191943.7-191949.4" cell \pll \pll connect \clk_24_i \pll_clk_24_i connect \clk_pll_o \pll_clk_pll_o @@ -383949,7 +400526,7 @@ module \test_issuer connect \pll_lck_o \pll_lck_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:182487.6-182848.4" + attribute \src "libresoc.v:191950.6-192343.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -384311,6 +400888,38 @@ module \test_issuer connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o connect \sdr_we_n__core__o \sdr_we_n__core__o connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \sram4k_0_wb__ack \sram4k_0_wb__ack + connect \sram4k_0_wb__adr \sram4k_0_wb__adr + connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc + connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r + connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w + connect \sram4k_0_wb__sel \sram4k_0_wb__sel + connect \sram4k_0_wb__stb \sram4k_0_wb__stb + connect \sram4k_0_wb__we \sram4k_0_wb__we + connect \sram4k_1_wb__ack \sram4k_1_wb__ack + connect \sram4k_1_wb__adr \sram4k_1_wb__adr + connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc + connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r + connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w + connect \sram4k_1_wb__sel \sram4k_1_wb__sel + connect \sram4k_1_wb__stb \sram4k_1_wb__stb + connect \sram4k_1_wb__we \sram4k_1_wb__we + connect \sram4k_2_wb__ack \sram4k_2_wb__ack + connect \sram4k_2_wb__adr \sram4k_2_wb__adr + connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc + connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r + connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w + connect \sram4k_2_wb__sel \sram4k_2_wb__sel + connect \sram4k_2_wb__stb \sram4k_2_wb__stb + connect \sram4k_2_wb__we \sram4k_2_wb__we + connect \sram4k_3_wb__ack \sram4k_3_wb__ack + connect \sram4k_3_wb__adr \sram4k_3_wb__adr + connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc + connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r + connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w + connect \sram4k_3_wb__sel \sram4k_3_wb__sel + connect \sram4k_3_wb__stb \sram4k_3_wb__stb + connect \sram4k_3_wb__we \sram4k_3_wb__we end connect \ti_coresync_clk \pll_clk_pll_o connect \pllclk_rst \rst @@ -384318,1439 +400927,2047 @@ module \test_issuer connect \pll_clk_24_i \clk connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:182858.1-186736.10" +attribute \src "libresoc.v:192353.1-197545.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $0\core_asmcode$next[7:0]$13478 - attribute \src "libresoc.v:185009.3-185010.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $0\core_asmcode$next[7:0]$13857 + attribute \src "libresoc.v:194947.3-194948.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:186479.3-186515.6" - wire $0\core_bigendian_i$10$next[0:0]$13760 - attribute \src "libresoc.v:185005.3-185006.57" - wire $0\core_bigendian_i$10[0:0]$13295 - attribute \src "libresoc.v:183001.7-183001.35" - wire $0\core_bigendian_i$10[0:0]$13791 - attribute \src "libresoc.v:186177.3-186189.6" - wire width 4 $0\core_cia__ren[3:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 64 $0\core_core_core_cia$next[63:0]$13479 - attribute \src "libresoc.v:185085.3-185086.53" + attribute \src "libresoc.v:195854.3-195878.6" + wire $0\core_bigendian_i$10$next[0:0]$13655 + attribute \src "libresoc.v:195077.3-195078.57" + wire $0\core_bigendian_i$10[0:0]$13574 + attribute \src "libresoc.v:192630.7-192630.35" + wire $0\core_bigendian_i$10[0:0]$14064 + attribute \src "libresoc.v:196436.3-196448.6" + wire width 3 $0\core_cia__ren[2:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13858 + attribute \src "libresoc.v:195021.3-195022.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$13480 - attribute \src "libresoc.v:185129.3-185130.57" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13859 + attribute \src "libresoc.v:195065.3-195066.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$13481 - attribute \src "libresoc.v:185131.3-185132.63" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13860 + attribute \src "libresoc.v:195067.3-195068.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$13482 - attribute \src "libresoc.v:185133.3-185134.57" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13861 + attribute \src "libresoc.v:195069.3-195070.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$13483 - attribute \src "libresoc.v:185111.3-185112.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13353 - attribute \src "libresoc.v:183027.7-183027.44" - wire $0\core_core_core_exc_$signal$3[0:0]$13799 - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$13484 - attribute \src "libresoc.v:185113.3-185114.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13355 - attribute \src "libresoc.v:183031.7-183031.44" - wire $0\core_core_core_exc_$signal$4[0:0]$13801 - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$13485 - attribute \src "libresoc.v:185115.3-185116.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13357 - attribute \src "libresoc.v:183035.7-183035.44" - wire $0\core_core_core_exc_$signal$5[0:0]$13803 - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$13486 - attribute \src "libresoc.v:185117.3-185118.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13359 - attribute \src "libresoc.v:183039.7-183039.44" - wire $0\core_core_core_exc_$signal$6[0:0]$13805 - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$13487 - attribute \src "libresoc.v:185119.3-185120.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13361 - attribute \src "libresoc.v:183043.7-183043.44" - wire $0\core_core_core_exc_$signal$7[0:0]$13807 - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$13488 - attribute \src "libresoc.v:185121.3-185122.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13363 - attribute \src "libresoc.v:183047.7-183047.44" - wire $0\core_core_core_exc_$signal$8[0:0]$13809 - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$13489 - attribute \src "libresoc.v:185123.3-185124.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13365 - attribute \src "libresoc.v:183051.7-183051.44" - wire $0\core_core_core_exc_$signal$9[0:0]$13811 - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_exc_$signal$next[0:0]$13490 - attribute \src "libresoc.v:185109.3-185110.71" - wire $0\core_core_core_exc_$signal[0:0]$13351 - attribute \src "libresoc.v:183025.7-183025.42" - wire $0\core_core_core_exc_$signal[0:0]$13797 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 12 $0\core_core_core_fn_unit$next[11:0]$13491 - attribute \src "libresoc.v:185091.3-185092.61" - wire width 12 $0\core_core_core_fn_unit[11:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$13492 - attribute \src "libresoc.v:185105.3-185106.69" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13862 + attribute \src "libresoc.v:195047.3-195048.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13552 + attribute \src "libresoc.v:192656.7-192656.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14072 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13863 + attribute \src "libresoc.v:195049.3-195050.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13554 + attribute \src "libresoc.v:192660.7-192660.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14074 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13864 + attribute \src "libresoc.v:195051.3-195052.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13556 + attribute \src "libresoc.v:192664.7-192664.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14076 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13865 + attribute \src "libresoc.v:195053.3-195054.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13558 + attribute \src "libresoc.v:192668.7-192668.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14078 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13866 + attribute \src "libresoc.v:195057.3-195058.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13561 + attribute \src "libresoc.v:192672.7-192672.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14080 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13867 + attribute \src "libresoc.v:195059.3-195060.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13563 + attribute \src "libresoc.v:192676.7-192676.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14082 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13868 + attribute \src "libresoc.v:195061.3-195062.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13565 + attribute \src "libresoc.v:192680.7-192680.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14084 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13869 + attribute \src "libresoc.v:195045.3-195046.71" + wire $0\core_core_core_exc_$signal[0:0]$13550 + attribute \src "libresoc.v:192654.7-192654.42" + wire $0\core_core_core_exc_$signal[0:0]$14070 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$13870 + attribute \src "libresoc.v:195027.3-195028.61" + wire width 14 $0\core_core_core_fn_unit[13:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13871 + attribute \src "libresoc.v:195041.3-195042.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 32 $0\core_core_core_insn$next[31:0]$13493 - attribute \src "libresoc.v:185087.3-185088.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13872 + attribute \src "libresoc.v:195023.3-195024.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$13494 - attribute \src "libresoc.v:185089.3-185090.65" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13873 + attribute \src "libresoc.v:195025.3-195026.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_is_32bit$next[0:0]$13495 - attribute \src "libresoc.v:185137.3-185138.63" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_is_32bit$next[0:0]$13874 + attribute \src "libresoc.v:195073.3-195074.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 64 $0\core_core_core_msr$next[63:0]$13496 - attribute \src "libresoc.v:185083.3-185084.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13875 + attribute \src "libresoc.v:195019.3-195020.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_oe$next[0:0]$13497 - attribute \src "libresoc.v:185099.3-185100.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_oe$next[0:0]$13876 + attribute \src "libresoc.v:195037.3-195038.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_oe_ok$next[0:0]$13498 - attribute \src "libresoc.v:185101.3-185102.57" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_oe_ok$next[0:0]$13877 + attribute \src "libresoc.v:195039.3-195040.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_rc$next[0:0]$13499 - attribute \src "libresoc.v:185095.3-185096.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_rc$next[0:0]$13878 + attribute \src "libresoc.v:195031.3-195032.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_core_rc_ok$next[0:0]$13500 - attribute \src "libresoc.v:185097.3-185098.57" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_rc_ok$next[0:0]$13879 + attribute \src "libresoc.v:195035.3-195036.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$13501 - attribute \src "libresoc.v:185127.3-185128.63" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13880 + attribute \src "libresoc.v:195063.3-195064.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$13502 - attribute \src "libresoc.v:185107.3-185108.63" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$13881 + attribute \src "libresoc.v:195043.3-195044.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_cr_in1$next[2:0]$13503 - attribute \src "libresoc.v:185065.3-185066.49" - wire width 3 $0\core_core_cr_in1[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_cr_in1_ok$next[0:0]$13504 - attribute \src "libresoc.v:185067.3-185068.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$13882 + attribute \src "libresoc.v:195001.3-195002.49" + wire width 7 $0\core_core_cr_in1[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13883 + attribute \src "libresoc.v:195003.3-195004.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_cr_in2$1$next[2:0]$13505 - attribute \src "libresoc.v:185073.3-185074.55" - wire width 3 $0\core_core_cr_in2$1[2:0]$13331 - attribute \src "libresoc.v:183206.13-183206.40" - wire width 3 $0\core_core_cr_in2$1[2:0]$13828 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_cr_in2$next[2:0]$13506 - attribute \src "libresoc.v:185069.3-185070.49" - wire width 3 $0\core_core_cr_in2[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$13507 - attribute \src "libresoc.v:185075.3-185076.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13333 - attribute \src "libresoc.v:183214.7-183214.37" - wire $0\core_core_cr_in2_ok$2[0:0]$13831 - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_cr_in2_ok$next[0:0]$13508 - attribute \src "libresoc.v:185071.3-185072.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$13884 + attribute \src "libresoc.v:195009.3-195010.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13530 + attribute \src "libresoc.v:192838.13-192838.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14101 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$13885 + attribute \src "libresoc.v:195005.3-195006.49" + wire width 7 $0\core_core_cr_in2[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13886 + attribute \src "libresoc.v:195013.3-195014.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13533 + attribute \src "libresoc.v:192846.7-192846.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14104 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_cr_in2_ok$next[0:0]$13887 + attribute \src "libresoc.v:195007.3-195008.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_cr_out$next[2:0]$13509 - attribute \src "libresoc.v:185077.3-185078.49" - wire width 3 $0\core_core_cr_out[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_cr_wr_ok$next[0:0]$13510 - attribute \src "libresoc.v:185135.3-185136.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_cr_out$next[6:0]$13888 + attribute \src "libresoc.v:195015.3-195016.49" + wire width 7 $0\core_core_cr_out[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_cr_wr_ok$next[0:0]$13889 + attribute \src "libresoc.v:195071.3-195072.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $0\core_core_ea$next[4:0]$13511 - attribute \src "libresoc.v:185017.3-185018.41" - wire width 5 $0\core_core_ea[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_fast1$next[2:0]$13512 - attribute \src "libresoc.v:185047.3-185048.47" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $0\core_core_dststep$next[6:0]$13609 + attribute \src "libresoc.v:194937.3-194938.51" + wire width 7 $0\core_core_dststep[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_ea$next[6:0]$13890 + attribute \src "libresoc.v:194953.3-194954.41" + wire width 7 $0\core_core_ea[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_fast1$next[2:0]$13891 + attribute \src "libresoc.v:194983.3-194984.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_fast1_ok$next[0:0]$13513 - attribute \src "libresoc.v:185049.3-185050.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_fast1_ok$next[0:0]$13892 + attribute \src "libresoc.v:194985.3-194986.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_fast2$next[2:0]$13514 - attribute \src "libresoc.v:185051.3-185052.47" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_fast2$next[2:0]$13893 + attribute \src "libresoc.v:194987.3-194988.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_fast2_ok$next[0:0]$13515 - attribute \src "libresoc.v:185053.3-185054.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_fast2_ok$next[0:0]$13894 + attribute \src "libresoc.v:194991.3-194992.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_fasto1$next[2:0]$13516 - attribute \src "libresoc.v:185055.3-185056.49" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_fasto1$next[2:0]$13895 + attribute \src "libresoc.v:194993.3-194994.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_fasto2$next[2:0]$13517 - attribute \src "libresoc.v:185061.3-185062.49" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_fasto2$next[2:0]$13896 + attribute \src "libresoc.v:194997.3-194998.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_lk$next[0:0]$13518 - attribute \src "libresoc.v:185093.3-185094.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_lk$next[0:0]$13897 + attribute \src "libresoc.v:195029.3-195030.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $0\core_core_pc$next[63:0]$13399 - attribute \src "libresoc.v:185125.3-185126.41" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13610 + attribute \src "libresoc.v:194943.3-194944.47" + wire width 7 $0\core_core_maxvl[6:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $0\core_core_pc$next[63:0]$13611 + attribute \src "libresoc.v:194915.3-194916.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $0\core_core_reg1$next[4:0]$13519 - attribute \src "libresoc.v:185021.3-185022.45" - wire width 5 $0\core_core_reg1[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_reg1_ok$next[0:0]$13520 - attribute \src "libresoc.v:185023.3-185024.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_reg1$next[6:0]$13898 + attribute \src "libresoc.v:194957.3-194958.45" + wire width 7 $0\core_core_reg1[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_reg1_ok$next[0:0]$13899 + attribute \src "libresoc.v:194959.3-194960.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $0\core_core_reg2$next[4:0]$13521 - attribute \src "libresoc.v:185025.3-185026.45" - wire width 5 $0\core_core_reg2[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_reg2_ok$next[0:0]$13522 - attribute \src "libresoc.v:185027.3-185028.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_reg2$next[6:0]$13900 + attribute \src "libresoc.v:194961.3-194962.45" + wire width 7 $0\core_core_reg2[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_reg2_ok$next[0:0]$13901 + attribute \src "libresoc.v:194963.3-194964.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $0\core_core_reg3$next[4:0]$13523 - attribute \src "libresoc.v:185029.3-185030.45" - wire width 5 $0\core_core_reg3[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_reg3_ok$next[0:0]$13524 - attribute \src "libresoc.v:185031.3-185032.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_reg3$next[6:0]$13902 + attribute \src "libresoc.v:194965.3-194966.45" + wire width 7 $0\core_core_reg3[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_reg3_ok$next[0:0]$13903 + attribute \src "libresoc.v:194969.3-194970.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $0\core_core_rego$next[4:0]$13525 - attribute \src "libresoc.v:185011.3-185012.45" - wire width 5 $0\core_core_rego[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 10 $0\core_core_spr1$next[9:0]$13526 - attribute \src "libresoc.v:185039.3-185040.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_rego$next[6:0]$13904 + attribute \src "libresoc.v:194949.3-194950.45" + wire width 7 $0\core_core_rego[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $0\core_core_spr1$next[9:0]$13905 + attribute \src "libresoc.v:194975.3-194976.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_core_spr1_ok$next[0:0]$13527 - attribute \src "libresoc.v:185041.3-185042.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_spr1_ok$next[0:0]$13906 + attribute \src "libresoc.v:194977.3-194978.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 10 $0\core_core_spro$next[9:0]$13528 - attribute \src "libresoc.v:185033.3-185034.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $0\core_core_spro$next[9:0]$13907 + attribute \src "libresoc.v:194971.3-194972.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $0\core_core_xer_in$next[2:0]$13529 - attribute \src "libresoc.v:185043.3-185044.49" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13612 + attribute \src "libresoc.v:194939.3-194940.51" + wire width 7 $0\core_core_srcstep[6:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $0\core_core_subvl$next[1:0]$13613 + attribute \src "libresoc.v:194935.3-194936.47" + wire width 2 $0\core_core_subvl[1:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $0\core_core_svstep$next[1:0]$13614 + attribute \src "libresoc.v:194933.3-194934.49" + wire width 2 $0\core_core_svstep[1:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $0\core_core_vl$next[6:0]$13615 + attribute \src "libresoc.v:194941.3-194942.41" + wire width 7 $0\core_core_vl[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_xer_in$next[2:0]$13908 + attribute \src "libresoc.v:194979.3-194980.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_cr_out_ok$next[0:0]$13530 - attribute \src "libresoc.v:185079.3-185080.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_cr_out_ok$next[0:0]$13909 + attribute \src "libresoc.v:195017.3-195018.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:186211.3-186231.6" + attribute \src "libresoc.v:196021.3-196030.6" + wire width 64 $0\core_data_i$12[63:0]$13673 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $0\core_dec$next[63:0]$13400 - attribute \src "libresoc.v:184995.3-184996.33" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $0\core_dec$next[63:0]$13616 + attribute \src "libresoc.v:194931.3-194932.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:185875.3-185884.6" + attribute \src "libresoc.v:196134.3-196143.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:185885.3-185894.6" + attribute \src "libresoc.v:196144.3-196153.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_ea_ok$next[0:0]$13531 - attribute \src "libresoc.v:185019.3-185020.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_ea_ok$next[0:0]$13910 + attribute \src "libresoc.v:194955.3-194956.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire $0\core_eint$next[0:0]$13401 - attribute \src "libresoc.v:185163.3-185164.35" + attribute \src "libresoc.v:195788.3-195832.6" + wire $0\core_eint$next[0:0]$13617 + attribute \src "libresoc.v:194929.3-194930.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_fasto1_ok$next[0:0]$13532 - attribute \src "libresoc.v:185057.3-185058.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_fasto1_ok$next[0:0]$13911 + attribute \src "libresoc.v:194995.3-194996.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_fasto2_ok$next[0:0]$13533 - attribute \src "libresoc.v:185063.3-185064.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_fasto2_ok$next[0:0]$13912 + attribute \src "libresoc.v:194999.3-195000.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:185924.3-185933.6" + attribute \src "libresoc.v:196183.3-196192.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:185963.3-185972.6" + attribute \src "libresoc.v:196222.3-196231.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:186071.3-186085.6" - wire width 3 $0\core_issue__addr$11[2:0]$13449 - attribute \src "libresoc.v:186002.3-186016.6" + attribute \src "libresoc.v:196330.3-196344.6" + wire width 3 $0\core_issue__addr$13[2:0]$13713 + attribute \src "libresoc.v:196261.3-196275.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:186101.3-186115.6" + attribute \src "libresoc.v:196360.3-196374.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:186017.3-186031.6" + attribute \src "libresoc.v:196276.3-196290.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:186086.3-186100.6" + attribute \src "libresoc.v:196345.3-196359.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:185864.3-185874.6" + attribute \src "libresoc.v:196067.3-196082.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:185844.3-185863.6" + attribute \src "libresoc.v:196042.3-196066.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $0\core_msr$next[63:0]$13402 - attribute \src "libresoc.v:185147.3-185148.33" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $0\core_msr$next[63:0]$13618 + attribute \src "libresoc.v:194927.3-194928.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:186232.3-186247.6" - wire width 4 $0\core_msr__ren[3:0] - attribute \src "libresoc.v:186442.3-186478.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13754 - attribute \src "libresoc.v:185007.3-185008.47" + attribute \src "libresoc.v:196632.3-196647.6" + wire width 3 $0\core_msr__ren[2:0] + attribute \src "libresoc.v:195833.3-195853.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13650 + attribute \src "libresoc.v:195099.3-195100.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_rego_ok$next[0:0]$13534 - attribute \src "libresoc.v:185013.3-185014.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_rego_ok$next[0:0]$13913 + attribute \src "libresoc.v:194951.3-194952.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_spro_ok$next[0:0]$13535 - attribute \src "libresoc.v:185035.3-185036.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_spro_ok$next[0:0]$13914 + attribute \src "libresoc.v:194973.3-194974.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:186679.3-186697.6" + attribute \src "libresoc.v:197141.3-197171.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:186190.3-186210.6" - wire width 4 $0\core_wen[3:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $0\core_xer_out$next[0:0]$13536 - attribute \src "libresoc.v:185045.3-185046.41" + attribute \src "libresoc.v:196474.3-196486.6" + wire width 3 $0\core_sv__ren[2:0] + attribute \src "libresoc.v:195879.3-195903.6" + wire $0\core_sv_a_nz$next[0:0]$13660 + attribute \src "libresoc.v:195055.3-195056.41" + wire $0\core_sv_a_nz[0:0] + attribute \src "libresoc.v:196011.3-196020.6" + wire width 3 $0\core_wen$11[2:0]$13670 + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $0\core_wen[2:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_xer_out$next[0:0]$13915 + attribute \src "libresoc.v:194981.3-194982.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:185143.3-185144.43" + attribute \src "libresoc.v:195113.3-195114.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:185934.3-185942.6" - wire $0\d_cr_delay$next[0:0]$13431 - attribute \src "libresoc.v:185059.3-185060.37" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13754 + attribute \src "libresoc.v:195097.3-195098.47" + wire width 7 $0\cur_cur_dststep[6:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13755 + attribute \src "libresoc.v:195105.3-195106.43" + wire width 7 $0\cur_cur_maxvl[6:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13756 + attribute \src "libresoc.v:195101.3-195102.47" + wire width 7 $0\cur_cur_srcstep[6:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13757 + attribute \src "libresoc.v:195095.3-195096.43" + wire width 2 $0\cur_cur_subvl[1:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13758 + attribute \src "libresoc.v:195093.3-195094.45" + wire width 2 $0\cur_cur_svstep[1:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13759 + attribute \src "libresoc.v:195103.3-195104.37" + wire width 7 $0\cur_cur_vl[6:0] + attribute \src "libresoc.v:196193.3-196201.6" + wire $0\d_cr_delay$next[0:0]$13695 + attribute \src "libresoc.v:194989.3-194990.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:185895.3-185903.6" - wire $0\d_reg_delay$next[0:0]$13425 - attribute \src "libresoc.v:185081.3-185082.39" + attribute \src "libresoc.v:196154.3-196162.6" + wire $0\d_reg_delay$next[0:0]$13689 + attribute \src "libresoc.v:195011.3-195012.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:185973.3-185981.6" - wire $0\d_xer_delay$next[0:0]$13437 - attribute \src "libresoc.v:185037.3-185038.39" + attribute \src "libresoc.v:196232.3-196240.6" + wire $0\d_xer_delay$next[0:0]$13701 + attribute \src "libresoc.v:194967.3-194968.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:186698.3-186716.6" + attribute \src "libresoc.v:197172.3-197202.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:185953.3-185962.6" + attribute \src "libresoc.v:196212.3-196221.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:185943.3-185952.6" + attribute \src "libresoc.v:196202.3-196211.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:185914.3-185923.6" + attribute \src "libresoc.v:196173.3-196182.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:185904.3-185913.6" + attribute \src "libresoc.v:196163.3-196172.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:185992.3-186001.6" + attribute \src "libresoc.v:196251.3-196260.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:185982.3-185991.6" + attribute \src "libresoc.v:196241.3-196250.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:185730.3-185738.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13387 - attribute \src "libresoc.v:185161.3-185162.45" + attribute \src "libresoc.v:195751.3-195759.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13597 + attribute \src "libresoc.v:194925.3-194926.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:186248.3-186256.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13470 - attribute \src "libresoc.v:185155.3-185156.39" + attribute \src "libresoc.v:196487.3-196495.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13736 + attribute \src "libresoc.v:194919.3-194920.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:185739.3-185747.6" - wire $0\dbg_dmi_req_i$next[0:0]$13390 - attribute \src "libresoc.v:185159.3-185160.43" + attribute \src "libresoc.v:195760.3-195768.6" + wire $0\dbg_dmi_req_i$next[0:0]$13600 + attribute \src "libresoc.v:194923.3-194924.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:186143.3-186151.6" - wire $0\dbg_dmi_we_i$next[0:0]$13459 - attribute \src "libresoc.v:185157.3-185158.41" + attribute \src "libresoc.v:196402.3-196410.6" + wire $0\dbg_dmi_we_i$next[0:0]$13723 + attribute \src "libresoc.v:194921.3-194922.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:186116.3-186131.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13454 - attribute \src "libresoc.v:184993.3-184994.41" + attribute \src "libresoc.v:196375.3-196390.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13718 + attribute \src "libresoc.v:194913.3-194914.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:186423.3-186431.6" - wire $0\dec2_cur_eint$next[0:0]$13748 - attribute \src "libresoc.v:185149.3-185150.43" + attribute \src "libresoc.v:195769.3-195777.6" + wire $0\dec2_cur_eint$next[0:0]$13603 + attribute \src "libresoc.v:195117.3-195118.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:185748.3-185768.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13393 - attribute \src "libresoc.v:184997.3-184998.41" + attribute \src "libresoc.v:196905.3-196925.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13802 + attribute \src "libresoc.v:195087.3-195088.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:186582.3-186602.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13769 - attribute \src "libresoc.v:185003.3-185004.39" + attribute \src "libresoc.v:196752.3-196772.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13749 + attribute \src "libresoc.v:195107.3-195108.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:185769.3-185787.6" + attribute \src "libresoc.v:196945.3-196975.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13811 + attribute \src "libresoc.v:195083.3-195084.53" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:186432.3-186441.6" - wire width 2 $0\delay$next[1:0]$13751 - attribute \src "libresoc.v:185145.3-185146.27" + attribute \src "libresoc.v:195778.3-195787.6" + wire width 2 $0\delay$next[1:0]$13606 + attribute \src "libresoc.v:195115.3-195116.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:186032.3-186059.6" - wire width 2 $0\fsm_state$133$next[1:0]$13444 - attribute \src "libresoc.v:185015.3-185016.45" - wire width 2 $0\fsm_state$133[1:0]$13301 - attribute \src "libresoc.v:184191.13-184191.35" - wire width 2 $0\fsm_state$133[1:0]$13880 - attribute \src "libresoc.v:186633.3-186678.6" - wire width 2 $0\fsm_state$next[1:0]$13780 - attribute \src "libresoc.v:184999.3-185000.35" + attribute \src "libresoc.v:196083.3-196117.6" + wire $0\exec_fsm_state$next[0:0]$13679 + attribute \src "libresoc.v:195033.3-195034.45" + wire $0\exec_fsm_state[0:0] + attribute \src "libresoc.v:196031.3-196041.6" + wire $0\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:195942.3-195952.6" + wire $0\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:195953.3-195968.6" + wire $0\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:196118.3-196133.6" + wire $0\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13794 + attribute \src "libresoc.v:195089.3-195090.47" + wire width 2 $0\fetch_fsm_state[1:0] + attribute \src "libresoc.v:197394.3-197404.6" + wire $0\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:196976.3-196986.6" + wire $0\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:196657.3-196667.6" + wire $0\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:197044.3-197059.6" + wire $0\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:196291.3-196318.6" + wire width 2 $0\fsm_state$next[1:0]$13708 + attribute \src "libresoc.v:194945.3-194946.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:185820.3-185843.6" - wire width 32 $0\ilatch$next[31:0]$13416 - attribute \src "libresoc.v:185103.3-185104.29" - wire width 32 $0\ilatch[31:0] - attribute \src "libresoc.v:186516.3-186531.6" + attribute \src "libresoc.v:196668.3-196683.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:186532.3-186556.6" + attribute \src "libresoc.v:196684.3-196717.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186557.3-186581.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:182859.7-182859.20" + attribute \src "libresoc.v:192354.7-192354.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186405.3-186413.6" + attribute \src "libresoc.v:195904.3-195941.6" + wire $0\insn_done[0:0] + attribute \src "libresoc.v:195990.3-196010.6" + wire $0\is_last[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $0\issue_fsm_state$next[2:0]$13819 + attribute \src "libresoc.v:195081.3-195082.47" + wire width 3 $0\issue_fsm_state[2:0] + attribute \src "libresoc.v:196648.3-196656.6" wire $0\jtag_dmi0__ack_o$next[0:0]$13742 - attribute \src "libresoc.v:185153.3-185154.49" + attribute \src "libresoc.v:194917.3-194918.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:186414.3-186422.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13745 - attribute \src "libresoc.v:185151.3-185152.47" + attribute \src "libresoc.v:196812.3-196820.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13785 + attribute \src "libresoc.v:195119.3-195120.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:186603.3-186632.6" - wire $0\msr_read$next[0:0]$13774 - attribute \src "libresoc.v:185001.3-185002.33" + attribute \src "libresoc.v:196821.3-196850.6" + wire $0\msr_read$next[0:0]$13788 + attribute \src "libresoc.v:195091.3-195092.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:186060.3-186070.6" + attribute \src "libresoc.v:196319.3-196329.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:186132.3-186142.6" + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $0\new_svstate_dststep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $0\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $0\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $0\new_svstate_subvl[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $0\new_svstate_svstep[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $0\new_svstate_vl[6:0] + attribute \src "libresoc.v:196391.3-196401.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:186161.3-186176.6" + attribute \src "libresoc.v:195969.3-195989.6" + wire width 7 $0\next_srcstep[6:0] + attribute \src "libresoc.v:196926.3-196944.6" + wire width 64 $0\nia$next[63:0]$13807 + attribute \src "libresoc.v:195085.3-195086.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:196420.3-196435.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:186257.3-186281.6" - wire $0\pc_changed$next[0:0]$13473 - attribute \src "libresoc.v:185139.3-185140.37" + attribute \src "libresoc.v:197203.3-197269.6" + wire $0\pc_changed$next[0:0]$13833 + attribute \src "libresoc.v:195079.3-195080.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:186152.3-186160.6" - wire $0\pc_ok_delay$next[0:0]$13462 - attribute \src "libresoc.v:185141.3-185142.39" + attribute \src "libresoc.v:196411.3-196419.6" + wire $0\pc_ok_delay$next[0:0]$13726 + attribute \src "libresoc.v:195111.3-195112.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $1\core_asmcode$next[7:0]$13537 - attribute \src "libresoc.v:182995.13-182995.33" + attribute \src "libresoc.v:197327.3-197393.6" + wire $0\sv_changed$next[0:0]$13845 + attribute \src "libresoc.v:195075.3-195076.37" + wire $0\sv_changed[0:0] + attribute \src "libresoc.v:196458.3-196473.6" + wire width 64 $0\svstate[63:0] + attribute \src "libresoc.v:196449.3-196457.6" + wire $0\svstate_ok_delay$next[0:0]$13731 + attribute \src "libresoc.v:195109.3-195110.49" + wire $0\svstate_ok_delay[0:0] + attribute \src "libresoc.v:197270.3-197326.6" + wire $0\update_svstate[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $10\issue_fsm_state$next[2:0]$13829 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $1\core_asmcode$next[7:0]$13916 + attribute \src "libresoc.v:192624.13-192624.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:186479.3-186515.6" - wire $1\core_bigendian_i$10$next[0:0]$13761 - attribute \src "libresoc.v:186177.3-186189.6" - wire width 4 $1\core_cia__ren[3:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 64 $1\core_core_core_cia$next[63:0]$13538 - attribute \src "libresoc.v:183009.14-183009.55" + attribute \src "libresoc.v:195854.3-195878.6" + wire $1\core_bigendian_i$10$next[0:0]$13656 + attribute \src "libresoc.v:196436.3-196448.6" + wire width 3 $1\core_cia__ren[2:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $1\core_core_core_cia$next[63:0]$13917 + attribute \src "libresoc.v:192638.14-192638.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$13539 - attribute \src "libresoc.v:183013.13-183013.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$13918 + attribute \src "libresoc.v:192642.13-192642.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$13540 - attribute \src "libresoc.v:183017.7-183017.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$13919 + attribute \src "libresoc.v:192646.7-192646.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$13541 - attribute \src "libresoc.v:183021.13-183021.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$13920 + attribute \src "libresoc.v:192650.13-192650.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$13542 - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$13543 - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$13544 - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$13545 - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$13546 - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$13547 - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$13548 - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_exc_$signal$next[0:0]$13549 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 12 $1\core_core_core_fn_unit$next[11:0]$13550 - attribute \src "libresoc.v:183070.14-183070.46" - wire width 12 $1\core_core_core_fn_unit[11:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$13551 - attribute \src "libresoc.v:183078.13-183078.46" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$13921 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$13922 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$13923 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$13924 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$13925 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$13926 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$13927 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$next[0:0]$13928 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$13929 + attribute \src "libresoc.v:192701.14-192701.47" + wire width 14 $1\core_core_core_fn_unit[13:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$13930 + attribute \src "libresoc.v:192709.13-192709.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 32 $1\core_core_core_insn$next[31:0]$13552 - attribute \src "libresoc.v:183082.14-183082.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 32 $1\core_core_core_insn$next[31:0]$13931 + attribute \src "libresoc.v:192713.14-192713.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$13553 - attribute \src "libresoc.v:183160.13-183160.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$13932 + attribute \src "libresoc.v:192792.13-192792.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_is_32bit$next[0:0]$13554 - attribute \src "libresoc.v:183164.7-183164.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_is_32bit$next[0:0]$13933 + attribute \src "libresoc.v:192796.7-192796.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 64 $1\core_core_core_msr$next[63:0]$13555 - attribute \src "libresoc.v:183168.14-183168.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $1\core_core_core_msr$next[63:0]$13934 + attribute \src "libresoc.v:192800.14-192800.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_oe$next[0:0]$13556 - attribute \src "libresoc.v:183172.7-183172.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_oe$next[0:0]$13935 + attribute \src "libresoc.v:192804.7-192804.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_oe_ok$next[0:0]$13557 - attribute \src "libresoc.v:183176.7-183176.34" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_oe_ok$next[0:0]$13936 + attribute \src "libresoc.v:192808.7-192808.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_rc$next[0:0]$13558 - attribute \src "libresoc.v:183180.7-183180.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_rc$next[0:0]$13937 + attribute \src "libresoc.v:192812.7-192812.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_core_rc_ok$next[0:0]$13559 - attribute \src "libresoc.v:183184.7-183184.34" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_rc_ok$next[0:0]$13938 + attribute \src "libresoc.v:192816.7-192816.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$13560 - attribute \src "libresoc.v:183188.14-183188.48" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$13939 + attribute \src "libresoc.v:192820.14-192820.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$13561 - attribute \src "libresoc.v:183192.13-183192.44" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$13940 + attribute \src "libresoc.v:192824.13-192824.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_cr_in1$next[2:0]$13562 - attribute \src "libresoc.v:183196.13-183196.36" - wire width 3 $1\core_core_cr_in1[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_cr_in1_ok$next[0:0]$13563 - attribute \src "libresoc.v:183200.7-183200.33" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$13941 + attribute \src "libresoc.v:192828.13-192828.37" + wire width 7 $1\core_core_cr_in1[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_cr_in1_ok$next[0:0]$13942 + attribute \src "libresoc.v:192832.7-192832.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_cr_in2$1$next[2:0]$13564 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_cr_in2$next[2:0]$13565 - attribute \src "libresoc.v:183204.13-183204.36" - wire width 3 $1\core_core_cr_in2[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$13566 - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_cr_in2_ok$next[0:0]$13567 - attribute \src "libresoc.v:183212.7-183212.33" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$13943 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$13944 + attribute \src "libresoc.v:192836.13-192836.37" + wire width 7 $1\core_core_cr_in2[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$13945 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_cr_in2_ok$next[0:0]$13946 + attribute \src "libresoc.v:192844.7-192844.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_cr_out$next[2:0]$13568 - attribute \src "libresoc.v:183220.13-183220.36" - wire width 3 $1\core_core_cr_out[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_cr_wr_ok$next[0:0]$13569 - attribute \src "libresoc.v:183224.7-183224.32" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_cr_out$next[6:0]$13947 + attribute \src "libresoc.v:192852.13-192852.37" + wire width 7 $1\core_core_cr_out[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_cr_wr_ok$next[0:0]$13948 + attribute \src "libresoc.v:192856.7-192856.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $1\core_core_ea$next[4:0]$13570 - attribute \src "libresoc.v:183228.13-183228.33" - wire width 5 $1\core_core_ea[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_fast1$next[2:0]$13571 - attribute \src "libresoc.v:183232.13-183232.35" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $1\core_core_dststep$next[6:0]$13619 + attribute \src "libresoc.v:192860.13-192860.38" + wire width 7 $1\core_core_dststep[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_ea$next[6:0]$13949 + attribute \src "libresoc.v:192864.13-192864.33" + wire width 7 $1\core_core_ea[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_fast1$next[2:0]$13950 + attribute \src "libresoc.v:192868.13-192868.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_fast1_ok$next[0:0]$13572 - attribute \src "libresoc.v:183236.7-183236.32" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_fast1_ok$next[0:0]$13951 + attribute \src "libresoc.v:192872.7-192872.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_fast2$next[2:0]$13573 - attribute \src "libresoc.v:183240.13-183240.35" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_fast2$next[2:0]$13952 + attribute \src "libresoc.v:192876.13-192876.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_fast2_ok$next[0:0]$13574 - attribute \src "libresoc.v:183244.7-183244.32" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_fast2_ok$next[0:0]$13953 + attribute \src "libresoc.v:192880.7-192880.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_fasto1$next[2:0]$13575 - attribute \src "libresoc.v:183248.13-183248.36" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_fasto1$next[2:0]$13954 + attribute \src "libresoc.v:192884.13-192884.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_fasto2$next[2:0]$13576 - attribute \src "libresoc.v:183252.13-183252.36" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_fasto2$next[2:0]$13955 + attribute \src "libresoc.v:192888.13-192888.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_lk$next[0:0]$13577 - attribute \src "libresoc.v:183256.7-183256.26" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_lk$next[0:0]$13956 + attribute \src "libresoc.v:192892.7-192892.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $1\core_core_pc$next[63:0]$13403 - attribute \src "libresoc.v:183260.14-183260.49" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13620 + attribute \src "libresoc.v:192896.13-192896.36" + wire width 7 $1\core_core_maxvl[6:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $1\core_core_pc$next[63:0]$13621 + attribute \src "libresoc.v:192900.14-192900.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $1\core_core_reg1$next[4:0]$13578 - attribute \src "libresoc.v:183264.13-183264.35" - wire width 5 $1\core_core_reg1[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_reg1_ok$next[0:0]$13579 - attribute \src "libresoc.v:183268.7-183268.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_reg1$next[6:0]$13957 + attribute \src "libresoc.v:192904.13-192904.35" + wire width 7 $1\core_core_reg1[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_reg1_ok$next[0:0]$13958 + attribute \src "libresoc.v:192908.7-192908.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $1\core_core_reg2$next[4:0]$13580 - attribute \src "libresoc.v:183272.13-183272.35" - wire width 5 $1\core_core_reg2[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_reg2_ok$next[0:0]$13581 - attribute \src "libresoc.v:183276.7-183276.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_reg2$next[6:0]$13959 + attribute \src "libresoc.v:192912.13-192912.35" + wire width 7 $1\core_core_reg2[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_reg2_ok$next[0:0]$13960 + attribute \src "libresoc.v:192916.7-192916.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $1\core_core_reg3$next[4:0]$13582 - attribute \src "libresoc.v:183280.13-183280.35" - wire width 5 $1\core_core_reg3[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_reg3_ok$next[0:0]$13583 - attribute \src "libresoc.v:183284.7-183284.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_reg3$next[6:0]$13961 + attribute \src "libresoc.v:192920.13-192920.35" + wire width 7 $1\core_core_reg3[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_reg3_ok$next[0:0]$13962 + attribute \src "libresoc.v:192924.7-192924.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $1\core_core_rego$next[4:0]$13584 - attribute \src "libresoc.v:183288.13-183288.35" - wire width 5 $1\core_core_rego[4:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 10 $1\core_core_spr1$next[9:0]$13585 - attribute \src "libresoc.v:183403.13-183403.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_rego$next[6:0]$13963 + attribute \src "libresoc.v:192928.13-192928.35" + wire width 7 $1\core_core_rego[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $1\core_core_spr1$next[9:0]$13964 + attribute \src "libresoc.v:193046.13-193046.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_core_spr1_ok$next[0:0]$13586 - attribute \src "libresoc.v:183407.7-183407.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_spr1_ok$next[0:0]$13965 + attribute \src "libresoc.v:193050.7-193050.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 10 $1\core_core_spro$next[9:0]$13587 - attribute \src "libresoc.v:183522.13-183522.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $1\core_core_spro$next[9:0]$13966 + attribute \src "libresoc.v:193168.13-193168.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $1\core_core_xer_in$next[2:0]$13588 - attribute \src "libresoc.v:183528.13-183528.36" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13622 + attribute \src "libresoc.v:193172.13-193172.38" + wire width 7 $1\core_core_srcstep[6:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $1\core_core_subvl$next[1:0]$13623 + attribute \src "libresoc.v:193176.13-193176.35" + wire width 2 $1\core_core_subvl[1:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $1\core_core_svstep$next[1:0]$13624 + attribute \src "libresoc.v:193180.13-193180.36" + wire width 2 $1\core_core_svstep[1:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $1\core_core_vl$next[6:0]$13625 + attribute \src "libresoc.v:193186.13-193186.33" + wire width 7 $1\core_core_vl[6:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_xer_in$next[2:0]$13967 + attribute \src "libresoc.v:193190.13-193190.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_cr_out_ok$next[0:0]$13589 - attribute \src "libresoc.v:183536.7-183536.28" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_cr_out_ok$next[0:0]$13968 + attribute \src "libresoc.v:193198.7-193198.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:186211.3-186231.6" + attribute \src "libresoc.v:196021.3-196030.6" + wire width 64 $1\core_data_i$12[63:0]$13674 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $1\core_dec$next[63:0]$13404 - attribute \src "libresoc.v:183550.14-183550.45" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $1\core_dec$next[63:0]$13626 + attribute \src "libresoc.v:193214.14-193214.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:185875.3-185884.6" + attribute \src "libresoc.v:196134.3-196143.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:185885.3-185894.6" + attribute \src "libresoc.v:196144.3-196153.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_ea_ok$next[0:0]$13590 - attribute \src "libresoc.v:183560.7-183560.24" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_ea_ok$next[0:0]$13969 + attribute \src "libresoc.v:193224.7-193224.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire $1\core_eint$next[0:0]$13405 - attribute \src "libresoc.v:183564.7-183564.23" + attribute \src "libresoc.v:195788.3-195832.6" + wire $1\core_eint$next[0:0]$13627 + attribute \src "libresoc.v:193228.7-193228.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_fasto1_ok$next[0:0]$13591 - attribute \src "libresoc.v:183568.7-183568.28" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_fasto1_ok$next[0:0]$13970 + attribute \src "libresoc.v:193232.7-193232.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_fasto2_ok$next[0:0]$13592 - attribute \src "libresoc.v:183572.7-183572.28" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_fasto2_ok$next[0:0]$13971 + attribute \src "libresoc.v:193236.7-193236.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:185924.3-185933.6" + attribute \src "libresoc.v:196183.3-196192.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:185963.3-185972.6" + attribute \src "libresoc.v:196222.3-196231.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:186071.3-186085.6" - wire width 3 $1\core_issue__addr$11[2:0]$13450 - attribute \src "libresoc.v:186002.3-186016.6" + attribute \src "libresoc.v:196330.3-196344.6" + wire width 3 $1\core_issue__addr$13[2:0]$13714 + attribute \src "libresoc.v:196261.3-196275.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:186101.3-186115.6" + attribute \src "libresoc.v:196360.3-196374.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:186017.3-186031.6" + attribute \src "libresoc.v:196276.3-196290.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:186086.3-186100.6" + attribute \src "libresoc.v:196345.3-196359.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:185864.3-185874.6" + attribute \src "libresoc.v:196067.3-196082.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:185844.3-185863.6" + attribute \src "libresoc.v:196042.3-196066.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $1\core_msr$next[63:0]$13406 - attribute \src "libresoc.v:183600.14-183600.45" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $1\core_msr$next[63:0]$13628 + attribute \src "libresoc.v:193264.14-193264.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:186232.3-186247.6" - wire width 4 $1\core_msr__ren[3:0] - attribute \src "libresoc.v:186442.3-186478.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13755 - attribute \src "libresoc.v:183608.14-183608.37" + attribute \src "libresoc.v:196632.3-196647.6" + wire width 3 $1\core_msr__ren[2:0] + attribute \src "libresoc.v:195833.3-195853.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13651 + attribute \src "libresoc.v:193272.14-193272.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_rego_ok$next[0:0]$13593 - attribute \src "libresoc.v:183612.7-183612.26" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_rego_ok$next[0:0]$13972 + attribute \src "libresoc.v:193276.7-193276.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_spro_ok$next[0:0]$13594 - attribute \src "libresoc.v:183616.7-183616.26" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_spro_ok$next[0:0]$13973 + attribute \src "libresoc.v:193280.7-193280.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:186679.3-186697.6" + attribute \src "libresoc.v:197141.3-197171.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:186190.3-186210.6" - wire width 4 $1\core_wen[3:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $1\core_xer_out$next[0:0]$13595 - attribute \src "libresoc.v:183628.7-183628.26" + attribute \src "libresoc.v:196474.3-196486.6" + wire width 3 $1\core_sv__ren[2:0] + attribute \src "libresoc.v:195879.3-195903.6" + wire $1\core_sv_a_nz$next[0:0]$13661 + attribute \src "libresoc.v:193292.7-193292.26" + wire $1\core_sv_a_nz[0:0] + attribute \src "libresoc.v:196011.3-196020.6" + wire width 3 $1\core_wen$11[2:0]$13671 + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $1\core_wen[2:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_xer_out$next[0:0]$13974 + attribute \src "libresoc.v:193302.7-193302.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:183634.7-183634.30" + attribute \src "libresoc.v:193308.7-193308.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:185934.3-185942.6" - wire $1\d_cr_delay$next[0:0]$13432 - attribute \src "libresoc.v:183640.7-183640.24" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13760 + attribute \src "libresoc.v:193314.13-193314.36" + wire width 7 $1\cur_cur_dststep[6:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13761 + attribute \src "libresoc.v:193318.13-193318.34" + wire width 7 $1\cur_cur_maxvl[6:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13762 + attribute \src "libresoc.v:193322.13-193322.36" + wire width 7 $1\cur_cur_srcstep[6:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13763 + attribute \src "libresoc.v:193326.13-193326.33" + wire width 2 $1\cur_cur_subvl[1:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13764 + attribute \src "libresoc.v:193330.13-193330.34" + wire width 2 $1\cur_cur_svstep[1:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13765 + attribute \src "libresoc.v:193334.13-193334.31" + wire width 7 $1\cur_cur_vl[6:0] + attribute \src "libresoc.v:196193.3-196201.6" + wire $1\d_cr_delay$next[0:0]$13696 + attribute \src "libresoc.v:193338.7-193338.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:185895.3-185903.6" - wire $1\d_reg_delay$next[0:0]$13426 - attribute \src "libresoc.v:183644.7-183644.25" + attribute \src "libresoc.v:196154.3-196162.6" + wire $1\d_reg_delay$next[0:0]$13690 + attribute \src "libresoc.v:193342.7-193342.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:185973.3-185981.6" - wire $1\d_xer_delay$next[0:0]$13438 - attribute \src "libresoc.v:183648.7-183648.25" + attribute \src "libresoc.v:196232.3-196240.6" + wire $1\d_xer_delay$next[0:0]$13702 + attribute \src "libresoc.v:193346.7-193346.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:186698.3-186716.6" + attribute \src "libresoc.v:197172.3-197202.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:185953.3-185962.6" + attribute \src "libresoc.v:196212.3-196221.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:185943.3-185952.6" + attribute \src "libresoc.v:196202.3-196211.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:185914.3-185923.6" + attribute \src "libresoc.v:196173.3-196182.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:185904.3-185913.6" + attribute \src "libresoc.v:196163.3-196172.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:185992.3-186001.6" + attribute \src "libresoc.v:196251.3-196260.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:185982.3-185991.6" + attribute \src "libresoc.v:196241.3-196250.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:185730.3-185738.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13388 - attribute \src "libresoc.v:183684.13-183684.34" + attribute \src "libresoc.v:195751.3-195759.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13598 + attribute \src "libresoc.v:193394.13-193394.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:186248.3-186256.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13471 - attribute \src "libresoc.v:183688.14-183688.48" + attribute \src "libresoc.v:196487.3-196495.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13737 + attribute \src "libresoc.v:193398.14-193398.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:185739.3-185747.6" - wire $1\dbg_dmi_req_i$next[0:0]$13391 - attribute \src "libresoc.v:183694.7-183694.27" + attribute \src "libresoc.v:195760.3-195768.6" + wire $1\dbg_dmi_req_i$next[0:0]$13601 + attribute \src "libresoc.v:193404.7-193404.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:186143.3-186151.6" - wire $1\dbg_dmi_we_i$next[0:0]$13460 - attribute \src "libresoc.v:183698.7-183698.26" + attribute \src "libresoc.v:196402.3-196410.6" + wire $1\dbg_dmi_we_i$next[0:0]$13724 + attribute \src "libresoc.v:193408.7-193408.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:186116.3-186131.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13455 - attribute \src "libresoc.v:183752.14-183752.49" + attribute \src "libresoc.v:196375.3-196390.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13719 + attribute \src "libresoc.v:193462.14-193462.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:186423.3-186431.6" - wire $1\dec2_cur_eint$next[0:0]$13749 - attribute \src "libresoc.v:183756.7-183756.27" + attribute \src "libresoc.v:195769.3-195777.6" + wire $1\dec2_cur_eint$next[0:0]$13604 + attribute \src "libresoc.v:193466.7-193466.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:185748.3-185768.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13394 - attribute \src "libresoc.v:183760.14-183760.49" + attribute \src "libresoc.v:196905.3-196925.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13803 + attribute \src "libresoc.v:193470.14-193470.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:186582.3-186602.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13770 - attribute \src "libresoc.v:183764.14-183764.48" + attribute \src "libresoc.v:196752.3-196772.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13750 + attribute \src "libresoc.v:193474.14-193474.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:185769.3-185787.6" + attribute \src "libresoc.v:196945.3-196975.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13812 + attribute \src "libresoc.v:193626.14-193626.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:186432.3-186441.6" - wire width 2 $1\delay$next[1:0]$13752 - attribute \src "libresoc.v:184173.13-184173.25" + attribute \src "libresoc.v:195778.3-195787.6" + wire width 2 $1\delay$next[1:0]$13607 + attribute \src "libresoc.v:193896.13-193896.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:186032.3-186059.6" - wire width 2 $1\fsm_state$133$next[1:0]$13445 - attribute \src "libresoc.v:186633.3-186678.6" - wire width 2 $1\fsm_state$next[1:0]$13781 - attribute \src "libresoc.v:184189.13-184189.29" + attribute \src "libresoc.v:196083.3-196117.6" + wire $1\exec_fsm_state$next[0:0]$13680 + attribute \src "libresoc.v:193912.7-193912.28" + wire $1\exec_fsm_state[0:0] + attribute \src "libresoc.v:196031.3-196041.6" + wire $1\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:195942.3-195952.6" + wire $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:195953.3-195968.6" + wire $1\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:196118.3-196133.6" + wire $1\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13795 + attribute \src "libresoc.v:193924.13-193924.35" + wire width 2 $1\fetch_fsm_state[1:0] + attribute \src "libresoc.v:197394.3-197404.6" + wire $1\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:196976.3-196986.6" + wire $1\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:196657.3-196667.6" + wire $1\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:197044.3-197059.6" + wire $1\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:196291.3-196318.6" + wire width 2 $1\fsm_state$next[1:0]$13709 + attribute \src "libresoc.v:193936.13-193936.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:185820.3-185843.6" - wire width 32 $1\ilatch$next[31:0]$13417 - attribute \src "libresoc.v:184433.14-184433.28" - wire width 32 $1\ilatch[31:0] - attribute \src "libresoc.v:186516.3-186531.6" + attribute \src "libresoc.v:196668.3-196683.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:186532.3-186556.6" + attribute \src "libresoc.v:196684.3-196717.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186557.3-186581.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:186405.3-186413.6" + attribute \src "libresoc.v:195904.3-195941.6" + wire $1\insn_done[0:0] + attribute \src "libresoc.v:195990.3-196010.6" + wire $1\is_last[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $1\issue_fsm_state$next[2:0]$13820 + attribute \src "libresoc.v:194196.13-194196.35" + wire width 3 $1\issue_fsm_state[2:0] + attribute \src "libresoc.v:196648.3-196656.6" wire $1\jtag_dmi0__ack_o$next[0:0]$13743 - attribute \src "libresoc.v:184451.7-184451.30" + attribute \src "libresoc.v:194200.7-194200.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:186414.3-186422.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13746 - attribute \src "libresoc.v:184459.14-184459.52" + attribute \src "libresoc.v:196812.3-196820.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13786 + attribute \src "libresoc.v:194208.14-194208.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:186603.3-186632.6" - wire $1\msr_read$next[0:0]$13775 - attribute \src "libresoc.v:184515.7-184515.22" + attribute \src "libresoc.v:196821.3-196850.6" + wire $1\msr_read$next[0:0]$13789 + attribute \src "libresoc.v:194266.7-194266.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:186060.3-186070.6" + attribute \src "libresoc.v:196319.3-196329.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:186132.3-186142.6" + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $1\new_svstate_dststep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $1\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $1\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $1\new_svstate_subvl[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $1\new_svstate_svstep[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $1\new_svstate_vl[6:0] + attribute \src "libresoc.v:196391.3-196401.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:186161.3-186176.6" + attribute \src "libresoc.v:195969.3-195989.6" + wire width 7 $1\next_srcstep[6:0] + attribute \src "libresoc.v:196926.3-196944.6" + wire width 64 $1\nia$next[63:0]$13808 + attribute \src "libresoc.v:194304.14-194304.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:196420.3-196435.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:186257.3-186281.6" - wire $1\pc_changed$next[0:0]$13474 - attribute \src "libresoc.v:184543.7-184543.24" + attribute \src "libresoc.v:197203.3-197269.6" + wire $1\pc_changed$next[0:0]$13834 + attribute \src "libresoc.v:194310.7-194310.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:186152.3-186160.6" - wire $1\pc_ok_delay$next[0:0]$13463 - attribute \src "libresoc.v:184553.7-184553.25" + attribute \src "libresoc.v:196411.3-196419.6" + wire $1\pc_ok_delay$next[0:0]$13727 + attribute \src "libresoc.v:194320.7-194320.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $2\core_asmcode$next[7:0]$13596 - attribute \src "libresoc.v:186479.3-186515.6" - wire $2\core_bigendian_i$10$next[0:0]$13762 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 64 $2\core_core_core_cia$next[63:0]$13597 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$13598 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$13599 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$13600 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$13601 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$13602 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$13603 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$13604 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$13605 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$13606 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$13607 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_exc_$signal$next[0:0]$13608 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 12 $2\core_core_core_fn_unit$next[11:0]$13609 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$13610 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 32 $2\core_core_core_insn$next[31:0]$13611 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$13612 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_is_32bit$next[0:0]$13613 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 64 $2\core_core_core_msr$next[63:0]$13614 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_oe$next[0:0]$13615 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_oe_ok$next[0:0]$13616 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_rc$next[0:0]$13617 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_core_rc_ok$next[0:0]$13618 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$13619 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$13620 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_cr_in1$next[2:0]$13621 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_cr_in1_ok$next[0:0]$13622 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_cr_in2$1$next[2:0]$13623 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_cr_in2$next[2:0]$13624 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$13625 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_cr_in2_ok$next[0:0]$13626 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_cr_out$next[2:0]$13627 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_cr_wr_ok$next[0:0]$13628 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $2\core_core_ea$next[4:0]$13629 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_fast1$next[2:0]$13630 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_fast1_ok$next[0:0]$13631 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_fast2$next[2:0]$13632 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_fast2_ok$next[0:0]$13633 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_fasto1$next[2:0]$13634 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_fasto2$next[2:0]$13635 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_lk$next[0:0]$13636 - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $2\core_core_pc$next[63:0]$13407 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $2\core_core_reg1$next[4:0]$13637 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_reg1_ok$next[0:0]$13638 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $2\core_core_reg2$next[4:0]$13639 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_reg2_ok$next[0:0]$13640 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $2\core_core_reg3$next[4:0]$13641 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_reg3_ok$next[0:0]$13642 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $2\core_core_rego$next[4:0]$13643 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 10 $2\core_core_spr1$next[9:0]$13644 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_core_spr1_ok$next[0:0]$13645 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 10 $2\core_core_spro$next[9:0]$13646 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $2\core_core_xer_in$next[2:0]$13647 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_cr_out_ok$next[0:0]$13648 - attribute \src "libresoc.v:186211.3-186231.6" + attribute \src "libresoc.v:197327.3-197393.6" + wire $1\sv_changed$next[0:0]$13846 + attribute \src "libresoc.v:194764.7-194764.24" + wire $1\sv_changed[0:0] + attribute \src "libresoc.v:196458.3-196473.6" + wire width 64 $1\svstate[63:0] + attribute \src "libresoc.v:196449.3-196457.6" + wire $1\svstate_ok_delay$next[0:0]$13732 + attribute \src "libresoc.v:194774.7-194774.30" + wire $1\svstate_ok_delay[0:0] + attribute \src "libresoc.v:197270.3-197326.6" + wire $1\update_svstate[0:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $2\core_asmcode$next[7:0]$13975 + attribute \src "libresoc.v:195854.3-195878.6" + wire $2\core_bigendian_i$10$next[0:0]$13657 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $2\core_core_core_cia$next[63:0]$13976 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$13977 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$13978 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$13979 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$13980 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$13981 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$13982 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$13983 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$13984 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$13985 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$13986 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$next[0:0]$13987 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 14 $2\core_core_core_fn_unit$next[13:0]$13988 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$13989 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 32 $2\core_core_core_insn$next[31:0]$13990 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$13991 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_is_32bit$next[0:0]$13992 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $2\core_core_core_msr$next[63:0]$13993 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_oe$next[0:0]$13994 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_oe_ok$next[0:0]$13995 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_rc$next[0:0]$13996 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_rc_ok$next[0:0]$13997 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$13998 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$13999 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14000 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14001 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14002 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14003 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14004 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14005 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14006 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14007 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $2\core_core_dststep$next[6:0]$13629 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_ea$next[6:0]$14008 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_fast1$next[2:0]$14009 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_fast1_ok$next[0:0]$14010 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_fast2$next[2:0]$14011 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_fast2_ok$next[0:0]$14012 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14013 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14014 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_lk$next[0:0]$14015 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13630 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $2\core_core_pc$next[63:0]$13631 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_reg1$next[6:0]$14016 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_reg1_ok$next[0:0]$14017 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_reg2$next[6:0]$14018 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_reg2_ok$next[0:0]$14019 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_reg3$next[6:0]$14020 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_reg3_ok$next[0:0]$14021 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_rego$next[6:0]$14022 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $2\core_core_spr1$next[9:0]$14023 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_spr1_ok$next[0:0]$14024 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $2\core_core_spro$next[9:0]$14025 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13632 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $2\core_core_subvl$next[1:0]$13633 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $2\core_core_svstep$next[1:0]$13634 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $2\core_core_vl$next[6:0]$13635 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14026 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_cr_out_ok$next[0:0]$14027 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $2\core_dec$next[63:0]$13408 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_ea_ok$next[0:0]$13649 - attribute \src "libresoc.v:185788.3-185819.6" - wire $2\core_eint$next[0:0]$13409 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_fasto1_ok$next[0:0]$13650 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_fasto2_ok$next[0:0]$13651 - attribute \src "libresoc.v:185844.3-185863.6" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $2\core_dec$next[63:0]$13636 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_ea_ok$next[0:0]$14028 + attribute \src "libresoc.v:195788.3-195832.6" + wire $2\core_eint$next[0:0]$13637 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_fasto1_ok$next[0:0]$14029 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_fasto2_ok$next[0:0]$14030 + attribute \src "libresoc.v:196067.3-196082.6" + wire $2\core_issue_i[0:0] + attribute \src "libresoc.v:196042.3-196066.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $2\core_msr$next[63:0]$13410 - attribute \src "libresoc.v:186232.3-186247.6" - wire width 4 $2\core_msr__ren[3:0] - attribute \src "libresoc.v:186442.3-186478.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13756 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_rego_ok$next[0:0]$13652 - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_spro_ok$next[0:0]$13653 - attribute \src "libresoc.v:186679.3-186697.6" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $2\core_msr$next[63:0]$13638 + attribute \src "libresoc.v:196632.3-196647.6" + wire width 3 $2\core_msr__ren[2:0] + attribute \src "libresoc.v:195833.3-195853.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13652 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_rego_ok$next[0:0]$14031 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_spro_ok$next[0:0]$14032 + attribute \src "libresoc.v:197141.3-197171.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:186190.3-186210.6" - wire width 4 $2\core_wen[3:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $2\core_xer_out$next[0:0]$13654 - attribute \src "libresoc.v:186698.3-186716.6" + attribute \src "libresoc.v:195879.3-195903.6" + wire $2\core_sv_a_nz$next[0:0]$13662 + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $2\core_wen[2:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_xer_out$next[0:0]$14033 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13766 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13767 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13768 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13769 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13770 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13771 + attribute \src "libresoc.v:197172.3-197202.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:186116.3-186131.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13456 - attribute \src "libresoc.v:185748.3-185768.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13395 - attribute \src "libresoc.v:186582.3-186602.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13771 - attribute \src "libresoc.v:185769.3-185787.6" - wire width 32 $2\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:186032.3-186059.6" - wire width 2 $2\fsm_state$133$next[1:0]$13446 - attribute \src "libresoc.v:186633.3-186678.6" - wire width 2 $2\fsm_state$next[1:0]$13782 - attribute \src "libresoc.v:185820.3-185843.6" - wire width 32 $2\ilatch$next[31:0]$13418 - attribute \src "libresoc.v:186516.3-186531.6" + attribute \src "libresoc.v:196375.3-196390.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13720 + attribute \src "libresoc.v:196905.3-196925.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13804 + attribute \src "libresoc.v:196752.3-196772.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13751 + attribute \src "libresoc.v:196945.3-196975.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13813 + attribute \src "libresoc.v:196083.3-196117.6" + wire $2\exec_fsm_state$next[0:0]$13681 + attribute \src "libresoc.v:195953.3-195968.6" + wire $2\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:196118.3-196133.6" + wire $2\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13796 + attribute \src "libresoc.v:197044.3-197059.6" + wire $2\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:196291.3-196318.6" + wire width 2 $2\fsm_state$next[1:0]$13710 + attribute \src "libresoc.v:196668.3-196683.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:186532.3-186556.6" + attribute \src "libresoc.v:196684.3-196717.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186557.3-186581.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:186603.3-186632.6" - wire $2\msr_read$next[0:0]$13776 - attribute \src "libresoc.v:186161.3-186176.6" + attribute \src "libresoc.v:195904.3-195941.6" + wire $2\insn_done[0:0] + attribute \src "libresoc.v:195990.3-196010.6" + wire $2\is_last[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $2\issue_fsm_state$next[2:0]$13821 + attribute \src "libresoc.v:196821.3-196850.6" + wire $2\msr_read$next[0:0]$13790 + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $2\new_svstate_dststep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $2\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $2\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $2\new_svstate_subvl[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $2\new_svstate_svstep[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $2\new_svstate_vl[6:0] + attribute \src "libresoc.v:195969.3-195989.6" + wire width 7 $2\next_srcstep[6:0] + attribute \src "libresoc.v:196926.3-196944.6" + wire width 64 $2\nia$next[63:0]$13809 + attribute \src "libresoc.v:196420.3-196435.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:186257.3-186281.6" - wire $2\pc_changed$next[0:0]$13475 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $3\core_asmcode$next[7:0]$13655 - attribute \src "libresoc.v:186479.3-186515.6" - wire $3\core_bigendian_i$10$next[0:0]$13763 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 64 $3\core_core_core_cia$next[63:0]$13656 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $3\core_core_core_cr_rd$next[7:0]$13657 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$13658 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $3\core_core_core_cr_wr$next[7:0]$13659 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$13660 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$13661 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$13662 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$13663 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$13664 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$13665 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$13666 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_exc_$signal$next[0:0]$13667 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 12 $3\core_core_core_fn_unit$next[11:0]$13668 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 2 $3\core_core_core_input_carry$next[1:0]$13669 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 32 $3\core_core_core_insn$next[31:0]$13670 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 7 $3\core_core_core_insn_type$next[6:0]$13671 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_is_32bit$next[0:0]$13672 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 64 $3\core_core_core_msr$next[63:0]$13673 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_oe$next[0:0]$13674 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_oe_ok$next[0:0]$13675 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_rc$next[0:0]$13676 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_core_rc_ok$next[0:0]$13677 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 13 $3\core_core_core_trapaddr$next[12:0]$13678 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 8 $3\core_core_core_traptype$next[7:0]$13679 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_cr_in1$next[2:0]$13680 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_cr_in1_ok$next[0:0]$13681 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_cr_in2$1$next[2:0]$13682 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_cr_in2$next[2:0]$13683 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$13684 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_cr_in2_ok$next[0:0]$13685 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_cr_out$next[2:0]$13686 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_cr_wr_ok$next[0:0]$13687 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $3\core_core_ea$next[4:0]$13688 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_fast1$next[2:0]$13689 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_fast1_ok$next[0:0]$13690 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_fast2$next[2:0]$13691 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_fast2_ok$next[0:0]$13692 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_fasto1$next[2:0]$13693 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_fasto2$next[2:0]$13694 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_lk$next[0:0]$13695 - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $3\core_core_pc$next[63:0]$13411 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $3\core_core_reg1$next[4:0]$13696 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_reg1_ok$next[0:0]$13697 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $3\core_core_reg2$next[4:0]$13698 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_reg2_ok$next[0:0]$13699 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $3\core_core_reg3$next[4:0]$13700 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_reg3_ok$next[0:0]$13701 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 5 $3\core_core_rego$next[4:0]$13702 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 10 $3\core_core_spr1$next[9:0]$13703 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_core_spr1_ok$next[0:0]$13704 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 10 $3\core_core_spro$next[9:0]$13705 - attribute \src "libresoc.v:186282.3-186404.6" - wire width 3 $3\core_core_xer_in$next[2:0]$13706 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_cr_out_ok$next[0:0]$13707 - attribute \src "libresoc.v:186211.3-186231.6" + attribute \src "libresoc.v:197203.3-197269.6" + wire $2\pc_changed$next[0:0]$13835 + attribute \src "libresoc.v:197327.3-197393.6" + wire $2\sv_changed$next[0:0]$13847 + attribute \src "libresoc.v:196458.3-196473.6" + wire width 64 $2\svstate[63:0] + attribute \src "libresoc.v:197270.3-197326.6" + wire $2\update_svstate[0:0] + attribute \src "libresoc.v:195854.3-195878.6" + wire $3\core_bigendian_i$10$next[0:0]$13658 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14034 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14035 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14036 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14037 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14038 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14039 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14040 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14041 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14042 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_oe_ok$next[0:0]$14043 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_rc_ok$next[0:0]$14044 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14045 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14046 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14047 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14048 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $3\core_core_dststep$next[6:0]$13639 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_fast1_ok$next[0:0]$14049 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_fast2_ok$next[0:0]$14050 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13640 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $3\core_core_pc$next[63:0]$13641 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_reg1_ok$next[0:0]$14051 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_reg2_ok$next[0:0]$14052 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_reg3_ok$next[0:0]$14053 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_spr1_ok$next[0:0]$14054 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13642 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $3\core_core_subvl$next[1:0]$13643 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $3\core_core_svstep$next[1:0]$13644 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $3\core_core_vl$next[6:0]$13645 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_cr_out_ok$next[0:0]$14055 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $3\core_dec$next[63:0]$13412 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_ea_ok$next[0:0]$13708 - attribute \src "libresoc.v:185788.3-185819.6" - wire $3\core_eint$next[0:0]$13413 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_fasto1_ok$next[0:0]$13709 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_fasto2_ok$next[0:0]$13710 - attribute \src "libresoc.v:185788.3-185819.6" - wire width 64 $3\core_msr$next[63:0]$13414 - attribute \src "libresoc.v:186442.3-186478.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13757 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_rego_ok$next[0:0]$13711 - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_spro_ok$next[0:0]$13712 - attribute \src "libresoc.v:186190.3-186210.6" - wire width 4 $3\core_wen[3:0] - attribute \src "libresoc.v:186282.3-186404.6" - wire $3\core_xer_out$next[0:0]$13713 - attribute \src "libresoc.v:185748.3-185768.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13396 - attribute \src "libresoc.v:186582.3-186602.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13772 - attribute \src "libresoc.v:186633.3-186678.6" - wire width 2 $3\fsm_state$next[1:0]$13783 - attribute \src "libresoc.v:185820.3-185843.6" - wire width 32 $3\ilatch$next[31:0]$13419 - attribute \src "libresoc.v:186532.3-186556.6" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $3\core_dec$next[63:0]$13646 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_ea_ok$next[0:0]$14056 + attribute \src "libresoc.v:195788.3-195832.6" + wire $3\core_eint$next[0:0]$13647 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_fasto1_ok$next[0:0]$14057 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_fasto2_ok$next[0:0]$14058 + attribute \src "libresoc.v:196042.3-196066.6" + wire $3\core_ivalid_i[0:0] + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $3\core_msr$next[63:0]$13648 + attribute \src "libresoc.v:195833.3-195853.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13653 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_rego_ok$next[0:0]$14059 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_spro_ok$next[0:0]$14060 + attribute \src "libresoc.v:197141.3-197171.6" + wire $3\core_stopped_i[0:0] + attribute \src "libresoc.v:195879.3-195903.6" + wire $3\core_sv_a_nz$next[0:0]$13663 + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $3\core_wen[2:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13772 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13773 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13774 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13775 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13776 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13777 + attribute \src "libresoc.v:197172.3-197202.6" + wire $3\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:196905.3-196925.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13805 + attribute \src "libresoc.v:196752.3-196772.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13752 + attribute \src "libresoc.v:196945.3-196975.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13814 + attribute \src "libresoc.v:196083.3-196117.6" + wire $3\exec_fsm_state$next[0:0]$13682 + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13797 + attribute \src "libresoc.v:196684.3-196717.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186557.3-186581.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:186603.3-186632.6" - wire $3\msr_read$next[0:0]$13777 - attribute \src "libresoc.v:186257.3-186281.6" - wire $3\pc_changed$next[0:0]$13476 - attribute \src "libresoc.v:186479.3-186515.6" - wire $4\core_bigendian_i$10$next[0:0]$13764 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_cr_rd_ok$next[0:0]$13714 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_exc_$signal$3$next[0:0]$13715 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_exc_$signal$4$next[0:0]$13716 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_exc_$signal$5$next[0:0]$13717 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_exc_$signal$6$next[0:0]$13718 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_exc_$signal$7$next[0:0]$13719 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_exc_$signal$8$next[0:0]$13720 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_exc_$signal$9$next[0:0]$13721 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_exc_$signal$next[0:0]$13722 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_oe_ok$next[0:0]$13723 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_core_rc_ok$next[0:0]$13724 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_cr_in1_ok$next[0:0]$13725 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_cr_in2_ok$2$next[0:0]$13726 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_cr_in2_ok$next[0:0]$13727 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_cr_wr_ok$next[0:0]$13728 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_fast1_ok$next[0:0]$13729 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_fast2_ok$next[0:0]$13730 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_reg1_ok$next[0:0]$13731 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_reg2_ok$next[0:0]$13732 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_reg3_ok$next[0:0]$13733 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_core_spr1_ok$next[0:0]$13734 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_cr_out_ok$next[0:0]$13735 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_ea_ok$next[0:0]$13736 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_fasto1_ok$next[0:0]$13737 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_fasto2_ok$next[0:0]$13738 - attribute \src "libresoc.v:186442.3-186478.6" - wire width 32 $4\core_raw_insn_i$next[31:0]$13758 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_rego_ok$next[0:0]$13739 - attribute \src "libresoc.v:186282.3-186404.6" - wire $4\core_spro_ok$next[0:0]$13740 - attribute \src "libresoc.v:186633.3-186678.6" - wire width 2 $4\fsm_state$next[1:0]$13784 - attribute \src "libresoc.v:186603.3-186632.6" - wire $4\msr_read$next[0:0]$13778 - attribute \src "libresoc.v:186633.3-186678.6" - wire width 2 $5\fsm_state$next[1:0]$13785 - attribute \src "libresoc.v:184954.19-184954.115" - wire width 65 $add$libresoc.v:184954$13249_Y - attribute \src "libresoc.v:184962.18-184962.107" - wire width 65 $add$libresoc.v:184962$13257_Y - attribute \src "libresoc.v:184937.19-184937.102" - wire $and$libresoc.v:184937$13230_Y - attribute \src "libresoc.v:184941.19-184941.104" - wire $and$libresoc.v:184941$13234_Y - attribute \src "libresoc.v:184944.19-184944.104" - wire $and$libresoc.v:184944$13237_Y - attribute \src "libresoc.v:184961.18-184961.109" - wire $and$libresoc.v:184961$13256_Y - attribute \src "libresoc.v:184970.18-184970.101" - wire $and$libresoc.v:184970$13265_Y - attribute \src "libresoc.v:184971.18-184971.114" - wire width 4 $and$libresoc.v:184971$13266_Y - attribute \src "libresoc.v:184978.18-184978.101" - wire $and$libresoc.v:184978$13273_Y - attribute \src "libresoc.v:184981.18-184981.101" - wire $and$libresoc.v:184981$13276_Y - attribute \src "libresoc.v:184984.18-184984.101" - wire $and$libresoc.v:184984$13279_Y - attribute \src "libresoc.v:184987.18-184987.101" - wire $and$libresoc.v:184987$13282_Y - attribute \src "libresoc.v:184990.18-184990.101" - wire $and$libresoc.v:184990$13285_Y - attribute \src "libresoc.v:184951.19-184951.114" - wire width 64 $extend$libresoc.v:184951$13244_Y - attribute \src "libresoc.v:184952.19-184952.113" - wire width 64 $extend$libresoc.v:184952$13246_Y - attribute \src "libresoc.v:184946.19-184946.111" - wire width 7 $mul$libresoc.v:184946$13239_Y - attribute \src "libresoc.v:184948.19-184948.111" - wire width 7 $mul$libresoc.v:184948$13241_Y - attribute \src "libresoc.v:184950.19-184950.123" - wire $ne$libresoc.v:184950$13243_Y - attribute \src "libresoc.v:184955.18-184955.102" - wire $ne$libresoc.v:184955$13250_Y - attribute \src "libresoc.v:184959.18-184959.102" - wire $ne$libresoc.v:184959$13254_Y - attribute \src "libresoc.v:184936.18-184936.108" - wire $not$libresoc.v:184936$13229_Y - attribute \src "libresoc.v:184938.19-184938.107" - wire $not$libresoc.v:184938$13231_Y - attribute \src "libresoc.v:184939.19-184939.107" - wire $not$libresoc.v:184939$13232_Y - attribute \src "libresoc.v:184940.19-184940.109" - wire $not$libresoc.v:184940$13233_Y - attribute \src "libresoc.v:184942.19-184942.107" - wire $not$libresoc.v:184942$13235_Y - attribute \src "libresoc.v:184943.19-184943.109" - wire $not$libresoc.v:184943$13236_Y - attribute \src "libresoc.v:184945.19-184945.100" - wire $not$libresoc.v:184945$13238_Y - attribute \src "libresoc.v:184960.18-184960.103" - wire $not$libresoc.v:184960$13255_Y - attribute \src "libresoc.v:184963.18-184963.98" - wire $not$libresoc.v:184963$13258_Y - attribute \src "libresoc.v:184964.18-184964.106" - wire $not$libresoc.v:184964$13259_Y - attribute \src "libresoc.v:184965.18-184965.101" - wire $not$libresoc.v:184965$13260_Y - attribute \src "libresoc.v:184966.18-184966.106" - wire $not$libresoc.v:184966$13261_Y - attribute \src "libresoc.v:184967.18-184967.101" - wire $not$libresoc.v:184967$13262_Y - attribute \src "libresoc.v:184968.18-184968.106" - wire $not$libresoc.v:184968$13263_Y - attribute \src "libresoc.v:184969.18-184969.108" - wire $not$libresoc.v:184969$13264_Y - attribute \src "libresoc.v:184973.18-184973.106" - wire $not$libresoc.v:184973$13268_Y - attribute \src "libresoc.v:184974.18-184974.106" - wire $not$libresoc.v:184974$13269_Y - attribute \src "libresoc.v:184975.18-184975.106" - wire $not$libresoc.v:184975$13270_Y - attribute \src "libresoc.v:184976.18-184976.106" - wire $not$libresoc.v:184976$13271_Y - attribute \src "libresoc.v:184977.18-184977.108" - wire $not$libresoc.v:184977$13272_Y - attribute \src "libresoc.v:184979.18-184979.106" - wire $not$libresoc.v:184979$13274_Y - attribute \src "libresoc.v:184980.18-184980.108" - wire $not$libresoc.v:184980$13275_Y - attribute \src "libresoc.v:184982.18-184982.106" - wire $not$libresoc.v:184982$13277_Y - attribute \src "libresoc.v:184983.18-184983.108" - wire $not$libresoc.v:184983$13278_Y - attribute \src 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"libresoc.v:184947.19-184947.42" - wire width 64 $shr$libresoc.v:184947$13240_Y - attribute \src "libresoc.v:184949.19-184949.42" - wire width 64 $shr$libresoc.v:184949$13242_Y - attribute \src "libresoc.v:184953.19-184953.115" - wire width 65 $sub$libresoc.v:184953$13248_Y - attribute \src "libresoc.v:184956.18-184956.101" - wire width 3 $sub$libresoc.v:184956$13251_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" - wire width 32 \$119 + attribute \src "libresoc.v:195904.3-195941.6" + wire $3\insn_done[0:0] + attribute \src "libresoc.v:195990.3-196010.6" + wire $3\is_last[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $3\issue_fsm_state$next[2:0]$13822 + attribute \src "libresoc.v:196821.3-196850.6" + wire $3\msr_read$next[0:0]$13791 + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $3\new_svstate_dststep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $3\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $3\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $3\new_svstate_subvl[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $3\new_svstate_svstep[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $3\new_svstate_vl[6:0] + attribute \src "libresoc.v:195969.3-195989.6" + wire width 7 $3\next_srcstep[6:0] + attribute \src "libresoc.v:197203.3-197269.6" + wire $3\pc_changed$next[0:0]$13836 + attribute \src "libresoc.v:197327.3-197393.6" + wire $3\sv_changed$next[0:0]$13848 + attribute \src "libresoc.v:197270.3-197326.6" + wire $3\update_svstate[0:0] + attribute \src "libresoc.v:196564.3-196631.6" + wire width 64 $4\core_data_i[63:0] + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $4\core_wen[2:0] + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13778 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13779 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13780 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13781 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13782 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13783 + attribute \src "libresoc.v:196083.3-196117.6" + wire $4\exec_fsm_state$next[0:0]$13683 + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13798 + attribute \src "libresoc.v:196684.3-196717.6" + wire $4\imem_a_valid_i[0:0] + attribute \src "libresoc.v:196718.3-196751.6" + wire $4\imem_f_valid_i[0:0] + attribute \src "libresoc.v:195904.3-195941.6" + wire $4\insn_done[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $4\issue_fsm_state$next[2:0]$13823 + attribute \src "libresoc.v:196821.3-196850.6" + wire $4\msr_read$next[0:0]$13792 + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $4\new_svstate_dststep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $4\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $4\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $4\new_svstate_subvl[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $4\new_svstate_svstep[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $4\new_svstate_vl[6:0] + attribute \src "libresoc.v:197203.3-197269.6" + wire $4\pc_changed$next[0:0]$13837 + attribute \src "libresoc.v:197327.3-197393.6" + wire $4\sv_changed$next[0:0]$13849 + attribute \src "libresoc.v:197270.3-197326.6" + wire $4\update_svstate[0:0] + attribute \src "libresoc.v:196564.3-196631.6" + wire width 64 $5\core_data_i[63:0] + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $5\core_wen[2:0] + attribute \src "libresoc.v:196083.3-196117.6" + wire $5\exec_fsm_state$next[0:0]$13684 + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13799 + attribute \src "libresoc.v:195904.3-195941.6" + wire $5\insn_done[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $5\issue_fsm_state$next[2:0]$13824 + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $5\new_svstate_dststep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $5\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $5\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $5\new_svstate_subvl[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 2 $5\new_svstate_svstep[1:0] + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $5\new_svstate_vl[6:0] + attribute \src "libresoc.v:197203.3-197269.6" + wire $5\pc_changed$next[0:0]$13838 + attribute \src "libresoc.v:197327.3-197393.6" + wire $5\sv_changed$next[0:0]$13850 + attribute \src "libresoc.v:197270.3-197326.6" + wire $5\update_svstate[0:0] + attribute \src "libresoc.v:196564.3-196631.6" + wire width 64 $6\core_data_i[63:0] + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $6\core_wen[2:0] + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13800 + attribute \src "libresoc.v:195904.3-195941.6" + wire $6\insn_done[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $6\issue_fsm_state$next[2:0]$13825 + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $6\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:197203.3-197269.6" + wire $6\pc_changed$next[0:0]$13839 + attribute \src "libresoc.v:197327.3-197393.6" + wire $6\sv_changed$next[0:0]$13851 + attribute \src "libresoc.v:197270.3-197326.6" + wire $6\update_svstate[0:0] + attribute \src "libresoc.v:196564.3-196631.6" + wire width 64 $7\core_data_i[63:0] + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $7\core_wen[2:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $7\issue_fsm_state$next[2:0]$13826 + attribute \src "libresoc.v:196987.3-197043.6" + wire width 7 $7\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:197203.3-197269.6" + wire $7\pc_changed$next[0:0]$13840 + attribute \src "libresoc.v:197327.3-197393.6" + wire $7\sv_changed$next[0:0]$13852 + attribute \src "libresoc.v:197270.3-197326.6" + wire $7\update_svstate[0:0] + attribute \src "libresoc.v:196564.3-196631.6" + wire width 64 $8\core_data_i[63:0] + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $8\core_wen[2:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $8\issue_fsm_state$next[2:0]$13827 + attribute \src "libresoc.v:197203.3-197269.6" + wire $8\pc_changed$next[0:0]$13841 + attribute \src "libresoc.v:197327.3-197393.6" + wire $8\sv_changed$next[0:0]$13853 + attribute \src "libresoc.v:196564.3-196631.6" + wire width 64 $9\core_data_i[63:0] + attribute \src "libresoc.v:196496.3-196563.6" + wire width 3 $9\core_wen[2:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + wire width 8 \$244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + wire width 8 \$245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" + wire width 3 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + wire \$253 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \$255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" + wire \$257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + wire \$259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" + wire width 3 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \$263 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \$265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + wire width 65 \$267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + wire width 65 \$268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" + wire width 65 \$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" + wire width 65 \$271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" - wire width 65 \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" - wire width 65 \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" - wire width 4 \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - wire \$99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:562" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + wire \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + wire \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + wire \$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + wire \$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + wire \$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + wire \$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + wire \$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + wire \$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + wire \$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" + wire width 65 \$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" + wire width 65 \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + wire width 32 \$95 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + wire width 32 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 342 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" @@ -385759,24 +402976,24 @@ module \ti wire output 333 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 343 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133" wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 360 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 392 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire \core_bigendian_i$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire \core_bigendian_i$10$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \core_cia__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \core_cia__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \core_core_core_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" @@ -385826,22 +403043,24 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 \core_core_core_fn_unit + wire width 14 \core_core_core_fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 \core_core_core_fn_unit$next + wire width 14 \core_core_core_fn_unit$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -385928,6 +403147,7 @@ module \ti attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \core_core_core_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" @@ -385965,21 +403185,21 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 8 \core_core_core_traptype$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \core_core_cr_in1 + wire width 7 \core_core_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \core_core_cr_in1$next + wire width 7 \core_core_cr_in1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \core_core_cr_in2 + wire width 7 \core_core_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \core_core_cr_in2$1 + wire width 7 \core_core_cr_in2$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \core_core_cr_in2$1$next + wire width 7 \core_core_cr_in2$1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \core_core_cr_in2$next + wire width 7 \core_core_cr_in2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -385989,17 +403209,21 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \core_core_cr_out + wire width 7 \core_core_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \core_core_cr_out$next + wire width 7 \core_core_cr_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_wr_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \core_core_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \core_core_dststep$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_ea + wire width 7 \core_core_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_ea$next + wire width 7 \core_core_ea$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -386028,38 +403252,42 @@ module \ti wire \core_core_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire \core_core_lk$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \core_core_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \core_core_maxvl$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \core_core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \core_core_pc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_reg1 + wire width 7 \core_core_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_reg1$next + wire width 7 \core_core_reg1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_reg2 + wire width 7 \core_core_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_reg2$next + wire width 7 \core_core_reg2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_reg3 + wire width 7 \core_core_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_reg3$next + wire width 7 \core_core_reg3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg3_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_rego + wire width 7 \core_core_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \core_core_rego$next + wire width 7 \core_core_rego$next attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -386125,6 +403353,9 @@ module \ti attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -386244,6 +403475,9 @@ module \ti attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -386294,15 +403528,31 @@ module \ti wire width 10 \core_core_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \core_core_spro$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \core_core_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \core_core_srcstep$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \core_core_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \core_core_subvl$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \core_core_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \core_core_svstep$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire \core_core_terminate_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \core_core_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \core_core_vl$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 \core_core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 \core_core_xer_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire \core_coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_cr_out_ok @@ -386316,25 +403566,27 @@ module \ti wire \core_cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire \core_cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \core_data_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \core_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \core_dec$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \core_dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_dmi__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_ea_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \core_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \core_eint$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_fasto1_ok @@ -386344,38 +403596,38 @@ module \ti wire \core_fasto2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_fasto2_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 \core_full_rd2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \core_full_rd2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 6 \core_full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \core_issue__addr$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \core_issue__addr$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" wire \core_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \core_ivalid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \core_msr__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \core_msr__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 32 \core_raw_insn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" @@ -386388,89 +403640,135 @@ module \ti wire \core_spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_spro_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \core_state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \core_state_nia_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \core_sv__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \core_sv__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire \core_sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire \core_sv_a_nz$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \core_wb_dcache_en - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \core_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \core_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \core_wen$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 2 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \cu_st__rel_o_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \cur_cur_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \cur_cur_dststep$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \cur_cur_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \cur_cur_maxvl$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \cur_cur_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \cur_cur_srcstep$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \cur_cur_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \cur_cur_subvl$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \cur_cur_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \cur_cur_svstep$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \cur_cur_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \cur_cur_vl$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:672" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:672" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:682" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:682" wire \d_xer_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \dbg_core_dbg_core_dbg_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \dbg_core_dbg_core_dbg_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \dbg_core_dbg_core_dbg_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \dbg_core_dbg_core_dbg_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \dbg_core_dbg_core_dbg_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \dbg_core_dbg_core_dbg_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dbg_core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dbg_core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" wire \dbg_core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" wire \dbg_core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" wire \dbg_core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" wire \dbg_d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 \dbg_d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire \dbg_d_cr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire \dbg_d_gpr_ack + wire \dbg_d_cr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" - wire width 7 \dbg_d_gpr_addr + wire \dbg_d_gpr_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 7 \dbg_d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 \dbg_d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire \dbg_d_gpr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" wire \dbg_d_xer_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 \dbg_d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire \dbg_d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" wire \dbg_dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" wire width 4 \dbg_dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \dbg_dmi_addr_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 4 \dbg_dmi_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" wire width 64 \dbg_dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \dbg_dmi_din$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 \dbg_dmi_dout + wire width 64 \dbg_dmi_din$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire width 64 \dbg_dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" wire \dbg_dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire \dbg_dmi_req_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_req_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" wire \dbg_dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" wire \dbg_dmi_we_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" wire \dbg_terminate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 9 \dbus__ack @@ -386492,24 +403790,24 @@ module \ti wire output 15 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \dec2_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire \dec2_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \dec2_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_cr_in1 + wire width 7 \dec2_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_cr_in2 + wire width 7 \dec2_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_cr_in2$12 + wire width 7 \dec2_cr_in2$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_cr_in2_ok$13 + wire \dec2_cr_in2_ok$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_cr_out + wire width 7 \dec2_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -386520,33 +403818,29 @@ module \ti wire width 8 \dec2_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \dec2_cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \dec2_cur_dec$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \dec2_cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \dec2_cur_eint$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dec2_cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dec2_cur_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dec2_cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dec2_cur_pc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_ea + wire width 7 \dec2_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \dec2_exc_$signal$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \dec2_exc_$signal$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$17 @@ -386556,6 +403850,10 @@ module \ti wire \dec2_exc_$signal$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec2_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -386573,20 +403871,22 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_fasto2_ok attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 \dec2_fn_unit + wire width 14 \dec2_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -386669,6 +403969,7 @@ module \ti attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \dec2_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" @@ -386681,26 +403982,28 @@ module \ti wire \dec2_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec2_raw_opcode_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_reg1 + wire width 7 \dec2_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_reg2 + wire width 7 \dec2_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_reg3 + wire width 7 \dec2_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_rego + wire width 7 \dec2_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rego_ok attribute \enum_base_type "SPR" @@ -386768,6 +404071,9 @@ module \ti attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -386883,6 +404189,9 @@ module \ti attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -386933,6 +404242,8 @@ module \ti wire width 10 \dec2_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec2_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 13 \dec2_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" @@ -386941,9 +404252,9 @@ module \ti wire width 3 \dec2_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 179 \eint_0__core__i @@ -386957,13 +404268,33 @@ module \ti wire output 181 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + wire \exec_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + wire \exec_fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:608" + wire \exec_insn_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" + wire \exec_insn_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" + wire \exec_pc_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" + wire \exec_pc_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + wire width 2 \fetch_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + wire width 2 \fetch_fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" + wire \fetch_insn_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" + wire \fetch_insn_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" + wire \fetch_pc_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" + wire \fetch_pc_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - wire width 2 \fsm_state$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - wire width 2 \fsm_state$133$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 188 \gpio_e10__core__i @@ -387172,39 +404503,35 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 344 \icp_wb__ack + wire output 376 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 350 \icp_wb__adr + wire width 28 input 382 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 345 \icp_wb__cyc + wire input 377 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 346 \icp_wb__dat_r + wire width 32 output 378 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 347 \icp_wb__dat_w + wire width 32 input 379 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 351 \icp_wb__sel + wire width 4 input 383 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 348 \icp_wb__stb + wire input 380 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 349 \icp_wb__we + wire input 381 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 357 \ics_wb__ack + wire output 389 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 352 \ics_wb__adr + wire width 28 input 384 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 354 \ics_wb__cyc + wire input 386 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 356 \ics_wb__dat_r + wire width 32 output 388 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 358 \ics_wb__dat_w + wire width 32 input 390 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 355 \ics_wb__stb + wire input 387 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 359 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" - wire width 32 \ilatch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" - wire width 32 \ilatch$next + wire input 391 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" @@ -387215,12 +404542,22 @@ module \ti wire width 64 \imem_f_instr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" wire \imem_f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:182859.7-182859.15" + attribute \src "libresoc.v:192354.7-192354.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 353 \int_level_i + wire width 16 input 385 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" + wire \is_last + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" + wire \is_svp64_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + wire width 3 \issue_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + wire width 3 \issue_fsm_state$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" @@ -387253,6 +404590,8 @@ module \ti wire output 337 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 338 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire \jtag_wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -387285,9 +404624,9 @@ module \ti wire input 81 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 236 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \mtwi_scl__core__o @@ -387305,29 +404644,45 @@ module \ti wire output 239 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 240 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" wire width 64 \new_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \new_svstate_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \new_svstate_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \new_svstate_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \new_svstate_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \new_svstate_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \new_svstate_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + wire width 7 \next_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542" wire \pc_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 7 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 6 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129" wire width 64 output 5 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513" wire \por_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \pwm_0__core__o @@ -387337,7 +404692,7 @@ module \ti wire input 88 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 243 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \sd0_clk__core__o @@ -387695,8 +405050,96 @@ module \ti wire input 146 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 301 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_0_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 346 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 347 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 344 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 348 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 349 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 351 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 345 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 350 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_1_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 354 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 355 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 352 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 356 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 357 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 359 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 353 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 358 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_2_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 362 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 363 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 360 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 364 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 365 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 367 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 361 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 366 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_3_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 370 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 371 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 368 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 372 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 373 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 375 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 369 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 374 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" + wire \sv_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" + wire \sv_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + wire width 64 \svstate + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \svstate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \svstate_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" + wire \svstate_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" + wire \svstate_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \ti_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + wire \update_svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" @@ -387707,8 +405150,30 @@ module \ti wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" - cell $add $add$libresoc.v:184954$13249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + cell $add $add$libresoc.v:194791$13361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:194791$13361_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + cell $add $add$libresoc.v:194864$13431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \cur_cur_srcstep + connect \B 1'1 + connect \Y $add$libresoc.v:194864$13431_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" + cell $add $add$libresoc.v:194877$13446 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -387716,10 +405181,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:184954$13249_Y + connect \Y $add$libresoc.v:194877$13446_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" - cell $add $add$libresoc.v:184962$13257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" + cell $add $add$libresoc.v:194910$13478 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -387727,158 +405192,419 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:184962$13257_Y + connect \Y $add$libresoc.v:194910$13478_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184937$13230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194796$13366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$97 - connect \B \$99 - connect \Y $and$libresoc.v:184937$13230_Y + connect \A \$106 + connect \B \$108 + connect \Y $and$libresoc.v:194796$13366_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184941$13234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194799$13369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$105 - connect \B \$107 - connect \Y $and$libresoc.v:184941$13234_Y + connect \A \$112 + connect \B \$114 + connect \Y $and$libresoc.v:194799$13369_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184944$13237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194805$13374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$111 - connect \B \$113 - connect \Y $and$libresoc.v:184944$13237_Y + connect \A \$124 + connect \B \$126 + connect \Y $and$libresoc.v:194805$13374_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:184961$13256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194808$13377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_cu_st__rel_o - connect \B \$32 - connect \Y $and$libresoc.v:184961$13256_Y + connect \A \$130 + connect \B \$132 + connect \Y $and$libresoc.v:194808$13377_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184970$13265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $and $and$libresoc.v:194810$13379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \$51 - connect \Y $and$libresoc.v:184970$13265_Y + connect \A \is_svp64_mode + connect \B \$136 + connect \Y $and$libresoc.v:194810$13379_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" - cell $and $and$libresoc.v:184971$13266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194813$13382 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$140 + connect \B \$142 + connect \Y $and$libresoc.v:194813$13382_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194819$13387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$152 + connect \B \$154 + connect \Y $and$libresoc.v:194819$13387_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194822$13390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$158 + connect \B \$160 + connect \Y $and$libresoc.v:194822$13390_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194825$13393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$164 + connect \B \$166 + connect \Y $and$libresoc.v:194825$13393_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194828$13396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$170 + connect \B \$172 + connect \Y $and$libresoc.v:194828$13396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194831$13399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$176 + connect \B \$178 + connect \Y $and$libresoc.v:194831$13399_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194834$13402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$182 + connect \B \$184 + connect \Y $and$libresoc.v:194834$13402_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" + cell $and $and$libresoc.v:194835$13403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 - connect \Y $and$libresoc.v:184971$13266_Y + connect \Y $and$libresoc.v:194835$13403_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184978$13273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194839$13407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$65 - connect \B \$67 - connect \Y $and$libresoc.v:184978$13273_Y + connect \A \$192 + connect \B \$194 + connect \Y $and$libresoc.v:194839$13407_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184981$13276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194842$13410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$71 - connect \B \$73 - connect \Y $and$libresoc.v:184981$13276_Y + connect \A \$198 + connect \B \$200 + connect \Y $and$libresoc.v:194842$13410_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184984$13279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194848$13415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$77 - connect \B \$79 - connect \Y $and$libresoc.v:184984$13279_Y + connect \A \$210 + connect \B \$212 + connect \Y $and$libresoc.v:194848$13415_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184987$13282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194851$13418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$83 - connect \B \$85 - connect \Y $and$libresoc.v:184987$13282_Y + connect \A \$216 + connect \B \$218 + connect \Y $and$libresoc.v:194851$13418_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:184990$13285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" + cell $and $and$libresoc.v:194852$13419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_state_nia_wen + connect \B 3'100 + connect \Y $and$libresoc.v:194852$13419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $and $and$libresoc.v:194855$13422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$89 - connect \B \$91 - connect \Y $and$libresoc.v:184990$13285_Y + connect \A \is_svp64_mode + connect \B \$226 + connect \Y $and$libresoc.v:194855$13422_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194859$13426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$232 + connect \B \$234 + connect \Y $and$libresoc.v:194859$13426_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194863$13430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$238 + connect \B \$240 + connect \Y $and$libresoc.v:194863$13430_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194867$13434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$247 + connect \B \$249 + connect \Y $and$libresoc.v:194867$13434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:194882$13451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_cu_st__rel_o + connect \B \$34 + connect \Y $and$libresoc.v:194882$13451_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194888$13458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:194888$13458_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $and $and$libresoc.v:194890$13460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_svp64_mode + connect \B \$50 + connect \Y $and$libresoc.v:194890$13460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194893$13463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$54 + connect \B \$56 + connect \Y $and$libresoc.v:194893$13463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194899$13468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$66 + connect \B \$68 + connect \Y $and$libresoc.v:194899$13468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $and $and$libresoc.v:194901$13470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_svp64_mode + connect \B \$72 + connect \Y $and$libresoc.v:194901$13470_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:184951$13244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194904$13473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$76 + connect \B \$78 + connect \Y $and$libresoc.v:194904$13473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $eq $eq$libresoc.v:194809$13378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_cur_vl + connect \B 1'0 + connect \Y $eq$libresoc.v:194809$13378_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $eq $eq$libresoc.v:194854$13421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_cur_vl + connect \B 1'0 + connect \Y $eq$libresoc.v:194854$13421_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + cell $eq $eq$libresoc.v:194868$13435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \next_srcstep + connect \B \cur_cur_vl + connect \Y $eq$libresoc.v:194868$13435_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $eq $eq$libresoc.v:194889$13459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_cur_vl + connect \B 1'0 + connect \Y $eq$libresoc.v:194889$13459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $eq $eq$libresoc.v:194900$13469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_cur_vl + connect \B 1'0 + connect \Y $eq$libresoc.v:194900$13469_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $extend$libresoc.v:194873$13440 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:184951$13244_Y + connect \Y $extend$libresoc.v:194873$13440_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:184952$13246 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $extend$libresoc.v:194874$13442 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:184952$13246_Y + connect \Y $extend$libresoc.v:194874$13442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:194885$13454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \svstate_i + connect \Y $extend$libresoc.v:194885$13454_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:184946$13239 + cell $mul $mul$libresoc.v:194792$13362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] + connect \A \$100 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:184946$13239_Y + connect \Y $mul$libresoc.v:194792$13362_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:184948$13241 + cell $mul $mul$libresoc.v:194911$13479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387886,10 +405612,21 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:184948$13241_Y + connect \Y $mul$libresoc.v:194911$13479_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" - cell $ne $ne$libresoc.v:184950$13243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + cell $ne $ne$libresoc.v:194861$13428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B 1'0 + connect \Y $ne$libresoc.v:194861$13428_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" + cell $ne $ne$libresoc.v:194870$13437 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387897,272 +405634,503 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:184950$13243_Y + connect \Y $ne$libresoc.v:194870$13437_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - cell $ne $ne$libresoc.v:184955$13250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $ne $ne$libresoc.v:194880$13449 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \delay - connect \B 1'0 - connect \Y $ne$libresoc.v:184955$13250_Y + connect \B \$30 + connect \Y $ne$libresoc.v:194880$13449_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" - cell $ne $ne$libresoc.v:184959$13254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194794$13364 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \delay - connect \B \$28 - connect \Y $ne$libresoc.v:184959$13254_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194794$13364_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184936$13229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194795$13365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184936$13229_Y + connect \Y $not$libresoc.v:194795$13365_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:184938$13231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194797$13367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:184938$13231_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194797$13367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194798$13368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194798$13368_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184939$13232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194803$13372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184939$13232_Y + connect \Y $not$libresoc.v:194803$13372_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184940$13233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194804$13373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184940$13233_Y + connect \Y $not$libresoc.v:194804$13373_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184942$13235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194806$13375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184942$13235_Y + connect \Y $not$libresoc.v:194806$13375_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184943$13236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194807$13376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184943$13236_Y + connect \Y $not$libresoc.v:194807$13376_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - cell $not $not$libresoc.v:184945$13238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194811$13380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:184945$13238_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194811$13380_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:184960$13255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194812$13381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:184960$13255_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194812$13381_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" - cell $not $not$libresoc.v:184963$13258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194817$13385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_i_ok - connect \Y $not$libresoc.v:184963$13258_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194817$13385_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:184964$13259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194818$13386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:184964$13259_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194818$13386_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - cell $not $not$libresoc.v:184965$13260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194820$13388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:184965$13260_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194820$13388_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:184966$13261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194821$13389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:184966$13261_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194821$13389_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - cell $not $not$libresoc.v:184967$13262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194823$13391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:184967$13262_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194823$13391_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184968$13263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194824$13392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194824$13392_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194826$13394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184968$13263_Y + connect \Y $not$libresoc.v:194826$13394_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184969$13264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194827$13395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184969$13264_Y + connect \Y $not$libresoc.v:194827$13395_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:184973$13268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194829$13397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:184973$13268_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194829$13397_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:184974$13269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194830$13398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:184974$13269_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194830$13398_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194832$13400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194832$13400_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194833$13401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194833$13401_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194837$13405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194837$13405_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194838$13406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194838$13406_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:184975$13270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194840$13408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194840$13408_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194841$13409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194841$13409_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194846$13413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194846$13413_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194847$13414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194847$13414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194849$13416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194849$13416_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194850$13417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194850$13417_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $not $not$libresoc.v:194856$13423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:184975$13270_Y + connect \Y $not$libresoc.v:194856$13423_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184976$13271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194857$13424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184976$13271_Y + connect \Y $not$libresoc.v:194857$13424_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184977$13272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194858$13425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184977$13272_Y + connect \Y $not$libresoc.v:194858$13425_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184979$13274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194860$13427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184979$13274_Y + connect \Y $not$libresoc.v:194860$13427_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184980$13275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194862$13429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184980$13275_Y + connect \Y $not$libresoc.v:194862$13429_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184982$13277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194865$13432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184982$13277_Y + connect \Y $not$libresoc.v:194865$13432_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184983$13278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194866$13433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184983$13278_Y + connect \Y $not$libresoc.v:194866$13433_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $not $not$libresoc.v:194871$13438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:194871$13438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $not $not$libresoc.v:194872$13439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:194872$13439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:194881$13450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:194881$13450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" + cell $not $not$libresoc.v:194883$13452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_i_ok + connect \Y $not$libresoc.v:194883$13452_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184985$13280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:562" + cell $not $not$libresoc.v:194884$13453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \svstate_i_ok + connect \Y $not$libresoc.v:194884$13453_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194886$13456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184985$13280_Y + connect \Y $not$libresoc.v:194886$13456_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184986$13281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194887$13457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184986$13281_Y + connect \Y $not$libresoc.v:194887$13457_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184988$13283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194891$13461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184988$13283_Y + connect \Y $not$libresoc.v:194891$13461_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184989$13284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194892$13462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:184989$13284_Y + connect \Y $not$libresoc.v:194892$13462_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - cell $not $not$libresoc.v:184991$13286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194897$13466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:184991$13286_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194897$13466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194898$13467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194898$13467_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:184992$13287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194902$13471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:184992$13287_Y + connect \Y $not$libresoc.v:194902$13471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194903$13472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194903$13472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + cell $not $not$libresoc.v:194908$13476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:194908$13476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + cell $not $not$libresoc.v:194909$13477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:194909$13477_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" - cell $or $or$libresoc.v:184957$13252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194800$13370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \B \sv_changed + connect \Y $or$libresoc.v:194800$13370_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194802$13371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$120 + connect \B \is_last + connect \Y $or$libresoc.v:194802$13371_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194814$13383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \B \sv_changed + connect \Y $or$libresoc.v:194814$13383_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194816$13384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$148 + connect \B \is_last + connect \Y $or$libresoc.v:194816$13384_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194843$13411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \B \sv_changed + connect \Y $or$libresoc.v:194843$13411_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194845$13412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$206 + connect \B \is_last + connect \Y $or$libresoc.v:194845$13412_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $or $or$libresoc.v:194878$13447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388170,67 +406138,135 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:184957$13252_Y + connect \Y $or$libresoc.v:194878$13447_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" - cell $or $or$libresoc.v:184958$13253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $or $or$libresoc.v:194879$13448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$26 + connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:184958$13253_Y + connect \Y $or$libresoc.v:194879$13448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194894$13464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \B \sv_changed + connect \Y $or$libresoc.v:194894$13464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194896$13465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$62 + connect \B \is_last + connect \Y $or$libresoc.v:194896$13465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194905$13474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \B \sv_changed + connect \Y $or$libresoc.v:194905$13474_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:184951$13245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194907$13475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$84 + connect \B \is_last + connect \Y $or$libresoc.v:194907$13475_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:194869$13436 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:184951$13244_Y - connect \Y $pos$libresoc.v:184951$13245_Y + connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + connect \Y $pos$libresoc.v:194869$13436_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:184952$13247 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:194873$13441 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:184952$13246_Y - connect \Y $pos$libresoc.v:184952$13247_Y + connect \A $extend$libresoc.v:194873$13440_Y + connect \Y $pos$libresoc.v:194873$13441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:194874$13443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:194874$13442_Y + connect \Y $pos$libresoc.v:194874$13443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:194885$13455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:194885$13454_Y + connect \Y $pos$libresoc.v:194885$13455_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:184972$13267 + cell $reduce_or $reduce_or$libresoc.v:194836$13404 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$56 - connect \Y $reduce_or$libresoc.v:184972$13267_Y + connect \A \$189 + connect \Y $reduce_or$libresoc.v:194836$13404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:194853$13420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$223 + connect \Y $reduce_or$libresoc.v:194853$13420_Y end - attribute \src "libresoc.v:184947.19-184947.42" - cell $shr $shr$libresoc.v:184947$13240 + attribute \src "libresoc.v:194793.18-194793.41" + cell $shr $shr$libresoc.v:194793$13363 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o - connect \B \$120 - connect \Y $shr$libresoc.v:184947$13240_Y + connect \B \$103 + connect \Y $shr$libresoc.v:194793$13363_Y end - attribute \src "libresoc.v:184949.19-184949.42" - cell $shr $shr$libresoc.v:184949$13242 + attribute \src "libresoc.v:194912.18-194912.40" + cell $shr $shr$libresoc.v:194912$13480 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o - connect \B \$124 - connect \Y $shr$libresoc.v:184949$13242_Y + connect \B \$96 + connect \Y $shr$libresoc.v:194912$13480_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393" - cell $sub $sub$libresoc.v:184953$13248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + cell $sub $sub$libresoc.v:194875$13444 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -388238,10 +406274,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:184953$13248_Y + connect \Y $sub$libresoc.v:194875$13444_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" - cell $sub $sub$libresoc.v:184956$13251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" + cell $sub $sub$libresoc.v:194876$13445 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -388249,10 +406285,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:184956$13251_Y + connect \Y $sub$libresoc.v:194876$13445_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:185165.8-185258.4" + attribute \src "libresoc.v:195121.8-195219.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -388316,6 +406352,7 @@ module \ti connect \cu_st__go_i \core_cu_st__go_i connect \cu_st__rel_o \core_cu_st__rel_o connect \data_i \core_data_i + connect \data_i$11 \core_data_i$12 connect \dbus__ack \dbus__ack connect \dbus__adr \dbus__adr connect \dbus__cyc \dbus__cyc @@ -388333,7 +406370,7 @@ module \ti connect \full_rd__data_o \core_full_rd__data_o connect \full_rd__ren \core_full_rd__ren connect \issue__addr \core_issue__addr - connect \issue__addr$10 \core_issue__addr$11 + connect \issue__addr$12 \core_issue__addr$13 connect \issue__data_i \core_issue__data_i connect \issue__data_o \core_issue__data_o connect \issue__ren \core_issue__ren @@ -388344,13 +406381,23 @@ module \ti connect \msr__ren \core_msr__ren connect \raw_insn_i \core_raw_insn_i connect \state_nia_wen \core_state_nia_wen + connect \sv__data_o \core_sv__data_o + connect \sv__ren \core_sv__ren + connect \sv_a_nz \core_sv_a_nz connect \wb_dcache_en \core_wb_dcache_en connect \wen \core_wen + connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:185259.7-185284.4" + attribute \src "libresoc.v:195220.7-195251.4" cell \dbg \dbg connect \clk \clk + connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep + connect \core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_maxvl + connect \core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_srcstep + connect \core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_subvl + connect \core_dbg_core_dbg_svstep \dbg_core_dbg_core_dbg_svstep + connect \core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_vl connect \core_dbg_msr \dbg_core_dbg_msr connect \core_dbg_pc \dbg_core_dbg_pc connect \core_rst_o \dbg_core_rst_o @@ -388376,7 +406423,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:185285.8-185351.4" + attribute \src "libresoc.v:195252.8-195319.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -388384,9 +406431,9 @@ module \ti connect \cr_in1 \dec2_cr_in1 connect \cr_in1_ok \dec2_cr_in1_ok connect \cr_in2 \dec2_cr_in2 - connect \cr_in2$1 \dec2_cr_in2$12 + connect \cr_in2$1 \dec2_cr_in2$14 connect \cr_in2_ok \dec2_cr_in2_ok - connect \cr_in2_ok$2 \dec2_cr_in2_ok$13 + connect \cr_in2_ok$2 \dec2_cr_in2_ok$15 connect \cr_out \dec2_cr_out connect \cr_out_ok \dec2_cr_out_ok connect \cr_rd \dec2_cr_rd @@ -388400,13 +406447,13 @@ module \ti connect \ea \dec2_ea connect \ea_ok \dec2_ea_ok connect \exc_$signal \dec2_exc_$signal - connect \exc_$signal$3 \dec2_exc_$signal$14 - connect \exc_$signal$4 \dec2_exc_$signal$15 - connect \exc_$signal$5 \dec2_exc_$signal$16 - connect \exc_$signal$6 \dec2_exc_$signal$17 - connect \exc_$signal$7 \dec2_exc_$signal$18 - connect \exc_$signal$8 \dec2_exc_$signal$19 - connect \exc_$signal$9 \dec2_exc_$signal$20 + connect \exc_$signal$3 \dec2_exc_$signal$16 + connect \exc_$signal$4 \dec2_exc_$signal$17 + connect \exc_$signal$5 \dec2_exc_$signal$18 + connect \exc_$signal$6 \dec2_exc_$signal$19 + connect \exc_$signal$7 \dec2_exc_$signal$20 + connect \exc_$signal$8 \dec2_exc_$signal$21 + connect \exc_$signal$9 \dec2_exc_$signal$22 connect \fast1 \dec2_fast1 connect \fast1_ok \dec2_fast1_ok connect \fast2 \dec2_fast2 @@ -388439,13 +406486,14 @@ module \ti connect \spr1_ok \dec2_spr1_ok connect \spro \dec2_spro connect \spro_ok \dec2_spro_ok + connect \sv_a_nz \dec2_sv_a_nz connect \trapaddr \dec2_trapaddr connect \traptype \dec2_traptype connect \xer_in \dec2_xer_in connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:185352.8-185368.4" + attribute \src "libresoc.v:195320.8-195336.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -388464,7 +406512,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:185369.8-185700.4" + attribute \src "libresoc.v:195337.8-195669.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -388796,9 +406844,70 @@ module \ti connect \sdr_we_n__pad__o \sdr_we_n__pad__o connect \wb_dcache_en \core_wb_dcache_en connect \wb_icache_en \imem_wb_icache_en + connect \wb_sram_en \jtag_wb_sram_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195670.12-195682.4" + cell \sram4k_0 \sram4k_0 + connect \clk \clk + connect \enable \sram4k_0_enable + connect \rst \rst + connect \sram4k_0_wb__ack \sram4k_0_wb__ack + connect \sram4k_0_wb__adr \sram4k_0_wb__adr + connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc + connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r + connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w + connect \sram4k_0_wb__sel \sram4k_0_wb__sel + connect \sram4k_0_wb__stb \sram4k_0_wb__stb + connect \sram4k_0_wb__we \sram4k_0_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195683.12-195695.4" + cell \sram4k_1 \sram4k_1 + connect \clk \clk + connect \enable \sram4k_1_enable + connect \rst \rst + connect \sram4k_1_wb__ack \sram4k_1_wb__ack + connect \sram4k_1_wb__adr \sram4k_1_wb__adr + connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc + connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r + connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w + connect \sram4k_1_wb__sel \sram4k_1_wb__sel + connect \sram4k_1_wb__stb \sram4k_1_wb__stb + connect \sram4k_1_wb__we \sram4k_1_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195696.12-195708.4" + cell \sram4k_2 \sram4k_2 + connect \clk \clk + connect \enable \sram4k_2_enable + connect \rst \rst + connect \sram4k_2_wb__ack \sram4k_2_wb__ack + connect \sram4k_2_wb__adr \sram4k_2_wb__adr + connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc + connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r + connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w + connect \sram4k_2_wb__sel \sram4k_2_wb__sel + connect \sram4k_2_wb__stb \sram4k_2_wb__stb + connect \sram4k_2_wb__we \sram4k_2_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:185701.12-185715.4" + attribute \src "libresoc.v:195709.12-195721.4" + cell \sram4k_3 \sram4k_3 + connect \clk \clk + connect \enable \sram4k_3_enable + connect \rst \rst + connect \sram4k_3_wb__ack \sram4k_3_wb__ack + connect \sram4k_3_wb__adr \sram4k_3_wb__adr + connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc + connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r + connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w + connect \sram4k_3_wb__sel \sram4k_3_wb__sel + connect \sram4k_3_wb__stb \sram4k_3_wb__stb + connect \sram4k_3_wb__we \sram4k_3_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195722.12-195736.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -388815,7 +406924,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:185716.12-185729.4" + attribute \src "libresoc.v:195737.12-195750.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -388830,1312 +406939,1582 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:182859.7-182859.20" - process $proc$libresoc.v:182859$13788 + attribute \src "libresoc.v:192354.7-192354.20" + process $proc$libresoc.v:192354$14061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182995.13-182995.33" - process $proc$libresoc.v:182995$13789 + attribute \src "libresoc.v:192624.13-192624.33" + process $proc$libresoc.v:192624$14062 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:183001.7-183001.35" - process $proc$libresoc.v:183001$13790 + attribute \src "libresoc.v:192630.7-192630.35" + process $proc$libresoc.v:192630$14063 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13791 1'0 + assign $0\core_bigendian_i$10[0:0]$14064 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13791 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14064 end - attribute \src "libresoc.v:183009.14-183009.55" - process $proc$libresoc.v:183009$13792 + attribute \src "libresoc.v:192638.14-192638.55" + process $proc$libresoc.v:192638$14065 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:183013.13-183013.41" - process $proc$libresoc.v:183013$13793 + attribute \src "libresoc.v:192642.13-192642.41" + process $proc$libresoc.v:192642$14066 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:183017.7-183017.37" - process $proc$libresoc.v:183017$13794 + attribute \src "libresoc.v:192646.7-192646.37" + process $proc$libresoc.v:192646$14067 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:183021.13-183021.41" - process $proc$libresoc.v:183021$13795 + attribute \src "libresoc.v:192650.13-192650.41" + process $proc$libresoc.v:192650$14068 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:183025.7-183025.42" - process $proc$libresoc.v:183025$13796 + attribute \src "libresoc.v:192654.7-192654.42" + process $proc$libresoc.v:192654$14069 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13797 1'0 + assign $0\core_core_core_exc_$signal[0:0]$14070 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13797 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14070 end - attribute \src "libresoc.v:183027.7-183027.44" - process $proc$libresoc.v:183027$13798 + attribute \src "libresoc.v:192656.7-192656.44" + process $proc$libresoc.v:192656$14071 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13799 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$14072 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13799 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14072 end - attribute \src "libresoc.v:183031.7-183031.44" - process $proc$libresoc.v:183031$13800 + attribute \src "libresoc.v:192660.7-192660.44" + process $proc$libresoc.v:192660$14073 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13801 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$14074 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13801 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14074 end - attribute \src "libresoc.v:183035.7-183035.44" - process $proc$libresoc.v:183035$13802 + attribute \src "libresoc.v:192664.7-192664.44" + process $proc$libresoc.v:192664$14075 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13803 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$14076 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13803 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14076 end - attribute \src "libresoc.v:183039.7-183039.44" - process $proc$libresoc.v:183039$13804 + attribute \src "libresoc.v:192668.7-192668.44" + process $proc$libresoc.v:192668$14077 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13805 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$14078 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13805 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14078 end - attribute \src "libresoc.v:183043.7-183043.44" - process $proc$libresoc.v:183043$13806 + attribute \src "libresoc.v:192672.7-192672.44" + process $proc$libresoc.v:192672$14079 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13807 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$14080 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13807 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14080 end - attribute \src "libresoc.v:183047.7-183047.44" - process $proc$libresoc.v:183047$13808 + attribute \src "libresoc.v:192676.7-192676.44" + process $proc$libresoc.v:192676$14081 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13809 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$14082 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13809 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14082 end - attribute \src "libresoc.v:183051.7-183051.44" - process $proc$libresoc.v:183051$13810 + attribute \src "libresoc.v:192680.7-192680.44" + process $proc$libresoc.v:192680$14083 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13811 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$14084 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13811 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14084 end - attribute \src "libresoc.v:183070.14-183070.46" - process $proc$libresoc.v:183070$13812 + attribute \src "libresoc.v:192701.14-192701.47" + process $proc$libresoc.v:192701$14085 assign { } { } - assign $1\core_core_core_fn_unit[11:0] 12'000000000000 + assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init - update \core_core_core_fn_unit $1\core_core_core_fn_unit[11:0] + update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:183078.13-183078.46" - process $proc$libresoc.v:183078$13813 + attribute \src "libresoc.v:192709.13-192709.46" + process $proc$libresoc.v:192709$14086 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:183082.14-183082.41" - process $proc$libresoc.v:183082$13814 + attribute \src "libresoc.v:192713.14-192713.41" + process $proc$libresoc.v:192713$14087 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:183160.13-183160.45" - process $proc$libresoc.v:183160$13815 + attribute \src "libresoc.v:192792.13-192792.45" + process $proc$libresoc.v:192792$14088 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:183164.7-183164.37" - process $proc$libresoc.v:183164$13816 + attribute \src "libresoc.v:192796.7-192796.37" + process $proc$libresoc.v:192796$14089 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:183168.14-183168.55" - process $proc$libresoc.v:183168$13817 + attribute \src "libresoc.v:192800.14-192800.55" + process $proc$libresoc.v:192800$14090 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:183172.7-183172.31" - process $proc$libresoc.v:183172$13818 + attribute \src "libresoc.v:192804.7-192804.31" + process $proc$libresoc.v:192804$14091 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:183176.7-183176.34" - process $proc$libresoc.v:183176$13819 + attribute \src "libresoc.v:192808.7-192808.34" + process $proc$libresoc.v:192808$14092 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:183180.7-183180.31" - process $proc$libresoc.v:183180$13820 + attribute \src "libresoc.v:192812.7-192812.31" + process $proc$libresoc.v:192812$14093 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:183184.7-183184.34" - process $proc$libresoc.v:183184$13821 + attribute \src "libresoc.v:192816.7-192816.34" + process $proc$libresoc.v:192816$14094 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:183188.14-183188.48" - process $proc$libresoc.v:183188$13822 + attribute \src "libresoc.v:192820.14-192820.48" + process $proc$libresoc.v:192820$14095 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:183192.13-183192.44" - process $proc$libresoc.v:183192$13823 + attribute \src "libresoc.v:192824.13-192824.44" + process $proc$libresoc.v:192824$14096 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:183196.13-183196.36" - process $proc$libresoc.v:183196$13824 + attribute \src "libresoc.v:192828.13-192828.37" + process $proc$libresoc.v:192828$14097 assign { } { } - assign $1\core_core_cr_in1[2:0] 3'000 + assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init - update \core_core_cr_in1 $1\core_core_cr_in1[2:0] + update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:183200.7-183200.33" - process $proc$libresoc.v:183200$13825 + attribute \src "libresoc.v:192832.7-192832.33" + process $proc$libresoc.v:192832$14098 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:183204.13-183204.36" - process $proc$libresoc.v:183204$13826 + attribute \src "libresoc.v:192836.13-192836.37" + process $proc$libresoc.v:192836$14099 assign { } { } - assign $1\core_core_cr_in2[2:0] 3'000 + assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init - update \core_core_cr_in2 $1\core_core_cr_in2[2:0] + update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:183206.13-183206.40" - process $proc$libresoc.v:183206$13827 + attribute \src "libresoc.v:192838.13-192838.41" + process $proc$libresoc.v:192838$14100 assign { } { } - assign $0\core_core_cr_in2$1[2:0]$13828 3'000 + assign $0\core_core_cr_in2$1[6:0]$14101 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13828 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14101 end - attribute \src "libresoc.v:183212.7-183212.33" - process $proc$libresoc.v:183212$13829 + attribute \src "libresoc.v:192844.7-192844.33" + process $proc$libresoc.v:192844$14102 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:183214.7-183214.37" - process $proc$libresoc.v:183214$13830 + attribute \src "libresoc.v:192846.7-192846.37" + process $proc$libresoc.v:192846$14103 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13831 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$14104 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13831 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14104 end - attribute \src "libresoc.v:183220.13-183220.36" - process $proc$libresoc.v:183220$13832 + attribute \src "libresoc.v:192852.13-192852.37" + process $proc$libresoc.v:192852$14105 assign { } { } - assign $1\core_core_cr_out[2:0] 3'000 + assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init - update \core_core_cr_out $1\core_core_cr_out[2:0] + update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:183224.7-183224.32" - process $proc$libresoc.v:183224$13833 + attribute \src "libresoc.v:192856.7-192856.32" + process $proc$libresoc.v:192856$14106 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:183228.13-183228.33" - process $proc$libresoc.v:183228$13834 + attribute \src "libresoc.v:192860.13-192860.38" + process $proc$libresoc.v:192860$14107 + assign { } { } + assign $1\core_core_dststep[6:0] 7'0000000 + sync always + sync init + update \core_core_dststep $1\core_core_dststep[6:0] + end + attribute \src "libresoc.v:192864.13-192864.33" + process $proc$libresoc.v:192864$14108 assign { } { } - assign $1\core_core_ea[4:0] 5'00000 + assign $1\core_core_ea[6:0] 7'0000000 sync always sync init - update \core_core_ea $1\core_core_ea[4:0] + update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:183232.13-183232.35" - process $proc$libresoc.v:183232$13835 + attribute \src "libresoc.v:192868.13-192868.35" + process $proc$libresoc.v:192868$14109 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:183236.7-183236.32" - process $proc$libresoc.v:183236$13836 + attribute \src "libresoc.v:192872.7-192872.32" + process $proc$libresoc.v:192872$14110 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:183240.13-183240.35" - process $proc$libresoc.v:183240$13837 + attribute \src "libresoc.v:192876.13-192876.35" + process $proc$libresoc.v:192876$14111 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:183244.7-183244.32" - process $proc$libresoc.v:183244$13838 + attribute \src "libresoc.v:192880.7-192880.32" + process $proc$libresoc.v:192880$14112 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:183248.13-183248.36" - process $proc$libresoc.v:183248$13839 + attribute \src "libresoc.v:192884.13-192884.36" + process $proc$libresoc.v:192884$14113 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:183252.13-183252.36" - process $proc$libresoc.v:183252$13840 + attribute \src "libresoc.v:192888.13-192888.36" + process $proc$libresoc.v:192888$14114 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:183256.7-183256.26" - process $proc$libresoc.v:183256$13841 + attribute \src "libresoc.v:192892.7-192892.26" + process $proc$libresoc.v:192892$14115 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:183260.14-183260.49" - process $proc$libresoc.v:183260$13842 + attribute \src "libresoc.v:192896.13-192896.36" + process $proc$libresoc.v:192896$14116 + assign { } { } + assign $1\core_core_maxvl[6:0] 7'0000000 + sync always + sync init + update \core_core_maxvl $1\core_core_maxvl[6:0] + end + attribute \src "libresoc.v:192900.14-192900.49" + process $proc$libresoc.v:192900$14117 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:183264.13-183264.35" - process $proc$libresoc.v:183264$13843 + attribute \src "libresoc.v:192904.13-192904.35" + process $proc$libresoc.v:192904$14118 assign { } { } - assign $1\core_core_reg1[4:0] 5'00000 + assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init - update \core_core_reg1 $1\core_core_reg1[4:0] + update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:183268.7-183268.31" - process $proc$libresoc.v:183268$13844 + attribute \src "libresoc.v:192908.7-192908.31" + process $proc$libresoc.v:192908$14119 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:183272.13-183272.35" - process $proc$libresoc.v:183272$13845 + attribute \src "libresoc.v:192912.13-192912.35" + process $proc$libresoc.v:192912$14120 assign { } { } - assign $1\core_core_reg2[4:0] 5'00000 + assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init - update \core_core_reg2 $1\core_core_reg2[4:0] + update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:183276.7-183276.31" - process $proc$libresoc.v:183276$13846 + attribute \src "libresoc.v:192916.7-192916.31" + process $proc$libresoc.v:192916$14121 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:183280.13-183280.35" - process $proc$libresoc.v:183280$13847 + attribute \src "libresoc.v:192920.13-192920.35" + process $proc$libresoc.v:192920$14122 assign { } { } - assign $1\core_core_reg3[4:0] 5'00000 + assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init - update \core_core_reg3 $1\core_core_reg3[4:0] + update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:183284.7-183284.31" - process $proc$libresoc.v:183284$13848 + attribute \src "libresoc.v:192924.7-192924.31" + process $proc$libresoc.v:192924$14123 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:183288.13-183288.35" - process $proc$libresoc.v:183288$13849 + attribute \src "libresoc.v:192928.13-192928.35" + process $proc$libresoc.v:192928$14124 assign { } { } - assign $1\core_core_rego[4:0] 5'00000 + assign $1\core_core_rego[6:0] 7'0000000 sync always sync init - update \core_core_rego $1\core_core_rego[4:0] + update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:183403.13-183403.37" - process $proc$libresoc.v:183403$13850 + attribute \src "libresoc.v:193046.13-193046.37" + process $proc$libresoc.v:193046$14125 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:183407.7-183407.31" - process $proc$libresoc.v:183407$13851 + attribute \src "libresoc.v:193050.7-193050.31" + process $proc$libresoc.v:193050$14126 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:183522.13-183522.37" - process $proc$libresoc.v:183522$13852 + attribute \src "libresoc.v:193168.13-193168.37" + process $proc$libresoc.v:193168$14127 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:183528.13-183528.36" - process $proc$libresoc.v:183528$13853 + attribute \src "libresoc.v:193172.13-193172.38" + process $proc$libresoc.v:193172$14128 + assign { } { } + assign $1\core_core_srcstep[6:0] 7'0000000 + sync always + sync init + update \core_core_srcstep $1\core_core_srcstep[6:0] + end + attribute \src "libresoc.v:193176.13-193176.35" + process $proc$libresoc.v:193176$14129 + assign { } { } + assign $1\core_core_subvl[1:0] 2'00 + sync always + sync init + update \core_core_subvl $1\core_core_subvl[1:0] + end + attribute \src "libresoc.v:193180.13-193180.36" + process $proc$libresoc.v:193180$14130 + assign { } { } + assign $1\core_core_svstep[1:0] 2'00 + sync always + sync init + update \core_core_svstep $1\core_core_svstep[1:0] + end + attribute \src "libresoc.v:193186.13-193186.33" + process $proc$libresoc.v:193186$14131 + assign { } { } + assign $1\core_core_vl[6:0] 7'0000000 + sync always + sync init + update \core_core_vl $1\core_core_vl[6:0] + end + attribute \src "libresoc.v:193190.13-193190.36" + process $proc$libresoc.v:193190$14132 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:183536.7-183536.28" - process $proc$libresoc.v:183536$13854 + attribute \src "libresoc.v:193198.7-193198.28" + process $proc$libresoc.v:193198$14133 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:183550.14-183550.45" - process $proc$libresoc.v:183550$13855 + attribute \src "libresoc.v:193214.14-193214.45" + process $proc$libresoc.v:193214$14134 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:183560.7-183560.24" - process $proc$libresoc.v:183560$13856 + attribute \src "libresoc.v:193224.7-193224.24" + process $proc$libresoc.v:193224$14135 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:183564.7-183564.23" - process $proc$libresoc.v:183564$13857 + attribute \src "libresoc.v:193228.7-193228.23" + process $proc$libresoc.v:193228$14136 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:183568.7-183568.28" - process $proc$libresoc.v:183568$13858 + attribute \src "libresoc.v:193232.7-193232.28" + process $proc$libresoc.v:193232$14137 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:183572.7-183572.28" - process $proc$libresoc.v:183572$13859 + attribute \src "libresoc.v:193236.7-193236.28" + process $proc$libresoc.v:193236$14138 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:183600.14-183600.45" - process $proc$libresoc.v:183600$13860 + attribute \src "libresoc.v:193264.14-193264.45" + process $proc$libresoc.v:193264$14139 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:183608.14-183608.37" - process $proc$libresoc.v:183608$13861 + attribute \src "libresoc.v:193272.14-193272.37" + process $proc$libresoc.v:193272$14140 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:183612.7-183612.26" - process $proc$libresoc.v:183612$13862 + attribute \src "libresoc.v:193276.7-193276.26" + process $proc$libresoc.v:193276$14141 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:183616.7-183616.26" - process $proc$libresoc.v:183616$13863 + attribute \src "libresoc.v:193280.7-193280.26" + process $proc$libresoc.v:193280$14142 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:183628.7-183628.26" - process $proc$libresoc.v:183628$13864 + attribute \src "libresoc.v:193292.7-193292.26" + process $proc$libresoc.v:193292$14143 + assign { } { } + assign $1\core_sv_a_nz[0:0] 1'0 + sync always + sync init + update \core_sv_a_nz $1\core_sv_a_nz[0:0] + end + attribute \src "libresoc.v:193302.7-193302.26" + process $proc$libresoc.v:193302$14144 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:183634.7-183634.30" - process $proc$libresoc.v:183634$13865 + attribute \src "libresoc.v:193308.7-193308.30" + process $proc$libresoc.v:193308$14145 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:183640.7-183640.24" - process $proc$libresoc.v:183640$13866 + attribute \src "libresoc.v:193314.13-193314.36" + process $proc$libresoc.v:193314$14146 + assign { } { } + assign $1\cur_cur_dststep[6:0] 7'0000000 + sync always + sync init + update \cur_cur_dststep $1\cur_cur_dststep[6:0] + end + attribute \src "libresoc.v:193318.13-193318.34" + process $proc$libresoc.v:193318$14147 + assign { } { } + assign $1\cur_cur_maxvl[6:0] 7'0000000 + sync always + sync init + update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] + end + attribute \src "libresoc.v:193322.13-193322.36" + process $proc$libresoc.v:193322$14148 + assign { } { } + assign $1\cur_cur_srcstep[6:0] 7'0000000 + sync always + sync init + update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] + end + attribute \src "libresoc.v:193326.13-193326.33" + process $proc$libresoc.v:193326$14149 + assign { } { } + assign $1\cur_cur_subvl[1:0] 2'00 + sync always + sync init + update \cur_cur_subvl $1\cur_cur_subvl[1:0] + end + attribute \src "libresoc.v:193330.13-193330.34" + process $proc$libresoc.v:193330$14150 + assign { } { } + assign $1\cur_cur_svstep[1:0] 2'00 + sync always + sync init + update \cur_cur_svstep $1\cur_cur_svstep[1:0] + end + attribute \src "libresoc.v:193334.13-193334.31" + process $proc$libresoc.v:193334$14151 + assign { } { } + assign $1\cur_cur_vl[6:0] 7'0000000 + sync always + sync init + update \cur_cur_vl $1\cur_cur_vl[6:0] + end + attribute \src "libresoc.v:193338.7-193338.24" + process $proc$libresoc.v:193338$14152 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:183644.7-183644.25" - process $proc$libresoc.v:183644$13867 + attribute \src "libresoc.v:193342.7-193342.25" + process $proc$libresoc.v:193342$14153 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:183648.7-183648.25" - process $proc$libresoc.v:183648$13868 + attribute \src "libresoc.v:193346.7-193346.25" + process $proc$libresoc.v:193346$14154 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:183684.13-183684.34" - process $proc$libresoc.v:183684$13869 + attribute \src "libresoc.v:193394.13-193394.34" + process $proc$libresoc.v:193394$14155 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:183688.14-183688.48" - process $proc$libresoc.v:183688$13870 + attribute \src "libresoc.v:193398.14-193398.48" + process $proc$libresoc.v:193398$14156 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:183694.7-183694.27" - process $proc$libresoc.v:183694$13871 + attribute \src "libresoc.v:193404.7-193404.27" + process $proc$libresoc.v:193404$14157 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:183698.7-183698.26" - process $proc$libresoc.v:183698$13872 + attribute \src "libresoc.v:193408.7-193408.26" + process $proc$libresoc.v:193408$14158 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:183752.14-183752.49" - process $proc$libresoc.v:183752$13873 + attribute \src "libresoc.v:193462.14-193462.49" + process $proc$libresoc.v:193462$14159 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:183756.7-183756.27" - process $proc$libresoc.v:183756$13874 + attribute \src "libresoc.v:193466.7-193466.27" + process $proc$libresoc.v:193466$14160 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:183760.14-183760.49" - process $proc$libresoc.v:183760$13875 + attribute \src "libresoc.v:193470.14-193470.49" + process $proc$libresoc.v:193470$14161 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:183764.14-183764.48" - process $proc$libresoc.v:183764$13876 + attribute \src "libresoc.v:193474.14-193474.48" + process $proc$libresoc.v:193474$14162 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:184173.13-184173.25" - process $proc$libresoc.v:184173$13877 + attribute \src "libresoc.v:193626.14-193626.40" + process $proc$libresoc.v:193626$14163 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] 0 + sync always + sync init + update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:193896.13-193896.25" + process $proc$libresoc.v:193896$14164 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:184189.13-184189.29" - process $proc$libresoc.v:184189$13878 + attribute \src "libresoc.v:193912.7-193912.28" + process $proc$libresoc.v:193912$14165 assign { } { } - assign $1\fsm_state[1:0] 2'00 + assign $1\exec_fsm_state[0:0] 1'0 sync always sync init - update \fsm_state $1\fsm_state[1:0] + update \exec_fsm_state $1\exec_fsm_state[0:0] + end + attribute \src "libresoc.v:193924.13-193924.35" + process $proc$libresoc.v:193924$14166 + assign { } { } + assign $1\fetch_fsm_state[1:0] 2'00 + sync always + sync init + update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:184191.13-184191.35" - process $proc$libresoc.v:184191$13879 + attribute \src "libresoc.v:193936.13-193936.29" + process $proc$libresoc.v:193936$14167 assign { } { } - assign $0\fsm_state$133[1:0]$13880 2'00 + assign $1\fsm_state[1:0] 2'00 sync always sync init - update \fsm_state$133 $0\fsm_state$133[1:0]$13880 + update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:184433.14-184433.28" - process $proc$libresoc.v:184433$13881 + attribute \src "libresoc.v:194196.13-194196.35" + process $proc$libresoc.v:194196$14168 assign { } { } - assign $1\ilatch[31:0] 0 + assign $1\issue_fsm_state[2:0] 3'000 sync always sync init - update \ilatch $1\ilatch[31:0] + update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:184451.7-184451.30" - process $proc$libresoc.v:184451$13882 + attribute \src "libresoc.v:194200.7-194200.30" + process $proc$libresoc.v:194200$14169 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:184459.14-184459.52" - process $proc$libresoc.v:184459$13883 + attribute \src "libresoc.v:194208.14-194208.52" + process $proc$libresoc.v:194208$14170 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:184515.7-184515.22" - process $proc$libresoc.v:184515$13884 + attribute \src "libresoc.v:194266.7-194266.22" + process $proc$libresoc.v:194266$14171 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:184543.7-184543.24" - process $proc$libresoc.v:184543$13885 + attribute \src "libresoc.v:194304.14-194304.40" + process $proc$libresoc.v:194304$14172 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:194310.7-194310.24" + process $proc$libresoc.v:194310$14173 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:184553.7-184553.25" - process $proc$libresoc.v:184553$13886 + attribute \src "libresoc.v:194320.7-194320.25" + process $proc$libresoc.v:194320$14174 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:184993.3-184994.41" - process $proc$libresoc.v:184993$13288 + attribute \src "libresoc.v:194764.7-194764.24" + process $proc$libresoc.v:194764$14175 + assign { } { } + assign $1\sv_changed[0:0] 1'0 + sync always + sync init + update \sv_changed $1\sv_changed[0:0] + end + attribute \src "libresoc.v:194774.7-194774.30" + process $proc$libresoc.v:194774$14176 + assign { } { } + assign $1\svstate_ok_delay[0:0] 1'0 + sync always + sync init + update \svstate_ok_delay $1\svstate_ok_delay[0:0] + end + attribute \src "libresoc.v:194913.3-194914.41" + process $proc$libresoc.v:194913$13481 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:184995.3-184996.33" - process $proc$libresoc.v:184995$13289 + attribute \src "libresoc.v:194915.3-194916.41" + process $proc$libresoc.v:194915$13482 + assign { } { } + assign $0\core_core_pc[63:0] \core_core_pc$next + sync posedge \clk + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "libresoc.v:194917.3-194918.49" + process $proc$libresoc.v:194917$13483 + assign { } { } + assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next + sync posedge \clk + update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:194919.3-194920.39" + process $proc$libresoc.v:194919$13484 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:194921.3-194922.41" + process $proc$libresoc.v:194921$13485 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:194923.3-194924.43" + process $proc$libresoc.v:194923$13486 + assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:194925.3-194926.45" + process $proc$libresoc.v:194925$13487 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:194927.3-194928.33" + process $proc$libresoc.v:194927$13488 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:194929.3-194930.35" + process $proc$libresoc.v:194929$13489 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "libresoc.v:194931.3-194932.33" + process $proc$libresoc.v:194931$13490 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:184997.3-184998.41" - process $proc$libresoc.v:184997$13290 + attribute \src "libresoc.v:194933.3-194934.49" + process $proc$libresoc.v:194933$13491 assign { } { } - assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk - update \dec2_cur_msr $0\dec2_cur_msr[63:0] + update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:184999.3-185000.35" - process $proc$libresoc.v:184999$13291 + attribute \src "libresoc.v:194935.3-194936.47" + process $proc$libresoc.v:194935$13492 assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next + assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk - update \fsm_state $0\fsm_state[1:0] + update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:185001.3-185002.33" - process $proc$libresoc.v:185001$13292 + attribute \src "libresoc.v:194937.3-194938.51" + process $proc$libresoc.v:194937$13493 assign { } { } - assign $0\msr_read[0:0] \msr_read$next + assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk - update \msr_read $0\msr_read[0:0] + update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:185003.3-185004.39" - process $proc$libresoc.v:185003$13293 + attribute \src "libresoc.v:194939.3-194940.51" + process $proc$libresoc.v:194939$13494 assign { } { } - assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk - update \dec2_cur_pc $0\dec2_cur_pc[63:0] + update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:185005.3-185006.57" - process $proc$libresoc.v:185005$13294 + attribute \src "libresoc.v:194941.3-194942.41" + process $proc$libresoc.v:194941$13495 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13295 \core_bigendian_i$10$next + assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13295 + update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:185007.3-185008.47" - process $proc$libresoc.v:185007$13296 + attribute \src "libresoc.v:194943.3-194944.47" + process $proc$libresoc.v:194943$13496 assign { } { } - assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next + assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk - update \core_raw_insn_i $0\core_raw_insn_i[31:0] + update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:185009.3-185010.41" - process $proc$libresoc.v:185009$13297 + attribute \src "libresoc.v:194945.3-194946.35" + process $proc$libresoc.v:194945$13497 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:194947.3-194948.41" + process $proc$libresoc.v:194947$13498 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:185011.3-185012.45" - process $proc$libresoc.v:185011$13298 + attribute \src "libresoc.v:194949.3-194950.45" + process $proc$libresoc.v:194949$13499 assign { } { } - assign $0\core_core_rego[4:0] \core_core_rego$next + assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk - update \core_core_rego $0\core_core_rego[4:0] + update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:185013.3-185014.41" - process $proc$libresoc.v:185013$13299 + attribute \src "libresoc.v:194951.3-194952.41" + process $proc$libresoc.v:194951$13500 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:185015.3-185016.45" - process $proc$libresoc.v:185015$13300 - assign { } { } - assign $0\fsm_state$133[1:0]$13301 \fsm_state$133$next - sync posedge \clk - update \fsm_state$133 $0\fsm_state$133[1:0]$13301 - end - attribute \src "libresoc.v:185017.3-185018.41" - process $proc$libresoc.v:185017$13302 + attribute \src "libresoc.v:194953.3-194954.41" + process $proc$libresoc.v:194953$13501 assign { } { } - assign $0\core_core_ea[4:0] \core_core_ea$next + assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk - update \core_core_ea $0\core_core_ea[4:0] + update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:185019.3-185020.37" - process $proc$libresoc.v:185019$13303 + attribute \src "libresoc.v:194955.3-194956.37" + process $proc$libresoc.v:194955$13502 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:185021.3-185022.45" - process $proc$libresoc.v:185021$13304 + attribute \src "libresoc.v:194957.3-194958.45" + process $proc$libresoc.v:194957$13503 assign { } { } - assign $0\core_core_reg1[4:0] \core_core_reg1$next + assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk - update \core_core_reg1 $0\core_core_reg1[4:0] + update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:185023.3-185024.51" - process $proc$libresoc.v:185023$13305 + attribute \src "libresoc.v:194959.3-194960.51" + process $proc$libresoc.v:194959$13504 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:185025.3-185026.45" - process $proc$libresoc.v:185025$13306 + attribute \src "libresoc.v:194961.3-194962.45" + process $proc$libresoc.v:194961$13505 assign { } { } - assign $0\core_core_reg2[4:0] \core_core_reg2$next + assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk - update \core_core_reg2 $0\core_core_reg2[4:0] + update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:185027.3-185028.51" - process $proc$libresoc.v:185027$13307 + attribute \src "libresoc.v:194963.3-194964.51" + process $proc$libresoc.v:194963$13506 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:185029.3-185030.45" - process $proc$libresoc.v:185029$13308 + attribute \src "libresoc.v:194965.3-194966.45" + process $proc$libresoc.v:194965$13507 assign { } { } - assign $0\core_core_reg3[4:0] \core_core_reg3$next + assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk - update \core_core_reg3 $0\core_core_reg3[4:0] + update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:185031.3-185032.51" - process $proc$libresoc.v:185031$13309 + attribute \src "libresoc.v:194967.3-194968.39" + process $proc$libresoc.v:194967$13508 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:194969.3-194970.51" + process $proc$libresoc.v:194969$13509 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:185033.3-185034.45" - process $proc$libresoc.v:185033$13310 + attribute \src "libresoc.v:194971.3-194972.45" + process $proc$libresoc.v:194971$13510 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:185035.3-185036.41" - process $proc$libresoc.v:185035$13311 + attribute \src "libresoc.v:194973.3-194974.41" + process $proc$libresoc.v:194973$13511 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:185037.3-185038.39" - process $proc$libresoc.v:185037$13312 - assign { } { } - assign $0\d_xer_delay[0:0] \d_xer_delay$next - sync posedge \clk - update \d_xer_delay $0\d_xer_delay[0:0] - end - attribute \src "libresoc.v:185039.3-185040.45" - process $proc$libresoc.v:185039$13313 + attribute \src "libresoc.v:194975.3-194976.45" + process $proc$libresoc.v:194975$13512 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:185041.3-185042.51" - process $proc$libresoc.v:185041$13314 + attribute \src "libresoc.v:194977.3-194978.51" + process $proc$libresoc.v:194977$13513 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:185043.3-185044.49" - process $proc$libresoc.v:185043$13315 + attribute \src "libresoc.v:194979.3-194980.49" + process $proc$libresoc.v:194979$13514 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:185045.3-185046.41" - process $proc$libresoc.v:185045$13316 + attribute \src "libresoc.v:194981.3-194982.41" + process $proc$libresoc.v:194981$13515 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:185047.3-185048.47" - process $proc$libresoc.v:185047$13317 + attribute \src "libresoc.v:194983.3-194984.47" + process $proc$libresoc.v:194983$13516 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:185049.3-185050.53" - process $proc$libresoc.v:185049$13318 + attribute \src "libresoc.v:194985.3-194986.53" + process $proc$libresoc.v:194985$13517 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:185051.3-185052.47" - process $proc$libresoc.v:185051$13319 + attribute \src "libresoc.v:194987.3-194988.47" + process $proc$libresoc.v:194987$13518 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:185053.3-185054.53" - process $proc$libresoc.v:185053$13320 + attribute \src "libresoc.v:194989.3-194990.37" + process $proc$libresoc.v:194989$13519 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "libresoc.v:194991.3-194992.53" + process $proc$libresoc.v:194991$13520 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:185055.3-185056.49" - process $proc$libresoc.v:185055$13321 + attribute \src "libresoc.v:194993.3-194994.49" + process $proc$libresoc.v:194993$13521 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:185057.3-185058.45" - process $proc$libresoc.v:185057$13322 + attribute \src "libresoc.v:194995.3-194996.45" + process $proc$libresoc.v:194995$13522 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:185059.3-185060.37" - process $proc$libresoc.v:185059$13323 - assign { } { } - assign $0\d_cr_delay[0:0] \d_cr_delay$next - sync posedge \clk - update \d_cr_delay $0\d_cr_delay[0:0] - end - attribute \src "libresoc.v:185061.3-185062.49" - process $proc$libresoc.v:185061$13324 + attribute \src "libresoc.v:194997.3-194998.49" + process $proc$libresoc.v:194997$13523 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:185063.3-185064.45" - process $proc$libresoc.v:185063$13325 + attribute \src "libresoc.v:194999.3-195000.45" + process $proc$libresoc.v:194999$13524 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:185065.3-185066.49" - process $proc$libresoc.v:185065$13326 + attribute \src "libresoc.v:195001.3-195002.49" + process $proc$libresoc.v:195001$13525 assign { } { } - assign $0\core_core_cr_in1[2:0] \core_core_cr_in1$next + assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk - update \core_core_cr_in1 $0\core_core_cr_in1[2:0] + update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:185067.3-185068.55" - process $proc$libresoc.v:185067$13327 + attribute \src "libresoc.v:195003.3-195004.55" + process $proc$libresoc.v:195003$13526 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:185069.3-185070.49" - process $proc$libresoc.v:185069$13328 + attribute \src "libresoc.v:195005.3-195006.49" + process $proc$libresoc.v:195005$13527 assign { } { } - assign $0\core_core_cr_in2[2:0] \core_core_cr_in2$next + assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk - update \core_core_cr_in2 $0\core_core_cr_in2[2:0] + update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:185071.3-185072.55" - process $proc$libresoc.v:185071$13329 + attribute \src "libresoc.v:195007.3-195008.55" + process $proc$libresoc.v:195007$13528 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:185073.3-185074.55" - process $proc$libresoc.v:185073$13330 + attribute \src "libresoc.v:195009.3-195010.55" + process $proc$libresoc.v:195009$13529 assign { } { } - assign $0\core_core_cr_in2$1[2:0]$13331 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[6:0]$13530 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13331 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13530 end - attribute \src "libresoc.v:185075.3-185076.61" - process $proc$libresoc.v:185075$13332 + attribute \src "libresoc.v:195011.3-195012.39" + process $proc$libresoc.v:195011$13531 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13333 \core_core_cr_in2_ok$2$next + assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13333 + update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:185077.3-185078.49" - process $proc$libresoc.v:185077$13334 + attribute \src "libresoc.v:195013.3-195014.61" + process $proc$libresoc.v:195013$13532 assign { } { } - assign $0\core_core_cr_out[2:0] \core_core_cr_out$next + assign $0\core_core_cr_in2_ok$2[0:0]$13533 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_out $0\core_core_cr_out[2:0] + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13533 end - attribute \src "libresoc.v:185079.3-185080.45" - process $proc$libresoc.v:185079$13335 + attribute \src "libresoc.v:195015.3-195016.49" + process $proc$libresoc.v:195015$13534 assign { } { } - assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk - update \core_cr_out_ok $0\core_cr_out_ok[0:0] + update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:185081.3-185082.39" - process $proc$libresoc.v:185081$13336 + attribute \src "libresoc.v:195017.3-195018.45" + process $proc$libresoc.v:195017$13535 assign { } { } - assign $0\d_reg_delay[0:0] \d_reg_delay$next + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk - update \d_reg_delay $0\d_reg_delay[0:0] + update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:185083.3-185084.53" - process $proc$libresoc.v:185083$13337 + attribute \src "libresoc.v:195019.3-195020.53" + process $proc$libresoc.v:195019$13536 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:185085.3-185086.53" - process $proc$libresoc.v:185085$13338 + attribute \src "libresoc.v:195021.3-195022.53" + process $proc$libresoc.v:195021$13537 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:185087.3-185088.55" - process $proc$libresoc.v:185087$13339 + attribute \src "libresoc.v:195023.3-195024.55" + process $proc$libresoc.v:195023$13538 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:185089.3-185090.65" - process $proc$libresoc.v:185089$13340 + attribute \src "libresoc.v:195025.3-195026.65" + process $proc$libresoc.v:195025$13539 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:185091.3-185092.61" - process $proc$libresoc.v:185091$13341 + attribute \src "libresoc.v:195027.3-195028.61" + process $proc$libresoc.v:195027$13540 assign { } { } - assign $0\core_core_core_fn_unit[11:0] \core_core_core_fn_unit$next + assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk - update \core_core_core_fn_unit $0\core_core_core_fn_unit[11:0] + update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:185093.3-185094.41" - process $proc$libresoc.v:185093$13342 + attribute \src "libresoc.v:195029.3-195030.41" + process $proc$libresoc.v:195029$13541 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:185095.3-185096.51" - process $proc$libresoc.v:185095$13343 + attribute \src "libresoc.v:195031.3-195032.51" + process $proc$libresoc.v:195031$13542 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:185097.3-185098.57" - process $proc$libresoc.v:185097$13344 + attribute \src "libresoc.v:195033.3-195034.45" + process $proc$libresoc.v:195033$13543 + assign { } { } + assign $0\exec_fsm_state[0:0] \exec_fsm_state$next + sync posedge \clk + update \exec_fsm_state $0\exec_fsm_state[0:0] + end + attribute \src "libresoc.v:195035.3-195036.57" + process $proc$libresoc.v:195035$13544 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:185099.3-185100.51" - process $proc$libresoc.v:185099$13345 + attribute \src "libresoc.v:195037.3-195038.51" + process $proc$libresoc.v:195037$13545 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:185101.3-185102.57" - process $proc$libresoc.v:185101$13346 + attribute \src "libresoc.v:195039.3-195040.57" + process $proc$libresoc.v:195039$13546 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:185103.3-185104.29" - process $proc$libresoc.v:185103$13347 - assign { } { } - assign $0\ilatch[31:0] \ilatch$next - sync posedge \clk - update \ilatch $0\ilatch[31:0] - end - attribute \src "libresoc.v:185105.3-185106.69" - process $proc$libresoc.v:185105$13348 + attribute \src "libresoc.v:195041.3-195042.69" + process $proc$libresoc.v:195041$13547 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:185107.3-185108.63" - process $proc$libresoc.v:185107$13349 + attribute \src "libresoc.v:195043.3-195044.63" + process $proc$libresoc.v:195043$13548 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:185109.3-185110.71" - process $proc$libresoc.v:185109$13350 + attribute \src "libresoc.v:195045.3-195046.71" + process $proc$libresoc.v:195045$13549 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13351 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13550 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13351 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13550 end - attribute \src "libresoc.v:185111.3-185112.75" - process $proc$libresoc.v:185111$13352 + attribute \src "libresoc.v:195047.3-195048.75" + process $proc$libresoc.v:195047$13551 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13353 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13552 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13353 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13552 end - attribute \src "libresoc.v:185113.3-185114.75" - process $proc$libresoc.v:185113$13354 + attribute \src "libresoc.v:195049.3-195050.75" + process $proc$libresoc.v:195049$13553 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13355 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13554 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13355 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13554 end - attribute \src "libresoc.v:185115.3-185116.75" - process $proc$libresoc.v:185115$13356 + attribute \src "libresoc.v:195051.3-195052.75" + process $proc$libresoc.v:195051$13555 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13357 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13556 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13357 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13556 end - attribute \src "libresoc.v:185117.3-185118.75" - process $proc$libresoc.v:185117$13358 + attribute \src "libresoc.v:195053.3-195054.75" + process $proc$libresoc.v:195053$13557 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13359 \core_core_core_exc_$signal$6$next + assign $0\core_core_core_exc_$signal$6[0:0]$13558 \core_core_core_exc_$signal$6$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13359 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13558 end - attribute \src "libresoc.v:185119.3-185120.75" - process $proc$libresoc.v:185119$13360 + attribute \src "libresoc.v:195055.3-195056.41" + process $proc$libresoc.v:195055$13559 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13361 \core_core_core_exc_$signal$7$next + assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13361 + update \core_sv_a_nz $0\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:185121.3-185122.75" - process $proc$libresoc.v:185121$13362 + attribute \src "libresoc.v:195057.3-195058.75" + process $proc$libresoc.v:195057$13560 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13363 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$7[0:0]$13561 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13363 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13561 end - attribute \src "libresoc.v:185123.3-185124.75" - process $proc$libresoc.v:185123$13364 + attribute \src "libresoc.v:195059.3-195060.75" + process $proc$libresoc.v:195059$13562 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13365 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$8[0:0]$13563 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13365 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13563 end - attribute \src "libresoc.v:185125.3-185126.41" - process $proc$libresoc.v:185125$13366 + attribute \src "libresoc.v:195061.3-195062.75" + process $proc$libresoc.v:195061$13564 assign { } { } - assign $0\core_core_pc[63:0] \core_core_pc$next + assign $0\core_core_core_exc_$signal$9[0:0]$13565 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_pc $0\core_core_pc[63:0] + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13565 end - attribute \src "libresoc.v:185127.3-185128.63" - process $proc$libresoc.v:185127$13367 + attribute \src "libresoc.v:195063.3-195064.63" + process $proc$libresoc.v:195063$13566 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:185129.3-185130.57" - process $proc$libresoc.v:185129$13368 + attribute \src "libresoc.v:195065.3-195066.57" + process $proc$libresoc.v:195065$13567 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:185131.3-185132.63" - process $proc$libresoc.v:185131$13369 + attribute \src "libresoc.v:195067.3-195068.63" + process $proc$libresoc.v:195067$13568 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:185133.3-185134.57" - process $proc$libresoc.v:185133$13370 + attribute \src "libresoc.v:195069.3-195070.57" + process $proc$libresoc.v:195069$13569 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:185135.3-185136.53" - process $proc$libresoc.v:185135$13371 + attribute \src "libresoc.v:195071.3-195072.53" + process $proc$libresoc.v:195071$13570 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:185137.3-185138.63" - process $proc$libresoc.v:185137$13372 + attribute \src "libresoc.v:195073.3-195074.63" + process $proc$libresoc.v:195073$13571 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:185139.3-185140.37" - process $proc$libresoc.v:185139$13373 + attribute \src "libresoc.v:195075.3-195076.37" + process $proc$libresoc.v:195075$13572 + assign { } { } + assign $0\sv_changed[0:0] \sv_changed$next + sync posedge \clk + update \sv_changed $0\sv_changed[0:0] + end + attribute \src "libresoc.v:195077.3-195078.57" + process $proc$libresoc.v:195077$13573 + assign { } { } + assign $0\core_bigendian_i$10[0:0]$13574 \core_bigendian_i$10$next + sync posedge \clk + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13574 + end + attribute \src "libresoc.v:195079.3-195080.37" + process $proc$libresoc.v:195079$13575 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:185141.3-185142.39" - process $proc$libresoc.v:185141$13374 + attribute \src "libresoc.v:195081.3-195082.47" + process $proc$libresoc.v:195081$13576 assign { } { } - assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk - update \pc_ok_delay $0\pc_ok_delay[0:0] + update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:185143.3-185144.43" - process $proc$libresoc.v:185143$13375 + attribute \src "libresoc.v:195083.3-195084.53" + process $proc$libresoc.v:195083$13577 assign { } { } - assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o + assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk - update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:185145.3-185146.27" - process $proc$libresoc.v:185145$13376 + attribute \src "libresoc.v:195085.3-195086.23" + process $proc$libresoc.v:195085$13578 assign { } { } - assign $0\delay[1:0] \delay$next - sync posedge \por_clk - update \delay $0\delay[1:0] + assign $0\nia[63:0] \nia$next + sync posedge \clk + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:185147.3-185148.33" - process $proc$libresoc.v:185147$13377 + attribute \src "libresoc.v:195087.3-195088.41" + process $proc$libresoc.v:195087$13579 assign { } { } - assign $0\core_msr[63:0] \core_msr$next + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk - update \core_msr $0\core_msr[63:0] + update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:185149.3-185150.43" - process $proc$libresoc.v:185149$13378 + attribute \src "libresoc.v:195089.3-195090.47" + process $proc$libresoc.v:195089$13580 assign { } { } - assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk - update \dec2_cur_eint $0\dec2_cur_eint[0:0] + update \fetch_fsm_state $0\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:185151.3-185152.47" - process $proc$libresoc.v:185151$13379 + attribute \src "libresoc.v:195091.3-195092.33" + process $proc$libresoc.v:195091$13581 assign { } { } - assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next + assign $0\msr_read[0:0] \msr_read$next sync posedge \clk - update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] + update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:185153.3-185154.49" - process $proc$libresoc.v:185153$13380 + attribute \src "libresoc.v:195093.3-195094.45" + process $proc$libresoc.v:195093$13582 assign { } { } - assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next + assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk - update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:185155.3-185156.39" - process $proc$libresoc.v:185155$13381 + attribute \src "libresoc.v:195095.3-195096.43" + process $proc$libresoc.v:195095$13583 assign { } { } - assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk - update \dbg_dmi_din $0\dbg_dmi_din[63:0] + update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:185157.3-185158.41" - process $proc$libresoc.v:185157$13382 + attribute \src "libresoc.v:195097.3-195098.47" + process $proc$libresoc.v:195097$13584 assign { } { } - assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk - update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:185159.3-185160.43" - process $proc$libresoc.v:185159$13383 + attribute \src "libresoc.v:195099.3-195100.47" + process $proc$libresoc.v:195099$13585 assign { } { } - assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk - update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:185161.3-185162.45" - process $proc$libresoc.v:185161$13384 + attribute \src "libresoc.v:195101.3-195102.47" + process $proc$libresoc.v:195101$13586 assign { } { } - assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk - update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:185163.3-185164.35" - process $proc$libresoc.v:185163$13385 + attribute \src "libresoc.v:195103.3-195104.37" + process $proc$libresoc.v:195103$13587 assign { } { } - assign $0\core_eint[0:0] \core_eint$next + assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk - update \core_eint $0\core_eint[0:0] + update \cur_cur_vl $0\cur_cur_vl[6:0] + end + attribute \src "libresoc.v:195105.3-195106.43" + process $proc$libresoc.v:195105$13588 + assign { } { } + assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next + sync posedge \clk + update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] + end + attribute \src "libresoc.v:195107.3-195108.39" + process $proc$libresoc.v:195107$13589 + assign { } { } + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:195109.3-195110.49" + process $proc$libresoc.v:195109$13590 + assign { } { } + assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next + sync posedge \clk + update \svstate_ok_delay $0\svstate_ok_delay[0:0] + end + attribute \src "libresoc.v:195111.3-195112.39" + process $proc$libresoc.v:195111$13591 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:195113.3-195114.43" + process $proc$libresoc.v:195113$13592 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:195115.3-195116.27" + process $proc$libresoc.v:195115$13593 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:195117.3-195118.43" + process $proc$libresoc.v:195117$13594 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:195119.3-195120.47" + process $proc$libresoc.v:195119$13595 + assign { } { } + assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next + sync posedge \clk + update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:185730.3-185738.6" - process $proc$libresoc.v:185730$13386 + attribute \src "libresoc.v:195751.3-195759.6" + process $proc$libresoc.v:195751$13596 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13387 $1\dbg_dmi_addr_i$next[3:0]$13388 - attribute \src "libresoc.v:185731.5-185731.29" + assign $0\dbg_dmi_addr_i$next[3:0]$13597 $1\dbg_dmi_addr_i$next[3:0]$13598 + attribute \src "libresoc.v:195752.5-195752.29" switch \initial - attribute \src "libresoc.v:185731.9-185731.17" + attribute \src "libresoc.v:195752.9-195752.17" case 1'1 case end @@ -390144,21 +408523,44 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13388 4'0000 + assign $1\dbg_dmi_addr_i$next[3:0]$13598 4'0000 case - assign $1\dbg_dmi_addr_i$next[3:0]$13388 \jtag_dmi0__addr_i + assign $1\dbg_dmi_addr_i$next[3:0]$13598 \jtag_dmi0__addr_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13387 + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13597 end - attribute \src "libresoc.v:185739.3-185747.6" - process $proc$libresoc.v:185739$13389 + attribute \src "libresoc.v:195760.3-195768.6" + process $proc$libresoc.v:195760$13599 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13390 $1\dbg_dmi_req_i$next[0:0]$13391 - attribute \src "libresoc.v:185740.5-185740.29" + assign $0\dbg_dmi_req_i$next[0:0]$13600 $1\dbg_dmi_req_i$next[0:0]$13601 + attribute \src "libresoc.v:195761.5-195761.29" switch \initial - attribute \src "libresoc.v:185740.9-185740.17" + attribute \src "libresoc.v:195761.9-195761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_req_i$next[0:0]$13601 1'0 + case + assign $1\dbg_dmi_req_i$next[0:0]$13601 \jtag_dmi0__req_i + end + sync always + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13600 + end + attribute \src "libresoc.v:195769.3-195777.6" + process $proc$libresoc.v:195769$13602 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$13603 $1\dec2_cur_eint$next[0:0]$13604 + attribute \src "libresoc.v:195770.5-195770.29" + switch \initial + attribute \src "libresoc.v:195770.9-195770.17" case 1'1 case end @@ -390167,418 +408569,1539 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13391 1'0 + assign $1\dec2_cur_eint$next[0:0]$13604 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$13604 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13603 + end + attribute \src "libresoc.v:195778.3-195787.6" + process $proc$libresoc.v:195778$13605 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$13606 $1\delay$next[1:0]$13607 + attribute \src "libresoc.v:195779.5-195779.29" + switch \initial + attribute \src "libresoc.v:195779.9-195779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$13607 \$25 [1:0] case - assign $1\dbg_dmi_req_i$next[0:0]$13391 \jtag_dmi0__req_i + assign $1\delay$next[1:0]$13607 \delay end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13390 + update \delay$next $0\delay$next[1:0]$13606 end - attribute \src "libresoc.v:185748.3-185768.6" - process $proc$libresoc.v:185748$13392 + attribute \src "libresoc.v:195788.3-195832.6" + process $proc$libresoc.v:195788$13608 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13393 $3\dec2_cur_msr$next[63:0]$13396 - attribute \src "libresoc.v:185749.5-185749.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_dststep$next[6:0]$13609 $3\core_core_dststep$next[6:0]$13639 + assign $0\core_core_maxvl$next[6:0]$13610 $3\core_core_maxvl$next[6:0]$13640 + assign $0\core_core_pc$next[63:0]$13611 $3\core_core_pc$next[63:0]$13641 + assign $0\core_core_srcstep$next[6:0]$13612 $3\core_core_srcstep$next[6:0]$13642 + assign $0\core_core_subvl$next[1:0]$13613 $3\core_core_subvl$next[1:0]$13643 + assign $0\core_core_svstep$next[1:0]$13614 $3\core_core_svstep$next[1:0]$13644 + assign $0\core_core_vl$next[6:0]$13615 $3\core_core_vl$next[6:0]$13645 + assign $0\core_dec$next[63:0]$13616 $3\core_dec$next[63:0]$13646 + assign $0\core_eint$next[0:0]$13617 $3\core_eint$next[0:0]$13647 + assign $0\core_msr$next[63:0]$13618 $3\core_msr$next[63:0]$13648 + attribute \src "libresoc.v:195789.5-195789.29" switch \initial - attribute \src "libresoc.v:185749.9-185749.17" + attribute \src "libresoc.v:195789.9-195789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'001 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13394 $2\dec2_cur_msr$next[63:0]$13395 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - switch \$117 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_core_dststep$next[6:0]$13619 $2\core_core_dststep$next[6:0]$13629 + assign $1\core_core_maxvl$next[6:0]$13620 $2\core_core_maxvl$next[6:0]$13630 + assign $1\core_core_pc$next[63:0]$13621 $2\core_core_pc$next[63:0]$13631 + assign $1\core_core_srcstep$next[6:0]$13622 $2\core_core_srcstep$next[6:0]$13632 + assign $1\core_core_subvl$next[1:0]$13623 $2\core_core_subvl$next[1:0]$13633 + assign $1\core_core_svstep$next[1:0]$13624 $2\core_core_svstep$next[1:0]$13634 + assign $1\core_core_vl$next[6:0]$13625 $2\core_core_vl$next[6:0]$13635 + assign $1\core_dec$next[63:0]$13626 $2\core_dec$next[63:0]$13636 + assign $1\core_eint$next[0:0]$13627 $2\core_eint$next[0:0]$13637 + assign $1\core_msr$next[63:0]$13628 $2\core_msr$next[63:0]$13638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13395 \core_msr__data_o + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_maxvl$next[6:0]$13630 $2\core_core_vl$next[6:0]$13635 $2\core_core_srcstep$next[6:0]$13632 $2\core_core_dststep$next[6:0]$13629 $2\core_core_subvl$next[1:0]$13633 $2\core_core_svstep$next[1:0]$13634 $2\core_dec$next[63:0]$13636 $2\core_eint$next[0:0]$13637 $2\core_msr$next[63:0]$13638 $2\core_core_pc$next[63:0]$13631 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $2\dec2_cur_msr$next[63:0]$13395 \dec2_cur_msr + assign $2\core_core_dststep$next[6:0]$13629 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13630 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13631 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13632 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13633 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13634 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13635 \core_core_vl + assign $2\core_dec$next[63:0]$13636 \core_dec + assign $2\core_eint$next[0:0]$13637 \core_eint + assign $2\core_msr$next[63:0]$13638 \core_msr end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_maxvl$next[6:0]$13620 $1\core_core_vl$next[6:0]$13625 $1\core_core_srcstep$next[6:0]$13622 $1\core_core_dststep$next[6:0]$13619 $1\core_core_subvl$next[1:0]$13623 $1\core_core_svstep$next[1:0]$13624 $1\core_dec$next[63:0]$13626 $1\core_eint$next[0:0]$13627 $1\core_msr$next[63:0]$13628 $1\core_core_pc$next[63:0]$13621 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $1\dec2_cur_msr$next[63:0]$13394 \dec2_cur_msr + assign $1\core_core_dststep$next[6:0]$13619 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13620 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13621 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13622 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13623 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13624 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13625 \core_core_vl + assign $1\core_dec$next[63:0]$13626 \core_dec + assign $1\core_eint$next[0:0]$13627 \core_eint + assign $1\core_msr$next[63:0]$13628 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13396 64'0000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\core_core_pc$next[63:0]$13641 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13648 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13647 1'0 + assign $3\core_dec$next[63:0]$13646 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13644 2'00 + assign $3\core_core_subvl$next[1:0]$13643 2'00 + assign $3\core_core_dststep$next[6:0]$13639 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13642 7'0000000 + assign $3\core_core_vl$next[6:0]$13645 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13640 7'0000000 case - assign $3\dec2_cur_msr$next[63:0]$13396 $1\dec2_cur_msr$next[63:0]$13394 + assign $3\core_core_dststep$next[6:0]$13639 $1\core_core_dststep$next[6:0]$13619 + assign $3\core_core_maxvl$next[6:0]$13640 $1\core_core_maxvl$next[6:0]$13620 + assign $3\core_core_pc$next[63:0]$13641 $1\core_core_pc$next[63:0]$13621 + assign $3\core_core_srcstep$next[6:0]$13642 $1\core_core_srcstep$next[6:0]$13622 + assign $3\core_core_subvl$next[1:0]$13643 $1\core_core_subvl$next[1:0]$13623 + assign $3\core_core_svstep$next[1:0]$13644 $1\core_core_svstep$next[1:0]$13624 + assign $3\core_core_vl$next[6:0]$13645 $1\core_core_vl$next[6:0]$13625 + assign $3\core_dec$next[63:0]$13646 $1\core_dec$next[63:0]$13626 + assign $3\core_eint$next[0:0]$13647 $1\core_eint$next[0:0]$13627 + assign $3\core_msr$next[63:0]$13648 $1\core_msr$next[63:0]$13628 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13393 + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13609 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13610 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13611 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13612 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13613 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13614 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13615 + update \core_dec$next $0\core_dec$next[63:0]$13616 + update \core_eint$next $0\core_eint$next[0:0]$13617 + update \core_msr$next $0\core_msr$next[63:0]$13618 end - attribute \src "libresoc.v:185769.3-185787.6" - process $proc$libresoc.v:185769$13397 + attribute \src "libresoc.v:195833.3-195853.6" + process $proc$libresoc.v:195833$13649 + assign { } { } assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:185770.5-185770.29" + assign $0\core_raw_insn_i$next[31:0]$13650 $3\core_raw_insn_i$next[31:0]$13653 + attribute \src "libresoc.v:195834.5-195834.29" switch \initial - attribute \src "libresoc.v:185770.9-185770.17" + attribute \src "libresoc.v:195834.9-195834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'001 assign { } { } - assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o + assign $1\core_raw_insn_i$next[31:0]$13651 $2\core_raw_insn_i$next[31:0]$13652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_raw_opcode_in[31:0] 0 + assign { } { } + assign $2\core_raw_insn_i$next[31:0]$13652 \dec2_raw_opcode_in + case + assign $2\core_raw_insn_i$next[31:0]$13652 \core_raw_insn_i + end + case + assign $1\core_raw_insn_i$next[31:0]$13651 \core_raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_raw_insn_i$next[31:0]$13653 0 + case + assign $3\core_raw_insn_i$next[31:0]$13653 $1\core_raw_insn_i$next[31:0]$13651 + end + sync always + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13650 + end + attribute \src "libresoc.v:195854.3-195878.6" + process $proc$libresoc.v:195854$13654 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_bigendian_i$10$next[0:0]$13655 $3\core_bigendian_i$10$next[0:0]$13658 + attribute \src "libresoc.v:195855.5-195855.29" + switch \initial + attribute \src "libresoc.v:195855.9-195855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13656 $2\core_bigendian_i$10$next[0:0]$13657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_bigendian_i$10$next[0:0]$13657 \core_bigendian_i case + assign $2\core_bigendian_i$10$next[0:0]$13657 \core_bigendian_i$10 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13656 \core_bigendian_i + case + assign $1\core_bigendian_i$10$next[0:0]$13656 \core_bigendian_i$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_bigendian_i$10$next[0:0]$13658 1'0 + case + assign $3\core_bigendian_i$10$next[0:0]$13658 $1\core_bigendian_i$10$next[0:0]$13656 + end + sync always + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13655 + end + attribute \src "libresoc.v:195879.3-195903.6" + process $proc$libresoc.v:195879$13659 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_sv_a_nz$next[0:0]$13660 $3\core_sv_a_nz$next[0:0]$13663 + attribute \src "libresoc.v:195880.5-195880.29" + switch \initial + attribute \src "libresoc.v:195880.9-195880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_sv_a_nz$next[0:0]$13661 $2\core_sv_a_nz$next[0:0]$13662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $2\dec2_raw_opcode_in[31:0] \$119 + assign $2\core_sv_a_nz$next[0:0]$13662 \dec2_sv_a_nz + case + assign $2\core_sv_a_nz$next[0:0]$13662 \core_sv_a_nz end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\core_sv_a_nz$next[0:0]$13661 \dec2_sv_a_nz + case + assign $1\core_sv_a_nz$next[0:0]$13661 \core_sv_a_nz + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_sv_a_nz$next[0:0]$13663 1'0 case - assign $1\dec2_raw_opcode_in[31:0] 0 + assign $3\core_sv_a_nz$next[0:0]$13663 $1\core_sv_a_nz$next[0:0]$13661 end sync always - update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13660 end - attribute \src "libresoc.v:185788.3-185819.6" - process $proc$libresoc.v:185788$13398 + attribute \src "libresoc.v:195904.3-195941.6" + process $proc$libresoc.v:195904$13664 + assign { } { } assign { } { } assign { } { } + assign $0\insn_done[0:0] $4\insn_done[0:0] + attribute \src "libresoc.v:195905.5-195905.29" + switch \initial + attribute \src "libresoc.v:195905.9-195905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\insn_done[0:0] $2\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\insn_done[0:0] $3\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \$228 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\insn_done[0:0] 1'1 + case + assign $3\insn_done[0:0] 1'0 + end + case + assign $2\insn_done[0:0] 1'0 + end + case + assign $1\insn_done[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\insn_done[0:0] $5\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + switch \$230 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\insn_done[0:0] $6\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:460" + switch \exec_pc_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\insn_done[0:0] 1'1 + case + assign $6\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $5\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $4\insn_done[0:0] $1\insn_done[0:0] + end + sync always + update \insn_done $0\insn_done[0:0] + end + attribute \src "libresoc.v:195942.3-195952.6" + process $proc$libresoc.v:195942$13665 assign { } { } assign { } { } + assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:195943.5-195943.29" + switch \initial + attribute \src "libresoc.v:195943.9-195943.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\exec_insn_valid_i[0:0] 1'1 + case + assign $1\exec_insn_valid_i[0:0] 1'0 + end + sync always + update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] + end + attribute \src "libresoc.v:195953.3-195968.6" + process $proc$libresoc.v:195953$13666 assign { } { } assign { } { } + assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:195954.5-195954.29" + switch \initial + attribute \src "libresoc.v:195954.9-195954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$236 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\exec_pc_ready_i[0:0] 1'1 + case + assign $2\exec_pc_ready_i[0:0] 1'0 + end + case + assign $1\exec_pc_ready_i[0:0] 1'0 + end + sync always + update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] + end + attribute \src "libresoc.v:195969.3-195989.6" + process $proc$libresoc.v:195969$13667 assign { } { } assign { } { } + assign $0\next_srcstep[6:0] $1\next_srcstep[6:0] + attribute \src "libresoc.v:195970.5-195970.29" + switch \initial + attribute \src "libresoc.v:195970.9-195970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\next_srcstep[6:0] $2\next_srcstep[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$242 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\next_srcstep[6:0] $3\next_srcstep[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\next_srcstep[6:0] \$244 [6:0] + case + assign $3\next_srcstep[6:0] 7'0000000 + end + case + assign $2\next_srcstep[6:0] 7'0000000 + end + case + assign $1\next_srcstep[6:0] 7'0000000 + end + sync always + update \next_srcstep $0\next_srcstep[6:0] + end + attribute \src "libresoc.v:195990.3-196010.6" + process $proc$libresoc.v:195990$13668 assign { } { } assign { } { } + assign $0\is_last[0:0] $1\is_last[0:0] + attribute \src "libresoc.v:195991.5-195991.29" + switch \initial + attribute \src "libresoc.v:195991.9-195991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\is_last[0:0] $2\is_last[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$251 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_last[0:0] $3\is_last[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\is_last[0:0] \$253 + case + assign $3\is_last[0:0] 1'0 + end + case + assign $2\is_last[0:0] 1'0 + end + case + assign $1\is_last[0:0] 1'0 + end + sync always + update \is_last $0\is_last[0:0] + end + attribute \src "libresoc.v:196011.3-196020.6" + process $proc$libresoc.v:196011$13669 assign { } { } assign { } { } - assign $0\core_core_pc$next[63:0]$13399 $3\core_core_pc$next[63:0]$13411 - assign $0\core_dec$next[63:0]$13400 $3\core_dec$next[63:0]$13412 - assign $0\core_eint$next[0:0]$13401 $3\core_eint$next[0:0]$13413 - assign $0\core_msr$next[63:0]$13402 $3\core_msr$next[63:0]$13414 - attribute \src "libresoc.v:185789.5-185789.29" + assign $0\core_wen$11[2:0]$13670 $1\core_wen$11[2:0]$13671 + attribute \src "libresoc.v:196012.5-196012.29" switch \initial - attribute \src "libresoc.v:185789.9-185789.17" + attribute \src "libresoc.v:196012.9-196012.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + switch \update_svstate attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } + assign $1\core_wen$11[2:0]$13671 3'100 + case + assign $1\core_wen$11[2:0]$13671 3'000 + end + sync always + update \core_wen$11 $0\core_wen$11[2:0]$13670 + end + attribute \src "libresoc.v:196021.3-196030.6" + process $proc$libresoc.v:196021$13672 + assign { } { } + assign { } { } + assign $0\core_data_i$12[63:0]$13673 $1\core_data_i$12[63:0]$13674 + attribute \src "libresoc.v:196022.5-196022.29" + switch \initial + attribute \src "libresoc.v:196022.9-196022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + switch \update_svstate + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $1\core_data_i$12[63:0]$13674 \$255 + case + assign $1\core_data_i$12[63:0]$13674 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_data_i$12 $0\core_data_i$12[63:0]$13673 + end + attribute \src "libresoc.v:196031.3-196041.6" + process $proc$libresoc.v:196031$13675 + assign { } { } + assign { } { } + assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:196032.5-196032.29" + switch \initial + attribute \src "libresoc.v:196032.9-196032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 assign { } { } + assign $1\exec_insn_ready_o[0:0] 1'1 + case + assign $1\exec_insn_ready_o[0:0] 1'0 + end + sync always + update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] + end + attribute \src "libresoc.v:196042.3-196066.6" + process $proc$libresoc.v:196042$13676 + assign { } { } + assign { } { } + assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:196043.5-196043.29" + switch \initial + attribute \src "libresoc.v:196043.9-196043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 assign { } { } - assign $1\core_core_pc$next[63:0]$13403 $2\core_core_pc$next[63:0]$13407 - assign $1\core_dec$next[63:0]$13404 $2\core_dec$next[63:0]$13408 - assign $1\core_eint$next[0:0]$13405 $2\core_eint$next[0:0]$13409 - assign $1\core_msr$next[63:0]$13406 $2\core_msr$next[63:0]$13410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o + assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\core_core_pc$next[63:0]$13407 \core_core_pc - assign $2\core_dec$next[63:0]$13408 \core_dec - assign $2\core_eint$next[0:0]$13409 \core_eint - assign $2\core_msr$next[63:0]$13410 \core_msr + assign { } { } + assign $2\core_ivalid_i[0:0] 1'1 + case + assign $2\core_ivalid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" + switch \$257 attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_ivalid_i[0:0] 1'1 case + assign $3\core_ivalid_i[0:0] 1'0 + end + case + assign $1\core_ivalid_i[0:0] 1'0 + end + sync always + update \core_ivalid_i $0\core_ivalid_i[0:0] + end + attribute \src "libresoc.v:196067.3-196082.6" + process $proc$libresoc.v:196067$13677 + assign { } { } + assign { } { } + assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] + attribute \src "libresoc.v:196068.5-196068.29" + switch \initial + attribute \src "libresoc.v:196068.9-196068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $2\core_issue_i[0:0] 1'1 + case + assign $2\core_issue_i[0:0] 1'0 + end + case + assign $1\core_issue_i[0:0] 1'0 + end + sync always + update \core_issue_i $0\core_issue_i[0:0] + end + attribute \src "libresoc.v:196083.3-196117.6" + process $proc$libresoc.v:196083$13678 + assign { } { } + assign { } { } + assign { } { } + assign $0\exec_fsm_state$next[0:0]$13679 $5\exec_fsm_state$next[0:0]$13684 + attribute \src "libresoc.v:196084.5-196084.29" + switch \initial + attribute \src "libresoc.v:196084.9-196084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $1\exec_fsm_state$next[0:0]$13680 $2\exec_fsm_state$next[0:0]$13681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $2\exec_fsm_state$next[0:0]$13681 1'1 + case + assign $2\exec_fsm_state$next[0:0]$13681 \exec_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\exec_fsm_state$next[0:0]$13680 $3\exec_fsm_state$next[0:0]$13682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + switch \$259 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $3\exec_fsm_state$next[0:0]$13682 $4\exec_fsm_state$next[0:0]$13683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:460" + switch \exec_pc_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\exec_fsm_state$next[0:0]$13683 1'0 + case + assign $4\exec_fsm_state$next[0:0]$13683 \exec_fsm_state + end + case + assign $3\exec_fsm_state$next[0:0]$13682 \exec_fsm_state + end + case + assign $1\exec_fsm_state$next[0:0]$13680 \exec_fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\exec_fsm_state$next[0:0]$13684 1'0 + case + assign $5\exec_fsm_state$next[0:0]$13684 $1\exec_fsm_state$next[0:0]$13680 + end + sync always + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13679 + end + attribute \src "libresoc.v:196118.3-196133.6" + process $proc$libresoc.v:196118$13685 + assign { } { } + assign { } { } + assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:196119.5-196119.29" + switch \initial + attribute \src "libresoc.v:196119.9-196119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + switch \$261 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { $2\core_dec$next[63:0]$13408 $2\core_eint$next[0:0]$13409 $2\core_msr$next[63:0]$13410 $2\core_core_pc$next[63:0]$13407 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign $2\exec_pc_valid_o[0:0] 1'1 + case + assign $2\exec_pc_valid_o[0:0] 1'0 end case - assign $1\core_core_pc$next[63:0]$13403 \core_core_pc - assign $1\core_dec$next[63:0]$13404 \core_dec - assign $1\core_eint$next[0:0]$13405 \core_eint - assign $1\core_msr$next[63:0]$13406 \core_msr + assign $1\exec_pc_valid_o[0:0] 1'0 + end + sync always + update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] + end + attribute \src "libresoc.v:196134.3-196143.6" + process $proc$libresoc.v:196134$13686 + assign { } { } + assign { } { } + assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:196135.5-196135.29" + switch \initial + attribute \src "libresoc.v:196135.9-196135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + case + assign $1\core_dmi__addr[4:0] 5'00000 + end + sync always + update \core_dmi__addr $0\core_dmi__addr[4:0] + end + attribute \src "libresoc.v:196144.3-196153.6" + process $proc$libresoc.v:196144$13687 + assign { } { } + assign { } { } + assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:196145.5-196145.29" + switch \initial + attribute \src "libresoc.v:196145.9-196145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__ren[0:0] 1'1 + case + assign $1\core_dmi__ren[0:0] 1'0 + end + sync always + update \core_dmi__ren $0\core_dmi__ren[0:0] + end + attribute \src "libresoc.v:196154.3-196162.6" + process $proc$libresoc.v:196154$13688 + assign { } { } + assign { } { } + assign $0\d_reg_delay$next[0:0]$13689 $1\d_reg_delay$next[0:0]$13690 + attribute \src "libresoc.v:196155.5-196155.29" + switch \initial + attribute \src "libresoc.v:196155.9-196155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_reg_delay$next[0:0]$13690 1'0 + case + assign $1\d_reg_delay$next[0:0]$13690 \dbg_d_gpr_req + end + sync always + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13689 + end + attribute \src "libresoc.v:196163.3-196172.6" + process $proc$libresoc.v:196163$13691 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:196164.5-196164.29" + switch \initial + attribute \src "libresoc.v:196164.9-196164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o + case + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + end + attribute \src "libresoc.v:196173.3-196182.6" + process $proc$libresoc.v:196173$13692 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:196174.5-196174.29" + switch \initial + attribute \src "libresoc.v:196174.9-196174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_ack[0:0] 1'1 + case + assign $1\dbg_d_gpr_ack[0:0] 1'0 + end + sync always + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + end + attribute \src "libresoc.v:196183.3-196192.6" + process $proc$libresoc.v:196183$13693 + assign { } { } + assign { } { } + assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:196184.5-196184.29" + switch \initial + attribute \src "libresoc.v:196184.9-196184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670" + switch \dbg_d_cr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd2__ren[7:0] 8'11111111 + case + assign $1\core_full_rd2__ren[7:0] 8'00000000 + end + sync always + update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] + end + attribute \src "libresoc.v:196193.3-196201.6" + process $proc$libresoc.v:196193$13694 + assign { } { } + assign { } { } + assign $0\d_cr_delay$next[0:0]$13695 $1\d_cr_delay$next[0:0]$13696 + attribute \src "libresoc.v:196194.5-196194.29" + switch \initial + attribute \src "libresoc.v:196194.9-196194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_cr_delay$next[0:0]$13696 1'0 + case + assign $1\d_cr_delay$next[0:0]$13696 \dbg_d_cr_req + end + sync always + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13695 + end + attribute \src "libresoc.v:196202.3-196211.6" + process $proc$libresoc.v:196202$13697 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:196203.5-196203.29" + switch \initial + attribute \src "libresoc.v:196203.9-196203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_data[63:0] \$263 + case + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + end + attribute \src "libresoc.v:196212.3-196221.6" + process $proc$libresoc.v:196212$13698 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:196213.5-196213.29" + switch \initial + attribute \src "libresoc.v:196213.9-196213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_ack[0:0] 1'1 + case + assign $1\dbg_d_cr_ack[0:0] 1'0 + end + sync always + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + end + attribute \src "libresoc.v:196222.3-196231.6" + process $proc$libresoc.v:196222$13699 + assign { } { } + assign { } { } + assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:196223.5-196223.29" + switch \initial + attribute \src "libresoc.v:196223.9-196223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" + switch \dbg_d_xer_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd__ren[2:0] 3'111 + case + assign $1\core_full_rd__ren[2:0] 3'000 + end + sync always + update \core_full_rd__ren $0\core_full_rd__ren[2:0] + end + attribute \src "libresoc.v:196232.3-196240.6" + process $proc$libresoc.v:196232$13700 + assign { } { } + assign { } { } + assign $0\d_xer_delay$next[0:0]$13701 $1\d_xer_delay$next[0:0]$13702 + attribute \src "libresoc.v:196233.5-196233.29" + switch \initial + attribute \src "libresoc.v:196233.9-196233.17" + case 1'1 + case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $1\d_xer_delay$next[0:0]$13702 1'0 + case + assign $1\d_xer_delay$next[0:0]$13702 \dbg_d_xer_req + end + sync always + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13701 + end + attribute \src "libresoc.v:196241.3-196250.6" + process $proc$libresoc.v:196241$13703 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:196242.5-196242.29" + switch \initial + attribute \src "libresoc.v:196242.9-196242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_data[63:0] \$265 + case + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + end + attribute \src "libresoc.v:196251.3-196260.6" + process $proc$libresoc.v:196251$13704 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:196252.5-196252.29" + switch \initial + attribute \src "libresoc.v:196252.9-196252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + end + attribute \src "libresoc.v:196261.3-196275.6" + process $proc$libresoc.v:196261$13705 + assign { } { } + assign { } { } + assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] + attribute \src "libresoc.v:196262.5-196262.29" + switch \initial + attribute \src "libresoc.v:196262.9-196262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__addr[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } + assign $1\core_issue__addr[2:0] 3'111 + case + assign $1\core_issue__addr[2:0] 3'000 + end + sync always + update \core_issue__addr $0\core_issue__addr[2:0] + end + attribute \src "libresoc.v:196276.3-196290.6" + process $proc$libresoc.v:196276$13706 + assign { } { } + assign { } { } + assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] + attribute \src "libresoc.v:196277.5-196277.29" + switch \initial + attribute \src "libresoc.v:196277.9-196277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign $3\core_core_pc$next[63:0]$13411 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13414 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13413 1'0 - assign $3\core_dec$next[63:0]$13412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_issue__ren[0:0] 1'1 case - assign $3\core_core_pc$next[63:0]$13411 $1\core_core_pc$next[63:0]$13403 - assign $3\core_dec$next[63:0]$13412 $1\core_dec$next[63:0]$13404 - assign $3\core_eint$next[0:0]$13413 $1\core_eint$next[0:0]$13405 - assign $3\core_msr$next[63:0]$13414 $1\core_msr$next[63:0]$13406 + assign $1\core_issue__ren[0:0] 1'0 end sync always - update \core_core_pc$next $0\core_core_pc$next[63:0]$13399 - update \core_dec$next $0\core_dec$next[63:0]$13400 - update \core_eint$next $0\core_eint$next[0:0]$13401 - update \core_msr$next $0\core_msr$next[63:0]$13402 + update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:185820.3-185843.6" - process $proc$libresoc.v:185820$13415 + attribute \src "libresoc.v:196291.3-196318.6" + process $proc$libresoc.v:196291$13707 assign { } { } assign { } { } assign { } { } - assign $0\ilatch$next[31:0]$13416 $3\ilatch$next[31:0]$13419 - attribute \src "libresoc.v:185821.5-185821.29" + assign $0\fsm_state$next[1:0]$13708 $2\fsm_state$next[1:0]$13710 + attribute \src "libresoc.v:196292.5-196292.29" switch \initial - attribute \src "libresoc.v:185821.9-185821.17" + attribute \src "libresoc.v:196292.9-196292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$13709 2'01 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\ilatch$next[31:0]$13417 $2\ilatch$next[31:0]$13418 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\ilatch$next[31:0]$13418 \ilatch - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ilatch$next[31:0]$13418 \$123 - end + assign $1\fsm_state$next[1:0]$13709 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$13709 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$13709 2'00 case - assign $1\ilatch$next[31:0]$13417 \ilatch + assign $1\fsm_state$next[1:0]$13709 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ilatch$next[31:0]$13419 0 + assign $2\fsm_state$next[1:0]$13710 2'00 case - assign $3\ilatch$next[31:0]$13419 $1\ilatch$next[31:0]$13417 + assign $2\fsm_state$next[1:0]$13710 $1\fsm_state$next[1:0]$13709 end sync always - update \ilatch$next $0\ilatch$next[31:0]$13416 + update \fsm_state$next $0\fsm_state$next[1:0]$13708 end - attribute \src "libresoc.v:185844.3-185863.6" - process $proc$libresoc.v:185844$13420 + attribute \src "libresoc.v:196319.3-196329.6" + process $proc$libresoc.v:196319$13711 assign { } { } assign { } { } - assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:185845.5-185845.29" + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:196320.5-196320.29" switch \initial - attribute \src "libresoc.v:185845.9-185845.17" + attribute \src "libresoc.v:196320.9-196320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 2'01 + assign { } { } + assign $1\new_dec[63:0] \$267 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_dec $0\new_dec[63:0] + end + attribute \src "libresoc.v:196330.3-196344.6" + process $proc$libresoc.v:196330$13712 + assign { } { } + assign { } { } + assign $0\core_issue__addr$13[2:0]$13713 $1\core_issue__addr$13[2:0]$13714 + attribute \src "libresoc.v:196331.5-196331.29" + switch \initial + attribute \src "libresoc.v:196331.9-196331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 assign { } { } - assign $1\core_ivalid_i[0:0] 1'1 + assign $1\core_issue__addr$13[2:0]$13714 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" - switch \$127 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_ivalid_i[0:0] 1'1 - case - assign $2\core_ivalid_i[0:0] 1'0 - end + assign $1\core_issue__addr$13[2:0]$13714 3'111 + case + assign $1\core_issue__addr$13[2:0]$13714 3'000 + end + sync always + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13713 + end + attribute \src "libresoc.v:196345.3-196359.6" + process $proc$libresoc.v:196345$13715 + assign { } { } + assign { } { } + assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] + attribute \src "libresoc.v:196346.5-196346.29" + switch \initial + attribute \src "libresoc.v:196346.9-196346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + case + assign $1\core_issue__wen[0:0] 1'0 + end + sync always + update \core_issue__wen $0\core_issue__wen[0:0] + end + attribute \src "libresoc.v:196360.3-196374.6" + process $proc$libresoc.v:196360$13716 + assign { } { } + assign { } { } + assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:196361.5-196361.29" + switch \initial + attribute \src "libresoc.v:196361.9-196361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_dec + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_tb + case + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_issue__data_i $0\core_issue__data_i[63:0] + end + attribute \src "libresoc.v:196375.3-196390.6" + process $proc$libresoc.v:196375$13717 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$13718 $2\dec2_cur_dec$next[63:0]$13720 + attribute \src "libresoc.v:196376.5-196376.29" + switch \initial + attribute \src "libresoc.v:196376.9-196376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$13719 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$13719 \dec2_cur_dec + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_dec$next[63:0]$13720 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$13720 $1\dec2_cur_dec$next[63:0]$13719 + end + sync always + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13718 + end + attribute \src "libresoc.v:196391.3-196401.6" + process $proc$libresoc.v:196391$13721 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:196392.5-196392.29" + switch \initial + attribute \src "libresoc.v:196392.9-196392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\new_tb[63:0] \$270 [63:0] case - assign $1\core_ivalid_i[0:0] 1'0 + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \core_ivalid_i $0\core_ivalid_i[0:0] + update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:185864.3-185874.6" - process $proc$libresoc.v:185864$13421 + attribute \src "libresoc.v:196402.3-196410.6" + process $proc$libresoc.v:196402$13722 assign { } { } assign { } { } - assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:185865.5-185865.29" + assign $0\dbg_dmi_we_i$next[0:0]$13723 $1\dbg_dmi_we_i$next[0:0]$13724 + attribute \src "libresoc.v:196403.5-196403.29" switch \initial - attribute \src "libresoc.v:185865.9-185865.17" + attribute \src "libresoc.v:196403.9-196403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 assign { } { } - assign $1\core_issue_i[0:0] 1'1 + assign $1\dbg_dmi_we_i$next[0:0]$13724 1'0 case - assign $1\core_issue_i[0:0] 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13724 \jtag_dmi0__we_i end sync always - update \core_issue_i $0\core_issue_i[0:0] + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13723 end - attribute \src "libresoc.v:185875.3-185884.6" - process $proc$libresoc.v:185875$13422 + attribute \src "libresoc.v:196411.3-196419.6" + process $proc$libresoc.v:196411$13725 assign { } { } assign { } { } - assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:185876.5-185876.29" + assign $0\pc_ok_delay$next[0:0]$13726 $1\pc_ok_delay$next[0:0]$13727 + attribute \src "libresoc.v:196412.5-196412.29" switch \initial - attribute \src "libresoc.v:185876.9-185876.17" + attribute \src "libresoc.v:196412.9-196412.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" - switch \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + assign $1\pc_ok_delay$next[0:0]$13727 1'0 case - assign $1\core_dmi__addr[4:0] 5'00000 + assign $1\pc_ok_delay$next[0:0]$13727 \$38 end sync always - update \core_dmi__addr $0\core_dmi__addr[4:0] + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13726 end - attribute \src "libresoc.v:185885.3-185894.6" - process $proc$libresoc.v:185885$13423 + attribute \src "libresoc.v:196420.3-196435.6" + process $proc$libresoc.v:196420$13728 assign { } { } assign { } { } - assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:185886.5-185886.29" + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:196421.5-196421.29" switch \initial - attribute \src "libresoc.v:185886.9-185886.17" + attribute \src "libresoc.v:196421.9-196421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" - switch \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" + switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_dmi__ren[0:0] 1'1 + assign $1\pc[63:0] \pc_i case - assign $1\core_dmi__ren[0:0] 1'0 + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" + switch \pc_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc[63:0] \core_cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] end sync always - update \core_dmi__ren $0\core_dmi__ren[0:0] + update \pc $0\pc[63:0] end - attribute \src "libresoc.v:185895.3-185903.6" - process $proc$libresoc.v:185895$13424 + attribute \src "libresoc.v:196436.3-196448.6" + process $proc$libresoc.v:196436$13729 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13425 $1\d_reg_delay$next[0:0]$13426 - attribute \src "libresoc.v:185896.5-185896.29" + assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] + attribute \src "libresoc.v:196437.5-196437.29" switch \initial - attribute \src "libresoc.v:185896.9-185896.17" + attribute \src "libresoc.v:196437.9-196437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" + switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign { } { } - assign $1\d_reg_delay$next[0:0]$13426 1'0 + assign $1\core_cia__ren[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case - assign $1\d_reg_delay$next[0:0]$13426 \dbg_d_gpr_req + assign { } { } + assign $1\core_cia__ren[2:0] 3'001 end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13425 + update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:185904.3-185913.6" - process $proc$libresoc.v:185904$13427 + attribute \src "libresoc.v:196449.3-196457.6" + process $proc$libresoc.v:196449$13730 assign { } { } assign { } { } - assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:185905.5-185905.29" + assign $0\svstate_ok_delay$next[0:0]$13731 $1\svstate_ok_delay$next[0:0]$13732 + attribute \src "libresoc.v:196450.5-196450.29" switch \initial - attribute \src "libresoc.v:185905.9-185905.17" + attribute \src "libresoc.v:196450.9-196450.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" - switch \d_reg_delay + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o + assign $1\svstate_ok_delay$next[0:0]$13732 1'0 case - assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\svstate_ok_delay$next[0:0]$13732 \$40 end sync always - update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13731 end - attribute \src "libresoc.v:185914.3-185923.6" - process $proc$libresoc.v:185914$13428 + attribute \src "libresoc.v:196458.3-196473.6" + process $proc$libresoc.v:196458$13733 assign { } { } assign { } { } - assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:185915.5-185915.29" + assign { } { } + assign $0\svstate[63:0] $2\svstate[63:0] + attribute \src "libresoc.v:196459.5-196459.29" switch \initial - attribute \src "libresoc.v:185915.9-185915.17" + attribute \src "libresoc.v:196459.9-196459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" - switch \d_reg_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" + switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_gpr_ack[0:0] 1'1 + assign $1\svstate[63:0] \$42 case - assign $1\dbg_d_gpr_ack[0:0] 1'0 + assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570" + switch \svstate_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\svstate[63:0] \core_sv__data_o + case + assign $2\svstate[63:0] $1\svstate[63:0] end sync always - update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + update \svstate $0\svstate[63:0] end - attribute \src "libresoc.v:185924.3-185933.6" - process $proc$libresoc.v:185924$13429 + attribute \src "libresoc.v:196474.3-196486.6" + process $proc$libresoc.v:196474$13734 assign { } { } assign { } { } - assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:185925.5-185925.29" + assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] + attribute \src "libresoc.v:196475.5-196475.29" switch \initial - attribute \src "libresoc.v:185925.9-185925.17" + attribute \src "libresoc.v:196475.9-196475.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - switch \dbg_d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" + switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign { } { } - assign $1\core_full_rd2__ren[7:0] 8'11111111 + assign $1\core_sv__ren[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case - assign $1\core_full_rd2__ren[7:0] 8'00000000 + assign { } { } + assign $1\core_sv__ren[2:0] 3'100 end sync always - update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] + update \core_sv__ren $0\core_sv__ren[2:0] end - attribute \src "libresoc.v:185934.3-185942.6" - process $proc$libresoc.v:185934$13430 + attribute \src "libresoc.v:196487.3-196495.6" + process $proc$libresoc.v:196487$13735 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13431 $1\d_cr_delay$next[0:0]$13432 - attribute \src "libresoc.v:185935.5-185935.29" + assign $0\dbg_dmi_din$next[63:0]$13736 $1\dbg_dmi_din$next[63:0]$13737 + attribute \src "libresoc.v:196488.5-196488.29" switch \initial - attribute \src "libresoc.v:185935.9-185935.17" + attribute \src "libresoc.v:196488.9-196488.17" case 1'1 case end @@ -390587,90 +410110,271 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13432 1'0 + assign $1\dbg_dmi_din$next[63:0]$13737 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\d_cr_delay$next[0:0]$13432 \dbg_d_cr_req + assign $1\dbg_dmi_din$next[63:0]$13737 \jtag_dmi0__din end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13431 + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13736 end - attribute \src "libresoc.v:185943.3-185952.6" - process $proc$libresoc.v:185943$13433 + attribute \src "libresoc.v:196496.3-196563.6" + process $proc$libresoc.v:196496$13738 assign { } { } assign { } { } - assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:185944.5-185944.29" + assign $0\core_wen[2:0] $1\core_wen[2:0] + attribute \src "libresoc.v:196497.5-196497.29" switch \initial - attribute \src "libresoc.v:185944.9-185944.17" + attribute \src "libresoc.v:196497.9-196497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" - switch \d_cr_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'000 + assign { } { } + assign $1\core_wen[2:0] $2\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_wen[2:0] $3\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_wen[2:0] 3'001 + case + assign $3\core_wen[2:0] 3'000 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_wen[2:0] $4\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_wen[2:0] $5\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \$52 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\core_wen[2:0] 3'001 + case + assign $5\core_wen[2:0] 3'000 + end + case + assign $4\core_wen[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$129 + assign $1\core_wen[2:0] $6\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$58 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\core_wen[2:0] $7\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\core_wen[2:0] $8\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$64 \$60 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $8\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $8\core_wen[2:0] 3'001 + case + assign $8\core_wen[2:0] 3'000 + end + case + assign $7\core_wen[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\core_wen[2:0] $9\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\core_wen[2:0] 3'001 + case + assign $9\core_wen[2:0] 3'000 + end + end case - assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_wen[2:0] 3'000 end sync always - update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:185953.3-185962.6" - process $proc$libresoc.v:185953$13434 + attribute \src "libresoc.v:196564.3-196631.6" + process $proc$libresoc.v:196564$13739 assign { } { } assign { } { } - assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:185954.5-185954.29" + assign $0\core_data_i[63:0] $1\core_data_i[63:0] + attribute \src "libresoc.v:196565.5-196565.29" switch \initial - attribute \src "libresoc.v:185954.9-185954.17" + attribute \src "libresoc.v:196565.9-196565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" - switch \d_cr_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'000 assign { } { } - assign $1\dbg_d_cr_ack[0:0] 1'1 + assign $1\core_data_i[63:0] $2\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$70 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_data_i[63:0] $3\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_data_i[63:0] \pc_i + case + assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_data_i[63:0] $4\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_data_i[63:0] $5\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \$74 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\core_data_i[63:0] \nia + case + assign $5\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\core_data_i[63:0] $6\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$80 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\core_data_i[63:0] $7\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\core_data_i[63:0] $8\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$86 \$82 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $8\core_data_i[63:0] \nia + case + assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $7\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\core_data_i[63:0] $9\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\core_data_i[63:0] \pc_i + case + assign $9\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end case - assign $1\dbg_d_cr_ack[0:0] 1'0 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:185963.3-185972.6" - process $proc$libresoc.v:185963$13435 + attribute \src "libresoc.v:196632.3-196647.6" + process $proc$libresoc.v:196632$13740 assign { } { } assign { } { } - assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:185964.5-185964.29" + assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] + attribute \src "libresoc.v:196633.5-196633.29" switch \initial - attribute \src "libresoc.v:185964.9-185964.17" + attribute \src "libresoc.v:196633.9-196633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - switch \dbg_d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'00 assign { } { } - assign $1\core_full_rd__ren[2:0] 3'111 + assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_msr__ren[2:0] 3'010 + case + assign $2\core_msr__ren[2:0] 3'000 + end case - assign $1\core_full_rd__ren[2:0] 3'000 + assign $1\core_msr__ren[2:0] 3'000 end sync always - update \core_full_rd__ren $0\core_full_rd__ren[2:0] + update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:185973.3-185981.6" - process $proc$libresoc.v:185973$13436 + attribute \src "libresoc.v:196648.3-196656.6" + process $proc$libresoc.v:196648$13741 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13437 $1\d_xer_delay$next[0:0]$13438 - attribute \src "libresoc.v:185974.5-185974.29" + assign $0\jtag_dmi0__ack_o$next[0:0]$13742 $1\jtag_dmi0__ack_o$next[0:0]$13743 + attribute \src "libresoc.v:196649.5-196649.29" switch \initial - attribute \src "libresoc.v:185974.9-185974.17" + attribute \src "libresoc.v:196649.9-196649.17" case 1'1 case end @@ -390679,606 +410383,1424 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13438 1'0 + assign $1\jtag_dmi0__ack_o$next[0:0]$13743 1'0 case - assign $1\d_xer_delay$next[0:0]$13438 \dbg_d_xer_req + assign $1\jtag_dmi0__ack_o$next[0:0]$13743 \dbg_dmi_ack_o end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13437 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13742 end - attribute \src "libresoc.v:185982.3-185991.6" - process $proc$libresoc.v:185982$13439 + attribute \src "libresoc.v:196657.3-196667.6" + process $proc$libresoc.v:196657$13744 assign { } { } assign { } { } - assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:185983.5-185983.29" + assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:196658.5-196658.29" switch \initial - attribute \src "libresoc.v:185983.9-185983.17" + attribute \src "libresoc.v:196658.9-196658.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - switch \d_xer_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'00 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$131 + assign $1\fetch_pc_ready_o[0:0] 1'1 case - assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fetch_pc_ready_o[0:0] 1'0 end sync always - update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:185992.3-186001.6" - process $proc$libresoc.v:185992$13440 + attribute \src "libresoc.v:196668.3-196683.6" + process $proc$libresoc.v:196668$13745 assign { } { } assign { } { } - assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:185993.5-185993.29" + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:196669.5-196669.29" switch \initial - attribute \src "libresoc.v:185993.9-185993.17" + attribute \src "libresoc.v:196669.9-196669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - switch \d_xer_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'00 assign { } { } - assign $1\dbg_d_xer_ack[0:0] 1'1 + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end case - assign $1\dbg_d_xer_ack[0:0] 1'0 + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 end sync always - update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:186002.3-186016.6" - process $proc$libresoc.v:186002$13441 + attribute \src "libresoc.v:196684.3-196717.6" + process $proc$libresoc.v:196684$13746 assign { } { } assign { } { } - assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:186003.5-186003.29" + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:196685.5-196685.29" switch \initial - attribute \src "libresoc.v:186003.9-186003.17" + attribute \src "libresoc.v:196685.9-196685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\core_issue__addr[2:0] 3'110 + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 2'01 assign { } { } - assign $1\core_issue__addr[2:0] 3'111 + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\imem_a_valid_i[0:0] 1'1 + case + assign $4\imem_a_valid_i[0:0] 1'0 + end case - assign $1\core_issue__addr[2:0] 3'000 + assign $1\imem_a_valid_i[0:0] 1'0 end sync always - update \core_issue__addr $0\core_issue__addr[2:0] + update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:186017.3-186031.6" - process $proc$libresoc.v:186017$13442 + attribute \src "libresoc.v:196718.3-196751.6" + process $proc$libresoc.v:196718$13747 assign { } { } assign { } { } - assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:186018.5-186018.29" + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:196719.5-196719.29" switch \initial - attribute \src "libresoc.v:186018.9-186018.17" + attribute \src "libresoc.v:196719.9-196719.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\core_issue__ren[0:0] 1'1 + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 2'01 assign { } { } - assign $1\core_issue__ren[0:0] 1'1 + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\imem_f_valid_i[0:0] 1'1 + case + assign $4\imem_f_valid_i[0:0] 1'0 + end case - assign $1\core_issue__ren[0:0] 1'0 + assign $1\imem_f_valid_i[0:0] 1'0 end sync always - update \core_issue__ren $0\core_issue__ren[0:0] + update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:186032.3-186059.6" - process $proc$libresoc.v:186032$13443 + attribute \src "libresoc.v:196752.3-196772.6" + process $proc$libresoc.v:196752$13748 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$133$next[1:0]$13444 $2\fsm_state$133$next[1:0]$13446 - attribute \src "libresoc.v:186033.5-186033.29" + assign $0\dec2_cur_pc$next[63:0]$13749 $3\dec2_cur_pc$next[63:0]$13752 + attribute \src "libresoc.v:196753.5-196753.29" switch \initial - attribute \src "libresoc.v:186033.9-186033.17" + attribute \src "libresoc.v:196753.9-196753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$133$next[1:0]$13445 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\fsm_state$133$next[1:0]$13445 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\fsm_state$133$next[1:0]$13445 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\fsm_state$133$next[1:0]$13445 2'00 + assign $1\dec2_cur_pc$next[63:0]$13750 $2\dec2_cur_pc$next[63:0]$13751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$13751 \pc + case + assign $2\dec2_cur_pc$next[63:0]$13751 \dec2_cur_pc + end case - assign $1\fsm_state$133$next[1:0]$13445 \fsm_state$133 + assign $1\dec2_cur_pc$next[63:0]$13750 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$133$next[1:0]$13446 2'00 + assign $3\dec2_cur_pc$next[63:0]$13752 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\fsm_state$133$next[1:0]$13446 $1\fsm_state$133$next[1:0]$13445 + assign $3\dec2_cur_pc$next[63:0]$13752 $1\dec2_cur_pc$next[63:0]$13750 end sync always - update \fsm_state$133$next $0\fsm_state$133$next[1:0]$13444 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13749 end - attribute \src "libresoc.v:186060.3-186070.6" - process $proc$libresoc.v:186060$13447 + attribute \src "libresoc.v:196773.3-196811.6" + process $proc$libresoc.v:196773$13753 assign { } { } assign { } { } - assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:186061.5-186061.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cur_cur_dststep$next[6:0]$13754 $4\cur_cur_dststep$next[6:0]$13778 + assign $0\cur_cur_maxvl$next[6:0]$13755 $4\cur_cur_maxvl$next[6:0]$13779 + assign $0\cur_cur_srcstep$next[6:0]$13756 $4\cur_cur_srcstep$next[6:0]$13780 + assign $0\cur_cur_subvl$next[1:0]$13757 $4\cur_cur_subvl$next[1:0]$13781 + assign $0\cur_cur_svstep$next[1:0]$13758 $4\cur_cur_svstep$next[1:0]$13782 + assign $0\cur_cur_vl$next[6:0]$13759 $4\cur_cur_vl$next[6:0]$13783 + attribute \src "libresoc.v:196774.5-196774.29" switch \initial - attribute \src "libresoc.v:186061.9-186061.17" + attribute \src "libresoc.v:196774.9-196774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cur_cur_dststep$next[6:0]$13760 $2\cur_cur_dststep$next[6:0]$13766 + assign $1\cur_cur_maxvl$next[6:0]$13761 $2\cur_cur_maxvl$next[6:0]$13767 + assign $1\cur_cur_srcstep$next[6:0]$13762 $2\cur_cur_srcstep$next[6:0]$13768 + assign $1\cur_cur_subvl$next[1:0]$13763 $2\cur_cur_subvl$next[1:0]$13769 + assign $1\cur_cur_svstep$next[1:0]$13764 $2\cur_cur_svstep$next[1:0]$13770 + assign $1\cur_cur_vl$next[6:0]$13765 $2\cur_cur_vl$next[6:0]$13771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\cur_cur_maxvl$next[6:0]$13767 $2\cur_cur_vl$next[6:0]$13771 $2\cur_cur_srcstep$next[6:0]$13768 $2\cur_cur_dststep$next[6:0]$13766 $2\cur_cur_subvl$next[1:0]$13769 $2\cur_cur_svstep$next[1:0]$13770 } \svstate [31:0] + case + assign $2\cur_cur_dststep$next[6:0]$13766 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13767 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13768 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13769 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13770 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13771 \cur_cur_vl + end + case + assign $1\cur_cur_dststep$next[6:0]$13760 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13761 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13762 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13763 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13764 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13765 \cur_cur_vl + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + switch \update_svstate + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } assign { } { } - assign $1\new_dec[63:0] \$134 [63:0] + assign { } { } + assign { } { } + assign { $3\cur_cur_maxvl$next[6:0]$13773 $3\cur_cur_vl$next[6:0]$13777 $3\cur_cur_srcstep$next[6:0]$13774 $3\cur_cur_dststep$next[6:0]$13772 $3\cur_cur_subvl$next[1:0]$13775 $3\cur_cur_svstep$next[1:0]$13776 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\cur_cur_dststep$next[6:0]$13772 $1\cur_cur_dststep$next[6:0]$13760 + assign $3\cur_cur_maxvl$next[6:0]$13773 $1\cur_cur_maxvl$next[6:0]$13761 + assign $3\cur_cur_srcstep$next[6:0]$13774 $1\cur_cur_srcstep$next[6:0]$13762 + assign $3\cur_cur_subvl$next[1:0]$13775 $1\cur_cur_subvl$next[1:0]$13763 + assign $3\cur_cur_svstep$next[1:0]$13776 $1\cur_cur_svstep$next[1:0]$13764 + assign $3\cur_cur_vl$next[6:0]$13777 $1\cur_cur_vl$next[6:0]$13765 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\cur_cur_svstep$next[1:0]$13782 2'00 + assign $4\cur_cur_subvl$next[1:0]$13781 2'00 + assign $4\cur_cur_dststep$next[6:0]$13778 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13780 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13783 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13779 7'0000000 + case + assign $4\cur_cur_dststep$next[6:0]$13778 $3\cur_cur_dststep$next[6:0]$13772 + assign $4\cur_cur_maxvl$next[6:0]$13779 $3\cur_cur_maxvl$next[6:0]$13773 + assign $4\cur_cur_srcstep$next[6:0]$13780 $3\cur_cur_srcstep$next[6:0]$13774 + assign $4\cur_cur_subvl$next[1:0]$13781 $3\cur_cur_subvl$next[1:0]$13775 + assign $4\cur_cur_svstep$next[1:0]$13782 $3\cur_cur_svstep$next[1:0]$13776 + assign $4\cur_cur_vl$next[6:0]$13783 $3\cur_cur_vl$next[6:0]$13777 end sync always - update \new_dec $0\new_dec[63:0] + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13754 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13755 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13756 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13757 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13758 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13759 end - attribute \src "libresoc.v:186071.3-186085.6" - process $proc$libresoc.v:186071$13448 + attribute \src "libresoc.v:196812.3-196820.6" + process $proc$libresoc.v:196812$13784 assign { } { } assign { } { } - assign $0\core_issue__addr$11[2:0]$13449 $1\core_issue__addr$11[2:0]$13450 - attribute \src "libresoc.v:186072.5-186072.29" + assign $0\jtag_dmi0__dout$next[63:0]$13785 $1\jtag_dmi0__dout$next[63:0]$13786 + attribute \src "libresoc.v:196813.5-196813.29" switch \initial - attribute \src "libresoc.v:186072.9-186072.17" + attribute \src "libresoc.v:196813.9-196813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\core_issue__addr$11[2:0]$13450 3'110 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\core_issue__addr$11[2:0]$13450 3'111 + assign $1\jtag_dmi0__dout$next[63:0]$13786 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\core_issue__addr$11[2:0]$13450 3'000 + assign $1\jtag_dmi0__dout$next[63:0]$13786 \dbg_dmi_dout end sync always - update \core_issue__addr$11 $0\core_issue__addr$11[2:0]$13449 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13785 end - attribute \src "libresoc.v:186086.3-186100.6" - process $proc$libresoc.v:186086$13451 + attribute \src "libresoc.v:196821.3-196850.6" + process $proc$libresoc.v:196821$13787 assign { } { } assign { } { } - assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:186087.5-186087.29" + assign { } { } + assign $0\msr_read$next[0:0]$13788 $4\msr_read$next[0:0]$13792 + attribute \src "libresoc.v:196822.5-196822.29" switch \initial - attribute \src "libresoc.v:186087.9-186087.17" + attribute \src "libresoc.v:196822.9-196822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$13789 $2\msr_read$next[0:0]$13790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$13790 1'0 + case + assign $2\msr_read$next[0:0]$13790 \msr_read + end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__wen[0:0] 1'1 + assign $1\msr_read$next[0:0]$13789 $3\msr_read$next[0:0]$13791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + switch \$88 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$13791 1'1 + case + assign $3\msr_read$next[0:0]$13791 \msr_read + end + case + assign $1\msr_read$next[0:0]$13789 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\core_issue__wen[0:0] 1'1 + assign $4\msr_read$next[0:0]$13792 1'1 case - assign $1\core_issue__wen[0:0] 1'0 + assign $4\msr_read$next[0:0]$13792 $1\msr_read$next[0:0]$13789 end sync always - update \core_issue__wen $0\core_issue__wen[0:0] + update \msr_read$next $0\msr_read$next[0:0]$13788 end - attribute \src "libresoc.v:186101.3-186115.6" - process $proc$libresoc.v:186101$13452 + attribute \src "libresoc.v:196851.3-196904.6" + process $proc$libresoc.v:196851$13793 assign { } { } assign { } { } - assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:186102.5-186102.29" + assign { } { } + assign $0\fetch_fsm_state$next[1:0]$13794 $6\fetch_fsm_state$next[1:0]$13800 + attribute \src "libresoc.v:196852.5-196852.29" switch \initial - attribute \src "libresoc.v:186102.9-186102.17" + attribute \src "libresoc.v:196852.9-196852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13795 $2\fetch_fsm_state$next[1:0]$13796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fetch_fsm_state$next[1:0]$13796 2'01 + case + assign $2\fetch_fsm_state$next[1:0]$13796 \fetch_fsm_state + end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__data_i[63:0] \new_dec + assign $1\fetch_fsm_state$next[1:0]$13795 $3\fetch_fsm_state$next[1:0]$13797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fetch_fsm_state$next[1:0]$13797 \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\fetch_fsm_state$next[1:0]$13797 2'10 + end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__data_i[63:0] \new_tb + assign $1\fetch_fsm_state$next[1:0]$13795 $4\fetch_fsm_state$next[1:0]$13798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\fetch_fsm_state$next[1:0]$13798 \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fetch_fsm_state$next[1:0]$13798 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13795 $5\fetch_fsm_state$next[1:0]$13799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:254" + switch \fetch_insn_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fetch_fsm_state$next[1:0]$13799 2'00 + case + assign $5\fetch_fsm_state$next[1:0]$13799 \fetch_fsm_state + end case - assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fetch_fsm_state$next[1:0]$13795 \fetch_fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fetch_fsm_state$next[1:0]$13800 2'00 + case + assign $6\fetch_fsm_state$next[1:0]$13800 $1\fetch_fsm_state$next[1:0]$13795 end sync always - update \core_issue__data_i $0\core_issue__data_i[63:0] + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13794 end - attribute \src "libresoc.v:186116.3-186131.6" - process $proc$libresoc.v:186116$13453 + attribute \src "libresoc.v:196905.3-196925.6" + process $proc$libresoc.v:196905$13801 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13454 $2\dec2_cur_dec$next[63:0]$13456 - attribute \src "libresoc.v:186117.5-186117.29" + assign $0\dec2_cur_msr$next[63:0]$13802 $3\dec2_cur_msr$next[63:0]$13805 + attribute \src "libresoc.v:196906.5-196906.29" switch \initial - attribute \src "libresoc.v:186117.9-186117.17" + attribute \src "libresoc.v:196906.9-196906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13455 \new_dec + assign $1\dec2_cur_msr$next[63:0]$13803 $2\dec2_cur_msr$next[63:0]$13804 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + switch \$90 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$13804 \core_msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$13804 \dec2_cur_msr + end case - assign $1\dec2_cur_dec$next[63:0]$13455 \dec2_cur_dec + assign $1\dec2_cur_msr$next[63:0]$13803 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13456 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_msr$next[63:0]$13805 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13456 $1\dec2_cur_dec$next[63:0]$13455 + assign $3\dec2_cur_msr$next[63:0]$13805 $1\dec2_cur_msr$next[63:0]$13803 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13454 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13802 end - attribute \src "libresoc.v:186132.3-186142.6" - process $proc$libresoc.v:186132$13457 + attribute \src "libresoc.v:196926.3-196944.6" + process $proc$libresoc.v:196926$13806 assign { } { } assign { } { } - assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:186133.5-186133.29" + assign $0\nia$next[63:0]$13807 $1\nia$next[63:0]$13808 + attribute \src "libresoc.v:196927.5-196927.29" switch \initial - attribute \src "libresoc.v:186133.9-186133.17" + attribute \src "libresoc.v:196927.9-196927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 2'01 assign { } { } - assign $1\new_tb[63:0] \$137 [63:0] + assign $1\nia$next[63:0]$13808 $2\nia$next[63:0]$13809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\nia$next[63:0]$13809 \nia + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\nia$next[63:0]$13809 \$92 [63:0] + end case - assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\nia$next[63:0]$13808 \nia end sync always - update \new_tb $0\new_tb[63:0] + update \nia$next $0\nia$next[63:0]$13807 end - attribute \src "libresoc.v:186143.3-186151.6" - process $proc$libresoc.v:186143$13458 + attribute \src "libresoc.v:196945.3-196975.6" + process $proc$libresoc.v:196945$13810 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13459 $1\dbg_dmi_we_i$next[0:0]$13460 - attribute \src "libresoc.v:186144.5-186144.29" + assign $0\dec2_raw_opcode_in$next[31:0]$13811 $1\dec2_raw_opcode_in$next[31:0]$13812 + attribute \src "libresoc.v:196946.5-196946.29" switch \initial - attribute \src "libresoc.v:186144.9-186144.17" + attribute \src "libresoc.v:196946.9-196946.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13460 1'0 + assign $1\dec2_raw_opcode_in$next[31:0]$13812 $2\dec2_raw_opcode_in$next[31:0]$13813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in$next[31:0]$13813 \dec2_raw_opcode_in + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in$next[31:0]$13813 \$95 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\dec2_raw_opcode_in$next[31:0]$13812 $3\dec2_raw_opcode_in$next[31:0]$13814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\dec2_raw_opcode_in$next[31:0]$13814 \dec2_raw_opcode_in + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\dec2_raw_opcode_in$next[31:0]$13814 \$99 + end case - assign $1\dbg_dmi_we_i$next[0:0]$13460 \jtag_dmi0__we_i + assign $1\dec2_raw_opcode_in$next[31:0]$13812 \dec2_raw_opcode_in end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13459 + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13811 end - attribute \src "libresoc.v:186152.3-186160.6" - process $proc$libresoc.v:186152$13461 + attribute \src "libresoc.v:196976.3-196986.6" + process $proc$libresoc.v:196976$13815 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13462 $1\pc_ok_delay$next[0:0]$13463 - attribute \src "libresoc.v:186153.5-186153.29" + assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:196977.5-196977.29" switch \initial - attribute \src "libresoc.v:186153.9-186153.17" + attribute \src "libresoc.v:196977.9-196977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13463 1'0 + assign $1\fetch_insn_valid_o[0:0] 1'1 case - assign $1\pc_ok_delay$next[0:0]$13463 \$39 + assign $1\fetch_insn_valid_o[0:0] 1'0 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13462 + update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:186161.3-186176.6" - process $proc$libresoc.v:186161$13464 + attribute \src "libresoc.v:196987.3-197043.6" + process $proc$libresoc.v:196987$13816 assign { } { } assign { } { } assign { } { } - assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:186162.5-186162.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\new_svstate_dststep[6:0] $1\new_svstate_dststep[6:0] + assign $0\new_svstate_maxvl[6:0] $1\new_svstate_maxvl[6:0] + assign $0\new_svstate_srcstep[6:0] $1\new_svstate_srcstep[6:0] + assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] + assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] + assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] + attribute \src "libresoc.v:196988.5-196988.29" switch \initial - attribute \src "libresoc.v:186162.9-186162.17" + attribute \src "libresoc.v:196988.9-196988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" - switch \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'000 assign { } { } - assign $1\pc[63:0] \pc_i - case - assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \pc_ok_delay + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\new_svstate_dststep[6:0] $2\new_svstate_dststep[6:0] + assign $1\new_svstate_maxvl[6:0] $2\new_svstate_maxvl[6:0] + assign $1\new_svstate_srcstep[6:0] $2\new_svstate_srcstep[6:0] + assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0] + assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0] + assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$110 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\new_svstate_dststep[6:0] \cur_cur_dststep + assign $2\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $2\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $2\new_svstate_subvl[1:0] \cur_cur_subvl + assign $2\new_svstate_svstep[1:0] \cur_cur_svstep + assign $2\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\new_svstate_dststep[6:0] $3\new_svstate_dststep[6:0] + assign $2\new_svstate_maxvl[6:0] $3\new_svstate_maxvl[6:0] + assign $2\new_svstate_srcstep[6:0] $3\new_svstate_srcstep[6:0] + assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0] + assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0] + assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\new_svstate_maxvl[6:0] $3\new_svstate_vl[6:0] $3\new_svstate_srcstep[6:0] $3\new_svstate_dststep[6:0] $3\new_svstate_subvl[1:0] $3\new_svstate_svstep[1:0] } \svstate_i + case + assign $3\new_svstate_dststep[6:0] \cur_cur_dststep + assign $3\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $3\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $3\new_svstate_subvl[1:0] \cur_cur_subvl + assign $3\new_svstate_svstep[1:0] \cur_cur_svstep + assign $3\new_svstate_vl[6:0] \cur_cur_vl + end + end attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'011 assign { } { } - assign $2\pc[63:0] \core_cia__data_o + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\new_svstate_dststep[6:0] $4\new_svstate_dststep[6:0] + assign $1\new_svstate_maxvl[6:0] $4\new_svstate_maxvl[6:0] + assign $1\new_svstate_srcstep[6:0] $4\new_svstate_srcstep[6:0] + assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] + assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] + assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\new_svstate_dststep[6:0] \cur_cur_dststep + assign $4\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign { } { } + assign $4\new_svstate_subvl[1:0] \cur_cur_subvl + assign $4\new_svstate_svstep[1:0] \cur_cur_svstep + assign $4\new_svstate_vl[6:0] \cur_cur_vl + assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$122 \$118 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\new_svstate_srcstep[6:0] \next_srcstep + end + case + assign $5\new_svstate_srcstep[6:0] \cur_cur_srcstep + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] + assign $4\new_svstate_maxvl[6:0] $5\new_svstate_maxvl[6:0] + assign $4\new_svstate_srcstep[6:0] $7\new_svstate_srcstep[6:0] + assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] + assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] + assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $7\new_svstate_srcstep[6:0] $5\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i + case + assign $5\new_svstate_dststep[6:0] \cur_cur_dststep + assign $5\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $7\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $5\new_svstate_subvl[1:0] \cur_cur_subvl + assign $5\new_svstate_svstep[1:0] \cur_cur_svstep + assign $5\new_svstate_vl[6:0] \cur_cur_vl + end + end case - assign $2\pc[63:0] $1\pc[63:0] + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl end sync always - update \pc $0\pc[63:0] + update \new_svstate_dststep $0\new_svstate_dststep[6:0] + update \new_svstate_maxvl $0\new_svstate_maxvl[6:0] + update \new_svstate_srcstep $0\new_svstate_srcstep[6:0] + update \new_svstate_subvl $0\new_svstate_subvl[1:0] + update \new_svstate_svstep $0\new_svstate_svstep[1:0] + update \new_svstate_vl $0\new_svstate_vl[6:0] end - attribute \src "libresoc.v:186177.3-186189.6" - process $proc$libresoc.v:186177$13465 + attribute \src "libresoc.v:197044.3-197059.6" + process $proc$libresoc.v:197044$13817 assign { } { } assign { } { } - assign $0\core_cia__ren[3:0] $1\core_cia__ren[3:0] - attribute \src "libresoc.v:186178.5-186178.29" + assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:197045.5-197045.29" switch \initial - attribute \src "libresoc.v:186178.9-186178.17" + attribute \src "libresoc.v:197045.9-197045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" - switch \pc_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\core_cia__ren[3:0] 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case + case 3'000 assign { } { } - assign $1\core_cia__ren[3:0] 4'0001 + assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$128 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fetch_pc_valid_i[0:0] 1'1 + case + assign $2\fetch_pc_valid_i[0:0] 1'0 + end + case + assign $1\fetch_pc_valid_i[0:0] 1'0 end sync always - update \core_cia__ren $0\core_cia__ren[3:0] + update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end - attribute \src "libresoc.v:186190.3-186210.6" - process $proc$libresoc.v:186190$13466 + attribute \src "libresoc.v:197060.3-197140.6" + process $proc$libresoc.v:197060$13818 + assign { } { } assign { } { } assign { } { } - assign $0\core_wen[3:0] $1\core_wen[3:0] - attribute \src "libresoc.v:186191.5-186191.29" + assign $0\issue_fsm_state$next[2:0]$13819 $10\issue_fsm_state$next[2:0]$13829 + attribute \src "libresoc.v:197061.5-197061.29" switch \initial - attribute \src "libresoc.v:186191.9-186191.17" + attribute \src "libresoc.v:197061.9-197061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'000 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$13820 $2\issue_fsm_state$next[2:0]$13821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$134 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\issue_fsm_state$next[2:0]$13821 $3\issue_fsm_state$next[2:0]$13822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + switch \fetch_pc_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\issue_fsm_state$next[2:0]$13822 3'001 + case + assign $3\issue_fsm_state$next[2:0]$13822 \issue_fsm_state + end + case + assign $2\issue_fsm_state$next[2:0]$13821 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$13820 $4\issue_fsm_state$next[2:0]$13823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\issue_fsm_state$next[2:0]$13823 $5\issue_fsm_state$next[2:0]$13824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \$138 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\issue_fsm_state$next[2:0]$13824 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\issue_fsm_state$next[2:0]$13824 3'010 + end + case + assign $4\issue_fsm_state$next[2:0]$13823 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$13820 $6\issue_fsm_state$next[2:0]$13825 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" + switch \exec_insn_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\issue_fsm_state$next[2:0]$13825 3'011 + case + assign $6\issue_fsm_state$next[2:0]$13825 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 assign { } { } - assign $1\core_wen[3:0] $2\core_wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$41 + assign $1\issue_fsm_state$next[2:0]$13820 $7\issue_fsm_state$next[2:0]$13826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_wen[3:0] $3\core_wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - switch \$43 + assign $7\issue_fsm_state$next[2:0]$13826 $8\issue_fsm_state$next[2:0]$13827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_wen[3:0] 4'0001 + assign $8\issue_fsm_state$next[2:0]$13827 $9\issue_fsm_state$next[2:0]$13828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$150 \$146 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $9\issue_fsm_state$next[2:0]$13828 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $9\issue_fsm_state$next[2:0]$13828 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $9\issue_fsm_state$next[2:0]$13828 3'100 + end case - assign $3\core_wen[3:0] 4'0000 + assign $8\issue_fsm_state$next[2:0]$13827 \issue_fsm_state end case - assign $2\core_wen[3:0] 4'0000 + assign $7\issue_fsm_state$next[2:0]$13826 \issue_fsm_state end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$13820 3'010 + case + assign $1\issue_fsm_state$next[2:0]$13820 \issue_fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\issue_fsm_state$next[2:0]$13829 3'000 case - assign $1\core_wen[3:0] 4'0000 + assign $10\issue_fsm_state$next[2:0]$13829 $1\issue_fsm_state$next[2:0]$13820 end sync always - update \core_wen $0\core_wen[3:0] + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13819 end - attribute \src "libresoc.v:186211.3-186231.6" - process $proc$libresoc.v:186211$13467 + attribute \src "libresoc.v:197141.3-197171.6" + process $proc$libresoc.v:197141$13830 assign { } { } assign { } { } - assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:186212.5-186212.29" + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:197142.5-197142.29" switch \initial - attribute \src "libresoc.v:186212.9-186212.17" + attribute \src "libresoc.v:197142.9-197142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'000 assign { } { } - assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$45 + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$156 attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - switch \$47 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_data_i[63:0] \nia - case - assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $2\core_stopped_i[0:0] 1'1 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$162 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case - assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign $3\core_stopped_i[0:0] 1'1 end case - assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_stopped_i[0:0] 1'0 end sync always - update \core_data_i $0\core_data_i[63:0] + update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:186232.3-186247.6" - process $proc$libresoc.v:186232$13468 + attribute \src "libresoc.v:197172.3-197202.6" + process $proc$libresoc.v:197172$13831 assign { } { } assign { } { } - assign $0\core_msr__ren[3:0] $1\core_msr__ren[3:0] - attribute \src "libresoc.v:186233.5-186233.29" + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:197173.5-197173.29" switch \initial - attribute \src "libresoc.v:186233.9-186233.17" + attribute \src "libresoc.v:197173.9-197173.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 3'000 assign { } { } - assign $1\core_msr__ren[3:0] $2\core_msr__ren[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$53 + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$168 attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $2\core_msr__ren[3:0] 4'0010 + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$174 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case - assign $2\core_msr__ren[3:0] 4'0000 + assign { } { } + assign $3\dbg_core_stopped_i[0:0] 1'1 end case - assign $1\core_msr__ren[3:0] 4'0000 + assign $1\dbg_core_stopped_i[0:0] 1'0 end sync always - update \core_msr__ren $0\core_msr__ren[3:0] + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:186248.3-186256.6" - process $proc$libresoc.v:186248$13469 + attribute \src "libresoc.v:197203.3-197269.6" + process $proc$libresoc.v:197203$13832 + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13470 $1\dbg_dmi_din$next[63:0]$13471 - attribute \src "libresoc.v:186249.5-186249.29" + assign $0\pc_changed$next[0:0]$13833 $9\pc_changed$next[0:0]$13842 + attribute \src "libresoc.v:197204.5-197204.29" switch \initial - attribute \src "libresoc.v:186249.9-186249.17" + attribute \src "libresoc.v:197204.9-197204.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\pc_changed$next[0:0]$13834 $2\pc_changed$next[0:0]$13835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$180 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\pc_changed$next[0:0]$13835 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\pc_changed$next[0:0]$13835 $3\pc_changed$next[0:0]$13836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$13836 1'1 + case + assign $3\pc_changed$next[0:0]$13836 \pc_changed + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\pc_changed$next[0:0]$13834 $4\pc_changed$next[0:0]$13837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$186 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\pc_changed$next[0:0]$13837 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\pc_changed$next[0:0]$13837 $5\pc_changed$next[0:0]$13838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\pc_changed$next[0:0]$13838 1'1 + case + assign $5\pc_changed$next[0:0]$13838 \pc_changed + end + end + case + assign $1\pc_changed$next[0:0]$13834 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $6\pc_changed$next[0:0]$13839 $7\pc_changed$next[0:0]$13840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\pc_changed$next[0:0]$13840 1'0 + case + assign $7\pc_changed$next[0:0]$13840 $1\pc_changed$next[0:0]$13834 + end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\pc_changed$next[0:0]$13839 $8\pc_changed$next[0:0]$13841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" + switch \$188 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\pc_changed$next[0:0]$13841 1'1 + case + assign $8\pc_changed$next[0:0]$13841 $1\pc_changed$next[0:0]$13834 + end + case + assign $6\pc_changed$next[0:0]$13839 $1\pc_changed$next[0:0]$13834 + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13471 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $9\pc_changed$next[0:0]$13842 1'0 + case + assign $9\pc_changed$next[0:0]$13842 $6\pc_changed$next[0:0]$13839 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$13833 + end + attribute \src "libresoc.v:197270.3-197326.6" + process $proc$libresoc.v:197270$13843 + assign { } { } + assign { } { } + assign $0\update_svstate[0:0] $1\update_svstate[0:0] + attribute \src "libresoc.v:197271.5-197271.29" + switch \initial + attribute \src "libresoc.v:197271.9-197271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\update_svstate[0:0] $2\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$196 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\update_svstate[0:0] $3\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\update_svstate[0:0] 1'1 + case + assign $3\update_svstate[0:0] 1'0 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\update_svstate[0:0] $4\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$202 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\update_svstate[0:0] $5\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\update_svstate[0:0] $6\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$208 \$204 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $6\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $6\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\update_svstate[0:0] 1'1 + end + case + assign $5\update_svstate[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\update_svstate[0:0] $7\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\update_svstate[0:0] 1'1 + case + assign $7\update_svstate[0:0] 1'0 + end + end case - assign $1\dbg_dmi_din$next[63:0]$13471 \jtag_dmi0__din + assign $1\update_svstate[0:0] 1'0 end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13470 + update \update_svstate $0\update_svstate[0:0] end - attribute \src "libresoc.v:186257.3-186281.6" - process $proc$libresoc.v:186257$13472 + attribute \src "libresoc.v:197327.3-197393.6" + process $proc$libresoc.v:197327$13844 assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$13473 $3\pc_changed$next[0:0]$13476 - attribute \src "libresoc.v:186258.5-186258.29" + assign { } { } + assign $0\sv_changed$next[0:0]$13845 $9\sv_changed$next[0:0]$13854 + attribute \src "libresoc.v:197328.5-197328.29" switch \initial - attribute \src "libresoc.v:186258.9-186258.17" + attribute \src "libresoc.v:197328.9-197328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 3'000 assign { } { } - assign $1\pc_changed$next[0:0]$13474 1'0 + assign $1\sv_changed$next[0:0]$13846 $2\sv_changed$next[0:0]$13847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$214 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\sv_changed$next[0:0]$13847 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\sv_changed$next[0:0]$13847 $3\sv_changed$next[0:0]$13848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv_changed$next[0:0]$13848 1'1 + case + assign $3\sv_changed$next[0:0]$13848 \sv_changed + end + end attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 + assign { } { } + assign $1\sv_changed$next[0:0]$13846 $4\sv_changed$next[0:0]$13849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$220 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\sv_changed$next[0:0]$13849 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\sv_changed$next[0:0]$13849 $5\sv_changed$next[0:0]$13850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv_changed$next[0:0]$13850 1'1 + case + assign $5\sv_changed$next[0:0]$13850 \sv_changed + end + end + case + assign $1\sv_changed$next[0:0]$13846 \sv_changed + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $6\sv_changed$next[0:0]$13851 $7\sv_changed$next[0:0]$13852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv_changed$next[0:0]$13852 1'0 + case + assign $7\sv_changed$next[0:0]$13852 $1\sv_changed$next[0:0]$13846 + end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\pc_changed$next[0:0]$13474 $2\pc_changed$next[0:0]$13475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" - switch \$55 + assign $6\sv_changed$next[0:0]$13851 $8\sv_changed$next[0:0]$13853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" + switch \$222 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\pc_changed$next[0:0]$13475 1'1 + assign $8\sv_changed$next[0:0]$13853 1'1 case - assign $2\pc_changed$next[0:0]$13475 \pc_changed + assign $8\sv_changed$next[0:0]$13853 $1\sv_changed$next[0:0]$13846 end case - assign $1\pc_changed$next[0:0]$13474 \pc_changed + assign $6\sv_changed$next[0:0]$13851 $1\sv_changed$next[0:0]$13846 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$13476 1'0 + assign $9\sv_changed$next[0:0]$13854 1'0 + case + assign $9\sv_changed$next[0:0]$13854 $6\sv_changed$next[0:0]$13851 + end + sync always + update \sv_changed$next $0\sv_changed$next[0:0]$13845 + end + attribute \src "libresoc.v:197394.3-197404.6" + process $proc$libresoc.v:197394$13855 + assign { } { } + assign { } { } + assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:197395.5-197395.29" + switch \initial + attribute \src "libresoc.v:197395.9-197395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fetch_insn_ready_i[0:0] 1'1 case - assign $3\pc_changed$next[0:0]$13476 $1\pc_changed$next[0:0]$13474 + assign $1\fetch_insn_ready_i[0:0] 1'0 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13473 + update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end - attribute \src "libresoc.v:186282.3-186404.6" - process $proc$libresoc.v:186282$13477 + attribute \src "libresoc.v:197405.3-197515.6" + process $proc$libresoc.v:197405$13856 assign { } { } assign { } { } assign { } { } @@ -391397,11 +411919,11 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$13478 $1\core_asmcode$next[7:0]$13537 - assign $0\core_core_core_cia$next[63:0]$13479 $1\core_core_core_cia$next[63:0]$13538 - assign $0\core_core_core_cr_rd$next[7:0]$13480 $1\core_core_core_cr_rd$next[7:0]$13539 + assign $0\core_asmcode$next[7:0]$13857 $1\core_asmcode$next[7:0]$13916 + assign $0\core_core_core_cia$next[63:0]$13858 $1\core_core_core_cia$next[63:0]$13917 + assign $0\core_core_core_cr_rd$next[7:0]$13859 $1\core_core_core_cr_rd$next[7:0]$13918 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$13482 $1\core_core_core_cr_wr$next[7:0]$13541 + assign $0\core_core_core_cr_wr$next[7:0]$13861 $1\core_core_core_cr_wr$next[7:0]$13920 assign { } { } assign { } { } assign { } { } @@ -391410,151 +411932,89 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[11:0]$13491 $1\core_core_core_fn_unit$next[11:0]$13550 - assign $0\core_core_core_input_carry$next[1:0]$13492 $1\core_core_core_input_carry$next[1:0]$13551 - assign $0\core_core_core_insn$next[31:0]$13493 $1\core_core_core_insn$next[31:0]$13552 - assign $0\core_core_core_insn_type$next[6:0]$13494 $1\core_core_core_insn_type$next[6:0]$13553 - assign $0\core_core_core_is_32bit$next[0:0]$13495 $1\core_core_core_is_32bit$next[0:0]$13554 - assign $0\core_core_core_msr$next[63:0]$13496 $1\core_core_core_msr$next[63:0]$13555 - assign $0\core_core_core_oe$next[0:0]$13497 $1\core_core_core_oe$next[0:0]$13556 + assign $0\core_core_core_fn_unit$next[13:0]$13870 $1\core_core_core_fn_unit$next[13:0]$13929 + assign $0\core_core_core_input_carry$next[1:0]$13871 $1\core_core_core_input_carry$next[1:0]$13930 + assign $0\core_core_core_insn$next[31:0]$13872 $1\core_core_core_insn$next[31:0]$13931 + assign $0\core_core_core_insn_type$next[6:0]$13873 $1\core_core_core_insn_type$next[6:0]$13932 + assign $0\core_core_core_is_32bit$next[0:0]$13874 $1\core_core_core_is_32bit$next[0:0]$13933 + assign $0\core_core_core_msr$next[63:0]$13875 $1\core_core_core_msr$next[63:0]$13934 + assign $0\core_core_core_oe$next[0:0]$13876 $1\core_core_core_oe$next[0:0]$13935 assign { } { } - assign $0\core_core_core_rc$next[0:0]$13499 $1\core_core_core_rc$next[0:0]$13558 + assign $0\core_core_core_rc$next[0:0]$13878 $1\core_core_core_rc$next[0:0]$13937 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$13501 $1\core_core_core_trapaddr$next[12:0]$13560 - assign $0\core_core_core_traptype$next[7:0]$13502 $1\core_core_core_traptype$next[7:0]$13561 - assign $0\core_core_cr_in1$next[2:0]$13503 $1\core_core_cr_in1$next[2:0]$13562 + assign $0\core_core_core_trapaddr$next[12:0]$13880 $1\core_core_core_trapaddr$next[12:0]$13939 + assign $0\core_core_core_traptype$next[7:0]$13881 $1\core_core_core_traptype$next[7:0]$13940 + assign $0\core_core_cr_in1$next[6:0]$13882 $1\core_core_cr_in1$next[6:0]$13941 assign { } { } - assign $0\core_core_cr_in2$1$next[2:0]$13505 $1\core_core_cr_in2$1$next[2:0]$13564 - assign $0\core_core_cr_in2$next[2:0]$13506 $1\core_core_cr_in2$next[2:0]$13565 + assign $0\core_core_cr_in2$1$next[6:0]$13884 $1\core_core_cr_in2$1$next[6:0]$13943 + assign $0\core_core_cr_in2$next[6:0]$13885 $1\core_core_cr_in2$next[6:0]$13944 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[2:0]$13509 $1\core_core_cr_out$next[2:0]$13568 + assign $0\core_core_cr_out$next[6:0]$13888 $1\core_core_cr_out$next[6:0]$13947 assign { } { } - assign $0\core_core_ea$next[4:0]$13511 $1\core_core_ea$next[4:0]$13570 - assign $0\core_core_fast1$next[2:0]$13512 $1\core_core_fast1$next[2:0]$13571 + assign $0\core_core_ea$next[6:0]$13890 $1\core_core_ea$next[6:0]$13949 + assign $0\core_core_fast1$next[2:0]$13891 $1\core_core_fast1$next[2:0]$13950 assign { } { } - assign $0\core_core_fast2$next[2:0]$13514 $1\core_core_fast2$next[2:0]$13573 + assign $0\core_core_fast2$next[2:0]$13893 $1\core_core_fast2$next[2:0]$13952 assign { } { } - assign $0\core_core_fasto1$next[2:0]$13516 $1\core_core_fasto1$next[2:0]$13575 - assign $0\core_core_fasto2$next[2:0]$13517 $1\core_core_fasto2$next[2:0]$13576 - assign $0\core_core_lk$next[0:0]$13518 $1\core_core_lk$next[0:0]$13577 - assign $0\core_core_reg1$next[4:0]$13519 $1\core_core_reg1$next[4:0]$13578 + assign $0\core_core_fasto1$next[2:0]$13895 $1\core_core_fasto1$next[2:0]$13954 + assign $0\core_core_fasto2$next[2:0]$13896 $1\core_core_fasto2$next[2:0]$13955 + assign $0\core_core_lk$next[0:0]$13897 $1\core_core_lk$next[0:0]$13956 + assign $0\core_core_reg1$next[6:0]$13898 $1\core_core_reg1$next[6:0]$13957 assign { } { } - assign $0\core_core_reg2$next[4:0]$13521 $1\core_core_reg2$next[4:0]$13580 + assign $0\core_core_reg2$next[6:0]$13900 $1\core_core_reg2$next[6:0]$13959 assign { } { } - assign $0\core_core_reg3$next[4:0]$13523 $1\core_core_reg3$next[4:0]$13582 + assign $0\core_core_reg3$next[6:0]$13902 $1\core_core_reg3$next[6:0]$13961 assign { } { } - assign $0\core_core_rego$next[4:0]$13525 $1\core_core_rego$next[4:0]$13584 - assign $0\core_core_spr1$next[9:0]$13526 $1\core_core_spr1$next[9:0]$13585 + assign $0\core_core_rego$next[6:0]$13904 $1\core_core_rego$next[6:0]$13963 + assign $0\core_core_spr1$next[9:0]$13905 $1\core_core_spr1$next[9:0]$13964 assign { } { } - assign $0\core_core_spro$next[9:0]$13528 $1\core_core_spro$next[9:0]$13587 - assign $0\core_core_xer_in$next[2:0]$13529 $1\core_core_xer_in$next[2:0]$13588 + assign $0\core_core_spro$next[9:0]$13907 $1\core_core_spro$next[9:0]$13966 + assign $0\core_core_xer_in$next[2:0]$13908 $1\core_core_xer_in$next[2:0]$13967 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$13536 $1\core_xer_out$next[0:0]$13595 - assign $0\core_core_core_cr_rd_ok$next[0:0]$13481 $4\core_core_core_cr_rd_ok$next[0:0]$13714 - assign $0\core_core_core_exc_$signal$3$next[0:0]$13483 $4\core_core_core_exc_$signal$3$next[0:0]$13715 - assign $0\core_core_core_exc_$signal$4$next[0:0]$13484 $4\core_core_core_exc_$signal$4$next[0:0]$13716 - assign $0\core_core_core_exc_$signal$5$next[0:0]$13485 $4\core_core_core_exc_$signal$5$next[0:0]$13717 - assign $0\core_core_core_exc_$signal$6$next[0:0]$13486 $4\core_core_core_exc_$signal$6$next[0:0]$13718 - assign $0\core_core_core_exc_$signal$7$next[0:0]$13487 $4\core_core_core_exc_$signal$7$next[0:0]$13719 - assign $0\core_core_core_exc_$signal$8$next[0:0]$13488 $4\core_core_core_exc_$signal$8$next[0:0]$13720 - assign $0\core_core_core_exc_$signal$9$next[0:0]$13489 $4\core_core_core_exc_$signal$9$next[0:0]$13721 - assign $0\core_core_core_exc_$signal$next[0:0]$13490 $4\core_core_core_exc_$signal$next[0:0]$13722 - assign $0\core_core_core_oe_ok$next[0:0]$13498 $4\core_core_core_oe_ok$next[0:0]$13723 - assign $0\core_core_core_rc_ok$next[0:0]$13500 $4\core_core_core_rc_ok$next[0:0]$13724 - assign $0\core_core_cr_in1_ok$next[0:0]$13504 $4\core_core_cr_in1_ok$next[0:0]$13725 - assign $0\core_core_cr_in2_ok$2$next[0:0]$13507 $4\core_core_cr_in2_ok$2$next[0:0]$13726 - assign $0\core_core_cr_in2_ok$next[0:0]$13508 $4\core_core_cr_in2_ok$next[0:0]$13727 - assign $0\core_core_cr_wr_ok$next[0:0]$13510 $4\core_core_cr_wr_ok$next[0:0]$13728 - assign $0\core_core_fast1_ok$next[0:0]$13513 $4\core_core_fast1_ok$next[0:0]$13729 - assign $0\core_core_fast2_ok$next[0:0]$13515 $4\core_core_fast2_ok$next[0:0]$13730 - assign $0\core_core_reg1_ok$next[0:0]$13520 $4\core_core_reg1_ok$next[0:0]$13731 - assign $0\core_core_reg2_ok$next[0:0]$13522 $4\core_core_reg2_ok$next[0:0]$13732 - assign $0\core_core_reg3_ok$next[0:0]$13524 $4\core_core_reg3_ok$next[0:0]$13733 - assign $0\core_core_spr1_ok$next[0:0]$13527 $4\core_core_spr1_ok$next[0:0]$13734 - assign $0\core_cr_out_ok$next[0:0]$13530 $4\core_cr_out_ok$next[0:0]$13735 - assign $0\core_ea_ok$next[0:0]$13531 $4\core_ea_ok$next[0:0]$13736 - assign $0\core_fasto1_ok$next[0:0]$13532 $4\core_fasto1_ok$next[0:0]$13737 - assign $0\core_fasto2_ok$next[0:0]$13533 $4\core_fasto2_ok$next[0:0]$13738 - assign $0\core_rego_ok$next[0:0]$13534 $4\core_rego_ok$next[0:0]$13739 - assign $0\core_spro_ok$next[0:0]$13535 $4\core_spro_ok$next[0:0]$13740 - attribute \src "libresoc.v:186283.5-186283.29" + assign $0\core_xer_out$next[0:0]$13915 $1\core_xer_out$next[0:0]$13974 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13860 $3\core_core_core_cr_rd_ok$next[0:0]$14034 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13862 $3\core_core_core_exc_$signal$3$next[0:0]$14035 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13863 $3\core_core_core_exc_$signal$4$next[0:0]$14036 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13864 $3\core_core_core_exc_$signal$5$next[0:0]$14037 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13865 $3\core_core_core_exc_$signal$6$next[0:0]$14038 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13866 $3\core_core_core_exc_$signal$7$next[0:0]$14039 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13867 $3\core_core_core_exc_$signal$8$next[0:0]$14040 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13868 $3\core_core_core_exc_$signal$9$next[0:0]$14041 + assign $0\core_core_core_exc_$signal$next[0:0]$13869 $3\core_core_core_exc_$signal$next[0:0]$14042 + assign $0\core_core_core_oe_ok$next[0:0]$13877 $3\core_core_core_oe_ok$next[0:0]$14043 + assign $0\core_core_core_rc_ok$next[0:0]$13879 $3\core_core_core_rc_ok$next[0:0]$14044 + assign $0\core_core_cr_in1_ok$next[0:0]$13883 $3\core_core_cr_in1_ok$next[0:0]$14045 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13886 $3\core_core_cr_in2_ok$2$next[0:0]$14046 + assign $0\core_core_cr_in2_ok$next[0:0]$13887 $3\core_core_cr_in2_ok$next[0:0]$14047 + assign $0\core_core_cr_wr_ok$next[0:0]$13889 $3\core_core_cr_wr_ok$next[0:0]$14048 + assign $0\core_core_fast1_ok$next[0:0]$13892 $3\core_core_fast1_ok$next[0:0]$14049 + assign $0\core_core_fast2_ok$next[0:0]$13894 $3\core_core_fast2_ok$next[0:0]$14050 + assign $0\core_core_reg1_ok$next[0:0]$13899 $3\core_core_reg1_ok$next[0:0]$14051 + assign $0\core_core_reg2_ok$next[0:0]$13901 $3\core_core_reg2_ok$next[0:0]$14052 + assign $0\core_core_reg3_ok$next[0:0]$13903 $3\core_core_reg3_ok$next[0:0]$14053 + assign $0\core_core_spr1_ok$next[0:0]$13906 $3\core_core_spr1_ok$next[0:0]$14054 + assign $0\core_cr_out_ok$next[0:0]$13909 $3\core_cr_out_ok$next[0:0]$14055 + assign $0\core_ea_ok$next[0:0]$13910 $3\core_ea_ok$next[0:0]$14056 + assign $0\core_fasto1_ok$next[0:0]$13911 $3\core_fasto1_ok$next[0:0]$14057 + assign $0\core_fasto2_ok$next[0:0]$13912 $3\core_fasto2_ok$next[0:0]$14058 + assign $0\core_rego_ok$next[0:0]$13913 $3\core_rego_ok$next[0:0]$14059 + assign $0\core_spro_ok$next[0:0]$13914 $3\core_spro_ok$next[0:0]$14060 + attribute \src "libresoc.v:197406.5-197406.29" switch \initial - attribute \src "libresoc.v:186283.9-186283.17" + attribute \src "libresoc.v:197406.9-197406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$13554 $1\core_core_cr_wr_ok$next[0:0]$13569 $1\core_core_core_cr_wr$next[7:0]$13541 $1\core_core_core_cr_rd_ok$next[0:0]$13540 $1\core_core_core_cr_rd$next[7:0]$13539 $1\core_core_core_trapaddr$next[12:0]$13560 $1\core_core_core_exc_$signal$9$next[0:0]$13548 $1\core_core_core_exc_$signal$8$next[0:0]$13547 $1\core_core_core_exc_$signal$7$next[0:0]$13546 $1\core_core_core_exc_$signal$6$next[0:0]$13545 $1\core_core_core_exc_$signal$5$next[0:0]$13544 $1\core_core_core_exc_$signal$4$next[0:0]$13543 $1\core_core_core_exc_$signal$3$next[0:0]$13542 $1\core_core_core_exc_$signal$next[0:0]$13549 $1\core_core_core_traptype$next[7:0]$13561 $1\core_core_core_input_carry$next[1:0]$13551 $1\core_core_core_oe_ok$next[0:0]$13557 $1\core_core_core_oe$next[0:0]$13556 $1\core_core_core_rc_ok$next[0:0]$13559 $1\core_core_core_rc$next[0:0]$13558 $1\core_core_lk$next[0:0]$13577 $1\core_core_core_fn_unit$next[11:0]$13550 $1\core_core_core_insn_type$next[6:0]$13553 $1\core_core_core_insn$next[31:0]$13552 $1\core_core_core_cia$next[63:0]$13538 $1\core_core_core_msr$next[63:0]$13555 $1\core_cr_out_ok$next[0:0]$13589 $1\core_core_cr_out$next[2:0]$13568 $1\core_core_cr_in2_ok$2$next[0:0]$13566 $1\core_core_cr_in2$1$next[2:0]$13564 $1\core_core_cr_in2_ok$next[0:0]$13567 $1\core_core_cr_in2$next[2:0]$13565 $1\core_core_cr_in1_ok$next[0:0]$13563 $1\core_core_cr_in1$next[2:0]$13562 $1\core_fasto2_ok$next[0:0]$13592 $1\core_core_fasto2$next[2:0]$13576 $1\core_fasto1_ok$next[0:0]$13591 $1\core_core_fasto1$next[2:0]$13575 $1\core_core_fast2_ok$next[0:0]$13574 $1\core_core_fast2$next[2:0]$13573 $1\core_core_fast1_ok$next[0:0]$13572 $1\core_core_fast1$next[2:0]$13571 $1\core_xer_out$next[0:0]$13595 $1\core_core_xer_in$next[2:0]$13588 $1\core_core_spr1_ok$next[0:0]$13586 $1\core_core_spr1$next[9:0]$13585 $1\core_spro_ok$next[0:0]$13594 $1\core_core_spro$next[9:0]$13587 $1\core_core_reg3_ok$next[0:0]$13583 $1\core_core_reg3$next[4:0]$13582 $1\core_core_reg2_ok$next[0:0]$13581 $1\core_core_reg2$next[4:0]$13580 $1\core_core_reg1_ok$next[0:0]$13579 $1\core_core_reg1$next[4:0]$13578 $1\core_ea_ok$next[0:0]$13590 $1\core_core_ea$next[4:0]$13570 $1\core_rego_ok$next[0:0]$13593 $1\core_core_rego$next[4:0]$13584 $1\core_asmcode$next[7:0]$13537 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'001 assign { } { } assign { } { } assign { } { } @@ -391614,130 +412074,69 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$13537 $2\core_asmcode$next[7:0]$13596 - assign $1\core_core_core_cia$next[63:0]$13538 $2\core_core_core_cia$next[63:0]$13597 - assign $1\core_core_core_cr_rd$next[7:0]$13539 $2\core_core_core_cr_rd$next[7:0]$13598 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13540 $2\core_core_core_cr_rd_ok$next[0:0]$13599 - assign $1\core_core_core_cr_wr$next[7:0]$13541 $2\core_core_core_cr_wr$next[7:0]$13600 - assign $1\core_core_core_exc_$signal$3$next[0:0]$13542 $2\core_core_core_exc_$signal$3$next[0:0]$13601 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13543 $2\core_core_core_exc_$signal$4$next[0:0]$13602 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13544 $2\core_core_core_exc_$signal$5$next[0:0]$13603 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13545 $2\core_core_core_exc_$signal$6$next[0:0]$13604 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13546 $2\core_core_core_exc_$signal$7$next[0:0]$13605 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13547 $2\core_core_core_exc_$signal$8$next[0:0]$13606 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13548 $2\core_core_core_exc_$signal$9$next[0:0]$13607 - assign $1\core_core_core_exc_$signal$next[0:0]$13549 $2\core_core_core_exc_$signal$next[0:0]$13608 - assign $1\core_core_core_fn_unit$next[11:0]$13550 $2\core_core_core_fn_unit$next[11:0]$13609 - assign $1\core_core_core_input_carry$next[1:0]$13551 $2\core_core_core_input_carry$next[1:0]$13610 - assign $1\core_core_core_insn$next[31:0]$13552 $2\core_core_core_insn$next[31:0]$13611 - assign $1\core_core_core_insn_type$next[6:0]$13553 $2\core_core_core_insn_type$next[6:0]$13612 - assign $1\core_core_core_is_32bit$next[0:0]$13554 $2\core_core_core_is_32bit$next[0:0]$13613 - assign $1\core_core_core_msr$next[63:0]$13555 $2\core_core_core_msr$next[63:0]$13614 - assign $1\core_core_core_oe$next[0:0]$13556 $2\core_core_core_oe$next[0:0]$13615 - assign $1\core_core_core_oe_ok$next[0:0]$13557 $2\core_core_core_oe_ok$next[0:0]$13616 - assign $1\core_core_core_rc$next[0:0]$13558 $2\core_core_core_rc$next[0:0]$13617 - assign $1\core_core_core_rc_ok$next[0:0]$13559 $2\core_core_core_rc_ok$next[0:0]$13618 - assign $1\core_core_core_trapaddr$next[12:0]$13560 $2\core_core_core_trapaddr$next[12:0]$13619 - assign $1\core_core_core_traptype$next[7:0]$13561 $2\core_core_core_traptype$next[7:0]$13620 - assign $1\core_core_cr_in1$next[2:0]$13562 $2\core_core_cr_in1$next[2:0]$13621 - assign $1\core_core_cr_in1_ok$next[0:0]$13563 $2\core_core_cr_in1_ok$next[0:0]$13622 - assign $1\core_core_cr_in2$1$next[2:0]$13564 $2\core_core_cr_in2$1$next[2:0]$13623 - assign $1\core_core_cr_in2$next[2:0]$13565 $2\core_core_cr_in2$next[2:0]$13624 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13566 $2\core_core_cr_in2_ok$2$next[0:0]$13625 - assign $1\core_core_cr_in2_ok$next[0:0]$13567 $2\core_core_cr_in2_ok$next[0:0]$13626 - assign $1\core_core_cr_out$next[2:0]$13568 $2\core_core_cr_out$next[2:0]$13627 - assign $1\core_core_cr_wr_ok$next[0:0]$13569 $2\core_core_cr_wr_ok$next[0:0]$13628 - assign $1\core_core_ea$next[4:0]$13570 $2\core_core_ea$next[4:0]$13629 - assign $1\core_core_fast1$next[2:0]$13571 $2\core_core_fast1$next[2:0]$13630 - assign $1\core_core_fast1_ok$next[0:0]$13572 $2\core_core_fast1_ok$next[0:0]$13631 - assign $1\core_core_fast2$next[2:0]$13573 $2\core_core_fast2$next[2:0]$13632 - assign $1\core_core_fast2_ok$next[0:0]$13574 $2\core_core_fast2_ok$next[0:0]$13633 - assign $1\core_core_fasto1$next[2:0]$13575 $2\core_core_fasto1$next[2:0]$13634 - assign $1\core_core_fasto2$next[2:0]$13576 $2\core_core_fasto2$next[2:0]$13635 - assign $1\core_core_lk$next[0:0]$13577 $2\core_core_lk$next[0:0]$13636 - assign $1\core_core_reg1$next[4:0]$13578 $2\core_core_reg1$next[4:0]$13637 - assign $1\core_core_reg1_ok$next[0:0]$13579 $2\core_core_reg1_ok$next[0:0]$13638 - assign $1\core_core_reg2$next[4:0]$13580 $2\core_core_reg2$next[4:0]$13639 - assign $1\core_core_reg2_ok$next[0:0]$13581 $2\core_core_reg2_ok$next[0:0]$13640 - assign $1\core_core_reg3$next[4:0]$13582 $2\core_core_reg3$next[4:0]$13641 - assign $1\core_core_reg3_ok$next[0:0]$13583 $2\core_core_reg3_ok$next[0:0]$13642 - assign $1\core_core_rego$next[4:0]$13584 $2\core_core_rego$next[4:0]$13643 - assign $1\core_core_spr1$next[9:0]$13585 $2\core_core_spr1$next[9:0]$13644 - assign $1\core_core_spr1_ok$next[0:0]$13586 $2\core_core_spr1_ok$next[0:0]$13645 - assign $1\core_core_spro$next[9:0]$13587 $2\core_core_spro$next[9:0]$13646 - assign $1\core_core_xer_in$next[2:0]$13588 $2\core_core_xer_in$next[2:0]$13647 - assign $1\core_cr_out_ok$next[0:0]$13589 $2\core_cr_out_ok$next[0:0]$13648 - assign $1\core_ea_ok$next[0:0]$13590 $2\core_ea_ok$next[0:0]$13649 - assign $1\core_fasto1_ok$next[0:0]$13591 $2\core_fasto1_ok$next[0:0]$13650 - assign $1\core_fasto2_ok$next[0:0]$13592 $2\core_fasto2_ok$next[0:0]$13651 - assign $1\core_rego_ok$next[0:0]$13593 $2\core_rego_ok$next[0:0]$13652 - assign $1\core_spro_ok$next[0:0]$13594 $2\core_spro_ok$next[0:0]$13653 - assign $1\core_xer_out$next[0:0]$13595 $2\core_xer_out$next[0:0]$13654 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o + assign $1\core_asmcode$next[7:0]$13916 $2\core_asmcode$next[7:0]$13975 + assign $1\core_core_core_cia$next[63:0]$13917 $2\core_core_core_cia$next[63:0]$13976 + assign $1\core_core_core_cr_rd$next[7:0]$13918 $2\core_core_core_cr_rd$next[7:0]$13977 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13919 $2\core_core_core_cr_rd_ok$next[0:0]$13978 + assign $1\core_core_core_cr_wr$next[7:0]$13920 $2\core_core_core_cr_wr$next[7:0]$13979 + assign $1\core_core_core_exc_$signal$3$next[0:0]$13921 $2\core_core_core_exc_$signal$3$next[0:0]$13980 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13922 $2\core_core_core_exc_$signal$4$next[0:0]$13981 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13923 $2\core_core_core_exc_$signal$5$next[0:0]$13982 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13924 $2\core_core_core_exc_$signal$6$next[0:0]$13983 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13925 $2\core_core_core_exc_$signal$7$next[0:0]$13984 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13926 $2\core_core_core_exc_$signal$8$next[0:0]$13985 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13927 $2\core_core_core_exc_$signal$9$next[0:0]$13986 + assign $1\core_core_core_exc_$signal$next[0:0]$13928 $2\core_core_core_exc_$signal$next[0:0]$13987 + assign $1\core_core_core_fn_unit$next[13:0]$13929 $2\core_core_core_fn_unit$next[13:0]$13988 + assign $1\core_core_core_input_carry$next[1:0]$13930 $2\core_core_core_input_carry$next[1:0]$13989 + assign $1\core_core_core_insn$next[31:0]$13931 $2\core_core_core_insn$next[31:0]$13990 + assign $1\core_core_core_insn_type$next[6:0]$13932 $2\core_core_core_insn_type$next[6:0]$13991 + assign $1\core_core_core_is_32bit$next[0:0]$13933 $2\core_core_core_is_32bit$next[0:0]$13992 + assign $1\core_core_core_msr$next[63:0]$13934 $2\core_core_core_msr$next[63:0]$13993 + assign $1\core_core_core_oe$next[0:0]$13935 $2\core_core_core_oe$next[0:0]$13994 + assign $1\core_core_core_oe_ok$next[0:0]$13936 $2\core_core_core_oe_ok$next[0:0]$13995 + assign $1\core_core_core_rc$next[0:0]$13937 $2\core_core_core_rc$next[0:0]$13996 + assign $1\core_core_core_rc_ok$next[0:0]$13938 $2\core_core_core_rc_ok$next[0:0]$13997 + assign $1\core_core_core_trapaddr$next[12:0]$13939 $2\core_core_core_trapaddr$next[12:0]$13998 + assign $1\core_core_core_traptype$next[7:0]$13940 $2\core_core_core_traptype$next[7:0]$13999 + assign $1\core_core_cr_in1$next[6:0]$13941 $2\core_core_cr_in1$next[6:0]$14000 + assign $1\core_core_cr_in1_ok$next[0:0]$13942 $2\core_core_cr_in1_ok$next[0:0]$14001 + assign $1\core_core_cr_in2$1$next[6:0]$13943 $2\core_core_cr_in2$1$next[6:0]$14002 + assign $1\core_core_cr_in2$next[6:0]$13944 $2\core_core_cr_in2$next[6:0]$14003 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13945 $2\core_core_cr_in2_ok$2$next[0:0]$14004 + assign $1\core_core_cr_in2_ok$next[0:0]$13946 $2\core_core_cr_in2_ok$next[0:0]$14005 + assign $1\core_core_cr_out$next[6:0]$13947 $2\core_core_cr_out$next[6:0]$14006 + assign $1\core_core_cr_wr_ok$next[0:0]$13948 $2\core_core_cr_wr_ok$next[0:0]$14007 + assign $1\core_core_ea$next[6:0]$13949 $2\core_core_ea$next[6:0]$14008 + assign $1\core_core_fast1$next[2:0]$13950 $2\core_core_fast1$next[2:0]$14009 + assign $1\core_core_fast1_ok$next[0:0]$13951 $2\core_core_fast1_ok$next[0:0]$14010 + assign $1\core_core_fast2$next[2:0]$13952 $2\core_core_fast2$next[2:0]$14011 + assign $1\core_core_fast2_ok$next[0:0]$13953 $2\core_core_fast2_ok$next[0:0]$14012 + assign $1\core_core_fasto1$next[2:0]$13954 $2\core_core_fasto1$next[2:0]$14013 + assign $1\core_core_fasto2$next[2:0]$13955 $2\core_core_fasto2$next[2:0]$14014 + assign $1\core_core_lk$next[0:0]$13956 $2\core_core_lk$next[0:0]$14015 + assign $1\core_core_reg1$next[6:0]$13957 $2\core_core_reg1$next[6:0]$14016 + assign $1\core_core_reg1_ok$next[0:0]$13958 $2\core_core_reg1_ok$next[0:0]$14017 + assign $1\core_core_reg2$next[6:0]$13959 $2\core_core_reg2$next[6:0]$14018 + assign $1\core_core_reg2_ok$next[0:0]$13960 $2\core_core_reg2_ok$next[0:0]$14019 + assign $1\core_core_reg3$next[6:0]$13961 $2\core_core_reg3$next[6:0]$14020 + assign $1\core_core_reg3_ok$next[0:0]$13962 $2\core_core_reg3_ok$next[0:0]$14021 + assign $1\core_core_rego$next[6:0]$13963 $2\core_core_rego$next[6:0]$14022 + assign $1\core_core_spr1$next[9:0]$13964 $2\core_core_spr1$next[9:0]$14023 + assign $1\core_core_spr1_ok$next[0:0]$13965 $2\core_core_spr1_ok$next[0:0]$14024 + assign $1\core_core_spro$next[9:0]$13966 $2\core_core_spro$next[9:0]$14025 + assign $1\core_core_xer_in$next[2:0]$13967 $2\core_core_xer_in$next[2:0]$14026 + assign $1\core_cr_out_ok$next[0:0]$13968 $2\core_cr_out_ok$next[0:0]$14027 + assign $1\core_ea_ok$next[0:0]$13969 $2\core_ea_ok$next[0:0]$14028 + assign $1\core_fasto1_ok$next[0:0]$13970 $2\core_fasto1_ok$next[0:0]$14029 + assign $1\core_fasto2_ok$next[0:0]$13971 $2\core_fasto2_ok$next[0:0]$14030 + assign $1\core_rego_ok$next[0:0]$13972 $2\core_rego_ok$next[0:0]$14031 + assign $1\core_spro_ok$next[0:0]$13973 $2\core_spro_ok$next[0:0]$14032 + assign $1\core_xer_out$next[0:0]$13974 $2\core_xer_out$next[0:0]$14033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\core_asmcode$next[7:0]$13596 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$13597 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$13598 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$13599 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$13600 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$13601 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$13602 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$13603 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$13604 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$13605 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$13606 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$13607 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$13608 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[11:0]$13609 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$13610 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$13611 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$13612 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$13613 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$13614 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$13615 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$13616 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$13617 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$13618 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$13619 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$13620 \core_core_core_traptype - assign $2\core_core_cr_in1$next[2:0]$13621 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$13622 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[2:0]$13623 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[2:0]$13624 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$13625 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$13626 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[2:0]$13627 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$13628 \core_core_cr_wr_ok - assign $2\core_core_ea$next[4:0]$13629 \core_core_ea - assign $2\core_core_fast1$next[2:0]$13630 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$13631 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$13632 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$13633 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$13634 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$13635 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$13636 \core_core_lk - assign $2\core_core_reg1$next[4:0]$13637 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$13638 \core_core_reg1_ok - assign $2\core_core_reg2$next[4:0]$13639 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$13640 \core_core_reg2_ok - assign $2\core_core_reg3$next[4:0]$13641 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$13642 \core_core_reg3_ok - assign $2\core_core_rego$next[4:0]$13643 \core_core_rego - assign $2\core_core_spr1$next[9:0]$13644 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$13645 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$13646 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$13647 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$13648 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$13649 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$13650 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$13651 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$13652 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$13653 \core_spro_ok - assign $2\core_xer_out$next[0:0]$13654 \core_xer_out - attribute \src "libresoc.v:0.0-0.0" - case assign { } { } assign { } { } assign { } { } @@ -391797,39 +412196,70 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$13613 $2\core_core_cr_wr_ok$next[0:0]$13628 $2\core_core_core_cr_wr$next[7:0]$13600 $2\core_core_core_cr_rd_ok$next[0:0]$13599 $2\core_core_core_cr_rd$next[7:0]$13598 $2\core_core_core_trapaddr$next[12:0]$13619 $2\core_core_core_exc_$signal$9$next[0:0]$13607 $2\core_core_core_exc_$signal$8$next[0:0]$13606 $2\core_core_core_exc_$signal$7$next[0:0]$13605 $2\core_core_core_exc_$signal$6$next[0:0]$13604 $2\core_core_core_exc_$signal$5$next[0:0]$13603 $2\core_core_core_exc_$signal$4$next[0:0]$13602 $2\core_core_core_exc_$signal$3$next[0:0]$13601 $2\core_core_core_exc_$signal$next[0:0]$13608 $2\core_core_core_traptype$next[7:0]$13620 $2\core_core_core_input_carry$next[1:0]$13610 $2\core_core_core_oe_ok$next[0:0]$13616 $2\core_core_core_oe$next[0:0]$13615 $2\core_core_core_rc_ok$next[0:0]$13618 $2\core_core_core_rc$next[0:0]$13617 $2\core_core_lk$next[0:0]$13636 $2\core_core_core_fn_unit$next[11:0]$13609 $2\core_core_core_insn_type$next[6:0]$13612 $2\core_core_core_insn$next[31:0]$13611 $2\core_core_core_cia$next[63:0]$13597 $2\core_core_core_msr$next[63:0]$13614 $2\core_cr_out_ok$next[0:0]$13648 $2\core_core_cr_out$next[2:0]$13627 $2\core_core_cr_in2_ok$2$next[0:0]$13625 $2\core_core_cr_in2$1$next[2:0]$13623 $2\core_core_cr_in2_ok$next[0:0]$13626 $2\core_core_cr_in2$next[2:0]$13624 $2\core_core_cr_in1_ok$next[0:0]$13622 $2\core_core_cr_in1$next[2:0]$13621 $2\core_fasto2_ok$next[0:0]$13651 $2\core_core_fasto2$next[2:0]$13635 $2\core_fasto1_ok$next[0:0]$13650 $2\core_core_fasto1$next[2:0]$13634 $2\core_core_fast2_ok$next[0:0]$13633 $2\core_core_fast2$next[2:0]$13632 $2\core_core_fast1_ok$next[0:0]$13631 $2\core_core_fast1$next[2:0]$13630 $2\core_xer_out$next[0:0]$13654 $2\core_core_xer_in$next[2:0]$13647 $2\core_core_spr1_ok$next[0:0]$13645 $2\core_core_spr1$next[9:0]$13644 $2\core_spro_ok$next[0:0]$13653 $2\core_core_spro$next[9:0]$13646 $2\core_core_reg3_ok$next[0:0]$13642 $2\core_core_reg3$next[4:0]$13641 $2\core_core_reg2_ok$next[0:0]$13640 $2\core_core_reg2$next[4:0]$13639 $2\core_core_reg1_ok$next[0:0]$13638 $2\core_core_reg1$next[4:0]$13637 $2\core_ea_ok$next[0:0]$13649 $2\core_core_ea$next[4:0]$13629 $2\core_rego_ok$next[0:0]$13652 $2\core_core_rego$next[4:0]$13643 $2\core_asmcode$next[7:0]$13596 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$14 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$13 \dec2_cr_in2$12 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $2\core_core_core_is_32bit$next[0:0]$13992 $2\core_core_cr_wr_ok$next[0:0]$14007 $2\core_core_core_cr_wr$next[7:0]$13979 $2\core_core_core_cr_rd_ok$next[0:0]$13978 $2\core_core_core_cr_rd$next[7:0]$13977 $2\core_core_core_trapaddr$next[12:0]$13998 $2\core_core_core_exc_$signal$9$next[0:0]$13986 $2\core_core_core_exc_$signal$8$next[0:0]$13985 $2\core_core_core_exc_$signal$7$next[0:0]$13984 $2\core_core_core_exc_$signal$6$next[0:0]$13983 $2\core_core_core_exc_$signal$5$next[0:0]$13982 $2\core_core_core_exc_$signal$4$next[0:0]$13981 $2\core_core_core_exc_$signal$3$next[0:0]$13980 $2\core_core_core_exc_$signal$next[0:0]$13987 $2\core_core_core_traptype$next[7:0]$13999 $2\core_core_core_input_carry$next[1:0]$13989 $2\core_core_core_oe_ok$next[0:0]$13995 $2\core_core_core_oe$next[0:0]$13994 $2\core_core_core_rc_ok$next[0:0]$13997 $2\core_core_core_rc$next[0:0]$13996 $2\core_core_lk$next[0:0]$14015 $2\core_core_core_fn_unit$next[13:0]$13988 $2\core_core_core_insn_type$next[6:0]$13991 $2\core_core_core_insn$next[31:0]$13990 $2\core_core_core_cia$next[63:0]$13976 $2\core_core_core_msr$next[63:0]$13993 $2\core_cr_out_ok$next[0:0]$14027 $2\core_core_cr_out$next[6:0]$14006 $2\core_core_cr_in2_ok$2$next[0:0]$14004 $2\core_core_cr_in2$1$next[6:0]$14002 $2\core_core_cr_in2_ok$next[0:0]$14005 $2\core_core_cr_in2$next[6:0]$14003 $2\core_core_cr_in1_ok$next[0:0]$14001 $2\core_core_cr_in1$next[6:0]$14000 $2\core_fasto2_ok$next[0:0]$14030 $2\core_core_fasto2$next[2:0]$14014 $2\core_fasto1_ok$next[0:0]$14029 $2\core_core_fasto1$next[2:0]$14013 $2\core_core_fast2_ok$next[0:0]$14012 $2\core_core_fast2$next[2:0]$14011 $2\core_core_fast1_ok$next[0:0]$14010 $2\core_core_fast1$next[2:0]$14009 $2\core_xer_out$next[0:0]$14033 $2\core_core_xer_in$next[2:0]$14026 $2\core_core_spr1_ok$next[0:0]$14024 $2\core_core_spr1$next[9:0]$14023 $2\core_spro_ok$next[0:0]$14032 $2\core_core_spro$next[9:0]$14025 $2\core_core_reg3_ok$next[0:0]$14021 $2\core_core_reg3$next[6:0]$14020 $2\core_core_reg2_ok$next[0:0]$14019 $2\core_core_reg2$next[6:0]$14018 $2\core_core_reg1_ok$next[0:0]$14017 $2\core_core_reg1$next[6:0]$14016 $2\core_ea_ok$next[0:0]$14028 $2\core_core_ea$next[6:0]$14008 $2\core_rego_ok$next[0:0]$14031 $2\core_core_rego$next[6:0]$14022 $2\core_asmcode$next[7:0]$13975 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + case + assign $2\core_asmcode$next[7:0]$13975 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$13976 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$13977 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$13978 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$13979 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$13980 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$13981 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$13982 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$13983 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$13984 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$13985 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$13986 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$13987 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[13:0]$13988 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$13989 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$13990 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$13991 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$13992 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$13993 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$13994 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$13995 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$13996 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$13997 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$13998 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$13999 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14000 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14001 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14002 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14003 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14004 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14005 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14006 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14007 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14008 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14009 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14010 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14011 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14012 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14013 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14014 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14015 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14016 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14017 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14018 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14019 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14020 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14021 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14022 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14023 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14024 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14025 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14026 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14027 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14028 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14029 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14030 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14031 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14032 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14033 \core_xer_out end attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 3'100 assign { } { } assign { } { } assign { } { } @@ -391860,255 +412290,6 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$13537 $3\core_asmcode$next[7:0]$13655 - assign $1\core_core_core_cia$next[63:0]$13538 $3\core_core_core_cia$next[63:0]$13656 - assign $1\core_core_core_cr_rd$next[7:0]$13539 $3\core_core_core_cr_rd$next[7:0]$13657 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13540 $3\core_core_core_cr_rd_ok$next[0:0]$13658 - assign $1\core_core_core_cr_wr$next[7:0]$13541 $3\core_core_core_cr_wr$next[7:0]$13659 - assign $1\core_core_core_exc_$signal$3$next[0:0]$13542 $3\core_core_core_exc_$signal$3$next[0:0]$13660 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13543 $3\core_core_core_exc_$signal$4$next[0:0]$13661 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13544 $3\core_core_core_exc_$signal$5$next[0:0]$13662 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13545 $3\core_core_core_exc_$signal$6$next[0:0]$13663 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13546 $3\core_core_core_exc_$signal$7$next[0:0]$13664 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13547 $3\core_core_core_exc_$signal$8$next[0:0]$13665 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13548 $3\core_core_core_exc_$signal$9$next[0:0]$13666 - assign $1\core_core_core_exc_$signal$next[0:0]$13549 $3\core_core_core_exc_$signal$next[0:0]$13667 - assign $1\core_core_core_fn_unit$next[11:0]$13550 $3\core_core_core_fn_unit$next[11:0]$13668 - assign $1\core_core_core_input_carry$next[1:0]$13551 $3\core_core_core_input_carry$next[1:0]$13669 - assign $1\core_core_core_insn$next[31:0]$13552 $3\core_core_core_insn$next[31:0]$13670 - assign $1\core_core_core_insn_type$next[6:0]$13553 $3\core_core_core_insn_type$next[6:0]$13671 - assign $1\core_core_core_is_32bit$next[0:0]$13554 $3\core_core_core_is_32bit$next[0:0]$13672 - assign $1\core_core_core_msr$next[63:0]$13555 $3\core_core_core_msr$next[63:0]$13673 - assign $1\core_core_core_oe$next[0:0]$13556 $3\core_core_core_oe$next[0:0]$13674 - assign $1\core_core_core_oe_ok$next[0:0]$13557 $3\core_core_core_oe_ok$next[0:0]$13675 - assign $1\core_core_core_rc$next[0:0]$13558 $3\core_core_core_rc$next[0:0]$13676 - assign $1\core_core_core_rc_ok$next[0:0]$13559 $3\core_core_core_rc_ok$next[0:0]$13677 - assign $1\core_core_core_trapaddr$next[12:0]$13560 $3\core_core_core_trapaddr$next[12:0]$13678 - assign $1\core_core_core_traptype$next[7:0]$13561 $3\core_core_core_traptype$next[7:0]$13679 - assign $1\core_core_cr_in1$next[2:0]$13562 $3\core_core_cr_in1$next[2:0]$13680 - assign $1\core_core_cr_in1_ok$next[0:0]$13563 $3\core_core_cr_in1_ok$next[0:0]$13681 - assign $1\core_core_cr_in2$1$next[2:0]$13564 $3\core_core_cr_in2$1$next[2:0]$13682 - assign $1\core_core_cr_in2$next[2:0]$13565 $3\core_core_cr_in2$next[2:0]$13683 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13566 $3\core_core_cr_in2_ok$2$next[0:0]$13684 - assign $1\core_core_cr_in2_ok$next[0:0]$13567 $3\core_core_cr_in2_ok$next[0:0]$13685 - assign $1\core_core_cr_out$next[2:0]$13568 $3\core_core_cr_out$next[2:0]$13686 - assign $1\core_core_cr_wr_ok$next[0:0]$13569 $3\core_core_cr_wr_ok$next[0:0]$13687 - assign $1\core_core_ea$next[4:0]$13570 $3\core_core_ea$next[4:0]$13688 - assign $1\core_core_fast1$next[2:0]$13571 $3\core_core_fast1$next[2:0]$13689 - assign $1\core_core_fast1_ok$next[0:0]$13572 $3\core_core_fast1_ok$next[0:0]$13690 - assign $1\core_core_fast2$next[2:0]$13573 $3\core_core_fast2$next[2:0]$13691 - assign $1\core_core_fast2_ok$next[0:0]$13574 $3\core_core_fast2_ok$next[0:0]$13692 - assign $1\core_core_fasto1$next[2:0]$13575 $3\core_core_fasto1$next[2:0]$13693 - assign $1\core_core_fasto2$next[2:0]$13576 $3\core_core_fasto2$next[2:0]$13694 - assign $1\core_core_lk$next[0:0]$13577 $3\core_core_lk$next[0:0]$13695 - assign $1\core_core_reg1$next[4:0]$13578 $3\core_core_reg1$next[4:0]$13696 - assign $1\core_core_reg1_ok$next[0:0]$13579 $3\core_core_reg1_ok$next[0:0]$13697 - assign $1\core_core_reg2$next[4:0]$13580 $3\core_core_reg2$next[4:0]$13698 - assign $1\core_core_reg2_ok$next[0:0]$13581 $3\core_core_reg2_ok$next[0:0]$13699 - assign $1\core_core_reg3$next[4:0]$13582 $3\core_core_reg3$next[4:0]$13700 - assign $1\core_core_reg3_ok$next[0:0]$13583 $3\core_core_reg3_ok$next[0:0]$13701 - assign $1\core_core_rego$next[4:0]$13584 $3\core_core_rego$next[4:0]$13702 - assign $1\core_core_spr1$next[9:0]$13585 $3\core_core_spr1$next[9:0]$13703 - assign $1\core_core_spr1_ok$next[0:0]$13586 $3\core_core_spr1_ok$next[0:0]$13704 - assign $1\core_core_spro$next[9:0]$13587 $3\core_core_spro$next[9:0]$13705 - assign $1\core_core_xer_in$next[2:0]$13588 $3\core_core_xer_in$next[2:0]$13706 - assign $1\core_cr_out_ok$next[0:0]$13589 $3\core_cr_out_ok$next[0:0]$13707 - assign $1\core_ea_ok$next[0:0]$13590 $3\core_ea_ok$next[0:0]$13708 - assign $1\core_fasto1_ok$next[0:0]$13591 $3\core_fasto1_ok$next[0:0]$13709 - assign $1\core_fasto2_ok$next[0:0]$13592 $3\core_fasto2_ok$next[0:0]$13710 - assign $1\core_rego_ok$next[0:0]$13593 $3\core_rego_ok$next[0:0]$13711 - assign $1\core_spro_ok$next[0:0]$13594 $3\core_spro_ok$next[0:0]$13712 - assign $1\core_xer_out$next[0:0]$13595 $3\core_xer_out$next[0:0]$13713 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$59 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\core_core_core_is_32bit$next[0:0]$13672 $3\core_core_cr_wr_ok$next[0:0]$13687 $3\core_core_core_cr_wr$next[7:0]$13659 $3\core_core_core_cr_rd_ok$next[0:0]$13658 $3\core_core_core_cr_rd$next[7:0]$13657 $3\core_core_core_trapaddr$next[12:0]$13678 $3\core_core_core_exc_$signal$9$next[0:0]$13666 $3\core_core_core_exc_$signal$8$next[0:0]$13665 $3\core_core_core_exc_$signal$7$next[0:0]$13664 $3\core_core_core_exc_$signal$6$next[0:0]$13663 $3\core_core_core_exc_$signal$5$next[0:0]$13662 $3\core_core_core_exc_$signal$4$next[0:0]$13661 $3\core_core_core_exc_$signal$3$next[0:0]$13660 $3\core_core_core_exc_$signal$next[0:0]$13667 $3\core_core_core_traptype$next[7:0]$13679 $3\core_core_core_input_carry$next[1:0]$13669 $3\core_core_core_oe_ok$next[0:0]$13675 $3\core_core_core_oe$next[0:0]$13674 $3\core_core_core_rc_ok$next[0:0]$13677 $3\core_core_core_rc$next[0:0]$13676 $3\core_core_lk$next[0:0]$13695 $3\core_core_core_fn_unit$next[11:0]$13668 $3\core_core_core_insn_type$next[6:0]$13671 $3\core_core_core_insn$next[31:0]$13670 $3\core_core_core_cia$next[63:0]$13656 $3\core_core_core_msr$next[63:0]$13673 $3\core_cr_out_ok$next[0:0]$13707 $3\core_core_cr_out$next[2:0]$13686 $3\core_core_cr_in2_ok$2$next[0:0]$13684 $3\core_core_cr_in2$1$next[2:0]$13682 $3\core_core_cr_in2_ok$next[0:0]$13685 $3\core_core_cr_in2$next[2:0]$13683 $3\core_core_cr_in1_ok$next[0:0]$13681 $3\core_core_cr_in1$next[2:0]$13680 $3\core_fasto2_ok$next[0:0]$13710 $3\core_core_fasto2$next[2:0]$13694 $3\core_fasto1_ok$next[0:0]$13709 $3\core_core_fasto1$next[2:0]$13693 $3\core_core_fast2_ok$next[0:0]$13692 $3\core_core_fast2$next[2:0]$13691 $3\core_core_fast1_ok$next[0:0]$13690 $3\core_core_fast1$next[2:0]$13689 $3\core_xer_out$next[0:0]$13713 $3\core_core_xer_in$next[2:0]$13706 $3\core_core_spr1_ok$next[0:0]$13704 $3\core_core_spr1$next[9:0]$13703 $3\core_spro_ok$next[0:0]$13712 $3\core_core_spro$next[9:0]$13705 $3\core_core_reg3_ok$next[0:0]$13701 $3\core_core_reg3$next[4:0]$13700 $3\core_core_reg2_ok$next[0:0]$13699 $3\core_core_reg2$next[4:0]$13698 $3\core_core_reg1_ok$next[0:0]$13697 $3\core_core_reg1$next[4:0]$13696 $3\core_ea_ok$next[0:0]$13708 $3\core_core_ea$next[4:0]$13688 $3\core_rego_ok$next[0:0]$13711 $3\core_core_rego$next[4:0]$13702 $3\core_asmcode$next[7:0]$13655 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\core_asmcode$next[7:0]$13655 \core_asmcode - assign $3\core_core_core_cia$next[63:0]$13656 \core_core_core_cia - assign $3\core_core_core_cr_rd$next[7:0]$13657 \core_core_core_cr_rd - assign $3\core_core_core_cr_rd_ok$next[0:0]$13658 \core_core_core_cr_rd_ok - assign $3\core_core_core_cr_wr$next[7:0]$13659 \core_core_core_cr_wr - assign $3\core_core_core_exc_$signal$3$next[0:0]$13660 \core_core_core_exc_$signal$3 - assign $3\core_core_core_exc_$signal$4$next[0:0]$13661 \core_core_core_exc_$signal$4 - assign $3\core_core_core_exc_$signal$5$next[0:0]$13662 \core_core_core_exc_$signal$5 - assign $3\core_core_core_exc_$signal$6$next[0:0]$13663 \core_core_core_exc_$signal$6 - assign $3\core_core_core_exc_$signal$7$next[0:0]$13664 \core_core_core_exc_$signal$7 - assign $3\core_core_core_exc_$signal$8$next[0:0]$13665 \core_core_core_exc_$signal$8 - assign $3\core_core_core_exc_$signal$9$next[0:0]$13666 \core_core_core_exc_$signal$9 - assign $3\core_core_core_exc_$signal$next[0:0]$13667 \core_core_core_exc_$signal - assign $3\core_core_core_fn_unit$next[11:0]$13668 \core_core_core_fn_unit - assign $3\core_core_core_input_carry$next[1:0]$13669 \core_core_core_input_carry - assign $3\core_core_core_insn$next[31:0]$13670 \core_core_core_insn - assign $3\core_core_core_insn_type$next[6:0]$13671 \core_core_core_insn_type - assign $3\core_core_core_is_32bit$next[0:0]$13672 \core_core_core_is_32bit - assign $3\core_core_core_msr$next[63:0]$13673 \core_core_core_msr - assign $3\core_core_core_oe$next[0:0]$13674 \core_core_core_oe - assign $3\core_core_core_oe_ok$next[0:0]$13675 \core_core_core_oe_ok - assign $3\core_core_core_rc$next[0:0]$13676 \core_core_core_rc - assign $3\core_core_core_rc_ok$next[0:0]$13677 \core_core_core_rc_ok - assign $3\core_core_core_trapaddr$next[12:0]$13678 \core_core_core_trapaddr - assign $3\core_core_core_traptype$next[7:0]$13679 \core_core_core_traptype - assign $3\core_core_cr_in1$next[2:0]$13680 \core_core_cr_in1 - assign $3\core_core_cr_in1_ok$next[0:0]$13681 \core_core_cr_in1_ok - assign $3\core_core_cr_in2$1$next[2:0]$13682 \core_core_cr_in2$1 - assign $3\core_core_cr_in2$next[2:0]$13683 \core_core_cr_in2 - assign $3\core_core_cr_in2_ok$2$next[0:0]$13684 \core_core_cr_in2_ok$2 - assign $3\core_core_cr_in2_ok$next[0:0]$13685 \core_core_cr_in2_ok - assign $3\core_core_cr_out$next[2:0]$13686 \core_core_cr_out - assign $3\core_core_cr_wr_ok$next[0:0]$13687 \core_core_cr_wr_ok - assign $3\core_core_ea$next[4:0]$13688 \core_core_ea - assign $3\core_core_fast1$next[2:0]$13689 \core_core_fast1 - assign $3\core_core_fast1_ok$next[0:0]$13690 \core_core_fast1_ok - assign $3\core_core_fast2$next[2:0]$13691 \core_core_fast2 - assign $3\core_core_fast2_ok$next[0:0]$13692 \core_core_fast2_ok - assign $3\core_core_fasto1$next[2:0]$13693 \core_core_fasto1 - assign $3\core_core_fasto2$next[2:0]$13694 \core_core_fasto2 - assign $3\core_core_lk$next[0:0]$13695 \core_core_lk - assign $3\core_core_reg1$next[4:0]$13696 \core_core_reg1 - assign $3\core_core_reg1_ok$next[0:0]$13697 \core_core_reg1_ok - assign $3\core_core_reg2$next[4:0]$13698 \core_core_reg2 - assign $3\core_core_reg2_ok$next[0:0]$13699 \core_core_reg2_ok - assign $3\core_core_reg3$next[4:0]$13700 \core_core_reg3 - assign $3\core_core_reg3_ok$next[0:0]$13701 \core_core_reg3_ok - assign $3\core_core_rego$next[4:0]$13702 \core_core_rego - assign $3\core_core_spr1$next[9:0]$13703 \core_core_spr1 - assign $3\core_core_spr1_ok$next[0:0]$13704 \core_core_spr1_ok - assign $3\core_core_spro$next[9:0]$13705 \core_core_spro - assign $3\core_core_xer_in$next[2:0]$13706 \core_core_xer_in - assign $3\core_cr_out_ok$next[0:0]$13707 \core_cr_out_ok - assign $3\core_ea_ok$next[0:0]$13708 \core_ea_ok - assign $3\core_fasto1_ok$next[0:0]$13709 \core_fasto1_ok - assign $3\core_fasto2_ok$next[0:0]$13710 \core_fasto2_ok - assign $3\core_rego_ok$next[0:0]$13711 \core_rego_ok - assign $3\core_spro_ok$next[0:0]$13712 \core_spro_ok - assign $3\core_xer_out$next[0:0]$13713 \core_xer_out - end - case - assign $1\core_asmcode$next[7:0]$13537 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13538 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13539 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13540 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13541 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13542 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13543 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13544 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13545 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13546 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13547 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13548 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13549 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[11:0]$13550 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13551 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13552 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13553 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13554 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13555 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13556 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13557 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13558 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13559 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13560 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13561 \core_core_core_traptype - assign $1\core_core_cr_in1$next[2:0]$13562 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13563 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[2:0]$13564 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[2:0]$13565 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13566 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13567 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[2:0]$13568 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13569 \core_core_cr_wr_ok - assign $1\core_core_ea$next[4:0]$13570 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13571 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13572 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13573 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13574 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13575 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13576 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13577 \core_core_lk - assign $1\core_core_reg1$next[4:0]$13578 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13579 \core_core_reg1_ok - assign $1\core_core_reg2$next[4:0]$13580 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13581 \core_core_reg2_ok - assign $1\core_core_reg3$next[4:0]$13582 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13583 \core_core_reg3_ok - assign $1\core_core_rego$next[4:0]$13584 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13585 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13586 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13587 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13588 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13589 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13590 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13591 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13592 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13593 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13594 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13595 \core_xer_out - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } @@ -392136,1249 +412317,849 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\core_rego_ok$next[0:0]$13739 1'0 - assign $4\core_ea_ok$next[0:0]$13736 1'0 - assign $4\core_core_reg1_ok$next[0:0]$13731 1'0 - assign $4\core_core_reg2_ok$next[0:0]$13732 1'0 - assign $4\core_core_reg3_ok$next[0:0]$13733 1'0 - assign $4\core_spro_ok$next[0:0]$13740 1'0 - assign $4\core_core_spr1_ok$next[0:0]$13734 1'0 - assign $4\core_core_fast1_ok$next[0:0]$13729 1'0 - assign $4\core_core_fast2_ok$next[0:0]$13730 1'0 - assign $4\core_fasto1_ok$next[0:0]$13737 1'0 - assign $4\core_fasto2_ok$next[0:0]$13738 1'0 - assign $4\core_core_cr_in1_ok$next[0:0]$13725 1'0 - assign $4\core_core_cr_in2_ok$next[0:0]$13727 1'0 - assign $4\core_core_cr_in2_ok$2$next[0:0]$13726 1'0 - assign $4\core_cr_out_ok$next[0:0]$13735 1'0 - assign $4\core_core_core_rc_ok$next[0:0]$13724 1'0 - assign $4\core_core_core_oe_ok$next[0:0]$13723 1'0 - assign $4\core_core_core_exc_$signal$next[0:0]$13722 1'0 - assign $4\core_core_core_exc_$signal$3$next[0:0]$13715 1'0 - assign $4\core_core_core_exc_$signal$4$next[0:0]$13716 1'0 - assign $4\core_core_core_exc_$signal$5$next[0:0]$13717 1'0 - assign $4\core_core_core_exc_$signal$6$next[0:0]$13718 1'0 - assign $4\core_core_core_exc_$signal$7$next[0:0]$13719 1'0 - assign $4\core_core_core_exc_$signal$8$next[0:0]$13720 1'0 - assign $4\core_core_core_exc_$signal$9$next[0:0]$13721 1'0 - assign $4\core_core_core_cr_rd_ok$next[0:0]$13714 1'0 - assign $4\core_core_cr_wr_ok$next[0:0]$13728 1'0 - case - assign $4\core_core_core_cr_rd_ok$next[0:0]$13714 $1\core_core_core_cr_rd_ok$next[0:0]$13540 - assign $4\core_core_core_exc_$signal$3$next[0:0]$13715 $1\core_core_core_exc_$signal$3$next[0:0]$13542 - assign $4\core_core_core_exc_$signal$4$next[0:0]$13716 $1\core_core_core_exc_$signal$4$next[0:0]$13543 - assign $4\core_core_core_exc_$signal$5$next[0:0]$13717 $1\core_core_core_exc_$signal$5$next[0:0]$13544 - assign $4\core_core_core_exc_$signal$6$next[0:0]$13718 $1\core_core_core_exc_$signal$6$next[0:0]$13545 - assign $4\core_core_core_exc_$signal$7$next[0:0]$13719 $1\core_core_core_exc_$signal$7$next[0:0]$13546 - assign $4\core_core_core_exc_$signal$8$next[0:0]$13720 $1\core_core_core_exc_$signal$8$next[0:0]$13547 - assign $4\core_core_core_exc_$signal$9$next[0:0]$13721 $1\core_core_core_exc_$signal$9$next[0:0]$13548 - assign $4\core_core_core_exc_$signal$next[0:0]$13722 $1\core_core_core_exc_$signal$next[0:0]$13549 - assign $4\core_core_core_oe_ok$next[0:0]$13723 $1\core_core_core_oe_ok$next[0:0]$13557 - assign $4\core_core_core_rc_ok$next[0:0]$13724 $1\core_core_core_rc_ok$next[0:0]$13559 - assign $4\core_core_cr_in1_ok$next[0:0]$13725 $1\core_core_cr_in1_ok$next[0:0]$13563 - assign $4\core_core_cr_in2_ok$2$next[0:0]$13726 $1\core_core_cr_in2_ok$2$next[0:0]$13566 - assign $4\core_core_cr_in2_ok$next[0:0]$13727 $1\core_core_cr_in2_ok$next[0:0]$13567 - assign $4\core_core_cr_wr_ok$next[0:0]$13728 $1\core_core_cr_wr_ok$next[0:0]$13569 - assign $4\core_core_fast1_ok$next[0:0]$13729 $1\core_core_fast1_ok$next[0:0]$13572 - assign $4\core_core_fast2_ok$next[0:0]$13730 $1\core_core_fast2_ok$next[0:0]$13574 - assign $4\core_core_reg1_ok$next[0:0]$13731 $1\core_core_reg1_ok$next[0:0]$13579 - assign $4\core_core_reg2_ok$next[0:0]$13732 $1\core_core_reg2_ok$next[0:0]$13581 - assign $4\core_core_reg3_ok$next[0:0]$13733 $1\core_core_reg3_ok$next[0:0]$13583 - assign $4\core_core_spr1_ok$next[0:0]$13734 $1\core_core_spr1_ok$next[0:0]$13586 - assign $4\core_cr_out_ok$next[0:0]$13735 $1\core_cr_out_ok$next[0:0]$13589 - assign $4\core_ea_ok$next[0:0]$13736 $1\core_ea_ok$next[0:0]$13590 - assign $4\core_fasto1_ok$next[0:0]$13737 $1\core_fasto1_ok$next[0:0]$13591 - assign $4\core_fasto2_ok$next[0:0]$13738 $1\core_fasto2_ok$next[0:0]$13592 - assign $4\core_rego_ok$next[0:0]$13739 $1\core_rego_ok$next[0:0]$13593 - assign $4\core_spro_ok$next[0:0]$13740 $1\core_spro_ok$next[0:0]$13594 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$13478 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13479 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13480 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13481 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13482 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13483 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13484 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13485 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13486 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13487 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13488 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13489 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13490 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[11:0]$13491 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13492 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13493 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13494 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13495 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13496 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13497 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13498 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13499 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13500 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13501 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13502 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[2:0]$13503 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13504 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[2:0]$13505 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[2:0]$13506 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13507 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13508 - update \core_core_cr_out$next $0\core_core_cr_out$next[2:0]$13509 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13510 - update \core_core_ea$next $0\core_core_ea$next[4:0]$13511 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13512 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13513 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13514 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13515 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13516 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13517 - update \core_core_lk$next $0\core_core_lk$next[0:0]$13518 - update \core_core_reg1$next $0\core_core_reg1$next[4:0]$13519 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13520 - update \core_core_reg2$next $0\core_core_reg2$next[4:0]$13521 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13522 - update \core_core_reg3$next $0\core_core_reg3$next[4:0]$13523 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13524 - update \core_core_rego$next $0\core_core_rego$next[4:0]$13525 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13526 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13527 - update \core_core_spro$next $0\core_core_spro$next[9:0]$13528 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13529 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13530 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13531 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13532 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13533 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13534 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13535 - update \core_xer_out$next $0\core_xer_out$next[0:0]$13536 - end - attribute \src "libresoc.v:186405.3-186413.6" - process $proc$libresoc.v:186405$13741 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13742 $1\jtag_dmi0__ack_o$next[0:0]$13743 - attribute \src "libresoc.v:186406.5-186406.29" - switch \initial - attribute \src "libresoc.v:186406.9-186406.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13743 1'0 - case - assign $1\jtag_dmi0__ack_o$next[0:0]$13743 \dbg_dmi_ack_o - end - sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13742 - end - attribute \src "libresoc.v:186414.3-186422.6" - process $proc$libresoc.v:186414$13744 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13745 $1\jtag_dmi0__dout$next[63:0]$13746 - attribute \src "libresoc.v:186415.5-186415.29" - switch \initial - attribute \src "libresoc.v:186415.9-186415.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13746 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\jtag_dmi0__dout$next[63:0]$13746 \dbg_dmi_dout - end - sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13745 - end - attribute \src "libresoc.v:186423.3-186431.6" - process $proc$libresoc.v:186423$13747 - assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13748 $1\dec2_cur_eint$next[0:0]$13749 - attribute \src "libresoc.v:186424.5-186424.29" - switch \initial - attribute \src "libresoc.v:186424.9-186424.17" - case 1'1 + assign { $1\core_core_core_is_32bit$next[0:0]$13933 $1\core_core_cr_wr_ok$next[0:0]$13948 $1\core_core_core_cr_wr$next[7:0]$13920 $1\core_core_core_cr_rd_ok$next[0:0]$13919 $1\core_core_core_cr_rd$next[7:0]$13918 $1\core_core_core_trapaddr$next[12:0]$13939 $1\core_core_core_exc_$signal$9$next[0:0]$13927 $1\core_core_core_exc_$signal$8$next[0:0]$13926 $1\core_core_core_exc_$signal$7$next[0:0]$13925 $1\core_core_core_exc_$signal$6$next[0:0]$13924 $1\core_core_core_exc_$signal$5$next[0:0]$13923 $1\core_core_core_exc_$signal$4$next[0:0]$13922 $1\core_core_core_exc_$signal$3$next[0:0]$13921 $1\core_core_core_exc_$signal$next[0:0]$13928 $1\core_core_core_traptype$next[7:0]$13940 $1\core_core_core_input_carry$next[1:0]$13930 $1\core_core_core_oe_ok$next[0:0]$13936 $1\core_core_core_oe$next[0:0]$13935 $1\core_core_core_rc_ok$next[0:0]$13938 $1\core_core_core_rc$next[0:0]$13937 $1\core_core_lk$next[0:0]$13956 $1\core_core_core_fn_unit$next[13:0]$13929 $1\core_core_core_insn_type$next[6:0]$13932 $1\core_core_core_insn$next[31:0]$13931 $1\core_core_core_cia$next[63:0]$13917 $1\core_core_core_msr$next[63:0]$13934 $1\core_cr_out_ok$next[0:0]$13968 $1\core_core_cr_out$next[6:0]$13947 $1\core_core_cr_in2_ok$2$next[0:0]$13945 $1\core_core_cr_in2$1$next[6:0]$13943 $1\core_core_cr_in2_ok$next[0:0]$13946 $1\core_core_cr_in2$next[6:0]$13944 $1\core_core_cr_in1_ok$next[0:0]$13942 $1\core_core_cr_in1$next[6:0]$13941 $1\core_fasto2_ok$next[0:0]$13971 $1\core_core_fasto2$next[2:0]$13955 $1\core_fasto1_ok$next[0:0]$13970 $1\core_core_fasto1$next[2:0]$13954 $1\core_core_fast2_ok$next[0:0]$13953 $1\core_core_fast2$next[2:0]$13952 $1\core_core_fast1_ok$next[0:0]$13951 $1\core_core_fast1$next[2:0]$13950 $1\core_xer_out$next[0:0]$13974 $1\core_core_xer_in$next[2:0]$13967 $1\core_core_spr1_ok$next[0:0]$13965 $1\core_core_spr1$next[9:0]$13964 $1\core_spro_ok$next[0:0]$13973 $1\core_core_spro$next[9:0]$13966 $1\core_core_reg3_ok$next[0:0]$13962 $1\core_core_reg3$next[6:0]$13961 $1\core_core_reg2_ok$next[0:0]$13960 $1\core_core_reg2$next[6:0]$13959 $1\core_core_reg1_ok$next[0:0]$13958 $1\core_core_reg1$next[6:0]$13957 $1\core_ea_ok$next[0:0]$13969 $1\core_core_ea$next[6:0]$13949 $1\core_rego_ok$next[0:0]$13972 $1\core_core_rego$next[6:0]$13963 $1\core_asmcode$next[7:0]$13916 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case + assign $1\core_asmcode$next[7:0]$13916 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13917 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13918 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13919 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13920 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13921 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13922 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13923 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13924 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13925 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13926 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13927 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13928 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13929 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13930 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13931 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13932 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13933 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13934 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13935 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13936 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13937 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13938 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13939 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13940 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13941 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13942 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13943 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13944 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13945 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13946 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13947 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13948 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13949 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13950 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13951 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13952 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13953 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13954 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13955 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13956 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13957 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13958 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13959 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13960 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13961 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13962 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13963 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13964 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13965 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13966 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13967 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13968 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13969 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13970 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13971 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13972 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13973 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13974 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13749 1'0 - case - assign $1\dec2_cur_eint$next[0:0]$13749 \xics_icp_core_irq_o - end - sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13748 - end - attribute \src "libresoc.v:186432.3-186441.6" - process $proc$libresoc.v:186432$13750 - assign { } { } - assign { } { } - assign $0\delay$next[1:0]$13751 $1\delay$next[1:0]$13752 - attribute \src "libresoc.v:186433.5-186433.29" - switch \initial - attribute \src "libresoc.v:186433.9-186433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\delay$next[1:0]$13752 \$23 [1:0] - case - assign $1\delay$next[1:0]$13752 \delay - end - sync always - update \delay$next $0\delay$next[1:0]$13751 - end - attribute \src "libresoc.v:186442.3-186478.6" - process $proc$libresoc.v:186442$13753 - assign { } { } - assign { } { } - assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13754 $4\core_raw_insn_i$next[31:0]$13758 - attribute \src "libresoc.v:186443.5-186443.29" - switch \initial - attribute \src "libresoc.v:186443.9-186443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13755 0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13755 $2\core_raw_insn_i$next[31:0]$13756 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_raw_insn_i$next[31:0]$13756 \core_raw_insn_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13756 \dec2_raw_opcode_in - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13755 $3\core_raw_insn_i$next[31:0]$13757 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$61 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13757 0 - case - assign $3\core_raw_insn_i$next[31:0]$13757 \core_raw_insn_i - end - case - assign $1\core_raw_insn_i$next[31:0]$13755 \core_raw_insn_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $4\core_raw_insn_i$next[31:0]$13758 0 - case - assign $4\core_raw_insn_i$next[31:0]$13758 $1\core_raw_insn_i$next[31:0]$13755 - end - sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13754 - end - attribute \src "libresoc.v:186479.3-186515.6" - process $proc$libresoc.v:186479$13759 - assign { } { } - assign { } { } - assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13760 $4\core_bigendian_i$10$next[0:0]$13764 - attribute \src "libresoc.v:186480.5-186480.29" - switch \initial - attribute \src "libresoc.v:186480.9-186480.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13761 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13761 $2\core_bigendian_i$10$next[0:0]$13762 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_bigendian_i$10$next[0:0]$13762 \core_bigendian_i$10 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13762 \core_bigendian_i - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13761 $3\core_bigendian_i$10$next[0:0]$13763 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13763 1'0 - case - assign $3\core_bigendian_i$10$next[0:0]$13763 \core_bigendian_i$10 - end - case - assign $1\core_bigendian_i$10$next[0:0]$13761 \core_bigendian_i$10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $4\core_bigendian_i$10$next[0:0]$13764 1'0 - case - assign $4\core_bigendian_i$10$next[0:0]$13764 $1\core_bigendian_i$10$next[0:0]$13761 - end - sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13760 - end - attribute \src "libresoc.v:186516.3-186531.6" - process $proc$libresoc.v:186516$13765 - assign { } { } - assign { } { } - assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:186517.5-186517.29" - switch \initial - attribute \src "libresoc.v:186517.9-186517.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_pc_i[47:0] \pc [47:0] - case - assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - case - assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - sync always - update \imem_a_pc_i $0\imem_a_pc_i[47:0] - end - attribute \src "libresoc.v:186532.3-186556.6" - process $proc$libresoc.v:186532$13766 - assign { } { } - assign { } { } - assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186533.5-186533.29" - switch \initial - attribute \src "libresoc.v:186533.9-186533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$75 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_valid_i[0:0] 1'1 - case - assign $2\imem_a_valid_i[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_a_valid_i[0:0] 1'1 - case - assign $3\imem_a_valid_i[0:0] 1'0 - end - case - assign $1\imem_a_valid_i[0:0] 1'0 - end - sync always - update \imem_a_valid_i $0\imem_a_valid_i[0:0] - end - attribute \src "libresoc.v:186557.3-186581.6" - process $proc$libresoc.v:186557$13767 - assign { } { } - assign { } { } - assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:186558.5-186558.29" - switch \initial - attribute \src "libresoc.v:186558.9-186558.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$81 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_f_valid_i[0:0] 1'1 - case - assign $2\imem_f_valid_i[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_f_valid_i[0:0] 1'1 - case - assign $3\imem_f_valid_i[0:0] 1'0 - end - case - assign $1\imem_f_valid_i[0:0] 1'0 - end - sync always - update \imem_f_valid_i $0\imem_f_valid_i[0:0] - end - attribute \src "libresoc.v:186582.3-186602.6" - process $proc$libresoc.v:186582$13768 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13769 $3\dec2_cur_pc$next[63:0]$13772 - attribute \src "libresoc.v:186583.5-186583.29" - switch \initial - attribute \src "libresoc.v:186583.9-186583.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13770 $2\dec2_cur_pc$next[63:0]$13771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13771 \pc - case - assign $2\dec2_cur_pc$next[63:0]$13771 \dec2_cur_pc - end - case - assign $1\dec2_cur_pc$next[63:0]$13770 \dec2_cur_pc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13772 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dec2_cur_pc$next[63:0]$13772 $1\dec2_cur_pc$next[63:0]$13770 - end - sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13769 - end - attribute \src "libresoc.v:186603.3-186632.6" - process $proc$libresoc.v:186603$13773 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr_read$next[0:0]$13774 $4\msr_read$next[0:0]$13778 - attribute \src "libresoc.v:186604.5-186604.29" - switch \initial - attribute \src "libresoc.v:186604.9-186604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13775 $2\msr_read$next[0:0]$13776 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr_read$next[0:0]$13776 1'0 - case - assign $2\msr_read$next[0:0]$13776 \msr_read - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13775 $3\msr_read$next[0:0]$13777 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - switch \$95 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr_read$next[0:0]$13777 1'1 - case - assign $3\msr_read$next[0:0]$13777 \msr_read - end - case - assign $1\msr_read$next[0:0]$13775 \msr_read - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13778 1'1 - case - assign $4\msr_read$next[0:0]$13778 $1\msr_read$next[0:0]$13775 - end - sync always - update \msr_read$next $0\msr_read$next[0:0]$13774 - end - attribute \src "libresoc.v:186633.3-186678.6" - process $proc$libresoc.v:186633$13779 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$next[1:0]$13780 $5\fsm_state$next[1:0]$13785 - attribute \src "libresoc.v:186634.5-186634.29" - switch \initial - attribute \src "libresoc.v:186634.9-186634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13781 $2\fsm_state$next[1:0]$13782 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$13782 2'01 - case - assign $2\fsm_state$next[1:0]$13782 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13781 $3\fsm_state$next[1:0]$13783 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $3\fsm_state$next[1:0]$13783 \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\fsm_state$next[1:0]$13783 2'10 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13781 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13781 $4\fsm_state$next[1:0]$13784 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$103 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$13784 2'00 - case - assign $4\fsm_state$next[1:0]$13784 \fsm_state - end - case - assign $1\fsm_state$next[1:0]$13781 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$13785 2'00 - case - assign $5\fsm_state$next[1:0]$13785 $1\fsm_state$next[1:0]$13781 - end - sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13780 - end - attribute \src "libresoc.v:186679.3-186697.6" - process $proc$libresoc.v:186679$13786 - assign { } { } - assign { } { } - assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:186680.5-186680.29" - switch \initial - attribute \src "libresoc.v:186680.9-186680.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$109 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_stopped_i[0:0] 1'1 - end - case - assign $1\core_stopped_i[0:0] 1'0 - end - sync always - update \core_stopped_i $0\core_stopped_i[0:0] - end - attribute \src "libresoc.v:186698.3-186716.6" - process $proc$libresoc.v:186698$13787 - assign { } { } - assign { } { } - assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:186699.5-186699.29" - switch \initial - attribute \src "libresoc.v:186699.9-186699.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dbg_core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbg_core_stopped_i[0:0] 1'1 - end - case - assign $1\dbg_core_stopped_i[0:0] 1'0 - end - sync always - update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] - end - connect \$99 $not$libresoc.v:184936$13229_Y - connect \$101 $and$libresoc.v:184937$13230_Y - connect \$103 $not$libresoc.v:184938$13231_Y - connect \$105 $not$libresoc.v:184939$13232_Y - connect \$107 $not$libresoc.v:184940$13233_Y - connect \$109 $and$libresoc.v:184941$13234_Y - connect \$111 $not$libresoc.v:184942$13235_Y - connect \$113 $not$libresoc.v:184943$13236_Y - connect \$115 $and$libresoc.v:184944$13237_Y - connect \$117 $not$libresoc.v:184945$13238_Y - connect \$120 $mul$libresoc.v:184946$13239_Y - connect \$119 $shr$libresoc.v:184947$13240_Y [31:0] - connect \$124 $mul$libresoc.v:184948$13241_Y - connect \$123 $shr$libresoc.v:184949$13242_Y [31:0] - connect \$127 $ne$libresoc.v:184950$13243_Y - connect \$129 $pos$libresoc.v:184951$13245_Y - connect \$131 $pos$libresoc.v:184952$13247_Y - connect \$135 $sub$libresoc.v:184953$13248_Y - connect \$138 $add$libresoc.v:184954$13249_Y - connect \$21 $ne$libresoc.v:184955$13250_Y - connect \$24 $sub$libresoc.v:184956$13251_Y - connect \$26 $or$libresoc.v:184957$13252_Y - connect \$28 $or$libresoc.v:184958$13253_Y - connect \$30 $ne$libresoc.v:184959$13254_Y - connect \$32 $not$libresoc.v:184960$13255_Y - connect \$34 $and$libresoc.v:184961$13256_Y - connect \$37 $add$libresoc.v:184962$13257_Y - connect \$39 $not$libresoc.v:184963$13258_Y - connect \$41 $not$libresoc.v:184964$13259_Y - connect \$43 $not$libresoc.v:184965$13260_Y - connect \$45 $not$libresoc.v:184966$13261_Y - connect \$47 $not$libresoc.v:184967$13262_Y - connect \$49 $not$libresoc.v:184968$13263_Y - connect \$51 $not$libresoc.v:184969$13264_Y - connect \$53 $and$libresoc.v:184970$13265_Y - connect \$56 $and$libresoc.v:184971$13266_Y - connect \$55 $reduce_or$libresoc.v:184972$13267_Y - connect \$59 $not$libresoc.v:184973$13268_Y - connect \$61 $not$libresoc.v:184974$13269_Y - connect \$63 $not$libresoc.v:184975$13270_Y - connect \$65 $not$libresoc.v:184976$13271_Y - connect \$67 $not$libresoc.v:184977$13272_Y - connect \$69 $and$libresoc.v:184978$13273_Y - connect \$71 $not$libresoc.v:184979$13274_Y - connect \$73 $not$libresoc.v:184980$13275_Y - connect \$75 $and$libresoc.v:184981$13276_Y - connect \$77 $not$libresoc.v:184982$13277_Y - connect \$79 $not$libresoc.v:184983$13278_Y - connect \$81 $and$libresoc.v:184984$13279_Y - connect \$83 $not$libresoc.v:184985$13280_Y - connect \$85 $not$libresoc.v:184986$13281_Y - connect \$87 $and$libresoc.v:184987$13282_Y - connect \$89 $not$libresoc.v:184988$13283_Y - connect \$91 $not$libresoc.v:184989$13284_Y - connect \$93 $and$libresoc.v:184990$13285_Y - connect \$95 $not$libresoc.v:184991$13286_Y - connect \$97 $not$libresoc.v:184992$13287_Y - connect \$23 \$24 - connect \$36 \$37 - connect \$134 \$135 - connect \$137 \$138 + assign $3\core_rego_ok$next[0:0]$14059 1'0 + assign $3\core_ea_ok$next[0:0]$14056 1'0 + assign $3\core_core_reg1_ok$next[0:0]$14051 1'0 + assign $3\core_core_reg2_ok$next[0:0]$14052 1'0 + assign $3\core_core_reg3_ok$next[0:0]$14053 1'0 + assign $3\core_spro_ok$next[0:0]$14060 1'0 + assign $3\core_core_spr1_ok$next[0:0]$14054 1'0 + assign $3\core_core_fast1_ok$next[0:0]$14049 1'0 + assign $3\core_core_fast2_ok$next[0:0]$14050 1'0 + assign $3\core_fasto1_ok$next[0:0]$14057 1'0 + assign $3\core_fasto2_ok$next[0:0]$14058 1'0 + assign $3\core_core_cr_in1_ok$next[0:0]$14045 1'0 + assign $3\core_core_cr_in2_ok$next[0:0]$14047 1'0 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14046 1'0 + assign $3\core_cr_out_ok$next[0:0]$14055 1'0 + assign $3\core_core_core_rc_ok$next[0:0]$14044 1'0 + assign $3\core_core_core_oe_ok$next[0:0]$14043 1'0 + assign $3\core_core_core_exc_$signal$next[0:0]$14042 1'0 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14035 1'0 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14036 1'0 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14037 1'0 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14038 1'0 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14039 1'0 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14040 1'0 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14041 1'0 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14034 1'0 + assign $3\core_core_cr_wr_ok$next[0:0]$14048 1'0 + case + assign $3\core_core_core_cr_rd_ok$next[0:0]$14034 $1\core_core_core_cr_rd_ok$next[0:0]$13919 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14035 $1\core_core_core_exc_$signal$3$next[0:0]$13921 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14036 $1\core_core_core_exc_$signal$4$next[0:0]$13922 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14037 $1\core_core_core_exc_$signal$5$next[0:0]$13923 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14038 $1\core_core_core_exc_$signal$6$next[0:0]$13924 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14039 $1\core_core_core_exc_$signal$7$next[0:0]$13925 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14040 $1\core_core_core_exc_$signal$8$next[0:0]$13926 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14041 $1\core_core_core_exc_$signal$9$next[0:0]$13927 + assign $3\core_core_core_exc_$signal$next[0:0]$14042 $1\core_core_core_exc_$signal$next[0:0]$13928 + assign $3\core_core_core_oe_ok$next[0:0]$14043 $1\core_core_core_oe_ok$next[0:0]$13936 + assign $3\core_core_core_rc_ok$next[0:0]$14044 $1\core_core_core_rc_ok$next[0:0]$13938 + assign $3\core_core_cr_in1_ok$next[0:0]$14045 $1\core_core_cr_in1_ok$next[0:0]$13942 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14046 $1\core_core_cr_in2_ok$2$next[0:0]$13945 + assign $3\core_core_cr_in2_ok$next[0:0]$14047 $1\core_core_cr_in2_ok$next[0:0]$13946 + assign $3\core_core_cr_wr_ok$next[0:0]$14048 $1\core_core_cr_wr_ok$next[0:0]$13948 + assign $3\core_core_fast1_ok$next[0:0]$14049 $1\core_core_fast1_ok$next[0:0]$13951 + assign $3\core_core_fast2_ok$next[0:0]$14050 $1\core_core_fast2_ok$next[0:0]$13953 + assign $3\core_core_reg1_ok$next[0:0]$14051 $1\core_core_reg1_ok$next[0:0]$13958 + assign $3\core_core_reg2_ok$next[0:0]$14052 $1\core_core_reg2_ok$next[0:0]$13960 + assign $3\core_core_reg3_ok$next[0:0]$14053 $1\core_core_reg3_ok$next[0:0]$13962 + assign $3\core_core_spr1_ok$next[0:0]$14054 $1\core_core_spr1_ok$next[0:0]$13965 + assign $3\core_cr_out_ok$next[0:0]$14055 $1\core_cr_out_ok$next[0:0]$13968 + assign $3\core_ea_ok$next[0:0]$14056 $1\core_ea_ok$next[0:0]$13969 + assign $3\core_fasto1_ok$next[0:0]$14057 $1\core_fasto1_ok$next[0:0]$13970 + assign $3\core_fasto2_ok$next[0:0]$14058 $1\core_fasto2_ok$next[0:0]$13971 + assign $3\core_rego_ok$next[0:0]$14059 $1\core_rego_ok$next[0:0]$13972 + assign $3\core_spro_ok$next[0:0]$14060 $1\core_spro_ok$next[0:0]$13973 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$13857 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13858 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13859 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13860 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13861 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13862 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13863 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13864 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13865 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13866 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13867 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13868 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13869 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13870 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13871 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13872 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13873 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13874 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13875 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13876 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13877 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13878 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13879 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13880 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13881 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13882 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13883 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13884 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13885 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13886 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13887 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13888 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13889 + update \core_core_ea$next $0\core_core_ea$next[6:0]$13890 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13891 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13892 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13893 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13894 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13895 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13896 + update \core_core_lk$next $0\core_core_lk$next[0:0]$13897 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13898 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13899 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13900 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13901 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13902 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13903 + update \core_core_rego$next $0\core_core_rego$next[6:0]$13904 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13905 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13906 + update \core_core_spro$next $0\core_core_spro$next[9:0]$13907 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13908 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13909 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13910 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13911 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13912 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13913 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13914 + update \core_xer_out$next $0\core_xer_out$next[0:0]$13915 + end + connect \$101 $add$libresoc.v:194791$13361_Y + connect \$103 $mul$libresoc.v:194792$13362_Y + connect \$99 $shr$libresoc.v:194793$13363_Y [31:0] + connect \$106 $not$libresoc.v:194794$13364_Y + connect \$108 $not$libresoc.v:194795$13365_Y + connect \$110 $and$libresoc.v:194796$13366_Y + connect \$112 $not$libresoc.v:194797$13367_Y + connect \$114 $not$libresoc.v:194798$13368_Y + connect \$116 $and$libresoc.v:194799$13369_Y + connect \$118 $or$libresoc.v:194800$13370_Y + connect \$120 1'1 + connect \$122 $or$libresoc.v:194802$13371_Y + connect \$124 $not$libresoc.v:194803$13372_Y + connect \$126 $not$libresoc.v:194804$13373_Y + connect \$128 $and$libresoc.v:194805$13374_Y + connect \$130 $not$libresoc.v:194806$13375_Y + connect \$132 $not$libresoc.v:194807$13376_Y + connect \$134 $and$libresoc.v:194808$13377_Y + connect \$136 $eq$libresoc.v:194809$13378_Y + connect \$138 $and$libresoc.v:194810$13379_Y + connect \$140 $not$libresoc.v:194811$13380_Y + connect \$142 $not$libresoc.v:194812$13381_Y + connect \$144 $and$libresoc.v:194813$13382_Y + connect \$146 $or$libresoc.v:194814$13383_Y + connect \$148 1'1 + connect \$150 $or$libresoc.v:194816$13384_Y + connect \$152 $not$libresoc.v:194817$13385_Y + connect \$154 $not$libresoc.v:194818$13386_Y + connect \$156 $and$libresoc.v:194819$13387_Y + connect \$158 $not$libresoc.v:194820$13388_Y + connect \$160 $not$libresoc.v:194821$13389_Y + connect \$162 $and$libresoc.v:194822$13390_Y + connect \$164 $not$libresoc.v:194823$13391_Y + connect \$166 $not$libresoc.v:194824$13392_Y + connect \$168 $and$libresoc.v:194825$13393_Y + connect \$170 $not$libresoc.v:194826$13394_Y + connect \$172 $not$libresoc.v:194827$13395_Y + connect \$174 $and$libresoc.v:194828$13396_Y + connect \$176 $not$libresoc.v:194829$13397_Y + connect \$178 $not$libresoc.v:194830$13398_Y + connect \$180 $and$libresoc.v:194831$13399_Y + connect \$182 $not$libresoc.v:194832$13400_Y + connect \$184 $not$libresoc.v:194833$13401_Y + connect \$186 $and$libresoc.v:194834$13402_Y + connect \$189 $and$libresoc.v:194835$13403_Y + connect \$188 $reduce_or$libresoc.v:194836$13404_Y + connect \$192 $not$libresoc.v:194837$13405_Y + connect \$194 $not$libresoc.v:194838$13406_Y + connect \$196 $and$libresoc.v:194839$13407_Y + connect \$198 $not$libresoc.v:194840$13408_Y + connect \$200 $not$libresoc.v:194841$13409_Y + connect \$202 $and$libresoc.v:194842$13410_Y + connect \$204 $or$libresoc.v:194843$13411_Y + connect \$206 1'1 + connect \$208 $or$libresoc.v:194845$13412_Y + connect \$210 $not$libresoc.v:194846$13413_Y + connect \$212 $not$libresoc.v:194847$13414_Y + connect \$214 $and$libresoc.v:194848$13415_Y + connect \$216 $not$libresoc.v:194849$13416_Y + connect \$218 $not$libresoc.v:194850$13417_Y + connect \$220 $and$libresoc.v:194851$13418_Y + connect \$223 $and$libresoc.v:194852$13419_Y + connect \$222 $reduce_or$libresoc.v:194853$13420_Y + connect \$226 $eq$libresoc.v:194854$13421_Y + connect \$228 $and$libresoc.v:194855$13422_Y + connect \$230 $not$libresoc.v:194856$13423_Y + connect \$232 $not$libresoc.v:194857$13424_Y + connect \$234 $not$libresoc.v:194858$13425_Y + connect \$236 $and$libresoc.v:194859$13426_Y + connect \$238 $not$libresoc.v:194860$13427_Y + connect \$23 $ne$libresoc.v:194861$13428_Y + connect \$240 $not$libresoc.v:194862$13429_Y + connect \$242 $and$libresoc.v:194863$13430_Y + connect \$245 $add$libresoc.v:194864$13431_Y + connect \$247 $not$libresoc.v:194865$13432_Y + connect \$249 $not$libresoc.v:194866$13433_Y + connect \$251 $and$libresoc.v:194867$13434_Y + connect \$253 $eq$libresoc.v:194868$13435_Y + connect \$255 $pos$libresoc.v:194869$13436_Y + connect \$257 $ne$libresoc.v:194870$13437_Y + connect \$259 $not$libresoc.v:194871$13438_Y + connect \$261 $not$libresoc.v:194872$13439_Y + connect \$263 $pos$libresoc.v:194873$13441_Y + connect \$265 $pos$libresoc.v:194874$13443_Y + connect \$268 $sub$libresoc.v:194875$13444_Y + connect \$26 $sub$libresoc.v:194876$13445_Y + connect \$271 $add$libresoc.v:194877$13446_Y + connect \$28 $or$libresoc.v:194878$13447_Y + connect \$30 $or$libresoc.v:194879$13448_Y + connect \$32 $ne$libresoc.v:194880$13449_Y + connect \$34 $not$libresoc.v:194881$13450_Y + connect \$36 $and$libresoc.v:194882$13451_Y + connect \$38 $not$libresoc.v:194883$13452_Y + connect \$40 $not$libresoc.v:194884$13453_Y + connect \$42 $pos$libresoc.v:194885$13455_Y + connect \$44 $not$libresoc.v:194886$13456_Y + connect \$46 $not$libresoc.v:194887$13457_Y + connect \$48 $and$libresoc.v:194888$13458_Y + connect \$50 $eq$libresoc.v:194889$13459_Y + connect \$52 $and$libresoc.v:194890$13460_Y + connect \$54 $not$libresoc.v:194891$13461_Y + connect \$56 $not$libresoc.v:194892$13462_Y + connect \$58 $and$libresoc.v:194893$13463_Y + connect \$60 $or$libresoc.v:194894$13464_Y + connect \$62 1'1 + connect \$64 $or$libresoc.v:194896$13465_Y + connect \$66 $not$libresoc.v:194897$13466_Y + connect \$68 $not$libresoc.v:194898$13467_Y + connect \$70 $and$libresoc.v:194899$13468_Y + connect \$72 $eq$libresoc.v:194900$13469_Y + connect \$74 $and$libresoc.v:194901$13470_Y + connect \$76 $not$libresoc.v:194902$13471_Y + connect \$78 $not$libresoc.v:194903$13472_Y + connect \$80 $and$libresoc.v:194904$13473_Y + connect \$82 $or$libresoc.v:194905$13474_Y + connect \$84 1'1 + connect \$86 $or$libresoc.v:194907$13475_Y + connect \$88 $not$libresoc.v:194908$13476_Y + connect \$90 $not$libresoc.v:194909$13477_Y + connect \$93 $add$libresoc.v:194910$13478_Y + connect \$96 $mul$libresoc.v:194911$13479_Y + connect \$95 $shr$libresoc.v:194912$13480_Y [31:0] + connect \$25 \$26 + connect \$92 \$93 + connect \$100 \$101 + connect \$244 \$245 + connect \$267 \$268 + connect \$270 \$271 + connect \dec2_sv_a_nz 1'0 + connect \svstate_i_ok 1'0 + connect \svstate_i 0 + connect \is_svp64_mode 1'0 connect \dbg_core_dbg_msr \dec2_cur_msr + connect { \dbg_core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_svstep } \svstate [31:0] connect \dbg_core_dbg_pc \pc connect \dbg_terminate_i \core_core_terminate_o - connect \nia \$37 [63:0] connect \pc_o \dec2_cur_pc connect \core_cu_st__go_i \cu_st__rel_o_rise connect \core_cu_ad__go_i \core_cu_ad__rel_o - connect \cu_st__rel_o_rise \$34 + connect \cu_st__rel_o_rise \$36 connect \cu_st__rel_o_dly$next \core_cu_st__rel_o connect \dec2_bigendian \core_bigendian_i connect \busy_o \core_corebusy_o connect \core_coresync_rst \ti_rst - connect \ti_rst \$30 + connect \ti_rst \$32 connect \por_clk \clk connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } + connect \sram4k_3_enable \jtag_wb_sram_en + connect \sram4k_2_enable \jtag_wb_sram_en + connect \sram4k_1_enable \jtag_wb_sram_en + connect \sram4k_0_enable \jtag_wb_sram_en end -attribute \src "libresoc.v:186740.1-187925.10" +attribute \src "libresoc.v:197549.1-198740.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:187470.3-187471.25" + attribute \src "libresoc.v:198285.3-198286.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:187468.3-187469.41" + attribute \src "libresoc.v:198283.3-198284.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:187828.3-187836.6" - wire $0\alu_l_r_alu$next[0:0]$14092 - attribute \src "libresoc.v:187396.3-187397.39" + attribute \src "libresoc.v:198643.3-198651.6" + wire $0\alu_l_r_alu$next[0:0]$14382 + attribute \src "libresoc.v:198211.3-198212.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14018 - attribute \src "libresoc.v:187436.3-187437.61" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14308 + attribute \src "libresoc.v:198251.3-198252.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 12 $0\alu_trap0_trap_op__fn_unit$next[11:0]$14019 - attribute \src "libresoc.v:187430.3-187431.69" - wire width 12 $0\alu_trap0_trap_op__fn_unit[11:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14020 - attribute \src "libresoc.v:187432.3-187433.63" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 + attribute \src "libresoc.v:198245.3-198246.69" + wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] + attribute \src "libresoc.v:198466.3-198483.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14310 + attribute \src "libresoc.v:198247.3-198248.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14021 - attribute \src "libresoc.v:187428.3-187429.73" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 + attribute \src "libresoc.v:198243.3-198244.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14022 - attribute \src "libresoc.v:187438.3-187439.71" + attribute \src "libresoc.v:198466.3-198483.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 + attribute \src "libresoc.v:198253.3-198254.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14023 - attribute \src "libresoc.v:187444.3-187445.71" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 + attribute \src "libresoc.v:198259.3-198260.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14024 - attribute \src "libresoc.v:187434.3-187435.61" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14314 + attribute \src "libresoc.v:198249.3-198250.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14025 - attribute \src "libresoc.v:187442.3-187443.71" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 + attribute \src "libresoc.v:198257.3-198258.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14026 - attribute \src "libresoc.v:187440.3-187441.71" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14316 + attribute \src "libresoc.v:198255.3-198256.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:187819.3-187827.6" - wire $0\alui_l_r_alui$next[0:0]$14089 - attribute \src "libresoc.v:187398.3-187399.43" + attribute \src "libresoc.v:198634.3-198642.6" + wire $0\alui_l_r_alui$next[0:0]$14379 + attribute \src "libresoc.v:198213.3-198214.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187669.3-187690.6" - wire width 64 $0\data_r0__o$next[63:0]$14037 - attribute \src "libresoc.v:187424.3-187425.37" + attribute \src "libresoc.v:198484.3-198505.6" + wire width 64 $0\data_r0__o$next[63:0]$14327 + attribute \src "libresoc.v:198239.3-198240.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:187669.3-187690.6" - wire $0\data_r0__o_ok$next[0:0]$14038 - attribute \src "libresoc.v:187426.3-187427.43" + attribute \src "libresoc.v:198484.3-198505.6" + wire $0\data_r0__o_ok$next[0:0]$14328 + attribute \src "libresoc.v:198241.3-198242.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187691.3-187712.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14045 - attribute \src "libresoc.v:187420.3-187421.45" + attribute \src "libresoc.v:198506.3-198527.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14335 + attribute \src "libresoc.v:198235.3-198236.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:187691.3-187712.6" - wire $0\data_r1__fast1_ok$next[0:0]$14046 - attribute \src "libresoc.v:187422.3-187423.51" + attribute \src "libresoc.v:198506.3-198527.6" + wire $0\data_r1__fast1_ok$next[0:0]$14336 + attribute \src "libresoc.v:198237.3-198238.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:187713.3-187734.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14053 - attribute \src "libresoc.v:187416.3-187417.45" + attribute \src "libresoc.v:198528.3-198549.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14343 + attribute \src "libresoc.v:198231.3-198232.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:187713.3-187734.6" - wire $0\data_r2__fast2_ok$next[0:0]$14054 - attribute \src "libresoc.v:187418.3-187419.51" + attribute \src "libresoc.v:198528.3-198549.6" + wire $0\data_r2__fast2_ok$next[0:0]$14344 + attribute \src "libresoc.v:198233.3-198234.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:187735.3-187756.6" - wire width 64 $0\data_r3__nia$next[63:0]$14061 - attribute \src "libresoc.v:187412.3-187413.41" + attribute \src "libresoc.v:198550.3-198571.6" + wire width 64 $0\data_r3__nia$next[63:0]$14351 + attribute \src "libresoc.v:198227.3-198228.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:187735.3-187756.6" - wire $0\data_r3__nia_ok$next[0:0]$14062 - attribute \src "libresoc.v:187414.3-187415.47" + attribute \src "libresoc.v:198550.3-198571.6" + wire $0\data_r3__nia_ok$next[0:0]$14352 + attribute \src "libresoc.v:198229.3-198230.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:187757.3-187778.6" - wire width 64 $0\data_r4__msr$next[63:0]$14069 - attribute \src "libresoc.v:187408.3-187409.41" + attribute \src "libresoc.v:198572.3-198593.6" + wire width 64 $0\data_r4__msr$next[63:0]$14359 + attribute \src "libresoc.v:198223.3-198224.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:187757.3-187778.6" - wire $0\data_r4__msr_ok$next[0:0]$14070 - attribute \src "libresoc.v:187410.3-187411.47" + attribute \src "libresoc.v:198572.3-198593.6" + wire $0\data_r4__msr_ok$next[0:0]$14360 + attribute \src "libresoc.v:198225.3-198226.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:187837.3-187846.6" + attribute \src "libresoc.v:198652.3-198661.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:187847.3-187856.6" + attribute \src "libresoc.v:198662.3-198671.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:187857.3-187866.6" + attribute \src "libresoc.v:198672.3-198681.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:187867.3-187876.6" + attribute \src "libresoc.v:198682.3-198691.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:187877.3-187886.6" + attribute \src "libresoc.v:198692.3-198701.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:186741.7-186741.20" + attribute \src "libresoc.v:197550.7-197550.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187606.3-187614.6" - wire $0\opc_l_r_opc$next[0:0]$14003 - attribute \src "libresoc.v:187454.3-187455.39" + attribute \src "libresoc.v:198421.3-198429.6" + wire $0\opc_l_r_opc$next[0:0]$14293 + attribute \src "libresoc.v:198269.3-198270.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187597.3-187605.6" - wire $0\opc_l_s_opc$next[0:0]$14000 - attribute \src "libresoc.v:187456.3-187457.39" + attribute \src "libresoc.v:198412.3-198420.6" + wire $0\opc_l_s_opc$next[0:0]$14290 + attribute \src "libresoc.v:198271.3-198272.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:187887.3-187895.6" - wire width 5 $0\prev_wr_go$next[4:0]$14100 - attribute \src "libresoc.v:187466.3-187467.37" + attribute \src "libresoc.v:198702.3-198710.6" + wire width 5 $0\prev_wr_go$next[4:0]$14390 + attribute \src "libresoc.v:198281.3-198282.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:187551.3-187560.6" + attribute \src "libresoc.v:198366.3-198375.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:187642.3-187650.6" - wire width 5 $0\req_l_r_req$next[4:0]$14015 - attribute \src "libresoc.v:187446.3-187447.39" + attribute \src "libresoc.v:198457.3-198465.6" + wire width 5 $0\req_l_r_req$next[4:0]$14305 + attribute \src "libresoc.v:198261.3-198262.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:187633.3-187641.6" - wire width 5 $0\req_l_s_req$next[4:0]$14012 - attribute \src "libresoc.v:187448.3-187449.39" + attribute \src "libresoc.v:198448.3-198456.6" + wire width 5 $0\req_l_s_req$next[4:0]$14302 + attribute \src "libresoc.v:198263.3-198264.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:187570.3-187578.6" - wire $0\rok_l_r_rdok$next[0:0]$13991 - attribute \src "libresoc.v:187462.3-187463.41" + attribute \src "libresoc.v:198385.3-198393.6" + wire $0\rok_l_r_rdok$next[0:0]$14281 + attribute \src "libresoc.v:198277.3-198278.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187561.3-187569.6" - wire $0\rok_l_s_rdok$next[0:0]$13988 - attribute \src "libresoc.v:187464.3-187465.41" + attribute \src "libresoc.v:198376.3-198384.6" + wire $0\rok_l_s_rdok$next[0:0]$14278 + attribute \src "libresoc.v:198279.3-198280.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187588.3-187596.6" - wire $0\rst_l_r_rst$next[0:0]$13997 - attribute \src "libresoc.v:187458.3-187459.39" + attribute \src "libresoc.v:198403.3-198411.6" + wire $0\rst_l_r_rst$next[0:0]$14287 + attribute \src "libresoc.v:198273.3-198274.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187579.3-187587.6" - wire $0\rst_l_s_rst$next[0:0]$13994 - attribute \src "libresoc.v:187460.3-187461.39" + attribute \src "libresoc.v:198394.3-198402.6" + wire $0\rst_l_s_rst$next[0:0]$14284 + attribute \src "libresoc.v:198275.3-198276.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187624.3-187632.6" - wire width 4 $0\src_l_r_src$next[3:0]$14009 - attribute \src "libresoc.v:187450.3-187451.39" + attribute \src "libresoc.v:198439.3-198447.6" + wire width 4 $0\src_l_r_src$next[3:0]$14299 + attribute \src "libresoc.v:198265.3-198266.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:187615.3-187623.6" - wire width 4 $0\src_l_s_src$next[3:0]$14006 - attribute \src "libresoc.v:187452.3-187453.39" + attribute \src "libresoc.v:198430.3-198438.6" + wire width 4 $0\src_l_s_src$next[3:0]$14296 + attribute \src "libresoc.v:198267.3-198268.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:187779.3-187788.6" - wire width 64 $0\src_r0$next[63:0]$14077 - attribute \src "libresoc.v:187406.3-187407.29" + attribute \src "libresoc.v:198594.3-198603.6" + wire width 64 $0\src_r0$next[63:0]$14367 + attribute \src "libresoc.v:198221.3-198222.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:187789.3-187798.6" - wire width 64 $0\src_r1$next[63:0]$14080 - attribute \src "libresoc.v:187404.3-187405.29" + attribute \src "libresoc.v:198604.3-198613.6" + wire width 64 $0\src_r1$next[63:0]$14370 + attribute \src "libresoc.v:198219.3-198220.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:187799.3-187808.6" - wire width 64 $0\src_r2$next[63:0]$14083 - attribute \src "libresoc.v:187402.3-187403.29" + attribute \src "libresoc.v:198614.3-198623.6" + wire width 64 $0\src_r2$next[63:0]$14373 + attribute \src "libresoc.v:198217.3-198218.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:187809.3-187818.6" - wire width 64 $0\src_r3$next[63:0]$14086 - attribute \src "libresoc.v:187400.3-187401.29" + attribute \src "libresoc.v:198624.3-198633.6" + wire width 64 $0\src_r3$next[63:0]$14376 + attribute \src "libresoc.v:198215.3-198216.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:186867.7-186867.24" + attribute \src "libresoc.v:197676.7-197676.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:186877.7-186877.26" + attribute \src "libresoc.v:197686.7-197686.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:187828.3-187836.6" - wire $1\alu_l_r_alu$next[0:0]$14093 - attribute \src "libresoc.v:186885.7-186885.25" + attribute \src "libresoc.v:198643.3-198651.6" + wire $1\alu_l_r_alu$next[0:0]$14383 + attribute \src "libresoc.v:197694.7-197694.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14027 - attribute \src "libresoc.v:186921.14-186921.59" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14317 + attribute \src "libresoc.v:197730.14-197730.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 12 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14028 - attribute \src "libresoc.v:186938.14-186938.50" - wire width 12 $1\alu_trap0_trap_op__fn_unit[11:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14029 - attribute \src "libresoc.v:186942.14-186942.45" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 + attribute \src "libresoc.v:197749.14-197749.51" + wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] + attribute \src "libresoc.v:198466.3-198483.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14319 + attribute \src "libresoc.v:197753.14-197753.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14030 - attribute \src "libresoc.v:187020.13-187020.49" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 + attribute \src "libresoc.v:197832.13-197832.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14031 - attribute \src "libresoc.v:187024.7-187024.41" + attribute \src "libresoc.v:198466.3-198483.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 + attribute \src "libresoc.v:197836.7-197836.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14032 - attribute \src "libresoc.v:187028.13-187028.48" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 + attribute \src "libresoc.v:197840.13-197840.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14033 - attribute \src "libresoc.v:187032.14-187032.59" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14323 + attribute \src "libresoc.v:197844.14-197844.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14034 - attribute \src "libresoc.v:187036.14-187036.52" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 + attribute \src "libresoc.v:197848.14-197848.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:187651.3-187668.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14035 - attribute \src "libresoc.v:187040.13-187040.48" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 + attribute \src "libresoc.v:197852.13-197852.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:187819.3-187827.6" - wire $1\alui_l_r_alui$next[0:0]$14090 - attribute \src "libresoc.v:187046.7-187046.27" + attribute \src "libresoc.v:198634.3-198642.6" + wire $1\alui_l_r_alui$next[0:0]$14380 + attribute \src "libresoc.v:197858.7-197858.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187669.3-187690.6" - wire width 64 $1\data_r0__o$next[63:0]$14039 - attribute \src "libresoc.v:187078.14-187078.47" + attribute \src "libresoc.v:198484.3-198505.6" + wire width 64 $1\data_r0__o$next[63:0]$14329 + attribute \src "libresoc.v:197890.14-197890.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:187669.3-187690.6" - wire $1\data_r0__o_ok$next[0:0]$14040 - attribute \src "libresoc.v:187082.7-187082.27" + attribute \src "libresoc.v:198484.3-198505.6" + wire $1\data_r0__o_ok$next[0:0]$14330 + attribute \src "libresoc.v:197894.7-197894.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187691.3-187712.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14047 - attribute \src "libresoc.v:187086.14-187086.51" + attribute \src "libresoc.v:198506.3-198527.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14337 + attribute \src "libresoc.v:197898.14-197898.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:187691.3-187712.6" - wire $1\data_r1__fast1_ok$next[0:0]$14048 - attribute \src "libresoc.v:187090.7-187090.31" + attribute \src "libresoc.v:198506.3-198527.6" + wire $1\data_r1__fast1_ok$next[0:0]$14338 + attribute \src "libresoc.v:197902.7-197902.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:187713.3-187734.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14055 - attribute \src "libresoc.v:187094.14-187094.51" + attribute \src "libresoc.v:198528.3-198549.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14345 + attribute \src "libresoc.v:197906.14-197906.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:187713.3-187734.6" - wire $1\data_r2__fast2_ok$next[0:0]$14056 - attribute \src "libresoc.v:187098.7-187098.31" + attribute \src "libresoc.v:198528.3-198549.6" + wire $1\data_r2__fast2_ok$next[0:0]$14346 + attribute \src "libresoc.v:197910.7-197910.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:187735.3-187756.6" - wire width 64 $1\data_r3__nia$next[63:0]$14063 - attribute \src "libresoc.v:187102.14-187102.49" + attribute \src "libresoc.v:198550.3-198571.6" + wire width 64 $1\data_r3__nia$next[63:0]$14353 + attribute \src "libresoc.v:197914.14-197914.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:187735.3-187756.6" - wire $1\data_r3__nia_ok$next[0:0]$14064 - attribute \src "libresoc.v:187106.7-187106.29" + attribute \src "libresoc.v:198550.3-198571.6" + wire $1\data_r3__nia_ok$next[0:0]$14354 + attribute \src "libresoc.v:197918.7-197918.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:187757.3-187778.6" - wire width 64 $1\data_r4__msr$next[63:0]$14071 - attribute \src "libresoc.v:187110.14-187110.49" + attribute \src "libresoc.v:198572.3-198593.6" + wire width 64 $1\data_r4__msr$next[63:0]$14361 + attribute \src "libresoc.v:197922.14-197922.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:187757.3-187778.6" - wire $1\data_r4__msr_ok$next[0:0]$14072 - attribute \src "libresoc.v:187114.7-187114.29" + attribute \src "libresoc.v:198572.3-198593.6" + wire $1\data_r4__msr_ok$next[0:0]$14362 + attribute \src "libresoc.v:197926.7-197926.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:187837.3-187846.6" + attribute \src "libresoc.v:198652.3-198661.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:187847.3-187856.6" + attribute \src "libresoc.v:198662.3-198671.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:187857.3-187866.6" + attribute \src "libresoc.v:198672.3-198681.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:187867.3-187876.6" + attribute \src "libresoc.v:198682.3-198691.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:187877.3-187886.6" + attribute \src "libresoc.v:198692.3-198701.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:187606.3-187614.6" - wire $1\opc_l_r_opc$next[0:0]$14004 - attribute \src "libresoc.v:187145.7-187145.25" + attribute \src "libresoc.v:198421.3-198429.6" + wire $1\opc_l_r_opc$next[0:0]$14294 + attribute \src "libresoc.v:197957.7-197957.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187597.3-187605.6" - wire $1\opc_l_s_opc$next[0:0]$14001 - attribute \src "libresoc.v:187149.7-187149.25" + attribute \src "libresoc.v:198412.3-198420.6" + wire $1\opc_l_s_opc$next[0:0]$14291 + attribute \src "libresoc.v:197961.7-197961.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:187887.3-187895.6" - wire width 5 $1\prev_wr_go$next[4:0]$14101 - attribute \src "libresoc.v:187258.13-187258.31" + attribute \src "libresoc.v:198702.3-198710.6" + wire width 5 $1\prev_wr_go$next[4:0]$14391 + attribute \src "libresoc.v:198073.13-198073.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:187551.3-187560.6" + attribute \src "libresoc.v:198366.3-198375.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:187642.3-187650.6" - wire width 5 $1\req_l_r_req$next[4:0]$14016 - attribute \src "libresoc.v:187266.13-187266.32" + attribute \src "libresoc.v:198457.3-198465.6" + wire width 5 $1\req_l_r_req$next[4:0]$14306 + attribute \src "libresoc.v:198081.13-198081.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:187633.3-187641.6" - wire width 5 $1\req_l_s_req$next[4:0]$14013 - attribute \src "libresoc.v:187270.13-187270.32" + attribute \src "libresoc.v:198448.3-198456.6" + wire width 5 $1\req_l_s_req$next[4:0]$14303 + attribute \src "libresoc.v:198085.13-198085.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:187570.3-187578.6" - wire $1\rok_l_r_rdok$next[0:0]$13992 - attribute \src "libresoc.v:187282.7-187282.26" + attribute \src "libresoc.v:198385.3-198393.6" + wire $1\rok_l_r_rdok$next[0:0]$14282 + attribute \src "libresoc.v:198097.7-198097.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187561.3-187569.6" - wire $1\rok_l_s_rdok$next[0:0]$13989 - attribute \src "libresoc.v:187286.7-187286.26" + attribute \src "libresoc.v:198376.3-198384.6" + wire $1\rok_l_s_rdok$next[0:0]$14279 + attribute \src "libresoc.v:198101.7-198101.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187588.3-187596.6" - wire $1\rst_l_r_rst$next[0:0]$13998 - attribute \src "libresoc.v:187290.7-187290.25" + attribute \src "libresoc.v:198403.3-198411.6" + wire $1\rst_l_r_rst$next[0:0]$14288 + attribute \src "libresoc.v:198105.7-198105.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187579.3-187587.6" - wire $1\rst_l_s_rst$next[0:0]$13995 - attribute \src "libresoc.v:187294.7-187294.25" + attribute \src "libresoc.v:198394.3-198402.6" + wire $1\rst_l_s_rst$next[0:0]$14285 + attribute \src "libresoc.v:198109.7-198109.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187624.3-187632.6" - wire width 4 $1\src_l_r_src$next[3:0]$14010 - attribute \src "libresoc.v:187310.13-187310.31" + attribute \src "libresoc.v:198439.3-198447.6" + wire width 4 $1\src_l_r_src$next[3:0]$14300 + attribute \src "libresoc.v:198125.13-198125.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:187615.3-187623.6" - wire width 4 $1\src_l_s_src$next[3:0]$14007 - attribute \src "libresoc.v:187314.13-187314.31" + attribute \src "libresoc.v:198430.3-198438.6" + wire width 4 $1\src_l_s_src$next[3:0]$14297 + attribute \src "libresoc.v:198129.13-198129.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:187779.3-187788.6" - wire width 64 $1\src_r0$next[63:0]$14078 - attribute \src "libresoc.v:187318.14-187318.43" + attribute \src "libresoc.v:198594.3-198603.6" + wire width 64 $1\src_r0$next[63:0]$14368 + attribute \src "libresoc.v:198133.14-198133.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:187789.3-187798.6" - wire width 64 $1\src_r1$next[63:0]$14081 - attribute \src "libresoc.v:187322.14-187322.43" + attribute \src "libresoc.v:198604.3-198613.6" + wire width 64 $1\src_r1$next[63:0]$14371 + attribute \src "libresoc.v:198137.14-198137.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:187799.3-187808.6" - wire width 64 $1\src_r2$next[63:0]$14084 - attribute \src "libresoc.v:187326.14-187326.43" + attribute \src "libresoc.v:198614.3-198623.6" + wire width 64 $1\src_r2$next[63:0]$14374 + attribute \src "libresoc.v:198141.14-198141.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:187809.3-187818.6" - wire width 64 $1\src_r3$next[63:0]$14087 - attribute \src "libresoc.v:187330.14-187330.43" + attribute \src "libresoc.v:198624.3-198633.6" + wire width 64 $1\src_r3$next[63:0]$14377 + attribute \src "libresoc.v:198145.14-198145.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:187669.3-187690.6" - wire width 64 $2\data_r0__o$next[63:0]$14041 - attribute \src "libresoc.v:187669.3-187690.6" - wire $2\data_r0__o_ok$next[0:0]$14042 - attribute \src "libresoc.v:187691.3-187712.6" - wire width 64 $2\data_r1__fast1$next[63:0]$14049 - attribute \src "libresoc.v:187691.3-187712.6" - wire $2\data_r1__fast1_ok$next[0:0]$14050 - attribute \src "libresoc.v:187713.3-187734.6" - wire width 64 $2\data_r2__fast2$next[63:0]$14057 - attribute \src "libresoc.v:187713.3-187734.6" - wire $2\data_r2__fast2_ok$next[0:0]$14058 - attribute \src "libresoc.v:187735.3-187756.6" - wire width 64 $2\data_r3__nia$next[63:0]$14065 - attribute \src "libresoc.v:187735.3-187756.6" - wire $2\data_r3__nia_ok$next[0:0]$14066 - attribute \src "libresoc.v:187757.3-187778.6" - wire width 64 $2\data_r4__msr$next[63:0]$14073 - attribute \src "libresoc.v:187757.3-187778.6" - wire $2\data_r4__msr_ok$next[0:0]$14074 - attribute \src "libresoc.v:187669.3-187690.6" - wire $3\data_r0__o_ok$next[0:0]$14043 - attribute \src "libresoc.v:187691.3-187712.6" - wire $3\data_r1__fast1_ok$next[0:0]$14051 - attribute \src "libresoc.v:187713.3-187734.6" - wire $3\data_r2__fast2_ok$next[0:0]$14059 - attribute \src "libresoc.v:187735.3-187756.6" - wire $3\data_r3__nia_ok$next[0:0]$14067 - attribute \src "libresoc.v:187757.3-187778.6" - wire $3\data_r4__msr_ok$next[0:0]$14075 - attribute \src "libresoc.v:187336.18-187336.112" - wire width 4 $and$libresoc.v:187336$13888_Y - attribute \src "libresoc.v:187337.19-187337.125" - wire $and$libresoc.v:187337$13889_Y - attribute \src "libresoc.v:187338.19-187338.125" - wire $and$libresoc.v:187338$13890_Y - attribute \src "libresoc.v:187339.19-187339.125" - wire $and$libresoc.v:187339$13891_Y - attribute \src "libresoc.v:187340.19-187340.125" - wire $and$libresoc.v:187340$13892_Y - attribute \src "libresoc.v:187341.19-187341.125" - wire $and$libresoc.v:187341$13893_Y - attribute \src "libresoc.v:187342.19-187342.157" - wire width 5 $and$libresoc.v:187342$13894_Y - attribute \src "libresoc.v:187343.19-187343.121" - wire width 5 $and$libresoc.v:187343$13895_Y - attribute \src "libresoc.v:187344.19-187344.127" - wire $and$libresoc.v:187344$13896_Y - attribute \src "libresoc.v:187345.19-187345.127" - wire $and$libresoc.v:187345$13897_Y - attribute \src "libresoc.v:187346.18-187346.110" - wire $and$libresoc.v:187346$13898_Y - attribute \src "libresoc.v:187347.19-187347.127" - wire $and$libresoc.v:187347$13899_Y - attribute \src "libresoc.v:187348.19-187348.127" - wire $and$libresoc.v:187348$13900_Y - attribute \src "libresoc.v:187349.19-187349.127" - wire $and$libresoc.v:187349$13901_Y - attribute \src "libresoc.v:187351.18-187351.98" - wire $and$libresoc.v:187351$13903_Y - attribute \src "libresoc.v:187353.18-187353.100" - wire $and$libresoc.v:187353$13905_Y - attribute \src "libresoc.v:187354.18-187354.171" - wire width 5 $and$libresoc.v:187354$13906_Y - attribute \src "libresoc.v:187356.18-187356.119" - wire width 5 $and$libresoc.v:187356$13908_Y - attribute \src "libresoc.v:187359.18-187359.116" - wire $and$libresoc.v:187359$13911_Y - attribute \src "libresoc.v:187363.17-187363.123" - wire $and$libresoc.v:187363$13915_Y - attribute \src "libresoc.v:187365.18-187365.113" - wire $and$libresoc.v:187365$13917_Y - attribute \src "libresoc.v:187366.18-187366.125" - wire width 5 $and$libresoc.v:187366$13918_Y - attribute \src "libresoc.v:187368.18-187368.112" - wire $and$libresoc.v:187368$13920_Y - attribute \src "libresoc.v:187370.18-187370.127" - wire $and$libresoc.v:187370$13922_Y - attribute \src "libresoc.v:187371.18-187371.127" - wire $and$libresoc.v:187371$13923_Y - attribute \src "libresoc.v:187372.18-187372.117" - wire $and$libresoc.v:187372$13924_Y - attribute \src "libresoc.v:187377.18-187377.131" - wire $and$libresoc.v:187377$13929_Y - attribute \src "libresoc.v:187378.18-187378.124" - wire width 5 $and$libresoc.v:187378$13930_Y - attribute \src "libresoc.v:187381.18-187381.116" - wire $and$libresoc.v:187381$13933_Y - attribute \src "libresoc.v:187382.18-187382.120" - wire $and$libresoc.v:187382$13934_Y - attribute \src "libresoc.v:187383.18-187383.120" - wire $and$libresoc.v:187383$13935_Y - attribute \src "libresoc.v:187384.18-187384.118" - wire $and$libresoc.v:187384$13936_Y - attribute \src "libresoc.v:187385.18-187385.118" - wire $and$libresoc.v:187385$13937_Y - attribute \src "libresoc.v:187391.18-187391.135" - wire $and$libresoc.v:187391$13943_Y - attribute \src "libresoc.v:187392.18-187392.133" - wire $and$libresoc.v:187392$13944_Y - attribute \src "libresoc.v:187393.18-187393.160" - wire width 4 $and$libresoc.v:187393$13945_Y - attribute \src "libresoc.v:187394.18-187394.112" - wire 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\src "libresoc.v:198187.18-198187.117" + wire $and$libresoc.v:198187$14214_Y + attribute \src "libresoc.v:198192.18-198192.131" + wire $and$libresoc.v:198192$14219_Y + attribute \src "libresoc.v:198193.18-198193.124" + wire width 5 $and$libresoc.v:198193$14220_Y + attribute \src "libresoc.v:198196.18-198196.116" + wire $and$libresoc.v:198196$14223_Y + attribute \src "libresoc.v:198197.18-198197.120" + wire $and$libresoc.v:198197$14224_Y + attribute \src "libresoc.v:198198.18-198198.120" + wire $and$libresoc.v:198198$14225_Y + attribute \src "libresoc.v:198199.18-198199.118" + wire $and$libresoc.v:198199$14226_Y + attribute \src "libresoc.v:198200.18-198200.118" + wire $and$libresoc.v:198200$14227_Y + attribute \src "libresoc.v:198206.18-198206.135" + wire $and$libresoc.v:198206$14233_Y + attribute \src "libresoc.v:198207.18-198207.133" + wire $and$libresoc.v:198207$14234_Y + attribute \src "libresoc.v:198208.18-198208.160" + wire width 4 $and$libresoc.v:198208$14235_Y + attribute \src "libresoc.v:198209.18-198209.112" + wire width 4 $and$libresoc.v:198209$14236_Y + attribute \src "libresoc.v:198182.18-198182.113" + wire $eq$libresoc.v:198182$14209_Y + attribute \src "libresoc.v:198184.18-198184.119" + wire $eq$libresoc.v:198184$14211_Y + attribute \src "libresoc.v:198165.18-198165.97" + wire $not$libresoc.v:198165$14192_Y + attribute \src "libresoc.v:198167.18-198167.99" + wire $not$libresoc.v:198167$14194_Y + attribute \src "libresoc.v:198170.18-198170.113" + wire width 5 $not$libresoc.v:198170$14197_Y + attribute \src "libresoc.v:198173.18-198173.106" + wire $not$libresoc.v:198173$14200_Y + attribute \src "libresoc.v:198179.18-198179.121" + wire $not$libresoc.v:198179$14206_Y + attribute \src "libresoc.v:198194.17-198194.113" + wire width 4 $not$libresoc.v:198194$14221_Y + attribute \src "libresoc.v:198210.18-198210.114" + wire width 4 $not$libresoc.v:198210$14237_Y + attribute \src "libresoc.v:198177.18-198177.112" + wire $or$libresoc.v:198177$14204_Y + attribute \src "libresoc.v:198188.18-198188.122" + wire $or$libresoc.v:198188$14215_Y + attribute \src "libresoc.v:198189.18-198189.124" + wire $or$libresoc.v:198189$14216_Y + attribute \src "libresoc.v:198190.18-198190.181" + wire width 5 $or$libresoc.v:198190$14217_Y + attribute \src "libresoc.v:198191.18-198191.168" + wire width 4 $or$libresoc.v:198191$14218_Y + attribute \src "libresoc.v:198195.18-198195.120" + wire width 5 $or$libresoc.v:198195$14222_Y + attribute \src "libresoc.v:198205.17-198205.117" + wire width 4 $or$libresoc.v:198205$14232_Y + attribute \src "libresoc.v:198150.17-198150.104" + wire $reduce_and$libresoc.v:198150$14177_Y + attribute \src "libresoc.v:198172.18-198172.106" + wire $reduce_or$libresoc.v:198172$14199_Y + attribute \src "libresoc.v:198175.18-198175.113" + wire $reduce_or$libresoc.v:198175$14202_Y + attribute \src "libresoc.v:198176.18-198176.112" + wire $reduce_or$libresoc.v:198176$14203_Y + attribute \src "libresoc.v:198201.18-198201.118" + wire width 64 $ternary$libresoc.v:198201$14228_Y + attribute \src "libresoc.v:198202.18-198202.118" + wire width 64 $ternary$libresoc.v:198202$14229_Y + attribute \src "libresoc.v:198203.18-198203.118" + wire width 64 $ternary$libresoc.v:198203$14230_Y + attribute \src "libresoc.v:198204.18-198204.118" + wire width 64 $ternary$libresoc.v:198204$14231_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -393405,13 +413186,13 @@ module \trap0 wire \$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 5 \$21 @@ -393481,13 +413262,13 @@ module \trap0 wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 4 \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$89 @@ -393503,29 +413284,29 @@ module \trap0 wire width 4 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse @@ -393541,17 +413322,17 @@ module \trap0 wire width 64 \alu_trap0_fast2$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_trap0_msr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_trap0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_trap0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_trap0_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_trap0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_trap0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_trap0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_ra @@ -393562,22 +413343,24 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_trap0_trap_op__cia$next attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_trap0_trap_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_trap0_trap_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_trap0_trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_trap0_trap_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_trap0_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -393656,6 +413439,7 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_trap0_trap_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -393680,17 +413464,17 @@ module \trap0 wire width 8 \alu_trap0_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \alu_trap0_trap_op__traptype$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o @@ -393768,7 +413552,7 @@ module \trap0 wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \fast2_ok - attribute \src "libresoc.v:186741.7-186741.15" + attribute \src "libresoc.v:197550.7-197550.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \msr_ok @@ -393776,33 +413560,35 @@ module \trap0 wire output 28 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 6 \oper_i_alu_trap0__cia attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_trap0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" @@ -393879,6 +413665,7 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -393897,15 +413684,15 @@ module \trap0 wire width 5 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset @@ -393913,23 +413700,23 @@ module \trap0 wire width 4 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r @@ -393941,36 +413728,36 @@ module \trap0 wire width 64 input 18 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 19 \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187336$13888 + cell $and $and$libresoc.v:198151$14178 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -393978,10 +413765,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:187336$13888_Y + connect \Y $and$libresoc.v:198151$14178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187337$13889 + cell $and $and$libresoc.v:198152$14179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393989,10 +413776,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187337$13889_Y + connect \Y $and$libresoc.v:198152$14179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187338$13890 + cell $and $and$libresoc.v:198153$14180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394000,10 +413787,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187338$13890_Y + connect \Y $and$libresoc.v:198153$14180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187339$13891 + cell $and $and$libresoc.v:198154$14181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394011,10 +413798,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187339$13891_Y + connect \Y $and$libresoc.v:198154$14181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187340$13892 + cell $and $and$libresoc.v:198155$14182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394022,10 +413809,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187340$13892_Y + connect \Y $and$libresoc.v:198155$14182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187341$13893 + cell $and $and$libresoc.v:198156$14183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394033,10 +413820,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187341$13893_Y + connect \Y $and$libresoc.v:198156$14183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187342$13894 + cell $and $and$libresoc.v:198157$14184 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394044,10 +413831,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:187342$13894_Y + connect \Y $and$libresoc.v:198157$14184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187343$13895 + cell $and $and$libresoc.v:198158$14185 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394055,10 +413842,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187343$13895_Y + connect \Y $and$libresoc.v:198158$14185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187344$13896 + cell $and $and$libresoc.v:198159$14186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394066,10 +413853,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187344$13896_Y + connect \Y $and$libresoc.v:198159$14186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187345$13897 + cell $and $and$libresoc.v:198160$14187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394077,10 +413864,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187345$13897_Y + connect \Y $and$libresoc.v:198160$14187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:187346$13898 + cell $and $and$libresoc.v:198161$14188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394088,10 +413875,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:187346$13898_Y + connect \Y $and$libresoc.v:198161$14188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187347$13899 + cell $and $and$libresoc.v:198162$14189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394099,10 +413886,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187347$13899_Y + connect \Y $and$libresoc.v:198162$14189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187348$13900 + cell $and $and$libresoc.v:198163$14190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394110,10 +413897,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187348$13900_Y + connect \Y $and$libresoc.v:198163$14190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187349$13901 + cell $and $and$libresoc.v:198164$14191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394121,10 +413908,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187349$13901_Y + connect \Y $and$libresoc.v:198164$14191_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:187351$13903 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:198166$14193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394132,10 +413919,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:187351$13903_Y + connect \Y $and$libresoc.v:198166$14193_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:187353$13905 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:198168$14195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394143,10 +413930,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:187353$13905_Y + connect \Y $and$libresoc.v:198168$14195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:187354$13906 + cell $and $and$libresoc.v:198169$14196 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394154,10 +413941,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187354$13906_Y + connect \Y $and$libresoc.v:198169$14196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187356$13908 + cell $and $and$libresoc.v:198171$14198 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394165,10 +413952,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:187356$13908_Y + connect \Y $and$libresoc.v:198171$14198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187359$13911 + cell $and $and$libresoc.v:198174$14201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394176,10 +413963,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:187359$13911_Y + connect \Y $and$libresoc.v:198174$14201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:187363$13915 + cell $and $and$libresoc.v:198178$14205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394187,10 +413974,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:187363$13915_Y + connect \Y $and$libresoc.v:198178$14205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:187365$13917 + cell $and $and$libresoc.v:198180$14207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394198,10 +413985,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:187365$13917_Y + connect \Y $and$libresoc.v:198180$14207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187366$13918 + cell $and $and$libresoc.v:198181$14208 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394209,10 +413996,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187366$13918_Y + connect \Y $and$libresoc.v:198181$14208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187368$13920 + cell $and $and$libresoc.v:198183$14210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394220,10 +414007,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:187368$13920_Y + connect \Y $and$libresoc.v:198183$14210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187370$13922 + cell $and $and$libresoc.v:198185$14212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394231,10 +414018,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:187370$13922_Y + connect \Y $and$libresoc.v:198185$14212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187371$13923 + cell $and $and$libresoc.v:198186$14213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394242,10 +414029,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:187371$13923_Y + connect \Y $and$libresoc.v:198186$14213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187372$13924 + cell $and $and$libresoc.v:198187$14214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394253,10 +414040,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:187372$13924_Y + connect \Y $and$libresoc.v:198187$14214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:187377$13929 + cell $and $and$libresoc.v:198192$14219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394264,10 +414051,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:187377$13929_Y + connect \Y $and$libresoc.v:198192$14219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:187378$13930 + cell $and $and$libresoc.v:198193$14220 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394275,10 +414062,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187378$13930_Y + connect \Y $and$libresoc.v:198193$14220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187381$13933 + cell $and $and$libresoc.v:198196$14223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394286,10 +414073,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187381$13933_Y + connect \Y $and$libresoc.v:198196$14223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187382$13934 + cell $and $and$libresoc.v:198197$14224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394297,10 +414084,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187382$13934_Y + connect \Y $and$libresoc.v:198197$14224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187383$13935 + cell $and $and$libresoc.v:198198$14225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394308,10 +414095,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187383$13935_Y + connect \Y $and$libresoc.v:198198$14225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187384$13936 + cell $and $and$libresoc.v:198199$14226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394319,10 +414106,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187384$13936_Y + connect \Y $and$libresoc.v:198199$14226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187385$13937 + cell $and $and$libresoc.v:198200$14227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394330,10 +414117,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187385$13937_Y + connect \Y $and$libresoc.v:198200$14227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:187391$13943 + cell $and $and$libresoc.v:198206$14233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394341,10 +414128,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:187391$13943_Y + connect \Y $and$libresoc.v:198206$14233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:187392$13944 + cell $and $and$libresoc.v:198207$14234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394352,10 +414139,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:187392$13944_Y + connect \Y $and$libresoc.v:198207$14234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187393$13945 + cell $and $and$libresoc.v:198208$14235 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -394363,10 +414150,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187393$13945_Y + connect \Y $and$libresoc.v:198208$14235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187394$13946 + cell $and $and$libresoc.v:198209$14236 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -394374,10 +414161,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:187394$13946_Y + connect \Y $and$libresoc.v:198209$14236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:187367$13919 + cell $eq $eq$libresoc.v:198182$14209 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394385,10 +414172,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:187367$13919_Y + connect \Y $eq$libresoc.v:198182$14209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:187369$13921 + cell $eq $eq$libresoc.v:198184$14211 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394396,66 +414183,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:187369$13921_Y + connect \Y $eq$libresoc.v:198184$14211_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:187350$13902 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:198165$14192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:187350$13902_Y + connect \Y $not$libresoc.v:198165$14192_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:187352$13904 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:198167$14194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:187352$13904_Y + connect \Y $not$libresoc.v:198167$14194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187355$13907 + cell $not $not$libresoc.v:198170$14197 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:187355$13907_Y + connect \Y $not$libresoc.v:198170$14197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187358$13910 + cell $not $not$libresoc.v:198173$14200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:187358$13910_Y + connect \Y $not$libresoc.v:198173$14200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:187364$13916 + cell $not $not$libresoc.v:198179$14206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:187364$13916_Y + connect \Y $not$libresoc.v:198179$14206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:187379$13931 + cell $not $not$libresoc.v:198194$14221 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:187379$13931_Y + connect \Y $not$libresoc.v:198194$14221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:187395$13947 + cell $not $not$libresoc.v:198210$14237 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:187395$13947_Y + connect \Y $not$libresoc.v:198210$14237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:187362$13914 + cell $or $or$libresoc.v:198177$14204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394463,10 +414250,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:187362$13914_Y + connect \Y $or$libresoc.v:198177$14204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:187373$13925 + cell $or $or$libresoc.v:198188$14215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394474,10 +414261,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187373$13925_Y + connect \Y $or$libresoc.v:198188$14215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:187374$13926 + cell $or $or$libresoc.v:198189$14216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394485,10 +414272,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187374$13926_Y + connect \Y $or$libresoc.v:198189$14216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:187375$13927 + cell $or $or$libresoc.v:198190$14217 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394496,10 +414283,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187375$13927_Y + connect \Y $or$libresoc.v:198190$14217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:187376$13928 + cell $or $or$libresoc.v:198191$14218 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -394507,10 +414294,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187376$13928_Y + connect \Y $or$libresoc.v:198191$14218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:187380$13932 + cell $or $or$libresoc.v:198195$14222 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -394518,10 +414305,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:187380$13932_Y + connect \Y $or$libresoc.v:198195$14222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:187390$13942 + cell $or $or$libresoc.v:198205$14232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -394529,74 +414316,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:187390$13942_Y + connect \Y $or$libresoc.v:198205$14232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:187335$13887 + cell $reduce_and $reduce_and$libresoc.v:198150$14177 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:187335$13887_Y + connect \Y $reduce_and$libresoc.v:198150$14177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:187357$13909 + cell $reduce_or $reduce_or$libresoc.v:198172$14199 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:187357$13909_Y + connect \Y $reduce_or$libresoc.v:198172$14199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187360$13912 + cell $reduce_or $reduce_or$libresoc.v:198175$14202 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:187360$13912_Y + connect \Y $reduce_or$libresoc.v:198175$14202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187361$13913 + cell $reduce_or $reduce_or$libresoc.v:198176$14203 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:187361$13913_Y + connect \Y $reduce_or$libresoc.v:198176$14203_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:187386$13938 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:198201$14228 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:187386$13938_Y + connect \Y $ternary$libresoc.v:198201$14228_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:187387$13939 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:198202$14229 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:187387$13939_Y + connect \Y $ternary$libresoc.v:198202$14229_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:187388$13940 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:198203$14230 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:187388$13940_Y + connect \Y $ternary$libresoc.v:198203$14230_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:187389$13941 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:198204$14231 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:187389$13941_Y + connect \Y $ternary$libresoc.v:198204$14231_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:187472.14-187478.4" + attribute \src "libresoc.v:198287.14-198293.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394605,7 +414392,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:187479.13-187509.4" + attribute \src "libresoc.v:198294.13-198324.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394638,7 +414425,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:187510.15-187516.4" + attribute \src "libresoc.v:198325.15-198331.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394647,7 +414434,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:187517.14-187523.4" + attribute \src "libresoc.v:198332.14-198338.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394656,7 +414443,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:187524.14-187530.4" + attribute \src "libresoc.v:198339.14-198345.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394665,7 +414452,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:187531.14-187537.4" + attribute \src "libresoc.v:198346.14-198352.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394674,7 +414461,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:187538.14-187543.4" + attribute \src "libresoc.v:198353.14-198358.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394682,7 +414469,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:187544.14-187550.4" + attribute \src "libresoc.v:198359.14-198365.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394690,592 +414477,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:186741.7-186741.20" - process $proc$libresoc.v:186741$14102 + attribute \src "libresoc.v:197550.7-197550.20" + process $proc$libresoc.v:197550$14392 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186867.7-186867.24" - process $proc$libresoc.v:186867$14103 + attribute \src "libresoc.v:197676.7-197676.24" + process $proc$libresoc.v:197676$14393 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:186877.7-186877.26" - process $proc$libresoc.v:186877$14104 + attribute \src "libresoc.v:197686.7-197686.26" + process $proc$libresoc.v:197686$14394 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:186885.7-186885.25" - process $proc$libresoc.v:186885$14105 + attribute \src "libresoc.v:197694.7-197694.25" + process $proc$libresoc.v:197694$14395 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:186921.14-186921.59" - process $proc$libresoc.v:186921$14106 + attribute \src "libresoc.v:197730.14-197730.59" + process $proc$libresoc.v:197730$14396 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:186938.14-186938.50" - process $proc$libresoc.v:186938$14107 + attribute \src "libresoc.v:197749.14-197749.51" + process $proc$libresoc.v:197749$14397 assign { } { } - assign $1\alu_trap0_trap_op__fn_unit[11:0] 12'000000000000 + assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[11:0] + update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:186942.14-186942.45" - process $proc$libresoc.v:186942$14108 + attribute \src "libresoc.v:197753.14-197753.45" + process $proc$libresoc.v:197753$14398 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:187020.13-187020.49" - process $proc$libresoc.v:187020$14109 + attribute \src "libresoc.v:197832.13-197832.49" + process $proc$libresoc.v:197832$14399 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:187024.7-187024.41" - process $proc$libresoc.v:187024$14110 + attribute \src "libresoc.v:197836.7-197836.41" + process $proc$libresoc.v:197836$14400 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:187028.13-187028.48" - process $proc$libresoc.v:187028$14111 + attribute \src "libresoc.v:197840.13-197840.48" + process $proc$libresoc.v:197840$14401 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:187032.14-187032.59" - process $proc$libresoc.v:187032$14112 + attribute \src "libresoc.v:197844.14-197844.59" + process $proc$libresoc.v:197844$14402 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:187036.14-187036.52" - process $proc$libresoc.v:187036$14113 + attribute \src "libresoc.v:197848.14-197848.52" + process $proc$libresoc.v:197848$14403 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:187040.13-187040.48" - process $proc$libresoc.v:187040$14114 + attribute \src "libresoc.v:197852.13-197852.48" + process $proc$libresoc.v:197852$14404 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:187046.7-187046.27" - process $proc$libresoc.v:187046$14115 + attribute \src "libresoc.v:197858.7-197858.27" + process $proc$libresoc.v:197858$14405 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187078.14-187078.47" - process $proc$libresoc.v:187078$14116 + attribute \src "libresoc.v:197890.14-197890.47" + process $proc$libresoc.v:197890$14406 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:187082.7-187082.27" - process $proc$libresoc.v:187082$14117 + attribute \src "libresoc.v:197894.7-197894.27" + process $proc$libresoc.v:197894$14407 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187086.14-187086.51" - process $proc$libresoc.v:187086$14118 + attribute \src "libresoc.v:197898.14-197898.51" + process $proc$libresoc.v:197898$14408 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:187090.7-187090.31" - process $proc$libresoc.v:187090$14119 + attribute \src "libresoc.v:197902.7-197902.31" + process $proc$libresoc.v:197902$14409 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:187094.14-187094.51" - process $proc$libresoc.v:187094$14120 + attribute \src "libresoc.v:197906.14-197906.51" + process $proc$libresoc.v:197906$14410 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:187098.7-187098.31" - process $proc$libresoc.v:187098$14121 + attribute \src "libresoc.v:197910.7-197910.31" + process $proc$libresoc.v:197910$14411 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:187102.14-187102.49" - process $proc$libresoc.v:187102$14122 + attribute \src "libresoc.v:197914.14-197914.49" + process $proc$libresoc.v:197914$14412 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:187106.7-187106.29" - process $proc$libresoc.v:187106$14123 + attribute \src "libresoc.v:197918.7-197918.29" + process $proc$libresoc.v:197918$14413 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:187110.14-187110.49" - process $proc$libresoc.v:187110$14124 + attribute \src "libresoc.v:197922.14-197922.49" + process $proc$libresoc.v:197922$14414 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:187114.7-187114.29" - process $proc$libresoc.v:187114$14125 + attribute \src "libresoc.v:197926.7-197926.29" + process $proc$libresoc.v:197926$14415 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:187145.7-187145.25" - process $proc$libresoc.v:187145$14126 + attribute \src "libresoc.v:197957.7-197957.25" + process $proc$libresoc.v:197957$14416 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187149.7-187149.25" - process $proc$libresoc.v:187149$14127 + attribute \src "libresoc.v:197961.7-197961.25" + process $proc$libresoc.v:197961$14417 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187258.13-187258.31" - process $proc$libresoc.v:187258$14128 + attribute \src "libresoc.v:198073.13-198073.31" + process $proc$libresoc.v:198073$14418 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:187266.13-187266.32" - process $proc$libresoc.v:187266$14129 + attribute \src "libresoc.v:198081.13-198081.32" + process $proc$libresoc.v:198081$14419 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:187270.13-187270.32" - process $proc$libresoc.v:187270$14130 + attribute \src "libresoc.v:198085.13-198085.32" + process $proc$libresoc.v:198085$14420 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:187282.7-187282.26" - process $proc$libresoc.v:187282$14131 + attribute \src "libresoc.v:198097.7-198097.26" + process $proc$libresoc.v:198097$14421 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187286.7-187286.26" - process $proc$libresoc.v:187286$14132 + attribute \src "libresoc.v:198101.7-198101.26" + process $proc$libresoc.v:198101$14422 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187290.7-187290.25" - process $proc$libresoc.v:187290$14133 + attribute \src "libresoc.v:198105.7-198105.25" + process $proc$libresoc.v:198105$14423 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187294.7-187294.25" - process $proc$libresoc.v:187294$14134 + attribute \src "libresoc.v:198109.7-198109.25" + process $proc$libresoc.v:198109$14424 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187310.13-187310.31" - process $proc$libresoc.v:187310$14135 + attribute \src "libresoc.v:198125.13-198125.31" + process $proc$libresoc.v:198125$14425 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:187314.13-187314.31" - process $proc$libresoc.v:187314$14136 + attribute \src "libresoc.v:198129.13-198129.31" + process $proc$libresoc.v:198129$14426 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:187318.14-187318.43" - process $proc$libresoc.v:187318$14137 + attribute \src "libresoc.v:198133.14-198133.43" + process $proc$libresoc.v:198133$14427 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:187322.14-187322.43" - process $proc$libresoc.v:187322$14138 + attribute \src "libresoc.v:198137.14-198137.43" + process $proc$libresoc.v:198137$14428 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:187326.14-187326.43" - process $proc$libresoc.v:187326$14139 + attribute \src "libresoc.v:198141.14-198141.43" + process $proc$libresoc.v:198141$14429 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:187330.14-187330.43" - process $proc$libresoc.v:187330$14140 + attribute \src "libresoc.v:198145.14-198145.43" + process $proc$libresoc.v:198145$14430 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:187396.3-187397.39" - process $proc$libresoc.v:187396$13948 + attribute \src "libresoc.v:198211.3-198212.39" + process $proc$libresoc.v:198211$14238 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187398.3-187399.43" - process $proc$libresoc.v:187398$13949 + attribute \src "libresoc.v:198213.3-198214.43" + process $proc$libresoc.v:198213$14239 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187400.3-187401.29" - process $proc$libresoc.v:187400$13950 + attribute \src "libresoc.v:198215.3-198216.29" + process $proc$libresoc.v:198215$14240 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:187402.3-187403.29" - process $proc$libresoc.v:187402$13951 + attribute \src "libresoc.v:198217.3-198218.29" + process $proc$libresoc.v:198217$14241 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:187404.3-187405.29" - process $proc$libresoc.v:187404$13952 + attribute \src "libresoc.v:198219.3-198220.29" + process $proc$libresoc.v:198219$14242 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:187406.3-187407.29" - process $proc$libresoc.v:187406$13953 + attribute \src "libresoc.v:198221.3-198222.29" + process $proc$libresoc.v:198221$14243 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:187408.3-187409.41" - process $proc$libresoc.v:187408$13954 + attribute \src "libresoc.v:198223.3-198224.41" + process $proc$libresoc.v:198223$14244 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:187410.3-187411.47" - process $proc$libresoc.v:187410$13955 + attribute \src "libresoc.v:198225.3-198226.47" + process $proc$libresoc.v:198225$14245 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:187412.3-187413.41" - process $proc$libresoc.v:187412$13956 + attribute \src "libresoc.v:198227.3-198228.41" + process $proc$libresoc.v:198227$14246 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:187414.3-187415.47" - process $proc$libresoc.v:187414$13957 + attribute \src "libresoc.v:198229.3-198230.47" + process $proc$libresoc.v:198229$14247 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:187416.3-187417.45" - process $proc$libresoc.v:187416$13958 + attribute \src "libresoc.v:198231.3-198232.45" + process $proc$libresoc.v:198231$14248 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:187418.3-187419.51" - process $proc$libresoc.v:187418$13959 + attribute \src "libresoc.v:198233.3-198234.51" + process $proc$libresoc.v:198233$14249 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:187420.3-187421.45" - process $proc$libresoc.v:187420$13960 + attribute \src "libresoc.v:198235.3-198236.45" + process $proc$libresoc.v:198235$14250 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:187422.3-187423.51" - process $proc$libresoc.v:187422$13961 + attribute \src "libresoc.v:198237.3-198238.51" + process $proc$libresoc.v:198237$14251 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:187424.3-187425.37" - process $proc$libresoc.v:187424$13962 + attribute \src "libresoc.v:198239.3-198240.37" + process $proc$libresoc.v:198239$14252 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:187426.3-187427.43" - process $proc$libresoc.v:187426$13963 + attribute \src "libresoc.v:198241.3-198242.43" + process $proc$libresoc.v:198241$14253 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187428.3-187429.73" - process $proc$libresoc.v:187428$13964 + attribute \src "libresoc.v:198243.3-198244.73" + process $proc$libresoc.v:198243$14254 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:187430.3-187431.69" - process $proc$libresoc.v:187430$13965 + attribute \src "libresoc.v:198245.3-198246.69" + process $proc$libresoc.v:198245$14255 assign { } { } - assign $0\alu_trap0_trap_op__fn_unit[11:0] \alu_trap0_trap_op__fn_unit$next + assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk - update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[11:0] + update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:187432.3-187433.63" - process $proc$libresoc.v:187432$13966 + attribute \src "libresoc.v:198247.3-198248.63" + process $proc$libresoc.v:198247$14256 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:187434.3-187435.61" - process $proc$libresoc.v:187434$13967 + attribute \src "libresoc.v:198249.3-198250.61" + process $proc$libresoc.v:198249$14257 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:187436.3-187437.61" - process $proc$libresoc.v:187436$13968 + attribute \src "libresoc.v:198251.3-198252.61" + process $proc$libresoc.v:198251$14258 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:187438.3-187439.71" - process $proc$libresoc.v:187438$13969 + attribute \src "libresoc.v:198253.3-198254.71" + process $proc$libresoc.v:198253$14259 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:187440.3-187441.71" - process $proc$libresoc.v:187440$13970 + attribute \src "libresoc.v:198255.3-198256.71" + process $proc$libresoc.v:198255$14260 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:187442.3-187443.71" - process $proc$libresoc.v:187442$13971 + attribute \src "libresoc.v:198257.3-198258.71" + process $proc$libresoc.v:198257$14261 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:187444.3-187445.71" - process $proc$libresoc.v:187444$13972 + attribute \src "libresoc.v:198259.3-198260.71" + process $proc$libresoc.v:198259$14262 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:187446.3-187447.39" - process $proc$libresoc.v:187446$13973 + attribute \src "libresoc.v:198261.3-198262.39" + process $proc$libresoc.v:198261$14263 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:187448.3-187449.39" - process $proc$libresoc.v:187448$13974 + attribute \src "libresoc.v:198263.3-198264.39" + process $proc$libresoc.v:198263$14264 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:187450.3-187451.39" - process $proc$libresoc.v:187450$13975 + attribute \src "libresoc.v:198265.3-198266.39" + process $proc$libresoc.v:198265$14265 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:187452.3-187453.39" - process $proc$libresoc.v:187452$13976 + attribute \src "libresoc.v:198267.3-198268.39" + process $proc$libresoc.v:198267$14266 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:187454.3-187455.39" - process $proc$libresoc.v:187454$13977 + attribute \src "libresoc.v:198269.3-198270.39" + process $proc$libresoc.v:198269$14267 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187456.3-187457.39" - process $proc$libresoc.v:187456$13978 + attribute \src "libresoc.v:198271.3-198272.39" + process $proc$libresoc.v:198271$14268 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187458.3-187459.39" - process $proc$libresoc.v:187458$13979 + attribute \src "libresoc.v:198273.3-198274.39" + process $proc$libresoc.v:198273$14269 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187460.3-187461.39" - process $proc$libresoc.v:187460$13980 + attribute \src "libresoc.v:198275.3-198276.39" + process $proc$libresoc.v:198275$14270 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187462.3-187463.41" - process $proc$libresoc.v:187462$13981 + attribute \src "libresoc.v:198277.3-198278.41" + process $proc$libresoc.v:198277$14271 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187464.3-187465.41" - process $proc$libresoc.v:187464$13982 + attribute \src "libresoc.v:198279.3-198280.41" + process $proc$libresoc.v:198279$14272 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187466.3-187467.37" - process $proc$libresoc.v:187466$13983 + attribute \src "libresoc.v:198281.3-198282.37" + process $proc$libresoc.v:198281$14273 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:187468.3-187469.41" - process $proc$libresoc.v:187468$13984 + attribute \src "libresoc.v:198283.3-198284.41" + process $proc$libresoc.v:198283$14274 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:187470.3-187471.25" - process $proc$libresoc.v:187470$13985 + attribute \src "libresoc.v:198285.3-198286.25" + process $proc$libresoc.v:198285$14275 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:187551.3-187560.6" - process $proc$libresoc.v:187551$13986 + attribute \src "libresoc.v:198366.3-198375.6" + process $proc$libresoc.v:198366$14276 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:187552.5-187552.29" + attribute \src "libresoc.v:198367.5-198367.29" switch \initial - attribute \src "libresoc.v:187552.9-187552.17" + attribute \src "libresoc.v:198367.9-198367.17" case 1'1 case end @@ -395291,14 +415078,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:187561.3-187569.6" - process $proc$libresoc.v:187561$13987 + attribute \src "libresoc.v:198376.3-198384.6" + process $proc$libresoc.v:198376$14277 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$13988 $1\rok_l_s_rdok$next[0:0]$13989 - attribute \src "libresoc.v:187562.5-187562.29" + assign $0\rok_l_s_rdok$next[0:0]$14278 $1\rok_l_s_rdok$next[0:0]$14279 + attribute \src "libresoc.v:198377.5-198377.29" switch \initial - attribute \src "libresoc.v:187562.9-187562.17" + attribute \src "libresoc.v:198377.9-198377.17" case 1'1 case end @@ -395307,21 +415094,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$13989 1'0 + assign $1\rok_l_s_rdok$next[0:0]$14279 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$13989 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$14279 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13988 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14278 end - attribute \src "libresoc.v:187570.3-187578.6" - process $proc$libresoc.v:187570$13990 + attribute \src "libresoc.v:198385.3-198393.6" + process $proc$libresoc.v:198385$14280 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$13991 $1\rok_l_r_rdok$next[0:0]$13992 - attribute \src "libresoc.v:187571.5-187571.29" + assign $0\rok_l_r_rdok$next[0:0]$14281 $1\rok_l_r_rdok$next[0:0]$14282 + attribute \src "libresoc.v:198386.5-198386.29" switch \initial - attribute \src "libresoc.v:187571.9-187571.17" + attribute \src "libresoc.v:198386.9-198386.17" case 1'1 case end @@ -395330,21 +415117,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$13992 1'1 + assign $1\rok_l_r_rdok$next[0:0]$14282 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$13992 \$65 + assign $1\rok_l_r_rdok$next[0:0]$14282 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13991 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14281 end - attribute \src "libresoc.v:187579.3-187587.6" - process $proc$libresoc.v:187579$13993 + attribute \src "libresoc.v:198394.3-198402.6" + process $proc$libresoc.v:198394$14283 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$13994 $1\rst_l_s_rst$next[0:0]$13995 - attribute \src "libresoc.v:187580.5-187580.29" + assign $0\rst_l_s_rst$next[0:0]$14284 $1\rst_l_s_rst$next[0:0]$14285 + attribute \src "libresoc.v:198395.5-198395.29" switch \initial - attribute \src "libresoc.v:187580.9-187580.17" + attribute \src "libresoc.v:198395.9-198395.17" case 1'1 case end @@ -395353,21 +415140,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$13995 1'0 + assign $1\rst_l_s_rst$next[0:0]$14285 1'0 case - assign $1\rst_l_s_rst$next[0:0]$13995 \all_rd + assign $1\rst_l_s_rst$next[0:0]$14285 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13994 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14284 end - attribute \src "libresoc.v:187588.3-187596.6" - process $proc$libresoc.v:187588$13996 + attribute \src "libresoc.v:198403.3-198411.6" + process $proc$libresoc.v:198403$14286 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$13997 $1\rst_l_r_rst$next[0:0]$13998 - attribute \src "libresoc.v:187589.5-187589.29" + assign $0\rst_l_r_rst$next[0:0]$14287 $1\rst_l_r_rst$next[0:0]$14288 + attribute \src "libresoc.v:198404.5-198404.29" switch \initial - attribute \src "libresoc.v:187589.9-187589.17" + attribute \src "libresoc.v:198404.9-198404.17" case 1'1 case end @@ -395376,21 +415163,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$13998 1'1 + assign $1\rst_l_r_rst$next[0:0]$14288 1'1 case - assign $1\rst_l_r_rst$next[0:0]$13998 \rst_r + assign $1\rst_l_r_rst$next[0:0]$14288 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13997 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14287 end - attribute \src "libresoc.v:187597.3-187605.6" - process $proc$libresoc.v:187597$13999 + attribute \src "libresoc.v:198412.3-198420.6" + process $proc$libresoc.v:198412$14289 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14000 $1\opc_l_s_opc$next[0:0]$14001 - attribute \src "libresoc.v:187598.5-187598.29" + assign $0\opc_l_s_opc$next[0:0]$14290 $1\opc_l_s_opc$next[0:0]$14291 + attribute \src "libresoc.v:198413.5-198413.29" switch \initial - attribute \src "libresoc.v:187598.9-187598.17" + attribute \src "libresoc.v:198413.9-198413.17" case 1'1 case end @@ -395399,21 +415186,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14001 1'0 + assign $1\opc_l_s_opc$next[0:0]$14291 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14001 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$14291 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14000 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14290 end - attribute \src "libresoc.v:187606.3-187614.6" - process $proc$libresoc.v:187606$14002 + attribute \src "libresoc.v:198421.3-198429.6" + process $proc$libresoc.v:198421$14292 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14003 $1\opc_l_r_opc$next[0:0]$14004 - attribute \src "libresoc.v:187607.5-187607.29" + assign $0\opc_l_r_opc$next[0:0]$14293 $1\opc_l_r_opc$next[0:0]$14294 + attribute \src "libresoc.v:198422.5-198422.29" switch \initial - attribute \src "libresoc.v:187607.9-187607.17" + attribute \src "libresoc.v:198422.9-198422.17" case 1'1 case end @@ -395422,21 +415209,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14004 1'1 + assign $1\opc_l_r_opc$next[0:0]$14294 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14004 \req_done + assign $1\opc_l_r_opc$next[0:0]$14294 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14003 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14293 end - attribute \src "libresoc.v:187615.3-187623.6" - process $proc$libresoc.v:187615$14005 + attribute \src "libresoc.v:198430.3-198438.6" + process $proc$libresoc.v:198430$14295 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14006 $1\src_l_s_src$next[3:0]$14007 - attribute \src "libresoc.v:187616.5-187616.29" + assign $0\src_l_s_src$next[3:0]$14296 $1\src_l_s_src$next[3:0]$14297 + attribute \src "libresoc.v:198431.5-198431.29" switch \initial - attribute \src "libresoc.v:187616.9-187616.17" + attribute \src "libresoc.v:198431.9-198431.17" case 1'1 case end @@ -395445,21 +415232,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14007 4'0000 + assign $1\src_l_s_src$next[3:0]$14297 4'0000 case - assign $1\src_l_s_src$next[3:0]$14007 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14297 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14006 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14296 end - attribute \src "libresoc.v:187624.3-187632.6" - process $proc$libresoc.v:187624$14008 + attribute \src "libresoc.v:198439.3-198447.6" + process $proc$libresoc.v:198439$14298 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14009 $1\src_l_r_src$next[3:0]$14010 - attribute \src "libresoc.v:187625.5-187625.29" + assign $0\src_l_r_src$next[3:0]$14299 $1\src_l_r_src$next[3:0]$14300 + attribute \src "libresoc.v:198440.5-198440.29" switch \initial - attribute \src "libresoc.v:187625.9-187625.17" + attribute \src "libresoc.v:198440.9-198440.17" case 1'1 case end @@ -395468,21 +415255,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14010 4'1111 + assign $1\src_l_r_src$next[3:0]$14300 4'1111 case - assign $1\src_l_r_src$next[3:0]$14010 \reset_r + assign $1\src_l_r_src$next[3:0]$14300 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14009 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14299 end - attribute \src "libresoc.v:187633.3-187641.6" - process $proc$libresoc.v:187633$14011 + attribute \src "libresoc.v:198448.3-198456.6" + process $proc$libresoc.v:198448$14301 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14012 $1\req_l_s_req$next[4:0]$14013 - attribute \src "libresoc.v:187634.5-187634.29" + assign $0\req_l_s_req$next[4:0]$14302 $1\req_l_s_req$next[4:0]$14303 + attribute \src "libresoc.v:198449.5-198449.29" switch \initial - attribute \src "libresoc.v:187634.9-187634.17" + attribute \src "libresoc.v:198449.9-198449.17" case 1'1 case end @@ -395491,21 +415278,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14013 5'00000 + assign $1\req_l_s_req$next[4:0]$14303 5'00000 case - assign $1\req_l_s_req$next[4:0]$14013 \$67 + assign $1\req_l_s_req$next[4:0]$14303 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14012 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14302 end - attribute \src "libresoc.v:187642.3-187650.6" - process $proc$libresoc.v:187642$14014 + attribute \src "libresoc.v:198457.3-198465.6" + process $proc$libresoc.v:198457$14304 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14015 $1\req_l_r_req$next[4:0]$14016 - attribute \src "libresoc.v:187643.5-187643.29" + assign $0\req_l_r_req$next[4:0]$14305 $1\req_l_r_req$next[4:0]$14306 + attribute \src "libresoc.v:198458.5-198458.29" switch \initial - attribute \src "libresoc.v:187643.9-187643.17" + attribute \src "libresoc.v:198458.9-198458.17" case 1'1 case end @@ -395514,15 +415301,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14016 5'11111 + assign $1\req_l_r_req$next[4:0]$14306 5'11111 case - assign $1\req_l_r_req$next[4:0]$14016 \$69 + assign $1\req_l_r_req$next[4:0]$14306 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14015 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14305 end - attribute \src "libresoc.v:187651.3-187668.6" - process $proc$libresoc.v:187651$14017 + attribute \src "libresoc.v:198466.3-198483.6" + process $proc$libresoc.v:198466$14307 assign { } { } assign { } { } assign { } { } @@ -395541,18 +415328,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14018 $1\alu_trap0_trap_op__cia$next[63:0]$14027 - assign $0\alu_trap0_trap_op__fn_unit$next[11:0]$14019 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14028 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14020 $1\alu_trap0_trap_op__insn$next[31:0]$14029 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14021 $1\alu_trap0_trap_op__insn_type$next[6:0]$14030 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14022 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14031 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14023 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14032 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14024 $1\alu_trap0_trap_op__msr$next[63:0]$14033 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14025 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14034 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14026 $1\alu_trap0_trap_op__traptype$next[7:0]$14035 - attribute \src "libresoc.v:187652.5-187652.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$14308 $1\alu_trap0_trap_op__cia$next[63:0]$14317 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14310 $1\alu_trap0_trap_op__insn$next[31:0]$14319 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14314 $1\alu_trap0_trap_op__msr$next[63:0]$14323 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14316 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 + attribute \src "libresoc.v:198467.5-198467.29" switch \initial - attribute \src "libresoc.v:187652.9-187652.17" + attribute \src "libresoc.v:198467.9-198467.17" case 1'1 case end @@ -395569,43 +415356,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14032 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14034 $1\alu_trap0_trap_op__traptype$next[7:0]$14035 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14031 $1\alu_trap0_trap_op__cia$next[63:0]$14027 $1\alu_trap0_trap_op__msr$next[63:0]$14033 $1\alu_trap0_trap_op__insn$next[31:0]$14029 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14028 $1\alu_trap0_trap_op__insn_type$next[6:0]$14030 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 $1\alu_trap0_trap_op__cia$next[63:0]$14317 $1\alu_trap0_trap_op__msr$next[63:0]$14323 $1\alu_trap0_trap_op__insn$next[31:0]$14319 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14027 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[11:0]$14028 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14029 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14030 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14031 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14032 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14033 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14034 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14035 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14317 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14319 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14323 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14325 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14018 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[11:0]$14019 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14020 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14021 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14022 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14023 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14024 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14025 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14026 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14308 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14310 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14314 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14316 end - attribute \src "libresoc.v:187669.3-187690.6" - process $proc$libresoc.v:187669$14036 + attribute \src "libresoc.v:198484.3-198505.6" + process $proc$libresoc.v:198484$14326 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14037 $2\data_r0__o$next[63:0]$14041 + assign $0\data_r0__o$next[63:0]$14327 $2\data_r0__o$next[63:0]$14331 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14038 $3\data_r0__o_ok$next[0:0]$14043 - attribute \src "libresoc.v:187670.5-187670.29" + assign $0\data_r0__o_ok$next[0:0]$14328 $3\data_r0__o_ok$next[0:0]$14333 + attribute \src "libresoc.v:198485.5-198485.29" switch \initial - attribute \src "libresoc.v:187670.9-187670.17" + attribute \src "libresoc.v:198485.9-198485.17" case 1'1 case end @@ -395615,10 +415402,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14040 $1\data_r0__o$next[63:0]$14039 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14330 $1\data_r0__o$next[63:0]$14329 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14039 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14040 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14329 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14330 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395626,38 +415413,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14042 $2\data_r0__o$next[63:0]$14041 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14332 $2\data_r0__o$next[63:0]$14331 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14041 $1\data_r0__o$next[63:0]$14039 - assign $2\data_r0__o_ok$next[0:0]$14042 $1\data_r0__o_ok$next[0:0]$14040 + assign $2\data_r0__o$next[63:0]$14331 $1\data_r0__o$next[63:0]$14329 + assign $2\data_r0__o_ok$next[0:0]$14332 $1\data_r0__o_ok$next[0:0]$14330 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14043 1'0 + assign $3\data_r0__o_ok$next[0:0]$14333 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14043 $2\data_r0__o_ok$next[0:0]$14042 + assign $3\data_r0__o_ok$next[0:0]$14333 $2\data_r0__o_ok$next[0:0]$14332 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14037 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14038 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14327 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14328 end - attribute \src "libresoc.v:187691.3-187712.6" - process $proc$libresoc.v:187691$14044 + attribute \src "libresoc.v:198506.3-198527.6" + process $proc$libresoc.v:198506$14334 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14045 $2\data_r1__fast1$next[63:0]$14049 + assign $0\data_r1__fast1$next[63:0]$14335 $2\data_r1__fast1$next[63:0]$14339 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14046 $3\data_r1__fast1_ok$next[0:0]$14051 - attribute \src "libresoc.v:187692.5-187692.29" + assign $0\data_r1__fast1_ok$next[0:0]$14336 $3\data_r1__fast1_ok$next[0:0]$14341 + attribute \src "libresoc.v:198507.5-198507.29" switch \initial - attribute \src "libresoc.v:187692.9-187692.17" + attribute \src "libresoc.v:198507.9-198507.17" case 1'1 case end @@ -395667,10 +415454,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14048 $1\data_r1__fast1$next[63:0]$14047 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14338 $1\data_r1__fast1$next[63:0]$14337 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14047 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14048 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14337 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14338 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395678,38 +415465,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14050 $2\data_r1__fast1$next[63:0]$14049 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14340 $2\data_r1__fast1$next[63:0]$14339 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14049 $1\data_r1__fast1$next[63:0]$14047 - assign $2\data_r1__fast1_ok$next[0:0]$14050 $1\data_r1__fast1_ok$next[0:0]$14048 + assign $2\data_r1__fast1$next[63:0]$14339 $1\data_r1__fast1$next[63:0]$14337 + assign $2\data_r1__fast1_ok$next[0:0]$14340 $1\data_r1__fast1_ok$next[0:0]$14338 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14051 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14341 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14051 $2\data_r1__fast1_ok$next[0:0]$14050 + assign $3\data_r1__fast1_ok$next[0:0]$14341 $2\data_r1__fast1_ok$next[0:0]$14340 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14045 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14046 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14335 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14336 end - attribute \src "libresoc.v:187713.3-187734.6" - process $proc$libresoc.v:187713$14052 + attribute \src "libresoc.v:198528.3-198549.6" + process $proc$libresoc.v:198528$14342 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14053 $2\data_r2__fast2$next[63:0]$14057 + assign $0\data_r2__fast2$next[63:0]$14343 $2\data_r2__fast2$next[63:0]$14347 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14054 $3\data_r2__fast2_ok$next[0:0]$14059 - attribute \src "libresoc.v:187714.5-187714.29" + assign $0\data_r2__fast2_ok$next[0:0]$14344 $3\data_r2__fast2_ok$next[0:0]$14349 + attribute \src "libresoc.v:198529.5-198529.29" switch \initial - attribute \src "libresoc.v:187714.9-187714.17" + attribute \src "libresoc.v:198529.9-198529.17" case 1'1 case end @@ -395719,10 +415506,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14056 $1\data_r2__fast2$next[63:0]$14055 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14346 $1\data_r2__fast2$next[63:0]$14345 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14055 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14056 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14345 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14346 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395730,38 +415517,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14058 $2\data_r2__fast2$next[63:0]$14057 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14348 $2\data_r2__fast2$next[63:0]$14347 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14057 $1\data_r2__fast2$next[63:0]$14055 - assign $2\data_r2__fast2_ok$next[0:0]$14058 $1\data_r2__fast2_ok$next[0:0]$14056 + assign $2\data_r2__fast2$next[63:0]$14347 $1\data_r2__fast2$next[63:0]$14345 + assign $2\data_r2__fast2_ok$next[0:0]$14348 $1\data_r2__fast2_ok$next[0:0]$14346 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14059 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14349 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14059 $2\data_r2__fast2_ok$next[0:0]$14058 + assign $3\data_r2__fast2_ok$next[0:0]$14349 $2\data_r2__fast2_ok$next[0:0]$14348 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14053 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14054 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14343 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14344 end - attribute \src "libresoc.v:187735.3-187756.6" - process $proc$libresoc.v:187735$14060 + attribute \src "libresoc.v:198550.3-198571.6" + process $proc$libresoc.v:198550$14350 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14061 $2\data_r3__nia$next[63:0]$14065 + assign $0\data_r3__nia$next[63:0]$14351 $2\data_r3__nia$next[63:0]$14355 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14062 $3\data_r3__nia_ok$next[0:0]$14067 - attribute \src "libresoc.v:187736.5-187736.29" + assign $0\data_r3__nia_ok$next[0:0]$14352 $3\data_r3__nia_ok$next[0:0]$14357 + attribute \src "libresoc.v:198551.5-198551.29" switch \initial - attribute \src "libresoc.v:187736.9-187736.17" + attribute \src "libresoc.v:198551.9-198551.17" case 1'1 case end @@ -395771,10 +415558,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14064 $1\data_r3__nia$next[63:0]$14063 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14354 $1\data_r3__nia$next[63:0]$14353 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14063 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14064 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14353 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14354 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395782,38 +415569,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14066 $2\data_r3__nia$next[63:0]$14065 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14356 $2\data_r3__nia$next[63:0]$14355 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14065 $1\data_r3__nia$next[63:0]$14063 - assign $2\data_r3__nia_ok$next[0:0]$14066 $1\data_r3__nia_ok$next[0:0]$14064 + assign $2\data_r3__nia$next[63:0]$14355 $1\data_r3__nia$next[63:0]$14353 + assign $2\data_r3__nia_ok$next[0:0]$14356 $1\data_r3__nia_ok$next[0:0]$14354 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14067 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14357 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14067 $2\data_r3__nia_ok$next[0:0]$14066 + assign $3\data_r3__nia_ok$next[0:0]$14357 $2\data_r3__nia_ok$next[0:0]$14356 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14061 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14062 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14351 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14352 end - attribute \src "libresoc.v:187757.3-187778.6" - process $proc$libresoc.v:187757$14068 + attribute \src "libresoc.v:198572.3-198593.6" + process $proc$libresoc.v:198572$14358 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14069 $2\data_r4__msr$next[63:0]$14073 + assign $0\data_r4__msr$next[63:0]$14359 $2\data_r4__msr$next[63:0]$14363 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14070 $3\data_r4__msr_ok$next[0:0]$14075 - attribute \src "libresoc.v:187758.5-187758.29" + assign $0\data_r4__msr_ok$next[0:0]$14360 $3\data_r4__msr_ok$next[0:0]$14365 + attribute \src "libresoc.v:198573.5-198573.29" switch \initial - attribute \src "libresoc.v:187758.9-187758.17" + attribute \src "libresoc.v:198573.9-198573.17" case 1'1 case end @@ -395823,10 +415610,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14072 $1\data_r4__msr$next[63:0]$14071 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14362 $1\data_r4__msr$next[63:0]$14361 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14071 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14072 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14361 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14362 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395834,124 +415621,124 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14074 $2\data_r4__msr$next[63:0]$14073 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14364 $2\data_r4__msr$next[63:0]$14363 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14073 $1\data_r4__msr$next[63:0]$14071 - assign $2\data_r4__msr_ok$next[0:0]$14074 $1\data_r4__msr_ok$next[0:0]$14072 + assign $2\data_r4__msr$next[63:0]$14363 $1\data_r4__msr$next[63:0]$14361 + assign $2\data_r4__msr_ok$next[0:0]$14364 $1\data_r4__msr_ok$next[0:0]$14362 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14075 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14365 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14075 $2\data_r4__msr_ok$next[0:0]$14074 + assign $3\data_r4__msr_ok$next[0:0]$14365 $2\data_r4__msr_ok$next[0:0]$14364 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14069 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14070 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14359 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14360 end - attribute \src "libresoc.v:187779.3-187788.6" - process $proc$libresoc.v:187779$14076 + attribute \src "libresoc.v:198594.3-198603.6" + process $proc$libresoc.v:198594$14366 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14077 $1\src_r0$next[63:0]$14078 - attribute \src "libresoc.v:187780.5-187780.29" + assign $0\src_r0$next[63:0]$14367 $1\src_r0$next[63:0]$14368 + attribute \src "libresoc.v:198595.5-198595.29" switch \initial - attribute \src "libresoc.v:187780.9-187780.17" + attribute \src "libresoc.v:198595.9-198595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14078 \src1_i + assign $1\src_r0$next[63:0]$14368 \src1_i case - assign $1\src_r0$next[63:0]$14078 \src_r0 + assign $1\src_r0$next[63:0]$14368 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14077 + update \src_r0$next $0\src_r0$next[63:0]$14367 end - attribute \src "libresoc.v:187789.3-187798.6" - process $proc$libresoc.v:187789$14079 + attribute \src "libresoc.v:198604.3-198613.6" + process $proc$libresoc.v:198604$14369 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14080 $1\src_r1$next[63:0]$14081 - attribute \src "libresoc.v:187790.5-187790.29" + assign $0\src_r1$next[63:0]$14370 $1\src_r1$next[63:0]$14371 + attribute \src "libresoc.v:198605.5-198605.29" switch \initial - attribute \src "libresoc.v:187790.9-187790.17" + attribute \src "libresoc.v:198605.9-198605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14081 \src2_i + assign $1\src_r1$next[63:0]$14371 \src2_i case - assign $1\src_r1$next[63:0]$14081 \src_r1 + assign $1\src_r1$next[63:0]$14371 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14080 + update \src_r1$next $0\src_r1$next[63:0]$14370 end - attribute \src "libresoc.v:187799.3-187808.6" - process $proc$libresoc.v:187799$14082 + attribute \src "libresoc.v:198614.3-198623.6" + process $proc$libresoc.v:198614$14372 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14083 $1\src_r2$next[63:0]$14084 - attribute \src "libresoc.v:187800.5-187800.29" + assign $0\src_r2$next[63:0]$14373 $1\src_r2$next[63:0]$14374 + attribute \src "libresoc.v:198615.5-198615.29" switch \initial - attribute \src "libresoc.v:187800.9-187800.17" + attribute \src "libresoc.v:198615.9-198615.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14084 \src3_i + assign $1\src_r2$next[63:0]$14374 \src3_i case - assign $1\src_r2$next[63:0]$14084 \src_r2 + assign $1\src_r2$next[63:0]$14374 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14083 + update \src_r2$next $0\src_r2$next[63:0]$14373 end - attribute \src "libresoc.v:187809.3-187818.6" - process $proc$libresoc.v:187809$14085 + attribute \src "libresoc.v:198624.3-198633.6" + process $proc$libresoc.v:198624$14375 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14086 $1\src_r3$next[63:0]$14087 - attribute \src "libresoc.v:187810.5-187810.29" + assign $0\src_r3$next[63:0]$14376 $1\src_r3$next[63:0]$14377 + attribute \src "libresoc.v:198625.5-198625.29" switch \initial - attribute \src "libresoc.v:187810.9-187810.17" + attribute \src "libresoc.v:198625.9-198625.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14087 \src4_i + assign $1\src_r3$next[63:0]$14377 \src4_i case - assign $1\src_r3$next[63:0]$14087 \src_r3 + assign $1\src_r3$next[63:0]$14377 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14086 + update \src_r3$next $0\src_r3$next[63:0]$14376 end - attribute \src "libresoc.v:187819.3-187827.6" - process $proc$libresoc.v:187819$14088 + attribute \src "libresoc.v:198634.3-198642.6" + process $proc$libresoc.v:198634$14378 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14089 $1\alui_l_r_alui$next[0:0]$14090 - attribute \src "libresoc.v:187820.5-187820.29" + assign $0\alui_l_r_alui$next[0:0]$14379 $1\alui_l_r_alui$next[0:0]$14380 + attribute \src "libresoc.v:198635.5-198635.29" switch \initial - attribute \src "libresoc.v:187820.9-187820.17" + attribute \src "libresoc.v:198635.9-198635.17" case 1'1 case end @@ -395960,21 +415747,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14090 1'1 + assign $1\alui_l_r_alui$next[0:0]$14380 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14090 \$89 + assign $1\alui_l_r_alui$next[0:0]$14380 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14089 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14379 end - attribute \src "libresoc.v:187828.3-187836.6" - process $proc$libresoc.v:187828$14091 + attribute \src "libresoc.v:198643.3-198651.6" + process $proc$libresoc.v:198643$14381 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14092 $1\alu_l_r_alu$next[0:0]$14093 - attribute \src "libresoc.v:187829.5-187829.29" + assign $0\alu_l_r_alu$next[0:0]$14382 $1\alu_l_r_alu$next[0:0]$14383 + attribute \src "libresoc.v:198644.5-198644.29" switch \initial - attribute \src "libresoc.v:187829.9-187829.17" + attribute \src "libresoc.v:198644.9-198644.17" case 1'1 case end @@ -395983,21 +415770,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14093 1'1 + assign $1\alu_l_r_alu$next[0:0]$14383 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14093 \$91 + assign $1\alu_l_r_alu$next[0:0]$14383 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14092 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14382 end - attribute \src "libresoc.v:187837.3-187846.6" - process $proc$libresoc.v:187837$14094 + attribute \src "libresoc.v:198652.3-198661.6" + process $proc$libresoc.v:198652$14384 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:187838.5-187838.29" + attribute \src "libresoc.v:198653.5-198653.29" switch \initial - attribute \src "libresoc.v:187838.9-187838.17" + attribute \src "libresoc.v:198653.9-198653.17" case 1'1 case end @@ -396013,14 +415800,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:187847.3-187856.6" - process $proc$libresoc.v:187847$14095 + attribute \src "libresoc.v:198662.3-198671.6" + process $proc$libresoc.v:198662$14385 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:187848.5-187848.29" + attribute \src "libresoc.v:198663.5-198663.29" switch \initial - attribute \src "libresoc.v:187848.9-187848.17" + attribute \src "libresoc.v:198663.9-198663.17" case 1'1 case end @@ -396036,14 +415823,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:187857.3-187866.6" - process $proc$libresoc.v:187857$14096 + attribute \src "libresoc.v:198672.3-198681.6" + process $proc$libresoc.v:198672$14386 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:187858.5-187858.29" + attribute \src "libresoc.v:198673.5-198673.29" switch \initial - attribute \src "libresoc.v:187858.9-187858.17" + attribute \src "libresoc.v:198673.9-198673.17" case 1'1 case end @@ -396059,14 +415846,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:187867.3-187876.6" - process $proc$libresoc.v:187867$14097 + attribute \src "libresoc.v:198682.3-198691.6" + process $proc$libresoc.v:198682$14387 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:187868.5-187868.29" + attribute \src "libresoc.v:198683.5-198683.29" switch \initial - attribute \src "libresoc.v:187868.9-187868.17" + attribute \src "libresoc.v:198683.9-198683.17" case 1'1 case end @@ -396082,14 +415869,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:187877.3-187886.6" - process $proc$libresoc.v:187877$14098 + attribute \src "libresoc.v:198692.3-198701.6" + process $proc$libresoc.v:198692$14388 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:187878.5-187878.29" + attribute \src "libresoc.v:198693.5-198693.29" switch \initial - attribute \src "libresoc.v:187878.9-187878.17" + attribute \src "libresoc.v:198693.9-198693.17" case 1'1 case end @@ -396105,14 +415892,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:187887.3-187895.6" - process $proc$libresoc.v:187887$14099 + attribute \src "libresoc.v:198702.3-198710.6" + process $proc$libresoc.v:198702$14389 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14100 $1\prev_wr_go$next[4:0]$14101 - attribute \src "libresoc.v:187888.5-187888.29" + assign $0\prev_wr_go$next[4:0]$14390 $1\prev_wr_go$next[4:0]$14391 + attribute \src "libresoc.v:198703.5-198703.29" switch \initial - attribute \src "libresoc.v:187888.9-187888.17" + attribute \src "libresoc.v:198703.9-198703.17" case 1'1 case end @@ -396121,74 +415908,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14101 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14101 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14100 - end - connect \$5 $reduce_and$libresoc.v:187335$13887_Y - connect \$99 $and$libresoc.v:187336$13888_Y - connect \$101 $and$libresoc.v:187337$13889_Y - connect \$103 $and$libresoc.v:187338$13890_Y - connect \$105 $and$libresoc.v:187339$13891_Y - connect \$107 $and$libresoc.v:187340$13892_Y - connect \$109 $and$libresoc.v:187341$13893_Y - connect \$111 $and$libresoc.v:187342$13894_Y - connect \$113 $and$libresoc.v:187343$13895_Y - connect \$115 $and$libresoc.v:187344$13896_Y - connect \$117 $and$libresoc.v:187345$13897_Y - connect \$11 $and$libresoc.v:187346$13898_Y - connect \$119 $and$libresoc.v:187347$13899_Y - connect \$121 $and$libresoc.v:187348$13900_Y - connect \$123 $and$libresoc.v:187349$13901_Y - connect \$13 $not$libresoc.v:187350$13902_Y - connect \$15 $and$libresoc.v:187351$13903_Y - connect \$17 $not$libresoc.v:187352$13904_Y - connect \$19 $and$libresoc.v:187353$13905_Y - connect \$21 $and$libresoc.v:187354$13906_Y - connect \$25 $not$libresoc.v:187355$13907_Y - connect \$27 $and$libresoc.v:187356$13908_Y - connect \$24 $reduce_or$libresoc.v:187357$13909_Y - connect \$23 $not$libresoc.v:187358$13910_Y - connect \$31 $and$libresoc.v:187359$13911_Y - connect \$33 $reduce_or$libresoc.v:187360$13912_Y - connect \$35 $reduce_or$libresoc.v:187361$13913_Y - connect \$37 $or$libresoc.v:187362$13914_Y - connect \$3 $and$libresoc.v:187363$13915_Y - connect \$39 $not$libresoc.v:187364$13916_Y - connect \$41 $and$libresoc.v:187365$13917_Y - connect \$43 $and$libresoc.v:187366$13918_Y - connect \$45 $eq$libresoc.v:187367$13919_Y - connect \$47 $and$libresoc.v:187368$13920_Y - connect \$49 $eq$libresoc.v:187369$13921_Y - connect \$51 $and$libresoc.v:187370$13922_Y - connect \$53 $and$libresoc.v:187371$13923_Y - connect \$55 $and$libresoc.v:187372$13924_Y - connect \$57 $or$libresoc.v:187373$13925_Y - connect \$59 $or$libresoc.v:187374$13926_Y - connect \$61 $or$libresoc.v:187375$13927_Y - connect \$63 $or$libresoc.v:187376$13928_Y - connect \$65 $and$libresoc.v:187377$13929_Y - connect \$67 $and$libresoc.v:187378$13930_Y - connect \$6 $not$libresoc.v:187379$13931_Y - connect \$69 $or$libresoc.v:187380$13932_Y - connect \$71 $and$libresoc.v:187381$13933_Y - connect \$73 $and$libresoc.v:187382$13934_Y - connect \$75 $and$libresoc.v:187383$13935_Y - connect \$77 $and$libresoc.v:187384$13936_Y - connect \$79 $and$libresoc.v:187385$13937_Y - connect \$81 $ternary$libresoc.v:187386$13938_Y - connect \$83 $ternary$libresoc.v:187387$13939_Y - connect \$85 $ternary$libresoc.v:187388$13940_Y - connect \$87 $ternary$libresoc.v:187389$13941_Y - connect \$8 $or$libresoc.v:187390$13942_Y - connect \$89 $and$libresoc.v:187391$13943_Y - connect \$91 $and$libresoc.v:187392$13944_Y - connect \$93 $and$libresoc.v:187393$13945_Y - connect \$95 $and$libresoc.v:187394$13946_Y - connect \$97 $not$libresoc.v:187395$13947_Y + assign $1\prev_wr_go$next[4:0]$14391 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14391 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14390 + end + connect \$5 $reduce_and$libresoc.v:198150$14177_Y + connect \$99 $and$libresoc.v:198151$14178_Y + connect \$101 $and$libresoc.v:198152$14179_Y + connect \$103 $and$libresoc.v:198153$14180_Y + connect \$105 $and$libresoc.v:198154$14181_Y + connect \$107 $and$libresoc.v:198155$14182_Y + connect \$109 $and$libresoc.v:198156$14183_Y + connect \$111 $and$libresoc.v:198157$14184_Y + connect \$113 $and$libresoc.v:198158$14185_Y + connect \$115 $and$libresoc.v:198159$14186_Y + connect \$117 $and$libresoc.v:198160$14187_Y + connect \$11 $and$libresoc.v:198161$14188_Y + connect \$119 $and$libresoc.v:198162$14189_Y + connect \$121 $and$libresoc.v:198163$14190_Y + connect \$123 $and$libresoc.v:198164$14191_Y + connect \$13 $not$libresoc.v:198165$14192_Y + connect \$15 $and$libresoc.v:198166$14193_Y + connect \$17 $not$libresoc.v:198167$14194_Y + connect \$19 $and$libresoc.v:198168$14195_Y + connect \$21 $and$libresoc.v:198169$14196_Y + connect \$25 $not$libresoc.v:198170$14197_Y + connect \$27 $and$libresoc.v:198171$14198_Y + connect \$24 $reduce_or$libresoc.v:198172$14199_Y + connect \$23 $not$libresoc.v:198173$14200_Y + connect \$31 $and$libresoc.v:198174$14201_Y + connect \$33 $reduce_or$libresoc.v:198175$14202_Y + connect \$35 $reduce_or$libresoc.v:198176$14203_Y + connect \$37 $or$libresoc.v:198177$14204_Y + connect \$3 $and$libresoc.v:198178$14205_Y + connect \$39 $not$libresoc.v:198179$14206_Y + connect \$41 $and$libresoc.v:198180$14207_Y + connect \$43 $and$libresoc.v:198181$14208_Y + connect \$45 $eq$libresoc.v:198182$14209_Y + connect \$47 $and$libresoc.v:198183$14210_Y + connect \$49 $eq$libresoc.v:198184$14211_Y + connect \$51 $and$libresoc.v:198185$14212_Y + connect \$53 $and$libresoc.v:198186$14213_Y + connect \$55 $and$libresoc.v:198187$14214_Y + connect \$57 $or$libresoc.v:198188$14215_Y + connect \$59 $or$libresoc.v:198189$14216_Y + connect \$61 $or$libresoc.v:198190$14217_Y + connect \$63 $or$libresoc.v:198191$14218_Y + connect \$65 $and$libresoc.v:198192$14219_Y + connect \$67 $and$libresoc.v:198193$14220_Y + connect \$6 $not$libresoc.v:198194$14221_Y + connect \$69 $or$libresoc.v:198195$14222_Y + connect \$71 $and$libresoc.v:198196$14223_Y + connect \$73 $and$libresoc.v:198197$14224_Y + connect \$75 $and$libresoc.v:198198$14225_Y + connect \$77 $and$libresoc.v:198199$14226_Y + connect \$79 $and$libresoc.v:198200$14227_Y + connect \$81 $ternary$libresoc.v:198201$14228_Y + connect \$83 $ternary$libresoc.v:198202$14229_Y + connect \$85 $ternary$libresoc.v:198203$14230_Y + connect \$87 $ternary$libresoc.v:198204$14231_Y + connect \$8 $or$libresoc.v:198205$14232_Y + connect \$89 $and$libresoc.v:198206$14233_Y + connect \$91 $and$libresoc.v:198207$14234_Y + connect \$93 $and$libresoc.v:198208$14235_Y + connect \$95 $and$libresoc.v:198209$14236_Y + connect \$97 $not$libresoc.v:198210$14237_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -396219,75 +416006,75 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:187929.1-187987.10" +attribute \src "libresoc.v:198744.1-198802.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:187930.7-187930.20" + attribute \src "libresoc.v:198745.7-198745.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187975.3-187983.6" - wire $0\q_int$next[0:0]$14151 - attribute \src "libresoc.v:187973.3-187974.27" + attribute \src "libresoc.v:198790.3-198798.6" + wire $0\q_int$next[0:0]$14441 + attribute \src "libresoc.v:198788.3-198789.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:187975.3-187983.6" - wire $1\q_int$next[0:0]$14152 - attribute \src "libresoc.v:187952.7-187952.19" + attribute \src "libresoc.v:198790.3-198798.6" + wire $1\q_int$next[0:0]$14442 + attribute \src "libresoc.v:198767.7-198767.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:187965.17-187965.96" - wire $and$libresoc.v:187965$14141_Y - attribute \src "libresoc.v:187970.17-187970.96" - wire $and$libresoc.v:187970$14146_Y - attribute \src "libresoc.v:187967.18-187967.93" - wire $not$libresoc.v:187967$14143_Y - attribute \src "libresoc.v:187969.17-187969.92" - wire $not$libresoc.v:187969$14145_Y - attribute \src "libresoc.v:187972.17-187972.92" - wire $not$libresoc.v:187972$14148_Y - attribute \src "libresoc.v:187966.18-187966.98" - wire $or$libresoc.v:187966$14142_Y - attribute \src "libresoc.v:187968.18-187968.99" - wire $or$libresoc.v:187968$14144_Y - attribute \src "libresoc.v:187971.17-187971.97" - wire $or$libresoc.v:187971$14147_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:198780.17-198780.96" + wire $and$libresoc.v:198780$14431_Y + attribute \src "libresoc.v:198785.17-198785.96" + wire $and$libresoc.v:198785$14436_Y + attribute \src "libresoc.v:198782.18-198782.93" + wire $not$libresoc.v:198782$14433_Y + attribute \src "libresoc.v:198784.17-198784.92" + wire $not$libresoc.v:198784$14435_Y + attribute \src "libresoc.v:198787.17-198787.92" + wire $not$libresoc.v:198787$14438_Y + attribute \src "libresoc.v:198781.18-198781.98" + wire $or$libresoc.v:198781$14432_Y + attribute \src "libresoc.v:198783.18-198783.99" + wire $or$libresoc.v:198783$14434_Y + attribute \src "libresoc.v:198786.17-198786.97" + wire $or$libresoc.v:198786$14437_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187930.7-187930.15" + attribute \src "libresoc.v:198745.7-198745.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:187965$14141 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:198780$14431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396295,10 +416082,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187965$14141_Y + connect \Y $and$libresoc.v:198780$14431_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:187970$14146 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:198785$14436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396306,34 +416093,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187970$14146_Y + connect \Y $and$libresoc.v:198785$14436_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:187967$14143 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:198782$14433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:187967$14143_Y + connect \Y $not$libresoc.v:198782$14433_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:187969$14145 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:198784$14435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:187969$14145_Y + connect \Y $not$libresoc.v:198784$14435_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:187972$14148 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:198787$14438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:187972$14148_Y + connect \Y $not$libresoc.v:198787$14438_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:187966$14142 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:198781$14432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396341,10 +416128,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:187966$14142_Y + connect \Y $or$libresoc.v:198781$14432_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:187968$14144 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:198783$14434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396352,10 +416139,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:187968$14144_Y + connect \Y $or$libresoc.v:198783$14434_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:187971$14147 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:198786$14437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396363,39 +416150,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:187971$14147_Y + connect \Y $or$libresoc.v:198786$14437_Y end - attribute \src "libresoc.v:187930.7-187930.20" - process $proc$libresoc.v:187930$14153 + attribute \src "libresoc.v:198745.7-198745.20" + process $proc$libresoc.v:198745$14443 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187952.7-187952.19" - process $proc$libresoc.v:187952$14154 + attribute \src "libresoc.v:198767.7-198767.19" + process $proc$libresoc.v:198767$14444 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:187973.3-187974.27" - process $proc$libresoc.v:187973$14149 + attribute \src "libresoc.v:198788.3-198789.27" + process $proc$libresoc.v:198788$14439 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:187975.3-187983.6" - process $proc$libresoc.v:187975$14150 + attribute \src "libresoc.v:198790.3-198798.6" + process $proc$libresoc.v:198790$14440 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14151 $1\q_int$next[0:0]$14152 - attribute \src "libresoc.v:187976.5-187976.29" + assign $0\q_int$next[0:0]$14441 $1\q_int$next[0:0]$14442 + attribute \src "libresoc.v:198791.5-198791.29" switch \initial - attribute \src "libresoc.v:187976.9-187976.17" + attribute \src "libresoc.v:198791.9-198791.17" case 1'1 case end @@ -396404,94 +416191,94 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14152 1'0 + assign $1\q_int$next[0:0]$14442 1'0 case - assign $1\q_int$next[0:0]$14152 \$5 + assign $1\q_int$next[0:0]$14442 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14151 + update \q_int$next $0\q_int$next[0:0]$14441 end - connect \$9 $and$libresoc.v:187965$14141_Y - connect \$11 $or$libresoc.v:187966$14142_Y - connect \$13 $not$libresoc.v:187967$14143_Y - connect \$15 $or$libresoc.v:187968$14144_Y - connect \$1 $not$libresoc.v:187969$14145_Y - connect \$3 $and$libresoc.v:187970$14146_Y - connect \$5 $or$libresoc.v:187971$14147_Y - connect \$7 $not$libresoc.v:187972$14148_Y + connect \$9 $and$libresoc.v:198780$14431_Y + connect \$11 $or$libresoc.v:198781$14432_Y + connect \$13 $not$libresoc.v:198782$14433_Y + connect \$15 $or$libresoc.v:198783$14434_Y + connect \$1 $not$libresoc.v:198784$14435_Y + connect \$3 $and$libresoc.v:198785$14436_Y + connect \$5 $or$libresoc.v:198786$14437_Y + connect \$7 $not$libresoc.v:198787$14438_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:187991.1-188049.10" +attribute \src "libresoc.v:198806.1-198864.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:187992.7-187992.20" + attribute \src "libresoc.v:198807.7-198807.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188037.3-188045.6" - wire $0\q_int$next[0:0]$14165 - attribute \src "libresoc.v:188035.3-188036.27" + attribute \src "libresoc.v:198852.3-198860.6" + wire $0\q_int$next[0:0]$14455 + attribute \src "libresoc.v:198850.3-198851.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188037.3-188045.6" - wire $1\q_int$next[0:0]$14166 - attribute \src "libresoc.v:188014.7-188014.19" + attribute \src "libresoc.v:198852.3-198860.6" + wire $1\q_int$next[0:0]$14456 + attribute \src "libresoc.v:198829.7-198829.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188027.17-188027.96" - wire $and$libresoc.v:188027$14155_Y - attribute \src "libresoc.v:188032.17-188032.96" - wire $and$libresoc.v:188032$14160_Y - attribute \src "libresoc.v:188029.18-188029.95" - wire $not$libresoc.v:188029$14157_Y - attribute \src "libresoc.v:188031.17-188031.94" - wire $not$libresoc.v:188031$14159_Y - attribute \src "libresoc.v:188034.17-188034.94" - wire $not$libresoc.v:188034$14162_Y - attribute \src "libresoc.v:188028.18-188028.100" - wire $or$libresoc.v:188028$14156_Y - attribute \src "libresoc.v:188030.18-188030.101" - wire $or$libresoc.v:188030$14158_Y - attribute \src "libresoc.v:188033.17-188033.99" - wire $or$libresoc.v:188033$14161_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:198842.17-198842.96" + wire $and$libresoc.v:198842$14445_Y + attribute \src "libresoc.v:198847.17-198847.96" + wire $and$libresoc.v:198847$14450_Y + attribute \src "libresoc.v:198844.18-198844.95" + wire $not$libresoc.v:198844$14447_Y + attribute \src "libresoc.v:198846.17-198846.94" + wire $not$libresoc.v:198846$14449_Y + attribute \src "libresoc.v:198849.17-198849.94" + wire $not$libresoc.v:198849$14452_Y + attribute \src "libresoc.v:198843.18-198843.100" + wire $or$libresoc.v:198843$14446_Y + attribute \src "libresoc.v:198845.18-198845.101" + wire $or$libresoc.v:198845$14448_Y + attribute \src "libresoc.v:198848.17-198848.99" + wire $or$libresoc.v:198848$14451_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187992.7-187992.15" + attribute \src "libresoc.v:198807.7-198807.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 3 \q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:188027$14155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:198842$14445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396499,10 +416286,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188027$14155_Y + connect \Y $and$libresoc.v:198842$14445_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:188032$14160 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:198847$14450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396510,34 +416297,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188032$14160_Y + connect \Y $and$libresoc.v:198847$14450_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:188029$14157 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:198844$14447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:188029$14157_Y + connect \Y $not$libresoc.v:198844$14447_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:188031$14159 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:198846$14449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:188031$14159_Y + connect \Y $not$libresoc.v:198846$14449_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:188034$14162 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:198849$14452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:188034$14162_Y + connect \Y $not$libresoc.v:198849$14452_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:188028$14156 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:198843$14446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396545,10 +416332,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:188028$14156_Y + connect \Y $or$libresoc.v:198843$14446_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:188030$14158 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:198845$14448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396556,10 +416343,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:188030$14158_Y + connect \Y $or$libresoc.v:198845$14448_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:188033$14161 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:198848$14451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396567,39 +416354,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:188033$14161_Y + connect \Y $or$libresoc.v:198848$14451_Y end - attribute \src "libresoc.v:187992.7-187992.20" - process $proc$libresoc.v:187992$14167 + attribute \src "libresoc.v:198807.7-198807.20" + process $proc$libresoc.v:198807$14457 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188014.7-188014.19" - process $proc$libresoc.v:188014$14168 + attribute \src "libresoc.v:198829.7-198829.19" + process $proc$libresoc.v:198829$14458 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188035.3-188036.27" - process $proc$libresoc.v:188035$14163 + attribute \src "libresoc.v:198850.3-198851.27" + process $proc$libresoc.v:198850$14453 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188037.3-188045.6" - process $proc$libresoc.v:188037$14164 + attribute \src "libresoc.v:198852.3-198860.6" + process $proc$libresoc.v:198852$14454 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14165 $1\q_int$next[0:0]$14166 - attribute \src "libresoc.v:188038.5-188038.29" + assign $0\q_int$next[0:0]$14455 $1\q_int$next[0:0]$14456 + attribute \src "libresoc.v:198853.5-198853.29" switch \initial - attribute \src "libresoc.v:188038.9-188038.17" + attribute \src "libresoc.v:198853.9-198853.17" case 1'1 case end @@ -396608,94 +416395,94 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14166 1'0 + assign $1\q_int$next[0:0]$14456 1'0 case - assign $1\q_int$next[0:0]$14166 \$5 + assign $1\q_int$next[0:0]$14456 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14165 + update \q_int$next $0\q_int$next[0:0]$14455 end - connect \$9 $and$libresoc.v:188027$14155_Y - connect \$11 $or$libresoc.v:188028$14156_Y - connect \$13 $not$libresoc.v:188029$14157_Y - connect \$15 $or$libresoc.v:188030$14158_Y - connect \$1 $not$libresoc.v:188031$14159_Y - connect \$3 $and$libresoc.v:188032$14160_Y - connect \$5 $or$libresoc.v:188033$14161_Y - connect \$7 $not$libresoc.v:188034$14162_Y + connect \$9 $and$libresoc.v:198842$14445_Y + connect \$11 $or$libresoc.v:198843$14446_Y + connect \$13 $not$libresoc.v:198844$14447_Y + connect \$15 $or$libresoc.v:198845$14448_Y + connect \$1 $not$libresoc.v:198846$14449_Y + connect \$3 $and$libresoc.v:198847$14450_Y + connect \$5 $or$libresoc.v:198848$14451_Y + connect \$7 $not$libresoc.v:198849$14452_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:188053.1-188111.10" +attribute \src "libresoc.v:198868.1-198926.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:188054.7-188054.20" + attribute \src "libresoc.v:198869.7-198869.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188099.3-188107.6" - wire $0\q_int$next[0:0]$14179 - attribute \src "libresoc.v:188097.3-188098.27" + attribute \src "libresoc.v:198914.3-198922.6" + wire $0\q_int$next[0:0]$14469 + attribute \src "libresoc.v:198912.3-198913.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188099.3-188107.6" - wire $1\q_int$next[0:0]$14180 - attribute \src "libresoc.v:188076.7-188076.19" + attribute \src "libresoc.v:198914.3-198922.6" + wire $1\q_int$next[0:0]$14470 + attribute \src "libresoc.v:198891.7-198891.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188089.17-188089.96" - wire $and$libresoc.v:188089$14169_Y - attribute \src "libresoc.v:188094.17-188094.96" - wire $and$libresoc.v:188094$14174_Y - attribute \src "libresoc.v:188091.18-188091.93" - wire $not$libresoc.v:188091$14171_Y - attribute \src "libresoc.v:188093.17-188093.92" - wire $not$libresoc.v:188093$14173_Y - attribute \src "libresoc.v:188096.17-188096.92" - wire $not$libresoc.v:188096$14176_Y - attribute \src "libresoc.v:188090.18-188090.98" - wire $or$libresoc.v:188090$14170_Y - attribute \src "libresoc.v:188092.18-188092.99" - wire $or$libresoc.v:188092$14172_Y - attribute \src "libresoc.v:188095.17-188095.97" - wire $or$libresoc.v:188095$14175_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "libresoc.v:198904.17-198904.96" + wire $and$libresoc.v:198904$14459_Y + attribute \src "libresoc.v:198909.17-198909.96" + wire $and$libresoc.v:198909$14464_Y + attribute \src "libresoc.v:198906.18-198906.93" + wire $not$libresoc.v:198906$14461_Y + attribute \src "libresoc.v:198908.17-198908.92" + wire $not$libresoc.v:198908$14463_Y + attribute \src "libresoc.v:198911.17-198911.92" + wire $not$libresoc.v:198911$14466_Y + attribute \src "libresoc.v:198905.18-198905.98" + wire $or$libresoc.v:198905$14460_Y + attribute \src "libresoc.v:198907.18-198907.99" + wire $or$libresoc.v:198907$14462_Y + attribute \src "libresoc.v:198910.17-198910.97" + wire $or$libresoc.v:198910$14465_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:188054.7-188054.15" + attribute \src "libresoc.v:198869.7-198869.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:188089$14169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:198904$14459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396703,10 +416490,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188089$14169_Y + connect \Y $and$libresoc.v:198904$14459_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:188094$14174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:198909$14464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396714,34 +416501,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188094$14174_Y + connect \Y $and$libresoc.v:198909$14464_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:188091$14171 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:198906$14461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:188091$14171_Y + connect \Y $not$libresoc.v:198906$14461_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:188093$14173 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:198908$14463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:188093$14173_Y + connect \Y $not$libresoc.v:198908$14463_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:188096$14176 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:198911$14466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:188096$14176_Y + connect \Y $not$libresoc.v:198911$14466_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:188090$14170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:198905$14460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396749,10 +416536,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:188090$14170_Y + connect \Y $or$libresoc.v:198905$14460_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:188092$14172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:198907$14462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396760,10 +416547,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:188092$14172_Y + connect \Y $or$libresoc.v:198907$14462_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:188095$14175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:198910$14465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396771,39 +416558,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:188095$14175_Y + connect \Y $or$libresoc.v:198910$14465_Y end - attribute \src "libresoc.v:188054.7-188054.20" - process $proc$libresoc.v:188054$14181 + attribute \src "libresoc.v:198869.7-198869.20" + process $proc$libresoc.v:198869$14471 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188076.7-188076.19" - process $proc$libresoc.v:188076$14182 + attribute \src "libresoc.v:198891.7-198891.19" + process $proc$libresoc.v:198891$14472 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188097.3-188098.27" - process $proc$libresoc.v:188097$14177 + attribute \src "libresoc.v:198912.3-198913.27" + process $proc$libresoc.v:198912$14467 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188099.3-188107.6" - process $proc$libresoc.v:188099$14178 + attribute \src "libresoc.v:198914.3-198922.6" + process $proc$libresoc.v:198914$14468 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14179 $1\q_int$next[0:0]$14180 - attribute \src "libresoc.v:188100.5-188100.29" + assign $0\q_int$next[0:0]$14469 $1\q_int$next[0:0]$14470 + attribute \src "libresoc.v:198915.5-198915.29" switch \initial - attribute \src "libresoc.v:188100.9-188100.17" + attribute \src "libresoc.v:198915.9-198915.17" case 1'1 case end @@ -396812,206 +416599,206 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14180 1'0 + assign $1\q_int$next[0:0]$14470 1'0 case - assign $1\q_int$next[0:0]$14180 \$5 + assign $1\q_int$next[0:0]$14470 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14179 + update \q_int$next $0\q_int$next[0:0]$14469 end - connect \$9 $and$libresoc.v:188089$14169_Y - connect \$11 $or$libresoc.v:188090$14170_Y - connect \$13 $not$libresoc.v:188091$14171_Y - connect \$15 $or$libresoc.v:188092$14172_Y - connect \$1 $not$libresoc.v:188093$14173_Y - connect \$3 $and$libresoc.v:188094$14174_Y - connect \$5 $or$libresoc.v:188095$14175_Y - connect \$7 $not$libresoc.v:188096$14176_Y + connect \$9 $and$libresoc.v:198904$14459_Y + connect \$11 $or$libresoc.v:198905$14460_Y + connect \$13 $not$libresoc.v:198906$14461_Y + connect \$15 $or$libresoc.v:198907$14462_Y + connect \$1 $not$libresoc.v:198908$14463_Y + connect \$3 $and$libresoc.v:198909$14464_Y + connect \$5 $or$libresoc.v:198910$14465_Y + connect \$7 $not$libresoc.v:198911$14466_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:188115.1-188181.10" +attribute \src "libresoc.v:198930.1-198996.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:188160.17-188160.91" - wire $not$libresoc.v:188160$14183_Y - attribute \src "libresoc.v:188162.18-188162.93" - wire $not$libresoc.v:188162$14185_Y - attribute \src "libresoc.v:188164.18-188164.93" - wire $not$libresoc.v:188164$14187_Y - attribute \src "libresoc.v:188165.17-188165.89" - wire width 6 $not$libresoc.v:188165$14188_Y - attribute \src "libresoc.v:188167.18-188167.93" - wire $not$libresoc.v:188167$14190_Y - attribute \src "libresoc.v:188170.17-188170.91" - wire $not$libresoc.v:188170$14193_Y - attribute \src "libresoc.v:188161.18-188161.106" - wire $reduce_or$libresoc.v:188161$14184_Y - attribute \src "libresoc.v:188163.18-188163.106" - wire $reduce_or$libresoc.v:188163$14186_Y - attribute \src "libresoc.v:188166.18-188166.106" - wire $reduce_or$libresoc.v:188166$14189_Y - attribute \src "libresoc.v:188168.18-188168.90" - wire $reduce_or$libresoc.v:188168$14191_Y - attribute \src "libresoc.v:188169.17-188169.103" - wire $reduce_or$libresoc.v:188169$14192_Y - attribute \src "libresoc.v:188171.17-188171.105" - wire $reduce_or$libresoc.v:188171$14194_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:198975.17-198975.91" + wire $not$libresoc.v:198975$14473_Y + attribute \src "libresoc.v:198977.18-198977.93" + wire $not$libresoc.v:198977$14475_Y + attribute \src "libresoc.v:198979.18-198979.93" + wire $not$libresoc.v:198979$14477_Y + attribute \src "libresoc.v:198980.17-198980.89" + wire width 6 $not$libresoc.v:198980$14478_Y + attribute \src "libresoc.v:198982.18-198982.93" + wire $not$libresoc.v:198982$14480_Y + attribute \src "libresoc.v:198985.17-198985.91" + wire $not$libresoc.v:198985$14483_Y + attribute \src "libresoc.v:198976.18-198976.106" + wire $reduce_or$libresoc.v:198976$14474_Y + attribute \src "libresoc.v:198978.18-198978.106" + wire $reduce_or$libresoc.v:198978$14476_Y + attribute \src "libresoc.v:198981.18-198981.106" + wire $reduce_or$libresoc.v:198981$14479_Y + attribute \src "libresoc.v:198983.18-198983.90" + wire $reduce_or$libresoc.v:198983$14481_Y + attribute \src "libresoc.v:198984.17-198984.103" + wire $reduce_or$libresoc.v:198984$14482_Y + attribute \src "libresoc.v:198986.17-198986.105" + wire $reduce_or$libresoc.v:198986$14484_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 6 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188160$14183 + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:198975$14473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:188160$14183_Y + connect \Y $not$libresoc.v:198975$14473_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188162$14185 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:198977$14475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:188162$14185_Y + connect \Y $not$libresoc.v:198977$14475_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188164$14187 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:198979$14477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:188164$14187_Y + connect \Y $not$libresoc.v:198979$14477_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188165$14188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:198980$14478 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:188165$14188_Y + connect \Y $not$libresoc.v:198980$14478_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188167$14190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:198982$14480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:188167$14190_Y + connect \Y $not$libresoc.v:198982$14480_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188170$14193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:198985$14483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:188170$14193_Y + connect \Y $not$libresoc.v:198985$14483_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188161$14184 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:198976$14474 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188161$14184_Y + connect \Y $reduce_or$libresoc.v:198976$14474_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188163$14186 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:198978$14476 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:188163$14186_Y + connect \Y $reduce_or$libresoc.v:198978$14476_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188166$14189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:198981$14479 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:188166$14189_Y + connect \Y $reduce_or$libresoc.v:198981$14479_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188168$14191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:198983$14481 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188168$14191_Y + connect \Y $reduce_or$libresoc.v:198983$14481_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188169$14192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:198984$14482 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188169$14192_Y + connect \Y $reduce_or$libresoc.v:198984$14482_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188171$14194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:198986$14484 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188171$14194_Y - end - connect \$7 $not$libresoc.v:188160$14183_Y - connect \$12 $reduce_or$libresoc.v:188161$14184_Y - connect \$11 $not$libresoc.v:188162$14185_Y - connect \$16 $reduce_or$libresoc.v:188163$14186_Y - connect \$15 $not$libresoc.v:188164$14187_Y - connect \$1 $not$libresoc.v:188165$14188_Y - connect \$20 $reduce_or$libresoc.v:188166$14189_Y - connect \$19 $not$libresoc.v:188167$14190_Y - connect \$23 $reduce_or$libresoc.v:188168$14191_Y - connect \$4 $reduce_or$libresoc.v:188169$14192_Y - connect \$3 $not$libresoc.v:188170$14193_Y - connect \$8 $reduce_or$libresoc.v:188171$14194_Y + connect \Y $reduce_or$libresoc.v:198986$14484_Y + end + connect \$7 $not$libresoc.v:198975$14473_Y + connect \$12 $reduce_or$libresoc.v:198976$14474_Y + connect \$11 $not$libresoc.v:198977$14475_Y + connect \$16 $reduce_or$libresoc.v:198978$14476_Y + connect \$15 $not$libresoc.v:198979$14477_Y + connect \$1 $not$libresoc.v:198980$14478_Y + connect \$20 $reduce_or$libresoc.v:198981$14479_Y + connect \$19 $not$libresoc.v:198982$14480_Y + connect \$23 $reduce_or$libresoc.v:198983$14481_Y + connect \$4 $reduce_or$libresoc.v:198984$14482_Y + connect \$3 $not$libresoc.v:198985$14483_Y + connect \$8 $reduce_or$libresoc.v:198986$14484_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -397022,205 +416809,205 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:188185.1-188206.10" +attribute \src "libresoc.v:199000.1-199021.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:188200.17-188200.89" - wire $not$libresoc.v:188200$14195_Y - attribute \src "libresoc.v:188201.17-188201.89" - wire $reduce_or$libresoc.v:188201$14196_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199015.17-199015.89" + wire $not$libresoc.v:199015$14485_Y + attribute \src "libresoc.v:199016.17-199016.89" + wire $reduce_or$libresoc.v:199016$14486_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188200$14195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199015$14485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:188200$14195_Y + connect \Y $not$libresoc.v:199015$14485_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188201$14196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199016$14486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188201$14196_Y + connect \Y $reduce_or$libresoc.v:199016$14486_Y end - connect \$1 $not$libresoc.v:188200$14195_Y - connect \$3 $reduce_or$libresoc.v:188201$14196_Y + connect \$1 $not$libresoc.v:199015$14485_Y + connect \$3 $reduce_or$libresoc.v:199016$14486_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:188210.1-188267.10" +attribute \src "libresoc.v:199025.1-199082.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:188249.17-188249.91" - wire $not$libresoc.v:188249$14197_Y - attribute \src "libresoc.v:188251.18-188251.93" - wire $not$libresoc.v:188251$14199_Y - attribute \src "libresoc.v:188253.18-188253.93" - wire $not$libresoc.v:188253$14201_Y - attribute \src "libresoc.v:188254.17-188254.89" - wire width 5 $not$libresoc.v:188254$14202_Y - attribute \src "libresoc.v:188257.17-188257.91" - wire $not$libresoc.v:188257$14205_Y - attribute \src "libresoc.v:188250.18-188250.106" - wire $reduce_or$libresoc.v:188250$14198_Y - attribute \src "libresoc.v:188252.18-188252.106" - wire $reduce_or$libresoc.v:188252$14200_Y - attribute \src "libresoc.v:188255.18-188255.90" - wire $reduce_or$libresoc.v:188255$14203_Y - attribute \src "libresoc.v:188256.17-188256.103" - wire $reduce_or$libresoc.v:188256$14204_Y - attribute \src "libresoc.v:188258.17-188258.105" - wire $reduce_or$libresoc.v:188258$14206_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199064.17-199064.91" + wire $not$libresoc.v:199064$14487_Y + attribute \src "libresoc.v:199066.18-199066.93" + wire $not$libresoc.v:199066$14489_Y + attribute \src "libresoc.v:199068.18-199068.93" + wire $not$libresoc.v:199068$14491_Y + attribute \src "libresoc.v:199069.17-199069.89" + wire width 5 $not$libresoc.v:199069$14492_Y + attribute \src "libresoc.v:199072.17-199072.91" + wire $not$libresoc.v:199072$14495_Y + attribute \src "libresoc.v:199065.18-199065.106" + wire $reduce_or$libresoc.v:199065$14488_Y + attribute \src "libresoc.v:199067.18-199067.106" + wire $reduce_or$libresoc.v:199067$14490_Y + attribute \src "libresoc.v:199070.18-199070.90" + wire $reduce_or$libresoc.v:199070$14493_Y + attribute \src "libresoc.v:199071.17-199071.103" + wire $reduce_or$libresoc.v:199071$14494_Y + attribute \src "libresoc.v:199073.17-199073.105" + wire $reduce_or$libresoc.v:199073$14496_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 5 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 5 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 5 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188249$14197 + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199064$14487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:188249$14197_Y + connect \Y $not$libresoc.v:199064$14487_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188251$14199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199066$14489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:188251$14199_Y + connect \Y $not$libresoc.v:199066$14489_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188253$14201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199068$14491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:188253$14201_Y + connect \Y $not$libresoc.v:199068$14491_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188254$14202 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199069$14492 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:188254$14202_Y + connect \Y $not$libresoc.v:199069$14492_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188257$14205 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199072$14495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:188257$14205_Y + connect \Y $not$libresoc.v:199072$14495_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188250$14198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199065$14488 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188250$14198_Y + connect \Y $reduce_or$libresoc.v:199065$14488_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188252$14200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199067$14490 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:188252$14200_Y + connect \Y $reduce_or$libresoc.v:199067$14490_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188255$14203 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199070$14493 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188255$14203_Y + connect \Y $reduce_or$libresoc.v:199070$14493_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188256$14204 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199071$14494 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188256$14204_Y + connect \Y $reduce_or$libresoc.v:199071$14494_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188258$14206 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199073$14496 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188258$14206_Y - end - connect \$7 $not$libresoc.v:188249$14197_Y - connect \$12 $reduce_or$libresoc.v:188250$14198_Y - connect \$11 $not$libresoc.v:188251$14199_Y - connect \$16 $reduce_or$libresoc.v:188252$14200_Y - connect \$15 $not$libresoc.v:188253$14201_Y - connect \$1 $not$libresoc.v:188254$14202_Y - connect \$19 $reduce_or$libresoc.v:188255$14203_Y - connect \$4 $reduce_or$libresoc.v:188256$14204_Y - connect \$3 $not$libresoc.v:188257$14205_Y - connect \$8 $reduce_or$libresoc.v:188258$14206_Y + connect \Y $reduce_or$libresoc.v:199073$14496_Y + end + connect \$7 $not$libresoc.v:199064$14487_Y + connect \$12 $reduce_or$libresoc.v:199065$14488_Y + connect \$11 $not$libresoc.v:199066$14489_Y + connect \$16 $reduce_or$libresoc.v:199067$14490_Y + connect \$15 $not$libresoc.v:199068$14491_Y + connect \$1 $not$libresoc.v:199069$14492_Y + connect \$19 $reduce_or$libresoc.v:199070$14493_Y + connect \$4 $reduce_or$libresoc.v:199071$14494_Y + connect \$3 $not$libresoc.v:199072$14495_Y + connect \$8 $reduce_or$libresoc.v:199073$14496_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -397230,299 +417017,299 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:188271.1-188373.10" +attribute \src "libresoc.v:199086.1-199188.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:188340.17-188340.91" - wire $not$libresoc.v:188340$14207_Y - attribute \src "libresoc.v:188342.18-188342.93" - wire $not$libresoc.v:188342$14209_Y - attribute \src "libresoc.v:188344.18-188344.93" - wire $not$libresoc.v:188344$14211_Y - attribute \src "libresoc.v:188345.17-188345.89" - wire width 10 $not$libresoc.v:188345$14212_Y - attribute \src "libresoc.v:188347.18-188347.93" - wire $not$libresoc.v:188347$14214_Y - attribute \src "libresoc.v:188349.18-188349.93" - wire $not$libresoc.v:188349$14216_Y - attribute \src "libresoc.v:188351.18-188351.93" - wire $not$libresoc.v:188351$14218_Y - attribute \src "libresoc.v:188353.18-188353.93" - wire $not$libresoc.v:188353$14220_Y - attribute \src "libresoc.v:188355.18-188355.93" - wire $not$libresoc.v:188355$14222_Y - attribute \src "libresoc.v:188358.17-188358.91" - wire $not$libresoc.v:188358$14225_Y - attribute \src "libresoc.v:188341.18-188341.106" - wire $reduce_or$libresoc.v:188341$14208_Y - attribute \src "libresoc.v:188343.18-188343.106" - wire $reduce_or$libresoc.v:188343$14210_Y - attribute \src "libresoc.v:188346.18-188346.106" - wire $reduce_or$libresoc.v:188346$14213_Y - attribute \src "libresoc.v:188348.18-188348.106" - wire $reduce_or$libresoc.v:188348$14215_Y - attribute \src "libresoc.v:188350.18-188350.106" - wire $reduce_or$libresoc.v:188350$14217_Y - attribute \src "libresoc.v:188352.18-188352.106" - wire $reduce_or$libresoc.v:188352$14219_Y - attribute \src "libresoc.v:188354.18-188354.106" - wire $reduce_or$libresoc.v:188354$14221_Y - attribute \src "libresoc.v:188356.18-188356.90" - wire $reduce_or$libresoc.v:188356$14223_Y - attribute \src "libresoc.v:188357.17-188357.103" - wire $reduce_or$libresoc.v:188357$14224_Y - attribute \src "libresoc.v:188359.17-188359.105" - wire $reduce_or$libresoc.v:188359$14226_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199155.17-199155.91" + wire $not$libresoc.v:199155$14497_Y + attribute \src "libresoc.v:199157.18-199157.93" + wire $not$libresoc.v:199157$14499_Y + attribute \src "libresoc.v:199159.18-199159.93" + wire $not$libresoc.v:199159$14501_Y + attribute \src "libresoc.v:199160.17-199160.89" + wire width 10 $not$libresoc.v:199160$14502_Y + attribute \src "libresoc.v:199162.18-199162.93" + wire $not$libresoc.v:199162$14504_Y + attribute \src "libresoc.v:199164.18-199164.93" + wire $not$libresoc.v:199164$14506_Y + attribute \src "libresoc.v:199166.18-199166.93" + wire $not$libresoc.v:199166$14508_Y + attribute \src "libresoc.v:199168.18-199168.93" + wire $not$libresoc.v:199168$14510_Y + attribute \src "libresoc.v:199170.18-199170.93" + wire $not$libresoc.v:199170$14512_Y + attribute \src "libresoc.v:199173.17-199173.91" + wire $not$libresoc.v:199173$14515_Y + attribute \src "libresoc.v:199156.18-199156.106" + wire $reduce_or$libresoc.v:199156$14498_Y + attribute \src "libresoc.v:199158.18-199158.106" + wire $reduce_or$libresoc.v:199158$14500_Y + attribute \src "libresoc.v:199161.18-199161.106" + wire $reduce_or$libresoc.v:199161$14503_Y + attribute \src "libresoc.v:199163.18-199163.106" + wire $reduce_or$libresoc.v:199163$14505_Y + attribute \src "libresoc.v:199165.18-199165.106" + wire $reduce_or$libresoc.v:199165$14507_Y + attribute \src "libresoc.v:199167.18-199167.106" + wire $reduce_or$libresoc.v:199167$14509_Y + attribute \src "libresoc.v:199169.18-199169.106" + wire $reduce_or$libresoc.v:199169$14511_Y + attribute \src "libresoc.v:199171.18-199171.90" + wire $reduce_or$libresoc.v:199171$14513_Y + attribute \src "libresoc.v:199172.17-199172.103" + wire $reduce_or$libresoc.v:199172$14514_Y + attribute \src "libresoc.v:199174.17-199174.105" + wire $reduce_or$libresoc.v:199174$14516_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 10 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 10 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 10 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188340$14207 + wire \t9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199155$14497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:188340$14207_Y + connect \Y $not$libresoc.v:199155$14497_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188342$14209 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199157$14499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:188342$14209_Y + connect \Y $not$libresoc.v:199157$14499_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188344$14211 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199159$14501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:188344$14211_Y + connect \Y $not$libresoc.v:199159$14501_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188345$14212 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199160$14502 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:188345$14212_Y + connect \Y $not$libresoc.v:199160$14502_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188347$14214 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199162$14504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:188347$14214_Y + connect \Y $not$libresoc.v:199162$14504_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188349$14216 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199164$14506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:188349$14216_Y + connect \Y $not$libresoc.v:199164$14506_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188351$14218 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199166$14508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:188351$14218_Y + connect \Y $not$libresoc.v:199166$14508_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188353$14220 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199168$14510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:188353$14220_Y + connect \Y $not$libresoc.v:199168$14510_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188355$14222 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199170$14512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:188355$14222_Y + connect \Y $not$libresoc.v:199170$14512_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188358$14225 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199173$14515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:188358$14225_Y + connect \Y $not$libresoc.v:199173$14515_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188341$14208 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199156$14498 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188341$14208_Y + connect \Y $reduce_or$libresoc.v:199156$14498_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188343$14210 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199158$14500 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:188343$14210_Y + connect \Y $reduce_or$libresoc.v:199158$14500_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188346$14213 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199161$14503 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:188346$14213_Y + connect \Y $reduce_or$libresoc.v:199161$14503_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188348$14215 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199163$14505 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:188348$14215_Y + connect \Y $reduce_or$libresoc.v:199163$14505_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188350$14217 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199165$14507 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:188350$14217_Y + connect \Y $reduce_or$libresoc.v:199165$14507_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188352$14219 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199167$14509 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:188352$14219_Y + connect \Y $reduce_or$libresoc.v:199167$14509_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188354$14221 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199169$14511 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:188354$14221_Y + connect \Y $reduce_or$libresoc.v:199169$14511_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188356$14223 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199171$14513 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188356$14223_Y + connect \Y $reduce_or$libresoc.v:199171$14513_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188357$14224 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199172$14514 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188357$14224_Y + connect \Y $reduce_or$libresoc.v:199172$14514_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188359$14226 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199174$14516 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188359$14226_Y - end - connect \$7 $not$libresoc.v:188340$14207_Y - connect \$12 $reduce_or$libresoc.v:188341$14208_Y - connect \$11 $not$libresoc.v:188342$14209_Y - connect \$16 $reduce_or$libresoc.v:188343$14210_Y - connect \$15 $not$libresoc.v:188344$14211_Y - connect \$1 $not$libresoc.v:188345$14212_Y - connect \$20 $reduce_or$libresoc.v:188346$14213_Y - connect \$19 $not$libresoc.v:188347$14214_Y - connect \$24 $reduce_or$libresoc.v:188348$14215_Y - connect \$23 $not$libresoc.v:188349$14216_Y - connect \$28 $reduce_or$libresoc.v:188350$14217_Y - connect \$27 $not$libresoc.v:188351$14218_Y - connect \$32 $reduce_or$libresoc.v:188352$14219_Y - connect \$31 $not$libresoc.v:188353$14220_Y - connect \$36 $reduce_or$libresoc.v:188354$14221_Y - connect \$35 $not$libresoc.v:188355$14222_Y - connect \$39 $reduce_or$libresoc.v:188356$14223_Y - connect \$4 $reduce_or$libresoc.v:188357$14224_Y - connect \$3 $not$libresoc.v:188358$14225_Y - connect \$8 $reduce_or$libresoc.v:188359$14226_Y + connect \Y $reduce_or$libresoc.v:199174$14516_Y + end + connect \$7 $not$libresoc.v:199155$14497_Y + connect \$12 $reduce_or$libresoc.v:199156$14498_Y + connect \$11 $not$libresoc.v:199157$14499_Y + connect \$16 $reduce_or$libresoc.v:199158$14500_Y + connect \$15 $not$libresoc.v:199159$14501_Y + connect \$1 $not$libresoc.v:199160$14502_Y + connect \$20 $reduce_or$libresoc.v:199161$14503_Y + connect \$19 $not$libresoc.v:199162$14504_Y + connect \$24 $reduce_or$libresoc.v:199163$14505_Y + connect \$23 $not$libresoc.v:199164$14506_Y + connect \$28 $reduce_or$libresoc.v:199165$14507_Y + connect \$27 $not$libresoc.v:199166$14508_Y + connect \$32 $reduce_or$libresoc.v:199167$14509_Y + connect \$31 $not$libresoc.v:199168$14510_Y + connect \$36 $reduce_or$libresoc.v:199169$14511_Y + connect \$35 $not$libresoc.v:199170$14512_Y + connect \$39 $reduce_or$libresoc.v:199171$14513_Y + connect \$4 $reduce_or$libresoc.v:199172$14514_Y + connect \$3 $not$libresoc.v:199173$14515_Y + connect \$8 $reduce_or$libresoc.v:199174$14516_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -397537,270 +417324,270 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:188377.1-188398.10" +attribute \src "libresoc.v:199192.1-199213.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:188392.17-188392.89" - wire $not$libresoc.v:188392$14227_Y - attribute \src "libresoc.v:188393.17-188393.89" - wire $reduce_or$libresoc.v:188393$14228_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199207.17-199207.89" + wire $not$libresoc.v:199207$14517_Y + attribute \src "libresoc.v:199208.17-199208.89" + wire $reduce_or$libresoc.v:199208$14518_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188392$14227 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199207$14517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:188392$14227_Y + connect \Y $not$libresoc.v:199207$14517_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188393$14228 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199208$14518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188393$14228_Y + connect \Y $reduce_or$libresoc.v:199208$14518_Y end - connect \$1 $not$libresoc.v:188392$14227_Y - connect \$3 $reduce_or$libresoc.v:188393$14228_Y + connect \$1 $not$libresoc.v:199207$14517_Y + connect \$3 $reduce_or$libresoc.v:199208$14518_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:188402.1-188423.10" +attribute \src "libresoc.v:199217.1-199238.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:188417.17-188417.89" - wire $not$libresoc.v:188417$14229_Y - attribute \src "libresoc.v:188418.17-188418.89" - wire $reduce_or$libresoc.v:188418$14230_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199232.17-199232.89" + wire $not$libresoc.v:199232$14519_Y + attribute \src "libresoc.v:199233.17-199233.89" + wire $reduce_or$libresoc.v:199233$14520_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188417$14229 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199232$14519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:188417$14229_Y + connect \Y $not$libresoc.v:199232$14519_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188418$14230 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199233$14520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188418$14230_Y + connect \Y $reduce_or$libresoc.v:199233$14520_Y end - connect \$1 $not$libresoc.v:188417$14229_Y - connect \$3 $reduce_or$libresoc.v:188418$14230_Y + connect \$1 $not$libresoc.v:199232$14519_Y + connect \$3 $reduce_or$libresoc.v:199233$14520_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:188427.1-188457.10" +attribute \src "libresoc.v:199242.1-199272.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:188448.17-188448.89" - wire width 2 $not$libresoc.v:188448$14231_Y - attribute \src "libresoc.v:188450.17-188450.91" - wire $not$libresoc.v:188450$14233_Y - attribute \src "libresoc.v:188449.17-188449.103" - wire $reduce_or$libresoc.v:188449$14232_Y - attribute \src "libresoc.v:188451.17-188451.89" - wire $reduce_or$libresoc.v:188451$14234_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199263.17-199263.89" + wire width 2 $not$libresoc.v:199263$14521_Y + attribute \src "libresoc.v:199265.17-199265.91" + wire $not$libresoc.v:199265$14523_Y + attribute \src "libresoc.v:199264.17-199264.103" + wire $reduce_or$libresoc.v:199264$14522_Y + attribute \src "libresoc.v:199266.17-199266.89" + wire $reduce_or$libresoc.v:199266$14524_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188448$14231 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199263$14521 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:188448$14231_Y + connect \Y $not$libresoc.v:199263$14521_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188450$14233 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199265$14523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:188450$14233_Y + connect \Y $not$libresoc.v:199265$14523_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188449$14232 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199264$14522 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188449$14232_Y + connect \Y $reduce_or$libresoc.v:199264$14522_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188451$14234 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199266$14524 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188451$14234_Y + connect \Y $reduce_or$libresoc.v:199266$14524_Y end - connect \$1 $not$libresoc.v:188448$14231_Y - connect \$4 $reduce_or$libresoc.v:188449$14232_Y - connect \$3 $not$libresoc.v:188450$14233_Y - connect \$7 $reduce_or$libresoc.v:188451$14234_Y + connect \$1 $not$libresoc.v:199263$14521_Y + connect \$4 $reduce_or$libresoc.v:199264$14522_Y + connect \$3 $not$libresoc.v:199265$14523_Y + connect \$7 $reduce_or$libresoc.v:199266$14524_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:188461.1-188500.10" +attribute \src "libresoc.v:199276.1-199315.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:188488.17-188488.91" - wire $not$libresoc.v:188488$14235_Y - attribute \src "libresoc.v:188490.17-188490.89" - wire width 3 $not$libresoc.v:188490$14237_Y - attribute \src "libresoc.v:188492.17-188492.91" - wire $not$libresoc.v:188492$14239_Y - attribute \src "libresoc.v:188489.18-188489.90" - wire $reduce_or$libresoc.v:188489$14236_Y - attribute \src "libresoc.v:188491.17-188491.103" - wire $reduce_or$libresoc.v:188491$14238_Y - attribute \src "libresoc.v:188493.17-188493.105" - wire $reduce_or$libresoc.v:188493$14240_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199303.17-199303.91" + wire $not$libresoc.v:199303$14525_Y + attribute \src "libresoc.v:199305.17-199305.89" + wire width 3 $not$libresoc.v:199305$14527_Y + attribute \src "libresoc.v:199307.17-199307.91" + wire $not$libresoc.v:199307$14529_Y + attribute \src "libresoc.v:199304.18-199304.90" + wire $reduce_or$libresoc.v:199304$14526_Y + attribute \src "libresoc.v:199306.17-199306.103" + wire $reduce_or$libresoc.v:199306$14528_Y + attribute \src "libresoc.v:199308.17-199308.105" + wire $reduce_or$libresoc.v:199308$14530_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188488$14235 + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199303$14525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:188488$14235_Y + connect \Y $not$libresoc.v:199303$14525_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188490$14237 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199305$14527 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:188490$14237_Y + connect \Y $not$libresoc.v:199305$14527_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188492$14239 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199307$14529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:188492$14239_Y + connect \Y $not$libresoc.v:199307$14529_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188489$14236 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199304$14526 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188489$14236_Y + connect \Y $reduce_or$libresoc.v:199304$14526_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188491$14238 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199306$14528 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188491$14238_Y + connect \Y $reduce_or$libresoc.v:199306$14528_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188493$14240 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199308$14530 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188493$14240_Y - end - connect \$7 $not$libresoc.v:188488$14235_Y - connect \$11 $reduce_or$libresoc.v:188489$14236_Y - connect \$1 $not$libresoc.v:188490$14237_Y - connect \$4 $reduce_or$libresoc.v:188491$14238_Y - connect \$3 $not$libresoc.v:188492$14239_Y - connect \$8 $reduce_or$libresoc.v:188493$14240_Y + connect \Y $reduce_or$libresoc.v:199308$14530_Y + end + connect \$7 $not$libresoc.v:199303$14525_Y + connect \$11 $reduce_or$libresoc.v:199304$14526_Y + connect \$1 $not$libresoc.v:199305$14527_Y + connect \$4 $reduce_or$libresoc.v:199306$14528_Y + connect \$3 $not$libresoc.v:199307$14529_Y + connect \$8 $reduce_or$libresoc.v:199308$14530_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -397808,131 +417595,131 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:188504.1-188552.10" +attribute \src "libresoc.v:199319.1-199367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:188537.17-188537.91" - wire $not$libresoc.v:188537$14241_Y - attribute \src "libresoc.v:188539.18-188539.93" - wire $not$libresoc.v:188539$14243_Y - attribute \src "libresoc.v:188541.17-188541.89" - wire width 4 $not$libresoc.v:188541$14245_Y - attribute \src "libresoc.v:188543.17-188543.91" - wire $not$libresoc.v:188543$14247_Y - attribute \src "libresoc.v:188538.18-188538.106" - wire $reduce_or$libresoc.v:188538$14242_Y - attribute \src "libresoc.v:188540.18-188540.90" - wire $reduce_or$libresoc.v:188540$14244_Y - attribute \src "libresoc.v:188542.17-188542.103" - wire $reduce_or$libresoc.v:188542$14246_Y - attribute \src "libresoc.v:188544.17-188544.105" - wire $reduce_or$libresoc.v:188544$14248_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199352.17-199352.91" + wire $not$libresoc.v:199352$14531_Y + attribute \src "libresoc.v:199354.18-199354.93" + wire $not$libresoc.v:199354$14533_Y + attribute \src "libresoc.v:199356.17-199356.89" + wire width 4 $not$libresoc.v:199356$14535_Y + attribute \src "libresoc.v:199358.17-199358.91" + wire $not$libresoc.v:199358$14537_Y + attribute \src "libresoc.v:199353.18-199353.106" + wire $reduce_or$libresoc.v:199353$14532_Y + attribute \src "libresoc.v:199355.18-199355.90" + wire $reduce_or$libresoc.v:199355$14534_Y + attribute \src "libresoc.v:199357.17-199357.103" + wire $reduce_or$libresoc.v:199357$14536_Y + attribute \src "libresoc.v:199359.17-199359.105" + wire $reduce_or$libresoc.v:199359$14538_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 4 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188537$14241 + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199352$14531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:188537$14241_Y + connect \Y $not$libresoc.v:199352$14531_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188539$14243 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199354$14533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:188539$14243_Y + connect \Y $not$libresoc.v:199354$14533_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188541$14245 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199356$14535 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:188541$14245_Y + connect \Y $not$libresoc.v:199356$14535_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188543$14247 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199358$14537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:188543$14247_Y + connect \Y $not$libresoc.v:199358$14537_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188538$14242 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199353$14532 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188538$14242_Y + connect \Y $reduce_or$libresoc.v:199353$14532_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188540$14244 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199355$14534 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188540$14244_Y + connect \Y $reduce_or$libresoc.v:199355$14534_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188542$14246 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199357$14536 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188542$14246_Y + connect \Y $reduce_or$libresoc.v:199357$14536_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188544$14248 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199359$14538 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188544$14248_Y - end - connect \$7 $not$libresoc.v:188537$14241_Y - connect \$12 $reduce_or$libresoc.v:188538$14242_Y - connect \$11 $not$libresoc.v:188539$14243_Y - connect \$15 $reduce_or$libresoc.v:188540$14244_Y - connect \$1 $not$libresoc.v:188541$14245_Y - connect \$4 $reduce_or$libresoc.v:188542$14246_Y - connect \$3 $not$libresoc.v:188543$14247_Y - connect \$8 $reduce_or$libresoc.v:188544$14248_Y + connect \Y $reduce_or$libresoc.v:199359$14538_Y + end + connect \$7 $not$libresoc.v:199352$14531_Y + connect \$12 $reduce_or$libresoc.v:199353$14532_Y + connect \$11 $not$libresoc.v:199354$14533_Y + connect \$15 $reduce_or$libresoc.v:199355$14534_Y + connect \$1 $not$libresoc.v:199356$14535_Y + connect \$4 $reduce_or$libresoc.v:199357$14536_Y + connect \$3 $not$libresoc.v:199358$14537_Y + connect \$8 $reduce_or$libresoc.v:199359$14538_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -397941,131 +417728,131 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:188556.1-188604.10" +attribute \src "libresoc.v:199371.1-199419.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:188589.17-188589.91" - wire $not$libresoc.v:188589$14249_Y - attribute \src "libresoc.v:188591.18-188591.93" - wire $not$libresoc.v:188591$14251_Y - attribute \src "libresoc.v:188593.17-188593.89" - wire width 4 $not$libresoc.v:188593$14253_Y - attribute \src "libresoc.v:188595.17-188595.91" - wire $not$libresoc.v:188595$14255_Y - attribute \src "libresoc.v:188590.18-188590.106" - wire $reduce_or$libresoc.v:188590$14250_Y - attribute \src "libresoc.v:188592.18-188592.90" - wire $reduce_or$libresoc.v:188592$14252_Y - attribute \src "libresoc.v:188594.17-188594.103" - wire $reduce_or$libresoc.v:188594$14254_Y - attribute \src "libresoc.v:188596.17-188596.105" - wire $reduce_or$libresoc.v:188596$14256_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + attribute \src "libresoc.v:199404.17-199404.91" + wire $not$libresoc.v:199404$14539_Y + attribute \src "libresoc.v:199406.18-199406.93" + wire $not$libresoc.v:199406$14541_Y + attribute \src "libresoc.v:199408.17-199408.89" + wire width 4 $not$libresoc.v:199408$14543_Y + attribute \src "libresoc.v:199410.17-199410.91" + wire $not$libresoc.v:199410$14545_Y + attribute \src "libresoc.v:199405.18-199405.106" + wire $reduce_or$libresoc.v:199405$14540_Y + attribute \src "libresoc.v:199407.18-199407.90" + wire $reduce_or$libresoc.v:199407$14542_Y + attribute \src "libresoc.v:199409.17-199409.103" + wire $reduce_or$libresoc.v:199409$14544_Y + attribute \src "libresoc.v:199411.17-199411.105" + wire $reduce_or$libresoc.v:199411$14546_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 4 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188589$14249 + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199404$14539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:188589$14249_Y + connect \Y $not$libresoc.v:199404$14539_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188591$14251 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199406$14541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:188591$14251_Y + connect \Y $not$libresoc.v:199406$14541_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188593$14253 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:199408$14543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:188593$14253_Y + connect \Y $not$libresoc.v:199408$14543_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188595$14255 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:199410$14545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:188595$14255_Y + connect \Y $not$libresoc.v:199410$14545_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188590$14250 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199405$14540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188590$14250_Y + connect \Y $reduce_or$libresoc.v:199405$14540_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188592$14252 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:199407$14542 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:188592$14252_Y + connect \Y $reduce_or$libresoc.v:199407$14542_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188594$14254 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199409$14544 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188594$14254_Y + connect \Y $reduce_or$libresoc.v:199409$14544_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188596$14256 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:199411$14546 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188596$14256_Y - end - connect \$7 $not$libresoc.v:188589$14249_Y - connect \$12 $reduce_or$libresoc.v:188590$14250_Y - connect \$11 $not$libresoc.v:188591$14251_Y - connect \$15 $reduce_or$libresoc.v:188592$14252_Y - connect \$1 $not$libresoc.v:188593$14253_Y - connect \$4 $reduce_or$libresoc.v:188594$14254_Y - connect \$3 $not$libresoc.v:188595$14255_Y - connect \$8 $reduce_or$libresoc.v:188596$14256_Y + connect \Y $reduce_or$libresoc.v:199411$14546_Y + end + connect \$7 $not$libresoc.v:199404$14539_Y + connect \$12 $reduce_or$libresoc.v:199405$14540_Y + connect \$11 $not$libresoc.v:199406$14541_Y + connect \$15 $reduce_or$libresoc.v:199407$14542_Y + connect \$1 $not$libresoc.v:199408$14543_Y + connect \$4 $reduce_or$libresoc.v:199409$14544_Y + connect \$3 $not$libresoc.v:199410$14545_Y + connect \$8 $reduce_or$libresoc.v:199411$14546_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -398074,200 +417861,200 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:188608.1-188928.10" +attribute \src "libresoc.v:199423.1-199743.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:188609.7-188609.20" + attribute \src "libresoc.v:199424.7-199424.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188888.3-188896.6" - wire width 3 $0\ren_delay$11$next[2:0]$14280 - attribute \src "libresoc.v:188786.3-188787.43" - wire width 3 $0\ren_delay$11[2:0]$14269 - attribute \src "libresoc.v:188745.13-188745.34" - wire width 3 $0\ren_delay$11[2:0]$14286 - attribute \src "libresoc.v:188850.3-188858.6" - wire width 3 $0\ren_delay$18$next[2:0]$14272 - attribute \src "libresoc.v:188784.3-188785.43" - wire width 3 $0\ren_delay$18[2:0]$14267 - attribute \src "libresoc.v:188749.13-188749.34" - wire width 3 $0\ren_delay$18[2:0]$14288 - attribute \src "libresoc.v:188869.3-188877.6" - wire width 3 $0\ren_delay$next[2:0]$14276 - attribute \src "libresoc.v:188788.3-188789.35" + attribute \src "libresoc.v:199703.3-199711.6" + wire width 3 $0\ren_delay$11$next[2:0]$14570 + attribute \src "libresoc.v:199601.3-199602.43" + wire width 3 $0\ren_delay$11[2:0]$14559 + attribute \src "libresoc.v:199560.13-199560.34" + wire width 3 $0\ren_delay$11[2:0]$14576 + attribute \src "libresoc.v:199665.3-199673.6" + wire width 3 $0\ren_delay$18$next[2:0]$14562 + attribute \src "libresoc.v:199599.3-199600.43" + wire width 3 $0\ren_delay$18[2:0]$14557 + attribute \src "libresoc.v:199564.13-199564.34" + wire width 3 $0\ren_delay$18[2:0]$14578 + attribute \src "libresoc.v:199684.3-199692.6" + wire width 3 $0\ren_delay$next[2:0]$14566 + attribute \src "libresoc.v:199603.3-199604.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:188878.3-188887.6" + attribute \src "libresoc.v:199693.3-199702.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:188897.3-188906.6" + attribute \src "libresoc.v:199712.3-199721.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:188859.3-188868.6" + attribute \src "libresoc.v:199674.3-199683.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:188888.3-188896.6" - wire width 3 $1\ren_delay$11$next[2:0]$14281 - attribute \src "libresoc.v:188850.3-188858.6" - wire width 3 $1\ren_delay$18$next[2:0]$14273 - attribute \src "libresoc.v:188869.3-188877.6" - wire width 3 $1\ren_delay$next[2:0]$14277 - attribute \src "libresoc.v:188743.13-188743.29" + attribute \src "libresoc.v:199703.3-199711.6" + wire width 3 $1\ren_delay$11$next[2:0]$14571 + attribute \src "libresoc.v:199665.3-199673.6" + wire width 3 $1\ren_delay$18$next[2:0]$14563 + attribute \src "libresoc.v:199684.3-199692.6" + wire width 3 $1\ren_delay$next[2:0]$14567 + attribute \src "libresoc.v:199558.13-199558.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:188878.3-188887.6" + attribute \src "libresoc.v:199693.3-199702.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:188897.3-188906.6" + attribute \src "libresoc.v:199712.3-199721.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:188859.3-188868.6" + attribute \src "libresoc.v:199674.3-199683.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:188775.17-188775.109" - wire width 2 $or$libresoc.v:188775$14257_Y - attribute \src "libresoc.v:188777.18-188777.126" - wire width 2 $or$libresoc.v:188777$14259_Y - attribute \src "libresoc.v:188778.18-188778.111" - wire width 2 $or$libresoc.v:188778$14260_Y - attribute \src "libresoc.v:188780.18-188780.126" - wire width 2 $or$libresoc.v:188780$14262_Y - attribute \src "libresoc.v:188781.18-188781.111" - wire width 2 $or$libresoc.v:188781$14263_Y - attribute \src "libresoc.v:188783.17-188783.125" - wire width 2 $or$libresoc.v:188783$14265_Y - attribute \src "libresoc.v:188776.18-188776.100" - wire $reduce_or$libresoc.v:188776$14258_Y - attribute \src "libresoc.v:188779.18-188779.100" - wire $reduce_or$libresoc.v:188779$14261_Y - attribute \src "libresoc.v:188782.17-188782.95" - wire $reduce_or$libresoc.v:188782$14264_Y + attribute \src "libresoc.v:199590.17-199590.109" + wire width 2 $or$libresoc.v:199590$14547_Y + attribute \src "libresoc.v:199592.18-199592.126" + wire width 2 $or$libresoc.v:199592$14549_Y + attribute \src "libresoc.v:199593.18-199593.111" + wire width 2 $or$libresoc.v:199593$14550_Y + attribute \src "libresoc.v:199595.18-199595.126" + wire width 2 $or$libresoc.v:199595$14552_Y + attribute \src "libresoc.v:199596.18-199596.111" + wire width 2 $or$libresoc.v:199596$14553_Y + attribute \src "libresoc.v:199598.17-199598.125" + wire width 2 $or$libresoc.v:199598$14555_Y + attribute \src "libresoc.v:199591.18-199591.100" + wire $reduce_or$libresoc.v:199591$14548_Y + attribute \src "libresoc.v:199594.18-199594.100" + wire $reduce_or$libresoc.v:199594$14551_Y + attribute \src "libresoc.v:199597.17-199597.95" + wire $reduce_or$libresoc.v:199597$14554_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$16 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$23 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 12 \data_i$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 14 \data_i$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 6 output 3 \full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 6 \full_wr__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:188609.7-188609.15" + attribute \src "libresoc.v:199424.7-199424.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest30__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest30__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_w0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_dest31__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest31__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_w1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest32__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay @@ -398281,26 +418068,26 @@ module \xer wire width 3 \ren_delay$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 4 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 5 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 6 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 7 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 8 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 9 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 11 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 13 \wen$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:188775$14257 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:199590$14547 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -398308,10 +418095,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:188775$14257_Y + connect \Y $or$libresoc.v:199590$14547_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:188777$14259 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:199592$14549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -398319,10 +418106,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:188777$14259_Y + connect \Y $or$libresoc.v:199592$14549_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:188778$14260 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:199593$14550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -398330,10 +418117,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:188778$14260_Y + connect \Y $or$libresoc.v:199593$14550_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:188780$14262 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:199595$14552 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -398341,10 +418128,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:188780$14262_Y + connect \Y $or$libresoc.v:199595$14552_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:188781$14263 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:199596$14553 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -398352,10 +418139,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:188781$14263_Y + connect \Y $or$libresoc.v:199596$14553_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:188783$14265 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:199598$14555 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -398363,34 +418150,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:188783$14265_Y + connect \Y $or$libresoc.v:199598$14555_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188776$14258 + cell $reduce_or $reduce_or$libresoc.v:199591$14548 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:188776$14258_Y + connect \Y $reduce_or$libresoc.v:199591$14548_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188779$14261 + cell $reduce_or $reduce_or$libresoc.v:199594$14551 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:188779$14261_Y + connect \Y $reduce_or$libresoc.v:199594$14551_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188782$14264 + cell $reduce_or $reduce_or$libresoc.v:199597$14554 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:188782$14264_Y + connect \Y $reduce_or$libresoc.v:199597$14554_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:188790.15-188809.4" + attribute \src "libresoc.v:199605.15-199624.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -398412,7 +418199,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:188810.15-188829.4" + attribute \src "libresoc.v:199625.15-199644.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -398434,7 +418221,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:188830.15-188849.4" + attribute \src "libresoc.v:199645.15-199664.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -398455,67 +418242,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:188609.7-188609.20" - process $proc$libresoc.v:188609$14283 + attribute \src "libresoc.v:199424.7-199424.20" + process $proc$libresoc.v:199424$14573 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188743.13-188743.29" - process $proc$libresoc.v:188743$14284 + attribute \src "libresoc.v:199558.13-199558.29" + process $proc$libresoc.v:199558$14574 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:188745.13-188745.34" - process $proc$libresoc.v:188745$14285 + attribute \src "libresoc.v:199560.13-199560.34" + process $proc$libresoc.v:199560$14575 assign { } { } - assign $0\ren_delay$11[2:0]$14286 3'000 + assign $0\ren_delay$11[2:0]$14576 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14286 + update \ren_delay$11 $0\ren_delay$11[2:0]$14576 end - attribute \src "libresoc.v:188749.13-188749.34" - process $proc$libresoc.v:188749$14287 + attribute \src "libresoc.v:199564.13-199564.34" + process $proc$libresoc.v:199564$14577 assign { } { } - assign $0\ren_delay$18[2:0]$14288 3'000 + assign $0\ren_delay$18[2:0]$14578 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14288 + update \ren_delay$18 $0\ren_delay$18[2:0]$14578 end - attribute \src "libresoc.v:188784.3-188785.43" - process $proc$libresoc.v:188784$14266 + attribute \src "libresoc.v:199599.3-199600.43" + process $proc$libresoc.v:199599$14556 assign { } { } - assign $0\ren_delay$18[2:0]$14267 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14557 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14267 + update \ren_delay$18 $0\ren_delay$18[2:0]$14557 end - attribute \src "libresoc.v:188786.3-188787.43" - process $proc$libresoc.v:188786$14268 + attribute \src "libresoc.v:199601.3-199602.43" + process $proc$libresoc.v:199601$14558 assign { } { } - assign $0\ren_delay$11[2:0]$14269 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14559 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14269 + update \ren_delay$11 $0\ren_delay$11[2:0]$14559 end - attribute \src "libresoc.v:188788.3-188789.35" - process $proc$libresoc.v:188788$14270 + attribute \src "libresoc.v:199603.3-199604.35" + process $proc$libresoc.v:199603$14560 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:188850.3-188858.6" - process $proc$libresoc.v:188850$14271 + attribute \src "libresoc.v:199665.3-199673.6" + process $proc$libresoc.v:199665$14561 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14272 $1\ren_delay$18$next[2:0]$14273 - attribute \src "libresoc.v:188851.5-188851.29" + assign $0\ren_delay$18$next[2:0]$14562 $1\ren_delay$18$next[2:0]$14563 + attribute \src "libresoc.v:199666.5-199666.29" switch \initial - attribute \src "libresoc.v:188851.9-188851.17" + attribute \src "libresoc.v:199666.9-199666.17" case 1'1 case end @@ -398524,21 +418311,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14273 3'000 + assign $1\ren_delay$18$next[2:0]$14563 3'000 case - assign $1\ren_delay$18$next[2:0]$14273 \src3__ren + assign $1\ren_delay$18$next[2:0]$14563 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14272 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14562 end - attribute \src "libresoc.v:188859.3-188868.6" - process $proc$libresoc.v:188859$14274 + attribute \src "libresoc.v:199674.3-199683.6" + process $proc$libresoc.v:199674$14564 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:188860.5-188860.29" + attribute \src "libresoc.v:199675.5-199675.29" switch \initial - attribute \src "libresoc.v:188860.9-188860.17" + attribute \src "libresoc.v:199675.9-199675.17" case 1'1 case end @@ -398554,14 +418341,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:188869.3-188877.6" - process $proc$libresoc.v:188869$14275 + attribute \src "libresoc.v:199684.3-199692.6" + process $proc$libresoc.v:199684$14565 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14276 $1\ren_delay$next[2:0]$14277 - attribute \src "libresoc.v:188870.5-188870.29" + assign $0\ren_delay$next[2:0]$14566 $1\ren_delay$next[2:0]$14567 + attribute \src "libresoc.v:199685.5-199685.29" switch \initial - attribute \src "libresoc.v:188870.9-188870.17" + attribute \src "libresoc.v:199685.9-199685.17" case 1'1 case end @@ -398570,21 +418357,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14277 3'000 + assign $1\ren_delay$next[2:0]$14567 3'000 case - assign $1\ren_delay$next[2:0]$14277 \src1__ren + assign $1\ren_delay$next[2:0]$14567 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14276 + update \ren_delay$next $0\ren_delay$next[2:0]$14566 end - attribute \src "libresoc.v:188878.3-188887.6" - process $proc$libresoc.v:188878$14278 + attribute \src "libresoc.v:199693.3-199702.6" + process $proc$libresoc.v:199693$14568 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:188879.5-188879.29" + attribute \src "libresoc.v:199694.5-199694.29" switch \initial - attribute \src "libresoc.v:188879.9-188879.17" + attribute \src "libresoc.v:199694.9-199694.17" case 1'1 case end @@ -398600,14 +418387,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:188888.3-188896.6" - process $proc$libresoc.v:188888$14279 + attribute \src "libresoc.v:199703.3-199711.6" + process $proc$libresoc.v:199703$14569 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14280 $1\ren_delay$11$next[2:0]$14281 - attribute \src "libresoc.v:188889.5-188889.29" + assign $0\ren_delay$11$next[2:0]$14570 $1\ren_delay$11$next[2:0]$14571 + attribute \src "libresoc.v:199704.5-199704.29" switch \initial - attribute \src "libresoc.v:188889.9-188889.17" + attribute \src "libresoc.v:199704.9-199704.17" case 1'1 case end @@ -398616,21 +418403,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14281 3'000 + assign $1\ren_delay$11$next[2:0]$14571 3'000 case - assign $1\ren_delay$11$next[2:0]$14281 \src2__ren + assign $1\ren_delay$11$next[2:0]$14571 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14280 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14570 end - attribute \src "libresoc.v:188897.3-188906.6" - process $proc$libresoc.v:188897$14282 + attribute \src "libresoc.v:199712.3-199721.6" + process $proc$libresoc.v:199712$14572 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:188898.5-188898.29" + attribute \src "libresoc.v:199713.5-199713.29" switch \initial - attribute \src "libresoc.v:188898.9-188898.17" + attribute \src "libresoc.v:199713.9-199713.17" case 1'1 case end @@ -398646,15 +418433,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:188775$14257_Y - connect \$12 $reduce_or$libresoc.v:188776$14258_Y - connect \$14 $or$libresoc.v:188777$14259_Y - connect \$16 $or$libresoc.v:188778$14260_Y - connect \$19 $reduce_or$libresoc.v:188779$14261_Y - connect \$21 $or$libresoc.v:188780$14262_Y - connect \$23 $or$libresoc.v:188781$14263_Y - connect \$5 $reduce_or$libresoc.v:188782$14264_Y - connect \$7 $or$libresoc.v:188783$14265_Y + connect \$9 $or$libresoc.v:199590$14547_Y + connect \$12 $reduce_or$libresoc.v:199591$14548_Y + connect \$14 $or$libresoc.v:199592$14549_Y + connect \$16 $or$libresoc.v:199593$14550_Y + connect \$19 $reduce_or$libresoc.v:199594$14551_Y + connect \$21 $or$libresoc.v:199595$14552_Y + connect \$23 $or$libresoc.v:199596$14553_Y + connect \$5 $reduce_or$libresoc.v:199597$14554_Y + connect \$7 $or$libresoc.v:199598$14555_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -398677,153 +418464,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:188932.1-189246.10" +attribute \src "libresoc.v:199747.1-200061.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:189110.3-189138.6" + attribute \src "libresoc.v:199925.3-199953.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:189161.3-189169.6" - wire $0\core_irq_o$next[0:0]$14324 - attribute \src "libresoc.v:189052.3-189053.37" + attribute \src "libresoc.v:199976.3-199984.6" + wire $0\core_irq_o$next[0:0]$14614 + attribute \src "libresoc.v:199867.3-199868.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $0\cppr$10[7:0]$14328 - attribute \src "libresoc.v:189066.3-189081.6" - wire width 8 $0\cppr$next[7:0]$14307 - attribute \src "libresoc.v:189056.3-189057.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $0\cppr$10[7:0]$14618 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 8 $0\cppr$next[7:0]$14597 + attribute \src "libresoc.v:199871.3-199872.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:189170.3-189179.6" + attribute \src "libresoc.v:199985.3-199994.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:188933.7-188933.20" + attribute \src "libresoc.v:199748.7-199748.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire $0\irq$12[0:0]$14329 - attribute \src "libresoc.v:189066.3-189081.6" - wire $0\irq$next[0:0]$14308 - attribute \src "libresoc.v:189060.3-189061.23" + attribute \src "libresoc.v:199995.3-200057.6" + wire $0\irq$12[0:0]$14619 + attribute \src "libresoc.v:199881.3-199896.6" + wire $0\irq$next[0:0]$14598 + attribute \src "libresoc.v:199875.3-199876.23" wire $0\irq[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $0\mfrr$11[7:0]$14330 - attribute \src "libresoc.v:189066.3-189081.6" - wire width 8 $0\mfrr$next[7:0]$14309 - attribute \src "libresoc.v:189058.3-189059.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $0\mfrr$11[7:0]$14620 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 8 $0\mfrr$next[7:0]$14599 + attribute \src "libresoc.v:199873.3-199874.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:189149.3-189160.6" + attribute \src "libresoc.v:199964.3-199975.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:189139.3-189148.6" + attribute \src "libresoc.v:199954.3-199963.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire $0\wb_ack$14[0:0]$14331 - attribute \src "libresoc.v:189066.3-189081.6" - wire $0\wb_ack$next[0:0]$14310 - attribute \src "libresoc.v:189064.3-189065.29" + attribute \src "libresoc.v:199995.3-200057.6" + wire $0\wb_ack$14[0:0]$14621 + attribute \src "libresoc.v:199881.3-199896.6" + wire $0\wb_ack$next[0:0]$14600 + attribute \src "libresoc.v:199879.3-199880.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 32 $0\wb_rd_data$13[31:0]$14332 - attribute \src "libresoc.v:189066.3-189081.6" - wire width 32 $0\wb_rd_data$next[31:0]$14311 - attribute \src "libresoc.v:189062.3-189063.37" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 32 $0\wb_rd_data$13[31:0]$14622 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 32 $0\wb_rd_data$next[31:0]$14601 + attribute \src "libresoc.v:199877.3-199878.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:189082.3-189109.6" + attribute \src "libresoc.v:199897.3-199924.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 24 $0\xisr$9[23:0]$14333 - attribute \src "libresoc.v:189066.3-189081.6" - wire width 24 $0\xisr$next[23:0]$14312 - attribute \src "libresoc.v:189054.3-189055.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 24 $0\xisr$9[23:0]$14623 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 24 $0\xisr$next[23:0]$14602 + attribute \src "libresoc.v:199869.3-199870.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:189110.3-189138.6" + attribute \src "libresoc.v:199925.3-199953.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:189161.3-189169.6" - wire $1\core_irq_o$next[0:0]$14325 - attribute \src "libresoc.v:188962.7-188962.24" + attribute \src "libresoc.v:199976.3-199984.6" + wire $1\core_irq_o$next[0:0]$14615 + attribute \src "libresoc.v:199777.7-199777.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $1\cppr$10[7:0]$14334 - attribute \src "libresoc.v:189066.3-189081.6" - wire width 8 $1\cppr$next[7:0]$14313 - attribute \src "libresoc.v:188966.13-188966.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $1\cppr$10[7:0]$14624 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 8 $1\cppr$next[7:0]$14603 + attribute \src "libresoc.v:199781.13-199781.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:189170.3-189179.6" + attribute \src "libresoc.v:199985.3-199994.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire $1\irq$12[0:0]$14344 - attribute \src "libresoc.v:189066.3-189081.6" - wire $1\irq$next[0:0]$14314 - attribute \src "libresoc.v:188995.7-188995.17" + attribute \src "libresoc.v:199995.3-200057.6" + wire $1\irq$12[0:0]$14634 + attribute \src "libresoc.v:199881.3-199896.6" + wire $1\irq$next[0:0]$14604 + attribute \src "libresoc.v:199810.7-199810.17" wire $1\irq[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $1\mfrr$11[7:0]$14335 - attribute \src "libresoc.v:189066.3-189081.6" - wire width 8 $1\mfrr$next[7:0]$14315 - attribute \src "libresoc.v:189003.13-189003.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $1\mfrr$11[7:0]$14625 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 8 $1\mfrr$next[7:0]$14605 + attribute \src "libresoc.v:199818.13-199818.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:189149.3-189160.6" + attribute \src "libresoc.v:199964.3-199975.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:189139.3-189148.6" + attribute \src "libresoc.v:199954.3-199963.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire $1\wb_ack$14[0:0]$14336 - attribute \src "libresoc.v:189066.3-189081.6" - wire $1\wb_ack$next[0:0]$14316 - attribute \src "libresoc.v:189017.7-189017.20" + attribute \src "libresoc.v:199995.3-200057.6" + wire $1\wb_ack$14[0:0]$14626 + attribute \src "libresoc.v:199881.3-199896.6" + wire $1\wb_ack$next[0:0]$14606 + attribute \src "libresoc.v:199832.7-199832.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:189066.3-189081.6" - wire width 32 $1\wb_rd_data$next[31:0]$14317 - attribute \src "libresoc.v:189025.14-189025.32" + attribute \src "libresoc.v:199881.3-199896.6" + wire width 32 $1\wb_rd_data$next[31:0]$14607 + attribute \src "libresoc.v:199840.14-199840.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:189082.3-189109.6" + attribute \src "libresoc.v:199897.3-199924.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 24 $1\xisr$9[23:0]$14341 - attribute \src "libresoc.v:189066.3-189081.6" - wire width 24 $1\xisr$next[23:0]$14318 - attribute \src "libresoc.v:189035.14-189035.31" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 24 $1\xisr$9[23:0]$14631 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 24 $1\xisr$next[23:0]$14608 + attribute \src "libresoc.v:199850.14-199850.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:189110.3-189138.6" + attribute \src "libresoc.v:199925.3-199953.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $2\cppr$10[7:0]$14337 - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $2\mfrr$11[7:0]$14338 - attribute \src "libresoc.v:189082.3-189109.6" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $2\cppr$10[7:0]$14627 + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $2\mfrr$11[7:0]$14628 + attribute \src "libresoc.v:199897.3-199924.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 24 $2\xisr$9[23:0]$14342 - attribute \src "libresoc.v:189110.3-189138.6" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 24 $2\xisr$9[23:0]$14632 + attribute \src "libresoc.v:199925.3-199953.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $3\cppr$10[7:0]$14339 - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $3\mfrr$11[7:0]$14340 - attribute \src "libresoc.v:189082.3-189109.6" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $3\cppr$10[7:0]$14629 + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $3\mfrr$11[7:0]$14630 + attribute \src "libresoc.v:199897.3-199924.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189180.3-189242.6" - wire width 8 $4\cppr$10[7:0]$14343 - attribute \src "libresoc.v:189082.3-189109.6" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $4\cppr$10[7:0]$14633 + attribute \src "libresoc.v:199897.3-199924.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189042.18-189042.116" - wire $and$libresoc.v:189042$14289_Y - attribute \src "libresoc.v:189046.18-189046.116" - wire $and$libresoc.v:189046$14293_Y - attribute \src "libresoc.v:189048.18-189048.116" - wire $and$libresoc.v:189048$14295_Y - attribute \src "libresoc.v:189051.17-189051.109" - wire $and$libresoc.v:189051$14298_Y - attribute \src "libresoc.v:189047.18-189047.110" - wire $eq$libresoc.v:189047$14294_Y - attribute \src "libresoc.v:189044.18-189044.114" - wire $lt$libresoc.v:189044$14291_Y - attribute \src "libresoc.v:189045.18-189045.109" - wire $lt$libresoc.v:189045$14292_Y - attribute \src "libresoc.v:189050.18-189050.114" - wire $lt$libresoc.v:189050$14297_Y - attribute \src "libresoc.v:189043.18-189043.109" - wire $ne$libresoc.v:189043$14290_Y - attribute \src "libresoc.v:189049.18-189049.109" - wire $ne$libresoc.v:189049$14296_Y + attribute \src "libresoc.v:199857.18-199857.116" + wire $and$libresoc.v:199857$14579_Y + attribute \src "libresoc.v:199861.18-199861.116" + wire $and$libresoc.v:199861$14583_Y + attribute \src "libresoc.v:199863.18-199863.116" + wire $and$libresoc.v:199863$14585_Y + attribute \src "libresoc.v:199866.17-199866.109" + wire $and$libresoc.v:199866$14588_Y + attribute \src "libresoc.v:199862.18-199862.110" + wire $eq$libresoc.v:199862$14584_Y + attribute \src "libresoc.v:199859.18-199859.114" + wire $lt$libresoc.v:199859$14581_Y + attribute \src "libresoc.v:199860.18-199860.109" + wire $lt$libresoc.v:199860$14582_Y + attribute \src "libresoc.v:199865.18-199865.114" + wire $lt$libresoc.v:199865$14587_Y + attribute \src "libresoc.v:199858.18-199858.109" + wire $ne$libresoc.v:199858$14580_Y + attribute \src "libresoc.v:199864.18-199864.109" + wire $ne$libresoc.v:199864$14586_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -398848,7 +418635,7 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 4 \core_irq_o @@ -398882,7 +418669,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:188933.7-188933.15" + attribute \src "libresoc.v:199748.7-199748.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -398904,7 +418691,7 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack @@ -398933,7 +418720,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:189042$14289 + cell $and $and$libresoc.v:199857$14579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398941,10 +418728,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:189042$14289_Y + connect \Y $and$libresoc.v:199857$14579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:189046$14293 + cell $and $and$libresoc.v:199861$14583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398952,10 +418739,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:189046$14293_Y + connect \Y $and$libresoc.v:199861$14583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:189048$14295 + cell $and $and$libresoc.v:199863$14585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398963,10 +418750,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:189048$14295_Y + connect \Y $and$libresoc.v:199863$14585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:189051$14298 + cell $and $and$libresoc.v:199866$14588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398974,10 +418761,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:189051$14298_Y + connect \Y $and$libresoc.v:199866$14588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:189047$14294 + cell $eq $eq$libresoc.v:199862$14584 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -398985,10 +418772,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:189047$14294_Y + connect \Y $eq$libresoc.v:199862$14584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:189044$14291 + cell $lt $lt$libresoc.v:199859$14581 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -398996,10 +418783,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:189044$14291_Y + connect \Y $lt$libresoc.v:199859$14581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:189045$14292 + cell $lt $lt$libresoc.v:199860$14582 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399007,10 +418794,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:189045$14292_Y + connect \Y $lt$libresoc.v:199860$14582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:189050$14297 + cell $lt $lt$libresoc.v:199865$14587 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399018,10 +418805,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:189050$14297_Y + connect \Y $lt$libresoc.v:199865$14587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:189043$14290 + cell $ne $ne$libresoc.v:199858$14580 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399029,10 +418816,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:189043$14290_Y + connect \Y $ne$libresoc.v:199858$14580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:189049$14296 + cell $ne $ne$libresoc.v:199864$14586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399040,123 +418827,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:189049$14296_Y + connect \Y $ne$libresoc.v:199864$14586_Y end - attribute \src "libresoc.v:188933.7-188933.20" - process $proc$libresoc.v:188933$14345 + attribute \src "libresoc.v:199748.7-199748.20" + process $proc$libresoc.v:199748$14635 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188962.7-188962.24" - process $proc$libresoc.v:188962$14346 + attribute \src "libresoc.v:199777.7-199777.24" + process $proc$libresoc.v:199777$14636 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:188966.13-188966.25" - process $proc$libresoc.v:188966$14347 + attribute \src "libresoc.v:199781.13-199781.25" + process $proc$libresoc.v:199781$14637 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:188995.7-188995.17" - process $proc$libresoc.v:188995$14348 + attribute \src "libresoc.v:199810.7-199810.17" + process $proc$libresoc.v:199810$14638 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:189003.13-189003.25" - process $proc$libresoc.v:189003$14349 + attribute \src "libresoc.v:199818.13-199818.25" + process $proc$libresoc.v:199818$14639 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:189017.7-189017.20" - process $proc$libresoc.v:189017$14350 + attribute \src "libresoc.v:199832.7-199832.20" + process $proc$libresoc.v:199832$14640 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:189025.14-189025.32" - process $proc$libresoc.v:189025$14351 + attribute \src "libresoc.v:199840.14-199840.32" + process $proc$libresoc.v:199840$14641 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:189035.14-189035.31" - process $proc$libresoc.v:189035$14352 + attribute \src "libresoc.v:199850.14-199850.31" + process $proc$libresoc.v:199850$14642 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:189052.3-189053.37" - process $proc$libresoc.v:189052$14299 + attribute \src "libresoc.v:199867.3-199868.37" + process $proc$libresoc.v:199867$14589 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:189054.3-189055.25" - process $proc$libresoc.v:189054$14300 + attribute \src "libresoc.v:199869.3-199870.25" + process $proc$libresoc.v:199869$14590 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:189056.3-189057.25" - process $proc$libresoc.v:189056$14301 + attribute \src "libresoc.v:199871.3-199872.25" + process $proc$libresoc.v:199871$14591 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:189058.3-189059.25" - process $proc$libresoc.v:189058$14302 + attribute \src "libresoc.v:199873.3-199874.25" + process $proc$libresoc.v:199873$14592 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:189060.3-189061.23" - process $proc$libresoc.v:189060$14303 + attribute \src "libresoc.v:199875.3-199876.23" + process $proc$libresoc.v:199875$14593 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:189062.3-189063.37" - process $proc$libresoc.v:189062$14304 + attribute \src "libresoc.v:199877.3-199878.37" + process $proc$libresoc.v:199877$14594 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:189064.3-189065.29" - process $proc$libresoc.v:189064$14305 + attribute \src "libresoc.v:199879.3-199880.29" + process $proc$libresoc.v:199879$14595 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:189066.3-189081.6" - process $proc$libresoc.v:189066$14306 + attribute \src "libresoc.v:199881.3-199896.6" + process $proc$libresoc.v:199881$14596 assign { } { } assign { } { } assign { } { } @@ -399164,15 +418951,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14307 $1\cppr$next[7:0]$14313 - assign $0\irq$next[0:0]$14308 $1\irq$next[0:0]$14314 - assign $0\mfrr$next[7:0]$14309 $1\mfrr$next[7:0]$14315 - assign $0\wb_ack$next[0:0]$14310 $1\wb_ack$next[0:0]$14316 - assign $0\wb_rd_data$next[31:0]$14311 $1\wb_rd_data$next[31:0]$14317 - assign $0\xisr$next[23:0]$14312 $1\xisr$next[23:0]$14318 - attribute \src "libresoc.v:189067.5-189067.29" + assign $0\cppr$next[7:0]$14597 $1\cppr$next[7:0]$14603 + assign $0\irq$next[0:0]$14598 $1\irq$next[0:0]$14604 + assign $0\mfrr$next[7:0]$14599 $1\mfrr$next[7:0]$14605 + assign $0\wb_ack$next[0:0]$14600 $1\wb_ack$next[0:0]$14606 + assign $0\wb_rd_data$next[31:0]$14601 $1\wb_rd_data$next[31:0]$14607 + assign $0\xisr$next[23:0]$14602 $1\xisr$next[23:0]$14608 + attribute \src "libresoc.v:199882.5-199882.29" switch \initial - attribute \src "libresoc.v:189067.9-189067.17" + attribute \src "libresoc.v:199882.9-199882.17" case 1'1 case end @@ -399186,36 +418973,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14318 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14313 8'00000000 - assign $1\mfrr$next[7:0]$14315 8'11111111 - assign $1\irq$next[0:0]$14314 1'0 - assign $1\wb_rd_data$next[31:0]$14317 0 - assign $1\wb_ack$next[0:0]$14316 1'0 + assign $1\xisr$next[23:0]$14608 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14603 8'00000000 + assign $1\mfrr$next[7:0]$14605 8'11111111 + assign $1\irq$next[0:0]$14604 1'0 + assign $1\wb_rd_data$next[31:0]$14607 0 + assign $1\wb_ack$next[0:0]$14606 1'0 case - assign $1\cppr$next[7:0]$14313 \cppr$2 - assign $1\irq$next[0:0]$14314 \irq$4 - assign $1\mfrr$next[7:0]$14315 \mfrr$3 - assign $1\wb_ack$next[0:0]$14316 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14317 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14318 \xisr$1 + assign $1\cppr$next[7:0]$14603 \cppr$2 + assign $1\irq$next[0:0]$14604 \irq$4 + assign $1\mfrr$next[7:0]$14605 \mfrr$3 + assign $1\wb_ack$next[0:0]$14606 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14607 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14608 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14307 - update \irq$next $0\irq$next[0:0]$14308 - update \mfrr$next $0\mfrr$next[7:0]$14309 - update \wb_ack$next $0\wb_ack$next[0:0]$14310 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14311 - update \xisr$next $0\xisr$next[23:0]$14312 + update \cppr$next $0\cppr$next[7:0]$14597 + update \irq$next $0\irq$next[0:0]$14598 + update \mfrr$next $0\mfrr$next[7:0]$14599 + update \wb_ack$next $0\wb_ack$next[0:0]$14600 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14601 + update \xisr$next $0\xisr$next[23:0]$14602 end - attribute \src "libresoc.v:189082.3-189109.6" - process $proc$libresoc.v:189082$14319 + attribute \src "libresoc.v:199897.3-199924.6" + process $proc$libresoc.v:199897$14609 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189083.5-189083.29" + attribute \src "libresoc.v:199898.5-199898.29" switch \initial - attribute \src "libresoc.v:189083.9-189083.17" + attribute \src "libresoc.v:199898.9-199898.17" case 1'1 case end @@ -399259,14 +419046,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:189110.3-189138.6" - process $proc$libresoc.v:189110$14320 + attribute \src "libresoc.v:199925.3-199953.6" + process $proc$libresoc.v:199925$14610 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:189111.5-189111.29" + attribute \src "libresoc.v:199926.5-199926.29" switch \initial - attribute \src "libresoc.v:189111.9-189111.17" + attribute \src "libresoc.v:199926.9-199926.17" case 1'1 case end @@ -399309,14 +419096,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:189139.3-189148.6" - process $proc$libresoc.v:189139$14321 + attribute \src "libresoc.v:199954.3-199963.6" + process $proc$libresoc.v:199954$14611 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:189140.5-189140.29" + attribute \src "libresoc.v:199955.5-199955.29" switch \initial - attribute \src "libresoc.v:189140.9-189140.17" + attribute \src "libresoc.v:199955.9-199955.17" case 1'1 case end @@ -399332,13 +419119,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:189149.3-189160.6" - process $proc$libresoc.v:189149$14322 + attribute \src "libresoc.v:199964.3-199975.6" + process $proc$libresoc.v:199964$14612 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:189150.5-189150.29" + attribute \src "libresoc.v:199965.5-199965.29" switch \initial - attribute \src "libresoc.v:189150.9-189150.17" + attribute \src "libresoc.v:199965.9-199965.17" case 1'1 case end @@ -399356,14 +419143,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:189161.3-189169.6" - process $proc$libresoc.v:189161$14323 + attribute \src "libresoc.v:199976.3-199984.6" + process $proc$libresoc.v:199976$14613 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14324 $1\core_irq_o$next[0:0]$14325 - attribute \src "libresoc.v:189162.5-189162.29" + assign $0\core_irq_o$next[0:0]$14614 $1\core_irq_o$next[0:0]$14615 + attribute \src "libresoc.v:199977.5-199977.29" switch \initial - attribute \src "libresoc.v:189162.9-189162.17" + attribute \src "libresoc.v:199977.9-199977.17" case 1'1 case end @@ -399372,21 +419159,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14325 1'0 + assign $1\core_irq_o$next[0:0]$14615 1'0 case - assign $1\core_irq_o$next[0:0]$14325 \irq + assign $1\core_irq_o$next[0:0]$14615 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14324 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14614 end - attribute \src "libresoc.v:189170.3-189179.6" - process $proc$libresoc.v:189170$14326 + attribute \src "libresoc.v:199985.3-199994.6" + process $proc$libresoc.v:199985$14616 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:189171.5-189171.29" + attribute \src "libresoc.v:199986.5-199986.29" switch \initial - attribute \src "libresoc.v:189171.9-189171.17" + attribute \src "libresoc.v:199986.9-199986.17" case 1'1 case end @@ -399402,8 +419189,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:189180.3-189242.6" - process $proc$libresoc.v:189180$14327 + attribute \src "libresoc.v:199995.3-200057.6" + process $proc$libresoc.v:199995$14617 assign { } { } assign { } { } assign { } { } @@ -399413,18 +419200,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14330 $1\mfrr$11[7:0]$14335 - assign $0\wb_ack$14[0:0]$14331 $1\wb_ack$14[0:0]$14336 + assign $0\mfrr$11[7:0]$14620 $1\mfrr$11[7:0]$14625 + assign $0\wb_ack$14[0:0]$14621 $1\wb_ack$14[0:0]$14626 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14333 $2\xisr$9[23:0]$14342 - assign $0\cppr$10[7:0]$14328 $4\cppr$10[7:0]$14343 - assign $0\wb_rd_data$13[31:0]$14332 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14329 $1\irq$12[0:0]$14344 - attribute \src "libresoc.v:189181.5-189181.29" + assign $0\xisr$9[23:0]$14623 $2\xisr$9[23:0]$14632 + assign $0\cppr$10[7:0]$14618 $4\cppr$10[7:0]$14633 + assign $0\wb_rd_data$13[31:0]$14622 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14619 $1\irq$12[0:0]$14634 + attribute \src "libresoc.v:199996.5-199996.29" switch \initial - attribute \src "libresoc.v:189181.9-189181.17" + attribute \src "libresoc.v:199996.9-199996.17" case 1'1 case end @@ -399435,712 +419222,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14336 1'1 - assign $1\cppr$10[7:0]$14334 $2\cppr$10[7:0]$14337 - assign $1\mfrr$11[7:0]$14335 $2\mfrr$11[7:0]$14338 + assign $1\wb_ack$14[0:0]$14626 1'1 + assign $1\cppr$10[7:0]$14624 $2\cppr$10[7:0]$14627 + assign $1\mfrr$11[7:0]$14625 $2\mfrr$11[7:0]$14628 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14337 $3\cppr$10[7:0]$14339 - assign $2\mfrr$11[7:0]$14338 $3\mfrr$11[7:0]$14340 + assign $2\cppr$10[7:0]$14627 $3\cppr$10[7:0]$14629 + assign $2\mfrr$11[7:0]$14628 $3\mfrr$11[7:0]$14630 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14340 \mfrr - assign $3\cppr$10[7:0]$14339 \be_in [31:24] + assign $3\mfrr$11[7:0]$14630 \mfrr + assign $3\cppr$10[7:0]$14629 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14340 \mfrr - assign $3\cppr$10[7:0]$14339 \be_in [31:24] + assign $3\mfrr$11[7:0]$14630 \mfrr + assign $3\cppr$10[7:0]$14629 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14339 \cppr + assign $3\cppr$10[7:0]$14629 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14340 \be_in [31:24] + assign $3\mfrr$11[7:0]$14630 \be_in [31:24] case - assign $3\cppr$10[7:0]$14339 \cppr - assign $3\mfrr$11[7:0]$14340 \mfrr + assign $3\cppr$10[7:0]$14629 \cppr + assign $3\mfrr$11[7:0]$14630 \mfrr end case - assign $2\cppr$10[7:0]$14337 \cppr - assign $2\mfrr$11[7:0]$14338 \mfrr + assign $2\cppr$10[7:0]$14627 \cppr + assign $2\mfrr$11[7:0]$14628 \mfrr end case - assign $1\cppr$10[7:0]$14334 \cppr - assign $1\mfrr$11[7:0]$14335 \mfrr - assign $1\wb_ack$14[0:0]$14336 1'0 + assign $1\cppr$10[7:0]$14624 \cppr + assign $1\mfrr$11[7:0]$14625 \mfrr + assign $1\wb_ack$14[0:0]$14626 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14341 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14631 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14341 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14631 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14342 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14632 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14342 $1\xisr$9[23:0]$14341 + assign $2\xisr$9[23:0]$14632 $1\xisr$9[23:0]$14631 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14343 \min_pri + assign $4\cppr$10[7:0]$14633 \min_pri case - assign $4\cppr$10[7:0]$14343 $1\cppr$10[7:0]$14334 + assign $4\cppr$10[7:0]$14633 $1\cppr$10[7:0]$14624 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14344 1'1 + assign $1\irq$12[0:0]$14634 1'1 case - assign $1\irq$12[0:0]$14344 1'0 + assign $1\irq$12[0:0]$14634 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14328 - update \irq$12 $0\irq$12[0:0]$14329 - update \mfrr$11 $0\mfrr$11[7:0]$14330 - update \wb_ack$14 $0\wb_ack$14[0:0]$14331 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14332 - update \xisr$9 $0\xisr$9[23:0]$14333 + update \cppr$10 $0\cppr$10[7:0]$14618 + update \irq$12 $0\irq$12[0:0]$14619 + update \mfrr$11 $0\mfrr$11[7:0]$14620 + update \wb_ack$14 $0\wb_ack$14[0:0]$14621 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14622 + update \xisr$9 $0\xisr$9[23:0]$14623 end - connect \$15 $and$libresoc.v:189042$14289_Y - connect \$17 $ne$libresoc.v:189043$14290_Y - connect \$19 $lt$libresoc.v:189044$14291_Y - connect \$21 $lt$libresoc.v:189045$14292_Y - connect \$23 $and$libresoc.v:189046$14293_Y - connect \$25 $eq$libresoc.v:189047$14294_Y - connect \$27 $and$libresoc.v:189048$14295_Y - connect \$29 $ne$libresoc.v:189049$14296_Y - connect \$31 $lt$libresoc.v:189050$14297_Y - connect \$7 $and$libresoc.v:189051$14298_Y + connect \$15 $and$libresoc.v:199857$14579_Y + connect \$17 $ne$libresoc.v:199858$14580_Y + connect \$19 $lt$libresoc.v:199859$14581_Y + connect \$21 $lt$libresoc.v:199860$14582_Y + connect \$23 $and$libresoc.v:199861$14583_Y + connect \$25 $eq$libresoc.v:199862$14584_Y + connect \$27 $and$libresoc.v:199863$14585_Y + connect \$29 $ne$libresoc.v:199864$14586_Y + connect \$31 $lt$libresoc.v:199865$14587_Y + connect \$7 $and$libresoc.v:199866$14588_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:189250.1-190299.10" +attribute \src "libresoc.v:200065.1-201114.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:190180.3-190229.6" + attribute \src "libresoc.v:200995.3-201044.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:189891.3-189900.6" + attribute \src "libresoc.v:200706.3-200715.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:190100.3-190109.6" + attribute \src "libresoc.v:200915.3-200924.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:190120.3-190129.6" + attribute \src "libresoc.v:200935.3-200944.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:190140.3-190149.6" + attribute \src "libresoc.v:200955.3-200964.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:190160.3-190169.6" + attribute \src "libresoc.v:200975.3-200984.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:190230.3-190239.6" + attribute \src "libresoc.v:201045.3-201054.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:190250.3-190259.6" + attribute \src "libresoc.v:201065.3-201074.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:189911.3-189920.6" + attribute \src "libresoc.v:200726.3-200735.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:189931.3-189940.6" + attribute \src "libresoc.v:200746.3-200755.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:189951.3-189960.6" + attribute \src "libresoc.v:200766.3-200775.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:189980.3-189989.6" + attribute \src "libresoc.v:200795.3-200804.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:190000.3-190009.6" + attribute \src "libresoc.v:200815.3-200824.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:190020.3-190029.6" + attribute \src "libresoc.v:200835.3-200844.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:190040.3-190049.6" + attribute \src "libresoc.v:200855.3-200864.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:190060.3-190069.6" + attribute \src "libresoc.v:200875.3-200884.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:190080.3-190089.6" + attribute \src "libresoc.v:200895.3-200904.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:189881.3-189890.6" + attribute \src "libresoc.v:200696.3-200705.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:190090.3-190099.6" + attribute \src "libresoc.v:200905.3-200914.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:190110.3-190119.6" + attribute \src "libresoc.v:200925.3-200934.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:190130.3-190139.6" + attribute \src "libresoc.v:200945.3-200954.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:190150.3-190159.6" + attribute \src "libresoc.v:200965.3-200974.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:190170.3-190179.6" + attribute \src "libresoc.v:200985.3-200994.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:190240.3-190249.6" + attribute \src "libresoc.v:201055.3-201064.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:189901.3-189910.6" + attribute \src "libresoc.v:200716.3-200725.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:189921.3-189930.6" + attribute \src "libresoc.v:200736.3-200745.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:189941.3-189950.6" + attribute \src "libresoc.v:200756.3-200765.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:189961.3-189970.6" + attribute \src "libresoc.v:200776.3-200785.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:189990.3-189999.6" + attribute \src "libresoc.v:200805.3-200814.6" wire width 8 $0\cur_pri5[7:0] - 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"libresoc.v:200566.18-200566.111" + wire $lt$libresoc.v:200566$14744_Y + attribute \src "libresoc.v:200553.18-200553.40" + wire width 16 $shr$libresoc.v:200553$14731_Y + attribute \src "libresoc.v:200465.17-200465.114" + wire width 8 $ternary$libresoc.v:200465$14643_Y + attribute \src "libresoc.v:200487.18-200487.116" + wire width 8 $ternary$libresoc.v:200487$14665_Y + attribute \src "libresoc.v:200509.18-200509.116" + wire width 8 $ternary$libresoc.v:200509$14687_Y + attribute \src "libresoc.v:200524.19-200524.118" + wire width 8 $ternary$libresoc.v:200524$14702_Y + attribute \src "libresoc.v:200526.18-200526.116" + wire width 8 $ternary$libresoc.v:200526$14704_Y + attribute \src "libresoc.v:200528.18-200528.116" + wire width 8 $ternary$libresoc.v:200528$14706_Y + attribute \src "libresoc.v:200530.18-200530.116" + wire width 8 $ternary$libresoc.v:200530$14708_Y + attribute \src "libresoc.v:200532.18-200532.116" + wire width 8 $ternary$libresoc.v:200532$14710_Y + attribute \src "libresoc.v:200534.18-200534.116" + wire width 8 $ternary$libresoc.v:200534$14712_Y + attribute \src "libresoc.v:200537.18-200537.116" + wire width 8 $ternary$libresoc.v:200537$14715_Y + attribute \src "libresoc.v:200539.18-200539.116" + wire width 8 $ternary$libresoc.v:200539$14717_Y + attribute \src "libresoc.v:200541.18-200541.117" + wire width 8 $ternary$libresoc.v:200541$14719_Y + attribute \src "libresoc.v:200543.18-200543.117" + wire width 8 $ternary$libresoc.v:200543$14721_Y + attribute \src "libresoc.v:200545.18-200545.117" + wire width 8 $ternary$libresoc.v:200545$14723_Y + attribute \src "libresoc.v:200548.18-200548.117" + wire width 8 $ternary$libresoc.v:200548$14726_Y + attribute \src "libresoc.v:200550.18-200550.117" + wire width 8 $ternary$libresoc.v:200550$14728_Y + attribute \src "libresoc.v:200552.18-200552.117" + wire width 8 $ternary$libresoc.v:200552$14730_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -400351,7 +420138,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -400449,7 +420236,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:189251.7-189251.15" + attribute \src "libresoc.v:200066.7-200066.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -400469,7 +420256,7 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid @@ -400538,7 +420325,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189652$14355 + cell $and $and$libresoc.v:200467$14645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400546,10 +420333,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:189652$14355_Y + connect \Y $and$libresoc.v:200467$14645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189654$14357 + cell $and $and$libresoc.v:200469$14647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400557,10 +420344,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:189654$14357_Y + connect \Y $and$libresoc.v:200469$14647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189656$14359 + cell $and $and$libresoc.v:200471$14649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400568,10 +420355,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:189656$14359_Y + connect \Y $and$libresoc.v:200471$14649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189658$14361 + cell $and $and$libresoc.v:200473$14651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400579,10 +420366,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:189658$14361_Y + connect \Y $and$libresoc.v:200473$14651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189660$14363 + cell $and $and$libresoc.v:200475$14653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400590,10 +420377,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:189660$14363_Y + connect \Y $and$libresoc.v:200475$14653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189662$14365 + cell $and $and$libresoc.v:200477$14655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400601,10 +420388,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:189662$14365_Y + connect \Y $and$libresoc.v:200477$14655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189664$14367 + cell $and $and$libresoc.v:200479$14657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400612,10 +420399,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:189664$14367_Y + connect \Y $and$libresoc.v:200479$14657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189667$14370 + cell $and $and$libresoc.v:200482$14660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400623,10 +420410,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:189667$14370_Y + connect \Y $and$libresoc.v:200482$14660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189669$14372 + cell $and $and$libresoc.v:200484$14662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400634,10 +420421,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:189669$14372_Y + connect \Y $and$libresoc.v:200484$14662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189671$14374 + cell $and $and$libresoc.v:200486$14664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400645,10 +420432,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:189671$14374_Y + connect \Y $and$libresoc.v:200486$14664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189674$14377 + cell $and $and$libresoc.v:200489$14667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400656,10 +420443,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:189674$14377_Y + connect \Y $and$libresoc.v:200489$14667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189676$14379 + cell $and $and$libresoc.v:200491$14669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400667,10 +420454,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:189676$14379_Y + connect \Y $and$libresoc.v:200491$14669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189678$14381 + cell $and $and$libresoc.v:200493$14671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400678,10 +420465,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:189678$14381_Y + connect \Y $and$libresoc.v:200493$14671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189680$14383 + cell $and $and$libresoc.v:200495$14673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400689,10 +420476,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:189680$14383_Y + connect \Y $and$libresoc.v:200495$14673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189682$14385 + cell $and $and$libresoc.v:200497$14675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400700,10 +420487,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:189682$14385_Y + connect \Y $and$libresoc.v:200497$14675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189684$14387 + cell $and $and$libresoc.v:200499$14677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400711,10 +420498,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:189684$14387_Y + connect \Y $and$libresoc.v:200499$14677_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189686$14389 + cell $and $and$libresoc.v:200501$14679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400722,10 +420509,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:189686$14389_Y + connect \Y $and$libresoc.v:200501$14679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189689$14392 + cell $and $and$libresoc.v:200504$14682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400733,10 +420520,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:189689$14392_Y + connect \Y $and$libresoc.v:200504$14682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189691$14394 + cell $and $and$libresoc.v:200506$14684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400744,10 +420531,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:189691$14394_Y + connect \Y $and$libresoc.v:200506$14684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189693$14396 + cell $and $and$libresoc.v:200508$14686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400755,10 +420542,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:189693$14396_Y + connect \Y $and$libresoc.v:200508$14686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189696$14399 + cell $and $and$libresoc.v:200511$14689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400766,10 +420553,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:189696$14399_Y + connect \Y $and$libresoc.v:200511$14689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189698$14401 + cell $and $and$libresoc.v:200513$14691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400777,10 +420564,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:189698$14401_Y + connect \Y $and$libresoc.v:200513$14691_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189700$14403 + cell $and $and$libresoc.v:200515$14693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400788,10 +420575,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:189700$14403_Y + connect \Y $and$libresoc.v:200515$14693_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189702$14405 + cell $and $and$libresoc.v:200517$14695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400799,10 +420586,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:189702$14405_Y + connect \Y $and$libresoc.v:200517$14695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189704$14407 + cell $and $and$libresoc.v:200519$14697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400810,10 +420597,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:189704$14407_Y + connect \Y $and$libresoc.v:200519$14697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189707$14410 + cell $and $and$libresoc.v:200522$14700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400821,10 +420608,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:189707$14410_Y + connect \Y $and$libresoc.v:200522$14700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:189731$14434 + cell $and $and$libresoc.v:200546$14724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400832,10 +420619,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:189731$14434_Y + connect \Y $and$libresoc.v:200546$14724_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:189739$14442 + cell $and $and$libresoc.v:200554$14732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400843,10 +420630,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:189739$14442_Y + connect \Y $and$libresoc.v:200554$14732_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189741$14444 + cell $and $and$libresoc.v:200556$14734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400854,10 +420641,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:189741$14444_Y + connect \Y $and$libresoc.v:200556$14734_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189743$14446 + cell $and $and$libresoc.v:200558$14736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400865,10 +420652,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:189743$14446_Y + connect \Y $and$libresoc.v:200558$14736_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189745$14448 + cell $and $and$libresoc.v:200560$14738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400876,10 +420663,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:189745$14448_Y + connect \Y $and$libresoc.v:200560$14738_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189748$14451 + cell $and $and$libresoc.v:200563$14741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400887,10 +420674,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:189748$14451_Y + connect \Y $and$libresoc.v:200563$14741_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189750$14453 + cell $and $and$libresoc.v:200565$14743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400898,10 +420685,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:189750$14453_Y + connect \Y $and$libresoc.v:200565$14743_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189752$14455 + cell $and $and$libresoc.v:200567$14745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400909,10 +420696,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:189752$14455_Y + connect \Y $and$libresoc.v:200567$14745_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189666$14369 + cell $eq $eq$libresoc.v:200481$14659 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400920,10 +420707,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189666$14369_Y + connect \Y $eq$libresoc.v:200481$14659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189688$14391 + cell $eq $eq$libresoc.v:200503$14681 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400931,10 +420718,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189688$14391_Y + connect \Y $eq$libresoc.v:200503$14681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:189705$14408 + cell $eq $eq$libresoc.v:200520$14698 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -400942,10 +420729,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:189705$14408_Y + connect \Y $eq$libresoc.v:200520$14698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189708$14411 + cell $eq $eq$libresoc.v:200523$14701 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400953,10 +420740,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:189708$14411_Y + connect \Y $eq$libresoc.v:200523$14701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189710$14413 + cell $eq $eq$libresoc.v:200525$14703 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400964,10 +420751,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189710$14413_Y + connect \Y $eq$libresoc.v:200525$14703_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189712$14415 + cell $eq $eq$libresoc.v:200527$14705 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400975,10 +420762,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189712$14415_Y + connect \Y $eq$libresoc.v:200527$14705_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189714$14417 + cell $eq $eq$libresoc.v:200529$14707 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400986,10 +420773,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189714$14417_Y + connect \Y $eq$libresoc.v:200529$14707_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189716$14419 + cell $eq $eq$libresoc.v:200531$14709 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400997,10 +420784,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189716$14419_Y + connect \Y $eq$libresoc.v:200531$14709_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189718$14421 + cell $eq $eq$libresoc.v:200533$14711 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401008,10 +420795,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189718$14421_Y + connect \Y $eq$libresoc.v:200533$14711_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:189720$14423 + cell $eq $eq$libresoc.v:200535$14713 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -401019,10 +420806,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:189720$14423_Y + connect \Y $eq$libresoc.v:200535$14713_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189721$14424 + cell $eq $eq$libresoc.v:200536$14714 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401030,10 +420817,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189721$14424_Y + connect \Y $eq$libresoc.v:200536$14714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189723$14426 + cell $eq $eq$libresoc.v:200538$14716 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401041,10 +420828,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189723$14426_Y + connect \Y $eq$libresoc.v:200538$14716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189725$14428 + cell $eq $eq$libresoc.v:200540$14718 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401052,10 +420839,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189725$14428_Y + connect \Y $eq$libresoc.v:200540$14718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189727$14430 + cell $eq $eq$libresoc.v:200542$14720 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401063,10 +420850,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189727$14430_Y + connect \Y $eq$libresoc.v:200542$14720_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189729$14432 + cell $eq $eq$libresoc.v:200544$14722 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401074,10 +420861,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189729$14432_Y + connect \Y $eq$libresoc.v:200544$14722_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189732$14435 + cell $eq $eq$libresoc.v:200547$14725 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401085,10 +420872,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189732$14435_Y + connect \Y $eq$libresoc.v:200547$14725_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189734$14437 + cell $eq $eq$libresoc.v:200549$14727 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401096,10 +420883,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189734$14437_Y + connect \Y $eq$libresoc.v:200549$14727_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189736$14439 + cell $eq $eq$libresoc.v:200551$14729 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401107,10 +420894,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189736$14439_Y + connect \Y $eq$libresoc.v:200551$14729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189747$14450 + cell $eq $eq$libresoc.v:200562$14740 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401118,10 +420905,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189747$14450_Y + connect \Y $eq$libresoc.v:200562$14740_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189651$14354 + cell $lt $lt$libresoc.v:200466$14644 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401129,10 +420916,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:189651$14354_Y + connect \Y $lt$libresoc.v:200466$14644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189653$14356 + cell $lt $lt$libresoc.v:200468$14646 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401140,10 +420927,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:189653$14356_Y + connect \Y $lt$libresoc.v:200468$14646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189655$14358 + cell $lt $lt$libresoc.v:200470$14648 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401151,10 +420938,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:189655$14358_Y + connect \Y $lt$libresoc.v:200470$14648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189657$14360 + cell $lt $lt$libresoc.v:200472$14650 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401162,10 +420949,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:189657$14360_Y + connect \Y $lt$libresoc.v:200472$14650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189659$14362 + cell $lt $lt$libresoc.v:200474$14652 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401173,10 +420960,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:189659$14362_Y + connect \Y $lt$libresoc.v:200474$14652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189661$14364 + cell $lt $lt$libresoc.v:200476$14654 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401184,10 +420971,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:189661$14364_Y + connect \Y $lt$libresoc.v:200476$14654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189663$14366 + cell $lt $lt$libresoc.v:200478$14656 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401195,10 +420982,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:189663$14366_Y + connect \Y $lt$libresoc.v:200478$14656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189665$14368 + cell $lt $lt$libresoc.v:200480$14658 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401206,10 +420993,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:189665$14368_Y + connect \Y $lt$libresoc.v:200480$14658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189668$14371 + cell $lt $lt$libresoc.v:200483$14661 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401217,10 +421004,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:189668$14371_Y + connect \Y $lt$libresoc.v:200483$14661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189670$14373 + cell $lt $lt$libresoc.v:200485$14663 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401228,10 +421015,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:189670$14373_Y + connect \Y $lt$libresoc.v:200485$14663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189673$14376 + cell $lt $lt$libresoc.v:200488$14666 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401239,10 +421026,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:189673$14376_Y + connect \Y $lt$libresoc.v:200488$14666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189675$14378 + cell $lt $lt$libresoc.v:200490$14668 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401250,10 +421037,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:189675$14378_Y + connect \Y $lt$libresoc.v:200490$14668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189677$14380 + cell $lt $lt$libresoc.v:200492$14670 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401261,10 +421048,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:189677$14380_Y + connect \Y $lt$libresoc.v:200492$14670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189679$14382 + cell $lt $lt$libresoc.v:200494$14672 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401272,10 +421059,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:189679$14382_Y + connect \Y $lt$libresoc.v:200494$14672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189681$14384 + cell $lt $lt$libresoc.v:200496$14674 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401283,10 +421070,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:189681$14384_Y + connect \Y $lt$libresoc.v:200496$14674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189683$14386 + cell $lt $lt$libresoc.v:200498$14676 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401294,10 +421081,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:189683$14386_Y + connect \Y $lt$libresoc.v:200498$14676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189685$14388 + cell $lt $lt$libresoc.v:200500$14678 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401305,10 +421092,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:189685$14388_Y + connect \Y $lt$libresoc.v:200500$14678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189687$14390 + cell $lt $lt$libresoc.v:200502$14680 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401316,10 +421103,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:189687$14390_Y + connect \Y $lt$libresoc.v:200502$14680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189690$14393 + cell $lt $lt$libresoc.v:200505$14683 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401327,10 +421114,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:189690$14393_Y + connect \Y $lt$libresoc.v:200505$14683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189692$14395 + cell $lt $lt$libresoc.v:200507$14685 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401338,10 +421125,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:189692$14395_Y + connect \Y $lt$libresoc.v:200507$14685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189695$14398 + cell $lt $lt$libresoc.v:200510$14688 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401349,10 +421136,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:189695$14398_Y + connect \Y $lt$libresoc.v:200510$14688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189697$14400 + cell $lt $lt$libresoc.v:200512$14690 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401360,10 +421147,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:189697$14400_Y + connect \Y $lt$libresoc.v:200512$14690_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189699$14402 + cell $lt $lt$libresoc.v:200514$14692 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401371,10 +421158,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:189699$14402_Y + connect \Y $lt$libresoc.v:200514$14692_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189701$14404 + cell $lt $lt$libresoc.v:200516$14694 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401382,10 +421169,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:189701$14404_Y + connect \Y $lt$libresoc.v:200516$14694_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189703$14406 + cell $lt $lt$libresoc.v:200518$14696 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401393,10 +421180,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:189703$14406_Y + connect \Y $lt$libresoc.v:200518$14696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189706$14409 + cell $lt $lt$libresoc.v:200521$14699 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401404,10 +421191,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:189706$14409_Y + connect \Y $lt$libresoc.v:200521$14699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189740$14443 + cell $lt $lt$libresoc.v:200555$14733 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401415,10 +421202,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:189740$14443_Y + connect \Y $lt$libresoc.v:200555$14733_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189742$14445 + cell $lt $lt$libresoc.v:200557$14735 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401426,10 +421213,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:189742$14445_Y + connect \Y $lt$libresoc.v:200557$14735_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189744$14447 + cell $lt $lt$libresoc.v:200559$14737 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401437,10 +421224,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:189744$14447_Y + connect \Y $lt$libresoc.v:200559$14737_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189746$14449 + cell $lt $lt$libresoc.v:200561$14739 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401448,10 +421235,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:189746$14449_Y + connect \Y $lt$libresoc.v:200561$14739_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189749$14452 + cell $lt $lt$libresoc.v:200564$14742 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401459,10 +421246,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:189749$14452_Y + connect \Y $lt$libresoc.v:200564$14742_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189751$14454 + cell $lt $lt$libresoc.v:200566$14744 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -401470,10 +421257,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:189751$14454_Y + connect \Y $lt$libresoc.v:200566$14744_Y end - attribute \src "libresoc.v:189738.18-189738.40" - cell $shr $shr$libresoc.v:189738$14441 + attribute \src "libresoc.v:200553.18-200553.40" + cell $shr $shr$libresoc.v:200553$14731 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -401481,469 +421268,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:189738$14441_Y + connect \Y $shr$libresoc.v:200553$14731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189650$14353 + cell $mux $ternary$libresoc.v:200465$14643 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:189650$14353_Y + connect \Y $ternary$libresoc.v:200465$14643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189672$14375 + cell $mux $ternary$libresoc.v:200487$14665 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:189672$14375_Y + connect \Y $ternary$libresoc.v:200487$14665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189694$14397 + cell $mux $ternary$libresoc.v:200509$14687 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:189694$14397_Y + connect \Y $ternary$libresoc.v:200509$14687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189709$14412 + cell $mux $ternary$libresoc.v:200524$14702 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:189709$14412_Y + connect \Y $ternary$libresoc.v:200524$14702_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189711$14414 + cell $mux $ternary$libresoc.v:200526$14704 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:189711$14414_Y + connect \Y $ternary$libresoc.v:200526$14704_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189713$14416 + cell $mux $ternary$libresoc.v:200528$14706 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:189713$14416_Y + connect \Y $ternary$libresoc.v:200528$14706_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189715$14418 + cell $mux $ternary$libresoc.v:200530$14708 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:189715$14418_Y + connect \Y $ternary$libresoc.v:200530$14708_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189717$14420 + cell $mux $ternary$libresoc.v:200532$14710 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:189717$14420_Y + connect \Y $ternary$libresoc.v:200532$14710_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189719$14422 + cell $mux $ternary$libresoc.v:200534$14712 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:189719$14422_Y + connect \Y $ternary$libresoc.v:200534$14712_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189722$14425 + cell $mux $ternary$libresoc.v:200537$14715 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:189722$14425_Y + connect \Y $ternary$libresoc.v:200537$14715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189724$14427 + cell $mux $ternary$libresoc.v:200539$14717 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:189724$14427_Y + connect \Y $ternary$libresoc.v:200539$14717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189726$14429 + cell $mux $ternary$libresoc.v:200541$14719 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:189726$14429_Y + connect \Y $ternary$libresoc.v:200541$14719_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189728$14431 + cell $mux $ternary$libresoc.v:200543$14721 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:189728$14431_Y + connect \Y $ternary$libresoc.v:200543$14721_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189730$14433 + cell $mux $ternary$libresoc.v:200545$14723 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:189730$14433_Y + connect \Y $ternary$libresoc.v:200545$14723_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189733$14436 + cell $mux $ternary$libresoc.v:200548$14726 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:189733$14436_Y + connect \Y $ternary$libresoc.v:200548$14726_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189735$14438 + cell $mux $ternary$libresoc.v:200550$14728 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:189735$14438_Y + connect \Y $ternary$libresoc.v:200550$14728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189737$14440 + cell $mux $ternary$libresoc.v:200552$14730 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:189737$14440_Y + connect \Y $ternary$libresoc.v:200552$14730_Y end - attribute \src "libresoc.v:189251.7-189251.20" - process $proc$libresoc.v:189251$14601 + attribute \src "libresoc.v:200066.7-200066.20" + process $proc$libresoc.v:200066$14891 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189532.13-189532.30" - process $proc$libresoc.v:189532$14602 + attribute \src "libresoc.v:200347.13-200347.30" + process $proc$libresoc.v:200347$14892 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:189537.13-189537.29" - process $proc$libresoc.v:189537$14603 + attribute \src "libresoc.v:200352.13-200352.29" + process $proc$libresoc.v:200352$14893 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:189546.7-189546.25" - process $proc$libresoc.v:189546$14604 + attribute \src "libresoc.v:200361.7-200361.25" + process $proc$libresoc.v:200361$14894 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:189555.14-189555.35" - process $proc$libresoc.v:189555$14605 + attribute \src "libresoc.v:200370.14-200370.35" + process $proc$libresoc.v:200370$14895 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:189567.14-189567.36" - process $proc$libresoc.v:189567$14606 + attribute \src "libresoc.v:200382.14-200382.36" + process $proc$libresoc.v:200382$14896 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:189587.13-189587.30" - process $proc$libresoc.v:189587$14607 + attribute \src "libresoc.v:200402.13-200402.30" + process $proc$libresoc.v:200402$14897 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:189591.13-189591.31" - process $proc$libresoc.v:189591$14608 + attribute \src "libresoc.v:200406.13-200406.31" + process $proc$libresoc.v:200406$14898 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:189595.13-189595.31" - process $proc$libresoc.v:189595$14609 + attribute \src "libresoc.v:200410.13-200410.31" + process $proc$libresoc.v:200410$14899 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:189599.13-189599.31" - process $proc$libresoc.v:189599$14610 + attribute \src "libresoc.v:200414.13-200414.31" + process $proc$libresoc.v:200414$14900 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:189603.13-189603.31" - process $proc$libresoc.v:189603$14611 + attribute \src "libresoc.v:200418.13-200418.31" + process $proc$libresoc.v:200418$14901 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:189607.13-189607.31" - process $proc$libresoc.v:189607$14612 + attribute \src "libresoc.v:200422.13-200422.31" + process $proc$libresoc.v:200422$14902 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:189611.13-189611.31" - process $proc$libresoc.v:189611$14613 + attribute \src "libresoc.v:200426.13-200426.31" + process $proc$libresoc.v:200426$14903 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:189615.13-189615.30" - process $proc$libresoc.v:189615$14614 + attribute \src "libresoc.v:200430.13-200430.30" + process $proc$libresoc.v:200430$14904 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:189619.13-189619.30" - process $proc$libresoc.v:189619$14615 + attribute \src "libresoc.v:200434.13-200434.30" + process $proc$libresoc.v:200434$14905 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:189623.13-189623.30" - process $proc$libresoc.v:189623$14616 + attribute \src "libresoc.v:200438.13-200438.30" + process $proc$libresoc.v:200438$14906 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:189627.13-189627.30" - process $proc$libresoc.v:189627$14617 + attribute \src "libresoc.v:200442.13-200442.30" + process $proc$libresoc.v:200442$14907 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:189631.13-189631.30" - process $proc$libresoc.v:189631$14618 + attribute \src "libresoc.v:200446.13-200446.30" + process $proc$libresoc.v:200446$14908 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:189635.13-189635.30" - process $proc$libresoc.v:189635$14619 + attribute \src "libresoc.v:200450.13-200450.30" + process $proc$libresoc.v:200450$14909 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:189639.13-189639.30" - process $proc$libresoc.v:189639$14620 + attribute \src "libresoc.v:200454.13-200454.30" + process $proc$libresoc.v:200454$14910 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:189643.13-189643.30" - process $proc$libresoc.v:189643$14621 + attribute \src "libresoc.v:200458.13-200458.30" + process $proc$libresoc.v:200458$14911 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:189647.13-189647.30" - process $proc$libresoc.v:189647$14622 + attribute \src "libresoc.v:200462.13-200462.30" + process $proc$libresoc.v:200462$14912 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:189753.3-189754.37" - process $proc$libresoc.v:189753$14456 - assign { } { } - assign $0\xive11_pri[7:0] \xive11_pri$next - sync posedge \clk - update \xive11_pri $0\xive11_pri[7:0] - end - attribute \src "libresoc.v:189755.3-189756.37" - process $proc$libresoc.v:189755$14457 - assign { } { } - assign $0\xive12_pri[7:0] \xive12_pri$next - sync posedge \clk - update \xive12_pri $0\xive12_pri[7:0] - end - attribute \src "libresoc.v:189757.3-189758.37" - process $proc$libresoc.v:189757$14458 - assign { } { } - assign $0\xive13_pri[7:0] \xive13_pri$next - sync posedge \clk - update \xive13_pri $0\xive13_pri[7:0] - end - attribute \src "libresoc.v:189759.3-189760.37" - process $proc$libresoc.v:189759$14459 - assign { } { } - assign $0\xive14_pri[7:0] \xive14_pri$next - sync posedge \clk - update \xive14_pri $0\xive14_pri[7:0] - end - attribute \src "libresoc.v:189761.3-189762.37" - process $proc$libresoc.v:189761$14460 - assign { } { } - assign $0\xive15_pri[7:0] \xive15_pri$next - sync posedge \clk - update \xive15_pri $0\xive15_pri[7:0] - end - attribute \src "libresoc.v:189763.3-189764.39" - process $proc$libresoc.v:189763$14461 - assign { } { } - assign $0\ics_wb__ack[0:0] \ics_wb__ack$next - sync posedge \clk - update \ics_wb__ack $0\ics_wb__ack[0:0] - end - attribute \src "libresoc.v:189765.3-189766.43" - process $proc$libresoc.v:189765$14462 - assign { } { } - assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next - sync posedge \clk - update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] - end - attribute \src "libresoc.v:189767.3-189768.39" - process $proc$libresoc.v:189767$14463 - assign { } { } - assign $0\int_level_l[15:0] \int_level_l$next - sync posedge \clk - update \int_level_l $0\int_level_l[15:0] - end - attribute \src "libresoc.v:189769.3-189770.28" - process $proc$libresoc.v:189769$14464 + attribute \src "libresoc.v:200568.3-200569.28" + process $proc$libresoc.v:200568$14746 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:189771.3-189772.25" - process $proc$libresoc.v:189771$14465 + attribute \src "libresoc.v:200570.3-200571.25" + process $proc$libresoc.v:200570$14747 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:189773.3-189774.35" - process $proc$libresoc.v:189773$14466 + attribute \src "libresoc.v:200572.3-200573.35" + process $proc$libresoc.v:200572$14748 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:189775.3-189776.35" - process $proc$libresoc.v:189775$14467 + attribute \src "libresoc.v:200574.3-200575.35" + process $proc$libresoc.v:200574$14749 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:189777.3-189778.35" - process $proc$libresoc.v:189777$14468 + attribute \src "libresoc.v:200576.3-200577.35" + process $proc$libresoc.v:200576$14750 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:189779.3-189780.35" - process $proc$libresoc.v:189779$14469 + attribute \src "libresoc.v:200578.3-200579.35" + process $proc$libresoc.v:200578$14751 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:189781.3-189782.35" - process $proc$libresoc.v:189781$14470 + attribute \src "libresoc.v:200580.3-200581.35" + process $proc$libresoc.v:200580$14752 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:189783.3-189784.35" - process $proc$libresoc.v:189783$14471 + attribute \src "libresoc.v:200582.3-200583.35" + process $proc$libresoc.v:200582$14753 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:189785.3-189786.35" - process $proc$libresoc.v:189785$14472 + attribute \src "libresoc.v:200584.3-200585.35" + process $proc$libresoc.v:200584$14754 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:189787.3-189788.35" - process $proc$libresoc.v:189787$14473 + attribute \src "libresoc.v:200586.3-200587.35" + process $proc$libresoc.v:200586$14755 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:189789.3-189790.35" - process $proc$libresoc.v:189789$14474 + attribute \src "libresoc.v:200588.3-200589.35" + process $proc$libresoc.v:200588$14756 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:189791.3-189792.35" - process $proc$libresoc.v:189791$14475 + attribute \src "libresoc.v:200590.3-200591.35" + process $proc$libresoc.v:200590$14757 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:189793.3-189794.37" - process $proc$libresoc.v:189793$14476 + attribute \src "libresoc.v:200592.3-200593.37" + process $proc$libresoc.v:200592$14758 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:189795.3-189880.6" - process $proc$libresoc.v:189795$14477 + attribute \src "libresoc.v:200594.3-200595.37" + process $proc$libresoc.v:200594$14759 + assign { } { } + assign $0\xive11_pri[7:0] \xive11_pri$next + sync posedge \clk + update \xive11_pri $0\xive11_pri[7:0] + end + attribute \src "libresoc.v:200596.3-200597.37" + process $proc$libresoc.v:200596$14760 + assign { } { } + assign $0\xive12_pri[7:0] \xive12_pri$next + sync posedge \clk + update \xive12_pri $0\xive12_pri[7:0] + end + attribute \src "libresoc.v:200598.3-200599.37" + process $proc$libresoc.v:200598$14761 + assign { } { } + assign $0\xive13_pri[7:0] \xive13_pri$next + sync posedge \clk + update \xive13_pri $0\xive13_pri[7:0] + end + attribute \src "libresoc.v:200600.3-200601.37" + process $proc$libresoc.v:200600$14762 + assign { } { } + assign $0\xive14_pri[7:0] \xive14_pri$next + sync posedge \clk + update \xive14_pri $0\xive14_pri[7:0] + end + attribute \src "libresoc.v:200602.3-200603.37" + process $proc$libresoc.v:200602$14763 + assign { } { } + assign $0\xive15_pri[7:0] \xive15_pri$next + sync posedge \clk + update \xive15_pri $0\xive15_pri[7:0] + end + attribute \src "libresoc.v:200604.3-200605.39" + process $proc$libresoc.v:200604$14764 + assign { } { } + assign $0\ics_wb__ack[0:0] \ics_wb__ack$next + sync posedge \clk + update \ics_wb__ack $0\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:200606.3-200607.43" + process $proc$libresoc.v:200606$14765 + assign { } { } + assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next + sync posedge \clk + update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:200608.3-200609.39" + process $proc$libresoc.v:200608$14766 + assign { } { } + assign $0\int_level_l[15:0] \int_level_l$next + sync posedge \clk + update \int_level_l $0\int_level_l[15:0] + end + attribute \src "libresoc.v:200610.3-200695.6" + process $proc$libresoc.v:200610$14767 assign { } { } assign { } { } assign { } { } @@ -401992,25 +421779,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14478 $4\xive0_pri$next[7:0]$14542 - assign $0\xive10_pri$next[7:0]$14479 $4\xive10_pri$next[7:0]$14543 - assign $0\xive11_pri$next[7:0]$14480 $4\xive11_pri$next[7:0]$14544 - assign $0\xive12_pri$next[7:0]$14481 $4\xive12_pri$next[7:0]$14545 - assign $0\xive13_pri$next[7:0]$14482 $4\xive13_pri$next[7:0]$14546 - assign $0\xive14_pri$next[7:0]$14483 $4\xive14_pri$next[7:0]$14547 - assign $0\xive15_pri$next[7:0]$14484 $4\xive15_pri$next[7:0]$14548 - assign $0\xive1_pri$next[7:0]$14485 $4\xive1_pri$next[7:0]$14549 - assign $0\xive2_pri$next[7:0]$14486 $4\xive2_pri$next[7:0]$14550 - assign $0\xive3_pri$next[7:0]$14487 $4\xive3_pri$next[7:0]$14551 - assign $0\xive4_pri$next[7:0]$14488 $4\xive4_pri$next[7:0]$14552 - assign $0\xive5_pri$next[7:0]$14489 $4\xive5_pri$next[7:0]$14553 - assign $0\xive6_pri$next[7:0]$14490 $4\xive6_pri$next[7:0]$14554 - assign $0\xive7_pri$next[7:0]$14491 $4\xive7_pri$next[7:0]$14555 - assign $0\xive8_pri$next[7:0]$14492 $4\xive8_pri$next[7:0]$14556 - assign $0\xive9_pri$next[7:0]$14493 $4\xive9_pri$next[7:0]$14557 - attribute \src "libresoc.v:189796.5-189796.29" + assign $0\xive0_pri$next[7:0]$14768 $4\xive0_pri$next[7:0]$14832 + assign $0\xive10_pri$next[7:0]$14769 $4\xive10_pri$next[7:0]$14833 + assign $0\xive11_pri$next[7:0]$14770 $4\xive11_pri$next[7:0]$14834 + assign $0\xive12_pri$next[7:0]$14771 $4\xive12_pri$next[7:0]$14835 + assign $0\xive13_pri$next[7:0]$14772 $4\xive13_pri$next[7:0]$14836 + assign $0\xive14_pri$next[7:0]$14773 $4\xive14_pri$next[7:0]$14837 + assign $0\xive15_pri$next[7:0]$14774 $4\xive15_pri$next[7:0]$14838 + assign $0\xive1_pri$next[7:0]$14775 $4\xive1_pri$next[7:0]$14839 + assign $0\xive2_pri$next[7:0]$14776 $4\xive2_pri$next[7:0]$14840 + assign $0\xive3_pri$next[7:0]$14777 $4\xive3_pri$next[7:0]$14841 + assign $0\xive4_pri$next[7:0]$14778 $4\xive4_pri$next[7:0]$14842 + assign $0\xive5_pri$next[7:0]$14779 $4\xive5_pri$next[7:0]$14843 + assign $0\xive6_pri$next[7:0]$14780 $4\xive6_pri$next[7:0]$14844 + assign $0\xive7_pri$next[7:0]$14781 $4\xive7_pri$next[7:0]$14845 + assign $0\xive8_pri$next[7:0]$14782 $4\xive8_pri$next[7:0]$14846 + assign $0\xive9_pri$next[7:0]$14783 $4\xive9_pri$next[7:0]$14847 + attribute \src "libresoc.v:200611.5-200611.29" switch \initial - attribute \src "libresoc.v:189796.9-189796.17" + attribute \src "libresoc.v:200611.9-200611.17" case 1'1 case end @@ -402034,22 +421821,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14494 $2\xive0_pri$next[7:0]$14510 - assign $1\xive10_pri$next[7:0]$14495 $2\xive10_pri$next[7:0]$14511 - assign $1\xive11_pri$next[7:0]$14496 $2\xive11_pri$next[7:0]$14512 - assign $1\xive12_pri$next[7:0]$14497 $2\xive12_pri$next[7:0]$14513 - assign $1\xive13_pri$next[7:0]$14498 $2\xive13_pri$next[7:0]$14514 - assign $1\xive14_pri$next[7:0]$14499 $2\xive14_pri$next[7:0]$14515 - assign $1\xive15_pri$next[7:0]$14500 $2\xive15_pri$next[7:0]$14516 - assign $1\xive1_pri$next[7:0]$14501 $2\xive1_pri$next[7:0]$14517 - assign $1\xive2_pri$next[7:0]$14502 $2\xive2_pri$next[7:0]$14518 - assign $1\xive3_pri$next[7:0]$14503 $2\xive3_pri$next[7:0]$14519 - assign $1\xive4_pri$next[7:0]$14504 $2\xive4_pri$next[7:0]$14520 - assign $1\xive5_pri$next[7:0]$14505 $2\xive5_pri$next[7:0]$14521 - assign $1\xive6_pri$next[7:0]$14506 $2\xive6_pri$next[7:0]$14522 - assign $1\xive7_pri$next[7:0]$14507 $2\xive7_pri$next[7:0]$14523 - assign $1\xive8_pri$next[7:0]$14508 $2\xive8_pri$next[7:0]$14524 - assign $1\xive9_pri$next[7:0]$14509 $2\xive9_pri$next[7:0]$14525 + assign $1\xive0_pri$next[7:0]$14784 $2\xive0_pri$next[7:0]$14800 + assign $1\xive10_pri$next[7:0]$14785 $2\xive10_pri$next[7:0]$14801 + assign $1\xive11_pri$next[7:0]$14786 $2\xive11_pri$next[7:0]$14802 + assign $1\xive12_pri$next[7:0]$14787 $2\xive12_pri$next[7:0]$14803 + assign $1\xive13_pri$next[7:0]$14788 $2\xive13_pri$next[7:0]$14804 + assign $1\xive14_pri$next[7:0]$14789 $2\xive14_pri$next[7:0]$14805 + assign $1\xive15_pri$next[7:0]$14790 $2\xive15_pri$next[7:0]$14806 + assign $1\xive1_pri$next[7:0]$14791 $2\xive1_pri$next[7:0]$14807 + assign $1\xive2_pri$next[7:0]$14792 $2\xive2_pri$next[7:0]$14808 + assign $1\xive3_pri$next[7:0]$14793 $2\xive3_pri$next[7:0]$14809 + assign $1\xive4_pri$next[7:0]$14794 $2\xive4_pri$next[7:0]$14810 + assign $1\xive5_pri$next[7:0]$14795 $2\xive5_pri$next[7:0]$14811 + assign $1\xive6_pri$next[7:0]$14796 $2\xive6_pri$next[7:0]$14812 + assign $1\xive7_pri$next[7:0]$14797 $2\xive7_pri$next[7:0]$14813 + assign $1\xive8_pri$next[7:0]$14798 $2\xive8_pri$next[7:0]$14814 + assign $1\xive9_pri$next[7:0]$14799 $2\xive9_pri$next[7:0]$14815 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -402070,381 +421857,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14510 $3\xive0_pri$next[7:0]$14526 - assign $2\xive10_pri$next[7:0]$14511 $3\xive10_pri$next[7:0]$14527 - assign $2\xive11_pri$next[7:0]$14512 $3\xive11_pri$next[7:0]$14528 - assign $2\xive12_pri$next[7:0]$14513 $3\xive12_pri$next[7:0]$14529 - assign $2\xive13_pri$next[7:0]$14514 $3\xive13_pri$next[7:0]$14530 - assign $2\xive14_pri$next[7:0]$14515 $3\xive14_pri$next[7:0]$14531 - assign $2\xive15_pri$next[7:0]$14516 $3\xive15_pri$next[7:0]$14532 - assign $2\xive1_pri$next[7:0]$14517 $3\xive1_pri$next[7:0]$14533 - assign $2\xive2_pri$next[7:0]$14518 $3\xive2_pri$next[7:0]$14534 - assign $2\xive3_pri$next[7:0]$14519 $3\xive3_pri$next[7:0]$14535 - assign $2\xive4_pri$next[7:0]$14520 $3\xive4_pri$next[7:0]$14536 - assign $2\xive5_pri$next[7:0]$14521 $3\xive5_pri$next[7:0]$14537 - assign $2\xive6_pri$next[7:0]$14522 $3\xive6_pri$next[7:0]$14538 - assign $2\xive7_pri$next[7:0]$14523 $3\xive7_pri$next[7:0]$14539 - assign $2\xive8_pri$next[7:0]$14524 $3\xive8_pri$next[7:0]$14540 - assign $2\xive9_pri$next[7:0]$14525 $3\xive9_pri$next[7:0]$14541 + assign $2\xive0_pri$next[7:0]$14800 $3\xive0_pri$next[7:0]$14816 + assign $2\xive10_pri$next[7:0]$14801 $3\xive10_pri$next[7:0]$14817 + assign $2\xive11_pri$next[7:0]$14802 $3\xive11_pri$next[7:0]$14818 + assign $2\xive12_pri$next[7:0]$14803 $3\xive12_pri$next[7:0]$14819 + assign $2\xive13_pri$next[7:0]$14804 $3\xive13_pri$next[7:0]$14820 + assign $2\xive14_pri$next[7:0]$14805 $3\xive14_pri$next[7:0]$14821 + assign $2\xive15_pri$next[7:0]$14806 $3\xive15_pri$next[7:0]$14822 + assign $2\xive1_pri$next[7:0]$14807 $3\xive1_pri$next[7:0]$14823 + assign $2\xive2_pri$next[7:0]$14808 $3\xive2_pri$next[7:0]$14824 + assign $2\xive3_pri$next[7:0]$14809 $3\xive3_pri$next[7:0]$14825 + assign $2\xive4_pri$next[7:0]$14810 $3\xive4_pri$next[7:0]$14826 + assign $2\xive5_pri$next[7:0]$14811 $3\xive5_pri$next[7:0]$14827 + assign $2\xive6_pri$next[7:0]$14812 $3\xive6_pri$next[7:0]$14828 + assign $2\xive7_pri$next[7:0]$14813 $3\xive7_pri$next[7:0]$14829 + assign $2\xive8_pri$next[7:0]$14814 $3\xive8_pri$next[7:0]$14830 + assign $2\xive9_pri$next[7:0]$14815 $3\xive9_pri$next[7:0]$14831 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive0_pri$next[7:0]$14526 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive0_pri$next[7:0]$14816 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive1_pri$next[7:0]$14533 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive1_pri$next[7:0]$14823 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive2_pri$next[7:0]$14534 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive2_pri$next[7:0]$14824 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive3_pri$next[7:0]$14535 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive3_pri$next[7:0]$14825 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive4_pri$next[7:0]$14536 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive4_pri$next[7:0]$14826 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive5_pri$next[7:0]$14537 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive5_pri$next[7:0]$14827 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive6_pri$next[7:0]$14538 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive6_pri$next[7:0]$14828 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive7_pri$next[7:0]$14539 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive7_pri$next[7:0]$14829 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive8_pri$next[7:0]$14540 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive8_pri$next[7:0]$14830 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14541 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14831 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive10_pri$next[7:0]$14527 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive10_pri$next[7:0]$14817 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive11_pri$next[7:0]$14528 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive11_pri$next[7:0]$14818 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive12_pri$next[7:0]$14529 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive12_pri$next[7:0]$14819 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive13_pri$next[7:0]$14530 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive13_pri$next[7:0]$14820 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive14_pri$next[7:0]$14531 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive14_pri$next[7:0]$14821 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri - assign $3\xive15_pri$next[7:0]$14532 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive15_pri$next[7:0]$14822 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$14526 \xive0_pri - assign $3\xive10_pri$next[7:0]$14527 \xive10_pri - assign $3\xive11_pri$next[7:0]$14528 \xive11_pri - assign $3\xive12_pri$next[7:0]$14529 \xive12_pri - assign $3\xive13_pri$next[7:0]$14530 \xive13_pri - assign $3\xive14_pri$next[7:0]$14531 \xive14_pri - assign $3\xive15_pri$next[7:0]$14532 \xive15_pri - assign $3\xive1_pri$next[7:0]$14533 \xive1_pri - assign $3\xive2_pri$next[7:0]$14534 \xive2_pri - assign $3\xive3_pri$next[7:0]$14535 \xive3_pri - assign $3\xive4_pri$next[7:0]$14536 \xive4_pri - assign $3\xive5_pri$next[7:0]$14537 \xive5_pri - assign $3\xive6_pri$next[7:0]$14538 \xive6_pri - assign $3\xive7_pri$next[7:0]$14539 \xive7_pri - assign $3\xive8_pri$next[7:0]$14540 \xive8_pri - assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14510 \xive0_pri - assign $2\xive10_pri$next[7:0]$14511 \xive10_pri - assign $2\xive11_pri$next[7:0]$14512 \xive11_pri - assign $2\xive12_pri$next[7:0]$14513 \xive12_pri - assign $2\xive13_pri$next[7:0]$14514 \xive13_pri - assign $2\xive14_pri$next[7:0]$14515 \xive14_pri - assign $2\xive15_pri$next[7:0]$14516 \xive15_pri - assign $2\xive1_pri$next[7:0]$14517 \xive1_pri - assign $2\xive2_pri$next[7:0]$14518 \xive2_pri - assign $2\xive3_pri$next[7:0]$14519 \xive3_pri - assign $2\xive4_pri$next[7:0]$14520 \xive4_pri - assign $2\xive5_pri$next[7:0]$14521 \xive5_pri - assign $2\xive6_pri$next[7:0]$14522 \xive6_pri - assign $2\xive7_pri$next[7:0]$14523 \xive7_pri - assign $2\xive8_pri$next[7:0]$14524 \xive8_pri - assign $2\xive9_pri$next[7:0]$14525 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14494 \xive0_pri - assign $1\xive10_pri$next[7:0]$14495 \xive10_pri - assign $1\xive11_pri$next[7:0]$14496 \xive11_pri - assign $1\xive12_pri$next[7:0]$14497 \xive12_pri - assign $1\xive13_pri$next[7:0]$14498 \xive13_pri - assign $1\xive14_pri$next[7:0]$14499 \xive14_pri - assign $1\xive15_pri$next[7:0]$14500 \xive15_pri - assign $1\xive1_pri$next[7:0]$14501 \xive1_pri - assign $1\xive2_pri$next[7:0]$14502 \xive2_pri - assign $1\xive3_pri$next[7:0]$14503 \xive3_pri - assign $1\xive4_pri$next[7:0]$14504 \xive4_pri - assign $1\xive5_pri$next[7:0]$14505 \xive5_pri - assign $1\xive6_pri$next[7:0]$14506 \xive6_pri - assign $1\xive7_pri$next[7:0]$14507 \xive7_pri - assign $1\xive8_pri$next[7:0]$14508 \xive8_pri - assign $1\xive9_pri$next[7:0]$14509 \xive9_pri + assign $2\xive0_pri$next[7:0]$14800 \xive0_pri + assign $2\xive10_pri$next[7:0]$14801 \xive10_pri + assign $2\xive11_pri$next[7:0]$14802 \xive11_pri + assign $2\xive12_pri$next[7:0]$14803 \xive12_pri + assign $2\xive13_pri$next[7:0]$14804 \xive13_pri + assign $2\xive14_pri$next[7:0]$14805 \xive14_pri + assign $2\xive15_pri$next[7:0]$14806 \xive15_pri + assign $2\xive1_pri$next[7:0]$14807 \xive1_pri + assign $2\xive2_pri$next[7:0]$14808 \xive2_pri + assign $2\xive3_pri$next[7:0]$14809 \xive3_pri + assign $2\xive4_pri$next[7:0]$14810 \xive4_pri + assign $2\xive5_pri$next[7:0]$14811 \xive5_pri + assign $2\xive6_pri$next[7:0]$14812 \xive6_pri + assign $2\xive7_pri$next[7:0]$14813 \xive7_pri + assign $2\xive8_pri$next[7:0]$14814 \xive8_pri + assign $2\xive9_pri$next[7:0]$14815 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14784 \xive0_pri + assign $1\xive10_pri$next[7:0]$14785 \xive10_pri + assign $1\xive11_pri$next[7:0]$14786 \xive11_pri + assign $1\xive12_pri$next[7:0]$14787 \xive12_pri + assign $1\xive13_pri$next[7:0]$14788 \xive13_pri + assign $1\xive14_pri$next[7:0]$14789 \xive14_pri + assign $1\xive15_pri$next[7:0]$14790 \xive15_pri + assign $1\xive1_pri$next[7:0]$14791 \xive1_pri + assign $1\xive2_pri$next[7:0]$14792 \xive2_pri + assign $1\xive3_pri$next[7:0]$14793 \xive3_pri + assign $1\xive4_pri$next[7:0]$14794 \xive4_pri + assign $1\xive5_pri$next[7:0]$14795 \xive5_pri + assign $1\xive6_pri$next[7:0]$14796 \xive6_pri + assign $1\xive7_pri$next[7:0]$14797 \xive7_pri + assign $1\xive8_pri$next[7:0]$14798 \xive8_pri + assign $1\xive9_pri$next[7:0]$14799 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -402466,66 +422253,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$14542 8'11111111 - assign $4\xive1_pri$next[7:0]$14549 8'11111111 - assign $4\xive2_pri$next[7:0]$14550 8'11111111 - assign $4\xive3_pri$next[7:0]$14551 8'11111111 - assign $4\xive4_pri$next[7:0]$14552 8'11111111 - assign $4\xive5_pri$next[7:0]$14553 8'11111111 - assign $4\xive6_pri$next[7:0]$14554 8'11111111 - assign $4\xive7_pri$next[7:0]$14555 8'11111111 - assign $4\xive8_pri$next[7:0]$14556 8'11111111 - assign $4\xive9_pri$next[7:0]$14557 8'11111111 - assign $4\xive10_pri$next[7:0]$14543 8'11111111 - assign $4\xive11_pri$next[7:0]$14544 8'11111111 - assign $4\xive12_pri$next[7:0]$14545 8'11111111 - assign $4\xive13_pri$next[7:0]$14546 8'11111111 - assign $4\xive14_pri$next[7:0]$14547 8'11111111 - assign $4\xive15_pri$next[7:0]$14548 8'11111111 + assign $4\xive0_pri$next[7:0]$14832 8'11111111 + assign $4\xive1_pri$next[7:0]$14839 8'11111111 + assign $4\xive2_pri$next[7:0]$14840 8'11111111 + assign $4\xive3_pri$next[7:0]$14841 8'11111111 + assign $4\xive4_pri$next[7:0]$14842 8'11111111 + assign $4\xive5_pri$next[7:0]$14843 8'11111111 + assign $4\xive6_pri$next[7:0]$14844 8'11111111 + assign $4\xive7_pri$next[7:0]$14845 8'11111111 + assign $4\xive8_pri$next[7:0]$14846 8'11111111 + assign $4\xive9_pri$next[7:0]$14847 8'11111111 + assign $4\xive10_pri$next[7:0]$14833 8'11111111 + assign $4\xive11_pri$next[7:0]$14834 8'11111111 + assign $4\xive12_pri$next[7:0]$14835 8'11111111 + assign $4\xive13_pri$next[7:0]$14836 8'11111111 + assign $4\xive14_pri$next[7:0]$14837 8'11111111 + assign $4\xive15_pri$next[7:0]$14838 8'11111111 case - assign $4\xive0_pri$next[7:0]$14542 $1\xive0_pri$next[7:0]$14494 - assign $4\xive10_pri$next[7:0]$14543 $1\xive10_pri$next[7:0]$14495 - assign $4\xive11_pri$next[7:0]$14544 $1\xive11_pri$next[7:0]$14496 - assign $4\xive12_pri$next[7:0]$14545 $1\xive12_pri$next[7:0]$14497 - assign $4\xive13_pri$next[7:0]$14546 $1\xive13_pri$next[7:0]$14498 - assign $4\xive14_pri$next[7:0]$14547 $1\xive14_pri$next[7:0]$14499 - assign $4\xive15_pri$next[7:0]$14548 $1\xive15_pri$next[7:0]$14500 - assign $4\xive1_pri$next[7:0]$14549 $1\xive1_pri$next[7:0]$14501 - assign $4\xive2_pri$next[7:0]$14550 $1\xive2_pri$next[7:0]$14502 - assign $4\xive3_pri$next[7:0]$14551 $1\xive3_pri$next[7:0]$14503 - assign $4\xive4_pri$next[7:0]$14552 $1\xive4_pri$next[7:0]$14504 - assign $4\xive5_pri$next[7:0]$14553 $1\xive5_pri$next[7:0]$14505 - assign $4\xive6_pri$next[7:0]$14554 $1\xive6_pri$next[7:0]$14506 - assign $4\xive7_pri$next[7:0]$14555 $1\xive7_pri$next[7:0]$14507 - assign $4\xive8_pri$next[7:0]$14556 $1\xive8_pri$next[7:0]$14508 - assign $4\xive9_pri$next[7:0]$14557 $1\xive9_pri$next[7:0]$14509 + assign $4\xive0_pri$next[7:0]$14832 $1\xive0_pri$next[7:0]$14784 + assign $4\xive10_pri$next[7:0]$14833 $1\xive10_pri$next[7:0]$14785 + assign $4\xive11_pri$next[7:0]$14834 $1\xive11_pri$next[7:0]$14786 + assign $4\xive12_pri$next[7:0]$14835 $1\xive12_pri$next[7:0]$14787 + assign $4\xive13_pri$next[7:0]$14836 $1\xive13_pri$next[7:0]$14788 + assign $4\xive14_pri$next[7:0]$14837 $1\xive14_pri$next[7:0]$14789 + assign $4\xive15_pri$next[7:0]$14838 $1\xive15_pri$next[7:0]$14790 + assign $4\xive1_pri$next[7:0]$14839 $1\xive1_pri$next[7:0]$14791 + assign $4\xive2_pri$next[7:0]$14840 $1\xive2_pri$next[7:0]$14792 + assign $4\xive3_pri$next[7:0]$14841 $1\xive3_pri$next[7:0]$14793 + assign $4\xive4_pri$next[7:0]$14842 $1\xive4_pri$next[7:0]$14794 + assign $4\xive5_pri$next[7:0]$14843 $1\xive5_pri$next[7:0]$14795 + assign $4\xive6_pri$next[7:0]$14844 $1\xive6_pri$next[7:0]$14796 + assign $4\xive7_pri$next[7:0]$14845 $1\xive7_pri$next[7:0]$14797 + assign $4\xive8_pri$next[7:0]$14846 $1\xive8_pri$next[7:0]$14798 + assign $4\xive9_pri$next[7:0]$14847 $1\xive9_pri$next[7:0]$14799 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14478 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14479 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14480 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14481 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14482 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14483 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14484 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14485 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14486 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14487 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14488 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14489 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14490 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14491 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14492 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14493 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14768 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14769 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14770 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14771 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14772 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14773 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14774 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14775 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14776 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14777 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14778 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14779 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14780 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14781 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14782 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14783 end - attribute \src "libresoc.v:189881.3-189890.6" - process $proc$libresoc.v:189881$14558 + attribute \src "libresoc.v:200696.3-200705.6" + process $proc$libresoc.v:200696$14848 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:189882.5-189882.29" + attribute \src "libresoc.v:200697.5-200697.29" switch \initial - attribute \src "libresoc.v:189882.9-189882.17" + attribute \src "libresoc.v:200697.9-200697.17" case 1'1 case end @@ -402541,14 +422328,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:189891.3-189900.6" - process $proc$libresoc.v:189891$14559 + attribute \src "libresoc.v:200706.3-200715.6" + process $proc$libresoc.v:200706$14849 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:189892.5-189892.29" + attribute \src "libresoc.v:200707.5-200707.29" switch \initial - attribute \src "libresoc.v:189892.9-189892.17" + attribute \src "libresoc.v:200707.9-200707.17" case 1'1 case end @@ -402564,14 +422351,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:189901.3-189910.6" - process $proc$libresoc.v:189901$14560 + attribute \src "libresoc.v:200716.3-200725.6" + process $proc$libresoc.v:200716$14850 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:189902.5-189902.29" + attribute \src "libresoc.v:200717.5-200717.29" switch \initial - attribute \src "libresoc.v:189902.9-189902.17" + attribute \src "libresoc.v:200717.9-200717.17" case 1'1 case end @@ -402587,14 +422374,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:189911.3-189920.6" - process $proc$libresoc.v:189911$14561 + attribute \src "libresoc.v:200726.3-200735.6" + process $proc$libresoc.v:200726$14851 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:189912.5-189912.29" + attribute \src "libresoc.v:200727.5-200727.29" switch \initial - attribute \src "libresoc.v:189912.9-189912.17" + attribute \src "libresoc.v:200727.9-200727.17" case 1'1 case end @@ -402610,14 +422397,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:189921.3-189930.6" - process $proc$libresoc.v:189921$14562 + attribute \src "libresoc.v:200736.3-200745.6" + process $proc$libresoc.v:200736$14852 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:189922.5-189922.29" + attribute \src "libresoc.v:200737.5-200737.29" switch \initial - attribute \src "libresoc.v:189922.9-189922.17" + attribute \src "libresoc.v:200737.9-200737.17" case 1'1 case end @@ -402633,14 +422420,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:189931.3-189940.6" - process $proc$libresoc.v:189931$14563 + attribute \src "libresoc.v:200746.3-200755.6" + process $proc$libresoc.v:200746$14853 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:189932.5-189932.29" + attribute \src "libresoc.v:200747.5-200747.29" switch \initial - attribute \src "libresoc.v:189932.9-189932.17" + attribute \src "libresoc.v:200747.9-200747.17" case 1'1 case end @@ -402656,14 +422443,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:189941.3-189950.6" - process $proc$libresoc.v:189941$14564 + attribute \src "libresoc.v:200756.3-200765.6" + process $proc$libresoc.v:200756$14854 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:189942.5-189942.29" + attribute \src "libresoc.v:200757.5-200757.29" switch \initial - attribute \src "libresoc.v:189942.9-189942.17" + attribute \src "libresoc.v:200757.9-200757.17" case 1'1 case end @@ -402679,14 +422466,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:189951.3-189960.6" - process $proc$libresoc.v:189951$14565 + attribute \src "libresoc.v:200766.3-200775.6" + process $proc$libresoc.v:200766$14855 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:189952.5-189952.29" + attribute \src "libresoc.v:200767.5-200767.29" switch \initial - attribute \src "libresoc.v:189952.9-189952.17" + attribute \src "libresoc.v:200767.9-200767.17" case 1'1 case end @@ -402702,14 +422489,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:189961.3-189970.6" - process $proc$libresoc.v:189961$14566 + attribute \src "libresoc.v:200776.3-200785.6" + process $proc$libresoc.v:200776$14856 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:189962.5-189962.29" + attribute \src "libresoc.v:200777.5-200777.29" switch \initial - attribute \src "libresoc.v:189962.9-189962.17" + attribute \src "libresoc.v:200777.9-200777.17" case 1'1 case end @@ -402725,14 +422512,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:189971.3-189979.6" - process $proc$libresoc.v:189971$14567 + attribute \src "libresoc.v:200786.3-200794.6" + process $proc$libresoc.v:200786$14857 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$14568 $1\int_level_l$next[15:0]$14569 - attribute \src "libresoc.v:189972.5-189972.29" + assign $0\int_level_l$next[15:0]$14858 $1\int_level_l$next[15:0]$14859 + attribute \src "libresoc.v:200787.5-200787.29" switch \initial - attribute \src "libresoc.v:189972.9-189972.17" + attribute \src "libresoc.v:200787.9-200787.17" case 1'1 case end @@ -402741,21 +422528,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$14569 16'0000000000000000 + assign $1\int_level_l$next[15:0]$14859 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$14569 \int_level_i + assign $1\int_level_l$next[15:0]$14859 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$14568 + update \int_level_l$next $0\int_level_l$next[15:0]$14858 end - attribute \src "libresoc.v:189980.3-189989.6" - process $proc$libresoc.v:189980$14570 + attribute \src "libresoc.v:200795.3-200804.6" + process $proc$libresoc.v:200795$14860 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:189981.5-189981.29" + attribute \src "libresoc.v:200796.5-200796.29" switch \initial - attribute \src "libresoc.v:189981.9-189981.17" + attribute \src "libresoc.v:200796.9-200796.17" case 1'1 case end @@ -402771,14 +422558,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:189990.3-189999.6" - process $proc$libresoc.v:189990$14571 + attribute \src "libresoc.v:200805.3-200814.6" + process $proc$libresoc.v:200805$14861 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:189991.5-189991.29" + attribute \src "libresoc.v:200806.5-200806.29" switch \initial - attribute \src "libresoc.v:189991.9-189991.17" + attribute \src "libresoc.v:200806.9-200806.17" case 1'1 case end @@ -402794,14 +422581,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:190000.3-190009.6" - process $proc$libresoc.v:190000$14572 + attribute \src "libresoc.v:200815.3-200824.6" + process $proc$libresoc.v:200815$14862 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:190001.5-190001.29" + attribute \src "libresoc.v:200816.5-200816.29" switch \initial - attribute \src "libresoc.v:190001.9-190001.17" + attribute \src "libresoc.v:200816.9-200816.17" case 1'1 case end @@ -402817,14 +422604,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:190010.3-190019.6" - process $proc$libresoc.v:190010$14573 + attribute \src "libresoc.v:200825.3-200834.6" + process $proc$libresoc.v:200825$14863 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:190011.5-190011.29" + attribute \src "libresoc.v:200826.5-200826.29" switch \initial - attribute \src "libresoc.v:190011.9-190011.17" + attribute \src "libresoc.v:200826.9-200826.17" case 1'1 case end @@ -402840,14 +422627,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:190020.3-190029.6" - process $proc$libresoc.v:190020$14574 + attribute \src "libresoc.v:200835.3-200844.6" + process $proc$libresoc.v:200835$14864 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:190021.5-190021.29" + attribute \src "libresoc.v:200836.5-200836.29" switch \initial - attribute \src "libresoc.v:190021.9-190021.17" + attribute \src "libresoc.v:200836.9-200836.17" case 1'1 case end @@ -402863,14 +422650,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:190030.3-190039.6" - process $proc$libresoc.v:190030$14575 + attribute \src "libresoc.v:200845.3-200854.6" + process $proc$libresoc.v:200845$14865 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:190031.5-190031.29" + attribute \src "libresoc.v:200846.5-200846.29" switch \initial - attribute \src "libresoc.v:190031.9-190031.17" + attribute \src "libresoc.v:200846.9-200846.17" case 1'1 case end @@ -402886,14 +422673,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:190040.3-190049.6" - process $proc$libresoc.v:190040$14576 + attribute \src "libresoc.v:200855.3-200864.6" + process $proc$libresoc.v:200855$14866 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:190041.5-190041.29" + attribute \src "libresoc.v:200856.5-200856.29" switch \initial - attribute \src "libresoc.v:190041.9-190041.17" + attribute \src "libresoc.v:200856.9-200856.17" case 1'1 case end @@ -402909,14 +422696,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:190050.3-190059.6" - process $proc$libresoc.v:190050$14577 + attribute \src "libresoc.v:200865.3-200874.6" + process $proc$libresoc.v:200865$14867 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:190051.5-190051.29" + attribute \src "libresoc.v:200866.5-200866.29" switch \initial - attribute \src "libresoc.v:190051.9-190051.17" + attribute \src "libresoc.v:200866.9-200866.17" case 1'1 case end @@ -402932,14 +422719,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:190060.3-190069.6" - process $proc$libresoc.v:190060$14578 + attribute \src "libresoc.v:200875.3-200884.6" + process $proc$libresoc.v:200875$14868 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:190061.5-190061.29" + attribute \src "libresoc.v:200876.5-200876.29" switch \initial - attribute \src "libresoc.v:190061.9-190061.17" + attribute \src "libresoc.v:200876.9-200876.17" case 1'1 case end @@ -402955,14 +422742,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:190070.3-190079.6" - process $proc$libresoc.v:190070$14579 + attribute \src "libresoc.v:200885.3-200894.6" + process $proc$libresoc.v:200885$14869 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:190071.5-190071.29" + attribute \src "libresoc.v:200886.5-200886.29" switch \initial - attribute \src "libresoc.v:190071.9-190071.17" + attribute \src "libresoc.v:200886.9-200886.17" case 1'1 case end @@ -402978,14 +422765,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:190080.3-190089.6" - process $proc$libresoc.v:190080$14580 + attribute \src "libresoc.v:200895.3-200904.6" + process $proc$libresoc.v:200895$14870 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:190081.5-190081.29" + attribute \src "libresoc.v:200896.5-200896.29" switch \initial - attribute \src "libresoc.v:190081.9-190081.17" + attribute \src "libresoc.v:200896.9-200896.17" case 1'1 case end @@ -403001,14 +422788,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:190090.3-190099.6" - process $proc$libresoc.v:190090$14581 + attribute \src "libresoc.v:200905.3-200914.6" + process $proc$libresoc.v:200905$14871 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:190091.5-190091.29" + attribute \src "libresoc.v:200906.5-200906.29" switch \initial - attribute \src "libresoc.v:190091.9-190091.17" + attribute \src "libresoc.v:200906.9-200906.17" case 1'1 case end @@ -403024,14 +422811,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:190100.3-190109.6" - process $proc$libresoc.v:190100$14582 + attribute \src "libresoc.v:200915.3-200924.6" + process $proc$libresoc.v:200915$14872 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:190101.5-190101.29" + attribute \src "libresoc.v:200916.5-200916.29" switch \initial - attribute \src "libresoc.v:190101.9-190101.17" + attribute \src "libresoc.v:200916.9-200916.17" case 1'1 case end @@ -403047,14 +422834,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:190110.3-190119.6" - process $proc$libresoc.v:190110$14583 + attribute \src "libresoc.v:200925.3-200934.6" + process $proc$libresoc.v:200925$14873 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:190111.5-190111.29" + attribute \src "libresoc.v:200926.5-200926.29" switch \initial - attribute \src "libresoc.v:190111.9-190111.17" + attribute \src "libresoc.v:200926.9-200926.17" case 1'1 case end @@ -403070,14 +422857,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:190120.3-190129.6" - process $proc$libresoc.v:190120$14584 + attribute \src "libresoc.v:200935.3-200944.6" + process $proc$libresoc.v:200935$14874 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:190121.5-190121.29" + attribute \src "libresoc.v:200936.5-200936.29" switch \initial - attribute \src "libresoc.v:190121.9-190121.17" + attribute \src "libresoc.v:200936.9-200936.17" case 1'1 case end @@ -403093,14 +422880,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:190130.3-190139.6" - process $proc$libresoc.v:190130$14585 + attribute \src "libresoc.v:200945.3-200954.6" + process $proc$libresoc.v:200945$14875 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:190131.5-190131.29" + attribute \src "libresoc.v:200946.5-200946.29" switch \initial - attribute \src "libresoc.v:190131.9-190131.17" + attribute \src "libresoc.v:200946.9-200946.17" case 1'1 case end @@ -403116,14 +422903,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:190140.3-190149.6" - process $proc$libresoc.v:190140$14586 + attribute \src "libresoc.v:200955.3-200964.6" + process $proc$libresoc.v:200955$14876 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:190141.5-190141.29" + attribute \src "libresoc.v:200956.5-200956.29" switch \initial - attribute \src "libresoc.v:190141.9-190141.17" + attribute \src "libresoc.v:200956.9-200956.17" case 1'1 case end @@ -403139,14 +422926,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:190150.3-190159.6" - process $proc$libresoc.v:190150$14587 + attribute \src "libresoc.v:200965.3-200974.6" + process $proc$libresoc.v:200965$14877 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:190151.5-190151.29" + attribute \src "libresoc.v:200966.5-200966.29" switch \initial - attribute \src "libresoc.v:190151.9-190151.17" + attribute \src "libresoc.v:200966.9-200966.17" case 1'1 case end @@ -403162,14 +422949,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:190160.3-190169.6" - process $proc$libresoc.v:190160$14588 + attribute \src "libresoc.v:200975.3-200984.6" + process $proc$libresoc.v:200975$14878 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:190161.5-190161.29" + attribute \src "libresoc.v:200976.5-200976.29" switch \initial - attribute \src "libresoc.v:190161.9-190161.17" + attribute \src "libresoc.v:200976.9-200976.17" case 1'1 case end @@ -403185,14 +422972,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:190170.3-190179.6" - process $proc$libresoc.v:190170$14589 + attribute \src "libresoc.v:200985.3-200994.6" + process $proc$libresoc.v:200985$14879 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:190171.5-190171.29" + attribute \src "libresoc.v:200986.5-200986.29" switch \initial - attribute \src "libresoc.v:190171.9-190171.17" + attribute \src "libresoc.v:200986.9-200986.17" case 1'1 case end @@ -403208,14 +422995,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:190180.3-190229.6" - process $proc$libresoc.v:190180$14590 + attribute \src "libresoc.v:200995.3-201044.6" + process $proc$libresoc.v:200995$14880 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:190181.5-190181.29" + attribute \src "libresoc.v:200996.5-200996.29" switch \initial - attribute \src "libresoc.v:190181.9-190181.17" + attribute \src "libresoc.v:200996.9-200996.17" case 1'1 case end @@ -403308,14 +423095,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:190230.3-190239.6" - process $proc$libresoc.v:190230$14591 + attribute \src "libresoc.v:201045.3-201054.6" + process $proc$libresoc.v:201045$14881 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:190231.5-190231.29" + attribute \src "libresoc.v:201046.5-201046.29" switch \initial - attribute \src "libresoc.v:190231.9-190231.17" + attribute \src "libresoc.v:201046.9-201046.17" case 1'1 case end @@ -403331,14 +423118,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:190240.3-190249.6" - process $proc$libresoc.v:190240$14592 + attribute \src "libresoc.v:201055.3-201064.6" + process $proc$libresoc.v:201055$14882 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:190241.5-190241.29" + attribute \src "libresoc.v:201056.5-201056.29" switch \initial - attribute \src "libresoc.v:190241.9-190241.17" + attribute \src "libresoc.v:201056.9-201056.17" case 1'1 case end @@ -403354,14 +423141,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:190250.3-190259.6" - process $proc$libresoc.v:190250$14593 + attribute \src "libresoc.v:201065.3-201074.6" + process $proc$libresoc.v:201065$14883 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:190251.5-190251.29" + attribute \src "libresoc.v:201066.5-201066.29" switch \initial - attribute \src "libresoc.v:190251.9-190251.17" + attribute \src "libresoc.v:201066.9-201066.17" case 1'1 case end @@ -403377,14 +423164,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:190260.3-190269.6" - process $proc$libresoc.v:190260$14594 + attribute \src "libresoc.v:201075.3-201084.6" + process $proc$libresoc.v:201075$14884 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:190261.5-190261.29" + attribute \src "libresoc.v:201076.5-201076.29" switch \initial - attribute \src "libresoc.v:190261.9-190261.17" + attribute \src "libresoc.v:201076.9-201076.17" case 1'1 case end @@ -403400,14 +423187,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:190270.3-190278.6" - process $proc$libresoc.v:190270$14595 + attribute \src "libresoc.v:201085.3-201093.6" + process $proc$libresoc.v:201085$14885 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$14596 $1\ics_wb__dat_r$next[31:0]$14597 - attribute \src "libresoc.v:190271.5-190271.29" + assign $0\ics_wb__dat_r$next[31:0]$14886 $1\ics_wb__dat_r$next[31:0]$14887 + attribute \src "libresoc.v:201086.5-201086.29" switch \initial - attribute \src "libresoc.v:190271.9-190271.17" + attribute \src "libresoc.v:201086.9-201086.17" case 1'1 case end @@ -403416,21 +423203,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$14597 0 + assign $1\ics_wb__dat_r$next[31:0]$14887 0 case - assign $1\ics_wb__dat_r$next[31:0]$14597 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$14887 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14596 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14886 end - attribute \src "libresoc.v:190279.3-190287.6" - process $proc$libresoc.v:190279$14598 + attribute \src "libresoc.v:201094.3-201102.6" + process $proc$libresoc.v:201094$14888 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$14599 $1\ics_wb__ack$next[0:0]$14600 - attribute \src "libresoc.v:190280.5-190280.29" + assign $0\ics_wb__ack$next[0:0]$14889 $1\ics_wb__ack$next[0:0]$14890 + attribute \src "libresoc.v:201095.5-201095.29" switch \initial - attribute \src "libresoc.v:190280.9-190280.17" + attribute \src "libresoc.v:201095.9-201095.17" case 1'1 case end @@ -403439,116 +423226,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$14600 1'0 - case - assign $1\ics_wb__ack$next[0:0]$14600 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14599 - end - connect \$7 $ternary$libresoc.v:189650$14353_Y - connect \$99 $lt$libresoc.v:189651$14354_Y - connect \$101 $and$libresoc.v:189652$14355_Y - connect \$103 $lt$libresoc.v:189653$14356_Y - connect \$105 $and$libresoc.v:189654$14357_Y - connect \$107 $lt$libresoc.v:189655$14358_Y - connect \$109 $and$libresoc.v:189656$14359_Y - connect \$111 $lt$libresoc.v:189657$14360_Y - connect \$113 $and$libresoc.v:189658$14361_Y - connect \$115 $lt$libresoc.v:189659$14362_Y - connect \$117 $and$libresoc.v:189660$14363_Y - connect \$119 $lt$libresoc.v:189661$14364_Y - connect \$121 $and$libresoc.v:189662$14365_Y - connect \$123 $lt$libresoc.v:189663$14366_Y - connect \$125 $and$libresoc.v:189664$14367_Y - connect \$127 $lt$libresoc.v:189665$14368_Y - connect \$12 $eq$libresoc.v:189666$14369_Y - connect \$129 $and$libresoc.v:189667$14370_Y - connect \$131 $lt$libresoc.v:189668$14371_Y - connect \$133 $and$libresoc.v:189669$14372_Y - connect \$135 $lt$libresoc.v:189670$14373_Y - connect \$137 $and$libresoc.v:189671$14374_Y - connect \$11 $ternary$libresoc.v:189672$14375_Y - connect \$139 $lt$libresoc.v:189673$14376_Y - connect \$141 $and$libresoc.v:189674$14377_Y - connect \$143 $lt$libresoc.v:189675$14378_Y - connect \$145 $and$libresoc.v:189676$14379_Y - connect \$147 $lt$libresoc.v:189677$14380_Y - connect \$149 $and$libresoc.v:189678$14381_Y - connect \$151 $lt$libresoc.v:189679$14382_Y - connect \$153 $and$libresoc.v:189680$14383_Y - connect \$155 $lt$libresoc.v:189681$14384_Y - connect \$157 $and$libresoc.v:189682$14385_Y - connect \$159 $lt$libresoc.v:189683$14386_Y - connect \$161 $and$libresoc.v:189684$14387_Y - connect \$163 $lt$libresoc.v:189685$14388_Y - connect \$165 $and$libresoc.v:189686$14389_Y - connect \$167 $lt$libresoc.v:189687$14390_Y - connect \$16 $eq$libresoc.v:189688$14391_Y - connect \$169 $and$libresoc.v:189689$14392_Y - connect \$171 $lt$libresoc.v:189690$14393_Y - connect \$173 $and$libresoc.v:189691$14394_Y - connect \$175 $lt$libresoc.v:189692$14395_Y - connect \$177 $and$libresoc.v:189693$14396_Y - connect \$15 $ternary$libresoc.v:189694$14397_Y - connect \$179 $lt$libresoc.v:189695$14398_Y - connect \$181 $and$libresoc.v:189696$14399_Y - connect \$183 $lt$libresoc.v:189697$14400_Y - connect \$185 $and$libresoc.v:189698$14401_Y - connect \$187 $lt$libresoc.v:189699$14402_Y - connect \$189 $and$libresoc.v:189700$14403_Y - connect \$191 $lt$libresoc.v:189701$14404_Y - connect \$193 $and$libresoc.v:189702$14405_Y - connect \$195 $lt$libresoc.v:189703$14406_Y - connect \$197 $and$libresoc.v:189704$14407_Y - connect \$1 $eq$libresoc.v:189705$14408_Y - connect \$199 $lt$libresoc.v:189706$14409_Y - connect \$201 $and$libresoc.v:189707$14410_Y - connect \$204 $eq$libresoc.v:189708$14411_Y - connect \$203 $ternary$libresoc.v:189709$14412_Y - connect \$20 $eq$libresoc.v:189710$14413_Y - connect \$19 $ternary$libresoc.v:189711$14414_Y - connect \$24 $eq$libresoc.v:189712$14415_Y - connect \$23 $ternary$libresoc.v:189713$14416_Y - connect \$28 $eq$libresoc.v:189714$14417_Y - connect \$27 $ternary$libresoc.v:189715$14418_Y - connect \$32 $eq$libresoc.v:189716$14419_Y - connect \$31 $ternary$libresoc.v:189717$14420_Y - connect \$36 $eq$libresoc.v:189718$14421_Y - connect \$35 $ternary$libresoc.v:189719$14422_Y - connect \$3 $eq$libresoc.v:189720$14423_Y - connect \$40 $eq$libresoc.v:189721$14424_Y - connect \$39 $ternary$libresoc.v:189722$14425_Y - connect \$44 $eq$libresoc.v:189723$14426_Y - connect \$43 $ternary$libresoc.v:189724$14427_Y - connect \$48 $eq$libresoc.v:189725$14428_Y - connect \$47 $ternary$libresoc.v:189726$14429_Y - connect \$52 $eq$libresoc.v:189727$14430_Y - connect \$51 $ternary$libresoc.v:189728$14431_Y - connect \$56 $eq$libresoc.v:189729$14432_Y - connect \$55 $ternary$libresoc.v:189730$14433_Y - connect \$5 $and$libresoc.v:189731$14434_Y - connect \$60 $eq$libresoc.v:189732$14435_Y - connect \$59 $ternary$libresoc.v:189733$14436_Y - connect \$64 $eq$libresoc.v:189734$14437_Y - connect \$63 $ternary$libresoc.v:189735$14438_Y - connect \$68 $eq$libresoc.v:189736$14439_Y - connect \$67 $ternary$libresoc.v:189737$14440_Y - connect \$71 $shr$libresoc.v:189738$14441_Y [0] - connect \$73 $and$libresoc.v:189739$14442_Y - connect \$75 $lt$libresoc.v:189740$14443_Y - connect \$77 $and$libresoc.v:189741$14444_Y - connect \$79 $lt$libresoc.v:189742$14445_Y - connect \$81 $and$libresoc.v:189743$14446_Y - connect \$83 $lt$libresoc.v:189744$14447_Y - connect \$85 $and$libresoc.v:189745$14448_Y - connect \$87 $lt$libresoc.v:189746$14449_Y - connect \$8 $eq$libresoc.v:189747$14450_Y - connect \$89 $and$libresoc.v:189748$14451_Y - connect \$91 $lt$libresoc.v:189749$14452_Y - connect \$93 $and$libresoc.v:189750$14453_Y - connect \$95 $lt$libresoc.v:189751$14454_Y - connect \$97 $and$libresoc.v:189752$14455_Y + assign $1\ics_wb__ack$next[0:0]$14890 1'0 + case + assign $1\ics_wb__ack$next[0:0]$14890 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14889 + end + connect \$7 $ternary$libresoc.v:200465$14643_Y + connect \$99 $lt$libresoc.v:200466$14644_Y + connect \$101 $and$libresoc.v:200467$14645_Y + connect \$103 $lt$libresoc.v:200468$14646_Y + connect \$105 $and$libresoc.v:200469$14647_Y + connect \$107 $lt$libresoc.v:200470$14648_Y + connect \$109 $and$libresoc.v:200471$14649_Y + connect \$111 $lt$libresoc.v:200472$14650_Y + connect \$113 $and$libresoc.v:200473$14651_Y + connect \$115 $lt$libresoc.v:200474$14652_Y + connect \$117 $and$libresoc.v:200475$14653_Y + connect \$119 $lt$libresoc.v:200476$14654_Y + connect \$121 $and$libresoc.v:200477$14655_Y + connect \$123 $lt$libresoc.v:200478$14656_Y + connect \$125 $and$libresoc.v:200479$14657_Y + connect \$127 $lt$libresoc.v:200480$14658_Y + connect \$12 $eq$libresoc.v:200481$14659_Y + connect \$129 $and$libresoc.v:200482$14660_Y + connect \$131 $lt$libresoc.v:200483$14661_Y + connect \$133 $and$libresoc.v:200484$14662_Y + connect \$135 $lt$libresoc.v:200485$14663_Y + connect \$137 $and$libresoc.v:200486$14664_Y + connect \$11 $ternary$libresoc.v:200487$14665_Y + connect \$139 $lt$libresoc.v:200488$14666_Y + connect \$141 $and$libresoc.v:200489$14667_Y + connect \$143 $lt$libresoc.v:200490$14668_Y + connect \$145 $and$libresoc.v:200491$14669_Y + connect \$147 $lt$libresoc.v:200492$14670_Y + connect \$149 $and$libresoc.v:200493$14671_Y + connect \$151 $lt$libresoc.v:200494$14672_Y + connect \$153 $and$libresoc.v:200495$14673_Y + connect \$155 $lt$libresoc.v:200496$14674_Y + connect \$157 $and$libresoc.v:200497$14675_Y + connect \$159 $lt$libresoc.v:200498$14676_Y + connect \$161 $and$libresoc.v:200499$14677_Y + connect \$163 $lt$libresoc.v:200500$14678_Y + connect \$165 $and$libresoc.v:200501$14679_Y + connect \$167 $lt$libresoc.v:200502$14680_Y + connect \$16 $eq$libresoc.v:200503$14681_Y + connect \$169 $and$libresoc.v:200504$14682_Y + connect \$171 $lt$libresoc.v:200505$14683_Y + connect \$173 $and$libresoc.v:200506$14684_Y + connect \$175 $lt$libresoc.v:200507$14685_Y + connect \$177 $and$libresoc.v:200508$14686_Y + connect \$15 $ternary$libresoc.v:200509$14687_Y + connect \$179 $lt$libresoc.v:200510$14688_Y + connect \$181 $and$libresoc.v:200511$14689_Y + connect \$183 $lt$libresoc.v:200512$14690_Y + connect \$185 $and$libresoc.v:200513$14691_Y + connect \$187 $lt$libresoc.v:200514$14692_Y + connect \$189 $and$libresoc.v:200515$14693_Y + connect \$191 $lt$libresoc.v:200516$14694_Y + connect \$193 $and$libresoc.v:200517$14695_Y + connect \$195 $lt$libresoc.v:200518$14696_Y + connect \$197 $and$libresoc.v:200519$14697_Y + connect \$1 $eq$libresoc.v:200520$14698_Y + connect \$199 $lt$libresoc.v:200521$14699_Y + connect \$201 $and$libresoc.v:200522$14700_Y + connect \$204 $eq$libresoc.v:200523$14701_Y + connect \$203 $ternary$libresoc.v:200524$14702_Y + connect \$20 $eq$libresoc.v:200525$14703_Y + connect \$19 $ternary$libresoc.v:200526$14704_Y + connect \$24 $eq$libresoc.v:200527$14705_Y + connect \$23 $ternary$libresoc.v:200528$14706_Y + connect \$28 $eq$libresoc.v:200529$14707_Y + connect \$27 $ternary$libresoc.v:200530$14708_Y + connect \$32 $eq$libresoc.v:200531$14709_Y + connect \$31 $ternary$libresoc.v:200532$14710_Y + connect \$36 $eq$libresoc.v:200533$14711_Y + connect \$35 $ternary$libresoc.v:200534$14712_Y + connect \$3 $eq$libresoc.v:200535$14713_Y + connect \$40 $eq$libresoc.v:200536$14714_Y + connect \$39 $ternary$libresoc.v:200537$14715_Y + connect \$44 $eq$libresoc.v:200538$14716_Y + connect \$43 $ternary$libresoc.v:200539$14717_Y + connect \$48 $eq$libresoc.v:200540$14718_Y + connect \$47 $ternary$libresoc.v:200541$14719_Y + connect \$52 $eq$libresoc.v:200542$14720_Y + connect \$51 $ternary$libresoc.v:200543$14721_Y + connect \$56 $eq$libresoc.v:200544$14722_Y + connect \$55 $ternary$libresoc.v:200545$14723_Y + connect \$5 $and$libresoc.v:200546$14724_Y + connect \$60 $eq$libresoc.v:200547$14725_Y + connect \$59 $ternary$libresoc.v:200548$14726_Y + connect \$64 $eq$libresoc.v:200549$14727_Y + connect \$63 $ternary$libresoc.v:200550$14728_Y + connect \$68 $eq$libresoc.v:200551$14729_Y + connect \$67 $ternary$libresoc.v:200552$14730_Y + connect \$71 $shr$libresoc.v:200553$14731_Y [0] + connect \$73 $and$libresoc.v:200554$14732_Y + connect \$75 $lt$libresoc.v:200555$14733_Y + connect \$77 $and$libresoc.v:200556$14734_Y + connect \$79 $lt$libresoc.v:200557$14735_Y + connect \$81 $and$libresoc.v:200558$14736_Y + connect \$83 $lt$libresoc.v:200559$14737_Y + connect \$85 $and$libresoc.v:200560$14738_Y + connect \$87 $lt$libresoc.v:200561$14739_Y + connect \$8 $eq$libresoc.v:200562$14740_Y + connect \$89 $and$libresoc.v:200563$14741_Y + connect \$91 $lt$libresoc.v:200564$14742_Y + connect \$93 $and$libresoc.v:200565$14743_Y + connect \$95 $lt$libresoc.v:200566$14744_Y + connect \$97 $and$libresoc.v:200567$14745_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 diff --git a/experiments9/symbolic/coriolis2/ls180/litex_pinpads.json b/experiments9/symbolic/coriolis2/ls180/litex_pinpads.json index d08a8e9..e522800 100644 --- a/experiments9/symbolic/coriolis2/ls180/litex_pinpads.json +++ b/experiments9/symbolic/coriolis2/ls180/litex_pinpads.json @@ -1,1329 +1 @@ -{ - "chip.clocks": { - "JTAG": "p_jtag_tck", - "MSPI": "p_spimaster_clk", - "MTWI": "p_i2c_scl", - "SD": "p_sdcard_clk", - "SDR": "p_sdram_clock" - }, - "chip.domains": { - "EINT": [ - "p_eint_0", - "p_eint_1", - "p_eint_2" - ], - "GPIO": [ - "p_gpio_8", - "p_gpio_9", - "p_gpio_10", - "p_gpio_11", - "p_gpio_12", - "p_gpio_13", - "p_gpio_14", - "p_gpio_15", - "p_gpio_0", - "p_gpio_1", - "p_gpio_2", - "p_gpio_3", - "p_gpio_4", - "p_gpio_5", - "p_gpio_6", - "p_gpio_7" - ], - "JTAG": [ - "p_jtag_tms", - "p_jtag_tdi", - "p_jtag_tdo", - "p_jtag_tck" - ], - "MSPI": [ - "p_spisdcard_clk", - "p_spisdcard_cs_n", - "p_spisdcard_mosi", - "p_spisdcard_miso", - "p_spimaster_clk", - "p_spimaster_cs_n", - "p_spimaster_mosi", - "p_spimaster_miso" - ], - "MTWI": [ - "p_i2c_sda", - "p_i2c_scl" - ], - "PWM": [ - "p_pwm0", - "p_pwm1" - ], - "SD": [ - "p_sdcard_cmd", - "p_sdcard_clk", - "p_sdcard_data0", - "p_sdcard_data1", - "p_sdcard_data2", - "p_sdcard_data3" - ], - "SDR": [ - "p_sdram_dm_0", - "p_sdram_dq_0", - "p_sdram_dq_1", - "p_sdram_dq_2", - "p_sdram_dq_3", - "p_sdram_dq_4", - "p_sdram_dq_5", - "p_sdram_dq_6", - "p_sdram_dq_7", - "p_sdram_a_0", - "p_sdram_a_1", - "p_sdram_a_2", - "p_sdram_a_3", - "p_sdram_a_4", - "p_sdram_a_5", - "p_sdram_a_6", - "p_sdram_a_7", - "p_sdram_a_8", - "p_sdram_a_9", - "p_sdram_ba_0", - "p_sdram_ba_1", - "p_sdram_clock", - "p_sdram_cke", - "p_sdram_ras_n", - "p_sdram_cas_n", - "p_sdram_we_n", - "p_sdram_cs_n", - "p_sdram_a_10", - "p_sdram_a_11", - "p_sdram_a_12", - "p_sdram_dm_1", - "p_sdram_dq_8", - "p_sdram_dq_9", - "p_sdram_dq_10", - "p_sdram_dq_11", - "p_sdram_dq_12", - "p_sdram_dq_13", - "p_sdram_dq_14", - "p_sdram_dq_15" - ], - "UART": [ - "p_uart_tx", - "p_uart_rx" - ] - }, - "chip.n_extpower": 3, - "chip.n_intpower": 5, - "pads.east": [ - "p_sdram_a_10", - "iopower_1", - "ioground_1", - "p_sdram_a_11", - "p_sdram_a_12", - "p_sdram_dm_1", - "p_sdram_dq_8", - "p_sdram_dq_9", - "p_sdram_dq_10", - "p_sdram_dq_11", - "p_sdram_dq_12", - "p_sdram_dq_13", - "p_sdram_dq_14", - "p_sdram_dq_15", - "power_1", - "ground_1", - "p_gpio_8", - "p_gpio_9", - "p_gpio_10", - "p_gpio_11", - "p_gpio_12", - "p_gpio_13", - "p_gpio_14", - "p_gpio_15", - "nc_0", - "p_jtag_tms", - "p_jtag_tdi", - "p_jtag_tdo", - "p_jtag_tck", - "nc_1", - "nc_2", - "nc_3" - ], - "pads.instances": [ - [ - "iopower_0", - "iovdd" - ], - [ - "ioground_0", - "iovss" - ], - [ - "p_sdram_dm_0", - "sdram_dm(0)", - "sdram_dm(0)", - "+" - ], - [ - "p_sdram_dq_0", - "sdram_dq_0", - "sdram_dq_o(0)", - "sdram_dq_i(0)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_1", - "sdram_dq_1", - "sdram_dq_o(1)", - "sdram_dq_i(1)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_2", - "sdram_dq_2", - "sdram_dq_o(2)", - "sdram_dq_i(2)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_3", - "sdram_dq_3", - "sdram_dq_o(3)", - "sdram_dq_i(3)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_4", - "sdram_dq_4", - "sdram_dq_o(4)", - "sdram_dq_i(4)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_5", - "sdram_dq_5", - "sdram_dq_o(5)", - "sdram_dq_i(5)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_6", - "sdram_dq_6", - "sdram_dq_o(6)", - "sdram_dq_i(6)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_7", - "sdram_dq_7", - "sdram_dq_o(7)", - "sdram_dq_i(7)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_a_0", - "sdram_a(0)", - "sdram_a(0)", - "+" - ], - [ - "p_sdram_a_1", - "sdram_a(1)", - "sdram_a(1)", - "+" - ], - [ - "p_sdram_a_2", - "sdram_a(2)", - "sdram_a(2)", - "+" - ], - [ - "p_sdram_a_3", - "sdram_a(3)", - "sdram_a(3)", - "+" - ], - [ - "p_sdram_a_4", - "sdram_a(4)", - "sdram_a(4)", - "+" - ], - [ - "p_sdram_a_5", - "sdram_a(5)", - "sdram_a(5)", - "+" - ], - [ - "p_sdram_a_6", - "sdram_a(6)", - "sdram_a(6)", - "+" - ], - [ - "p_sdram_a_7", - "sdram_a(7)", - "sdram_a(7)", - "+" - ], - [ - "p_sdram_a_8", - "sdram_a(8)", - "sdram_a(8)", - "+" - ], - [ - "p_sdram_a_9", - "sdram_a(9)", - "sdram_a(9)", - "+" - ], - [ - "p_sdram_ba_0", - "sdram_ba(0)", - "sdram_ba(0)", - "+" - ], - [ - "p_sdram_ba_1", - "sdram_ba(1)", - "sdram_ba(1)", - "+" - ], - [ - "p_sdram_clock", - "sdram_clock", - "sdram_clock", - "+" - ], - [ - "p_sdram_cke", - "sdram_cke", - "sdram_cke", - "+" - ], - [ - "p_sdram_ras_n", - "sdram_ras_n", - "sdram_ras_n", - "+" - ], - [ - "p_sdram_cas_n", - "sdram_cas_n", - "sdram_cas_n", - "+" - ], - [ - "p_sdram_we_n", - "sdram_we_n", - "sdram_we_n", - "+" - ], - [ - "p_sdram_cs_n", - "sdram_cs_n", - "sdram_cs_n", - "+" - ], - [ - "power_0", - "vdd" - ], - [ - "ground_0", - "vss" - ], - [ - "iopower_1", - "iovdd" - ], - [ - "ioground_1", - "iovdd" - ], - [ - "p_sdram_a_10", - "sdram_a(10)", - "sdram_a(10)", - "+" - ], - [ - "p_sdram_a_11", - "sdram_a(11)", - "sdram_a(11)", - "+" - ], - [ - "p_sdram_a_12", - "sdram_a(12)", - "sdram_a(12)", - "+" - ], - [ - "p_sdram_dm_1", - "sdram_dm(1)", - "sdram_dm(1)", - "*" - ], - [ - "p_sdram_dq_8", - "sdram_dq_8", - "sdram_dq_o(8)", - "sdram_dq_i(8)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_9", - "sdram_dq_9", - "sdram_dq_o(9)", - "sdram_dq_i(9)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_10", - "sdram_dq_10", - "sdram_dq_o(10)", - "sdram_dq_i(10)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_11", - "sdram_dq_11", - "sdram_dq_o(11)", - "sdram_dq_i(11)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_12", - "sdram_dq_12", - "sdram_dq_o(12)", - "sdram_dq_i(12)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_13", - "sdram_dq_13", - "sdram_dq_o(13)", - "sdram_dq_i(13)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_14", - "sdram_dq_14", - "sdram_dq_o(14)", - "sdram_dq_i(14)", - "sdram_dq_oe", - "*" - ], - [ - "p_sdram_dq_15", - "sdram_dq_15", - "sdram_dq_o(15)", - "sdram_dq_i(15)", - "sdram_dq_oe", - "*" - ], - [ - "power_1", - "vdd" - ], - [ - "ground_1", - "vss" - ], - [ - "p_gpio_8", - "gpio_8", - "gpio_o(8)", - "gpio_i(8)", - "gpio_oe(8)", - "*" - ], - [ - "p_gpio_9", - "gpio_9", - "gpio_o(9)", - "gpio_i(9)", - "gpio_oe(9)", - "*" - ], - [ - "p_gpio_10", - "gpio_10", - "gpio_o(10)", - "gpio_i(10)", - "gpio_oe(10)", - "*" - ], - [ - "p_gpio_11", - "gpio_11", - "gpio_o(11)", - "gpio_i(11)", - "gpio_oe(11)", - "*" - ], - [ - "p_gpio_12", - "gpio_12", - "gpio_o(12)", - "gpio_i(12)", - "gpio_oe(12)", - "*" - ], - [ - "p_gpio_13", - "gpio_13", - "gpio_o(13)", - "gpio_i(13)", - "gpio_oe(13)", - "*" - ], - [ - "p_gpio_14", - "gpio_14", - "gpio_o(14)", - "gpio_i(14)", - "gpio_oe(14)", - "*" - ], - [ - "p_gpio_15", - "gpio_15", - "gpio_o(15)", - "gpio_i(15)", - "gpio_oe(15)", - "*" - ], - [ - "p_jtag_tms", - "jtag_tms", - "jtag_tms", - "-" - ], - [ - "p_jtag_tdi", - "jtag_tdi", - "jtag_tdi", - "-" - ], - [ - "p_jtag_tdo", - "jtag_tdo", - "jtag_tdo", - "+" - ], - [ - "p_jtag_tck", - "jtag_tck", - "jtag_tck", - "+" - ], - [ - "power_2", - "vdd" - ], - [ - "ground_2", - "vss" - ], - [ - "p_i2c_sda", - "i2c_sda", - "i2c_sda_o", - "i2c_sda_i", - "i2c_sda_oe", - "*" - ], - [ - "p_i2c_scl", - "i2c_scl", - "i2c_scl", - "+" - ], - [ - "p_spisdcard_clk", - "spisdcard_clk", - "spisdcard_clk", - "+" - ], - [ - "p_spisdcard_cs_n", - "spisdcard_cs_n", - "spisdcard_cs_n", - "+" - ], - [ - "p_spisdcard_mosi", - "spisdcard_mosi", - "spisdcard_mosi", - "+" - ], - [ - "p_spisdcard_miso", - "spisdcard_miso", - "spisdcard_miso", - "-" - ], - [ - "p_uart_tx", - "uart_tx", - "uart_tx", - "+" - ], - [ - "p_uart_rx", - "uart_rx", - "uart_rx", - "-" - ], - [ - "p_gpio_0", - "gpio_0", - "gpio_o(0)", - "gpio_i(0)", - "gpio_oe(0)", - "*" - ], - [ - "p_gpio_1", - "gpio_1", - "gpio_o(1)", - "gpio_i(1)", - "gpio_oe(1)", - "*" - ], - [ - "p_gpio_2", - "gpio_2", - "gpio_o(2)", - "gpio_i(2)", - "gpio_oe(2)", - "*" - ], - [ - "p_gpio_3", - "gpio_3", - "gpio_o(3)", - "gpio_i(3)", - "gpio_oe(3)", - "*" - ], - [ - "p_gpio_4", - "gpio_4", - "gpio_o(4)", - "gpio_i(4)", - "gpio_oe(4)", - "*" - ], - [ - "p_gpio_5", - "gpio_5", - "gpio_o(5)", - "gpio_i(5)", - "gpio_oe(5)", - "*" - ], - [ - "p_gpio_6", - "gpio_6", - "gpio_o(6)", - "gpio_i(6)", - "gpio_oe(6)", - "*" - ], - [ - "p_gpio_7", - "gpio_7", - "gpio_o(7)", - "gpio_i(7)", - "gpio_oe(7)", - "*" - ], - [ - "p_sys_clk", - "sys_clk", - "sys_clk", - "-" - ], - [ - "sys_rst", - "sys_rst", - "sys_rst", - "-" - ], - [ - "p_sys_pll_18_o", - "sys_pll_18_o", - "sys_pll_18_o", - "+" - ], - [ - "p_sys_clksel_0", - "sys_clksel_i(0)", - "sys_clksel_i(0)", - "-" - ], - [ - "p_sys_clksel_1", - "sys_clksel_i(1)", - "sys_clksel_i(1)", - "-" - ], - [ - "p_sys_pll_lck_o", - "sys_pll_lck_o", - "sys_pll_lck_o", - "+" - ], - [ - "power_3", - "vdd" - ], - [ - "ground_3", - "vss" - ], - [ - "iopower_2", - "iovdd" - ], - [ - "ioground_2", - "iovss" - ], - [ - "p_pwm0", - "pwm(0)", - "pwm(0)", - "+" - ], - [ - "p_pwm1", - "pwm(1)", - "pwm(1)", - "+" - ], - [ - "p_eint_0", - "eint(0)", - "eint(0)", - "-" - ], - [ - "p_eint_1", - "eint(1)", - "eint(1)", - "-" - ], - [ - "p_eint_2", - "eint(2)", - "eint(2)", - "-" - ], - [ - "p_spimaster_clk", - "spimaster_clk", - "spimaster_clk", - "+" - ], - [ - "p_spimaster_cs_n", - "spimaster_cs_n", - "spimaster_cs_n", - "+" - ], - [ - "p_spimaster_mosi", - "spimaster_mosi", - "spimaster_mosi", - "+" - ], - [ - "p_spimaster_miso", - "spimaster_miso", - "spimaster_miso", - "-" - ], - [ - "p_sdcard_cmd", - "sdcard_cmd", - "sdcard_cmd_o", - "sdcard_cmd_i", - "sdcard_cmd_oe", - "*" - ], - [ - "p_sdcard_clk", - "sdcard_clk", - "sdcard_clk", - "+" - ], - [ - "p_sdcard_data0", - "sdcard_data0", - "sdcard_data_o(0)", - "sdcard_data_i(0)", - "sdcard_data_oe", - "*" - ], - [ - "p_sdcard_data1", - "sdcard_data1", - "sdcard_data_o(1)", - "sdcard_data_i(1)", - "sdcard_data_oe", - "*" - ], - [ - "p_sdcard_data2", - "sdcard_data2", - "sdcard_data_o(2)", - "sdcard_data_i(2)", - "sdcard_data_oe", - "*" - ], - [ - "p_sdcard_data3", - "sdcard_data3", - "sdcard_data_o(3)", - "sdcard_data_i(3)", - "sdcard_data_oe", - "*" - ], - [ - "power_4", - "vdd" - ], - [ - "ground_4", - "vss" - ], - [ - "nc_0", - "nc(0)", - "nc(0)", - "-" - ], - [ - "nc_1", - "nc(1)", - "nc(1)", - "-" - ], - [ - "nc_2", - "nc(2)", - "nc(2)", - "-" - ], - [ - "nc_3", - "nc(3)", - "nc(3)", - "-" - ], - [ - "nc_4", - "nc(4)", - "nc(4)", - "-" - ], - [ - "nc_5", - "nc(5)", - "nc(5)", - "-" - ], - [ - "nc_6", - "nc(6)", - "nc(6)", - "-" - ], - [ - "nc_7", - "nc(7)", - "nc(7)", - "-" - ], - [ - "nc_8", - "nc(8)", - "nc(8)", - "-" - ], - [ - "nc_9", - "nc(9)", - "nc(9)", - "-" - ], - [ - "nc_10", - "nc(10)", - "nc(10)", - "-" - ], - [ - "nc_11", - "nc(11)", - "nc(11)", - "-" - ], - [ - "nc_12", - "nc(12)", - "nc(12)", - "-" - ], - [ - "nc_13", - "nc(13)", - "nc(13)", - "-" - ], - [ - "nc_14", - "nc(14)", - "nc(14)", - "-" - ], - [ - "nc_15", - "nc(15)", - "nc(15)", - "-" - ], - [ - "nc_16", - "nc(16)", - "nc(16)", - "-" - ], - [ - "nc_17", - "nc(17)", - "nc(17)", - "-" - ], - [ - "nc_18", - "nc(18)", - "nc(18)", - "-" - ], - [ - "nc_19", - "nc(19)", - "nc(19)", - "-" - ], - [ - "nc_20", - "nc(20)", - "nc(20)", - "-" - ], - [ - "nc_21", - "nc(21)", - "nc(21)", - "-" - ], - [ - "nc_22", - "nc(22)", - "nc(22)", - "-" - ], - [ - "nc_23", - "nc(23)", - "nc(23)", - "-" - ] - ], - "pads.north": [ - "p_sdram_dm_0", - "iopower_0", - "ioground_0", - "p_sdram_dq_0", - "p_sdram_dq_1", - "p_sdram_dq_2", - "p_sdram_dq_3", - "p_sdram_dq_4", - "p_sdram_dq_5", - "p_sdram_dq_6", - "p_sdram_dq_7", - "p_sdram_a_0", - "p_sdram_a_1", - "p_sdram_a_2", - "p_sdram_a_3", - "p_sdram_a_4", - "p_sdram_a_5", - "p_sdram_a_6", - "p_sdram_a_7", - "p_sdram_a_8", - "p_sdram_a_9", - "p_sdram_ba_0", - "p_sdram_ba_1", - "p_sdram_clock", - "p_sdram_cke", - "p_sdram_ras_n", - "p_sdram_cas_n", - "p_sdram_we_n", - "p_sdram_cs_n", - "power_0", - "ground_0", - "nc_17" - ], - "pads.south": [ - "p_i2c_sda", - "power_2", - "ground_2", - "p_i2c_scl", - "nc_18", - "nc_19", - "nc_20", - "nc_21", - "p_spisdcard_clk", - "p_spisdcard_cs_n", - "p_spisdcard_mosi", - "p_spisdcard_miso", - "nc_22", - "p_uart_tx", - "p_uart_rx", - "p_gpio_0", - "p_gpio_1", - "p_gpio_2", - "p_gpio_3", - "p_gpio_4", - "p_gpio_5", - "p_gpio_6", - "p_gpio_7", - "p_sys_clk", - "sys_rst", - "nc_23", - "p_sys_pll_18_o", - "p_sys_clksel_0", - "p_sys_clksel_1", - "power_3", - "ground_3", - "p_sys_pll_lck_o" - ], - "pads.west": [ - "p_pwm0", - "iopower_2", - "ioground_2", - "p_pwm1", - "p_eint_0", - "p_eint_1", - "p_eint_2", - "p_spimaster_clk", - "p_spimaster_cs_n", - "p_spimaster_mosi", - "p_spimaster_miso", - "p_sdcard_cmd", - "p_sdcard_clk", - "p_sdcard_data0", - "p_sdcard_data1", - "p_sdcard_data2", - "p_sdcard_data3", - "nc_4", - "nc_5", - "nc_6", - "nc_7", - "nc_8", - "nc_9", - "nc_10", - "nc_11", - "nc_12", - "nc_13", - "nc_14", - "nc_15", - "power_4", - "ground_4", - "nc_16" - ], - "pins.map": { - "eint_0": "p_eint_0", - "eint_1": "p_eint_1", - "eint_2": "p_eint_2", - "gpioe_e10": "p_gpio_10", - "gpioe_e11": "p_gpio_11", - "gpioe_e12": "p_gpio_12", - "gpioe_e13": "p_gpio_13", - "gpioe_e14": "p_gpio_14", - "gpioe_e15": "p_gpio_15", - "gpioe_e8": "p_gpio_8", - "gpioe_e9": "p_gpio_9", - "gpios_s0": "p_gpio_0", - "gpios_s1": "p_gpio_1", - "gpios_s2": "p_gpio_2", - "gpios_s3": "p_gpio_3", - "gpios_s4": "p_gpio_4", - "gpios_s5": "p_gpio_5", - "gpios_s6": "p_gpio_6", - "gpios_s7": "p_gpio_7", - "jtag_tck": "p_jtag_tck", - "jtag_tdi": "p_jtag_tdi", - "jtag_tdo": "p_jtag_tdo", - "jtag_tms": "p_jtag_tms", - "mspi0_ck": "p_spisdcard_clk", - "mspi0_miso": "p_spisdcard_miso", - "mspi0_mosi": "p_spisdcard_mosi", - "mspi0_nss": "p_spisdcard_cs_n", - "mspi1_ck": "p_spimaster_clk", - "mspi1_miso": "p_spimaster_miso", - "mspi1_mosi": "p_spimaster_mosi", - "mspi1_nss": "p_spimaster_cs_n", - "mtwi_scl": "p_i2c_scl", - "mtwi_sda": "p_i2c_sda", - "nc_0": "nc_0", - "nc_1": "nc_1", - "nc_10": "nc_10", - "nc_11": "nc_11", - "nc_12": "nc_12", - "nc_13": "nc_13", - "nc_14": "nc_14", - "nc_15": "nc_15", - "nc_16": "nc_16", - "nc_17": "nc_17", - "nc_18": "nc_18", - "nc_19": "nc_19", - "nc_2": "nc_2", - "nc_20": "nc_20", - "nc_21": "nc_21", - "nc_22": "nc_22", - "nc_23": "nc_23", - "nc_3": "nc_3", - "nc_4": "nc_4", - "nc_5": "nc_5", - "nc_6": "nc_6", - "nc_7": "nc_7", - "nc_8": "nc_8", - "nc_9": "nc_9", - "pwm0_out": "p_pwm0", - "pwm1_out": "p_pwm1", - "sd0_clk": "p_sdcard_clk", - "sd0_cmd": "p_sdcard_cmd", - "sd0_d0": "p_sdcard_data0", - "sd0_d1": "p_sdcard_data1", - "sd0_d2": "p_sdcard_data2", - "sd0_d3": "p_sdcard_data3", - "sdr_ad0": "p_sdram_a_0", - "sdr_ad1": "p_sdram_a_1", - "sdr_ad10": "p_sdram_a_10", - "sdr_ad11": "p_sdram_a_11", - "sdr_ad12": "p_sdram_a_12", - "sdr_ad2": "p_sdram_a_2", - "sdr_ad3": "p_sdram_a_3", - "sdr_ad4": "p_sdram_a_4", - "sdr_ad5": "p_sdram_a_5", - "sdr_ad6": "p_sdram_a_6", - "sdr_ad7": "p_sdram_a_7", - "sdr_ad8": "p_sdram_a_8", - "sdr_ad9": "p_sdram_a_9", - "sdr_ba0": "p_sdram_ba_0", - "sdr_ba1": "p_sdram_ba_1", - "sdr_casn": "p_sdram_cas_n", - "sdr_cke": "p_sdram_cke", - "sdr_clk": "p_sdram_clock", - "sdr_csn0": "p_sdram_cs_n", - "sdr_d0": "p_sdram_dq_0", - "sdr_d1": "p_sdram_dq_1", - "sdr_d10": "p_sdram_dq_10", - "sdr_d11": "p_sdram_dq_11", - "sdr_d12": "p_sdram_dq_12", - "sdr_d13": "p_sdram_dq_13", - "sdr_d14": "p_sdram_dq_14", - "sdr_d15": "p_sdram_dq_15", - "sdr_d2": "p_sdram_dq_2", - "sdr_d3": "p_sdram_dq_3", - "sdr_d4": "p_sdram_dq_4", - "sdr_d5": "p_sdram_dq_5", - "sdr_d6": "p_sdram_dq_6", - "sdr_d7": "p_sdram_dq_7", - "sdr_d8": "p_sdram_dq_8", - "sdr_d9": "p_sdram_dq_9", - "sdr_dqm0": "p_sdram_dm_0", - "sdr_dqm1": "p_sdram_dm_1", - "sdr_rasn": "p_sdram_ras_n", - "sdr_wen": "p_sdram_we_n", - "sys_clk": "p_sys_clk", - "sys_csel0": "p_sys_clksel_0", - "sys_csel1": "p_sys_clksel_1", - "sys_pllock": "p_sys_pll_lck_o", - "sys_pllout": "p_sys_pll_18_o", - "uart0_rx": "p_uart_rx", - "uart0_tx": "p_uart_tx", - "vdde_0": "ioground_0", - "vdde_1": "ioground_1", - "vdde_2": "ioground_2", - "vddi_0": "ground_0", - "vddi_1": "ground_1", - "vddi_2": "ground_2", - "vddi_3": "ground_3", - "vddi_4": "ground_4", - "vsse_0": "iopower_0", - "vsse_1": "iopower_1", - "vsse_2": "iopower_2", - "vssi_0": "power_0", - "vssi_1": "power_1", - "vssi_2": "power_2", - "vssi_3": "power_3", - "vssi_4": "power_4" - }, - "pins.specs": { - "EINT:": [ - "0-", - "1-", - "2-" - ], - "GPIO:": [ - "E8*", - "E9*", - "E10*", - "E11*", - "E12*", - "E13*", - "E14*", - "E15*", - "S0*", - "S1*", - "S2*", - "S3*", - "S4*", - "S5*", - "S6*", - "S7*" - ], - "JTAG:": [ - "TMS-", - "TDI-", - "TDO+", - "TCK+" - ], - "MSPI:0": [ - "CK+", - "NSS+", - "MOSI+", - "MISO-" - ], - "MSPI:1": [ - "CK+", - "NSS+", - "MOSI+", - "MISO-" - ], - "MTWI:": [ - "SDA*", - "SCL+" - ], - "PWM:": [ - "0+", - "1+" - ], - "SD:0": [ - "CMD*", - "CLK+", - "D0*", - "D1*", - "D2*", - "D3*" - ], - "SDR:": [ - "DQM0+", - "D0*", - "D1*", - "D2*", - "D3*", - "D4*", - "D5*", - "D6*", - "D7*", - "AD0+", - "AD1+", - "AD2+", - "AD3+", - "AD4+", - "AD5+", - "AD6+", - "AD7+", - "AD8+", - "AD9+", - "BA0+", - "BA1+", - "CLK+", - "CKE+", - "RASn+", - "CASn+", - "WEn+", - "CSn0+", - "AD10+", - "AD11+", - "AD12+", - "DQM1*", - "D8*", - "D9*", - "D10*", - "D11*", - "D12*", - "D13*", - "D14*", - "D15*" - ], - "SYS:": [ - "CLK-", - "RST-", - "PLLCLK-", - "PLLOUT+", - "CSEL0-", - "CSEL1-", - "PLLOCK+" - ], - "UART:0": [ - "TX+", - "RX-" - ], - "VDD:E": [ - "0-", - "1-", - "2-" - ], - "VDD:I": [ - "0-", - "1-", - "2-", - "3-", - "4-" - ], - "VSS:E": [ - "0-", - "1-", - "2-" - ], - "VSS:I": [ - "0-", - "1-", - "2-", - "3-", - "4-" - ] - } -} +{"pins.map": {"vddi_4": "power_4", "vddi_0": "power_0", "vddi_1": "power_1", "vddi_2": "power_2", "vddi_3": "power_3", "sdr_clk": "p_sdram_clock", "sdr_casn": "p_sdram_cas_n", "sdr_ad10": "p_sdram_a_10", "sdr_ad11": "p_sdram_a_11", "vsse_0": "ioground_0", "vsse_1": "ioground_1", "sys_csel0": "p_sys_clksel_0", "sys_clk": "p_sys_clk", "jtag_tdi": "p_jtag_tdi", "jtag_tdo": "p_jtag_tdo", "mspi1_nss": "p_spimaster_cs_n", "jtag_tms": "p_jtag_tms", "gpioe_e10": "p_gpio_10", "gpioe_e11": "p_gpio_11", "gpioe_e12": "p_gpio_12", "gpioe_e13": "p_gpio_13", "gpioe_e14": "p_gpio_14", "gpioe_e15": "p_gpio_15", "nc_9": "nc_9", "sdr_rasn": "p_sdram_ras_n", "mspi1_miso": "p_spimaster_miso", "gpios_s6": "p_gpio_6", "gpios_s7": "p_gpio_7", "gpios_s4": "p_gpio_4", "gpios_s5": "p_gpio_5", "gpios_s2": "p_gpio_2", "gpios_s3": "p_gpio_3", "gpios_s0": "p_gpio_0", "gpios_s1": "p_gpio_1", "gpioe_e8": "p_gpio_8", "gpioe_e9": "p_gpio_9", "nc_12": "nc_12", "nc_13": "nc_13", "nc_10": "nc_10", "nc_11": "nc_11", "nc_16": "nc_16", "nc_17": "nc_17", "nc_14": "nc_14", "nc_15": "nc_15", "nc_18": "nc_18", "nc_19": "nc_19", "nc_5": "nc_5", "nc_7": "nc_7", "pwm0_out": "p_pwm0", "mspi1_mosi": "p_spimaster_mosi", "vsse_2": "ioground_2", "sdr_ad12": "p_sdram_a_12", "sdr_dqm0": "p_sdram_dm_0", "sdr_dqm1": "p_sdram_dm_1", "nc_23": "nc_23", "nc_22": "nc_22", "nc_21": "nc_21", "nc_20": "nc_20", "sdr_cke": "p_sdram_cke", "uart0_rx": "p_uart_rx", "nc_8": "nc_8", "sd0_d0": "p_sdcard_data0", "sd0_d1": "p_sdcard_data1", "nc_0": "nc_0", "nc_1": "nc_1", "nc_2": "nc_2", "nc_3": "nc_3", "nc_4": "nc_4", "sd0_d2": "p_sdcard_data2", "nc_6": "nc_6", "mspi1_ck": "p_spimaster_clk", "sd0_d3": "p_sdcard_data3", "sys_csel1": "p_sys_clksel_1", "pwm1_out": "p_pwm1", "sd0_clk": "p_sdcard_clk", "mspi0_ck": "p_spisdcard_clk", "mtwi_scl": "p_i2c_scl", "mspi0_miso": "p_spisdcard_miso", "mspi0_mosi": "p_spisdcard_mosi", "mtwi_sda": "p_i2c_sda", "sd0_cmd": "p_sdcard_cmd", "sdr_d8": "p_sdram_dq_8", "sdr_d9": "p_sdram_dq_9", "uart0_tx": "p_uart_tx", "sdr_d2": "p_sdram_dq_2", "sdr_d3": "p_sdram_dq_3", "sdr_d0": "p_sdram_dq_0", "sdr_d1": "p_sdram_dq_1", "sdr_d6": "p_sdram_dq_6", "sdr_d7": "p_sdram_dq_7", "sdr_d4": "p_sdram_dq_4", "sdr_d5": "p_sdram_dq_5", "sys_pllock": "p_sys_pll_lck_o", "mspi0_nss": "p_spisdcard_cs_n", "vdde_0": "iopower_0", "vdde_1": "iopower_1", "vdde_2": "iopower_2", "sdr_ad2": "p_sdram_a_2", "sdr_ad3": "p_sdram_a_3", "sdr_ad0": "p_sdram_a_0", "sdr_ad1": "p_sdram_a_1", "sdr_ad6": "p_sdram_a_6", "sdr_ad7": "p_sdram_a_7", "sdr_ad4": "p_sdram_a_4", "sdr_ad5": "p_sdram_a_5", "sdr_ad8": "p_sdram_a_8", "sdr_ad9": "p_sdram_a_9", "jtag_tck": "p_jtag_tck", "sys_pllout": "p_sys_pll_18_o", "sdr_d10": "p_sdram_dq_10", "sdr_d11": "p_sdram_dq_11", "sdr_d12": "p_sdram_dq_12", "sdr_d13": "p_sdram_dq_13", "sdr_d14": "p_sdram_dq_14", "sdr_d15": "p_sdram_dq_15", "sdr_wen": "p_sdram_we_n", "vssi_2": "ground_2", "vssi_3": "ground_3", "vssi_0": "ground_0", "vssi_1": "ground_1", "vssi_4": "ground_4", "sdr_csn0": "p_sdram_cs_n", "eint_2": "p_eint_2", "eint_1": "p_eint_1", "eint_0": "p_eint_0", "sdr_ba0": "p_sdram_ba_0", "sdr_ba1": "p_sdram_ba_1"}, "chip.n_extpower": 3, "pads.north": ["ioground_0", "iopower_0", "p_sdram_dm_0", "p_sdram_dq_0", "p_sdram_dq_1", "p_sdram_dq_2", "p_sdram_dq_3", "p_sdram_dq_4", "p_sdram_dq_5", "p_sdram_dq_6", "p_sdram_dq_7", "p_sdram_a_0", "p_sdram_a_1", "p_sdram_a_2", "p_sdram_a_3", "p_sdram_a_4", "p_sdram_a_5", "p_sdram_a_6", "p_sdram_a_7", "p_sdram_a_8", "p_sdram_a_9", "p_sdram_ba_0", "p_sdram_ba_1", "p_sdram_clock", "p_sdram_cke", "p_sdram_ras_n", "p_sdram_cas_n", "p_sdram_we_n", "p_sdram_cs_n", "nc_17", "ground_0", "power_0"], "chip.clocks": {"SDR": "p_sdram_clock", "MTWI": "p_i2c_scl", "MSPI": "p_spimaster_clk", "JTAG": "p_jtag_tck", "SD": "p_sdcard_clk"}, "chip.n_intpower": 5, "pins.specs": {"MSPI:1": ["CK+", "NSS+", "MOSI+", "MISO-"], "MSPI:0": ["CK+", "NSS+", "MOSI+", "MISO-"], "VSS:I": ["0-", "1-", "2-", "3-", "4-"], "VDD:I": ["0-", "1-", "2-", "3-", "4-"], "PWM:": ["0+", "1+"], "JTAG:": ["TMS-", "TDI-", "TDO+", "TCK+"], "VDD:E": ["0-", "1-", "2-"], "SYS:": ["CLK-", "RST-", "PLLCLK-", "PLLOUT+", "CSEL0-", "CSEL1-", "PLLOCK+"], "UART:0": ["TX+", "RX-"], "VSS:E": ["0-", "1-", "2-"], "SDR:": ["DQM0+", "D0*", "D1*", "D2*", "D3*", "D4*", "D5*", "D6*", "D7*", "AD0+", "AD1+", "AD2+", "AD3+", "AD4+", "AD5+", "AD6+", "AD7+", "AD8+", "AD9+", "BA0+", "BA1+", "CLK+", "CKE+", "RASn+", "CASn+", "WEn+", "CSn0+", "AD10+", "AD11+", "AD12+", "DQM1+", "D8*", "D9*", "D10*", "D11*", "D12*", "D13*", "D14*", "D15*"], "GPIO:": ["E8*", "E9*", "E10*", "E11*", "E12*", "E13*", "E14*", "E15*", "S0*", "S1*", "S2*", "S3*", "S4*", "S5*", "S6*", "S7*"], "MTWI:": ["SDA*", "SCL+"], "SD:0": ["CMD*", "CLK+", "D0*", "D1*", "D2*", "D3*"], "EINT:": ["0-", "1-", "2-"]}, "pads.east": ["ioground_1", "iopower_1", "p_sdram_a_10", "p_sdram_a_11", "p_sdram_a_12", "p_sdram_dm_1", "p_sdram_dq_8", "p_sdram_dq_9", "p_sdram_dq_10", "p_sdram_dq_11", "p_sdram_dq_12", "p_sdram_dq_13", "p_sdram_dq_14", "p_sdram_dq_15", "ground_1", "power_1", "p_gpio_8", "p_gpio_9", "p_gpio_10", "p_gpio_11", "p_gpio_12", "p_gpio_13", "p_gpio_14", "p_gpio_15", "nc_0", "p_jtag_tms", "p_jtag_tdi", "p_jtag_tdo", "p_jtag_tck", "nc_1", "nc_2", "nc_3"], "chip.domains": {"EINT": ["p_eint_0", "p_eint_1", "p_eint_2"], "SDR": ["p_sdram_dm_0", "p_sdram_dq_0", "p_sdram_dq_1", "p_sdram_dq_2", "p_sdram_dq_3", "p_sdram_dq_4", "p_sdram_dq_5", "p_sdram_dq_6", "p_sdram_dq_7", "p_sdram_a_0", "p_sdram_a_1", "p_sdram_a_2", "p_sdram_a_3", "p_sdram_a_4", "p_sdram_a_5", "p_sdram_a_6", "p_sdram_a_7", "p_sdram_a_8", "p_sdram_a_9", "p_sdram_ba_0", "p_sdram_ba_1", "p_sdram_clock", "p_sdram_cke", "p_sdram_ras_n", "p_sdram_cas_n", "p_sdram_we_n", "p_sdram_cs_n", "p_sdram_a_10", "p_sdram_a_11", "p_sdram_a_12", "p_sdram_dm_1", "p_sdram_dq_8", "p_sdram_dq_9", "p_sdram_dq_10", "p_sdram_dq_11", "p_sdram_dq_12", "p_sdram_dq_13", "p_sdram_dq_14", "p_sdram_dq_15"], "MTWI": ["p_i2c_sda", "p_i2c_scl"], "UART": ["p_uart_tx", "p_uart_rx"], "MSPI": ["p_spisdcard_clk", "p_spisdcard_cs_n", "p_spisdcard_mosi", "p_spisdcard_miso", "p_spimaster_clk", "p_spimaster_cs_n", "p_spimaster_mosi", "p_spimaster_miso"], "GPIO": ["p_gpio_8", "p_gpio_9", "p_gpio_10", "p_gpio_11", "p_gpio_12", "p_gpio_13", "p_gpio_14", "p_gpio_15", "p_gpio_0", "p_gpio_1", "p_gpio_2", "p_gpio_3", "p_gpio_4", "p_gpio_5", "p_gpio_6", "p_gpio_7"], "PWM": ["p_pwm0", "p_pwm1"], "JTAG": ["p_jtag_tms", "p_jtag_tdi", "p_jtag_tdo", "p_jtag_tck"], "SD": ["p_sdcard_cmd", "p_sdcard_clk", "p_sdcard_data0", "p_sdcard_data1", "p_sdcard_data2", "p_sdcard_data3"]}, "pads.west": ["ioground_2", "iopower_2", "p_pwm0", "p_pwm1", "p_eint_0", "p_eint_1", "p_eint_2", "p_spimaster_clk", "p_spimaster_cs_n", "p_spimaster_mosi", "p_spimaster_miso", "p_sdcard_cmd", "p_sdcard_clk", "p_sdcard_data0", "p_sdcard_data1", "p_sdcard_data2", "p_sdcard_data3", "nc_4", "nc_5", "nc_6", "nc_7", "nc_8", "nc_9", "nc_10", "nc_11", "nc_12", "nc_13", "nc_14", "nc_15", "nc_16", "ground_4", "power_4"], "pads.instances": [["ioground_0", "iovss"], ["iopower_0", "iovdd"], ["p_sdram_dm_0", "sdram_dm(0)", "sdram_dm(0)", "+"], ["p_sdram_dq_0", "sdram_dq_0", "sdram_dq_o(0)", "sdram_dq_i(0)", "sdram_dq_oe", "*"], ["p_sdram_dq_1", "sdram_dq_1", "sdram_dq_o(1)", "sdram_dq_i(1)", "sdram_dq_oe", "*"], ["p_sdram_dq_2", "sdram_dq_2", "sdram_dq_o(2)", "sdram_dq_i(2)", "sdram_dq_oe", "*"], ["p_sdram_dq_3", "sdram_dq_3", "sdram_dq_o(3)", "sdram_dq_i(3)", "sdram_dq_oe", "*"], ["p_sdram_dq_4", "sdram_dq_4", "sdram_dq_o(4)", "sdram_dq_i(4)", "sdram_dq_oe", "*"], ["p_sdram_dq_5", "sdram_dq_5", "sdram_dq_o(5)", "sdram_dq_i(5)", "sdram_dq_oe", "*"], ["p_sdram_dq_6", "sdram_dq_6", "sdram_dq_o(6)", "sdram_dq_i(6)", "sdram_dq_oe", "*"], ["p_sdram_dq_7", "sdram_dq_7", "sdram_dq_o(7)", "sdram_dq_i(7)", "sdram_dq_oe", "*"], ["p_sdram_a_0", "sdram_a(0)", "sdram_a(0)", "+"], ["p_sdram_a_1", "sdram_a(1)", "sdram_a(1)", "+"], ["p_sdram_a_2", "sdram_a(2)", "sdram_a(2)", "+"], ["p_sdram_a_3", "sdram_a(3)", "sdram_a(3)", "+"], ["p_sdram_a_4", "sdram_a(4)", "sdram_a(4)", "+"], ["p_sdram_a_5", "sdram_a(5)", "sdram_a(5)", "+"], ["p_sdram_a_6", "sdram_a(6)", "sdram_a(6)", "+"], ["p_sdram_a_7", "sdram_a(7)", "sdram_a(7)", "+"], ["p_sdram_a_8", "sdram_a(8)", "sdram_a(8)", "+"], ["p_sdram_a_9", "sdram_a(9)", "sdram_a(9)", "+"], ["p_sdram_ba_0", "sdram_ba(0)", "sdram_ba(0)", "+"], ["p_sdram_ba_1", "sdram_ba(1)", "sdram_ba(1)", "+"], ["p_sdram_clock", "sdram_clock", "sdram_clock", "+"], ["p_sdram_cke", "sdram_cke", "sdram_cke", "+"], ["p_sdram_ras_n", "sdram_ras_n", "sdram_ras_n", "+"], ["p_sdram_cas_n", "sdram_cas_n", "sdram_cas_n", "+"], ["p_sdram_we_n", "sdram_we_n", "sdram_we_n", "+"], ["p_sdram_cs_n", "sdram_cs_n", "sdram_cs_n", "+"], ["ground_0", "vss"], ["power_0", "vdd"], ["ioground_1", "iovss"], ["iopower_1", "iovdd"], ["p_sdram_a_10", "sdram_a(10)", "sdram_a(10)", "+"], ["p_sdram_a_11", "sdram_a(11)", "sdram_a(11)", "+"], ["p_sdram_a_12", "sdram_a(12)", "sdram_a(12)", "+"], ["p_sdram_dm_1", "sdram_dm(1)", "sdram_dm(1)", "+"], ["p_sdram_dq_8", "sdram_dq_8", "sdram_dq_o(8)", "sdram_dq_i(8)", "sdram_dq_oe", "*"], ["p_sdram_dq_9", "sdram_dq_9", "sdram_dq_o(9)", "sdram_dq_i(9)", "sdram_dq_oe", "*"], ["p_sdram_dq_10", "sdram_dq_10", "sdram_dq_o(10)", "sdram_dq_i(10)", "sdram_dq_oe", "*"], ["p_sdram_dq_11", "sdram_dq_11", "sdram_dq_o(11)", "sdram_dq_i(11)", "sdram_dq_oe", "*"], ["p_sdram_dq_12", "sdram_dq_12", "sdram_dq_o(12)", "sdram_dq_i(12)", "sdram_dq_oe", "*"], ["p_sdram_dq_13", "sdram_dq_13", "sdram_dq_o(13)", "sdram_dq_i(13)", "sdram_dq_oe", "*"], ["p_sdram_dq_14", "sdram_dq_14", "sdram_dq_o(14)", "sdram_dq_i(14)", "sdram_dq_oe", "*"], ["p_sdram_dq_15", "sdram_dq_15", "sdram_dq_o(15)", "sdram_dq_i(15)", "sdram_dq_oe", "*"], ["ground_1", "vss"], ["power_1", "vdd"], ["p_gpio_8", "gpio_8", "gpio_o(8)", "gpio_i(8)", "gpio_oe(8)", "*"], ["p_gpio_9", "gpio_9", "gpio_o(9)", "gpio_i(9)", "gpio_oe(9)", "*"], ["p_gpio_10", "gpio_10", "gpio_o(10)", "gpio_i(10)", "gpio_oe(10)", "*"], ["p_gpio_11", "gpio_11", "gpio_o(11)", "gpio_i(11)", "gpio_oe(11)", "*"], ["p_gpio_12", "gpio_12", "gpio_o(12)", "gpio_i(12)", "gpio_oe(12)", "*"], ["p_gpio_13", "gpio_13", "gpio_o(13)", "gpio_i(13)", "gpio_oe(13)", "*"], ["p_gpio_14", "gpio_14", "gpio_o(14)", "gpio_i(14)", "gpio_oe(14)", "*"], ["p_gpio_15", "gpio_15", "gpio_o(15)", "gpio_i(15)", "gpio_oe(15)", "*"], ["p_jtag_tms", "jtag_tms", "jtag_tms", "-"], ["p_jtag_tdi", "jtag_tdi", "jtag_tdi", "-"], ["p_jtag_tdo", "jtag_tdo", "jtag_tdo", "+"], ["p_jtag_tck", "jtag_tck", "jtag_tck", "+"], ["ground_2", "vss"], ["power_2", "vdd"], ["p_i2c_sda", "i2c_sda", "i2c_sda_o", "i2c_sda_i", "i2c_sda_oe", "*"], ["p_i2c_scl", "i2c_scl", "i2c_scl", "+"], ["p_spisdcard_clk", "spisdcard_clk", "spisdcard_clk", "+"], ["p_spisdcard_cs_n", "spisdcard_cs_n", "spisdcard_cs_n", "+"], ["p_spisdcard_mosi", "spisdcard_mosi", "spisdcard_mosi", "+"], ["p_spisdcard_miso", "spisdcard_miso", "spisdcard_miso", "-"], ["p_uart_tx", "uart_tx", "uart_tx", "+"], ["p_uart_rx", "uart_rx", "uart_rx", "-"], ["p_gpio_0", "gpio_0", "gpio_o(0)", "gpio_i(0)", "gpio_oe(0)", "*"], ["p_gpio_1", "gpio_1", "gpio_o(1)", "gpio_i(1)", "gpio_oe(1)", "*"], ["p_gpio_2", "gpio_2", "gpio_o(2)", "gpio_i(2)", "gpio_oe(2)", "*"], ["p_gpio_3", "gpio_3", "gpio_o(3)", "gpio_i(3)", "gpio_oe(3)", "*"], ["p_gpio_4", "gpio_4", "gpio_o(4)", "gpio_i(4)", "gpio_oe(4)", "*"], ["p_gpio_5", "gpio_5", "gpio_o(5)", "gpio_i(5)", "gpio_oe(5)", "*"], ["p_gpio_6", "gpio_6", "gpio_o(6)", "gpio_i(6)", "gpio_oe(6)", "*"], ["p_gpio_7", "gpio_7", "gpio_o(7)", "gpio_i(7)", "gpio_oe(7)", "*"], ["p_sys_clk", "sys_clk", "sys_clk", "-"], ["sys_rst", "sys_rst", "sys_rst", "-"], ["p_sys_pll_18_o", "sys_pll_18_o", "sys_pll_18_o", "+"], ["p_sys_clksel_0", "sys_clksel_i(0)", "sys_clksel_i(0)", "-"], ["p_sys_clksel_1", "sys_clksel_i(1)", "sys_clksel_i(1)", "-"], ["p_sys_pll_lck_o", "sys_pll_lck_o", "sys_pll_lck_o", "+"], ["ground_3", "vss"], ["power_3", "vdd"], ["ioground_2", "iovss"], ["iopower_2", "iovdd"], ["p_pwm0", "pwm(0)", "pwm(0)", "+"], ["p_pwm1", "pwm(1)", "pwm(1)", "+"], ["p_eint_0", "eint(0)", "eint(0)", "-"], ["p_eint_1", "eint(1)", "eint(1)", "-"], ["p_eint_2", "eint(2)", "eint(2)", "-"], ["p_spimaster_clk", "spimaster_clk", "spimaster_clk", "+"], ["p_spimaster_cs_n", "spimaster_cs_n", "spimaster_cs_n", "+"], ["p_spimaster_mosi", "spimaster_mosi", "spimaster_mosi", "+"], ["p_spimaster_miso", "spimaster_miso", "spimaster_miso", "-"], ["p_sdcard_cmd", "sdcard_cmd", "sdcard_cmd_o", "sdcard_cmd_i", "sdcard_cmd_oe", "*"], ["p_sdcard_clk", "sdcard_clk", "sdcard_clk", "+"], ["p_sdcard_data0", "sdcard_data0", "sdcard_data_o(0)", "sdcard_data_i(0)", "sdcard_data_oe", "*"], ["p_sdcard_data1", "sdcard_data1", "sdcard_data_o(1)", "sdcard_data_i(1)", "sdcard_data_oe", "*"], ["p_sdcard_data2", "sdcard_data2", "sdcard_data_o(2)", "sdcard_data_i(2)", "sdcard_data_oe", "*"], ["p_sdcard_data3", "sdcard_data3", "sdcard_data_o(3)", "sdcard_data_i(3)", "sdcard_data_oe", "*"], ["ground_4", "vss"], ["power_4", "vdd"], ["nc_0", "nc(0)", "nc(0)", "-"], ["nc_1", "nc(1)", "nc(1)", "-"], ["nc_2", "nc(2)", "nc(2)", "-"], ["nc_3", "nc(3)", "nc(3)", "-"], ["nc_4", "nc(4)", "nc(4)", "-"], ["nc_5", "nc(5)", "nc(5)", "-"], ["nc_6", "nc(6)", "nc(6)", "-"], ["nc_7", "nc(7)", "nc(7)", "-"], ["nc_8", "nc(8)", "nc(8)", "-"], ["nc_9", "nc(9)", "nc(9)", "-"], ["nc_10", "nc(10)", "nc(10)", "-"], ["nc_11", "nc(11)", "nc(11)", "-"], ["nc_12", "nc(12)", "nc(12)", "-"], ["nc_13", "nc(13)", "nc(13)", "-"], ["nc_14", "nc(14)", "nc(14)", "-"], ["nc_15", "nc(15)", "nc(15)", "-"], ["nc_16", "nc(16)", "nc(16)", "-"], ["nc_17", "nc(17)", "nc(17)", "-"], ["nc_18", "nc(18)", "nc(18)", "-"], ["nc_19", "nc(19)", "nc(19)", "-"], ["nc_20", "nc(20)", "nc(20)", "-"], ["nc_21", "nc(21)", "nc(21)", "-"], ["nc_22", "nc(22)", "nc(22)", "-"], ["nc_23", "nc(23)", "nc(23)", "-"]], "pads.south": ["ground_2", "power_2", "p_i2c_sda", "p_i2c_scl", "nc_18", "nc_19", "nc_20", "nc_21", "p_spisdcard_clk", "p_spisdcard_cs_n", "p_spisdcard_mosi", "p_spisdcard_miso", "nc_22", "p_uart_tx", "p_uart_rx", "p_gpio_0", "p_gpio_1", "p_gpio_2", "p_gpio_3", "p_gpio_4", "p_gpio_5", "p_gpio_6", "p_gpio_7", "p_sys_clk", "sys_rst", "nc_23", "p_sys_pll_18_o", "p_sys_clksel_0", "p_sys_clksel_1", "p_sys_pll_lck_o", "ground_3", "power_3"]} \ No newline at end of file diff --git a/experiments9/symbolic/coriolis2/ls180/ls180_pins.py b/experiments9/symbolic/coriolis2/ls180/ls180_pins.py index 773bd69..cee0e2a 100644 --- a/experiments9/symbolic/coriolis2/ls180/ls180_pins.py +++ b/experiments9/symbolic/coriolis2/ls180/ls180_pins.py @@ -21,7 +21,7 @@ pindict = { 'ad7+', 'ad8+', 'ad9+', 'ba0+', 'ba1+', 'clk+', 'cke+', 'rasn+', 'casn+', 'wen+', 'csn0+', 'ad10+', - 'ad11+', 'ad12+', 'dqm1*', 'd8*', + 'ad11+', 'ad12+', 'dqm1+', 'd8*', 'd9*', 'd10*', 'd11*', 'd12*', 'd13*', 'd14*', 'd15*', ], 'gpio': [ 'e8*', 'e9*', 'e10*', 'e11*', @@ -55,7 +55,7 @@ litexdict = { 'sdram_a_7+', 'sdram_a_8+', 'sdram_a_9+', 'sdram_ba_0+', 'sdram_ba_1+', 'sdram_clock+', 'sdram_cke+', 'sdram_ras_n+', 'sdram_cas_n+', 'sdram_we_n+', 'sdram_cs_n+', 'sdram_a_10+', - 'sdram_a_11+', 'sdram_a_12+', 'sdram_dm_1*', 'sdram_dq_8*', + 'sdram_a_11+', 'sdram_a_12+', 'sdram_dm_1+', 'sdram_dq_8*', 'sdram_dq_9*', 'sdram_dq_10*', 'sdram_dq_11*', 'sdram_dq_12*', 'sdram_dq_13*', 'sdram_dq_14*', 'sdram_dq_15*', ], 'gpio': [ 'e8*', 'e9*', 'e10*', 'e11*', diff --git a/experiments9/symbolic/coriolis2/ls180/sdr.txt b/experiments9/symbolic/coriolis2/ls180/sdr.txt index c3e1647..ed5c134 100644 --- a/experiments9/symbolic/coriolis2/ls180/sdr.txt +++ b/experiments9/symbolic/coriolis2/ls180/sdr.txt @@ -28,7 +28,7 @@ csn0 out ad10 out ad11 out ad12 out -dqm1 inout +dqm1 out d8 inout bus d9 inout bus d10 inout bus diff --git a/experiments9/symbolic/coriolis2/pinparse.py b/experiments9/symbolic/coriolis2/pinparse.py index a704604..6e01033 120000 --- a/experiments9/symbolic/coriolis2/pinparse.py +++ b/experiments9/symbolic/coriolis2/pinparse.py @@ -1 +1 @@ -../pinmux/src/parse.py \ No newline at end of file +../../../pinmux/src/parse.py \ No newline at end of file -- 2.30.2